2 * Copyright © 2006-2016 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_display_types.h"
25 #include "intel_dpio_phy.h"
26 #include "intel_dpll_mgr.h"
31 * Display PLLs used for driving outputs vary by platform. While some have
32 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
33 * from a pool. In the latter scenario, it is possible that multiple pipes
34 * share a PLL if their configurations match.
36 * This file provides an abstraction over display PLLs. The function
37 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
38 * users of a PLL are tracked and that tracking is integrated with the atomic
39 * modset interface. During an atomic operation, required PLLs can be reserved
40 * for a given CRTC and encoder configuration by calling
41 * intel_reserve_shared_dplls() and previously reserved PLLs can be released
42 * with intel_release_shared_dplls().
43 * Changes to the users are first staged in the atomic state, and then made
44 * effective by calling intel_shared_dpll_swap_state() during the atomic
48 struct intel_dpll_mgr {
49 const struct dpll_info *dpll_info;
51 bool (*get_dplls)(struct intel_atomic_state *state,
52 struct intel_crtc *crtc,
53 struct intel_encoder *encoder);
54 void (*put_dplls)(struct intel_atomic_state *state,
55 struct intel_crtc *crtc);
56 void (*update_active_dpll)(struct intel_atomic_state *state,
57 struct intel_crtc *crtc,
58 struct intel_encoder *encoder);
59 void (*update_ref_clks)(struct drm_i915_private *i915);
60 void (*dump_hw_state)(struct drm_i915_private *dev_priv,
61 const struct intel_dpll_hw_state *hw_state);
65 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
66 struct intel_shared_dpll_state *shared_dpll)
70 /* Copy shared dpll state */
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
74 shared_dpll[i] = pll->state;
78 static struct intel_shared_dpll_state *
79 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
81 struct intel_atomic_state *state = to_intel_atomic_state(s);
83 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
85 if (!state->dpll_set) {
86 state->dpll_set = true;
88 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
92 return state->shared_dpll;
96 * intel_get_shared_dpll_by_id - get a DPLL given its id
97 * @dev_priv: i915 device instance
101 * A pointer to the DPLL with @id
103 struct intel_shared_dpll *
104 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
105 enum intel_dpll_id id)
107 return &dev_priv->dpll.shared_dplls[id];
111 * intel_get_shared_dpll_id - get the id of a DPLL
112 * @dev_priv: i915 device instance
119 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
120 struct intel_shared_dpll *pll)
122 long pll_idx = pll - dev_priv->dpll.shared_dplls;
124 if (drm_WARN_ON(&dev_priv->drm,
126 pll_idx >= dev_priv->dpll.num_shared_dpll))
133 void assert_shared_dpll(struct drm_i915_private *dev_priv,
134 struct intel_shared_dpll *pll,
138 struct intel_dpll_hw_state hw_state;
140 if (drm_WARN(&dev_priv->drm, !pll,
141 "asserting DPLL %s with no DPLL\n", onoff(state)))
144 cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
145 I915_STATE_WARN(cur_state != state,
146 "%s assertion failure (expected %s, current %s)\n",
147 pll->info->name, onoff(state), onoff(cur_state));
151 * intel_prepare_shared_dpll - call a dpll's prepare hook
152 * @crtc_state: CRTC, and its state, which has a shared dpll
154 * This calls the PLL's prepare hook if it has one and if the PLL is not
155 * already enabled. The prepare hook is platform specific.
157 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
159 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
160 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
161 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
163 if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
166 mutex_lock(&dev_priv->dpll.lock);
167 drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask);
168 if (!pll->active_mask) {
169 drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);
170 drm_WARN_ON(&dev_priv->drm, pll->on);
171 assert_shared_dpll_disabled(dev_priv, pll);
173 pll->info->funcs->prepare(dev_priv, pll);
175 mutex_unlock(&dev_priv->dpll.lock);
179 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
180 * @crtc_state: CRTC, and its state, which has a shared DPLL
182 * Enable the shared DPLL used by @crtc.
184 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
186 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
187 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
188 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
189 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
190 unsigned int old_mask;
192 if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
195 mutex_lock(&dev_priv->dpll.lock);
196 old_mask = pll->active_mask;
198 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask)) ||
199 drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask))
202 pll->active_mask |= crtc_mask;
204 drm_dbg_kms(&dev_priv->drm,
205 "enable %s (active %x, on? %d) for crtc %d\n",
206 pll->info->name, pll->active_mask, pll->on,
210 drm_WARN_ON(&dev_priv->drm, !pll->on);
211 assert_shared_dpll_enabled(dev_priv, pll);
214 drm_WARN_ON(&dev_priv->drm, pll->on);
216 drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name);
217 pll->info->funcs->enable(dev_priv, pll);
221 mutex_unlock(&dev_priv->dpll.lock);
225 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
226 * @crtc_state: CRTC, and its state, which has a shared DPLL
228 * Disable the shared DPLL used by @crtc.
230 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
232 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
234 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
235 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
237 /* PCH only available on ILK+ */
238 if (INTEL_GEN(dev_priv) < 5)
244 mutex_lock(&dev_priv->dpll.lock);
245 if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask)))
248 drm_dbg_kms(&dev_priv->drm,
249 "disable %s (active %x, on? %d) for crtc %d\n",
250 pll->info->name, pll->active_mask, pll->on,
253 assert_shared_dpll_enabled(dev_priv, pll);
254 drm_WARN_ON(&dev_priv->drm, !pll->on);
256 pll->active_mask &= ~crtc_mask;
257 if (pll->active_mask)
260 drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
261 pll->info->funcs->disable(dev_priv, pll);
265 mutex_unlock(&dev_priv->dpll.lock);
268 static struct intel_shared_dpll *
269 intel_find_shared_dpll(struct intel_atomic_state *state,
270 const struct intel_crtc *crtc,
271 const struct intel_dpll_hw_state *pll_state,
272 unsigned long dpll_mask)
274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
275 struct intel_shared_dpll *pll, *unused_pll = NULL;
276 struct intel_shared_dpll_state *shared_dpll;
277 enum intel_dpll_id i;
279 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
281 drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
283 for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
284 pll = &dev_priv->dpll.shared_dplls[i];
286 /* Only want to check enabled timings first */
287 if (shared_dpll[i].crtc_mask == 0) {
293 if (memcmp(pll_state,
294 &shared_dpll[i].hw_state,
295 sizeof(*pll_state)) == 0) {
296 drm_dbg_kms(&dev_priv->drm,
297 "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
298 crtc->base.base.id, crtc->base.name,
300 shared_dpll[i].crtc_mask,
306 /* Ok no matching timings, maybe there's a free one? */
308 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n",
309 crtc->base.base.id, crtc->base.name,
310 unused_pll->info->name);
318 intel_reference_shared_dpll(struct intel_atomic_state *state,
319 const struct intel_crtc *crtc,
320 const struct intel_shared_dpll *pll,
321 const struct intel_dpll_hw_state *pll_state)
323 struct drm_i915_private *i915 = to_i915(state->base.dev);
324 struct intel_shared_dpll_state *shared_dpll;
325 const enum intel_dpll_id id = pll->info->id;
327 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
329 if (shared_dpll[id].crtc_mask == 0)
330 shared_dpll[id].hw_state = *pll_state;
332 drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
333 pipe_name(crtc->pipe));
335 shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
338 static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
339 const struct intel_crtc *crtc,
340 const struct intel_shared_dpll *pll)
342 struct intel_shared_dpll_state *shared_dpll;
344 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
345 shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
348 static void intel_put_dpll(struct intel_atomic_state *state,
349 struct intel_crtc *crtc)
351 const struct intel_crtc_state *old_crtc_state =
352 intel_atomic_get_old_crtc_state(state, crtc);
353 struct intel_crtc_state *new_crtc_state =
354 intel_atomic_get_new_crtc_state(state, crtc);
356 new_crtc_state->shared_dpll = NULL;
358 if (!old_crtc_state->shared_dpll)
361 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
365 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
366 * @state: atomic state
368 * This is the dpll version of drm_atomic_helper_swap_state() since the
369 * helper does not handle driver-specific global state.
371 * For consistency with atomic helpers this function does a complete swap,
372 * i.e. it also puts the current state into @state, even though there is no
373 * need for that at this moment.
375 void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
377 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
378 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
379 enum intel_dpll_id i;
381 if (!state->dpll_set)
384 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
385 struct intel_shared_dpll *pll =
386 &dev_priv->dpll.shared_dplls[i];
388 swap(pll->state, shared_dpll[i]);
392 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
393 struct intel_shared_dpll *pll,
394 struct intel_dpll_hw_state *hw_state)
396 const enum intel_dpll_id id = pll->info->id;
397 intel_wakeref_t wakeref;
400 wakeref = intel_display_power_get_if_enabled(dev_priv,
401 POWER_DOMAIN_DISPLAY_CORE);
405 val = intel_de_read(dev_priv, PCH_DPLL(id));
406 hw_state->dpll = val;
407 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id));
408 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id));
410 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
412 return val & DPLL_VCO_ENABLE;
415 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
416 struct intel_shared_dpll *pll)
418 const enum intel_dpll_id id = pll->info->id;
420 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0);
421 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1);
424 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
429 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
431 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
432 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
433 DREF_SUPERSPREAD_SOURCE_MASK));
434 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
437 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
438 struct intel_shared_dpll *pll)
440 const enum intel_dpll_id id = pll->info->id;
442 /* PCH refclock must be enabled first */
443 ibx_assert_pch_refclk_enabled(dev_priv);
445 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);
447 /* Wait for the clocks to stabilize. */
448 intel_de_posting_read(dev_priv, PCH_DPLL(id));
451 /* The pixel multiplier can only be updated once the
452 * DPLL is enabled and the clocks are stable.
456 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);
457 intel_de_posting_read(dev_priv, PCH_DPLL(id));
461 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
462 struct intel_shared_dpll *pll)
464 const enum intel_dpll_id id = pll->info->id;
466 intel_de_write(dev_priv, PCH_DPLL(id), 0);
467 intel_de_posting_read(dev_priv, PCH_DPLL(id));
471 static bool ibx_get_dpll(struct intel_atomic_state *state,
472 struct intel_crtc *crtc,
473 struct intel_encoder *encoder)
475 struct intel_crtc_state *crtc_state =
476 intel_atomic_get_new_crtc_state(state, crtc);
477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
478 struct intel_shared_dpll *pll;
479 enum intel_dpll_id i;
481 if (HAS_PCH_IBX(dev_priv)) {
482 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
483 i = (enum intel_dpll_id) crtc->pipe;
484 pll = &dev_priv->dpll.shared_dplls[i];
486 drm_dbg_kms(&dev_priv->drm,
487 "[CRTC:%d:%s] using pre-allocated %s\n",
488 crtc->base.base.id, crtc->base.name,
491 pll = intel_find_shared_dpll(state, crtc,
492 &crtc_state->dpll_hw_state,
493 BIT(DPLL_ID_PCH_PLL_B) |
494 BIT(DPLL_ID_PCH_PLL_A));
500 /* reference the pll */
501 intel_reference_shared_dpll(state, crtc,
502 pll, &crtc_state->dpll_hw_state);
504 crtc_state->shared_dpll = pll;
509 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
510 const struct intel_dpll_hw_state *hw_state)
512 drm_dbg_kms(&dev_priv->drm,
513 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
514 "fp0: 0x%x, fp1: 0x%x\n",
521 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
522 .prepare = ibx_pch_dpll_prepare,
523 .enable = ibx_pch_dpll_enable,
524 .disable = ibx_pch_dpll_disable,
525 .get_hw_state = ibx_pch_dpll_get_hw_state,
528 static const struct dpll_info pch_plls[] = {
529 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
530 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
534 static const struct intel_dpll_mgr pch_pll_mgr = {
535 .dpll_info = pch_plls,
536 .get_dplls = ibx_get_dpll,
537 .put_dplls = intel_put_dpll,
538 .dump_hw_state = ibx_dump_hw_state,
541 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
542 struct intel_shared_dpll *pll)
544 const enum intel_dpll_id id = pll->info->id;
546 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll);
547 intel_de_posting_read(dev_priv, WRPLL_CTL(id));
551 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
552 struct intel_shared_dpll *pll)
554 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll);
555 intel_de_posting_read(dev_priv, SPLL_CTL);
559 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
560 struct intel_shared_dpll *pll)
562 const enum intel_dpll_id id = pll->info->id;
565 val = intel_de_read(dev_priv, WRPLL_CTL(id));
566 intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
567 intel_de_posting_read(dev_priv, WRPLL_CTL(id));
570 * Try to set up the PCH reference clock once all DPLLs
571 * that depend on it have been shut down.
573 if (dev_priv->pch_ssc_use & BIT(id))
574 intel_init_pch_refclk(dev_priv);
577 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
578 struct intel_shared_dpll *pll)
580 enum intel_dpll_id id = pll->info->id;
583 val = intel_de_read(dev_priv, SPLL_CTL);
584 intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE);
585 intel_de_posting_read(dev_priv, SPLL_CTL);
588 * Try to set up the PCH reference clock once all DPLLs
589 * that depend on it have been shut down.
591 if (dev_priv->pch_ssc_use & BIT(id))
592 intel_init_pch_refclk(dev_priv);
595 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
596 struct intel_shared_dpll *pll,
597 struct intel_dpll_hw_state *hw_state)
599 const enum intel_dpll_id id = pll->info->id;
600 intel_wakeref_t wakeref;
603 wakeref = intel_display_power_get_if_enabled(dev_priv,
604 POWER_DOMAIN_DISPLAY_CORE);
608 val = intel_de_read(dev_priv, WRPLL_CTL(id));
609 hw_state->wrpll = val;
611 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
613 return val & WRPLL_PLL_ENABLE;
616 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
617 struct intel_shared_dpll *pll,
618 struct intel_dpll_hw_state *hw_state)
620 intel_wakeref_t wakeref;
623 wakeref = intel_display_power_get_if_enabled(dev_priv,
624 POWER_DOMAIN_DISPLAY_CORE);
628 val = intel_de_read(dev_priv, SPLL_CTL);
629 hw_state->spll = val;
631 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
633 return val & SPLL_PLL_ENABLE;
637 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
643 /* Constraints for PLL good behavior */
649 struct hsw_wrpll_rnp {
653 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
727 static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
728 unsigned int r2, unsigned int n2,
730 struct hsw_wrpll_rnp *best)
732 u64 a, b, c, d, diff, diff_best;
734 /* No best (r,n,p) yet */
743 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
747 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
750 * and we would like delta <= budget.
752 * If the discrepancy is above the PPM-based budget, always prefer to
753 * improve upon the previous solution. However, if you're within the
754 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
756 a = freq2k * budget * p * r2;
757 b = freq2k * budget * best->p * best->r2;
758 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
759 diff_best = abs_diff(freq2k * best->p * best->r2,
760 LC_FREQ_2K * best->n2);
762 d = 1000000 * diff_best;
764 if (a < c && b < d) {
765 /* If both are above the budget, pick the closer */
766 if (best->p * best->r2 * diff < p * r2 * diff_best) {
771 } else if (a >= c && b < d) {
772 /* If A is below the threshold but B is above it? Update. */
776 } else if (a >= c && b >= d) {
777 /* Both are below the limit, so pick the higher n2/(r2*r2) */
778 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
784 /* Otherwise a < c && b >= d, do nothing */
788 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
789 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
793 struct hsw_wrpll_rnp best = { 0, 0, 0 };
796 freq2k = clock / 100;
798 budget = hsw_wrpll_get_budget_for_freq(clock);
800 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
801 * and directly pass the LC PLL to it. */
802 if (freq2k == 5400000) {
810 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
813 * We want R so that REF_MIN <= Ref <= REF_MAX.
814 * Injecting R2 = 2 * R gives:
815 * REF_MAX * r2 > LC_FREQ * 2 and
816 * REF_MIN * r2 < LC_FREQ * 2
818 * Which means the desired boundaries for r2 are:
819 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
822 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
823 r2 <= LC_FREQ * 2 / REF_MIN;
827 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
829 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
830 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
831 * VCO_MAX * r2 > n2 * LC_FREQ and
832 * VCO_MIN * r2 < n2 * LC_FREQ)
834 * Which means the desired boundaries for n2 are:
835 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
837 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
838 n2 <= VCO_MAX * r2 / LC_FREQ;
841 for (p = P_MIN; p <= P_MAX; p += P_INC)
842 hsw_wrpll_update_rnp(freq2k, budget,
852 static struct intel_shared_dpll *
853 hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
854 struct intel_crtc *crtc)
856 struct intel_crtc_state *crtc_state =
857 intel_atomic_get_new_crtc_state(state, crtc);
858 struct intel_shared_dpll *pll;
860 unsigned int p, n2, r2;
862 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
864 val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
865 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
866 WRPLL_DIVIDER_POST(p);
868 crtc_state->dpll_hw_state.wrpll = val;
870 pll = intel_find_shared_dpll(state, crtc,
871 &crtc_state->dpll_hw_state,
872 BIT(DPLL_ID_WRPLL2) |
873 BIT(DPLL_ID_WRPLL1));
881 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
882 const struct intel_shared_dpll *pll)
886 u32 wrpll = pll->state.hw_state.wrpll;
888 switch (wrpll & WRPLL_REF_MASK) {
889 case WRPLL_REF_SPECIAL_HSW:
890 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
891 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
892 refclk = dev_priv->dpll.ref_clks.nssc;
896 case WRPLL_REF_PCH_SSC:
898 * We could calculate spread here, but our checking
899 * code only cares about 5% accuracy, and spread is a max of
902 refclk = dev_priv->dpll.ref_clks.ssc;
904 case WRPLL_REF_LCPLL:
912 r = wrpll & WRPLL_DIVIDER_REF_MASK;
913 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
914 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
916 /* Convert to KHz, p & r have a fixed point portion */
917 return (refclk * n / 10) / (p * r) * 2;
920 static struct intel_shared_dpll *
921 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
923 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
924 struct intel_shared_dpll *pll;
925 enum intel_dpll_id pll_id;
926 int clock = crtc_state->port_clock;
930 pll_id = DPLL_ID_LCPLL_810;
933 pll_id = DPLL_ID_LCPLL_1350;
936 pll_id = DPLL_ID_LCPLL_2700;
939 drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
944 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
952 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
953 const struct intel_shared_dpll *pll)
957 switch (pll->info->id) {
958 case DPLL_ID_LCPLL_810:
961 case DPLL_ID_LCPLL_1350:
964 case DPLL_ID_LCPLL_2700:
968 drm_WARN(&i915->drm, 1, "bad port clock sel\n");
972 return link_clock * 2;
975 static struct intel_shared_dpll *
976 hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
977 struct intel_crtc *crtc)
979 struct intel_crtc_state *crtc_state =
980 intel_atomic_get_new_crtc_state(state, crtc);
982 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
985 crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
988 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
992 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
993 const struct intel_shared_dpll *pll)
997 switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
998 case SPLL_FREQ_810MHz:
1001 case SPLL_FREQ_1350MHz:
1002 link_clock = 135000;
1004 case SPLL_FREQ_2700MHz:
1005 link_clock = 270000;
1008 drm_WARN(&i915->drm, 1, "bad spll freq\n");
1012 return link_clock * 2;
1015 static bool hsw_get_dpll(struct intel_atomic_state *state,
1016 struct intel_crtc *crtc,
1017 struct intel_encoder *encoder)
1019 struct intel_crtc_state *crtc_state =
1020 intel_atomic_get_new_crtc_state(state, crtc);
1021 struct intel_shared_dpll *pll;
1023 memset(&crtc_state->dpll_hw_state, 0,
1024 sizeof(crtc_state->dpll_hw_state));
1026 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1027 pll = hsw_ddi_wrpll_get_dpll(state, crtc);
1028 else if (intel_crtc_has_dp_encoder(crtc_state))
1029 pll = hsw_ddi_lcpll_get_dpll(crtc_state);
1030 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1031 pll = hsw_ddi_spll_get_dpll(state, crtc);
1038 intel_reference_shared_dpll(state, crtc,
1039 pll, &crtc_state->dpll_hw_state);
1041 crtc_state->shared_dpll = pll;
1046 static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
1048 i915->dpll.ref_clks.ssc = 135000;
1049 /* Non-SSC is only used on non-ULT HSW. */
1050 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1051 i915->dpll.ref_clks.nssc = 24000;
1053 i915->dpll.ref_clks.nssc = 135000;
1056 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
1057 const struct intel_dpll_hw_state *hw_state)
1059 drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
1060 hw_state->wrpll, hw_state->spll);
1063 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
1064 .enable = hsw_ddi_wrpll_enable,
1065 .disable = hsw_ddi_wrpll_disable,
1066 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
1067 .get_freq = hsw_ddi_wrpll_get_freq,
1070 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
1071 .enable = hsw_ddi_spll_enable,
1072 .disable = hsw_ddi_spll_disable,
1073 .get_hw_state = hsw_ddi_spll_get_hw_state,
1074 .get_freq = hsw_ddi_spll_get_freq,
1077 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
1078 struct intel_shared_dpll *pll)
1082 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
1083 struct intel_shared_dpll *pll)
1087 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
1088 struct intel_shared_dpll *pll,
1089 struct intel_dpll_hw_state *hw_state)
1094 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
1095 .enable = hsw_ddi_lcpll_enable,
1096 .disable = hsw_ddi_lcpll_disable,
1097 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
1098 .get_freq = hsw_ddi_lcpll_get_freq,
1101 static const struct dpll_info hsw_plls[] = {
1102 { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
1103 { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
1104 { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
1105 { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
1106 { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1107 { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1111 static const struct intel_dpll_mgr hsw_pll_mgr = {
1112 .dpll_info = hsw_plls,
1113 .get_dplls = hsw_get_dpll,
1114 .put_dplls = intel_put_dpll,
1115 .update_ref_clks = hsw_update_dpll_ref_clks,
1116 .dump_hw_state = hsw_dump_hw_state,
1119 struct skl_dpll_regs {
1120 i915_reg_t ctl, cfgcr1, cfgcr2;
1123 /* this array is indexed by the *shared* pll id */
1124 static const struct skl_dpll_regs skl_dpll_regs[4] = {
1128 /* DPLL 0 doesn't support HDMI mode */
1133 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1134 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1138 .ctl = WRPLL_CTL(0),
1139 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1140 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1144 .ctl = WRPLL_CTL(1),
1145 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1146 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1150 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
1151 struct intel_shared_dpll *pll)
1153 const enum intel_dpll_id id = pll->info->id;
1156 val = intel_de_read(dev_priv, DPLL_CTRL1);
1158 val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
1159 DPLL_CTRL1_SSC(id) |
1160 DPLL_CTRL1_LINK_RATE_MASK(id));
1161 val |= pll->state.hw_state.ctrl1 << (id * 6);
1163 intel_de_write(dev_priv, DPLL_CTRL1, val);
1164 intel_de_posting_read(dev_priv, DPLL_CTRL1);
1167 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll)
1170 const struct skl_dpll_regs *regs = skl_dpll_regs;
1171 const enum intel_dpll_id id = pll->info->id;
1173 skl_ddi_pll_write_ctrl1(dev_priv, pll);
1175 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
1176 intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
1177 intel_de_posting_read(dev_priv, regs[id].cfgcr1);
1178 intel_de_posting_read(dev_priv, regs[id].cfgcr2);
1180 /* the enable bit is always bit 31 */
1181 intel_de_write(dev_priv, regs[id].ctl,
1182 intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE);
1184 if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5))
1185 drm_err(&dev_priv->drm, "DPLL %d not locked\n", id);
1188 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
1189 struct intel_shared_dpll *pll)
1191 skl_ddi_pll_write_ctrl1(dev_priv, pll);
1194 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1195 struct intel_shared_dpll *pll)
1197 const struct skl_dpll_regs *regs = skl_dpll_regs;
1198 const enum intel_dpll_id id = pll->info->id;
1200 /* the enable bit is always bit 31 */
1201 intel_de_write(dev_priv, regs[id].ctl,
1202 intel_de_read(dev_priv, regs[id].ctl) & ~LCPLL_PLL_ENABLE);
1203 intel_de_posting_read(dev_priv, regs[id].ctl);
1206 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
1207 struct intel_shared_dpll *pll)
1211 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1212 struct intel_shared_dpll *pll,
1213 struct intel_dpll_hw_state *hw_state)
1216 const struct skl_dpll_regs *regs = skl_dpll_regs;
1217 const enum intel_dpll_id id = pll->info->id;
1218 intel_wakeref_t wakeref;
1221 wakeref = intel_display_power_get_if_enabled(dev_priv,
1222 POWER_DOMAIN_DISPLAY_CORE);
1228 val = intel_de_read(dev_priv, regs[id].ctl);
1229 if (!(val & LCPLL_PLL_ENABLE))
1232 val = intel_de_read(dev_priv, DPLL_CTRL1);
1233 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1235 /* avoid reading back stale values if HDMI mode is not enabled */
1236 if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1237 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1);
1238 hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2);
1243 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1248 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1249 struct intel_shared_dpll *pll,
1250 struct intel_dpll_hw_state *hw_state)
1252 const struct skl_dpll_regs *regs = skl_dpll_regs;
1253 const enum intel_dpll_id id = pll->info->id;
1254 intel_wakeref_t wakeref;
1258 wakeref = intel_display_power_get_if_enabled(dev_priv,
1259 POWER_DOMAIN_DISPLAY_CORE);
1265 /* DPLL0 is always enabled since it drives CDCLK */
1266 val = intel_de_read(dev_priv, regs[id].ctl);
1267 if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE)))
1270 val = intel_de_read(dev_priv, DPLL_CTRL1);
1271 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1276 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1281 struct skl_wrpll_context {
1282 u64 min_deviation; /* current minimal deviation */
1283 u64 central_freq; /* chosen central freq */
1284 u64 dco_freq; /* chosen dco freq */
1285 unsigned int p; /* chosen divider */
1288 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1290 memset(ctx, 0, sizeof(*ctx));
1292 ctx->min_deviation = U64_MAX;
1295 /* DCO freq must be within +1%/-6% of the DCO central freq */
1296 #define SKL_DCO_MAX_PDEVIATION 100
1297 #define SKL_DCO_MAX_NDEVIATION 600
1299 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1302 unsigned int divider)
1306 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1309 /* positive deviation */
1310 if (dco_freq >= central_freq) {
1311 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1312 deviation < ctx->min_deviation) {
1313 ctx->min_deviation = deviation;
1314 ctx->central_freq = central_freq;
1315 ctx->dco_freq = dco_freq;
1318 /* negative deviation */
1319 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1320 deviation < ctx->min_deviation) {
1321 ctx->min_deviation = deviation;
1322 ctx->central_freq = central_freq;
1323 ctx->dco_freq = dco_freq;
1328 static void skl_wrpll_get_multipliers(unsigned int p,
1329 unsigned int *p0 /* out */,
1330 unsigned int *p1 /* out */,
1331 unsigned int *p2 /* out */)
1335 unsigned int half = p / 2;
1337 if (half == 1 || half == 2 || half == 3 || half == 5) {
1341 } else if (half % 2 == 0) {
1345 } else if (half % 3 == 0) {
1349 } else if (half % 7 == 0) {
1354 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1358 } else if (p == 5 || p == 7) {
1362 } else if (p == 15) {
1366 } else if (p == 21) {
1370 } else if (p == 35) {
1377 struct skl_wrpll_params {
1387 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1391 u32 p0, u32 p1, u32 p2)
1395 switch (central_freq) {
1397 params->central_freq = 0;
1400 params->central_freq = 1;
1403 params->central_freq = 3;
1420 WARN(1, "Incorrect PDiv\n");
1437 WARN(1, "Incorrect KDiv\n");
1440 params->qdiv_ratio = p1;
1441 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1443 dco_freq = p0 * p1 * p2 * afe_clock;
1446 * Intermediate values are in Hz.
1447 * Divide by MHz to match bsepc
1449 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
1450 params->dco_fraction =
1451 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
1452 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1456 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1458 struct skl_wrpll_params *wrpll_params)
1460 u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1461 u64 dco_central_freq[3] = { 8400000000ULL,
1464 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1465 24, 28, 30, 32, 36, 40, 42, 44,
1466 48, 52, 54, 56, 60, 64, 66, 68,
1467 70, 72, 76, 78, 80, 84, 88, 90,
1469 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1470 static const struct {
1474 { even_dividers, ARRAY_SIZE(even_dividers) },
1475 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1477 struct skl_wrpll_context ctx;
1478 unsigned int dco, d, i;
1479 unsigned int p0, p1, p2;
1481 skl_wrpll_context_init(&ctx);
1483 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1484 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1485 for (i = 0; i < dividers[d].n_dividers; i++) {
1486 unsigned int p = dividers[d].list[i];
1487 u64 dco_freq = p * afe_clock;
1489 skl_wrpll_try_divider(&ctx,
1490 dco_central_freq[dco],
1494 * Skip the remaining dividers if we're sure to
1495 * have found the definitive divider, we can't
1496 * improve a 0 deviation.
1498 if (ctx.min_deviation == 0)
1499 goto skip_remaining_dividers;
1503 skip_remaining_dividers:
1505 * If a solution is found with an even divider, prefer
1508 if (d == 0 && ctx.p)
1513 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1518 * gcc incorrectly analyses that these can be used without being
1519 * initialized. To be fair, it's hard to guess.
1522 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1523 skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
1524 ctx.central_freq, p0, p1, p2);
1529 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1531 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1532 u32 ctrl1, cfgcr1, cfgcr2;
1533 struct skl_wrpll_params wrpll_params = { 0, };
1536 * See comment in intel_dpll_hw_state to understand why we always use 0
1537 * as the DPLL id in this function.
1539 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1541 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1543 if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
1544 i915->dpll.ref_clks.nssc,
1548 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1549 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1550 wrpll_params.dco_integer;
1552 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1553 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1554 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1555 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1556 wrpll_params.central_freq;
1558 memset(&crtc_state->dpll_hw_state, 0,
1559 sizeof(crtc_state->dpll_hw_state));
1561 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1562 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1563 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1567 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
1568 const struct intel_shared_dpll *pll)
1570 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
1571 int ref_clock = i915->dpll.ref_clks.nssc;
1572 u32 p0, p1, p2, dco_freq;
1574 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1575 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1577 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1578 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1584 case DPLL_CFGCR2_PDIV_1:
1587 case DPLL_CFGCR2_PDIV_2:
1590 case DPLL_CFGCR2_PDIV_3:
1593 case DPLL_CFGCR2_PDIV_7:
1599 case DPLL_CFGCR2_KDIV_5:
1602 case DPLL_CFGCR2_KDIV_2:
1605 case DPLL_CFGCR2_KDIV_3:
1608 case DPLL_CFGCR2_KDIV_1:
1613 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
1616 dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
1619 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
1622 return dco_freq / (p0 * p1 * p2 * 5);
1626 skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1631 * See comment in intel_dpll_hw_state to understand why we always use 0
1632 * as the DPLL id in this function.
1634 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1635 switch (crtc_state->port_clock / 2) {
1637 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1640 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1643 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1647 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1650 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1653 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1657 memset(&crtc_state->dpll_hw_state, 0,
1658 sizeof(crtc_state->dpll_hw_state));
1660 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1665 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1666 const struct intel_shared_dpll *pll)
1670 switch ((pll->state.hw_state.ctrl1 &
1671 DPLL_CTRL1_LINK_RATE_MASK(0)) >>
1672 DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
1673 case DPLL_CTRL1_LINK_RATE_810:
1676 case DPLL_CTRL1_LINK_RATE_1080:
1677 link_clock = 108000;
1679 case DPLL_CTRL1_LINK_RATE_1350:
1680 link_clock = 135000;
1682 case DPLL_CTRL1_LINK_RATE_1620:
1683 link_clock = 162000;
1685 case DPLL_CTRL1_LINK_RATE_2160:
1686 link_clock = 216000;
1688 case DPLL_CTRL1_LINK_RATE_2700:
1689 link_clock = 270000;
1692 drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
1696 return link_clock * 2;
1699 static bool skl_get_dpll(struct intel_atomic_state *state,
1700 struct intel_crtc *crtc,
1701 struct intel_encoder *encoder)
1703 struct intel_crtc_state *crtc_state =
1704 intel_atomic_get_new_crtc_state(state, crtc);
1705 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1706 struct intel_shared_dpll *pll;
1709 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1710 bret = skl_ddi_hdmi_pll_dividers(crtc_state);
1712 drm_dbg_kms(&i915->drm,
1713 "Could not get HDMI pll dividers.\n");
1716 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1717 bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
1719 drm_dbg_kms(&i915->drm,
1720 "Could not set DP dpll HW state.\n");
1727 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1728 pll = intel_find_shared_dpll(state, crtc,
1729 &crtc_state->dpll_hw_state,
1730 BIT(DPLL_ID_SKL_DPLL0));
1732 pll = intel_find_shared_dpll(state, crtc,
1733 &crtc_state->dpll_hw_state,
1734 BIT(DPLL_ID_SKL_DPLL3) |
1735 BIT(DPLL_ID_SKL_DPLL2) |
1736 BIT(DPLL_ID_SKL_DPLL1));
1740 intel_reference_shared_dpll(state, crtc,
1741 pll, &crtc_state->dpll_hw_state);
1743 crtc_state->shared_dpll = pll;
1748 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
1749 const struct intel_shared_dpll *pll)
1752 * ctrl1 register is already shifted for each pll, just use 0 to get
1753 * the internal shift for each field
1755 if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
1756 return skl_ddi_wrpll_get_freq(i915, pll);
1758 return skl_ddi_lcpll_get_freq(i915, pll);
1761 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
1764 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
1767 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1768 const struct intel_dpll_hw_state *hw_state)
1770 drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
1771 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1777 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1778 .enable = skl_ddi_pll_enable,
1779 .disable = skl_ddi_pll_disable,
1780 .get_hw_state = skl_ddi_pll_get_hw_state,
1781 .get_freq = skl_ddi_pll_get_freq,
1784 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1785 .enable = skl_ddi_dpll0_enable,
1786 .disable = skl_ddi_dpll0_disable,
1787 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1788 .get_freq = skl_ddi_pll_get_freq,
1791 static const struct dpll_info skl_plls[] = {
1792 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1793 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1794 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1795 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
1799 static const struct intel_dpll_mgr skl_pll_mgr = {
1800 .dpll_info = skl_plls,
1801 .get_dplls = skl_get_dpll,
1802 .put_dplls = intel_put_dpll,
1803 .update_ref_clks = skl_update_dpll_ref_clks,
1804 .dump_hw_state = skl_dump_hw_state,
1807 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1808 struct intel_shared_dpll *pll)
1811 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1813 enum dpio_channel ch;
1815 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1817 /* Non-SSC reference */
1818 temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1819 temp |= PORT_PLL_REF_SEL;
1820 intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp);
1822 if (IS_GEMINILAKE(dev_priv)) {
1823 temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1824 temp |= PORT_PLL_POWER_ENABLE;
1825 intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp);
1827 if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &
1828 PORT_PLL_POWER_STATE), 200))
1829 drm_err(&dev_priv->drm,
1830 "Power state not set for PLL:%d\n", port);
1833 /* Disable 10 bit clock */
1834 temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
1835 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1836 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1839 temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch));
1840 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1841 temp |= pll->state.hw_state.ebb0;
1842 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), temp);
1844 /* Write M2 integer */
1845 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
1846 temp &= ~PORT_PLL_M2_MASK;
1847 temp |= pll->state.hw_state.pll0;
1848 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0), temp);
1851 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1));
1852 temp &= ~PORT_PLL_N_MASK;
1853 temp |= pll->state.hw_state.pll1;
1854 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 1), temp);
1856 /* Write M2 fraction */
1857 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2));
1858 temp &= ~PORT_PLL_M2_FRAC_MASK;
1859 temp |= pll->state.hw_state.pll2;
1860 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 2), temp);
1862 /* Write M2 fraction enable */
1863 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3));
1864 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1865 temp |= pll->state.hw_state.pll3;
1866 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 3), temp);
1869 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6));
1870 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1871 temp &= ~PORT_PLL_INT_COEFF_MASK;
1872 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1873 temp |= pll->state.hw_state.pll6;
1874 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp);
1876 /* Write calibration val */
1877 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8));
1878 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1879 temp |= pll->state.hw_state.pll8;
1880 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 8), temp);
1882 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9));
1883 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1884 temp |= pll->state.hw_state.pll9;
1885 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 9), temp);
1887 temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10));
1888 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1889 temp &= ~PORT_PLL_DCO_AMP_MASK;
1890 temp |= pll->state.hw_state.pll10;
1891 intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp);
1893 /* Recalibrate with new settings */
1894 temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
1895 temp |= PORT_PLL_RECALIBRATE;
1896 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1897 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1898 temp |= pll->state.hw_state.ebb4;
1899 intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1902 temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1903 temp |= PORT_PLL_ENABLE;
1904 intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp);
1905 intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1907 if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1909 drm_err(&dev_priv->drm, "PLL %d not locked\n", port);
1911 if (IS_GEMINILAKE(dev_priv)) {
1912 temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch));
1913 temp |= DCC_DELAY_RANGE_2;
1914 intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1918 * While we write to the group register to program all lanes at once we
1919 * can read only lane registers and we pick lanes 0/1 for that.
1921 temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch));
1922 temp &= ~LANE_STAGGER_MASK;
1923 temp &= ~LANESTAGGER_STRAP_OVRD;
1924 temp |= pll->state.hw_state.pcsdw12;
1925 intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1928 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1929 struct intel_shared_dpll *pll)
1931 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1934 temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1935 temp &= ~PORT_PLL_ENABLE;
1936 intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp);
1937 intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1939 if (IS_GEMINILAKE(dev_priv)) {
1940 temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1941 temp &= ~PORT_PLL_POWER_ENABLE;
1942 intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp);
1944 if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &
1945 PORT_PLL_POWER_STATE), 200))
1946 drm_err(&dev_priv->drm,
1947 "Power state not reset for PLL:%d\n", port);
1951 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1952 struct intel_shared_dpll *pll,
1953 struct intel_dpll_hw_state *hw_state)
1955 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1956 intel_wakeref_t wakeref;
1958 enum dpio_channel ch;
1962 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1964 wakeref = intel_display_power_get_if_enabled(dev_priv,
1965 POWER_DOMAIN_DISPLAY_CORE);
1971 val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1972 if (!(val & PORT_PLL_ENABLE))
1975 hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch));
1976 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1978 hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
1979 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1981 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
1982 hw_state->pll0 &= PORT_PLL_M2_MASK;
1984 hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1));
1985 hw_state->pll1 &= PORT_PLL_N_MASK;
1987 hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2));
1988 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1990 hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3));
1991 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1993 hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6));
1994 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1995 PORT_PLL_INT_COEFF_MASK |
1996 PORT_PLL_GAIN_CTL_MASK;
1998 hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8));
1999 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2001 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9));
2002 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2004 hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10));
2005 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2006 PORT_PLL_DCO_AMP_MASK;
2009 * While we write to the group register to program all lanes at once we
2010 * can read only lane registers. We configure all lanes the same way, so
2011 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2013 hw_state->pcsdw12 = intel_de_read(dev_priv,
2014 BXT_PORT_PCS_DW12_LN01(phy, ch));
2015 if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
2016 drm_dbg(&dev_priv->drm,
2017 "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2019 intel_de_read(dev_priv,
2020 BXT_PORT_PCS_DW12_LN23(phy, ch)));
2021 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2026 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2031 /* bxt clock parameters */
2032 struct bxt_clk_div {
2044 /* pre-calculated values for DP linkrates */
2045 static const struct bxt_clk_div bxt_dp_clk_val[] = {
2046 {162000, 4, 2, 32, 1677722, 1, 1},
2047 {270000, 4, 1, 27, 0, 0, 1},
2048 {540000, 2, 1, 27, 0, 0, 1},
2049 {216000, 3, 2, 32, 1677722, 1, 1},
2050 {243000, 4, 1, 24, 1258291, 1, 1},
2051 {324000, 4, 1, 32, 1677722, 1, 1},
2052 {432000, 3, 1, 32, 1677722, 1, 1}
2056 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
2057 struct bxt_clk_div *clk_div)
2059 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2061 struct dpll best_clock;
2063 /* Calculate HDMI div */
2065 * FIXME: tie the following calculation into
2066 * i9xx_crtc_compute_clock
2068 if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
2069 drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
2070 crtc_state->port_clock,
2071 pipe_name(crtc->pipe));
2075 clk_div->p1 = best_clock.p1;
2076 clk_div->p2 = best_clock.p2;
2077 drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
2078 clk_div->n = best_clock.n;
2079 clk_div->m2_int = best_clock.m2 >> 22;
2080 clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
2081 clk_div->m2_frac_en = clk_div->m2_frac != 0;
2083 clk_div->vco = best_clock.vco;
2088 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
2089 struct bxt_clk_div *clk_div)
2091 int clock = crtc_state->port_clock;
2094 *clk_div = bxt_dp_clk_val[0];
2095 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
2096 if (bxt_dp_clk_val[i].clock == clock) {
2097 *clk_div = bxt_dp_clk_val[i];
2102 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
2105 static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
2106 const struct bxt_clk_div *clk_div)
2108 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2109 struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
2110 int clock = crtc_state->port_clock;
2111 int vco = clk_div->vco;
2112 u32 prop_coef, int_coef, gain_ctl, targ_cnt;
2115 memset(dpll_hw_state, 0, sizeof(*dpll_hw_state));
2117 if (vco >= 6200000 && vco <= 6700000) {
2122 } else if ((vco > 5400000 && vco < 6200000) ||
2123 (vco >= 4800000 && vco < 5400000)) {
2128 } else if (vco == 5400000) {
2134 drm_err(&i915->drm, "Invalid VCO\n");
2140 else if (clock > 135000)
2142 else if (clock > 67000)
2144 else if (clock > 33000)
2149 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
2150 dpll_hw_state->pll0 = clk_div->m2_int;
2151 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
2152 dpll_hw_state->pll2 = clk_div->m2_frac;
2154 if (clk_div->m2_frac_en)
2155 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
2157 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
2158 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
2160 dpll_hw_state->pll8 = targ_cnt;
2162 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
2164 dpll_hw_state->pll10 =
2165 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
2166 | PORT_PLL_DCO_AMP_OVR_EN_H;
2168 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
2170 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
2176 bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2178 struct bxt_clk_div clk_div = {};
2180 bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
2182 return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2186 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2188 struct bxt_clk_div clk_div = {};
2190 bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
2192 return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2195 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
2196 const struct intel_shared_dpll *pll)
2198 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
2202 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
2203 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
2204 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
2205 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
2206 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
2207 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
2209 return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
2212 static bool bxt_get_dpll(struct intel_atomic_state *state,
2213 struct intel_crtc *crtc,
2214 struct intel_encoder *encoder)
2216 struct intel_crtc_state *crtc_state =
2217 intel_atomic_get_new_crtc_state(state, crtc);
2218 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2219 struct intel_shared_dpll *pll;
2220 enum intel_dpll_id id;
2222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
2223 !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
2226 if (intel_crtc_has_dp_encoder(crtc_state) &&
2227 !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
2230 /* 1:1 mapping between ports and PLLs */
2231 id = (enum intel_dpll_id) encoder->port;
2232 pll = intel_get_shared_dpll_by_id(dev_priv, id);
2234 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
2235 crtc->base.base.id, crtc->base.name, pll->info->name);
2237 intel_reference_shared_dpll(state, crtc,
2238 pll, &crtc_state->dpll_hw_state);
2240 crtc_state->shared_dpll = pll;
2245 static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
2247 i915->dpll.ref_clks.ssc = 100000;
2248 i915->dpll.ref_clks.nssc = 100000;
2249 /* DSI non-SSC ref 19.2MHz */
2252 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
2253 const struct intel_dpll_hw_state *hw_state)
2255 drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
2256 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
2257 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
2271 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
2272 .enable = bxt_ddi_pll_enable,
2273 .disable = bxt_ddi_pll_disable,
2274 .get_hw_state = bxt_ddi_pll_get_hw_state,
2275 .get_freq = bxt_ddi_pll_get_freq,
2278 static const struct dpll_info bxt_plls[] = {
2279 { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2280 { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2281 { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2285 static const struct intel_dpll_mgr bxt_pll_mgr = {
2286 .dpll_info = bxt_plls,
2287 .get_dplls = bxt_get_dpll,
2288 .put_dplls = intel_put_dpll,
2289 .update_ref_clks = bxt_update_dpll_ref_clks,
2290 .dump_hw_state = bxt_dump_hw_state,
2293 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2294 struct intel_shared_dpll *pll)
2296 const enum intel_dpll_id id = pll->info->id;
2299 /* 1. Enable DPLL power in DPLL_ENABLE. */
2300 val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
2301 val |= PLL_POWER_ENABLE;
2302 intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
2304 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
2305 if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
2306 PLL_POWER_STATE, 5))
2307 drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
2310 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
2311 * select DP mode, and set DP link rate.
2313 val = pll->state.hw_state.cfgcr0;
2314 intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
2316 /* 4. Reab back to ensure writes completed */
2317 intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
2319 /* 3. Configure DPLL_CFGCR0 */
2320 /* Avoid touch CFGCR1 if HDMI mode is not enabled */
2321 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
2322 val = pll->state.hw_state.cfgcr1;
2323 intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
2324 /* 4. Reab back to ensure writes completed */
2325 intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
2329 * 5. If the frequency will result in a change to the voltage
2330 * requirement, follow the Display Voltage Frequency Switching
2331 * Sequence Before Frequency Change
2333 * Note: DVFS is actually handled via the cdclk code paths,
2334 * hence we do nothing here.
2337 /* 6. Enable DPLL in DPLL_ENABLE. */
2338 val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
2340 intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
2342 /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2343 if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
2344 drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
2347 * 8. If the frequency will result in a change to the voltage
2348 * requirement, follow the Display Voltage Frequency Switching
2349 * Sequence After Frequency Change
2351 * Note: DVFS is actually handled via the cdclk code paths,
2352 * hence we do nothing here.
2356 * 9. turn on the clock for the DDI and map the DPLL to the DDI
2357 * Done at intel_ddi_clk_select
2361 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2362 struct intel_shared_dpll *pll)
2364 const enum intel_dpll_id id = pll->info->id;
2368 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2369 * Done at intel_ddi_post_disable
2373 * 2. If the frequency will result in a change to the voltage
2374 * requirement, follow the Display Voltage Frequency Switching
2375 * Sequence Before Frequency Change
2377 * Note: DVFS is actually handled via the cdclk code paths,
2378 * hence we do nothing here.
2381 /* 3. Disable DPLL through DPLL_ENABLE. */
2382 val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
2384 intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
2386 /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2387 if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
2388 drm_err(&dev_priv->drm, "PLL %d locked\n", id);
2391 * 5. If the frequency will result in a change to the voltage
2392 * requirement, follow the Display Voltage Frequency Switching
2393 * Sequence After Frequency Change
2395 * Note: DVFS is actually handled via the cdclk code paths,
2396 * hence we do nothing here.
2399 /* 6. Disable DPLL power in DPLL_ENABLE. */
2400 val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
2401 val &= ~PLL_POWER_ENABLE;
2402 intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
2404 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2405 if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),
2406 PLL_POWER_STATE, 5))
2407 drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id);
2410 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2411 struct intel_shared_dpll *pll,
2412 struct intel_dpll_hw_state *hw_state)
2414 const enum intel_dpll_id id = pll->info->id;
2415 intel_wakeref_t wakeref;
2419 wakeref = intel_display_power_get_if_enabled(dev_priv,
2420 POWER_DOMAIN_DISPLAY_CORE);
2426 val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
2427 if (!(val & PLL_ENABLE))
2430 val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id));
2431 hw_state->cfgcr0 = val;
2433 /* avoid reading back stale values if HDMI mode is not enabled */
2434 if (val & DPLL_CFGCR0_HDMI_MODE) {
2435 hw_state->cfgcr1 = intel_de_read(dev_priv,
2436 CNL_DPLL_CFGCR1(id));
2441 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2446 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2447 int *qdiv, int *kdiv)
2450 if (bestdiv % 2 == 0) {
2455 } else if (bestdiv % 4 == 0) {
2457 *qdiv = bestdiv / 4;
2459 } else if (bestdiv % 6 == 0) {
2461 *qdiv = bestdiv / 6;
2463 } else if (bestdiv % 5 == 0) {
2465 *qdiv = bestdiv / 10;
2467 } else if (bestdiv % 14 == 0) {
2469 *qdiv = bestdiv / 14;
2473 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2477 } else { /* 9, 15, 21 */
2478 *pdiv = bestdiv / 3;
2485 static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
2486 u32 dco_freq, u32 ref_freq,
2487 int pdiv, int qdiv, int kdiv)
2502 WARN(1, "Incorrect KDiv\n");
2519 WARN(1, "Incorrect PDiv\n");
2522 WARN_ON(kdiv != 2 && qdiv != 1);
2524 params->qdiv_ratio = qdiv;
2525 params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2527 dco = div_u64((u64)dco_freq << 15, ref_freq);
2529 params->dco_integer = dco >> 15;
2530 params->dco_fraction = dco & 0x7fff;
2534 __cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
2535 struct skl_wrpll_params *wrpll_params,
2538 u32 afe_clock = crtc_state->port_clock * 5;
2539 u32 dco_min = 7998000;
2540 u32 dco_max = 10000000;
2541 u32 dco_mid = (dco_min + dco_max) / 2;
2542 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
2543 18, 20, 24, 28, 30, 32, 36, 40,
2544 42, 44, 48, 50, 52, 54, 56, 60,
2545 64, 66, 68, 70, 72, 76, 78, 80,
2546 84, 88, 90, 92, 96, 98, 100, 102,
2547 3, 5, 7, 9, 15, 21 };
2548 u32 dco, best_dco = 0, dco_centrality = 0;
2549 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2550 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2552 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2553 dco = afe_clock * dividers[d];
2555 if ((dco <= dco_max) && (dco >= dco_min)) {
2556 dco_centrality = abs(dco - dco_mid);
2558 if (dco_centrality < best_dco_centrality) {
2559 best_dco_centrality = dco_centrality;
2560 best_div = dividers[d];
2569 cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2570 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
2577 cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
2578 struct skl_wrpll_params *wrpll_params)
2580 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2582 return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
2583 i915->dpll.ref_clks.nssc);
2586 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
2589 struct skl_wrpll_params wrpll_params = { 0, };
2591 cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2593 if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
2596 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2597 wrpll_params.dco_integer;
2599 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2600 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2601 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2602 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2603 DPLL_CFGCR1_CENTRAL_FREQ;
2605 memset(&crtc_state->dpll_hw_state, 0,
2606 sizeof(crtc_state->dpll_hw_state));
2608 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2609 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2613 static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
2614 const struct intel_shared_dpll *pll,
2617 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
2618 u32 p0, p1, p2, dco_freq;
2620 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
2621 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
2623 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
2624 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2625 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2631 case DPLL_CFGCR1_PDIV_2:
2634 case DPLL_CFGCR1_PDIV_3:
2637 case DPLL_CFGCR1_PDIV_5:
2640 case DPLL_CFGCR1_PDIV_7:
2646 case DPLL_CFGCR1_KDIV_1:
2649 case DPLL_CFGCR1_KDIV_2:
2652 case DPLL_CFGCR1_KDIV_3:
2657 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
2660 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2661 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
2663 if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
2666 return dco_freq / (p0 * p1 * p2 * 5);
2669 static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
2670 const struct intel_shared_dpll *pll)
2672 return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);
2676 cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2680 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2682 switch (crtc_state->port_clock / 2) {
2684 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2687 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2690 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2694 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2697 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2700 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2703 /* Some SKUs may require elevated I/O voltage to support this */
2704 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2707 /* Some SKUs may require elevated I/O voltage to support this */
2708 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2712 memset(&crtc_state->dpll_hw_state, 0,
2713 sizeof(crtc_state->dpll_hw_state));
2715 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2720 static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
2721 const struct intel_shared_dpll *pll)
2725 switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
2726 case DPLL_CFGCR0_LINK_RATE_810:
2729 case DPLL_CFGCR0_LINK_RATE_1080:
2730 link_clock = 108000;
2732 case DPLL_CFGCR0_LINK_RATE_1350:
2733 link_clock = 135000;
2735 case DPLL_CFGCR0_LINK_RATE_1620:
2736 link_clock = 162000;
2738 case DPLL_CFGCR0_LINK_RATE_2160:
2739 link_clock = 216000;
2741 case DPLL_CFGCR0_LINK_RATE_2700:
2742 link_clock = 270000;
2744 case DPLL_CFGCR0_LINK_RATE_3240:
2745 link_clock = 324000;
2747 case DPLL_CFGCR0_LINK_RATE_4050:
2748 link_clock = 405000;
2751 drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
2755 return link_clock * 2;
2758 static bool cnl_get_dpll(struct intel_atomic_state *state,
2759 struct intel_crtc *crtc,
2760 struct intel_encoder *encoder)
2762 struct intel_crtc_state *crtc_state =
2763 intel_atomic_get_new_crtc_state(state, crtc);
2764 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2765 struct intel_shared_dpll *pll;
2768 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2769 bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
2771 drm_dbg_kms(&i915->drm,
2772 "Could not get HDMI pll dividers.\n");
2775 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2776 bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
2778 drm_dbg_kms(&i915->drm,
2779 "Could not set DP dpll HW state.\n");
2783 drm_dbg_kms(&i915->drm,
2784 "Skip DPLL setup for output_types 0x%x\n",
2785 crtc_state->output_types);
2789 pll = intel_find_shared_dpll(state, crtc,
2790 &crtc_state->dpll_hw_state,
2791 BIT(DPLL_ID_SKL_DPLL2) |
2792 BIT(DPLL_ID_SKL_DPLL1) |
2793 BIT(DPLL_ID_SKL_DPLL0));
2795 drm_dbg_kms(&i915->drm, "No PLL selected\n");
2799 intel_reference_shared_dpll(state, crtc,
2800 pll, &crtc_state->dpll_hw_state);
2802 crtc_state->shared_dpll = pll;
2807 static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
2808 const struct intel_shared_dpll *pll)
2810 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
2811 return cnl_ddi_wrpll_get_freq(i915, pll);
2813 return cnl_ddi_lcpll_get_freq(i915, pll);
2816 static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
2818 /* No SSC reference */
2819 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
2822 static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
2823 const struct intel_dpll_hw_state *hw_state)
2825 drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
2826 "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
2831 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2832 .enable = cnl_ddi_pll_enable,
2833 .disable = cnl_ddi_pll_disable,
2834 .get_hw_state = cnl_ddi_pll_get_hw_state,
2835 .get_freq = cnl_ddi_pll_get_freq,
2838 static const struct dpll_info cnl_plls[] = {
2839 { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2840 { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2841 { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2845 static const struct intel_dpll_mgr cnl_pll_mgr = {
2846 .dpll_info = cnl_plls,
2847 .get_dplls = cnl_get_dpll,
2848 .put_dplls = intel_put_dpll,
2849 .update_ref_clks = cnl_update_dpll_ref_clks,
2850 .dump_hw_state = cnl_dump_hw_state,
2853 struct icl_combo_pll_params {
2855 struct skl_wrpll_params wrpll;
2859 * These values alrea already adjusted: they're the bits we write to the
2860 * registers, not the logical values.
2862 static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
2864 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
2865 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2867 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
2868 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2870 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
2871 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2873 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
2874 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2876 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */
2877 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2879 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */
2880 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2882 { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */
2883 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2885 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
2886 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2890 /* Also used for 38.4 MHz values. */
2891 static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
2893 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
2894 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2896 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
2897 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2899 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
2900 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2902 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
2903 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2905 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */
2906 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2908 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */
2909 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2911 { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
2912 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2914 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
2915 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2918 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2919 .dco_integer = 0x151, .dco_fraction = 0x4000,
2920 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2923 static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2924 .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2925 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2928 static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
2929 .dco_integer = 0x54, .dco_fraction = 0x3000,
2930 /* the following params are unused */
2931 .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2934 static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
2935 .dco_integer = 0x43, .dco_fraction = 0x4000,
2936 /* the following params are unused */
2940 * Display WA #22010492432: tgl
2941 * Divide the nominal .dco_fraction value by 2.
2943 static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
2944 .dco_integer = 0x54, .dco_fraction = 0x1800,
2945 /* the following params are unused */
2946 .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2949 static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
2950 struct skl_wrpll_params *pll_params)
2952 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2953 const struct icl_combo_pll_params *params =
2954 dev_priv->dpll.ref_clks.nssc == 24000 ?
2955 icl_dp_combo_pll_24MHz_values :
2956 icl_dp_combo_pll_19_2MHz_values;
2957 int clock = crtc_state->port_clock;
2960 for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
2961 if (clock == params[i].clock) {
2962 *pll_params = params[i].wrpll;
2967 MISSING_CASE(clock);
2971 static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
2972 struct skl_wrpll_params *pll_params)
2974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2976 if (INTEL_GEN(dev_priv) >= 12) {
2977 switch (dev_priv->dpll.ref_clks.nssc) {
2979 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
2982 *pll_params = tgl_tbt_pll_19_2MHz_values;
2985 *pll_params = tgl_tbt_pll_24MHz_values;
2988 *pll_params = tgl_tbt_pll_38_4MHz_values;
2992 switch (dev_priv->dpll.ref_clks.nssc) {
2994 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
2998 *pll_params = icl_tbt_pll_19_2MHz_values;
3001 *pll_params = icl_tbt_pll_24MHz_values;
3009 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
3010 const struct intel_shared_dpll *pll)
3013 * The PLL outputs multiple frequencies at the same time, selection is
3014 * made at DDI clock mux level.
3016 drm_WARN_ON(&i915->drm, 1);
3021 static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
3023 int ref_clock = i915->dpll.ref_clks.nssc;
3026 * For ICL+, the spec states: if reference frequency is 38.4,
3027 * use 19.2 because the DPLL automatically divides that by 2.
3029 if (ref_clock == 38400)
3036 icl_calc_wrpll(struct intel_crtc_state *crtc_state,
3037 struct skl_wrpll_params *wrpll_params)
3039 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
3041 return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
3042 icl_wrpll_ref_clock(i915));
3045 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
3046 const struct intel_shared_dpll *pll)
3048 return __cnl_ddi_wrpll_get_freq(i915, pll,
3049 icl_wrpll_ref_clock(i915));
3052 static void icl_calc_dpll_state(struct drm_i915_private *i915,
3053 const struct skl_wrpll_params *pll_params,
3054 struct intel_dpll_hw_state *pll_state)
3056 memset(pll_state, 0, sizeof(*pll_state));
3058 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) |
3059 pll_params->dco_integer;
3061 pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
3062 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
3063 DPLL_CFGCR1_KDIV(pll_params->kdiv) |
3064 DPLL_CFGCR1_PDIV(pll_params->pdiv);
3066 if (INTEL_GEN(i915) >= 12)
3067 pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
3069 pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
3072 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
3074 return id - DPLL_ID_ICL_MGPLL1;
3077 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
3079 return tc_port + DPLL_ID_ICL_MGPLL1;
3082 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
3083 u32 *target_dco_khz,
3084 struct intel_dpll_hw_state *state,
3087 u32 dco_min_freq, dco_max_freq;
3088 int div1_vals[] = {7, 5, 3, 2};
3092 dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
3093 dco_max_freq = is_dp ? 8100000 : 10000000;
3095 for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
3096 int div1 = div1_vals[i];
3098 for (div2 = 10; div2 > 0; div2--) {
3099 int dco = div1 * div2 * clock_khz * 5;
3100 int a_divratio, tlinedrv, inputsel;
3103 if (dco < dco_min_freq || dco > dco_max_freq)
3108 * Note: a_divratio not matching TGL BSpec
3109 * algorithm but matching hardcoded values and
3110 * working on HW for DP alt-mode at least
3112 a_divratio = is_dp ? 10 : 5;
3113 tlinedrv = is_dkl ? 1 : 2;
3118 inputsel = is_dp ? 0 : 1;
3125 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
3128 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
3131 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
3134 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
3138 *target_dco_khz = dco;
3140 state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
3142 state->mg_clktop2_coreclkctl1 =
3143 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
3145 state->mg_clktop2_hsclkctl =
3146 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
3147 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
3149 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
3159 * The specification for this function uses real numbers, so the math had to be
3160 * adapted to integer-only calculation, that's why it looks so different.
3162 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
3163 struct intel_dpll_hw_state *pll_state)
3165 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3166 int refclk_khz = dev_priv->dpll.ref_clks.nssc;
3167 int clock = crtc_state->port_clock;
3168 u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
3169 u32 iref_ndiv, iref_trim, iref_pulse_w;
3170 u32 prop_coeff, int_coeff;
3171 u32 tdc_targetcnt, feedfwgain;
3172 u64 ssc_stepsize, ssc_steplen, ssc_steplog;
3174 bool use_ssc = false;
3175 bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
3176 bool is_dkl = INTEL_GEN(dev_priv) >= 12;
3178 memset(pll_state, 0, sizeof(*pll_state));
3180 if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
3181 pll_state, is_dkl)) {
3182 drm_dbg_kms(&dev_priv->drm,
3183 "Failed to find divisors for clock %d\n", clock);
3188 m2div_int = dco_khz / (refclk_khz * m1div);
3189 if (m2div_int > 255) {
3192 m2div_int = dco_khz / (refclk_khz * m1div);
3195 if (m2div_int > 255) {
3196 drm_dbg_kms(&dev_priv->drm,
3197 "Failed to find mdiv for clock %d\n",
3202 m2div_rem = dco_khz % (refclk_khz * m1div);
3204 tmp = (u64)m2div_rem * (1 << 22);
3205 do_div(tmp, refclk_khz * m1div);
3208 switch (refclk_khz) {
3225 MISSING_CASE(refclk_khz);
3230 * tdc_res = 0.000003
3231 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
3233 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
3234 * was supposed to be a division, but we rearranged the operations of
3235 * the formula to avoid early divisions so we don't multiply the
3238 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
3239 * we also rearrange to work with integers.
3241 * The 0.5 transformed to 5 results in a multiplication by 10 and the
3242 * last division by 10.
3244 tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
3247 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
3248 * 32 bits. That's not a problem since we round the division down
3251 feedfwgain = (use_ssc || m2div_rem > 0) ?
3252 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
3254 if (dco_khz >= 9000000) {
3263 tmp = mul_u32_u32(dco_khz, 47 * 32);
3264 do_div(tmp, refclk_khz * m1div * 10000);
3267 tmp = mul_u32_u32(dco_khz, 1000);
3268 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
3275 /* write pll_state calculations */
3277 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
3278 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
3279 DKL_PLL_DIV0_FBPREDIV(m1div) |
3280 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
3282 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
3283 DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
3285 pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
3286 DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
3287 DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
3288 (use_ssc ? DKL_PLL_SSC_EN : 0);
3290 pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
3291 DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
3293 pll_state->mg_pll_tdc_coldst_bias =
3294 DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
3295 DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
3298 pll_state->mg_pll_div0 =
3299 (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
3300 MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
3301 MG_PLL_DIV0_FBDIV_INT(m2div_int);
3303 pll_state->mg_pll_div1 =
3304 MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
3305 MG_PLL_DIV1_DITHER_DIV_2 |
3306 MG_PLL_DIV1_NDIVRATIO(1) |
3307 MG_PLL_DIV1_FBPREDIV(m1div);
3309 pll_state->mg_pll_lf =
3310 MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
3311 MG_PLL_LF_AFCCNTSEL_512 |
3312 MG_PLL_LF_GAINCTRL(1) |
3313 MG_PLL_LF_INT_COEFF(int_coeff) |
3314 MG_PLL_LF_PROP_COEFF(prop_coeff);
3316 pll_state->mg_pll_frac_lock =
3317 MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
3318 MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
3319 MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
3320 MG_PLL_FRAC_LOCK_DCODITHEREN |
3321 MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
3322 if (use_ssc || m2div_rem > 0)
3323 pll_state->mg_pll_frac_lock |=
3324 MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
3326 pll_state->mg_pll_ssc =
3327 (use_ssc ? MG_PLL_SSC_EN : 0) |
3328 MG_PLL_SSC_TYPE(2) |
3329 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
3330 MG_PLL_SSC_STEPNUM(ssc_steplog) |
3332 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
3334 pll_state->mg_pll_tdc_coldst_bias =
3335 MG_PLL_TDC_COLDST_COLDSTART |
3336 MG_PLL_TDC_COLDST_IREFINT_EN |
3337 MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
3338 MG_PLL_TDC_TDCOVCCORR_EN |
3339 MG_PLL_TDC_TDCSEL(3);
3341 pll_state->mg_pll_bias =
3342 MG_PLL_BIAS_BIAS_GB_SEL(3) |
3343 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
3344 MG_PLL_BIAS_BIAS_BONUS(10) |
3345 MG_PLL_BIAS_BIASCAL_EN |
3346 MG_PLL_BIAS_CTRIM(12) |
3347 MG_PLL_BIAS_VREF_RDAC(4) |
3348 MG_PLL_BIAS_IREFTRIM(iref_trim);
3350 if (refclk_khz == 38400) {
3351 pll_state->mg_pll_tdc_coldst_bias_mask =
3352 MG_PLL_TDC_COLDST_COLDSTART;
3353 pll_state->mg_pll_bias_mask = 0;
3355 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
3356 pll_state->mg_pll_bias_mask = -1U;
3359 pll_state->mg_pll_tdc_coldst_bias &=
3360 pll_state->mg_pll_tdc_coldst_bias_mask;
3361 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
3367 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
3368 const struct intel_shared_dpll *pll)
3370 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
3371 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
3374 ref_clock = dev_priv->dpll.ref_clks.nssc;
3376 if (INTEL_GEN(dev_priv) >= 12) {
3377 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
3378 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
3379 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
3381 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
3382 m2_frac = pll_state->mg_pll_bias &
3383 DKL_PLL_BIAS_FBDIV_FRAC_MASK;
3384 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
3389 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
3390 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
3392 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
3393 m2_frac = pll_state->mg_pll_div0 &
3394 MG_PLL_DIV0_FBDIV_FRAC_MASK;
3395 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
3401 switch (pll_state->mg_clktop2_hsclkctl &
3402 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
3403 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
3406 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
3409 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
3412 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
3416 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
3420 div2 = (pll_state->mg_clktop2_hsclkctl &
3421 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
3422 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
3424 /* div2 value of 0 is same as 1 means no div */
3429 * Adjust the original formula to delay the division by 2^22 in order to
3430 * minimize possible rounding errors.
3432 tmp = (u64)m1 * m2_int * ref_clock +
3433 (((u64)m1 * m2_frac * ref_clock) >> 22);
3434 tmp = div_u64(tmp, 5 * div1 * div2);
3440 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3441 * @crtc_state: state for the CRTC to select the DPLL for
3442 * @port_dpll_id: the active @port_dpll_id to select
3444 * Select the given @port_dpll_id instance from the DPLLs reserved for the
3447 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
3448 enum icl_port_dpll_id port_dpll_id)
3450 struct icl_port_dpll *port_dpll =
3451 &crtc_state->icl_port_dplls[port_dpll_id];
3453 crtc_state->shared_dpll = port_dpll->pll;
3454 crtc_state->dpll_hw_state = port_dpll->hw_state;
3457 static void icl_update_active_dpll(struct intel_atomic_state *state,
3458 struct intel_crtc *crtc,
3459 struct intel_encoder *encoder)
3461 struct intel_crtc_state *crtc_state =
3462 intel_atomic_get_new_crtc_state(state, crtc);
3463 struct intel_digital_port *primary_port;
3464 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3466 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
3467 enc_to_mst(encoder)->primary :
3468 enc_to_dig_port(encoder);
3471 (primary_port->tc_mode == TC_PORT_DP_ALT ||
3472 primary_port->tc_mode == TC_PORT_LEGACY))
3473 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3475 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3478 static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
3479 struct intel_crtc *crtc,
3480 struct intel_encoder *encoder)
3482 struct intel_crtc_state *crtc_state =
3483 intel_atomic_get_new_crtc_state(state, crtc);
3484 struct skl_wrpll_params pll_params = { };
3485 struct icl_port_dpll *port_dpll =
3486 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3488 enum port port = encoder->port;
3489 unsigned long dpll_mask;
3492 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
3493 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
3494 ret = icl_calc_wrpll(crtc_state, &pll_params);
3496 ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
3499 drm_dbg_kms(&dev_priv->drm,
3500 "Could not calculate combo PHY PLL state.\n");
3505 icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
3507 if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
3509 BIT(DPLL_ID_EHL_DPLL4) |
3510 BIT(DPLL_ID_ICL_DPLL1) |
3511 BIT(DPLL_ID_ICL_DPLL0);
3513 dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
3515 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3516 &port_dpll->hw_state,
3518 if (!port_dpll->pll) {
3519 drm_dbg_kms(&dev_priv->drm,
3520 "No combo PHY PLL found for [ENCODER:%d:%s]\n",
3521 encoder->base.base.id, encoder->base.name);
3525 intel_reference_shared_dpll(state, crtc,
3526 port_dpll->pll, &port_dpll->hw_state);
3528 icl_update_active_dpll(state, crtc, encoder);
3533 static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
3534 struct intel_crtc *crtc,
3535 struct intel_encoder *encoder)
3537 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3538 struct intel_crtc_state *crtc_state =
3539 intel_atomic_get_new_crtc_state(state, crtc);
3540 struct skl_wrpll_params pll_params = { };
3541 struct icl_port_dpll *port_dpll;
3542 enum intel_dpll_id dpll_id;
3544 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3545 if (!icl_calc_tbt_pll(crtc_state, &pll_params)) {
3546 drm_dbg_kms(&dev_priv->drm,
3547 "Could not calculate TBT PLL state.\n");
3551 icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
3553 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3554 &port_dpll->hw_state,
3555 BIT(DPLL_ID_ICL_TBTPLL));
3556 if (!port_dpll->pll) {
3557 drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
3560 intel_reference_shared_dpll(state, crtc,
3561 port_dpll->pll, &port_dpll->hw_state);
3564 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3565 if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
3566 drm_dbg_kms(&dev_priv->drm,
3567 "Could not calculate MG PHY PLL state.\n");
3568 goto err_unreference_tbt_pll;
3571 dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
3573 port_dpll->pll = intel_find_shared_dpll(state, crtc,
3574 &port_dpll->hw_state,
3576 if (!port_dpll->pll) {
3577 drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
3578 goto err_unreference_tbt_pll;
3580 intel_reference_shared_dpll(state, crtc,
3581 port_dpll->pll, &port_dpll->hw_state);
3583 icl_update_active_dpll(state, crtc, encoder);
3587 err_unreference_tbt_pll:
3588 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3589 intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
3594 static bool icl_get_dplls(struct intel_atomic_state *state,
3595 struct intel_crtc *crtc,
3596 struct intel_encoder *encoder)
3598 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3599 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3601 if (intel_phy_is_combo(dev_priv, phy))
3602 return icl_get_combo_phy_dpll(state, crtc, encoder);
3603 else if (intel_phy_is_tc(dev_priv, phy))
3604 return icl_get_tc_phy_dplls(state, crtc, encoder);
3611 static void icl_put_dplls(struct intel_atomic_state *state,
3612 struct intel_crtc *crtc)
3614 const struct intel_crtc_state *old_crtc_state =
3615 intel_atomic_get_old_crtc_state(state, crtc);
3616 struct intel_crtc_state *new_crtc_state =
3617 intel_atomic_get_new_crtc_state(state, crtc);
3618 enum icl_port_dpll_id id;
3620 new_crtc_state->shared_dpll = NULL;
3622 for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
3623 const struct icl_port_dpll *old_port_dpll =
3624 &old_crtc_state->icl_port_dplls[id];
3625 struct icl_port_dpll *new_port_dpll =
3626 &new_crtc_state->icl_port_dplls[id];
3628 new_port_dpll->pll = NULL;
3630 if (!old_port_dpll->pll)
3633 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
3637 static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
3638 struct intel_shared_dpll *pll,
3639 struct intel_dpll_hw_state *hw_state)
3641 const enum intel_dpll_id id = pll->info->id;
3642 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3643 intel_wakeref_t wakeref;
3647 wakeref = intel_display_power_get_if_enabled(dev_priv,
3648 POWER_DOMAIN_DISPLAY_CORE);
3652 val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
3653 if (!(val & PLL_ENABLE))
3656 hw_state->mg_refclkin_ctl = intel_de_read(dev_priv,
3657 MG_REFCLKIN_CTL(tc_port));
3658 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3660 hw_state->mg_clktop2_coreclkctl1 =
3661 intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port));
3662 hw_state->mg_clktop2_coreclkctl1 &=
3663 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3665 hw_state->mg_clktop2_hsclkctl =
3666 intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port));
3667 hw_state->mg_clktop2_hsclkctl &=
3668 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3669 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3670 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3671 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3673 hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port));
3674 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port));
3675 hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port));
3676 hw_state->mg_pll_frac_lock = intel_de_read(dev_priv,
3677 MG_PLL_FRAC_LOCK(tc_port));
3678 hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port));
3680 hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
3681 hw_state->mg_pll_tdc_coldst_bias =
3682 intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
3684 if (dev_priv->dpll.ref_clks.nssc == 38400) {
3685 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3686 hw_state->mg_pll_bias_mask = 0;
3688 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3689 hw_state->mg_pll_bias_mask = -1U;
3692 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3693 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3697 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3701 static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
3702 struct intel_shared_dpll *pll,
3703 struct intel_dpll_hw_state *hw_state)
3705 const enum intel_dpll_id id = pll->info->id;
3706 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3707 intel_wakeref_t wakeref;
3711 wakeref = intel_display_power_get_if_enabled(dev_priv,
3712 POWER_DOMAIN_DISPLAY_CORE);
3716 val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
3717 if (!(val & PLL_ENABLE))
3721 * All registers read here have the same HIP_INDEX_REG even though
3722 * they are on different building blocks
3724 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3725 HIP_INDEX_VAL(tc_port, 0x2));
3727 hw_state->mg_refclkin_ctl = intel_de_read(dev_priv,
3728 DKL_REFCLKIN_CTL(tc_port));
3729 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3731 hw_state->mg_clktop2_hsclkctl =
3732 intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
3733 hw_state->mg_clktop2_hsclkctl &=
3734 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3735 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3736 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3737 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3739 hw_state->mg_clktop2_coreclkctl1 =
3740 intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3741 hw_state->mg_clktop2_coreclkctl1 &=
3742 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3744 hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port));
3745 hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK |
3746 DKL_PLL_DIV0_PROP_COEFF_MASK |
3747 DKL_PLL_DIV0_FBPREDIV_MASK |
3748 DKL_PLL_DIV0_FBDIV_INT_MASK);
3750 hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port));
3751 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3752 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3754 hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port));
3755 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3756 DKL_PLL_SSC_STEP_LEN_MASK |
3757 DKL_PLL_SSC_STEP_NUM_MASK |
3760 hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port));
3761 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
3762 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3764 hw_state->mg_pll_tdc_coldst_bias =
3765 intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3766 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3767 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3771 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3775 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
3776 struct intel_shared_dpll *pll,
3777 struct intel_dpll_hw_state *hw_state,
3778 i915_reg_t enable_reg)
3780 const enum intel_dpll_id id = pll->info->id;
3781 intel_wakeref_t wakeref;
3785 wakeref = intel_display_power_get_if_enabled(dev_priv,
3786 POWER_DOMAIN_DISPLAY_CORE);
3790 val = intel_de_read(dev_priv, enable_reg);
3791 if (!(val & PLL_ENABLE))
3794 if (INTEL_GEN(dev_priv) >= 12) {
3795 hw_state->cfgcr0 = intel_de_read(dev_priv,
3796 TGL_DPLL_CFGCR0(id));
3797 hw_state->cfgcr1 = intel_de_read(dev_priv,
3798 TGL_DPLL_CFGCR1(id));
3800 if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
3801 hw_state->cfgcr0 = intel_de_read(dev_priv,
3802 ICL_DPLL_CFGCR0(4));
3803 hw_state->cfgcr1 = intel_de_read(dev_priv,
3804 ICL_DPLL_CFGCR1(4));
3806 hw_state->cfgcr0 = intel_de_read(dev_priv,
3807 ICL_DPLL_CFGCR0(id));
3808 hw_state->cfgcr1 = intel_de_read(dev_priv,
3809 ICL_DPLL_CFGCR1(id));
3815 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3819 static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
3820 struct intel_shared_dpll *pll,
3821 struct intel_dpll_hw_state *hw_state)
3823 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
3825 if (IS_ELKHARTLAKE(dev_priv) &&
3826 pll->info->id == DPLL_ID_EHL_DPLL4) {
3827 enable_reg = MG_PLL_ENABLE(0);
3830 return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
3833 static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
3834 struct intel_shared_dpll *pll,
3835 struct intel_dpll_hw_state *hw_state)
3837 return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
3840 static void icl_dpll_write(struct drm_i915_private *dev_priv,
3841 struct intel_shared_dpll *pll)
3843 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3844 const enum intel_dpll_id id = pll->info->id;
3845 i915_reg_t cfgcr0_reg, cfgcr1_reg;
3847 if (INTEL_GEN(dev_priv) >= 12) {
3848 cfgcr0_reg = TGL_DPLL_CFGCR0(id);
3849 cfgcr1_reg = TGL_DPLL_CFGCR1(id);
3851 if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
3852 cfgcr0_reg = ICL_DPLL_CFGCR0(4);
3853 cfgcr1_reg = ICL_DPLL_CFGCR1(4);
3855 cfgcr0_reg = ICL_DPLL_CFGCR0(id);
3856 cfgcr1_reg = ICL_DPLL_CFGCR1(id);
3860 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
3861 intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
3862 intel_de_posting_read(dev_priv, cfgcr1_reg);
3865 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3866 struct intel_shared_dpll *pll)
3868 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3869 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3873 * Some of the following registers have reserved fields, so program
3874 * these with RMW based on a mask. The mask can be fixed or generated
3875 * during the calc/readout phase if the mask depends on some other HW
3876 * state like refclk, see icl_calc_mg_pll_state().
3878 val = intel_de_read(dev_priv, MG_REFCLKIN_CTL(tc_port));
3879 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3880 val |= hw_state->mg_refclkin_ctl;
3881 intel_de_write(dev_priv, MG_REFCLKIN_CTL(tc_port), val);
3883 val = intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port));
3884 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3885 val |= hw_state->mg_clktop2_coreclkctl1;
3886 intel_de_write(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), val);
3888 val = intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port));
3889 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3890 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3891 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3892 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3893 val |= hw_state->mg_clktop2_hsclkctl;
3894 intel_de_write(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), val);
3896 intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3897 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3898 intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3899 intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port),
3900 hw_state->mg_pll_frac_lock);
3901 intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3903 val = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
3904 val &= ~hw_state->mg_pll_bias_mask;
3905 val |= hw_state->mg_pll_bias;
3906 intel_de_write(dev_priv, MG_PLL_BIAS(tc_port), val);
3908 val = intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
3909 val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
3910 val |= hw_state->mg_pll_tdc_coldst_bias;
3911 intel_de_write(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), val);
3913 intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
3916 static void dkl_pll_write(struct drm_i915_private *dev_priv,
3917 struct intel_shared_dpll *pll)
3919 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3920 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3924 * All registers programmed here have the same HIP_INDEX_REG even
3925 * though on different building block
3927 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3928 HIP_INDEX_VAL(tc_port, 0x2));
3930 /* All the registers are RMW */
3931 val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port));
3932 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3933 val |= hw_state->mg_refclkin_ctl;
3934 intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val);
3936 val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3937 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3938 val |= hw_state->mg_clktop2_coreclkctl1;
3939 intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
3941 val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
3942 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3943 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3944 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3945 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3946 val |= hw_state->mg_clktop2_hsclkctl;
3947 intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
3949 val = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port));
3950 val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
3951 DKL_PLL_DIV0_PROP_COEFF_MASK |
3952 DKL_PLL_DIV0_FBPREDIV_MASK |
3953 DKL_PLL_DIV0_FBDIV_INT_MASK);
3954 val |= hw_state->mg_pll_div0;
3955 intel_de_write(dev_priv, DKL_PLL_DIV0(tc_port), val);
3957 val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port));
3958 val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
3959 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3960 val |= hw_state->mg_pll_div1;
3961 intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port), val);
3963 val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port));
3964 val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3965 DKL_PLL_SSC_STEP_LEN_MASK |
3966 DKL_PLL_SSC_STEP_NUM_MASK |
3968 val |= hw_state->mg_pll_ssc;
3969 intel_de_write(dev_priv, DKL_PLL_SSC(tc_port), val);
3971 val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port));
3972 val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
3973 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3974 val |= hw_state->mg_pll_bias;
3975 intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port), val);
3977 val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3978 val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3979 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3980 val |= hw_state->mg_pll_tdc_coldst_bias;
3981 intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
3983 intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3986 static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
3987 struct intel_shared_dpll *pll,
3988 i915_reg_t enable_reg)
3992 val = intel_de_read(dev_priv, enable_reg);
3993 val |= PLL_POWER_ENABLE;
3994 intel_de_write(dev_priv, enable_reg, val);
3997 * The spec says we need to "wait" but it also says it should be
4000 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1))
4001 drm_err(&dev_priv->drm, "PLL %d Power not enabled\n",
4005 static void icl_pll_enable(struct drm_i915_private *dev_priv,
4006 struct intel_shared_dpll *pll,
4007 i915_reg_t enable_reg)
4011 val = intel_de_read(dev_priv, enable_reg);
4013 intel_de_write(dev_priv, enable_reg, val);
4015 /* Timeout is actually 600us. */
4016 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1))
4017 drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id);
4020 static void combo_pll_enable(struct drm_i915_private *dev_priv,
4021 struct intel_shared_dpll *pll)
4023 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
4025 if (IS_ELKHARTLAKE(dev_priv) &&
4026 pll->info->id == DPLL_ID_EHL_DPLL4) {
4027 enable_reg = MG_PLL_ENABLE(0);
4030 * We need to disable DC states when this DPLL is enabled.
4031 * This can be done by taking a reference on DPLL4 power
4034 pll->wakeref = intel_display_power_get(dev_priv,
4035 POWER_DOMAIN_DPLL_DC_OFF);
4038 icl_pll_power_enable(dev_priv, pll, enable_reg);
4040 icl_dpll_write(dev_priv, pll);
4043 * DVFS pre sequence would be here, but in our driver the cdclk code
4044 * paths should already be setting the appropriate voltage, hence we do
4048 icl_pll_enable(dev_priv, pll, enable_reg);
4050 /* DVFS post sequence would be here. See the comment above. */
4053 static void tbt_pll_enable(struct drm_i915_private *dev_priv,
4054 struct intel_shared_dpll *pll)
4056 icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE);
4058 icl_dpll_write(dev_priv, pll);
4061 * DVFS pre sequence would be here, but in our driver the cdclk code
4062 * paths should already be setting the appropriate voltage, hence we do
4066 icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE);
4068 /* DVFS post sequence would be here. See the comment above. */
4071 static void mg_pll_enable(struct drm_i915_private *dev_priv,
4072 struct intel_shared_dpll *pll)
4074 i915_reg_t enable_reg =
4075 MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
4077 icl_pll_power_enable(dev_priv, pll, enable_reg);
4079 if (INTEL_GEN(dev_priv) >= 12)
4080 dkl_pll_write(dev_priv, pll);
4082 icl_mg_pll_write(dev_priv, pll);
4085 * DVFS pre sequence would be here, but in our driver the cdclk code
4086 * paths should already be setting the appropriate voltage, hence we do
4090 icl_pll_enable(dev_priv, pll, enable_reg);
4092 /* DVFS post sequence would be here. See the comment above. */
4095 static void icl_pll_disable(struct drm_i915_private *dev_priv,
4096 struct intel_shared_dpll *pll,
4097 i915_reg_t enable_reg)
4101 /* The first steps are done by intel_ddi_post_disable(). */
4104 * DVFS pre sequence would be here, but in our driver the cdclk code
4105 * paths should already be setting the appropriate voltage, hence we do
4109 val = intel_de_read(dev_priv, enable_reg);
4111 intel_de_write(dev_priv, enable_reg, val);
4113 /* Timeout is actually 1us. */
4114 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1))
4115 drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id);
4117 /* DVFS post sequence would be here. See the comment above. */
4119 val = intel_de_read(dev_priv, enable_reg);
4120 val &= ~PLL_POWER_ENABLE;
4121 intel_de_write(dev_priv, enable_reg, val);
4124 * The spec says we need to "wait" but it also says it should be
4127 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1))
4128 drm_err(&dev_priv->drm, "PLL %d Power not disabled\n",
4132 static void combo_pll_disable(struct drm_i915_private *dev_priv,
4133 struct intel_shared_dpll *pll)
4135 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
4137 if (IS_ELKHARTLAKE(dev_priv) &&
4138 pll->info->id == DPLL_ID_EHL_DPLL4) {
4139 enable_reg = MG_PLL_ENABLE(0);
4140 icl_pll_disable(dev_priv, pll, enable_reg);
4142 intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
4147 icl_pll_disable(dev_priv, pll, enable_reg);
4150 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
4151 struct intel_shared_dpll *pll)
4153 icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
4156 static void mg_pll_disable(struct drm_i915_private *dev_priv,
4157 struct intel_shared_dpll *pll)
4159 i915_reg_t enable_reg =
4160 MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
4162 icl_pll_disable(dev_priv, pll, enable_reg);
4165 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
4168 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
4171 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
4172 const struct intel_dpll_hw_state *hw_state)
4174 drm_dbg_kms(&dev_priv->drm,
4175 "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
4176 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
4177 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
4178 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
4179 "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
4180 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
4181 hw_state->cfgcr0, hw_state->cfgcr1,
4182 hw_state->mg_refclkin_ctl,
4183 hw_state->mg_clktop2_coreclkctl1,
4184 hw_state->mg_clktop2_hsclkctl,
4185 hw_state->mg_pll_div0,
4186 hw_state->mg_pll_div1,
4187 hw_state->mg_pll_lf,
4188 hw_state->mg_pll_frac_lock,
4189 hw_state->mg_pll_ssc,
4190 hw_state->mg_pll_bias,
4191 hw_state->mg_pll_tdc_coldst_bias);
4194 static const struct intel_shared_dpll_funcs combo_pll_funcs = {
4195 .enable = combo_pll_enable,
4196 .disable = combo_pll_disable,
4197 .get_hw_state = combo_pll_get_hw_state,
4198 .get_freq = icl_ddi_combo_pll_get_freq,
4201 static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
4202 .enable = tbt_pll_enable,
4203 .disable = tbt_pll_disable,
4204 .get_hw_state = tbt_pll_get_hw_state,
4205 .get_freq = icl_ddi_tbt_pll_get_freq,
4208 static const struct intel_shared_dpll_funcs mg_pll_funcs = {
4209 .enable = mg_pll_enable,
4210 .disable = mg_pll_disable,
4211 .get_hw_state = mg_pll_get_hw_state,
4212 .get_freq = icl_ddi_mg_pll_get_freq,
4215 static const struct dpll_info icl_plls[] = {
4216 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4217 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4218 { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
4219 { "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
4220 { "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
4221 { "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
4222 { "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
4226 static const struct intel_dpll_mgr icl_pll_mgr = {
4227 .dpll_info = icl_plls,
4228 .get_dplls = icl_get_dplls,
4229 .put_dplls = icl_put_dplls,
4230 .update_active_dpll = icl_update_active_dpll,
4231 .update_ref_clks = icl_update_dpll_ref_clks,
4232 .dump_hw_state = icl_dump_hw_state,
4235 static const struct dpll_info ehl_plls[] = {
4236 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4237 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4238 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4242 static const struct intel_dpll_mgr ehl_pll_mgr = {
4243 .dpll_info = ehl_plls,
4244 .get_dplls = icl_get_dplls,
4245 .put_dplls = icl_put_dplls,
4246 .update_ref_clks = icl_update_dpll_ref_clks,
4247 .dump_hw_state = icl_dump_hw_state,
4250 static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
4251 .enable = mg_pll_enable,
4252 .disable = mg_pll_disable,
4253 .get_hw_state = dkl_pll_get_hw_state,
4254 .get_freq = icl_ddi_mg_pll_get_freq,
4257 static const struct dpll_info tgl_plls[] = {
4258 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4259 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4260 { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
4261 { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
4262 { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
4263 { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
4264 { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
4265 { "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
4266 { "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
4270 static const struct intel_dpll_mgr tgl_pll_mgr = {
4271 .dpll_info = tgl_plls,
4272 .get_dplls = icl_get_dplls,
4273 .put_dplls = icl_put_dplls,
4274 .update_active_dpll = icl_update_active_dpll,
4275 .update_ref_clks = icl_update_dpll_ref_clks,
4276 .dump_hw_state = icl_dump_hw_state,
4280 * intel_shared_dpll_init - Initialize shared DPLLs
4283 * Initialize shared DPLLs for @dev.
4285 void intel_shared_dpll_init(struct drm_device *dev)
4287 struct drm_i915_private *dev_priv = to_i915(dev);
4288 const struct intel_dpll_mgr *dpll_mgr = NULL;
4289 const struct dpll_info *dpll_info;
4292 if (INTEL_GEN(dev_priv) >= 12)
4293 dpll_mgr = &tgl_pll_mgr;
4294 else if (IS_ELKHARTLAKE(dev_priv))
4295 dpll_mgr = &ehl_pll_mgr;
4296 else if (INTEL_GEN(dev_priv) >= 11)
4297 dpll_mgr = &icl_pll_mgr;
4298 else if (IS_CANNONLAKE(dev_priv))
4299 dpll_mgr = &cnl_pll_mgr;
4300 else if (IS_GEN9_BC(dev_priv))
4301 dpll_mgr = &skl_pll_mgr;
4302 else if (IS_GEN9_LP(dev_priv))
4303 dpll_mgr = &bxt_pll_mgr;
4304 else if (HAS_DDI(dev_priv))
4305 dpll_mgr = &hsw_pll_mgr;
4306 else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
4307 dpll_mgr = &pch_pll_mgr;
4310 dev_priv->dpll.num_shared_dpll = 0;
4314 dpll_info = dpll_mgr->dpll_info;
4316 for (i = 0; dpll_info[i].name; i++) {
4317 drm_WARN_ON(dev, i != dpll_info[i].id);
4318 dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
4321 dev_priv->dpll.mgr = dpll_mgr;
4322 dev_priv->dpll.num_shared_dpll = i;
4323 mutex_init(&dev_priv->dpll.lock);
4325 BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
4329 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4330 * @state: atomic state
4331 * @crtc: CRTC to reserve DPLLs for
4334 * This function reserves all required DPLLs for the given CRTC and encoder
4335 * combination in the current atomic commit @state and the new @crtc atomic
4338 * The new configuration in the atomic commit @state is made effective by
4339 * calling intel_shared_dpll_swap_state().
4341 * The reserved DPLLs should be released by calling
4342 * intel_release_shared_dplls().
4345 * True if all required DPLLs were successfully reserved.
4347 bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
4348 struct intel_crtc *crtc,
4349 struct intel_encoder *encoder)
4351 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4352 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
4354 if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
4357 return dpll_mgr->get_dplls(state, crtc, encoder);
4361 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4362 * @state: atomic state
4363 * @crtc: crtc from which the DPLLs are to be released
4365 * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
4366 * from the current atomic commit @state and the old @crtc atomic state.
4368 * The new configuration in the atomic commit @state is made effective by
4369 * calling intel_shared_dpll_swap_state().
4371 void intel_release_shared_dplls(struct intel_atomic_state *state,
4372 struct intel_crtc *crtc)
4374 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4375 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
4378 * FIXME: this function is called for every platform having a
4379 * compute_clock hook, even though the platform doesn't yet support
4380 * the shared DPLL framework and intel_reserve_shared_dplls() is not
4386 dpll_mgr->put_dplls(state, crtc);
4390 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4391 * @state: atomic state
4392 * @crtc: the CRTC for which to update the active DPLL
4393 * @encoder: encoder determining the type of port DPLL
4395 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4396 * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
4397 * DPLL selected will be based on the current mode of the encoder's port.
4399 void intel_update_active_dpll(struct intel_atomic_state *state,
4400 struct intel_crtc *crtc,
4401 struct intel_encoder *encoder)
4403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4404 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
4406 if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
4409 dpll_mgr->update_active_dpll(state, crtc, encoder);
4413 * intel_dpll_get_freq - calculate the DPLL's output frequency
4414 * @i915: i915 device
4415 * @pll: DPLL for which to calculate the output frequency
4417 * Return the output frequency corresponding to @pll's current state.
4419 int intel_dpll_get_freq(struct drm_i915_private *i915,
4420 const struct intel_shared_dpll *pll)
4422 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
4425 return pll->info->funcs->get_freq(i915, pll);
4428 static void readout_dpll_hw_state(struct drm_i915_private *i915,
4429 struct intel_shared_dpll *pll)
4431 struct intel_crtc *crtc;
4433 pll->on = pll->info->funcs->get_hw_state(i915, pll,
4434 &pll->state.hw_state);
4436 if (IS_ELKHARTLAKE(i915) && pll->on &&
4437 pll->info->id == DPLL_ID_EHL_DPLL4) {
4438 pll->wakeref = intel_display_power_get(i915,
4439 POWER_DOMAIN_DPLL_DC_OFF);
4442 pll->state.crtc_mask = 0;
4443 for_each_intel_crtc(&i915->drm, crtc) {
4444 struct intel_crtc_state *crtc_state =
4445 to_intel_crtc_state(crtc->base.state);
4447 if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
4448 pll->state.crtc_mask |= 1 << crtc->pipe;
4450 pll->active_mask = pll->state.crtc_mask;
4452 drm_dbg_kms(&i915->drm,
4453 "%s hw state readout: crtc_mask 0x%08x, on %i\n",
4454 pll->info->name, pll->state.crtc_mask, pll->on);
4457 void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
4461 if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
4462 i915->dpll.mgr->update_ref_clks(i915);
4464 for (i = 0; i < i915->dpll.num_shared_dpll; i++)
4465 readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
4468 static void sanitize_dpll_state(struct drm_i915_private *i915,
4469 struct intel_shared_dpll *pll)
4471 if (!pll->on || pll->active_mask)
4474 drm_dbg_kms(&i915->drm,
4475 "%s enabled but not in use, disabling\n",
4478 pll->info->funcs->disable(i915, pll);
4482 void intel_dpll_sanitize_state(struct drm_i915_private *i915)
4486 for (i = 0; i < i915->dpll.num_shared_dpll; i++)
4487 sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
4491 * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
4492 * @dev_priv: i915 drm device
4493 * @hw_state: hw state to be written to the log
4495 * Write the relevant values in @hw_state to dmesg using drm_dbg_kms.
4497 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
4498 const struct intel_dpll_hw_state *hw_state)
4500 if (dev_priv->dpll.mgr) {
4501 dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
4503 /* fallback for platforms that don't use the shared dpll
4506 drm_dbg_kms(&dev_priv->drm,
4507 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
4508 "fp0: 0x%x, fp1: 0x%x\n",