drivers/gpu/drm/i915/display/intel_dpll.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6 #include "intel_crtc.h"
   7 #include "intel_de.h"
   8 #include "intel_display_types.h"
   9 #include "intel_display.h"
  10 #include "intel_dpll.h"
  11 #include "intel_lvds.h"
  12 #include "intel_panel.h"
  13 #include "intel_sideband.h"
  14
  15 struct intel_limit {
  16         struct {
  17                 int min, max;
  18         } dot, vco, n, m, m1, m2, p, p1;
  19
  20         struct {
  21                 int dot_limit;
  22                 int p2_slow, p2_fast;
  23         } p2;
  24 };
  25 static const struct intel_limit intel_limits_i8xx_dac = {
  26         .dot = { .min = 25000, .max = 350000 },
  27         .vco = { .min = 908000, .max = 1512000 },
  28         .n = { .min = 2, .max = 16 },
  29         .m = { .min = 96, .max = 140 },
  30         .m1 = { .min = 18, .max = 26 },
  31         .m2 = { .min = 6, .max = 16 },
  32         .p = { .min = 4, .max = 128 },
  33         .p1 = { .min = 2, .max = 33 },
  34         .p2 = { .dot_limit = 165000,
  35                 .p2_slow = 4, .p2_fast = 2 },
  36 };
  37
  38 static const struct intel_limit intel_limits_i8xx_dvo = {
  39         .dot = { .min = 25000, .max = 350000 },
  40         .vco = { .min = 908000, .max = 1512000 },
  41         .n = { .min = 2, .max = 16 },
  42         .m = { .min = 96, .max = 140 },
  43         .m1 = { .min = 18, .max = 26 },
  44         .m2 = { .min = 6, .max = 16 },
  45         .p = { .min = 4, .max = 128 },
  46         .p1 = { .min = 2, .max = 33 },
  47         .p2 = { .dot_limit = 165000,
  48                 .p2_slow = 4, .p2_fast = 4 },
  49 };
  50
  51 static const struct intel_limit intel_limits_i8xx_lvds = {
  52         .dot = { .min = 25000, .max = 350000 },
  53         .vco = { .min = 908000, .max = 1512000 },
  54         .n = { .min = 2, .max = 16 },
  55         .m = { .min = 96, .max = 140 },
  56         .m1 = { .min = 18, .max = 26 },
  57         .m2 = { .min = 6, .max = 16 },
  58         .p = { .min = 4, .max = 128 },
  59         .p1 = { .min = 1, .max = 6 },
  60         .p2 = { .dot_limit = 165000,
  61                 .p2_slow = 14, .p2_fast = 7 },
  62 };
  63
  64 static const struct intel_limit intel_limits_i9xx_sdvo = {
  65         .dot = { .min = 20000, .max = 400000 },
  66         .vco = { .min = 1400000, .max = 2800000 },
  67         .n = { .min = 1, .max = 6 },
  68         .m = { .min = 70, .max = 120 },
  69         .m1 = { .min = 8, .max = 18 },
  70         .m2 = { .min = 3, .max = 7 },
  71         .p = { .min = 5, .max = 80 },
  72         .p1 = { .min = 1, .max = 8 },
  73         .p2 = { .dot_limit = 200000,
  74                 .p2_slow = 10, .p2_fast = 5 },
  75 };
  76
  77 static const struct intel_limit intel_limits_i9xx_lvds = {
  78         .dot = { .min = 20000, .max = 400000 },
  79         .vco = { .min = 1400000, .max = 2800000 },
  80         .n = { .min = 1, .max = 6 },
  81         .m = { .min = 70, .max = 120 },
  82         .m1 = { .min = 8, .max = 18 },
  83         .m2 = { .min = 3, .max = 7 },
  84         .p = { .min = 7, .max = 98 },
  85         .p1 = { .min = 1, .max = 8 },
  86         .p2 = { .dot_limit = 112000,
  87                 .p2_slow = 14, .p2_fast = 7 },
  88 };
  89
  90
  91 static const struct intel_limit intel_limits_g4x_sdvo = {
  92         .dot = { .min = 25000, .max = 270000 },
  93         .vco = { .min = 1750000, .max = 3500000},
  94         .n = { .min = 1, .max = 4 },
  95         .m = { .min = 104, .max = 138 },
  96         .m1 = { .min = 17, .max = 23 },
  97         .m2 = { .min = 5, .max = 11 },
  98         .p = { .min = 10, .max = 30 },
  99         .p1 = { .min = 1, .max = 3},
 100         .p2 = { .dot_limit = 270000,
 101                 .p2_slow = 10,
 102                 .p2_fast = 10
 103         },
 104 };
 105
 106 static const struct intel_limit intel_limits_g4x_hdmi = {
 107         .dot = { .min = 22000, .max = 400000 },
 108         .vco = { .min = 1750000, .max = 3500000},
 109         .n = { .min = 1, .max = 4 },
 110         .m = { .min = 104, .max = 138 },
 111         .m1 = { .min = 16, .max = 23 },
 112         .m2 = { .min = 5, .max = 11 },
 113         .p = { .min = 5, .max = 80 },
 114         .p1 = { .min = 1, .max = 8},
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 10, .p2_fast = 5 },
 117 };
 118
 119 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 120         .dot = { .min = 20000, .max = 115000 },
 121         .vco = { .min = 1750000, .max = 3500000 },
 122         .n = { .min = 1, .max = 3 },
 123         .m = { .min = 104, .max = 138 },
 124         .m1 = { .min = 17, .max = 23 },
 125         .m2 = { .min = 5, .max = 11 },
 126         .p = { .min = 28, .max = 112 },
 127         .p1 = { .min = 2, .max = 8 },
 128         .p2 = { .dot_limit = 0,
 129                 .p2_slow = 14, .p2_fast = 14
 130         },
 131 };
 132
 133 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 134         .dot = { .min = 80000, .max = 224000 },
 135         .vco = { .min = 1750000, .max = 3500000 },
 136         .n = { .min = 1, .max = 3 },
 137         .m = { .min = 104, .max = 138 },
 138         .m1 = { .min = 17, .max = 23 },
 139         .m2 = { .min = 5, .max = 11 },
 140         .p = { .min = 14, .max = 42 },
 141         .p1 = { .min = 2, .max = 6 },
 142         .p2 = { .dot_limit = 0,
 143                 .p2_slow = 7, .p2_fast = 7
 144         },
 145 };
 146
 147 static const struct intel_limit pnv_limits_sdvo = {
 148         .dot = { .min = 20000, .max = 400000},
 149         .vco = { .min = 1700000, .max = 3500000 },
 150         /* Pineview's Ncounter is a ring counter */
 151         .n = { .min = 3, .max = 6 },
 152         .m = { .min = 2, .max = 256 },
 153         /* Pineview only has one combined m divider, which we treat as m2. */
 154         .m1 = { .min = 0, .max = 0 },
 155         .m2 = { .min = 0, .max = 254 },
 156         .p = { .min = 5, .max = 80 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 200000,
 159                 .p2_slow = 10, .p2_fast = 5 },
 160 };
 161
 162 static const struct intel_limit pnv_limits_lvds = {
 163         .dot = { .min = 20000, .max = 400000 },
 164         .vco = { .min = 1700000, .max = 3500000 },
 165         .n = { .min = 3, .max = 6 },
 166         .m = { .min = 2, .max = 256 },
 167         .m1 = { .min = 0, .max = 0 },
 168         .m2 = { .min = 0, .max = 254 },
 169         .p = { .min = 7, .max = 112 },
 170         .p1 = { .min = 1, .max = 8 },
 171         .p2 = { .dot_limit = 112000,
 172                 .p2_slow = 14, .p2_fast = 14 },
 173 };
 174
 175 /* Ironlake / Sandybridge
 176  *
 177  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 178  * the range value for them is (actual_value - 2).
 179  */
 180 static const struct intel_limit ilk_limits_dac = {
 181         .dot = { .min = 25000, .max = 350000 },
 182         .vco = { .min = 1760000, .max = 3510000 },
 183         .n = { .min = 1, .max = 5 },
 184         .m = { .min = 79, .max = 127 },
 185         .m1 = { .min = 12, .max = 22 },
 186         .m2 = { .min = 5, .max = 9 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8 },
 189         .p2 = { .dot_limit = 225000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191 };
 192
 193 static const struct intel_limit ilk_limits_single_lvds = {
 194         .dot = { .min = 25000, .max = 350000 },
 195         .vco = { .min = 1760000, .max = 3510000 },
 196         .n = { .min = 1, .max = 3 },
 197         .m = { .min = 79, .max = 118 },
 198         .m1 = { .min = 12, .max = 22 },
 199         .m2 = { .min = 5, .max = 9 },
 200         .p = { .min = 28, .max = 112 },
 201         .p1 = { .min = 2, .max = 8 },
 202         .p2 = { .dot_limit = 225000,
 203                 .p2_slow = 14, .p2_fast = 14 },
 204 };
 205
 206 static const struct intel_limit ilk_limits_dual_lvds = {
 207         .dot = { .min = 25000, .max = 350000 },
 208         .vco = { .min = 1760000, .max = 3510000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 79, .max = 127 },
 211         .m1 = { .min = 12, .max = 22 },
 212         .m2 = { .min = 5, .max = 9 },
 213         .p = { .min = 14, .max = 56 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 225000,
 216                 .p2_slow = 7, .p2_fast = 7 },
 217 };
 218
 219 /* LVDS 100mhz refclk limits. */
 220 static const struct intel_limit ilk_limits_single_lvds_100m = {
 221         .dot = { .min = 25000, .max = 350000 },
 222         .vco = { .min = 1760000, .max = 3510000 },
 223         .n = { .min = 1, .max = 2 },
 224         .m = { .min = 79, .max = 126 },
 225         .m1 = { .min = 12, .max = 22 },
 226         .m2 = { .min = 5, .max = 9 },
 227         .p = { .min = 28, .max = 112 },
 228         .p1 = { .min = 2, .max = 8 },
 229         .p2 = { .dot_limit = 225000,
 230                 .p2_slow = 14, .p2_fast = 14 },
 231 };
 232
 233 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 234         .dot = { .min = 25000, .max = 350000 },
 235         .vco = { .min = 1760000, .max = 3510000 },
 236         .n = { .min = 1, .max = 3 },
 237         .m = { .min = 79, .max = 126 },
 238         .m1 = { .min = 12, .max = 22 },
 239         .m2 = { .min = 5, .max = 9 },
 240         .p = { .min = 14, .max = 42 },
 241         .p1 = { .min = 2, .max = 6 },
 242         .p2 = { .dot_limit = 225000,
 243                 .p2_slow = 7, .p2_fast = 7 },
 244 };
 245
 246 static const struct intel_limit intel_limits_vlv = {
 247          /*
 248           * These are the data rate limits (measured in fast clocks)
 249           * since those are the strictest limits we have. The fast
 250           * clock and actual rate limits are more relaxed, so checking
 251           * them would make no difference.
 252           */
 253         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 254         .vco = { .min = 4000000, .max = 6000000 },
 255         .n = { .min = 1, .max = 7 },
 256         .m1 = { .min = 2, .max = 3 },
 257         .m2 = { .min = 11, .max = 156 },
 258         .p1 = { .min = 2, .max = 3 },
 259         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 260 };
 261
 262 static const struct intel_limit intel_limits_chv = {
 263         /*
 264          * These are the data rate limits (measured in fast clocks)
 265          * since those are the strictest limits we have.  The fast
 266          * clock and actual rate limits are more relaxed, so checking
 267          * them would make no difference.
 268          */
 269         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 270         .vco = { .min = 4800000, .max = 6480000 },
 271         .n = { .min = 1, .max = 1 },
 272         .m1 = { .min = 2, .max = 2 },
 273         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 274         .p1 = { .min = 2, .max = 4 },
 275         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 276 };
 277
 278 static const struct intel_limit intel_limits_bxt = {
 279         /* FIXME: find real dot limits */
 280         .dot = { .min = 0, .max = INT_MAX },
 281         .vco = { .min = 4800000, .max = 6700000 },
 282         .n = { .min = 1, .max = 1 },
 283         .m1 = { .min = 2, .max = 2 },
 284         /* FIXME: find real m2 limits */
 285         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 286         .p1 = { .min = 2, .max = 4 },
 287         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 288 };
 289
 290 /*
 291  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 292  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 293  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 294  * The helpers' return value is the rate of the clock that is fed to the
 295  * display engine's pipe which can be the above fast dot clock rate or a
 296  * divided-down version of it.
 297  */
 298 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 299 int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 300 {
 301         clock->m = clock->m2 + 2;
 302         clock->p = clock->p1 * clock->p2;
 303         if (WARN_ON(clock->n == 0 || clock->p == 0))
 304                 return 0;
 305         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 306         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 307
 308         return clock->dot;
 309 }
 310
 311 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 312 {
 313         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 314 }
 315
 316 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 317 {
 318         clock->m = i9xx_dpll_compute_m(clock);
 319         clock->p = clock->p1 * clock->p2;
 320         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 321                 return 0;
 322         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 323         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 324
 325         return clock->dot;
 326 }
 327
 328 int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return 0;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336
 337         return clock->dot / 5;
 338 }
 339
 340 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 341 {
 342         clock->m = clock->m1 * clock->m2;
 343         clock->p = clock->p1 * clock->p2;
 344         if (WARN_ON(clock->n == 0 || clock->p == 0))
 345                 return 0;
 346         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 347                                            clock->n << 22);
 348         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 349
 350         return clock->dot / 5;
 351 }
 352
 353 /*
 354  * Returns whether the given set of divisors are valid for a given refclk with
 355  * the given connectors.
 356  */
 357 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 358                                const struct intel_limit *limit,
 359                                const struct dpll *clock)
 360 {
 361         if (clock->n < limit->n.min || limit->n.max < clock->n)
 362                 return false;
 363         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 364                 return false;
 365         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 366                 return false;
 367         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 368                 return false;
 369
 370         if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv))
 371                 if (clock->m1 <= clock->m2)
 372                         return false;
 373
 374         if (!IS_LP(dev_priv)) {
 375                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 376                         return false;
 377                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 378                         return false;
 379         }
 380
 381         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 382                 return false;
 383         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 384          * connector, etc., rather than just a single range.
 385          */
 386         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 387                 return false;
 388
 389         return true;
 390 }
 391
 392 static int
 393 i9xx_select_p2_div(const struct intel_limit *limit,
 394                    const struct intel_crtc_state *crtc_state,
 395                    int target)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 398
 399         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 400                 /*
 401                  * For LVDS just rely on its current settings for dual-channel.
 402                  * We haven't figured out how to reliably set up different
 403                  * single/dual channel state, if we even can.
 404                  */
 405                 if (intel_is_dual_link_lvds(dev_priv))
 406                         return limit->p2.p2_fast;
 407                 else
 408                         return limit->p2.p2_slow;
 409         } else {
 410                 if (target < limit->p2.dot_limit)
 411                         return limit->p2.p2_slow;
 412                 else
 413                         return limit->p2.p2_fast;
 414         }
 415 }
 416
 417 /*
 418  * Returns a set of divisors for the desired target clock with the given
 419  * refclk, or FALSE.  The returned values represent the clock equation:
 420  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 421  *
 422  * Target and reference clocks are specified in kHz.
 423  *
 424  * If match_clock is provided, then best_clock P divider must match the P
 425  * divider from @match_clock used for LVDS downclocking.
 426  */
 427 static bool
 428 i9xx_find_best_dpll(const struct intel_limit *limit,
 429                     struct intel_crtc_state *crtc_state,
 430                     int target, int refclk, struct dpll *match_clock,
 431                     struct dpll *best_clock)
 432 {
 433         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 434         struct dpll clock;
 435         int err = target;
 436
 437         memset(best_clock, 0, sizeof(*best_clock));
 438
 439         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 440
 441         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 442              clock.m1++) {
 443                 for (clock.m2 = limit->m2.min;
 444                      clock.m2 <= limit->m2.max; clock.m2++) {
 445                         if (clock.m2 >= clock.m1)
 446                                 break;
 447                         for (clock.n = limit->n.min;
 448                              clock.n <= limit->n.max; clock.n++) {
 449                                 for (clock.p1 = limit->p1.min;
 450                                         clock.p1 <= limit->p1.max; clock.p1++) {
 451                                         int this_err;
 452
 453                                         i9xx_calc_dpll_params(refclk, &clock);
 454                                         if (!intel_pll_is_valid(to_i915(dev),
 455                                                                 limit,
 456                                                                 &clock))
 457                                                 continue;
 458                                         if (match_clock &&
 459                                             clock.p != match_clock->p)
 460                                                 continue;
 461
 462                                         this_err = abs(clock.dot - target);
 463                                         if (this_err < err) {
 464                                                 *best_clock = clock;
 465                                                 err = this_err;
 466                                         }
 467                                 }
 468                         }
 469                 }
 470         }
 471
 472         return (err != target);
 473 }
 474
 475 /*
 476  * Returns a set of divisors for the desired target clock with the given
 477  * refclk, or FALSE.  The returned values represent the clock equation:
 478  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 479  *
 480  * Target and reference clocks are specified in kHz.
 481  *
 482  * If match_clock is provided, then best_clock P divider must match the P
 483  * divider from @match_clock used for LVDS downclocking.
 484  */
 485 static bool
 486 pnv_find_best_dpll(const struct intel_limit *limit,
 487                    struct intel_crtc_state *crtc_state,
 488                    int target, int refclk, struct dpll *match_clock,
 489                    struct dpll *best_clock)
 490 {
 491         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 492         struct dpll clock;
 493         int err = target;
 494
 495         memset(best_clock, 0, sizeof(*best_clock));
 496
 497         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 498
 499         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 500              clock.m1++) {
 501                 for (clock.m2 = limit->m2.min;
 502                      clock.m2 <= limit->m2.max; clock.m2++) {
 503                         for (clock.n = limit->n.min;
 504                              clock.n <= limit->n.max; clock.n++) {
 505                                 for (clock.p1 = limit->p1.min;
 506                                         clock.p1 <= limit->p1.max; clock.p1++) {
 507                                         int this_err;
 508
 509                                         pnv_calc_dpll_params(refclk, &clock);
 510                                         if (!intel_pll_is_valid(to_i915(dev),
 511                                                                 limit,
 512                                                                 &clock))
 513                                                 continue;
 514                                         if (match_clock &&
 515                                             clock.p != match_clock->p)
 516                                                 continue;
 517
 518                                         this_err = abs(clock.dot - target);
 519                                         if (this_err < err) {
 520                                                 *best_clock = clock;
 521                                                 err = this_err;
 522                                         }
 523                                 }
 524                         }
 525                 }
 526         }
 527
 528         return (err != target);
 529 }
 530
 531 /*
 532  * Returns a set of divisors for the desired target clock with the given
 533  * refclk, or FALSE.  The returned values represent the clock equation:
 534  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 535  *
 536  * Target and reference clocks are specified in kHz.
 537  *
 538  * If match_clock is provided, then best_clock P divider must match the P
 539  * divider from @match_clock used for LVDS downclocking.
 540  */
 541 static bool
 542 g4x_find_best_dpll(const struct intel_limit *limit,
 543                    struct intel_crtc_state *crtc_state,
 544                    int target, int refclk, struct dpll *match_clock,
 545                    struct dpll *best_clock)
 546 {
 547         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 548         struct dpll clock;
 549         int max_n;
 550         bool found = false;
 551         /* approximately equals target * 0.00585 */
 552         int err_most = (target >> 8) + (target >> 9);
 553
 554         memset(best_clock, 0, sizeof(*best_clock));
 555
 556         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 557
 558         max_n = limit->n.max;
 559         /* based on hardware requirement, prefer smaller n to precision */
 560         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 561                 /* based on hardware requirement, prefere larger m1,m2 */
 562                 for (clock.m1 = limit->m1.max;
 563                      clock.m1 >= limit->m1.min; clock.m1--) {
 564                         for (clock.m2 = limit->m2.max;
 565                              clock.m2 >= limit->m2.min; clock.m2--) {
 566                                 for (clock.p1 = limit->p1.max;
 567                                      clock.p1 >= limit->p1.min; clock.p1--) {
 568                                         int this_err;
 569
 570                                         i9xx_calc_dpll_params(refclk, &clock);
 571                                         if (!intel_pll_is_valid(to_i915(dev),
 572                                                                 limit,
 573                                                                 &clock))
 574                                                 continue;
 575
 576                                         this_err = abs(clock.dot - target);
 577                                         if (this_err < err_most) {
 578                                                 *best_clock = clock;
 579                                                 err_most = this_err;
 580                                                 max_n = clock.n;
 581                                                 found = true;
 582                                         }
 583                                 }
 584                         }
 585                 }
 586         }
 587         return found;
 588 }
 589
 590 /*
 591  * Check if the calculated PLL configuration is more optimal compared to the
 592  * best configuration and error found so far. Return the calculated error.
 593  */
 594 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 595                                const struct dpll *calculated_clock,
 596                                const struct dpll *best_clock,
 597                                unsigned int best_error_ppm,
 598                                unsigned int *error_ppm)
 599 {
 600         /*
 601          * For CHV ignore the error and consider only the P value.
 602          * Prefer a bigger P value based on HW requirements.
 603          */
 604         if (IS_CHERRYVIEW(to_i915(dev))) {
 605                 *error_ppm = 0;
 606
 607                 return calculated_clock->p > best_clock->p;
 608         }
 609
 610         if (drm_WARN_ON_ONCE(dev, !target_freq))
 611                 return false;
 612
 613         *error_ppm = div_u64(1000000ULL *
 614                                 abs(target_freq - calculated_clock->dot),
 615                              target_freq);
 616         /*
 617          * Prefer a better P value over a better (smaller) error if the error
 618          * is small. Ensure this preference for future configurations too by
 619          * setting the error to 0.
 620          */
 621         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 622                 *error_ppm = 0;
 623
 624                 return true;
 625         }
 626
 627         return *error_ppm + 10 < best_error_ppm;
 628 }
 629
 630 /*
 631  * Returns a set of divisors for the desired target clock with the given
 632  * refclk, or FALSE.  The returned values represent the clock equation:
 633  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 634  */
 635 static bool
 636 vlv_find_best_dpll(const struct intel_limit *limit,
 637                    struct intel_crtc_state *crtc_state,
 638                    int target, int refclk, struct dpll *match_clock,
 639                    struct dpll *best_clock)
 640 {
 641         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 642         struct drm_device *dev = crtc->base.dev;
 643         struct dpll clock;
 644         unsigned int bestppm = 1000000;
 645         /* min update 19.2 MHz */
 646         int max_n = min(limit->n.max, refclk / 19200);
 647         bool found = false;
 648
 649         target *= 5; /* fast clock */
 650
 651         memset(best_clock, 0, sizeof(*best_clock));
 652
 653         /* based on hardware requirement, prefer smaller n to precision */
 654         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 655                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 656                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 657                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 658                                 clock.p = clock.p1 * clock.p2;
 659                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 660                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 661                                         unsigned int ppm;
 662
 663                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 664                                                                      refclk * clock.m1);
 665
 666                                         vlv_calc_dpll_params(refclk, &clock);
 667
 668                                         if (!intel_pll_is_valid(to_i915(dev),
 669                                                                 limit,
 670                                                                 &clock))
 671                                                 continue;
 672
 673                                         if (!vlv_PLL_is_optimal(dev, target,
 674                                                                 &clock,
 675                                                                 best_clock,
 676                                                                 bestppm, &ppm))
 677                                                 continue;
 678
 679                                         *best_clock = clock;
 680                                         bestppm = ppm;
 681                                         found = true;
 682                                 }
 683                         }
 684                 }
 685         }
 686
 687         return found;
 688 }
 689
 690 /*
 691  * Returns a set of divisors for the desired target clock with the given
 692  * refclk, or FALSE.  The returned values represent the clock equation:
 693  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 694  */
 695 static bool
 696 chv_find_best_dpll(const struct intel_limit *limit,
 697                    struct intel_crtc_state *crtc_state,
 698                    int target, int refclk, struct dpll *match_clock,
 699                    struct dpll *best_clock)
 700 {
 701         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 702         struct drm_device *dev = crtc->base.dev;
 703         unsigned int best_error_ppm;
 704         struct dpll clock;
 705         u64 m2;
 706         int found = false;
 707
 708         memset(best_clock, 0, sizeof(*best_clock));
 709         best_error_ppm = 1000000;
 710
 711         /*
 712          * Based on hardware doc, the n always set to 1, and m1 always
 713          * set to 2.  If requires to support 200Mhz refclk, we need to
 714          * revisit this because n may not 1 anymore.
 715          */
 716         clock.n = 1;
 717         clock.m1 = 2;
 718         target *= 5;    /* fast clock */
 719
 720         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 721                 for (clock.p2 = limit->p2.p2_fast;
 722                                 clock.p2 >= limit->p2.p2_slow;
 723                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 724                         unsigned int error_ppm;
 725
 726                         clock.p = clock.p1 * clock.p2;
 727
 728                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 729                                                    refclk * clock.m1);
 730
 731                         if (m2 > INT_MAX/clock.m1)
 732                                 continue;
 733
 734                         clock.m2 = m2;
 735
 736                         chv_calc_dpll_params(refclk, &clock);
 737
 738                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
 739                                 continue;
 740
 741                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 742                                                 best_error_ppm, &error_ppm))
 743                                 continue;
 744
 745                         *best_clock = clock;
 746                         best_error_ppm = error_ppm;
 747                         found = true;
 748                 }
 749         }
 750
 751         return found;
 752 }
 753
 754 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 755                         struct dpll *best_clock)
 756 {
 757         int refclk = 100000;
 758         const struct intel_limit *limit = &intel_limits_bxt;
 759
 760         return chv_find_best_dpll(limit, crtc_state,
 761                                   crtc_state->port_clock, refclk,
 762                                   NULL, best_clock);
 763 }
 764
 765 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
 766 {
 767         return (1 << dpll->n) << 16 | dpll->m2;
 768 }
 769
 770 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 771                                      struct intel_crtc_state *crtc_state,
 772                                      struct dpll *reduced_clock)
 773 {
 774         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 775         u32 fp, fp2 = 0;
 776
 777         if (IS_PINEVIEW(dev_priv)) {
 778                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
 779                 if (reduced_clock)
 780                         fp2 = pnv_dpll_compute_fp(reduced_clock);
 781         } else {
 782                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 783                 if (reduced_clock)
 784                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
 785         }
 786
 787         crtc_state->dpll_hw_state.fp0 = fp;
 788
 789         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 790             reduced_clock) {
 791                 crtc_state->dpll_hw_state.fp1 = fp2;
 792         } else {
 793                 crtc_state->dpll_hw_state.fp1 = fp;
 794         }
 795 }
 796
 797 static void i9xx_compute_dpll(struct intel_crtc *crtc,
 798                               struct intel_crtc_state *crtc_state,
 799                               struct dpll *reduced_clock)
 800 {
 801         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 802         u32 dpll;
 803         struct dpll *clock = &crtc_state->dpll;
 804
 805         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 806
 807         dpll = DPLL_VGA_MODE_DIS;
 808
 809         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 810                 dpll |= DPLLB_MODE_LVDS;
 811         else
 812                 dpll |= DPLLB_MODE_DAC_SERIAL;
 813
 814         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 815             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
 816                 dpll |= (crtc_state->pixel_multiplier - 1)
 817                         << SDVO_MULTIPLIER_SHIFT_HIRES;
 818         }
 819
 820         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 821             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 822                 dpll |= DPLL_SDVO_HIGH_SPEED;
 823
 824         if (intel_crtc_has_dp_encoder(crtc_state))
 825                 dpll |= DPLL_SDVO_HIGH_SPEED;
 826
 827         /* compute bitmask from p1 value */
 828         if (IS_PINEVIEW(dev_priv))
 829                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
 830         else {
 831                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 832                 if (IS_G4X(dev_priv) && reduced_clock)
 833                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 834         }
 835         switch (clock->p2) {
 836         case 5:
 837                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 838                 break;
 839         case 7:
 840                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 841                 break;
 842         case 10:
 843                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 844                 break;
 845         case 14:
 846                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 847                 break;
 848         }
 849         if (DISPLAY_VER(dev_priv) >= 4)
 850                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 851
 852         if (crtc_state->sdvo_tv_clock)
 853                 dpll |= PLL_REF_INPUT_TVCLKINBC;
 854         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 855                  intel_panel_use_ssc(dev_priv))
 856                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 857         else
 858                 dpll |= PLL_REF_INPUT_DREFCLK;
 859
 860         dpll |= DPLL_VCO_ENABLE;
 861         crtc_state->dpll_hw_state.dpll = dpll;
 862
 863         if (DISPLAY_VER(dev_priv) >= 4) {
 864                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 865                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 866                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
 867         }
 868 }
 869
 870 static void i8xx_compute_dpll(struct intel_crtc *crtc,
 871                               struct intel_crtc_state *crtc_state,
 872                               struct dpll *reduced_clock)
 873 {
 874         struct drm_device *dev = crtc->base.dev;
 875         struct drm_i915_private *dev_priv = to_i915(dev);
 876         u32 dpll;
 877         struct dpll *clock = &crtc_state->dpll;
 878
 879         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 880
 881         dpll = DPLL_VGA_MODE_DIS;
 882
 883         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 884                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 885         } else {
 886                 if (clock->p1 == 2)
 887                         dpll |= PLL_P1_DIVIDE_BY_TWO;
 888                 else
 889                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 890                 if (clock->p2 == 4)
 891                         dpll |= PLL_P2_DIVIDE_BY_4;
 892         }
 893
 894         /*
 895          * Bspec:
 896          * "[Almador Errata}: For the correct operation of the muxed DVO pins
 897          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
 898          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
 899          *  Enable) must be set to “1” in both the DPLL A Control Register
 900          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
 901          *
 902          * For simplicity We simply keep both bits always enabled in
 903          * both DPLLS. The spec says we should disable the DVO 2X clock
 904          * when not needed, but this seems to work fine in practice.
 905          */
 906         if (IS_I830(dev_priv) ||
 907             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
 908                 dpll |= DPLL_DVO_2X_MODE;
 909
 910         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 911             intel_panel_use_ssc(dev_priv))
 912                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 913         else
 914                 dpll |= PLL_REF_INPUT_DREFCLK;
 915
 916         dpll |= DPLL_VCO_ENABLE;
 917         crtc_state->dpll_hw_state.dpll = dpll;
 918 }
 919
 920 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
 921                                   struct intel_crtc_state *crtc_state)
 922 {
 923         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 924         struct intel_atomic_state *state =
 925                 to_intel_atomic_state(crtc_state->uapi.state);
 926
 927         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
 928             DISPLAY_VER(dev_priv) >= 11) {
 929                 struct intel_encoder *encoder =
 930                         intel_get_crtc_new_encoder(state, crtc_state);
 931
 932                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
 933                         drm_dbg_kms(&dev_priv->drm,
 934                                     "failed to find PLL for pipe %c\n",
 935                                     pipe_name(crtc->pipe));
 936                         return -EINVAL;
 937                 }
 938         }
 939
 940         return 0;
 941 }
 942
 943 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
 944 {
 945         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
 946 }
 947
 948
 949 static void ilk_compute_dpll(struct intel_crtc *crtc,
 950                              struct intel_crtc_state *crtc_state,
 951                              struct dpll *reduced_clock)
 952 {
 953         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 954         u32 dpll, fp, fp2;
 955         int factor;
 956
 957         /* Enable autotuning of the PLL clock (if permissible) */
 958         factor = 21;
 959         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 960                 if ((intel_panel_use_ssc(dev_priv) &&
 961                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
 962                     (HAS_PCH_IBX(dev_priv) &&
 963                      intel_is_dual_link_lvds(dev_priv)))
 964                         factor = 25;
 965         } else if (crtc_state->sdvo_tv_clock) {
 966                 factor = 20;
 967         }
 968
 969         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 970
 971         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
 972                 fp |= FP_CB_TUNE;
 973
 974         if (reduced_clock) {
 975                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
 976
 977                 if (reduced_clock->m < factor * reduced_clock->n)
 978                         fp2 |= FP_CB_TUNE;
 979         } else {
 980                 fp2 = fp;
 981         }
 982
 983         dpll = 0;
 984
 985         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 986                 dpll |= DPLLB_MODE_LVDS;
 987         else
 988                 dpll |= DPLLB_MODE_DAC_SERIAL;
 989
 990         dpll |= (crtc_state->pixel_multiplier - 1)
 991                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 992
 993         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 994             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 995                 dpll |= DPLL_SDVO_HIGH_SPEED;
 996
 997         if (intel_crtc_has_dp_encoder(crtc_state))
 998                 dpll |= DPLL_SDVO_HIGH_SPEED;
 999
1000         /*
1001          * The high speed IO clock is only really required for
1002          * SDVO/HDMI/DP, but we also enable it for CRT to make it
1003          * possible to share the DPLL between CRT and HDMI. Enabling
1004          * the clock needlessly does no real harm, except use up a
1005          * bit of power potentially.
1006          *
1007          * We'll limit this to IVB with 3 pipes, since it has only two
1008          * DPLLs and so DPLL sharing is the only way to get three pipes
1009          * driving PCH ports at the same time. On SNB we could do this,
1010          * and potentially avoid enabling the second DPLL, but it's not
1011          * clear if it''s a win or loss power wise. No point in doing
1012          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1013          */
1014         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1015             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1016                 dpll |= DPLL_SDVO_HIGH_SPEED;
1017
1018         /* compute bitmask from p1 value */
1019         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1020         /* also FPA1 */
1021         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1022
1023         switch (crtc_state->dpll.p2) {
1024         case 5:
1025                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1026                 break;
1027         case 7:
1028                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1029                 break;
1030         case 10:
1031                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1032                 break;
1033         case 14:
1034                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1035                 break;
1036         }
1037
1038         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1039             intel_panel_use_ssc(dev_priv))
1040                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1041         else
1042                 dpll |= PLL_REF_INPUT_DREFCLK;
1043
1044         dpll |= DPLL_VCO_ENABLE;
1045
1046         crtc_state->dpll_hw_state.dpll = dpll;
1047         crtc_state->dpll_hw_state.fp0 = fp;
1048         crtc_state->dpll_hw_state.fp1 = fp2;
1049 }
1050
1051 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
1052                                   struct intel_crtc_state *crtc_state)
1053 {
1054         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1055         struct intel_atomic_state *state =
1056                 to_intel_atomic_state(crtc_state->uapi.state);
1057         const struct intel_limit *limit;
1058         int refclk = 120000;
1059
1060         memset(&crtc_state->dpll_hw_state, 0,
1061                sizeof(crtc_state->dpll_hw_state));
1062
1063         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1064         if (!crtc_state->has_pch_encoder)
1065                 return 0;
1066
1067         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1068                 if (intel_panel_use_ssc(dev_priv)) {
1069                         drm_dbg_kms(&dev_priv->drm,
1070                                     "using SSC reference clock of %d kHz\n",
1071                                     dev_priv->vbt.lvds_ssc_freq);
1072                         refclk = dev_priv->vbt.lvds_ssc_freq;
1073                 }
1074
1075                 if (intel_is_dual_link_lvds(dev_priv)) {
1076                         if (refclk == 100000)
1077                                 limit = &ilk_limits_dual_lvds_100m;
1078                         else
1079                                 limit = &ilk_limits_dual_lvds;
1080                 } else {
1081                         if (refclk == 100000)
1082                                 limit = &ilk_limits_single_lvds_100m;
1083                         else
1084                                 limit = &ilk_limits_single_lvds;
1085                 }
1086         } else {
1087                 limit = &ilk_limits_dac;
1088         }
1089
1090         if (!crtc_state->clock_set &&
1091             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1092                                 refclk, NULL, &crtc_state->dpll)) {
1093                 drm_err(&dev_priv->drm,
1094                         "Couldn't find PLL settings for mode!\n");
1095                 return -EINVAL;
1096         }
1097
1098         ilk_compute_dpll(crtc, crtc_state, NULL);
1099
1100         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
1101                 drm_dbg_kms(&dev_priv->drm,
1102                             "failed to find PLL for pipe %c\n",
1103                             pipe_name(crtc->pipe));
1104                 return -EINVAL;
1105         }
1106
1107         return 0;
1108 }
1109
1110 void vlv_compute_dpll(struct intel_crtc *crtc,
1111                       struct intel_crtc_state *pipe_config)
1112 {
1113         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1114                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1115         if (crtc->pipe != PIPE_A)
1116                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1117
1118         /* DPLL not used with DSI, but still need the rest set up */
1119         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
1120                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
1121                         DPLL_EXT_BUFFER_ENABLE_VLV;
1122
1123         pipe_config->dpll_hw_state.dpll_md =
1124                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1125 }
1126
1127 void chv_compute_dpll(struct intel_crtc *crtc,
1128                       struct intel_crtc_state *pipe_config)
1129 {
1130         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
1131                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1132         if (crtc->pipe != PIPE_A)
1133                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1134
1135         /* DPLL not used with DSI, but still need the rest set up */
1136         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
1137                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
1138
1139         pipe_config->dpll_hw_state.dpll_md =
1140                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1141 }
1142
1143 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
1144                                   struct intel_crtc_state *crtc_state)
1145 {
1146         int refclk = 100000;
1147         const struct intel_limit *limit = &intel_limits_chv;
1148         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1149
1150         memset(&crtc_state->dpll_hw_state, 0,
1151                sizeof(crtc_state->dpll_hw_state));
1152
1153         if (!crtc_state->clock_set &&
1154             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1155                                 refclk, NULL, &crtc_state->dpll)) {
1156                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
1157                 return -EINVAL;
1158         }
1159
1160         chv_compute_dpll(crtc, crtc_state);
1161
1162         return 0;
1163 }
1164
1165 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
1166                                   struct intel_crtc_state *crtc_state)
1167 {
1168         int refclk = 100000;
1169         const struct intel_limit *limit = &intel_limits_vlv;
1170         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1171
1172         memset(&crtc_state->dpll_hw_state, 0,
1173                sizeof(crtc_state->dpll_hw_state));
1174
1175         if (!crtc_state->clock_set &&
1176             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1177                                 refclk, NULL, &crtc_state->dpll)) {
1178                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
1179                 return -EINVAL;
1180         }
1181
1182         vlv_compute_dpll(crtc, crtc_state);
1183
1184         return 0;
1185 }
1186
1187 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
1188                                   struct intel_crtc_state *crtc_state)
1189 {
1190         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1191         const struct intel_limit *limit;
1192         int refclk = 96000;
1193
1194         memset(&crtc_state->dpll_hw_state, 0,
1195                sizeof(crtc_state->dpll_hw_state));
1196
1197         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1198                 if (intel_panel_use_ssc(dev_priv)) {
1199                         refclk = dev_priv->vbt.lvds_ssc_freq;
1200                         drm_dbg_kms(&dev_priv->drm,
1201                                     "using SSC reference clock of %d kHz\n",
1202                                     refclk);
1203                 }
1204
1205                 if (intel_is_dual_link_lvds(dev_priv))
1206                         limit = &intel_limits_g4x_dual_channel_lvds;
1207                 else
1208                         limit = &intel_limits_g4x_single_channel_lvds;
1209         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1210                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1211                 limit = &intel_limits_g4x_hdmi;
1212         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1213                 limit = &intel_limits_g4x_sdvo;
1214         } else {
1215                 /* The option is for other outputs */
1216                 limit = &intel_limits_i9xx_sdvo;
1217         }
1218
1219         if (!crtc_state->clock_set &&
1220             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1221                                 refclk, NULL, &crtc_state->dpll)) {
1222                 drm_err(&dev_priv->drm,
1223                         "Couldn't find PLL settings for mode!\n");
1224                 return -EINVAL;
1225         }
1226
1227         i9xx_compute_dpll(crtc, crtc_state, NULL);
1228
1229         return 0;
1230 }
1231
1232 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
1233                                   struct intel_crtc_state *crtc_state)
1234 {
1235         struct drm_device *dev = crtc->base.dev;
1236         struct drm_i915_private *dev_priv = to_i915(dev);
1237         const struct intel_limit *limit;
1238         int refclk = 96000;
1239
1240         memset(&crtc_state->dpll_hw_state, 0,
1241                sizeof(crtc_state->dpll_hw_state));
1242
1243         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1244                 if (intel_panel_use_ssc(dev_priv)) {
1245                         refclk = dev_priv->vbt.lvds_ssc_freq;
1246                         drm_dbg_kms(&dev_priv->drm,
1247                                     "using SSC reference clock of %d kHz\n",
1248                                     refclk);
1249                 }
1250
1251                 limit = &pnv_limits_lvds;
1252         } else {
1253                 limit = &pnv_limits_sdvo;
1254         }
1255
1256         if (!crtc_state->clock_set &&
1257             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1258                                 refclk, NULL, &crtc_state->dpll)) {
1259                 drm_err(&dev_priv->drm,
1260                         "Couldn't find PLL settings for mode!\n");
1261                 return -EINVAL;
1262         }
1263
1264         i9xx_compute_dpll(crtc, crtc_state, NULL);
1265
1266         return 0;
1267 }
1268
1269 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
1270                                    struct intel_crtc_state *crtc_state)
1271 {
1272         struct drm_device *dev = crtc->base.dev;
1273         struct drm_i915_private *dev_priv = to_i915(dev);
1274         const struct intel_limit *limit;
1275         int refclk = 96000;
1276
1277         memset(&crtc_state->dpll_hw_state, 0,
1278                sizeof(crtc_state->dpll_hw_state));
1279
1280         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1281                 if (intel_panel_use_ssc(dev_priv)) {
1282                         refclk = dev_priv->vbt.lvds_ssc_freq;
1283                         drm_dbg_kms(&dev_priv->drm,
1284                                     "using SSC reference clock of %d kHz\n",
1285                                     refclk);
1286                 }
1287
1288                 limit = &intel_limits_i9xx_lvds;
1289         } else {
1290                 limit = &intel_limits_i9xx_sdvo;
1291         }
1292
1293         if (!crtc_state->clock_set &&
1294             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1295                                  refclk, NULL, &crtc_state->dpll)) {
1296                 drm_err(&dev_priv->drm,
1297                         "Couldn't find PLL settings for mode!\n");
1298                 return -EINVAL;
1299         }
1300
1301         i9xx_compute_dpll(crtc, crtc_state, NULL);
1302
1303         return 0;
1304 }
1305
1306 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
1307                                    struct intel_crtc_state *crtc_state)
1308 {
1309         struct drm_device *dev = crtc->base.dev;
1310         struct drm_i915_private *dev_priv = to_i915(dev);
1311         const struct intel_limit *limit;
1312         int refclk = 48000;
1313
1314         memset(&crtc_state->dpll_hw_state, 0,
1315                sizeof(crtc_state->dpll_hw_state));
1316
1317         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1318                 if (intel_panel_use_ssc(dev_priv)) {
1319                         refclk = dev_priv->vbt.lvds_ssc_freq;
1320                         drm_dbg_kms(&dev_priv->drm,
1321                                     "using SSC reference clock of %d kHz\n",
1322                                     refclk);
1323                 }
1324
1325                 limit = &intel_limits_i8xx_lvds;
1326         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1327                 limit = &intel_limits_i8xx_dvo;
1328         } else {
1329                 limit = &intel_limits_i8xx_dac;
1330         }
1331
1332         if (!crtc_state->clock_set &&
1333             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1334                                  refclk, NULL, &crtc_state->dpll)) {
1335                 drm_err(&dev_priv->drm,
1336                         "Couldn't find PLL settings for mode!\n");
1337                 return -EINVAL;
1338         }
1339
1340         i8xx_compute_dpll(crtc, crtc_state, NULL);
1341
1342         return 0;
1343 }
1344
1345 void
1346 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1347 {
1348         if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1349                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
1350         else if (HAS_PCH_SPLIT(dev_priv))
1351                 dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
1352         else if (IS_CHERRYVIEW(dev_priv))
1353                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
1354         else if (IS_VALLEYVIEW(dev_priv))
1355                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
1356         else if (IS_G4X(dev_priv))
1357                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
1358         else if (IS_PINEVIEW(dev_priv))
1359                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
1360         else if (DISPLAY_VER(dev_priv) != 2)
1361                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
1362         else
1363                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
1364 }
1365
1366 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1367 {
1368         if (IS_I830(dev_priv))
1369                 return false;
1370
1371         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1372 }
1373
1374 void i9xx_enable_pll(struct intel_crtc *crtc,
1375                      const struct intel_crtc_state *crtc_state)
1376 {
1377         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1378         i915_reg_t reg = DPLL(crtc->pipe);
1379         u32 dpll = crtc_state->dpll_hw_state.dpll;
1380         int i;
1381
1382         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1383
1384         /* PLL is protected by panel, make sure we can write it */
1385         if (i9xx_has_pps(dev_priv))
1386                 assert_panel_unlocked(dev_priv, crtc->pipe);
1387
1388         /*
1389          * Apparently we need to have VGA mode enabled prior to changing
1390          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1391          * dividers, even though the register value does change.
1392          */
1393         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1394         intel_de_write(dev_priv, reg, dpll);
1395
1396         /* Wait for the clocks to stabilize. */
1397         intel_de_posting_read(dev_priv, reg);
1398         udelay(150);
1399
1400         if (DISPLAY_VER(dev_priv) >= 4) {
1401                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1402                                crtc_state->dpll_hw_state.dpll_md);
1403         } else {
1404                 /* The pixel multiplier can only be updated once the
1405                  * DPLL is enabled and the clocks are stable.
1406                  *
1407                  * So write it again.
1408                  */
1409                 intel_de_write(dev_priv, reg, dpll);
1410         }
1411
1412         /* We do this three times for luck */
1413         for (i = 0; i < 3; i++) {
1414                 intel_de_write(dev_priv, reg, dpll);
1415                 intel_de_posting_read(dev_priv, reg);
1416                 udelay(150); /* wait for warmup */
1417         }
1418 }
1419
1420 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1421                                  enum pipe pipe)
1422 {
1423         u32 reg_val;
1424
1425         /*
1426          * PLLB opamp always calibrates to max value of 0x3f, force enable it
1427          * and set it to a reasonable value instead.
1428          */
1429         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1430         reg_val &= 0xffffff00;
1431         reg_val |= 0x00000030;
1432         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1433
1434         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1435         reg_val &= 0x00ffffff;
1436         reg_val |= 0x8c000000;
1437         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1438
1439         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1440         reg_val &= 0xffffff00;
1441         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1442
1443         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1444         reg_val &= 0x00ffffff;
1445         reg_val |= 0xb0000000;
1446         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1447 }
1448
1449 static void _vlv_enable_pll(struct intel_crtc *crtc,
1450                             const struct intel_crtc_state *pipe_config)
1451 {
1452         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1453         enum pipe pipe = crtc->pipe;
1454
1455         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1456         intel_de_posting_read(dev_priv, DPLL(pipe));
1457         udelay(150);
1458
1459         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1460                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1461 }
1462
1463 void vlv_enable_pll(struct intel_crtc *crtc,
1464                     const struct intel_crtc_state *pipe_config)
1465 {
1466         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1467         enum pipe pipe = crtc->pipe;
1468
1469         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470
1471         /* PLL is protected by panel, make sure we can write it */
1472         assert_panel_unlocked(dev_priv, pipe);
1473
1474         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1475                 _vlv_enable_pll(crtc, pipe_config);
1476
1477         intel_de_write(dev_priv, DPLL_MD(pipe),
1478                        pipe_config->dpll_hw_state.dpll_md);
1479         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1480 }
1481
1482
1483 static void _chv_enable_pll(struct intel_crtc *crtc,
1484                             const struct intel_crtc_state *pipe_config)
1485 {
1486         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1487         enum pipe pipe = crtc->pipe;
1488         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1489         u32 tmp;
1490
1491         vlv_dpio_get(dev_priv);
1492
1493         /* Enable back the 10bit clock to display controller */
1494         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1495         tmp |= DPIO_DCLKP_EN;
1496         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1497
1498         vlv_dpio_put(dev_priv);
1499
1500         /*
1501          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1502          */
1503         udelay(1);
1504
1505         /* Enable PLL */
1506         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1507
1508         /* Check PLL is locked */
1509         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1510                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1511 }
1512
1513 void chv_enable_pll(struct intel_crtc *crtc,
1514                     const struct intel_crtc_state *pipe_config)
1515 {
1516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517         enum pipe pipe = crtc->pipe;
1518
1519         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1520
1521         /* PLL is protected by panel, make sure we can write it */
1522         assert_panel_unlocked(dev_priv, pipe);
1523
1524         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1525                 _chv_enable_pll(crtc, pipe_config);
1526
1527         if (pipe != PIPE_A) {
1528                 /*
1529                  * WaPixelRepeatModeFixForC0:chv
1530                  *
1531                  * DPLLCMD is AWOL. Use chicken bits to propagate
1532                  * the value from DPLLBMD to either pipe B or C.
1533                  */
1534                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1535                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1536                                pipe_config->dpll_hw_state.dpll_md);
1537                 intel_de_write(dev_priv, CBR4_VLV, 0);
1538                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1539
1540                 /*
1541                  * DPLLB VGA mode also seems to cause problems.
1542                  * We should always have it disabled.
1543                  */
1544                 drm_WARN_ON(&dev_priv->drm,
1545                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1546                              DPLL_VGA_MODE_DIS) == 0);
1547         } else {
1548                 intel_de_write(dev_priv, DPLL_MD(pipe),
1549                                pipe_config->dpll_hw_state.dpll_md);
1550                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1551         }
1552 }
1553
1554 void vlv_prepare_pll(struct intel_crtc *crtc,
1555                      const struct intel_crtc_state *pipe_config)
1556 {
1557         struct drm_device *dev = crtc->base.dev;
1558         struct drm_i915_private *dev_priv = to_i915(dev);
1559         enum pipe pipe = crtc->pipe;
1560         u32 mdiv;
1561         u32 bestn, bestm1, bestm2, bestp1, bestp2;
1562         u32 coreclk, reg_val;
1563
1564         /* Enable Refclk */
1565         intel_de_write(dev_priv, DPLL(pipe),
1566                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
1567
1568         /* No need to actually set up the DPLL with DSI */
1569         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
1570                 return;
1571
1572         vlv_dpio_get(dev_priv);
1573
1574         bestn = pipe_config->dpll.n;
1575         bestm1 = pipe_config->dpll.m1;
1576         bestm2 = pipe_config->dpll.m2;
1577         bestp1 = pipe_config->dpll.p1;
1578         bestp2 = pipe_config->dpll.p2;
1579
1580         /* See eDP HDMI DPIO driver vbios notes doc */
1581
1582         /* PLL B needs special handling */
1583         if (pipe == PIPE_B)
1584                 vlv_pllb_recal_opamp(dev_priv, pipe);
1585
1586         /* Set up Tx target for periodic Rcomp update */
1587         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
1588
1589         /* Disable target IRef on PLL */
1590         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
1591         reg_val &= 0x00ffffff;
1592         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
1593
1594         /* Disable fast lock */
1595         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
1596
1597         /* Set idtafcrecal before PLL is enabled */
1598         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1599         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
1600         mdiv |= ((bestn << DPIO_N_SHIFT));
1601         mdiv |= (1 << DPIO_K_SHIFT);
1602
1603         /*
1604          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
1605          * but we don't support that).
1606          * Note: don't use the DAC post divider as it seems unstable.
1607          */
1608         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
1609         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1610
1611         mdiv |= DPIO_ENABLE_CALIBRATION;
1612         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1613
1614         /* Set HBR and RBR LPF coefficients */
1615         if (pipe_config->port_clock == 162000 ||
1616             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
1617             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1618                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1619                                  0x009f0003);
1620         else
1621                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1622                                  0x00d0000f);
1623
1624         if (intel_crtc_has_dp_encoder(pipe_config)) {
1625                 /* Use SSC source */
1626                 if (pipe == PIPE_A)
1627                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1628                                          0x0df40000);
1629                 else
1630                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1631                                          0x0df70000);
1632         } else { /* HDMI or VGA */
1633                 /* Use bend source */
1634                 if (pipe == PIPE_A)
1635                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1636                                          0x0df70000);
1637                 else
1638                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1639                                          0x0df40000);
1640         }
1641
1642         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
1643         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
1644         if (intel_crtc_has_dp_encoder(pipe_config))
1645                 coreclk |= 0x01000000;
1646         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
1647
1648         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
1649
1650         vlv_dpio_put(dev_priv);
1651 }
1652
1653 void chv_prepare_pll(struct intel_crtc *crtc,
1654                      const struct intel_crtc_state *pipe_config)
1655 {
1656         struct drm_device *dev = crtc->base.dev;
1657         struct drm_i915_private *dev_priv = to_i915(dev);
1658         enum pipe pipe = crtc->pipe;
1659         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660         u32 loopfilter, tribuf_calcntr;
1661         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
1662         u32 dpio_val;
1663         int vco;
1664
1665         /* Enable Refclk and SSC */
1666         intel_de_write(dev_priv, DPLL(pipe),
1667                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
1668
1669         /* No need to actually set up the DPLL with DSI */
1670         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
1671                 return;
1672
1673         bestn = pipe_config->dpll.n;
1674         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
1675         bestm1 = pipe_config->dpll.m1;
1676         bestm2 = pipe_config->dpll.m2 >> 22;
1677         bestp1 = pipe_config->dpll.p1;
1678         bestp2 = pipe_config->dpll.p2;
1679         vco = pipe_config->dpll.vco;
1680         dpio_val = 0;
1681         loopfilter = 0;
1682
1683         vlv_dpio_get(dev_priv);
1684
1685         /* p1 and p2 divider */
1686         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
1687                         5 << DPIO_CHV_S1_DIV_SHIFT |
1688                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
1689                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
1690                         1 << DPIO_CHV_K_DIV_SHIFT);
1691
1692         /* Feedback post-divider - m2 */
1693         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
1694
1695         /* Feedback refclk divider - n and m1 */
1696         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
1697                         DPIO_CHV_M1_DIV_BY_2 |
1698                         1 << DPIO_CHV_N_DIV_SHIFT);
1699
1700         /* M2 fraction division */
1701         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
1702
1703         /* M2 fraction division enable */
1704         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
1705         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
1706         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
1707         if (bestm2_frac)
1708                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
1709         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
1710
1711         /* Program digital lock detect threshold */
1712         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
1713         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
1714                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
1715         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
1716         if (!bestm2_frac)
1717                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
1718         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
1719
1720         /* Loop filter */
1721         if (vco == 5400000) {
1722                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
1723                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
1724                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
1725                 tribuf_calcntr = 0x9;
1726         } else if (vco <= 6200000) {
1727                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
1728                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
1729                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1730                 tribuf_calcntr = 0x9;
1731         } else if (vco <= 6480000) {
1732                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1733                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1734                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1735                 tribuf_calcntr = 0x8;
1736         } else {
1737                 /* Not supported. Apply the same limits as in the max case */
1738                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1739                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1740                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1741                 tribuf_calcntr = 0;
1742         }
1743         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
1744
1745         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
1746         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
1747         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
1748         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
1749
1750         /* AFC Recal */
1751         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
1752                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
1753                         DPIO_AFC_RECAL);
1754
1755         vlv_dpio_put(dev_priv);
1756 }
1757
1758 /**
1759  * vlv_force_pll_on - forcibly enable just the PLL
1760  * @dev_priv: i915 private structure
1761  * @pipe: pipe PLL to enable
1762  * @dpll: PLL configuration
1763  *
1764  * Enable the PLL for @pipe using the supplied @dpll config. To be used
1765  * in cases where we need the PLL enabled even when @pipe is not going to
1766  * be enabled.
1767  */
1768 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1769                      const struct dpll *dpll)
1770 {
1771         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1772         struct intel_crtc_state *pipe_config;
1773
1774         pipe_config = intel_crtc_state_alloc(crtc);
1775         if (!pipe_config)
1776                 return -ENOMEM;
1777
1778         pipe_config->cpu_transcoder = (enum transcoder)pipe;
1779         pipe_config->pixel_multiplier = 1;
1780         pipe_config->dpll = *dpll;
1781
1782         if (IS_CHERRYVIEW(dev_priv)) {
1783                 chv_compute_dpll(crtc, pipe_config);
1784                 chv_prepare_pll(crtc, pipe_config);
1785                 chv_enable_pll(crtc, pipe_config);
1786         } else {
1787                 vlv_compute_dpll(crtc, pipe_config);
1788                 vlv_prepare_pll(crtc, pipe_config);
1789                 vlv_enable_pll(crtc, pipe_config);
1790         }
1791
1792         kfree(pipe_config);
1793
1794         return 0;
1795 }
1796
1797 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799         u32 val;
1800
1801         /* Make sure the pipe isn't still relying on us */
1802         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1803
1804         val = DPLL_INTEGRATED_REF_CLK_VLV |
1805                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1806         if (pipe != PIPE_A)
1807                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1808
1809         intel_de_write(dev_priv, DPLL(pipe), val);
1810         intel_de_posting_read(dev_priv, DPLL(pipe));
1811 }
1812
1813 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1814 {
1815         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1816         u32 val;
1817
1818         /* Make sure the pipe isn't still relying on us */
1819         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1820
1821         val = DPLL_SSC_REF_CLK_CHV |
1822                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1823         if (pipe != PIPE_A)
1824                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1825
1826         intel_de_write(dev_priv, DPLL(pipe), val);
1827         intel_de_posting_read(dev_priv, DPLL(pipe));
1828
1829         vlv_dpio_get(dev_priv);
1830
1831         /* Disable 10bit clock to display controller */
1832         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833         val &= ~DPIO_DCLKP_EN;
1834         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836         vlv_dpio_put(dev_priv);
1837 }
1838
1839 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1840 {
1841         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1843         enum pipe pipe = crtc->pipe;
1844
1845         /* Don't disable pipe or pipe PLLs if needed */
1846         if (IS_I830(dev_priv))
1847                 return;
1848
1849         /* Make sure the pipe isn't still relying on us */
1850         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1851
1852         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1853         intel_de_posting_read(dev_priv, DPLL(pipe));
1854 }
1855
1856
1857 /**
1858  * vlv_force_pll_off - forcibly disable just the PLL
1859  * @dev_priv: i915 private structure
1860  * @pipe: pipe PLL to disable
1861  *
1862  * Disable the PLL for @pipe. To be used in cases where we need
1863  * the PLL enabled even when @pipe is not going to be enabled.
1864  */
1865 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
1866 {
1867         if (IS_CHERRYVIEW(dev_priv))
1868                 chv_disable_pll(dev_priv, pipe);
1869         else
1870                 vlv_disable_pll(dev_priv, pipe);
1871 }