2 * Copyright © 2008 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_probe_helper.h>
33 #include "intel_atomic.h"
34 #include "intel_audio.h"
35 #include "intel_connector.h"
36 #include "intel_crtc.h"
37 #include "intel_ddi.h"
39 #include "intel_display_types.h"
41 #include "intel_dp_hdcp.h"
42 #include "intel_dp_mst.h"
43 #include "intel_dpio_phy.h"
44 #include "intel_hdcp.h"
45 #include "intel_hotplug.h"
46 #include "skl_scaler.h"
48 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
49 struct intel_crtc_state *crtc_state,
52 struct link_config_limits *limits,
53 struct drm_connector_state *conn_state,
57 struct drm_atomic_state *state = crtc_state->uapi.state;
58 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
59 struct intel_dp *intel_dp = &intel_mst->primary->dp;
60 struct drm_dp_mst_topology_state *mst_state;
61 struct intel_connector *connector =
62 to_intel_connector(conn_state->connector);
63 struct drm_i915_private *i915 = to_i915(connector->base.dev);
64 const struct drm_display_mode *adjusted_mode =
65 &crtc_state->hw.adjusted_mode;
66 int bpp, slots = -EINVAL;
69 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
70 if (IS_ERR(mst_state))
71 return PTR_ERR(mst_state);
73 crtc_state->lane_count = limits->max_lane_count;
74 crtc_state->port_clock = limits->max_rate;
76 // TODO: Handle pbn_div changes by adding a new MST helper
77 if (!mst_state->pbn_div) {
78 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
79 crtc_state->port_clock,
80 crtc_state->lane_count);
83 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
84 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
88 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
90 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
93 if (slots == -EDEADLK)
97 ret = drm_dp_mst_atomic_check(state);
99 * If we got slots >= 0 and we can fit those based on check
100 * then we can exit the loop. Otherwise keep trying.
107 /* Despite slots are non-zero, we still failed the atomic check */
108 if (ret && slots >= 0)
112 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
116 crtc_state->pipe_bpp = bpp;
118 crtc_state->dsc.compressed_bpp = bpp;
119 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
125 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
126 struct intel_crtc_state *crtc_state,
127 struct drm_connector_state *conn_state,
128 struct link_config_limits *limits)
130 const struct drm_display_mode *adjusted_mode =
131 &crtc_state->hw.adjusted_mode;
134 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
135 limits->min_bpp, limits,
136 conn_state, 2 * 3, false);
141 intel_link_compute_m_n(crtc_state->pipe_bpp,
142 crtc_state->lane_count,
143 adjusted_mode->crtc_clock,
144 crtc_state->port_clock,
146 crtc_state->fec_enable);
147 crtc_state->dp_m_n.tu = slots;
152 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
153 struct intel_crtc_state *crtc_state,
154 struct drm_connector_state *conn_state,
155 struct link_config_limits *limits)
157 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
158 struct intel_dp *intel_dp = &intel_mst->primary->dp;
159 struct intel_connector *connector =
160 to_intel_connector(conn_state->connector);
161 struct drm_i915_private *i915 = to_i915(connector->base.dev);
162 const struct drm_display_mode *adjusted_mode =
163 &crtc_state->hw.adjusted_mode;
167 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
169 bool need_timeslot_recalc = false;
170 u32 last_compressed_bpp;
172 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
173 if (DISPLAY_VER(i915) >= 12)
174 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
176 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
178 max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
179 min_bpp = limits->min_bpp;
181 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
184 drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
187 sink_max_bpp = dsc_bpc[0] * 3;
188 sink_min_bpp = sink_max_bpp;
190 for (i = 1; i < num_bpc; i++) {
191 if (sink_min_bpp > dsc_bpc[i] * 3)
192 sink_min_bpp = dsc_bpc[i] * 3;
193 if (sink_max_bpp < dsc_bpc[i] * 3)
194 sink_max_bpp = dsc_bpc[i] * 3;
197 drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
198 sink_min_bpp, sink_max_bpp);
200 if (min_bpp < sink_min_bpp)
201 min_bpp = sink_min_bpp;
203 if (max_bpp > sink_max_bpp)
204 max_bpp = sink_max_bpp;
206 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
208 conn_state, 2 * 3, true);
213 last_compressed_bpp = crtc_state->dsc.compressed_bpp;
215 crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
217 crtc_state->pipe_bpp);
219 if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
220 need_timeslot_recalc = true;
223 * Apparently some MST hubs dislike if vcpi slots are not matching precisely
224 * the actual compressed bpp we use.
226 if (need_timeslot_recalc) {
227 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
228 crtc_state->dsc.compressed_bpp,
229 crtc_state->dsc.compressed_bpp,
230 limits, conn_state, 2 * 3, true);
235 intel_link_compute_m_n(crtc_state->pipe_bpp,
236 crtc_state->lane_count,
237 adjusted_mode->crtc_clock,
238 crtc_state->port_clock,
240 crtc_state->fec_enable);
241 crtc_state->dp_m_n.tu = slots;
245 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
246 struct intel_crtc_state *crtc_state,
247 struct drm_connector_state *conn_state)
249 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
250 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
251 struct intel_dp *intel_dp = &intel_mst->primary->dp;
252 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
253 struct drm_dp_mst_topology_state *topology_state;
254 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
255 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
257 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
258 if (IS_ERR(topology_state)) {
259 drm_dbg_kms(&i915->drm, "slot update failed\n");
260 return PTR_ERR(topology_state);
263 drm_dp_mst_update_slots(topology_state, link_coding_cap);
268 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
269 struct intel_crtc_state *pipe_config,
270 struct drm_connector_state *conn_state)
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
274 struct intel_dp *intel_dp = &intel_mst->primary->dp;
275 struct intel_connector *connector =
276 to_intel_connector(conn_state->connector);
277 struct intel_digital_connector_state *intel_conn_state =
278 to_intel_digital_connector_state(conn_state);
279 const struct drm_display_mode *adjusted_mode =
280 &pipe_config->hw.adjusted_mode;
281 struct link_config_limits limits;
284 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
287 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
288 pipe_config->has_pch_encoder = false;
290 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
291 pipe_config->has_audio = connector->port->has_audio;
293 pipe_config->has_audio =
294 intel_conn_state->force_audio == HDMI_AUDIO_ON;
297 * for MST we always configure max link bw - the spec doesn't
298 * seem to suggest we should do otherwise.
301 limits.max_rate = intel_dp_max_link_rate(intel_dp);
303 limits.min_lane_count =
304 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
306 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
308 * FIXME: If all the streams can't fit into the link with
309 * their current pipe_bpp we should reduce pipe_bpp across
310 * the board until things start to fit. Until then we
311 * limit to <= 8bpc since that's what was hardcoded for all
312 * MST streams previously. This hack should be removed once
313 * we have the proper retry logic in place.
315 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
317 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
319 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
320 conn_state, &limits);
325 /* enable compression if the mode doesn't fit available BW */
326 drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
327 if (ret || intel_dp->force_dsc_en) {
329 * Try to get at least some timeslots and then see, if
330 * we can fit there with DSC.
332 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
334 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
335 conn_state, &limits);
339 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
341 pipe_config->dp_m_n.tu, false);
347 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
351 pipe_config->limited_color_range =
352 intel_dp_limited_color_range(pipe_config, conn_state);
354 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
355 pipe_config->lane_lat_optim_mask =
356 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
358 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
364 * Iterate over all connectors and return a mask of
365 * all CPU transcoders streaming over the same DP link.
368 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
369 struct intel_dp *mst_port)
371 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
372 const struct intel_digital_connector_state *conn_state;
373 struct intel_connector *connector;
377 if (DISPLAY_VER(dev_priv) < 12)
380 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
381 const struct intel_crtc_state *crtc_state;
382 struct intel_crtc *crtc;
384 if (connector->mst_port != mst_port || !conn_state->base.crtc)
387 crtc = to_intel_crtc(conn_state->base.crtc);
388 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
390 if (!crtc_state->hw.active)
393 transcoders |= BIT(crtc_state->cpu_transcoder);
399 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
400 struct intel_crtc_state *crtc_state,
401 struct drm_connector_state *conn_state)
403 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
404 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
405 struct intel_dp *intel_dp = &intel_mst->primary->dp;
407 /* lowest numbered transcoder will be designated master */
408 crtc_state->mst_master_transcoder =
409 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
415 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
416 * that shares the same MST stream as mode changed,
417 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
418 * a fastset when possible.
421 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
422 struct intel_atomic_state *state)
424 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
425 struct drm_connector_list_iter connector_list_iter;
426 struct intel_connector *connector_iter;
429 if (DISPLAY_VER(dev_priv) < 12)
432 if (!intel_connector_needs_modeset(state, &connector->base))
435 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
436 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
437 struct intel_digital_connector_state *conn_iter_state;
438 struct intel_crtc_state *crtc_state;
439 struct intel_crtc *crtc;
441 if (connector_iter->mst_port != connector->mst_port ||
442 connector_iter == connector)
445 conn_iter_state = intel_atomic_get_digital_connector_state(state,
447 if (IS_ERR(conn_iter_state)) {
448 ret = PTR_ERR(conn_iter_state);
452 if (!conn_iter_state->base.crtc)
455 crtc = to_intel_crtc(conn_iter_state->base.crtc);
456 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
457 if (IS_ERR(crtc_state)) {
458 ret = PTR_ERR(crtc_state);
462 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
465 crtc_state->uapi.mode_changed = true;
467 drm_connector_list_iter_end(&connector_list_iter);
473 intel_dp_mst_atomic_check(struct drm_connector *connector,
474 struct drm_atomic_state *_state)
476 struct intel_atomic_state *state = to_intel_atomic_state(_state);
477 struct intel_connector *intel_connector =
478 to_intel_connector(connector);
481 ret = intel_digital_connector_atomic_check(connector, &state->base);
485 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
489 return drm_dp_atomic_release_time_slots(&state->base,
490 &intel_connector->mst_port->mst_mgr,
491 intel_connector->port);
494 static void clear_act_sent(struct intel_encoder *encoder,
495 const struct intel_crtc_state *crtc_state)
497 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
499 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
500 DP_TP_STATUS_ACT_SENT);
503 static void wait_for_act_sent(struct intel_encoder *encoder,
504 const struct intel_crtc_state *crtc_state)
506 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
507 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
508 struct intel_dp *intel_dp = &intel_mst->primary->dp;
510 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
511 DP_TP_STATUS_ACT_SENT, 1))
512 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
514 drm_dp_check_act_status(&intel_dp->mst_mgr);
517 static void intel_mst_disable_dp(struct intel_atomic_state *state,
518 struct intel_encoder *encoder,
519 const struct intel_crtc_state *old_crtc_state,
520 const struct drm_connector_state *old_conn_state)
522 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
523 struct intel_digital_port *dig_port = intel_mst->primary;
524 struct intel_dp *intel_dp = &dig_port->dp;
525 struct intel_connector *connector =
526 to_intel_connector(old_conn_state->connector);
527 struct drm_dp_mst_topology_state *old_mst_state =
528 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
529 struct drm_dp_mst_topology_state *new_mst_state =
530 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
531 const struct drm_dp_mst_atomic_payload *old_payload =
532 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
533 struct drm_dp_mst_atomic_payload *new_payload =
534 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
535 struct drm_i915_private *i915 = to_i915(connector->base.dev);
537 drm_dbg_kms(&i915->drm, "active links %d\n",
538 intel_dp->active_mst_links);
540 intel_hdcp_disable(intel_mst->connector);
542 drm_dp_remove_payload(&intel_dp->mst_mgr, new_mst_state,
543 old_payload, new_payload);
545 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
548 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
549 struct intel_encoder *encoder,
550 const struct intel_crtc_state *old_crtc_state,
551 const struct drm_connector_state *old_conn_state)
553 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
554 struct intel_digital_port *dig_port = intel_mst->primary;
555 struct intel_dp *intel_dp = &dig_port->dp;
556 struct intel_connector *connector =
557 to_intel_connector(old_conn_state->connector);
558 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
559 bool last_mst_stream;
561 intel_dp->active_mst_links--;
562 last_mst_stream = intel_dp->active_mst_links == 0;
563 drm_WARN_ON(&dev_priv->drm,
564 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
565 !intel_dp_mst_is_master_trans(old_crtc_state));
567 intel_crtc_vblank_off(old_crtc_state);
569 intel_disable_transcoder(old_crtc_state);
571 clear_act_sent(encoder, old_crtc_state);
573 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
574 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
576 wait_for_act_sent(encoder, old_crtc_state);
578 intel_ddi_disable_transcoder_func(old_crtc_state);
580 if (DISPLAY_VER(dev_priv) >= 9)
581 skl_scaler_disable(old_crtc_state);
583 ilk_pfit_disable(old_crtc_state);
586 * Power down mst path before disabling the port, otherwise we end
587 * up getting interrupts from the sink upon detecting link loss.
589 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
593 * BSpec 4287: disable DIP after the transcoder is disabled and before
594 * the transcoder clock select is set to none.
597 intel_dp_set_infoframes(&dig_port->base, false,
598 old_crtc_state, NULL);
600 * From TGL spec: "If multi-stream slave transcoder: Configure
601 * Transcoder Clock Select to direct no clock to the transcoder"
603 * From older GENs spec: "Configure Transcoder Clock Select to direct
604 * no clock to the transcoder"
606 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
607 intel_ddi_disable_pipe_clock(old_crtc_state);
610 intel_mst->connector = NULL;
612 dig_port->base.post_disable(state, &dig_port->base,
613 old_crtc_state, NULL);
615 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
616 intel_dp->active_mst_links);
619 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
620 struct intel_encoder *encoder,
621 const struct intel_crtc_state *pipe_config,
622 const struct drm_connector_state *conn_state)
624 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
625 struct intel_digital_port *dig_port = intel_mst->primary;
626 struct intel_dp *intel_dp = &dig_port->dp;
628 if (intel_dp->active_mst_links == 0)
629 dig_port->base.pre_pll_enable(state, &dig_port->base,
633 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
634 struct intel_encoder *encoder,
635 const struct intel_crtc_state *pipe_config,
636 const struct drm_connector_state *conn_state)
638 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
639 struct intel_digital_port *dig_port = intel_mst->primary;
640 struct intel_dp *intel_dp = &dig_port->dp;
641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
642 struct intel_connector *connector =
643 to_intel_connector(conn_state->connector);
644 struct drm_dp_mst_topology_state *mst_state =
645 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
647 bool first_mst_stream;
649 /* MST encoders are bound to a crtc, not to a connector,
650 * force the mapping here for get_hw_state.
652 connector->encoder = encoder;
653 intel_mst->connector = connector;
654 first_mst_stream = intel_dp->active_mst_links == 0;
655 drm_WARN_ON(&dev_priv->drm,
656 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
657 !intel_dp_mst_is_master_trans(pipe_config));
659 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
660 intel_dp->active_mst_links);
662 if (first_mst_stream)
663 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
665 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
667 if (first_mst_stream)
668 dig_port->base.pre_enable(state, &dig_port->base,
671 intel_dp->active_mst_links++;
673 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
674 drm_atomic_get_mst_payload_state(mst_state, connector->port));
676 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
677 connector->base.name, ret);
680 * Before Gen 12 this is not done as part of
681 * dig_port->base.pre_enable() and should be done here. For
682 * Gen 12+ the step in which this should be done is different for the
683 * first MST stream, so it's done on the DDI for the first stream and
684 * here for the following ones.
686 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
687 intel_ddi_enable_pipe_clock(encoder, pipe_config);
689 intel_ddi_set_dp_msa(pipe_config, conn_state);
692 static void intel_mst_enable_dp(struct intel_atomic_state *state,
693 struct intel_encoder *encoder,
694 const struct intel_crtc_state *pipe_config,
695 const struct drm_connector_state *conn_state)
697 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
698 struct intel_digital_port *dig_port = intel_mst->primary;
699 struct intel_dp *intel_dp = &dig_port->dp;
700 struct intel_connector *connector = to_intel_connector(conn_state->connector);
701 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
702 struct drm_dp_mst_topology_state *mst_state =
703 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
704 enum transcoder trans = pipe_config->cpu_transcoder;
706 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
708 clear_act_sent(encoder, pipe_config);
710 if (intel_dp_is_uhbr(pipe_config)) {
711 const struct drm_display_mode *adjusted_mode =
712 &pipe_config->hw.adjusted_mode;
713 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
715 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
716 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
717 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
718 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
721 intel_ddi_enable_transcoder_func(encoder, pipe_config);
723 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
724 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
726 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
727 intel_dp->active_mst_links);
729 wait_for_act_sent(encoder, pipe_config);
731 drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
732 drm_atomic_get_mst_payload_state(mst_state, connector->port));
734 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
735 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
736 FECSTALL_DIS_DPTSTREAM_DPTTG);
737 else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
738 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
739 FECSTALL_DIS_DPTSTREAM_DPTTG);
741 intel_enable_transcoder(pipe_config);
743 intel_crtc_vblank_on(pipe_config);
745 intel_audio_codec_enable(encoder, pipe_config, conn_state);
747 /* Enable hdcp if it's desired */
748 if (conn_state->content_protection ==
749 DRM_MODE_CONTENT_PROTECTION_DESIRED)
750 intel_hdcp_enable(to_intel_connector(conn_state->connector),
752 (u8)conn_state->hdcp_content_type);
755 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
758 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
759 *pipe = intel_mst->pipe;
760 if (intel_mst->connector)
765 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
766 struct intel_crtc_state *pipe_config)
768 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
769 struct intel_digital_port *dig_port = intel_mst->primary;
771 dig_port->base.get_config(&dig_port->base, pipe_config);
774 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
775 struct intel_crtc_state *crtc_state)
777 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
778 struct intel_digital_port *dig_port = intel_mst->primary;
780 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
783 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
785 struct intel_connector *intel_connector = to_intel_connector(connector);
786 struct intel_dp *intel_dp = intel_connector->mst_port;
790 if (drm_connector_is_unregistered(connector))
791 return intel_connector_update_modes(connector, NULL);
793 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
794 ret = intel_connector_update_modes(connector, edid);
801 intel_dp_mst_connector_late_register(struct drm_connector *connector)
803 struct intel_connector *intel_connector = to_intel_connector(connector);
806 ret = drm_dp_mst_connector_late_register(connector,
807 intel_connector->port);
811 ret = intel_connector_register(connector);
813 drm_dp_mst_connector_early_unregister(connector,
814 intel_connector->port);
820 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
822 struct intel_connector *intel_connector = to_intel_connector(connector);
824 intel_connector_unregister(connector);
825 drm_dp_mst_connector_early_unregister(connector,
826 intel_connector->port);
829 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
830 .fill_modes = drm_helper_probe_single_connector_modes,
831 .atomic_get_property = intel_digital_connector_atomic_get_property,
832 .atomic_set_property = intel_digital_connector_atomic_set_property,
833 .late_register = intel_dp_mst_connector_late_register,
834 .early_unregister = intel_dp_mst_connector_early_unregister,
835 .destroy = intel_connector_destroy,
836 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
837 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
840 static int intel_dp_mst_get_modes(struct drm_connector *connector)
842 return intel_dp_mst_get_ddc_modes(connector);
846 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
847 struct drm_display_mode *mode,
848 struct drm_modeset_acquire_ctx *ctx,
849 enum drm_mode_status *status)
851 struct drm_i915_private *dev_priv = to_i915(connector->dev);
852 struct intel_connector *intel_connector = to_intel_connector(connector);
853 struct intel_dp *intel_dp = intel_connector->mst_port;
854 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
855 struct drm_dp_mst_port *port = intel_connector->port;
856 const int min_bpp = 18;
857 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
858 int max_rate, mode_rate, max_lanes, max_link_clock;
860 bool dsc = false, bigjoiner = false;
861 u16 dsc_max_output_bpp = 0;
862 u8 dsc_slice_count = 0;
863 int target_clock = mode->clock;
865 if (drm_connector_is_unregistered(connector)) {
866 *status = MODE_ERROR;
870 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
871 *status = MODE_NO_DBLESCAN;
875 max_link_clock = intel_dp_max_link_rate(intel_dp);
876 max_lanes = intel_dp_max_lane_count(intel_dp);
878 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
879 mode_rate = intel_dp_link_required(mode->clock, min_bpp);
881 ret = drm_modeset_lock(&mgr->base.lock, ctx);
885 if (mode_rate > max_rate || mode->clock > max_dotclk ||
886 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
887 *status = MODE_CLOCK_HIGH;
891 if (mode->clock < 10000) {
892 *status = MODE_CLOCK_LOW;
896 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
897 *status = MODE_H_ILLEGAL;
901 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
906 if (DISPLAY_VER(dev_priv) >= 10 &&
907 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
909 * TBD pass the connector BPC,
910 * for now U8_MAX so that max BPC on that platform would be picked
912 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
914 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
916 intel_dp_dsc_get_output_bpp(dev_priv,
924 intel_dp_dsc_get_slice_count(intel_dp,
930 dsc = dsc_max_output_bpp && dsc_slice_count;
934 * Big joiner configuration needs DSC for TGL which is not true for
935 * XE_LPD where uncompressed joiner is supported.
937 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
938 return MODE_CLOCK_HIGH;
940 if (mode_rate > max_rate && !dsc)
941 return MODE_CLOCK_HIGH;
943 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
947 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
948 struct drm_atomic_state *state)
950 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
952 struct intel_connector *intel_connector = to_intel_connector(connector);
953 struct intel_dp *intel_dp = intel_connector->mst_port;
954 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
956 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
960 intel_dp_mst_detect(struct drm_connector *connector,
961 struct drm_modeset_acquire_ctx *ctx, bool force)
963 struct drm_i915_private *i915 = to_i915(connector->dev);
964 struct intel_connector *intel_connector = to_intel_connector(connector);
965 struct intel_dp *intel_dp = intel_connector->mst_port;
967 if (!INTEL_DISPLAY_ENABLED(i915))
968 return connector_status_disconnected;
970 if (drm_connector_is_unregistered(connector))
971 return connector_status_disconnected;
973 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
974 intel_connector->port);
977 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
978 .get_modes = intel_dp_mst_get_modes,
979 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
980 .atomic_best_encoder = intel_mst_atomic_best_encoder,
981 .atomic_check = intel_dp_mst_atomic_check,
982 .detect_ctx = intel_dp_mst_detect,
985 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
987 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
989 drm_encoder_cleanup(encoder);
993 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
994 .destroy = intel_dp_mst_encoder_destroy,
997 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
999 if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1001 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1008 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1009 struct drm_connector *connector,
1010 const char *pathprop)
1012 struct drm_i915_private *i915 = to_i915(connector->dev);
1014 drm_object_attach_property(&connector->base,
1015 i915->drm.mode_config.path_property, 0);
1016 drm_object_attach_property(&connector->base,
1017 i915->drm.mode_config.tile_property, 0);
1019 intel_attach_force_audio_property(connector);
1020 intel_attach_broadcast_rgb_property(connector);
1023 * Reuse the prop from the SST connector because we're
1024 * not allowed to create new props after device registration.
1026 connector->max_bpc_property =
1027 intel_dp->attached_connector->base.max_bpc_property;
1028 if (connector->max_bpc_property)
1029 drm_connector_attach_max_bpc_property(connector, 6, 12);
1031 return drm_connector_set_path_property(connector, pathprop);
1034 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1035 struct drm_dp_mst_port *port,
1036 const char *pathprop)
1038 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1039 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1040 struct drm_device *dev = dig_port->base.base.dev;
1041 struct drm_i915_private *dev_priv = to_i915(dev);
1042 struct intel_connector *intel_connector;
1043 struct drm_connector *connector;
1047 intel_connector = intel_connector_alloc();
1048 if (!intel_connector)
1051 intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1052 intel_connector->mst_port = intel_dp;
1053 intel_connector->port = port;
1054 drm_dp_mst_get_port_malloc(port);
1056 connector = &intel_connector->base;
1057 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1058 DRM_MODE_CONNECTOR_DisplayPort);
1060 drm_dp_mst_put_port_malloc(port);
1061 intel_connector_free(intel_connector);
1065 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1067 for_each_pipe(dev_priv, pipe) {
1068 struct drm_encoder *enc =
1069 &intel_dp->mst_encoders[pipe]->base.base;
1071 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1076 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1080 ret = intel_dp_hdcp_init(dig_port, intel_connector);
1082 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1083 connector->name, connector->base.id);
1088 drm_connector_cleanup(connector);
1093 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1095 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1097 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1100 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1101 .add_connector = intel_dp_add_mst_connector,
1102 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1105 static struct intel_dp_mst_encoder *
1106 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1108 struct intel_dp_mst_encoder *intel_mst;
1109 struct intel_encoder *intel_encoder;
1110 struct drm_device *dev = dig_port->base.base.dev;
1112 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1117 intel_mst->pipe = pipe;
1118 intel_encoder = &intel_mst->base;
1119 intel_mst->primary = dig_port;
1121 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1122 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1124 intel_encoder->type = INTEL_OUTPUT_DP_MST;
1125 intel_encoder->power_domain = dig_port->base.power_domain;
1126 intel_encoder->port = dig_port->base.port;
1127 intel_encoder->cloneable = 0;
1129 * This is wrong, but broken userspace uses the intersection
1130 * of possible_crtcs of all the encoders of a given connector
1131 * to figure out which crtcs can drive said connector. What
1132 * should be used instead is the union of possible_crtcs.
1133 * To keep such userspace functioning we must misconfigure
1134 * this to make sure the intersection is not empty :(
1136 intel_encoder->pipe_mask = ~0;
1138 intel_encoder->compute_config = intel_dp_mst_compute_config;
1139 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1140 intel_encoder->disable = intel_mst_disable_dp;
1141 intel_encoder->post_disable = intel_mst_post_disable_dp;
1142 intel_encoder->update_pipe = intel_ddi_update_pipe;
1143 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1144 intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1145 intel_encoder->enable = intel_mst_enable_dp;
1146 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1147 intel_encoder->get_config = intel_dp_mst_enc_get_config;
1148 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1155 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1157 struct intel_dp *intel_dp = &dig_port->dp;
1158 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1161 for_each_pipe(dev_priv, pipe)
1162 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1167 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1169 return dig_port->dp.active_mst_links;
1173 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1175 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1176 struct intel_dp *intel_dp = &dig_port->dp;
1177 enum port port = dig_port->base.port;
1180 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1183 if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1186 if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1189 intel_dp->mst_mgr.cbs = &mst_cbs;
1191 /* create encoders */
1192 intel_dp_create_fake_mst_encoders(dig_port);
1193 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1194 &intel_dp->aux, 16, 3, conn_base_id);
1196 intel_dp->mst_mgr.cbs = NULL;
1203 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1205 return intel_dp->mst_mgr.cbs;
1209 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1211 struct intel_dp *intel_dp = &dig_port->dp;
1213 if (!intel_dp_mst_source_support(intel_dp))
1216 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1217 /* encoders will get killed by normal cleanup */
1219 intel_dp->mst_mgr.cbs = NULL;
1222 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1224 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1227 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1229 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1230 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1234 * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1235 * @state: atomic state
1236 * @connector: connector to add the state for
1237 * @crtc: the CRTC @connector is attached to
1239 * Add the MST topology state for @connector to @state.
1241 * Returns 0 on success, negative error code on failure.
1244 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1245 struct intel_connector *connector,
1246 struct intel_crtc *crtc)
1248 struct drm_dp_mst_topology_state *mst_state;
1250 if (!connector->mst_port)
1253 mst_state = drm_atomic_get_mst_topology_state(&state->base,
1254 &connector->mst_port->mst_mgr);
1255 if (IS_ERR(mst_state))
1256 return PTR_ERR(mst_state);
1258 mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1264 * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1265 * @state: atomic state
1266 * @crtc: CRTC to add the state for
1268 * Add the MST topology state for @crtc to @state.
1270 * Returns 0 on success, negative error code on failure.
1272 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1273 struct intel_crtc *crtc)
1275 struct drm_connector *_connector;
1276 struct drm_connector_state *conn_state;
1279 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1280 struct intel_connector *connector = to_intel_connector(_connector);
1283 if (conn_state->crtc != &crtc->base)
1286 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);