drivers/gpu/drm/i915/display/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_display_types.h"
  25 #include "intel_dp.h"
  26 #include "intel_dp_link_training.h"
  27
  28 static void
  29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  30 {
  31
  32         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  33                       link_status[0], link_status[1], link_status[2],
  34                       link_status[3], link_status[4], link_status[5]);
  35 }
  36
  37 static void
  38 intel_get_adjust_train(struct intel_dp *intel_dp,
  39                        const u8 link_status[DP_LINK_STATUS_SIZE])
  40 {
  41         u8 v = 0;
  42         u8 p = 0;
  43         int lane;
  44         u8 voltage_max;
  45         u8 preemph_max;
  46
  47         for (lane = 0; lane < intel_dp->lane_count; lane++) {
  48                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  49                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  50
  51                 if (this_v > v)
  52                         v = this_v;
  53                 if (this_p > p)
  54                         p = this_p;
  55         }
  56
  57         voltage_max = intel_dp_voltage_max(intel_dp);
  58         if (v >= voltage_max)
  59                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  60
  61         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  62         if (p >= preemph_max)
  63                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  64
  65         for (lane = 0; lane < 4; lane++)
  66                 intel_dp->train_set[lane] = v | p;
  67 }
  68
  69 static bool
  70 intel_dp_set_link_train(struct intel_dp *intel_dp,
  71                         u8 dp_train_pat)
  72 {
  73         u8 buf[sizeof(intel_dp->train_set) + 1];
  74         int ret, len;
  75
  76         intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  77
  78         buf[0] = dp_train_pat;
  79         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
  80             DP_TRAINING_PATTERN_DISABLE) {
  81                 /* don't write DP_TRAINING_LANEx_SET on disable */
  82                 len = 1;
  83         } else {
  84                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
  85                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
  86                 len = intel_dp->lane_count + 1;
  87         }
  88
  89         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
  90                                 buf, len);
  91
  92         return ret == len;
  93 }
  94
  95 static bool
  96 intel_dp_reset_link_train(struct intel_dp *intel_dp,
  97                         u8 dp_train_pat)
  98 {
  99         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 100         intel_dp_set_signal_levels(intel_dp);
 101         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 102 }
 103
 104 static bool
 105 intel_dp_update_link_train(struct intel_dp *intel_dp)
 106 {
 107         int ret;
 108
 109         intel_dp_set_signal_levels(intel_dp);
 110
 111         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 112                                 intel_dp->train_set, intel_dp->lane_count);
 113
 114         return ret == intel_dp->lane_count;
 115 }
 116
 117 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 118 {
 119         int lane;
 120
 121         for (lane = 0; lane < intel_dp->lane_count; lane++)
 122                 if ((intel_dp->train_set[lane] &
 123                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 124                         return false;
 125
 126         return true;
 127 }
 128
 129 /* Enable corresponding port and start training pattern 1 */
 130 static bool
 131 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 132 {
 133         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 134         u8 voltage;
 135         int voltage_tries, cr_tries, max_cr_tries;
 136         bool max_vswing_reached = false;
 137         u8 link_config[2];
 138         u8 link_bw, rate_select;
 139
 140         if (intel_dp->prepare_link_retrain)
 141                 intel_dp->prepare_link_retrain(intel_dp);
 142
 143         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 144                               &link_bw, &rate_select);
 145
 146         if (link_bw)
 147                 drm_dbg_kms(&i915->drm,
 148                             "Using LINK_BW_SET value %02x\n", link_bw);
 149         else
 150                 drm_dbg_kms(&i915->drm,
 151                             "Using LINK_RATE_SET value %02x\n", rate_select);
 152
 153         /* Write the link configuration data */
 154         link_config[0] = link_bw;
 155         link_config[1] = intel_dp->lane_count;
 156         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 157                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 158         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 159
 160         /* eDP 1.4 rate select method. */
 161         if (!link_bw)
 162                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 163                                   &rate_select, 1);
 164
 165         link_config[0] = 0;
 166         link_config[1] = DP_SET_ANSI_8B10B;
 167         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 168
 169         intel_dp->DP |= DP_PORT_EN;
 170
 171         /* clock recovery */
 172         if (!intel_dp_reset_link_train(intel_dp,
 173                                        DP_TRAINING_PATTERN_1 |
 174                                        DP_LINK_SCRAMBLING_DISABLE)) {
 175                 drm_err(&i915->drm, "failed to enable link training\n");
 176                 return false;
 177         }
 178
 179         /*
 180          * The DP 1.4 spec defines the max clock recovery retries value
 181          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 182          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 183          * x 5 identical voltage retries). Since the previous specs didn't
 184          * define a limit and created the possibility of an infinite loop
 185          * we want to prevent any sync from triggering that corner case.
 186          */
 187         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 188                 max_cr_tries = 10;
 189         else
 190                 max_cr_tries = 80;
 191
 192         voltage_tries = 1;
 193         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 194                 u8 link_status[DP_LINK_STATUS_SIZE];
 195
 196                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 197
 198                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 199                         drm_err(&i915->drm, "failed to get link status\n");
 200                         return false;
 201                 }
 202
 203                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 204                         drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 205                         return true;
 206                 }
 207
 208                 if (voltage_tries == 5) {
 209                         drm_dbg_kms(&i915->drm,
 210                                     "Same voltage tried 5 times\n");
 211                         return false;
 212                 }
 213
 214                 if (max_vswing_reached) {
 215                         drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
 216                         return false;
 217                 }
 218
 219                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 220
 221                 /* Update training set as requested by target */
 222                 intel_get_adjust_train(intel_dp, link_status);
 223                 if (!intel_dp_update_link_train(intel_dp)) {
 224                         drm_err(&i915->drm,
 225                                 "failed to update link training\n");
 226                         return false;
 227                 }
 228
 229                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 230                     voltage)
 231                         ++voltage_tries;
 232                 else
 233                         voltage_tries = 1;
 234
 235                 if (intel_dp_link_max_vswing_reached(intel_dp))
 236                         max_vswing_reached = true;
 237
 238         }
 239         drm_err(&i915->drm,
 240                 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
 241         return false;
 242 }
 243
 244 /*
 245  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 246  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 247  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 248  */
 249 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 250 {
 251         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 252
 253         /*
 254          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 255          * for all downstream devices that support HBR3. There are no known eDP
 256          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 257          * specification.
 258          */
 259         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 260         sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 261         if (source_tps4 && sink_tps4) {
 262                 return DP_TRAINING_PATTERN_4;
 263         } else if (intel_dp->link_rate == 810000) {
 264                 if (!source_tps4)
 265                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 266                                     "8.1 Gbps link rate without source HBR3/TPS4 support\n");
 267                 if (!sink_tps4)
 268                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 269                                     "8.1 Gbps link rate without sink TPS4 support\n");
 270         }
 271         /*
 272          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 273          * also mandatory for downstream devices that support HBR2. However, not
 274          * all sinks follow the spec.
 275          */
 276         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 277         sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 278         if (source_tps3 && sink_tps3) {
 279                 return  DP_TRAINING_PATTERN_3;
 280         } else if (intel_dp->link_rate >= 540000) {
 281                 if (!source_tps3)
 282                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 283                                     ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 284                 if (!sink_tps3)
 285                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 286                                     ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 287         }
 288
 289         return DP_TRAINING_PATTERN_2;
 290 }
 291
 292 static bool
 293 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 294 {
 295         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 296         int tries;
 297         u32 training_pattern;
 298         u8 link_status[DP_LINK_STATUS_SIZE];
 299         bool channel_eq = false;
 300
 301         training_pattern = intel_dp_training_pattern(intel_dp);
 302         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 303         if (training_pattern != DP_TRAINING_PATTERN_4)
 304                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 305
 306         /* channel equalization */
 307         if (!intel_dp_set_link_train(intel_dp,
 308                                      training_pattern)) {
 309                 drm_err(&i915->drm, "failed to start channel equalization\n");
 310                 return false;
 311         }
 312
 313         for (tries = 0; tries < 5; tries++) {
 314
 315                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 316                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 317                         drm_err(&i915->drm,
 318                                 "failed to get link status\n");
 319                         break;
 320                 }
 321
 322                 /* Make sure clock is still ok */
 323                 if (!drm_dp_clock_recovery_ok(link_status,
 324                                               intel_dp->lane_count)) {
 325                         intel_dp_dump_link_status(link_status);
 326                         drm_dbg_kms(&i915->drm,
 327                                     "Clock recovery check failed, cannot "
 328                                     "continue channel equalization\n");
 329                         break;
 330                 }
 331
 332                 if (drm_dp_channel_eq_ok(link_status,
 333                                          intel_dp->lane_count)) {
 334                         channel_eq = true;
 335                         drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 336                                     "successful\n");
 337                         break;
 338                 }
 339
 340                 /* Update training set as requested by target */
 341                 intel_get_adjust_train(intel_dp, link_status);
 342                 if (!intel_dp_update_link_train(intel_dp)) {
 343                         drm_err(&i915->drm,
 344                                 "failed to update link training\n");
 345                         break;
 346                 }
 347         }
 348
 349         /* Try 5 times, else fail and try at lower BW */
 350         if (tries == 5) {
 351                 intel_dp_dump_link_status(link_status);
 352                 drm_dbg_kms(&i915->drm,
 353                             "Channel equalization failed 5 times\n");
 354         }
 355
 356         intel_dp_set_idle_link_train(intel_dp);
 357
 358         return channel_eq;
 359
 360 }
 361
 362 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 363 {
 364         intel_dp->link_trained = true;
 365
 366         intel_dp_set_link_train(intel_dp,
 367                                 DP_TRAINING_PATTERN_DISABLE);
 368 }
 369
 370 void
 371 intel_dp_start_link_train(struct intel_dp *intel_dp)
 372 {
 373         struct intel_connector *intel_connector = intel_dp->attached_connector;
 374
 375         if (!intel_dp_link_training_clock_recovery(intel_dp))
 376                 goto failure_handling;
 377         if (!intel_dp_link_training_channel_equalization(intel_dp))
 378                 goto failure_handling;
 379
 380         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 381                     "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 382                     intel_connector->base.base.id,
 383                     intel_connector->base.name,
 384                     intel_dp->link_rate, intel_dp->lane_count);
 385         return;
 386
 387  failure_handling:
 388         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 389                     "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 390                     intel_connector->base.base.id,
 391                     intel_connector->base.name,
 392                     intel_dp->link_rate, intel_dp->lane_count);
 393         if (!intel_dp_get_link_train_fallback_values(intel_dp,
 394                                                      intel_dp->link_rate,
 395                                                      intel_dp->lane_count))
 396                 /* Schedule a Hotplug Uevent to userspace to start modeset */
 397                 schedule_work(&intel_connector->modeset_retry_work);
 398         return;
 399 }