drivers/gpu/drm/i915/display/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_display_types.h"
  25 #include "intel_dp.h"
  26 #include "intel_dp_link_training.h"
  27
  28 static void
  29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  30 {
  31
  32         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  33                       link_status[0], link_status[1], link_status[2],
  34                       link_status[3], link_status[4], link_status[5]);
  35 }
  36
  37 static u8 dp_voltage_max(u8 preemph)
  38 {
  39         switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
  40         case DP_TRAIN_PRE_EMPH_LEVEL_0:
  41                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
  42         case DP_TRAIN_PRE_EMPH_LEVEL_1:
  43                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
  44         case DP_TRAIN_PRE_EMPH_LEVEL_2:
  45                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
  46         case DP_TRAIN_PRE_EMPH_LEVEL_3:
  47         default:
  48                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
  49         }
  50 }
  51
  52 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
  53                                const u8 link_status[DP_LINK_STATUS_SIZE])
  54 {
  55         u8 v = 0;
  56         u8 p = 0;
  57         int lane;
  58         u8 voltage_max;
  59         u8 preemph_max;
  60
  61         for (lane = 0; lane < intel_dp->lane_count; lane++) {
  62                 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
  63                 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
  64         }
  65
  66         preemph_max = intel_dp->preemph_max(intel_dp);
  67         if (p >= preemph_max)
  68                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  69
  70         voltage_max = min(intel_dp->voltage_max(intel_dp),
  71                           dp_voltage_max(p));
  72         if (v >= voltage_max)
  73                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  74
  75         for (lane = 0; lane < 4; lane++)
  76                 intel_dp->train_set[lane] = v | p;
  77 }
  78
  79 static bool
  80 intel_dp_set_link_train(struct intel_dp *intel_dp,
  81                         u8 dp_train_pat)
  82 {
  83         u8 buf[sizeof(intel_dp->train_set) + 1];
  84         int ret, len;
  85
  86         intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  87
  88         buf[0] = dp_train_pat;
  89         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
  90             DP_TRAINING_PATTERN_DISABLE) {
  91                 /* don't write DP_TRAINING_LANEx_SET on disable */
  92                 len = 1;
  93         } else {
  94                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
  95                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
  96                 len = intel_dp->lane_count + 1;
  97         }
  98
  99         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
 100                                 buf, len);
 101
 102         return ret == len;
 103 }
 104
 105 static bool
 106 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 107                         u8 dp_train_pat)
 108 {
 109         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 110         intel_dp_set_signal_levels(intel_dp);
 111         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 112 }
 113
 114 static bool
 115 intel_dp_update_link_train(struct intel_dp *intel_dp)
 116 {
 117         int ret;
 118
 119         intel_dp_set_signal_levels(intel_dp);
 120
 121         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 122                                 intel_dp->train_set, intel_dp->lane_count);
 123
 124         return ret == intel_dp->lane_count;
 125 }
 126
 127 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 128 {
 129         int lane;
 130
 131         for (lane = 0; lane < intel_dp->lane_count; lane++)
 132                 if ((intel_dp->train_set[lane] &
 133                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 134                         return false;
 135
 136         return true;
 137 }
 138
 139 /* Enable corresponding port and start training pattern 1 */
 140 static bool
 141 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 142 {
 143         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 144         u8 voltage;
 145         int voltage_tries, cr_tries, max_cr_tries;
 146         bool max_vswing_reached = false;
 147         u8 link_config[2];
 148         u8 link_bw, rate_select;
 149
 150         if (intel_dp->prepare_link_retrain)
 151                 intel_dp->prepare_link_retrain(intel_dp);
 152
 153         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 154                               &link_bw, &rate_select);
 155
 156         if (link_bw)
 157                 drm_dbg_kms(&i915->drm,
 158                             "Using LINK_BW_SET value %02x\n", link_bw);
 159         else
 160                 drm_dbg_kms(&i915->drm,
 161                             "Using LINK_RATE_SET value %02x\n", rate_select);
 162
 163         /* Write the link configuration data */
 164         link_config[0] = link_bw;
 165         link_config[1] = intel_dp->lane_count;
 166         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 167                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 168         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 169
 170         /* eDP 1.4 rate select method. */
 171         if (!link_bw)
 172                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 173                                   &rate_select, 1);
 174
 175         link_config[0] = 0;
 176         link_config[1] = DP_SET_ANSI_8B10B;
 177         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 178
 179         intel_dp->DP |= DP_PORT_EN;
 180
 181         /* clock recovery */
 182         if (!intel_dp_reset_link_train(intel_dp,
 183                                        DP_TRAINING_PATTERN_1 |
 184                                        DP_LINK_SCRAMBLING_DISABLE)) {
 185                 drm_err(&i915->drm, "failed to enable link training\n");
 186                 return false;
 187         }
 188
 189         /*
 190          * The DP 1.4 spec defines the max clock recovery retries value
 191          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 192          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 193          * x 5 identical voltage retries). Since the previous specs didn't
 194          * define a limit and created the possibility of an infinite loop
 195          * we want to prevent any sync from triggering that corner case.
 196          */
 197         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 198                 max_cr_tries = 10;
 199         else
 200                 max_cr_tries = 80;
 201
 202         voltage_tries = 1;
 203         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 204                 u8 link_status[DP_LINK_STATUS_SIZE];
 205
 206                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 207
 208                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 209                         drm_err(&i915->drm, "failed to get link status\n");
 210                         return false;
 211                 }
 212
 213                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 214                         drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 215                         return true;
 216                 }
 217
 218                 if (voltage_tries == 5) {
 219                         drm_dbg_kms(&i915->drm,
 220                                     "Same voltage tried 5 times\n");
 221                         return false;
 222                 }
 223
 224                 if (max_vswing_reached) {
 225                         drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
 226                         return false;
 227                 }
 228
 229                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 230
 231                 /* Update training set as requested by target */
 232                 intel_dp_get_adjust_train(intel_dp, link_status);
 233                 if (!intel_dp_update_link_train(intel_dp)) {
 234                         drm_err(&i915->drm,
 235                                 "failed to update link training\n");
 236                         return false;
 237                 }
 238
 239                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 240                     voltage)
 241                         ++voltage_tries;
 242                 else
 243                         voltage_tries = 1;
 244
 245                 if (intel_dp_link_max_vswing_reached(intel_dp))
 246                         max_vswing_reached = true;
 247
 248         }
 249         drm_err(&i915->drm,
 250                 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
 251         return false;
 252 }
 253
 254 /*
 255  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 256  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 257  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 258  */
 259 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 260 {
 261         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 262
 263         /*
 264          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 265          * for all downstream devices that support HBR3. There are no known eDP
 266          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 267          * specification.
 268          */
 269         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 270         sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 271         if (source_tps4 && sink_tps4) {
 272                 return DP_TRAINING_PATTERN_4;
 273         } else if (intel_dp->link_rate == 810000) {
 274                 if (!source_tps4)
 275                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 276                                     "8.1 Gbps link rate without source HBR3/TPS4 support\n");
 277                 if (!sink_tps4)
 278                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 279                                     "8.1 Gbps link rate without sink TPS4 support\n");
 280         }
 281         /*
 282          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 283          * also mandatory for downstream devices that support HBR2. However, not
 284          * all sinks follow the spec.
 285          */
 286         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 287         sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 288         if (source_tps3 && sink_tps3) {
 289                 return  DP_TRAINING_PATTERN_3;
 290         } else if (intel_dp->link_rate >= 540000) {
 291                 if (!source_tps3)
 292                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 293                                     ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 294                 if (!sink_tps3)
 295                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 296                                     ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 297         }
 298
 299         return DP_TRAINING_PATTERN_2;
 300 }
 301
 302 static bool
 303 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 304 {
 305         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 306         int tries;
 307         u32 training_pattern;
 308         u8 link_status[DP_LINK_STATUS_SIZE];
 309         bool channel_eq = false;
 310
 311         training_pattern = intel_dp_training_pattern(intel_dp);
 312         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 313         if (training_pattern != DP_TRAINING_PATTERN_4)
 314                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 315
 316         /* channel equalization */
 317         if (!intel_dp_set_link_train(intel_dp,
 318                                      training_pattern)) {
 319                 drm_err(&i915->drm, "failed to start channel equalization\n");
 320                 return false;
 321         }
 322
 323         for (tries = 0; tries < 5; tries++) {
 324
 325                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 326                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 327                         drm_err(&i915->drm,
 328                                 "failed to get link status\n");
 329                         break;
 330                 }
 331
 332                 /* Make sure clock is still ok */
 333                 if (!drm_dp_clock_recovery_ok(link_status,
 334                                               intel_dp->lane_count)) {
 335                         intel_dp_dump_link_status(link_status);
 336                         drm_dbg_kms(&i915->drm,
 337                                     "Clock recovery check failed, cannot "
 338                                     "continue channel equalization\n");
 339                         break;
 340                 }
 341
 342                 if (drm_dp_channel_eq_ok(link_status,
 343                                          intel_dp->lane_count)) {
 344                         channel_eq = true;
 345                         drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 346                                     "successful\n");
 347                         break;
 348                 }
 349
 350                 /* Update training set as requested by target */
 351                 intel_dp_get_adjust_train(intel_dp, link_status);
 352                 if (!intel_dp_update_link_train(intel_dp)) {
 353                         drm_err(&i915->drm,
 354                                 "failed to update link training\n");
 355                         break;
 356                 }
 357         }
 358
 359         /* Try 5 times, else fail and try at lower BW */
 360         if (tries == 5) {
 361                 intel_dp_dump_link_status(link_status);
 362                 drm_dbg_kms(&i915->drm,
 363                             "Channel equalization failed 5 times\n");
 364         }
 365
 366         intel_dp_set_idle_link_train(intel_dp);
 367
 368         return channel_eq;
 369
 370 }
 371
 372 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 373 {
 374         intel_dp->link_trained = true;
 375
 376         intel_dp_set_link_train(intel_dp,
 377                                 DP_TRAINING_PATTERN_DISABLE);
 378 }
 379
 380 void
 381 intel_dp_start_link_train(struct intel_dp *intel_dp)
 382 {
 383         struct intel_connector *intel_connector = intel_dp->attached_connector;
 384
 385         if (!intel_dp_link_training_clock_recovery(intel_dp))
 386                 goto failure_handling;
 387         if (!intel_dp_link_training_channel_equalization(intel_dp))
 388                 goto failure_handling;
 389
 390         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 391                     "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 392                     intel_connector->base.base.id,
 393                     intel_connector->base.name,
 394                     intel_dp->link_rate, intel_dp->lane_count);
 395         return;
 396
 397  failure_handling:
 398         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 399                     "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 400                     intel_connector->base.base.id,
 401                     intel_connector->base.name,
 402                     intel_dp->link_rate, intel_dp->lane_count);
 403         if (!intel_dp_get_link_train_fallback_values(intel_dp,
 404                                                      intel_dp->link_rate,
 405                                                      intel_dp->lane_count))
 406                 /* Schedule a Hotplug Uevent to userspace to start modeset */
 407                 schedule_work(&intel_connector->modeset_retry_work);
 408         return;
 409 }