1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2020 Google, Inc.
6 * Sean Paul <seanpaul@chromium.org>
9 #include <drm/drm_dp_helper.h>
10 #include <drm/drm_dp_mst_helper.h>
11 #include <drm/drm_hdcp.h>
12 #include <drm/drm_print.h>
14 #include "intel_display_types.h"
15 #include "intel_ddi.h"
17 #include "intel_hdcp.h"
19 static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
23 switch (cpu_transcoder) {
25 stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
28 stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
31 stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
34 stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
40 return stream_enc_mask;
43 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
47 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
48 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
49 msecs_to_jiffies(timeout));
52 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
56 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
59 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
60 u8 aksv[DRM_HDCP_KSV_LEN] = {};
63 /* Output An first, that's easy */
64 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
66 if (dpcd_ret != DRM_HDCP_AN_LEN) {
67 drm_dbg_kms(&i915->drm,
68 "Failed to write An over DP/AUX (%zd)\n",
70 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
74 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
75 * send an empty buffer of the correct length through the DP helpers. On
76 * the other side, in the transfer hook, we'll generate a flag based on
77 * the destination address which will tickle the hardware to output the
78 * Aksv on our behalf after the header is sent.
80 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
81 aksv, DRM_HDCP_KSV_LEN);
82 if (dpcd_ret != DRM_HDCP_KSV_LEN) {
83 drm_dbg_kms(&i915->drm,
84 "Failed to write Aksv over DP/AUX (%zd)\n",
86 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
91 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
94 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
97 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
99 if (ret != DRM_HDCP_KSV_LEN) {
100 drm_dbg_kms(&i915->drm,
101 "Read Bksv from DP/AUX failed (%zd)\n", ret);
102 return ret >= 0 ? -EIO : ret;
107 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
110 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
114 * For some reason the HDMI and DP HDCP specs call this register
115 * definition by different names. In the HDMI spec, it's called BSTATUS,
116 * but in DP it's called BINFO.
118 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
119 bstatus, DRM_HDCP_BSTATUS_LEN);
120 if (ret != DRM_HDCP_BSTATUS_LEN) {
121 drm_dbg_kms(&i915->drm,
122 "Read bstatus from DP/AUX failed (%zd)\n", ret);
123 return ret >= 0 ? -EIO : ret;
129 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
132 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
135 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
138 drm_dbg_kms(&i915->drm,
139 "Read bcaps from DP/AUX failed (%zd)\n", ret);
140 return ret >= 0 ? -EIO : ret;
147 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
148 bool *repeater_present)
153 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
157 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
162 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
165 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
168 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
169 ri_prime, DRM_HDCP_RI_LEN);
170 if (ret != DRM_HDCP_RI_LEN) {
171 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
173 return ret >= 0 ? -EIO : ret;
179 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
182 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
186 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
189 drm_dbg_kms(&i915->drm,
190 "Read bstatus from DP/AUX failed (%zd)\n", ret);
191 return ret >= 0 ? -EIO : ret;
193 *ksv_ready = bstatus & DP_BSTATUS_READY;
198 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
199 int num_downstream, u8 *ksv_fifo)
201 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
205 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
206 for (i = 0; i < num_downstream; i += 3) {
207 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
208 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
209 DP_AUX_HDCP_KSV_FIFO,
210 ksv_fifo + i * DRM_HDCP_KSV_LEN,
213 drm_dbg_kms(&i915->drm,
214 "Read ksv[%d] from DP/AUX failed (%zd)\n",
216 return ret >= 0 ? -EIO : ret;
223 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
226 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
229 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
232 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
233 DP_AUX_HDCP_V_PRIME(i), part,
234 DRM_HDCP_V_PRIME_PART_LEN);
235 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
236 drm_dbg_kms(&i915->drm,
237 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
238 return ret >= 0 ? -EIO : ret;
244 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
245 enum transcoder cpu_transcoder,
248 /* Not used for single stream DisplayPort setups */
253 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
254 struct intel_connector *connector)
256 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
260 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
263 drm_dbg_kms(&i915->drm,
264 "Read bstatus from DP/AUX failed (%zd)\n", ret);
268 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
272 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
278 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
282 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
286 struct hdcp2_dp_errata_stream_type {
291 struct hdcp2_dp_msg_data {
296 u32 timeout2; /* Added for non_paired situation */
297 /* Timeout to read entire msg */
298 u32 msg_read_timeout;
301 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
302 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
303 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
304 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
305 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
307 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
309 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
310 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
311 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
312 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
313 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
314 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
315 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
316 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
317 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
318 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
320 { HDCP_2_2_REP_SEND_RECVID_LIST,
321 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
322 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
323 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
325 { HDCP_2_2_REP_STREAM_MANAGE,
326 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
328 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
329 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
330 /* local define to shovel this through the write_2_2 interface */
331 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
332 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
333 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
338 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
341 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
344 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
345 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
346 HDCP_2_2_DP_RXSTATUS_LEN);
347 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
348 drm_dbg_kms(&i915->drm,
349 "Read bstatus from DP/AUX failed (%zd)\n", ret);
350 return ret >= 0 ? -EIO : ret;
357 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
358 u8 msg_id, bool *msg_ready)
364 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
369 case HDCP_2_2_AKE_SEND_HPRIME:
370 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
373 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
374 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
377 case HDCP_2_2_REP_SEND_RECVID_LIST:
378 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
382 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
390 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
391 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
393 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
394 struct intel_dp *dp = &dig_port->dp;
395 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
396 u8 msg_id = hdcp2_msg_data->msg_id;
398 bool msg_ready = false;
400 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
401 timeout = hdcp2_msg_data->timeout2;
403 timeout = hdcp2_msg_data->timeout;
406 * There is no way to detect the CERT, LPRIME and STREAM_READY
407 * availability. So Wait for timeout and read the msg.
409 if (!hdcp2_msg_data->msg_detectable) {
414 * As we want to check the msg availability at timeout, Ignoring
415 * the timeout at wait for CP_IRQ.
417 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
418 ret = hdcp2_detect_msg_availability(dig_port,
425 drm_dbg_kms(&i915->drm,
426 "msg_id %d, ret %d, timeout(mSec): %d\n",
427 hdcp2_msg_data->msg_id, ret, timeout);
432 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
436 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
437 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
438 return &hdcp2_dp_msg_data[i];
444 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
445 void *buf, size_t size)
447 struct intel_dp *dp = &dig_port->dp;
448 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
451 ssize_t ret, bytes_to_write, len;
452 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
454 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
458 offset = hdcp2_msg_data->offset;
460 /* No msg_id in DP HDCP2.2 msgs */
461 bytes_to_write = size - 1;
464 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
466 while (bytes_to_write) {
467 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
468 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
470 ret = drm_dp_dpcd_write(&dig_port->dp.aux,
471 offset, (void *)byte, len);
475 bytes_to_write -= ret;
484 get_rxinfo_hdcp_1_dev_downstream(struct intel_digital_port *dig_port, bool *hdcp_1_x)
486 u8 rx_info[HDCP_2_2_RXINFO_LEN];
489 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
490 DP_HDCP_2_2_REG_RXINFO_OFFSET,
491 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
493 if (ret != HDCP_2_2_RXINFO_LEN)
494 return ret >= 0 ? -EIO : ret;
496 *hdcp_1_x = HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) ? true : false;
501 ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port)
503 u8 rx_info[HDCP_2_2_RXINFO_LEN];
507 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
508 DP_HDCP_2_2_REG_RXINFO_OFFSET,
509 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
510 if (ret != HDCP_2_2_RXINFO_LEN)
511 return ret >= 0 ? -EIO : ret;
513 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
514 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
516 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
517 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
519 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
520 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
521 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
527 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
528 u8 msg_id, void *buf, size_t size)
530 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
533 ssize_t ret, bytes_to_recv, len;
534 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
538 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
541 offset = hdcp2_msg_data->offset;
543 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
547 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
548 ret = get_receiver_id_list_size(dig_port);
554 bytes_to_recv = size - 1;
556 /* DP adaptation msgs has no msg_id */
559 while (bytes_to_recv) {
560 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
561 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
563 /* Entire msg read timeout since initiate of msg read */
564 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
565 msg_end = ktime_add_ms(ktime_get_raw(),
566 hdcp2_msg_data->msg_read_timeout);
568 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
571 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
576 bytes_to_recv -= ret;
581 if (hdcp2_msg_data->msg_read_timeout > 0) {
582 msg_expired = ktime_after(ktime_get_raw(), msg_end);
584 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
585 msg_id, hdcp2_msg_data->msg_read_timeout);
597 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
598 bool is_repeater, u8 content_type)
601 struct hdcp2_dp_errata_stream_type stream_type_msg;
607 * Errata for DP: As Stream type is used for encryption, Receiver
608 * should be communicated with stream type for the decryption of the
610 * Repeater will be communicated with stream type as a part of it's
611 * auth later in time.
613 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
614 stream_type_msg.stream_type = content_type;
616 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
617 sizeof(stream_type_msg));
619 return ret < 0 ? ret : 0;
624 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
625 struct intel_connector *connector)
630 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
634 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
635 ret = HDCP_REAUTH_REQUEST;
636 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
637 ret = HDCP_LINK_INTEGRITY_FAILURE;
638 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
639 ret = HDCP_TOPOLOGY_CHANGE;
645 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
652 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
653 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
654 rx_caps, HDCP_2_2_RXCAPS_LEN);
655 if (ret != HDCP_2_2_RXCAPS_LEN)
656 return ret >= 0 ? -EIO : ret;
658 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
659 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
666 int intel_dp_mst_streams_type1_capable(struct intel_connector *connector,
669 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
670 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
674 ret = get_rxinfo_hdcp_1_dev_downstream(dig_port, &hdcp_1_x);
676 drm_dbg_kms(&i915->drm,
677 "[%s:%d] failed to read RxInfo ret=%d\n",
678 connector->base.name, connector->base.base.id, ret);
682 *capable = !hdcp_1_x;
686 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
687 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
688 .read_bksv = intel_dp_hdcp_read_bksv,
689 .read_bstatus = intel_dp_hdcp_read_bstatus,
690 .repeater_present = intel_dp_hdcp_repeater_present,
691 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
692 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
693 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
694 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
695 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
696 .check_link = intel_dp_hdcp_check_link,
697 .hdcp_capable = intel_dp_hdcp_capable,
698 .write_2_2_msg = intel_dp_hdcp2_write_msg,
699 .read_2_2_msg = intel_dp_hdcp2_read_msg,
700 .config_stream_type = intel_dp_hdcp2_config_stream_type,
701 .check_2_2_link = intel_dp_hdcp2_check_link,
702 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
703 .protocol = HDCP_PROTOCOL_DP,
707 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
710 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
711 struct drm_i915_private *i915 = to_i915(connector->base.dev);
712 struct intel_hdcp *hdcp = &connector->hdcp;
715 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
716 hdcp->stream_transcoder, enable,
717 TRANS_DDI_HDCP_SELECT);
719 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
720 enable ? "Enable" : "Disable", ret);
725 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
728 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
729 struct drm_i915_private *i915 = to_i915(connector->base.dev);
730 struct intel_hdcp *hdcp = &connector->hdcp;
731 enum port port = dig_port->base.port;
732 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
733 u32 stream_enc_status;
736 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
740 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder);
741 if (!stream_enc_status)
744 /* Wait for encryption confirmation */
745 if (intel_de_wait_for_register(i915,
746 HDCP_STATUS(i915, cpu_transcoder, port),
748 enable ? stream_enc_status : 0,
749 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
750 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
751 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
759 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
762 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
763 struct drm_i915_private *i915 = to_i915(connector->base.dev);
764 struct hdcp_port_data *data = &dig_port->hdcp_port_data;
765 struct intel_hdcp *hdcp = &connector->hdcp;
766 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
767 enum pipe pipe = (enum pipe)cpu_transcoder;
768 enum port port = dig_port->base.port;
771 drm_WARN_ON(&i915->drm, enable &&
772 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
773 & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
775 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
779 /* Wait for encryption confirmation */
780 if (intel_de_wait_for_register(i915,
781 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
782 STREAM_ENCRYPTION_STATUS,
783 enable ? STREAM_ENCRYPTION_STATUS : 0,
784 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
785 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
786 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
794 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
795 struct intel_connector *connector)
797 struct intel_hdcp *hdcp = &connector->hdcp;
801 * We do need to do the Link Check only for the connector involved with
802 * HDCP port authentication and encryption.
803 * We can re-use the hdcp->is_repeater flag to know that the connector
804 * involved with HDCP port authentication and encryption.
806 if (hdcp->is_repeater) {
807 ret = intel_dp_hdcp2_check_link(dig_port, connector);
815 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
816 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
817 .read_bksv = intel_dp_hdcp_read_bksv,
818 .read_bstatus = intel_dp_hdcp_read_bstatus,
819 .repeater_present = intel_dp_hdcp_repeater_present,
820 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
821 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
822 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
823 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
824 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
825 .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
826 .check_link = intel_dp_hdcp_check_link,
827 .hdcp_capable = intel_dp_hdcp_capable,
828 .write_2_2_msg = intel_dp_hdcp2_write_msg,
829 .read_2_2_msg = intel_dp_hdcp2_read_msg,
830 .config_stream_type = intel_dp_hdcp2_config_stream_type,
831 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
832 .check_2_2_link = intel_dp_mst_hdcp2_check_link,
833 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
834 .streams_type1_capable = intel_dp_mst_streams_type1_capable,
835 .protocol = HDCP_PROTOCOL_DP,
838 int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
839 struct intel_connector *intel_connector)
841 struct drm_device *dev = intel_connector->base.dev;
842 struct drm_i915_private *dev_priv = to_i915(dev);
843 struct intel_encoder *intel_encoder = &dig_port->base;
844 enum port port = intel_encoder->port;
845 struct intel_dp *intel_dp = &dig_port->dp;
847 if (!is_hdcp_supported(dev_priv, port))
850 if (intel_connector->mst_port)
851 return intel_hdcp_init(intel_connector, dig_port,
852 &intel_dp_mst_hdcp_shim);
853 else if (!intel_dp_is_edp(intel_dp))
854 return intel_hdcp_init(intel_connector, dig_port,
855 &intel_dp_hdcp_shim);