drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43
  44 #include "i915_debugfs.h"
  45 #include "i915_drv.h"
  46 #include "i915_trace.h"
  47 #include "intel_atomic.h"
  48 #include "intel_audio.h"
  49 #include "intel_connector.h"
  50 #include "intel_ddi.h"
  51 #include "intel_display_types.h"
  52 #include "intel_dp.h"
  53 #include "intel_dp_link_training.h"
  54 #include "intel_dp_mst.h"
  55 #include "intel_dpio_phy.h"
  56 #include "intel_fifo_underrun.h"
  57 #include "intel_hdcp.h"
  58 #include "intel_hdmi.h"
  59 #include "intel_hotplug.h"
  60 #include "intel_lspcon.h"
  61 #include "intel_lvds.h"
  62 #include "intel_panel.h"
  63 #include "intel_psr.h"
  64 #include "intel_sideband.h"
  65 #include "intel_tc.h"
  66 #include "intel_vdsc.h"
  67
  68 #define DP_DPRX_ESI_LEN 14
  69
  70 /* DP DSC throughput values used for slice count calculations KPixels/s */
  71 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  72 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  74
  75 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  76 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  77
  78 /* Compliance test status bits  */
  79 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  80 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83
  84 struct dp_link_dpll {
  85         int clock;
  86         struct dpll dpll;
  87 };
  88
  89 static const struct dp_link_dpll g4x_dpll[] = {
  90         { 162000,
  91                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  92         { 270000,
  93                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  94 };
  95
  96 static const struct dp_link_dpll pch_dpll[] = {
  97         { 162000,
  98                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  99         { 270000,
 100                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 101 };
 102
 103 static const struct dp_link_dpll vlv_dpll[] = {
 104         { 162000,
 105                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 106         { 270000,
 107                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 108 };
 109
 110 /*
 111  * CHV supports eDP 1.4 that have  more link rates.
 112  * Below only provides the fixed rate but exclude variable rate.
 113  */
 114 static const struct dp_link_dpll chv_dpll[] = {
 115         /*
 116          * CHV requires to program fractional division for m2.
 117          * m2 is stored in fixed point format using formula below
 118          * (m2_int << 22) | m2_fraction
 119          */
 120         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 121                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 122         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 123                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 124 };
 125
 126 /* Constants for DP DSC configurations */
 127 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 128
 129 /* With Single pipe configuration, HW is capable of supporting maximum
 130  * of 4 slices per line.
 131  */
 132 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 133
 134 /**
 135  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 136  * @intel_dp: DP struct
 137  *
 138  * If a CPU or PCH DP output is attached to an eDP panel, this function
 139  * will return true, and false otherwise.
 140  */
 141 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 142 {
 143         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 144
 145         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 146 }
 147
 148 static void intel_dp_link_down(struct intel_encoder *encoder,
 149                                const struct intel_crtc_state *old_crtc_state);
 150 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 151 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 152 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 153                                            const struct intel_crtc_state *crtc_state);
 154 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 155                                       enum pipe pipe);
 156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 157
 158 /* update sink rates from dpcd */
 159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 160 {
 161         static const int dp_rates[] = {
 162                 162000, 270000, 540000, 810000
 163         };
 164         int i, max_rate;
 165
 166         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 167                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 168                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 169                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 170
 171                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 172                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 173
 174                 return;
 175         }
 176
 177         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 178
 179         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 180                 if (dp_rates[i] > max_rate)
 181                         break;
 182                 intel_dp->sink_rates[i] = dp_rates[i];
 183         }
 184
 185         intel_dp->num_sink_rates = i;
 186 }
 187
 188 /* Get length of rates array potentially limited by max_rate. */
 189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 190 {
 191         int i;
 192
 193         /* Limit results by potentially reduced max rate */
 194         for (i = 0; i < len; i++) {
 195                 if (rates[len - i - 1] <= max_rate)
 196                         return len - i;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /* Get length of common rates array potentially limited by max_rate. */
 203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 204                                           int max_rate)
 205 {
 206         return intel_dp_rate_limit_len(intel_dp->common_rates,
 207                                        intel_dp->num_common_rates, max_rate);
 208 }
 209
 210 /* Theoretical max between source and sink */
 211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 212 {
 213         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 214 }
 215
 216 /* Theoretical max between source and sink */
 217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 218 {
 219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 220         int source_max = intel_dig_port->max_lanes;
 221         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 222         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 223
 224         return min3(source_max, sink_max, fia_max);
 225 }
 226
 227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 228 {
 229         return intel_dp->max_link_lane_count;
 230 }
 231
 232 int
 233 intel_dp_link_required(int pixel_clock, int bpp)
 234 {
 235         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 236         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 237 }
 238
 239 int
 240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 241 {
 242         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 243          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 244          * is transmitted every LS_Clk per lane, there is no need to account for
 245          * the channel encoding that is done in the PHY layer here.
 246          */
 247
 248         return max_link_clock * max_lanes;
 249 }
 250
 251 static int
 252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 253 {
 254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 255         struct intel_encoder *encoder = &intel_dig_port->base;
 256         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257         int max_dotclk = dev_priv->max_dotclk_freq;
 258         int ds_max_dotclk;
 259
 260         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 261
 262         if (type != DP_DS_PORT_TYPE_VGA)
 263                 return max_dotclk;
 264
 265         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 266                                                     intel_dp->downstream_ports);
 267
 268         if (ds_max_dotclk != 0)
 269                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 270
 271         return max_dotclk;
 272 }
 273
 274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 275 {
 276         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 277         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 278         enum port port = dig_port->base.port;
 279
 280         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 281
 282         /* Low voltage SKUs are limited to max of 5.4G */
 283         if (voltage == VOLTAGE_INFO_0_85V)
 284                 return 540000;
 285
 286         /* For this SKU 8.1G is supported in all ports */
 287         if (IS_CNL_WITH_PORT_F(dev_priv))
 288                 return 810000;
 289
 290         /* For other SKUs, max rate on ports A and D is 5.4G */
 291         if (port == PORT_A || port == PORT_D)
 292                 return 540000;
 293
 294         return 810000;
 295 }
 296
 297 static int icl_max_source_rate(struct intel_dp *intel_dp)
 298 {
 299         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 300         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 301         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 302
 303         if (intel_phy_is_combo(dev_priv, phy) &&
 304             !IS_ELKHARTLAKE(dev_priv) &&
 305             !intel_dp_is_edp(intel_dp))
 306                 return 540000;
 307
 308         return 810000;
 309 }
 310
 311 static void
 312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 313 {
 314         /* The values must be in increasing order */
 315         static const int cnl_rates[] = {
 316                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 317         };
 318         static const int bxt_rates[] = {
 319                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 320         };
 321         static const int skl_rates[] = {
 322                 162000, 216000, 270000, 324000, 432000, 540000
 323         };
 324         static const int hsw_rates[] = {
 325                 162000, 270000, 540000
 326         };
 327         static const int g4x_rates[] = {
 328                 162000, 270000
 329         };
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         struct intel_encoder *encoder = &dig_port->base;
 332         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 333         const int *source_rates;
 334         int size, max_rate = 0, vbt_max_rate;
 335
 336         /* This should only be done once */
 337         drm_WARN_ON(&dev_priv->drm,
 338                     intel_dp->source_rates || intel_dp->num_source_rates);
 339
 340         if (INTEL_GEN(dev_priv) >= 10) {
 341                 source_rates = cnl_rates;
 342                 size = ARRAY_SIZE(cnl_rates);
 343                 if (IS_GEN(dev_priv, 10))
 344                         max_rate = cnl_max_source_rate(intel_dp);
 345                 else
 346                         max_rate = icl_max_source_rate(intel_dp);
 347         } else if (IS_GEN9_LP(dev_priv)) {
 348                 source_rates = bxt_rates;
 349                 size = ARRAY_SIZE(bxt_rates);
 350         } else if (IS_GEN9_BC(dev_priv)) {
 351                 source_rates = skl_rates;
 352                 size = ARRAY_SIZE(skl_rates);
 353         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 354                    IS_BROADWELL(dev_priv)) {
 355                 source_rates = hsw_rates;
 356                 size = ARRAY_SIZE(hsw_rates);
 357         } else {
 358                 source_rates = g4x_rates;
 359                 size = ARRAY_SIZE(g4x_rates);
 360         }
 361
 362         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 363         if (max_rate && vbt_max_rate)
 364                 max_rate = min(max_rate, vbt_max_rate);
 365         else if (vbt_max_rate)
 366                 max_rate = vbt_max_rate;
 367
 368         if (max_rate)
 369                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 370
 371         intel_dp->source_rates = source_rates;
 372         intel_dp->num_source_rates = size;
 373 }
 374
 375 static int intersect_rates(const int *source_rates, int source_len,
 376                            const int *sink_rates, int sink_len,
 377                            int *common_rates)
 378 {
 379         int i = 0, j = 0, k = 0;
 380
 381         while (i < source_len && j < sink_len) {
 382                 if (source_rates[i] == sink_rates[j]) {
 383                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 384                                 return k;
 385                         common_rates[k] = source_rates[i];
 386                         ++k;
 387                         ++i;
 388                         ++j;
 389                 } else if (source_rates[i] < sink_rates[j]) {
 390                         ++i;
 391                 } else {
 392                         ++j;
 393                 }
 394         }
 395         return k;
 396 }
 397
 398 /* return index of rate in rates array, or -1 if not found */
 399 static int intel_dp_rate_index(const int *rates, int len, int rate)
 400 {
 401         int i;
 402
 403         for (i = 0; i < len; i++)
 404                 if (rate == rates[i])
 405                         return i;
 406
 407         return -1;
 408 }
 409
 410 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 411 {
 412         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 413
 414         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 415                                                      intel_dp->num_source_rates,
 416                                                      intel_dp->sink_rates,
 417                                                      intel_dp->num_sink_rates,
 418                                                      intel_dp->common_rates);
 419
 420         /* Paranoia, there should always be something in common. */
 421         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 422                 intel_dp->common_rates[0] = 162000;
 423                 intel_dp->num_common_rates = 1;
 424         }
 425 }
 426
 427 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 428                                        u8 lane_count)
 429 {
 430         /*
 431          * FIXME: we need to synchronize the current link parameters with
 432          * hardware readout. Currently fast link training doesn't work on
 433          * boot-up.
 434          */
 435         if (link_rate == 0 ||
 436             link_rate > intel_dp->max_link_rate)
 437                 return false;
 438
 439         if (lane_count == 0 ||
 440             lane_count > intel_dp_max_lane_count(intel_dp))
 441                 return false;
 442
 443         return true;
 444 }
 445
 446 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 447                                                      int link_rate,
 448                                                      u8 lane_count)
 449 {
 450         const struct drm_display_mode *fixed_mode =
 451                 intel_dp->attached_connector->panel.fixed_mode;
 452         int mode_rate, max_rate;
 453
 454         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 455         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 456         if (mode_rate > max_rate)
 457                 return false;
 458
 459         return true;
 460 }
 461
 462 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 463                                             int link_rate, u8 lane_count)
 464 {
 465         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 466         int index;
 467
 468         index = intel_dp_rate_index(intel_dp->common_rates,
 469                                     intel_dp->num_common_rates,
 470                                     link_rate);
 471         if (index > 0) {
 472                 if (intel_dp_is_edp(intel_dp) &&
 473                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 474                                                               intel_dp->common_rates[index - 1],
 475                                                               lane_count)) {
 476                         drm_dbg_kms(&i915->drm,
 477                                     "Retrying Link training for eDP with same parameters\n");
 478                         return 0;
 479                 }
 480                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 481                 intel_dp->max_link_lane_count = lane_count;
 482         } else if (lane_count > 1) {
 483                 if (intel_dp_is_edp(intel_dp) &&
 484                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 485                                                               intel_dp_max_common_rate(intel_dp),
 486                                                               lane_count >> 1)) {
 487                         drm_dbg_kms(&i915->drm,
 488                                     "Retrying Link training for eDP with same parameters\n");
 489                         return 0;
 490                 }
 491                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 492                 intel_dp->max_link_lane_count = lane_count >> 1;
 493         } else {
 494                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 495                 return -1;
 496         }
 497
 498         return 0;
 499 }
 500
 501 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 502 {
 503         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 504                        DP_DSC_FEC_OVERHEAD_FACTOR);
 505 }
 506
 507 static int
 508 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 509 {
 510         if (INTEL_GEN(i915) >= 11)
 511                 return 7680 * 8;
 512         else
 513                 return 6144 * 8;
 514 }
 515
 516 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 517                                        u32 link_clock, u32 lane_count,
 518                                        u32 mode_clock, u32 mode_hdisplay)
 519 {
 520         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 521         int i;
 522
 523         /*
 524          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 525          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 526          * for SST -> TimeSlotsPerMTP is 1,
 527          * for MST -> TimeSlotsPerMTP has to be calculated
 528          */
 529         bits_per_pixel = (link_clock * lane_count * 8) /
 530                          intel_dp_mode_to_fec_clock(mode_clock);
 531         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 532
 533         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 534         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 535                 mode_hdisplay;
 536         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 537                     max_bpp_small_joiner_ram);
 538
 539         /*
 540          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 541          * check, output bpp from small joiner RAM check)
 542          */
 543         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 544
 545         /* Error out if the max bpp is less than smallest allowed valid bpp */
 546         if (bits_per_pixel < valid_dsc_bpp[0]) {
 547                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 548                             bits_per_pixel, valid_dsc_bpp[0]);
 549                 return 0;
 550         }
 551
 552         /* Find the nearest match in the array of known BPPs from VESA */
 553         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 554                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 555                         break;
 556         }
 557         bits_per_pixel = valid_dsc_bpp[i];
 558
 559         /*
 560          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 561          * fractional part is 0
 562          */
 563         return bits_per_pixel << 4;
 564 }
 565
 566 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 567                                        int mode_clock, int mode_hdisplay)
 568 {
 569         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 570         u8 min_slice_count, i;
 571         int max_slice_width;
 572
 573         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 574                 min_slice_count = DIV_ROUND_UP(mode_clock,
 575                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 576         else
 577                 min_slice_count = DIV_ROUND_UP(mode_clock,
 578                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 579
 580         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 581         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 582                 drm_dbg_kms(&i915->drm,
 583                             "Unsupported slice width %d by DP DSC Sink device\n",
 584                             max_slice_width);
 585                 return 0;
 586         }
 587         /* Also take into account max slice width */
 588         min_slice_count = min_t(u8, min_slice_count,
 589                                 DIV_ROUND_UP(mode_hdisplay,
 590                                              max_slice_width));
 591
 592         /* Find the closest match to the valid slice count values */
 593         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 594                 if (valid_dsc_slicecount[i] >
 595                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 596                                                     false))
 597                         break;
 598                 if (min_slice_count  <= valid_dsc_slicecount[i])
 599                         return valid_dsc_slicecount[i];
 600         }
 601
 602         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 603                     min_slice_count);
 604         return 0;
 605 }
 606
 607 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 608                                   int hdisplay)
 609 {
 610         /*
 611          * Older platforms don't like hdisplay==4096 with DP.
 612          *
 613          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 614          * and frame counter increment), but we don't get vblank interrupts,
 615          * and the pipe underruns immediately. The link also doesn't seem
 616          * to get trained properly.
 617          *
 618          * On CHV the vblank interrupts don't seem to disappear but
 619          * otherwise the symptoms are similar.
 620          *
 621          * TODO: confirm the behaviour on HSW+
 622          */
 623         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 624 }
 625
 626 static enum drm_mode_status
 627 intel_dp_mode_valid(struct drm_connector *connector,
 628                     struct drm_display_mode *mode)
 629 {
 630         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 631         struct intel_connector *intel_connector = to_intel_connector(connector);
 632         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 633         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 634         int target_clock = mode->clock;
 635         int max_rate, mode_rate, max_lanes, max_link_clock;
 636         int max_dotclk;
 637         u16 dsc_max_output_bpp = 0;
 638         u8 dsc_slice_count = 0;
 639
 640         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 641                 return MODE_NO_DBLESCAN;
 642
 643         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 644
 645         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 646                 if (mode->hdisplay > fixed_mode->hdisplay)
 647                         return MODE_PANEL;
 648
 649                 if (mode->vdisplay > fixed_mode->vdisplay)
 650                         return MODE_PANEL;
 651
 652                 target_clock = fixed_mode->clock;
 653         }
 654
 655         max_link_clock = intel_dp_max_link_rate(intel_dp);
 656         max_lanes = intel_dp_max_lane_count(intel_dp);
 657
 658         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 659         mode_rate = intel_dp_link_required(target_clock, 18);
 660
 661         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 662                 return MODE_H_ILLEGAL;
 663
 664         /*
 665          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 666          * integer value since we support only integer values of bpp.
 667          */
 668         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 669             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 670                 if (intel_dp_is_edp(intel_dp)) {
 671                         dsc_max_output_bpp =
 672                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 673                         dsc_slice_count =
 674                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 675                                                                 true);
 676                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 677                         dsc_max_output_bpp =
 678                                 intel_dp_dsc_get_output_bpp(dev_priv,
 679                                                             max_link_clock,
 680                                                             max_lanes,
 681                                                             target_clock,
 682                                                             mode->hdisplay) >> 4;
 683                         dsc_slice_count =
 684                                 intel_dp_dsc_get_slice_count(intel_dp,
 685                                                              target_clock,
 686                                                              mode->hdisplay);
 687                 }
 688         }
 689
 690         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 691             target_clock > max_dotclk)
 692                 return MODE_CLOCK_HIGH;
 693
 694         if (mode->clock < 10000)
 695                 return MODE_CLOCK_LOW;
 696
 697         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 698                 return MODE_H_ILLEGAL;
 699
 700         return intel_mode_valid_max_plane_size(dev_priv, mode);
 701 }
 702
 703 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 704 {
 705         int i;
 706         u32 v = 0;
 707
 708         if (src_bytes > 4)
 709                 src_bytes = 4;
 710         for (i = 0; i < src_bytes; i++)
 711                 v |= ((u32)src[i]) << ((3 - i) * 8);
 712         return v;
 713 }
 714
 715 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 716 {
 717         int i;
 718         if (dst_bytes > 4)
 719                 dst_bytes = 4;
 720         for (i = 0; i < dst_bytes; i++)
 721                 dst[i] = src >> ((3-i) * 8);
 722 }
 723
 724 static void
 725 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 726 static void
 727 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 728                                               bool force_disable_vdd);
 729 static void
 730 intel_dp_pps_init(struct intel_dp *intel_dp);
 731
 732 static intel_wakeref_t
 733 pps_lock(struct intel_dp *intel_dp)
 734 {
 735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 736         intel_wakeref_t wakeref;
 737
 738         /*
 739          * See intel_power_sequencer_reset() why we need
 740          * a power domain reference here.
 741          */
 742         wakeref = intel_display_power_get(dev_priv,
 743                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 744
 745         mutex_lock(&dev_priv->pps_mutex);
 746
 747         return wakeref;
 748 }
 749
 750 static intel_wakeref_t
 751 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 752 {
 753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 754
 755         mutex_unlock(&dev_priv->pps_mutex);
 756         intel_display_power_put(dev_priv,
 757                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 758                                 wakeref);
 759         return 0;
 760 }
 761
 762 #define with_pps_lock(dp, wf) \
 763         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 764
 765 static void
 766 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 767 {
 768         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 769         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 770         enum pipe pipe = intel_dp->pps_pipe;
 771         bool pll_enabled, release_cl_override = false;
 772         enum dpio_phy phy = DPIO_PHY(pipe);
 773         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 774         u32 DP;
 775
 776         if (drm_WARN(&dev_priv->drm,
 777                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 778                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 779                      pipe_name(pipe), intel_dig_port->base.base.base.id,
 780                      intel_dig_port->base.base.name))
 781                 return;
 782
 783         drm_dbg_kms(&dev_priv->drm,
 784                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 785                     pipe_name(pipe), intel_dig_port->base.base.base.id,
 786                     intel_dig_port->base.base.name);
 787
 788         /* Preserve the BIOS-computed detected bit. This is
 789          * supposed to be read-only.
 790          */
 791         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 792         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 793         DP |= DP_PORT_WIDTH(1);
 794         DP |= DP_LINK_TRAIN_PAT_1;
 795
 796         if (IS_CHERRYVIEW(dev_priv))
 797                 DP |= DP_PIPE_SEL_CHV(pipe);
 798         else
 799                 DP |= DP_PIPE_SEL(pipe);
 800
 801         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 802
 803         /*
 804          * The DPLL for the pipe must be enabled for this to work.
 805          * So enable temporarily it if it's not already enabled.
 806          */
 807         if (!pll_enabled) {
 808                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 809                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 810
 811                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 812                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 813                         drm_err(&dev_priv->drm,
 814                                 "Failed to force on pll for pipe %c!\n",
 815                                 pipe_name(pipe));
 816                         return;
 817                 }
 818         }
 819
 820         /*
 821          * Similar magic as in intel_dp_enable_port().
 822          * We _must_ do this port enable + disable trick
 823          * to make this power sequencer lock onto the port.
 824          * Otherwise even VDD force bit won't work.
 825          */
 826         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 827         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 828
 829         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 830         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 831
 832         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 833         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 834
 835         if (!pll_enabled) {
 836                 vlv_force_pll_off(dev_priv, pipe);
 837
 838                 if (release_cl_override)
 839                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 840         }
 841 }
 842
 843 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 844 {
 845         struct intel_encoder *encoder;
 846         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 847
 848         /*
 849          * We don't have power sequencer currently.
 850          * Pick one that's not used by other ports.
 851          */
 852         for_each_intel_dp(&dev_priv->drm, encoder) {
 853                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 854
 855                 if (encoder->type == INTEL_OUTPUT_EDP) {
 856                         drm_WARN_ON(&dev_priv->drm,
 857                                     intel_dp->active_pipe != INVALID_PIPE &&
 858                                     intel_dp->active_pipe !=
 859                                     intel_dp->pps_pipe);
 860
 861                         if (intel_dp->pps_pipe != INVALID_PIPE)
 862                                 pipes &= ~(1 << intel_dp->pps_pipe);
 863                 } else {
 864                         drm_WARN_ON(&dev_priv->drm,
 865                                     intel_dp->pps_pipe != INVALID_PIPE);
 866
 867                         if (intel_dp->active_pipe != INVALID_PIPE)
 868                                 pipes &= ~(1 << intel_dp->active_pipe);
 869                 }
 870         }
 871
 872         if (pipes == 0)
 873                 return INVALID_PIPE;
 874
 875         return ffs(pipes) - 1;
 876 }
 877
 878 static enum pipe
 879 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 880 {
 881         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 882         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 883         enum pipe pipe;
 884
 885         lockdep_assert_held(&dev_priv->pps_mutex);
 886
 887         /* We should never land here with regular DP ports */
 888         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 889
 890         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
 891                     intel_dp->active_pipe != intel_dp->pps_pipe);
 892
 893         if (intel_dp->pps_pipe != INVALID_PIPE)
 894                 return intel_dp->pps_pipe;
 895
 896         pipe = vlv_find_free_pps(dev_priv);
 897
 898         /*
 899          * Didn't find one. This should not happen since there
 900          * are two power sequencers and up to two eDP ports.
 901          */
 902         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 903                 pipe = PIPE_A;
 904
 905         vlv_steal_power_sequencer(dev_priv, pipe);
 906         intel_dp->pps_pipe = pipe;
 907
 908         drm_dbg_kms(&dev_priv->drm,
 909                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 910                     pipe_name(intel_dp->pps_pipe),
 911                     intel_dig_port->base.base.base.id,
 912                     intel_dig_port->base.base.name);
 913
 914         /* init power sequencer on this pipe and port */
 915         intel_dp_init_panel_power_sequencer(intel_dp);
 916         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 917
 918         /*
 919          * Even vdd force doesn't work until we've made
 920          * the power sequencer lock in on the port.
 921          */
 922         vlv_power_sequencer_kick(intel_dp);
 923
 924         return intel_dp->pps_pipe;
 925 }
 926
 927 static int
 928 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 929 {
 930         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 931         int backlight_controller = dev_priv->vbt.backlight.controller;
 932
 933         lockdep_assert_held(&dev_priv->pps_mutex);
 934
 935         /* We should never land here with regular DP ports */
 936         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 937
 938         if (!intel_dp->pps_reset)
 939                 return backlight_controller;
 940
 941         intel_dp->pps_reset = false;
 942
 943         /*
 944          * Only the HW needs to be reprogrammed, the SW state is fixed and
 945          * has been setup during connector init.
 946          */
 947         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 948
 949         return backlight_controller;
 950 }
 951
 952 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 953                                enum pipe pipe);
 954
 955 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 956                                enum pipe pipe)
 957 {
 958         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 959 }
 960
 961 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 962                                 enum pipe pipe)
 963 {
 964         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 965 }
 966
 967 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 968                          enum pipe pipe)
 969 {
 970         return true;
 971 }
 972
 973 static enum pipe
 974 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 975                      enum port port,
 976                      vlv_pipe_check pipe_check)
 977 {
 978         enum pipe pipe;
 979
 980         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 981                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 982                         PANEL_PORT_SELECT_MASK;
 983
 984                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 985                         continue;
 986
 987                 if (!pipe_check(dev_priv, pipe))
 988                         continue;
 989
 990                 return pipe;
 991         }
 992
 993         return INVALID_PIPE;
 994 }
 995
 996 static void
 997 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 998 {
 999         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1000         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1001         enum port port = intel_dig_port->base.port;
1002
1003         lockdep_assert_held(&dev_priv->pps_mutex);
1004
1005         /* try to find a pipe with this port selected */
1006         /* first pick one where the panel is on */
1007         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1008                                                   vlv_pipe_has_pp_on);
1009         /* didn't find one? pick one where vdd is on */
1010         if (intel_dp->pps_pipe == INVALID_PIPE)
1011                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1012                                                           vlv_pipe_has_vdd_on);
1013         /* didn't find one? pick one with just the correct port */
1014         if (intel_dp->pps_pipe == INVALID_PIPE)
1015                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1016                                                           vlv_pipe_any);
1017
1018         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1019         if (intel_dp->pps_pipe == INVALID_PIPE) {
1020                 drm_dbg_kms(&dev_priv->drm,
1021                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1022                             intel_dig_port->base.base.base.id,
1023                             intel_dig_port->base.base.name);
1024                 return;
1025         }
1026
1027         drm_dbg_kms(&dev_priv->drm,
1028                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1029                     intel_dig_port->base.base.base.id,
1030                     intel_dig_port->base.base.name,
1031                     pipe_name(intel_dp->pps_pipe));
1032
1033         intel_dp_init_panel_power_sequencer(intel_dp);
1034         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1035 }
1036
1037 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1038 {
1039         struct intel_encoder *encoder;
1040
1041         if (drm_WARN_ON(&dev_priv->drm,
1042                         !(IS_VALLEYVIEW(dev_priv) ||
1043                           IS_CHERRYVIEW(dev_priv) ||
1044                           IS_GEN9_LP(dev_priv))))
1045                 return;
1046
1047         /*
1048          * We can't grab pps_mutex here due to deadlock with power_domain
1049          * mutex when power_domain functions are called while holding pps_mutex.
1050          * That also means that in order to use pps_pipe the code needs to
1051          * hold both a power domain reference and pps_mutex, and the power domain
1052          * reference get/put must be done while _not_ holding pps_mutex.
1053          * pps_{lock,unlock}() do these steps in the correct order, so one
1054          * should use them always.
1055          */
1056
1057         for_each_intel_dp(&dev_priv->drm, encoder) {
1058                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1059
1060                 drm_WARN_ON(&dev_priv->drm,
1061                             intel_dp->active_pipe != INVALID_PIPE);
1062
1063                 if (encoder->type != INTEL_OUTPUT_EDP)
1064                         continue;
1065
1066                 if (IS_GEN9_LP(dev_priv))
1067                         intel_dp->pps_reset = true;
1068                 else
1069                         intel_dp->pps_pipe = INVALID_PIPE;
1070         }
1071 }
1072
1073 struct pps_registers {
1074         i915_reg_t pp_ctrl;
1075         i915_reg_t pp_stat;
1076         i915_reg_t pp_on;
1077         i915_reg_t pp_off;
1078         i915_reg_t pp_div;
1079 };
1080
1081 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1082                                     struct pps_registers *regs)
1083 {
1084         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1085         int pps_idx = 0;
1086
1087         memset(regs, 0, sizeof(*regs));
1088
1089         if (IS_GEN9_LP(dev_priv))
1090                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1091         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1092                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1093
1094         regs->pp_ctrl = PP_CONTROL(pps_idx);
1095         regs->pp_stat = PP_STATUS(pps_idx);
1096         regs->pp_on = PP_ON_DELAYS(pps_idx);
1097         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1098
1099         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1100         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1101                 regs->pp_div = INVALID_MMIO_REG;
1102         else
1103                 regs->pp_div = PP_DIVISOR(pps_idx);
1104 }
1105
1106 static i915_reg_t
1107 _pp_ctrl_reg(struct intel_dp *intel_dp)
1108 {
1109         struct pps_registers regs;
1110
1111         intel_pps_get_registers(intel_dp, &regs);
1112
1113         return regs.pp_ctrl;
1114 }
1115
1116 static i915_reg_t
1117 _pp_stat_reg(struct intel_dp *intel_dp)
1118 {
1119         struct pps_registers regs;
1120
1121         intel_pps_get_registers(intel_dp, &regs);
1122
1123         return regs.pp_stat;
1124 }
1125
1126 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1127    This function only applicable when panel PM state is not to be tracked */
1128 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1129                               void *unused)
1130 {
1131         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1132                                                  edp_notifier);
1133         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1134         intel_wakeref_t wakeref;
1135
1136         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1137                 return 0;
1138
1139         with_pps_lock(intel_dp, wakeref) {
1140                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1141                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1142                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1143                         u32 pp_div;
1144
1145                         pp_ctrl_reg = PP_CONTROL(pipe);
1146                         pp_div_reg  = PP_DIVISOR(pipe);
1147                         pp_div = intel_de_read(dev_priv, pp_div_reg);
1148                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1149
1150                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1151                         intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1152                         intel_de_write(dev_priv, pp_ctrl_reg,
1153                                        PANEL_UNLOCK_REGS);
1154                         msleep(intel_dp->panel_power_cycle_delay);
1155                 }
1156         }
1157
1158         return 0;
1159 }
1160
1161 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1162 {
1163         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1164
1165         lockdep_assert_held(&dev_priv->pps_mutex);
1166
1167         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1168             intel_dp->pps_pipe == INVALID_PIPE)
1169                 return false;
1170
1171         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1172 }
1173
1174 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1175 {
1176         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1177
1178         lockdep_assert_held(&dev_priv->pps_mutex);
1179
1180         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1181             intel_dp->pps_pipe == INVALID_PIPE)
1182                 return false;
1183
1184         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1185 }
1186
1187 static void
1188 intel_dp_check_edp(struct intel_dp *intel_dp)
1189 {
1190         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1191
1192         if (!intel_dp_is_edp(intel_dp))
1193                 return;
1194
1195         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1196                 drm_WARN(&dev_priv->drm, 1,
1197                          "eDP powered off while attempting aux channel communication.\n");
1198                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1199                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1200                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1201         }
1202 }
1203
1204 static u32
1205 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1206 {
1207         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1209         const unsigned int timeout_ms = 10;
1210         u32 status;
1211         bool done;
1212
1213 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1214         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1215                                   msecs_to_jiffies_timeout(timeout_ms));
1216
1217         /* just trace the final value */
1218         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1219
1220         if (!done)
1221                 drm_err(&i915->drm,
1222                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1223                         intel_dp->aux.name, timeout_ms, status);
1224 #undef C
1225
1226         return status;
1227 }
1228
1229 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1230 {
1231         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1232
1233         if (index)
1234                 return 0;
1235
1236         /*
1237          * The clock divider is based off the hrawclk, and would like to run at
1238          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1239          */
1240         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1241 }
1242
1243 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1244 {
1245         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1246         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1247         u32 freq;
1248
1249         if (index)
1250                 return 0;
1251
1252         /*
1253          * The clock divider is based off the cdclk or PCH rawclk, and would
1254          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1255          * divide by 2000 and use that
1256          */
1257         if (dig_port->aux_ch == AUX_CH_A)
1258                 freq = dev_priv->cdclk.hw.cdclk;
1259         else
1260                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1261         return DIV_ROUND_CLOSEST(freq, 2000);
1262 }
1263
1264 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1265 {
1266         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1267         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1268
1269         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1270                 /* Workaround for non-ULT HSW */
1271                 switch (index) {
1272                 case 0: return 63;
1273                 case 1: return 72;
1274                 default: return 0;
1275                 }
1276         }
1277
1278         return ilk_get_aux_clock_divider(intel_dp, index);
1279 }
1280
1281 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1282 {
1283         /*
1284          * SKL doesn't need us to program the AUX clock divider (Hardware will
1285          * derive the clock from CDCLK automatically). We still implement the
1286          * get_aux_clock_divider vfunc to plug-in into the existing code.
1287          */
1288         return index ? 0 : 1;
1289 }
1290
1291 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1292                                 int send_bytes,
1293                                 u32 aux_clock_divider)
1294 {
1295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296         struct drm_i915_private *dev_priv =
1297                         to_i915(intel_dig_port->base.base.dev);
1298         u32 precharge, timeout;
1299
1300         if (IS_GEN(dev_priv, 6))
1301                 precharge = 3;
1302         else
1303                 precharge = 5;
1304
1305         if (IS_BROADWELL(dev_priv))
1306                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1307         else
1308                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1309
1310         return DP_AUX_CH_CTL_SEND_BUSY |
1311                DP_AUX_CH_CTL_DONE |
1312                DP_AUX_CH_CTL_INTERRUPT |
1313                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1314                timeout |
1315                DP_AUX_CH_CTL_RECEIVE_ERROR |
1316                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1317                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1318                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1319 }
1320
1321 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1322                                 int send_bytes,
1323                                 u32 unused)
1324 {
1325         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1326         struct drm_i915_private *i915 =
1327                         to_i915(intel_dig_port->base.base.dev);
1328         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1329         u32 ret;
1330
1331         ret = DP_AUX_CH_CTL_SEND_BUSY |
1332               DP_AUX_CH_CTL_DONE |
1333               DP_AUX_CH_CTL_INTERRUPT |
1334               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1335               DP_AUX_CH_CTL_TIME_OUT_MAX |
1336               DP_AUX_CH_CTL_RECEIVE_ERROR |
1337               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1338               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1339               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1340
1341         if (intel_phy_is_tc(i915, phy) &&
1342             intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1343                 ret |= DP_AUX_CH_CTL_TBT_IO;
1344
1345         return ret;
1346 }
1347
1348 static int
1349 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1350                   const u8 *send, int send_bytes,
1351                   u8 *recv, int recv_size,
1352                   u32 aux_send_ctl_flags)
1353 {
1354         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355         struct drm_i915_private *i915 =
1356                         to_i915(intel_dig_port->base.base.dev);
1357         struct intel_uncore *uncore = &i915->uncore;
1358         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1359         bool is_tc_port = intel_phy_is_tc(i915, phy);
1360         i915_reg_t ch_ctl, ch_data[5];
1361         u32 aux_clock_divider;
1362         enum intel_display_power_domain aux_domain =
1363                 intel_aux_power_domain(intel_dig_port);
1364         intel_wakeref_t aux_wakeref;
1365         intel_wakeref_t pps_wakeref;
1366         int i, ret, recv_bytes;
1367         int try, clock = 0;
1368         u32 status;
1369         bool vdd;
1370
1371         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1372         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1373                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1374
1375         if (is_tc_port)
1376                 intel_tc_port_lock(intel_dig_port);
1377
1378         aux_wakeref = intel_display_power_get(i915, aux_domain);
1379         pps_wakeref = pps_lock(intel_dp);
1380
1381         /*
1382          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1383          * In such cases we want to leave VDD enabled and it's up to upper layers
1384          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1385          * ourselves.
1386          */
1387         vdd = edp_panel_vdd_on(intel_dp);
1388
1389         /* dp aux is extremely sensitive to irq latency, hence request the
1390          * lowest possible wakeup latency and so prevent the cpu from going into
1391          * deep sleep states.
1392          */
1393         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1394
1395         intel_dp_check_edp(intel_dp);
1396
1397         /* Try to wait for any previous AUX channel activity */
1398         for (try = 0; try < 3; try++) {
1399                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1400                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1401                         break;
1402                 msleep(1);
1403         }
1404         /* just trace the final value */
1405         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1406
1407         if (try == 3) {
1408                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1409
1410                 if (status != intel_dp->aux_busy_last_status) {
1411                         drm_WARN(&i915->drm, 1,
1412                                  "%s: not started (status 0x%08x)\n",
1413                                  intel_dp->aux.name, status);
1414                         intel_dp->aux_busy_last_status = status;
1415                 }
1416
1417                 ret = -EBUSY;
1418                 goto out;
1419         }
1420
1421         /* Only 5 data registers! */
1422         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1423                 ret = -E2BIG;
1424                 goto out;
1425         }
1426
1427         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1428                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1429                                                           send_bytes,
1430                                                           aux_clock_divider);
1431
1432                 send_ctl |= aux_send_ctl_flags;
1433
1434                 /* Must try at least 3 times according to DP spec */
1435                 for (try = 0; try < 5; try++) {
1436                         /* Load the send data into the aux channel data registers */
1437                         for (i = 0; i < send_bytes; i += 4)
1438                                 intel_uncore_write(uncore,
1439                                                    ch_data[i >> 2],
1440                                                    intel_dp_pack_aux(send + i,
1441                                                                      send_bytes - i));
1442
1443                         /* Send the command and wait for it to complete */
1444                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1445
1446                         status = intel_dp_aux_wait_done(intel_dp);
1447
1448                         /* Clear done status and any errors */
1449                         intel_uncore_write(uncore,
1450                                            ch_ctl,
1451                                            status |
1452                                            DP_AUX_CH_CTL_DONE |
1453                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1454                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1455
1456                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1457                          *   400us delay required for errors and timeouts
1458                          *   Timeout errors from the HW already meet this
1459                          *   requirement so skip to next iteration
1460                          */
1461                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1462                                 continue;
1463
1464                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1465                                 usleep_range(400, 500);
1466                                 continue;
1467                         }
1468                         if (status & DP_AUX_CH_CTL_DONE)
1469                                 goto done;
1470                 }
1471         }
1472
1473         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1474                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1475                         intel_dp->aux.name, status);
1476                 ret = -EBUSY;
1477                 goto out;
1478         }
1479
1480 done:
1481         /* Check for timeout or receive error.
1482          * Timeouts occur when the sink is not connected
1483          */
1484         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1485                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1486                         intel_dp->aux.name, status);
1487                 ret = -EIO;
1488                 goto out;
1489         }
1490
1491         /* Timeouts occur when the device isn't connected, so they're
1492          * "normal" -- don't fill the kernel log with these */
1493         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1494                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1495                             intel_dp->aux.name, status);
1496                 ret = -ETIMEDOUT;
1497                 goto out;
1498         }
1499
1500         /* Unload any bytes sent back from the other side */
1501         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1502                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1503
1504         /*
1505          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1506          * We have no idea of what happened so we return -EBUSY so
1507          * drm layer takes care for the necessary retries.
1508          */
1509         if (recv_bytes == 0 || recv_bytes > 20) {
1510                 drm_dbg_kms(&i915->drm,
1511                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1512                             intel_dp->aux.name, recv_bytes);
1513                 ret = -EBUSY;
1514                 goto out;
1515         }
1516
1517         if (recv_bytes > recv_size)
1518                 recv_bytes = recv_size;
1519
1520         for (i = 0; i < recv_bytes; i += 4)
1521                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1522                                     recv + i, recv_bytes - i);
1523
1524         ret = recv_bytes;
1525 out:
1526         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1527
1528         if (vdd)
1529                 edp_panel_vdd_off(intel_dp, false);
1530
1531         pps_unlock(intel_dp, pps_wakeref);
1532         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1533
1534         if (is_tc_port)
1535                 intel_tc_port_unlock(intel_dig_port);
1536
1537         return ret;
1538 }
1539
1540 #define BARE_ADDRESS_SIZE       3
1541 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1542
1543 static void
1544 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1545                     const struct drm_dp_aux_msg *msg)
1546 {
1547         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1548         txbuf[1] = (msg->address >> 8) & 0xff;
1549         txbuf[2] = msg->address & 0xff;
1550         txbuf[3] = msg->size - 1;
1551 }
1552
1553 static ssize_t
1554 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1555 {
1556         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1557         u8 txbuf[20], rxbuf[20];
1558         size_t txsize, rxsize;
1559         int ret;
1560
1561         intel_dp_aux_header(txbuf, msg);
1562
1563         switch (msg->request & ~DP_AUX_I2C_MOT) {
1564         case DP_AUX_NATIVE_WRITE:
1565         case DP_AUX_I2C_WRITE:
1566         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1567                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1568                 rxsize = 2; /* 0 or 1 data bytes */
1569
1570                 if (WARN_ON(txsize > 20))
1571                         return -E2BIG;
1572
1573                 WARN_ON(!msg->buffer != !msg->size);
1574
1575                 if (msg->buffer)
1576                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1577
1578                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1579                                         rxbuf, rxsize, 0);
1580                 if (ret > 0) {
1581                         msg->reply = rxbuf[0] >> 4;
1582
1583                         if (ret > 1) {
1584                                 /* Number of bytes written in a short write. */
1585                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1586                         } else {
1587                                 /* Return payload size. */
1588                                 ret = msg->size;
1589                         }
1590                 }
1591                 break;
1592
1593         case DP_AUX_NATIVE_READ:
1594         case DP_AUX_I2C_READ:
1595                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1596                 rxsize = msg->size + 1;
1597
1598                 if (WARN_ON(rxsize > 20))
1599                         return -E2BIG;
1600
1601                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1602                                         rxbuf, rxsize, 0);
1603                 if (ret > 0) {
1604                         msg->reply = rxbuf[0] >> 4;
1605                         /*
1606                          * Assume happy day, and copy the data. The caller is
1607                          * expected to check msg->reply before touching it.
1608                          *
1609                          * Return payload size.
1610                          */
1611                         ret--;
1612                         memcpy(msg->buffer, rxbuf + 1, ret);
1613                 }
1614                 break;
1615
1616         default:
1617                 ret = -EINVAL;
1618                 break;
1619         }
1620
1621         return ret;
1622 }
1623
1624
1625 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1626 {
1627         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1628         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1629         enum aux_ch aux_ch = dig_port->aux_ch;
1630
1631         switch (aux_ch) {
1632         case AUX_CH_B:
1633         case AUX_CH_C:
1634         case AUX_CH_D:
1635                 return DP_AUX_CH_CTL(aux_ch);
1636         default:
1637                 MISSING_CASE(aux_ch);
1638                 return DP_AUX_CH_CTL(AUX_CH_B);
1639         }
1640 }
1641
1642 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1643 {
1644         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1645         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1646         enum aux_ch aux_ch = dig_port->aux_ch;
1647
1648         switch (aux_ch) {
1649         case AUX_CH_B:
1650         case AUX_CH_C:
1651         case AUX_CH_D:
1652                 return DP_AUX_CH_DATA(aux_ch, index);
1653         default:
1654                 MISSING_CASE(aux_ch);
1655                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1656         }
1657 }
1658
1659 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1660 {
1661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1662         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1663         enum aux_ch aux_ch = dig_port->aux_ch;
1664
1665         switch (aux_ch) {
1666         case AUX_CH_A:
1667                 return DP_AUX_CH_CTL(aux_ch);
1668         case AUX_CH_B:
1669         case AUX_CH_C:
1670         case AUX_CH_D:
1671                 return PCH_DP_AUX_CH_CTL(aux_ch);
1672         default:
1673                 MISSING_CASE(aux_ch);
1674                 return DP_AUX_CH_CTL(AUX_CH_A);
1675         }
1676 }
1677
1678 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1679 {
1680         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1681         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1682         enum aux_ch aux_ch = dig_port->aux_ch;
1683
1684         switch (aux_ch) {
1685         case AUX_CH_A:
1686                 return DP_AUX_CH_DATA(aux_ch, index);
1687         case AUX_CH_B:
1688         case AUX_CH_C:
1689         case AUX_CH_D:
1690                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1691         default:
1692                 MISSING_CASE(aux_ch);
1693                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1694         }
1695 }
1696
1697 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1698 {
1699         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1700         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1701         enum aux_ch aux_ch = dig_port->aux_ch;
1702
1703         switch (aux_ch) {
1704         case AUX_CH_A:
1705         case AUX_CH_B:
1706         case AUX_CH_C:
1707         case AUX_CH_D:
1708         case AUX_CH_E:
1709         case AUX_CH_F:
1710         case AUX_CH_G:
1711                 return DP_AUX_CH_CTL(aux_ch);
1712         default:
1713                 MISSING_CASE(aux_ch);
1714                 return DP_AUX_CH_CTL(AUX_CH_A);
1715         }
1716 }
1717
1718 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1719 {
1720         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1721         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1722         enum aux_ch aux_ch = dig_port->aux_ch;
1723
1724         switch (aux_ch) {
1725         case AUX_CH_A:
1726         case AUX_CH_B:
1727         case AUX_CH_C:
1728         case AUX_CH_D:
1729         case AUX_CH_E:
1730         case AUX_CH_F:
1731         case AUX_CH_G:
1732                 return DP_AUX_CH_DATA(aux_ch, index);
1733         default:
1734                 MISSING_CASE(aux_ch);
1735                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1736         }
1737 }
1738
1739 static void
1740 intel_dp_aux_fini(struct intel_dp *intel_dp)
1741 {
1742         kfree(intel_dp->aux.name);
1743 }
1744
1745 static void
1746 intel_dp_aux_init(struct intel_dp *intel_dp)
1747 {
1748         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1749         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750         struct intel_encoder *encoder = &dig_port->base;
1751
1752         if (INTEL_GEN(dev_priv) >= 9) {
1753                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1754                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1755         } else if (HAS_PCH_SPLIT(dev_priv)) {
1756                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1757                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1758         } else {
1759                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1760                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1761         }
1762
1763         if (INTEL_GEN(dev_priv) >= 9)
1764                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1765         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1766                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1767         else if (HAS_PCH_SPLIT(dev_priv))
1768                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1769         else
1770                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1771
1772         if (INTEL_GEN(dev_priv) >= 9)
1773                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1774         else
1775                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1776
1777         drm_dp_aux_init(&intel_dp->aux);
1778
1779         /* Failure to allocate our preferred name is not critical */
1780         intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1781                                        aux_ch_name(dig_port->aux_ch),
1782                                        port_name(encoder->port));
1783         intel_dp->aux.transfer = intel_dp_aux_transfer;
1784 }
1785
1786 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1787 {
1788         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1789
1790         return max_rate >= 540000;
1791 }
1792
1793 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1794 {
1795         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1796
1797         return max_rate >= 810000;
1798 }
1799
1800 static void
1801 intel_dp_set_clock(struct intel_encoder *encoder,
1802                    struct intel_crtc_state *pipe_config)
1803 {
1804         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1805         const struct dp_link_dpll *divisor = NULL;
1806         int i, count = 0;
1807
1808         if (IS_G4X(dev_priv)) {
1809                 divisor = g4x_dpll;
1810                 count = ARRAY_SIZE(g4x_dpll);
1811         } else if (HAS_PCH_SPLIT(dev_priv)) {
1812                 divisor = pch_dpll;
1813                 count = ARRAY_SIZE(pch_dpll);
1814         } else if (IS_CHERRYVIEW(dev_priv)) {
1815                 divisor = chv_dpll;
1816                 count = ARRAY_SIZE(chv_dpll);
1817         } else if (IS_VALLEYVIEW(dev_priv)) {
1818                 divisor = vlv_dpll;
1819                 count = ARRAY_SIZE(vlv_dpll);
1820         }
1821
1822         if (divisor && count) {
1823                 for (i = 0; i < count; i++) {
1824                         if (pipe_config->port_clock == divisor[i].clock) {
1825                                 pipe_config->dpll = divisor[i].dpll;
1826                                 pipe_config->clock_set = true;
1827                                 break;
1828                         }
1829                 }
1830         }
1831 }
1832
1833 static void snprintf_int_array(char *str, size_t len,
1834                                const int *array, int nelem)
1835 {
1836         int i;
1837
1838         str[0] = '\0';
1839
1840         for (i = 0; i < nelem; i++) {
1841                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1842                 if (r >= len)
1843                         return;
1844                 str += r;
1845                 len -= r;
1846         }
1847 }
1848
1849 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1850 {
1851         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1852         char str[128]; /* FIXME: too big for stack? */
1853
1854         if (!drm_debug_enabled(DRM_UT_KMS))
1855                 return;
1856
1857         snprintf_int_array(str, sizeof(str),
1858                            intel_dp->source_rates, intel_dp->num_source_rates);
1859         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1860
1861         snprintf_int_array(str, sizeof(str),
1862                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1863         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1864
1865         snprintf_int_array(str, sizeof(str),
1866                            intel_dp->common_rates, intel_dp->num_common_rates);
1867         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1868 }
1869
1870 int
1871 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1872 {
1873         int len;
1874
1875         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1876         if (WARN_ON(len <= 0))
1877                 return 162000;
1878
1879         return intel_dp->common_rates[len - 1];
1880 }
1881
1882 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1883 {
1884         int i = intel_dp_rate_index(intel_dp->sink_rates,
1885                                     intel_dp->num_sink_rates, rate);
1886
1887         if (WARN_ON(i < 0))
1888                 i = 0;
1889
1890         return i;
1891 }
1892
1893 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1894                            u8 *link_bw, u8 *rate_select)
1895 {
1896         /* eDP 1.4 rate select method. */
1897         if (intel_dp->use_rate_select) {
1898                 *link_bw = 0;
1899                 *rate_select =
1900                         intel_dp_rate_select(intel_dp, port_clock);
1901         } else {
1902                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1903                 *rate_select = 0;
1904         }
1905 }
1906
1907 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1908                                          const struct intel_crtc_state *pipe_config)
1909 {
1910         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1911
1912         /* On TGL, FEC is supported on all Pipes */
1913         if (INTEL_GEN(dev_priv) >= 12)
1914                 return true;
1915
1916         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1917                 return true;
1918
1919         return false;
1920 }
1921
1922 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1923                                   const struct intel_crtc_state *pipe_config)
1924 {
1925         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1926                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1927 }
1928
1929 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1930                                   const struct intel_crtc_state *crtc_state)
1931 {
1932         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1933
1934         if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1935                 return false;
1936
1937         return intel_dsc_source_support(encoder, crtc_state) &&
1938                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1939 }
1940
1941 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1942                                 struct intel_crtc_state *pipe_config)
1943 {
1944         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1945         struct intel_connector *intel_connector = intel_dp->attached_connector;
1946         int bpp, bpc;
1947
1948         bpp = pipe_config->pipe_bpp;
1949         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1950
1951         if (bpc > 0)
1952                 bpp = min(bpp, 3*bpc);
1953
1954         if (intel_dp_is_edp(intel_dp)) {
1955                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1956                 if (intel_connector->base.display_info.bpc == 0 &&
1957                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1958                         drm_dbg_kms(&dev_priv->drm,
1959                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1960                                     dev_priv->vbt.edp.bpp);
1961                         bpp = dev_priv->vbt.edp.bpp;
1962                 }
1963         }
1964
1965         return bpp;
1966 }
1967
1968 /* Adjust link config limits based on compliance test requests. */
1969 void
1970 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1971                                   struct intel_crtc_state *pipe_config,
1972                                   struct link_config_limits *limits)
1973 {
1974         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1975
1976         /* For DP Compliance we override the computed bpp for the pipe */
1977         if (intel_dp->compliance.test_data.bpc != 0) {
1978                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1979
1980                 limits->min_bpp = limits->max_bpp = bpp;
1981                 pipe_config->dither_force_disable = bpp == 6 * 3;
1982
1983                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1984         }
1985
1986         /* Use values requested by Compliance Test Request */
1987         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1988                 int index;
1989
1990                 /* Validate the compliance test data since max values
1991                  * might have changed due to link train fallback.
1992                  */
1993                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1994                                                intel_dp->compliance.test_lane_count)) {
1995                         index = intel_dp_rate_index(intel_dp->common_rates,
1996                                                     intel_dp->num_common_rates,
1997                                                     intel_dp->compliance.test_link_rate);
1998                         if (index >= 0)
1999                                 limits->min_clock = limits->max_clock = index;
2000                         limits->min_lane_count = limits->max_lane_count =
2001                                 intel_dp->compliance.test_lane_count;
2002                 }
2003         }
2004 }
2005
2006 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2007 {
2008         /*
2009          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2010          * format of the number of bytes per pixel will be half the number
2011          * of bytes of RGB pixel.
2012          */
2013         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2014                 bpp /= 2;
2015
2016         return bpp;
2017 }
2018
2019 /* Optimize link config in order: max bpp, min clock, min lanes */
2020 static int
2021 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2022                                   struct intel_crtc_state *pipe_config,
2023                                   const struct link_config_limits *limits)
2024 {
2025         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2026         int bpp, clock, lane_count;
2027         int mode_rate, link_clock, link_avail;
2028
2029         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2030                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2031
2032                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2033                                                    output_bpp);
2034
2035                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2036                         for (lane_count = limits->min_lane_count;
2037                              lane_count <= limits->max_lane_count;
2038                              lane_count <<= 1) {
2039                                 link_clock = intel_dp->common_rates[clock];
2040                                 link_avail = intel_dp_max_data_rate(link_clock,
2041                                                                     lane_count);
2042
2043                                 if (mode_rate <= link_avail) {
2044                                         pipe_config->lane_count = lane_count;
2045                                         pipe_config->pipe_bpp = bpp;
2046                                         pipe_config->port_clock = link_clock;
2047
2048                                         return 0;
2049                                 }
2050                         }
2051                 }
2052         }
2053
2054         return -EINVAL;
2055 }
2056
2057 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2058 {
2059         int i, num_bpc;
2060         u8 dsc_bpc[3] = {0};
2061
2062         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2063                                                        dsc_bpc);
2064         for (i = 0; i < num_bpc; i++) {
2065                 if (dsc_max_bpc >= dsc_bpc[i])
2066                         return dsc_bpc[i] * 3;
2067         }
2068
2069         return 0;
2070 }
2071
2072 #define DSC_SUPPORTED_VERSION_MIN               1
2073
2074 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2075                                        struct intel_crtc_state *crtc_state)
2076 {
2077         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2078         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2079         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2080         u8 line_buf_depth;
2081         int ret;
2082
2083         ret = intel_dsc_compute_params(encoder, crtc_state);
2084         if (ret)
2085                 return ret;
2086
2087         /*
2088          * Slice Height of 8 works for all currently available panels. So start
2089          * with that if pic_height is an integral multiple of 8. Eventually add
2090          * logic to try multiple slice heights.
2091          */
2092         if (vdsc_cfg->pic_height % 8 == 0)
2093                 vdsc_cfg->slice_height = 8;
2094         else if (vdsc_cfg->pic_height % 4 == 0)
2095                 vdsc_cfg->slice_height = 4;
2096         else
2097                 vdsc_cfg->slice_height = 2;
2098
2099         vdsc_cfg->dsc_version_major =
2100                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2101                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2102         vdsc_cfg->dsc_version_minor =
2103                 min(DSC_SUPPORTED_VERSION_MIN,
2104                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2105                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2106
2107         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2108                 DP_DSC_RGB;
2109
2110         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2111         if (!line_buf_depth) {
2112                 drm_dbg_kms(&i915->drm,
2113                             "DSC Sink Line Buffer Depth invalid\n");
2114                 return -EINVAL;
2115         }
2116
2117         if (vdsc_cfg->dsc_version_minor == 2)
2118                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2119                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2120         else
2121                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2122                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2123
2124         vdsc_cfg->block_pred_enable =
2125                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2126                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2127
2128         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2129 }
2130
2131 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2132                                        struct intel_crtc_state *pipe_config,
2133                                        struct drm_connector_state *conn_state,
2134                                        struct link_config_limits *limits)
2135 {
2136         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2137         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2138         const struct drm_display_mode *adjusted_mode =
2139                 &pipe_config->hw.adjusted_mode;
2140         u8 dsc_max_bpc;
2141         int pipe_bpp;
2142         int ret;
2143
2144         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2145                 intel_dp_supports_fec(intel_dp, pipe_config);
2146
2147         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2148                 return -EINVAL;
2149
2150         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2151         if (INTEL_GEN(dev_priv) >= 12)
2152                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2153         else
2154                 dsc_max_bpc = min_t(u8, 10,
2155                                     conn_state->max_requested_bpc);
2156
2157         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2158
2159         /* Min Input BPC for ICL+ is 8 */
2160         if (pipe_bpp < 8 * 3) {
2161                 drm_dbg_kms(&dev_priv->drm,
2162                             "No DSC support for less than 8bpc\n");
2163                 return -EINVAL;
2164         }
2165
2166         /*
2167          * For now enable DSC for max bpp, max link rate, max lane count.
2168          * Optimize this later for the minimum possible link rate/lane count
2169          * with DSC enabled for the requested mode.
2170          */
2171         pipe_config->pipe_bpp = pipe_bpp;
2172         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2173         pipe_config->lane_count = limits->max_lane_count;
2174
2175         if (intel_dp_is_edp(intel_dp)) {
2176                 pipe_config->dsc.compressed_bpp =
2177                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2178                               pipe_config->pipe_bpp);
2179                 pipe_config->dsc.slice_count =
2180                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2181                                                         true);
2182         } else {
2183                 u16 dsc_max_output_bpp;
2184                 u8 dsc_dp_slice_count;
2185
2186                 dsc_max_output_bpp =
2187                         intel_dp_dsc_get_output_bpp(dev_priv,
2188                                                     pipe_config->port_clock,
2189                                                     pipe_config->lane_count,
2190                                                     adjusted_mode->crtc_clock,
2191                                                     adjusted_mode->crtc_hdisplay);
2192                 dsc_dp_slice_count =
2193                         intel_dp_dsc_get_slice_count(intel_dp,
2194                                                      adjusted_mode->crtc_clock,
2195                                                      adjusted_mode->crtc_hdisplay);
2196                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2197                         drm_dbg_kms(&dev_priv->drm,
2198                                     "Compressed BPP/Slice Count not supported\n");
2199                         return -EINVAL;
2200                 }
2201                 pipe_config->dsc.compressed_bpp = min_t(u16,
2202                                                                dsc_max_output_bpp >> 4,
2203                                                                pipe_config->pipe_bpp);
2204                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2205         }
2206         /*
2207          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2208          * is greater than the maximum Cdclock and if slice count is even
2209          * then we need to use 2 VDSC instances.
2210          */
2211         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2212                 if (pipe_config->dsc.slice_count > 1) {
2213                         pipe_config->dsc.dsc_split = true;
2214                 } else {
2215                         drm_dbg_kms(&dev_priv->drm,
2216                                     "Cannot split stream to use 2 VDSC instances\n");
2217                         return -EINVAL;
2218                 }
2219         }
2220
2221         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2222         if (ret < 0) {
2223                 drm_dbg_kms(&dev_priv->drm,
2224                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2225                             "Compressed BPP = %d\n",
2226                             pipe_config->pipe_bpp,
2227                             pipe_config->dsc.compressed_bpp);
2228                 return ret;
2229         }
2230
2231         pipe_config->dsc.compression_enable = true;
2232         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2233                     "Compressed Bpp = %d Slice Count = %d\n",
2234                     pipe_config->pipe_bpp,
2235                     pipe_config->dsc.compressed_bpp,
2236                     pipe_config->dsc.slice_count);
2237
2238         return 0;
2239 }
2240
2241 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2242 {
2243         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2244                 return 6 * 3;
2245         else
2246                 return 8 * 3;
2247 }
2248
2249 static int
2250 intel_dp_compute_link_config(struct intel_encoder *encoder,
2251                              struct intel_crtc_state *pipe_config,
2252                              struct drm_connector_state *conn_state)
2253 {
2254         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2255         const struct drm_display_mode *adjusted_mode =
2256                 &pipe_config->hw.adjusted_mode;
2257         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2258         struct link_config_limits limits;
2259         int common_len;
2260         int ret;
2261
2262         common_len = intel_dp_common_len_rate_limit(intel_dp,
2263                                                     intel_dp->max_link_rate);
2264
2265         /* No common link rates between source and sink */
2266         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2267
2268         limits.min_clock = 0;
2269         limits.max_clock = common_len - 1;
2270
2271         limits.min_lane_count = 1;
2272         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2273
2274         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2275         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2276
2277         if (intel_dp_is_edp(intel_dp)) {
2278                 /*
2279                  * Use the maximum clock and number of lanes the eDP panel
2280                  * advertizes being capable of. The panels are generally
2281                  * designed to support only a single clock and lane
2282                  * configuration, and typically these values correspond to the
2283                  * native resolution of the panel.
2284                  */
2285                 limits.min_lane_count = limits.max_lane_count;
2286                 limits.min_clock = limits.max_clock;
2287         }
2288
2289         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2290
2291         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2292                     "max rate %d max bpp %d pixel clock %iKHz\n",
2293                     limits.max_lane_count,
2294                     intel_dp->common_rates[limits.max_clock],
2295                     limits.max_bpp, adjusted_mode->crtc_clock);
2296
2297         /*
2298          * Optimize for slow and wide. This is the place to add alternative
2299          * optimization policy.
2300          */
2301         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2302
2303         /* enable compression if the mode doesn't fit available BW */
2304         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2305         if (ret || intel_dp->force_dsc_en) {
2306                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2307                                                   conn_state, &limits);
2308                 if (ret < 0)
2309                         return ret;
2310         }
2311
2312         if (pipe_config->dsc.compression_enable) {
2313                 drm_dbg_kms(&i915->drm,
2314                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2315                             pipe_config->lane_count, pipe_config->port_clock,
2316                             pipe_config->pipe_bpp,
2317                             pipe_config->dsc.compressed_bpp);
2318
2319                 drm_dbg_kms(&i915->drm,
2320                             "DP link rate required %i available %i\n",
2321                             intel_dp_link_required(adjusted_mode->crtc_clock,
2322                                                    pipe_config->dsc.compressed_bpp),
2323                             intel_dp_max_data_rate(pipe_config->port_clock,
2324                                                    pipe_config->lane_count));
2325         } else {
2326                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2327                             pipe_config->lane_count, pipe_config->port_clock,
2328                             pipe_config->pipe_bpp);
2329
2330                 drm_dbg_kms(&i915->drm,
2331                             "DP link rate required %i available %i\n",
2332                             intel_dp_link_required(adjusted_mode->crtc_clock,
2333                                                    pipe_config->pipe_bpp),
2334                             intel_dp_max_data_rate(pipe_config->port_clock,
2335                                                    pipe_config->lane_count));
2336         }
2337         return 0;
2338 }
2339
2340 static int
2341 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2342                          struct drm_connector *connector,
2343                          struct intel_crtc_state *crtc_state)
2344 {
2345         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2346         const struct drm_display_info *info = &connector->display_info;
2347         const struct drm_display_mode *adjusted_mode =
2348                 &crtc_state->hw.adjusted_mode;
2349         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2350         int ret;
2351
2352         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2353             !intel_dp_get_colorimetry_status(intel_dp) ||
2354             !connector->ycbcr_420_allowed)
2355                 return 0;
2356
2357         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2358
2359         /* YCBCR 420 output conversion needs a scaler */
2360         ret = skl_update_scaler_crtc(crtc_state);
2361         if (ret) {
2362                 drm_dbg_kms(&i915->drm,
2363                             "Scaler allocation for output failed\n");
2364                 return ret;
2365         }
2366
2367         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2368
2369         return 0;
2370 }
2371
2372 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2373                                   const struct drm_connector_state *conn_state)
2374 {
2375         const struct intel_digital_connector_state *intel_conn_state =
2376                 to_intel_digital_connector_state(conn_state);
2377         const struct drm_display_mode *adjusted_mode =
2378                 &crtc_state->hw.adjusted_mode;
2379
2380         /*
2381          * Our YCbCr output is always limited range.
2382          * crtc_state->limited_color_range only applies to RGB,
2383          * and it must never be set for YCbCr or we risk setting
2384          * some conflicting bits in PIPECONF which will mess up
2385          * the colors on the monitor.
2386          */
2387         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2388                 return false;
2389
2390         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2391                 /*
2392                  * See:
2393                  * CEA-861-E - 5.1 Default Encoding Parameters
2394                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2395                  */
2396                 return crtc_state->pipe_bpp != 18 &&
2397                         drm_default_rgb_quant_range(adjusted_mode) ==
2398                         HDMI_QUANTIZATION_RANGE_LIMITED;
2399         } else {
2400                 return intel_conn_state->broadcast_rgb ==
2401                         INTEL_BROADCAST_RGB_LIMITED;
2402         }
2403 }
2404
2405 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2406                                     enum port port)
2407 {
2408         if (IS_G4X(dev_priv))
2409                 return false;
2410         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2411                 return false;
2412
2413         return true;
2414 }
2415
2416 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2417                                              const struct drm_connector_state *conn_state,
2418                                              struct drm_dp_vsc_sdp *vsc)
2419 {
2420         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2422
2423         /*
2424          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2425          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2426          * Colorimetry Format indication.
2427          */
2428         vsc->revision = 0x5;
2429         vsc->length = 0x13;
2430
2431         /* DP 1.4a spec, Table 2-120 */
2432         switch (crtc_state->output_format) {
2433         case INTEL_OUTPUT_FORMAT_YCBCR444:
2434                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2435                 break;
2436         case INTEL_OUTPUT_FORMAT_YCBCR420:
2437                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2438                 break;
2439         case INTEL_OUTPUT_FORMAT_RGB:
2440         default:
2441                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2442         }
2443
2444         switch (conn_state->colorspace) {
2445         case DRM_MODE_COLORIMETRY_BT709_YCC:
2446                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2447                 break;
2448         case DRM_MODE_COLORIMETRY_XVYCC_601:
2449                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2450                 break;
2451         case DRM_MODE_COLORIMETRY_XVYCC_709:
2452                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2453                 break;
2454         case DRM_MODE_COLORIMETRY_SYCC_601:
2455                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2456                 break;
2457         case DRM_MODE_COLORIMETRY_OPYCC_601:
2458                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2459                 break;
2460         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2461                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2462                 break;
2463         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2464                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2465                 break;
2466         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2467                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2468                 break;
2469         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2470         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2471                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2472                 break;
2473         default:
2474                 /*
2475                  * RGB->YCBCR color conversion uses the BT.709
2476                  * color space.
2477                  */
2478                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2479                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2480                 else
2481                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2482                 break;
2483         }
2484
2485         vsc->bpc = crtc_state->pipe_bpp / 3;
2486
2487         /* only RGB pixelformat supports 6 bpc */
2488         drm_WARN_ON(&dev_priv->drm,
2489                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2490
2491         /* all YCbCr are always limited range */
2492         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2493         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2494 }
2495
2496 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2497                                      struct intel_crtc_state *crtc_state,
2498                                      const struct drm_connector_state *conn_state)
2499 {
2500         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2501
2502         /* When PSR is enabled, VSC SDP is handled by PSR routine */
2503         if (intel_psr_enabled(intel_dp))
2504                 return;
2505
2506         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2507                 return;
2508
2509         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2510         vsc->sdp_type = DP_SDP_VSC;
2511         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2512                                          &crtc_state->infoframes.vsc);
2513 }
2514
2515 static void
2516 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2517                                             struct intel_crtc_state *crtc_state,
2518                                             const struct drm_connector_state *conn_state)
2519 {
2520         int ret;
2521         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2522         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2523
2524         if (!conn_state->hdr_output_metadata)
2525                 return;
2526
2527         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2528
2529         if (ret) {
2530                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2531                 return;
2532         }
2533
2534         crtc_state->infoframes.enable |=
2535                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2536 }
2537
2538 int
2539 intel_dp_compute_config(struct intel_encoder *encoder,
2540                         struct intel_crtc_state *pipe_config,
2541                         struct drm_connector_state *conn_state)
2542 {
2543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2545         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2546         struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2547         enum port port = encoder->port;
2548         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2549         struct intel_connector *intel_connector = intel_dp->attached_connector;
2550         struct intel_digital_connector_state *intel_conn_state =
2551                 to_intel_digital_connector_state(conn_state);
2552         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2553                                            DP_DPCD_QUIRK_CONSTANT_N);
2554         int ret = 0, output_bpp;
2555
2556         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2557                 pipe_config->has_pch_encoder = true;
2558
2559         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2560
2561         if (lspcon->active)
2562                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2563         else
2564                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2565                                                pipe_config);
2566
2567         if (ret)
2568                 return ret;
2569
2570         pipe_config->has_drrs = false;
2571         if (!intel_dp_port_has_audio(dev_priv, port))
2572                 pipe_config->has_audio = false;
2573         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2574                 pipe_config->has_audio = intel_dp->has_audio;
2575         else
2576                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2577
2578         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2579                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2580                                        adjusted_mode);
2581
2582                 if (INTEL_GEN(dev_priv) >= 9) {
2583                         ret = skl_update_scaler_crtc(pipe_config);
2584                         if (ret)
2585                                 return ret;
2586                 }
2587
2588                 if (HAS_GMCH(dev_priv))
2589                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2590                                                  conn_state->scaling_mode);
2591                 else
2592                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2593                                                 conn_state->scaling_mode);
2594         }
2595
2596         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2597                 return -EINVAL;
2598
2599         if (HAS_GMCH(dev_priv) &&
2600             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2601                 return -EINVAL;
2602
2603         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2604                 return -EINVAL;
2605
2606         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2607                 return -EINVAL;
2608
2609         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2610         if (ret < 0)
2611                 return ret;
2612
2613         pipe_config->limited_color_range =
2614                 intel_dp_limited_color_range(pipe_config, conn_state);
2615
2616         if (pipe_config->dsc.compression_enable)
2617                 output_bpp = pipe_config->dsc.compressed_bpp;
2618         else
2619                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2620
2621         intel_link_compute_m_n(output_bpp,
2622                                pipe_config->lane_count,
2623                                adjusted_mode->crtc_clock,
2624                                pipe_config->port_clock,
2625                                &pipe_config->dp_m_n,
2626                                constant_n, pipe_config->fec_enable);
2627
2628         if (intel_connector->panel.downclock_mode != NULL &&
2629                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2630                         pipe_config->has_drrs = true;
2631                         intel_link_compute_m_n(output_bpp,
2632                                                pipe_config->lane_count,
2633                                                intel_connector->panel.downclock_mode->clock,
2634                                                pipe_config->port_clock,
2635                                                &pipe_config->dp_m2_n2,
2636                                                constant_n, pipe_config->fec_enable);
2637         }
2638
2639         if (!HAS_DDI(dev_priv))
2640                 intel_dp_set_clock(encoder, pipe_config);
2641
2642         intel_psr_compute_config(intel_dp, pipe_config);
2643         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2644         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2645
2646         return 0;
2647 }
2648
2649 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2650                               int link_rate, u8 lane_count,
2651                               bool link_mst)
2652 {
2653         intel_dp->link_trained = false;
2654         intel_dp->link_rate = link_rate;
2655         intel_dp->lane_count = lane_count;
2656         intel_dp->link_mst = link_mst;
2657 }
2658
2659 static void intel_dp_prepare(struct intel_encoder *encoder,
2660                              const struct intel_crtc_state *pipe_config)
2661 {
2662         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2663         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2664         enum port port = encoder->port;
2665         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2666         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2667
2668         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2669                                  pipe_config->lane_count,
2670                                  intel_crtc_has_type(pipe_config,
2671                                                      INTEL_OUTPUT_DP_MST));
2672
2673         /*
2674          * There are four kinds of DP registers:
2675          *
2676          *      IBX PCH
2677          *      SNB CPU
2678          *      IVB CPU
2679          *      CPT PCH
2680          *
2681          * IBX PCH and CPU are the same for almost everything,
2682          * except that the CPU DP PLL is configured in this
2683          * register
2684          *
2685          * CPT PCH is quite different, having many bits moved
2686          * to the TRANS_DP_CTL register instead. That
2687          * configuration happens (oddly) in ilk_pch_enable
2688          */
2689
2690         /* Preserve the BIOS-computed detected bit. This is
2691          * supposed to be read-only.
2692          */
2693         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2694
2695         /* Handle DP bits in common between all three register formats */
2696         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2697         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2698
2699         /* Split out the IBX/CPU vs CPT settings */
2700
2701         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2702                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2703                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2704                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2705                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2706                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2707
2708                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2709                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2710
2711                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2712         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2713                 u32 trans_dp;
2714
2715                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2716
2717                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2718                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2719                         trans_dp |= TRANS_DP_ENH_FRAMING;
2720                 else
2721                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2722                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2723         } else {
2724                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2725                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2726
2727                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2728                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2729                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2730                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2731                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2732
2733                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2734                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2735
2736                 if (IS_CHERRYVIEW(dev_priv))
2737                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2738                 else
2739                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2740         }
2741 }
2742
2743 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2744 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2745
2746 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2747 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2748
2749 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2750 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2751
2752 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2753
2754 static void wait_panel_status(struct intel_dp *intel_dp,
2755                                        u32 mask,
2756                                        u32 value)
2757 {
2758         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2759         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2760
2761         lockdep_assert_held(&dev_priv->pps_mutex);
2762
2763         intel_pps_verify_state(intel_dp);
2764
2765         pp_stat_reg = _pp_stat_reg(intel_dp);
2766         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2767
2768         drm_dbg_kms(&dev_priv->drm,
2769                     "mask %08x value %08x status %08x control %08x\n",
2770                     mask, value,
2771                     intel_de_read(dev_priv, pp_stat_reg),
2772                     intel_de_read(dev_priv, pp_ctrl_reg));
2773
2774         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2775                                        mask, value, 5000))
2776                 drm_err(&dev_priv->drm,
2777                         "Panel status timeout: status %08x control %08x\n",
2778                         intel_de_read(dev_priv, pp_stat_reg),
2779                         intel_de_read(dev_priv, pp_ctrl_reg));
2780
2781         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2782 }
2783
2784 static void wait_panel_on(struct intel_dp *intel_dp)
2785 {
2786         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2787
2788         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2789         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2790 }
2791
2792 static void wait_panel_off(struct intel_dp *intel_dp)
2793 {
2794         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2795
2796         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2797         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2798 }
2799
2800 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2801 {
2802         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2803         ktime_t panel_power_on_time;
2804         s64 panel_power_off_duration;
2805
2806         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2807
2808         /* take the difference of currrent time and panel power off time
2809          * and then make panel wait for t11_t12 if needed. */
2810         panel_power_on_time = ktime_get_boottime();
2811         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2812
2813         /* When we disable the VDD override bit last we have to do the manual
2814          * wait. */
2815         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2816                 wait_remaining_ms_from_jiffies(jiffies,
2817                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2818
2819         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2820 }
2821
2822 static void wait_backlight_on(struct intel_dp *intel_dp)
2823 {
2824         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2825                                        intel_dp->backlight_on_delay);
2826 }
2827
2828 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2829 {
2830         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2831                                        intel_dp->backlight_off_delay);
2832 }
2833
2834 /* Read the current pp_control value, unlocking the register if it
2835  * is locked
2836  */
2837
2838 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2839 {
2840         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2841         u32 control;
2842
2843         lockdep_assert_held(&dev_priv->pps_mutex);
2844
2845         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2846         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2847                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2848                 control &= ~PANEL_UNLOCK_MASK;
2849                 control |= PANEL_UNLOCK_REGS;
2850         }
2851         return control;
2852 }
2853
2854 /*
2855  * Must be paired with edp_panel_vdd_off().
2856  * Must hold pps_mutex around the whole on/off sequence.
2857  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2858  */
2859 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2860 {
2861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2863         u32 pp;
2864         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2865         bool need_to_disable = !intel_dp->want_panel_vdd;
2866
2867         lockdep_assert_held(&dev_priv->pps_mutex);
2868
2869         if (!intel_dp_is_edp(intel_dp))
2870                 return false;
2871
2872         cancel_delayed_work(&intel_dp->panel_vdd_work);
2873         intel_dp->want_panel_vdd = true;
2874
2875         if (edp_have_panel_vdd(intel_dp))
2876                 return need_to_disable;
2877
2878         intel_display_power_get(dev_priv,
2879                                 intel_aux_power_domain(intel_dig_port));
2880
2881         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2882                     intel_dig_port->base.base.base.id,
2883                     intel_dig_port->base.base.name);
2884
2885         if (!edp_have_panel_power(intel_dp))
2886                 wait_panel_power_cycle(intel_dp);
2887
2888         pp = ilk_get_pp_control(intel_dp);
2889         pp |= EDP_FORCE_VDD;
2890
2891         pp_stat_reg = _pp_stat_reg(intel_dp);
2892         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2893
2894         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2895         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2896         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2897                     intel_de_read(dev_priv, pp_stat_reg),
2898                     intel_de_read(dev_priv, pp_ctrl_reg));
2899         /*
2900          * If the panel wasn't on, delay before accessing aux channel
2901          */
2902         if (!edp_have_panel_power(intel_dp)) {
2903                 drm_dbg_kms(&dev_priv->drm,
2904                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
2905                             intel_dig_port->base.base.base.id,
2906                             intel_dig_port->base.base.name);
2907                 msleep(intel_dp->panel_power_up_delay);
2908         }
2909
2910         return need_to_disable;
2911 }
2912
2913 /*
2914  * Must be paired with intel_edp_panel_vdd_off() or
2915  * intel_edp_panel_off().
2916  * Nested calls to these functions are not allowed since
2917  * we drop the lock. Caller must use some higher level
2918  * locking to prevent nested calls from other threads.
2919  */
2920 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2921 {
2922         intel_wakeref_t wakeref;
2923         bool vdd;
2924
2925         if (!intel_dp_is_edp(intel_dp))
2926                 return;
2927
2928         vdd = false;
2929         with_pps_lock(intel_dp, wakeref)
2930                 vdd = edp_panel_vdd_on(intel_dp);
2931         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2932                         dp_to_dig_port(intel_dp)->base.base.base.id,
2933                         dp_to_dig_port(intel_dp)->base.base.name);
2934 }
2935
2936 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2937 {
2938         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2939         struct intel_digital_port *intel_dig_port =
2940                 dp_to_dig_port(intel_dp);
2941         u32 pp;
2942         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2943
2944         lockdep_assert_held(&dev_priv->pps_mutex);
2945
2946         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2947
2948         if (!edp_have_panel_vdd(intel_dp))
2949                 return;
2950
2951         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2952                     intel_dig_port->base.base.base.id,
2953                     intel_dig_port->base.base.name);
2954
2955         pp = ilk_get_pp_control(intel_dp);
2956         pp &= ~EDP_FORCE_VDD;
2957
2958         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2959         pp_stat_reg = _pp_stat_reg(intel_dp);
2960
2961         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2962         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2963
2964         /* Make sure sequencer is idle before allowing subsequent activity */
2965         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2966                     intel_de_read(dev_priv, pp_stat_reg),
2967                     intel_de_read(dev_priv, pp_ctrl_reg));
2968
2969         if ((pp & PANEL_POWER_ON) == 0)
2970                 intel_dp->panel_power_off_time = ktime_get_boottime();
2971
2972         intel_display_power_put_unchecked(dev_priv,
2973                                           intel_aux_power_domain(intel_dig_port));
2974 }
2975
2976 static void edp_panel_vdd_work(struct work_struct *__work)
2977 {
2978         struct intel_dp *intel_dp =
2979                 container_of(to_delayed_work(__work),
2980                              struct intel_dp, panel_vdd_work);
2981         intel_wakeref_t wakeref;
2982
2983         with_pps_lock(intel_dp, wakeref) {
2984                 if (!intel_dp->want_panel_vdd)
2985                         edp_panel_vdd_off_sync(intel_dp);
2986         }
2987 }
2988
2989 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2990 {
2991         unsigned long delay;
2992
2993         /*
2994          * Queue the timer to fire a long time from now (relative to the power
2995          * down delay) to keep the panel power up across a sequence of
2996          * operations.
2997          */
2998         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2999         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3000 }
3001
3002 /*
3003  * Must be paired with edp_panel_vdd_on().
3004  * Must hold pps_mutex around the whole on/off sequence.
3005  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3006  */
3007 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3008 {
3009         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3010
3011         lockdep_assert_held(&dev_priv->pps_mutex);
3012
3013         if (!intel_dp_is_edp(intel_dp))
3014                 return;
3015
3016         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3017                         dp_to_dig_port(intel_dp)->base.base.base.id,
3018                         dp_to_dig_port(intel_dp)->base.base.name);
3019
3020         intel_dp->want_panel_vdd = false;
3021
3022         if (sync)
3023                 edp_panel_vdd_off_sync(intel_dp);
3024         else
3025                 edp_panel_vdd_schedule_off(intel_dp);
3026 }
3027
3028 static void edp_panel_on(struct intel_dp *intel_dp)
3029 {
3030         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3031         u32 pp;
3032         i915_reg_t pp_ctrl_reg;
3033
3034         lockdep_assert_held(&dev_priv->pps_mutex);
3035
3036         if (!intel_dp_is_edp(intel_dp))
3037                 return;
3038
3039         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3040                     dp_to_dig_port(intel_dp)->base.base.base.id,
3041                     dp_to_dig_port(intel_dp)->base.base.name);
3042
3043         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3044                      "[ENCODER:%d:%s] panel power already on\n",
3045                      dp_to_dig_port(intel_dp)->base.base.base.id,
3046                      dp_to_dig_port(intel_dp)->base.base.name))
3047                 return;
3048
3049         wait_panel_power_cycle(intel_dp);
3050
3051         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3052         pp = ilk_get_pp_control(intel_dp);
3053         if (IS_GEN(dev_priv, 5)) {
3054                 /* ILK workaround: disable reset around power sequence */
3055                 pp &= ~PANEL_POWER_RESET;
3056                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3057                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3058         }
3059
3060         pp |= PANEL_POWER_ON;
3061         if (!IS_GEN(dev_priv, 5))
3062                 pp |= PANEL_POWER_RESET;
3063
3064         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3065         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3066
3067         wait_panel_on(intel_dp);
3068         intel_dp->last_power_on = jiffies;
3069
3070         if (IS_GEN(dev_priv, 5)) {
3071                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3072                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3073                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3074         }
3075 }
3076
3077 void intel_edp_panel_on(struct intel_dp *intel_dp)
3078 {
3079         intel_wakeref_t wakeref;
3080
3081         if (!intel_dp_is_edp(intel_dp))
3082                 return;
3083
3084         with_pps_lock(intel_dp, wakeref)
3085                 edp_panel_on(intel_dp);
3086 }
3087
3088
3089 static void edp_panel_off(struct intel_dp *intel_dp)
3090 {
3091         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3092         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3093         u32 pp;
3094         i915_reg_t pp_ctrl_reg;
3095
3096         lockdep_assert_held(&dev_priv->pps_mutex);
3097
3098         if (!intel_dp_is_edp(intel_dp))
3099                 return;
3100
3101         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3102                     dig_port->base.base.base.id, dig_port->base.base.name);
3103
3104         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3105                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3106                  dig_port->base.base.base.id, dig_port->base.base.name);
3107
3108         pp = ilk_get_pp_control(intel_dp);
3109         /* We need to switch off panel power _and_ force vdd, for otherwise some
3110          * panels get very unhappy and cease to work. */
3111         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3112                 EDP_BLC_ENABLE);
3113
3114         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3115
3116         intel_dp->want_panel_vdd = false;
3117
3118         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3119         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3120
3121         wait_panel_off(intel_dp);
3122         intel_dp->panel_power_off_time = ktime_get_boottime();
3123
3124         /* We got a reference when we enabled the VDD. */
3125         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3126 }
3127
3128 void intel_edp_panel_off(struct intel_dp *intel_dp)
3129 {
3130         intel_wakeref_t wakeref;
3131
3132         if (!intel_dp_is_edp(intel_dp))
3133                 return;
3134
3135         with_pps_lock(intel_dp, wakeref)
3136                 edp_panel_off(intel_dp);
3137 }
3138
3139 /* Enable backlight in the panel power control. */
3140 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3141 {
3142         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3143         intel_wakeref_t wakeref;
3144
3145         /*
3146          * If we enable the backlight right away following a panel power
3147          * on, we may see slight flicker as the panel syncs with the eDP
3148          * link.  So delay a bit to make sure the image is solid before
3149          * allowing it to appear.
3150          */
3151         wait_backlight_on(intel_dp);
3152
3153         with_pps_lock(intel_dp, wakeref) {
3154                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3155                 u32 pp;
3156
3157                 pp = ilk_get_pp_control(intel_dp);
3158                 pp |= EDP_BLC_ENABLE;
3159
3160                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3161                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3162         }
3163 }
3164
3165 /* Enable backlight PWM and backlight PP control. */
3166 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3167                             const struct drm_connector_state *conn_state)
3168 {
3169         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3170         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3171
3172         if (!intel_dp_is_edp(intel_dp))
3173                 return;
3174
3175         drm_dbg_kms(&i915->drm, "\n");
3176
3177         intel_panel_enable_backlight(crtc_state, conn_state);
3178         _intel_edp_backlight_on(intel_dp);
3179 }
3180
3181 /* Disable backlight in the panel power control. */
3182 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3183 {
3184         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3185         intel_wakeref_t wakeref;
3186
3187         if (!intel_dp_is_edp(intel_dp))
3188                 return;
3189
3190         with_pps_lock(intel_dp, wakeref) {
3191                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3192                 u32 pp;
3193
3194                 pp = ilk_get_pp_control(intel_dp);
3195                 pp &= ~EDP_BLC_ENABLE;
3196
3197                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3198                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3199         }
3200
3201         intel_dp->last_backlight_off = jiffies;
3202         edp_wait_backlight_off(intel_dp);
3203 }
3204
3205 /* Disable backlight PP control and backlight PWM. */
3206 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3207 {
3208         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3209         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3210
3211         if (!intel_dp_is_edp(intel_dp))
3212                 return;
3213
3214         drm_dbg_kms(&i915->drm, "\n");
3215
3216         _intel_edp_backlight_off(intel_dp);
3217         intel_panel_disable_backlight(old_conn_state);
3218 }
3219
3220 /*
3221  * Hook for controlling the panel power control backlight through the bl_power
3222  * sysfs attribute. Take care to handle multiple calls.
3223  */
3224 static void intel_edp_backlight_power(struct intel_connector *connector,
3225                                       bool enable)
3226 {
3227         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3228         struct intel_dp *intel_dp = intel_attached_dp(connector);
3229         intel_wakeref_t wakeref;
3230         bool is_enabled;
3231
3232         is_enabled = false;
3233         with_pps_lock(intel_dp, wakeref)
3234                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3235         if (is_enabled == enable)
3236                 return;
3237
3238         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3239                     enable ? "enable" : "disable");
3240
3241         if (enable)
3242                 _intel_edp_backlight_on(intel_dp);
3243         else
3244                 _intel_edp_backlight_off(intel_dp);
3245 }
3246
3247 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3248 {
3249         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3250         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3251         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3252
3253         I915_STATE_WARN(cur_state != state,
3254                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3255                         dig_port->base.base.base.id, dig_port->base.base.name,
3256                         onoff(state), onoff(cur_state));
3257 }
3258 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3259
3260 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3261 {
3262         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3263
3264         I915_STATE_WARN(cur_state != state,
3265                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3266                         onoff(state), onoff(cur_state));
3267 }
3268 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3269 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3270
3271 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3272                            const struct intel_crtc_state *pipe_config)
3273 {
3274         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3276
3277         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3278         assert_dp_port_disabled(intel_dp);
3279         assert_edp_pll_disabled(dev_priv);
3280
3281         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3282                     pipe_config->port_clock);
3283
3284         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3285
3286         if (pipe_config->port_clock == 162000)
3287                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3288         else
3289                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3290
3291         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3292         intel_de_posting_read(dev_priv, DP_A);
3293         udelay(500);
3294
3295         /*
3296          * [DevILK] Work around required when enabling DP PLL
3297          * while a pipe is enabled going to FDI:
3298          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3299          * 2. Program DP PLL enable
3300          */
3301         if (IS_GEN(dev_priv, 5))
3302                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3303
3304         intel_dp->DP |= DP_PLL_ENABLE;
3305
3306         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3307         intel_de_posting_read(dev_priv, DP_A);
3308         udelay(200);
3309 }
3310
3311 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3312                             const struct intel_crtc_state *old_crtc_state)
3313 {
3314         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3315         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3316
3317         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3318         assert_dp_port_disabled(intel_dp);
3319         assert_edp_pll_enabled(dev_priv);
3320
3321         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3322
3323         intel_dp->DP &= ~DP_PLL_ENABLE;
3324
3325         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3326         intel_de_posting_read(dev_priv, DP_A);
3327         udelay(200);
3328 }
3329
3330 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3331 {
3332         /*
3333          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3334          * be capable of signalling downstream hpd with a long pulse.
3335          * Whether or not that means D3 is safe to use is not clear,
3336          * but let's assume so until proven otherwise.
3337          *
3338          * FIXME should really check all downstream ports...
3339          */
3340         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3341                 drm_dp_is_branch(intel_dp->dpcd) &&
3342                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3343 }
3344
3345 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3346                                            const struct intel_crtc_state *crtc_state,
3347                                            bool enable)
3348 {
3349         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3350         int ret;
3351
3352         if (!crtc_state->dsc.compression_enable)
3353                 return;
3354
3355         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3356                                  enable ? DP_DECOMPRESSION_EN : 0);
3357         if (ret < 0)
3358                 drm_dbg_kms(&i915->drm,
3359                             "Failed to %s sink decompression state\n",
3360                             enable ? "enable" : "disable");
3361 }
3362
3363 /* If the sink supports it, try to set the power state appropriately */
3364 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3365 {
3366         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3367         int ret, i;
3368
3369         /* Should have a valid DPCD by this point */
3370         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3371                 return;
3372
3373         if (mode != DRM_MODE_DPMS_ON) {
3374                 if (downstream_hpd_needs_d0(intel_dp))
3375                         return;
3376
3377                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3378                                          DP_SET_POWER_D3);
3379         } else {
3380                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3381
3382                 /*
3383                  * When turning on, we need to retry for 1ms to give the sink
3384                  * time to wake up.
3385                  */
3386                 for (i = 0; i < 3; i++) {
3387                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3388                                                  DP_SET_POWER_D0);
3389                         if (ret == 1)
3390                                 break;
3391                         msleep(1);
3392                 }
3393
3394                 if (ret == 1 && lspcon->active)
3395                         lspcon_wait_pcon_mode(lspcon);
3396         }
3397
3398         if (ret != 1)
3399                 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3400                             mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3401 }
3402
3403 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3404                                  enum port port, enum pipe *pipe)
3405 {
3406         enum pipe p;
3407
3408         for_each_pipe(dev_priv, p) {
3409                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3410
3411                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3412                         *pipe = p;
3413                         return true;
3414                 }
3415         }
3416
3417         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3418                     port_name(port));
3419
3420         /* must initialize pipe to something for the asserts */
3421         *pipe = PIPE_A;
3422
3423         return false;
3424 }
3425
3426 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3427                            i915_reg_t dp_reg, enum port port,
3428                            enum pipe *pipe)
3429 {
3430         bool ret;
3431         u32 val;
3432
3433         val = intel_de_read(dev_priv, dp_reg);
3434
3435         ret = val & DP_PORT_EN;
3436
3437         /* asserts want to know the pipe even if the port is disabled */
3438         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3439                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3440         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3441                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3442         else if (IS_CHERRYVIEW(dev_priv))
3443                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3444         else
3445                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3446
3447         return ret;
3448 }
3449
3450 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3451                                   enum pipe *pipe)
3452 {
3453         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3454         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3455         intel_wakeref_t wakeref;
3456         bool ret;
3457
3458         wakeref = intel_display_power_get_if_enabled(dev_priv,
3459                                                      encoder->power_domain);
3460         if (!wakeref)
3461                 return false;
3462
3463         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3464                                     encoder->port, pipe);
3465
3466         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3467
3468         return ret;
3469 }
3470
3471 static void intel_dp_get_config(struct intel_encoder *encoder,
3472                                 struct intel_crtc_state *pipe_config)
3473 {
3474         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3475         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3476         u32 tmp, flags = 0;
3477         enum port port = encoder->port;
3478         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3479
3480         if (encoder->type == INTEL_OUTPUT_EDP)
3481                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3482         else
3483                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3484
3485         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3486
3487         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3488
3489         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3490                 u32 trans_dp = intel_de_read(dev_priv,
3491                                              TRANS_DP_CTL(crtc->pipe));
3492
3493                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3494                         flags |= DRM_MODE_FLAG_PHSYNC;
3495                 else
3496                         flags |= DRM_MODE_FLAG_NHSYNC;
3497
3498                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3499                         flags |= DRM_MODE_FLAG_PVSYNC;
3500                 else
3501                         flags |= DRM_MODE_FLAG_NVSYNC;
3502         } else {
3503                 if (tmp & DP_SYNC_HS_HIGH)
3504                         flags |= DRM_MODE_FLAG_PHSYNC;
3505                 else
3506                         flags |= DRM_MODE_FLAG_NHSYNC;
3507
3508                 if (tmp & DP_SYNC_VS_HIGH)
3509                         flags |= DRM_MODE_FLAG_PVSYNC;
3510                 else
3511                         flags |= DRM_MODE_FLAG_NVSYNC;
3512         }
3513
3514         pipe_config->hw.adjusted_mode.flags |= flags;
3515
3516         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3517                 pipe_config->limited_color_range = true;
3518
3519         pipe_config->lane_count =
3520                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3521
3522         intel_dp_get_m_n(crtc, pipe_config);
3523
3524         if (port == PORT_A) {
3525                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3526                         pipe_config->port_clock = 162000;
3527                 else
3528                         pipe_config->port_clock = 270000;
3529         }
3530
3531         pipe_config->hw.adjusted_mode.crtc_clock =
3532                 intel_dotclock_calculate(pipe_config->port_clock,
3533                                          &pipe_config->dp_m_n);
3534
3535         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3536             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3537                 /*
3538                  * This is a big fat ugly hack.
3539                  *
3540                  * Some machines in UEFI boot mode provide us a VBT that has 18
3541                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3542                  * unknown we fail to light up. Yet the same BIOS boots up with
3543                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3544                  * max, not what it tells us to use.
3545                  *
3546                  * Note: This will still be broken if the eDP panel is not lit
3547                  * up by the BIOS, and thus we can't get the mode at module
3548                  * load.
3549                  */
3550                 drm_dbg_kms(&dev_priv->drm,
3551                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3552                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3553                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3554         }
3555 }
3556
3557 static void intel_disable_dp(struct intel_atomic_state *state,
3558                              struct intel_encoder *encoder,
3559                              const struct intel_crtc_state *old_crtc_state,
3560                              const struct drm_connector_state *old_conn_state)
3561 {
3562         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3563
3564         intel_dp->link_trained = false;
3565
3566         if (old_crtc_state->has_audio)
3567                 intel_audio_codec_disable(encoder,
3568                                           old_crtc_state, old_conn_state);
3569
3570         /* Make sure the panel is off before trying to change the mode. But also
3571          * ensure that we have vdd while we switch off the panel. */
3572         intel_edp_panel_vdd_on(intel_dp);
3573         intel_edp_backlight_off(old_conn_state);
3574         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3575         intel_edp_panel_off(intel_dp);
3576 }
3577
3578 static void g4x_disable_dp(struct intel_atomic_state *state,
3579                            struct intel_encoder *encoder,
3580                            const struct intel_crtc_state *old_crtc_state,
3581                            const struct drm_connector_state *old_conn_state)
3582 {
3583         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3584 }
3585
3586 static void vlv_disable_dp(struct intel_atomic_state *state,
3587                            struct intel_encoder *encoder,
3588                            const struct intel_crtc_state *old_crtc_state,
3589                            const struct drm_connector_state *old_conn_state)
3590 {
3591         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3592 }
3593
3594 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3595                                 struct intel_encoder *encoder,
3596                                 const struct intel_crtc_state *old_crtc_state,
3597                                 const struct drm_connector_state *old_conn_state)
3598 {
3599         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3600         enum port port = encoder->port;
3601
3602         /*
3603          * Bspec does not list a specific disable sequence for g4x DP.
3604          * Follow the ilk+ sequence (disable pipe before the port) for
3605          * g4x DP as it does not suffer from underruns like the normal
3606          * g4x modeset sequence (disable pipe after the port).
3607          */
3608         intel_dp_link_down(encoder, old_crtc_state);
3609
3610         /* Only ilk+ has port A */
3611         if (port == PORT_A)
3612                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3613 }
3614
3615 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3616                                 struct intel_encoder *encoder,
3617                                 const struct intel_crtc_state *old_crtc_state,
3618                                 const struct drm_connector_state *old_conn_state)
3619 {
3620         intel_dp_link_down(encoder, old_crtc_state);
3621 }
3622
3623 static void chv_post_disable_dp(struct intel_atomic_state *state,
3624                                 struct intel_encoder *encoder,
3625                                 const struct intel_crtc_state *old_crtc_state,
3626                                 const struct drm_connector_state *old_conn_state)
3627 {
3628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3629
3630         intel_dp_link_down(encoder, old_crtc_state);
3631
3632         vlv_dpio_get(dev_priv);
3633
3634         /* Assert data lane reset */
3635         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3636
3637         vlv_dpio_put(dev_priv);
3638 }
3639
3640 static void
3641 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3642                          u32 *DP,
3643                          u8 dp_train_pat)
3644 {
3645         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3646         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3647         enum port port = intel_dig_port->base.port;
3648         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3649
3650         if (dp_train_pat & train_pat_mask)
3651                 drm_dbg_kms(&dev_priv->drm,
3652                             "Using DP training pattern TPS%d\n",
3653                             dp_train_pat & train_pat_mask);
3654
3655         if (HAS_DDI(dev_priv)) {
3656                 u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3657
3658                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3659                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3660                 else
3661                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3662
3663                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3664                 switch (dp_train_pat & train_pat_mask) {
3665                 case DP_TRAINING_PATTERN_DISABLE:
3666                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3667
3668                         break;
3669                 case DP_TRAINING_PATTERN_1:
3670                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3671                         break;
3672                 case DP_TRAINING_PATTERN_2:
3673                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3674                         break;
3675                 case DP_TRAINING_PATTERN_3:
3676                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3677                         break;
3678                 case DP_TRAINING_PATTERN_4:
3679                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3680                         break;
3681                 }
3682                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3683
3684         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3685                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3686                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3687
3688                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3689                 case DP_TRAINING_PATTERN_DISABLE:
3690                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3691                         break;
3692                 case DP_TRAINING_PATTERN_1:
3693                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3694                         break;
3695                 case DP_TRAINING_PATTERN_2:
3696                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3697                         break;
3698                 case DP_TRAINING_PATTERN_3:
3699                         drm_dbg_kms(&dev_priv->drm,
3700                                     "TPS3 not supported, using TPS2 instead\n");
3701                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3702                         break;
3703                 }
3704
3705         } else {
3706                 *DP &= ~DP_LINK_TRAIN_MASK;
3707
3708                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3709                 case DP_TRAINING_PATTERN_DISABLE:
3710                         *DP |= DP_LINK_TRAIN_OFF;
3711                         break;
3712                 case DP_TRAINING_PATTERN_1:
3713                         *DP |= DP_LINK_TRAIN_PAT_1;
3714                         break;
3715                 case DP_TRAINING_PATTERN_2:
3716                         *DP |= DP_LINK_TRAIN_PAT_2;
3717                         break;
3718                 case DP_TRAINING_PATTERN_3:
3719                         drm_dbg_kms(&dev_priv->drm,
3720                                     "TPS3 not supported, using TPS2 instead\n");
3721                         *DP |= DP_LINK_TRAIN_PAT_2;
3722                         break;
3723                 }
3724         }
3725 }
3726
3727 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3728                                  const struct intel_crtc_state *old_crtc_state)
3729 {
3730         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3731
3732         /* enable with pattern 1 (as per spec) */
3733
3734         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3735
3736         /*
3737          * Magic for VLV/CHV. We _must_ first set up the register
3738          * without actually enabling the port, and then do another
3739          * write to enable the port. Otherwise link training will
3740          * fail when the power sequencer is freshly used for this port.
3741          */
3742         intel_dp->DP |= DP_PORT_EN;
3743         if (old_crtc_state->has_audio)
3744                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3745
3746         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3747         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3748 }
3749
3750 static void intel_enable_dp(struct intel_atomic_state *state,
3751                             struct intel_encoder *encoder,
3752                             const struct intel_crtc_state *pipe_config,
3753                             const struct drm_connector_state *conn_state)
3754 {
3755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3756         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3757         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3758         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3759         enum pipe pipe = crtc->pipe;
3760         intel_wakeref_t wakeref;
3761
3762         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3763                 return;
3764
3765         with_pps_lock(intel_dp, wakeref) {
3766                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3767                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3768
3769                 intel_dp_enable_port(intel_dp, pipe_config);
3770
3771                 edp_panel_vdd_on(intel_dp);
3772                 edp_panel_on(intel_dp);
3773                 edp_panel_vdd_off(intel_dp, true);
3774         }
3775
3776         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3777                 unsigned int lane_mask = 0x0;
3778
3779                 if (IS_CHERRYVIEW(dev_priv))
3780                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3781
3782                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3783                                     lane_mask);
3784         }
3785
3786         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3787         intel_dp_start_link_train(intel_dp);
3788         intel_dp_stop_link_train(intel_dp);
3789
3790         if (pipe_config->has_audio) {
3791                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3792                         pipe_name(pipe));
3793                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3794         }
3795 }
3796
3797 static void g4x_enable_dp(struct intel_atomic_state *state,
3798                           struct intel_encoder *encoder,
3799                           const struct intel_crtc_state *pipe_config,
3800                           const struct drm_connector_state *conn_state)
3801 {
3802         intel_enable_dp(state, encoder, pipe_config, conn_state);
3803         intel_edp_backlight_on(pipe_config, conn_state);
3804 }
3805
3806 static void vlv_enable_dp(struct intel_atomic_state *state,
3807                           struct intel_encoder *encoder,
3808                           const struct intel_crtc_state *pipe_config,
3809                           const struct drm_connector_state *conn_state)
3810 {
3811         intel_edp_backlight_on(pipe_config, conn_state);
3812 }
3813
3814 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3815                               struct intel_encoder *encoder,
3816                               const struct intel_crtc_state *pipe_config,
3817                               const struct drm_connector_state *conn_state)
3818 {
3819         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3820         enum port port = encoder->port;
3821
3822         intel_dp_prepare(encoder, pipe_config);
3823
3824         /* Only ilk+ has port A */
3825         if (port == PORT_A)
3826                 ilk_edp_pll_on(intel_dp, pipe_config);
3827 }
3828
3829 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3830 {
3831         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3832         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3833         enum pipe pipe = intel_dp->pps_pipe;
3834         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3835
3836         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3837
3838         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3839                 return;
3840
3841         edp_panel_vdd_off_sync(intel_dp);
3842
3843         /*
3844          * VLV seems to get confused when multiple power sequencers
3845          * have the same port selected (even if only one has power/vdd
3846          * enabled). The failure manifests as vlv_wait_port_ready() failing
3847          * CHV on the other hand doesn't seem to mind having the same port
3848          * selected in multiple power sequencers, but let's clear the
3849          * port select always when logically disconnecting a power sequencer
3850          * from a port.
3851          */
3852         drm_dbg_kms(&dev_priv->drm,
3853                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3854                     pipe_name(pipe), intel_dig_port->base.base.base.id,
3855                     intel_dig_port->base.base.name);
3856         intel_de_write(dev_priv, pp_on_reg, 0);
3857         intel_de_posting_read(dev_priv, pp_on_reg);
3858
3859         intel_dp->pps_pipe = INVALID_PIPE;
3860 }
3861
3862 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3863                                       enum pipe pipe)
3864 {
3865         struct intel_encoder *encoder;
3866
3867         lockdep_assert_held(&dev_priv->pps_mutex);
3868
3869         for_each_intel_dp(&dev_priv->drm, encoder) {
3870                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3871
3872                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3873                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3874                          pipe_name(pipe), encoder->base.base.id,
3875                          encoder->base.name);
3876
3877                 if (intel_dp->pps_pipe != pipe)
3878                         continue;
3879
3880                 drm_dbg_kms(&dev_priv->drm,
3881                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3882                             pipe_name(pipe), encoder->base.base.id,
3883                             encoder->base.name);
3884
3885                 /* make sure vdd is off before we steal it */
3886                 vlv_detach_power_sequencer(intel_dp);
3887         }
3888 }
3889
3890 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3891                                            const struct intel_crtc_state *crtc_state)
3892 {
3893         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3894         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3895         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3896
3897         lockdep_assert_held(&dev_priv->pps_mutex);
3898
3899         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3900
3901         if (intel_dp->pps_pipe != INVALID_PIPE &&
3902             intel_dp->pps_pipe != crtc->pipe) {
3903                 /*
3904                  * If another power sequencer was being used on this
3905                  * port previously make sure to turn off vdd there while
3906                  * we still have control of it.
3907                  */
3908                 vlv_detach_power_sequencer(intel_dp);
3909         }
3910
3911         /*
3912          * We may be stealing the power
3913          * sequencer from another port.
3914          */
3915         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3916
3917         intel_dp->active_pipe = crtc->pipe;
3918
3919         if (!intel_dp_is_edp(intel_dp))
3920                 return;
3921
3922         /* now it's all ours */
3923         intel_dp->pps_pipe = crtc->pipe;
3924
3925         drm_dbg_kms(&dev_priv->drm,
3926                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3927                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3928                     encoder->base.name);
3929
3930         /* init power sequencer on this pipe and port */
3931         intel_dp_init_panel_power_sequencer(intel_dp);
3932         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3933 }
3934
3935 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3936                               struct intel_encoder *encoder,
3937                               const struct intel_crtc_state *pipe_config,
3938                               const struct drm_connector_state *conn_state)
3939 {
3940         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3941
3942         intel_enable_dp(state, encoder, pipe_config, conn_state);
3943 }
3944
3945 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3946                                   struct intel_encoder *encoder,
3947                                   const struct intel_crtc_state *pipe_config,
3948                                   const struct drm_connector_state *conn_state)
3949 {
3950         intel_dp_prepare(encoder, pipe_config);
3951
3952         vlv_phy_pre_pll_enable(encoder, pipe_config);
3953 }
3954
3955 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3956                               struct intel_encoder *encoder,
3957                               const struct intel_crtc_state *pipe_config,
3958                               const struct drm_connector_state *conn_state)
3959 {
3960         chv_phy_pre_encoder_enable(encoder, pipe_config);
3961
3962         intel_enable_dp(state, encoder, pipe_config, conn_state);
3963
3964         /* Second common lane will stay alive on its own now */
3965         chv_phy_release_cl2_override(encoder);
3966 }
3967
3968 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3969                                   struct intel_encoder *encoder,
3970                                   const struct intel_crtc_state *pipe_config,
3971                                   const struct drm_connector_state *conn_state)
3972 {
3973         intel_dp_prepare(encoder, pipe_config);
3974
3975         chv_phy_pre_pll_enable(encoder, pipe_config);
3976 }
3977
3978 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3979                                     struct intel_encoder *encoder,
3980                                     const struct intel_crtc_state *old_crtc_state,
3981                                     const struct drm_connector_state *old_conn_state)
3982 {
3983         chv_phy_post_pll_disable(encoder, old_crtc_state);
3984 }
3985
3986 /*
3987  * Fetch AUX CH registers 0x202 - 0x207 which contain
3988  * link status information
3989  */
3990 bool
3991 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3992 {
3993         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3994                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3995 }
3996
3997 /* These are source-specific values. */
3998 u8
3999 intel_dp_voltage_max(struct intel_dp *intel_dp)
4000 {
4001         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4002         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4003         enum port port = encoder->port;
4004
4005         if (HAS_DDI(dev_priv))
4006                 return intel_ddi_dp_voltage_max(encoder);
4007         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4008                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4009         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
4010                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4011         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
4012                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4013         else
4014                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4015 }
4016
4017 u8
4018 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4019 {
4020         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4021         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4022         enum port port = encoder->port;
4023
4024         if (HAS_DDI(dev_priv)) {
4025                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4026         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4027                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4029                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4030                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4031                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4032                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4033                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4034                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4035                 default:
4036                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4037                 }
4038         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4039                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4040                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4041                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4042                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4043                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4044                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4045                 default:
4046                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4047                 }
4048         } else {
4049                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4051                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4052                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4053                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4054                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4055                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4056                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4057                 default:
4058                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4059                 }
4060         }
4061 }
4062
4063 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
4064 {
4065         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4066         unsigned long demph_reg_value, preemph_reg_value,
4067                 uniqtranscale_reg_value;
4068         u8 train_set = intel_dp->train_set[0];
4069
4070         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4071         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4072                 preemph_reg_value = 0x0004000;
4073                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4074                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4075                         demph_reg_value = 0x2B405555;
4076                         uniqtranscale_reg_value = 0x552AB83A;
4077                         break;
4078                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4079                         demph_reg_value = 0x2B404040;
4080                         uniqtranscale_reg_value = 0x5548B83A;
4081                         break;
4082                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4083                         demph_reg_value = 0x2B245555;
4084                         uniqtranscale_reg_value = 0x5560B83A;
4085                         break;
4086                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4087                         demph_reg_value = 0x2B405555;
4088                         uniqtranscale_reg_value = 0x5598DA3A;
4089                         break;
4090                 default:
4091                         return 0;
4092                 }
4093                 break;
4094         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4095                 preemph_reg_value = 0x0002000;
4096                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4097                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4098                         demph_reg_value = 0x2B404040;
4099                         uniqtranscale_reg_value = 0x5552B83A;
4100                         break;
4101                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4102                         demph_reg_value = 0x2B404848;
4103                         uniqtranscale_reg_value = 0x5580B83A;
4104                         break;
4105                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4106                         demph_reg_value = 0x2B404040;
4107                         uniqtranscale_reg_value = 0x55ADDA3A;
4108                         break;
4109                 default:
4110                         return 0;
4111                 }
4112                 break;
4113         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4114                 preemph_reg_value = 0x0000000;
4115                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4116                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4117                         demph_reg_value = 0x2B305555;
4118                         uniqtranscale_reg_value = 0x5570B83A;
4119                         break;
4120                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4121                         demph_reg_value = 0x2B2B4040;
4122                         uniqtranscale_reg_value = 0x55ADDA3A;
4123                         break;
4124                 default:
4125                         return 0;
4126                 }
4127                 break;
4128         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4129                 preemph_reg_value = 0x0006000;
4130                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4132                         demph_reg_value = 0x1B405555;
4133                         uniqtranscale_reg_value = 0x55ADDA3A;
4134                         break;
4135                 default:
4136                         return 0;
4137                 }
4138                 break;
4139         default:
4140                 return 0;
4141         }
4142
4143         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4144                                  uniqtranscale_reg_value, 0);
4145
4146         return 0;
4147 }
4148
4149 static u32 chv_signal_levels(struct intel_dp *intel_dp)
4150 {
4151         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4152         u32 deemph_reg_value, margin_reg_value;
4153         bool uniq_trans_scale = false;
4154         u8 train_set = intel_dp->train_set[0];
4155
4156         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4157         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4158                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4159                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4160                         deemph_reg_value = 128;
4161                         margin_reg_value = 52;
4162                         break;
4163                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4164                         deemph_reg_value = 128;
4165                         margin_reg_value = 77;
4166                         break;
4167                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4168                         deemph_reg_value = 128;
4169                         margin_reg_value = 102;
4170                         break;
4171                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4172                         deemph_reg_value = 128;
4173                         margin_reg_value = 154;
4174                         uniq_trans_scale = true;
4175                         break;
4176                 default:
4177                         return 0;
4178                 }
4179                 break;
4180         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4181                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4183                         deemph_reg_value = 85;
4184                         margin_reg_value = 78;
4185                         break;
4186                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4187                         deemph_reg_value = 85;
4188                         margin_reg_value = 116;
4189                         break;
4190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4191                         deemph_reg_value = 85;
4192                         margin_reg_value = 154;
4193                         break;
4194                 default:
4195                         return 0;
4196                 }
4197                 break;
4198         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4199                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4201                         deemph_reg_value = 64;
4202                         margin_reg_value = 104;
4203                         break;
4204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4205                         deemph_reg_value = 64;
4206                         margin_reg_value = 154;
4207                         break;
4208                 default:
4209                         return 0;
4210                 }
4211                 break;
4212         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4213                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4214                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4215                         deemph_reg_value = 43;
4216                         margin_reg_value = 154;
4217                         break;
4218                 default:
4219                         return 0;
4220                 }
4221                 break;
4222         default:
4223                 return 0;
4224         }
4225
4226         chv_set_phy_signal_level(encoder, deemph_reg_value,
4227                                  margin_reg_value, uniq_trans_scale);
4228
4229         return 0;
4230 }
4231
4232 static u32
4233 g4x_signal_levels(u8 train_set)
4234 {
4235         u32 signal_levels = 0;
4236
4237         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4238         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4239         default:
4240                 signal_levels |= DP_VOLTAGE_0_4;
4241                 break;
4242         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4243                 signal_levels |= DP_VOLTAGE_0_6;
4244                 break;
4245         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4246                 signal_levels |= DP_VOLTAGE_0_8;
4247                 break;
4248         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4249                 signal_levels |= DP_VOLTAGE_1_2;
4250                 break;
4251         }
4252         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4253         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4254         default:
4255                 signal_levels |= DP_PRE_EMPHASIS_0;
4256                 break;
4257         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4258                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4259                 break;
4260         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4261                 signal_levels |= DP_PRE_EMPHASIS_6;
4262                 break;
4263         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4264                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4265                 break;
4266         }
4267         return signal_levels;
4268 }
4269
4270 /* SNB CPU eDP voltage swing and pre-emphasis control */
4271 static u32
4272 snb_cpu_edp_signal_levels(u8 train_set)
4273 {
4274         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4275                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4276         switch (signal_levels) {
4277         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4278         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4279                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4280         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4281                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4282         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4283         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4284                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4285         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4286         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4287                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4288         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4289         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4290                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4291         default:
4292                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4293                               "0x%x\n", signal_levels);
4294                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4295         }
4296 }
4297
4298 /* IVB CPU eDP voltage swing and pre-emphasis control */
4299 static u32
4300 ivb_cpu_edp_signal_levels(u8 train_set)
4301 {
4302         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4303                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4304         switch (signal_levels) {
4305         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4306                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4307         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4308                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4309         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4310                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4311
4312         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4313                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4314         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4315                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4316
4317         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4318                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4319         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4320                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4321
4322         default:
4323                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4324                               "0x%x\n", signal_levels);
4325                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4326         }
4327 }
4328
4329 void
4330 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4331 {
4332         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4333         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4334         enum port port = intel_dig_port->base.port;
4335         u32 signal_levels, mask = 0;
4336         u8 train_set = intel_dp->train_set[0];
4337
4338         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4339                 signal_levels = bxt_signal_levels(intel_dp);
4340         } else if (HAS_DDI(dev_priv)) {
4341                 signal_levels = ddi_signal_levels(intel_dp);
4342                 mask = DDI_BUF_EMP_MASK;
4343         } else if (IS_CHERRYVIEW(dev_priv)) {
4344                 signal_levels = chv_signal_levels(intel_dp);
4345         } else if (IS_VALLEYVIEW(dev_priv)) {
4346                 signal_levels = vlv_signal_levels(intel_dp);
4347         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4348                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4349                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4350         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4351                 signal_levels = snb_cpu_edp_signal_levels(train_set);
4352                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4353         } else {
4354                 signal_levels = g4x_signal_levels(train_set);
4355                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4356         }
4357
4358         if (mask)
4359                 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4360                             signal_levels);
4361
4362         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4363                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4364                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4365         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4366                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4367                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4368                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4369                     " (max)" : "");
4370
4371         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4372
4373         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4374         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4375 }
4376
4377 void
4378 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4379                                        u8 dp_train_pat)
4380 {
4381         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4382         struct drm_i915_private *dev_priv =
4383                 to_i915(intel_dig_port->base.base.dev);
4384
4385         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4386
4387         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4388         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4389 }
4390
4391 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4392 {
4393         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4394         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4395         enum port port = intel_dig_port->base.port;
4396         u32 val;
4397
4398         if (!HAS_DDI(dev_priv))
4399                 return;
4400
4401         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4402         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4403         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4404         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4405
4406         /*
4407          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4408          * reason we need to set idle transmission mode is to work around a HW
4409          * issue where we enable the pipe while not in idle link-training mode.
4410          * In this case there is requirement to wait for a minimum number of
4411          * idle patterns to be sent.
4412          */
4413         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4414                 return;
4415
4416         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4417                                   DP_TP_STATUS_IDLE_DONE, 1))
4418                 drm_err(&dev_priv->drm,
4419                         "Timed out waiting for DP idle patterns\n");
4420 }
4421
4422 static void
4423 intel_dp_link_down(struct intel_encoder *encoder,
4424                    const struct intel_crtc_state *old_crtc_state)
4425 {
4426         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4427         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4428         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4429         enum port port = encoder->port;
4430         u32 DP = intel_dp->DP;
4431
4432         if (drm_WARN_ON(&dev_priv->drm,
4433                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4434                          DP_PORT_EN) == 0))
4435                 return;
4436
4437         drm_dbg_kms(&dev_priv->drm, "\n");
4438
4439         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4440             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4441                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4442                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4443         } else {
4444                 DP &= ~DP_LINK_TRAIN_MASK;
4445                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4446         }
4447         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4448         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4449
4450         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4451         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4452         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4453
4454         /*
4455          * HW workaround for IBX, we need to move the port
4456          * to transcoder A after disabling it to allow the
4457          * matching HDMI port to be enabled on transcoder A.
4458          */
4459         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4460                 /*
4461                  * We get CPU/PCH FIFO underruns on the other pipe when
4462                  * doing the workaround. Sweep them under the rug.
4463                  */
4464                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4465                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4466
4467                 /* always enable with pattern 1 (as per spec) */
4468                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4469                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4470                         DP_LINK_TRAIN_PAT_1;
4471                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4472                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4473
4474                 DP &= ~DP_PORT_EN;
4475                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4476                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4477
4478                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4479                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4480                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4481         }
4482
4483         msleep(intel_dp->panel_power_down_delay);
4484
4485         intel_dp->DP = DP;
4486
4487         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4488                 intel_wakeref_t wakeref;
4489
4490                 with_pps_lock(intel_dp, wakeref)
4491                         intel_dp->active_pipe = INVALID_PIPE;
4492         }
4493 }
4494
4495 static void
4496 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4497 {
4498         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4499         u8 dpcd_ext[6];
4500
4501         /*
4502          * Prior to DP1.3 the bit represented by
4503          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4504          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4505          * the true capability of the panel. The only way to check is to
4506          * then compare 0000h and 2200h.
4507          */
4508         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4509               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4510                 return;
4511
4512         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4513                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4514                 drm_err(&i915->drm,
4515                         "DPCD failed read at extended capabilities\n");
4516                 return;
4517         }
4518
4519         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4520                 drm_dbg_kms(&i915->drm,
4521                             "DPCD extended DPCD rev less than base DPCD rev\n");
4522                 return;
4523         }
4524
4525         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4526                 return;
4527
4528         drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4529                     (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4530
4531         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4532 }
4533
4534 bool
4535 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4536 {
4537         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4538
4539         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4540                              sizeof(intel_dp->dpcd)) < 0)
4541                 return false; /* aux transfer failed */
4542
4543         intel_dp_extended_receiver_capabilities(intel_dp);
4544
4545         drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4546                     intel_dp->dpcd);
4547
4548         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4549 }
4550
4551 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4552 {
4553         u8 dprx = 0;
4554
4555         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4556                               &dprx) != 1)
4557                 return false;
4558         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4559 }
4560
4561 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4562 {
4563         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4564
4565         /*
4566          * Clear the cached register set to avoid using stale values
4567          * for the sinks that do not support DSC.
4568          */
4569         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4570
4571         /* Clear fec_capable to avoid using stale values */
4572         intel_dp->fec_capable = 0;
4573
4574         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4575         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4576             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4577                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4578                                      intel_dp->dsc_dpcd,
4579                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4580                         drm_err(&i915->drm,
4581                                 "Failed to read DPCD register 0x%x\n",
4582                                 DP_DSC_SUPPORT);
4583
4584                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4585                             (int)sizeof(intel_dp->dsc_dpcd),
4586                             intel_dp->dsc_dpcd);
4587
4588                 /* FEC is supported only on DP 1.4 */
4589                 if (!intel_dp_is_edp(intel_dp) &&
4590                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4591                                       &intel_dp->fec_capable) < 0)
4592                         drm_err(&i915->drm,
4593                                 "Failed to read FEC DPCD register\n");
4594
4595                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4596                             intel_dp->fec_capable);
4597         }
4598 }
4599
4600 static bool
4601 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4602 {
4603         struct drm_i915_private *dev_priv =
4604                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4605
4606         /* this function is meant to be called only once */
4607         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4608
4609         if (!intel_dp_read_dpcd(intel_dp))
4610                 return false;
4611
4612         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4613                          drm_dp_is_branch(intel_dp->dpcd));
4614
4615         /*
4616          * Read the eDP display control registers.
4617          *
4618          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4619          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4620          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4621          * method). The display control registers should read zero if they're
4622          * not supported anyway.
4623          */
4624         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4625                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4626                              sizeof(intel_dp->edp_dpcd))
4627                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4628                             (int)sizeof(intel_dp->edp_dpcd),
4629                             intel_dp->edp_dpcd);
4630
4631         /*
4632          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4633          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4634          */
4635         intel_psr_init_dpcd(intel_dp);
4636
4637         /* Read the eDP 1.4+ supported link rates. */
4638         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4639                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4640                 int i;
4641
4642                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4643                                 sink_rates, sizeof(sink_rates));
4644
4645                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4646                         int val = le16_to_cpu(sink_rates[i]);
4647
4648                         if (val == 0)
4649                                 break;
4650
4651                         /* Value read multiplied by 200kHz gives the per-lane
4652                          * link rate in kHz. The source rates are, however,
4653                          * stored in terms of LS_Clk kHz. The full conversion
4654                          * back to symbols is
4655                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4656                          */
4657                         intel_dp->sink_rates[i] = (val * 200) / 10;
4658                 }
4659                 intel_dp->num_sink_rates = i;
4660         }
4661
4662         /*
4663          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4664          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4665          */
4666         if (intel_dp->num_sink_rates)
4667                 intel_dp->use_rate_select = true;
4668         else
4669                 intel_dp_set_sink_rates(intel_dp);
4670
4671         intel_dp_set_common_rates(intel_dp);
4672
4673         /* Read the eDP DSC DPCD registers */
4674         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4675                 intel_dp_get_dsc_sink_cap(intel_dp);
4676
4677         return true;
4678 }
4679
4680
4681 static bool
4682 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4683 {
4684         if (!intel_dp_read_dpcd(intel_dp))
4685                 return false;
4686
4687         /*
4688          * Don't clobber cached eDP rates. Also skip re-reading
4689          * the OUI/ID since we know it won't change.
4690          */
4691         if (!intel_dp_is_edp(intel_dp)) {
4692                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4693                                  drm_dp_is_branch(intel_dp->dpcd));
4694
4695                 intel_dp_set_sink_rates(intel_dp);
4696                 intel_dp_set_common_rates(intel_dp);
4697         }
4698
4699         /*
4700          * Some eDP panels do not set a valid value for sink count, that is why
4701          * it don't care about read it here and in intel_edp_init_dpcd().
4702          */
4703         if (!intel_dp_is_edp(intel_dp) &&
4704             !drm_dp_has_quirk(&intel_dp->desc, 0,
4705                               DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4706                 u8 count;
4707                 ssize_t r;
4708
4709                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4710                 if (r < 1)
4711                         return false;
4712
4713                 /*
4714                  * Sink count can change between short pulse hpd hence
4715                  * a member variable in intel_dp will track any changes
4716                  * between short pulse interrupts.
4717                  */
4718                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4719
4720                 /*
4721                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4722                  * a dongle is present but no display. Unless we require to know
4723                  * if a dongle is present or not, we don't need to update
4724                  * downstream port information. So, an early return here saves
4725                  * time from performing other operations which are not required.
4726                  */
4727                 if (!intel_dp->sink_count)
4728                         return false;
4729         }
4730
4731         if (!drm_dp_is_branch(intel_dp->dpcd))
4732                 return true; /* native DP sink */
4733
4734         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4735                 return true; /* no per-port downstream info */
4736
4737         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4738                              intel_dp->downstream_ports,
4739                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4740                 return false; /* downstream port status fetch failed */
4741
4742         return true;
4743 }
4744
4745 static bool
4746 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4747 {
4748         u8 mstm_cap;
4749
4750         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4751                 return false;
4752
4753         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4754                 return false;
4755
4756         return mstm_cap & DP_MST_CAP;
4757 }
4758
4759 static bool
4760 intel_dp_can_mst(struct intel_dp *intel_dp)
4761 {
4762         return i915_modparams.enable_dp_mst &&
4763                 intel_dp->can_mst &&
4764                 intel_dp_sink_can_mst(intel_dp);
4765 }
4766
4767 static void
4768 intel_dp_configure_mst(struct intel_dp *intel_dp)
4769 {
4770         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4771         struct intel_encoder *encoder =
4772                 &dp_to_dig_port(intel_dp)->base;
4773         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4774
4775         drm_dbg_kms(&i915->drm,
4776                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4777                     encoder->base.base.id, encoder->base.name,
4778                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
4779                     yesno(i915_modparams.enable_dp_mst));
4780
4781         if (!intel_dp->can_mst)
4782                 return;
4783
4784         intel_dp->is_mst = sink_can_mst &&
4785                 i915_modparams.enable_dp_mst;
4786
4787         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4788                                         intel_dp->is_mst);
4789 }
4790
4791 static bool
4792 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4793 {
4794         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4795                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4796                 DP_DPRX_ESI_LEN;
4797 }
4798
4799 bool
4800 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4801                        const struct drm_connector_state *conn_state)
4802 {
4803         /*
4804          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4805          * of Color Encoding Format and Content Color Gamut], in order to
4806          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4807          */
4808         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4809                 return true;
4810
4811         switch (conn_state->colorspace) {
4812         case DRM_MODE_COLORIMETRY_SYCC_601:
4813         case DRM_MODE_COLORIMETRY_OPYCC_601:
4814         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4815         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4816         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4817                 return true;
4818         default:
4819                 break;
4820         }
4821
4822         return false;
4823 }
4824
4825 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4826                                      struct dp_sdp *sdp, size_t size)
4827 {
4828         size_t length = sizeof(struct dp_sdp);
4829
4830         if (size < length)
4831                 return -ENOSPC;
4832
4833         memset(sdp, 0, size);
4834
4835         /*
4836          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4837          * VSC SDP Header Bytes
4838          */
4839         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4840         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4841         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4842         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4843
4844         /* VSC SDP Payload for DB16 through DB18 */
4845         /* Pixel Encoding and Colorimetry Formats  */
4846         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4847         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4848
4849         switch (vsc->bpc) {
4850         case 6:
4851                 /* 6bpc: 0x0 */
4852                 break;
4853         case 8:
4854                 sdp->db[17] = 0x1; /* DB17[3:0] */
4855                 break;
4856         case 10:
4857                 sdp->db[17] = 0x2;
4858                 break;
4859         case 12:
4860                 sdp->db[17] = 0x3;
4861                 break;
4862         case 16:
4863                 sdp->db[17] = 0x4;
4864                 break;
4865         default:
4866                 MISSING_CASE(vsc->bpc);
4867                 break;
4868         }
4869         /* Dynamic Range and Component Bit Depth */
4870         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4871                 sdp->db[17] |= 0x80;  /* DB17[7] */
4872
4873         /* Content Type */
4874         sdp->db[18] = vsc->content_type & 0x7;
4875
4876         return length;
4877 }
4878
4879 static ssize_t
4880 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4881                                          struct dp_sdp *sdp,
4882                                          size_t size)
4883 {
4884         size_t length = sizeof(struct dp_sdp);
4885         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4886         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4887         ssize_t len;
4888
4889         if (size < length)
4890                 return -ENOSPC;
4891
4892         memset(sdp, 0, size);
4893
4894         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4895         if (len < 0) {
4896                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4897                 return -ENOSPC;
4898         }
4899
4900         if (len != infoframe_size) {
4901                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4902                 return -ENOSPC;
4903         }
4904
4905         /*
4906          * Set up the infoframe sdp packet for HDR static metadata.
4907          * Prepare VSC Header for SU as per DP 1.4a spec,
4908          * Table 2-100 and Table 2-101
4909          */
4910
4911         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4912         sdp->sdp_header.HB0 = 0;
4913         /*
4914          * Packet Type 80h + Non-audio INFOFRAME Type value
4915          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4916          * - 80h + Non-audio INFOFRAME Type value
4917          * - InfoFrame Type: 0x07
4918          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4919          */
4920         sdp->sdp_header.HB1 = drm_infoframe->type;
4921         /*
4922          * Least Significant Eight Bits of (Data Byte Count – 1)
4923          * infoframe_size - 1
4924          */
4925         sdp->sdp_header.HB2 = 0x1D;
4926         /* INFOFRAME SDP Version Number */
4927         sdp->sdp_header.HB3 = (0x13 << 2);
4928         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4929         sdp->db[0] = drm_infoframe->version;
4930         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4931         sdp->db[1] = drm_infoframe->length;
4932         /*
4933          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4934          * HDMI_INFOFRAME_HEADER_SIZE
4935          */
4936         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4937         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4938                HDMI_DRM_INFOFRAME_SIZE);
4939
4940         /*
4941          * Size of DP infoframe sdp packet for HDR static metadata consists of
4942          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4943          * - Two Data Blocks: 2 bytes
4944          *    CTA Header Byte2 (INFOFRAME Version Number)
4945          *    CTA Header Byte3 (Length of INFOFRAME)
4946          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4947          *
4948          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4949          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4950          * will pad rest of the size.
4951          */
4952         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4953 }
4954
4955 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4956                                const struct intel_crtc_state *crtc_state,
4957                                unsigned int type)
4958 {
4959         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4960         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4961         struct dp_sdp sdp = {};
4962         ssize_t len;
4963
4964         if ((crtc_state->infoframes.enable &
4965              intel_hdmi_infoframe_enable(type)) == 0)
4966                 return;
4967
4968         switch (type) {
4969         case DP_SDP_VSC:
4970                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4971                                             sizeof(sdp));
4972                 break;
4973         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4974                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4975                                                                &sdp, sizeof(sdp));
4976                 break;
4977         default:
4978                 MISSING_CASE(type);
4979                 return;
4980         }
4981
4982         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4983                 return;
4984
4985         intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4986 }
4987
4988 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4989                              bool enable,
4990                              const struct intel_crtc_state *crtc_state,
4991                              const struct drm_connector_state *conn_state)
4992 {
4993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4994         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4995         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4996         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4997                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4998                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4999         u32 val = intel_de_read(dev_priv, reg);
5000
5001         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5002         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5003         if (intel_psr_enabled(intel_dp))
5004                 val &= ~dip_enable;
5005         else
5006                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5007
5008         if (!enable) {
5009                 intel_de_write(dev_priv, reg, val);
5010                 intel_de_posting_read(dev_priv, reg);
5011                 return;
5012         }
5013
5014         intel_de_write(dev_priv, reg, val);
5015         intel_de_posting_read(dev_priv, reg);
5016
5017         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5018         if (!intel_psr_enabled(intel_dp))
5019                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5020
5021         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5022 }
5023
5024 static void
5025 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
5026                        const struct intel_crtc_state *crtc_state,
5027                        const struct drm_connector_state *conn_state)
5028 {
5029         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5030         struct dp_sdp vsc_sdp = {};
5031
5032         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
5033         vsc_sdp.sdp_header.HB0 = 0;
5034         vsc_sdp.sdp_header.HB1 = 0x7;
5035
5036         /*
5037          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
5038          * Colorimetry Format indication.
5039          */
5040         vsc_sdp.sdp_header.HB2 = 0x5;
5041
5042         /*
5043          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
5044          * Colorimetry Format indication (HB2 = 05h).
5045          */
5046         vsc_sdp.sdp_header.HB3 = 0x13;
5047
5048         /* DP 1.4a spec, Table 2-120 */
5049         switch (crtc_state->output_format) {
5050         case INTEL_OUTPUT_FORMAT_YCBCR444:
5051                 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
5052                 break;
5053         case INTEL_OUTPUT_FORMAT_YCBCR420:
5054                 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
5055                 break;
5056         case INTEL_OUTPUT_FORMAT_RGB:
5057         default:
5058                 /* RGB: DB16[7:4] = 0h */
5059                 break;
5060         }
5061
5062         switch (conn_state->colorspace) {
5063         case DRM_MODE_COLORIMETRY_BT709_YCC:
5064                 vsc_sdp.db[16] |= 0x1;
5065                 break;
5066         case DRM_MODE_COLORIMETRY_XVYCC_601:
5067                 vsc_sdp.db[16] |= 0x2;
5068                 break;
5069         case DRM_MODE_COLORIMETRY_XVYCC_709:
5070                 vsc_sdp.db[16] |= 0x3;
5071                 break;
5072         case DRM_MODE_COLORIMETRY_SYCC_601:
5073                 vsc_sdp.db[16] |= 0x4;
5074                 break;
5075         case DRM_MODE_COLORIMETRY_OPYCC_601:
5076                 vsc_sdp.db[16] |= 0x5;
5077                 break;
5078         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5079         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5080                 vsc_sdp.db[16] |= 0x6;
5081                 break;
5082         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5083                 vsc_sdp.db[16] |= 0x7;
5084                 break;
5085         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
5086         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
5087                 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
5088                 break;
5089         default:
5090                 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
5091
5092                 /* RGB->YCBCR color conversion uses the BT.709 color space. */
5093                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5094                         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
5095                 break;
5096         }
5097
5098         /*
5099          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
5100          * the following Component Bit Depth values are defined:
5101          * 001b = 8bpc.
5102          * 010b = 10bpc.
5103          * 011b = 12bpc.
5104          * 100b = 16bpc.
5105          */
5106         switch (crtc_state->pipe_bpp) {
5107         case 24: /* 8bpc */
5108                 vsc_sdp.db[17] = 0x1;
5109                 break;
5110         case 30: /* 10bpc */
5111                 vsc_sdp.db[17] = 0x2;
5112                 break;
5113         case 36: /* 12bpc */
5114                 vsc_sdp.db[17] = 0x3;
5115                 break;
5116         case 48: /* 16bpc */
5117                 vsc_sdp.db[17] = 0x4;
5118                 break;
5119         default:
5120                 MISSING_CASE(crtc_state->pipe_bpp);
5121                 break;
5122         }
5123
5124         /*
5125          * Dynamic Range (Bit 7)
5126          * 0 = VESA range, 1 = CTA range.
5127          * all YCbCr are always limited range
5128          */
5129         vsc_sdp.db[17] |= 0x80;
5130
5131         /*
5132          * Content Type (Bits 2:0)
5133          * 000b = Not defined.
5134          * 001b = Graphics.
5135          * 010b = Photo.
5136          * 011b = Video.
5137          * 100b = Game
5138          * All other values are RESERVED.
5139          * Note: See CTA-861-G for the definition and expected
5140          * processing by a stream sink for the above contect types.
5141          */
5142         vsc_sdp.db[18] = 0;
5143
5144         intel_dig_port->write_infoframe(&intel_dig_port->base,
5145                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
5146 }
5147
5148 static void
5149 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
5150                                           const struct intel_crtc_state *crtc_state,
5151                                           const struct drm_connector_state *conn_state)
5152 {
5153         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5154         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5155         struct dp_sdp infoframe_sdp = {};
5156         struct hdmi_drm_infoframe drm_infoframe = {};
5157         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5158         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5159         ssize_t len;
5160         int ret;
5161
5162         ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
5163         if (ret) {
5164                 drm_dbg_kms(&i915->drm,
5165                             "couldn't set HDR metadata in infoframe\n");
5166                 return;
5167         }
5168
5169         len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
5170         if (len < 0) {
5171                 drm_dbg_kms(&i915->drm,
5172                             "buffer size is smaller than hdr metadata infoframe\n");
5173                 return;
5174         }
5175
5176         if (len != infoframe_size) {
5177                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
5178                 return;
5179         }
5180
5181         /*
5182          * Set up the infoframe sdp packet for HDR static metadata.
5183          * Prepare VSC Header for SU as per DP 1.4a spec,
5184          * Table 2-100 and Table 2-101
5185          */
5186
5187         /* Packet ID, 00h for non-Audio INFOFRAME */
5188         infoframe_sdp.sdp_header.HB0 = 0;
5189         /*
5190          * Packet Type 80h + Non-audio INFOFRAME Type value
5191          * HDMI_INFOFRAME_TYPE_DRM: 0x87,
5192          */
5193         infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
5194         /*
5195          * Least Significant Eight Bits of (Data Byte Count – 1)
5196          * infoframe_size - 1,
5197          */
5198         infoframe_sdp.sdp_header.HB2 = 0x1D;
5199         /* INFOFRAME SDP Version Number */
5200         infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
5201         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5202         infoframe_sdp.db[0] = drm_infoframe.version;
5203         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5204         infoframe_sdp.db[1] = drm_infoframe.length;
5205         /*
5206          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5207          * HDMI_INFOFRAME_HEADER_SIZE
5208          */
5209         BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5210         memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5211                HDMI_DRM_INFOFRAME_SIZE);
5212
5213         /*
5214          * Size of DP infoframe sdp packet for HDR static metadata is consist of
5215          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5216          * - Two Data Blocks: 2 bytes
5217          *    CTA Header Byte2 (INFOFRAME Version Number)
5218          *    CTA Header Byte3 (Length of INFOFRAME)
5219          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5220          *
5221          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5222          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5223          * will pad rest of the size.
5224          */
5225         intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
5226                                         HDMI_PACKET_TYPE_GAMUT_METADATA,
5227                                         &infoframe_sdp,
5228                                         sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
5229 }
5230
5231 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
5232                          const struct intel_crtc_state *crtc_state,
5233                          const struct drm_connector_state *conn_state)
5234 {
5235         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
5236                 return;
5237
5238         intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
5239 }
5240
5241 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
5242                                   const struct intel_crtc_state *crtc_state,
5243                                   const struct drm_connector_state *conn_state)
5244 {
5245         if (!conn_state->hdr_output_metadata)
5246                 return;
5247
5248         intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
5249                                                   crtc_state,
5250                                                   conn_state);
5251 }
5252
5253 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5254 {
5255         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5256         int status = 0;
5257         int test_link_rate;
5258         u8 test_lane_count, test_link_bw;
5259         /* (DP CTS 1.2)
5260          * 4.3.1.11
5261          */
5262         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5263         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5264                                    &test_lane_count);
5265
5266         if (status <= 0) {
5267                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5268                 return DP_TEST_NAK;
5269         }
5270         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5271
5272         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5273                                    &test_link_bw);
5274         if (status <= 0) {
5275                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5276                 return DP_TEST_NAK;
5277         }
5278         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5279
5280         /* Validate the requested link rate and lane count */
5281         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5282                                         test_lane_count))
5283                 return DP_TEST_NAK;
5284
5285         intel_dp->compliance.test_lane_count = test_lane_count;
5286         intel_dp->compliance.test_link_rate = test_link_rate;
5287
5288         return DP_TEST_ACK;
5289 }
5290
5291 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5292 {
5293         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5294         u8 test_pattern;
5295         u8 test_misc;
5296         __be16 h_width, v_height;
5297         int status = 0;
5298
5299         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5300         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5301                                    &test_pattern);
5302         if (status <= 0) {
5303                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5304                 return DP_TEST_NAK;
5305         }
5306         if (test_pattern != DP_COLOR_RAMP)
5307                 return DP_TEST_NAK;
5308
5309         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5310                                   &h_width, 2);
5311         if (status <= 0) {
5312                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5313                 return DP_TEST_NAK;
5314         }
5315
5316         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5317                                   &v_height, 2);
5318         if (status <= 0) {
5319                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5320                 return DP_TEST_NAK;
5321         }
5322
5323         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5324                                    &test_misc);
5325         if (status <= 0) {
5326                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5327                 return DP_TEST_NAK;
5328         }
5329         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5330                 return DP_TEST_NAK;
5331         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5332                 return DP_TEST_NAK;
5333         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5334         case DP_TEST_BIT_DEPTH_6:
5335                 intel_dp->compliance.test_data.bpc = 6;
5336                 break;
5337         case DP_TEST_BIT_DEPTH_8:
5338                 intel_dp->compliance.test_data.bpc = 8;
5339                 break;
5340         default:
5341                 return DP_TEST_NAK;
5342         }
5343
5344         intel_dp->compliance.test_data.video_pattern = test_pattern;
5345         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5346         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5347         /* Set test active flag here so userspace doesn't interrupt things */
5348         intel_dp->compliance.test_active = true;
5349
5350         return DP_TEST_ACK;
5351 }
5352
5353 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5354 {
5355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5356         u8 test_result = DP_TEST_ACK;
5357         struct intel_connector *intel_connector = intel_dp->attached_connector;
5358         struct drm_connector *connector = &intel_connector->base;
5359
5360         if (intel_connector->detect_edid == NULL ||
5361             connector->edid_corrupt ||
5362             intel_dp->aux.i2c_defer_count > 6) {
5363                 /* Check EDID read for NACKs, DEFERs and corruption
5364                  * (DP CTS 1.2 Core r1.1)
5365                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5366                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5367                  *    4.2.2.6 : EDID corruption detected
5368                  * Use failsafe mode for all cases
5369                  */
5370                 if (intel_dp->aux.i2c_nack_count > 0 ||
5371                         intel_dp->aux.i2c_defer_count > 0)
5372                         drm_dbg_kms(&i915->drm,
5373                                     "EDID read had %d NACKs, %d DEFERs\n",
5374                                     intel_dp->aux.i2c_nack_count,
5375                                     intel_dp->aux.i2c_defer_count);
5376                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5377         } else {
5378                 struct edid *block = intel_connector->detect_edid;
5379
5380                 /* We have to write the checksum
5381                  * of the last block read
5382                  */
5383                 block += intel_connector->detect_edid->extensions;
5384
5385                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5386                                        block->checksum) <= 0)
5387                         drm_dbg_kms(&i915->drm,
5388                                     "Failed to write EDID checksum\n");
5389
5390                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5391                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5392         }
5393
5394         /* Set test active flag here so userspace doesn't interrupt things */
5395         intel_dp->compliance.test_active = true;
5396
5397         return test_result;
5398 }
5399
5400 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5401 {
5402         struct drm_dp_phy_test_params *data =
5403                 &intel_dp->compliance.test_data.phytest;
5404
5405         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5406                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5407                 return DP_TEST_NAK;
5408         }
5409
5410         /*
5411          * link_mst is set to false to avoid executing mst related code
5412          * during compliance testing.
5413          */
5414         intel_dp->link_mst = false;
5415
5416         return DP_TEST_ACK;
5417 }
5418
5419 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5420 {
5421         struct drm_i915_private *dev_priv =
5422                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5423         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5424         struct drm_dp_phy_test_params *data =
5425                         &intel_dp->compliance.test_data.phytest;
5426         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5427         enum pipe pipe = crtc->pipe;
5428         u32 pattern_val;
5429
5430         switch (data->phy_pattern) {
5431         case DP_PHY_TEST_PATTERN_NONE:
5432                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5433                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5434                 break;
5435         case DP_PHY_TEST_PATTERN_D10_2:
5436                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5437                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5438                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5439                 break;
5440         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5441                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5442                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5443                                DDI_DP_COMP_CTL_ENABLE |
5444                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5445                 break;
5446         case DP_PHY_TEST_PATTERN_PRBS7:
5447                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5448                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5449                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5450                 break;
5451         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5452                 /*
5453                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5454                  * current firmware of DPR-100 could not set it, so hardcoding
5455                  * now for complaince test.
5456                  */
5457                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5458                 pattern_val = 0x3e0f83e0;
5459                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5460                 pattern_val = 0x0f83e0f8;
5461                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5462                 pattern_val = 0x0000f83e;
5463                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5464                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5465                                DDI_DP_COMP_CTL_ENABLE |
5466                                DDI_DP_COMP_CTL_CUSTOM80);
5467                 break;
5468         case DP_PHY_TEST_PATTERN_CP2520:
5469                 /*
5470                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5471                  * current firmware of DPR-100 could not set it, so hardcoding
5472                  * now for complaince test.
5473                  */
5474                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5475                 pattern_val = 0xFB;
5476                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5477                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5478                                pattern_val);
5479                 break;
5480         default:
5481                 WARN(1, "Invalid Phy Test Pattern\n");
5482         }
5483 }
5484
5485 static void
5486 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5487 {
5488         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5489         struct drm_device *dev = intel_dig_port->base.base.dev;
5490         struct drm_i915_private *dev_priv = to_i915(dev);
5491         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5492         enum pipe pipe = crtc->pipe;
5493         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5494
5495         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5496                                                  TRANS_DDI_FUNC_CTL(pipe));
5497         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5498         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5499
5500         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5501                                       TGL_TRANS_DDI_PORT_MASK);
5502         trans_conf_value &= ~PIPECONF_ENABLE;
5503         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5504
5505         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5506         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5507                        trans_ddi_func_ctl_value);
5508         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5509 }
5510
5511 static void
5512 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5513 {
5514         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5515         struct drm_device *dev = intel_dig_port->base.base.dev;
5516         struct drm_i915_private *dev_priv = to_i915(dev);
5517         enum port port = intel_dig_port->base.port;
5518         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5519         enum pipe pipe = crtc->pipe;
5520         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5521
5522         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5523                                                  TRANS_DDI_FUNC_CTL(pipe));
5524         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5525         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5526
5527         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5528                                     TGL_TRANS_DDI_SELECT_PORT(port);
5529         trans_conf_value |= PIPECONF_ENABLE;
5530         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5531
5532         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5533         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5534         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5535                        trans_ddi_func_ctl_value);
5536 }
5537
5538 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5539 {
5540         struct drm_dp_phy_test_params *data =
5541                 &intel_dp->compliance.test_data.phytest;
5542         u8 link_status[DP_LINK_STATUS_SIZE];
5543
5544         if (!intel_dp_get_link_status(intel_dp, link_status)) {
5545                 DRM_DEBUG_KMS("failed to get link status\n");
5546                 return;
5547         }
5548
5549         /* retrieve vswing & pre-emphasis setting */
5550         intel_dp_get_adjust_train(intel_dp, link_status);
5551
5552         intel_dp_autotest_phy_ddi_disable(intel_dp);
5553
5554         intel_dp_set_signal_levels(intel_dp);
5555
5556         intel_dp_phy_pattern_update(intel_dp);
5557
5558         intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5559
5560         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5561                                     link_status[DP_DPCD_REV]);
5562 }
5563
5564 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5565 {
5566         u8 test_result = DP_TEST_NAK;
5567
5568         test_result = intel_dp_prepare_phytest(intel_dp);
5569         if (test_result != DP_TEST_ACK)
5570                 DRM_ERROR("Phy test preparation failed\n");
5571
5572         intel_dp_process_phy_request(intel_dp);
5573
5574         return test_result;
5575 }
5576
5577 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5578 {
5579         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5580         u8 response = DP_TEST_NAK;
5581         u8 request = 0;
5582         int status;
5583
5584         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5585         if (status <= 0) {
5586                 drm_dbg_kms(&i915->drm,
5587                             "Could not read test request from sink\n");
5588                 goto update_status;
5589         }
5590
5591         switch (request) {
5592         case DP_TEST_LINK_TRAINING:
5593                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5594                 response = intel_dp_autotest_link_training(intel_dp);
5595                 break;
5596         case DP_TEST_LINK_VIDEO_PATTERN:
5597                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5598                 response = intel_dp_autotest_video_pattern(intel_dp);
5599                 break;
5600         case DP_TEST_LINK_EDID_READ:
5601                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5602                 response = intel_dp_autotest_edid(intel_dp);
5603                 break;
5604         case DP_TEST_LINK_PHY_TEST_PATTERN:
5605                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5606                 response = intel_dp_autotest_phy_pattern(intel_dp);
5607                 break;
5608         default:
5609                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5610                             request);
5611                 break;
5612         }
5613
5614         if (response & DP_TEST_ACK)
5615                 intel_dp->compliance.test_type = request;
5616
5617 update_status:
5618         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5619         if (status <= 0)
5620                 drm_dbg_kms(&i915->drm,
5621                             "Could not write test response to sink\n");
5622 }
5623
5624 static int
5625 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5626 {
5627         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5628         bool bret;
5629
5630         if (intel_dp->is_mst) {
5631                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
5632                 int ret = 0;
5633                 int retry;
5634                 bool handled;
5635
5636                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5637                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5638 go_again:
5639                 if (bret == true) {
5640
5641                         /* check link status - esi[10] = 0x200c */
5642                         if (intel_dp->active_mst_links > 0 &&
5643                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5644                                 drm_dbg_kms(&i915->drm,
5645                                             "channel EQ not ok, retraining\n");
5646                                 intel_dp_start_link_train(intel_dp);
5647                                 intel_dp_stop_link_train(intel_dp);
5648                         }
5649
5650                         drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5651                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5652
5653                         if (handled) {
5654                                 for (retry = 0; retry < 3; retry++) {
5655                                         int wret;
5656                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5657                                                                  DP_SINK_COUNT_ESI+1,
5658                                                                  &esi[1], 3);
5659                                         if (wret == 3) {
5660                                                 break;
5661                                         }
5662                                 }
5663
5664                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5665                                 if (bret == true) {
5666                                         drm_dbg_kms(&i915->drm,
5667                                                     "got esi2 %3ph\n", esi);
5668                                         goto go_again;
5669                                 }
5670                         } else
5671                                 ret = 0;
5672
5673                         return ret;
5674                 } else {
5675                         drm_dbg_kms(&i915->drm,
5676                                     "failed to get ESI - device may have failed\n");
5677                         intel_dp->is_mst = false;
5678                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5679                                                         intel_dp->is_mst);
5680                 }
5681         }
5682         return -EINVAL;
5683 }
5684
5685 static bool
5686 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5687 {
5688         u8 link_status[DP_LINK_STATUS_SIZE];
5689
5690         if (!intel_dp->link_trained)
5691                 return false;
5692
5693         /*
5694          * While PSR source HW is enabled, it will control main-link sending
5695          * frames, enabling and disabling it so trying to do a retrain will fail
5696          * as the link would or not be on or it could mix training patterns
5697          * and frame data at the same time causing retrain to fail.
5698          * Also when exiting PSR, HW will retrain the link anyways fixing
5699          * any link status error.
5700          */
5701         if (intel_psr_enabled(intel_dp))
5702                 return false;
5703
5704         if (!intel_dp_get_link_status(intel_dp, link_status))
5705                 return false;
5706
5707         /*
5708          * Validate the cached values of intel_dp->link_rate and
5709          * intel_dp->lane_count before attempting to retrain.
5710          */
5711         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5712                                         intel_dp->lane_count))
5713                 return false;
5714
5715         /* Retrain if Channel EQ or CR not ok */
5716         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5717 }
5718
5719 int intel_dp_retrain_link(struct intel_encoder *encoder,
5720                           struct drm_modeset_acquire_ctx *ctx)
5721 {
5722         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5723         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5724         struct intel_connector *connector = intel_dp->attached_connector;
5725         struct drm_connector_state *conn_state;
5726         struct intel_crtc_state *crtc_state;
5727         struct intel_crtc *crtc;
5728         int ret;
5729
5730         /* FIXME handle the MST connectors as well */
5731
5732         if (!connector || connector->base.status != connector_status_connected)
5733                 return 0;
5734
5735         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5736                                ctx);
5737         if (ret)
5738                 return ret;
5739
5740         conn_state = connector->base.state;
5741
5742         crtc = to_intel_crtc(conn_state->crtc);
5743         if (!crtc)
5744                 return 0;
5745
5746         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5747         if (ret)
5748                 return ret;
5749
5750         crtc_state = to_intel_crtc_state(crtc->base.state);
5751
5752         drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state));
5753
5754         if (!crtc_state->hw.active)
5755                 return 0;
5756
5757         if (conn_state->commit &&
5758             !try_wait_for_completion(&conn_state->commit->hw_done))
5759                 return 0;
5760
5761         if (!intel_dp_needs_link_retrain(intel_dp))
5762                 return 0;
5763
5764         /* Suppress underruns caused by re-training */
5765         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5766         if (crtc_state->has_pch_encoder)
5767                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5768                                                       intel_crtc_pch_transcoder(crtc), false);
5769
5770         intel_dp_start_link_train(intel_dp);
5771         intel_dp_stop_link_train(intel_dp);
5772
5773         /* Keep underrun reporting disabled until things are stable */
5774         intel_wait_for_vblank(dev_priv, crtc->pipe);
5775
5776         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5777         if (crtc_state->has_pch_encoder)
5778                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5779                                                       intel_crtc_pch_transcoder(crtc), true);
5780
5781         return 0;
5782 }
5783
5784 /*
5785  * If display is now connected check links status,
5786  * there has been known issues of link loss triggering
5787  * long pulse.
5788  *
5789  * Some sinks (eg. ASUS PB287Q) seem to perform some
5790  * weird HPD ping pong during modesets. So we can apparently
5791  * end up with HPD going low during a modeset, and then
5792  * going back up soon after. And once that happens we must
5793  * retrain the link to get a picture. That's in case no
5794  * userspace component reacted to intermittent HPD dip.
5795  */
5796 static enum intel_hotplug_state
5797 intel_dp_hotplug(struct intel_encoder *encoder,
5798                  struct intel_connector *connector)
5799 {
5800         struct drm_modeset_acquire_ctx ctx;
5801         enum intel_hotplug_state state;
5802         int ret;
5803
5804         state = intel_encoder_hotplug(encoder, connector);
5805
5806         drm_modeset_acquire_init(&ctx, 0);
5807
5808         for (;;) {
5809                 ret = intel_dp_retrain_link(encoder, &ctx);
5810
5811                 if (ret == -EDEADLK) {
5812                         drm_modeset_backoff(&ctx);
5813                         continue;
5814                 }
5815
5816                 break;
5817         }
5818
5819         drm_modeset_drop_locks(&ctx);
5820         drm_modeset_acquire_fini(&ctx);
5821         drm_WARN(encoder->base.dev, ret,
5822                  "Acquiring modeset locks failed with %i\n", ret);
5823
5824         /*
5825          * Keeping it consistent with intel_ddi_hotplug() and
5826          * intel_hdmi_hotplug().
5827          */
5828         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5829                 state = INTEL_HOTPLUG_RETRY;
5830
5831         return state;
5832 }
5833
5834 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5835 {
5836         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5837         u8 val;
5838
5839         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5840                 return;
5841
5842         if (drm_dp_dpcd_readb(&intel_dp->aux,
5843                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5844                 return;
5845
5846         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5847
5848         if (val & DP_AUTOMATED_TEST_REQUEST)
5849                 intel_dp_handle_test_request(intel_dp);
5850
5851         if (val & DP_CP_IRQ)
5852                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5853
5854         if (val & DP_SINK_SPECIFIC_IRQ)
5855                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5856 }
5857
5858 /*
5859  * According to DP spec
5860  * 5.1.2:
5861  *  1. Read DPCD
5862  *  2. Configure link according to Receiver Capabilities
5863  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5864  *  4. Check link status on receipt of hot-plug interrupt
5865  *
5866  * intel_dp_short_pulse -  handles short pulse interrupts
5867  * when full detection is not required.
5868  * Returns %true if short pulse is handled and full detection
5869  * is NOT required and %false otherwise.
5870  */
5871 static bool
5872 intel_dp_short_pulse(struct intel_dp *intel_dp)
5873 {
5874         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5875         u8 old_sink_count = intel_dp->sink_count;
5876         bool ret;
5877
5878         /*
5879          * Clearing compliance test variables to allow capturing
5880          * of values for next automated test request.
5881          */
5882         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5883
5884         /*
5885          * Now read the DPCD to see if it's actually running
5886          * If the current value of sink count doesn't match with
5887          * the value that was stored earlier or dpcd read failed
5888          * we need to do full detection
5889          */
5890         ret = intel_dp_get_dpcd(intel_dp);
5891
5892         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5893                 /* No need to proceed if we are going to do full detect */
5894                 return false;
5895         }
5896
5897         intel_dp_check_service_irq(intel_dp);
5898
5899         /* Handle CEC interrupts, if any */
5900         drm_dp_cec_irq(&intel_dp->aux);
5901
5902         /* defer to the hotplug work for link retraining if needed */
5903         if (intel_dp_needs_link_retrain(intel_dp))
5904                 return false;
5905
5906         intel_psr_short_pulse(intel_dp);
5907
5908         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5909                 drm_dbg_kms(&dev_priv->drm,
5910                             "Link Training Compliance Test requested\n");
5911                 /* Send a Hotplug Uevent to userspace to start modeset */
5912                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5913         }
5914
5915         return true;
5916 }
5917
5918 /* XXX this is probably wrong for multiple downstream ports */
5919 static enum drm_connector_status
5920 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5921 {
5922         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5923         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5924         u8 *dpcd = intel_dp->dpcd;
5925         u8 type;
5926
5927         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5928                 return connector_status_connected;
5929
5930         if (lspcon->active)
5931                 lspcon_resume(lspcon);
5932
5933         if (!intel_dp_get_dpcd(intel_dp))
5934                 return connector_status_disconnected;
5935
5936         /* if there's no downstream port, we're done */
5937         if (!drm_dp_is_branch(dpcd))
5938                 return connector_status_connected;
5939
5940         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5941         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5942             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5943
5944                 return intel_dp->sink_count ?
5945                 connector_status_connected : connector_status_disconnected;
5946         }
5947
5948         if (intel_dp_can_mst(intel_dp))
5949                 return connector_status_connected;
5950
5951         /* If no HPD, poke DDC gently */
5952         if (drm_probe_ddc(&intel_dp->aux.ddc))
5953                 return connector_status_connected;
5954
5955         /* Well we tried, say unknown for unreliable port types */
5956         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5957                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5958                 if (type == DP_DS_PORT_TYPE_VGA ||
5959                     type == DP_DS_PORT_TYPE_NON_EDID)
5960                         return connector_status_unknown;
5961         } else {
5962                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5963                         DP_DWN_STRM_PORT_TYPE_MASK;
5964                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5965                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5966                         return connector_status_unknown;
5967         }
5968
5969         /* Anything else is out of spec, warn and ignore */
5970         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5971         return connector_status_disconnected;
5972 }
5973
5974 static enum drm_connector_status
5975 edp_detect(struct intel_dp *intel_dp)
5976 {
5977         return connector_status_connected;
5978 }
5979
5980 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5981 {
5982         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5983         u32 bit;
5984
5985         switch (encoder->hpd_pin) {
5986         case HPD_PORT_B:
5987                 bit = SDE_PORTB_HOTPLUG;
5988                 break;
5989         case HPD_PORT_C:
5990                 bit = SDE_PORTC_HOTPLUG;
5991                 break;
5992         case HPD_PORT_D:
5993                 bit = SDE_PORTD_HOTPLUG;
5994                 break;
5995         default:
5996                 MISSING_CASE(encoder->hpd_pin);
5997                 return false;
5998         }
5999
6000         return intel_de_read(dev_priv, SDEISR) & bit;
6001 }
6002
6003 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
6004 {
6005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6006         u32 bit;
6007
6008         switch (encoder->hpd_pin) {
6009         case HPD_PORT_B:
6010                 bit = SDE_PORTB_HOTPLUG_CPT;
6011                 break;
6012         case HPD_PORT_C:
6013                 bit = SDE_PORTC_HOTPLUG_CPT;
6014                 break;
6015         case HPD_PORT_D:
6016                 bit = SDE_PORTD_HOTPLUG_CPT;
6017                 break;
6018         default:
6019                 MISSING_CASE(encoder->hpd_pin);
6020                 return false;
6021         }
6022
6023         return intel_de_read(dev_priv, SDEISR) & bit;
6024 }
6025
6026 static bool spt_digital_port_connected(struct intel_encoder *encoder)
6027 {
6028         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6029         u32 bit;
6030
6031         switch (encoder->hpd_pin) {
6032         case HPD_PORT_A:
6033                 bit = SDE_PORTA_HOTPLUG_SPT;
6034                 break;
6035         case HPD_PORT_E:
6036                 bit = SDE_PORTE_HOTPLUG_SPT;
6037                 break;
6038         default:
6039                 return cpt_digital_port_connected(encoder);
6040         }
6041
6042         return intel_de_read(dev_priv, SDEISR) & bit;
6043 }
6044
6045 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6046 {
6047         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6048         u32 bit;
6049
6050         switch (encoder->hpd_pin) {
6051         case HPD_PORT_B:
6052                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6053                 break;
6054         case HPD_PORT_C:
6055                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6056                 break;
6057         case HPD_PORT_D:
6058                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6059                 break;
6060         default:
6061                 MISSING_CASE(encoder->hpd_pin);
6062                 return false;
6063         }
6064
6065         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6066 }
6067
6068 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6069 {
6070         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6071         u32 bit;
6072
6073         switch (encoder->hpd_pin) {
6074         case HPD_PORT_B:
6075                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6076                 break;
6077         case HPD_PORT_C:
6078                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6079                 break;
6080         case HPD_PORT_D:
6081                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6082                 break;
6083         default:
6084                 MISSING_CASE(encoder->hpd_pin);
6085                 return false;
6086         }
6087
6088         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6089 }
6090
6091 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6092 {
6093         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6094
6095         if (encoder->hpd_pin == HPD_PORT_A)
6096                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6097         else
6098                 return ibx_digital_port_connected(encoder);
6099 }
6100
6101 static bool snb_digital_port_connected(struct intel_encoder *encoder)
6102 {
6103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6104
6105         if (encoder->hpd_pin == HPD_PORT_A)
6106                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6107         else
6108                 return cpt_digital_port_connected(encoder);
6109 }
6110
6111 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
6112 {
6113         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6114
6115         if (encoder->hpd_pin == HPD_PORT_A)
6116                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
6117         else
6118                 return cpt_digital_port_connected(encoder);
6119 }
6120
6121 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
6122 {
6123         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6124
6125         if (encoder->hpd_pin == HPD_PORT_A)
6126                 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
6127         else
6128                 return cpt_digital_port_connected(encoder);
6129 }
6130
6131 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
6132 {
6133         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6134         u32 bit;
6135
6136         switch (encoder->hpd_pin) {
6137         case HPD_PORT_A:
6138                 bit = BXT_DE_PORT_HP_DDIA;
6139                 break;
6140         case HPD_PORT_B:
6141                 bit = BXT_DE_PORT_HP_DDIB;
6142                 break;
6143         case HPD_PORT_C:
6144                 bit = BXT_DE_PORT_HP_DDIC;
6145                 break;
6146         default:
6147                 MISSING_CASE(encoder->hpd_pin);
6148                 return false;
6149         }
6150
6151         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
6152 }
6153
6154 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
6155                                       enum phy phy)
6156 {
6157         if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
6158                 return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
6159
6160         return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
6161 }
6162
6163 static bool icp_digital_port_connected(struct intel_encoder *encoder)
6164 {
6165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6166         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6167         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
6168
6169         if (intel_phy_is_combo(dev_priv, phy))
6170                 return intel_combo_phy_connected(dev_priv, phy);
6171         else if (intel_phy_is_tc(dev_priv, phy))
6172                 return intel_tc_port_connected(dig_port);
6173         else
6174                 MISSING_CASE(encoder->hpd_pin);
6175
6176         return false;
6177 }
6178
6179 /*
6180  * intel_digital_port_connected - is the specified port connected?
6181  * @encoder: intel_encoder
6182  *
6183  * In cases where there's a connector physically connected but it can't be used
6184  * by our hardware we also return false, since the rest of the driver should
6185  * pretty much treat the port as disconnected. This is relevant for type-C
6186  * (starting on ICL) where there's ownership involved.
6187  *
6188  * Return %true if port is connected, %false otherwise.
6189  */
6190 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
6191 {
6192         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6193
6194         if (HAS_GMCH(dev_priv)) {
6195                 if (IS_GM45(dev_priv))
6196                         return gm45_digital_port_connected(encoder);
6197                 else
6198                         return g4x_digital_port_connected(encoder);
6199         }
6200
6201         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
6202                 return icp_digital_port_connected(encoder);
6203         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
6204                 return spt_digital_port_connected(encoder);
6205         else if (IS_GEN9_LP(dev_priv))
6206                 return bxt_digital_port_connected(encoder);
6207         else if (IS_GEN(dev_priv, 8))
6208                 return bdw_digital_port_connected(encoder);
6209         else if (IS_GEN(dev_priv, 7))
6210                 return ivb_digital_port_connected(encoder);
6211         else if (IS_GEN(dev_priv, 6))
6212                 return snb_digital_port_connected(encoder);
6213         else if (IS_GEN(dev_priv, 5))
6214                 return ilk_digital_port_connected(encoder);
6215
6216         MISSING_CASE(INTEL_GEN(dev_priv));
6217         return false;
6218 }
6219
6220 bool intel_digital_port_connected(struct intel_encoder *encoder)
6221 {
6222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6223         bool is_connected = false;
6224         intel_wakeref_t wakeref;
6225
6226         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6227                 is_connected = __intel_digital_port_connected(encoder);
6228
6229         return is_connected;
6230 }
6231
6232 static struct edid *
6233 intel_dp_get_edid(struct intel_dp *intel_dp)
6234 {
6235         struct intel_connector *intel_connector = intel_dp->attached_connector;
6236
6237         /* use cached edid if we have one */
6238         if (intel_connector->edid) {
6239                 /* invalid edid */
6240                 if (IS_ERR(intel_connector->edid))
6241                         return NULL;
6242
6243                 return drm_edid_duplicate(intel_connector->edid);
6244         } else
6245                 return drm_get_edid(&intel_connector->base,
6246                                     &intel_dp->aux.ddc);
6247 }
6248
6249 static void
6250 intel_dp_set_edid(struct intel_dp *intel_dp)
6251 {
6252         struct intel_connector *intel_connector = intel_dp->attached_connector;
6253         struct edid *edid;
6254
6255         intel_dp_unset_edid(intel_dp);
6256         edid = intel_dp_get_edid(intel_dp);
6257         intel_connector->detect_edid = edid;
6258
6259         intel_dp->has_audio = drm_detect_monitor_audio(edid);
6260         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6261         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6262 }
6263
6264 static void
6265 intel_dp_unset_edid(struct intel_dp *intel_dp)
6266 {
6267         struct intel_connector *intel_connector = intel_dp->attached_connector;
6268
6269         drm_dp_cec_unset_edid(&intel_dp->aux);
6270         kfree(intel_connector->detect_edid);
6271         intel_connector->detect_edid = NULL;
6272
6273         intel_dp->has_audio = false;
6274         intel_dp->edid_quirks = 0;
6275 }
6276
6277 static int
6278 intel_dp_detect(struct drm_connector *connector,
6279                 struct drm_modeset_acquire_ctx *ctx,
6280                 bool force)
6281 {
6282         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6283         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6284         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6285         struct intel_encoder *encoder = &dig_port->base;
6286         enum drm_connector_status status;
6287
6288         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6289                     connector->base.id, connector->name);
6290         drm_WARN_ON(&dev_priv->drm,
6291                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6292
6293         /* Can't disconnect eDP */
6294         if (intel_dp_is_edp(intel_dp))
6295                 status = edp_detect(intel_dp);
6296         else if (intel_digital_port_connected(encoder))
6297                 status = intel_dp_detect_dpcd(intel_dp);
6298         else
6299                 status = connector_status_disconnected;
6300
6301         if (status == connector_status_disconnected) {
6302                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6303                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6304
6305                 if (intel_dp->is_mst) {
6306                         drm_dbg_kms(&dev_priv->drm,
6307                                     "MST device may have disappeared %d vs %d\n",
6308                                     intel_dp->is_mst,
6309                                     intel_dp->mst_mgr.mst_state);
6310                         intel_dp->is_mst = false;
6311                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6312                                                         intel_dp->is_mst);
6313                 }
6314
6315                 goto out;
6316         }
6317
6318         if (intel_dp->reset_link_params) {
6319                 /* Initial max link lane count */
6320                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6321
6322                 /* Initial max link rate */
6323                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6324
6325                 intel_dp->reset_link_params = false;
6326         }
6327
6328         intel_dp_print_rates(intel_dp);
6329
6330         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6331         if (INTEL_GEN(dev_priv) >= 11)
6332                 intel_dp_get_dsc_sink_cap(intel_dp);
6333
6334         intel_dp_configure_mst(intel_dp);
6335
6336         if (intel_dp->is_mst) {
6337                 /*
6338                  * If we are in MST mode then this connector
6339                  * won't appear connected or have anything
6340                  * with EDID on it
6341                  */
6342                 status = connector_status_disconnected;
6343                 goto out;
6344         }
6345
6346         /*
6347          * Some external monitors do not signal loss of link synchronization
6348          * with an IRQ_HPD, so force a link status check.
6349          */
6350         if (!intel_dp_is_edp(intel_dp)) {
6351                 int ret;
6352
6353                 ret = intel_dp_retrain_link(encoder, ctx);
6354                 if (ret)
6355                         return ret;
6356         }
6357
6358         /*
6359          * Clearing NACK and defer counts to get their exact values
6360          * while reading EDID which are required by Compliance tests
6361          * 4.2.2.4 and 4.2.2.5
6362          */
6363         intel_dp->aux.i2c_nack_count = 0;
6364         intel_dp->aux.i2c_defer_count = 0;
6365
6366         intel_dp_set_edid(intel_dp);
6367         if (intel_dp_is_edp(intel_dp) ||
6368             to_intel_connector(connector)->detect_edid)
6369                 status = connector_status_connected;
6370
6371         intel_dp_check_service_irq(intel_dp);
6372
6373 out:
6374         if (status != connector_status_connected && !intel_dp->is_mst)
6375                 intel_dp_unset_edid(intel_dp);
6376
6377         /*
6378          * Make sure the refs for power wells enabled during detect are
6379          * dropped to avoid a new detect cycle triggered by HPD polling.
6380          */
6381         intel_display_power_flush_work(dev_priv);
6382
6383         return status;
6384 }
6385
6386 static void
6387 intel_dp_force(struct drm_connector *connector)
6388 {
6389         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6390         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6391         struct intel_encoder *intel_encoder = &dig_port->base;
6392         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6393         enum intel_display_power_domain aux_domain =
6394                 intel_aux_power_domain(dig_port);
6395         intel_wakeref_t wakeref;
6396
6397         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6398                     connector->base.id, connector->name);
6399         intel_dp_unset_edid(intel_dp);
6400
6401         if (connector->status != connector_status_connected)
6402                 return;
6403
6404         wakeref = intel_display_power_get(dev_priv, aux_domain);
6405
6406         intel_dp_set_edid(intel_dp);
6407
6408         intel_display_power_put(dev_priv, aux_domain, wakeref);
6409 }
6410
6411 static int intel_dp_get_modes(struct drm_connector *connector)
6412 {
6413         struct intel_connector *intel_connector = to_intel_connector(connector);
6414         struct edid *edid;
6415
6416         edid = intel_connector->detect_edid;
6417         if (edid) {
6418                 int ret = intel_connector_update_modes(connector, edid);
6419                 if (ret)
6420                         return ret;
6421         }
6422
6423         /* if eDP has no EDID, fall back to fixed mode */
6424         if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6425             intel_connector->panel.fixed_mode) {
6426                 struct drm_display_mode *mode;
6427
6428                 mode = drm_mode_duplicate(connector->dev,
6429                                           intel_connector->panel.fixed_mode);
6430                 if (mode) {
6431                         drm_mode_probed_add(connector, mode);
6432                         return 1;
6433                 }
6434         }
6435
6436         return 0;
6437 }
6438
6439 static int
6440 intel_dp_connector_register(struct drm_connector *connector)
6441 {
6442         struct drm_i915_private *i915 = to_i915(connector->dev);
6443         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6444         int ret;
6445
6446         ret = intel_connector_register(connector);
6447         if (ret)
6448                 return ret;
6449
6450         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6451                     intel_dp->aux.name, connector->kdev->kobj.name);
6452
6453         intel_dp->aux.dev = connector->kdev;
6454         ret = drm_dp_aux_register(&intel_dp->aux);
6455         if (!ret)
6456                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6457         return ret;
6458 }
6459
6460 static void
6461 intel_dp_connector_unregister(struct drm_connector *connector)
6462 {
6463         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6464
6465         drm_dp_cec_unregister_connector(&intel_dp->aux);
6466         drm_dp_aux_unregister(&intel_dp->aux);
6467         intel_connector_unregister(connector);
6468 }
6469
6470 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6471 {
6472         struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6473         struct intel_dp *intel_dp = &intel_dig_port->dp;
6474
6475         intel_dp_mst_encoder_cleanup(intel_dig_port);
6476         if (intel_dp_is_edp(intel_dp)) {
6477                 intel_wakeref_t wakeref;
6478
6479                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6480                 /*
6481                  * vdd might still be enabled do to the delayed vdd off.
6482                  * Make sure vdd is actually turned off here.
6483                  */
6484                 with_pps_lock(intel_dp, wakeref)
6485                         edp_panel_vdd_off_sync(intel_dp);
6486
6487                 if (intel_dp->edp_notifier.notifier_call) {
6488                         unregister_reboot_notifier(&intel_dp->edp_notifier);
6489                         intel_dp->edp_notifier.notifier_call = NULL;
6490                 }
6491         }
6492
6493         intel_dp_aux_fini(intel_dp);
6494 }
6495
6496 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6497 {
6498         intel_dp_encoder_flush_work(encoder);
6499
6500         drm_encoder_cleanup(encoder);
6501         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6502 }
6503
6504 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6505 {
6506         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6507         intel_wakeref_t wakeref;
6508
6509         if (!intel_dp_is_edp(intel_dp))
6510                 return;
6511
6512         /*
6513          * vdd might still be enabled do to the delayed vdd off.
6514          * Make sure vdd is actually turned off here.
6515          */
6516         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6517         with_pps_lock(intel_dp, wakeref)
6518                 edp_panel_vdd_off_sync(intel_dp);
6519 }
6520
6521 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6522 {
6523         long ret;
6524
6525 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6526         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6527                                                msecs_to_jiffies(timeout));
6528
6529         if (!ret)
6530                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6531 }
6532
6533 static
6534 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6535                                 u8 *an)
6536 {
6537         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6538         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6539         static const struct drm_dp_aux_msg msg = {
6540                 .request = DP_AUX_NATIVE_WRITE,
6541                 .address = DP_AUX_HDCP_AKSV,
6542                 .size = DRM_HDCP_KSV_LEN,
6543         };
6544         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6545         ssize_t dpcd_ret;
6546         int ret;
6547
6548         /* Output An first, that's easy */
6549         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6550                                      an, DRM_HDCP_AN_LEN);
6551         if (dpcd_ret != DRM_HDCP_AN_LEN) {
6552                 drm_dbg_kms(&i915->drm,
6553                             "Failed to write An over DP/AUX (%zd)\n",
6554                             dpcd_ret);
6555                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6556         }
6557
6558         /*
6559          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6560          * order to get it on the wire, we need to create the AUX header as if
6561          * we were writing the data, and then tickle the hardware to output the
6562          * data once the header is sent out.
6563          */
6564         intel_dp_aux_header(txbuf, &msg);
6565
6566         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6567                                 rxbuf, sizeof(rxbuf),
6568                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6569         if (ret < 0) {
6570                 drm_dbg_kms(&i915->drm,
6571                             "Write Aksv over DP/AUX failed (%d)\n", ret);
6572                 return ret;
6573         } else if (ret == 0) {
6574                 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6575                 return -EIO;
6576         }
6577
6578         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6579         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6580                 drm_dbg_kms(&i915->drm,
6581                             "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6582                             reply);
6583                 return -EIO;
6584         }
6585         return 0;
6586 }
6587
6588 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6589                                    u8 *bksv)
6590 {
6591         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6592         ssize_t ret;
6593
6594         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6595                                DRM_HDCP_KSV_LEN);
6596         if (ret != DRM_HDCP_KSV_LEN) {
6597                 drm_dbg_kms(&i915->drm,
6598                             "Read Bksv from DP/AUX failed (%zd)\n", ret);
6599                 return ret >= 0 ? -EIO : ret;
6600         }
6601         return 0;
6602 }
6603
6604 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6605                                       u8 *bstatus)
6606 {
6607         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6608         ssize_t ret;
6609
6610         /*
6611          * For some reason the HDMI and DP HDCP specs call this register
6612          * definition by different names. In the HDMI spec, it's called BSTATUS,
6613          * but in DP it's called BINFO.
6614          */
6615         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6616                                bstatus, DRM_HDCP_BSTATUS_LEN);
6617         if (ret != DRM_HDCP_BSTATUS_LEN) {
6618                 drm_dbg_kms(&i915->drm,
6619                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6620                 return ret >= 0 ? -EIO : ret;
6621         }
6622         return 0;
6623 }
6624
6625 static
6626 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6627                              u8 *bcaps)
6628 {
6629         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6630         ssize_t ret;
6631
6632         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6633                                bcaps, 1);
6634         if (ret != 1) {
6635                 drm_dbg_kms(&i915->drm,
6636                             "Read bcaps from DP/AUX failed (%zd)\n", ret);
6637                 return ret >= 0 ? -EIO : ret;
6638         }
6639
6640         return 0;
6641 }
6642
6643 static
6644 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6645                                    bool *repeater_present)
6646 {
6647         ssize_t ret;
6648         u8 bcaps;
6649
6650         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6651         if (ret)
6652                 return ret;
6653
6654         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6655         return 0;
6656 }
6657
6658 static
6659 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6660                                 u8 *ri_prime)
6661 {
6662         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6663         ssize_t ret;
6664
6665         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6666                                ri_prime, DRM_HDCP_RI_LEN);
6667         if (ret != DRM_HDCP_RI_LEN) {
6668                 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6669                             ret);
6670                 return ret >= 0 ? -EIO : ret;
6671         }
6672         return 0;
6673 }
6674
6675 static
6676 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6677                                  bool *ksv_ready)
6678 {
6679         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6680         ssize_t ret;
6681         u8 bstatus;
6682
6683         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6684                                &bstatus, 1);
6685         if (ret != 1) {
6686                 drm_dbg_kms(&i915->drm,
6687                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6688                 return ret >= 0 ? -EIO : ret;
6689         }
6690         *ksv_ready = bstatus & DP_BSTATUS_READY;
6691         return 0;
6692 }
6693
6694 static
6695 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6696                                 int num_downstream, u8 *ksv_fifo)
6697 {
6698         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6699         ssize_t ret;
6700         int i;
6701
6702         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6703         for (i = 0; i < num_downstream; i += 3) {
6704                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6705                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6706                                        DP_AUX_HDCP_KSV_FIFO,
6707                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
6708                                        len);
6709                 if (ret != len) {
6710                         drm_dbg_kms(&i915->drm,
6711                                     "Read ksv[%d] from DP/AUX failed (%zd)\n",
6712                                     i, ret);
6713                         return ret >= 0 ? -EIO : ret;
6714                 }
6715         }
6716         return 0;
6717 }
6718
6719 static
6720 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6721                                     int i, u32 *part)
6722 {
6723         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6724         ssize_t ret;
6725
6726         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6727                 return -EINVAL;
6728
6729         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6730                                DP_AUX_HDCP_V_PRIME(i), part,
6731                                DRM_HDCP_V_PRIME_PART_LEN);
6732         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6733                 drm_dbg_kms(&i915->drm,
6734                             "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6735                 return ret >= 0 ? -EIO : ret;
6736         }
6737         return 0;
6738 }
6739
6740 static
6741 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6742                                     bool enable)
6743 {
6744         /* Not used for single stream DisplayPort setups */
6745         return 0;
6746 }
6747
6748 static
6749 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6750 {
6751         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6752         ssize_t ret;
6753         u8 bstatus;
6754
6755         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6756                                &bstatus, 1);
6757         if (ret != 1) {
6758                 drm_dbg_kms(&i915->drm,
6759                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6760                 return false;
6761         }
6762
6763         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6764 }
6765
6766 static
6767 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6768                           bool *hdcp_capable)
6769 {
6770         ssize_t ret;
6771         u8 bcaps;
6772
6773         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6774         if (ret)
6775                 return ret;
6776
6777         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6778         return 0;
6779 }
6780
6781 struct hdcp2_dp_errata_stream_type {
6782         u8      msg_id;
6783         u8      stream_type;
6784 } __packed;
6785
6786 struct hdcp2_dp_msg_data {
6787         u8 msg_id;
6788         u32 offset;
6789         bool msg_detectable;
6790         u32 timeout;
6791         u32 timeout2; /* Added for non_paired situation */
6792 };
6793
6794 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6795         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6796         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6797           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6798         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6799           false, 0, 0 },
6800         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6801           false, 0, 0 },
6802         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6803           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6804           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6805         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6806           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6807           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6808         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6809         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6810           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6811         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6812           0, 0 },
6813         { HDCP_2_2_REP_SEND_RECVID_LIST,
6814           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6815           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6816         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6817           0, 0 },
6818         { HDCP_2_2_REP_STREAM_MANAGE,
6819           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6820           0, 0 },
6821         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6822           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6823 /* local define to shovel this through the write_2_2 interface */
6824 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
6825         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6826           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6827           0, 0 },
6828 };
6829
6830 static inline
6831 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6832                                   u8 *rx_status)
6833 {
6834         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6835         ssize_t ret;
6836
6837         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6838                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6839                                HDCP_2_2_DP_RXSTATUS_LEN);
6840         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6841                 drm_dbg_kms(&i915->drm,
6842                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6843                 return ret >= 0 ? -EIO : ret;
6844         }
6845
6846         return 0;
6847 }
6848
6849 static
6850 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6851                                   u8 msg_id, bool *msg_ready)
6852 {
6853         u8 rx_status;
6854         int ret;
6855
6856         *msg_ready = false;
6857         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6858         if (ret < 0)
6859                 return ret;
6860
6861         switch (msg_id) {
6862         case HDCP_2_2_AKE_SEND_HPRIME:
6863                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6864                         *msg_ready = true;
6865                 break;
6866         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6867                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6868                         *msg_ready = true;
6869                 break;
6870         case HDCP_2_2_REP_SEND_RECVID_LIST:
6871                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6872                         *msg_ready = true;
6873                 break;
6874         default:
6875                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6876                 return -EINVAL;
6877         }
6878
6879         return 0;
6880 }
6881
6882 static ssize_t
6883 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6884                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6885 {
6886         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6887         struct intel_dp *dp = &intel_dig_port->dp;
6888         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6889         u8 msg_id = hdcp2_msg_data->msg_id;
6890         int ret, timeout;
6891         bool msg_ready = false;
6892
6893         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6894                 timeout = hdcp2_msg_data->timeout2;
6895         else
6896                 timeout = hdcp2_msg_data->timeout;
6897
6898         /*
6899          * There is no way to detect the CERT, LPRIME and STREAM_READY
6900          * availability. So Wait for timeout and read the msg.
6901          */
6902         if (!hdcp2_msg_data->msg_detectable) {
6903                 mdelay(timeout);
6904                 ret = 0;
6905         } else {
6906                 /*
6907                  * As we want to check the msg availability at timeout, Ignoring
6908                  * the timeout at wait for CP_IRQ.
6909                  */
6910                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6911                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6912                                                     msg_id, &msg_ready);
6913                 if (!msg_ready)
6914                         ret = -ETIMEDOUT;
6915         }
6916
6917         if (ret)
6918                 drm_dbg_kms(&i915->drm,
6919                             "msg_id %d, ret %d, timeout(mSec): %d\n",
6920                             hdcp2_msg_data->msg_id, ret, timeout);
6921
6922         return ret;
6923 }
6924
6925 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6926 {
6927         int i;
6928
6929         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6930                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6931                         return &hdcp2_dp_msg_data[i];
6932
6933         return NULL;
6934 }
6935
6936 static
6937 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6938                              void *buf, size_t size)
6939 {
6940         struct intel_dp *dp = &intel_dig_port->dp;
6941         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6942         unsigned int offset;
6943         u8 *byte = buf;
6944         ssize_t ret, bytes_to_write, len;
6945         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6946
6947         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6948         if (!hdcp2_msg_data)
6949                 return -EINVAL;
6950
6951         offset = hdcp2_msg_data->offset;
6952
6953         /* No msg_id in DP HDCP2.2 msgs */
6954         bytes_to_write = size - 1;
6955         byte++;
6956
6957         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6958
6959         while (bytes_to_write) {
6960                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6961                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6962
6963                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6964                                         offset, (void *)byte, len);
6965                 if (ret < 0)
6966                         return ret;
6967
6968                 bytes_to_write -= ret;
6969                 byte += ret;
6970                 offset += ret;
6971         }
6972
6973         return size;
6974 }
6975
6976 static
6977 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6978 {
6979         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6980         u32 dev_cnt;
6981         ssize_t ret;
6982
6983         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6984                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6985                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6986         if (ret != HDCP_2_2_RXINFO_LEN)
6987                 return ret >= 0 ? -EIO : ret;
6988
6989         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6990                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6991
6992         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6993                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6994
6995         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6996                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6997                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6998
6999         return ret;
7000 }
7001
7002 static
7003 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
7004                             u8 msg_id, void *buf, size_t size)
7005 {
7006         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7007         unsigned int offset;
7008         u8 *byte = buf;
7009         ssize_t ret, bytes_to_recv, len;
7010         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
7011
7012         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
7013         if (!hdcp2_msg_data)
7014                 return -EINVAL;
7015         offset = hdcp2_msg_data->offset;
7016
7017         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
7018         if (ret < 0)
7019                 return ret;
7020
7021         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
7022                 ret = get_receiver_id_list_size(intel_dig_port);
7023                 if (ret < 0)
7024                         return ret;
7025
7026                 size = ret;
7027         }
7028         bytes_to_recv = size - 1;
7029
7030         /* DP adaptation msgs has no msg_id */
7031         byte++;
7032
7033         while (bytes_to_recv) {
7034                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
7035                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
7036
7037                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
7038                                        (void *)byte, len);
7039                 if (ret < 0) {
7040                         drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
7041                                     msg_id, ret);
7042                         return ret;
7043                 }
7044
7045                 bytes_to_recv -= ret;
7046                 byte += ret;
7047                 offset += ret;
7048         }
7049         byte = buf;
7050         *byte = msg_id;
7051
7052         return size;
7053 }
7054
7055 static
7056 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
7057                                       bool is_repeater, u8 content_type)
7058 {
7059         int ret;
7060         struct hdcp2_dp_errata_stream_type stream_type_msg;
7061
7062         if (is_repeater)
7063                 return 0;
7064
7065         /*
7066          * Errata for DP: As Stream type is used for encryption, Receiver
7067          * should be communicated with stream type for the decryption of the
7068          * content.
7069          * Repeater will be communicated with stream type as a part of it's
7070          * auth later in time.
7071          */
7072         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
7073         stream_type_msg.stream_type = content_type;
7074
7075         ret =  intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
7076                                         sizeof(stream_type_msg));
7077
7078         return ret < 0 ? ret : 0;
7079
7080 }
7081
7082 static
7083 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
7084 {
7085         u8 rx_status;
7086         int ret;
7087
7088         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
7089         if (ret)
7090                 return ret;
7091
7092         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
7093                 ret = HDCP_REAUTH_REQUEST;
7094         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
7095                 ret = HDCP_LINK_INTEGRITY_FAILURE;
7096         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
7097                 ret = HDCP_TOPOLOGY_CHANGE;
7098
7099         return ret;
7100 }
7101
7102 static
7103 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
7104                            bool *capable)
7105 {
7106         u8 rx_caps[3];
7107         int ret;
7108
7109         *capable = false;
7110         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
7111                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
7112                                rx_caps, HDCP_2_2_RXCAPS_LEN);
7113         if (ret != HDCP_2_2_RXCAPS_LEN)
7114                 return ret >= 0 ? -EIO : ret;
7115
7116         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
7117             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
7118                 *capable = true;
7119
7120         return 0;
7121 }
7122
7123 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
7124         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
7125         .read_bksv = intel_dp_hdcp_read_bksv,
7126         .read_bstatus = intel_dp_hdcp_read_bstatus,
7127         .repeater_present = intel_dp_hdcp_repeater_present,
7128         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
7129         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
7130         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
7131         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
7132         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
7133         .check_link = intel_dp_hdcp_check_link,
7134         .hdcp_capable = intel_dp_hdcp_capable,
7135         .write_2_2_msg = intel_dp_hdcp2_write_msg,
7136         .read_2_2_msg = intel_dp_hdcp2_read_msg,
7137         .config_stream_type = intel_dp_hdcp2_config_stream_type,
7138         .check_2_2_link = intel_dp_hdcp2_check_link,
7139         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
7140         .protocol = HDCP_PROTOCOL_DP,
7141 };
7142
7143 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7144 {
7145         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7146         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7147
7148         lockdep_assert_held(&dev_priv->pps_mutex);
7149
7150         if (!edp_have_panel_vdd(intel_dp))
7151                 return;
7152
7153         /*
7154          * The VDD bit needs a power domain reference, so if the bit is
7155          * already enabled when we boot or resume, grab this reference and
7156          * schedule a vdd off, so we don't hold on to the reference
7157          * indefinitely.
7158          */
7159         drm_dbg_kms(&dev_priv->drm,
7160                     "VDD left on by BIOS, adjusting state tracking\n");
7161         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7162
7163         edp_panel_vdd_schedule_off(intel_dp);
7164 }
7165
7166 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7167 {
7168         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7169         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7170         enum pipe pipe;
7171
7172         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7173                                   encoder->port, &pipe))
7174                 return pipe;
7175
7176         return INVALID_PIPE;
7177 }
7178
7179 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7180 {
7181         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7182         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7183         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7184         intel_wakeref_t wakeref;
7185
7186         if (!HAS_DDI(dev_priv))
7187                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7188
7189         if (lspcon->active)
7190                 lspcon_resume(lspcon);
7191
7192         intel_dp->reset_link_params = true;
7193
7194         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7195             !intel_dp_is_edp(intel_dp))
7196                 return;
7197
7198         with_pps_lock(intel_dp, wakeref) {
7199                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7200                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7201
7202                 if (intel_dp_is_edp(intel_dp)) {
7203                         /*
7204                          * Reinit the power sequencer, in case BIOS did
7205                          * something nasty with it.
7206                          */
7207                         intel_dp_pps_init(intel_dp);
7208                         intel_edp_panel_vdd_sanitize(intel_dp);
7209                 }
7210         }
7211 }
7212
7213 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7214                                     int tile_group_id)
7215 {
7216         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7217         struct drm_connector_list_iter conn_iter;
7218         struct drm_connector *connector;
7219         int ret = 0;
7220
7221         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7222         drm_for_each_connector_iter(connector, &conn_iter) {
7223                 struct drm_connector_state *conn_state;
7224                 struct intel_crtc_state *crtc_state;
7225                 struct intel_crtc *crtc;
7226
7227                 if (!connector->has_tile ||
7228                     connector->tile_group->id != tile_group_id)
7229                         continue;
7230
7231                 conn_state = drm_atomic_get_connector_state(&state->base,
7232                                                             connector);
7233                 if (IS_ERR(conn_state)) {
7234                         ret = PTR_ERR(conn_state);
7235                         break;
7236                 }
7237
7238                 crtc = to_intel_crtc(conn_state->crtc);
7239
7240                 if (!crtc)
7241                         continue;
7242
7243                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7244                 crtc_state->uapi.mode_changed = true;
7245
7246                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7247                 if (ret)
7248                         break;
7249         }
7250         drm_connector_list_iter_end(&conn_iter);
7251
7252         return ret;
7253 }
7254
7255 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7256 {
7257         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7258         struct intel_crtc *crtc;
7259
7260         if (transcoders == 0)
7261                 return 0;
7262
7263         for_each_intel_crtc(&dev_priv->drm, crtc) {
7264                 struct intel_crtc_state *crtc_state;
7265                 int ret;
7266
7267                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7268                 if (IS_ERR(crtc_state))
7269                         return PTR_ERR(crtc_state);
7270
7271                 if (!crtc_state->hw.enable)
7272                         continue;
7273
7274                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7275                         continue;
7276
7277                 crtc_state->uapi.mode_changed = true;
7278
7279                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7280                 if (ret)
7281                         return ret;
7282
7283                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7284                 if (ret)
7285                         return ret;
7286
7287                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7288         }
7289
7290         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7291
7292         return 0;
7293 }
7294
7295 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7296                                       struct drm_connector *connector)
7297 {
7298         const struct drm_connector_state *old_conn_state =
7299                 drm_atomic_get_old_connector_state(&state->base, connector);
7300         const struct intel_crtc_state *old_crtc_state;
7301         struct intel_crtc *crtc;
7302         u8 transcoders;
7303
7304         crtc = to_intel_crtc(old_conn_state->crtc);
7305         if (!crtc)
7306                 return 0;
7307
7308         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7309
7310         if (!old_crtc_state->hw.active)
7311                 return 0;
7312
7313         transcoders = old_crtc_state->sync_mode_slaves_mask;
7314         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7315                 transcoders |= BIT(old_crtc_state->master_transcoder);
7316
7317         return intel_modeset_affected_transcoders(state,
7318                                                   transcoders);
7319 }
7320
7321 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7322                                            struct drm_atomic_state *_state)
7323 {
7324         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7325         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7326         int ret;
7327
7328         ret = intel_digital_connector_atomic_check(conn, &state->base);
7329         if (ret)
7330                 return ret;
7331
7332         /*
7333          * We don't enable port sync on BDW due to missing w/as and
7334          * due to not having adjusted the modeset sequence appropriately.
7335          */
7336         if (INTEL_GEN(dev_priv) < 9)
7337                 return 0;
7338
7339         if (!intel_connector_needs_modeset(state, conn))
7340                 return 0;
7341
7342         if (conn->has_tile) {
7343                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7344                 if (ret)
7345                         return ret;
7346         }
7347
7348         return intel_modeset_synced_crtcs(state, conn);
7349 }
7350
7351 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7352         .force = intel_dp_force,
7353         .fill_modes = drm_helper_probe_single_connector_modes,
7354         .atomic_get_property = intel_digital_connector_atomic_get_property,
7355         .atomic_set_property = intel_digital_connector_atomic_set_property,
7356         .late_register = intel_dp_connector_register,
7357         .early_unregister = intel_dp_connector_unregister,
7358         .destroy = intel_connector_destroy,
7359         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7360         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7361 };
7362
7363 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7364         .detect_ctx = intel_dp_detect,
7365         .get_modes = intel_dp_get_modes,
7366         .mode_valid = intel_dp_mode_valid,
7367         .atomic_check = intel_dp_connector_atomic_check,
7368 };
7369
7370 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7371         .reset = intel_dp_encoder_reset,
7372         .destroy = intel_dp_encoder_destroy,
7373 };
7374
7375 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7376 {
7377         intel_wakeref_t wakeref;
7378         bool have_power = false;
7379
7380         with_pps_lock(intel_dp, wakeref) {
7381                 have_power = edp_have_panel_power(intel_dp) &&
7382                                                   edp_have_panel_vdd(intel_dp);
7383         }
7384
7385         return have_power;
7386 }
7387
7388 enum irqreturn
7389 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7390 {
7391         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7392         struct intel_dp *intel_dp = &intel_dig_port->dp;
7393
7394         if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7395             (long_hpd || !intel_edp_have_power(intel_dp))) {
7396                 /*
7397                  * vdd off can generate a long/short pulse on eDP which
7398                  * would require vdd on to handle it, and thus we
7399                  * would end up in an endless cycle of
7400                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7401                  */
7402                 drm_dbg_kms(&i915->drm,
7403                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7404                             long_hpd ? "long" : "short",
7405                             intel_dig_port->base.base.base.id,
7406                             intel_dig_port->base.base.name);
7407                 return IRQ_HANDLED;
7408         }
7409
7410         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7411                     intel_dig_port->base.base.base.id,
7412                     intel_dig_port->base.base.name,
7413                     long_hpd ? "long" : "short");
7414
7415         if (long_hpd) {
7416                 intel_dp->reset_link_params = true;
7417                 return IRQ_NONE;
7418         }
7419
7420         if (intel_dp->is_mst) {
7421                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
7422                         /*
7423                          * If we were in MST mode, and device is not
7424                          * there, get out of MST mode
7425                          */
7426                         drm_dbg_kms(&i915->drm,
7427                                     "MST device may have disappeared %d vs %d\n",
7428                                     intel_dp->is_mst,
7429                                     intel_dp->mst_mgr.mst_state);
7430                         intel_dp->is_mst = false;
7431                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7432                                                         intel_dp->is_mst);
7433
7434                         return IRQ_NONE;
7435                 }
7436         }
7437
7438         if (!intel_dp->is_mst) {
7439                 bool handled;
7440
7441                 handled = intel_dp_short_pulse(intel_dp);
7442
7443                 if (!handled)
7444                         return IRQ_NONE;
7445         }
7446
7447         return IRQ_HANDLED;
7448 }
7449
7450 /* check the VBT to see whether the eDP is on another port */
7451 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7452 {
7453         /*
7454          * eDP not supported on g4x. so bail out early just
7455          * for a bit extra safety in case the VBT is bonkers.
7456          */
7457         if (INTEL_GEN(dev_priv) < 5)
7458                 return false;
7459
7460         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7461                 return true;
7462
7463         return intel_bios_is_port_edp(dev_priv, port);
7464 }
7465
7466 static void
7467 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7468 {
7469         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7470         enum port port = dp_to_dig_port(intel_dp)->base.port;
7471
7472         if (!IS_G4X(dev_priv) && port != PORT_A)
7473                 intel_attach_force_audio_property(connector);
7474
7475         intel_attach_broadcast_rgb_property(connector);
7476         if (HAS_GMCH(dev_priv))
7477                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7478         else if (INTEL_GEN(dev_priv) >= 5)
7479                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7480
7481         intel_attach_colorspace_property(connector);
7482
7483         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7484                 drm_object_attach_property(&connector->base,
7485                                            connector->dev->mode_config.hdr_output_metadata_property,
7486                                            0);
7487
7488         if (intel_dp_is_edp(intel_dp)) {
7489                 u32 allowed_scalers;
7490
7491                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7492                 if (!HAS_GMCH(dev_priv))
7493                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7494
7495                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7496
7497                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7498
7499         }
7500 }
7501
7502 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7503 {
7504         intel_dp->panel_power_off_time = ktime_get_boottime();
7505         intel_dp->last_power_on = jiffies;
7506         intel_dp->last_backlight_off = jiffies;
7507 }
7508
7509 static void
7510 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7511 {
7512         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7513         u32 pp_on, pp_off, pp_ctl;
7514         struct pps_registers regs;
7515
7516         intel_pps_get_registers(intel_dp, &regs);
7517
7518         pp_ctl = ilk_get_pp_control(intel_dp);
7519
7520         /* Ensure PPS is unlocked */
7521         if (!HAS_DDI(dev_priv))
7522                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7523
7524         pp_on = intel_de_read(dev_priv, regs.pp_on);
7525         pp_off = intel_de_read(dev_priv, regs.pp_off);
7526
7527         /* Pull timing values out of registers */
7528         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7529         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7530         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7531         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7532
7533         if (i915_mmio_reg_valid(regs.pp_div)) {
7534                 u32 pp_div;
7535
7536                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7537
7538                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7539         } else {
7540                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7541         }
7542 }
7543
7544 static void
7545 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7546 {
7547         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7548                       state_name,
7549                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7550 }
7551
7552 static void
7553 intel_pps_verify_state(struct intel_dp *intel_dp)
7554 {
7555         struct edp_power_seq hw;
7556         struct edp_power_seq *sw = &intel_dp->pps_delays;
7557
7558         intel_pps_readout_hw_state(intel_dp, &hw);
7559
7560         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7561             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7562                 DRM_ERROR("PPS state mismatch\n");
7563                 intel_pps_dump_state("sw", sw);
7564                 intel_pps_dump_state("hw", &hw);
7565         }
7566 }
7567
7568 static void
7569 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7570 {
7571         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7572         struct edp_power_seq cur, vbt, spec,
7573                 *final = &intel_dp->pps_delays;
7574
7575         lockdep_assert_held(&dev_priv->pps_mutex);
7576
7577         /* already initialized? */
7578         if (final->t11_t12 != 0)
7579                 return;
7580
7581         intel_pps_readout_hw_state(intel_dp, &cur);
7582
7583         intel_pps_dump_state("cur", &cur);
7584
7585         vbt = dev_priv->vbt.edp.pps;
7586         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7587          * of 500ms appears to be too short. Ocassionally the panel
7588          * just fails to power back on. Increasing the delay to 800ms
7589          * seems sufficient to avoid this problem.
7590          */
7591         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7592                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7593                 drm_dbg_kms(&dev_priv->drm,
7594                             "Increasing T12 panel delay as per the quirk to %d\n",
7595                             vbt.t11_t12);
7596         }
7597         /* T11_T12 delay is special and actually in units of 100ms, but zero
7598          * based in the hw (so we need to add 100 ms). But the sw vbt
7599          * table multiplies it with 1000 to make it in units of 100usec,
7600          * too. */
7601         vbt.t11_t12 += 100 * 10;
7602
7603         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7604          * our hw here, which are all in 100usec. */
7605         spec.t1_t3 = 210 * 10;
7606         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7607         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7608         spec.t10 = 500 * 10;
7609         /* This one is special and actually in units of 100ms, but zero
7610          * based in the hw (so we need to add 100 ms). But the sw vbt
7611          * table multiplies it with 1000 to make it in units of 100usec,
7612          * too. */
7613         spec.t11_t12 = (510 + 100) * 10;
7614
7615         intel_pps_dump_state("vbt", &vbt);
7616
7617         /* Use the max of the register settings and vbt. If both are
7618          * unset, fall back to the spec limits. */
7619 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7620                                        spec.field : \
7621                                        max(cur.field, vbt.field))
7622         assign_final(t1_t3);
7623         assign_final(t8);
7624         assign_final(t9);
7625         assign_final(t10);
7626         assign_final(t11_t12);
7627 #undef assign_final
7628
7629 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7630         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7631         intel_dp->backlight_on_delay = get_delay(t8);
7632         intel_dp->backlight_off_delay = get_delay(t9);
7633         intel_dp->panel_power_down_delay = get_delay(t10);
7634         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7635 #undef get_delay
7636
7637         drm_dbg_kms(&dev_priv->drm,
7638                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7639                     intel_dp->panel_power_up_delay,
7640                     intel_dp->panel_power_down_delay,
7641                     intel_dp->panel_power_cycle_delay);
7642
7643         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7644                     intel_dp->backlight_on_delay,
7645                     intel_dp->backlight_off_delay);
7646
7647         /*
7648          * We override the HW backlight delays to 1 because we do manual waits
7649          * on them. For T8, even BSpec recommends doing it. For T9, if we
7650          * don't do this, we'll end up waiting for the backlight off delay
7651          * twice: once when we do the manual sleep, and once when we disable
7652          * the panel and wait for the PP_STATUS bit to become zero.
7653          */
7654         final->t8 = 1;
7655         final->t9 = 1;
7656
7657         /*
7658          * HW has only a 100msec granularity for t11_t12 so round it up
7659          * accordingly.
7660          */
7661         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7662 }
7663
7664 static void
7665 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7666                                               bool force_disable_vdd)
7667 {
7668         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7669         u32 pp_on, pp_off, port_sel = 0;
7670         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7671         struct pps_registers regs;
7672         enum port port = dp_to_dig_port(intel_dp)->base.port;
7673         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7674
7675         lockdep_assert_held(&dev_priv->pps_mutex);
7676
7677         intel_pps_get_registers(intel_dp, &regs);
7678
7679         /*
7680          * On some VLV machines the BIOS can leave the VDD
7681          * enabled even on power sequencers which aren't
7682          * hooked up to any port. This would mess up the
7683          * power domain tracking the first time we pick
7684          * one of these power sequencers for use since
7685          * edp_panel_vdd_on() would notice that the VDD was
7686          * already on and therefore wouldn't grab the power
7687          * domain reference. Disable VDD first to avoid this.
7688          * This also avoids spuriously turning the VDD on as
7689          * soon as the new power sequencer gets initialized.
7690          */
7691         if (force_disable_vdd) {
7692                 u32 pp = ilk_get_pp_control(intel_dp);
7693
7694                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7695                          "Panel power already on\n");
7696
7697                 if (pp & EDP_FORCE_VDD)
7698                         drm_dbg_kms(&dev_priv->drm,
7699                                     "VDD already on, disabling first\n");
7700
7701                 pp &= ~EDP_FORCE_VDD;
7702
7703                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7704         }
7705
7706         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7707                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7708         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7709                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7710
7711         /* Haswell doesn't have any port selection bits for the panel
7712          * power sequencer any more. */
7713         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7714                 port_sel = PANEL_PORT_SELECT_VLV(port);
7715         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7716                 switch (port) {
7717                 case PORT_A:
7718                         port_sel = PANEL_PORT_SELECT_DPA;
7719                         break;
7720                 case PORT_C:
7721                         port_sel = PANEL_PORT_SELECT_DPC;
7722                         break;
7723                 case PORT_D:
7724                         port_sel = PANEL_PORT_SELECT_DPD;
7725                         break;
7726                 default:
7727                         MISSING_CASE(port);
7728                         break;
7729                 }
7730         }
7731
7732         pp_on |= port_sel;
7733
7734         intel_de_write(dev_priv, regs.pp_on, pp_on);
7735         intel_de_write(dev_priv, regs.pp_off, pp_off);
7736
7737         /*
7738          * Compute the divisor for the pp clock, simply match the Bspec formula.
7739          */
7740         if (i915_mmio_reg_valid(regs.pp_div)) {
7741                 intel_de_write(dev_priv, regs.pp_div,
7742                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7743         } else {
7744                 u32 pp_ctl;
7745
7746                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7747                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7748                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7749                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7750         }
7751
7752         drm_dbg_kms(&dev_priv->drm,
7753                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7754                     intel_de_read(dev_priv, regs.pp_on),
7755                     intel_de_read(dev_priv, regs.pp_off),
7756                     i915_mmio_reg_valid(regs.pp_div) ?
7757                     intel_de_read(dev_priv, regs.pp_div) :
7758                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7759 }
7760
7761 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7762 {
7763         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7764
7765         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7766                 vlv_initial_power_sequencer_setup(intel_dp);
7767         } else {
7768                 intel_dp_init_panel_power_sequencer(intel_dp);
7769                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7770         }
7771 }
7772
7773 /**
7774  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7775  * @dev_priv: i915 device
7776  * @crtc_state: a pointer to the active intel_crtc_state
7777  * @refresh_rate: RR to be programmed
7778  *
7779  * This function gets called when refresh rate (RR) has to be changed from
7780  * one frequency to another. Switches can be between high and low RR
7781  * supported by the panel or to any other RR based on media playback (in
7782  * this case, RR value needs to be passed from user space).
7783  *
7784  * The caller of this function needs to take a lock on dev_priv->drrs.
7785  */
7786 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7787                                     const struct intel_crtc_state *crtc_state,
7788                                     int refresh_rate)
7789 {
7790         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7792         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7793
7794         if (refresh_rate <= 0) {
7795                 drm_dbg_kms(&dev_priv->drm,
7796                             "Refresh rate should be positive non-zero.\n");
7797                 return;
7798         }
7799
7800         if (intel_dp == NULL) {
7801                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7802                 return;
7803         }
7804
7805         if (!intel_crtc) {
7806                 drm_dbg_kms(&dev_priv->drm,
7807                             "DRRS: intel_crtc not initialized\n");
7808                 return;
7809         }
7810
7811         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7812                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7813                 return;
7814         }
7815
7816         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7817                         refresh_rate)
7818                 index = DRRS_LOW_RR;
7819
7820         if (index == dev_priv->drrs.refresh_rate_type) {
7821                 drm_dbg_kms(&dev_priv->drm,
7822                             "DRRS requested for previously set RR...ignoring\n");
7823                 return;
7824         }
7825
7826         if (!crtc_state->hw.active) {
7827                 drm_dbg_kms(&dev_priv->drm,
7828                             "eDP encoder disabled. CRTC not Active\n");
7829                 return;
7830         }
7831
7832         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7833                 switch (index) {
7834                 case DRRS_HIGH_RR:
7835                         intel_dp_set_m_n(crtc_state, M1_N1);
7836                         break;
7837                 case DRRS_LOW_RR:
7838                         intel_dp_set_m_n(crtc_state, M2_N2);
7839                         break;
7840                 case DRRS_MAX_RR:
7841                 default:
7842                         drm_err(&dev_priv->drm,
7843                                 "Unsupported refreshrate type\n");
7844                 }
7845         } else if (INTEL_GEN(dev_priv) > 6) {
7846                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7847                 u32 val;
7848
7849                 val = intel_de_read(dev_priv, reg);
7850                 if (index > DRRS_HIGH_RR) {
7851                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7852                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7853                         else
7854                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7855                 } else {
7856                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7857                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7858                         else
7859                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7860                 }
7861                 intel_de_write(dev_priv, reg, val);
7862         }
7863
7864         dev_priv->drrs.refresh_rate_type = index;
7865
7866         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7867                     refresh_rate);
7868 }
7869
7870 /**
7871  * intel_edp_drrs_enable - init drrs struct if supported
7872  * @intel_dp: DP struct
7873  * @crtc_state: A pointer to the active crtc state.
7874  *
7875  * Initializes frontbuffer_bits and drrs.dp
7876  */
7877 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7878                            const struct intel_crtc_state *crtc_state)
7879 {
7880         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7881
7882         if (!crtc_state->has_drrs) {
7883                 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7884                 return;
7885         }
7886
7887         if (dev_priv->psr.enabled) {
7888                 drm_dbg_kms(&dev_priv->drm,
7889                             "PSR enabled. Not enabling DRRS.\n");
7890                 return;
7891         }
7892
7893         mutex_lock(&dev_priv->drrs.mutex);
7894         if (dev_priv->drrs.dp) {
7895                 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7896                 goto unlock;
7897         }
7898
7899         dev_priv->drrs.busy_frontbuffer_bits = 0;
7900
7901         dev_priv->drrs.dp = intel_dp;
7902
7903 unlock:
7904         mutex_unlock(&dev_priv->drrs.mutex);
7905 }
7906
7907 /**
7908  * intel_edp_drrs_disable - Disable DRRS
7909  * @intel_dp: DP struct
7910  * @old_crtc_state: Pointer to old crtc_state.
7911  *
7912  */
7913 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7914                             const struct intel_crtc_state *old_crtc_state)
7915 {
7916         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7917
7918         if (!old_crtc_state->has_drrs)
7919                 return;
7920
7921         mutex_lock(&dev_priv->drrs.mutex);
7922         if (!dev_priv->drrs.dp) {
7923                 mutex_unlock(&dev_priv->drrs.mutex);
7924                 return;
7925         }
7926
7927         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7928                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7929                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7930
7931         dev_priv->drrs.dp = NULL;
7932         mutex_unlock(&dev_priv->drrs.mutex);
7933
7934         cancel_delayed_work_sync(&dev_priv->drrs.work);
7935 }
7936
7937 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7938 {
7939         struct drm_i915_private *dev_priv =
7940                 container_of(work, typeof(*dev_priv), drrs.work.work);
7941         struct intel_dp *intel_dp;
7942
7943         mutex_lock(&dev_priv->drrs.mutex);
7944
7945         intel_dp = dev_priv->drrs.dp;
7946
7947         if (!intel_dp)
7948                 goto unlock;
7949
7950         /*
7951          * The delayed work can race with an invalidate hence we need to
7952          * recheck.
7953          */
7954
7955         if (dev_priv->drrs.busy_frontbuffer_bits)
7956                 goto unlock;
7957
7958         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7959                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7960
7961                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7962                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7963         }
7964
7965 unlock:
7966         mutex_unlock(&dev_priv->drrs.mutex);
7967 }
7968
7969 /**
7970  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7971  * @dev_priv: i915 device
7972  * @frontbuffer_bits: frontbuffer plane tracking bits
7973  *
7974  * This function gets called everytime rendering on the given planes start.
7975  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7976  *
7977  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7978  */
7979 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7980                                unsigned int frontbuffer_bits)
7981 {
7982         struct drm_crtc *crtc;
7983         enum pipe pipe;
7984
7985         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7986                 return;
7987
7988         cancel_delayed_work(&dev_priv->drrs.work);
7989
7990         mutex_lock(&dev_priv->drrs.mutex);
7991         if (!dev_priv->drrs.dp) {
7992                 mutex_unlock(&dev_priv->drrs.mutex);
7993                 return;
7994         }
7995
7996         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7997         pipe = to_intel_crtc(crtc)->pipe;
7998
7999         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8000         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
8001
8002         /* invalidate means busy screen hence upclock */
8003         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8004                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8005                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8006
8007         mutex_unlock(&dev_priv->drrs.mutex);
8008 }
8009
8010 /**
8011  * intel_edp_drrs_flush - Restart Idleness DRRS
8012  * @dev_priv: i915 device
8013  * @frontbuffer_bits: frontbuffer plane tracking bits
8014  *
8015  * This function gets called every time rendering on the given planes has
8016  * completed or flip on a crtc is completed. So DRRS should be upclocked
8017  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
8018  * if no other planes are dirty.
8019  *
8020  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8021  */
8022 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
8023                           unsigned int frontbuffer_bits)
8024 {
8025         struct drm_crtc *crtc;
8026         enum pipe pipe;
8027
8028         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8029                 return;
8030
8031         cancel_delayed_work(&dev_priv->drrs.work);
8032
8033         mutex_lock(&dev_priv->drrs.mutex);
8034         if (!dev_priv->drrs.dp) {
8035                 mutex_unlock(&dev_priv->drrs.mutex);
8036                 return;
8037         }
8038
8039         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
8040         pipe = to_intel_crtc(crtc)->pipe;
8041
8042         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8043         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
8044
8045         /* flush means busy screen hence upclock */
8046         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8047                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8048                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8049
8050         /*
8051          * flush also means no more activity hence schedule downclock, if all
8052          * other fbs are quiescent too
8053          */
8054         if (!dev_priv->drrs.busy_frontbuffer_bits)
8055                 schedule_delayed_work(&dev_priv->drrs.work,
8056                                 msecs_to_jiffies(1000));
8057         mutex_unlock(&dev_priv->drrs.mutex);
8058 }
8059
8060 /**
8061  * DOC: Display Refresh Rate Switching (DRRS)
8062  *
8063  * Display Refresh Rate Switching (DRRS) is a power conservation feature
8064  * which enables swtching between low and high refresh rates,
8065  * dynamically, based on the usage scenario. This feature is applicable
8066  * for internal panels.
8067  *
8068  * Indication that the panel supports DRRS is given by the panel EDID, which
8069  * would list multiple refresh rates for one resolution.
8070  *
8071  * DRRS is of 2 types - static and seamless.
8072  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
8073  * (may appear as a blink on screen) and is used in dock-undock scenario.
8074  * Seamless DRRS involves changing RR without any visual effect to the user
8075  * and can be used during normal system usage. This is done by programming
8076  * certain registers.
8077  *
8078  * Support for static/seamless DRRS may be indicated in the VBT based on
8079  * inputs from the panel spec.
8080  *
8081  * DRRS saves power by switching to low RR based on usage scenarios.
8082  *
8083  * The implementation is based on frontbuffer tracking implementation.  When
8084  * there is a disturbance on the screen triggered by user activity or a periodic
8085  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
8086  * no movement on screen, after a timeout of 1 second, a switch to low RR is
8087  * made.
8088  *
8089  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8090  * and intel_edp_drrs_flush() are called.
8091  *
8092  * DRRS can be further extended to support other internal panels and also
8093  * the scenario of video playback wherein RR is set based on the rate
8094  * requested by userspace.
8095  */
8096
8097 /**
8098  * intel_dp_drrs_init - Init basic DRRS work and mutex.
8099  * @connector: eDP connector
8100  * @fixed_mode: preferred mode of panel
8101  *
8102  * This function is  called only once at driver load to initialize basic
8103  * DRRS stuff.
8104  *
8105  * Returns:
8106  * Downclock mode if panel supports it, else return NULL.
8107  * DRRS support is determined by the presence of downclock mode (apart
8108  * from VBT setting).
8109  */
8110 static struct drm_display_mode *
8111 intel_dp_drrs_init(struct intel_connector *connector,
8112                    struct drm_display_mode *fixed_mode)
8113 {
8114         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8115         struct drm_display_mode *downclock_mode = NULL;
8116
8117         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8118         mutex_init(&dev_priv->drrs.mutex);
8119
8120         if (INTEL_GEN(dev_priv) <= 6) {
8121                 drm_dbg_kms(&dev_priv->drm,
8122                             "DRRS supported for Gen7 and above\n");
8123                 return NULL;
8124         }
8125
8126         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8127                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8128                 return NULL;
8129         }
8130
8131         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8132         if (!downclock_mode) {
8133                 drm_dbg_kms(&dev_priv->drm,
8134                             "Downclock mode is not found. DRRS not supported\n");
8135                 return NULL;
8136         }
8137
8138         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8139
8140         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8141         drm_dbg_kms(&dev_priv->drm,
8142                     "seamless DRRS supported for eDP panel.\n");
8143         return downclock_mode;
8144 }
8145
8146 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8147                                      struct intel_connector *intel_connector)
8148 {
8149         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8150         struct drm_device *dev = &dev_priv->drm;
8151         struct drm_connector *connector = &intel_connector->base;
8152         struct drm_display_mode *fixed_mode = NULL;
8153         struct drm_display_mode *downclock_mode = NULL;
8154         bool has_dpcd;
8155         enum pipe pipe = INVALID_PIPE;
8156         intel_wakeref_t wakeref;
8157         struct edid *edid;
8158
8159         if (!intel_dp_is_edp(intel_dp))
8160                 return true;
8161
8162         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8163
8164         /*
8165          * On IBX/CPT we may get here with LVDS already registered. Since the
8166          * driver uses the only internal power sequencer available for both
8167          * eDP and LVDS bail out early in this case to prevent interfering
8168          * with an already powered-on LVDS power sequencer.
8169          */
8170         if (intel_get_lvds_encoder(dev_priv)) {
8171                 drm_WARN_ON(dev,
8172                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8173                 drm_info(&dev_priv->drm,
8174                          "LVDS was detected, not registering eDP\n");
8175
8176                 return false;
8177         }
8178
8179         with_pps_lock(intel_dp, wakeref) {
8180                 intel_dp_init_panel_power_timestamps(intel_dp);
8181                 intel_dp_pps_init(intel_dp);
8182                 intel_edp_panel_vdd_sanitize(intel_dp);
8183         }
8184
8185         /* Cache DPCD and EDID for edp. */
8186         has_dpcd = intel_edp_init_dpcd(intel_dp);
8187
8188         if (!has_dpcd) {
8189                 /* if this fails, presume the device is a ghost */
8190                 drm_info(&dev_priv->drm,
8191                          "failed to retrieve link info, disabling eDP\n");
8192                 goto out_vdd_off;
8193         }
8194
8195         mutex_lock(&dev->mode_config.mutex);
8196         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8197         if (edid) {
8198                 if (drm_add_edid_modes(connector, edid)) {
8199                         drm_connector_update_edid_property(connector, edid);
8200                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8201                 } else {
8202                         kfree(edid);
8203                         edid = ERR_PTR(-EINVAL);
8204                 }
8205         } else {
8206                 edid = ERR_PTR(-ENOENT);
8207         }
8208         intel_connector->edid = edid;
8209
8210         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8211         if (fixed_mode)
8212                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8213
8214         /* fallback to VBT if available for eDP */
8215         if (!fixed_mode)
8216                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8217         mutex_unlock(&dev->mode_config.mutex);
8218
8219         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8220                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8221                 register_reboot_notifier(&intel_dp->edp_notifier);
8222
8223                 /*
8224                  * Figure out the current pipe for the initial backlight setup.
8225                  * If the current pipe isn't valid, try the PPS pipe, and if that
8226                  * fails just assume pipe A.
8227                  */
8228                 pipe = vlv_active_pipe(intel_dp);
8229
8230                 if (pipe != PIPE_A && pipe != PIPE_B)
8231                         pipe = intel_dp->pps_pipe;
8232
8233                 if (pipe != PIPE_A && pipe != PIPE_B)
8234                         pipe = PIPE_A;
8235
8236                 drm_dbg_kms(&dev_priv->drm,
8237                             "using pipe %c for initial backlight setup\n",
8238                             pipe_name(pipe));
8239         }
8240
8241         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8242         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8243         intel_panel_setup_backlight(connector, pipe);
8244
8245         if (fixed_mode) {
8246                 drm_connector_set_panel_orientation_with_quirk(connector,
8247                                 dev_priv->vbt.orientation,
8248                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8249         }
8250
8251         return true;
8252
8253 out_vdd_off:
8254         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8255         /*
8256          * vdd might still be enabled do to the delayed vdd off.
8257          * Make sure vdd is actually turned off here.
8258          */
8259         with_pps_lock(intel_dp, wakeref)
8260                 edp_panel_vdd_off_sync(intel_dp);
8261
8262         return false;
8263 }
8264
8265 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8266 {
8267         struct intel_connector *intel_connector;
8268         struct drm_connector *connector;
8269
8270         intel_connector = container_of(work, typeof(*intel_connector),
8271                                        modeset_retry_work);
8272         connector = &intel_connector->base;
8273         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8274                       connector->name);
8275
8276         /* Grab the locks before changing connector property*/
8277         mutex_lock(&connector->dev->mode_config.mutex);
8278         /* Set connector link status to BAD and send a Uevent to notify
8279          * userspace to do a modeset.
8280          */
8281         drm_connector_set_link_status_property(connector,
8282                                                DRM_MODE_LINK_STATUS_BAD);
8283         mutex_unlock(&connector->dev->mode_config.mutex);
8284         /* Send Hotplug uevent so userspace can reprobe */
8285         drm_kms_helper_hotplug_event(connector->dev);
8286 }
8287
8288 bool
8289 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8290                         struct intel_connector *intel_connector)
8291 {
8292         struct drm_connector *connector = &intel_connector->base;
8293         struct intel_dp *intel_dp = &intel_dig_port->dp;
8294         struct intel_encoder *intel_encoder = &intel_dig_port->base;
8295         struct drm_device *dev = intel_encoder->base.dev;
8296         struct drm_i915_private *dev_priv = to_i915(dev);
8297         enum port port = intel_encoder->port;
8298         enum phy phy = intel_port_to_phy(dev_priv, port);
8299         int type;
8300
8301         /* Initialize the work for modeset in case of link train failure */
8302         INIT_WORK(&intel_connector->modeset_retry_work,
8303                   intel_dp_modeset_retry_work_fn);
8304
8305         if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8306                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8307                      intel_dig_port->max_lanes, intel_encoder->base.base.id,
8308                      intel_encoder->base.name))
8309                 return false;
8310
8311         intel_dp_set_source_rates(intel_dp);
8312
8313         intel_dp->reset_link_params = true;
8314         intel_dp->pps_pipe = INVALID_PIPE;
8315         intel_dp->active_pipe = INVALID_PIPE;
8316
8317         /* Preserve the current hw state. */
8318         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8319         intel_dp->attached_connector = intel_connector;
8320
8321         if (intel_dp_is_port_edp(dev_priv, port)) {
8322                 /*
8323                  * Currently we don't support eDP on TypeC ports, although in
8324                  * theory it could work on TypeC legacy ports.
8325                  */
8326                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8327                 type = DRM_MODE_CONNECTOR_eDP;
8328         } else {
8329                 type = DRM_MODE_CONNECTOR_DisplayPort;
8330         }
8331
8332         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8333                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8334
8335         /*
8336          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8337          * for DP the encoder type can be set by the caller to
8338          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8339          */
8340         if (type == DRM_MODE_CONNECTOR_eDP)
8341                 intel_encoder->type = INTEL_OUTPUT_EDP;
8342
8343         /* eDP only on port B and/or C on vlv/chv */
8344         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8345                               IS_CHERRYVIEW(dev_priv)) &&
8346                         intel_dp_is_edp(intel_dp) &&
8347                         port != PORT_B && port != PORT_C))
8348                 return false;
8349
8350         drm_dbg_kms(&dev_priv->drm,
8351                     "Adding %s connector on [ENCODER:%d:%s]\n",
8352                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8353                     intel_encoder->base.base.id, intel_encoder->base.name);
8354
8355         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8356         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8357
8358         if (!HAS_GMCH(dev_priv))
8359                 connector->interlace_allowed = true;
8360         connector->doublescan_allowed = 0;
8361
8362         if (INTEL_GEN(dev_priv) >= 11)
8363                 connector->ycbcr_420_allowed = true;
8364
8365         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8366         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8367
8368         intel_dp_aux_init(intel_dp);
8369
8370         intel_connector_attach_encoder(intel_connector, intel_encoder);
8371
8372         if (HAS_DDI(dev_priv))
8373                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8374         else
8375                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8376
8377         /* init MST on ports that can support it */
8378         intel_dp_mst_encoder_init(intel_dig_port,
8379                                   intel_connector->base.base.id);
8380
8381         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8382                 intel_dp_aux_fini(intel_dp);
8383                 intel_dp_mst_encoder_cleanup(intel_dig_port);
8384                 goto fail;
8385         }
8386
8387         intel_dp_add_properties(intel_dp, connector);
8388
8389         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8390                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8391                 if (ret)
8392                         drm_dbg_kms(&dev_priv->drm,
8393                                     "HDCP init failed, skipping.\n");
8394         }
8395
8396         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8397          * 0xd.  Failure to do so will result in spurious interrupts being
8398          * generated on the port when a cable is not attached.
8399          */
8400         if (IS_G45(dev_priv)) {
8401                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8402                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8403                                (temp & ~0xf) | 0xd);
8404         }
8405
8406         return true;
8407
8408 fail:
8409         drm_connector_cleanup(connector);
8410
8411         return false;
8412 }
8413
8414 bool intel_dp_init(struct drm_i915_private *dev_priv,
8415                    i915_reg_t output_reg,
8416                    enum port port)
8417 {
8418         struct intel_digital_port *intel_dig_port;
8419         struct intel_encoder *intel_encoder;
8420         struct drm_encoder *encoder;
8421         struct intel_connector *intel_connector;
8422
8423         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8424         if (!intel_dig_port)
8425                 return false;
8426
8427         intel_connector = intel_connector_alloc();
8428         if (!intel_connector)
8429                 goto err_connector_alloc;
8430
8431         intel_encoder = &intel_dig_port->base;
8432         encoder = &intel_encoder->base;
8433
8434         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8435                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8436                              "DP %c", port_name(port)))
8437                 goto err_encoder_init;
8438
8439         intel_encoder->hotplug = intel_dp_hotplug;
8440         intel_encoder->compute_config = intel_dp_compute_config;
8441         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8442         intel_encoder->get_config = intel_dp_get_config;
8443         intel_encoder->update_pipe = intel_panel_update_backlight;
8444         intel_encoder->suspend = intel_dp_encoder_suspend;
8445         if (IS_CHERRYVIEW(dev_priv)) {
8446                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8447                 intel_encoder->pre_enable = chv_pre_enable_dp;
8448                 intel_encoder->enable = vlv_enable_dp;
8449                 intel_encoder->disable = vlv_disable_dp;
8450                 intel_encoder->post_disable = chv_post_disable_dp;
8451                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8452         } else if (IS_VALLEYVIEW(dev_priv)) {
8453                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8454                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8455                 intel_encoder->enable = vlv_enable_dp;
8456                 intel_encoder->disable = vlv_disable_dp;
8457                 intel_encoder->post_disable = vlv_post_disable_dp;
8458         } else {
8459                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8460                 intel_encoder->enable = g4x_enable_dp;
8461                 intel_encoder->disable = g4x_disable_dp;
8462                 intel_encoder->post_disable = g4x_post_disable_dp;
8463         }
8464
8465         intel_dig_port->dp.output_reg = output_reg;
8466         intel_dig_port->max_lanes = 4;
8467         intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
8468         intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
8469
8470         intel_encoder->type = INTEL_OUTPUT_DP;
8471         intel_encoder->power_domain = intel_port_to_power_domain(port);
8472         if (IS_CHERRYVIEW(dev_priv)) {
8473                 if (port == PORT_D)
8474                         intel_encoder->pipe_mask = BIT(PIPE_C);
8475                 else
8476                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8477         } else {
8478                 intel_encoder->pipe_mask = ~0;
8479         }
8480         intel_encoder->cloneable = 0;
8481         intel_encoder->port = port;
8482
8483         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8484
8485         if (port != PORT_A)
8486                 intel_infoframe_init(intel_dig_port);
8487
8488         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8489         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8490                 goto err_init_connector;
8491
8492         return true;
8493
8494 err_init_connector:
8495         drm_encoder_cleanup(encoder);
8496 err_encoder_init:
8497         kfree(intel_connector);
8498 err_connector_alloc:
8499         kfree(intel_dig_port);
8500         return false;
8501 }
8502
8503 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8504 {
8505         struct intel_encoder *encoder;
8506
8507         for_each_intel_encoder(&dev_priv->drm, encoder) {
8508                 struct intel_dp *intel_dp;
8509
8510                 if (encoder->type != INTEL_OUTPUT_DDI)
8511                         continue;
8512
8513                 intel_dp = enc_to_intel_dp(encoder);
8514
8515                 if (!intel_dp->can_mst)
8516                         continue;
8517
8518                 if (intel_dp->is_mst)
8519                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8520         }
8521 }
8522
8523 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8524 {
8525         struct intel_encoder *encoder;
8526
8527         for_each_intel_encoder(&dev_priv->drm, encoder) {
8528                 struct intel_dp *intel_dp;
8529                 int ret;
8530
8531                 if (encoder->type != INTEL_OUTPUT_DDI)
8532                         continue;
8533
8534                 intel_dp = enc_to_intel_dp(encoder);
8535
8536                 if (!intel_dp->can_mst)
8537                         continue;
8538
8539                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8540                                                      true);
8541                 if (ret) {
8542                         intel_dp->is_mst = false;
8543                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8544                                                         false);
8545                 }
8546         }
8547 }