drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  72 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  73 #define DP_DSC_MIN_SUPPORTED_BPC                8
  74 #define DP_DSC_MAX_SUPPORTED_BPC                10
  75
  76 /* DP DSC throughput values used for slice count calculations KPixels/s */
  77 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  78 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  79 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  80
  81 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  82 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  83
  84 /* Compliance test status bits  */
  85 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  86 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  88 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  89
  90 struct dp_link_dpll {
  91         int clock;
  92         struct dpll dpll;
  93 };
  94
  95 static const struct dp_link_dpll g4x_dpll[] = {
  96         { 162000,
  97                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  98         { 270000,
  99                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 100 };
 101
 102 static const struct dp_link_dpll pch_dpll[] = {
 103         { 162000,
 104                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 105         { 270000,
 106                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 107 };
 108
 109 static const struct dp_link_dpll vlv_dpll[] = {
 110         { 162000,
 111                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 112         { 270000,
 113                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 114 };
 115
 116 /*
 117  * CHV supports eDP 1.4 that have  more link rates.
 118  * Below only provides the fixed rate but exclude variable rate.
 119  */
 120 static const struct dp_link_dpll chv_dpll[] = {
 121         /*
 122          * CHV requires to program fractional division for m2.
 123          * m2 is stored in fixed point format using formula below
 124          * (m2_int << 22) | m2_fraction
 125          */
 126         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 127                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 128         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 129                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 130 };
 131
 132 /* Constants for DP DSC configurations */
 133 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 134
 135 /* With Single pipe configuration, HW is capable of supporting maximum
 136  * of 4 slices per line.
 137  */
 138 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 139
 140 /**
 141  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 142  * @intel_dp: DP struct
 143  *
 144  * If a CPU or PCH DP output is attached to an eDP panel, this function
 145  * will return true, and false otherwise.
 146  */
 147 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 150
 151         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 152 }
 153
 154 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 155 {
 156         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 157 }
 158
 159 static void intel_dp_link_down(struct intel_encoder *encoder,
 160                                const struct intel_crtc_state *old_crtc_state);
 161 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 162 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 163 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 164                                            const struct intel_crtc_state *crtc_state);
 165 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 166                                       enum pipe pipe);
 167 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 168
 169 /* update sink rates from dpcd */
 170 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 171 {
 172         static const int dp_rates[] = {
 173                 162000, 270000, 540000, 810000
 174         };
 175         int i, max_rate;
 176
 177         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 178
 179         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 180                 if (dp_rates[i] > max_rate)
 181                         break;
 182                 intel_dp->sink_rates[i] = dp_rates[i];
 183         }
 184
 185         intel_dp->num_sink_rates = i;
 186 }
 187
 188 /* Get length of rates array potentially limited by max_rate. */
 189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 190 {
 191         int i;
 192
 193         /* Limit results by potentially reduced max rate */
 194         for (i = 0; i < len; i++) {
 195                 if (rates[len - i - 1] <= max_rate)
 196                         return len - i;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /* Get length of common rates array potentially limited by max_rate. */
 203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 204                                           int max_rate)
 205 {
 206         return intel_dp_rate_limit_len(intel_dp->common_rates,
 207                                        intel_dp->num_common_rates, max_rate);
 208 }
 209
 210 /* Theoretical max between source and sink */
 211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 212 {
 213         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 214 }
 215
 216 /* Theoretical max between source and sink */
 217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 218 {
 219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 220         int source_max = intel_dig_port->max_lanes;
 221         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 222         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 223
 224         return min3(source_max, sink_max, fia_max);
 225 }
 226
 227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 228 {
 229         return intel_dp->max_link_lane_count;
 230 }
 231
 232 int
 233 intel_dp_link_required(int pixel_clock, int bpp)
 234 {
 235         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 236         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 237 }
 238
 239 int
 240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 241 {
 242         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 243          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 244          * is transmitted every LS_Clk per lane, there is no need to account for
 245          * the channel encoding that is done in the PHY layer here.
 246          */
 247
 248         return max_link_clock * max_lanes;
 249 }
 250
 251 static int
 252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 253 {
 254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 255         struct intel_encoder *encoder = &intel_dig_port->base;
 256         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257         int max_dotclk = dev_priv->max_dotclk_freq;
 258         int ds_max_dotclk;
 259
 260         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 261
 262         if (type != DP_DS_PORT_TYPE_VGA)
 263                 return max_dotclk;
 264
 265         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 266                                                     intel_dp->downstream_ports);
 267
 268         if (ds_max_dotclk != 0)
 269                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 270
 271         return max_dotclk;
 272 }
 273
 274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 275 {
 276         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 277         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 278         enum port port = dig_port->base.port;
 279
 280         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 281
 282         /* Low voltage SKUs are limited to max of 5.4G */
 283         if (voltage == VOLTAGE_INFO_0_85V)
 284                 return 540000;
 285
 286         /* For this SKU 8.1G is supported in all ports */
 287         if (IS_CNL_WITH_PORT_F(dev_priv))
 288                 return 810000;
 289
 290         /* For other SKUs, max rate on ports A and D is 5.4G */
 291         if (port == PORT_A || port == PORT_D)
 292                 return 540000;
 293
 294         return 810000;
 295 }
 296
 297 static int icl_max_source_rate(struct intel_dp *intel_dp)
 298 {
 299         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 300         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 301         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 302
 303         if (intel_phy_is_combo(dev_priv, phy) &&
 304             !IS_ELKHARTLAKE(dev_priv) &&
 305             !intel_dp_is_edp(intel_dp))
 306                 return 540000;
 307
 308         return 810000;
 309 }
 310
 311 static void
 312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 313 {
 314         /* The values must be in increasing order */
 315         static const int cnl_rates[] = {
 316                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 317         };
 318         static const int bxt_rates[] = {
 319                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 320         };
 321         static const int skl_rates[] = {
 322                 162000, 216000, 270000, 324000, 432000, 540000
 323         };
 324         static const int hsw_rates[] = {
 325                 162000, 270000, 540000
 326         };
 327         static const int g4x_rates[] = {
 328                 162000, 270000
 329         };
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 332         const struct ddi_vbt_port_info *info =
 333                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 336
 337         /* This should only be done once */
 338         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 339
 340         if (INTEL_GEN(dev_priv) >= 10) {
 341                 source_rates = cnl_rates;
 342                 size = ARRAY_SIZE(cnl_rates);
 343                 if (IS_GEN(dev_priv, 10))
 344                         max_rate = cnl_max_source_rate(intel_dp);
 345                 else
 346                         max_rate = icl_max_source_rate(intel_dp);
 347         } else if (IS_GEN9_LP(dev_priv)) {
 348                 source_rates = bxt_rates;
 349                 size = ARRAY_SIZE(bxt_rates);
 350         } else if (IS_GEN9_BC(dev_priv)) {
 351                 source_rates = skl_rates;
 352                 size = ARRAY_SIZE(skl_rates);
 353         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 354                    IS_BROADWELL(dev_priv)) {
 355                 source_rates = hsw_rates;
 356                 size = ARRAY_SIZE(hsw_rates);
 357         } else {
 358                 source_rates = g4x_rates;
 359                 size = ARRAY_SIZE(g4x_rates);
 360         }
 361
 362         if (max_rate && vbt_max_rate)
 363                 max_rate = min(max_rate, vbt_max_rate);
 364         else if (vbt_max_rate)
 365                 max_rate = vbt_max_rate;
 366
 367         if (max_rate)
 368                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 369
 370         intel_dp->source_rates = source_rates;
 371         intel_dp->num_source_rates = size;
 372 }
 373
 374 static int intersect_rates(const int *source_rates, int source_len,
 375                            const int *sink_rates, int sink_len,
 376                            int *common_rates)
 377 {
 378         int i = 0, j = 0, k = 0;
 379
 380         while (i < source_len && j < sink_len) {
 381                 if (source_rates[i] == sink_rates[j]) {
 382                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 383                                 return k;
 384                         common_rates[k] = source_rates[i];
 385                         ++k;
 386                         ++i;
 387                         ++j;
 388                 } else if (source_rates[i] < sink_rates[j]) {
 389                         ++i;
 390                 } else {
 391                         ++j;
 392                 }
 393         }
 394         return k;
 395 }
 396
 397 /* return index of rate in rates array, or -1 if not found */
 398 static int intel_dp_rate_index(const int *rates, int len, int rate)
 399 {
 400         int i;
 401
 402         for (i = 0; i < len; i++)
 403                 if (rate == rates[i])
 404                         return i;
 405
 406         return -1;
 407 }
 408
 409 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 410 {
 411         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 412
 413         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 414                                                      intel_dp->num_source_rates,
 415                                                      intel_dp->sink_rates,
 416                                                      intel_dp->num_sink_rates,
 417                                                      intel_dp->common_rates);
 418
 419         /* Paranoia, there should always be something in common. */
 420         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 421                 intel_dp->common_rates[0] = 162000;
 422                 intel_dp->num_common_rates = 1;
 423         }
 424 }
 425
 426 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 427                                        u8 lane_count)
 428 {
 429         /*
 430          * FIXME: we need to synchronize the current link parameters with
 431          * hardware readout. Currently fast link training doesn't work on
 432          * boot-up.
 433          */
 434         if (link_rate == 0 ||
 435             link_rate > intel_dp->max_link_rate)
 436                 return false;
 437
 438         if (lane_count == 0 ||
 439             lane_count > intel_dp_max_lane_count(intel_dp))
 440                 return false;
 441
 442         return true;
 443 }
 444
 445 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 446                                                      int link_rate,
 447                                                      u8 lane_count)
 448 {
 449         const struct drm_display_mode *fixed_mode =
 450                 intel_dp->attached_connector->panel.fixed_mode;
 451         int mode_rate, max_rate;
 452
 453         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 454         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 455         if (mode_rate > max_rate)
 456                 return false;
 457
 458         return true;
 459 }
 460
 461 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 462                                             int link_rate, u8 lane_count)
 463 {
 464         int index;
 465
 466         index = intel_dp_rate_index(intel_dp->common_rates,
 467                                     intel_dp->num_common_rates,
 468                                     link_rate);
 469         if (index > 0) {
 470                 if (intel_dp_is_edp(intel_dp) &&
 471                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 472                                                               intel_dp->common_rates[index - 1],
 473                                                               lane_count)) {
 474                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 475                         return 0;
 476                 }
 477                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 478                 intel_dp->max_link_lane_count = lane_count;
 479         } else if (lane_count > 1) {
 480                 if (intel_dp_is_edp(intel_dp) &&
 481                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 482                                                               intel_dp_max_common_rate(intel_dp),
 483                                                               lane_count >> 1)) {
 484                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 485                         return 0;
 486                 }
 487                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 488                 intel_dp->max_link_lane_count = lane_count >> 1;
 489         } else {
 490                 DRM_ERROR("Link Training Unsuccessful\n");
 491                 return -1;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static enum drm_mode_status
 498 intel_dp_mode_valid(struct drm_connector *connector,
 499                     struct drm_display_mode *mode)
 500 {
 501         struct intel_dp *intel_dp = intel_attached_dp(connector);
 502         struct intel_connector *intel_connector = to_intel_connector(connector);
 503         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 504         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 505         int target_clock = mode->clock;
 506         int max_rate, mode_rate, max_lanes, max_link_clock;
 507         int max_dotclk;
 508         u16 dsc_max_output_bpp = 0;
 509         u8 dsc_slice_count = 0;
 510
 511         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 512                 return MODE_NO_DBLESCAN;
 513
 514         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 515
 516         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 517                 if (mode->hdisplay > fixed_mode->hdisplay)
 518                         return MODE_PANEL;
 519
 520                 if (mode->vdisplay > fixed_mode->vdisplay)
 521                         return MODE_PANEL;
 522
 523                 target_clock = fixed_mode->clock;
 524         }
 525
 526         max_link_clock = intel_dp_max_link_rate(intel_dp);
 527         max_lanes = intel_dp_max_lane_count(intel_dp);
 528
 529         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 530         mode_rate = intel_dp_link_required(target_clock, 18);
 531
 532         /*
 533          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 534          * integer value since we support only integer values of bpp.
 535          */
 536         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 537             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 538                 if (intel_dp_is_edp(intel_dp)) {
 539                         dsc_max_output_bpp =
 540                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 541                         dsc_slice_count =
 542                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 543                                                                 true);
 544                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 545                         dsc_max_output_bpp =
 546                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 547                                                             max_lanes,
 548                                                             target_clock,
 549                                                             mode->hdisplay) >> 4;
 550                         dsc_slice_count =
 551                                 intel_dp_dsc_get_slice_count(intel_dp,
 552                                                              target_clock,
 553                                                              mode->hdisplay);
 554                 }
 555         }
 556
 557         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 558             target_clock > max_dotclk)
 559                 return MODE_CLOCK_HIGH;
 560
 561         if (mode->clock < 10000)
 562                 return MODE_CLOCK_LOW;
 563
 564         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 565                 return MODE_H_ILLEGAL;
 566
 567         return MODE_OK;
 568 }
 569
 570 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 571 {
 572         int i;
 573         u32 v = 0;
 574
 575         if (src_bytes > 4)
 576                 src_bytes = 4;
 577         for (i = 0; i < src_bytes; i++)
 578                 v |= ((u32)src[i]) << ((3 - i) * 8);
 579         return v;
 580 }
 581
 582 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 583 {
 584         int i;
 585         if (dst_bytes > 4)
 586                 dst_bytes = 4;
 587         for (i = 0; i < dst_bytes; i++)
 588                 dst[i] = src >> ((3-i) * 8);
 589 }
 590
 591 static void
 592 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 593 static void
 594 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 595                                               bool force_disable_vdd);
 596 static void
 597 intel_dp_pps_init(struct intel_dp *intel_dp);
 598
 599 static intel_wakeref_t
 600 pps_lock(struct intel_dp *intel_dp)
 601 {
 602         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 603         intel_wakeref_t wakeref;
 604
 605         /*
 606          * See intel_power_sequencer_reset() why we need
 607          * a power domain reference here.
 608          */
 609         wakeref = intel_display_power_get(dev_priv,
 610                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 611
 612         mutex_lock(&dev_priv->pps_mutex);
 613
 614         return wakeref;
 615 }
 616
 617 static intel_wakeref_t
 618 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 619 {
 620         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 621
 622         mutex_unlock(&dev_priv->pps_mutex);
 623         intel_display_power_put(dev_priv,
 624                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 625                                 wakeref);
 626         return 0;
 627 }
 628
 629 #define with_pps_lock(dp, wf) \
 630         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 631
 632 static void
 633 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 634 {
 635         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 636         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 637         enum pipe pipe = intel_dp->pps_pipe;
 638         bool pll_enabled, release_cl_override = false;
 639         enum dpio_phy phy = DPIO_PHY(pipe);
 640         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 641         u32 DP;
 642
 643         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 644                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 645                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 646                 return;
 647
 648         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 649                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 650
 651         /* Preserve the BIOS-computed detected bit. This is
 652          * supposed to be read-only.
 653          */
 654         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 655         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 656         DP |= DP_PORT_WIDTH(1);
 657         DP |= DP_LINK_TRAIN_PAT_1;
 658
 659         if (IS_CHERRYVIEW(dev_priv))
 660                 DP |= DP_PIPE_SEL_CHV(pipe);
 661         else
 662                 DP |= DP_PIPE_SEL(pipe);
 663
 664         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 665
 666         /*
 667          * The DPLL for the pipe must be enabled for this to work.
 668          * So enable temporarily it if it's not already enabled.
 669          */
 670         if (!pll_enabled) {
 671                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 672                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 673
 674                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 675                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 676                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 677                                   pipe_name(pipe));
 678                         return;
 679                 }
 680         }
 681
 682         /*
 683          * Similar magic as in intel_dp_enable_port().
 684          * We _must_ do this port enable + disable trick
 685          * to make this power sequencer lock onto the port.
 686          * Otherwise even VDD force bit won't work.
 687          */
 688         I915_WRITE(intel_dp->output_reg, DP);
 689         POSTING_READ(intel_dp->output_reg);
 690
 691         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 692         POSTING_READ(intel_dp->output_reg);
 693
 694         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 695         POSTING_READ(intel_dp->output_reg);
 696
 697         if (!pll_enabled) {
 698                 vlv_force_pll_off(dev_priv, pipe);
 699
 700                 if (release_cl_override)
 701                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 702         }
 703 }
 704
 705 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 706 {
 707         struct intel_encoder *encoder;
 708         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 709
 710         /*
 711          * We don't have power sequencer currently.
 712          * Pick one that's not used by other ports.
 713          */
 714         for_each_intel_dp(&dev_priv->drm, encoder) {
 715                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 716
 717                 if (encoder->type == INTEL_OUTPUT_EDP) {
 718                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 719                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 720
 721                         if (intel_dp->pps_pipe != INVALID_PIPE)
 722                                 pipes &= ~(1 << intel_dp->pps_pipe);
 723                 } else {
 724                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 725
 726                         if (intel_dp->active_pipe != INVALID_PIPE)
 727                                 pipes &= ~(1 << intel_dp->active_pipe);
 728                 }
 729         }
 730
 731         if (pipes == 0)
 732                 return INVALID_PIPE;
 733
 734         return ffs(pipes) - 1;
 735 }
 736
 737 static enum pipe
 738 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 739 {
 740         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         enum pipe pipe;
 743
 744         lockdep_assert_held(&dev_priv->pps_mutex);
 745
 746         /* We should never land here with regular DP ports */
 747         WARN_ON(!intel_dp_is_edp(intel_dp));
 748
 749         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 750                 intel_dp->active_pipe != intel_dp->pps_pipe);
 751
 752         if (intel_dp->pps_pipe != INVALID_PIPE)
 753                 return intel_dp->pps_pipe;
 754
 755         pipe = vlv_find_free_pps(dev_priv);
 756
 757         /*
 758          * Didn't find one. This should not happen since there
 759          * are two power sequencers and up to two eDP ports.
 760          */
 761         if (WARN_ON(pipe == INVALID_PIPE))
 762                 pipe = PIPE_A;
 763
 764         vlv_steal_power_sequencer(dev_priv, pipe);
 765         intel_dp->pps_pipe = pipe;
 766
 767         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 768                       pipe_name(intel_dp->pps_pipe),
 769                       port_name(intel_dig_port->base.port));
 770
 771         /* init power sequencer on this pipe and port */
 772         intel_dp_init_panel_power_sequencer(intel_dp);
 773         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 774
 775         /*
 776          * Even vdd force doesn't work until we've made
 777          * the power sequencer lock in on the port.
 778          */
 779         vlv_power_sequencer_kick(intel_dp);
 780
 781         return intel_dp->pps_pipe;
 782 }
 783
 784 static int
 785 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 786 {
 787         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 788         int backlight_controller = dev_priv->vbt.backlight.controller;
 789
 790         lockdep_assert_held(&dev_priv->pps_mutex);
 791
 792         /* We should never land here with regular DP ports */
 793         WARN_ON(!intel_dp_is_edp(intel_dp));
 794
 795         if (!intel_dp->pps_reset)
 796                 return backlight_controller;
 797
 798         intel_dp->pps_reset = false;
 799
 800         /*
 801          * Only the HW needs to be reprogrammed, the SW state is fixed and
 802          * has been setup during connector init.
 803          */
 804         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 805
 806         return backlight_controller;
 807 }
 808
 809 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 810                                enum pipe pipe);
 811
 812 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 813                                enum pipe pipe)
 814 {
 815         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 816 }
 817
 818 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 819                                 enum pipe pipe)
 820 {
 821         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 822 }
 823
 824 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 825                          enum pipe pipe)
 826 {
 827         return true;
 828 }
 829
 830 static enum pipe
 831 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 832                      enum port port,
 833                      vlv_pipe_check pipe_check)
 834 {
 835         enum pipe pipe;
 836
 837         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 838                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 839                         PANEL_PORT_SELECT_MASK;
 840
 841                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 842                         continue;
 843
 844                 if (!pipe_check(dev_priv, pipe))
 845                         continue;
 846
 847                 return pipe;
 848         }
 849
 850         return INVALID_PIPE;
 851 }
 852
 853 static void
 854 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 855 {
 856         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 857         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 858         enum port port = intel_dig_port->base.port;
 859
 860         lockdep_assert_held(&dev_priv->pps_mutex);
 861
 862         /* try to find a pipe with this port selected */
 863         /* first pick one where the panel is on */
 864         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 865                                                   vlv_pipe_has_pp_on);
 866         /* didn't find one? pick one where vdd is on */
 867         if (intel_dp->pps_pipe == INVALID_PIPE)
 868                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 869                                                           vlv_pipe_has_vdd_on);
 870         /* didn't find one? pick one with just the correct port */
 871         if (intel_dp->pps_pipe == INVALID_PIPE)
 872                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 873                                                           vlv_pipe_any);
 874
 875         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 876         if (intel_dp->pps_pipe == INVALID_PIPE) {
 877                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 878                               port_name(port));
 879                 return;
 880         }
 881
 882         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 883                       port_name(port), pipe_name(intel_dp->pps_pipe));
 884
 885         intel_dp_init_panel_power_sequencer(intel_dp);
 886         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 887 }
 888
 889 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 890 {
 891         struct intel_encoder *encoder;
 892
 893         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 894                     !IS_GEN9_LP(dev_priv)))
 895                 return;
 896
 897         /*
 898          * We can't grab pps_mutex here due to deadlock with power_domain
 899          * mutex when power_domain functions are called while holding pps_mutex.
 900          * That also means that in order to use pps_pipe the code needs to
 901          * hold both a power domain reference and pps_mutex, and the power domain
 902          * reference get/put must be done while _not_ holding pps_mutex.
 903          * pps_{lock,unlock}() do these steps in the correct order, so one
 904          * should use them always.
 905          */
 906
 907         for_each_intel_dp(&dev_priv->drm, encoder) {
 908                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 909
 910                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 911
 912                 if (encoder->type != INTEL_OUTPUT_EDP)
 913                         continue;
 914
 915                 if (IS_GEN9_LP(dev_priv))
 916                         intel_dp->pps_reset = true;
 917                 else
 918                         intel_dp->pps_pipe = INVALID_PIPE;
 919         }
 920 }
 921
 922 struct pps_registers {
 923         i915_reg_t pp_ctrl;
 924         i915_reg_t pp_stat;
 925         i915_reg_t pp_on;
 926         i915_reg_t pp_off;
 927         i915_reg_t pp_div;
 928 };
 929
 930 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 931                                     struct pps_registers *regs)
 932 {
 933         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 934         int pps_idx = 0;
 935
 936         memset(regs, 0, sizeof(*regs));
 937
 938         if (IS_GEN9_LP(dev_priv))
 939                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 940         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 941                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 942
 943         regs->pp_ctrl = PP_CONTROL(pps_idx);
 944         regs->pp_stat = PP_STATUS(pps_idx);
 945         regs->pp_on = PP_ON_DELAYS(pps_idx);
 946         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 947
 948         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 949         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 950                 regs->pp_div = INVALID_MMIO_REG;
 951         else
 952                 regs->pp_div = PP_DIVISOR(pps_idx);
 953 }
 954
 955 static i915_reg_t
 956 _pp_ctrl_reg(struct intel_dp *intel_dp)
 957 {
 958         struct pps_registers regs;
 959
 960         intel_pps_get_registers(intel_dp, &regs);
 961
 962         return regs.pp_ctrl;
 963 }
 964
 965 static i915_reg_t
 966 _pp_stat_reg(struct intel_dp *intel_dp)
 967 {
 968         struct pps_registers regs;
 969
 970         intel_pps_get_registers(intel_dp, &regs);
 971
 972         return regs.pp_stat;
 973 }
 974
 975 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 976    This function only applicable when panel PM state is not to be tracked */
 977 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 978                               void *unused)
 979 {
 980         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 981                                                  edp_notifier);
 982         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 983         intel_wakeref_t wakeref;
 984
 985         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 986                 return 0;
 987
 988         with_pps_lock(intel_dp, wakeref) {
 989                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 990                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 991                         i915_reg_t pp_ctrl_reg, pp_div_reg;
 992                         u32 pp_div;
 993
 994                         pp_ctrl_reg = PP_CONTROL(pipe);
 995                         pp_div_reg  = PP_DIVISOR(pipe);
 996                         pp_div = I915_READ(pp_div_reg);
 997                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
 998
 999                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1000                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1001                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1002                         msleep(intel_dp->panel_power_cycle_delay);
1003                 }
1004         }
1005
1006         return 0;
1007 }
1008
1009 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1010 {
1011         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1012
1013         lockdep_assert_held(&dev_priv->pps_mutex);
1014
1015         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1016             intel_dp->pps_pipe == INVALID_PIPE)
1017                 return false;
1018
1019         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1020 }
1021
1022 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1023 {
1024         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1025
1026         lockdep_assert_held(&dev_priv->pps_mutex);
1027
1028         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1029             intel_dp->pps_pipe == INVALID_PIPE)
1030                 return false;
1031
1032         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1033 }
1034
1035 static void
1036 intel_dp_check_edp(struct intel_dp *intel_dp)
1037 {
1038         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1039
1040         if (!intel_dp_is_edp(intel_dp))
1041                 return;
1042
1043         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1044                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1045                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1046                               I915_READ(_pp_stat_reg(intel_dp)),
1047                               I915_READ(_pp_ctrl_reg(intel_dp)));
1048         }
1049 }
1050
1051 static u32
1052 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1053 {
1054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1055         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1056         u32 status;
1057         bool done;
1058
1059 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1060         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1061                                   msecs_to_jiffies_timeout(10));
1062
1063         /* just trace the final value */
1064         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1065
1066         if (!done)
1067                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1068 #undef C
1069
1070         return status;
1071 }
1072
1073 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1074 {
1075         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1076
1077         if (index)
1078                 return 0;
1079
1080         /*
1081          * The clock divider is based off the hrawclk, and would like to run at
1082          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1083          */
1084         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1085 }
1086
1087 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1088 {
1089         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1090         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1091
1092         if (index)
1093                 return 0;
1094
1095         /*
1096          * The clock divider is based off the cdclk or PCH rawclk, and would
1097          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1098          * divide by 2000 and use that
1099          */
1100         if (dig_port->aux_ch == AUX_CH_A)
1101                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1102         else
1103                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1104 }
1105
1106 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1107 {
1108         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1109         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1110
1111         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1112                 /* Workaround for non-ULT HSW */
1113                 switch (index) {
1114                 case 0: return 63;
1115                 case 1: return 72;
1116                 default: return 0;
1117                 }
1118         }
1119
1120         return ilk_get_aux_clock_divider(intel_dp, index);
1121 }
1122
1123 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1124 {
1125         /*
1126          * SKL doesn't need us to program the AUX clock divider (Hardware will
1127          * derive the clock from CDCLK automatically). We still implement the
1128          * get_aux_clock_divider vfunc to plug-in into the existing code.
1129          */
1130         return index ? 0 : 1;
1131 }
1132
1133 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1134                                 int send_bytes,
1135                                 u32 aux_clock_divider)
1136 {
1137         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1138         struct drm_i915_private *dev_priv =
1139                         to_i915(intel_dig_port->base.base.dev);
1140         u32 precharge, timeout;
1141
1142         if (IS_GEN(dev_priv, 6))
1143                 precharge = 3;
1144         else
1145                 precharge = 5;
1146
1147         if (IS_BROADWELL(dev_priv))
1148                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1149         else
1150                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1151
1152         return DP_AUX_CH_CTL_SEND_BUSY |
1153                DP_AUX_CH_CTL_DONE |
1154                DP_AUX_CH_CTL_INTERRUPT |
1155                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1156                timeout |
1157                DP_AUX_CH_CTL_RECEIVE_ERROR |
1158                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1159                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1160                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1161 }
1162
1163 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1164                                 int send_bytes,
1165                                 u32 unused)
1166 {
1167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1168         u32 ret;
1169
1170         ret = DP_AUX_CH_CTL_SEND_BUSY |
1171               DP_AUX_CH_CTL_DONE |
1172               DP_AUX_CH_CTL_INTERRUPT |
1173               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1174               DP_AUX_CH_CTL_TIME_OUT_MAX |
1175               DP_AUX_CH_CTL_RECEIVE_ERROR |
1176               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1177               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1178               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1179
1180         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1181                 ret |= DP_AUX_CH_CTL_TBT_IO;
1182
1183         return ret;
1184 }
1185
1186 static int
1187 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1188                   const u8 *send, int send_bytes,
1189                   u8 *recv, int recv_size,
1190                   u32 aux_send_ctl_flags)
1191 {
1192         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1193         struct drm_i915_private *i915 =
1194                         to_i915(intel_dig_port->base.base.dev);
1195         struct intel_uncore *uncore = &i915->uncore;
1196         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1197         bool is_tc_port = intel_phy_is_tc(i915, phy);
1198         i915_reg_t ch_ctl, ch_data[5];
1199         u32 aux_clock_divider;
1200         enum intel_display_power_domain aux_domain =
1201                 intel_aux_power_domain(intel_dig_port);
1202         intel_wakeref_t aux_wakeref;
1203         intel_wakeref_t pps_wakeref;
1204         int i, ret, recv_bytes;
1205         int try, clock = 0;
1206         u32 status;
1207         bool vdd;
1208
1209         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1210         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1211                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1212
1213         if (is_tc_port)
1214                 intel_tc_port_lock(intel_dig_port);
1215
1216         aux_wakeref = intel_display_power_get(i915, aux_domain);
1217         pps_wakeref = pps_lock(intel_dp);
1218
1219         /*
1220          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1221          * In such cases we want to leave VDD enabled and it's up to upper layers
1222          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1223          * ourselves.
1224          */
1225         vdd = edp_panel_vdd_on(intel_dp);
1226
1227         /* dp aux is extremely sensitive to irq latency, hence request the
1228          * lowest possible wakeup latency and so prevent the cpu from going into
1229          * deep sleep states.
1230          */
1231         pm_qos_update_request(&i915->pm_qos, 0);
1232
1233         intel_dp_check_edp(intel_dp);
1234
1235         /* Try to wait for any previous AUX channel activity */
1236         for (try = 0; try < 3; try++) {
1237                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1238                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1239                         break;
1240                 msleep(1);
1241         }
1242         /* just trace the final value */
1243         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1244
1245         if (try == 3) {
1246                 static u32 last_status = -1;
1247                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1248
1249                 if (status != last_status) {
1250                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1251                              status);
1252                         last_status = status;
1253                 }
1254
1255                 ret = -EBUSY;
1256                 goto out;
1257         }
1258
1259         /* Only 5 data registers! */
1260         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1261                 ret = -E2BIG;
1262                 goto out;
1263         }
1264
1265         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1266                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1267                                                           send_bytes,
1268                                                           aux_clock_divider);
1269
1270                 send_ctl |= aux_send_ctl_flags;
1271
1272                 /* Must try at least 3 times according to DP spec */
1273                 for (try = 0; try < 5; try++) {
1274                         /* Load the send data into the aux channel data registers */
1275                         for (i = 0; i < send_bytes; i += 4)
1276                                 intel_uncore_write(uncore,
1277                                                    ch_data[i >> 2],
1278                                                    intel_dp_pack_aux(send + i,
1279                                                                      send_bytes - i));
1280
1281                         /* Send the command and wait for it to complete */
1282                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1283
1284                         status = intel_dp_aux_wait_done(intel_dp);
1285
1286                         /* Clear done status and any errors */
1287                         intel_uncore_write(uncore,
1288                                            ch_ctl,
1289                                            status |
1290                                            DP_AUX_CH_CTL_DONE |
1291                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1292                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1293
1294                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1295                          *   400us delay required for errors and timeouts
1296                          *   Timeout errors from the HW already meet this
1297                          *   requirement so skip to next iteration
1298                          */
1299                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1300                                 continue;
1301
1302                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1303                                 usleep_range(400, 500);
1304                                 continue;
1305                         }
1306                         if (status & DP_AUX_CH_CTL_DONE)
1307                                 goto done;
1308                 }
1309         }
1310
1311         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1312                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1313                 ret = -EBUSY;
1314                 goto out;
1315         }
1316
1317 done:
1318         /* Check for timeout or receive error.
1319          * Timeouts occur when the sink is not connected
1320          */
1321         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1322                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1323                 ret = -EIO;
1324                 goto out;
1325         }
1326
1327         /* Timeouts occur when the device isn't connected, so they're
1328          * "normal" -- don't fill the kernel log with these */
1329         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1330                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1331                 ret = -ETIMEDOUT;
1332                 goto out;
1333         }
1334
1335         /* Unload any bytes sent back from the other side */
1336         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1337                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1338
1339         /*
1340          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1341          * We have no idea of what happened so we return -EBUSY so
1342          * drm layer takes care for the necessary retries.
1343          */
1344         if (recv_bytes == 0 || recv_bytes > 20) {
1345                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1346                               recv_bytes);
1347                 ret = -EBUSY;
1348                 goto out;
1349         }
1350
1351         if (recv_bytes > recv_size)
1352                 recv_bytes = recv_size;
1353
1354         for (i = 0; i < recv_bytes; i += 4)
1355                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1356                                     recv + i, recv_bytes - i);
1357
1358         ret = recv_bytes;
1359 out:
1360         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1361
1362         if (vdd)
1363                 edp_panel_vdd_off(intel_dp, false);
1364
1365         pps_unlock(intel_dp, pps_wakeref);
1366         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1367
1368         if (is_tc_port)
1369                 intel_tc_port_unlock(intel_dig_port);
1370
1371         return ret;
1372 }
1373
1374 #define BARE_ADDRESS_SIZE       3
1375 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1376
1377 static void
1378 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1379                     const struct drm_dp_aux_msg *msg)
1380 {
1381         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1382         txbuf[1] = (msg->address >> 8) & 0xff;
1383         txbuf[2] = msg->address & 0xff;
1384         txbuf[3] = msg->size - 1;
1385 }
1386
1387 static ssize_t
1388 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1389 {
1390         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1391         u8 txbuf[20], rxbuf[20];
1392         size_t txsize, rxsize;
1393         int ret;
1394
1395         intel_dp_aux_header(txbuf, msg);
1396
1397         switch (msg->request & ~DP_AUX_I2C_MOT) {
1398         case DP_AUX_NATIVE_WRITE:
1399         case DP_AUX_I2C_WRITE:
1400         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1401                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1402                 rxsize = 2; /* 0 or 1 data bytes */
1403
1404                 if (WARN_ON(txsize > 20))
1405                         return -E2BIG;
1406
1407                 WARN_ON(!msg->buffer != !msg->size);
1408
1409                 if (msg->buffer)
1410                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1411
1412                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1413                                         rxbuf, rxsize, 0);
1414                 if (ret > 0) {
1415                         msg->reply = rxbuf[0] >> 4;
1416
1417                         if (ret > 1) {
1418                                 /* Number of bytes written in a short write. */
1419                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1420                         } else {
1421                                 /* Return payload size. */
1422                                 ret = msg->size;
1423                         }
1424                 }
1425                 break;
1426
1427         case DP_AUX_NATIVE_READ:
1428         case DP_AUX_I2C_READ:
1429                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1430                 rxsize = msg->size + 1;
1431
1432                 if (WARN_ON(rxsize > 20))
1433                         return -E2BIG;
1434
1435                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1436                                         rxbuf, rxsize, 0);
1437                 if (ret > 0) {
1438                         msg->reply = rxbuf[0] >> 4;
1439                         /*
1440                          * Assume happy day, and copy the data. The caller is
1441                          * expected to check msg->reply before touching it.
1442                          *
1443                          * Return payload size.
1444                          */
1445                         ret--;
1446                         memcpy(msg->buffer, rxbuf + 1, ret);
1447                 }
1448                 break;
1449
1450         default:
1451                 ret = -EINVAL;
1452                 break;
1453         }
1454
1455         return ret;
1456 }
1457
1458
1459 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1460 {
1461         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1462         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1463         enum aux_ch aux_ch = dig_port->aux_ch;
1464
1465         switch (aux_ch) {
1466         case AUX_CH_B:
1467         case AUX_CH_C:
1468         case AUX_CH_D:
1469                 return DP_AUX_CH_CTL(aux_ch);
1470         default:
1471                 MISSING_CASE(aux_ch);
1472                 return DP_AUX_CH_CTL(AUX_CH_B);
1473         }
1474 }
1475
1476 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1477 {
1478         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1479         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1480         enum aux_ch aux_ch = dig_port->aux_ch;
1481
1482         switch (aux_ch) {
1483         case AUX_CH_B:
1484         case AUX_CH_C:
1485         case AUX_CH_D:
1486                 return DP_AUX_CH_DATA(aux_ch, index);
1487         default:
1488                 MISSING_CASE(aux_ch);
1489                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1490         }
1491 }
1492
1493 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1494 {
1495         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1496         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1497         enum aux_ch aux_ch = dig_port->aux_ch;
1498
1499         switch (aux_ch) {
1500         case AUX_CH_A:
1501                 return DP_AUX_CH_CTL(aux_ch);
1502         case AUX_CH_B:
1503         case AUX_CH_C:
1504         case AUX_CH_D:
1505                 return PCH_DP_AUX_CH_CTL(aux_ch);
1506         default:
1507                 MISSING_CASE(aux_ch);
1508                 return DP_AUX_CH_CTL(AUX_CH_A);
1509         }
1510 }
1511
1512 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1513 {
1514         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1515         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1516         enum aux_ch aux_ch = dig_port->aux_ch;
1517
1518         switch (aux_ch) {
1519         case AUX_CH_A:
1520                 return DP_AUX_CH_DATA(aux_ch, index);
1521         case AUX_CH_B:
1522         case AUX_CH_C:
1523         case AUX_CH_D:
1524                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1525         default:
1526                 MISSING_CASE(aux_ch);
1527                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1528         }
1529 }
1530
1531 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1532 {
1533         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1534         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1535         enum aux_ch aux_ch = dig_port->aux_ch;
1536
1537         switch (aux_ch) {
1538         case AUX_CH_A:
1539         case AUX_CH_B:
1540         case AUX_CH_C:
1541         case AUX_CH_D:
1542         case AUX_CH_E:
1543         case AUX_CH_F:
1544                 return DP_AUX_CH_CTL(aux_ch);
1545         default:
1546                 MISSING_CASE(aux_ch);
1547                 return DP_AUX_CH_CTL(AUX_CH_A);
1548         }
1549 }
1550
1551 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1552 {
1553         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1554         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1555         enum aux_ch aux_ch = dig_port->aux_ch;
1556
1557         switch (aux_ch) {
1558         case AUX_CH_A:
1559         case AUX_CH_B:
1560         case AUX_CH_C:
1561         case AUX_CH_D:
1562         case AUX_CH_E:
1563         case AUX_CH_F:
1564                 return DP_AUX_CH_DATA(aux_ch, index);
1565         default:
1566                 MISSING_CASE(aux_ch);
1567                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1568         }
1569 }
1570
1571 static void
1572 intel_dp_aux_fini(struct intel_dp *intel_dp)
1573 {
1574         kfree(intel_dp->aux.name);
1575 }
1576
1577 static void
1578 intel_dp_aux_init(struct intel_dp *intel_dp)
1579 {
1580         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1581         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1582         struct intel_encoder *encoder = &dig_port->base;
1583
1584         if (INTEL_GEN(dev_priv) >= 9) {
1585                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1586                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1587         } else if (HAS_PCH_SPLIT(dev_priv)) {
1588                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1589                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1590         } else {
1591                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1592                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1593         }
1594
1595         if (INTEL_GEN(dev_priv) >= 9)
1596                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1597         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1598                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1599         else if (HAS_PCH_SPLIT(dev_priv))
1600                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1601         else
1602                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1603
1604         if (INTEL_GEN(dev_priv) >= 9)
1605                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1606         else
1607                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1608
1609         drm_dp_aux_init(&intel_dp->aux);
1610
1611         /* Failure to allocate our preferred name is not critical */
1612         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1613                                        port_name(encoder->port));
1614         intel_dp->aux.transfer = intel_dp_aux_transfer;
1615 }
1616
1617 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1618 {
1619         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1620
1621         return max_rate >= 540000;
1622 }
1623
1624 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1625 {
1626         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1627
1628         return max_rate >= 810000;
1629 }
1630
1631 static void
1632 intel_dp_set_clock(struct intel_encoder *encoder,
1633                    struct intel_crtc_state *pipe_config)
1634 {
1635         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1636         const struct dp_link_dpll *divisor = NULL;
1637         int i, count = 0;
1638
1639         if (IS_G4X(dev_priv)) {
1640                 divisor = g4x_dpll;
1641                 count = ARRAY_SIZE(g4x_dpll);
1642         } else if (HAS_PCH_SPLIT(dev_priv)) {
1643                 divisor = pch_dpll;
1644                 count = ARRAY_SIZE(pch_dpll);
1645         } else if (IS_CHERRYVIEW(dev_priv)) {
1646                 divisor = chv_dpll;
1647                 count = ARRAY_SIZE(chv_dpll);
1648         } else if (IS_VALLEYVIEW(dev_priv)) {
1649                 divisor = vlv_dpll;
1650                 count = ARRAY_SIZE(vlv_dpll);
1651         }
1652
1653         if (divisor && count) {
1654                 for (i = 0; i < count; i++) {
1655                         if (pipe_config->port_clock == divisor[i].clock) {
1656                                 pipe_config->dpll = divisor[i].dpll;
1657                                 pipe_config->clock_set = true;
1658                                 break;
1659                         }
1660                 }
1661         }
1662 }
1663
1664 static void snprintf_int_array(char *str, size_t len,
1665                                const int *array, int nelem)
1666 {
1667         int i;
1668
1669         str[0] = '\0';
1670
1671         for (i = 0; i < nelem; i++) {
1672                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1673                 if (r >= len)
1674                         return;
1675                 str += r;
1676                 len -= r;
1677         }
1678 }
1679
1680 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1681 {
1682         char str[128]; /* FIXME: too big for stack? */
1683
1684         if ((drm_debug & DRM_UT_KMS) == 0)
1685                 return;
1686
1687         snprintf_int_array(str, sizeof(str),
1688                            intel_dp->source_rates, intel_dp->num_source_rates);
1689         DRM_DEBUG_KMS("source rates: %s\n", str);
1690
1691         snprintf_int_array(str, sizeof(str),
1692                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1693         DRM_DEBUG_KMS("sink rates: %s\n", str);
1694
1695         snprintf_int_array(str, sizeof(str),
1696                            intel_dp->common_rates, intel_dp->num_common_rates);
1697         DRM_DEBUG_KMS("common rates: %s\n", str);
1698 }
1699
1700 int
1701 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1702 {
1703         int len;
1704
1705         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1706         if (WARN_ON(len <= 0))
1707                 return 162000;
1708
1709         return intel_dp->common_rates[len - 1];
1710 }
1711
1712 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1713 {
1714         int i = intel_dp_rate_index(intel_dp->sink_rates,
1715                                     intel_dp->num_sink_rates, rate);
1716
1717         if (WARN_ON(i < 0))
1718                 i = 0;
1719
1720         return i;
1721 }
1722
1723 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1724                            u8 *link_bw, u8 *rate_select)
1725 {
1726         /* eDP 1.4 rate select method. */
1727         if (intel_dp->use_rate_select) {
1728                 *link_bw = 0;
1729                 *rate_select =
1730                         intel_dp_rate_select(intel_dp, port_clock);
1731         } else {
1732                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1733                 *rate_select = 0;
1734         }
1735 }
1736
1737 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1738                                          const struct intel_crtc_state *pipe_config)
1739 {
1740         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1741
1742         return INTEL_GEN(dev_priv) >= 11 &&
1743                 pipe_config->cpu_transcoder != TRANSCODER_A;
1744 }
1745
1746 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1747                                   const struct intel_crtc_state *pipe_config)
1748 {
1749         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1750                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1751 }
1752
1753 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1754                                          const struct intel_crtc_state *pipe_config)
1755 {
1756         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1757
1758         return INTEL_GEN(dev_priv) >= 10 &&
1759                 pipe_config->cpu_transcoder != TRANSCODER_A;
1760 }
1761
1762 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1763                                   const struct intel_crtc_state *pipe_config)
1764 {
1765         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1766                 return false;
1767
1768         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1769                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1770 }
1771
1772 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1773                                 struct intel_crtc_state *pipe_config)
1774 {
1775         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1776         struct intel_connector *intel_connector = intel_dp->attached_connector;
1777         int bpp, bpc;
1778
1779         bpp = pipe_config->pipe_bpp;
1780         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1781
1782         if (bpc > 0)
1783                 bpp = min(bpp, 3*bpc);
1784
1785         if (intel_dp_is_edp(intel_dp)) {
1786                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1787                 if (intel_connector->base.display_info.bpc == 0 &&
1788                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1789                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1790                                       dev_priv->vbt.edp.bpp);
1791                         bpp = dev_priv->vbt.edp.bpp;
1792                 }
1793         }
1794
1795         return bpp;
1796 }
1797
1798 /* Adjust link config limits based on compliance test requests. */
1799 void
1800 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1801                                   struct intel_crtc_state *pipe_config,
1802                                   struct link_config_limits *limits)
1803 {
1804         /* For DP Compliance we override the computed bpp for the pipe */
1805         if (intel_dp->compliance.test_data.bpc != 0) {
1806                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1807
1808                 limits->min_bpp = limits->max_bpp = bpp;
1809                 pipe_config->dither_force_disable = bpp == 6 * 3;
1810
1811                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1812         }
1813
1814         /* Use values requested by Compliance Test Request */
1815         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1816                 int index;
1817
1818                 /* Validate the compliance test data since max values
1819                  * might have changed due to link train fallback.
1820                  */
1821                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1822                                                intel_dp->compliance.test_lane_count)) {
1823                         index = intel_dp_rate_index(intel_dp->common_rates,
1824                                                     intel_dp->num_common_rates,
1825                                                     intel_dp->compliance.test_link_rate);
1826                         if (index >= 0)
1827                                 limits->min_clock = limits->max_clock = index;
1828                         limits->min_lane_count = limits->max_lane_count =
1829                                 intel_dp->compliance.test_lane_count;
1830                 }
1831         }
1832 }
1833
1834 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1835 {
1836         /*
1837          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1838          * format of the number of bytes per pixel will be half the number
1839          * of bytes of RGB pixel.
1840          */
1841         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1842                 bpp /= 2;
1843
1844         return bpp;
1845 }
1846
1847 /* Optimize link config in order: max bpp, min clock, min lanes */
1848 static int
1849 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1850                                   struct intel_crtc_state *pipe_config,
1851                                   const struct link_config_limits *limits)
1852 {
1853         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1854         int bpp, clock, lane_count;
1855         int mode_rate, link_clock, link_avail;
1856
1857         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1858                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
1859
1860                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1861                                                    output_bpp);
1862
1863                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1864                         for (lane_count = limits->min_lane_count;
1865                              lane_count <= limits->max_lane_count;
1866                              lane_count <<= 1) {
1867                                 link_clock = intel_dp->common_rates[clock];
1868                                 link_avail = intel_dp_max_data_rate(link_clock,
1869                                                                     lane_count);
1870
1871                                 if (mode_rate <= link_avail) {
1872                                         pipe_config->lane_count = lane_count;
1873                                         pipe_config->pipe_bpp = bpp;
1874                                         pipe_config->port_clock = link_clock;
1875
1876                                         return 0;
1877                                 }
1878                         }
1879                 }
1880         }
1881
1882         return -EINVAL;
1883 }
1884
1885 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1886 {
1887         int i, num_bpc;
1888         u8 dsc_bpc[3] = {0};
1889
1890         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1891                                                        dsc_bpc);
1892         for (i = 0; i < num_bpc; i++) {
1893                 if (dsc_max_bpc >= dsc_bpc[i])
1894                         return dsc_bpc[i] * 3;
1895         }
1896
1897         return 0;
1898 }
1899
1900 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1901                                        struct intel_crtc_state *pipe_config,
1902                                        struct drm_connector_state *conn_state,
1903                                        struct link_config_limits *limits)
1904 {
1905         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1906         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1907         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1908         u8 dsc_max_bpc;
1909         int pipe_bpp;
1910         int ret;
1911
1912         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1913                 intel_dp_supports_fec(intel_dp, pipe_config);
1914
1915         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1916                 return -EINVAL;
1917
1918         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1919                             conn_state->max_requested_bpc);
1920
1921         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1922         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1923                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1924                 return -EINVAL;
1925         }
1926
1927         /*
1928          * For now enable DSC for max bpp, max link rate, max lane count.
1929          * Optimize this later for the minimum possible link rate/lane count
1930          * with DSC enabled for the requested mode.
1931          */
1932         pipe_config->pipe_bpp = pipe_bpp;
1933         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1934         pipe_config->lane_count = limits->max_lane_count;
1935
1936         if (intel_dp_is_edp(intel_dp)) {
1937                 pipe_config->dsc_params.compressed_bpp =
1938                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1939                               pipe_config->pipe_bpp);
1940                 pipe_config->dsc_params.slice_count =
1941                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1942                                                         true);
1943         } else {
1944                 u16 dsc_max_output_bpp;
1945                 u8 dsc_dp_slice_count;
1946
1947                 dsc_max_output_bpp =
1948                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1949                                                     pipe_config->lane_count,
1950                                                     adjusted_mode->crtc_clock,
1951                                                     adjusted_mode->crtc_hdisplay);
1952                 dsc_dp_slice_count =
1953                         intel_dp_dsc_get_slice_count(intel_dp,
1954                                                      adjusted_mode->crtc_clock,
1955                                                      adjusted_mode->crtc_hdisplay);
1956                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1957                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1958                         return -EINVAL;
1959                 }
1960                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1961                                                                dsc_max_output_bpp >> 4,
1962                                                                pipe_config->pipe_bpp);
1963                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1964         }
1965         /*
1966          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1967          * is greater than the maximum Cdclock and if slice count is even
1968          * then we need to use 2 VDSC instances.
1969          */
1970         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1971                 if (pipe_config->dsc_params.slice_count > 1) {
1972                         pipe_config->dsc_params.dsc_split = true;
1973                 } else {
1974                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1975                         return -EINVAL;
1976                 }
1977         }
1978
1979         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1980         if (ret < 0) {
1981                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1982                               "Compressed BPP = %d\n",
1983                               pipe_config->pipe_bpp,
1984                               pipe_config->dsc_params.compressed_bpp);
1985                 return ret;
1986         }
1987
1988         pipe_config->dsc_params.compression_enable = true;
1989         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1990                       "Compressed Bpp = %d Slice Count = %d\n",
1991                       pipe_config->pipe_bpp,
1992                       pipe_config->dsc_params.compressed_bpp,
1993                       pipe_config->dsc_params.slice_count);
1994
1995         return 0;
1996 }
1997
1998 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
1999 {
2000         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2001                 return 6 * 3;
2002         else
2003                 return 8 * 3;
2004 }
2005
2006 static int
2007 intel_dp_compute_link_config(struct intel_encoder *encoder,
2008                              struct intel_crtc_state *pipe_config,
2009                              struct drm_connector_state *conn_state)
2010 {
2011         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2012         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2013         struct link_config_limits limits;
2014         int common_len;
2015         int ret;
2016
2017         common_len = intel_dp_common_len_rate_limit(intel_dp,
2018                                                     intel_dp->max_link_rate);
2019
2020         /* No common link rates between source and sink */
2021         WARN_ON(common_len <= 0);
2022
2023         limits.min_clock = 0;
2024         limits.max_clock = common_len - 1;
2025
2026         limits.min_lane_count = 1;
2027         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2028
2029         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2030         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2031
2032         if (intel_dp_is_edp(intel_dp)) {
2033                 /*
2034                  * Use the maximum clock and number of lanes the eDP panel
2035                  * advertizes being capable of. The panels are generally
2036                  * designed to support only a single clock and lane
2037                  * configuration, and typically these values correspond to the
2038                  * native resolution of the panel.
2039                  */
2040                 limits.min_lane_count = limits.max_lane_count;
2041                 limits.min_clock = limits.max_clock;
2042         }
2043
2044         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2045
2046         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2047                       "max rate %d max bpp %d pixel clock %iKHz\n",
2048                       limits.max_lane_count,
2049                       intel_dp->common_rates[limits.max_clock],
2050                       limits.max_bpp, adjusted_mode->crtc_clock);
2051
2052         /*
2053          * Optimize for slow and wide. This is the place to add alternative
2054          * optimization policy.
2055          */
2056         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2057
2058         /* enable compression if the mode doesn't fit available BW */
2059         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2060         if (ret || intel_dp->force_dsc_en) {
2061                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2062                                                   conn_state, &limits);
2063                 if (ret < 0)
2064                         return ret;
2065         }
2066
2067         if (pipe_config->dsc_params.compression_enable) {
2068                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2069                               pipe_config->lane_count, pipe_config->port_clock,
2070                               pipe_config->pipe_bpp,
2071                               pipe_config->dsc_params.compressed_bpp);
2072
2073                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2074                               intel_dp_link_required(adjusted_mode->crtc_clock,
2075                                                      pipe_config->dsc_params.compressed_bpp),
2076                               intel_dp_max_data_rate(pipe_config->port_clock,
2077                                                      pipe_config->lane_count));
2078         } else {
2079                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2080                               pipe_config->lane_count, pipe_config->port_clock,
2081                               pipe_config->pipe_bpp);
2082
2083                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2084                               intel_dp_link_required(adjusted_mode->crtc_clock,
2085                                                      pipe_config->pipe_bpp),
2086                               intel_dp_max_data_rate(pipe_config->port_clock,
2087                                                      pipe_config->lane_count));
2088         }
2089         return 0;
2090 }
2091
2092 static int
2093 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2094                          struct drm_connector *connector,
2095                          struct intel_crtc_state *crtc_state)
2096 {
2097         const struct drm_display_info *info = &connector->display_info;
2098         const struct drm_display_mode *adjusted_mode =
2099                 &crtc_state->base.adjusted_mode;
2100         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2101         int ret;
2102
2103         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2104             !intel_dp_get_colorimetry_status(intel_dp) ||
2105             !connector->ycbcr_420_allowed)
2106                 return 0;
2107
2108         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2109
2110         /* YCBCR 420 output conversion needs a scaler */
2111         ret = skl_update_scaler_crtc(crtc_state);
2112         if (ret) {
2113                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2114                 return ret;
2115         }
2116
2117         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2118
2119         return 0;
2120 }
2121
2122 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2123                                   const struct drm_connector_state *conn_state)
2124 {
2125         const struct intel_digital_connector_state *intel_conn_state =
2126                 to_intel_digital_connector_state(conn_state);
2127         const struct drm_display_mode *adjusted_mode =
2128                 &crtc_state->base.adjusted_mode;
2129
2130         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2131                 /*
2132                  * See:
2133                  * CEA-861-E - 5.1 Default Encoding Parameters
2134                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2135                  */
2136                 return crtc_state->pipe_bpp != 18 &&
2137                         drm_default_rgb_quant_range(adjusted_mode) ==
2138                         HDMI_QUANTIZATION_RANGE_LIMITED;
2139         } else {
2140                 return intel_conn_state->broadcast_rgb ==
2141                         INTEL_BROADCAST_RGB_LIMITED;
2142         }
2143 }
2144
2145 int
2146 intel_dp_compute_config(struct intel_encoder *encoder,
2147                         struct intel_crtc_state *pipe_config,
2148                         struct drm_connector_state *conn_state)
2149 {
2150         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2151         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2152         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2153         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2154         enum port port = encoder->port;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2156         struct intel_connector *intel_connector = intel_dp->attached_connector;
2157         struct intel_digital_connector_state *intel_conn_state =
2158                 to_intel_digital_connector_state(conn_state);
2159         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2160                                            DP_DPCD_QUIRK_CONSTANT_N);
2161         int ret = 0, output_bpp;
2162
2163         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2164                 pipe_config->has_pch_encoder = true;
2165
2166         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2167         if (lspcon->active)
2168                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2169         else
2170                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2171                                                pipe_config);
2172
2173         if (ret)
2174                 return ret;
2175
2176         pipe_config->has_drrs = false;
2177         if (IS_G4X(dev_priv) || port == PORT_A)
2178                 pipe_config->has_audio = false;
2179         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2180                 pipe_config->has_audio = intel_dp->has_audio;
2181         else
2182                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2183
2184         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2185                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2186                                        adjusted_mode);
2187
2188                 if (INTEL_GEN(dev_priv) >= 9) {
2189                         ret = skl_update_scaler_crtc(pipe_config);
2190                         if (ret)
2191                                 return ret;
2192                 }
2193
2194                 if (HAS_GMCH(dev_priv))
2195                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2196                                                  conn_state->scaling_mode);
2197                 else
2198                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2199                                                 conn_state->scaling_mode);
2200         }
2201
2202         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2203                 return -EINVAL;
2204
2205         if (HAS_GMCH(dev_priv) &&
2206             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2207                 return -EINVAL;
2208
2209         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2210                 return -EINVAL;
2211
2212         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2213         if (ret < 0)
2214                 return ret;
2215
2216         pipe_config->limited_color_range =
2217                 intel_dp_limited_color_range(pipe_config, conn_state);
2218
2219         if (pipe_config->dsc_params.compression_enable)
2220                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2221         else
2222                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2223
2224         intel_link_compute_m_n(output_bpp,
2225                                pipe_config->lane_count,
2226                                adjusted_mode->crtc_clock,
2227                                pipe_config->port_clock,
2228                                &pipe_config->dp_m_n,
2229                                constant_n);
2230
2231         if (intel_connector->panel.downclock_mode != NULL &&
2232                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2233                         pipe_config->has_drrs = true;
2234                         intel_link_compute_m_n(output_bpp,
2235                                                pipe_config->lane_count,
2236                                                intel_connector->panel.downclock_mode->clock,
2237                                                pipe_config->port_clock,
2238                                                &pipe_config->dp_m2_n2,
2239                                                constant_n);
2240         }
2241
2242         if (!HAS_DDI(dev_priv))
2243                 intel_dp_set_clock(encoder, pipe_config);
2244
2245         intel_psr_compute_config(intel_dp, pipe_config);
2246
2247         return 0;
2248 }
2249
2250 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2251                               int link_rate, u8 lane_count,
2252                               bool link_mst)
2253 {
2254         intel_dp->link_trained = false;
2255         intel_dp->link_rate = link_rate;
2256         intel_dp->lane_count = lane_count;
2257         intel_dp->link_mst = link_mst;
2258 }
2259
2260 static void intel_dp_prepare(struct intel_encoder *encoder,
2261                              const struct intel_crtc_state *pipe_config)
2262 {
2263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2264         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2265         enum port port = encoder->port;
2266         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2267         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2268
2269         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2270                                  pipe_config->lane_count,
2271                                  intel_crtc_has_type(pipe_config,
2272                                                      INTEL_OUTPUT_DP_MST));
2273
2274         /*
2275          * There are four kinds of DP registers:
2276          *
2277          *      IBX PCH
2278          *      SNB CPU
2279          *      IVB CPU
2280          *      CPT PCH
2281          *
2282          * IBX PCH and CPU are the same for almost everything,
2283          * except that the CPU DP PLL is configured in this
2284          * register
2285          *
2286          * CPT PCH is quite different, having many bits moved
2287          * to the TRANS_DP_CTL register instead. That
2288          * configuration happens (oddly) in ironlake_pch_enable
2289          */
2290
2291         /* Preserve the BIOS-computed detected bit. This is
2292          * supposed to be read-only.
2293          */
2294         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2295
2296         /* Handle DP bits in common between all three register formats */
2297         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2298         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2299
2300         /* Split out the IBX/CPU vs CPT settings */
2301
2302         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2303                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2304                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2305                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2306                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2307                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2308
2309                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2310                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2311
2312                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2313         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2314                 u32 trans_dp;
2315
2316                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2317
2318                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2319                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2320                         trans_dp |= TRANS_DP_ENH_FRAMING;
2321                 else
2322                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2323                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2324         } else {
2325                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2326                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2327
2328                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2329                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2330                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2331                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2332                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2333
2334                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2335                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2336
2337                 if (IS_CHERRYVIEW(dev_priv))
2338                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2339                 else
2340                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2341         }
2342 }
2343
2344 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2345 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2346
2347 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2348 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2349
2350 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2351 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2352
2353 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2354
2355 static void wait_panel_status(struct intel_dp *intel_dp,
2356                                        u32 mask,
2357                                        u32 value)
2358 {
2359         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2360         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2361
2362         lockdep_assert_held(&dev_priv->pps_mutex);
2363
2364         intel_pps_verify_state(intel_dp);
2365
2366         pp_stat_reg = _pp_stat_reg(intel_dp);
2367         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2368
2369         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2370                         mask, value,
2371                         I915_READ(pp_stat_reg),
2372                         I915_READ(pp_ctrl_reg));
2373
2374         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2375                                        mask, value, 5000))
2376                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2377                                 I915_READ(pp_stat_reg),
2378                                 I915_READ(pp_ctrl_reg));
2379
2380         DRM_DEBUG_KMS("Wait complete\n");
2381 }
2382
2383 static void wait_panel_on(struct intel_dp *intel_dp)
2384 {
2385         DRM_DEBUG_KMS("Wait for panel power on\n");
2386         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2387 }
2388
2389 static void wait_panel_off(struct intel_dp *intel_dp)
2390 {
2391         DRM_DEBUG_KMS("Wait for panel power off time\n");
2392         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2393 }
2394
2395 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2396 {
2397         ktime_t panel_power_on_time;
2398         s64 panel_power_off_duration;
2399
2400         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2401
2402         /* take the difference of currrent time and panel power off time
2403          * and then make panel wait for t11_t12 if needed. */
2404         panel_power_on_time = ktime_get_boottime();
2405         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2406
2407         /* When we disable the VDD override bit last we have to do the manual
2408          * wait. */
2409         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2410                 wait_remaining_ms_from_jiffies(jiffies,
2411                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2412
2413         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2414 }
2415
2416 static void wait_backlight_on(struct intel_dp *intel_dp)
2417 {
2418         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2419                                        intel_dp->backlight_on_delay);
2420 }
2421
2422 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2423 {
2424         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2425                                        intel_dp->backlight_off_delay);
2426 }
2427
2428 /* Read the current pp_control value, unlocking the register if it
2429  * is locked
2430  */
2431
2432 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2433 {
2434         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2435         u32 control;
2436
2437         lockdep_assert_held(&dev_priv->pps_mutex);
2438
2439         control = I915_READ(_pp_ctrl_reg(intel_dp));
2440         if (WARN_ON(!HAS_DDI(dev_priv) &&
2441                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2442                 control &= ~PANEL_UNLOCK_MASK;
2443                 control |= PANEL_UNLOCK_REGS;
2444         }
2445         return control;
2446 }
2447
2448 /*
2449  * Must be paired with edp_panel_vdd_off().
2450  * Must hold pps_mutex around the whole on/off sequence.
2451  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2452  */
2453 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2454 {
2455         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2456         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2457         u32 pp;
2458         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2459         bool need_to_disable = !intel_dp->want_panel_vdd;
2460
2461         lockdep_assert_held(&dev_priv->pps_mutex);
2462
2463         if (!intel_dp_is_edp(intel_dp))
2464                 return false;
2465
2466         cancel_delayed_work(&intel_dp->panel_vdd_work);
2467         intel_dp->want_panel_vdd = true;
2468
2469         if (edp_have_panel_vdd(intel_dp))
2470                 return need_to_disable;
2471
2472         intel_display_power_get(dev_priv,
2473                                 intel_aux_power_domain(intel_dig_port));
2474
2475         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2476                       port_name(intel_dig_port->base.port));
2477
2478         if (!edp_have_panel_power(intel_dp))
2479                 wait_panel_power_cycle(intel_dp);
2480
2481         pp = ironlake_get_pp_control(intel_dp);
2482         pp |= EDP_FORCE_VDD;
2483
2484         pp_stat_reg = _pp_stat_reg(intel_dp);
2485         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2486
2487         I915_WRITE(pp_ctrl_reg, pp);
2488         POSTING_READ(pp_ctrl_reg);
2489         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2490                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2491         /*
2492          * If the panel wasn't on, delay before accessing aux channel
2493          */
2494         if (!edp_have_panel_power(intel_dp)) {
2495                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2496                               port_name(intel_dig_port->base.port));
2497                 msleep(intel_dp->panel_power_up_delay);
2498         }
2499
2500         return need_to_disable;
2501 }
2502
2503 /*
2504  * Must be paired with intel_edp_panel_vdd_off() or
2505  * intel_edp_panel_off().
2506  * Nested calls to these functions are not allowed since
2507  * we drop the lock. Caller must use some higher level
2508  * locking to prevent nested calls from other threads.
2509  */
2510 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2511 {
2512         intel_wakeref_t wakeref;
2513         bool vdd;
2514
2515         if (!intel_dp_is_edp(intel_dp))
2516                 return;
2517
2518         vdd = false;
2519         with_pps_lock(intel_dp, wakeref)
2520                 vdd = edp_panel_vdd_on(intel_dp);
2521         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2522              port_name(dp_to_dig_port(intel_dp)->base.port));
2523 }
2524
2525 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2526 {
2527         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2528         struct intel_digital_port *intel_dig_port =
2529                 dp_to_dig_port(intel_dp);
2530         u32 pp;
2531         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2532
2533         lockdep_assert_held(&dev_priv->pps_mutex);
2534
2535         WARN_ON(intel_dp->want_panel_vdd);
2536
2537         if (!edp_have_panel_vdd(intel_dp))
2538                 return;
2539
2540         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2541                       port_name(intel_dig_port->base.port));
2542
2543         pp = ironlake_get_pp_control(intel_dp);
2544         pp &= ~EDP_FORCE_VDD;
2545
2546         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2547         pp_stat_reg = _pp_stat_reg(intel_dp);
2548
2549         I915_WRITE(pp_ctrl_reg, pp);
2550         POSTING_READ(pp_ctrl_reg);
2551
2552         /* Make sure sequencer is idle before allowing subsequent activity */
2553         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2554         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2555
2556         if ((pp & PANEL_POWER_ON) == 0)
2557                 intel_dp->panel_power_off_time = ktime_get_boottime();
2558
2559         intel_display_power_put_unchecked(dev_priv,
2560                                           intel_aux_power_domain(intel_dig_port));
2561 }
2562
2563 static void edp_panel_vdd_work(struct work_struct *__work)
2564 {
2565         struct intel_dp *intel_dp =
2566                 container_of(to_delayed_work(__work),
2567                              struct intel_dp, panel_vdd_work);
2568         intel_wakeref_t wakeref;
2569
2570         with_pps_lock(intel_dp, wakeref) {
2571                 if (!intel_dp->want_panel_vdd)
2572                         edp_panel_vdd_off_sync(intel_dp);
2573         }
2574 }
2575
2576 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2577 {
2578         unsigned long delay;
2579
2580         /*
2581          * Queue the timer to fire a long time from now (relative to the power
2582          * down delay) to keep the panel power up across a sequence of
2583          * operations.
2584          */
2585         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2586         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2587 }
2588
2589 /*
2590  * Must be paired with edp_panel_vdd_on().
2591  * Must hold pps_mutex around the whole on/off sequence.
2592  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2593  */
2594 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2595 {
2596         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2597
2598         lockdep_assert_held(&dev_priv->pps_mutex);
2599
2600         if (!intel_dp_is_edp(intel_dp))
2601                 return;
2602
2603         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2604              port_name(dp_to_dig_port(intel_dp)->base.port));
2605
2606         intel_dp->want_panel_vdd = false;
2607
2608         if (sync)
2609                 edp_panel_vdd_off_sync(intel_dp);
2610         else
2611                 edp_panel_vdd_schedule_off(intel_dp);
2612 }
2613
2614 static void edp_panel_on(struct intel_dp *intel_dp)
2615 {
2616         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2617         u32 pp;
2618         i915_reg_t pp_ctrl_reg;
2619
2620         lockdep_assert_held(&dev_priv->pps_mutex);
2621
2622         if (!intel_dp_is_edp(intel_dp))
2623                 return;
2624
2625         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2626                       port_name(dp_to_dig_port(intel_dp)->base.port));
2627
2628         if (WARN(edp_have_panel_power(intel_dp),
2629                  "eDP port %c panel power already on\n",
2630                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2631                 return;
2632
2633         wait_panel_power_cycle(intel_dp);
2634
2635         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2636         pp = ironlake_get_pp_control(intel_dp);
2637         if (IS_GEN(dev_priv, 5)) {
2638                 /* ILK workaround: disable reset around power sequence */
2639                 pp &= ~PANEL_POWER_RESET;
2640                 I915_WRITE(pp_ctrl_reg, pp);
2641                 POSTING_READ(pp_ctrl_reg);
2642         }
2643
2644         pp |= PANEL_POWER_ON;
2645         if (!IS_GEN(dev_priv, 5))
2646                 pp |= PANEL_POWER_RESET;
2647
2648         I915_WRITE(pp_ctrl_reg, pp);
2649         POSTING_READ(pp_ctrl_reg);
2650
2651         wait_panel_on(intel_dp);
2652         intel_dp->last_power_on = jiffies;
2653
2654         if (IS_GEN(dev_priv, 5)) {
2655                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2656                 I915_WRITE(pp_ctrl_reg, pp);
2657                 POSTING_READ(pp_ctrl_reg);
2658         }
2659 }
2660
2661 void intel_edp_panel_on(struct intel_dp *intel_dp)
2662 {
2663         intel_wakeref_t wakeref;
2664
2665         if (!intel_dp_is_edp(intel_dp))
2666                 return;
2667
2668         with_pps_lock(intel_dp, wakeref)
2669                 edp_panel_on(intel_dp);
2670 }
2671
2672
2673 static void edp_panel_off(struct intel_dp *intel_dp)
2674 {
2675         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2676         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2677         u32 pp;
2678         i915_reg_t pp_ctrl_reg;
2679
2680         lockdep_assert_held(&dev_priv->pps_mutex);
2681
2682         if (!intel_dp_is_edp(intel_dp))
2683                 return;
2684
2685         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2686                       port_name(dig_port->base.port));
2687
2688         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2689              port_name(dig_port->base.port));
2690
2691         pp = ironlake_get_pp_control(intel_dp);
2692         /* We need to switch off panel power _and_ force vdd, for otherwise some
2693          * panels get very unhappy and cease to work. */
2694         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2695                 EDP_BLC_ENABLE);
2696
2697         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2698
2699         intel_dp->want_panel_vdd = false;
2700
2701         I915_WRITE(pp_ctrl_reg, pp);
2702         POSTING_READ(pp_ctrl_reg);
2703
2704         wait_panel_off(intel_dp);
2705         intel_dp->panel_power_off_time = ktime_get_boottime();
2706
2707         /* We got a reference when we enabled the VDD. */
2708         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2709 }
2710
2711 void intel_edp_panel_off(struct intel_dp *intel_dp)
2712 {
2713         intel_wakeref_t wakeref;
2714
2715         if (!intel_dp_is_edp(intel_dp))
2716                 return;
2717
2718         with_pps_lock(intel_dp, wakeref)
2719                 edp_panel_off(intel_dp);
2720 }
2721
2722 /* Enable backlight in the panel power control. */
2723 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2724 {
2725         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2726         intel_wakeref_t wakeref;
2727
2728         /*
2729          * If we enable the backlight right away following a panel power
2730          * on, we may see slight flicker as the panel syncs with the eDP
2731          * link.  So delay a bit to make sure the image is solid before
2732          * allowing it to appear.
2733          */
2734         wait_backlight_on(intel_dp);
2735
2736         with_pps_lock(intel_dp, wakeref) {
2737                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2738                 u32 pp;
2739
2740                 pp = ironlake_get_pp_control(intel_dp);
2741                 pp |= EDP_BLC_ENABLE;
2742
2743                 I915_WRITE(pp_ctrl_reg, pp);
2744                 POSTING_READ(pp_ctrl_reg);
2745         }
2746 }
2747
2748 /* Enable backlight PWM and backlight PP control. */
2749 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2750                             const struct drm_connector_state *conn_state)
2751 {
2752         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2753
2754         if (!intel_dp_is_edp(intel_dp))
2755                 return;
2756
2757         DRM_DEBUG_KMS("\n");
2758
2759         intel_panel_enable_backlight(crtc_state, conn_state);
2760         _intel_edp_backlight_on(intel_dp);
2761 }
2762
2763 /* Disable backlight in the panel power control. */
2764 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2765 {
2766         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2767         intel_wakeref_t wakeref;
2768
2769         if (!intel_dp_is_edp(intel_dp))
2770                 return;
2771
2772         with_pps_lock(intel_dp, wakeref) {
2773                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2774                 u32 pp;
2775
2776                 pp = ironlake_get_pp_control(intel_dp);
2777                 pp &= ~EDP_BLC_ENABLE;
2778
2779                 I915_WRITE(pp_ctrl_reg, pp);
2780                 POSTING_READ(pp_ctrl_reg);
2781         }
2782
2783         intel_dp->last_backlight_off = jiffies;
2784         edp_wait_backlight_off(intel_dp);
2785 }
2786
2787 /* Disable backlight PP control and backlight PWM. */
2788 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2789 {
2790         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2791
2792         if (!intel_dp_is_edp(intel_dp))
2793                 return;
2794
2795         DRM_DEBUG_KMS("\n");
2796
2797         _intel_edp_backlight_off(intel_dp);
2798         intel_panel_disable_backlight(old_conn_state);
2799 }
2800
2801 /*
2802  * Hook for controlling the panel power control backlight through the bl_power
2803  * sysfs attribute. Take care to handle multiple calls.
2804  */
2805 static void intel_edp_backlight_power(struct intel_connector *connector,
2806                                       bool enable)
2807 {
2808         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2809         intel_wakeref_t wakeref;
2810         bool is_enabled;
2811
2812         is_enabled = false;
2813         with_pps_lock(intel_dp, wakeref)
2814                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2815         if (is_enabled == enable)
2816                 return;
2817
2818         DRM_DEBUG_KMS("panel power control backlight %s\n",
2819                       enable ? "enable" : "disable");
2820
2821         if (enable)
2822                 _intel_edp_backlight_on(intel_dp);
2823         else
2824                 _intel_edp_backlight_off(intel_dp);
2825 }
2826
2827 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2828 {
2829         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2830         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2831         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2832
2833         I915_STATE_WARN(cur_state != state,
2834                         "DP port %c state assertion failure (expected %s, current %s)\n",
2835                         port_name(dig_port->base.port),
2836                         onoff(state), onoff(cur_state));
2837 }
2838 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2839
2840 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2841 {
2842         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2843
2844         I915_STATE_WARN(cur_state != state,
2845                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2846                         onoff(state), onoff(cur_state));
2847 }
2848 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2849 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2850
2851 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2852                                 const struct intel_crtc_state *pipe_config)
2853 {
2854         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2855         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2856
2857         assert_pipe_disabled(dev_priv, crtc->pipe);
2858         assert_dp_port_disabled(intel_dp);
2859         assert_edp_pll_disabled(dev_priv);
2860
2861         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2862                       pipe_config->port_clock);
2863
2864         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2865
2866         if (pipe_config->port_clock == 162000)
2867                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2868         else
2869                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2870
2871         I915_WRITE(DP_A, intel_dp->DP);
2872         POSTING_READ(DP_A);
2873         udelay(500);
2874
2875         /*
2876          * [DevILK] Work around required when enabling DP PLL
2877          * while a pipe is enabled going to FDI:
2878          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2879          * 2. Program DP PLL enable
2880          */
2881         if (IS_GEN(dev_priv, 5))
2882                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2883
2884         intel_dp->DP |= DP_PLL_ENABLE;
2885
2886         I915_WRITE(DP_A, intel_dp->DP);
2887         POSTING_READ(DP_A);
2888         udelay(200);
2889 }
2890
2891 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2892                                  const struct intel_crtc_state *old_crtc_state)
2893 {
2894         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2896
2897         assert_pipe_disabled(dev_priv, crtc->pipe);
2898         assert_dp_port_disabled(intel_dp);
2899         assert_edp_pll_enabled(dev_priv);
2900
2901         DRM_DEBUG_KMS("disabling eDP PLL\n");
2902
2903         intel_dp->DP &= ~DP_PLL_ENABLE;
2904
2905         I915_WRITE(DP_A, intel_dp->DP);
2906         POSTING_READ(DP_A);
2907         udelay(200);
2908 }
2909
2910 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2911 {
2912         /*
2913          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2914          * be capable of signalling downstream hpd with a long pulse.
2915          * Whether or not that means D3 is safe to use is not clear,
2916          * but let's assume so until proven otherwise.
2917          *
2918          * FIXME should really check all downstream ports...
2919          */
2920         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2921                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2922                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2923 }
2924
2925 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2926                                            const struct intel_crtc_state *crtc_state,
2927                                            bool enable)
2928 {
2929         int ret;
2930
2931         if (!crtc_state->dsc_params.compression_enable)
2932                 return;
2933
2934         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2935                                  enable ? DP_DECOMPRESSION_EN : 0);
2936         if (ret < 0)
2937                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2938                               enable ? "enable" : "disable");
2939 }
2940
2941 /* If the sink supports it, try to set the power state appropriately */
2942 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2943 {
2944         int ret, i;
2945
2946         /* Should have a valid DPCD by this point */
2947         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2948                 return;
2949
2950         if (mode != DRM_MODE_DPMS_ON) {
2951                 if (downstream_hpd_needs_d0(intel_dp))
2952                         return;
2953
2954                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2955                                          DP_SET_POWER_D3);
2956         } else {
2957                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2958
2959                 /*
2960                  * When turning on, we need to retry for 1ms to give the sink
2961                  * time to wake up.
2962                  */
2963                 for (i = 0; i < 3; i++) {
2964                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2965                                                  DP_SET_POWER_D0);
2966                         if (ret == 1)
2967                                 break;
2968                         msleep(1);
2969                 }
2970
2971                 if (ret == 1 && lspcon->active)
2972                         lspcon_wait_pcon_mode(lspcon);
2973         }
2974
2975         if (ret != 1)
2976                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2977                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2978 }
2979
2980 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2981                                  enum port port, enum pipe *pipe)
2982 {
2983         enum pipe p;
2984
2985         for_each_pipe(dev_priv, p) {
2986                 u32 val = I915_READ(TRANS_DP_CTL(p));
2987
2988                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2989                         *pipe = p;
2990                         return true;
2991                 }
2992         }
2993
2994         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2995
2996         /* must initialize pipe to something for the asserts */
2997         *pipe = PIPE_A;
2998
2999         return false;
3000 }
3001
3002 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3003                            i915_reg_t dp_reg, enum port port,
3004                            enum pipe *pipe)
3005 {
3006         bool ret;
3007         u32 val;
3008
3009         val = I915_READ(dp_reg);
3010
3011         ret = val & DP_PORT_EN;
3012
3013         /* asserts want to know the pipe even if the port is disabled */
3014         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3015                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3016         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3017                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3018         else if (IS_CHERRYVIEW(dev_priv))
3019                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3020         else
3021                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3022
3023         return ret;
3024 }
3025
3026 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3027                                   enum pipe *pipe)
3028 {
3029         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3030         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3031         intel_wakeref_t wakeref;
3032         bool ret;
3033
3034         wakeref = intel_display_power_get_if_enabled(dev_priv,
3035                                                      encoder->power_domain);
3036         if (!wakeref)
3037                 return false;
3038
3039         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3040                                     encoder->port, pipe);
3041
3042         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3043
3044         return ret;
3045 }
3046
3047 static void intel_dp_get_config(struct intel_encoder *encoder,
3048                                 struct intel_crtc_state *pipe_config)
3049 {
3050         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3051         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3052         u32 tmp, flags = 0;
3053         enum port port = encoder->port;
3054         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3055
3056         if (encoder->type == INTEL_OUTPUT_EDP)
3057                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3058         else
3059                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3060
3061         tmp = I915_READ(intel_dp->output_reg);
3062
3063         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3064
3065         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3066                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3067
3068                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3069                         flags |= DRM_MODE_FLAG_PHSYNC;
3070                 else
3071                         flags |= DRM_MODE_FLAG_NHSYNC;
3072
3073                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3074                         flags |= DRM_MODE_FLAG_PVSYNC;
3075                 else
3076                         flags |= DRM_MODE_FLAG_NVSYNC;
3077         } else {
3078                 if (tmp & DP_SYNC_HS_HIGH)
3079                         flags |= DRM_MODE_FLAG_PHSYNC;
3080                 else
3081                         flags |= DRM_MODE_FLAG_NHSYNC;
3082
3083                 if (tmp & DP_SYNC_VS_HIGH)
3084                         flags |= DRM_MODE_FLAG_PVSYNC;
3085                 else
3086                         flags |= DRM_MODE_FLAG_NVSYNC;
3087         }
3088
3089         pipe_config->base.adjusted_mode.flags |= flags;
3090
3091         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3092                 pipe_config->limited_color_range = true;
3093
3094         pipe_config->lane_count =
3095                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3096
3097         intel_dp_get_m_n(crtc, pipe_config);
3098
3099         if (port == PORT_A) {
3100                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3101                         pipe_config->port_clock = 162000;
3102                 else
3103                         pipe_config->port_clock = 270000;
3104         }
3105
3106         pipe_config->base.adjusted_mode.crtc_clock =
3107                 intel_dotclock_calculate(pipe_config->port_clock,
3108                                          &pipe_config->dp_m_n);
3109
3110         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3111             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3112                 /*
3113                  * This is a big fat ugly hack.
3114                  *
3115                  * Some machines in UEFI boot mode provide us a VBT that has 18
3116                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3117                  * unknown we fail to light up. Yet the same BIOS boots up with
3118                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3119                  * max, not what it tells us to use.
3120                  *
3121                  * Note: This will still be broken if the eDP panel is not lit
3122                  * up by the BIOS, and thus we can't get the mode at module
3123                  * load.
3124                  */
3125                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3126                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3127                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3128         }
3129 }
3130
3131 static void intel_disable_dp(struct intel_encoder *encoder,
3132                              const struct intel_crtc_state *old_crtc_state,
3133                              const struct drm_connector_state *old_conn_state)
3134 {
3135         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3136
3137         intel_dp->link_trained = false;
3138
3139         if (old_crtc_state->has_audio)
3140                 intel_audio_codec_disable(encoder,
3141                                           old_crtc_state, old_conn_state);
3142
3143         /* Make sure the panel is off before trying to change the mode. But also
3144          * ensure that we have vdd while we switch off the panel. */
3145         intel_edp_panel_vdd_on(intel_dp);
3146         intel_edp_backlight_off(old_conn_state);
3147         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3148         intel_edp_panel_off(intel_dp);
3149 }
3150
3151 static void g4x_disable_dp(struct intel_encoder *encoder,
3152                            const struct intel_crtc_state *old_crtc_state,
3153                            const struct drm_connector_state *old_conn_state)
3154 {
3155         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3156 }
3157
3158 static void vlv_disable_dp(struct intel_encoder *encoder,
3159                            const struct intel_crtc_state *old_crtc_state,
3160                            const struct drm_connector_state *old_conn_state)
3161 {
3162         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3163 }
3164
3165 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3166                                 const struct intel_crtc_state *old_crtc_state,
3167                                 const struct drm_connector_state *old_conn_state)
3168 {
3169         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3170         enum port port = encoder->port;
3171
3172         /*
3173          * Bspec does not list a specific disable sequence for g4x DP.
3174          * Follow the ilk+ sequence (disable pipe before the port) for
3175          * g4x DP as it does not suffer from underruns like the normal
3176          * g4x modeset sequence (disable pipe after the port).
3177          */
3178         intel_dp_link_down(encoder, old_crtc_state);
3179
3180         /* Only ilk+ has port A */
3181         if (port == PORT_A)
3182                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3183 }
3184
3185 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3186                                 const struct intel_crtc_state *old_crtc_state,
3187                                 const struct drm_connector_state *old_conn_state)
3188 {
3189         intel_dp_link_down(encoder, old_crtc_state);
3190 }
3191
3192 static void chv_post_disable_dp(struct intel_encoder *encoder,
3193                                 const struct intel_crtc_state *old_crtc_state,
3194                                 const struct drm_connector_state *old_conn_state)
3195 {
3196         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3197
3198         intel_dp_link_down(encoder, old_crtc_state);
3199
3200         vlv_dpio_get(dev_priv);
3201
3202         /* Assert data lane reset */
3203         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3204
3205         vlv_dpio_put(dev_priv);
3206 }
3207
3208 static void
3209 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3210                          u32 *DP,
3211                          u8 dp_train_pat)
3212 {
3213         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3214         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3215         enum port port = intel_dig_port->base.port;
3216         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3217
3218         if (dp_train_pat & train_pat_mask)
3219                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3220                               dp_train_pat & train_pat_mask);
3221
3222         if (HAS_DDI(dev_priv)) {
3223                 u32 temp = I915_READ(DP_TP_CTL(port));
3224
3225                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3226                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3227                 else
3228                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3229
3230                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3231                 switch (dp_train_pat & train_pat_mask) {
3232                 case DP_TRAINING_PATTERN_DISABLE:
3233                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3234
3235                         break;
3236                 case DP_TRAINING_PATTERN_1:
3237                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3238                         break;
3239                 case DP_TRAINING_PATTERN_2:
3240                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3241                         break;
3242                 case DP_TRAINING_PATTERN_3:
3243                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3244                         break;
3245                 case DP_TRAINING_PATTERN_4:
3246                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3247                         break;
3248                 }
3249                 I915_WRITE(DP_TP_CTL(port), temp);
3250
3251         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3252                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3253                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3254
3255                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3256                 case DP_TRAINING_PATTERN_DISABLE:
3257                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3258                         break;
3259                 case DP_TRAINING_PATTERN_1:
3260                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3261                         break;
3262                 case DP_TRAINING_PATTERN_2:
3263                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3264                         break;
3265                 case DP_TRAINING_PATTERN_3:
3266                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3267                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3268                         break;
3269                 }
3270
3271         } else {
3272                 *DP &= ~DP_LINK_TRAIN_MASK;
3273
3274                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3275                 case DP_TRAINING_PATTERN_DISABLE:
3276                         *DP |= DP_LINK_TRAIN_OFF;
3277                         break;
3278                 case DP_TRAINING_PATTERN_1:
3279                         *DP |= DP_LINK_TRAIN_PAT_1;
3280                         break;
3281                 case DP_TRAINING_PATTERN_2:
3282                         *DP |= DP_LINK_TRAIN_PAT_2;
3283                         break;
3284                 case DP_TRAINING_PATTERN_3:
3285                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3286                         *DP |= DP_LINK_TRAIN_PAT_2;
3287                         break;
3288                 }
3289         }
3290 }
3291
3292 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3293                                  const struct intel_crtc_state *old_crtc_state)
3294 {
3295         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3296
3297         /* enable with pattern 1 (as per spec) */
3298
3299         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3300
3301         /*
3302          * Magic for VLV/CHV. We _must_ first set up the register
3303          * without actually enabling the port, and then do another
3304          * write to enable the port. Otherwise link training will
3305          * fail when the power sequencer is freshly used for this port.
3306          */
3307         intel_dp->DP |= DP_PORT_EN;
3308         if (old_crtc_state->has_audio)
3309                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3310
3311         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3312         POSTING_READ(intel_dp->output_reg);
3313 }
3314
3315 static void intel_enable_dp(struct intel_encoder *encoder,
3316                             const struct intel_crtc_state *pipe_config,
3317                             const struct drm_connector_state *conn_state)
3318 {
3319         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3320         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3321         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3322         u32 dp_reg = I915_READ(intel_dp->output_reg);
3323         enum pipe pipe = crtc->pipe;
3324         intel_wakeref_t wakeref;
3325
3326         if (WARN_ON(dp_reg & DP_PORT_EN))
3327                 return;
3328
3329         with_pps_lock(intel_dp, wakeref) {
3330                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3331                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3332
3333                 intel_dp_enable_port(intel_dp, pipe_config);
3334
3335                 edp_panel_vdd_on(intel_dp);
3336                 edp_panel_on(intel_dp);
3337                 edp_panel_vdd_off(intel_dp, true);
3338         }
3339
3340         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3341                 unsigned int lane_mask = 0x0;
3342
3343                 if (IS_CHERRYVIEW(dev_priv))
3344                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3345
3346                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3347                                     lane_mask);
3348         }
3349
3350         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3351         intel_dp_start_link_train(intel_dp);
3352         intel_dp_stop_link_train(intel_dp);
3353
3354         if (pipe_config->has_audio) {
3355                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3356                                  pipe_name(pipe));
3357                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3358         }
3359 }
3360
3361 static void g4x_enable_dp(struct intel_encoder *encoder,
3362                           const struct intel_crtc_state *pipe_config,
3363                           const struct drm_connector_state *conn_state)
3364 {
3365         intel_enable_dp(encoder, pipe_config, conn_state);
3366         intel_edp_backlight_on(pipe_config, conn_state);
3367 }
3368
3369 static void vlv_enable_dp(struct intel_encoder *encoder,
3370                           const struct intel_crtc_state *pipe_config,
3371                           const struct drm_connector_state *conn_state)
3372 {
3373         intel_edp_backlight_on(pipe_config, conn_state);
3374 }
3375
3376 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3377                               const struct intel_crtc_state *pipe_config,
3378                               const struct drm_connector_state *conn_state)
3379 {
3380         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3381         enum port port = encoder->port;
3382
3383         intel_dp_prepare(encoder, pipe_config);
3384
3385         /* Only ilk+ has port A */
3386         if (port == PORT_A)
3387                 ironlake_edp_pll_on(intel_dp, pipe_config);
3388 }
3389
3390 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3391 {
3392         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3393         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3394         enum pipe pipe = intel_dp->pps_pipe;
3395         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3396
3397         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3398
3399         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3400                 return;
3401
3402         edp_panel_vdd_off_sync(intel_dp);
3403
3404         /*
3405          * VLV seems to get confused when multiple power sequencers
3406          * have the same port selected (even if only one has power/vdd
3407          * enabled). The failure manifests as vlv_wait_port_ready() failing
3408          * CHV on the other hand doesn't seem to mind having the same port
3409          * selected in multiple power sequencers, but let's clear the
3410          * port select always when logically disconnecting a power sequencer
3411          * from a port.
3412          */
3413         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3414                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3415         I915_WRITE(pp_on_reg, 0);
3416         POSTING_READ(pp_on_reg);
3417
3418         intel_dp->pps_pipe = INVALID_PIPE;
3419 }
3420
3421 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3422                                       enum pipe pipe)
3423 {
3424         struct intel_encoder *encoder;
3425
3426         lockdep_assert_held(&dev_priv->pps_mutex);
3427
3428         for_each_intel_dp(&dev_priv->drm, encoder) {
3429                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3430                 enum port port = encoder->port;
3431
3432                 WARN(intel_dp->active_pipe == pipe,
3433                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3434                      pipe_name(pipe), port_name(port));
3435
3436                 if (intel_dp->pps_pipe != pipe)
3437                         continue;
3438
3439                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3440                               pipe_name(pipe), port_name(port));
3441
3442                 /* make sure vdd is off before we steal it */
3443                 vlv_detach_power_sequencer(intel_dp);
3444         }
3445 }
3446
3447 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3448                                            const struct intel_crtc_state *crtc_state)
3449 {
3450         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3451         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3452         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3453
3454         lockdep_assert_held(&dev_priv->pps_mutex);
3455
3456         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3457
3458         if (intel_dp->pps_pipe != INVALID_PIPE &&
3459             intel_dp->pps_pipe != crtc->pipe) {
3460                 /*
3461                  * If another power sequencer was being used on this
3462                  * port previously make sure to turn off vdd there while
3463                  * we still have control of it.
3464                  */
3465                 vlv_detach_power_sequencer(intel_dp);
3466         }
3467
3468         /*
3469          * We may be stealing the power
3470          * sequencer from another port.
3471          */
3472         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3473
3474         intel_dp->active_pipe = crtc->pipe;
3475
3476         if (!intel_dp_is_edp(intel_dp))
3477                 return;
3478
3479         /* now it's all ours */
3480         intel_dp->pps_pipe = crtc->pipe;
3481
3482         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3483                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3484
3485         /* init power sequencer on this pipe and port */
3486         intel_dp_init_panel_power_sequencer(intel_dp);
3487         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3488 }
3489
3490 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3491                               const struct intel_crtc_state *pipe_config,
3492                               const struct drm_connector_state *conn_state)
3493 {
3494         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3495
3496         intel_enable_dp(encoder, pipe_config, conn_state);
3497 }
3498
3499 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3500                                   const struct intel_crtc_state *pipe_config,
3501                                   const struct drm_connector_state *conn_state)
3502 {
3503         intel_dp_prepare(encoder, pipe_config);
3504
3505         vlv_phy_pre_pll_enable(encoder, pipe_config);
3506 }
3507
3508 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3509                               const struct intel_crtc_state *pipe_config,
3510                               const struct drm_connector_state *conn_state)
3511 {
3512         chv_phy_pre_encoder_enable(encoder, pipe_config);
3513
3514         intel_enable_dp(encoder, pipe_config, conn_state);
3515
3516         /* Second common lane will stay alive on its own now */
3517         chv_phy_release_cl2_override(encoder);
3518 }
3519
3520 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3521                                   const struct intel_crtc_state *pipe_config,
3522                                   const struct drm_connector_state *conn_state)
3523 {
3524         intel_dp_prepare(encoder, pipe_config);
3525
3526         chv_phy_pre_pll_enable(encoder, pipe_config);
3527 }
3528
3529 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3530                                     const struct intel_crtc_state *old_crtc_state,
3531                                     const struct drm_connector_state *old_conn_state)
3532 {
3533         chv_phy_post_pll_disable(encoder, old_crtc_state);
3534 }
3535
3536 /*
3537  * Fetch AUX CH registers 0x202 - 0x207 which contain
3538  * link status information
3539  */
3540 bool
3541 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3542 {
3543         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3544                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3545 }
3546
3547 /* These are source-specific values. */
3548 u8
3549 intel_dp_voltage_max(struct intel_dp *intel_dp)
3550 {
3551         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3552         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3553         enum port port = encoder->port;
3554
3555         if (HAS_DDI(dev_priv))
3556                 return intel_ddi_dp_voltage_max(encoder);
3557         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3558                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3559         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3560                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3561         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3562                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3563         else
3564                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3565 }
3566
3567 u8
3568 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3569 {
3570         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3571         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3572         enum port port = encoder->port;
3573
3574         if (HAS_DDI(dev_priv)) {
3575                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3576         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3577                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3578                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3579                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3580                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3581                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3582                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3583                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3584                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3585                 default:
3586                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3587                 }
3588         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3589                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3590                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3591                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3592                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3593                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3594                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3595                 default:
3596                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3597                 }
3598         } else {
3599                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3600                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3601                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3602                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3603                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3604                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3605                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3606                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3607                 default:
3608                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3609                 }
3610         }
3611 }
3612
3613 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3614 {
3615         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3616         unsigned long demph_reg_value, preemph_reg_value,
3617                 uniqtranscale_reg_value;
3618         u8 train_set = intel_dp->train_set[0];
3619
3620         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3621         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3622                 preemph_reg_value = 0x0004000;
3623                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3624                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3625                         demph_reg_value = 0x2B405555;
3626                         uniqtranscale_reg_value = 0x552AB83A;
3627                         break;
3628                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3629                         demph_reg_value = 0x2B404040;
3630                         uniqtranscale_reg_value = 0x5548B83A;
3631                         break;
3632                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3633                         demph_reg_value = 0x2B245555;
3634                         uniqtranscale_reg_value = 0x5560B83A;
3635                         break;
3636                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3637                         demph_reg_value = 0x2B405555;
3638                         uniqtranscale_reg_value = 0x5598DA3A;
3639                         break;
3640                 default:
3641                         return 0;
3642                 }
3643                 break;
3644         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3645                 preemph_reg_value = 0x0002000;
3646                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3647                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3648                         demph_reg_value = 0x2B404040;
3649                         uniqtranscale_reg_value = 0x5552B83A;
3650                         break;
3651                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3652                         demph_reg_value = 0x2B404848;
3653                         uniqtranscale_reg_value = 0x5580B83A;
3654                         break;
3655                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3656                         demph_reg_value = 0x2B404040;
3657                         uniqtranscale_reg_value = 0x55ADDA3A;
3658                         break;
3659                 default:
3660                         return 0;
3661                 }
3662                 break;
3663         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3664                 preemph_reg_value = 0x0000000;
3665                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3666                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3667                         demph_reg_value = 0x2B305555;
3668                         uniqtranscale_reg_value = 0x5570B83A;
3669                         break;
3670                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3671                         demph_reg_value = 0x2B2B4040;
3672                         uniqtranscale_reg_value = 0x55ADDA3A;
3673                         break;
3674                 default:
3675                         return 0;
3676                 }
3677                 break;
3678         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3679                 preemph_reg_value = 0x0006000;
3680                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3681                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3682                         demph_reg_value = 0x1B405555;
3683                         uniqtranscale_reg_value = 0x55ADDA3A;
3684                         break;
3685                 default:
3686                         return 0;
3687                 }
3688                 break;
3689         default:
3690                 return 0;
3691         }
3692
3693         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3694                                  uniqtranscale_reg_value, 0);
3695
3696         return 0;
3697 }
3698
3699 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3700 {
3701         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3702         u32 deemph_reg_value, margin_reg_value;
3703         bool uniq_trans_scale = false;
3704         u8 train_set = intel_dp->train_set[0];
3705
3706         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3707         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3708                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3709                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3710                         deemph_reg_value = 128;
3711                         margin_reg_value = 52;
3712                         break;
3713                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3714                         deemph_reg_value = 128;
3715                         margin_reg_value = 77;
3716                         break;
3717                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3718                         deemph_reg_value = 128;
3719                         margin_reg_value = 102;
3720                         break;
3721                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3722                         deemph_reg_value = 128;
3723                         margin_reg_value = 154;
3724                         uniq_trans_scale = true;
3725                         break;
3726                 default:
3727                         return 0;
3728                 }
3729                 break;
3730         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3731                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3732                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3733                         deemph_reg_value = 85;
3734                         margin_reg_value = 78;
3735                         break;
3736                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3737                         deemph_reg_value = 85;
3738                         margin_reg_value = 116;
3739                         break;
3740                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3741                         deemph_reg_value = 85;
3742                         margin_reg_value = 154;
3743                         break;
3744                 default:
3745                         return 0;
3746                 }
3747                 break;
3748         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3749                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3750                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3751                         deemph_reg_value = 64;
3752                         margin_reg_value = 104;
3753                         break;
3754                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3755                         deemph_reg_value = 64;
3756                         margin_reg_value = 154;
3757                         break;
3758                 default:
3759                         return 0;
3760                 }
3761                 break;
3762         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3763                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3764                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3765                         deemph_reg_value = 43;
3766                         margin_reg_value = 154;
3767                         break;
3768                 default:
3769                         return 0;
3770                 }
3771                 break;
3772         default:
3773                 return 0;
3774         }
3775
3776         chv_set_phy_signal_level(encoder, deemph_reg_value,
3777                                  margin_reg_value, uniq_trans_scale);
3778
3779         return 0;
3780 }
3781
3782 static u32
3783 g4x_signal_levels(u8 train_set)
3784 {
3785         u32 signal_levels = 0;
3786
3787         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3788         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3789         default:
3790                 signal_levels |= DP_VOLTAGE_0_4;
3791                 break;
3792         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3793                 signal_levels |= DP_VOLTAGE_0_6;
3794                 break;
3795         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3796                 signal_levels |= DP_VOLTAGE_0_8;
3797                 break;
3798         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3799                 signal_levels |= DP_VOLTAGE_1_2;
3800                 break;
3801         }
3802         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3803         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3804         default:
3805                 signal_levels |= DP_PRE_EMPHASIS_0;
3806                 break;
3807         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3808                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3809                 break;
3810         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3811                 signal_levels |= DP_PRE_EMPHASIS_6;
3812                 break;
3813         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3814                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3815                 break;
3816         }
3817         return signal_levels;
3818 }
3819
3820 /* SNB CPU eDP voltage swing and pre-emphasis control */
3821 static u32
3822 snb_cpu_edp_signal_levels(u8 train_set)
3823 {
3824         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3825                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3826         switch (signal_levels) {
3827         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3828         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3829                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3830         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3831                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3832         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3833         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3834                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3835         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3836         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3837                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3838         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3839         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3840                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3841         default:
3842                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3843                               "0x%x\n", signal_levels);
3844                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3845         }
3846 }
3847
3848 /* IVB CPU eDP voltage swing and pre-emphasis control */
3849 static u32
3850 ivb_cpu_edp_signal_levels(u8 train_set)
3851 {
3852         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3853                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3854         switch (signal_levels) {
3855         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3856                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3857         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3858                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3859         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3860                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3861
3862         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3863                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3864         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3865                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3866
3867         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3868                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3869         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3870                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3871
3872         default:
3873                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3874                               "0x%x\n", signal_levels);
3875                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3876         }
3877 }
3878
3879 void
3880 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3881 {
3882         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3883         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3884         enum port port = intel_dig_port->base.port;
3885         u32 signal_levels, mask = 0;
3886         u8 train_set = intel_dp->train_set[0];
3887
3888         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3889                 signal_levels = bxt_signal_levels(intel_dp);
3890         } else if (HAS_DDI(dev_priv)) {
3891                 signal_levels = ddi_signal_levels(intel_dp);
3892                 mask = DDI_BUF_EMP_MASK;
3893         } else if (IS_CHERRYVIEW(dev_priv)) {
3894                 signal_levels = chv_signal_levels(intel_dp);
3895         } else if (IS_VALLEYVIEW(dev_priv)) {
3896                 signal_levels = vlv_signal_levels(intel_dp);
3897         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3898                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3899                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3900         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3901                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3902                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3903         } else {
3904                 signal_levels = g4x_signal_levels(train_set);
3905                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3906         }
3907
3908         if (mask)
3909                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3910
3911         DRM_DEBUG_KMS("Using vswing level %d\n",
3912                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3913         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3914                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3915                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3916
3917         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3918
3919         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3920         POSTING_READ(intel_dp->output_reg);
3921 }
3922
3923 void
3924 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3925                                        u8 dp_train_pat)
3926 {
3927         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3928         struct drm_i915_private *dev_priv =
3929                 to_i915(intel_dig_port->base.base.dev);
3930
3931         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3932
3933         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3934         POSTING_READ(intel_dp->output_reg);
3935 }
3936
3937 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3938 {
3939         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3940         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3941         enum port port = intel_dig_port->base.port;
3942         u32 val;
3943
3944         if (!HAS_DDI(dev_priv))
3945                 return;
3946
3947         val = I915_READ(DP_TP_CTL(port));
3948         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3949         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3950         I915_WRITE(DP_TP_CTL(port), val);
3951
3952         /*
3953          * On PORT_A we can have only eDP in SST mode. There the only reason
3954          * we need to set idle transmission mode is to work around a HW issue
3955          * where we enable the pipe while not in idle link-training mode.
3956          * In this case there is requirement to wait for a minimum number of
3957          * idle patterns to be sent.
3958          */
3959         if (port == PORT_A)
3960                 return;
3961
3962         if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
3963                                   DP_TP_STATUS_IDLE_DONE, 1))
3964                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3965 }
3966
3967 static void
3968 intel_dp_link_down(struct intel_encoder *encoder,
3969                    const struct intel_crtc_state *old_crtc_state)
3970 {
3971         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3972         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3973         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3974         enum port port = encoder->port;
3975         u32 DP = intel_dp->DP;
3976
3977         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3978                 return;
3979
3980         DRM_DEBUG_KMS("\n");
3981
3982         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3983             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3984                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3985                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3986         } else {
3987                 DP &= ~DP_LINK_TRAIN_MASK;
3988                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3989         }
3990         I915_WRITE(intel_dp->output_reg, DP);
3991         POSTING_READ(intel_dp->output_reg);
3992
3993         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3994         I915_WRITE(intel_dp->output_reg, DP);
3995         POSTING_READ(intel_dp->output_reg);
3996
3997         /*
3998          * HW workaround for IBX, we need to move the port
3999          * to transcoder A after disabling it to allow the
4000          * matching HDMI port to be enabled on transcoder A.
4001          */
4002         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4003                 /*
4004                  * We get CPU/PCH FIFO underruns on the other pipe when
4005                  * doing the workaround. Sweep them under the rug.
4006                  */
4007                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4008                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4009
4010                 /* always enable with pattern 1 (as per spec) */
4011                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4012                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4013                         DP_LINK_TRAIN_PAT_1;
4014                 I915_WRITE(intel_dp->output_reg, DP);
4015                 POSTING_READ(intel_dp->output_reg);
4016
4017                 DP &= ~DP_PORT_EN;
4018                 I915_WRITE(intel_dp->output_reg, DP);
4019                 POSTING_READ(intel_dp->output_reg);
4020
4021                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4022                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4023                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4024         }
4025
4026         msleep(intel_dp->panel_power_down_delay);
4027
4028         intel_dp->DP = DP;
4029
4030         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4031                 intel_wakeref_t wakeref;
4032
4033                 with_pps_lock(intel_dp, wakeref)
4034                         intel_dp->active_pipe = INVALID_PIPE;
4035         }
4036 }
4037
4038 static void
4039 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4040 {
4041         u8 dpcd_ext[6];
4042
4043         /*
4044          * Prior to DP1.3 the bit represented by
4045          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4046          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4047          * the true capability of the panel. The only way to check is to
4048          * then compare 0000h and 2200h.
4049          */
4050         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4051               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4052                 return;
4053
4054         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4055                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4056                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4057                 return;
4058         }
4059
4060         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4061                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4062                 return;
4063         }
4064
4065         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4066                 return;
4067
4068         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4069                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4070
4071         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4072 }
4073
4074 bool
4075 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4076 {
4077         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4078                              sizeof(intel_dp->dpcd)) < 0)
4079                 return false; /* aux transfer failed */
4080
4081         intel_dp_extended_receiver_capabilities(intel_dp);
4082
4083         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4084
4085         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4086 }
4087
4088 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4089 {
4090         u8 dprx = 0;
4091
4092         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4093                               &dprx) != 1)
4094                 return false;
4095         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4096 }
4097
4098 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4099 {
4100         /*
4101          * Clear the cached register set to avoid using stale values
4102          * for the sinks that do not support DSC.
4103          */
4104         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4105
4106         /* Clear fec_capable to avoid using stale values */
4107         intel_dp->fec_capable = 0;
4108
4109         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4110         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4111             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4112                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4113                                      intel_dp->dsc_dpcd,
4114                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4115                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4116                                   DP_DSC_SUPPORT);
4117
4118                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4119                               (int)sizeof(intel_dp->dsc_dpcd),
4120                               intel_dp->dsc_dpcd);
4121
4122                 /* FEC is supported only on DP 1.4 */
4123                 if (!intel_dp_is_edp(intel_dp) &&
4124                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4125                                       &intel_dp->fec_capable) < 0)
4126                         DRM_ERROR("Failed to read FEC DPCD register\n");
4127
4128                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4129         }
4130 }
4131
4132 static bool
4133 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4134 {
4135         struct drm_i915_private *dev_priv =
4136                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4137
4138         /* this function is meant to be called only once */
4139         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4140
4141         if (!intel_dp_read_dpcd(intel_dp))
4142                 return false;
4143
4144         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4145                          drm_dp_is_branch(intel_dp->dpcd));
4146
4147         /*
4148          * Read the eDP display control registers.
4149          *
4150          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4151          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4152          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4153          * method). The display control registers should read zero if they're
4154          * not supported anyway.
4155          */
4156         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4157                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4158                              sizeof(intel_dp->edp_dpcd))
4159                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4160                               intel_dp->edp_dpcd);
4161
4162         /*
4163          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4164          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4165          */
4166         intel_psr_init_dpcd(intel_dp);
4167
4168         /* Read the eDP 1.4+ supported link rates. */
4169         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4170                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4171                 int i;
4172
4173                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4174                                 sink_rates, sizeof(sink_rates));
4175
4176                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4177                         int val = le16_to_cpu(sink_rates[i]);
4178
4179                         if (val == 0)
4180                                 break;
4181
4182                         /* Value read multiplied by 200kHz gives the per-lane
4183                          * link rate in kHz. The source rates are, however,
4184                          * stored in terms of LS_Clk kHz. The full conversion
4185                          * back to symbols is
4186                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4187                          */
4188                         intel_dp->sink_rates[i] = (val * 200) / 10;
4189                 }
4190                 intel_dp->num_sink_rates = i;
4191         }
4192
4193         /*
4194          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4195          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4196          */
4197         if (intel_dp->num_sink_rates)
4198                 intel_dp->use_rate_select = true;
4199         else
4200                 intel_dp_set_sink_rates(intel_dp);
4201
4202         intel_dp_set_common_rates(intel_dp);
4203
4204         /* Read the eDP DSC DPCD registers */
4205         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4206                 intel_dp_get_dsc_sink_cap(intel_dp);
4207
4208         return true;
4209 }
4210
4211
4212 static bool
4213 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4214 {
4215         if (!intel_dp_read_dpcd(intel_dp))
4216                 return false;
4217
4218         /*
4219          * Don't clobber cached eDP rates. Also skip re-reading
4220          * the OUI/ID since we know it won't change.
4221          */
4222         if (!intel_dp_is_edp(intel_dp)) {
4223                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4224                                  drm_dp_is_branch(intel_dp->dpcd));
4225
4226                 intel_dp_set_sink_rates(intel_dp);
4227                 intel_dp_set_common_rates(intel_dp);
4228         }
4229
4230         /*
4231          * Some eDP panels do not set a valid value for sink count, that is why
4232          * it don't care about read it here and in intel_edp_init_dpcd().
4233          */
4234         if (!intel_dp_is_edp(intel_dp) &&
4235             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4236                 u8 count;
4237                 ssize_t r;
4238
4239                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4240                 if (r < 1)
4241                         return false;
4242
4243                 /*
4244                  * Sink count can change between short pulse hpd hence
4245                  * a member variable in intel_dp will track any changes
4246                  * between short pulse interrupts.
4247                  */
4248                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4249
4250                 /*
4251                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4252                  * a dongle is present but no display. Unless we require to know
4253                  * if a dongle is present or not, we don't need to update
4254                  * downstream port information. So, an early return here saves
4255                  * time from performing other operations which are not required.
4256                  */
4257                 if (!intel_dp->sink_count)
4258                         return false;
4259         }
4260
4261         if (!drm_dp_is_branch(intel_dp->dpcd))
4262                 return true; /* native DP sink */
4263
4264         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4265                 return true; /* no per-port downstream info */
4266
4267         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4268                              intel_dp->downstream_ports,
4269                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4270                 return false; /* downstream port status fetch failed */
4271
4272         return true;
4273 }
4274
4275 static bool
4276 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4277 {
4278         u8 mstm_cap;
4279
4280         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4281                 return false;
4282
4283         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4284                 return false;
4285
4286         return mstm_cap & DP_MST_CAP;
4287 }
4288
4289 static bool
4290 intel_dp_can_mst(struct intel_dp *intel_dp)
4291 {
4292         return i915_modparams.enable_dp_mst &&
4293                 intel_dp->can_mst &&
4294                 intel_dp_sink_can_mst(intel_dp);
4295 }
4296
4297 static void
4298 intel_dp_configure_mst(struct intel_dp *intel_dp)
4299 {
4300         struct intel_encoder *encoder =
4301                 &dp_to_dig_port(intel_dp)->base;
4302         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4303
4304         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4305                       port_name(encoder->port), yesno(intel_dp->can_mst),
4306                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4307
4308         if (!intel_dp->can_mst)
4309                 return;
4310
4311         intel_dp->is_mst = sink_can_mst &&
4312                 i915_modparams.enable_dp_mst;
4313
4314         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4315                                         intel_dp->is_mst);
4316 }
4317
4318 static bool
4319 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4320 {
4321         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4322                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4323                 DP_DPRX_ESI_LEN;
4324 }
4325
4326 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4327                                 int mode_clock, int mode_hdisplay)
4328 {
4329         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4330         int i;
4331
4332         /*
4333          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4334          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4335          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4336          * for MST -> TimeSlotsPerMTP has to be calculated
4337          */
4338         bits_per_pixel = (link_clock * lane_count * 8 *
4339                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4340                 mode_clock;
4341
4342         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4343         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4344                 mode_hdisplay;
4345
4346         /*
4347          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4348          * check, output bpp from small joiner RAM check)
4349          */
4350         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4351
4352         /* Error out if the max bpp is less than smallest allowed valid bpp */
4353         if (bits_per_pixel < valid_dsc_bpp[0]) {
4354                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4355                 return 0;
4356         }
4357
4358         /* Find the nearest match in the array of known BPPs from VESA */
4359         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4360                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4361                         break;
4362         }
4363         bits_per_pixel = valid_dsc_bpp[i];
4364
4365         /*
4366          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4367          * fractional part is 0
4368          */
4369         return bits_per_pixel << 4;
4370 }
4371
4372 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4373                                 int mode_clock,
4374                                 int mode_hdisplay)
4375 {
4376         u8 min_slice_count, i;
4377         int max_slice_width;
4378
4379         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4380                 min_slice_count = DIV_ROUND_UP(mode_clock,
4381                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4382         else
4383                 min_slice_count = DIV_ROUND_UP(mode_clock,
4384                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4385
4386         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4387         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4388                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4389                               max_slice_width);
4390                 return 0;
4391         }
4392         /* Also take into account max slice width */
4393         min_slice_count = min_t(u8, min_slice_count,
4394                                 DIV_ROUND_UP(mode_hdisplay,
4395                                              max_slice_width));
4396
4397         /* Find the closest match to the valid slice count values */
4398         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4399                 if (valid_dsc_slicecount[i] >
4400                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4401                                                     false))
4402                         break;
4403                 if (min_slice_count  <= valid_dsc_slicecount[i])
4404                         return valid_dsc_slicecount[i];
4405         }
4406
4407         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4408         return 0;
4409 }
4410
4411 static void
4412 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
4413                                const struct intel_crtc_state *crtc_state)
4414 {
4415         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4416         struct dp_sdp vsc_sdp = {};
4417
4418         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4419         vsc_sdp.sdp_header.HB0 = 0;
4420         vsc_sdp.sdp_header.HB1 = 0x7;
4421
4422         /*
4423          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4424          * Colorimetry Format indication.
4425          */
4426         vsc_sdp.sdp_header.HB2 = 0x5;
4427
4428         /*
4429          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4430          * Colorimetry Format indication (HB2 = 05h).
4431          */
4432         vsc_sdp.sdp_header.HB3 = 0x13;
4433
4434         /*
4435          * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
4436          * DB16[3:0] DP 1.4a spec, Table 2-120
4437          */
4438         vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
4439         /* RGB->YCBCR color conversion uses the BT.709 color space. */
4440         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4441
4442         /*
4443          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4444          * the following Component Bit Depth values are defined:
4445          * 001b = 8bpc.
4446          * 010b = 10bpc.
4447          * 011b = 12bpc.
4448          * 100b = 16bpc.
4449          */
4450         switch (crtc_state->pipe_bpp) {
4451         case 24: /* 8bpc */
4452                 vsc_sdp.db[17] = 0x1;
4453                 break;
4454         case 30: /* 10bpc */
4455                 vsc_sdp.db[17] = 0x2;
4456                 break;
4457         case 36: /* 12bpc */
4458                 vsc_sdp.db[17] = 0x3;
4459                 break;
4460         case 48: /* 16bpc */
4461                 vsc_sdp.db[17] = 0x4;
4462                 break;
4463         default:
4464                 MISSING_CASE(crtc_state->pipe_bpp);
4465                 break;
4466         }
4467
4468         /*
4469          * Dynamic Range (Bit 7)
4470          * 0 = VESA range, 1 = CTA range.
4471          * all YCbCr are always limited range
4472          */
4473         vsc_sdp.db[17] |= 0x80;
4474
4475         /*
4476          * Content Type (Bits 2:0)
4477          * 000b = Not defined.
4478          * 001b = Graphics.
4479          * 010b = Photo.
4480          * 011b = Video.
4481          * 100b = Game
4482          * All other values are RESERVED.
4483          * Note: See CTA-861-G for the definition and expected
4484          * processing by a stream sink for the above contect types.
4485          */
4486         vsc_sdp.db[18] = 0;
4487
4488         intel_dig_port->write_infoframe(&intel_dig_port->base,
4489                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4490 }
4491
4492 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
4493                                const struct intel_crtc_state *crtc_state)
4494 {
4495         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
4496                 return;
4497
4498         intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
4499 }
4500
4501 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4502 {
4503         int status = 0;
4504         int test_link_rate;
4505         u8 test_lane_count, test_link_bw;
4506         /* (DP CTS 1.2)
4507          * 4.3.1.11
4508          */
4509         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4510         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4511                                    &test_lane_count);
4512
4513         if (status <= 0) {
4514                 DRM_DEBUG_KMS("Lane count read failed\n");
4515                 return DP_TEST_NAK;
4516         }
4517         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4518
4519         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4520                                    &test_link_bw);
4521         if (status <= 0) {
4522                 DRM_DEBUG_KMS("Link Rate read failed\n");
4523                 return DP_TEST_NAK;
4524         }
4525         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4526
4527         /* Validate the requested link rate and lane count */
4528         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4529                                         test_lane_count))
4530                 return DP_TEST_NAK;
4531
4532         intel_dp->compliance.test_lane_count = test_lane_count;
4533         intel_dp->compliance.test_link_rate = test_link_rate;
4534
4535         return DP_TEST_ACK;
4536 }
4537
4538 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4539 {
4540         u8 test_pattern;
4541         u8 test_misc;
4542         __be16 h_width, v_height;
4543         int status = 0;
4544
4545         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4546         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4547                                    &test_pattern);
4548         if (status <= 0) {
4549                 DRM_DEBUG_KMS("Test pattern read failed\n");
4550                 return DP_TEST_NAK;
4551         }
4552         if (test_pattern != DP_COLOR_RAMP)
4553                 return DP_TEST_NAK;
4554
4555         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4556                                   &h_width, 2);
4557         if (status <= 0) {
4558                 DRM_DEBUG_KMS("H Width read failed\n");
4559                 return DP_TEST_NAK;
4560         }
4561
4562         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4563                                   &v_height, 2);
4564         if (status <= 0) {
4565                 DRM_DEBUG_KMS("V Height read failed\n");
4566                 return DP_TEST_NAK;
4567         }
4568
4569         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4570                                    &test_misc);
4571         if (status <= 0) {
4572                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4573                 return DP_TEST_NAK;
4574         }
4575         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4576                 return DP_TEST_NAK;
4577         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4578                 return DP_TEST_NAK;
4579         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4580         case DP_TEST_BIT_DEPTH_6:
4581                 intel_dp->compliance.test_data.bpc = 6;
4582                 break;
4583         case DP_TEST_BIT_DEPTH_8:
4584                 intel_dp->compliance.test_data.bpc = 8;
4585                 break;
4586         default:
4587                 return DP_TEST_NAK;
4588         }
4589
4590         intel_dp->compliance.test_data.video_pattern = test_pattern;
4591         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4592         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4593         /* Set test active flag here so userspace doesn't interrupt things */
4594         intel_dp->compliance.test_active = 1;
4595
4596         return DP_TEST_ACK;
4597 }
4598
4599 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4600 {
4601         u8 test_result = DP_TEST_ACK;
4602         struct intel_connector *intel_connector = intel_dp->attached_connector;
4603         struct drm_connector *connector = &intel_connector->base;
4604
4605         if (intel_connector->detect_edid == NULL ||
4606             connector->edid_corrupt ||
4607             intel_dp->aux.i2c_defer_count > 6) {
4608                 /* Check EDID read for NACKs, DEFERs and corruption
4609                  * (DP CTS 1.2 Core r1.1)
4610                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4611                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4612                  *    4.2.2.6 : EDID corruption detected
4613                  * Use failsafe mode for all cases
4614                  */
4615                 if (intel_dp->aux.i2c_nack_count > 0 ||
4616                         intel_dp->aux.i2c_defer_count > 0)
4617                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4618                                       intel_dp->aux.i2c_nack_count,
4619                                       intel_dp->aux.i2c_defer_count);
4620                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4621         } else {
4622                 struct edid *block = intel_connector->detect_edid;
4623
4624                 /* We have to write the checksum
4625                  * of the last block read
4626                  */
4627                 block += intel_connector->detect_edid->extensions;
4628
4629                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4630                                        block->checksum) <= 0)
4631                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4632
4633                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4634                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4635         }
4636
4637         /* Set test active flag here so userspace doesn't interrupt things */
4638         intel_dp->compliance.test_active = 1;
4639
4640         return test_result;
4641 }
4642
4643 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4644 {
4645         u8 test_result = DP_TEST_NAK;
4646         return test_result;
4647 }
4648
4649 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4650 {
4651         u8 response = DP_TEST_NAK;
4652         u8 request = 0;
4653         int status;
4654
4655         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4656         if (status <= 0) {
4657                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4658                 goto update_status;
4659         }
4660
4661         switch (request) {
4662         case DP_TEST_LINK_TRAINING:
4663                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4664                 response = intel_dp_autotest_link_training(intel_dp);
4665                 break;
4666         case DP_TEST_LINK_VIDEO_PATTERN:
4667                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4668                 response = intel_dp_autotest_video_pattern(intel_dp);
4669                 break;
4670         case DP_TEST_LINK_EDID_READ:
4671                 DRM_DEBUG_KMS("EDID test requested\n");
4672                 response = intel_dp_autotest_edid(intel_dp);
4673                 break;
4674         case DP_TEST_LINK_PHY_TEST_PATTERN:
4675                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4676                 response = intel_dp_autotest_phy_pattern(intel_dp);
4677                 break;
4678         default:
4679                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4680                 break;
4681         }
4682
4683         if (response & DP_TEST_ACK)
4684                 intel_dp->compliance.test_type = request;
4685
4686 update_status:
4687         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4688         if (status <= 0)
4689                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4690 }
4691
4692 static int
4693 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4694 {
4695         bool bret;
4696
4697         if (intel_dp->is_mst) {
4698                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4699                 int ret = 0;
4700                 int retry;
4701                 bool handled;
4702
4703                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4704                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4705 go_again:
4706                 if (bret == true) {
4707
4708                         /* check link status - esi[10] = 0x200c */
4709                         if (intel_dp->active_mst_links > 0 &&
4710                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4711                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4712                                 intel_dp_start_link_train(intel_dp);
4713                                 intel_dp_stop_link_train(intel_dp);
4714                         }
4715
4716                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4717                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4718
4719                         if (handled) {
4720                                 for (retry = 0; retry < 3; retry++) {
4721                                         int wret;
4722                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4723                                                                  DP_SINK_COUNT_ESI+1,
4724                                                                  &esi[1], 3);
4725                                         if (wret == 3) {
4726                                                 break;
4727                                         }
4728                                 }
4729
4730                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4731                                 if (bret == true) {
4732                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4733                                         goto go_again;
4734                                 }
4735                         } else
4736                                 ret = 0;
4737
4738                         return ret;
4739                 } else {
4740                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4741                         intel_dp->is_mst = false;
4742                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4743                                                         intel_dp->is_mst);
4744                 }
4745         }
4746         return -EINVAL;
4747 }
4748
4749 static bool
4750 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4751 {
4752         u8 link_status[DP_LINK_STATUS_SIZE];
4753
4754         if (!intel_dp->link_trained)
4755                 return false;
4756
4757         /*
4758          * While PSR source HW is enabled, it will control main-link sending
4759          * frames, enabling and disabling it so trying to do a retrain will fail
4760          * as the link would or not be on or it could mix training patterns
4761          * and frame data at the same time causing retrain to fail.
4762          * Also when exiting PSR, HW will retrain the link anyways fixing
4763          * any link status error.
4764          */
4765         if (intel_psr_enabled(intel_dp))
4766                 return false;
4767
4768         if (!intel_dp_get_link_status(intel_dp, link_status))
4769                 return false;
4770
4771         /*
4772          * Validate the cached values of intel_dp->link_rate and
4773          * intel_dp->lane_count before attempting to retrain.
4774          */
4775         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4776                                         intel_dp->lane_count))
4777                 return false;
4778
4779         /* Retrain if Channel EQ or CR not ok */
4780         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4781 }
4782
4783 int intel_dp_retrain_link(struct intel_encoder *encoder,
4784                           struct drm_modeset_acquire_ctx *ctx)
4785 {
4786         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4787         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4788         struct intel_connector *connector = intel_dp->attached_connector;
4789         struct drm_connector_state *conn_state;
4790         struct intel_crtc_state *crtc_state;
4791         struct intel_crtc *crtc;
4792         int ret;
4793
4794         /* FIXME handle the MST connectors as well */
4795
4796         if (!connector || connector->base.status != connector_status_connected)
4797                 return 0;
4798
4799         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4800                                ctx);
4801         if (ret)
4802                 return ret;
4803
4804         conn_state = connector->base.state;
4805
4806         crtc = to_intel_crtc(conn_state->crtc);
4807         if (!crtc)
4808                 return 0;
4809
4810         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4811         if (ret)
4812                 return ret;
4813
4814         crtc_state = to_intel_crtc_state(crtc->base.state);
4815
4816         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4817
4818         if (!crtc_state->base.active)
4819                 return 0;
4820
4821         if (conn_state->commit &&
4822             !try_wait_for_completion(&conn_state->commit->hw_done))
4823                 return 0;
4824
4825         if (!intel_dp_needs_link_retrain(intel_dp))
4826                 return 0;
4827
4828         /* Suppress underruns caused by re-training */
4829         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4830         if (crtc_state->has_pch_encoder)
4831                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4832                                                       intel_crtc_pch_transcoder(crtc), false);
4833
4834         intel_dp_start_link_train(intel_dp);
4835         intel_dp_stop_link_train(intel_dp);
4836
4837         /* Keep underrun reporting disabled until things are stable */
4838         intel_wait_for_vblank(dev_priv, crtc->pipe);
4839
4840         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4841         if (crtc_state->has_pch_encoder)
4842                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4843                                                       intel_crtc_pch_transcoder(crtc), true);
4844
4845         return 0;
4846 }
4847
4848 /*
4849  * If display is now connected check links status,
4850  * there has been known issues of link loss triggering
4851  * long pulse.
4852  *
4853  * Some sinks (eg. ASUS PB287Q) seem to perform some
4854  * weird HPD ping pong during modesets. So we can apparently
4855  * end up with HPD going low during a modeset, and then
4856  * going back up soon after. And once that happens we must
4857  * retrain the link to get a picture. That's in case no
4858  * userspace component reacted to intermittent HPD dip.
4859  */
4860 static enum intel_hotplug_state
4861 intel_dp_hotplug(struct intel_encoder *encoder,
4862                  struct intel_connector *connector,
4863                  bool irq_received)
4864 {
4865         struct drm_modeset_acquire_ctx ctx;
4866         enum intel_hotplug_state state;
4867         int ret;
4868
4869         state = intel_encoder_hotplug(encoder, connector, irq_received);
4870
4871         drm_modeset_acquire_init(&ctx, 0);
4872
4873         for (;;) {
4874                 ret = intel_dp_retrain_link(encoder, &ctx);
4875
4876                 if (ret == -EDEADLK) {
4877                         drm_modeset_backoff(&ctx);
4878                         continue;
4879                 }
4880
4881                 break;
4882         }
4883
4884         drm_modeset_drop_locks(&ctx);
4885         drm_modeset_acquire_fini(&ctx);
4886         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4887
4888         /*
4889          * Keeping it consistent with intel_ddi_hotplug() and
4890          * intel_hdmi_hotplug().
4891          */
4892         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
4893                 state = INTEL_HOTPLUG_RETRY;
4894
4895         return state;
4896 }
4897
4898 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4899 {
4900         u8 val;
4901
4902         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4903                 return;
4904
4905         if (drm_dp_dpcd_readb(&intel_dp->aux,
4906                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4907                 return;
4908
4909         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4910
4911         if (val & DP_AUTOMATED_TEST_REQUEST)
4912                 intel_dp_handle_test_request(intel_dp);
4913
4914         if (val & DP_CP_IRQ)
4915                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4916
4917         if (val & DP_SINK_SPECIFIC_IRQ)
4918                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4919 }
4920
4921 /*
4922  * According to DP spec
4923  * 5.1.2:
4924  *  1. Read DPCD
4925  *  2. Configure link according to Receiver Capabilities
4926  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4927  *  4. Check link status on receipt of hot-plug interrupt
4928  *
4929  * intel_dp_short_pulse -  handles short pulse interrupts
4930  * when full detection is not required.
4931  * Returns %true if short pulse is handled and full detection
4932  * is NOT required and %false otherwise.
4933  */
4934 static bool
4935 intel_dp_short_pulse(struct intel_dp *intel_dp)
4936 {
4937         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4938         u8 old_sink_count = intel_dp->sink_count;
4939         bool ret;
4940
4941         /*
4942          * Clearing compliance test variables to allow capturing
4943          * of values for next automated test request.
4944          */
4945         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4946
4947         /*
4948          * Now read the DPCD to see if it's actually running
4949          * If the current value of sink count doesn't match with
4950          * the value that was stored earlier or dpcd read failed
4951          * we need to do full detection
4952          */
4953         ret = intel_dp_get_dpcd(intel_dp);
4954
4955         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4956                 /* No need to proceed if we are going to do full detect */
4957                 return false;
4958         }
4959
4960         intel_dp_check_service_irq(intel_dp);
4961
4962         /* Handle CEC interrupts, if any */
4963         drm_dp_cec_irq(&intel_dp->aux);
4964
4965         /* defer to the hotplug work for link retraining if needed */
4966         if (intel_dp_needs_link_retrain(intel_dp))
4967                 return false;
4968
4969         intel_psr_short_pulse(intel_dp);
4970
4971         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4972                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4973                 /* Send a Hotplug Uevent to userspace to start modeset */
4974                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4975         }
4976
4977         return true;
4978 }
4979
4980 /* XXX this is probably wrong for multiple downstream ports */
4981 static enum drm_connector_status
4982 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4983 {
4984         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4985         u8 *dpcd = intel_dp->dpcd;
4986         u8 type;
4987
4988         if (WARN_ON(intel_dp_is_edp(intel_dp)))
4989                 return connector_status_connected;
4990
4991         if (lspcon->active)
4992                 lspcon_resume(lspcon);
4993
4994         if (!intel_dp_get_dpcd(intel_dp))
4995                 return connector_status_disconnected;
4996
4997         /* if there's no downstream port, we're done */
4998         if (!drm_dp_is_branch(dpcd))
4999                 return connector_status_connected;
5000
5001         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5002         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5003             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5004
5005                 return intel_dp->sink_count ?
5006                 connector_status_connected : connector_status_disconnected;
5007         }
5008
5009         if (intel_dp_can_mst(intel_dp))
5010                 return connector_status_connected;
5011
5012         /* If no HPD, poke DDC gently */
5013         if (drm_probe_ddc(&intel_dp->aux.ddc))
5014                 return connector_status_connected;
5015
5016         /* Well we tried, say unknown for unreliable port types */
5017         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5018                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5019                 if (type == DP_DS_PORT_TYPE_VGA ||
5020                     type == DP_DS_PORT_TYPE_NON_EDID)
5021                         return connector_status_unknown;
5022         } else {
5023                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5024                         DP_DWN_STRM_PORT_TYPE_MASK;
5025                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5026                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5027                         return connector_status_unknown;
5028         }
5029
5030         /* Anything else is out of spec, warn and ignore */
5031         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5032         return connector_status_disconnected;
5033 }
5034
5035 static enum drm_connector_status
5036 edp_detect(struct intel_dp *intel_dp)
5037 {
5038         return connector_status_connected;
5039 }
5040
5041 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5042 {
5043         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5044         u32 bit;
5045
5046         switch (encoder->hpd_pin) {
5047         case HPD_PORT_B:
5048                 bit = SDE_PORTB_HOTPLUG;
5049                 break;
5050         case HPD_PORT_C:
5051                 bit = SDE_PORTC_HOTPLUG;
5052                 break;
5053         case HPD_PORT_D:
5054                 bit = SDE_PORTD_HOTPLUG;
5055                 break;
5056         default:
5057                 MISSING_CASE(encoder->hpd_pin);
5058                 return false;
5059         }
5060
5061         return I915_READ(SDEISR) & bit;
5062 }
5063
5064 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5067         u32 bit;
5068
5069         switch (encoder->hpd_pin) {
5070         case HPD_PORT_B:
5071                 bit = SDE_PORTB_HOTPLUG_CPT;
5072                 break;
5073         case HPD_PORT_C:
5074                 bit = SDE_PORTC_HOTPLUG_CPT;
5075                 break;
5076         case HPD_PORT_D:
5077                 bit = SDE_PORTD_HOTPLUG_CPT;
5078                 break;
5079         default:
5080                 MISSING_CASE(encoder->hpd_pin);
5081                 return false;
5082         }
5083
5084         return I915_READ(SDEISR) & bit;
5085 }
5086
5087 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5088 {
5089         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5090         u32 bit;
5091
5092         switch (encoder->hpd_pin) {
5093         case HPD_PORT_A:
5094                 bit = SDE_PORTA_HOTPLUG_SPT;
5095                 break;
5096         case HPD_PORT_E:
5097                 bit = SDE_PORTE_HOTPLUG_SPT;
5098                 break;
5099         default:
5100                 return cpt_digital_port_connected(encoder);
5101         }
5102
5103         return I915_READ(SDEISR) & bit;
5104 }
5105
5106 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5107 {
5108         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5109         u32 bit;
5110
5111         switch (encoder->hpd_pin) {
5112         case HPD_PORT_B:
5113                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5114                 break;
5115         case HPD_PORT_C:
5116                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5117                 break;
5118         case HPD_PORT_D:
5119                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5120                 break;
5121         default:
5122                 MISSING_CASE(encoder->hpd_pin);
5123                 return false;
5124         }
5125
5126         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5127 }
5128
5129 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5130 {
5131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5132         u32 bit;
5133
5134         switch (encoder->hpd_pin) {
5135         case HPD_PORT_B:
5136                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5137                 break;
5138         case HPD_PORT_C:
5139                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5140                 break;
5141         case HPD_PORT_D:
5142                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5143                 break;
5144         default:
5145                 MISSING_CASE(encoder->hpd_pin);
5146                 return false;
5147         }
5148
5149         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5150 }
5151
5152 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5153 {
5154         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5155
5156         if (encoder->hpd_pin == HPD_PORT_A)
5157                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5158         else
5159                 return ibx_digital_port_connected(encoder);
5160 }
5161
5162 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5163 {
5164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5165
5166         if (encoder->hpd_pin == HPD_PORT_A)
5167                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5168         else
5169                 return cpt_digital_port_connected(encoder);
5170 }
5171
5172 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5173 {
5174         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5175
5176         if (encoder->hpd_pin == HPD_PORT_A)
5177                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5178         else
5179                 return cpt_digital_port_connected(encoder);
5180 }
5181
5182 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5183 {
5184         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5185
5186         if (encoder->hpd_pin == HPD_PORT_A)
5187                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5188         else
5189                 return cpt_digital_port_connected(encoder);
5190 }
5191
5192 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5193 {
5194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5195         u32 bit;
5196
5197         switch (encoder->hpd_pin) {
5198         case HPD_PORT_A:
5199                 bit = BXT_DE_PORT_HP_DDIA;
5200                 break;
5201         case HPD_PORT_B:
5202                 bit = BXT_DE_PORT_HP_DDIB;
5203                 break;
5204         case HPD_PORT_C:
5205                 bit = BXT_DE_PORT_HP_DDIC;
5206                 break;
5207         default:
5208                 MISSING_CASE(encoder->hpd_pin);
5209                 return false;
5210         }
5211
5212         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5213 }
5214
5215 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5216                                      struct intel_digital_port *intel_dig_port)
5217 {
5218         enum port port = intel_dig_port->base.port;
5219
5220         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5221 }
5222
5223 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5224 {
5225         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5226         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5227         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5228
5229         if (intel_phy_is_combo(dev_priv, phy))
5230                 return icl_combo_port_connected(dev_priv, dig_port);
5231         else if (intel_phy_is_tc(dev_priv, phy))
5232                 return intel_tc_port_connected(dig_port);
5233         else
5234                 MISSING_CASE(encoder->hpd_pin);
5235
5236         return false;
5237 }
5238
5239 /*
5240  * intel_digital_port_connected - is the specified port connected?
5241  * @encoder: intel_encoder
5242  *
5243  * In cases where there's a connector physically connected but it can't be used
5244  * by our hardware we also return false, since the rest of the driver should
5245  * pretty much treat the port as disconnected. This is relevant for type-C
5246  * (starting on ICL) where there's ownership involved.
5247  *
5248  * Return %true if port is connected, %false otherwise.
5249  */
5250 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5251 {
5252         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5253
5254         if (HAS_GMCH(dev_priv)) {
5255                 if (IS_GM45(dev_priv))
5256                         return gm45_digital_port_connected(encoder);
5257                 else
5258                         return g4x_digital_port_connected(encoder);
5259         }
5260
5261         if (INTEL_GEN(dev_priv) >= 11)
5262                 return icl_digital_port_connected(encoder);
5263         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5264                 return spt_digital_port_connected(encoder);
5265         else if (IS_GEN9_LP(dev_priv))
5266                 return bxt_digital_port_connected(encoder);
5267         else if (IS_GEN(dev_priv, 8))
5268                 return bdw_digital_port_connected(encoder);
5269         else if (IS_GEN(dev_priv, 7))
5270                 return ivb_digital_port_connected(encoder);
5271         else if (IS_GEN(dev_priv, 6))
5272                 return snb_digital_port_connected(encoder);
5273         else if (IS_GEN(dev_priv, 5))
5274                 return ilk_digital_port_connected(encoder);
5275
5276         MISSING_CASE(INTEL_GEN(dev_priv));
5277         return false;
5278 }
5279
5280 bool intel_digital_port_connected(struct intel_encoder *encoder)
5281 {
5282         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5283         bool is_connected = false;
5284         intel_wakeref_t wakeref;
5285
5286         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5287                 is_connected = __intel_digital_port_connected(encoder);
5288
5289         return is_connected;
5290 }
5291
5292 static struct edid *
5293 intel_dp_get_edid(struct intel_dp *intel_dp)
5294 {
5295         struct intel_connector *intel_connector = intel_dp->attached_connector;
5296
5297         /* use cached edid if we have one */
5298         if (intel_connector->edid) {
5299                 /* invalid edid */
5300                 if (IS_ERR(intel_connector->edid))
5301                         return NULL;
5302
5303                 return drm_edid_duplicate(intel_connector->edid);
5304         } else
5305                 return drm_get_edid(&intel_connector->base,
5306                                     &intel_dp->aux.ddc);
5307 }
5308
5309 static void
5310 intel_dp_set_edid(struct intel_dp *intel_dp)
5311 {
5312         struct intel_connector *intel_connector = intel_dp->attached_connector;
5313         struct edid *edid;
5314
5315         intel_dp_unset_edid(intel_dp);
5316         edid = intel_dp_get_edid(intel_dp);
5317         intel_connector->detect_edid = edid;
5318
5319         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5320         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5321 }
5322
5323 static void
5324 intel_dp_unset_edid(struct intel_dp *intel_dp)
5325 {
5326         struct intel_connector *intel_connector = intel_dp->attached_connector;
5327
5328         drm_dp_cec_unset_edid(&intel_dp->aux);
5329         kfree(intel_connector->detect_edid);
5330         intel_connector->detect_edid = NULL;
5331
5332         intel_dp->has_audio = false;
5333 }
5334
5335 static int
5336 intel_dp_detect(struct drm_connector *connector,
5337                 struct drm_modeset_acquire_ctx *ctx,
5338                 bool force)
5339 {
5340         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5341         struct intel_dp *intel_dp = intel_attached_dp(connector);
5342         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5343         struct intel_encoder *encoder = &dig_port->base;
5344         enum drm_connector_status status;
5345
5346         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5347                       connector->base.id, connector->name);
5348         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5349
5350         /* Can't disconnect eDP */
5351         if (intel_dp_is_edp(intel_dp))
5352                 status = edp_detect(intel_dp);
5353         else if (intel_digital_port_connected(encoder))
5354                 status = intel_dp_detect_dpcd(intel_dp);
5355         else
5356                 status = connector_status_disconnected;
5357
5358         if (status == connector_status_disconnected) {
5359                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5360                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5361
5362                 if (intel_dp->is_mst) {
5363                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5364                                       intel_dp->is_mst,
5365                                       intel_dp->mst_mgr.mst_state);
5366                         intel_dp->is_mst = false;
5367                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5368                                                         intel_dp->is_mst);
5369                 }
5370
5371                 goto out;
5372         }
5373
5374         if (intel_dp->reset_link_params) {
5375                 /* Initial max link lane count */
5376                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5377
5378                 /* Initial max link rate */
5379                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5380
5381                 intel_dp->reset_link_params = false;
5382         }
5383
5384         intel_dp_print_rates(intel_dp);
5385
5386         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5387         if (INTEL_GEN(dev_priv) >= 11)
5388                 intel_dp_get_dsc_sink_cap(intel_dp);
5389
5390         intel_dp_configure_mst(intel_dp);
5391
5392         if (intel_dp->is_mst) {
5393                 /*
5394                  * If we are in MST mode then this connector
5395                  * won't appear connected or have anything
5396                  * with EDID on it
5397                  */
5398                 status = connector_status_disconnected;
5399                 goto out;
5400         }
5401
5402         /*
5403          * Some external monitors do not signal loss of link synchronization
5404          * with an IRQ_HPD, so force a link status check.
5405          */
5406         if (!intel_dp_is_edp(intel_dp)) {
5407                 int ret;
5408
5409                 ret = intel_dp_retrain_link(encoder, ctx);
5410                 if (ret)
5411                         return ret;
5412         }
5413
5414         /*
5415          * Clearing NACK and defer counts to get their exact values
5416          * while reading EDID which are required by Compliance tests
5417          * 4.2.2.4 and 4.2.2.5
5418          */
5419         intel_dp->aux.i2c_nack_count = 0;
5420         intel_dp->aux.i2c_defer_count = 0;
5421
5422         intel_dp_set_edid(intel_dp);
5423         if (intel_dp_is_edp(intel_dp) ||
5424             to_intel_connector(connector)->detect_edid)
5425                 status = connector_status_connected;
5426
5427         intel_dp_check_service_irq(intel_dp);
5428
5429 out:
5430         if (status != connector_status_connected && !intel_dp->is_mst)
5431                 intel_dp_unset_edid(intel_dp);
5432
5433         return status;
5434 }
5435
5436 static void
5437 intel_dp_force(struct drm_connector *connector)
5438 {
5439         struct intel_dp *intel_dp = intel_attached_dp(connector);
5440         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5441         struct intel_encoder *intel_encoder = &dig_port->base;
5442         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5443         enum intel_display_power_domain aux_domain =
5444                 intel_aux_power_domain(dig_port);
5445         intel_wakeref_t wakeref;
5446
5447         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5448                       connector->base.id, connector->name);
5449         intel_dp_unset_edid(intel_dp);
5450
5451         if (connector->status != connector_status_connected)
5452                 return;
5453
5454         wakeref = intel_display_power_get(dev_priv, aux_domain);
5455
5456         intel_dp_set_edid(intel_dp);
5457
5458         intel_display_power_put(dev_priv, aux_domain, wakeref);
5459 }
5460
5461 static int intel_dp_get_modes(struct drm_connector *connector)
5462 {
5463         struct intel_connector *intel_connector = to_intel_connector(connector);
5464         struct edid *edid;
5465
5466         edid = intel_connector->detect_edid;
5467         if (edid) {
5468                 int ret = intel_connector_update_modes(connector, edid);
5469                 if (ret)
5470                         return ret;
5471         }
5472
5473         /* if eDP has no EDID, fall back to fixed mode */
5474         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5475             intel_connector->panel.fixed_mode) {
5476                 struct drm_display_mode *mode;
5477
5478                 mode = drm_mode_duplicate(connector->dev,
5479                                           intel_connector->panel.fixed_mode);
5480                 if (mode) {
5481                         drm_mode_probed_add(connector, mode);
5482                         return 1;
5483                 }
5484         }
5485
5486         return 0;
5487 }
5488
5489 static int
5490 intel_dp_connector_register(struct drm_connector *connector)
5491 {
5492         struct intel_dp *intel_dp = intel_attached_dp(connector);
5493         struct drm_device *dev = connector->dev;
5494         int ret;
5495
5496         ret = intel_connector_register(connector);
5497         if (ret)
5498                 return ret;
5499
5500         i915_debugfs_connector_add(connector);
5501
5502         DRM_DEBUG_KMS("registering %s bus for %s\n",
5503                       intel_dp->aux.name, connector->kdev->kobj.name);
5504
5505         intel_dp->aux.dev = connector->kdev;
5506         ret = drm_dp_aux_register(&intel_dp->aux);
5507         if (!ret)
5508                 drm_dp_cec_register_connector(&intel_dp->aux,
5509                                               connector->name, dev->dev);
5510         return ret;
5511 }
5512
5513 static void
5514 intel_dp_connector_unregister(struct drm_connector *connector)
5515 {
5516         struct intel_dp *intel_dp = intel_attached_dp(connector);
5517
5518         drm_dp_cec_unregister_connector(&intel_dp->aux);
5519         drm_dp_aux_unregister(&intel_dp->aux);
5520         intel_connector_unregister(connector);
5521 }
5522
5523 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5524 {
5525         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5526         struct intel_dp *intel_dp = &intel_dig_port->dp;
5527
5528         intel_dp_mst_encoder_cleanup(intel_dig_port);
5529         if (intel_dp_is_edp(intel_dp)) {
5530                 intel_wakeref_t wakeref;
5531
5532                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5533                 /*
5534                  * vdd might still be enabled do to the delayed vdd off.
5535                  * Make sure vdd is actually turned off here.
5536                  */
5537                 with_pps_lock(intel_dp, wakeref)
5538                         edp_panel_vdd_off_sync(intel_dp);
5539
5540                 if (intel_dp->edp_notifier.notifier_call) {
5541                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5542                         intel_dp->edp_notifier.notifier_call = NULL;
5543                 }
5544         }
5545
5546         intel_dp_aux_fini(intel_dp);
5547 }
5548
5549 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5550 {
5551         intel_dp_encoder_flush_work(encoder);
5552
5553         drm_encoder_cleanup(encoder);
5554         kfree(enc_to_dig_port(encoder));
5555 }
5556
5557 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5558 {
5559         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5560         intel_wakeref_t wakeref;
5561
5562         if (!intel_dp_is_edp(intel_dp))
5563                 return;
5564
5565         /*
5566          * vdd might still be enabled do to the delayed vdd off.
5567          * Make sure vdd is actually turned off here.
5568          */
5569         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5570         with_pps_lock(intel_dp, wakeref)
5571                 edp_panel_vdd_off_sync(intel_dp);
5572 }
5573
5574 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5575 {
5576         long ret;
5577
5578 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5579         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5580                                                msecs_to_jiffies(timeout));
5581
5582         if (!ret)
5583                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5584 }
5585
5586 static
5587 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5588                                 u8 *an)
5589 {
5590         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5591         static const struct drm_dp_aux_msg msg = {
5592                 .request = DP_AUX_NATIVE_WRITE,
5593                 .address = DP_AUX_HDCP_AKSV,
5594                 .size = DRM_HDCP_KSV_LEN,
5595         };
5596         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5597         ssize_t dpcd_ret;
5598         int ret;
5599
5600         /* Output An first, that's easy */
5601         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5602                                      an, DRM_HDCP_AN_LEN);
5603         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5604                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5605                               dpcd_ret);
5606                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5607         }
5608
5609         /*
5610          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5611          * order to get it on the wire, we need to create the AUX header as if
5612          * we were writing the data, and then tickle the hardware to output the
5613          * data once the header is sent out.
5614          */
5615         intel_dp_aux_header(txbuf, &msg);
5616
5617         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5618                                 rxbuf, sizeof(rxbuf),
5619                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5620         if (ret < 0) {
5621                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5622                 return ret;
5623         } else if (ret == 0) {
5624                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5625                 return -EIO;
5626         }
5627
5628         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5629         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5630                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5631                               reply);
5632                 return -EIO;
5633         }
5634         return 0;
5635 }
5636
5637 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5638                                    u8 *bksv)
5639 {
5640         ssize_t ret;
5641         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5642                                DRM_HDCP_KSV_LEN);
5643         if (ret != DRM_HDCP_KSV_LEN) {
5644                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5645                 return ret >= 0 ? -EIO : ret;
5646         }
5647         return 0;
5648 }
5649
5650 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5651                                       u8 *bstatus)
5652 {
5653         ssize_t ret;
5654         /*
5655          * For some reason the HDMI and DP HDCP specs call this register
5656          * definition by different names. In the HDMI spec, it's called BSTATUS,
5657          * but in DP it's called BINFO.
5658          */
5659         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5660                                bstatus, DRM_HDCP_BSTATUS_LEN);
5661         if (ret != DRM_HDCP_BSTATUS_LEN) {
5662                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5663                 return ret >= 0 ? -EIO : ret;
5664         }
5665         return 0;
5666 }
5667
5668 static
5669 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5670                              u8 *bcaps)
5671 {
5672         ssize_t ret;
5673
5674         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5675                                bcaps, 1);
5676         if (ret != 1) {
5677                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5678                 return ret >= 0 ? -EIO : ret;
5679         }
5680
5681         return 0;
5682 }
5683
5684 static
5685 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5686                                    bool *repeater_present)
5687 {
5688         ssize_t ret;
5689         u8 bcaps;
5690
5691         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5692         if (ret)
5693                 return ret;
5694
5695         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5696         return 0;
5697 }
5698
5699 static
5700 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5701                                 u8 *ri_prime)
5702 {
5703         ssize_t ret;
5704         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5705                                ri_prime, DRM_HDCP_RI_LEN);
5706         if (ret != DRM_HDCP_RI_LEN) {
5707                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5708                 return ret >= 0 ? -EIO : ret;
5709         }
5710         return 0;
5711 }
5712
5713 static
5714 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5715                                  bool *ksv_ready)
5716 {
5717         ssize_t ret;
5718         u8 bstatus;
5719         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5720                                &bstatus, 1);
5721         if (ret != 1) {
5722                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5723                 return ret >= 0 ? -EIO : ret;
5724         }
5725         *ksv_ready = bstatus & DP_BSTATUS_READY;
5726         return 0;
5727 }
5728
5729 static
5730 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5731                                 int num_downstream, u8 *ksv_fifo)
5732 {
5733         ssize_t ret;
5734         int i;
5735
5736         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5737         for (i = 0; i < num_downstream; i += 3) {
5738                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5739                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5740                                        DP_AUX_HDCP_KSV_FIFO,
5741                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5742                                        len);
5743                 if (ret != len) {
5744                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5745                                       i, ret);
5746                         return ret >= 0 ? -EIO : ret;
5747                 }
5748         }
5749         return 0;
5750 }
5751
5752 static
5753 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5754                                     int i, u32 *part)
5755 {
5756         ssize_t ret;
5757
5758         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5759                 return -EINVAL;
5760
5761         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5762                                DP_AUX_HDCP_V_PRIME(i), part,
5763                                DRM_HDCP_V_PRIME_PART_LEN);
5764         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5765                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5766                 return ret >= 0 ? -EIO : ret;
5767         }
5768         return 0;
5769 }
5770
5771 static
5772 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5773                                     bool enable)
5774 {
5775         /* Not used for single stream DisplayPort setups */
5776         return 0;
5777 }
5778
5779 static
5780 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5781 {
5782         ssize_t ret;
5783         u8 bstatus;
5784
5785         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5786                                &bstatus, 1);
5787         if (ret != 1) {
5788                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5789                 return false;
5790         }
5791
5792         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5793 }
5794
5795 static
5796 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5797                           bool *hdcp_capable)
5798 {
5799         ssize_t ret;
5800         u8 bcaps;
5801
5802         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5803         if (ret)
5804                 return ret;
5805
5806         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5807         return 0;
5808 }
5809
5810 struct hdcp2_dp_errata_stream_type {
5811         u8      msg_id;
5812         u8      stream_type;
5813 } __packed;
5814
5815 struct hdcp2_dp_msg_data {
5816         u8 msg_id;
5817         u32 offset;
5818         bool msg_detectable;
5819         u32 timeout;
5820         u32 timeout2; /* Added for non_paired situation */
5821 };
5822
5823 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
5824         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
5825         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5826           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
5827         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5828           false, 0, 0 },
5829         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5830           false, 0, 0 },
5831         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5832           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5833           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
5834         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
5835           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5836           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
5837         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
5838         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5839           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
5840         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5841           0, 0 },
5842         { HDCP_2_2_REP_SEND_RECVID_LIST,
5843           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5844           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
5845         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5846           0, 0 },
5847         { HDCP_2_2_REP_STREAM_MANAGE,
5848           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5849           0, 0 },
5850         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5851           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
5852 /* local define to shovel this through the write_2_2 interface */
5853 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5854         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5855           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5856           0, 0 },
5857 };
5858
5859 static inline
5860 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5861                                   u8 *rx_status)
5862 {
5863         ssize_t ret;
5864
5865         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5866                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5867                                HDCP_2_2_DP_RXSTATUS_LEN);
5868         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5869                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5870                 return ret >= 0 ? -EIO : ret;
5871         }
5872
5873         return 0;
5874 }
5875
5876 static
5877 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5878                                   u8 msg_id, bool *msg_ready)
5879 {
5880         u8 rx_status;
5881         int ret;
5882
5883         *msg_ready = false;
5884         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5885         if (ret < 0)
5886                 return ret;
5887
5888         switch (msg_id) {
5889         case HDCP_2_2_AKE_SEND_HPRIME:
5890                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5891                         *msg_ready = true;
5892                 break;
5893         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5894                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5895                         *msg_ready = true;
5896                 break;
5897         case HDCP_2_2_REP_SEND_RECVID_LIST:
5898                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5899                         *msg_ready = true;
5900                 break;
5901         default:
5902                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5903                 return -EINVAL;
5904         }
5905
5906         return 0;
5907 }
5908
5909 static ssize_t
5910 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5911                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
5912 {
5913         struct intel_dp *dp = &intel_dig_port->dp;
5914         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5915         u8 msg_id = hdcp2_msg_data->msg_id;
5916         int ret, timeout;
5917         bool msg_ready = false;
5918
5919         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5920                 timeout = hdcp2_msg_data->timeout2;
5921         else
5922                 timeout = hdcp2_msg_data->timeout;
5923
5924         /*
5925          * There is no way to detect the CERT, LPRIME and STREAM_READY
5926          * availability. So Wait for timeout and read the msg.
5927          */
5928         if (!hdcp2_msg_data->msg_detectable) {
5929                 mdelay(timeout);
5930                 ret = 0;
5931         } else {
5932                 /*
5933                  * As we want to check the msg availability at timeout, Ignoring
5934                  * the timeout at wait for CP_IRQ.
5935                  */
5936                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5937                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5938                                                     msg_id, &msg_ready);
5939                 if (!msg_ready)
5940                         ret = -ETIMEDOUT;
5941         }
5942
5943         if (ret)
5944                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5945                               hdcp2_msg_data->msg_id, ret, timeout);
5946
5947         return ret;
5948 }
5949
5950 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
5951 {
5952         int i;
5953
5954         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
5955                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
5956                         return &hdcp2_dp_msg_data[i];
5957
5958         return NULL;
5959 }
5960
5961 static
5962 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
5963                              void *buf, size_t size)
5964 {
5965         struct intel_dp *dp = &intel_dig_port->dp;
5966         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5967         unsigned int offset;
5968         u8 *byte = buf;
5969         ssize_t ret, bytes_to_write, len;
5970         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
5971
5972         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
5973         if (!hdcp2_msg_data)
5974                 return -EINVAL;
5975
5976         offset = hdcp2_msg_data->offset;
5977
5978         /* No msg_id in DP HDCP2.2 msgs */
5979         bytes_to_write = size - 1;
5980         byte++;
5981
5982         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
5983
5984         while (bytes_to_write) {
5985                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
5986                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
5987
5988                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
5989                                         offset, (void *)byte, len);
5990                 if (ret < 0)
5991                         return ret;
5992
5993                 bytes_to_write -= ret;
5994                 byte += ret;
5995                 offset += ret;
5996         }
5997
5998         return size;
5999 }
6000
6001 static
6002 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6003 {
6004         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6005         u32 dev_cnt;
6006         ssize_t ret;
6007
6008         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6009                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6010                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6011         if (ret != HDCP_2_2_RXINFO_LEN)
6012                 return ret >= 0 ? -EIO : ret;
6013
6014         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6015                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6016
6017         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6018                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6019
6020         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6021                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6022                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6023
6024         return ret;
6025 }
6026
6027 static
6028 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6029                             u8 msg_id, void *buf, size_t size)
6030 {
6031         unsigned int offset;
6032         u8 *byte = buf;
6033         ssize_t ret, bytes_to_recv, len;
6034         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6035
6036         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6037         if (!hdcp2_msg_data)
6038                 return -EINVAL;
6039         offset = hdcp2_msg_data->offset;
6040
6041         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6042         if (ret < 0)
6043                 return ret;
6044
6045         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6046                 ret = get_receiver_id_list_size(intel_dig_port);
6047                 if (ret < 0)
6048                         return ret;
6049
6050                 size = ret;
6051         }
6052         bytes_to_recv = size - 1;
6053
6054         /* DP adaptation msgs has no msg_id */
6055         byte++;
6056
6057         while (bytes_to_recv) {
6058                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6059                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6060
6061                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6062                                        (void *)byte, len);
6063                 if (ret < 0) {
6064                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6065                         return ret;
6066                 }
6067
6068                 bytes_to_recv -= ret;
6069                 byte += ret;
6070                 offset += ret;
6071         }
6072         byte = buf;
6073         *byte = msg_id;
6074
6075         return size;
6076 }
6077
6078 static
6079 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6080                                       bool is_repeater, u8 content_type)
6081 {
6082         struct hdcp2_dp_errata_stream_type stream_type_msg;
6083
6084         if (is_repeater)
6085                 return 0;
6086
6087         /*
6088          * Errata for DP: As Stream type is used for encryption, Receiver
6089          * should be communicated with stream type for the decryption of the
6090          * content.
6091          * Repeater will be communicated with stream type as a part of it's
6092          * auth later in time.
6093          */
6094         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6095         stream_type_msg.stream_type = content_type;
6096
6097         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6098                                         sizeof(stream_type_msg));
6099 }
6100
6101 static
6102 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6103 {
6104         u8 rx_status;
6105         int ret;
6106
6107         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6108         if (ret)
6109                 return ret;
6110
6111         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6112                 ret = HDCP_REAUTH_REQUEST;
6113         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6114                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6115         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6116                 ret = HDCP_TOPOLOGY_CHANGE;
6117
6118         return ret;
6119 }
6120
6121 static
6122 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6123                            bool *capable)
6124 {
6125         u8 rx_caps[3];
6126         int ret;
6127
6128         *capable = false;
6129         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6130                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6131                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6132         if (ret != HDCP_2_2_RXCAPS_LEN)
6133                 return ret >= 0 ? -EIO : ret;
6134
6135         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6136             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6137                 *capable = true;
6138
6139         return 0;
6140 }
6141
6142 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6143         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6144         .read_bksv = intel_dp_hdcp_read_bksv,
6145         .read_bstatus = intel_dp_hdcp_read_bstatus,
6146         .repeater_present = intel_dp_hdcp_repeater_present,
6147         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6148         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6149         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6150         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6151         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6152         .check_link = intel_dp_hdcp_check_link,
6153         .hdcp_capable = intel_dp_hdcp_capable,
6154         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6155         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6156         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6157         .check_2_2_link = intel_dp_hdcp2_check_link,
6158         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6159         .protocol = HDCP_PROTOCOL_DP,
6160 };
6161
6162 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6163 {
6164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6165         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6166
6167         lockdep_assert_held(&dev_priv->pps_mutex);
6168
6169         if (!edp_have_panel_vdd(intel_dp))
6170                 return;
6171
6172         /*
6173          * The VDD bit needs a power domain reference, so if the bit is
6174          * already enabled when we boot or resume, grab this reference and
6175          * schedule a vdd off, so we don't hold on to the reference
6176          * indefinitely.
6177          */
6178         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6179         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6180
6181         edp_panel_vdd_schedule_off(intel_dp);
6182 }
6183
6184 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6185 {
6186         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6187         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6188         enum pipe pipe;
6189
6190         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6191                                   encoder->port, &pipe))
6192                 return pipe;
6193
6194         return INVALID_PIPE;
6195 }
6196
6197 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6198 {
6199         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6200         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6201         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6202         intel_wakeref_t wakeref;
6203
6204         if (!HAS_DDI(dev_priv))
6205                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6206
6207         if (lspcon->active)
6208                 lspcon_resume(lspcon);
6209
6210         intel_dp->reset_link_params = true;
6211
6212         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6213             !intel_dp_is_edp(intel_dp))
6214                 return;
6215
6216         with_pps_lock(intel_dp, wakeref) {
6217                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6218                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6219
6220                 if (intel_dp_is_edp(intel_dp)) {
6221                         /*
6222                          * Reinit the power sequencer, in case BIOS did
6223                          * something nasty with it.
6224                          */
6225                         intel_dp_pps_init(intel_dp);
6226                         intel_edp_panel_vdd_sanitize(intel_dp);
6227                 }
6228         }
6229 }
6230
6231 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6232         .force = intel_dp_force,
6233         .fill_modes = drm_helper_probe_single_connector_modes,
6234         .atomic_get_property = intel_digital_connector_atomic_get_property,
6235         .atomic_set_property = intel_digital_connector_atomic_set_property,
6236         .late_register = intel_dp_connector_register,
6237         .early_unregister = intel_dp_connector_unregister,
6238         .destroy = intel_connector_destroy,
6239         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6240         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6241 };
6242
6243 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6244         .detect_ctx = intel_dp_detect,
6245         .get_modes = intel_dp_get_modes,
6246         .mode_valid = intel_dp_mode_valid,
6247         .atomic_check = intel_digital_connector_atomic_check,
6248 };
6249
6250 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6251         .reset = intel_dp_encoder_reset,
6252         .destroy = intel_dp_encoder_destroy,
6253 };
6254
6255 enum irqreturn
6256 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6257 {
6258         struct intel_dp *intel_dp = &intel_dig_port->dp;
6259
6260         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6261                 /*
6262                  * vdd off can generate a long pulse on eDP which
6263                  * would require vdd on to handle it, and thus we
6264                  * would end up in an endless cycle of
6265                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6266                  */
6267                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6268                               port_name(intel_dig_port->base.port));
6269                 return IRQ_HANDLED;
6270         }
6271
6272         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6273                       port_name(intel_dig_port->base.port),
6274                       long_hpd ? "long" : "short");
6275
6276         if (long_hpd) {
6277                 intel_dp->reset_link_params = true;
6278                 return IRQ_NONE;
6279         }
6280
6281         if (intel_dp->is_mst) {
6282                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6283                         /*
6284                          * If we were in MST mode, and device is not
6285                          * there, get out of MST mode
6286                          */
6287                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6288                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6289                         intel_dp->is_mst = false;
6290                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6291                                                         intel_dp->is_mst);
6292
6293                         return IRQ_NONE;
6294                 }
6295         }
6296
6297         if (!intel_dp->is_mst) {
6298                 bool handled;
6299
6300                 handled = intel_dp_short_pulse(intel_dp);
6301
6302                 if (!handled)
6303                         return IRQ_NONE;
6304         }
6305
6306         return IRQ_HANDLED;
6307 }
6308
6309 /* check the VBT to see whether the eDP is on another port */
6310 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6311 {
6312         /*
6313          * eDP not supported on g4x. so bail out early just
6314          * for a bit extra safety in case the VBT is bonkers.
6315          */
6316         if (INTEL_GEN(dev_priv) < 5)
6317                 return false;
6318
6319         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6320                 return true;
6321
6322         return intel_bios_is_port_edp(dev_priv, port);
6323 }
6324
6325 static void
6326 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6327 {
6328         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6329         enum port port = dp_to_dig_port(intel_dp)->base.port;
6330
6331         if (!IS_G4X(dev_priv) && port != PORT_A)
6332                 intel_attach_force_audio_property(connector);
6333
6334         intel_attach_broadcast_rgb_property(connector);
6335         if (HAS_GMCH(dev_priv))
6336                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6337         else if (INTEL_GEN(dev_priv) >= 5)
6338                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6339
6340         if (intel_dp_is_edp(intel_dp)) {
6341                 u32 allowed_scalers;
6342
6343                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6344                 if (!HAS_GMCH(dev_priv))
6345                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6346
6347                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6348
6349                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6350
6351         }
6352 }
6353
6354 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6355 {
6356         intel_dp->panel_power_off_time = ktime_get_boottime();
6357         intel_dp->last_power_on = jiffies;
6358         intel_dp->last_backlight_off = jiffies;
6359 }
6360
6361 static void
6362 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6363 {
6364         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6365         u32 pp_on, pp_off, pp_ctl;
6366         struct pps_registers regs;
6367
6368         intel_pps_get_registers(intel_dp, &regs);
6369
6370         pp_ctl = ironlake_get_pp_control(intel_dp);
6371
6372         /* Ensure PPS is unlocked */
6373         if (!HAS_DDI(dev_priv))
6374                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6375
6376         pp_on = I915_READ(regs.pp_on);
6377         pp_off = I915_READ(regs.pp_off);
6378
6379         /* Pull timing values out of registers */
6380         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6381         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6382         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6383         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6384
6385         if (i915_mmio_reg_valid(regs.pp_div)) {
6386                 u32 pp_div;
6387
6388                 pp_div = I915_READ(regs.pp_div);
6389
6390                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6391         } else {
6392                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6393         }
6394 }
6395
6396 static void
6397 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6398 {
6399         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6400                       state_name,
6401                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6402 }
6403
6404 static void
6405 intel_pps_verify_state(struct intel_dp *intel_dp)
6406 {
6407         struct edp_power_seq hw;
6408         struct edp_power_seq *sw = &intel_dp->pps_delays;
6409
6410         intel_pps_readout_hw_state(intel_dp, &hw);
6411
6412         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6413             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6414                 DRM_ERROR("PPS state mismatch\n");
6415                 intel_pps_dump_state("sw", sw);
6416                 intel_pps_dump_state("hw", &hw);
6417         }
6418 }
6419
6420 static void
6421 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6422 {
6423         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6424         struct edp_power_seq cur, vbt, spec,
6425                 *final = &intel_dp->pps_delays;
6426
6427         lockdep_assert_held(&dev_priv->pps_mutex);
6428
6429         /* already initialized? */
6430         if (final->t11_t12 != 0)
6431                 return;
6432
6433         intel_pps_readout_hw_state(intel_dp, &cur);
6434
6435         intel_pps_dump_state("cur", &cur);
6436
6437         vbt = dev_priv->vbt.edp.pps;
6438         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6439          * of 500ms appears to be too short. Ocassionally the panel
6440          * just fails to power back on. Increasing the delay to 800ms
6441          * seems sufficient to avoid this problem.
6442          */
6443         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6444                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6445                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6446                               vbt.t11_t12);
6447         }
6448         /* T11_T12 delay is special and actually in units of 100ms, but zero
6449          * based in the hw (so we need to add 100 ms). But the sw vbt
6450          * table multiplies it with 1000 to make it in units of 100usec,
6451          * too. */
6452         vbt.t11_t12 += 100 * 10;
6453
6454         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6455          * our hw here, which are all in 100usec. */
6456         spec.t1_t3 = 210 * 10;
6457         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6458         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6459         spec.t10 = 500 * 10;
6460         /* This one is special and actually in units of 100ms, but zero
6461          * based in the hw (so we need to add 100 ms). But the sw vbt
6462          * table multiplies it with 1000 to make it in units of 100usec,
6463          * too. */
6464         spec.t11_t12 = (510 + 100) * 10;
6465
6466         intel_pps_dump_state("vbt", &vbt);
6467
6468         /* Use the max of the register settings and vbt. If both are
6469          * unset, fall back to the spec limits. */
6470 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6471                                        spec.field : \
6472                                        max(cur.field, vbt.field))
6473         assign_final(t1_t3);
6474         assign_final(t8);
6475         assign_final(t9);
6476         assign_final(t10);
6477         assign_final(t11_t12);
6478 #undef assign_final
6479
6480 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6481         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6482         intel_dp->backlight_on_delay = get_delay(t8);
6483         intel_dp->backlight_off_delay = get_delay(t9);
6484         intel_dp->panel_power_down_delay = get_delay(t10);
6485         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6486 #undef get_delay
6487
6488         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6489                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6490                       intel_dp->panel_power_cycle_delay);
6491
6492         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6493                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6494
6495         /*
6496          * We override the HW backlight delays to 1 because we do manual waits
6497          * on them. For T8, even BSpec recommends doing it. For T9, if we
6498          * don't do this, we'll end up waiting for the backlight off delay
6499          * twice: once when we do the manual sleep, and once when we disable
6500          * the panel and wait for the PP_STATUS bit to become zero.
6501          */
6502         final->t8 = 1;
6503         final->t9 = 1;
6504
6505         /*
6506          * HW has only a 100msec granularity for t11_t12 so round it up
6507          * accordingly.
6508          */
6509         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6510 }
6511
6512 static void
6513 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6514                                               bool force_disable_vdd)
6515 {
6516         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6517         u32 pp_on, pp_off, port_sel = 0;
6518         int div = dev_priv->rawclk_freq / 1000;
6519         struct pps_registers regs;
6520         enum port port = dp_to_dig_port(intel_dp)->base.port;
6521         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6522
6523         lockdep_assert_held(&dev_priv->pps_mutex);
6524
6525         intel_pps_get_registers(intel_dp, &regs);
6526
6527         /*
6528          * On some VLV machines the BIOS can leave the VDD
6529          * enabled even on power sequencers which aren't
6530          * hooked up to any port. This would mess up the
6531          * power domain tracking the first time we pick
6532          * one of these power sequencers for use since
6533          * edp_panel_vdd_on() would notice that the VDD was
6534          * already on and therefore wouldn't grab the power
6535          * domain reference. Disable VDD first to avoid this.
6536          * This also avoids spuriously turning the VDD on as
6537          * soon as the new power sequencer gets initialized.
6538          */
6539         if (force_disable_vdd) {
6540                 u32 pp = ironlake_get_pp_control(intel_dp);
6541
6542                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6543
6544                 if (pp & EDP_FORCE_VDD)
6545                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6546
6547                 pp &= ~EDP_FORCE_VDD;
6548
6549                 I915_WRITE(regs.pp_ctrl, pp);
6550         }
6551
6552         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6553                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6554         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6555                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6556
6557         /* Haswell doesn't have any port selection bits for the panel
6558          * power sequencer any more. */
6559         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6560                 port_sel = PANEL_PORT_SELECT_VLV(port);
6561         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6562                 switch (port) {
6563                 case PORT_A:
6564                         port_sel = PANEL_PORT_SELECT_DPA;
6565                         break;
6566                 case PORT_C:
6567                         port_sel = PANEL_PORT_SELECT_DPC;
6568                         break;
6569                 case PORT_D:
6570                         port_sel = PANEL_PORT_SELECT_DPD;
6571                         break;
6572                 default:
6573                         MISSING_CASE(port);
6574                         break;
6575                 }
6576         }
6577
6578         pp_on |= port_sel;
6579
6580         I915_WRITE(regs.pp_on, pp_on);
6581         I915_WRITE(regs.pp_off, pp_off);
6582
6583         /*
6584          * Compute the divisor for the pp clock, simply match the Bspec formula.
6585          */
6586         if (i915_mmio_reg_valid(regs.pp_div)) {
6587                 I915_WRITE(regs.pp_div,
6588                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6589                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6590         } else {
6591                 u32 pp_ctl;
6592
6593                 pp_ctl = I915_READ(regs.pp_ctrl);
6594                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6595                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6596                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6597         }
6598
6599         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6600                       I915_READ(regs.pp_on),
6601                       I915_READ(regs.pp_off),
6602                       i915_mmio_reg_valid(regs.pp_div) ?
6603                       I915_READ(regs.pp_div) :
6604                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6605 }
6606
6607 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6608 {
6609         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6610
6611         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6612                 vlv_initial_power_sequencer_setup(intel_dp);
6613         } else {
6614                 intel_dp_init_panel_power_sequencer(intel_dp);
6615                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6616         }
6617 }
6618
6619 /**
6620  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6621  * @dev_priv: i915 device
6622  * @crtc_state: a pointer to the active intel_crtc_state
6623  * @refresh_rate: RR to be programmed
6624  *
6625  * This function gets called when refresh rate (RR) has to be changed from
6626  * one frequency to another. Switches can be between high and low RR
6627  * supported by the panel or to any other RR based on media playback (in
6628  * this case, RR value needs to be passed from user space).
6629  *
6630  * The caller of this function needs to take a lock on dev_priv->drrs.
6631  */
6632 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6633                                     const struct intel_crtc_state *crtc_state,
6634                                     int refresh_rate)
6635 {
6636         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6638         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6639
6640         if (refresh_rate <= 0) {
6641                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6642                 return;
6643         }
6644
6645         if (intel_dp == NULL) {
6646                 DRM_DEBUG_KMS("DRRS not supported.\n");
6647                 return;
6648         }
6649
6650         if (!intel_crtc) {
6651                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6652                 return;
6653         }
6654
6655         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6656                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6657                 return;
6658         }
6659
6660         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6661                         refresh_rate)
6662                 index = DRRS_LOW_RR;
6663
6664         if (index == dev_priv->drrs.refresh_rate_type) {
6665                 DRM_DEBUG_KMS(
6666                         "DRRS requested for previously set RR...ignoring\n");
6667                 return;
6668         }
6669
6670         if (!crtc_state->base.active) {
6671                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6672                 return;
6673         }
6674
6675         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6676                 switch (index) {
6677                 case DRRS_HIGH_RR:
6678                         intel_dp_set_m_n(crtc_state, M1_N1);
6679                         break;
6680                 case DRRS_LOW_RR:
6681                         intel_dp_set_m_n(crtc_state, M2_N2);
6682                         break;
6683                 case DRRS_MAX_RR:
6684                 default:
6685                         DRM_ERROR("Unsupported refreshrate type\n");
6686                 }
6687         } else if (INTEL_GEN(dev_priv) > 6) {
6688                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6689                 u32 val;
6690
6691                 val = I915_READ(reg);
6692                 if (index > DRRS_HIGH_RR) {
6693                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6694                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6695                         else
6696                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6697                 } else {
6698                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6699                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6700                         else
6701                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6702                 }
6703                 I915_WRITE(reg, val);
6704         }
6705
6706         dev_priv->drrs.refresh_rate_type = index;
6707
6708         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6709 }
6710
6711 /**
6712  * intel_edp_drrs_enable - init drrs struct if supported
6713  * @intel_dp: DP struct
6714  * @crtc_state: A pointer to the active crtc state.
6715  *
6716  * Initializes frontbuffer_bits and drrs.dp
6717  */
6718 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6719                            const struct intel_crtc_state *crtc_state)
6720 {
6721         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6722
6723         if (!crtc_state->has_drrs) {
6724                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6725                 return;
6726         }
6727
6728         if (dev_priv->psr.enabled) {
6729                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6730                 return;
6731         }
6732
6733         mutex_lock(&dev_priv->drrs.mutex);
6734         if (dev_priv->drrs.dp) {
6735                 DRM_DEBUG_KMS("DRRS already enabled\n");
6736                 goto unlock;
6737         }
6738
6739         dev_priv->drrs.busy_frontbuffer_bits = 0;
6740
6741         dev_priv->drrs.dp = intel_dp;
6742
6743 unlock:
6744         mutex_unlock(&dev_priv->drrs.mutex);
6745 }
6746
6747 /**
6748  * intel_edp_drrs_disable - Disable DRRS
6749  * @intel_dp: DP struct
6750  * @old_crtc_state: Pointer to old crtc_state.
6751  *
6752  */
6753 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6754                             const struct intel_crtc_state *old_crtc_state)
6755 {
6756         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6757
6758         if (!old_crtc_state->has_drrs)
6759                 return;
6760
6761         mutex_lock(&dev_priv->drrs.mutex);
6762         if (!dev_priv->drrs.dp) {
6763                 mutex_unlock(&dev_priv->drrs.mutex);
6764                 return;
6765         }
6766
6767         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6768                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6769                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6770
6771         dev_priv->drrs.dp = NULL;
6772         mutex_unlock(&dev_priv->drrs.mutex);
6773
6774         cancel_delayed_work_sync(&dev_priv->drrs.work);
6775 }
6776
6777 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6778 {
6779         struct drm_i915_private *dev_priv =
6780                 container_of(work, typeof(*dev_priv), drrs.work.work);
6781         struct intel_dp *intel_dp;
6782
6783         mutex_lock(&dev_priv->drrs.mutex);
6784
6785         intel_dp = dev_priv->drrs.dp;
6786
6787         if (!intel_dp)
6788                 goto unlock;
6789
6790         /*
6791          * The delayed work can race with an invalidate hence we need to
6792          * recheck.
6793          */
6794
6795         if (dev_priv->drrs.busy_frontbuffer_bits)
6796                 goto unlock;
6797
6798         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6799                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6800
6801                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6802                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6803         }
6804
6805 unlock:
6806         mutex_unlock(&dev_priv->drrs.mutex);
6807 }
6808
6809 /**
6810  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6811  * @dev_priv: i915 device
6812  * @frontbuffer_bits: frontbuffer plane tracking bits
6813  *
6814  * This function gets called everytime rendering on the given planes start.
6815  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6816  *
6817  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6818  */
6819 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6820                                unsigned int frontbuffer_bits)
6821 {
6822         struct drm_crtc *crtc;
6823         enum pipe pipe;
6824
6825         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6826                 return;
6827
6828         cancel_delayed_work(&dev_priv->drrs.work);
6829
6830         mutex_lock(&dev_priv->drrs.mutex);
6831         if (!dev_priv->drrs.dp) {
6832                 mutex_unlock(&dev_priv->drrs.mutex);
6833                 return;
6834         }
6835
6836         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6837         pipe = to_intel_crtc(crtc)->pipe;
6838
6839         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6840         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6841
6842         /* invalidate means busy screen hence upclock */
6843         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6844                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6845                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6846
6847         mutex_unlock(&dev_priv->drrs.mutex);
6848 }
6849
6850 /**
6851  * intel_edp_drrs_flush - Restart Idleness DRRS
6852  * @dev_priv: i915 device
6853  * @frontbuffer_bits: frontbuffer plane tracking bits
6854  *
6855  * This function gets called every time rendering on the given planes has
6856  * completed or flip on a crtc is completed. So DRRS should be upclocked
6857  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6858  * if no other planes are dirty.
6859  *
6860  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6861  */
6862 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6863                           unsigned int frontbuffer_bits)
6864 {
6865         struct drm_crtc *crtc;
6866         enum pipe pipe;
6867
6868         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6869                 return;
6870
6871         cancel_delayed_work(&dev_priv->drrs.work);
6872
6873         mutex_lock(&dev_priv->drrs.mutex);
6874         if (!dev_priv->drrs.dp) {
6875                 mutex_unlock(&dev_priv->drrs.mutex);
6876                 return;
6877         }
6878
6879         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6880         pipe = to_intel_crtc(crtc)->pipe;
6881
6882         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6883         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6884
6885         /* flush means busy screen hence upclock */
6886         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6887                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6888                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6889
6890         /*
6891          * flush also means no more activity hence schedule downclock, if all
6892          * other fbs are quiescent too
6893          */
6894         if (!dev_priv->drrs.busy_frontbuffer_bits)
6895                 schedule_delayed_work(&dev_priv->drrs.work,
6896                                 msecs_to_jiffies(1000));
6897         mutex_unlock(&dev_priv->drrs.mutex);
6898 }
6899
6900 /**
6901  * DOC: Display Refresh Rate Switching (DRRS)
6902  *
6903  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6904  * which enables swtching between low and high refresh rates,
6905  * dynamically, based on the usage scenario. This feature is applicable
6906  * for internal panels.
6907  *
6908  * Indication that the panel supports DRRS is given by the panel EDID, which
6909  * would list multiple refresh rates for one resolution.
6910  *
6911  * DRRS is of 2 types - static and seamless.
6912  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6913  * (may appear as a blink on screen) and is used in dock-undock scenario.
6914  * Seamless DRRS involves changing RR without any visual effect to the user
6915  * and can be used during normal system usage. This is done by programming
6916  * certain registers.
6917  *
6918  * Support for static/seamless DRRS may be indicated in the VBT based on
6919  * inputs from the panel spec.
6920  *
6921  * DRRS saves power by switching to low RR based on usage scenarios.
6922  *
6923  * The implementation is based on frontbuffer tracking implementation.  When
6924  * there is a disturbance on the screen triggered by user activity or a periodic
6925  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6926  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6927  * made.
6928  *
6929  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6930  * and intel_edp_drrs_flush() are called.
6931  *
6932  * DRRS can be further extended to support other internal panels and also
6933  * the scenario of video playback wherein RR is set based on the rate
6934  * requested by userspace.
6935  */
6936
6937 /**
6938  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6939  * @connector: eDP connector
6940  * @fixed_mode: preferred mode of panel
6941  *
6942  * This function is  called only once at driver load to initialize basic
6943  * DRRS stuff.
6944  *
6945  * Returns:
6946  * Downclock mode if panel supports it, else return NULL.
6947  * DRRS support is determined by the presence of downclock mode (apart
6948  * from VBT setting).
6949  */
6950 static struct drm_display_mode *
6951 intel_dp_drrs_init(struct intel_connector *connector,
6952                    struct drm_display_mode *fixed_mode)
6953 {
6954         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6955         struct drm_display_mode *downclock_mode = NULL;
6956
6957         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6958         mutex_init(&dev_priv->drrs.mutex);
6959
6960         if (INTEL_GEN(dev_priv) <= 6) {
6961                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6962                 return NULL;
6963         }
6964
6965         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6966                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6967                 return NULL;
6968         }
6969
6970         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
6971         if (!downclock_mode) {
6972                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6973                 return NULL;
6974         }
6975
6976         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6977
6978         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6979         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6980         return downclock_mode;
6981 }
6982
6983 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6984                                      struct intel_connector *intel_connector)
6985 {
6986         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6987         struct drm_device *dev = &dev_priv->drm;
6988         struct drm_connector *connector = &intel_connector->base;
6989         struct drm_display_mode *fixed_mode = NULL;
6990         struct drm_display_mode *downclock_mode = NULL;
6991         bool has_dpcd;
6992         enum pipe pipe = INVALID_PIPE;
6993         intel_wakeref_t wakeref;
6994         struct edid *edid;
6995
6996         if (!intel_dp_is_edp(intel_dp))
6997                 return true;
6998
6999         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7000
7001         /*
7002          * On IBX/CPT we may get here with LVDS already registered. Since the
7003          * driver uses the only internal power sequencer available for both
7004          * eDP and LVDS bail out early in this case to prevent interfering
7005          * with an already powered-on LVDS power sequencer.
7006          */
7007         if (intel_get_lvds_encoder(dev_priv)) {
7008                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7009                 DRM_INFO("LVDS was detected, not registering eDP\n");
7010
7011                 return false;
7012         }
7013
7014         with_pps_lock(intel_dp, wakeref) {
7015                 intel_dp_init_panel_power_timestamps(intel_dp);
7016                 intel_dp_pps_init(intel_dp);
7017                 intel_edp_panel_vdd_sanitize(intel_dp);
7018         }
7019
7020         /* Cache DPCD and EDID for edp. */
7021         has_dpcd = intel_edp_init_dpcd(intel_dp);
7022
7023         if (!has_dpcd) {
7024                 /* if this fails, presume the device is a ghost */
7025                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7026                 goto out_vdd_off;
7027         }
7028
7029         mutex_lock(&dev->mode_config.mutex);
7030         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7031         if (edid) {
7032                 if (drm_add_edid_modes(connector, edid)) {
7033                         drm_connector_update_edid_property(connector,
7034                                                                 edid);
7035                 } else {
7036                         kfree(edid);
7037                         edid = ERR_PTR(-EINVAL);
7038                 }
7039         } else {
7040                 edid = ERR_PTR(-ENOENT);
7041         }
7042         intel_connector->edid = edid;
7043
7044         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7045         if (fixed_mode)
7046                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7047
7048         /* fallback to VBT if available for eDP */
7049         if (!fixed_mode)
7050                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7051         mutex_unlock(&dev->mode_config.mutex);
7052
7053         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7054                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7055                 register_reboot_notifier(&intel_dp->edp_notifier);
7056
7057                 /*
7058                  * Figure out the current pipe for the initial backlight setup.
7059                  * If the current pipe isn't valid, try the PPS pipe, and if that
7060                  * fails just assume pipe A.
7061                  */
7062                 pipe = vlv_active_pipe(intel_dp);
7063
7064                 if (pipe != PIPE_A && pipe != PIPE_B)
7065                         pipe = intel_dp->pps_pipe;
7066
7067                 if (pipe != PIPE_A && pipe != PIPE_B)
7068                         pipe = PIPE_A;
7069
7070                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7071                               pipe_name(pipe));
7072         }
7073
7074         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7075         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7076         intel_panel_setup_backlight(connector, pipe);
7077
7078         if (fixed_mode)
7079                 drm_connector_init_panel_orientation_property(
7080                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7081
7082         return true;
7083
7084 out_vdd_off:
7085         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7086         /*
7087          * vdd might still be enabled do to the delayed vdd off.
7088          * Make sure vdd is actually turned off here.
7089          */
7090         with_pps_lock(intel_dp, wakeref)
7091                 edp_panel_vdd_off_sync(intel_dp);
7092
7093         return false;
7094 }
7095
7096 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7097 {
7098         struct intel_connector *intel_connector;
7099         struct drm_connector *connector;
7100
7101         intel_connector = container_of(work, typeof(*intel_connector),
7102                                        modeset_retry_work);
7103         connector = &intel_connector->base;
7104         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7105                       connector->name);
7106
7107         /* Grab the locks before changing connector property*/
7108         mutex_lock(&connector->dev->mode_config.mutex);
7109         /* Set connector link status to BAD and send a Uevent to notify
7110          * userspace to do a modeset.
7111          */
7112         drm_connector_set_link_status_property(connector,
7113                                                DRM_MODE_LINK_STATUS_BAD);
7114         mutex_unlock(&connector->dev->mode_config.mutex);
7115         /* Send Hotplug uevent so userspace can reprobe */
7116         drm_kms_helper_hotplug_event(connector->dev);
7117 }
7118
7119 bool
7120 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7121                         struct intel_connector *intel_connector)
7122 {
7123         struct drm_connector *connector = &intel_connector->base;
7124         struct intel_dp *intel_dp = &intel_dig_port->dp;
7125         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7126         struct drm_device *dev = intel_encoder->base.dev;
7127         struct drm_i915_private *dev_priv = to_i915(dev);
7128         enum port port = intel_encoder->port;
7129         enum phy phy = intel_port_to_phy(dev_priv, port);
7130         int type;
7131
7132         /* Initialize the work for modeset in case of link train failure */
7133         INIT_WORK(&intel_connector->modeset_retry_work,
7134                   intel_dp_modeset_retry_work_fn);
7135
7136         if (WARN(intel_dig_port->max_lanes < 1,
7137                  "Not enough lanes (%d) for DP on port %c\n",
7138                  intel_dig_port->max_lanes, port_name(port)))
7139                 return false;
7140
7141         intel_dp_set_source_rates(intel_dp);
7142
7143         intel_dp->reset_link_params = true;
7144         intel_dp->pps_pipe = INVALID_PIPE;
7145         intel_dp->active_pipe = INVALID_PIPE;
7146
7147         /* Preserve the current hw state. */
7148         intel_dp->DP = I915_READ(intel_dp->output_reg);
7149         intel_dp->attached_connector = intel_connector;
7150
7151         if (intel_dp_is_port_edp(dev_priv, port)) {
7152                 /*
7153                  * Currently we don't support eDP on TypeC ports, although in
7154                  * theory it could work on TypeC legacy ports.
7155                  */
7156                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7157                 type = DRM_MODE_CONNECTOR_eDP;
7158         } else {
7159                 type = DRM_MODE_CONNECTOR_DisplayPort;
7160         }
7161
7162         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7163                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7164
7165         /*
7166          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7167          * for DP the encoder type can be set by the caller to
7168          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7169          */
7170         if (type == DRM_MODE_CONNECTOR_eDP)
7171                 intel_encoder->type = INTEL_OUTPUT_EDP;
7172
7173         /* eDP only on port B and/or C on vlv/chv */
7174         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7175                     intel_dp_is_edp(intel_dp) &&
7176                     port != PORT_B && port != PORT_C))
7177                 return false;
7178
7179         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7180                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7181                         port_name(port));
7182
7183         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7184         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7185
7186         if (!HAS_GMCH(dev_priv))
7187                 connector->interlace_allowed = true;
7188         connector->doublescan_allowed = 0;
7189
7190         if (INTEL_GEN(dev_priv) >= 11)
7191                 connector->ycbcr_420_allowed = true;
7192
7193         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7194
7195         intel_dp_aux_init(intel_dp);
7196
7197         intel_connector_attach_encoder(intel_connector, intel_encoder);
7198
7199         if (HAS_DDI(dev_priv))
7200                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7201         else
7202                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7203
7204         /* init MST on ports that can support it */
7205         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7206             (port == PORT_B || port == PORT_C ||
7207              port == PORT_D || port == PORT_F))
7208                 intel_dp_mst_encoder_init(intel_dig_port,
7209                                           intel_connector->base.base.id);
7210
7211         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7212                 intel_dp_aux_fini(intel_dp);
7213                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7214                 goto fail;
7215         }
7216
7217         intel_dp_add_properties(intel_dp, connector);
7218
7219         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7220                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7221                 if (ret)
7222                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7223         }
7224
7225         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7226          * 0xd.  Failure to do so will result in spurious interrupts being
7227          * generated on the port when a cable is not attached.
7228          */
7229         if (IS_G45(dev_priv)) {
7230                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7231                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7232         }
7233
7234         return true;
7235
7236 fail:
7237         drm_connector_cleanup(connector);
7238
7239         return false;
7240 }
7241
7242 bool intel_dp_init(struct drm_i915_private *dev_priv,
7243                    i915_reg_t output_reg,
7244                    enum port port)
7245 {
7246         struct intel_digital_port *intel_dig_port;
7247         struct intel_encoder *intel_encoder;
7248         struct drm_encoder *encoder;
7249         struct intel_connector *intel_connector;
7250
7251         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7252         if (!intel_dig_port)
7253                 return false;
7254
7255         intel_connector = intel_connector_alloc();
7256         if (!intel_connector)
7257                 goto err_connector_alloc;
7258
7259         intel_encoder = &intel_dig_port->base;
7260         encoder = &intel_encoder->base;
7261
7262         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7263                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7264                              "DP %c", port_name(port)))
7265                 goto err_encoder_init;
7266
7267         intel_encoder->hotplug = intel_dp_hotplug;
7268         intel_encoder->compute_config = intel_dp_compute_config;
7269         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7270         intel_encoder->get_config = intel_dp_get_config;
7271         intel_encoder->update_pipe = intel_panel_update_backlight;
7272         intel_encoder->suspend = intel_dp_encoder_suspend;
7273         if (IS_CHERRYVIEW(dev_priv)) {
7274                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7275                 intel_encoder->pre_enable = chv_pre_enable_dp;
7276                 intel_encoder->enable = vlv_enable_dp;
7277                 intel_encoder->disable = vlv_disable_dp;
7278                 intel_encoder->post_disable = chv_post_disable_dp;
7279                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7280         } else if (IS_VALLEYVIEW(dev_priv)) {
7281                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7282                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7283                 intel_encoder->enable = vlv_enable_dp;
7284                 intel_encoder->disable = vlv_disable_dp;
7285                 intel_encoder->post_disable = vlv_post_disable_dp;
7286         } else {
7287                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7288                 intel_encoder->enable = g4x_enable_dp;
7289                 intel_encoder->disable = g4x_disable_dp;
7290                 intel_encoder->post_disable = g4x_post_disable_dp;
7291         }
7292
7293         intel_dig_port->dp.output_reg = output_reg;
7294         intel_dig_port->max_lanes = 4;
7295
7296         intel_encoder->type = INTEL_OUTPUT_DP;
7297         intel_encoder->power_domain = intel_port_to_power_domain(port);
7298         if (IS_CHERRYVIEW(dev_priv)) {
7299                 if (port == PORT_D)
7300                         intel_encoder->crtc_mask = 1 << 2;
7301                 else
7302                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7303         } else {
7304                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7305         }
7306         intel_encoder->cloneable = 0;
7307         intel_encoder->port = port;
7308
7309         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7310
7311         if (port != PORT_A)
7312                 intel_infoframe_init(intel_dig_port);
7313
7314         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7315         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7316                 goto err_init_connector;
7317
7318         return true;
7319
7320 err_init_connector:
7321         drm_encoder_cleanup(encoder);
7322 err_encoder_init:
7323         kfree(intel_connector);
7324 err_connector_alloc:
7325         kfree(intel_dig_port);
7326         return false;
7327 }
7328
7329 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7330 {
7331         struct intel_encoder *encoder;
7332
7333         for_each_intel_encoder(&dev_priv->drm, encoder) {
7334                 struct intel_dp *intel_dp;
7335
7336                 if (encoder->type != INTEL_OUTPUT_DDI)
7337                         continue;
7338
7339                 intel_dp = enc_to_intel_dp(&encoder->base);
7340
7341                 if (!intel_dp->can_mst)
7342                         continue;
7343
7344                 if (intel_dp->is_mst)
7345                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7346         }
7347 }
7348
7349 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7350 {
7351         struct intel_encoder *encoder;
7352
7353         for_each_intel_encoder(&dev_priv->drm, encoder) {
7354                 struct intel_dp *intel_dp;
7355                 int ret;
7356
7357                 if (encoder->type != INTEL_OUTPUT_DDI)
7358                         continue;
7359
7360                 intel_dp = enc_to_intel_dp(&encoder->base);
7361
7362                 if (!intel_dp->can_mst)
7363                         continue;
7364
7365                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7366                 if (ret) {
7367                         intel_dp->is_mst = false;
7368                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7369                                                         false);
7370                 }
7371         }
7372 }