drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  72 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  73 #define DP_DSC_MIN_SUPPORTED_BPC                8
  74 #define DP_DSC_MAX_SUPPORTED_BPC                10
  75
  76 /* DP DSC throughput values used for slice count calculations KPixels/s */
  77 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  78 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  79 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  80
  81 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  82 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  83
  84 /* Compliance test status bits  */
  85 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  86 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  88 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  89
  90 struct dp_link_dpll {
  91         int clock;
  92         struct dpll dpll;
  93 };
  94
  95 static const struct dp_link_dpll g4x_dpll[] = {
  96         { 162000,
  97                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  98         { 270000,
  99                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 100 };
 101
 102 static const struct dp_link_dpll pch_dpll[] = {
 103         { 162000,
 104                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 105         { 270000,
 106                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 107 };
 108
 109 static const struct dp_link_dpll vlv_dpll[] = {
 110         { 162000,
 111                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 112         { 270000,
 113                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 114 };
 115
 116 /*
 117  * CHV supports eDP 1.4 that have  more link rates.
 118  * Below only provides the fixed rate but exclude variable rate.
 119  */
 120 static const struct dp_link_dpll chv_dpll[] = {
 121         /*
 122          * CHV requires to program fractional division for m2.
 123          * m2 is stored in fixed point format using formula below
 124          * (m2_int << 22) | m2_fraction
 125          */
 126         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 127                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 128         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 129                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 130 };
 131
 132 /* Constants for DP DSC configurations */
 133 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 134
 135 /* With Single pipe configuration, HW is capable of supporting maximum
 136  * of 4 slices per line.
 137  */
 138 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 139
 140 /**
 141  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 142  * @intel_dp: DP struct
 143  *
 144  * If a CPU or PCH DP output is attached to an eDP panel, this function
 145  * will return true, and false otherwise.
 146  */
 147 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 150
 151         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 152 }
 153
 154 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 155 {
 156         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 157 }
 158
 159 static void intel_dp_link_down(struct intel_encoder *encoder,
 160                                const struct intel_crtc_state *old_crtc_state);
 161 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 162 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 163 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 164                                            const struct intel_crtc_state *crtc_state);
 165 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 166                                       enum pipe pipe);
 167 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 168
 169 /* update sink rates from dpcd */
 170 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 171 {
 172         static const int dp_rates[] = {
 173                 162000, 270000, 540000, 810000
 174         };
 175         int i, max_rate;
 176
 177         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 178
 179         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 180                 if (dp_rates[i] > max_rate)
 181                         break;
 182                 intel_dp->sink_rates[i] = dp_rates[i];
 183         }
 184
 185         intel_dp->num_sink_rates = i;
 186 }
 187
 188 /* Get length of rates array potentially limited by max_rate. */
 189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 190 {
 191         int i;
 192
 193         /* Limit results by potentially reduced max rate */
 194         for (i = 0; i < len; i++) {
 195                 if (rates[len - i - 1] <= max_rate)
 196                         return len - i;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /* Get length of common rates array potentially limited by max_rate. */
 203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 204                                           int max_rate)
 205 {
 206         return intel_dp_rate_limit_len(intel_dp->common_rates,
 207                                        intel_dp->num_common_rates, max_rate);
 208 }
 209
 210 /* Theoretical max between source and sink */
 211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 212 {
 213         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 214 }
 215
 216 /* Theoretical max between source and sink */
 217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 218 {
 219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 220         int source_max = intel_dig_port->max_lanes;
 221         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 222         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 223
 224         return min3(source_max, sink_max, fia_max);
 225 }
 226
 227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 228 {
 229         return intel_dp->max_link_lane_count;
 230 }
 231
 232 int
 233 intel_dp_link_required(int pixel_clock, int bpp)
 234 {
 235         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 236         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 237 }
 238
 239 int
 240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 241 {
 242         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 243          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 244          * is transmitted every LS_Clk per lane, there is no need to account for
 245          * the channel encoding that is done in the PHY layer here.
 246          */
 247
 248         return max_link_clock * max_lanes;
 249 }
 250
 251 static int
 252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 253 {
 254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 255         struct intel_encoder *encoder = &intel_dig_port->base;
 256         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257         int max_dotclk = dev_priv->max_dotclk_freq;
 258         int ds_max_dotclk;
 259
 260         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 261
 262         if (type != DP_DS_PORT_TYPE_VGA)
 263                 return max_dotclk;
 264
 265         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 266                                                     intel_dp->downstream_ports);
 267
 268         if (ds_max_dotclk != 0)
 269                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 270
 271         return max_dotclk;
 272 }
 273
 274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 275 {
 276         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 277         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 278         enum port port = dig_port->base.port;
 279
 280         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 281
 282         /* Low voltage SKUs are limited to max of 5.4G */
 283         if (voltage == VOLTAGE_INFO_0_85V)
 284                 return 540000;
 285
 286         /* For this SKU 8.1G is supported in all ports */
 287         if (IS_CNL_WITH_PORT_F(dev_priv))
 288                 return 810000;
 289
 290         /* For other SKUs, max rate on ports A and D is 5.4G */
 291         if (port == PORT_A || port == PORT_D)
 292                 return 540000;
 293
 294         return 810000;
 295 }
 296
 297 static int icl_max_source_rate(struct intel_dp *intel_dp)
 298 {
 299         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 300         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 301         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 302
 303         if (intel_phy_is_combo(dev_priv, phy) &&
 304             !IS_ELKHARTLAKE(dev_priv) &&
 305             !intel_dp_is_edp(intel_dp))
 306                 return 540000;
 307
 308         return 810000;
 309 }
 310
 311 static void
 312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 313 {
 314         /* The values must be in increasing order */
 315         static const int cnl_rates[] = {
 316                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 317         };
 318         static const int bxt_rates[] = {
 319                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 320         };
 321         static const int skl_rates[] = {
 322                 162000, 216000, 270000, 324000, 432000, 540000
 323         };
 324         static const int hsw_rates[] = {
 325                 162000, 270000, 540000
 326         };
 327         static const int g4x_rates[] = {
 328                 162000, 270000
 329         };
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 332         const struct ddi_vbt_port_info *info =
 333                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 336
 337         /* This should only be done once */
 338         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 339
 340         if (INTEL_GEN(dev_priv) >= 10) {
 341                 source_rates = cnl_rates;
 342                 size = ARRAY_SIZE(cnl_rates);
 343                 if (IS_GEN(dev_priv, 10))
 344                         max_rate = cnl_max_source_rate(intel_dp);
 345                 else
 346                         max_rate = icl_max_source_rate(intel_dp);
 347         } else if (IS_GEN9_LP(dev_priv)) {
 348                 source_rates = bxt_rates;
 349                 size = ARRAY_SIZE(bxt_rates);
 350         } else if (IS_GEN9_BC(dev_priv)) {
 351                 source_rates = skl_rates;
 352                 size = ARRAY_SIZE(skl_rates);
 353         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 354                    IS_BROADWELL(dev_priv)) {
 355                 source_rates = hsw_rates;
 356                 size = ARRAY_SIZE(hsw_rates);
 357         } else {
 358                 source_rates = g4x_rates;
 359                 size = ARRAY_SIZE(g4x_rates);
 360         }
 361
 362         if (max_rate && vbt_max_rate)
 363                 max_rate = min(max_rate, vbt_max_rate);
 364         else if (vbt_max_rate)
 365                 max_rate = vbt_max_rate;
 366
 367         if (max_rate)
 368                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 369
 370         intel_dp->source_rates = source_rates;
 371         intel_dp->num_source_rates = size;
 372 }
 373
 374 static int intersect_rates(const int *source_rates, int source_len,
 375                            const int *sink_rates, int sink_len,
 376                            int *common_rates)
 377 {
 378         int i = 0, j = 0, k = 0;
 379
 380         while (i < source_len && j < sink_len) {
 381                 if (source_rates[i] == sink_rates[j]) {
 382                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 383                                 return k;
 384                         common_rates[k] = source_rates[i];
 385                         ++k;
 386                         ++i;
 387                         ++j;
 388                 } else if (source_rates[i] < sink_rates[j]) {
 389                         ++i;
 390                 } else {
 391                         ++j;
 392                 }
 393         }
 394         return k;
 395 }
 396
 397 /* return index of rate in rates array, or -1 if not found */
 398 static int intel_dp_rate_index(const int *rates, int len, int rate)
 399 {
 400         int i;
 401
 402         for (i = 0; i < len; i++)
 403                 if (rate == rates[i])
 404                         return i;
 405
 406         return -1;
 407 }
 408
 409 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 410 {
 411         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 412
 413         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 414                                                      intel_dp->num_source_rates,
 415                                                      intel_dp->sink_rates,
 416                                                      intel_dp->num_sink_rates,
 417                                                      intel_dp->common_rates);
 418
 419         /* Paranoia, there should always be something in common. */
 420         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 421                 intel_dp->common_rates[0] = 162000;
 422                 intel_dp->num_common_rates = 1;
 423         }
 424 }
 425
 426 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 427                                        u8 lane_count)
 428 {
 429         /*
 430          * FIXME: we need to synchronize the current link parameters with
 431          * hardware readout. Currently fast link training doesn't work on
 432          * boot-up.
 433          */
 434         if (link_rate == 0 ||
 435             link_rate > intel_dp->max_link_rate)
 436                 return false;
 437
 438         if (lane_count == 0 ||
 439             lane_count > intel_dp_max_lane_count(intel_dp))
 440                 return false;
 441
 442         return true;
 443 }
 444
 445 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 446                                                      int link_rate,
 447                                                      u8 lane_count)
 448 {
 449         const struct drm_display_mode *fixed_mode =
 450                 intel_dp->attached_connector->panel.fixed_mode;
 451         int mode_rate, max_rate;
 452
 453         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 454         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 455         if (mode_rate > max_rate)
 456                 return false;
 457
 458         return true;
 459 }
 460
 461 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 462                                             int link_rate, u8 lane_count)
 463 {
 464         int index;
 465
 466         index = intel_dp_rate_index(intel_dp->common_rates,
 467                                     intel_dp->num_common_rates,
 468                                     link_rate);
 469         if (index > 0) {
 470                 if (intel_dp_is_edp(intel_dp) &&
 471                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 472                                                               intel_dp->common_rates[index - 1],
 473                                                               lane_count)) {
 474                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 475                         return 0;
 476                 }
 477                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 478                 intel_dp->max_link_lane_count = lane_count;
 479         } else if (lane_count > 1) {
 480                 if (intel_dp_is_edp(intel_dp) &&
 481                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 482                                                               intel_dp_max_common_rate(intel_dp),
 483                                                               lane_count >> 1)) {
 484                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 485                         return 0;
 486                 }
 487                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 488                 intel_dp->max_link_lane_count = lane_count >> 1;
 489         } else {
 490                 DRM_ERROR("Link Training Unsuccessful\n");
 491                 return -1;
 492         }
 493
 494         return 0;
 495 }
 496
 497 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 498 {
 499         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 500                        DP_DSC_FEC_OVERHEAD_FACTOR);
 501 }
 502
 503 static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
 504                                        u32 mode_clock, u32 mode_hdisplay)
 505 {
 506         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 507         int i;
 508
 509         /*
 510          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 511          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 512          * for SST -> TimeSlotsPerMTP is 1,
 513          * for MST -> TimeSlotsPerMTP has to be calculated
 514          */
 515         bits_per_pixel = (link_clock * lane_count * 8) /
 516                          intel_dp_mode_to_fec_clock(mode_clock);
 517         DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
 518
 519         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 520         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
 521         DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
 522
 523         /*
 524          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 525          * check, output bpp from small joiner RAM check)
 526          */
 527         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 528
 529         /* Error out if the max bpp is less than smallest allowed valid bpp */
 530         if (bits_per_pixel < valid_dsc_bpp[0]) {
 531                 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
 532                               bits_per_pixel, valid_dsc_bpp[0]);
 533                 return 0;
 534         }
 535
 536         /* Find the nearest match in the array of known BPPs from VESA */
 537         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 538                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 539                         break;
 540         }
 541         bits_per_pixel = valid_dsc_bpp[i];
 542
 543         /*
 544          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 545          * fractional part is 0
 546          */
 547         return bits_per_pixel << 4;
 548 }
 549
 550 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 551                                        int mode_clock, int mode_hdisplay)
 552 {
 553         u8 min_slice_count, i;
 554         int max_slice_width;
 555
 556         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 557                 min_slice_count = DIV_ROUND_UP(mode_clock,
 558                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 559         else
 560                 min_slice_count = DIV_ROUND_UP(mode_clock,
 561                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 562
 563         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 564         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 565                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
 566                               max_slice_width);
 567                 return 0;
 568         }
 569         /* Also take into account max slice width */
 570         min_slice_count = min_t(u8, min_slice_count,
 571                                 DIV_ROUND_UP(mode_hdisplay,
 572                                              max_slice_width));
 573
 574         /* Find the closest match to the valid slice count values */
 575         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 576                 if (valid_dsc_slicecount[i] >
 577                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 578                                                     false))
 579                         break;
 580                 if (min_slice_count  <= valid_dsc_slicecount[i])
 581                         return valid_dsc_slicecount[i];
 582         }
 583
 584         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
 585         return 0;
 586 }
 587
 588 static enum drm_mode_status
 589 intel_dp_mode_valid(struct drm_connector *connector,
 590                     struct drm_display_mode *mode)
 591 {
 592         struct intel_dp *intel_dp = intel_attached_dp(connector);
 593         struct intel_connector *intel_connector = to_intel_connector(connector);
 594         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 595         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 596         int target_clock = mode->clock;
 597         int max_rate, mode_rate, max_lanes, max_link_clock;
 598         int max_dotclk;
 599         u16 dsc_max_output_bpp = 0;
 600         u8 dsc_slice_count = 0;
 601
 602         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 603                 return MODE_NO_DBLESCAN;
 604
 605         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 606
 607         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 608                 if (mode->hdisplay > fixed_mode->hdisplay)
 609                         return MODE_PANEL;
 610
 611                 if (mode->vdisplay > fixed_mode->vdisplay)
 612                         return MODE_PANEL;
 613
 614                 target_clock = fixed_mode->clock;
 615         }
 616
 617         max_link_clock = intel_dp_max_link_rate(intel_dp);
 618         max_lanes = intel_dp_max_lane_count(intel_dp);
 619
 620         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 621         mode_rate = intel_dp_link_required(target_clock, 18);
 622
 623         /*
 624          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 625          * integer value since we support only integer values of bpp.
 626          */
 627         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 628             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 629                 if (intel_dp_is_edp(intel_dp)) {
 630                         dsc_max_output_bpp =
 631                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 632                         dsc_slice_count =
 633                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 634                                                                 true);
 635                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 636                         dsc_max_output_bpp =
 637                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 638                                                             max_lanes,
 639                                                             target_clock,
 640                                                             mode->hdisplay) >> 4;
 641                         dsc_slice_count =
 642                                 intel_dp_dsc_get_slice_count(intel_dp,
 643                                                              target_clock,
 644                                                              mode->hdisplay);
 645                 }
 646         }
 647
 648         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 649             target_clock > max_dotclk)
 650                 return MODE_CLOCK_HIGH;
 651
 652         if (mode->clock < 10000)
 653                 return MODE_CLOCK_LOW;
 654
 655         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 656                 return MODE_H_ILLEGAL;
 657
 658         return MODE_OK;
 659 }
 660
 661 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 662 {
 663         int i;
 664         u32 v = 0;
 665
 666         if (src_bytes > 4)
 667                 src_bytes = 4;
 668         for (i = 0; i < src_bytes; i++)
 669                 v |= ((u32)src[i]) << ((3 - i) * 8);
 670         return v;
 671 }
 672
 673 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 674 {
 675         int i;
 676         if (dst_bytes > 4)
 677                 dst_bytes = 4;
 678         for (i = 0; i < dst_bytes; i++)
 679                 dst[i] = src >> ((3-i) * 8);
 680 }
 681
 682 static void
 683 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 684 static void
 685 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 686                                               bool force_disable_vdd);
 687 static void
 688 intel_dp_pps_init(struct intel_dp *intel_dp);
 689
 690 static intel_wakeref_t
 691 pps_lock(struct intel_dp *intel_dp)
 692 {
 693         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 694         intel_wakeref_t wakeref;
 695
 696         /*
 697          * See intel_power_sequencer_reset() why we need
 698          * a power domain reference here.
 699          */
 700         wakeref = intel_display_power_get(dev_priv,
 701                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 702
 703         mutex_lock(&dev_priv->pps_mutex);
 704
 705         return wakeref;
 706 }
 707
 708 static intel_wakeref_t
 709 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 710 {
 711         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 712
 713         mutex_unlock(&dev_priv->pps_mutex);
 714         intel_display_power_put(dev_priv,
 715                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 716                                 wakeref);
 717         return 0;
 718 }
 719
 720 #define with_pps_lock(dp, wf) \
 721         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 722
 723 static void
 724 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 725 {
 726         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 727         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 728         enum pipe pipe = intel_dp->pps_pipe;
 729         bool pll_enabled, release_cl_override = false;
 730         enum dpio_phy phy = DPIO_PHY(pipe);
 731         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 732         u32 DP;
 733
 734         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 735                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 736                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 737                 return;
 738
 739         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 740                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 741
 742         /* Preserve the BIOS-computed detected bit. This is
 743          * supposed to be read-only.
 744          */
 745         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 746         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 747         DP |= DP_PORT_WIDTH(1);
 748         DP |= DP_LINK_TRAIN_PAT_1;
 749
 750         if (IS_CHERRYVIEW(dev_priv))
 751                 DP |= DP_PIPE_SEL_CHV(pipe);
 752         else
 753                 DP |= DP_PIPE_SEL(pipe);
 754
 755         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 756
 757         /*
 758          * The DPLL for the pipe must be enabled for this to work.
 759          * So enable temporarily it if it's not already enabled.
 760          */
 761         if (!pll_enabled) {
 762                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 763                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 764
 765                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 766                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 767                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 768                                   pipe_name(pipe));
 769                         return;
 770                 }
 771         }
 772
 773         /*
 774          * Similar magic as in intel_dp_enable_port().
 775          * We _must_ do this port enable + disable trick
 776          * to make this power sequencer lock onto the port.
 777          * Otherwise even VDD force bit won't work.
 778          */
 779         I915_WRITE(intel_dp->output_reg, DP);
 780         POSTING_READ(intel_dp->output_reg);
 781
 782         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 783         POSTING_READ(intel_dp->output_reg);
 784
 785         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 786         POSTING_READ(intel_dp->output_reg);
 787
 788         if (!pll_enabled) {
 789                 vlv_force_pll_off(dev_priv, pipe);
 790
 791                 if (release_cl_override)
 792                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 793         }
 794 }
 795
 796 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 797 {
 798         struct intel_encoder *encoder;
 799         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 800
 801         /*
 802          * We don't have power sequencer currently.
 803          * Pick one that's not used by other ports.
 804          */
 805         for_each_intel_dp(&dev_priv->drm, encoder) {
 806                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 807
 808                 if (encoder->type == INTEL_OUTPUT_EDP) {
 809                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 810                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 811
 812                         if (intel_dp->pps_pipe != INVALID_PIPE)
 813                                 pipes &= ~(1 << intel_dp->pps_pipe);
 814                 } else {
 815                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 816
 817                         if (intel_dp->active_pipe != INVALID_PIPE)
 818                                 pipes &= ~(1 << intel_dp->active_pipe);
 819                 }
 820         }
 821
 822         if (pipes == 0)
 823                 return INVALID_PIPE;
 824
 825         return ffs(pipes) - 1;
 826 }
 827
 828 static enum pipe
 829 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 830 {
 831         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 832         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 833         enum pipe pipe;
 834
 835         lockdep_assert_held(&dev_priv->pps_mutex);
 836
 837         /* We should never land here with regular DP ports */
 838         WARN_ON(!intel_dp_is_edp(intel_dp));
 839
 840         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 841                 intel_dp->active_pipe != intel_dp->pps_pipe);
 842
 843         if (intel_dp->pps_pipe != INVALID_PIPE)
 844                 return intel_dp->pps_pipe;
 845
 846         pipe = vlv_find_free_pps(dev_priv);
 847
 848         /*
 849          * Didn't find one. This should not happen since there
 850          * are two power sequencers and up to two eDP ports.
 851          */
 852         if (WARN_ON(pipe == INVALID_PIPE))
 853                 pipe = PIPE_A;
 854
 855         vlv_steal_power_sequencer(dev_priv, pipe);
 856         intel_dp->pps_pipe = pipe;
 857
 858         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 859                       pipe_name(intel_dp->pps_pipe),
 860                       port_name(intel_dig_port->base.port));
 861
 862         /* init power sequencer on this pipe and port */
 863         intel_dp_init_panel_power_sequencer(intel_dp);
 864         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 865
 866         /*
 867          * Even vdd force doesn't work until we've made
 868          * the power sequencer lock in on the port.
 869          */
 870         vlv_power_sequencer_kick(intel_dp);
 871
 872         return intel_dp->pps_pipe;
 873 }
 874
 875 static int
 876 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 877 {
 878         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 879         int backlight_controller = dev_priv->vbt.backlight.controller;
 880
 881         lockdep_assert_held(&dev_priv->pps_mutex);
 882
 883         /* We should never land here with regular DP ports */
 884         WARN_ON(!intel_dp_is_edp(intel_dp));
 885
 886         if (!intel_dp->pps_reset)
 887                 return backlight_controller;
 888
 889         intel_dp->pps_reset = false;
 890
 891         /*
 892          * Only the HW needs to be reprogrammed, the SW state is fixed and
 893          * has been setup during connector init.
 894          */
 895         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 896
 897         return backlight_controller;
 898 }
 899
 900 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 901                                enum pipe pipe);
 902
 903 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 904                                enum pipe pipe)
 905 {
 906         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 907 }
 908
 909 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 910                                 enum pipe pipe)
 911 {
 912         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 913 }
 914
 915 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 916                          enum pipe pipe)
 917 {
 918         return true;
 919 }
 920
 921 static enum pipe
 922 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 923                      enum port port,
 924                      vlv_pipe_check pipe_check)
 925 {
 926         enum pipe pipe;
 927
 928         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 929                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 930                         PANEL_PORT_SELECT_MASK;
 931
 932                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 933                         continue;
 934
 935                 if (!pipe_check(dev_priv, pipe))
 936                         continue;
 937
 938                 return pipe;
 939         }
 940
 941         return INVALID_PIPE;
 942 }
 943
 944 static void
 945 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 946 {
 947         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 948         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 949         enum port port = intel_dig_port->base.port;
 950
 951         lockdep_assert_held(&dev_priv->pps_mutex);
 952
 953         /* try to find a pipe with this port selected */
 954         /* first pick one where the panel is on */
 955         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 956                                                   vlv_pipe_has_pp_on);
 957         /* didn't find one? pick one where vdd is on */
 958         if (intel_dp->pps_pipe == INVALID_PIPE)
 959                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 960                                                           vlv_pipe_has_vdd_on);
 961         /* didn't find one? pick one with just the correct port */
 962         if (intel_dp->pps_pipe == INVALID_PIPE)
 963                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 964                                                           vlv_pipe_any);
 965
 966         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 967         if (intel_dp->pps_pipe == INVALID_PIPE) {
 968                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 969                               port_name(port));
 970                 return;
 971         }
 972
 973         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 974                       port_name(port), pipe_name(intel_dp->pps_pipe));
 975
 976         intel_dp_init_panel_power_sequencer(intel_dp);
 977         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 978 }
 979
 980 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 981 {
 982         struct intel_encoder *encoder;
 983
 984         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 985                     !IS_GEN9_LP(dev_priv)))
 986                 return;
 987
 988         /*
 989          * We can't grab pps_mutex here due to deadlock with power_domain
 990          * mutex when power_domain functions are called while holding pps_mutex.
 991          * That also means that in order to use pps_pipe the code needs to
 992          * hold both a power domain reference and pps_mutex, and the power domain
 993          * reference get/put must be done while _not_ holding pps_mutex.
 994          * pps_{lock,unlock}() do these steps in the correct order, so one
 995          * should use them always.
 996          */
 997
 998         for_each_intel_dp(&dev_priv->drm, encoder) {
 999                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1000
1001                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1002
1003                 if (encoder->type != INTEL_OUTPUT_EDP)
1004                         continue;
1005
1006                 if (IS_GEN9_LP(dev_priv))
1007                         intel_dp->pps_reset = true;
1008                 else
1009                         intel_dp->pps_pipe = INVALID_PIPE;
1010         }
1011 }
1012
1013 struct pps_registers {
1014         i915_reg_t pp_ctrl;
1015         i915_reg_t pp_stat;
1016         i915_reg_t pp_on;
1017         i915_reg_t pp_off;
1018         i915_reg_t pp_div;
1019 };
1020
1021 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1022                                     struct pps_registers *regs)
1023 {
1024         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1025         int pps_idx = 0;
1026
1027         memset(regs, 0, sizeof(*regs));
1028
1029         if (IS_GEN9_LP(dev_priv))
1030                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1031         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1032                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1033
1034         regs->pp_ctrl = PP_CONTROL(pps_idx);
1035         regs->pp_stat = PP_STATUS(pps_idx);
1036         regs->pp_on = PP_ON_DELAYS(pps_idx);
1037         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1038
1039         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1040         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1041                 regs->pp_div = INVALID_MMIO_REG;
1042         else
1043                 regs->pp_div = PP_DIVISOR(pps_idx);
1044 }
1045
1046 static i915_reg_t
1047 _pp_ctrl_reg(struct intel_dp *intel_dp)
1048 {
1049         struct pps_registers regs;
1050
1051         intel_pps_get_registers(intel_dp, &regs);
1052
1053         return regs.pp_ctrl;
1054 }
1055
1056 static i915_reg_t
1057 _pp_stat_reg(struct intel_dp *intel_dp)
1058 {
1059         struct pps_registers regs;
1060
1061         intel_pps_get_registers(intel_dp, &regs);
1062
1063         return regs.pp_stat;
1064 }
1065
1066 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1067    This function only applicable when panel PM state is not to be tracked */
1068 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1069                               void *unused)
1070 {
1071         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1072                                                  edp_notifier);
1073         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1074         intel_wakeref_t wakeref;
1075
1076         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1077                 return 0;
1078
1079         with_pps_lock(intel_dp, wakeref) {
1080                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1081                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1082                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1083                         u32 pp_div;
1084
1085                         pp_ctrl_reg = PP_CONTROL(pipe);
1086                         pp_div_reg  = PP_DIVISOR(pipe);
1087                         pp_div = I915_READ(pp_div_reg);
1088                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1089
1090                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1091                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1092                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1093                         msleep(intel_dp->panel_power_cycle_delay);
1094                 }
1095         }
1096
1097         return 0;
1098 }
1099
1100 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1101 {
1102         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1103
1104         lockdep_assert_held(&dev_priv->pps_mutex);
1105
1106         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1107             intel_dp->pps_pipe == INVALID_PIPE)
1108                 return false;
1109
1110         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1111 }
1112
1113 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1114 {
1115         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1116
1117         lockdep_assert_held(&dev_priv->pps_mutex);
1118
1119         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1120             intel_dp->pps_pipe == INVALID_PIPE)
1121                 return false;
1122
1123         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1124 }
1125
1126 static void
1127 intel_dp_check_edp(struct intel_dp *intel_dp)
1128 {
1129         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1130
1131         if (!intel_dp_is_edp(intel_dp))
1132                 return;
1133
1134         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1135                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1136                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1137                               I915_READ(_pp_stat_reg(intel_dp)),
1138                               I915_READ(_pp_ctrl_reg(intel_dp)));
1139         }
1140 }
1141
1142 static u32
1143 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1144 {
1145         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1146         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1147         u32 status;
1148         bool done;
1149
1150 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1151         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1152                                   msecs_to_jiffies_timeout(10));
1153
1154         /* just trace the final value */
1155         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1156
1157         if (!done)
1158                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1159 #undef C
1160
1161         return status;
1162 }
1163
1164 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1165 {
1166         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1167
1168         if (index)
1169                 return 0;
1170
1171         /*
1172          * The clock divider is based off the hrawclk, and would like to run at
1173          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1174          */
1175         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1176 }
1177
1178 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1179 {
1180         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1181         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1182
1183         if (index)
1184                 return 0;
1185
1186         /*
1187          * The clock divider is based off the cdclk or PCH rawclk, and would
1188          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1189          * divide by 2000 and use that
1190          */
1191         if (dig_port->aux_ch == AUX_CH_A)
1192                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1193         else
1194                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1195 }
1196
1197 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1198 {
1199         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1200         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1201
1202         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1203                 /* Workaround for non-ULT HSW */
1204                 switch (index) {
1205                 case 0: return 63;
1206                 case 1: return 72;
1207                 default: return 0;
1208                 }
1209         }
1210
1211         return ilk_get_aux_clock_divider(intel_dp, index);
1212 }
1213
1214 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1215 {
1216         /*
1217          * SKL doesn't need us to program the AUX clock divider (Hardware will
1218          * derive the clock from CDCLK automatically). We still implement the
1219          * get_aux_clock_divider vfunc to plug-in into the existing code.
1220          */
1221         return index ? 0 : 1;
1222 }
1223
1224 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1225                                 int send_bytes,
1226                                 u32 aux_clock_divider)
1227 {
1228         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1229         struct drm_i915_private *dev_priv =
1230                         to_i915(intel_dig_port->base.base.dev);
1231         u32 precharge, timeout;
1232
1233         if (IS_GEN(dev_priv, 6))
1234                 precharge = 3;
1235         else
1236                 precharge = 5;
1237
1238         if (IS_BROADWELL(dev_priv))
1239                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1240         else
1241                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1242
1243         return DP_AUX_CH_CTL_SEND_BUSY |
1244                DP_AUX_CH_CTL_DONE |
1245                DP_AUX_CH_CTL_INTERRUPT |
1246                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1247                timeout |
1248                DP_AUX_CH_CTL_RECEIVE_ERROR |
1249                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1250                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1251                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1252 }
1253
1254 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1255                                 int send_bytes,
1256                                 u32 unused)
1257 {
1258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259         u32 ret;
1260
1261         ret = DP_AUX_CH_CTL_SEND_BUSY |
1262               DP_AUX_CH_CTL_DONE |
1263               DP_AUX_CH_CTL_INTERRUPT |
1264               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1265               DP_AUX_CH_CTL_TIME_OUT_MAX |
1266               DP_AUX_CH_CTL_RECEIVE_ERROR |
1267               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1268               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1269               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1270
1271         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1272                 ret |= DP_AUX_CH_CTL_TBT_IO;
1273
1274         return ret;
1275 }
1276
1277 static int
1278 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1279                   const u8 *send, int send_bytes,
1280                   u8 *recv, int recv_size,
1281                   u32 aux_send_ctl_flags)
1282 {
1283         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1284         struct drm_i915_private *i915 =
1285                         to_i915(intel_dig_port->base.base.dev);
1286         struct intel_uncore *uncore = &i915->uncore;
1287         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1288         bool is_tc_port = intel_phy_is_tc(i915, phy);
1289         i915_reg_t ch_ctl, ch_data[5];
1290         u32 aux_clock_divider;
1291         enum intel_display_power_domain aux_domain =
1292                 intel_aux_power_domain(intel_dig_port);
1293         intel_wakeref_t aux_wakeref;
1294         intel_wakeref_t pps_wakeref;
1295         int i, ret, recv_bytes;
1296         int try, clock = 0;
1297         u32 status;
1298         bool vdd;
1299
1300         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1301         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1302                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1303
1304         if (is_tc_port)
1305                 intel_tc_port_lock(intel_dig_port);
1306
1307         aux_wakeref = intel_display_power_get(i915, aux_domain);
1308         pps_wakeref = pps_lock(intel_dp);
1309
1310         /*
1311          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1312          * In such cases we want to leave VDD enabled and it's up to upper layers
1313          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1314          * ourselves.
1315          */
1316         vdd = edp_panel_vdd_on(intel_dp);
1317
1318         /* dp aux is extremely sensitive to irq latency, hence request the
1319          * lowest possible wakeup latency and so prevent the cpu from going into
1320          * deep sleep states.
1321          */
1322         pm_qos_update_request(&i915->pm_qos, 0);
1323
1324         intel_dp_check_edp(intel_dp);
1325
1326         /* Try to wait for any previous AUX channel activity */
1327         for (try = 0; try < 3; try++) {
1328                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1329                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1330                         break;
1331                 msleep(1);
1332         }
1333         /* just trace the final value */
1334         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1335
1336         if (try == 3) {
1337                 static u32 last_status = -1;
1338                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1339
1340                 if (status != last_status) {
1341                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1342                              status);
1343                         last_status = status;
1344                 }
1345
1346                 ret = -EBUSY;
1347                 goto out;
1348         }
1349
1350         /* Only 5 data registers! */
1351         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1352                 ret = -E2BIG;
1353                 goto out;
1354         }
1355
1356         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1357                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1358                                                           send_bytes,
1359                                                           aux_clock_divider);
1360
1361                 send_ctl |= aux_send_ctl_flags;
1362
1363                 /* Must try at least 3 times according to DP spec */
1364                 for (try = 0; try < 5; try++) {
1365                         /* Load the send data into the aux channel data registers */
1366                         for (i = 0; i < send_bytes; i += 4)
1367                                 intel_uncore_write(uncore,
1368                                                    ch_data[i >> 2],
1369                                                    intel_dp_pack_aux(send + i,
1370                                                                      send_bytes - i));
1371
1372                         /* Send the command and wait for it to complete */
1373                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1374
1375                         status = intel_dp_aux_wait_done(intel_dp);
1376
1377                         /* Clear done status and any errors */
1378                         intel_uncore_write(uncore,
1379                                            ch_ctl,
1380                                            status |
1381                                            DP_AUX_CH_CTL_DONE |
1382                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1383                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1384
1385                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1386                          *   400us delay required for errors and timeouts
1387                          *   Timeout errors from the HW already meet this
1388                          *   requirement so skip to next iteration
1389                          */
1390                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1391                                 continue;
1392
1393                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1394                                 usleep_range(400, 500);
1395                                 continue;
1396                         }
1397                         if (status & DP_AUX_CH_CTL_DONE)
1398                                 goto done;
1399                 }
1400         }
1401
1402         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1403                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1404                 ret = -EBUSY;
1405                 goto out;
1406         }
1407
1408 done:
1409         /* Check for timeout or receive error.
1410          * Timeouts occur when the sink is not connected
1411          */
1412         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1413                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1414                 ret = -EIO;
1415                 goto out;
1416         }
1417
1418         /* Timeouts occur when the device isn't connected, so they're
1419          * "normal" -- don't fill the kernel log with these */
1420         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1421                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1422                 ret = -ETIMEDOUT;
1423                 goto out;
1424         }
1425
1426         /* Unload any bytes sent back from the other side */
1427         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1428                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1429
1430         /*
1431          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1432          * We have no idea of what happened so we return -EBUSY so
1433          * drm layer takes care for the necessary retries.
1434          */
1435         if (recv_bytes == 0 || recv_bytes > 20) {
1436                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1437                               recv_bytes);
1438                 ret = -EBUSY;
1439                 goto out;
1440         }
1441
1442         if (recv_bytes > recv_size)
1443                 recv_bytes = recv_size;
1444
1445         for (i = 0; i < recv_bytes; i += 4)
1446                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1447                                     recv + i, recv_bytes - i);
1448
1449         ret = recv_bytes;
1450 out:
1451         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1452
1453         if (vdd)
1454                 edp_panel_vdd_off(intel_dp, false);
1455
1456         pps_unlock(intel_dp, pps_wakeref);
1457         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1458
1459         if (is_tc_port)
1460                 intel_tc_port_unlock(intel_dig_port);
1461
1462         return ret;
1463 }
1464
1465 #define BARE_ADDRESS_SIZE       3
1466 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1467
1468 static void
1469 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1470                     const struct drm_dp_aux_msg *msg)
1471 {
1472         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1473         txbuf[1] = (msg->address >> 8) & 0xff;
1474         txbuf[2] = msg->address & 0xff;
1475         txbuf[3] = msg->size - 1;
1476 }
1477
1478 static ssize_t
1479 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1480 {
1481         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1482         u8 txbuf[20], rxbuf[20];
1483         size_t txsize, rxsize;
1484         int ret;
1485
1486         intel_dp_aux_header(txbuf, msg);
1487
1488         switch (msg->request & ~DP_AUX_I2C_MOT) {
1489         case DP_AUX_NATIVE_WRITE:
1490         case DP_AUX_I2C_WRITE:
1491         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1492                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1493                 rxsize = 2; /* 0 or 1 data bytes */
1494
1495                 if (WARN_ON(txsize > 20))
1496                         return -E2BIG;
1497
1498                 WARN_ON(!msg->buffer != !msg->size);
1499
1500                 if (msg->buffer)
1501                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1502
1503                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1504                                         rxbuf, rxsize, 0);
1505                 if (ret > 0) {
1506                         msg->reply = rxbuf[0] >> 4;
1507
1508                         if (ret > 1) {
1509                                 /* Number of bytes written in a short write. */
1510                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1511                         } else {
1512                                 /* Return payload size. */
1513                                 ret = msg->size;
1514                         }
1515                 }
1516                 break;
1517
1518         case DP_AUX_NATIVE_READ:
1519         case DP_AUX_I2C_READ:
1520                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1521                 rxsize = msg->size + 1;
1522
1523                 if (WARN_ON(rxsize > 20))
1524                         return -E2BIG;
1525
1526                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1527                                         rxbuf, rxsize, 0);
1528                 if (ret > 0) {
1529                         msg->reply = rxbuf[0] >> 4;
1530                         /*
1531                          * Assume happy day, and copy the data. The caller is
1532                          * expected to check msg->reply before touching it.
1533                          *
1534                          * Return payload size.
1535                          */
1536                         ret--;
1537                         memcpy(msg->buffer, rxbuf + 1, ret);
1538                 }
1539                 break;
1540
1541         default:
1542                 ret = -EINVAL;
1543                 break;
1544         }
1545
1546         return ret;
1547 }
1548
1549
1550 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1551 {
1552         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1553         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1554         enum aux_ch aux_ch = dig_port->aux_ch;
1555
1556         switch (aux_ch) {
1557         case AUX_CH_B:
1558         case AUX_CH_C:
1559         case AUX_CH_D:
1560                 return DP_AUX_CH_CTL(aux_ch);
1561         default:
1562                 MISSING_CASE(aux_ch);
1563                 return DP_AUX_CH_CTL(AUX_CH_B);
1564         }
1565 }
1566
1567 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1568 {
1569         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1570         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1571         enum aux_ch aux_ch = dig_port->aux_ch;
1572
1573         switch (aux_ch) {
1574         case AUX_CH_B:
1575         case AUX_CH_C:
1576         case AUX_CH_D:
1577                 return DP_AUX_CH_DATA(aux_ch, index);
1578         default:
1579                 MISSING_CASE(aux_ch);
1580                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1581         }
1582 }
1583
1584 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1585 {
1586         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1587         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1588         enum aux_ch aux_ch = dig_port->aux_ch;
1589
1590         switch (aux_ch) {
1591         case AUX_CH_A:
1592                 return DP_AUX_CH_CTL(aux_ch);
1593         case AUX_CH_B:
1594         case AUX_CH_C:
1595         case AUX_CH_D:
1596                 return PCH_DP_AUX_CH_CTL(aux_ch);
1597         default:
1598                 MISSING_CASE(aux_ch);
1599                 return DP_AUX_CH_CTL(AUX_CH_A);
1600         }
1601 }
1602
1603 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1604 {
1605         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1606         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1607         enum aux_ch aux_ch = dig_port->aux_ch;
1608
1609         switch (aux_ch) {
1610         case AUX_CH_A:
1611                 return DP_AUX_CH_DATA(aux_ch, index);
1612         case AUX_CH_B:
1613         case AUX_CH_C:
1614         case AUX_CH_D:
1615                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1616         default:
1617                 MISSING_CASE(aux_ch);
1618                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1619         }
1620 }
1621
1622 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1623 {
1624         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1625         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1626         enum aux_ch aux_ch = dig_port->aux_ch;
1627
1628         switch (aux_ch) {
1629         case AUX_CH_A:
1630         case AUX_CH_B:
1631         case AUX_CH_C:
1632         case AUX_CH_D:
1633         case AUX_CH_E:
1634         case AUX_CH_F:
1635                 return DP_AUX_CH_CTL(aux_ch);
1636         default:
1637                 MISSING_CASE(aux_ch);
1638                 return DP_AUX_CH_CTL(AUX_CH_A);
1639         }
1640 }
1641
1642 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1643 {
1644         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1645         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1646         enum aux_ch aux_ch = dig_port->aux_ch;
1647
1648         switch (aux_ch) {
1649         case AUX_CH_A:
1650         case AUX_CH_B:
1651         case AUX_CH_C:
1652         case AUX_CH_D:
1653         case AUX_CH_E:
1654         case AUX_CH_F:
1655                 return DP_AUX_CH_DATA(aux_ch, index);
1656         default:
1657                 MISSING_CASE(aux_ch);
1658                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1659         }
1660 }
1661
1662 static void
1663 intel_dp_aux_fini(struct intel_dp *intel_dp)
1664 {
1665         kfree(intel_dp->aux.name);
1666 }
1667
1668 static void
1669 intel_dp_aux_init(struct intel_dp *intel_dp)
1670 {
1671         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1672         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1673         struct intel_encoder *encoder = &dig_port->base;
1674
1675         if (INTEL_GEN(dev_priv) >= 9) {
1676                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1677                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1678         } else if (HAS_PCH_SPLIT(dev_priv)) {
1679                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1680                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1681         } else {
1682                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1683                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1684         }
1685
1686         if (INTEL_GEN(dev_priv) >= 9)
1687                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1688         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1689                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1690         else if (HAS_PCH_SPLIT(dev_priv))
1691                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1692         else
1693                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1694
1695         if (INTEL_GEN(dev_priv) >= 9)
1696                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1697         else
1698                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1699
1700         drm_dp_aux_init(&intel_dp->aux);
1701
1702         /* Failure to allocate our preferred name is not critical */
1703         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1704                                        port_name(encoder->port));
1705         intel_dp->aux.transfer = intel_dp_aux_transfer;
1706 }
1707
1708 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1709 {
1710         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1711
1712         return max_rate >= 540000;
1713 }
1714
1715 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1716 {
1717         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1718
1719         return max_rate >= 810000;
1720 }
1721
1722 static void
1723 intel_dp_set_clock(struct intel_encoder *encoder,
1724                    struct intel_crtc_state *pipe_config)
1725 {
1726         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1727         const struct dp_link_dpll *divisor = NULL;
1728         int i, count = 0;
1729
1730         if (IS_G4X(dev_priv)) {
1731                 divisor = g4x_dpll;
1732                 count = ARRAY_SIZE(g4x_dpll);
1733         } else if (HAS_PCH_SPLIT(dev_priv)) {
1734                 divisor = pch_dpll;
1735                 count = ARRAY_SIZE(pch_dpll);
1736         } else if (IS_CHERRYVIEW(dev_priv)) {
1737                 divisor = chv_dpll;
1738                 count = ARRAY_SIZE(chv_dpll);
1739         } else if (IS_VALLEYVIEW(dev_priv)) {
1740                 divisor = vlv_dpll;
1741                 count = ARRAY_SIZE(vlv_dpll);
1742         }
1743
1744         if (divisor && count) {
1745                 for (i = 0; i < count; i++) {
1746                         if (pipe_config->port_clock == divisor[i].clock) {
1747                                 pipe_config->dpll = divisor[i].dpll;
1748                                 pipe_config->clock_set = true;
1749                                 break;
1750                         }
1751                 }
1752         }
1753 }
1754
1755 static void snprintf_int_array(char *str, size_t len,
1756                                const int *array, int nelem)
1757 {
1758         int i;
1759
1760         str[0] = '\0';
1761
1762         for (i = 0; i < nelem; i++) {
1763                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1764                 if (r >= len)
1765                         return;
1766                 str += r;
1767                 len -= r;
1768         }
1769 }
1770
1771 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1772 {
1773         char str[128]; /* FIXME: too big for stack? */
1774
1775         if ((drm_debug & DRM_UT_KMS) == 0)
1776                 return;
1777
1778         snprintf_int_array(str, sizeof(str),
1779                            intel_dp->source_rates, intel_dp->num_source_rates);
1780         DRM_DEBUG_KMS("source rates: %s\n", str);
1781
1782         snprintf_int_array(str, sizeof(str),
1783                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1784         DRM_DEBUG_KMS("sink rates: %s\n", str);
1785
1786         snprintf_int_array(str, sizeof(str),
1787                            intel_dp->common_rates, intel_dp->num_common_rates);
1788         DRM_DEBUG_KMS("common rates: %s\n", str);
1789 }
1790
1791 int
1792 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1793 {
1794         int len;
1795
1796         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1797         if (WARN_ON(len <= 0))
1798                 return 162000;
1799
1800         return intel_dp->common_rates[len - 1];
1801 }
1802
1803 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1804 {
1805         int i = intel_dp_rate_index(intel_dp->sink_rates,
1806                                     intel_dp->num_sink_rates, rate);
1807
1808         if (WARN_ON(i < 0))
1809                 i = 0;
1810
1811         return i;
1812 }
1813
1814 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1815                            u8 *link_bw, u8 *rate_select)
1816 {
1817         /* eDP 1.4 rate select method. */
1818         if (intel_dp->use_rate_select) {
1819                 *link_bw = 0;
1820                 *rate_select =
1821                         intel_dp_rate_select(intel_dp, port_clock);
1822         } else {
1823                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1824                 *rate_select = 0;
1825         }
1826 }
1827
1828 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1829                                          const struct intel_crtc_state *pipe_config)
1830 {
1831         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1832
1833         return INTEL_GEN(dev_priv) >= 11 &&
1834                 pipe_config->cpu_transcoder != TRANSCODER_A;
1835 }
1836
1837 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1838                                   const struct intel_crtc_state *pipe_config)
1839 {
1840         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1841                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1842 }
1843
1844 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1845                                          const struct intel_crtc_state *pipe_config)
1846 {
1847         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1848
1849         return INTEL_GEN(dev_priv) >= 10 &&
1850                 pipe_config->cpu_transcoder != TRANSCODER_A;
1851 }
1852
1853 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1854                                   const struct intel_crtc_state *pipe_config)
1855 {
1856         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1857                 return false;
1858
1859         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1860                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1861 }
1862
1863 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1864                                 struct intel_crtc_state *pipe_config)
1865 {
1866         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1867         struct intel_connector *intel_connector = intel_dp->attached_connector;
1868         int bpp, bpc;
1869
1870         bpp = pipe_config->pipe_bpp;
1871         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1872
1873         if (bpc > 0)
1874                 bpp = min(bpp, 3*bpc);
1875
1876         if (intel_dp_is_edp(intel_dp)) {
1877                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1878                 if (intel_connector->base.display_info.bpc == 0 &&
1879                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1880                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1881                                       dev_priv->vbt.edp.bpp);
1882                         bpp = dev_priv->vbt.edp.bpp;
1883                 }
1884         }
1885
1886         return bpp;
1887 }
1888
1889 /* Adjust link config limits based on compliance test requests. */
1890 void
1891 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1892                                   struct intel_crtc_state *pipe_config,
1893                                   struct link_config_limits *limits)
1894 {
1895         /* For DP Compliance we override the computed bpp for the pipe */
1896         if (intel_dp->compliance.test_data.bpc != 0) {
1897                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1898
1899                 limits->min_bpp = limits->max_bpp = bpp;
1900                 pipe_config->dither_force_disable = bpp == 6 * 3;
1901
1902                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1903         }
1904
1905         /* Use values requested by Compliance Test Request */
1906         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1907                 int index;
1908
1909                 /* Validate the compliance test data since max values
1910                  * might have changed due to link train fallback.
1911                  */
1912                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1913                                                intel_dp->compliance.test_lane_count)) {
1914                         index = intel_dp_rate_index(intel_dp->common_rates,
1915                                                     intel_dp->num_common_rates,
1916                                                     intel_dp->compliance.test_link_rate);
1917                         if (index >= 0)
1918                                 limits->min_clock = limits->max_clock = index;
1919                         limits->min_lane_count = limits->max_lane_count =
1920                                 intel_dp->compliance.test_lane_count;
1921                 }
1922         }
1923 }
1924
1925 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1926 {
1927         /*
1928          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1929          * format of the number of bytes per pixel will be half the number
1930          * of bytes of RGB pixel.
1931          */
1932         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1933                 bpp /= 2;
1934
1935         return bpp;
1936 }
1937
1938 /* Optimize link config in order: max bpp, min clock, min lanes */
1939 static int
1940 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1941                                   struct intel_crtc_state *pipe_config,
1942                                   const struct link_config_limits *limits)
1943 {
1944         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1945         int bpp, clock, lane_count;
1946         int mode_rate, link_clock, link_avail;
1947
1948         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1949                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
1950
1951                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1952                                                    output_bpp);
1953
1954                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1955                         for (lane_count = limits->min_lane_count;
1956                              lane_count <= limits->max_lane_count;
1957                              lane_count <<= 1) {
1958                                 link_clock = intel_dp->common_rates[clock];
1959                                 link_avail = intel_dp_max_data_rate(link_clock,
1960                                                                     lane_count);
1961
1962                                 if (mode_rate <= link_avail) {
1963                                         pipe_config->lane_count = lane_count;
1964                                         pipe_config->pipe_bpp = bpp;
1965                                         pipe_config->port_clock = link_clock;
1966
1967                                         return 0;
1968                                 }
1969                         }
1970                 }
1971         }
1972
1973         return -EINVAL;
1974 }
1975
1976 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1977 {
1978         int i, num_bpc;
1979         u8 dsc_bpc[3] = {0};
1980
1981         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1982                                                        dsc_bpc);
1983         for (i = 0; i < num_bpc; i++) {
1984                 if (dsc_max_bpc >= dsc_bpc[i])
1985                         return dsc_bpc[i] * 3;
1986         }
1987
1988         return 0;
1989 }
1990
1991 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1992                                        struct intel_crtc_state *pipe_config,
1993                                        struct drm_connector_state *conn_state,
1994                                        struct link_config_limits *limits)
1995 {
1996         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1997         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1998         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1999         u8 dsc_max_bpc;
2000         int pipe_bpp;
2001         int ret;
2002
2003         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2004                 intel_dp_supports_fec(intel_dp, pipe_config);
2005
2006         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2007                 return -EINVAL;
2008
2009         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
2010                             conn_state->max_requested_bpc);
2011
2012         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2013         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
2014                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2015                 return -EINVAL;
2016         }
2017
2018         /*
2019          * For now enable DSC for max bpp, max link rate, max lane count.
2020          * Optimize this later for the minimum possible link rate/lane count
2021          * with DSC enabled for the requested mode.
2022          */
2023         pipe_config->pipe_bpp = pipe_bpp;
2024         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2025         pipe_config->lane_count = limits->max_lane_count;
2026
2027         if (intel_dp_is_edp(intel_dp)) {
2028                 pipe_config->dsc_params.compressed_bpp =
2029                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2030                               pipe_config->pipe_bpp);
2031                 pipe_config->dsc_params.slice_count =
2032                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2033                                                         true);
2034         } else {
2035                 u16 dsc_max_output_bpp;
2036                 u8 dsc_dp_slice_count;
2037
2038                 dsc_max_output_bpp =
2039                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
2040                                                     pipe_config->lane_count,
2041                                                     adjusted_mode->crtc_clock,
2042                                                     adjusted_mode->crtc_hdisplay);
2043                 dsc_dp_slice_count =
2044                         intel_dp_dsc_get_slice_count(intel_dp,
2045                                                      adjusted_mode->crtc_clock,
2046                                                      adjusted_mode->crtc_hdisplay);
2047                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2048                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2049                         return -EINVAL;
2050                 }
2051                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
2052                                                                dsc_max_output_bpp >> 4,
2053                                                                pipe_config->pipe_bpp);
2054                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
2055         }
2056         /*
2057          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2058          * is greater than the maximum Cdclock and if slice count is even
2059          * then we need to use 2 VDSC instances.
2060          */
2061         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2062                 if (pipe_config->dsc_params.slice_count > 1) {
2063                         pipe_config->dsc_params.dsc_split = true;
2064                 } else {
2065                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2066                         return -EINVAL;
2067                 }
2068         }
2069
2070         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
2071         if (ret < 0) {
2072                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2073                               "Compressed BPP = %d\n",
2074                               pipe_config->pipe_bpp,
2075                               pipe_config->dsc_params.compressed_bpp);
2076                 return ret;
2077         }
2078
2079         pipe_config->dsc_params.compression_enable = true;
2080         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2081                       "Compressed Bpp = %d Slice Count = %d\n",
2082                       pipe_config->pipe_bpp,
2083                       pipe_config->dsc_params.compressed_bpp,
2084                       pipe_config->dsc_params.slice_count);
2085
2086         return 0;
2087 }
2088
2089 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2090 {
2091         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2092                 return 6 * 3;
2093         else
2094                 return 8 * 3;
2095 }
2096
2097 static int
2098 intel_dp_compute_link_config(struct intel_encoder *encoder,
2099                              struct intel_crtc_state *pipe_config,
2100                              struct drm_connector_state *conn_state)
2101 {
2102         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2103         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2104         struct link_config_limits limits;
2105         int common_len;
2106         int ret;
2107
2108         common_len = intel_dp_common_len_rate_limit(intel_dp,
2109                                                     intel_dp->max_link_rate);
2110
2111         /* No common link rates between source and sink */
2112         WARN_ON(common_len <= 0);
2113
2114         limits.min_clock = 0;
2115         limits.max_clock = common_len - 1;
2116
2117         limits.min_lane_count = 1;
2118         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2119
2120         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2121         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2122
2123         if (intel_dp_is_edp(intel_dp)) {
2124                 /*
2125                  * Use the maximum clock and number of lanes the eDP panel
2126                  * advertizes being capable of. The panels are generally
2127                  * designed to support only a single clock and lane
2128                  * configuration, and typically these values correspond to the
2129                  * native resolution of the panel.
2130                  */
2131                 limits.min_lane_count = limits.max_lane_count;
2132                 limits.min_clock = limits.max_clock;
2133         }
2134
2135         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2136
2137         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2138                       "max rate %d max bpp %d pixel clock %iKHz\n",
2139                       limits.max_lane_count,
2140                       intel_dp->common_rates[limits.max_clock],
2141                       limits.max_bpp, adjusted_mode->crtc_clock);
2142
2143         /*
2144          * Optimize for slow and wide. This is the place to add alternative
2145          * optimization policy.
2146          */
2147         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2148
2149         /* enable compression if the mode doesn't fit available BW */
2150         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2151         if (ret || intel_dp->force_dsc_en) {
2152                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2153                                                   conn_state, &limits);
2154                 if (ret < 0)
2155                         return ret;
2156         }
2157
2158         if (pipe_config->dsc_params.compression_enable) {
2159                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2160                               pipe_config->lane_count, pipe_config->port_clock,
2161                               pipe_config->pipe_bpp,
2162                               pipe_config->dsc_params.compressed_bpp);
2163
2164                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2165                               intel_dp_link_required(adjusted_mode->crtc_clock,
2166                                                      pipe_config->dsc_params.compressed_bpp),
2167                               intel_dp_max_data_rate(pipe_config->port_clock,
2168                                                      pipe_config->lane_count));
2169         } else {
2170                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2171                               pipe_config->lane_count, pipe_config->port_clock,
2172                               pipe_config->pipe_bpp);
2173
2174                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2175                               intel_dp_link_required(adjusted_mode->crtc_clock,
2176                                                      pipe_config->pipe_bpp),
2177                               intel_dp_max_data_rate(pipe_config->port_clock,
2178                                                      pipe_config->lane_count));
2179         }
2180         return 0;
2181 }
2182
2183 static int
2184 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2185                          struct drm_connector *connector,
2186                          struct intel_crtc_state *crtc_state)
2187 {
2188         const struct drm_display_info *info = &connector->display_info;
2189         const struct drm_display_mode *adjusted_mode =
2190                 &crtc_state->base.adjusted_mode;
2191         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2192         int ret;
2193
2194         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2195             !intel_dp_get_colorimetry_status(intel_dp) ||
2196             !connector->ycbcr_420_allowed)
2197                 return 0;
2198
2199         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2200
2201         /* YCBCR 420 output conversion needs a scaler */
2202         ret = skl_update_scaler_crtc(crtc_state);
2203         if (ret) {
2204                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2205                 return ret;
2206         }
2207
2208         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2209
2210         return 0;
2211 }
2212
2213 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2214                                   const struct drm_connector_state *conn_state)
2215 {
2216         const struct intel_digital_connector_state *intel_conn_state =
2217                 to_intel_digital_connector_state(conn_state);
2218         const struct drm_display_mode *adjusted_mode =
2219                 &crtc_state->base.adjusted_mode;
2220
2221         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2222                 /*
2223                  * See:
2224                  * CEA-861-E - 5.1 Default Encoding Parameters
2225                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2226                  */
2227                 return crtc_state->pipe_bpp != 18 &&
2228                         drm_default_rgb_quant_range(adjusted_mode) ==
2229                         HDMI_QUANTIZATION_RANGE_LIMITED;
2230         } else {
2231                 return intel_conn_state->broadcast_rgb ==
2232                         INTEL_BROADCAST_RGB_LIMITED;
2233         }
2234 }
2235
2236 int
2237 intel_dp_compute_config(struct intel_encoder *encoder,
2238                         struct intel_crtc_state *pipe_config,
2239                         struct drm_connector_state *conn_state)
2240 {
2241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2242         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2243         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2244         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2245         enum port port = encoder->port;
2246         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2247         struct intel_connector *intel_connector = intel_dp->attached_connector;
2248         struct intel_digital_connector_state *intel_conn_state =
2249                 to_intel_digital_connector_state(conn_state);
2250         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2251                                            DP_DPCD_QUIRK_CONSTANT_N);
2252         int ret = 0, output_bpp;
2253
2254         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2255                 pipe_config->has_pch_encoder = true;
2256
2257         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2258         if (lspcon->active)
2259                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2260         else
2261                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2262                                                pipe_config);
2263
2264         if (ret)
2265                 return ret;
2266
2267         pipe_config->has_drrs = false;
2268         if (IS_G4X(dev_priv) || port == PORT_A)
2269                 pipe_config->has_audio = false;
2270         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2271                 pipe_config->has_audio = intel_dp->has_audio;
2272         else
2273                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2274
2275         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2276                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2277                                        adjusted_mode);
2278
2279                 if (INTEL_GEN(dev_priv) >= 9) {
2280                         ret = skl_update_scaler_crtc(pipe_config);
2281                         if (ret)
2282                                 return ret;
2283                 }
2284
2285                 if (HAS_GMCH(dev_priv))
2286                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2287                                                  conn_state->scaling_mode);
2288                 else
2289                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2290                                                 conn_state->scaling_mode);
2291         }
2292
2293         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2294                 return -EINVAL;
2295
2296         if (HAS_GMCH(dev_priv) &&
2297             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2298                 return -EINVAL;
2299
2300         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2301                 return -EINVAL;
2302
2303         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2304         if (ret < 0)
2305                 return ret;
2306
2307         pipe_config->limited_color_range =
2308                 intel_dp_limited_color_range(pipe_config, conn_state);
2309
2310         if (pipe_config->dsc_params.compression_enable)
2311                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2312         else
2313                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2314
2315         intel_link_compute_m_n(output_bpp,
2316                                pipe_config->lane_count,
2317                                adjusted_mode->crtc_clock,
2318                                pipe_config->port_clock,
2319                                &pipe_config->dp_m_n,
2320                                constant_n, pipe_config->fec_enable);
2321
2322         if (intel_connector->panel.downclock_mode != NULL &&
2323                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2324                         pipe_config->has_drrs = true;
2325                         intel_link_compute_m_n(output_bpp,
2326                                                pipe_config->lane_count,
2327                                                intel_connector->panel.downclock_mode->clock,
2328                                                pipe_config->port_clock,
2329                                                &pipe_config->dp_m2_n2,
2330                                                constant_n, pipe_config->fec_enable);
2331         }
2332
2333         if (!HAS_DDI(dev_priv))
2334                 intel_dp_set_clock(encoder, pipe_config);
2335
2336         intel_psr_compute_config(intel_dp, pipe_config);
2337
2338         return 0;
2339 }
2340
2341 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2342                               int link_rate, u8 lane_count,
2343                               bool link_mst)
2344 {
2345         intel_dp->link_trained = false;
2346         intel_dp->link_rate = link_rate;
2347         intel_dp->lane_count = lane_count;
2348         intel_dp->link_mst = link_mst;
2349 }
2350
2351 static void intel_dp_prepare(struct intel_encoder *encoder,
2352                              const struct intel_crtc_state *pipe_config)
2353 {
2354         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2355         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2356         enum port port = encoder->port;
2357         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2358         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2359
2360         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2361                                  pipe_config->lane_count,
2362                                  intel_crtc_has_type(pipe_config,
2363                                                      INTEL_OUTPUT_DP_MST));
2364
2365         /*
2366          * There are four kinds of DP registers:
2367          *
2368          *      IBX PCH
2369          *      SNB CPU
2370          *      IVB CPU
2371          *      CPT PCH
2372          *
2373          * IBX PCH and CPU are the same for almost everything,
2374          * except that the CPU DP PLL is configured in this
2375          * register
2376          *
2377          * CPT PCH is quite different, having many bits moved
2378          * to the TRANS_DP_CTL register instead. That
2379          * configuration happens (oddly) in ironlake_pch_enable
2380          */
2381
2382         /* Preserve the BIOS-computed detected bit. This is
2383          * supposed to be read-only.
2384          */
2385         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2386
2387         /* Handle DP bits in common between all three register formats */
2388         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2389         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2390
2391         /* Split out the IBX/CPU vs CPT settings */
2392
2393         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2394                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2395                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2396                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2397                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2398                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2399
2400                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2401                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2402
2403                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2404         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2405                 u32 trans_dp;
2406
2407                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2408
2409                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2410                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2411                         trans_dp |= TRANS_DP_ENH_FRAMING;
2412                 else
2413                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2414                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2415         } else {
2416                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2417                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2418
2419                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2420                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2421                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2422                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2423                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2424
2425                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2426                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2427
2428                 if (IS_CHERRYVIEW(dev_priv))
2429                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2430                 else
2431                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2432         }
2433 }
2434
2435 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2436 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2437
2438 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2439 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2440
2441 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2442 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2443
2444 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2445
2446 static void wait_panel_status(struct intel_dp *intel_dp,
2447                                        u32 mask,
2448                                        u32 value)
2449 {
2450         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2451         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2452
2453         lockdep_assert_held(&dev_priv->pps_mutex);
2454
2455         intel_pps_verify_state(intel_dp);
2456
2457         pp_stat_reg = _pp_stat_reg(intel_dp);
2458         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2459
2460         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2461                         mask, value,
2462                         I915_READ(pp_stat_reg),
2463                         I915_READ(pp_ctrl_reg));
2464
2465         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2466                                        mask, value, 5000))
2467                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2468                                 I915_READ(pp_stat_reg),
2469                                 I915_READ(pp_ctrl_reg));
2470
2471         DRM_DEBUG_KMS("Wait complete\n");
2472 }
2473
2474 static void wait_panel_on(struct intel_dp *intel_dp)
2475 {
2476         DRM_DEBUG_KMS("Wait for panel power on\n");
2477         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2478 }
2479
2480 static void wait_panel_off(struct intel_dp *intel_dp)
2481 {
2482         DRM_DEBUG_KMS("Wait for panel power off time\n");
2483         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2484 }
2485
2486 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2487 {
2488         ktime_t panel_power_on_time;
2489         s64 panel_power_off_duration;
2490
2491         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2492
2493         /* take the difference of currrent time and panel power off time
2494          * and then make panel wait for t11_t12 if needed. */
2495         panel_power_on_time = ktime_get_boottime();
2496         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2497
2498         /* When we disable the VDD override bit last we have to do the manual
2499          * wait. */
2500         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2501                 wait_remaining_ms_from_jiffies(jiffies,
2502                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2503
2504         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2505 }
2506
2507 static void wait_backlight_on(struct intel_dp *intel_dp)
2508 {
2509         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2510                                        intel_dp->backlight_on_delay);
2511 }
2512
2513 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2514 {
2515         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2516                                        intel_dp->backlight_off_delay);
2517 }
2518
2519 /* Read the current pp_control value, unlocking the register if it
2520  * is locked
2521  */
2522
2523 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2524 {
2525         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2526         u32 control;
2527
2528         lockdep_assert_held(&dev_priv->pps_mutex);
2529
2530         control = I915_READ(_pp_ctrl_reg(intel_dp));
2531         if (WARN_ON(!HAS_DDI(dev_priv) &&
2532                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2533                 control &= ~PANEL_UNLOCK_MASK;
2534                 control |= PANEL_UNLOCK_REGS;
2535         }
2536         return control;
2537 }
2538
2539 /*
2540  * Must be paired with edp_panel_vdd_off().
2541  * Must hold pps_mutex around the whole on/off sequence.
2542  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2543  */
2544 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2545 {
2546         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2547         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2548         u32 pp;
2549         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2550         bool need_to_disable = !intel_dp->want_panel_vdd;
2551
2552         lockdep_assert_held(&dev_priv->pps_mutex);
2553
2554         if (!intel_dp_is_edp(intel_dp))
2555                 return false;
2556
2557         cancel_delayed_work(&intel_dp->panel_vdd_work);
2558         intel_dp->want_panel_vdd = true;
2559
2560         if (edp_have_panel_vdd(intel_dp))
2561                 return need_to_disable;
2562
2563         intel_display_power_get(dev_priv,
2564                                 intel_aux_power_domain(intel_dig_port));
2565
2566         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2567                       port_name(intel_dig_port->base.port));
2568
2569         if (!edp_have_panel_power(intel_dp))
2570                 wait_panel_power_cycle(intel_dp);
2571
2572         pp = ironlake_get_pp_control(intel_dp);
2573         pp |= EDP_FORCE_VDD;
2574
2575         pp_stat_reg = _pp_stat_reg(intel_dp);
2576         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2577
2578         I915_WRITE(pp_ctrl_reg, pp);
2579         POSTING_READ(pp_ctrl_reg);
2580         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2581                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2582         /*
2583          * If the panel wasn't on, delay before accessing aux channel
2584          */
2585         if (!edp_have_panel_power(intel_dp)) {
2586                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2587                               port_name(intel_dig_port->base.port));
2588                 msleep(intel_dp->panel_power_up_delay);
2589         }
2590
2591         return need_to_disable;
2592 }
2593
2594 /*
2595  * Must be paired with intel_edp_panel_vdd_off() or
2596  * intel_edp_panel_off().
2597  * Nested calls to these functions are not allowed since
2598  * we drop the lock. Caller must use some higher level
2599  * locking to prevent nested calls from other threads.
2600  */
2601 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2602 {
2603         intel_wakeref_t wakeref;
2604         bool vdd;
2605
2606         if (!intel_dp_is_edp(intel_dp))
2607                 return;
2608
2609         vdd = false;
2610         with_pps_lock(intel_dp, wakeref)
2611                 vdd = edp_panel_vdd_on(intel_dp);
2612         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2613              port_name(dp_to_dig_port(intel_dp)->base.port));
2614 }
2615
2616 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2617 {
2618         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2619         struct intel_digital_port *intel_dig_port =
2620                 dp_to_dig_port(intel_dp);
2621         u32 pp;
2622         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2623
2624         lockdep_assert_held(&dev_priv->pps_mutex);
2625
2626         WARN_ON(intel_dp->want_panel_vdd);
2627
2628         if (!edp_have_panel_vdd(intel_dp))
2629                 return;
2630
2631         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2632                       port_name(intel_dig_port->base.port));
2633
2634         pp = ironlake_get_pp_control(intel_dp);
2635         pp &= ~EDP_FORCE_VDD;
2636
2637         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2638         pp_stat_reg = _pp_stat_reg(intel_dp);
2639
2640         I915_WRITE(pp_ctrl_reg, pp);
2641         POSTING_READ(pp_ctrl_reg);
2642
2643         /* Make sure sequencer is idle before allowing subsequent activity */
2644         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2645         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2646
2647         if ((pp & PANEL_POWER_ON) == 0)
2648                 intel_dp->panel_power_off_time = ktime_get_boottime();
2649
2650         intel_display_power_put_unchecked(dev_priv,
2651                                           intel_aux_power_domain(intel_dig_port));
2652 }
2653
2654 static void edp_panel_vdd_work(struct work_struct *__work)
2655 {
2656         struct intel_dp *intel_dp =
2657                 container_of(to_delayed_work(__work),
2658                              struct intel_dp, panel_vdd_work);
2659         intel_wakeref_t wakeref;
2660
2661         with_pps_lock(intel_dp, wakeref) {
2662                 if (!intel_dp->want_panel_vdd)
2663                         edp_panel_vdd_off_sync(intel_dp);
2664         }
2665 }
2666
2667 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2668 {
2669         unsigned long delay;
2670
2671         /*
2672          * Queue the timer to fire a long time from now (relative to the power
2673          * down delay) to keep the panel power up across a sequence of
2674          * operations.
2675          */
2676         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2677         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2678 }
2679
2680 /*
2681  * Must be paired with edp_panel_vdd_on().
2682  * Must hold pps_mutex around the whole on/off sequence.
2683  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2684  */
2685 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2686 {
2687         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2688
2689         lockdep_assert_held(&dev_priv->pps_mutex);
2690
2691         if (!intel_dp_is_edp(intel_dp))
2692                 return;
2693
2694         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2695              port_name(dp_to_dig_port(intel_dp)->base.port));
2696
2697         intel_dp->want_panel_vdd = false;
2698
2699         if (sync)
2700                 edp_panel_vdd_off_sync(intel_dp);
2701         else
2702                 edp_panel_vdd_schedule_off(intel_dp);
2703 }
2704
2705 static void edp_panel_on(struct intel_dp *intel_dp)
2706 {
2707         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2708         u32 pp;
2709         i915_reg_t pp_ctrl_reg;
2710
2711         lockdep_assert_held(&dev_priv->pps_mutex);
2712
2713         if (!intel_dp_is_edp(intel_dp))
2714                 return;
2715
2716         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2717                       port_name(dp_to_dig_port(intel_dp)->base.port));
2718
2719         if (WARN(edp_have_panel_power(intel_dp),
2720                  "eDP port %c panel power already on\n",
2721                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2722                 return;
2723
2724         wait_panel_power_cycle(intel_dp);
2725
2726         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2727         pp = ironlake_get_pp_control(intel_dp);
2728         if (IS_GEN(dev_priv, 5)) {
2729                 /* ILK workaround: disable reset around power sequence */
2730                 pp &= ~PANEL_POWER_RESET;
2731                 I915_WRITE(pp_ctrl_reg, pp);
2732                 POSTING_READ(pp_ctrl_reg);
2733         }
2734
2735         pp |= PANEL_POWER_ON;
2736         if (!IS_GEN(dev_priv, 5))
2737                 pp |= PANEL_POWER_RESET;
2738
2739         I915_WRITE(pp_ctrl_reg, pp);
2740         POSTING_READ(pp_ctrl_reg);
2741
2742         wait_panel_on(intel_dp);
2743         intel_dp->last_power_on = jiffies;
2744
2745         if (IS_GEN(dev_priv, 5)) {
2746                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2747                 I915_WRITE(pp_ctrl_reg, pp);
2748                 POSTING_READ(pp_ctrl_reg);
2749         }
2750 }
2751
2752 void intel_edp_panel_on(struct intel_dp *intel_dp)
2753 {
2754         intel_wakeref_t wakeref;
2755
2756         if (!intel_dp_is_edp(intel_dp))
2757                 return;
2758
2759         with_pps_lock(intel_dp, wakeref)
2760                 edp_panel_on(intel_dp);
2761 }
2762
2763
2764 static void edp_panel_off(struct intel_dp *intel_dp)
2765 {
2766         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2767         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2768         u32 pp;
2769         i915_reg_t pp_ctrl_reg;
2770
2771         lockdep_assert_held(&dev_priv->pps_mutex);
2772
2773         if (!intel_dp_is_edp(intel_dp))
2774                 return;
2775
2776         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2777                       port_name(dig_port->base.port));
2778
2779         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2780              port_name(dig_port->base.port));
2781
2782         pp = ironlake_get_pp_control(intel_dp);
2783         /* We need to switch off panel power _and_ force vdd, for otherwise some
2784          * panels get very unhappy and cease to work. */
2785         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2786                 EDP_BLC_ENABLE);
2787
2788         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2789
2790         intel_dp->want_panel_vdd = false;
2791
2792         I915_WRITE(pp_ctrl_reg, pp);
2793         POSTING_READ(pp_ctrl_reg);
2794
2795         wait_panel_off(intel_dp);
2796         intel_dp->panel_power_off_time = ktime_get_boottime();
2797
2798         /* We got a reference when we enabled the VDD. */
2799         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2800 }
2801
2802 void intel_edp_panel_off(struct intel_dp *intel_dp)
2803 {
2804         intel_wakeref_t wakeref;
2805
2806         if (!intel_dp_is_edp(intel_dp))
2807                 return;
2808
2809         with_pps_lock(intel_dp, wakeref)
2810                 edp_panel_off(intel_dp);
2811 }
2812
2813 /* Enable backlight in the panel power control. */
2814 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2815 {
2816         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2817         intel_wakeref_t wakeref;
2818
2819         /*
2820          * If we enable the backlight right away following a panel power
2821          * on, we may see slight flicker as the panel syncs with the eDP
2822          * link.  So delay a bit to make sure the image is solid before
2823          * allowing it to appear.
2824          */
2825         wait_backlight_on(intel_dp);
2826
2827         with_pps_lock(intel_dp, wakeref) {
2828                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2829                 u32 pp;
2830
2831                 pp = ironlake_get_pp_control(intel_dp);
2832                 pp |= EDP_BLC_ENABLE;
2833
2834                 I915_WRITE(pp_ctrl_reg, pp);
2835                 POSTING_READ(pp_ctrl_reg);
2836         }
2837 }
2838
2839 /* Enable backlight PWM and backlight PP control. */
2840 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2841                             const struct drm_connector_state *conn_state)
2842 {
2843         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2844
2845         if (!intel_dp_is_edp(intel_dp))
2846                 return;
2847
2848         DRM_DEBUG_KMS("\n");
2849
2850         intel_panel_enable_backlight(crtc_state, conn_state);
2851         _intel_edp_backlight_on(intel_dp);
2852 }
2853
2854 /* Disable backlight in the panel power control. */
2855 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2856 {
2857         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2858         intel_wakeref_t wakeref;
2859
2860         if (!intel_dp_is_edp(intel_dp))
2861                 return;
2862
2863         with_pps_lock(intel_dp, wakeref) {
2864                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2865                 u32 pp;
2866
2867                 pp = ironlake_get_pp_control(intel_dp);
2868                 pp &= ~EDP_BLC_ENABLE;
2869
2870                 I915_WRITE(pp_ctrl_reg, pp);
2871                 POSTING_READ(pp_ctrl_reg);
2872         }
2873
2874         intel_dp->last_backlight_off = jiffies;
2875         edp_wait_backlight_off(intel_dp);
2876 }
2877
2878 /* Disable backlight PP control and backlight PWM. */
2879 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2880 {
2881         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2882
2883         if (!intel_dp_is_edp(intel_dp))
2884                 return;
2885
2886         DRM_DEBUG_KMS("\n");
2887
2888         _intel_edp_backlight_off(intel_dp);
2889         intel_panel_disable_backlight(old_conn_state);
2890 }
2891
2892 /*
2893  * Hook for controlling the panel power control backlight through the bl_power
2894  * sysfs attribute. Take care to handle multiple calls.
2895  */
2896 static void intel_edp_backlight_power(struct intel_connector *connector,
2897                                       bool enable)
2898 {
2899         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2900         intel_wakeref_t wakeref;
2901         bool is_enabled;
2902
2903         is_enabled = false;
2904         with_pps_lock(intel_dp, wakeref)
2905                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2906         if (is_enabled == enable)
2907                 return;
2908
2909         DRM_DEBUG_KMS("panel power control backlight %s\n",
2910                       enable ? "enable" : "disable");
2911
2912         if (enable)
2913                 _intel_edp_backlight_on(intel_dp);
2914         else
2915                 _intel_edp_backlight_off(intel_dp);
2916 }
2917
2918 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2919 {
2920         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2921         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2922         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2923
2924         I915_STATE_WARN(cur_state != state,
2925                         "DP port %c state assertion failure (expected %s, current %s)\n",
2926                         port_name(dig_port->base.port),
2927                         onoff(state), onoff(cur_state));
2928 }
2929 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2930
2931 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2932 {
2933         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2934
2935         I915_STATE_WARN(cur_state != state,
2936                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2937                         onoff(state), onoff(cur_state));
2938 }
2939 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2940 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2941
2942 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2943                                 const struct intel_crtc_state *pipe_config)
2944 {
2945         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2946         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2947
2948         assert_pipe_disabled(dev_priv, crtc->pipe);
2949         assert_dp_port_disabled(intel_dp);
2950         assert_edp_pll_disabled(dev_priv);
2951
2952         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2953                       pipe_config->port_clock);
2954
2955         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2956
2957         if (pipe_config->port_clock == 162000)
2958                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2959         else
2960                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2961
2962         I915_WRITE(DP_A, intel_dp->DP);
2963         POSTING_READ(DP_A);
2964         udelay(500);
2965
2966         /*
2967          * [DevILK] Work around required when enabling DP PLL
2968          * while a pipe is enabled going to FDI:
2969          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2970          * 2. Program DP PLL enable
2971          */
2972         if (IS_GEN(dev_priv, 5))
2973                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2974
2975         intel_dp->DP |= DP_PLL_ENABLE;
2976
2977         I915_WRITE(DP_A, intel_dp->DP);
2978         POSTING_READ(DP_A);
2979         udelay(200);
2980 }
2981
2982 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2983                                  const struct intel_crtc_state *old_crtc_state)
2984 {
2985         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2986         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2987
2988         assert_pipe_disabled(dev_priv, crtc->pipe);
2989         assert_dp_port_disabled(intel_dp);
2990         assert_edp_pll_enabled(dev_priv);
2991
2992         DRM_DEBUG_KMS("disabling eDP PLL\n");
2993
2994         intel_dp->DP &= ~DP_PLL_ENABLE;
2995
2996         I915_WRITE(DP_A, intel_dp->DP);
2997         POSTING_READ(DP_A);
2998         udelay(200);
2999 }
3000
3001 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3002 {
3003         /*
3004          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3005          * be capable of signalling downstream hpd with a long pulse.
3006          * Whether or not that means D3 is safe to use is not clear,
3007          * but let's assume so until proven otherwise.
3008          *
3009          * FIXME should really check all downstream ports...
3010          */
3011         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3012                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3013                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3014 }
3015
3016 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3017                                            const struct intel_crtc_state *crtc_state,
3018                                            bool enable)
3019 {
3020         int ret;
3021
3022         if (!crtc_state->dsc_params.compression_enable)
3023                 return;
3024
3025         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3026                                  enable ? DP_DECOMPRESSION_EN : 0);
3027         if (ret < 0)
3028                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3029                               enable ? "enable" : "disable");
3030 }
3031
3032 /* If the sink supports it, try to set the power state appropriately */
3033 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3034 {
3035         int ret, i;
3036
3037         /* Should have a valid DPCD by this point */
3038         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3039                 return;
3040
3041         if (mode != DRM_MODE_DPMS_ON) {
3042                 if (downstream_hpd_needs_d0(intel_dp))
3043                         return;
3044
3045                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3046                                          DP_SET_POWER_D3);
3047         } else {
3048                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3049
3050                 /*
3051                  * When turning on, we need to retry for 1ms to give the sink
3052                  * time to wake up.
3053                  */
3054                 for (i = 0; i < 3; i++) {
3055                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3056                                                  DP_SET_POWER_D0);
3057                         if (ret == 1)
3058                                 break;
3059                         msleep(1);
3060                 }
3061
3062                 if (ret == 1 && lspcon->active)
3063                         lspcon_wait_pcon_mode(lspcon);
3064         }
3065
3066         if (ret != 1)
3067                 DRM_DEBUG_KMS("failed to %s sink power state\n",
3068                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3069 }
3070
3071 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3072                                  enum port port, enum pipe *pipe)
3073 {
3074         enum pipe p;
3075
3076         for_each_pipe(dev_priv, p) {
3077                 u32 val = I915_READ(TRANS_DP_CTL(p));
3078
3079                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3080                         *pipe = p;
3081                         return true;
3082                 }
3083         }
3084
3085         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3086
3087         /* must initialize pipe to something for the asserts */
3088         *pipe = PIPE_A;
3089
3090         return false;
3091 }
3092
3093 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3094                            i915_reg_t dp_reg, enum port port,
3095                            enum pipe *pipe)
3096 {
3097         bool ret;
3098         u32 val;
3099
3100         val = I915_READ(dp_reg);
3101
3102         ret = val & DP_PORT_EN;
3103
3104         /* asserts want to know the pipe even if the port is disabled */
3105         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3106                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3107         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3108                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3109         else if (IS_CHERRYVIEW(dev_priv))
3110                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3111         else
3112                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3113
3114         return ret;
3115 }
3116
3117 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3118                                   enum pipe *pipe)
3119 {
3120         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3121         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3122         intel_wakeref_t wakeref;
3123         bool ret;
3124
3125         wakeref = intel_display_power_get_if_enabled(dev_priv,
3126                                                      encoder->power_domain);
3127         if (!wakeref)
3128                 return false;
3129
3130         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3131                                     encoder->port, pipe);
3132
3133         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3134
3135         return ret;
3136 }
3137
3138 static void intel_dp_get_config(struct intel_encoder *encoder,
3139                                 struct intel_crtc_state *pipe_config)
3140 {
3141         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3142         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3143         u32 tmp, flags = 0;
3144         enum port port = encoder->port;
3145         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3146
3147         if (encoder->type == INTEL_OUTPUT_EDP)
3148                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3149         else
3150                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3151
3152         tmp = I915_READ(intel_dp->output_reg);
3153
3154         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3155
3156         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3157                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3158
3159                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3160                         flags |= DRM_MODE_FLAG_PHSYNC;
3161                 else
3162                         flags |= DRM_MODE_FLAG_NHSYNC;
3163
3164                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3165                         flags |= DRM_MODE_FLAG_PVSYNC;
3166                 else
3167                         flags |= DRM_MODE_FLAG_NVSYNC;
3168         } else {
3169                 if (tmp & DP_SYNC_HS_HIGH)
3170                         flags |= DRM_MODE_FLAG_PHSYNC;
3171                 else
3172                         flags |= DRM_MODE_FLAG_NHSYNC;
3173
3174                 if (tmp & DP_SYNC_VS_HIGH)
3175                         flags |= DRM_MODE_FLAG_PVSYNC;
3176                 else
3177                         flags |= DRM_MODE_FLAG_NVSYNC;
3178         }
3179
3180         pipe_config->base.adjusted_mode.flags |= flags;
3181
3182         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3183                 pipe_config->limited_color_range = true;
3184
3185         pipe_config->lane_count =
3186                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3187
3188         intel_dp_get_m_n(crtc, pipe_config);
3189
3190         if (port == PORT_A) {
3191                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3192                         pipe_config->port_clock = 162000;
3193                 else
3194                         pipe_config->port_clock = 270000;
3195         }
3196
3197         pipe_config->base.adjusted_mode.crtc_clock =
3198                 intel_dotclock_calculate(pipe_config->port_clock,
3199                                          &pipe_config->dp_m_n);
3200
3201         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3202             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3203                 /*
3204                  * This is a big fat ugly hack.
3205                  *
3206                  * Some machines in UEFI boot mode provide us a VBT that has 18
3207                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3208                  * unknown we fail to light up. Yet the same BIOS boots up with
3209                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3210                  * max, not what it tells us to use.
3211                  *
3212                  * Note: This will still be broken if the eDP panel is not lit
3213                  * up by the BIOS, and thus we can't get the mode at module
3214                  * load.
3215                  */
3216                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3217                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3218                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3219         }
3220 }
3221
3222 static void intel_disable_dp(struct intel_encoder *encoder,
3223                              const struct intel_crtc_state *old_crtc_state,
3224                              const struct drm_connector_state *old_conn_state)
3225 {
3226         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3227
3228         intel_dp->link_trained = false;
3229
3230         if (old_crtc_state->has_audio)
3231                 intel_audio_codec_disable(encoder,
3232                                           old_crtc_state, old_conn_state);
3233
3234         /* Make sure the panel is off before trying to change the mode. But also
3235          * ensure that we have vdd while we switch off the panel. */
3236         intel_edp_panel_vdd_on(intel_dp);
3237         intel_edp_backlight_off(old_conn_state);
3238         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3239         intel_edp_panel_off(intel_dp);
3240 }
3241
3242 static void g4x_disable_dp(struct intel_encoder *encoder,
3243                            const struct intel_crtc_state *old_crtc_state,
3244                            const struct drm_connector_state *old_conn_state)
3245 {
3246         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3247 }
3248
3249 static void vlv_disable_dp(struct intel_encoder *encoder,
3250                            const struct intel_crtc_state *old_crtc_state,
3251                            const struct drm_connector_state *old_conn_state)
3252 {
3253         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3254 }
3255
3256 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3257                                 const struct intel_crtc_state *old_crtc_state,
3258                                 const struct drm_connector_state *old_conn_state)
3259 {
3260         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3261         enum port port = encoder->port;
3262
3263         /*
3264          * Bspec does not list a specific disable sequence for g4x DP.
3265          * Follow the ilk+ sequence (disable pipe before the port) for
3266          * g4x DP as it does not suffer from underruns like the normal
3267          * g4x modeset sequence (disable pipe after the port).
3268          */
3269         intel_dp_link_down(encoder, old_crtc_state);
3270
3271         /* Only ilk+ has port A */
3272         if (port == PORT_A)
3273                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3274 }
3275
3276 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3277                                 const struct intel_crtc_state *old_crtc_state,
3278                                 const struct drm_connector_state *old_conn_state)
3279 {
3280         intel_dp_link_down(encoder, old_crtc_state);
3281 }
3282
3283 static void chv_post_disable_dp(struct intel_encoder *encoder,
3284                                 const struct intel_crtc_state *old_crtc_state,
3285                                 const struct drm_connector_state *old_conn_state)
3286 {
3287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3288
3289         intel_dp_link_down(encoder, old_crtc_state);
3290
3291         vlv_dpio_get(dev_priv);
3292
3293         /* Assert data lane reset */
3294         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3295
3296         vlv_dpio_put(dev_priv);
3297 }
3298
3299 static void
3300 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3301                          u32 *DP,
3302                          u8 dp_train_pat)
3303 {
3304         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3305         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3306         enum port port = intel_dig_port->base.port;
3307         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3308
3309         if (dp_train_pat & train_pat_mask)
3310                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3311                               dp_train_pat & train_pat_mask);
3312
3313         if (HAS_DDI(dev_priv)) {
3314                 u32 temp = I915_READ(DP_TP_CTL(port));
3315
3316                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3317                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3318                 else
3319                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3320
3321                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3322                 switch (dp_train_pat & train_pat_mask) {
3323                 case DP_TRAINING_PATTERN_DISABLE:
3324                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3325
3326                         break;
3327                 case DP_TRAINING_PATTERN_1:
3328                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3329                         break;
3330                 case DP_TRAINING_PATTERN_2:
3331                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3332                         break;
3333                 case DP_TRAINING_PATTERN_3:
3334                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3335                         break;
3336                 case DP_TRAINING_PATTERN_4:
3337                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3338                         break;
3339                 }
3340                 I915_WRITE(DP_TP_CTL(port), temp);
3341
3342         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3343                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3344                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3345
3346                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3347                 case DP_TRAINING_PATTERN_DISABLE:
3348                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3349                         break;
3350                 case DP_TRAINING_PATTERN_1:
3351                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3352                         break;
3353                 case DP_TRAINING_PATTERN_2:
3354                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3355                         break;
3356                 case DP_TRAINING_PATTERN_3:
3357                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3358                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3359                         break;
3360                 }
3361
3362         } else {
3363                 *DP &= ~DP_LINK_TRAIN_MASK;
3364
3365                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3366                 case DP_TRAINING_PATTERN_DISABLE:
3367                         *DP |= DP_LINK_TRAIN_OFF;
3368                         break;
3369                 case DP_TRAINING_PATTERN_1:
3370                         *DP |= DP_LINK_TRAIN_PAT_1;
3371                         break;
3372                 case DP_TRAINING_PATTERN_2:
3373                         *DP |= DP_LINK_TRAIN_PAT_2;
3374                         break;
3375                 case DP_TRAINING_PATTERN_3:
3376                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3377                         *DP |= DP_LINK_TRAIN_PAT_2;
3378                         break;
3379                 }
3380         }
3381 }
3382
3383 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3384                                  const struct intel_crtc_state *old_crtc_state)
3385 {
3386         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3387
3388         /* enable with pattern 1 (as per spec) */
3389
3390         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3391
3392         /*
3393          * Magic for VLV/CHV. We _must_ first set up the register
3394          * without actually enabling the port, and then do another
3395          * write to enable the port. Otherwise link training will
3396          * fail when the power sequencer is freshly used for this port.
3397          */
3398         intel_dp->DP |= DP_PORT_EN;
3399         if (old_crtc_state->has_audio)
3400                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3401
3402         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3403         POSTING_READ(intel_dp->output_reg);
3404 }
3405
3406 static void intel_enable_dp(struct intel_encoder *encoder,
3407                             const struct intel_crtc_state *pipe_config,
3408                             const struct drm_connector_state *conn_state)
3409 {
3410         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3411         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3412         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3413         u32 dp_reg = I915_READ(intel_dp->output_reg);
3414         enum pipe pipe = crtc->pipe;
3415         intel_wakeref_t wakeref;
3416
3417         if (WARN_ON(dp_reg & DP_PORT_EN))
3418                 return;
3419
3420         with_pps_lock(intel_dp, wakeref) {
3421                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3422                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3423
3424                 intel_dp_enable_port(intel_dp, pipe_config);
3425
3426                 edp_panel_vdd_on(intel_dp);
3427                 edp_panel_on(intel_dp);
3428                 edp_panel_vdd_off(intel_dp, true);
3429         }
3430
3431         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3432                 unsigned int lane_mask = 0x0;
3433
3434                 if (IS_CHERRYVIEW(dev_priv))
3435                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3436
3437                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3438                                     lane_mask);
3439         }
3440
3441         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3442         intel_dp_start_link_train(intel_dp);
3443         intel_dp_stop_link_train(intel_dp);
3444
3445         if (pipe_config->has_audio) {
3446                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3447                                  pipe_name(pipe));
3448                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3449         }
3450 }
3451
3452 static void g4x_enable_dp(struct intel_encoder *encoder,
3453                           const struct intel_crtc_state *pipe_config,
3454                           const struct drm_connector_state *conn_state)
3455 {
3456         intel_enable_dp(encoder, pipe_config, conn_state);
3457         intel_edp_backlight_on(pipe_config, conn_state);
3458 }
3459
3460 static void vlv_enable_dp(struct intel_encoder *encoder,
3461                           const struct intel_crtc_state *pipe_config,
3462                           const struct drm_connector_state *conn_state)
3463 {
3464         intel_edp_backlight_on(pipe_config, conn_state);
3465 }
3466
3467 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3468                               const struct intel_crtc_state *pipe_config,
3469                               const struct drm_connector_state *conn_state)
3470 {
3471         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3472         enum port port = encoder->port;
3473
3474         intel_dp_prepare(encoder, pipe_config);
3475
3476         /* Only ilk+ has port A */
3477         if (port == PORT_A)
3478                 ironlake_edp_pll_on(intel_dp, pipe_config);
3479 }
3480
3481 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3482 {
3483         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3484         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3485         enum pipe pipe = intel_dp->pps_pipe;
3486         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3487
3488         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3489
3490         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3491                 return;
3492
3493         edp_panel_vdd_off_sync(intel_dp);
3494
3495         /*
3496          * VLV seems to get confused when multiple power sequencers
3497          * have the same port selected (even if only one has power/vdd
3498          * enabled). The failure manifests as vlv_wait_port_ready() failing
3499          * CHV on the other hand doesn't seem to mind having the same port
3500          * selected in multiple power sequencers, but let's clear the
3501          * port select always when logically disconnecting a power sequencer
3502          * from a port.
3503          */
3504         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3505                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3506         I915_WRITE(pp_on_reg, 0);
3507         POSTING_READ(pp_on_reg);
3508
3509         intel_dp->pps_pipe = INVALID_PIPE;
3510 }
3511
3512 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3513                                       enum pipe pipe)
3514 {
3515         struct intel_encoder *encoder;
3516
3517         lockdep_assert_held(&dev_priv->pps_mutex);
3518
3519         for_each_intel_dp(&dev_priv->drm, encoder) {
3520                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3521                 enum port port = encoder->port;
3522
3523                 WARN(intel_dp->active_pipe == pipe,
3524                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3525                      pipe_name(pipe), port_name(port));
3526
3527                 if (intel_dp->pps_pipe != pipe)
3528                         continue;
3529
3530                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3531                               pipe_name(pipe), port_name(port));
3532
3533                 /* make sure vdd is off before we steal it */
3534                 vlv_detach_power_sequencer(intel_dp);
3535         }
3536 }
3537
3538 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3539                                            const struct intel_crtc_state *crtc_state)
3540 {
3541         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3542         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3543         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3544
3545         lockdep_assert_held(&dev_priv->pps_mutex);
3546
3547         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3548
3549         if (intel_dp->pps_pipe != INVALID_PIPE &&
3550             intel_dp->pps_pipe != crtc->pipe) {
3551                 /*
3552                  * If another power sequencer was being used on this
3553                  * port previously make sure to turn off vdd there while
3554                  * we still have control of it.
3555                  */
3556                 vlv_detach_power_sequencer(intel_dp);
3557         }
3558
3559         /*
3560          * We may be stealing the power
3561          * sequencer from another port.
3562          */
3563         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3564
3565         intel_dp->active_pipe = crtc->pipe;
3566
3567         if (!intel_dp_is_edp(intel_dp))
3568                 return;
3569
3570         /* now it's all ours */
3571         intel_dp->pps_pipe = crtc->pipe;
3572
3573         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3574                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3575
3576         /* init power sequencer on this pipe and port */
3577         intel_dp_init_panel_power_sequencer(intel_dp);
3578         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3579 }
3580
3581 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3582                               const struct intel_crtc_state *pipe_config,
3583                               const struct drm_connector_state *conn_state)
3584 {
3585         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3586
3587         intel_enable_dp(encoder, pipe_config, conn_state);
3588 }
3589
3590 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3591                                   const struct intel_crtc_state *pipe_config,
3592                                   const struct drm_connector_state *conn_state)
3593 {
3594         intel_dp_prepare(encoder, pipe_config);
3595
3596         vlv_phy_pre_pll_enable(encoder, pipe_config);
3597 }
3598
3599 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3600                               const struct intel_crtc_state *pipe_config,
3601                               const struct drm_connector_state *conn_state)
3602 {
3603         chv_phy_pre_encoder_enable(encoder, pipe_config);
3604
3605         intel_enable_dp(encoder, pipe_config, conn_state);
3606
3607         /* Second common lane will stay alive on its own now */
3608         chv_phy_release_cl2_override(encoder);
3609 }
3610
3611 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3612                                   const struct intel_crtc_state *pipe_config,
3613                                   const struct drm_connector_state *conn_state)
3614 {
3615         intel_dp_prepare(encoder, pipe_config);
3616
3617         chv_phy_pre_pll_enable(encoder, pipe_config);
3618 }
3619
3620 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3621                                     const struct intel_crtc_state *old_crtc_state,
3622                                     const struct drm_connector_state *old_conn_state)
3623 {
3624         chv_phy_post_pll_disable(encoder, old_crtc_state);
3625 }
3626
3627 /*
3628  * Fetch AUX CH registers 0x202 - 0x207 which contain
3629  * link status information
3630  */
3631 bool
3632 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3633 {
3634         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3635                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3636 }
3637
3638 /* These are source-specific values. */
3639 u8
3640 intel_dp_voltage_max(struct intel_dp *intel_dp)
3641 {
3642         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3643         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3644         enum port port = encoder->port;
3645
3646         if (HAS_DDI(dev_priv))
3647                 return intel_ddi_dp_voltage_max(encoder);
3648         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3649                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3650         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3651                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3652         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3653                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3654         else
3655                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3656 }
3657
3658 u8
3659 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3660 {
3661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3662         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3663         enum port port = encoder->port;
3664
3665         if (HAS_DDI(dev_priv)) {
3666                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3667         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3668                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3669                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3670                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3671                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3672                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3673                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3674                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3675                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3676                 default:
3677                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3678                 }
3679         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3680                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3681                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3682                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3683                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3684                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3685                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3686                 default:
3687                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3688                 }
3689         } else {
3690                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3691                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3692                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3693                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3694                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3695                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3696                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3697                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3698                 default:
3699                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3700                 }
3701         }
3702 }
3703
3704 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3705 {
3706         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3707         unsigned long demph_reg_value, preemph_reg_value,
3708                 uniqtranscale_reg_value;
3709         u8 train_set = intel_dp->train_set[0];
3710
3711         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3712         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3713                 preemph_reg_value = 0x0004000;
3714                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3716                         demph_reg_value = 0x2B405555;
3717                         uniqtranscale_reg_value = 0x552AB83A;
3718                         break;
3719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3720                         demph_reg_value = 0x2B404040;
3721                         uniqtranscale_reg_value = 0x5548B83A;
3722                         break;
3723                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3724                         demph_reg_value = 0x2B245555;
3725                         uniqtranscale_reg_value = 0x5560B83A;
3726                         break;
3727                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3728                         demph_reg_value = 0x2B405555;
3729                         uniqtranscale_reg_value = 0x5598DA3A;
3730                         break;
3731                 default:
3732                         return 0;
3733                 }
3734                 break;
3735         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3736                 preemph_reg_value = 0x0002000;
3737                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3738                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3739                         demph_reg_value = 0x2B404040;
3740                         uniqtranscale_reg_value = 0x5552B83A;
3741                         break;
3742                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3743                         demph_reg_value = 0x2B404848;
3744                         uniqtranscale_reg_value = 0x5580B83A;
3745                         break;
3746                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3747                         demph_reg_value = 0x2B404040;
3748                         uniqtranscale_reg_value = 0x55ADDA3A;
3749                         break;
3750                 default:
3751                         return 0;
3752                 }
3753                 break;
3754         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3755                 preemph_reg_value = 0x0000000;
3756                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3757                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3758                         demph_reg_value = 0x2B305555;
3759                         uniqtranscale_reg_value = 0x5570B83A;
3760                         break;
3761                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3762                         demph_reg_value = 0x2B2B4040;
3763                         uniqtranscale_reg_value = 0x55ADDA3A;
3764                         break;
3765                 default:
3766                         return 0;
3767                 }
3768                 break;
3769         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3770                 preemph_reg_value = 0x0006000;
3771                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3772                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3773                         demph_reg_value = 0x1B405555;
3774                         uniqtranscale_reg_value = 0x55ADDA3A;
3775                         break;
3776                 default:
3777                         return 0;
3778                 }
3779                 break;
3780         default:
3781                 return 0;
3782         }
3783
3784         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3785                                  uniqtranscale_reg_value, 0);
3786
3787         return 0;
3788 }
3789
3790 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3791 {
3792         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3793         u32 deemph_reg_value, margin_reg_value;
3794         bool uniq_trans_scale = false;
3795         u8 train_set = intel_dp->train_set[0];
3796
3797         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3798         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3799                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3800                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3801                         deemph_reg_value = 128;
3802                         margin_reg_value = 52;
3803                         break;
3804                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3805                         deemph_reg_value = 128;
3806                         margin_reg_value = 77;
3807                         break;
3808                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3809                         deemph_reg_value = 128;
3810                         margin_reg_value = 102;
3811                         break;
3812                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3813                         deemph_reg_value = 128;
3814                         margin_reg_value = 154;
3815                         uniq_trans_scale = true;
3816                         break;
3817                 default:
3818                         return 0;
3819                 }
3820                 break;
3821         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3822                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3823                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3824                         deemph_reg_value = 85;
3825                         margin_reg_value = 78;
3826                         break;
3827                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3828                         deemph_reg_value = 85;
3829                         margin_reg_value = 116;
3830                         break;
3831                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3832                         deemph_reg_value = 85;
3833                         margin_reg_value = 154;
3834                         break;
3835                 default:
3836                         return 0;
3837                 }
3838                 break;
3839         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3840                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3841                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3842                         deemph_reg_value = 64;
3843                         margin_reg_value = 104;
3844                         break;
3845                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3846                         deemph_reg_value = 64;
3847                         margin_reg_value = 154;
3848                         break;
3849                 default:
3850                         return 0;
3851                 }
3852                 break;
3853         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3854                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3855                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3856                         deemph_reg_value = 43;
3857                         margin_reg_value = 154;
3858                         break;
3859                 default:
3860                         return 0;
3861                 }
3862                 break;
3863         default:
3864                 return 0;
3865         }
3866
3867         chv_set_phy_signal_level(encoder, deemph_reg_value,
3868                                  margin_reg_value, uniq_trans_scale);
3869
3870         return 0;
3871 }
3872
3873 static u32
3874 g4x_signal_levels(u8 train_set)
3875 {
3876         u32 signal_levels = 0;
3877
3878         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3879         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3880         default:
3881                 signal_levels |= DP_VOLTAGE_0_4;
3882                 break;
3883         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3884                 signal_levels |= DP_VOLTAGE_0_6;
3885                 break;
3886         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3887                 signal_levels |= DP_VOLTAGE_0_8;
3888                 break;
3889         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3890                 signal_levels |= DP_VOLTAGE_1_2;
3891                 break;
3892         }
3893         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3894         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3895         default:
3896                 signal_levels |= DP_PRE_EMPHASIS_0;
3897                 break;
3898         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3899                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3900                 break;
3901         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3902                 signal_levels |= DP_PRE_EMPHASIS_6;
3903                 break;
3904         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3905                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3906                 break;
3907         }
3908         return signal_levels;
3909 }
3910
3911 /* SNB CPU eDP voltage swing and pre-emphasis control */
3912 static u32
3913 snb_cpu_edp_signal_levels(u8 train_set)
3914 {
3915         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3916                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3917         switch (signal_levels) {
3918         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3919         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3920                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3921         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3922                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3923         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3924         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3925                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3926         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3927         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3928                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3929         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3930         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3931                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3932         default:
3933                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3934                               "0x%x\n", signal_levels);
3935                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3936         }
3937 }
3938
3939 /* IVB CPU eDP voltage swing and pre-emphasis control */
3940 static u32
3941 ivb_cpu_edp_signal_levels(u8 train_set)
3942 {
3943         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3944                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3945         switch (signal_levels) {
3946         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3947                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3948         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3949                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3950         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3951                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3952
3953         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3954                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3955         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3956                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3957
3958         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3959                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3960         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3961                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3962
3963         default:
3964                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3965                               "0x%x\n", signal_levels);
3966                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3967         }
3968 }
3969
3970 void
3971 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3972 {
3973         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3974         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3975         enum port port = intel_dig_port->base.port;
3976         u32 signal_levels, mask = 0;
3977         u8 train_set = intel_dp->train_set[0];
3978
3979         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3980                 signal_levels = bxt_signal_levels(intel_dp);
3981         } else if (HAS_DDI(dev_priv)) {
3982                 signal_levels = ddi_signal_levels(intel_dp);
3983                 mask = DDI_BUF_EMP_MASK;
3984         } else if (IS_CHERRYVIEW(dev_priv)) {
3985                 signal_levels = chv_signal_levels(intel_dp);
3986         } else if (IS_VALLEYVIEW(dev_priv)) {
3987                 signal_levels = vlv_signal_levels(intel_dp);
3988         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3989                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3990                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3991         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3992                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3993                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3994         } else {
3995                 signal_levels = g4x_signal_levels(train_set);
3996                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3997         }
3998
3999         if (mask)
4000                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4001
4002         DRM_DEBUG_KMS("Using vswing level %d\n",
4003                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4004         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4005                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4006                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
4007
4008         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4009
4010         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4011         POSTING_READ(intel_dp->output_reg);
4012 }
4013
4014 void
4015 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4016                                        u8 dp_train_pat)
4017 {
4018         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4019         struct drm_i915_private *dev_priv =
4020                 to_i915(intel_dig_port->base.base.dev);
4021
4022         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4023
4024         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4025         POSTING_READ(intel_dp->output_reg);
4026 }
4027
4028 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4029 {
4030         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4031         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4032         enum port port = intel_dig_port->base.port;
4033         u32 val;
4034
4035         if (!HAS_DDI(dev_priv))
4036                 return;
4037
4038         val = I915_READ(DP_TP_CTL(port));
4039         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4040         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4041         I915_WRITE(DP_TP_CTL(port), val);
4042
4043         /*
4044          * On PORT_A we can have only eDP in SST mode. There the only reason
4045          * we need to set idle transmission mode is to work around a HW issue
4046          * where we enable the pipe while not in idle link-training mode.
4047          * In this case there is requirement to wait for a minimum number of
4048          * idle patterns to be sent.
4049          */
4050         if (port == PORT_A)
4051                 return;
4052
4053         if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
4054                                   DP_TP_STATUS_IDLE_DONE, 1))
4055                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4056 }
4057
4058 static void
4059 intel_dp_link_down(struct intel_encoder *encoder,
4060                    const struct intel_crtc_state *old_crtc_state)
4061 {
4062         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4063         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4064         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4065         enum port port = encoder->port;
4066         u32 DP = intel_dp->DP;
4067
4068         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4069                 return;
4070
4071         DRM_DEBUG_KMS("\n");
4072
4073         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4074             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4075                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4076                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4077         } else {
4078                 DP &= ~DP_LINK_TRAIN_MASK;
4079                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4080         }
4081         I915_WRITE(intel_dp->output_reg, DP);
4082         POSTING_READ(intel_dp->output_reg);
4083
4084         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4085         I915_WRITE(intel_dp->output_reg, DP);
4086         POSTING_READ(intel_dp->output_reg);
4087
4088         /*
4089          * HW workaround for IBX, we need to move the port
4090          * to transcoder A after disabling it to allow the
4091          * matching HDMI port to be enabled on transcoder A.
4092          */
4093         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4094                 /*
4095                  * We get CPU/PCH FIFO underruns on the other pipe when
4096                  * doing the workaround. Sweep them under the rug.
4097                  */
4098                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4099                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4100
4101                 /* always enable with pattern 1 (as per spec) */
4102                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4103                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4104                         DP_LINK_TRAIN_PAT_1;
4105                 I915_WRITE(intel_dp->output_reg, DP);
4106                 POSTING_READ(intel_dp->output_reg);
4107
4108                 DP &= ~DP_PORT_EN;
4109                 I915_WRITE(intel_dp->output_reg, DP);
4110                 POSTING_READ(intel_dp->output_reg);
4111
4112                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4113                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4114                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4115         }
4116
4117         msleep(intel_dp->panel_power_down_delay);
4118
4119         intel_dp->DP = DP;
4120
4121         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4122                 intel_wakeref_t wakeref;
4123
4124                 with_pps_lock(intel_dp, wakeref)
4125                         intel_dp->active_pipe = INVALID_PIPE;
4126         }
4127 }
4128
4129 static void
4130 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4131 {
4132         u8 dpcd_ext[6];
4133
4134         /*
4135          * Prior to DP1.3 the bit represented by
4136          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4137          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4138          * the true capability of the panel. The only way to check is to
4139          * then compare 0000h and 2200h.
4140          */
4141         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4142               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4143                 return;
4144
4145         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4146                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4147                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4148                 return;
4149         }
4150
4151         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4152                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4153                 return;
4154         }
4155
4156         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4157                 return;
4158
4159         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4160                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4161
4162         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4163 }
4164
4165 bool
4166 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4167 {
4168         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4169                              sizeof(intel_dp->dpcd)) < 0)
4170                 return false; /* aux transfer failed */
4171
4172         intel_dp_extended_receiver_capabilities(intel_dp);
4173
4174         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4175
4176         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4177 }
4178
4179 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4180 {
4181         u8 dprx = 0;
4182
4183         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4184                               &dprx) != 1)
4185                 return false;
4186         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4187 }
4188
4189 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4190 {
4191         /*
4192          * Clear the cached register set to avoid using stale values
4193          * for the sinks that do not support DSC.
4194          */
4195         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4196
4197         /* Clear fec_capable to avoid using stale values */
4198         intel_dp->fec_capable = 0;
4199
4200         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4201         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4202             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4203                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4204                                      intel_dp->dsc_dpcd,
4205                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4206                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4207                                   DP_DSC_SUPPORT);
4208
4209                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4210                               (int)sizeof(intel_dp->dsc_dpcd),
4211                               intel_dp->dsc_dpcd);
4212
4213                 /* FEC is supported only on DP 1.4 */
4214                 if (!intel_dp_is_edp(intel_dp) &&
4215                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4216                                       &intel_dp->fec_capable) < 0)
4217                         DRM_ERROR("Failed to read FEC DPCD register\n");
4218
4219                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4220         }
4221 }
4222
4223 static bool
4224 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4225 {
4226         struct drm_i915_private *dev_priv =
4227                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4228
4229         /* this function is meant to be called only once */
4230         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4231
4232         if (!intel_dp_read_dpcd(intel_dp))
4233                 return false;
4234
4235         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4236                          drm_dp_is_branch(intel_dp->dpcd));
4237
4238         /*
4239          * Read the eDP display control registers.
4240          *
4241          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4242          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4243          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4244          * method). The display control registers should read zero if they're
4245          * not supported anyway.
4246          */
4247         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4248                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4249                              sizeof(intel_dp->edp_dpcd))
4250                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4251                               intel_dp->edp_dpcd);
4252
4253         /*
4254          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4255          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4256          */
4257         intel_psr_init_dpcd(intel_dp);
4258
4259         /* Read the eDP 1.4+ supported link rates. */
4260         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4261                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4262                 int i;
4263
4264                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4265                                 sink_rates, sizeof(sink_rates));
4266
4267                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4268                         int val = le16_to_cpu(sink_rates[i]);
4269
4270                         if (val == 0)
4271                                 break;
4272
4273                         /* Value read multiplied by 200kHz gives the per-lane
4274                          * link rate in kHz. The source rates are, however,
4275                          * stored in terms of LS_Clk kHz. The full conversion
4276                          * back to symbols is
4277                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4278                          */
4279                         intel_dp->sink_rates[i] = (val * 200) / 10;
4280                 }
4281                 intel_dp->num_sink_rates = i;
4282         }
4283
4284         /*
4285          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4286          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4287          */
4288         if (intel_dp->num_sink_rates)
4289                 intel_dp->use_rate_select = true;
4290         else
4291                 intel_dp_set_sink_rates(intel_dp);
4292
4293         intel_dp_set_common_rates(intel_dp);
4294
4295         /* Read the eDP DSC DPCD registers */
4296         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4297                 intel_dp_get_dsc_sink_cap(intel_dp);
4298
4299         return true;
4300 }
4301
4302
4303 static bool
4304 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4305 {
4306         if (!intel_dp_read_dpcd(intel_dp))
4307                 return false;
4308
4309         /*
4310          * Don't clobber cached eDP rates. Also skip re-reading
4311          * the OUI/ID since we know it won't change.
4312          */
4313         if (!intel_dp_is_edp(intel_dp)) {
4314                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4315                                  drm_dp_is_branch(intel_dp->dpcd));
4316
4317                 intel_dp_set_sink_rates(intel_dp);
4318                 intel_dp_set_common_rates(intel_dp);
4319         }
4320
4321         /*
4322          * Some eDP panels do not set a valid value for sink count, that is why
4323          * it don't care about read it here and in intel_edp_init_dpcd().
4324          */
4325         if (!intel_dp_is_edp(intel_dp) &&
4326             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4327                 u8 count;
4328                 ssize_t r;
4329
4330                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4331                 if (r < 1)
4332                         return false;
4333
4334                 /*
4335                  * Sink count can change between short pulse hpd hence
4336                  * a member variable in intel_dp will track any changes
4337                  * between short pulse interrupts.
4338                  */
4339                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4340
4341                 /*
4342                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4343                  * a dongle is present but no display. Unless we require to know
4344                  * if a dongle is present or not, we don't need to update
4345                  * downstream port information. So, an early return here saves
4346                  * time from performing other operations which are not required.
4347                  */
4348                 if (!intel_dp->sink_count)
4349                         return false;
4350         }
4351
4352         if (!drm_dp_is_branch(intel_dp->dpcd))
4353                 return true; /* native DP sink */
4354
4355         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4356                 return true; /* no per-port downstream info */
4357
4358         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4359                              intel_dp->downstream_ports,
4360                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4361                 return false; /* downstream port status fetch failed */
4362
4363         return true;
4364 }
4365
4366 static bool
4367 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4368 {
4369         u8 mstm_cap;
4370
4371         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4372                 return false;
4373
4374         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4375                 return false;
4376
4377         return mstm_cap & DP_MST_CAP;
4378 }
4379
4380 static bool
4381 intel_dp_can_mst(struct intel_dp *intel_dp)
4382 {
4383         return i915_modparams.enable_dp_mst &&
4384                 intel_dp->can_mst &&
4385                 intel_dp_sink_can_mst(intel_dp);
4386 }
4387
4388 static void
4389 intel_dp_configure_mst(struct intel_dp *intel_dp)
4390 {
4391         struct intel_encoder *encoder =
4392                 &dp_to_dig_port(intel_dp)->base;
4393         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4394
4395         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4396                       port_name(encoder->port), yesno(intel_dp->can_mst),
4397                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4398
4399         if (!intel_dp->can_mst)
4400                 return;
4401
4402         intel_dp->is_mst = sink_can_mst &&
4403                 i915_modparams.enable_dp_mst;
4404
4405         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4406                                         intel_dp->is_mst);
4407 }
4408
4409 static bool
4410 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4411 {
4412         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4413                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4414                 DP_DPRX_ESI_LEN;
4415 }
4416
4417 static void
4418 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
4419                                const struct intel_crtc_state *crtc_state)
4420 {
4421         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4422         struct dp_sdp vsc_sdp = {};
4423
4424         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4425         vsc_sdp.sdp_header.HB0 = 0;
4426         vsc_sdp.sdp_header.HB1 = 0x7;
4427
4428         /*
4429          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4430          * Colorimetry Format indication.
4431          */
4432         vsc_sdp.sdp_header.HB2 = 0x5;
4433
4434         /*
4435          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4436          * Colorimetry Format indication (HB2 = 05h).
4437          */
4438         vsc_sdp.sdp_header.HB3 = 0x13;
4439
4440         /*
4441          * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
4442          * DB16[3:0] DP 1.4a spec, Table 2-120
4443          */
4444         vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
4445         /* RGB->YCBCR color conversion uses the BT.709 color space. */
4446         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4447
4448         /*
4449          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4450          * the following Component Bit Depth values are defined:
4451          * 001b = 8bpc.
4452          * 010b = 10bpc.
4453          * 011b = 12bpc.
4454          * 100b = 16bpc.
4455          */
4456         switch (crtc_state->pipe_bpp) {
4457         case 24: /* 8bpc */
4458                 vsc_sdp.db[17] = 0x1;
4459                 break;
4460         case 30: /* 10bpc */
4461                 vsc_sdp.db[17] = 0x2;
4462                 break;
4463         case 36: /* 12bpc */
4464                 vsc_sdp.db[17] = 0x3;
4465                 break;
4466         case 48: /* 16bpc */
4467                 vsc_sdp.db[17] = 0x4;
4468                 break;
4469         default:
4470                 MISSING_CASE(crtc_state->pipe_bpp);
4471                 break;
4472         }
4473
4474         /*
4475          * Dynamic Range (Bit 7)
4476          * 0 = VESA range, 1 = CTA range.
4477          * all YCbCr are always limited range
4478          */
4479         vsc_sdp.db[17] |= 0x80;
4480
4481         /*
4482          * Content Type (Bits 2:0)
4483          * 000b = Not defined.
4484          * 001b = Graphics.
4485          * 010b = Photo.
4486          * 011b = Video.
4487          * 100b = Game
4488          * All other values are RESERVED.
4489          * Note: See CTA-861-G for the definition and expected
4490          * processing by a stream sink for the above contect types.
4491          */
4492         vsc_sdp.db[18] = 0;
4493
4494         intel_dig_port->write_infoframe(&intel_dig_port->base,
4495                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4496 }
4497
4498 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
4499                                const struct intel_crtc_state *crtc_state)
4500 {
4501         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
4502                 return;
4503
4504         intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
4505 }
4506
4507 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4508 {
4509         int status = 0;
4510         int test_link_rate;
4511         u8 test_lane_count, test_link_bw;
4512         /* (DP CTS 1.2)
4513          * 4.3.1.11
4514          */
4515         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4516         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4517                                    &test_lane_count);
4518
4519         if (status <= 0) {
4520                 DRM_DEBUG_KMS("Lane count read failed\n");
4521                 return DP_TEST_NAK;
4522         }
4523         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4524
4525         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4526                                    &test_link_bw);
4527         if (status <= 0) {
4528                 DRM_DEBUG_KMS("Link Rate read failed\n");
4529                 return DP_TEST_NAK;
4530         }
4531         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4532
4533         /* Validate the requested link rate and lane count */
4534         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4535                                         test_lane_count))
4536                 return DP_TEST_NAK;
4537
4538         intel_dp->compliance.test_lane_count = test_lane_count;
4539         intel_dp->compliance.test_link_rate = test_link_rate;
4540
4541         return DP_TEST_ACK;
4542 }
4543
4544 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4545 {
4546         u8 test_pattern;
4547         u8 test_misc;
4548         __be16 h_width, v_height;
4549         int status = 0;
4550
4551         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4552         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4553                                    &test_pattern);
4554         if (status <= 0) {
4555                 DRM_DEBUG_KMS("Test pattern read failed\n");
4556                 return DP_TEST_NAK;
4557         }
4558         if (test_pattern != DP_COLOR_RAMP)
4559                 return DP_TEST_NAK;
4560
4561         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4562                                   &h_width, 2);
4563         if (status <= 0) {
4564                 DRM_DEBUG_KMS("H Width read failed\n");
4565                 return DP_TEST_NAK;
4566         }
4567
4568         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4569                                   &v_height, 2);
4570         if (status <= 0) {
4571                 DRM_DEBUG_KMS("V Height read failed\n");
4572                 return DP_TEST_NAK;
4573         }
4574
4575         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4576                                    &test_misc);
4577         if (status <= 0) {
4578                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4579                 return DP_TEST_NAK;
4580         }
4581         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4582                 return DP_TEST_NAK;
4583         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4584                 return DP_TEST_NAK;
4585         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4586         case DP_TEST_BIT_DEPTH_6:
4587                 intel_dp->compliance.test_data.bpc = 6;
4588                 break;
4589         case DP_TEST_BIT_DEPTH_8:
4590                 intel_dp->compliance.test_data.bpc = 8;
4591                 break;
4592         default:
4593                 return DP_TEST_NAK;
4594         }
4595
4596         intel_dp->compliance.test_data.video_pattern = test_pattern;
4597         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4598         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4599         /* Set test active flag here so userspace doesn't interrupt things */
4600         intel_dp->compliance.test_active = 1;
4601
4602         return DP_TEST_ACK;
4603 }
4604
4605 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4606 {
4607         u8 test_result = DP_TEST_ACK;
4608         struct intel_connector *intel_connector = intel_dp->attached_connector;
4609         struct drm_connector *connector = &intel_connector->base;
4610
4611         if (intel_connector->detect_edid == NULL ||
4612             connector->edid_corrupt ||
4613             intel_dp->aux.i2c_defer_count > 6) {
4614                 /* Check EDID read for NACKs, DEFERs and corruption
4615                  * (DP CTS 1.2 Core r1.1)
4616                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4617                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4618                  *    4.2.2.6 : EDID corruption detected
4619                  * Use failsafe mode for all cases
4620                  */
4621                 if (intel_dp->aux.i2c_nack_count > 0 ||
4622                         intel_dp->aux.i2c_defer_count > 0)
4623                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4624                                       intel_dp->aux.i2c_nack_count,
4625                                       intel_dp->aux.i2c_defer_count);
4626                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4627         } else {
4628                 struct edid *block = intel_connector->detect_edid;
4629
4630                 /* We have to write the checksum
4631                  * of the last block read
4632                  */
4633                 block += intel_connector->detect_edid->extensions;
4634
4635                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4636                                        block->checksum) <= 0)
4637                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4638
4639                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4640                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4641         }
4642
4643         /* Set test active flag here so userspace doesn't interrupt things */
4644         intel_dp->compliance.test_active = 1;
4645
4646         return test_result;
4647 }
4648
4649 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4650 {
4651         u8 test_result = DP_TEST_NAK;
4652         return test_result;
4653 }
4654
4655 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4656 {
4657         u8 response = DP_TEST_NAK;
4658         u8 request = 0;
4659         int status;
4660
4661         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4662         if (status <= 0) {
4663                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4664                 goto update_status;
4665         }
4666
4667         switch (request) {
4668         case DP_TEST_LINK_TRAINING:
4669                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4670                 response = intel_dp_autotest_link_training(intel_dp);
4671                 break;
4672         case DP_TEST_LINK_VIDEO_PATTERN:
4673                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4674                 response = intel_dp_autotest_video_pattern(intel_dp);
4675                 break;
4676         case DP_TEST_LINK_EDID_READ:
4677                 DRM_DEBUG_KMS("EDID test requested\n");
4678                 response = intel_dp_autotest_edid(intel_dp);
4679                 break;
4680         case DP_TEST_LINK_PHY_TEST_PATTERN:
4681                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4682                 response = intel_dp_autotest_phy_pattern(intel_dp);
4683                 break;
4684         default:
4685                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4686                 break;
4687         }
4688
4689         if (response & DP_TEST_ACK)
4690                 intel_dp->compliance.test_type = request;
4691
4692 update_status:
4693         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4694         if (status <= 0)
4695                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4696 }
4697
4698 static int
4699 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4700 {
4701         bool bret;
4702
4703         if (intel_dp->is_mst) {
4704                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4705                 int ret = 0;
4706                 int retry;
4707                 bool handled;
4708
4709                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4710                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4711 go_again:
4712                 if (bret == true) {
4713
4714                         /* check link status - esi[10] = 0x200c */
4715                         if (intel_dp->active_mst_links > 0 &&
4716                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4717                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4718                                 intel_dp_start_link_train(intel_dp);
4719                                 intel_dp_stop_link_train(intel_dp);
4720                         }
4721
4722                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4723                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4724
4725                         if (handled) {
4726                                 for (retry = 0; retry < 3; retry++) {
4727                                         int wret;
4728                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4729                                                                  DP_SINK_COUNT_ESI+1,
4730                                                                  &esi[1], 3);
4731                                         if (wret == 3) {
4732                                                 break;
4733                                         }
4734                                 }
4735
4736                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4737                                 if (bret == true) {
4738                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4739                                         goto go_again;
4740                                 }
4741                         } else
4742                                 ret = 0;
4743
4744                         return ret;
4745                 } else {
4746                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4747                         intel_dp->is_mst = false;
4748                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4749                                                         intel_dp->is_mst);
4750                 }
4751         }
4752         return -EINVAL;
4753 }
4754
4755 static bool
4756 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4757 {
4758         u8 link_status[DP_LINK_STATUS_SIZE];
4759
4760         if (!intel_dp->link_trained)
4761                 return false;
4762
4763         /*
4764          * While PSR source HW is enabled, it will control main-link sending
4765          * frames, enabling and disabling it so trying to do a retrain will fail
4766          * as the link would or not be on or it could mix training patterns
4767          * and frame data at the same time causing retrain to fail.
4768          * Also when exiting PSR, HW will retrain the link anyways fixing
4769          * any link status error.
4770          */
4771         if (intel_psr_enabled(intel_dp))
4772                 return false;
4773
4774         if (!intel_dp_get_link_status(intel_dp, link_status))
4775                 return false;
4776
4777         /*
4778          * Validate the cached values of intel_dp->link_rate and
4779          * intel_dp->lane_count before attempting to retrain.
4780          */
4781         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4782                                         intel_dp->lane_count))
4783                 return false;
4784
4785         /* Retrain if Channel EQ or CR not ok */
4786         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4787 }
4788
4789 int intel_dp_retrain_link(struct intel_encoder *encoder,
4790                           struct drm_modeset_acquire_ctx *ctx)
4791 {
4792         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4793         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4794         struct intel_connector *connector = intel_dp->attached_connector;
4795         struct drm_connector_state *conn_state;
4796         struct intel_crtc_state *crtc_state;
4797         struct intel_crtc *crtc;
4798         int ret;
4799
4800         /* FIXME handle the MST connectors as well */
4801
4802         if (!connector || connector->base.status != connector_status_connected)
4803                 return 0;
4804
4805         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4806                                ctx);
4807         if (ret)
4808                 return ret;
4809
4810         conn_state = connector->base.state;
4811
4812         crtc = to_intel_crtc(conn_state->crtc);
4813         if (!crtc)
4814                 return 0;
4815
4816         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4817         if (ret)
4818                 return ret;
4819
4820         crtc_state = to_intel_crtc_state(crtc->base.state);
4821
4822         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4823
4824         if (!crtc_state->base.active)
4825                 return 0;
4826
4827         if (conn_state->commit &&
4828             !try_wait_for_completion(&conn_state->commit->hw_done))
4829                 return 0;
4830
4831         if (!intel_dp_needs_link_retrain(intel_dp))
4832                 return 0;
4833
4834         /* Suppress underruns caused by re-training */
4835         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4836         if (crtc_state->has_pch_encoder)
4837                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4838                                                       intel_crtc_pch_transcoder(crtc), false);
4839
4840         intel_dp_start_link_train(intel_dp);
4841         intel_dp_stop_link_train(intel_dp);
4842
4843         /* Keep underrun reporting disabled until things are stable */
4844         intel_wait_for_vblank(dev_priv, crtc->pipe);
4845
4846         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4847         if (crtc_state->has_pch_encoder)
4848                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4849                                                       intel_crtc_pch_transcoder(crtc), true);
4850
4851         return 0;
4852 }
4853
4854 /*
4855  * If display is now connected check links status,
4856  * there has been known issues of link loss triggering
4857  * long pulse.
4858  *
4859  * Some sinks (eg. ASUS PB287Q) seem to perform some
4860  * weird HPD ping pong during modesets. So we can apparently
4861  * end up with HPD going low during a modeset, and then
4862  * going back up soon after. And once that happens we must
4863  * retrain the link to get a picture. That's in case no
4864  * userspace component reacted to intermittent HPD dip.
4865  */
4866 static enum intel_hotplug_state
4867 intel_dp_hotplug(struct intel_encoder *encoder,
4868                  struct intel_connector *connector,
4869                  bool irq_received)
4870 {
4871         struct drm_modeset_acquire_ctx ctx;
4872         enum intel_hotplug_state state;
4873         int ret;
4874
4875         state = intel_encoder_hotplug(encoder, connector, irq_received);
4876
4877         drm_modeset_acquire_init(&ctx, 0);
4878
4879         for (;;) {
4880                 ret = intel_dp_retrain_link(encoder, &ctx);
4881
4882                 if (ret == -EDEADLK) {
4883                         drm_modeset_backoff(&ctx);
4884                         continue;
4885                 }
4886
4887                 break;
4888         }
4889
4890         drm_modeset_drop_locks(&ctx);
4891         drm_modeset_acquire_fini(&ctx);
4892         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4893
4894         /*
4895          * Keeping it consistent with intel_ddi_hotplug() and
4896          * intel_hdmi_hotplug().
4897          */
4898         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
4899                 state = INTEL_HOTPLUG_RETRY;
4900
4901         return state;
4902 }
4903
4904 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4905 {
4906         u8 val;
4907
4908         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4909                 return;
4910
4911         if (drm_dp_dpcd_readb(&intel_dp->aux,
4912                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4913                 return;
4914
4915         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4916
4917         if (val & DP_AUTOMATED_TEST_REQUEST)
4918                 intel_dp_handle_test_request(intel_dp);
4919
4920         if (val & DP_CP_IRQ)
4921                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4922
4923         if (val & DP_SINK_SPECIFIC_IRQ)
4924                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4925 }
4926
4927 /*
4928  * According to DP spec
4929  * 5.1.2:
4930  *  1. Read DPCD
4931  *  2. Configure link according to Receiver Capabilities
4932  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4933  *  4. Check link status on receipt of hot-plug interrupt
4934  *
4935  * intel_dp_short_pulse -  handles short pulse interrupts
4936  * when full detection is not required.
4937  * Returns %true if short pulse is handled and full detection
4938  * is NOT required and %false otherwise.
4939  */
4940 static bool
4941 intel_dp_short_pulse(struct intel_dp *intel_dp)
4942 {
4943         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4944         u8 old_sink_count = intel_dp->sink_count;
4945         bool ret;
4946
4947         /*
4948          * Clearing compliance test variables to allow capturing
4949          * of values for next automated test request.
4950          */
4951         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4952
4953         /*
4954          * Now read the DPCD to see if it's actually running
4955          * If the current value of sink count doesn't match with
4956          * the value that was stored earlier or dpcd read failed
4957          * we need to do full detection
4958          */
4959         ret = intel_dp_get_dpcd(intel_dp);
4960
4961         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4962                 /* No need to proceed if we are going to do full detect */
4963                 return false;
4964         }
4965
4966         intel_dp_check_service_irq(intel_dp);
4967
4968         /* Handle CEC interrupts, if any */
4969         drm_dp_cec_irq(&intel_dp->aux);
4970
4971         /* defer to the hotplug work for link retraining if needed */
4972         if (intel_dp_needs_link_retrain(intel_dp))
4973                 return false;
4974
4975         intel_psr_short_pulse(intel_dp);
4976
4977         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4978                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4979                 /* Send a Hotplug Uevent to userspace to start modeset */
4980                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4981         }
4982
4983         return true;
4984 }
4985
4986 /* XXX this is probably wrong for multiple downstream ports */
4987 static enum drm_connector_status
4988 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4989 {
4990         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4991         u8 *dpcd = intel_dp->dpcd;
4992         u8 type;
4993
4994         if (WARN_ON(intel_dp_is_edp(intel_dp)))
4995                 return connector_status_connected;
4996
4997         if (lspcon->active)
4998                 lspcon_resume(lspcon);
4999
5000         if (!intel_dp_get_dpcd(intel_dp))
5001                 return connector_status_disconnected;
5002
5003         /* if there's no downstream port, we're done */
5004         if (!drm_dp_is_branch(dpcd))
5005                 return connector_status_connected;
5006
5007         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5008         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5009             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5010
5011                 return intel_dp->sink_count ?
5012                 connector_status_connected : connector_status_disconnected;
5013         }
5014
5015         if (intel_dp_can_mst(intel_dp))
5016                 return connector_status_connected;
5017
5018         /* If no HPD, poke DDC gently */
5019         if (drm_probe_ddc(&intel_dp->aux.ddc))
5020                 return connector_status_connected;
5021
5022         /* Well we tried, say unknown for unreliable port types */
5023         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5024                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5025                 if (type == DP_DS_PORT_TYPE_VGA ||
5026                     type == DP_DS_PORT_TYPE_NON_EDID)
5027                         return connector_status_unknown;
5028         } else {
5029                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5030                         DP_DWN_STRM_PORT_TYPE_MASK;
5031                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5032                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5033                         return connector_status_unknown;
5034         }
5035
5036         /* Anything else is out of spec, warn and ignore */
5037         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5038         return connector_status_disconnected;
5039 }
5040
5041 static enum drm_connector_status
5042 edp_detect(struct intel_dp *intel_dp)
5043 {
5044         return connector_status_connected;
5045 }
5046
5047 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5048 {
5049         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5050         u32 bit;
5051
5052         switch (encoder->hpd_pin) {
5053         case HPD_PORT_B:
5054                 bit = SDE_PORTB_HOTPLUG;
5055                 break;
5056         case HPD_PORT_C:
5057                 bit = SDE_PORTC_HOTPLUG;
5058                 break;
5059         case HPD_PORT_D:
5060                 bit = SDE_PORTD_HOTPLUG;
5061                 break;
5062         default:
5063                 MISSING_CASE(encoder->hpd_pin);
5064                 return false;
5065         }
5066
5067         return I915_READ(SDEISR) & bit;
5068 }
5069
5070 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5071 {
5072         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5073         u32 bit;
5074
5075         switch (encoder->hpd_pin) {
5076         case HPD_PORT_B:
5077                 bit = SDE_PORTB_HOTPLUG_CPT;
5078                 break;
5079         case HPD_PORT_C:
5080                 bit = SDE_PORTC_HOTPLUG_CPT;
5081                 break;
5082         case HPD_PORT_D:
5083                 bit = SDE_PORTD_HOTPLUG_CPT;
5084                 break;
5085         default:
5086                 MISSING_CASE(encoder->hpd_pin);
5087                 return false;
5088         }
5089
5090         return I915_READ(SDEISR) & bit;
5091 }
5092
5093 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5094 {
5095         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5096         u32 bit;
5097
5098         switch (encoder->hpd_pin) {
5099         case HPD_PORT_A:
5100                 bit = SDE_PORTA_HOTPLUG_SPT;
5101                 break;
5102         case HPD_PORT_E:
5103                 bit = SDE_PORTE_HOTPLUG_SPT;
5104                 break;
5105         default:
5106                 return cpt_digital_port_connected(encoder);
5107         }
5108
5109         return I915_READ(SDEISR) & bit;
5110 }
5111
5112 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5113 {
5114         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5115         u32 bit;
5116
5117         switch (encoder->hpd_pin) {
5118         case HPD_PORT_B:
5119                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5120                 break;
5121         case HPD_PORT_C:
5122                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5123                 break;
5124         case HPD_PORT_D:
5125                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5126                 break;
5127         default:
5128                 MISSING_CASE(encoder->hpd_pin);
5129                 return false;
5130         }
5131
5132         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5133 }
5134
5135 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5136 {
5137         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5138         u32 bit;
5139
5140         switch (encoder->hpd_pin) {
5141         case HPD_PORT_B:
5142                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5143                 break;
5144         case HPD_PORT_C:
5145                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5146                 break;
5147         case HPD_PORT_D:
5148                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5149                 break;
5150         default:
5151                 MISSING_CASE(encoder->hpd_pin);
5152                 return false;
5153         }
5154
5155         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5156 }
5157
5158 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5159 {
5160         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5161
5162         if (encoder->hpd_pin == HPD_PORT_A)
5163                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5164         else
5165                 return ibx_digital_port_connected(encoder);
5166 }
5167
5168 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5169 {
5170         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5171
5172         if (encoder->hpd_pin == HPD_PORT_A)
5173                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5174         else
5175                 return cpt_digital_port_connected(encoder);
5176 }
5177
5178 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5179 {
5180         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5181
5182         if (encoder->hpd_pin == HPD_PORT_A)
5183                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5184         else
5185                 return cpt_digital_port_connected(encoder);
5186 }
5187
5188 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5189 {
5190         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5191
5192         if (encoder->hpd_pin == HPD_PORT_A)
5193                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5194         else
5195                 return cpt_digital_port_connected(encoder);
5196 }
5197
5198 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5199 {
5200         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5201         u32 bit;
5202
5203         switch (encoder->hpd_pin) {
5204         case HPD_PORT_A:
5205                 bit = BXT_DE_PORT_HP_DDIA;
5206                 break;
5207         case HPD_PORT_B:
5208                 bit = BXT_DE_PORT_HP_DDIB;
5209                 break;
5210         case HPD_PORT_C:
5211                 bit = BXT_DE_PORT_HP_DDIC;
5212                 break;
5213         default:
5214                 MISSING_CASE(encoder->hpd_pin);
5215                 return false;
5216         }
5217
5218         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5219 }
5220
5221 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5222                                      struct intel_digital_port *intel_dig_port)
5223 {
5224         enum port port = intel_dig_port->base.port;
5225
5226         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5227 }
5228
5229 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5230 {
5231         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5232         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5233         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5234
5235         if (intel_phy_is_combo(dev_priv, phy))
5236                 return icl_combo_port_connected(dev_priv, dig_port);
5237         else if (intel_phy_is_tc(dev_priv, phy))
5238                 return intel_tc_port_connected(dig_port);
5239         else
5240                 MISSING_CASE(encoder->hpd_pin);
5241
5242         return false;
5243 }
5244
5245 /*
5246  * intel_digital_port_connected - is the specified port connected?
5247  * @encoder: intel_encoder
5248  *
5249  * In cases where there's a connector physically connected but it can't be used
5250  * by our hardware we also return false, since the rest of the driver should
5251  * pretty much treat the port as disconnected. This is relevant for type-C
5252  * (starting on ICL) where there's ownership involved.
5253  *
5254  * Return %true if port is connected, %false otherwise.
5255  */
5256 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5257 {
5258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5259
5260         if (HAS_GMCH(dev_priv)) {
5261                 if (IS_GM45(dev_priv))
5262                         return gm45_digital_port_connected(encoder);
5263                 else
5264                         return g4x_digital_port_connected(encoder);
5265         }
5266
5267         if (INTEL_GEN(dev_priv) >= 11)
5268                 return icl_digital_port_connected(encoder);
5269         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5270                 return spt_digital_port_connected(encoder);
5271         else if (IS_GEN9_LP(dev_priv))
5272                 return bxt_digital_port_connected(encoder);
5273         else if (IS_GEN(dev_priv, 8))
5274                 return bdw_digital_port_connected(encoder);
5275         else if (IS_GEN(dev_priv, 7))
5276                 return ivb_digital_port_connected(encoder);
5277         else if (IS_GEN(dev_priv, 6))
5278                 return snb_digital_port_connected(encoder);
5279         else if (IS_GEN(dev_priv, 5))
5280                 return ilk_digital_port_connected(encoder);
5281
5282         MISSING_CASE(INTEL_GEN(dev_priv));
5283         return false;
5284 }
5285
5286 bool intel_digital_port_connected(struct intel_encoder *encoder)
5287 {
5288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5289         bool is_connected = false;
5290         intel_wakeref_t wakeref;
5291
5292         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5293                 is_connected = __intel_digital_port_connected(encoder);
5294
5295         return is_connected;
5296 }
5297
5298 static struct edid *
5299 intel_dp_get_edid(struct intel_dp *intel_dp)
5300 {
5301         struct intel_connector *intel_connector = intel_dp->attached_connector;
5302
5303         /* use cached edid if we have one */
5304         if (intel_connector->edid) {
5305                 /* invalid edid */
5306                 if (IS_ERR(intel_connector->edid))
5307                         return NULL;
5308
5309                 return drm_edid_duplicate(intel_connector->edid);
5310         } else
5311                 return drm_get_edid(&intel_connector->base,
5312                                     &intel_dp->aux.ddc);
5313 }
5314
5315 static void
5316 intel_dp_set_edid(struct intel_dp *intel_dp)
5317 {
5318         struct intel_connector *intel_connector = intel_dp->attached_connector;
5319         struct edid *edid;
5320
5321         intel_dp_unset_edid(intel_dp);
5322         edid = intel_dp_get_edid(intel_dp);
5323         intel_connector->detect_edid = edid;
5324
5325         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5326         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5327 }
5328
5329 static void
5330 intel_dp_unset_edid(struct intel_dp *intel_dp)
5331 {
5332         struct intel_connector *intel_connector = intel_dp->attached_connector;
5333
5334         drm_dp_cec_unset_edid(&intel_dp->aux);
5335         kfree(intel_connector->detect_edid);
5336         intel_connector->detect_edid = NULL;
5337
5338         intel_dp->has_audio = false;
5339 }
5340
5341 static int
5342 intel_dp_detect(struct drm_connector *connector,
5343                 struct drm_modeset_acquire_ctx *ctx,
5344                 bool force)
5345 {
5346         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5347         struct intel_dp *intel_dp = intel_attached_dp(connector);
5348         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5349         struct intel_encoder *encoder = &dig_port->base;
5350         enum drm_connector_status status;
5351
5352         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5353                       connector->base.id, connector->name);
5354         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5355
5356         /* Can't disconnect eDP */
5357         if (intel_dp_is_edp(intel_dp))
5358                 status = edp_detect(intel_dp);
5359         else if (intel_digital_port_connected(encoder))
5360                 status = intel_dp_detect_dpcd(intel_dp);
5361         else
5362                 status = connector_status_disconnected;
5363
5364         if (status == connector_status_disconnected) {
5365                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5366                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5367
5368                 if (intel_dp->is_mst) {
5369                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5370                                       intel_dp->is_mst,
5371                                       intel_dp->mst_mgr.mst_state);
5372                         intel_dp->is_mst = false;
5373                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5374                                                         intel_dp->is_mst);
5375                 }
5376
5377                 goto out;
5378         }
5379
5380         if (intel_dp->reset_link_params) {
5381                 /* Initial max link lane count */
5382                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5383
5384                 /* Initial max link rate */
5385                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5386
5387                 intel_dp->reset_link_params = false;
5388         }
5389
5390         intel_dp_print_rates(intel_dp);
5391
5392         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5393         if (INTEL_GEN(dev_priv) >= 11)
5394                 intel_dp_get_dsc_sink_cap(intel_dp);
5395
5396         intel_dp_configure_mst(intel_dp);
5397
5398         if (intel_dp->is_mst) {
5399                 /*
5400                  * If we are in MST mode then this connector
5401                  * won't appear connected or have anything
5402                  * with EDID on it
5403                  */
5404                 status = connector_status_disconnected;
5405                 goto out;
5406         }
5407
5408         /*
5409          * Some external monitors do not signal loss of link synchronization
5410          * with an IRQ_HPD, so force a link status check.
5411          */
5412         if (!intel_dp_is_edp(intel_dp)) {
5413                 int ret;
5414
5415                 ret = intel_dp_retrain_link(encoder, ctx);
5416                 if (ret)
5417                         return ret;
5418         }
5419
5420         /*
5421          * Clearing NACK and defer counts to get their exact values
5422          * while reading EDID which are required by Compliance tests
5423          * 4.2.2.4 and 4.2.2.5
5424          */
5425         intel_dp->aux.i2c_nack_count = 0;
5426         intel_dp->aux.i2c_defer_count = 0;
5427
5428         intel_dp_set_edid(intel_dp);
5429         if (intel_dp_is_edp(intel_dp) ||
5430             to_intel_connector(connector)->detect_edid)
5431                 status = connector_status_connected;
5432
5433         intel_dp_check_service_irq(intel_dp);
5434
5435 out:
5436         if (status != connector_status_connected && !intel_dp->is_mst)
5437                 intel_dp_unset_edid(intel_dp);
5438
5439         return status;
5440 }
5441
5442 static void
5443 intel_dp_force(struct drm_connector *connector)
5444 {
5445         struct intel_dp *intel_dp = intel_attached_dp(connector);
5446         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5447         struct intel_encoder *intel_encoder = &dig_port->base;
5448         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5449         enum intel_display_power_domain aux_domain =
5450                 intel_aux_power_domain(dig_port);
5451         intel_wakeref_t wakeref;
5452
5453         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5454                       connector->base.id, connector->name);
5455         intel_dp_unset_edid(intel_dp);
5456
5457         if (connector->status != connector_status_connected)
5458                 return;
5459
5460         wakeref = intel_display_power_get(dev_priv, aux_domain);
5461
5462         intel_dp_set_edid(intel_dp);
5463
5464         intel_display_power_put(dev_priv, aux_domain, wakeref);
5465 }
5466
5467 static int intel_dp_get_modes(struct drm_connector *connector)
5468 {
5469         struct intel_connector *intel_connector = to_intel_connector(connector);
5470         struct edid *edid;
5471
5472         edid = intel_connector->detect_edid;
5473         if (edid) {
5474                 int ret = intel_connector_update_modes(connector, edid);
5475                 if (ret)
5476                         return ret;
5477         }
5478
5479         /* if eDP has no EDID, fall back to fixed mode */
5480         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5481             intel_connector->panel.fixed_mode) {
5482                 struct drm_display_mode *mode;
5483
5484                 mode = drm_mode_duplicate(connector->dev,
5485                                           intel_connector->panel.fixed_mode);
5486                 if (mode) {
5487                         drm_mode_probed_add(connector, mode);
5488                         return 1;
5489                 }
5490         }
5491
5492         return 0;
5493 }
5494
5495 static int
5496 intel_dp_connector_register(struct drm_connector *connector)
5497 {
5498         struct intel_dp *intel_dp = intel_attached_dp(connector);
5499         struct drm_device *dev = connector->dev;
5500         int ret;
5501
5502         ret = intel_connector_register(connector);
5503         if (ret)
5504                 return ret;
5505
5506         i915_debugfs_connector_add(connector);
5507
5508         DRM_DEBUG_KMS("registering %s bus for %s\n",
5509                       intel_dp->aux.name, connector->kdev->kobj.name);
5510
5511         intel_dp->aux.dev = connector->kdev;
5512         ret = drm_dp_aux_register(&intel_dp->aux);
5513         if (!ret)
5514                 drm_dp_cec_register_connector(&intel_dp->aux,
5515                                               connector->name, dev->dev);
5516         return ret;
5517 }
5518
5519 static void
5520 intel_dp_connector_unregister(struct drm_connector *connector)
5521 {
5522         struct intel_dp *intel_dp = intel_attached_dp(connector);
5523
5524         drm_dp_cec_unregister_connector(&intel_dp->aux);
5525         drm_dp_aux_unregister(&intel_dp->aux);
5526         intel_connector_unregister(connector);
5527 }
5528
5529 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5530 {
5531         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5532         struct intel_dp *intel_dp = &intel_dig_port->dp;
5533
5534         intel_dp_mst_encoder_cleanup(intel_dig_port);
5535         if (intel_dp_is_edp(intel_dp)) {
5536                 intel_wakeref_t wakeref;
5537
5538                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5539                 /*
5540                  * vdd might still be enabled do to the delayed vdd off.
5541                  * Make sure vdd is actually turned off here.
5542                  */
5543                 with_pps_lock(intel_dp, wakeref)
5544                         edp_panel_vdd_off_sync(intel_dp);
5545
5546                 if (intel_dp->edp_notifier.notifier_call) {
5547                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5548                         intel_dp->edp_notifier.notifier_call = NULL;
5549                 }
5550         }
5551
5552         intel_dp_aux_fini(intel_dp);
5553 }
5554
5555 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5556 {
5557         intel_dp_encoder_flush_work(encoder);
5558
5559         drm_encoder_cleanup(encoder);
5560         kfree(enc_to_dig_port(encoder));
5561 }
5562
5563 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5564 {
5565         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5566         intel_wakeref_t wakeref;
5567
5568         if (!intel_dp_is_edp(intel_dp))
5569                 return;
5570
5571         /*
5572          * vdd might still be enabled do to the delayed vdd off.
5573          * Make sure vdd is actually turned off here.
5574          */
5575         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5576         with_pps_lock(intel_dp, wakeref)
5577                 edp_panel_vdd_off_sync(intel_dp);
5578 }
5579
5580 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5581 {
5582         long ret;
5583
5584 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5585         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5586                                                msecs_to_jiffies(timeout));
5587
5588         if (!ret)
5589                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5590 }
5591
5592 static
5593 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5594                                 u8 *an)
5595 {
5596         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5597         static const struct drm_dp_aux_msg msg = {
5598                 .request = DP_AUX_NATIVE_WRITE,
5599                 .address = DP_AUX_HDCP_AKSV,
5600                 .size = DRM_HDCP_KSV_LEN,
5601         };
5602         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5603         ssize_t dpcd_ret;
5604         int ret;
5605
5606         /* Output An first, that's easy */
5607         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5608                                      an, DRM_HDCP_AN_LEN);
5609         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5610                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5611                               dpcd_ret);
5612                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5613         }
5614
5615         /*
5616          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5617          * order to get it on the wire, we need to create the AUX header as if
5618          * we were writing the data, and then tickle the hardware to output the
5619          * data once the header is sent out.
5620          */
5621         intel_dp_aux_header(txbuf, &msg);
5622
5623         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5624                                 rxbuf, sizeof(rxbuf),
5625                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5626         if (ret < 0) {
5627                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5628                 return ret;
5629         } else if (ret == 0) {
5630                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5631                 return -EIO;
5632         }
5633
5634         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5635         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5636                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5637                               reply);
5638                 return -EIO;
5639         }
5640         return 0;
5641 }
5642
5643 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5644                                    u8 *bksv)
5645 {
5646         ssize_t ret;
5647         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5648                                DRM_HDCP_KSV_LEN);
5649         if (ret != DRM_HDCP_KSV_LEN) {
5650                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5651                 return ret >= 0 ? -EIO : ret;
5652         }
5653         return 0;
5654 }
5655
5656 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5657                                       u8 *bstatus)
5658 {
5659         ssize_t ret;
5660         /*
5661          * For some reason the HDMI and DP HDCP specs call this register
5662          * definition by different names. In the HDMI spec, it's called BSTATUS,
5663          * but in DP it's called BINFO.
5664          */
5665         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5666                                bstatus, DRM_HDCP_BSTATUS_LEN);
5667         if (ret != DRM_HDCP_BSTATUS_LEN) {
5668                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5669                 return ret >= 0 ? -EIO : ret;
5670         }
5671         return 0;
5672 }
5673
5674 static
5675 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5676                              u8 *bcaps)
5677 {
5678         ssize_t ret;
5679
5680         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5681                                bcaps, 1);
5682         if (ret != 1) {
5683                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5684                 return ret >= 0 ? -EIO : ret;
5685         }
5686
5687         return 0;
5688 }
5689
5690 static
5691 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5692                                    bool *repeater_present)
5693 {
5694         ssize_t ret;
5695         u8 bcaps;
5696
5697         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5698         if (ret)
5699                 return ret;
5700
5701         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5702         return 0;
5703 }
5704
5705 static
5706 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5707                                 u8 *ri_prime)
5708 {
5709         ssize_t ret;
5710         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5711                                ri_prime, DRM_HDCP_RI_LEN);
5712         if (ret != DRM_HDCP_RI_LEN) {
5713                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5714                 return ret >= 0 ? -EIO : ret;
5715         }
5716         return 0;
5717 }
5718
5719 static
5720 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5721                                  bool *ksv_ready)
5722 {
5723         ssize_t ret;
5724         u8 bstatus;
5725         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5726                                &bstatus, 1);
5727         if (ret != 1) {
5728                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5729                 return ret >= 0 ? -EIO : ret;
5730         }
5731         *ksv_ready = bstatus & DP_BSTATUS_READY;
5732         return 0;
5733 }
5734
5735 static
5736 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5737                                 int num_downstream, u8 *ksv_fifo)
5738 {
5739         ssize_t ret;
5740         int i;
5741
5742         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5743         for (i = 0; i < num_downstream; i += 3) {
5744                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5745                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5746                                        DP_AUX_HDCP_KSV_FIFO,
5747                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5748                                        len);
5749                 if (ret != len) {
5750                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5751                                       i, ret);
5752                         return ret >= 0 ? -EIO : ret;
5753                 }
5754         }
5755         return 0;
5756 }
5757
5758 static
5759 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5760                                     int i, u32 *part)
5761 {
5762         ssize_t ret;
5763
5764         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5765                 return -EINVAL;
5766
5767         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5768                                DP_AUX_HDCP_V_PRIME(i), part,
5769                                DRM_HDCP_V_PRIME_PART_LEN);
5770         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5771                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5772                 return ret >= 0 ? -EIO : ret;
5773         }
5774         return 0;
5775 }
5776
5777 static
5778 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5779                                     bool enable)
5780 {
5781         /* Not used for single stream DisplayPort setups */
5782         return 0;
5783 }
5784
5785 static
5786 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5787 {
5788         ssize_t ret;
5789         u8 bstatus;
5790
5791         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5792                                &bstatus, 1);
5793         if (ret != 1) {
5794                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5795                 return false;
5796         }
5797
5798         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5799 }
5800
5801 static
5802 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5803                           bool *hdcp_capable)
5804 {
5805         ssize_t ret;
5806         u8 bcaps;
5807
5808         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5809         if (ret)
5810                 return ret;
5811
5812         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5813         return 0;
5814 }
5815
5816 struct hdcp2_dp_errata_stream_type {
5817         u8      msg_id;
5818         u8      stream_type;
5819 } __packed;
5820
5821 struct hdcp2_dp_msg_data {
5822         u8 msg_id;
5823         u32 offset;
5824         bool msg_detectable;
5825         u32 timeout;
5826         u32 timeout2; /* Added for non_paired situation */
5827 };
5828
5829 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
5830         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
5831         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5832           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
5833         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5834           false, 0, 0 },
5835         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5836           false, 0, 0 },
5837         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5838           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5839           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
5840         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
5841           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5842           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
5843         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
5844         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5845           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
5846         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5847           0, 0 },
5848         { HDCP_2_2_REP_SEND_RECVID_LIST,
5849           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5850           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
5851         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5852           0, 0 },
5853         { HDCP_2_2_REP_STREAM_MANAGE,
5854           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5855           0, 0 },
5856         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5857           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
5858 /* local define to shovel this through the write_2_2 interface */
5859 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5860         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5861           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5862           0, 0 },
5863 };
5864
5865 static inline
5866 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5867                                   u8 *rx_status)
5868 {
5869         ssize_t ret;
5870
5871         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5872                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5873                                HDCP_2_2_DP_RXSTATUS_LEN);
5874         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5875                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5876                 return ret >= 0 ? -EIO : ret;
5877         }
5878
5879         return 0;
5880 }
5881
5882 static
5883 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5884                                   u8 msg_id, bool *msg_ready)
5885 {
5886         u8 rx_status;
5887         int ret;
5888
5889         *msg_ready = false;
5890         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5891         if (ret < 0)
5892                 return ret;
5893
5894         switch (msg_id) {
5895         case HDCP_2_2_AKE_SEND_HPRIME:
5896                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5897                         *msg_ready = true;
5898                 break;
5899         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5900                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5901                         *msg_ready = true;
5902                 break;
5903         case HDCP_2_2_REP_SEND_RECVID_LIST:
5904                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5905                         *msg_ready = true;
5906                 break;
5907         default:
5908                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5909                 return -EINVAL;
5910         }
5911
5912         return 0;
5913 }
5914
5915 static ssize_t
5916 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5917                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
5918 {
5919         struct intel_dp *dp = &intel_dig_port->dp;
5920         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5921         u8 msg_id = hdcp2_msg_data->msg_id;
5922         int ret, timeout;
5923         bool msg_ready = false;
5924
5925         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5926                 timeout = hdcp2_msg_data->timeout2;
5927         else
5928                 timeout = hdcp2_msg_data->timeout;
5929
5930         /*
5931          * There is no way to detect the CERT, LPRIME and STREAM_READY
5932          * availability. So Wait for timeout and read the msg.
5933          */
5934         if (!hdcp2_msg_data->msg_detectable) {
5935                 mdelay(timeout);
5936                 ret = 0;
5937         } else {
5938                 /*
5939                  * As we want to check the msg availability at timeout, Ignoring
5940                  * the timeout at wait for CP_IRQ.
5941                  */
5942                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5943                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5944                                                     msg_id, &msg_ready);
5945                 if (!msg_ready)
5946                         ret = -ETIMEDOUT;
5947         }
5948
5949         if (ret)
5950                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5951                               hdcp2_msg_data->msg_id, ret, timeout);
5952
5953         return ret;
5954 }
5955
5956 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
5957 {
5958         int i;
5959
5960         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
5961                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
5962                         return &hdcp2_dp_msg_data[i];
5963
5964         return NULL;
5965 }
5966
5967 static
5968 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
5969                              void *buf, size_t size)
5970 {
5971         struct intel_dp *dp = &intel_dig_port->dp;
5972         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5973         unsigned int offset;
5974         u8 *byte = buf;
5975         ssize_t ret, bytes_to_write, len;
5976         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
5977
5978         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
5979         if (!hdcp2_msg_data)
5980                 return -EINVAL;
5981
5982         offset = hdcp2_msg_data->offset;
5983
5984         /* No msg_id in DP HDCP2.2 msgs */
5985         bytes_to_write = size - 1;
5986         byte++;
5987
5988         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
5989
5990         while (bytes_to_write) {
5991                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
5992                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
5993
5994                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
5995                                         offset, (void *)byte, len);
5996                 if (ret < 0)
5997                         return ret;
5998
5999                 bytes_to_write -= ret;
6000                 byte += ret;
6001                 offset += ret;
6002         }
6003
6004         return size;
6005 }
6006
6007 static
6008 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6009 {
6010         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6011         u32 dev_cnt;
6012         ssize_t ret;
6013
6014         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6015                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6016                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6017         if (ret != HDCP_2_2_RXINFO_LEN)
6018                 return ret >= 0 ? -EIO : ret;
6019
6020         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6021                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6022
6023         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6024                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6025
6026         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6027                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6028                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6029
6030         return ret;
6031 }
6032
6033 static
6034 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6035                             u8 msg_id, void *buf, size_t size)
6036 {
6037         unsigned int offset;
6038         u8 *byte = buf;
6039         ssize_t ret, bytes_to_recv, len;
6040         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6041
6042         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6043         if (!hdcp2_msg_data)
6044                 return -EINVAL;
6045         offset = hdcp2_msg_data->offset;
6046
6047         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6048         if (ret < 0)
6049                 return ret;
6050
6051         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6052                 ret = get_receiver_id_list_size(intel_dig_port);
6053                 if (ret < 0)
6054                         return ret;
6055
6056                 size = ret;
6057         }
6058         bytes_to_recv = size - 1;
6059
6060         /* DP adaptation msgs has no msg_id */
6061         byte++;
6062
6063         while (bytes_to_recv) {
6064                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6065                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6066
6067                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6068                                        (void *)byte, len);
6069                 if (ret < 0) {
6070                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6071                         return ret;
6072                 }
6073
6074                 bytes_to_recv -= ret;
6075                 byte += ret;
6076                 offset += ret;
6077         }
6078         byte = buf;
6079         *byte = msg_id;
6080
6081         return size;
6082 }
6083
6084 static
6085 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6086                                       bool is_repeater, u8 content_type)
6087 {
6088         struct hdcp2_dp_errata_stream_type stream_type_msg;
6089
6090         if (is_repeater)
6091                 return 0;
6092
6093         /*
6094          * Errata for DP: As Stream type is used for encryption, Receiver
6095          * should be communicated with stream type for the decryption of the
6096          * content.
6097          * Repeater will be communicated with stream type as a part of it's
6098          * auth later in time.
6099          */
6100         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6101         stream_type_msg.stream_type = content_type;
6102
6103         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6104                                         sizeof(stream_type_msg));
6105 }
6106
6107 static
6108 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6109 {
6110         u8 rx_status;
6111         int ret;
6112
6113         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6114         if (ret)
6115                 return ret;
6116
6117         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6118                 ret = HDCP_REAUTH_REQUEST;
6119         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6120                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6121         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6122                 ret = HDCP_TOPOLOGY_CHANGE;
6123
6124         return ret;
6125 }
6126
6127 static
6128 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6129                            bool *capable)
6130 {
6131         u8 rx_caps[3];
6132         int ret;
6133
6134         *capable = false;
6135         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6136                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6137                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6138         if (ret != HDCP_2_2_RXCAPS_LEN)
6139                 return ret >= 0 ? -EIO : ret;
6140
6141         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6142             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6143                 *capable = true;
6144
6145         return 0;
6146 }
6147
6148 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6149         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6150         .read_bksv = intel_dp_hdcp_read_bksv,
6151         .read_bstatus = intel_dp_hdcp_read_bstatus,
6152         .repeater_present = intel_dp_hdcp_repeater_present,
6153         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6154         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6155         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6156         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6157         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6158         .check_link = intel_dp_hdcp_check_link,
6159         .hdcp_capable = intel_dp_hdcp_capable,
6160         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6161         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6162         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6163         .check_2_2_link = intel_dp_hdcp2_check_link,
6164         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6165         .protocol = HDCP_PROTOCOL_DP,
6166 };
6167
6168 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6169 {
6170         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6171         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6172
6173         lockdep_assert_held(&dev_priv->pps_mutex);
6174
6175         if (!edp_have_panel_vdd(intel_dp))
6176                 return;
6177
6178         /*
6179          * The VDD bit needs a power domain reference, so if the bit is
6180          * already enabled when we boot or resume, grab this reference and
6181          * schedule a vdd off, so we don't hold on to the reference
6182          * indefinitely.
6183          */
6184         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6185         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6186
6187         edp_panel_vdd_schedule_off(intel_dp);
6188 }
6189
6190 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6191 {
6192         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6193         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6194         enum pipe pipe;
6195
6196         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6197                                   encoder->port, &pipe))
6198                 return pipe;
6199
6200         return INVALID_PIPE;
6201 }
6202
6203 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6204 {
6205         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6206         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6207         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6208         intel_wakeref_t wakeref;
6209
6210         if (!HAS_DDI(dev_priv))
6211                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6212
6213         if (lspcon->active)
6214                 lspcon_resume(lspcon);
6215
6216         intel_dp->reset_link_params = true;
6217
6218         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6219             !intel_dp_is_edp(intel_dp))
6220                 return;
6221
6222         with_pps_lock(intel_dp, wakeref) {
6223                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6224                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6225
6226                 if (intel_dp_is_edp(intel_dp)) {
6227                         /*
6228                          * Reinit the power sequencer, in case BIOS did
6229                          * something nasty with it.
6230                          */
6231                         intel_dp_pps_init(intel_dp);
6232                         intel_edp_panel_vdd_sanitize(intel_dp);
6233                 }
6234         }
6235 }
6236
6237 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6238         .force = intel_dp_force,
6239         .fill_modes = drm_helper_probe_single_connector_modes,
6240         .atomic_get_property = intel_digital_connector_atomic_get_property,
6241         .atomic_set_property = intel_digital_connector_atomic_set_property,
6242         .late_register = intel_dp_connector_register,
6243         .early_unregister = intel_dp_connector_unregister,
6244         .destroy = intel_connector_destroy,
6245         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6246         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6247 };
6248
6249 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6250         .detect_ctx = intel_dp_detect,
6251         .get_modes = intel_dp_get_modes,
6252         .mode_valid = intel_dp_mode_valid,
6253         .atomic_check = intel_digital_connector_atomic_check,
6254 };
6255
6256 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6257         .reset = intel_dp_encoder_reset,
6258         .destroy = intel_dp_encoder_destroy,
6259 };
6260
6261 enum irqreturn
6262 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6263 {
6264         struct intel_dp *intel_dp = &intel_dig_port->dp;
6265
6266         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6267                 /*
6268                  * vdd off can generate a long pulse on eDP which
6269                  * would require vdd on to handle it, and thus we
6270                  * would end up in an endless cycle of
6271                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6272                  */
6273                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6274                               port_name(intel_dig_port->base.port));
6275                 return IRQ_HANDLED;
6276         }
6277
6278         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6279                       port_name(intel_dig_port->base.port),
6280                       long_hpd ? "long" : "short");
6281
6282         if (long_hpd) {
6283                 intel_dp->reset_link_params = true;
6284                 return IRQ_NONE;
6285         }
6286
6287         if (intel_dp->is_mst) {
6288                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6289                         /*
6290                          * If we were in MST mode, and device is not
6291                          * there, get out of MST mode
6292                          */
6293                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6294                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6295                         intel_dp->is_mst = false;
6296                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6297                                                         intel_dp->is_mst);
6298
6299                         return IRQ_NONE;
6300                 }
6301         }
6302
6303         if (!intel_dp->is_mst) {
6304                 bool handled;
6305
6306                 handled = intel_dp_short_pulse(intel_dp);
6307
6308                 if (!handled)
6309                         return IRQ_NONE;
6310         }
6311
6312         return IRQ_HANDLED;
6313 }
6314
6315 /* check the VBT to see whether the eDP is on another port */
6316 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6317 {
6318         /*
6319          * eDP not supported on g4x. so bail out early just
6320          * for a bit extra safety in case the VBT is bonkers.
6321          */
6322         if (INTEL_GEN(dev_priv) < 5)
6323                 return false;
6324
6325         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6326                 return true;
6327
6328         return intel_bios_is_port_edp(dev_priv, port);
6329 }
6330
6331 static void
6332 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6333 {
6334         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6335         enum port port = dp_to_dig_port(intel_dp)->base.port;
6336
6337         if (!IS_G4X(dev_priv) && port != PORT_A)
6338                 intel_attach_force_audio_property(connector);
6339
6340         intel_attach_broadcast_rgb_property(connector);
6341         if (HAS_GMCH(dev_priv))
6342                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6343         else if (INTEL_GEN(dev_priv) >= 5)
6344                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6345
6346         if (intel_dp_is_edp(intel_dp)) {
6347                 u32 allowed_scalers;
6348
6349                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6350                 if (!HAS_GMCH(dev_priv))
6351                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6352
6353                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6354
6355                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6356
6357         }
6358 }
6359
6360 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6361 {
6362         intel_dp->panel_power_off_time = ktime_get_boottime();
6363         intel_dp->last_power_on = jiffies;
6364         intel_dp->last_backlight_off = jiffies;
6365 }
6366
6367 static void
6368 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6369 {
6370         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6371         u32 pp_on, pp_off, pp_ctl;
6372         struct pps_registers regs;
6373
6374         intel_pps_get_registers(intel_dp, &regs);
6375
6376         pp_ctl = ironlake_get_pp_control(intel_dp);
6377
6378         /* Ensure PPS is unlocked */
6379         if (!HAS_DDI(dev_priv))
6380                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6381
6382         pp_on = I915_READ(regs.pp_on);
6383         pp_off = I915_READ(regs.pp_off);
6384
6385         /* Pull timing values out of registers */
6386         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6387         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6388         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6389         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6390
6391         if (i915_mmio_reg_valid(regs.pp_div)) {
6392                 u32 pp_div;
6393
6394                 pp_div = I915_READ(regs.pp_div);
6395
6396                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6397         } else {
6398                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6399         }
6400 }
6401
6402 static void
6403 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6404 {
6405         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6406                       state_name,
6407                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6408 }
6409
6410 static void
6411 intel_pps_verify_state(struct intel_dp *intel_dp)
6412 {
6413         struct edp_power_seq hw;
6414         struct edp_power_seq *sw = &intel_dp->pps_delays;
6415
6416         intel_pps_readout_hw_state(intel_dp, &hw);
6417
6418         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6419             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6420                 DRM_ERROR("PPS state mismatch\n");
6421                 intel_pps_dump_state("sw", sw);
6422                 intel_pps_dump_state("hw", &hw);
6423         }
6424 }
6425
6426 static void
6427 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6428 {
6429         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6430         struct edp_power_seq cur, vbt, spec,
6431                 *final = &intel_dp->pps_delays;
6432
6433         lockdep_assert_held(&dev_priv->pps_mutex);
6434
6435         /* already initialized? */
6436         if (final->t11_t12 != 0)
6437                 return;
6438
6439         intel_pps_readout_hw_state(intel_dp, &cur);
6440
6441         intel_pps_dump_state("cur", &cur);
6442
6443         vbt = dev_priv->vbt.edp.pps;
6444         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6445          * of 500ms appears to be too short. Ocassionally the panel
6446          * just fails to power back on. Increasing the delay to 800ms
6447          * seems sufficient to avoid this problem.
6448          */
6449         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6450                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6451                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6452                               vbt.t11_t12);
6453         }
6454         /* T11_T12 delay is special and actually in units of 100ms, but zero
6455          * based in the hw (so we need to add 100 ms). But the sw vbt
6456          * table multiplies it with 1000 to make it in units of 100usec,
6457          * too. */
6458         vbt.t11_t12 += 100 * 10;
6459
6460         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6461          * our hw here, which are all in 100usec. */
6462         spec.t1_t3 = 210 * 10;
6463         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6464         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6465         spec.t10 = 500 * 10;
6466         /* This one is special and actually in units of 100ms, but zero
6467          * based in the hw (so we need to add 100 ms). But the sw vbt
6468          * table multiplies it with 1000 to make it in units of 100usec,
6469          * too. */
6470         spec.t11_t12 = (510 + 100) * 10;
6471
6472         intel_pps_dump_state("vbt", &vbt);
6473
6474         /* Use the max of the register settings and vbt. If both are
6475          * unset, fall back to the spec limits. */
6476 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6477                                        spec.field : \
6478                                        max(cur.field, vbt.field))
6479         assign_final(t1_t3);
6480         assign_final(t8);
6481         assign_final(t9);
6482         assign_final(t10);
6483         assign_final(t11_t12);
6484 #undef assign_final
6485
6486 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6487         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6488         intel_dp->backlight_on_delay = get_delay(t8);
6489         intel_dp->backlight_off_delay = get_delay(t9);
6490         intel_dp->panel_power_down_delay = get_delay(t10);
6491         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6492 #undef get_delay
6493
6494         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6495                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6496                       intel_dp->panel_power_cycle_delay);
6497
6498         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6499                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6500
6501         /*
6502          * We override the HW backlight delays to 1 because we do manual waits
6503          * on them. For T8, even BSpec recommends doing it. For T9, if we
6504          * don't do this, we'll end up waiting for the backlight off delay
6505          * twice: once when we do the manual sleep, and once when we disable
6506          * the panel and wait for the PP_STATUS bit to become zero.
6507          */
6508         final->t8 = 1;
6509         final->t9 = 1;
6510
6511         /*
6512          * HW has only a 100msec granularity for t11_t12 so round it up
6513          * accordingly.
6514          */
6515         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6516 }
6517
6518 static void
6519 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6520                                               bool force_disable_vdd)
6521 {
6522         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6523         u32 pp_on, pp_off, port_sel = 0;
6524         int div = dev_priv->rawclk_freq / 1000;
6525         struct pps_registers regs;
6526         enum port port = dp_to_dig_port(intel_dp)->base.port;
6527         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6528
6529         lockdep_assert_held(&dev_priv->pps_mutex);
6530
6531         intel_pps_get_registers(intel_dp, &regs);
6532
6533         /*
6534          * On some VLV machines the BIOS can leave the VDD
6535          * enabled even on power sequencers which aren't
6536          * hooked up to any port. This would mess up the
6537          * power domain tracking the first time we pick
6538          * one of these power sequencers for use since
6539          * edp_panel_vdd_on() would notice that the VDD was
6540          * already on and therefore wouldn't grab the power
6541          * domain reference. Disable VDD first to avoid this.
6542          * This also avoids spuriously turning the VDD on as
6543          * soon as the new power sequencer gets initialized.
6544          */
6545         if (force_disable_vdd) {
6546                 u32 pp = ironlake_get_pp_control(intel_dp);
6547
6548                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6549
6550                 if (pp & EDP_FORCE_VDD)
6551                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6552
6553                 pp &= ~EDP_FORCE_VDD;
6554
6555                 I915_WRITE(regs.pp_ctrl, pp);
6556         }
6557
6558         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6559                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6560         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6561                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6562
6563         /* Haswell doesn't have any port selection bits for the panel
6564          * power sequencer any more. */
6565         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6566                 port_sel = PANEL_PORT_SELECT_VLV(port);
6567         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6568                 switch (port) {
6569                 case PORT_A:
6570                         port_sel = PANEL_PORT_SELECT_DPA;
6571                         break;
6572                 case PORT_C:
6573                         port_sel = PANEL_PORT_SELECT_DPC;
6574                         break;
6575                 case PORT_D:
6576                         port_sel = PANEL_PORT_SELECT_DPD;
6577                         break;
6578                 default:
6579                         MISSING_CASE(port);
6580                         break;
6581                 }
6582         }
6583
6584         pp_on |= port_sel;
6585
6586         I915_WRITE(regs.pp_on, pp_on);
6587         I915_WRITE(regs.pp_off, pp_off);
6588
6589         /*
6590          * Compute the divisor for the pp clock, simply match the Bspec formula.
6591          */
6592         if (i915_mmio_reg_valid(regs.pp_div)) {
6593                 I915_WRITE(regs.pp_div,
6594                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6595                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6596         } else {
6597                 u32 pp_ctl;
6598
6599                 pp_ctl = I915_READ(regs.pp_ctrl);
6600                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6601                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6602                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6603         }
6604
6605         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6606                       I915_READ(regs.pp_on),
6607                       I915_READ(regs.pp_off),
6608                       i915_mmio_reg_valid(regs.pp_div) ?
6609                       I915_READ(regs.pp_div) :
6610                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6611 }
6612
6613 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6614 {
6615         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6616
6617         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6618                 vlv_initial_power_sequencer_setup(intel_dp);
6619         } else {
6620                 intel_dp_init_panel_power_sequencer(intel_dp);
6621                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6622         }
6623 }
6624
6625 /**
6626  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6627  * @dev_priv: i915 device
6628  * @crtc_state: a pointer to the active intel_crtc_state
6629  * @refresh_rate: RR to be programmed
6630  *
6631  * This function gets called when refresh rate (RR) has to be changed from
6632  * one frequency to another. Switches can be between high and low RR
6633  * supported by the panel or to any other RR based on media playback (in
6634  * this case, RR value needs to be passed from user space).
6635  *
6636  * The caller of this function needs to take a lock on dev_priv->drrs.
6637  */
6638 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6639                                     const struct intel_crtc_state *crtc_state,
6640                                     int refresh_rate)
6641 {
6642         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6644         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6645
6646         if (refresh_rate <= 0) {
6647                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6648                 return;
6649         }
6650
6651         if (intel_dp == NULL) {
6652                 DRM_DEBUG_KMS("DRRS not supported.\n");
6653                 return;
6654         }
6655
6656         if (!intel_crtc) {
6657                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6658                 return;
6659         }
6660
6661         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6662                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6663                 return;
6664         }
6665
6666         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6667                         refresh_rate)
6668                 index = DRRS_LOW_RR;
6669
6670         if (index == dev_priv->drrs.refresh_rate_type) {
6671                 DRM_DEBUG_KMS(
6672                         "DRRS requested for previously set RR...ignoring\n");
6673                 return;
6674         }
6675
6676         if (!crtc_state->base.active) {
6677                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6678                 return;
6679         }
6680
6681         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6682                 switch (index) {
6683                 case DRRS_HIGH_RR:
6684                         intel_dp_set_m_n(crtc_state, M1_N1);
6685                         break;
6686                 case DRRS_LOW_RR:
6687                         intel_dp_set_m_n(crtc_state, M2_N2);
6688                         break;
6689                 case DRRS_MAX_RR:
6690                 default:
6691                         DRM_ERROR("Unsupported refreshrate type\n");
6692                 }
6693         } else if (INTEL_GEN(dev_priv) > 6) {
6694                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6695                 u32 val;
6696
6697                 val = I915_READ(reg);
6698                 if (index > DRRS_HIGH_RR) {
6699                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6700                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6701                         else
6702                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6703                 } else {
6704                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6705                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6706                         else
6707                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6708                 }
6709                 I915_WRITE(reg, val);
6710         }
6711
6712         dev_priv->drrs.refresh_rate_type = index;
6713
6714         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6715 }
6716
6717 /**
6718  * intel_edp_drrs_enable - init drrs struct if supported
6719  * @intel_dp: DP struct
6720  * @crtc_state: A pointer to the active crtc state.
6721  *
6722  * Initializes frontbuffer_bits and drrs.dp
6723  */
6724 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6725                            const struct intel_crtc_state *crtc_state)
6726 {
6727         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6728
6729         if (!crtc_state->has_drrs) {
6730                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6731                 return;
6732         }
6733
6734         if (dev_priv->psr.enabled) {
6735                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6736                 return;
6737         }
6738
6739         mutex_lock(&dev_priv->drrs.mutex);
6740         if (dev_priv->drrs.dp) {
6741                 DRM_DEBUG_KMS("DRRS already enabled\n");
6742                 goto unlock;
6743         }
6744
6745         dev_priv->drrs.busy_frontbuffer_bits = 0;
6746
6747         dev_priv->drrs.dp = intel_dp;
6748
6749 unlock:
6750         mutex_unlock(&dev_priv->drrs.mutex);
6751 }
6752
6753 /**
6754  * intel_edp_drrs_disable - Disable DRRS
6755  * @intel_dp: DP struct
6756  * @old_crtc_state: Pointer to old crtc_state.
6757  *
6758  */
6759 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6760                             const struct intel_crtc_state *old_crtc_state)
6761 {
6762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6763
6764         if (!old_crtc_state->has_drrs)
6765                 return;
6766
6767         mutex_lock(&dev_priv->drrs.mutex);
6768         if (!dev_priv->drrs.dp) {
6769                 mutex_unlock(&dev_priv->drrs.mutex);
6770                 return;
6771         }
6772
6773         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6774                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6775                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6776
6777         dev_priv->drrs.dp = NULL;
6778         mutex_unlock(&dev_priv->drrs.mutex);
6779
6780         cancel_delayed_work_sync(&dev_priv->drrs.work);
6781 }
6782
6783 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6784 {
6785         struct drm_i915_private *dev_priv =
6786                 container_of(work, typeof(*dev_priv), drrs.work.work);
6787         struct intel_dp *intel_dp;
6788
6789         mutex_lock(&dev_priv->drrs.mutex);
6790
6791         intel_dp = dev_priv->drrs.dp;
6792
6793         if (!intel_dp)
6794                 goto unlock;
6795
6796         /*
6797          * The delayed work can race with an invalidate hence we need to
6798          * recheck.
6799          */
6800
6801         if (dev_priv->drrs.busy_frontbuffer_bits)
6802                 goto unlock;
6803
6804         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6805                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6806
6807                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6808                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6809         }
6810
6811 unlock:
6812         mutex_unlock(&dev_priv->drrs.mutex);
6813 }
6814
6815 /**
6816  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6817  * @dev_priv: i915 device
6818  * @frontbuffer_bits: frontbuffer plane tracking bits
6819  *
6820  * This function gets called everytime rendering on the given planes start.
6821  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6822  *
6823  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6824  */
6825 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6826                                unsigned int frontbuffer_bits)
6827 {
6828         struct drm_crtc *crtc;
6829         enum pipe pipe;
6830
6831         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6832                 return;
6833
6834         cancel_delayed_work(&dev_priv->drrs.work);
6835
6836         mutex_lock(&dev_priv->drrs.mutex);
6837         if (!dev_priv->drrs.dp) {
6838                 mutex_unlock(&dev_priv->drrs.mutex);
6839                 return;
6840         }
6841
6842         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6843         pipe = to_intel_crtc(crtc)->pipe;
6844
6845         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6846         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6847
6848         /* invalidate means busy screen hence upclock */
6849         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6850                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6851                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6852
6853         mutex_unlock(&dev_priv->drrs.mutex);
6854 }
6855
6856 /**
6857  * intel_edp_drrs_flush - Restart Idleness DRRS
6858  * @dev_priv: i915 device
6859  * @frontbuffer_bits: frontbuffer plane tracking bits
6860  *
6861  * This function gets called every time rendering on the given planes has
6862  * completed or flip on a crtc is completed. So DRRS should be upclocked
6863  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6864  * if no other planes are dirty.
6865  *
6866  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6867  */
6868 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6869                           unsigned int frontbuffer_bits)
6870 {
6871         struct drm_crtc *crtc;
6872         enum pipe pipe;
6873
6874         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6875                 return;
6876
6877         cancel_delayed_work(&dev_priv->drrs.work);
6878
6879         mutex_lock(&dev_priv->drrs.mutex);
6880         if (!dev_priv->drrs.dp) {
6881                 mutex_unlock(&dev_priv->drrs.mutex);
6882                 return;
6883         }
6884
6885         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6886         pipe = to_intel_crtc(crtc)->pipe;
6887
6888         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6889         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6890
6891         /* flush means busy screen hence upclock */
6892         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6893                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6894                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6895
6896         /*
6897          * flush also means no more activity hence schedule downclock, if all
6898          * other fbs are quiescent too
6899          */
6900         if (!dev_priv->drrs.busy_frontbuffer_bits)
6901                 schedule_delayed_work(&dev_priv->drrs.work,
6902                                 msecs_to_jiffies(1000));
6903         mutex_unlock(&dev_priv->drrs.mutex);
6904 }
6905
6906 /**
6907  * DOC: Display Refresh Rate Switching (DRRS)
6908  *
6909  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6910  * which enables swtching between low and high refresh rates,
6911  * dynamically, based on the usage scenario. This feature is applicable
6912  * for internal panels.
6913  *
6914  * Indication that the panel supports DRRS is given by the panel EDID, which
6915  * would list multiple refresh rates for one resolution.
6916  *
6917  * DRRS is of 2 types - static and seamless.
6918  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6919  * (may appear as a blink on screen) and is used in dock-undock scenario.
6920  * Seamless DRRS involves changing RR without any visual effect to the user
6921  * and can be used during normal system usage. This is done by programming
6922  * certain registers.
6923  *
6924  * Support for static/seamless DRRS may be indicated in the VBT based on
6925  * inputs from the panel spec.
6926  *
6927  * DRRS saves power by switching to low RR based on usage scenarios.
6928  *
6929  * The implementation is based on frontbuffer tracking implementation.  When
6930  * there is a disturbance on the screen triggered by user activity or a periodic
6931  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6932  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6933  * made.
6934  *
6935  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6936  * and intel_edp_drrs_flush() are called.
6937  *
6938  * DRRS can be further extended to support other internal panels and also
6939  * the scenario of video playback wherein RR is set based on the rate
6940  * requested by userspace.
6941  */
6942
6943 /**
6944  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6945  * @connector: eDP connector
6946  * @fixed_mode: preferred mode of panel
6947  *
6948  * This function is  called only once at driver load to initialize basic
6949  * DRRS stuff.
6950  *
6951  * Returns:
6952  * Downclock mode if panel supports it, else return NULL.
6953  * DRRS support is determined by the presence of downclock mode (apart
6954  * from VBT setting).
6955  */
6956 static struct drm_display_mode *
6957 intel_dp_drrs_init(struct intel_connector *connector,
6958                    struct drm_display_mode *fixed_mode)
6959 {
6960         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6961         struct drm_display_mode *downclock_mode = NULL;
6962
6963         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6964         mutex_init(&dev_priv->drrs.mutex);
6965
6966         if (INTEL_GEN(dev_priv) <= 6) {
6967                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6968                 return NULL;
6969         }
6970
6971         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6972                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6973                 return NULL;
6974         }
6975
6976         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
6977         if (!downclock_mode) {
6978                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6979                 return NULL;
6980         }
6981
6982         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6983
6984         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6985         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6986         return downclock_mode;
6987 }
6988
6989 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6990                                      struct intel_connector *intel_connector)
6991 {
6992         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6993         struct drm_device *dev = &dev_priv->drm;
6994         struct drm_connector *connector = &intel_connector->base;
6995         struct drm_display_mode *fixed_mode = NULL;
6996         struct drm_display_mode *downclock_mode = NULL;
6997         bool has_dpcd;
6998         enum pipe pipe = INVALID_PIPE;
6999         intel_wakeref_t wakeref;
7000         struct edid *edid;
7001
7002         if (!intel_dp_is_edp(intel_dp))
7003                 return true;
7004
7005         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7006
7007         /*
7008          * On IBX/CPT we may get here with LVDS already registered. Since the
7009          * driver uses the only internal power sequencer available for both
7010          * eDP and LVDS bail out early in this case to prevent interfering
7011          * with an already powered-on LVDS power sequencer.
7012          */
7013         if (intel_get_lvds_encoder(dev_priv)) {
7014                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7015                 DRM_INFO("LVDS was detected, not registering eDP\n");
7016
7017                 return false;
7018         }
7019
7020         with_pps_lock(intel_dp, wakeref) {
7021                 intel_dp_init_panel_power_timestamps(intel_dp);
7022                 intel_dp_pps_init(intel_dp);
7023                 intel_edp_panel_vdd_sanitize(intel_dp);
7024         }
7025
7026         /* Cache DPCD and EDID for edp. */
7027         has_dpcd = intel_edp_init_dpcd(intel_dp);
7028
7029         if (!has_dpcd) {
7030                 /* if this fails, presume the device is a ghost */
7031                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7032                 goto out_vdd_off;
7033         }
7034
7035         mutex_lock(&dev->mode_config.mutex);
7036         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7037         if (edid) {
7038                 if (drm_add_edid_modes(connector, edid)) {
7039                         drm_connector_update_edid_property(connector,
7040                                                                 edid);
7041                 } else {
7042                         kfree(edid);
7043                         edid = ERR_PTR(-EINVAL);
7044                 }
7045         } else {
7046                 edid = ERR_PTR(-ENOENT);
7047         }
7048         intel_connector->edid = edid;
7049
7050         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7051         if (fixed_mode)
7052                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7053
7054         /* fallback to VBT if available for eDP */
7055         if (!fixed_mode)
7056                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7057         mutex_unlock(&dev->mode_config.mutex);
7058
7059         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7060                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7061                 register_reboot_notifier(&intel_dp->edp_notifier);
7062
7063                 /*
7064                  * Figure out the current pipe for the initial backlight setup.
7065                  * If the current pipe isn't valid, try the PPS pipe, and if that
7066                  * fails just assume pipe A.
7067                  */
7068                 pipe = vlv_active_pipe(intel_dp);
7069
7070                 if (pipe != PIPE_A && pipe != PIPE_B)
7071                         pipe = intel_dp->pps_pipe;
7072
7073                 if (pipe != PIPE_A && pipe != PIPE_B)
7074                         pipe = PIPE_A;
7075
7076                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7077                               pipe_name(pipe));
7078         }
7079
7080         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7081         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7082         intel_panel_setup_backlight(connector, pipe);
7083
7084         if (fixed_mode)
7085                 drm_connector_init_panel_orientation_property(
7086                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7087
7088         return true;
7089
7090 out_vdd_off:
7091         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7092         /*
7093          * vdd might still be enabled do to the delayed vdd off.
7094          * Make sure vdd is actually turned off here.
7095          */
7096         with_pps_lock(intel_dp, wakeref)
7097                 edp_panel_vdd_off_sync(intel_dp);
7098
7099         return false;
7100 }
7101
7102 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7103 {
7104         struct intel_connector *intel_connector;
7105         struct drm_connector *connector;
7106
7107         intel_connector = container_of(work, typeof(*intel_connector),
7108                                        modeset_retry_work);
7109         connector = &intel_connector->base;
7110         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7111                       connector->name);
7112
7113         /* Grab the locks before changing connector property*/
7114         mutex_lock(&connector->dev->mode_config.mutex);
7115         /* Set connector link status to BAD and send a Uevent to notify
7116          * userspace to do a modeset.
7117          */
7118         drm_connector_set_link_status_property(connector,
7119                                                DRM_MODE_LINK_STATUS_BAD);
7120         mutex_unlock(&connector->dev->mode_config.mutex);
7121         /* Send Hotplug uevent so userspace can reprobe */
7122         drm_kms_helper_hotplug_event(connector->dev);
7123 }
7124
7125 bool
7126 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7127                         struct intel_connector *intel_connector)
7128 {
7129         struct drm_connector *connector = &intel_connector->base;
7130         struct intel_dp *intel_dp = &intel_dig_port->dp;
7131         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7132         struct drm_device *dev = intel_encoder->base.dev;
7133         struct drm_i915_private *dev_priv = to_i915(dev);
7134         enum port port = intel_encoder->port;
7135         enum phy phy = intel_port_to_phy(dev_priv, port);
7136         int type;
7137
7138         /* Initialize the work for modeset in case of link train failure */
7139         INIT_WORK(&intel_connector->modeset_retry_work,
7140                   intel_dp_modeset_retry_work_fn);
7141
7142         if (WARN(intel_dig_port->max_lanes < 1,
7143                  "Not enough lanes (%d) for DP on port %c\n",
7144                  intel_dig_port->max_lanes, port_name(port)))
7145                 return false;
7146
7147         intel_dp_set_source_rates(intel_dp);
7148
7149         intel_dp->reset_link_params = true;
7150         intel_dp->pps_pipe = INVALID_PIPE;
7151         intel_dp->active_pipe = INVALID_PIPE;
7152
7153         /* Preserve the current hw state. */
7154         intel_dp->DP = I915_READ(intel_dp->output_reg);
7155         intel_dp->attached_connector = intel_connector;
7156
7157         if (intel_dp_is_port_edp(dev_priv, port)) {
7158                 /*
7159                  * Currently we don't support eDP on TypeC ports, although in
7160                  * theory it could work on TypeC legacy ports.
7161                  */
7162                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7163                 type = DRM_MODE_CONNECTOR_eDP;
7164         } else {
7165                 type = DRM_MODE_CONNECTOR_DisplayPort;
7166         }
7167
7168         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7169                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7170
7171         /*
7172          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7173          * for DP the encoder type can be set by the caller to
7174          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7175          */
7176         if (type == DRM_MODE_CONNECTOR_eDP)
7177                 intel_encoder->type = INTEL_OUTPUT_EDP;
7178
7179         /* eDP only on port B and/or C on vlv/chv */
7180         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7181                     intel_dp_is_edp(intel_dp) &&
7182                     port != PORT_B && port != PORT_C))
7183                 return false;
7184
7185         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7186                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7187                         port_name(port));
7188
7189         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7190         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7191
7192         if (!HAS_GMCH(dev_priv))
7193                 connector->interlace_allowed = true;
7194         connector->doublescan_allowed = 0;
7195
7196         if (INTEL_GEN(dev_priv) >= 11)
7197                 connector->ycbcr_420_allowed = true;
7198
7199         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7200
7201         intel_dp_aux_init(intel_dp);
7202
7203         intel_connector_attach_encoder(intel_connector, intel_encoder);
7204
7205         if (HAS_DDI(dev_priv))
7206                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7207         else
7208                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7209
7210         /* init MST on ports that can support it */
7211         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7212             (port == PORT_B || port == PORT_C ||
7213              port == PORT_D || port == PORT_F))
7214                 intel_dp_mst_encoder_init(intel_dig_port,
7215                                           intel_connector->base.base.id);
7216
7217         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7218                 intel_dp_aux_fini(intel_dp);
7219                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7220                 goto fail;
7221         }
7222
7223         intel_dp_add_properties(intel_dp, connector);
7224
7225         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7226                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7227                 if (ret)
7228                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7229         }
7230
7231         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7232          * 0xd.  Failure to do so will result in spurious interrupts being
7233          * generated on the port when a cable is not attached.
7234          */
7235         if (IS_G45(dev_priv)) {
7236                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7237                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7238         }
7239
7240         return true;
7241
7242 fail:
7243         drm_connector_cleanup(connector);
7244
7245         return false;
7246 }
7247
7248 bool intel_dp_init(struct drm_i915_private *dev_priv,
7249                    i915_reg_t output_reg,
7250                    enum port port)
7251 {
7252         struct intel_digital_port *intel_dig_port;
7253         struct intel_encoder *intel_encoder;
7254         struct drm_encoder *encoder;
7255         struct intel_connector *intel_connector;
7256
7257         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7258         if (!intel_dig_port)
7259                 return false;
7260
7261         intel_connector = intel_connector_alloc();
7262         if (!intel_connector)
7263                 goto err_connector_alloc;
7264
7265         intel_encoder = &intel_dig_port->base;
7266         encoder = &intel_encoder->base;
7267
7268         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7269                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7270                              "DP %c", port_name(port)))
7271                 goto err_encoder_init;
7272
7273         intel_encoder->hotplug = intel_dp_hotplug;
7274         intel_encoder->compute_config = intel_dp_compute_config;
7275         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7276         intel_encoder->get_config = intel_dp_get_config;
7277         intel_encoder->update_pipe = intel_panel_update_backlight;
7278         intel_encoder->suspend = intel_dp_encoder_suspend;
7279         if (IS_CHERRYVIEW(dev_priv)) {
7280                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7281                 intel_encoder->pre_enable = chv_pre_enable_dp;
7282                 intel_encoder->enable = vlv_enable_dp;
7283                 intel_encoder->disable = vlv_disable_dp;
7284                 intel_encoder->post_disable = chv_post_disable_dp;
7285                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7286         } else if (IS_VALLEYVIEW(dev_priv)) {
7287                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7288                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7289                 intel_encoder->enable = vlv_enable_dp;
7290                 intel_encoder->disable = vlv_disable_dp;
7291                 intel_encoder->post_disable = vlv_post_disable_dp;
7292         } else {
7293                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7294                 intel_encoder->enable = g4x_enable_dp;
7295                 intel_encoder->disable = g4x_disable_dp;
7296                 intel_encoder->post_disable = g4x_post_disable_dp;
7297         }
7298
7299         intel_dig_port->dp.output_reg = output_reg;
7300         intel_dig_port->max_lanes = 4;
7301
7302         intel_encoder->type = INTEL_OUTPUT_DP;
7303         intel_encoder->power_domain = intel_port_to_power_domain(port);
7304         if (IS_CHERRYVIEW(dev_priv)) {
7305                 if (port == PORT_D)
7306                         intel_encoder->crtc_mask = 1 << 2;
7307                 else
7308                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7309         } else {
7310                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7311         }
7312         intel_encoder->cloneable = 0;
7313         intel_encoder->port = port;
7314
7315         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7316
7317         if (port != PORT_A)
7318                 intel_infoframe_init(intel_dig_port);
7319
7320         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7321         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7322                 goto err_init_connector;
7323
7324         return true;
7325
7326 err_init_connector:
7327         drm_encoder_cleanup(encoder);
7328 err_encoder_init:
7329         kfree(intel_connector);
7330 err_connector_alloc:
7331         kfree(intel_dig_port);
7332         return false;
7333 }
7334
7335 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7336 {
7337         struct intel_encoder *encoder;
7338
7339         for_each_intel_encoder(&dev_priv->drm, encoder) {
7340                 struct intel_dp *intel_dp;
7341
7342                 if (encoder->type != INTEL_OUTPUT_DDI)
7343                         continue;
7344
7345                 intel_dp = enc_to_intel_dp(&encoder->base);
7346
7347                 if (!intel_dp->can_mst)
7348                         continue;
7349
7350                 if (intel_dp->is_mst)
7351                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7352         }
7353 }
7354
7355 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7356 {
7357         struct intel_encoder *encoder;
7358
7359         for_each_intel_encoder(&dev_priv->drm, encoder) {
7360                 struct intel_dp *intel_dp;
7361                 int ret;
7362
7363                 if (encoder->type != INTEL_OUTPUT_DDI)
7364                         continue;
7365
7366                 intel_dp = enc_to_intel_dp(&encoder->base);
7367
7368                 if (!intel_dp->can_mst)
7369                         continue;
7370
7371                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7372                 if (ret) {
7373                         intel_dp->is_mst = false;
7374                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7375                                                         false);
7376                 }
7377         }
7378 }