drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dp_tunnel.h>
  40 #include <drm/display/drm_dsc_helper.h>
  41 #include <drm/display/drm_hdmi_helper.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_crtc.h>
  44 #include <drm/drm_edid.h>
  45 #include <drm/drm_probe_helper.h>
  46
  47 #include "g4x_dp.h"
  48 #include "i915_drv.h"
  49 #include "i915_irq.h"
  50 #include "i915_reg.h"
  51 #include "intel_atomic.h"
  52 #include "intel_audio.h"
  53 #include "intel_backlight.h"
  54 #include "intel_combo_phy_regs.h"
  55 #include "intel_connector.h"
  56 #include "intel_crtc.h"
  57 #include "intel_cx0_phy.h"
  58 #include "intel_ddi.h"
  59 #include "intel_de.h"
  60 #include "intel_display_driver.h"
  61 #include "intel_display_types.h"
  62 #include "intel_dp.h"
  63 #include "intel_dp_aux.h"
  64 #include "intel_dp_hdcp.h"
  65 #include "intel_dp_link_training.h"
  66 #include "intel_dp_mst.h"
  67 #include "intel_dp_tunnel.h"
  68 #include "intel_dpio_phy.h"
  69 #include "intel_dpll.h"
  70 #include "intel_fifo_underrun.h"
  71 #include "intel_hdcp.h"
  72 #include "intel_hdmi.h"
  73 #include "intel_hotplug.h"
  74 #include "intel_hotplug_irq.h"
  75 #include "intel_lspcon.h"
  76 #include "intel_lvds.h"
  77 #include "intel_panel.h"
  78 #include "intel_pch_display.h"
  79 #include "intel_pps.h"
  80 #include "intel_psr.h"
  81 #include "intel_tc.h"
  82 #include "intel_vdsc.h"
  83 #include "intel_vrr.h"
  84 #include "intel_crtc_state_dump.h"
  85
  86 /* DP DSC throughput values used for slice count calculations KPixels/s */
  87 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  88 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  89 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  90
  91 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
  92 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
  93
  94 /* Compliance test status bits  */
  95 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  96 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  97 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  98 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  99
 100
 101 /* Constants for DP DSC configurations */
 102 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 103
 104 /* With Single pipe configuration, HW is capable of supporting maximum
 105  * of 4 slices per line.
 106  */
 107 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 108
 109 /**
 110  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 111  * @intel_dp: DP struct
 112  *
 113  * If a CPU or PCH DP output is attached to an eDP panel, this function
 114  * will return true, and false otherwise.
 115  *
 116  * This function is not safe to use prior to encoder type being set.
 117  */
 118 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 119 {
 120         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 121
 122         return dig_port->base.type == INTEL_OUTPUT_EDP;
 123 }
 124
 125 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 126
 127 /* Is link rate UHBR and thus 128b/132b? */
 128 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 129 {
 130         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 131 }
 132
 133 /**
 134  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 135  * @rate: link rate in 10kbit/s units
 136  *
 137  * Returns the link symbol size in bits/symbol units depending on the link
 138  * rate -> channel coding.
 139  */
 140 int intel_dp_link_symbol_size(int rate)
 141 {
 142         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 143 }
 144
 145 /**
 146  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 147  * @rate: link rate in 10kbit/s units
 148  *
 149  * Returns the link symbol clock frequency in kHz units depending on the
 150  * link rate and channel coding.
 151  */
 152 int intel_dp_link_symbol_clock(int rate)
 153 {
 154         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 155 }
 156
 157 static int max_dprx_rate(struct intel_dp *intel_dp)
 158 {
 159         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 160                 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
 161
 162         return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 163 }
 164
 165 static int max_dprx_lane_count(struct intel_dp *intel_dp)
 166 {
 167         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 168                 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
 169
 170         return drm_dp_max_lane_count(intel_dp->dpcd);
 171 }
 172
 173 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 174 {
 175         intel_dp->sink_rates[0] = 162000;
 176         intel_dp->num_sink_rates = 1;
 177 }
 178
 179 /* update sink rates from dpcd */
 180 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 181 {
 182         static const int dp_rates[] = {
 183                 162000, 270000, 540000, 810000
 184         };
 185         int i, max_rate;
 186         int max_lttpr_rate;
 187
 188         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 189                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 190                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 191
 192                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 193                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 194
 195                 return;
 196         }
 197
 198         /*
 199          * Sink rates for 8b/10b.
 200          */
 201         max_rate = max_dprx_rate(intel_dp);
 202         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 203         if (max_lttpr_rate)
 204                 max_rate = min(max_rate, max_lttpr_rate);
 205
 206         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 207                 if (dp_rates[i] > max_rate)
 208                         break;
 209                 intel_dp->sink_rates[i] = dp_rates[i];
 210         }
 211
 212         /*
 213          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 214          * rates and 10 Gbps.
 215          */
 216         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 217                 u8 uhbr_rates = 0;
 218
 219                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 220
 221                 drm_dp_dpcd_readb(&intel_dp->aux,
 222                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 223
 224                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 225                         /* We have a repeater */
 226                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 227                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 228                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 229                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 230                                 /* Repeater supports 128b/132b, valid UHBR rates */
 231                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 232                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 233                         } else {
 234                                 /* Does not support 128b/132b */
 235                                 uhbr_rates = 0;
 236                         }
 237                 }
 238
 239                 if (uhbr_rates & DP_UHBR10)
 240                         intel_dp->sink_rates[i++] = 1000000;
 241                 if (uhbr_rates & DP_UHBR13_5)
 242                         intel_dp->sink_rates[i++] = 1350000;
 243                 if (uhbr_rates & DP_UHBR20)
 244                         intel_dp->sink_rates[i++] = 2000000;
 245         }
 246
 247         intel_dp->num_sink_rates = i;
 248 }
 249
 250 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 251 {
 252         struct intel_connector *connector = intel_dp->attached_connector;
 253         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 254         struct intel_encoder *encoder = &intel_dig_port->base;
 255
 256         intel_dp_set_dpcd_sink_rates(intel_dp);
 257
 258         if (intel_dp->num_sink_rates)
 259                 return;
 260
 261         drm_err(&dp_to_i915(intel_dp)->drm,
 262                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 263                 connector->base.base.id, connector->base.name,
 264                 encoder->base.base.id, encoder->base.name);
 265
 266         intel_dp_set_default_sink_rates(intel_dp);
 267 }
 268
 269 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 270 {
 271         intel_dp->max_sink_lane_count = 1;
 272 }
 273
 274 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 275 {
 276         struct intel_connector *connector = intel_dp->attached_connector;
 277         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 278         struct intel_encoder *encoder = &intel_dig_port->base;
 279
 280         intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
 281
 282         switch (intel_dp->max_sink_lane_count) {
 283         case 1:
 284         case 2:
 285         case 4:
 286                 return;
 287         }
 288
 289         drm_err(&dp_to_i915(intel_dp)->drm,
 290                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 291                 connector->base.base.id, connector->base.name,
 292                 encoder->base.base.id, encoder->base.name,
 293                 intel_dp->max_sink_lane_count);
 294
 295         intel_dp_set_default_max_sink_lane_count(intel_dp);
 296 }
 297
 298 /* Get length of rates array potentially limited by max_rate. */
 299 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 300 {
 301         int i;
 302
 303         /* Limit results by potentially reduced max rate */
 304         for (i = 0; i < len; i++) {
 305                 if (rates[len - i - 1] <= max_rate)
 306                         return len - i;
 307         }
 308
 309         return 0;
 310 }
 311
 312 /* Get length of common rates array potentially limited by max_rate. */
 313 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 314                                           int max_rate)
 315 {
 316         return intel_dp_rate_limit_len(intel_dp->common_rates,
 317                                        intel_dp->num_common_rates, max_rate);
 318 }
 319
 320 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 321 {
 322         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 323                         index < 0 || index >= intel_dp->num_common_rates))
 324                 return 162000;
 325
 326         return intel_dp->common_rates[index];
 327 }
 328
 329 /* Theoretical max between source and sink */
 330 int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 331 {
 332         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 333 }
 334
 335 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 336 {
 337         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 338         int max_lanes = dig_port->max_lanes;
 339
 340         if (vbt_max_lanes)
 341                 max_lanes = min(max_lanes, vbt_max_lanes);
 342
 343         return max_lanes;
 344 }
 345
 346 /* Theoretical max between source and sink */
 347 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 348 {
 349         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 350         int source_max = intel_dp_max_source_lane_count(dig_port);
 351         int sink_max = intel_dp->max_sink_lane_count;
 352         int lane_max = intel_tc_port_max_lane_count(dig_port);
 353         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 354
 355         if (lttpr_max)
 356                 sink_max = min(sink_max, lttpr_max);
 357
 358         return min3(source_max, sink_max, lane_max);
 359 }
 360
 361 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 362 {
 363         switch (intel_dp->max_link_lane_count) {
 364         case 1:
 365         case 2:
 366         case 4:
 367                 return intel_dp->max_link_lane_count;
 368         default:
 369                 MISSING_CASE(intel_dp->max_link_lane_count);
 370                 return 1;
 371         }
 372 }
 373
 374 /*
 375  * The required data bandwidth for a mode with given pixel clock and bpp. This
 376  * is the required net bandwidth independent of the data bandwidth efficiency.
 377  *
 378  * TODO: check if callers of this functions should use
 379  * intel_dp_effective_data_rate() instead.
 380  */
 381 int
 382 intel_dp_link_required(int pixel_clock, int bpp)
 383 {
 384         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 385         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 386 }
 387
 388 /**
 389  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 390  * @pixel_clock: pixel clock in kHz
 391  * @bpp_x16: bits per pixel .4 fixed point format
 392  * @bw_overhead: BW allocation overhead in 1ppm units
 393  *
 394  * Return the effective pixel data rate in kB/sec units taking into account
 395  * the provided SSC, FEC, DSC BW allocation overhead.
 396  */
 397 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 398                                  int bw_overhead)
 399 {
 400         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 401                                 1000000 * 16 * 8);
 402 }
 403
 404 /**
 405  * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
 406  * @intel_dp: Intel DP object
 407  * @max_dprx_rate: Maximum data rate of the DPRX
 408  * @max_dprx_lanes: Maximum lane count of the DPRX
 409  *
 410  * Calculate the maximum data rate for the provided link parameters taking into
 411  * account any BW limitations by a DP tunnel attached to @intel_dp.
 412  *
 413  * Returns the maximum data rate in kBps units.
 414  */
 415 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
 416                                 int max_dprx_rate, int max_dprx_lanes)
 417 {
 418         int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
 419
 420         if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
 421                 max_rate = min(max_rate,
 422                                drm_dp_tunnel_available_bw(intel_dp->tunnel));
 423
 424         return max_rate;
 425 }
 426
 427 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 428 {
 429         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 430         struct intel_encoder *encoder = &intel_dig_port->base;
 431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 432
 433         return DISPLAY_VER(dev_priv) >= 12 ||
 434                 (DISPLAY_VER(dev_priv) == 11 &&
 435                  encoder->port != PORT_A);
 436 }
 437
 438 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 439 {
 440         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 441 }
 442
 443 static int icl_max_source_rate(struct intel_dp *intel_dp)
 444 {
 445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 446         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 447         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 448
 449         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 450                 return 540000;
 451
 452         return 810000;
 453 }
 454
 455 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 456 {
 457         if (intel_dp_is_edp(intel_dp))
 458                 return 540000;
 459
 460         return 810000;
 461 }
 462
 463 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 464 {
 465         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 466         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 467         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 468
 469         if (intel_is_c10phy(i915, phy))
 470                 return 810000;
 471
 472         return 2000000;
 473 }
 474
 475 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 476 {
 477         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 478         int max_rate;
 479
 480         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 481
 482         if (intel_dp_is_edp(intel_dp)) {
 483                 struct intel_connector *connector = intel_dp->attached_connector;
 484                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 485
 486                 if (max_rate && edp_max_rate)
 487                         max_rate = min(max_rate, edp_max_rate);
 488                 else if (edp_max_rate)
 489                         max_rate = edp_max_rate;
 490         }
 491
 492         return max_rate;
 493 }
 494
 495 static void
 496 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 497 {
 498         /* The values must be in increasing order */
 499         static const int mtl_rates[] = {
 500                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 501                 810000, 1000000, 1350000, 2000000,
 502         };
 503         static const int icl_rates[] = {
 504                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 505                 1000000, 1350000,
 506         };
 507         static const int bxt_rates[] = {
 508                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 509         };
 510         static const int skl_rates[] = {
 511                 162000, 216000, 270000, 324000, 432000, 540000
 512         };
 513         static const int hsw_rates[] = {
 514                 162000, 270000, 540000
 515         };
 516         static const int g4x_rates[] = {
 517                 162000, 270000
 518         };
 519         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 520         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 521         const int *source_rates;
 522         int size, max_rate = 0, vbt_max_rate;
 523
 524         /* This should only be done once */
 525         drm_WARN_ON(&dev_priv->drm,
 526                     intel_dp->source_rates || intel_dp->num_source_rates);
 527
 528         if (DISPLAY_VER(dev_priv) >= 14) {
 529                 source_rates = mtl_rates;
 530                 size = ARRAY_SIZE(mtl_rates);
 531                 max_rate = mtl_max_source_rate(intel_dp);
 532         } else if (DISPLAY_VER(dev_priv) >= 11) {
 533                 source_rates = icl_rates;
 534                 size = ARRAY_SIZE(icl_rates);
 535                 if (IS_DG2(dev_priv))
 536                         max_rate = dg2_max_source_rate(intel_dp);
 537                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 538                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 539                         max_rate = 810000;
 540                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 541                         max_rate = ehl_max_source_rate(intel_dp);
 542                 else
 543                         max_rate = icl_max_source_rate(intel_dp);
 544         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 545                 source_rates = bxt_rates;
 546                 size = ARRAY_SIZE(bxt_rates);
 547         } else if (DISPLAY_VER(dev_priv) == 9) {
 548                 source_rates = skl_rates;
 549                 size = ARRAY_SIZE(skl_rates);
 550         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 551                    IS_BROADWELL(dev_priv)) {
 552                 source_rates = hsw_rates;
 553                 size = ARRAY_SIZE(hsw_rates);
 554         } else {
 555                 source_rates = g4x_rates;
 556                 size = ARRAY_SIZE(g4x_rates);
 557         }
 558
 559         vbt_max_rate = vbt_max_link_rate(intel_dp);
 560         if (max_rate && vbt_max_rate)
 561                 max_rate = min(max_rate, vbt_max_rate);
 562         else if (vbt_max_rate)
 563                 max_rate = vbt_max_rate;
 564
 565         if (max_rate)
 566                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 567
 568         intel_dp->source_rates = source_rates;
 569         intel_dp->num_source_rates = size;
 570 }
 571
 572 static int intersect_rates(const int *source_rates, int source_len,
 573                            const int *sink_rates, int sink_len,
 574                            int *common_rates)
 575 {
 576         int i = 0, j = 0, k = 0;
 577
 578         while (i < source_len && j < sink_len) {
 579                 if (source_rates[i] == sink_rates[j]) {
 580                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 581                                 return k;
 582                         common_rates[k] = source_rates[i];
 583                         ++k;
 584                         ++i;
 585                         ++j;
 586                 } else if (source_rates[i] < sink_rates[j]) {
 587                         ++i;
 588                 } else {
 589                         ++j;
 590                 }
 591         }
 592         return k;
 593 }
 594
 595 /* return index of rate in rates array, or -1 if not found */
 596 static int intel_dp_rate_index(const int *rates, int len, int rate)
 597 {
 598         int i;
 599
 600         for (i = 0; i < len; i++)
 601                 if (rate == rates[i])
 602                         return i;
 603
 604         return -1;
 605 }
 606
 607 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 608 {
 609         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 610
 611         drm_WARN_ON(&i915->drm,
 612                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 613
 614         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 615                                                      intel_dp->num_source_rates,
 616                                                      intel_dp->sink_rates,
 617                                                      intel_dp->num_sink_rates,
 618                                                      intel_dp->common_rates);
 619
 620         /* Paranoia, there should always be something in common. */
 621         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 622                 intel_dp->common_rates[0] = 162000;
 623                 intel_dp->num_common_rates = 1;
 624         }
 625 }
 626
 627 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 628                                        u8 lane_count)
 629 {
 630         /*
 631          * FIXME: we need to synchronize the current link parameters with
 632          * hardware readout. Currently fast link training doesn't work on
 633          * boot-up.
 634          */
 635         if (link_rate == 0 ||
 636             link_rate > intel_dp->max_link_rate)
 637                 return false;
 638
 639         if (lane_count == 0 ||
 640             lane_count > intel_dp_max_lane_count(intel_dp))
 641                 return false;
 642
 643         return true;
 644 }
 645
 646 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 647                                                      int link_rate,
 648                                                      u8 lane_count)
 649 {
 650         /* FIXME figure out what we actually want here */
 651         const struct drm_display_mode *fixed_mode =
 652                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 653         int mode_rate, max_rate;
 654
 655         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 656         max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
 657         if (mode_rate > max_rate)
 658                 return false;
 659
 660         return true;
 661 }
 662
 663 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 664                                             int link_rate, u8 lane_count)
 665 {
 666         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 667         int index;
 668
 669         /*
 670          * TODO: Enable fallback on MST links once MST link compute can handle
 671          * the fallback params.
 672          */
 673         if (intel_dp->is_mst) {
 674                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 675                 return -1;
 676         }
 677
 678         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 679                 drm_dbg_kms(&i915->drm,
 680                             "Retrying Link training for eDP with max parameters\n");
 681                 intel_dp->use_max_params = true;
 682                 return 0;
 683         }
 684
 685         index = intel_dp_rate_index(intel_dp->common_rates,
 686                                     intel_dp->num_common_rates,
 687                                     link_rate);
 688         if (index > 0) {
 689                 if (intel_dp_is_edp(intel_dp) &&
 690                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 691                                                               intel_dp_common_rate(intel_dp, index - 1),
 692                                                               lane_count)) {
 693                         drm_dbg_kms(&i915->drm,
 694                                     "Retrying Link training for eDP with same parameters\n");
 695                         return 0;
 696                 }
 697                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 698                 intel_dp->max_link_lane_count = lane_count;
 699         } else if (lane_count > 1) {
 700                 if (intel_dp_is_edp(intel_dp) &&
 701                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 702                                                               intel_dp_max_common_rate(intel_dp),
 703                                                               lane_count >> 1)) {
 704                         drm_dbg_kms(&i915->drm,
 705                                     "Retrying Link training for eDP with same parameters\n");
 706                         return 0;
 707                 }
 708                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 709                 intel_dp->max_link_lane_count = lane_count >> 1;
 710         } else {
 711                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 712                 return -1;
 713         }
 714
 715         return 0;
 716 }
 717
 718 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 719 {
 720         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 721                        1000000U);
 722 }
 723
 724 int intel_dp_bw_fec_overhead(bool fec_enabled)
 725 {
 726         /*
 727          * TODO: Calculate the actual overhead for a given mode.
 728          * The hard-coded 1/0.972261=2.853% overhead factor
 729          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 730          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 731          * which has a DSC overhead of up to ~0.2%, but may not be
 732          * enough for a 1024 width mode where this is ~0.8% (on a 4
 733          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 734          */
 735         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 736 }
 737
 738 static int
 739 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 740 {
 741         if (DISPLAY_VER(i915) >= 13)
 742                 return 17280 * 8;
 743         else if (DISPLAY_VER(i915) >= 11)
 744                 return 7680 * 8;
 745         else
 746                 return 6144 * 8;
 747 }
 748
 749 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 750 {
 751         u32 bits_per_pixel = bpp;
 752         int i;
 753
 754         /* Error out if the max bpp is less than smallest allowed valid bpp */
 755         if (bits_per_pixel < valid_dsc_bpp[0]) {
 756                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 757                             bits_per_pixel, valid_dsc_bpp[0]);
 758                 return 0;
 759         }
 760
 761         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 762         if (DISPLAY_VER(i915) >= 13) {
 763                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 764
 765                 /*
 766                  * According to BSpec, 27 is the max DSC output bpp,
 767                  * 8 is the min DSC output bpp.
 768                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 769                  * if it is required to oompress up to bpp < 8, means we can't do
 770                  * that and probably means we can't fit the required mode, even with
 771                  * DSC enabled.
 772                  */
 773                 if (bits_per_pixel < 8) {
 774                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 775                                     bits_per_pixel);
 776                         return 0;
 777                 }
 778                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 779         } else {
 780                 /* Find the nearest match in the array of known BPPs from VESA */
 781                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 782                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 783                                 break;
 784                 }
 785                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 786                             bits_per_pixel, valid_dsc_bpp[i]);
 787
 788                 bits_per_pixel = valid_dsc_bpp[i];
 789         }
 790
 791         return bits_per_pixel;
 792 }
 793
 794 static
 795 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 796                                        u32 mode_clock, u32 mode_hdisplay,
 797                                        bool bigjoiner)
 798 {
 799         u32 max_bpp_small_joiner_ram;
 800
 801         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 802         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 803
 804         if (bigjoiner) {
 805                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 806                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 807                 int ppc = 2;
 808                 u32 max_bpp_bigjoiner =
 809                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 810                         intel_dp_mode_to_fec_clock(mode_clock);
 811
 812                 max_bpp_small_joiner_ram *= 2;
 813
 814                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 815         }
 816
 817         return max_bpp_small_joiner_ram;
 818 }
 819
 820 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 821                                         u32 link_clock, u32 lane_count,
 822                                         u32 mode_clock, u32 mode_hdisplay,
 823                                         bool bigjoiner,
 824                                         enum intel_output_format output_format,
 825                                         u32 pipe_bpp,
 826                                         u32 timeslots)
 827 {
 828         u32 bits_per_pixel, joiner_max_bpp;
 829
 830         /*
 831          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 832          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 833          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 834          * for MST -> TimeSlots has to be calculated, based on mode requirements
 835          *
 836          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 837          * To support the given mode:
 838          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 839          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 840          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 841          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 842          *                     (ModeClock / FEC Overhead)
 843          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 844          *                     (ModeClock / FEC Overhead * 8)
 845          */
 846         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 847                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 848
 849         /* Bandwidth required for 420 is half, that of 444 format */
 850         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 851                 bits_per_pixel *= 2;
 852
 853         /*
 854          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 855          * supported PPS value can be 63.9375 and with the further
 856          * mention that for 420, 422 formats, bpp should be programmed double
 857          * the target bpp restricting our target bpp to be 31.9375 at max.
 858          */
 859         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 860                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 861
 862         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 863                                 "total bw %u pixel clock %u\n",
 864                                 bits_per_pixel, timeslots,
 865                                 (link_clock * lane_count * 8),
 866                                 intel_dp_mode_to_fec_clock(mode_clock));
 867
 868         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 869                                                             mode_hdisplay, bigjoiner);
 870         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 871
 872         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 873
 874         return bits_per_pixel;
 875 }
 876
 877 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 878                                 int mode_clock, int mode_hdisplay,
 879                                 bool bigjoiner)
 880 {
 881         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 882         u8 min_slice_count, i;
 883         int max_slice_width;
 884
 885         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 886                 min_slice_count = DIV_ROUND_UP(mode_clock,
 887                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 888         else
 889                 min_slice_count = DIV_ROUND_UP(mode_clock,
 890                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 891
 892         /*
 893          * Due to some DSC engine BW limitations, we need to enable second
 894          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 895          */
 896         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 897                 min_slice_count = max_t(u8, min_slice_count, 2);
 898
 899         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 900         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 901                 drm_dbg_kms(&i915->drm,
 902                             "Unsupported slice width %d by DP DSC Sink device\n",
 903                             max_slice_width);
 904                 return 0;
 905         }
 906         /* Also take into account max slice width */
 907         min_slice_count = max_t(u8, min_slice_count,
 908                                 DIV_ROUND_UP(mode_hdisplay,
 909                                              max_slice_width));
 910
 911         /* Find the closest match to the valid slice count values */
 912         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 913                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 914
 915                 if (test_slice_count >
 916                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 917                         break;
 918
 919                 /* big joiner needs small joiner to be enabled */
 920                 if (bigjoiner && test_slice_count < 4)
 921                         continue;
 922
 923                 if (min_slice_count <= test_slice_count)
 924                         return test_slice_count;
 925         }
 926
 927         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 928                     min_slice_count);
 929         return 0;
 930 }
 931
 932 static bool source_can_output(struct intel_dp *intel_dp,
 933                               enum intel_output_format format)
 934 {
 935         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 936
 937         switch (format) {
 938         case INTEL_OUTPUT_FORMAT_RGB:
 939                 return true;
 940
 941         case INTEL_OUTPUT_FORMAT_YCBCR444:
 942                 /*
 943                  * No YCbCr output support on gmch platforms.
 944                  * Also, ILK doesn't seem capable of DP YCbCr output.
 945                  * The displayed image is severly corrupted. SNB+ is fine.
 946                  */
 947                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 948
 949         case INTEL_OUTPUT_FORMAT_YCBCR420:
 950                 /* Platform < Gen 11 cannot output YCbCr420 format */
 951                 return DISPLAY_VER(i915) >= 11;
 952
 953         default:
 954                 MISSING_CASE(format);
 955                 return false;
 956         }
 957 }
 958
 959 static bool
 960 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 961                          enum intel_output_format sink_format)
 962 {
 963         if (!drm_dp_is_branch(intel_dp->dpcd))
 964                 return false;
 965
 966         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 967                 return intel_dp->dfp.rgb_to_ycbcr;
 968
 969         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 970                 return intel_dp->dfp.rgb_to_ycbcr &&
 971                         intel_dp->dfp.ycbcr_444_to_420;
 972
 973         return false;
 974 }
 975
 976 static bool
 977 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 978                               enum intel_output_format sink_format)
 979 {
 980         if (!drm_dp_is_branch(intel_dp->dpcd))
 981                 return false;
 982
 983         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 984                 return intel_dp->dfp.ycbcr_444_to_420;
 985
 986         return false;
 987 }
 988
 989 static bool
 990 dfp_can_convert(struct intel_dp *intel_dp,
 991                 enum intel_output_format output_format,
 992                 enum intel_output_format sink_format)
 993 {
 994         switch (output_format) {
 995         case INTEL_OUTPUT_FORMAT_RGB:
 996                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
 997         case INTEL_OUTPUT_FORMAT_YCBCR444:
 998                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
 999         default:
1000                 MISSING_CASE(output_format);
1001                 return false;
1002         }
1003
1004         return false;
1005 }
1006
1007 static enum intel_output_format
1008 intel_dp_output_format(struct intel_connector *connector,
1009                        enum intel_output_format sink_format)
1010 {
1011         struct intel_dp *intel_dp = intel_attached_dp(connector);
1012         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1013         enum intel_output_format force_dsc_output_format =
1014                 intel_dp->force_dsc_output_format;
1015         enum intel_output_format output_format;
1016         if (force_dsc_output_format) {
1017                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1018                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1019                      sink_format != force_dsc_output_format ||
1020                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1021                         return force_dsc_output_format;
1022
1023                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1024         }
1025
1026         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1027             dfp_can_convert_from_rgb(intel_dp, sink_format))
1028                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1029
1030         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1031                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1032                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1033
1034         else
1035                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1036
1037         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1038
1039         return output_format;
1040 }
1041
1042 int intel_dp_min_bpp(enum intel_output_format output_format)
1043 {
1044         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1045                 return 6 * 3;
1046         else
1047                 return 8 * 3;
1048 }
1049
1050 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1051 {
1052         /*
1053          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1054          * format of the number of bytes per pixel will be half the number
1055          * of bytes of RGB pixel.
1056          */
1057         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1058                 bpp /= 2;
1059
1060         return bpp;
1061 }
1062
1063 static enum intel_output_format
1064 intel_dp_sink_format(struct intel_connector *connector,
1065                      const struct drm_display_mode *mode)
1066 {
1067         const struct drm_display_info *info = &connector->base.display_info;
1068
1069         if (drm_mode_is_420_only(info, mode))
1070                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1071
1072         return INTEL_OUTPUT_FORMAT_RGB;
1073 }
1074
1075 static int
1076 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1077                              const struct drm_display_mode *mode)
1078 {
1079         enum intel_output_format output_format, sink_format;
1080
1081         sink_format = intel_dp_sink_format(connector, mode);
1082
1083         output_format = intel_dp_output_format(connector, sink_format);
1084
1085         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1086 }
1087
1088 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1089                                   int hdisplay)
1090 {
1091         /*
1092          * Older platforms don't like hdisplay==4096 with DP.
1093          *
1094          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1095          * and frame counter increment), but we don't get vblank interrupts,
1096          * and the pipe underruns immediately. The link also doesn't seem
1097          * to get trained properly.
1098          *
1099          * On CHV the vblank interrupts don't seem to disappear but
1100          * otherwise the symptoms are similar.
1101          *
1102          * TODO: confirm the behaviour on HSW+
1103          */
1104         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1105 }
1106
1107 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1108 {
1109         struct intel_connector *connector = intel_dp->attached_connector;
1110         const struct drm_display_info *info = &connector->base.display_info;
1111         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1112
1113         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1114         if (max_tmds_clock && info->max_tmds_clock)
1115                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1116
1117         return max_tmds_clock;
1118 }
1119
1120 static enum drm_mode_status
1121 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1122                           int clock, int bpc,
1123                           enum intel_output_format sink_format,
1124                           bool respect_downstream_limits)
1125 {
1126         int tmds_clock, min_tmds_clock, max_tmds_clock;
1127
1128         if (!respect_downstream_limits)
1129                 return MODE_OK;
1130
1131         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1132
1133         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1134         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1135
1136         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1137                 return MODE_CLOCK_LOW;
1138
1139         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1140                 return MODE_CLOCK_HIGH;
1141
1142         return MODE_OK;
1143 }
1144
1145 static enum drm_mode_status
1146 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1147                                const struct drm_display_mode *mode,
1148                                int target_clock)
1149 {
1150         struct intel_dp *intel_dp = intel_attached_dp(connector);
1151         const struct drm_display_info *info = &connector->base.display_info;
1152         enum drm_mode_status status;
1153         enum intel_output_format sink_format;
1154
1155         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1156         if (intel_dp->dfp.pcon_max_frl_bw) {
1157                 int target_bw;
1158                 int max_frl_bw;
1159                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1160
1161                 target_bw = bpp * target_clock;
1162
1163                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1164
1165                 /* converting bw from Gbps to Kbps*/
1166                 max_frl_bw = max_frl_bw * 1000000;
1167
1168                 if (target_bw > max_frl_bw)
1169                         return MODE_CLOCK_HIGH;
1170
1171                 return MODE_OK;
1172         }
1173
1174         if (intel_dp->dfp.max_dotclock &&
1175             target_clock > intel_dp->dfp.max_dotclock)
1176                 return MODE_CLOCK_HIGH;
1177
1178         sink_format = intel_dp_sink_format(connector, mode);
1179
1180         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1181         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1182                                            8, sink_format, true);
1183
1184         if (status != MODE_OK) {
1185                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1186                     !connector->base.ycbcr_420_allowed ||
1187                     !drm_mode_is_420_also(info, mode))
1188                         return status;
1189                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1190                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1191                                                    8, sink_format, true);
1192                 if (status != MODE_OK)
1193                         return status;
1194         }
1195
1196         return MODE_OK;
1197 }
1198
1199 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1200                              int hdisplay, int clock)
1201 {
1202         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1203         struct intel_connector *connector = intel_dp->attached_connector;
1204
1205         if (!intel_dp_can_bigjoiner(intel_dp))
1206                 return false;
1207
1208         return clock > i915->max_dotclk_freq || hdisplay > 5120 ||
1209                connector->force_bigjoiner_enable;
1210 }
1211
1212 static enum drm_mode_status
1213 intel_dp_mode_valid(struct drm_connector *_connector,
1214                     struct drm_display_mode *mode)
1215 {
1216         struct intel_connector *connector = to_intel_connector(_connector);
1217         struct intel_dp *intel_dp = intel_attached_dp(connector);
1218         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1219         const struct drm_display_mode *fixed_mode;
1220         int target_clock = mode->clock;
1221         int max_rate, mode_rate, max_lanes, max_link_clock;
1222         int max_dotclk = dev_priv->max_dotclk_freq;
1223         u16 dsc_max_compressed_bpp = 0;
1224         u8 dsc_slice_count = 0;
1225         enum drm_mode_status status;
1226         bool dsc = false, bigjoiner = false;
1227
1228         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1229         if (status != MODE_OK)
1230                 return status;
1231
1232         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1233                 return MODE_H_ILLEGAL;
1234
1235         fixed_mode = intel_panel_fixed_mode(connector, mode);
1236         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1237                 status = intel_panel_mode_valid(connector, mode);
1238                 if (status != MODE_OK)
1239                         return status;
1240
1241                 target_clock = fixed_mode->clock;
1242         }
1243
1244         if (mode->clock < 10000)
1245                 return MODE_CLOCK_LOW;
1246
1247         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1248                 bigjoiner = true;
1249                 max_dotclk *= 2;
1250         }
1251         if (target_clock > max_dotclk)
1252                 return MODE_CLOCK_HIGH;
1253
1254         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1255                 return MODE_H_ILLEGAL;
1256
1257         max_link_clock = intel_dp_max_link_rate(intel_dp);
1258         max_lanes = intel_dp_max_lane_count(intel_dp);
1259
1260         max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1261
1262         mode_rate = intel_dp_link_required(target_clock,
1263                                            intel_dp_mode_min_output_bpp(connector, mode));
1264
1265         if (HAS_DSC(dev_priv) &&
1266             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1267                 enum intel_output_format sink_format, output_format;
1268                 int pipe_bpp;
1269
1270                 sink_format = intel_dp_sink_format(connector, mode);
1271                 output_format = intel_dp_output_format(connector, sink_format);
1272                 /*
1273                  * TBD pass the connector BPC,
1274                  * for now U8_MAX so that max BPC on that platform would be picked
1275                  */
1276                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1277
1278                 /*
1279                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1280                  * integer value since we support only integer values of bpp.
1281                  */
1282                 if (intel_dp_is_edp(intel_dp)) {
1283                         dsc_max_compressed_bpp =
1284                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1285                         dsc_slice_count =
1286                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1287                                                                 true);
1288                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1289                         dsc_max_compressed_bpp =
1290                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1291                                                                     max_link_clock,
1292                                                                     max_lanes,
1293                                                                     target_clock,
1294                                                                     mode->hdisplay,
1295                                                                     bigjoiner,
1296                                                                     output_format,
1297                                                                     pipe_bpp, 64);
1298                         dsc_slice_count =
1299                                 intel_dp_dsc_get_slice_count(connector,
1300                                                              target_clock,
1301                                                              mode->hdisplay,
1302                                                              bigjoiner);
1303                 }
1304
1305                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1306         }
1307
1308         /*
1309          * Big joiner configuration needs DSC for TGL which is not true for
1310          * XE_LPD where uncompressed joiner is supported.
1311          */
1312         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1313                 return MODE_CLOCK_HIGH;
1314
1315         if (mode_rate > max_rate && !dsc)
1316                 return MODE_CLOCK_HIGH;
1317
1318         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1319         if (status != MODE_OK)
1320                 return status;
1321
1322         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1323 }
1324
1325 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1326 {
1327         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1328 }
1329
1330 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1331 {
1332         return DISPLAY_VER(i915) >= 10;
1333 }
1334
1335 static void snprintf_int_array(char *str, size_t len,
1336                                const int *array, int nelem)
1337 {
1338         int i;
1339
1340         str[0] = '\0';
1341
1342         for (i = 0; i < nelem; i++) {
1343                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1344                 if (r >= len)
1345                         return;
1346                 str += r;
1347                 len -= r;
1348         }
1349 }
1350
1351 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1352 {
1353         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1354         char str[128]; /* FIXME: too big for stack? */
1355
1356         if (!drm_debug_enabled(DRM_UT_KMS))
1357                 return;
1358
1359         snprintf_int_array(str, sizeof(str),
1360                            intel_dp->source_rates, intel_dp->num_source_rates);
1361         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1362
1363         snprintf_int_array(str, sizeof(str),
1364                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1365         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1366
1367         snprintf_int_array(str, sizeof(str),
1368                            intel_dp->common_rates, intel_dp->num_common_rates);
1369         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1370 }
1371
1372 int
1373 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1374 {
1375         int len;
1376
1377         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1378
1379         return intel_dp_common_rate(intel_dp, len - 1);
1380 }
1381
1382 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1383 {
1384         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1385         int i = intel_dp_rate_index(intel_dp->sink_rates,
1386                                     intel_dp->num_sink_rates, rate);
1387
1388         if (drm_WARN_ON(&i915->drm, i < 0))
1389                 i = 0;
1390
1391         return i;
1392 }
1393
1394 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1395                            u8 *link_bw, u8 *rate_select)
1396 {
1397         /* eDP 1.4 rate select method. */
1398         if (intel_dp->use_rate_select) {
1399                 *link_bw = 0;
1400                 *rate_select =
1401                         intel_dp_rate_select(intel_dp, port_clock);
1402         } else {
1403                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1404                 *rate_select = 0;
1405         }
1406 }
1407
1408 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1409 {
1410         struct intel_connector *connector = intel_dp->attached_connector;
1411
1412         return connector->base.display_info.is_hdmi;
1413 }
1414
1415 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1416                                          const struct intel_crtc_state *pipe_config)
1417 {
1418         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1419         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1420
1421         if (DISPLAY_VER(dev_priv) >= 12)
1422                 return true;
1423
1424         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1425                 return true;
1426
1427         return false;
1428 }
1429
1430 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1431                            const struct intel_connector *connector,
1432                            const struct intel_crtc_state *pipe_config)
1433 {
1434         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1435                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1436 }
1437
1438 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1439                                   const struct intel_crtc_state *crtc_state)
1440 {
1441         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1442                 return false;
1443
1444         return intel_dsc_source_support(crtc_state) &&
1445                 connector->dp.dsc_decompression_aux &&
1446                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1447 }
1448
1449 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1450                                      const struct intel_crtc_state *crtc_state,
1451                                      int bpc, bool respect_downstream_limits)
1452 {
1453         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1454
1455         /*
1456          * Current bpc could already be below 8bpc due to
1457          * FDI bandwidth constraints or other limits.
1458          * HDMI minimum is 8bpc however.
1459          */
1460         bpc = max(bpc, 8);
1461
1462         /*
1463          * We will never exceed downstream TMDS clock limits while
1464          * attempting deep color. If the user insists on forcing an
1465          * out of spec mode they will have to be satisfied with 8bpc.
1466          */
1467         if (!respect_downstream_limits)
1468                 bpc = 8;
1469
1470         for (; bpc >= 8; bpc -= 2) {
1471                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1472                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1473                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1474                                               respect_downstream_limits) == MODE_OK)
1475                         return bpc;
1476         }
1477
1478         return -EINVAL;
1479 }
1480
1481 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1482                             const struct intel_crtc_state *crtc_state,
1483                             bool respect_downstream_limits)
1484 {
1485         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1486         struct intel_connector *intel_connector = intel_dp->attached_connector;
1487         int bpp, bpc;
1488
1489         bpc = crtc_state->pipe_bpp / 3;
1490
1491         if (intel_dp->dfp.max_bpc)
1492                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1493
1494         if (intel_dp->dfp.min_tmds_clock) {
1495                 int max_hdmi_bpc;
1496
1497                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1498                                                          respect_downstream_limits);
1499                 if (max_hdmi_bpc < 0)
1500                         return 0;
1501
1502                 bpc = min(bpc, max_hdmi_bpc);
1503         }
1504
1505         bpp = bpc * 3;
1506         if (intel_dp_is_edp(intel_dp)) {
1507                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1508                 if (intel_connector->base.display_info.bpc == 0 &&
1509                     intel_connector->panel.vbt.edp.bpp &&
1510                     intel_connector->panel.vbt.edp.bpp < bpp) {
1511                         drm_dbg_kms(&dev_priv->drm,
1512                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1513                                     intel_connector->panel.vbt.edp.bpp);
1514                         bpp = intel_connector->panel.vbt.edp.bpp;
1515                 }
1516         }
1517
1518         return bpp;
1519 }
1520
1521 /* Adjust link config limits based on compliance test requests. */
1522 void
1523 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1524                                   struct intel_crtc_state *pipe_config,
1525                                   struct link_config_limits *limits)
1526 {
1527         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1528
1529         /* For DP Compliance we override the computed bpp for the pipe */
1530         if (intel_dp->compliance.test_data.bpc != 0) {
1531                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1532
1533                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1534                 pipe_config->dither_force_disable = bpp == 6 * 3;
1535
1536                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1537         }
1538
1539         /* Use values requested by Compliance Test Request */
1540         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1541                 int index;
1542
1543                 /* Validate the compliance test data since max values
1544                  * might have changed due to link train fallback.
1545                  */
1546                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1547                                                intel_dp->compliance.test_lane_count)) {
1548                         index = intel_dp_rate_index(intel_dp->common_rates,
1549                                                     intel_dp->num_common_rates,
1550                                                     intel_dp->compliance.test_link_rate);
1551                         if (index >= 0)
1552                                 limits->min_rate = limits->max_rate =
1553                                         intel_dp->compliance.test_link_rate;
1554                         limits->min_lane_count = limits->max_lane_count =
1555                                 intel_dp->compliance.test_lane_count;
1556                 }
1557         }
1558 }
1559
1560 static bool has_seamless_m_n(struct intel_connector *connector)
1561 {
1562         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1563
1564         /*
1565          * Seamless M/N reprogramming only implemented
1566          * for BDW+ double buffered M/N registers so far.
1567          */
1568         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1569                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1570 }
1571
1572 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1573                                const struct drm_connector_state *conn_state)
1574 {
1575         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1576         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1577
1578         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1579         if (has_seamless_m_n(connector))
1580                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1581         else
1582                 return adjusted_mode->crtc_clock;
1583 }
1584
1585 /* Optimize link config in order: max bpp, min clock, min lanes */
1586 static int
1587 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1588                                   struct intel_crtc_state *pipe_config,
1589                                   const struct drm_connector_state *conn_state,
1590                                   const struct link_config_limits *limits)
1591 {
1592         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1593         int mode_rate, link_rate, link_avail;
1594
1595         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1596              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1597              bpp -= 2 * 3) {
1598                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1599
1600                 mode_rate = intel_dp_link_required(clock, link_bpp);
1601
1602                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1603                         link_rate = intel_dp_common_rate(intel_dp, i);
1604                         if (link_rate < limits->min_rate ||
1605                             link_rate > limits->max_rate)
1606                                 continue;
1607
1608                         for (lane_count = limits->min_lane_count;
1609                              lane_count <= limits->max_lane_count;
1610                              lane_count <<= 1) {
1611                                 link_avail = intel_dp_max_link_data_rate(intel_dp,
1612                                                                          link_rate,
1613                                                                          lane_count);
1614
1615
1616                                 if (mode_rate <= link_avail) {
1617                                         pipe_config->lane_count = lane_count;
1618                                         pipe_config->pipe_bpp = bpp;
1619                                         pipe_config->port_clock = link_rate;
1620
1621                                         return 0;
1622                                 }
1623                         }
1624                 }
1625         }
1626
1627         return -EINVAL;
1628 }
1629
1630 static
1631 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1632 {
1633         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1634         if (DISPLAY_VER(i915) >= 12)
1635                 return 12;
1636         if (DISPLAY_VER(i915) == 11)
1637                 return 10;
1638
1639         return 0;
1640 }
1641
1642 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1643                                  u8 max_req_bpc)
1644 {
1645         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1646         int i, num_bpc;
1647         u8 dsc_bpc[3] = {};
1648         u8 dsc_max_bpc;
1649
1650         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1651
1652         if (!dsc_max_bpc)
1653                 return dsc_max_bpc;
1654
1655         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1656
1657         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1658                                                        dsc_bpc);
1659         for (i = 0; i < num_bpc; i++) {
1660                 if (dsc_max_bpc >= dsc_bpc[i])
1661                         return dsc_bpc[i] * 3;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1668 {
1669         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1670 }
1671
1672 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1673 {
1674         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1675                 DP_DSC_MINOR_SHIFT;
1676 }
1677
1678 static int intel_dp_get_slice_height(int vactive)
1679 {
1680         int slice_height;
1681
1682         /*
1683          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1684          * lines is an optimal slice height, but any size can be used as long as
1685          * vertical active integer multiple and maximum vertical slice count
1686          * requirements are met.
1687          */
1688         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1689                 if (vactive % slice_height == 0)
1690                         return slice_height;
1691
1692         /*
1693          * Highly unlikely we reach here as most of the resolutions will end up
1694          * finding appropriate slice_height in above loop but returning
1695          * slice_height as 2 here as it should work with all resolutions.
1696          */
1697         return 2;
1698 }
1699
1700 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1701                                        struct intel_crtc_state *crtc_state)
1702 {
1703         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1704         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1705         u8 line_buf_depth;
1706         int ret;
1707
1708         /*
1709          * RC_MODEL_SIZE is currently a constant across all configurations.
1710          *
1711          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1712          * DP_DSC_RC_BUF_SIZE for this.
1713          */
1714         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1715         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1716
1717         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1718
1719         ret = intel_dsc_compute_params(crtc_state);
1720         if (ret)
1721                 return ret;
1722
1723         vdsc_cfg->dsc_version_major =
1724                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1725                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1726         vdsc_cfg->dsc_version_minor =
1727                 min(intel_dp_source_dsc_version_minor(i915),
1728                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1729         if (vdsc_cfg->convert_rgb)
1730                 vdsc_cfg->convert_rgb =
1731                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1732                         DP_DSC_RGB;
1733
1734         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1735         if (!line_buf_depth) {
1736                 drm_dbg_kms(&i915->drm,
1737                             "DSC Sink Line Buffer Depth invalid\n");
1738                 return -EINVAL;
1739         }
1740
1741         if (vdsc_cfg->dsc_version_minor == 2)
1742                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1743                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1744         else
1745                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1746                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1747
1748         vdsc_cfg->block_pred_enable =
1749                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1750                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1751
1752         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1753 }
1754
1755 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1756                                          enum intel_output_format output_format)
1757 {
1758         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1759         u8 sink_dsc_format;
1760
1761         switch (output_format) {
1762         case INTEL_OUTPUT_FORMAT_RGB:
1763                 sink_dsc_format = DP_DSC_RGB;
1764                 break;
1765         case INTEL_OUTPUT_FORMAT_YCBCR444:
1766                 sink_dsc_format = DP_DSC_YCbCr444;
1767                 break;
1768         case INTEL_OUTPUT_FORMAT_YCBCR420:
1769                 if (min(intel_dp_source_dsc_version_minor(i915),
1770                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1771                         return false;
1772                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1773                 break;
1774         default:
1775                 return false;
1776         }
1777
1778         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1779 }
1780
1781 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1782                                             u32 lane_count, u32 mode_clock,
1783                                             enum intel_output_format output_format,
1784                                             int timeslots)
1785 {
1786         u32 available_bw, required_bw;
1787
1788         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1789         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1790
1791         return available_bw > required_bw;
1792 }
1793
1794 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1795                                    struct intel_crtc_state *pipe_config,
1796                                    struct link_config_limits *limits,
1797                                    u16 compressed_bppx16,
1798                                    int timeslots)
1799 {
1800         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1801         int link_rate, lane_count;
1802         int i;
1803
1804         for (i = 0; i < intel_dp->num_common_rates; i++) {
1805                 link_rate = intel_dp_common_rate(intel_dp, i);
1806                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1807                         continue;
1808
1809                 for (lane_count = limits->min_lane_count;
1810                      lane_count <= limits->max_lane_count;
1811                      lane_count <<= 1) {
1812                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1813                                                              lane_count, adjusted_mode->clock,
1814                                                              pipe_config->output_format,
1815                                                              timeslots))
1816                                 continue;
1817
1818                         pipe_config->lane_count = lane_count;
1819                         pipe_config->port_clock = link_rate;
1820
1821                         return 0;
1822                 }
1823         }
1824
1825         return -EINVAL;
1826 }
1827
1828 static
1829 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1830                                             struct intel_crtc_state *pipe_config,
1831                                             int bpc)
1832 {
1833         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1834
1835         if (max_bppx16)
1836                 return max_bppx16;
1837         /*
1838          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1839          * values as given in spec Table 2-157 DP v2.0
1840          */
1841         switch (pipe_config->output_format) {
1842         case INTEL_OUTPUT_FORMAT_RGB:
1843         case INTEL_OUTPUT_FORMAT_YCBCR444:
1844                 return (3 * bpc) << 4;
1845         case INTEL_OUTPUT_FORMAT_YCBCR420:
1846                 return (3 * (bpc / 2)) << 4;
1847         default:
1848                 MISSING_CASE(pipe_config->output_format);
1849                 break;
1850         }
1851
1852         return 0;
1853 }
1854
1855 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1856 {
1857         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1858         switch (pipe_config->output_format) {
1859         case INTEL_OUTPUT_FORMAT_RGB:
1860         case INTEL_OUTPUT_FORMAT_YCBCR444:
1861                 return 8;
1862         case INTEL_OUTPUT_FORMAT_YCBCR420:
1863                 return 6;
1864         default:
1865                 MISSING_CASE(pipe_config->output_format);
1866                 break;
1867         }
1868
1869         return 0;
1870 }
1871
1872 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1873                                          struct intel_crtc_state *pipe_config,
1874                                          int bpc)
1875 {
1876         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1877                                                        pipe_config, bpc) >> 4;
1878 }
1879
1880 static int dsc_src_min_compressed_bpp(void)
1881 {
1882         /* Min Compressed bpp supported by source is 8 */
1883         return 8;
1884 }
1885
1886 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1887 {
1888         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1889
1890         /*
1891          * Max Compressed bpp for Gen 13+ is 27bpp.
1892          * For earlier platform is 23bpp. (Bspec:49259).
1893          */
1894         if (DISPLAY_VER(i915) < 13)
1895                 return 23;
1896         else
1897                 return 27;
1898 }
1899
1900 /*
1901  * From a list of valid compressed bpps try different compressed bpp and find a
1902  * suitable link configuration that can support it.
1903  */
1904 static int
1905 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1906                             struct intel_crtc_state *pipe_config,
1907                             struct link_config_limits *limits,
1908                             int dsc_max_bpp,
1909                             int dsc_min_bpp,
1910                             int pipe_bpp,
1911                             int timeslots)
1912 {
1913         int i, ret;
1914
1915         /* Compressed BPP should be less than the Input DSC bpp */
1916         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1917
1918         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1919                 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1920                     valid_dsc_bpp[i] > dsc_max_bpp)
1921                         break;
1922
1923                 ret = dsc_compute_link_config(intel_dp,
1924                                               pipe_config,
1925                                               limits,
1926                                               valid_dsc_bpp[i] << 4,
1927                                               timeslots);
1928                 if (ret == 0) {
1929                         pipe_config->dsc.compressed_bpp_x16 =
1930                                 to_bpp_x16(valid_dsc_bpp[i]);
1931                         return 0;
1932                 }
1933         }
1934
1935         return -EINVAL;
1936 }
1937
1938 /*
1939  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1940  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1941  * link configuration is able to support that compressed bpp, if not we
1942  * step down and check for lower compressed bpp.
1943  */
1944 static int
1945 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1946                               const struct intel_connector *connector,
1947                               struct intel_crtc_state *pipe_config,
1948                               struct link_config_limits *limits,
1949                               int dsc_max_bpp,
1950                               int dsc_min_bpp,
1951                               int pipe_bpp,
1952                               int timeslots)
1953 {
1954         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1955         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956         u16 compressed_bppx16;
1957         u8 bppx16_step;
1958         int ret;
1959
1960         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1961                 bppx16_step = 16;
1962         else
1963                 bppx16_step = 16 / bppx16_incr;
1964
1965         /* Compressed BPP should be less than the Input DSC bpp */
1966         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1967         dsc_min_bpp = dsc_min_bpp << 4;
1968
1969         for (compressed_bppx16 = dsc_max_bpp;
1970              compressed_bppx16 >= dsc_min_bpp;
1971              compressed_bppx16 -= bppx16_step) {
1972                 if (intel_dp->force_dsc_fractional_bpp_en &&
1973                     !to_bpp_frac(compressed_bppx16))
1974                         continue;
1975                 ret = dsc_compute_link_config(intel_dp,
1976                                               pipe_config,
1977                                               limits,
1978                                               compressed_bppx16,
1979                                               timeslots);
1980                 if (ret == 0) {
1981                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1982                         if (intel_dp->force_dsc_fractional_bpp_en &&
1983                             to_bpp_frac(compressed_bppx16))
1984                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1985
1986                         return 0;
1987                 }
1988         }
1989         return -EINVAL;
1990 }
1991
1992 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1993                                       const struct intel_connector *connector,
1994                                       struct intel_crtc_state *pipe_config,
1995                                       struct link_config_limits *limits,
1996                                       int pipe_bpp,
1997                                       int timeslots)
1998 {
1999         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2000         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2001         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2002         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2003         int dsc_joiner_max_bpp;
2004
2005         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2006         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2007         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2008         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2009
2010         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2011         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2012                                                                 pipe_config,
2013                                                                 pipe_bpp / 3);
2014         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2015
2016         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2017                                                                 adjusted_mode->hdisplay,
2018                                                                 pipe_config->bigjoiner_pipes);
2019         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2020         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2021
2022         if (DISPLAY_VER(i915) >= 13)
2023                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2024                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2025         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2026                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2027 }
2028
2029 static
2030 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2031 {
2032         /* Min DSC Input BPC for ICL+ is 8 */
2033         return HAS_DSC(i915) ? 8 : 0;
2034 }
2035
2036 static
2037 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2038                                 struct drm_connector_state *conn_state,
2039                                 struct link_config_limits *limits,
2040                                 int pipe_bpp)
2041 {
2042         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2043
2044         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2045         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2046
2047         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2048         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2049
2050         return pipe_bpp >= dsc_min_pipe_bpp &&
2051                pipe_bpp <= dsc_max_pipe_bpp;
2052 }
2053
2054 static
2055 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2056                                 struct drm_connector_state *conn_state,
2057                                 struct link_config_limits *limits)
2058 {
2059         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2060         int forced_bpp;
2061
2062         if (!intel_dp->force_dsc_bpc)
2063                 return 0;
2064
2065         forced_bpp = intel_dp->force_dsc_bpc * 3;
2066
2067         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2068                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2069                 return forced_bpp;
2070         }
2071
2072         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2073                     intel_dp->force_dsc_bpc);
2074
2075         return 0;
2076 }
2077
2078 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2079                                          struct intel_crtc_state *pipe_config,
2080                                          struct drm_connector_state *conn_state,
2081                                          struct link_config_limits *limits,
2082                                          int timeslots)
2083 {
2084         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085         const struct intel_connector *connector =
2086                 to_intel_connector(conn_state->connector);
2087         u8 max_req_bpc = conn_state->max_requested_bpc;
2088         u8 dsc_max_bpc, dsc_max_bpp;
2089         u8 dsc_min_bpc, dsc_min_bpp;
2090         u8 dsc_bpc[3] = {};
2091         int forced_bpp, pipe_bpp;
2092         int num_bpc, i, ret;
2093
2094         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2095
2096         if (forced_bpp) {
2097                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2098                                                  limits, forced_bpp, timeslots);
2099                 if (ret == 0) {
2100                         pipe_config->pipe_bpp = forced_bpp;
2101                         return 0;
2102                 }
2103         }
2104
2105         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2106         if (!dsc_max_bpc)
2107                 return -EINVAL;
2108
2109         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2110         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2111
2112         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2113         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2114
2115         /*
2116          * Get the maximum DSC bpc that will be supported by any valid
2117          * link configuration and compressed bpp.
2118          */
2119         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2120         for (i = 0; i < num_bpc; i++) {
2121                 pipe_bpp = dsc_bpc[i] * 3;
2122                 if (pipe_bpp < dsc_min_bpp)
2123                         break;
2124                 if (pipe_bpp > dsc_max_bpp)
2125                         continue;
2126                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2127                                                  limits, pipe_bpp, timeslots);
2128                 if (ret == 0) {
2129                         pipe_config->pipe_bpp = pipe_bpp;
2130                         return 0;
2131                 }
2132         }
2133
2134         return -EINVAL;
2135 }
2136
2137 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2138                                           struct intel_crtc_state *pipe_config,
2139                                           struct drm_connector_state *conn_state,
2140                                           struct link_config_limits *limits)
2141 {
2142         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2143         struct intel_connector *connector =
2144                 to_intel_connector(conn_state->connector);
2145         int pipe_bpp, forced_bpp;
2146         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2147         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2148
2149         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2150
2151         if (forced_bpp) {
2152                 pipe_bpp = forced_bpp;
2153         } else {
2154                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2155
2156                 /* For eDP use max bpp that can be supported with DSC. */
2157                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2158                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2159                         drm_dbg_kms(&i915->drm,
2160                                     "Computed BPC is not in DSC BPC limits\n");
2161                         return -EINVAL;
2162                 }
2163         }
2164         pipe_config->port_clock = limits->max_rate;
2165         pipe_config->lane_count = limits->max_lane_count;
2166
2167         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2168         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2169         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2170         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2171
2172         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2173         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2174                                                                 pipe_config,
2175                                                                 pipe_bpp / 3);
2176         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2177         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2178
2179         /* Compressed BPP should be less than the Input DSC bpp */
2180         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2181
2182         pipe_config->dsc.compressed_bpp_x16 =
2183                 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2184
2185         pipe_config->pipe_bpp = pipe_bpp;
2186
2187         return 0;
2188 }
2189
2190 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2191                                 struct intel_crtc_state *pipe_config,
2192                                 struct drm_connector_state *conn_state,
2193                                 struct link_config_limits *limits,
2194                                 int timeslots,
2195                                 bool compute_pipe_bpp)
2196 {
2197         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2198         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2199         const struct intel_connector *connector =
2200                 to_intel_connector(conn_state->connector);
2201         const struct drm_display_mode *adjusted_mode =
2202                 &pipe_config->hw.adjusted_mode;
2203         int ret;
2204
2205         pipe_config->fec_enable = pipe_config->fec_enable ||
2206                 (!intel_dp_is_edp(intel_dp) &&
2207                  intel_dp_supports_fec(intel_dp, connector, pipe_config));
2208
2209         if (!intel_dp_supports_dsc(connector, pipe_config))
2210                 return -EINVAL;
2211
2212         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2213                 return -EINVAL;
2214
2215         /*
2216          * compute pipe bpp is set to false for DP MST DSC case
2217          * and compressed_bpp is calculated same time once
2218          * vpci timeslots are allocated, because overall bpp
2219          * calculation procedure is bit different for MST case.
2220          */
2221         if (compute_pipe_bpp) {
2222                 if (intel_dp_is_edp(intel_dp))
2223                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2224                                                              conn_state, limits);
2225                 else
2226                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2227                                                             conn_state, limits, timeslots);
2228                 if (ret) {
2229                         drm_dbg_kms(&dev_priv->drm,
2230                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2231                         return ret;
2232                 }
2233         }
2234
2235         /* Calculate Slice count */
2236         if (intel_dp_is_edp(intel_dp)) {
2237                 pipe_config->dsc.slice_count =
2238                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2239                                                         true);
2240                 if (!pipe_config->dsc.slice_count) {
2241                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2242                                     pipe_config->dsc.slice_count);
2243                         return -EINVAL;
2244                 }
2245         } else {
2246                 u8 dsc_dp_slice_count;
2247
2248                 dsc_dp_slice_count =
2249                         intel_dp_dsc_get_slice_count(connector,
2250                                                      adjusted_mode->crtc_clock,
2251                                                      adjusted_mode->crtc_hdisplay,
2252                                                      pipe_config->bigjoiner_pipes);
2253                 if (!dsc_dp_slice_count) {
2254                         drm_dbg_kms(&dev_priv->drm,
2255                                     "Compressed Slice Count not supported\n");
2256                         return -EINVAL;
2257                 }
2258
2259                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2260         }
2261         /*
2262          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2263          * is greater than the maximum Cdclock and if slice count is even
2264          * then we need to use 2 VDSC instances.
2265          */
2266         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2267                 pipe_config->dsc.dsc_split = true;
2268
2269         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2270         if (ret < 0) {
2271                 drm_dbg_kms(&dev_priv->drm,
2272                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2273                             "Compressed BPP = " BPP_X16_FMT "\n",
2274                             pipe_config->pipe_bpp,
2275                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2276                 return ret;
2277         }
2278
2279         pipe_config->dsc.compression_enable = true;
2280         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2281                     "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2282                     pipe_config->pipe_bpp,
2283                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2284                     pipe_config->dsc.slice_count);
2285
2286         return 0;
2287 }
2288
2289 /**
2290  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2291  * @intel_dp: intel DP
2292  * @crtc_state: crtc state
2293  * @dsc: DSC compression mode
2294  * @limits: link configuration limits
2295  *
2296  * Calculates the output link min, max bpp values in @limits based on the
2297  * pipe bpp range, @crtc_state and @dsc mode.
2298  *
2299  * Returns %true in case of success.
2300  */
2301 bool
2302 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2303                                         const struct intel_crtc_state *crtc_state,
2304                                         bool dsc,
2305                                         struct link_config_limits *limits)
2306 {
2307         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2308         const struct drm_display_mode *adjusted_mode =
2309                 &crtc_state->hw.adjusted_mode;
2310         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2311         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2312         int max_link_bpp_x16;
2313
2314         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2315                                to_bpp_x16(limits->pipe.max_bpp));
2316
2317         if (!dsc) {
2318                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2319
2320                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2321                         return false;
2322
2323                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2324         } else {
2325                 /*
2326                  * TODO: set the DSC link limits already here, atm these are
2327                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2328                  * intel_dp_dsc_compute_pipe_bpp()
2329                  */
2330                 limits->link.min_bpp_x16 = 0;
2331         }
2332
2333         limits->link.max_bpp_x16 = max_link_bpp_x16;
2334
2335         drm_dbg_kms(&i915->drm,
2336                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2337                     encoder->base.base.id, encoder->base.name,
2338                     crtc->base.base.id, crtc->base.name,
2339                     adjusted_mode->crtc_clock,
2340                     dsc ? "on" : "off",
2341                     limits->max_lane_count,
2342                     limits->max_rate,
2343                     limits->pipe.max_bpp,
2344                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2345
2346         return true;
2347 }
2348
2349 static bool
2350 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2351                                struct intel_crtc_state *crtc_state,
2352                                bool respect_downstream_limits,
2353                                bool dsc,
2354                                struct link_config_limits *limits)
2355 {
2356         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2357         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2358
2359         /* FIXME 128b/132b SST support missing */
2360         limits->max_rate = min(limits->max_rate, 810000);
2361
2362         limits->min_lane_count = 1;
2363         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2364
2365         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2366         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2367                                                      respect_downstream_limits);
2368
2369         if (intel_dp->use_max_params) {
2370                 /*
2371                  * Use the maximum clock and number of lanes the eDP panel
2372                  * advertizes being capable of in case the initial fast
2373                  * optimal params failed us. The panels are generally
2374                  * designed to support only a single clock and lane
2375                  * configuration, and typically on older panels these
2376                  * values correspond to the native resolution of the panel.
2377                  */
2378                 limits->min_lane_count = limits->max_lane_count;
2379                 limits->min_rate = limits->max_rate;
2380         }
2381
2382         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2383
2384         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2385                                                        crtc_state,
2386                                                        dsc,
2387                                                        limits);
2388 }
2389
2390 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2391 {
2392         const struct drm_display_mode *adjusted_mode =
2393                 &crtc_state->hw.adjusted_mode;
2394         int bpp = crtc_state->dsc.compression_enable ?
2395                 to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2396                 crtc_state->pipe_bpp;
2397
2398         return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2399 }
2400
2401 static int
2402 intel_dp_compute_link_config(struct intel_encoder *encoder,
2403                              struct intel_crtc_state *pipe_config,
2404                              struct drm_connector_state *conn_state,
2405                              bool respect_downstream_limits)
2406 {
2407         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2408         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2409         const struct intel_connector *connector =
2410                 to_intel_connector(conn_state->connector);
2411         const struct drm_display_mode *adjusted_mode =
2412                 &pipe_config->hw.adjusted_mode;
2413         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2414         struct link_config_limits limits;
2415         bool joiner_needs_dsc = false;
2416         bool dsc_needed;
2417         int ret = 0;
2418
2419         if (pipe_config->fec_enable &&
2420             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2421                 return -EINVAL;
2422
2423         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2424                                     adjusted_mode->crtc_clock))
2425                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2426
2427         /*
2428          * Pipe joiner needs compression up to display 12 due to bandwidth
2429          * limitation. DG2 onwards pipe joiner can be enabled without
2430          * compression.
2431          */
2432         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2433
2434         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2435                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2436                                                      respect_downstream_limits,
2437                                                      false,
2438                                                      &limits);
2439
2440         if (!dsc_needed) {
2441                 /*
2442                  * Optimize for slow and wide for everything, because there are some
2443                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2444                  */
2445                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2446                                                         conn_state, &limits);
2447                 if (ret)
2448                         dsc_needed = true;
2449         }
2450
2451         if (dsc_needed) {
2452                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2453                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2454                             str_yes_no(intel_dp->force_dsc_en));
2455
2456                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2457                                                     respect_downstream_limits,
2458                                                     true,
2459                                                     &limits))
2460                         return -EINVAL;
2461
2462                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2463                                                   conn_state, &limits, 64, true);
2464                 if (ret < 0)
2465                         return ret;
2466         }
2467
2468         drm_dbg_kms(&i915->drm,
2469                     "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
2470                     pipe_config->lane_count, pipe_config->port_clock,
2471                     pipe_config->pipe_bpp,
2472                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2473                     intel_dp_config_required_rate(pipe_config),
2474                     intel_dp_max_link_data_rate(intel_dp,
2475                                                 pipe_config->port_clock,
2476                                                 pipe_config->lane_count));
2477
2478         return 0;
2479 }
2480
2481 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2482                                   const struct drm_connector_state *conn_state)
2483 {
2484         const struct intel_digital_connector_state *intel_conn_state =
2485                 to_intel_digital_connector_state(conn_state);
2486         const struct drm_display_mode *adjusted_mode =
2487                 &crtc_state->hw.adjusted_mode;
2488
2489         /*
2490          * Our YCbCr output is always limited range.
2491          * crtc_state->limited_color_range only applies to RGB,
2492          * and it must never be set for YCbCr or we risk setting
2493          * some conflicting bits in TRANSCONF which will mess up
2494          * the colors on the monitor.
2495          */
2496         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2497                 return false;
2498
2499         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2500                 /*
2501                  * See:
2502                  * CEA-861-E - 5.1 Default Encoding Parameters
2503                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2504                  */
2505                 return crtc_state->pipe_bpp != 18 &&
2506                         drm_default_rgb_quant_range(adjusted_mode) ==
2507                         HDMI_QUANTIZATION_RANGE_LIMITED;
2508         } else {
2509                 return intel_conn_state->broadcast_rgb ==
2510                         INTEL_BROADCAST_RGB_LIMITED;
2511         }
2512 }
2513
2514 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2515                                     enum port port)
2516 {
2517         if (IS_G4X(dev_priv))
2518                 return false;
2519         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2520                 return false;
2521
2522         return true;
2523 }
2524
2525 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2526                                              const struct drm_connector_state *conn_state,
2527                                              struct drm_dp_vsc_sdp *vsc)
2528 {
2529         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2530         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2531
2532         if (crtc_state->has_panel_replay) {
2533                 /*
2534                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2535                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2536                  * Encoding/Colorimetry Format indication.
2537                  */
2538                 vsc->revision = 0x7;
2539         } else {
2540                 /*
2541                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2542                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2543                  * Colorimetry Format indication.
2544                  */
2545                 vsc->revision = 0x5;
2546         }
2547
2548         vsc->length = 0x13;
2549
2550         /* DP 1.4a spec, Table 2-120 */
2551         switch (crtc_state->output_format) {
2552         case INTEL_OUTPUT_FORMAT_YCBCR444:
2553                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2554                 break;
2555         case INTEL_OUTPUT_FORMAT_YCBCR420:
2556                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2557                 break;
2558         case INTEL_OUTPUT_FORMAT_RGB:
2559         default:
2560                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2561         }
2562
2563         switch (conn_state->colorspace) {
2564         case DRM_MODE_COLORIMETRY_BT709_YCC:
2565                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2566                 break;
2567         case DRM_MODE_COLORIMETRY_XVYCC_601:
2568                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2569                 break;
2570         case DRM_MODE_COLORIMETRY_XVYCC_709:
2571                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2572                 break;
2573         case DRM_MODE_COLORIMETRY_SYCC_601:
2574                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2575                 break;
2576         case DRM_MODE_COLORIMETRY_OPYCC_601:
2577                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2578                 break;
2579         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2580                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2581                 break;
2582         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2583                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2584                 break;
2585         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2586                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2587                 break;
2588         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2589         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2590                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2591                 break;
2592         default:
2593                 /*
2594                  * RGB->YCBCR color conversion uses the BT.709
2595                  * color space.
2596                  */
2597                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2598                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2599                 else
2600                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2601                 break;
2602         }
2603
2604         vsc->bpc = crtc_state->pipe_bpp / 3;
2605
2606         /* only RGB pixelformat supports 6 bpc */
2607         drm_WARN_ON(&dev_priv->drm,
2608                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2609
2610         /* all YCbCr are always limited range */
2611         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2612         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2613 }
2614
2615 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2616                                      struct intel_crtc_state *crtc_state,
2617                                      const struct drm_connector_state *conn_state)
2618 {
2619         struct drm_dp_vsc_sdp *vsc;
2620
2621         if ((!intel_dp->colorimetry_support ||
2622              !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2623             !crtc_state->has_psr)
2624                 return;
2625
2626         vsc = &crtc_state->infoframes.vsc;
2627
2628         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2629         vsc->sdp_type = DP_SDP_VSC;
2630
2631         /* Needs colorimetry */
2632         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2633                 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2634                                                  vsc);
2635         } else if (crtc_state->has_psr2) {
2636                 /*
2637                  * [PSR2 without colorimetry]
2638                  * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2639                  * 3D stereo + PSR/PSR2 + Y-coordinate.
2640                  */
2641                 vsc->revision = 0x4;
2642                 vsc->length = 0xe;
2643         } else if (crtc_state->has_panel_replay) {
2644                 /*
2645                  * [Panel Replay without colorimetry info]
2646                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2647                  * VSC SDP supporting 3D stereo + Panel Replay.
2648                  */
2649                 vsc->revision = 0x6;
2650                 vsc->length = 0x10;
2651         } else {
2652                 /*
2653                  * [PSR1]
2654                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2655                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2656                  * higher).
2657                  */
2658                 vsc->revision = 0x2;
2659                 vsc->length = 0x8;
2660         }
2661 }
2662
2663 static void
2664 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2665                                             struct intel_crtc_state *crtc_state,
2666                                             const struct drm_connector_state *conn_state)
2667 {
2668         int ret;
2669         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2670         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2671
2672         if (!conn_state->hdr_output_metadata)
2673                 return;
2674
2675         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2676
2677         if (ret) {
2678                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2679                 return;
2680         }
2681
2682         crtc_state->infoframes.enable |=
2683                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2684 }
2685
2686 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2687                                     enum transcoder cpu_transcoder)
2688 {
2689         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2690                 return true;
2691
2692         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2693 }
2694
2695 static bool can_enable_drrs(struct intel_connector *connector,
2696                             const struct intel_crtc_state *pipe_config,
2697                             const struct drm_display_mode *downclock_mode)
2698 {
2699         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2700
2701         if (pipe_config->vrr.enable)
2702                 return false;
2703
2704         /*
2705          * DRRS and PSR can't be enable together, so giving preference to PSR
2706          * as it allows more power-savings by complete shutting down display,
2707          * so to guarantee this, intel_drrs_compute_config() must be called
2708          * after intel_psr_compute_config().
2709          */
2710         if (pipe_config->has_psr)
2711                 return false;
2712
2713         /* FIXME missing FDI M2/N2 etc. */
2714         if (pipe_config->has_pch_encoder)
2715                 return false;
2716
2717         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2718                 return false;
2719
2720         return downclock_mode &&
2721                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2722 }
2723
2724 static void
2725 intel_dp_drrs_compute_config(struct intel_connector *connector,
2726                              struct intel_crtc_state *pipe_config,
2727                              int link_bpp_x16)
2728 {
2729         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2730         const struct drm_display_mode *downclock_mode =
2731                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2732         int pixel_clock;
2733
2734         if (has_seamless_m_n(connector))
2735                 pipe_config->update_m_n = true;
2736
2737         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2738                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2739                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2740                 return;
2741         }
2742
2743         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2744                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2745
2746         pipe_config->has_drrs = true;
2747
2748         pixel_clock = downclock_mode->clock;
2749         if (pipe_config->splitter.enable)
2750                 pixel_clock /= pipe_config->splitter.link_count;
2751
2752         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2753                                pipe_config->port_clock,
2754                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2755                                &pipe_config->dp_m2_n2);
2756
2757         /* FIXME: abstract this better */
2758         if (pipe_config->splitter.enable)
2759                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2760 }
2761
2762 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2763                                struct intel_crtc_state *crtc_state,
2764                                const struct drm_connector_state *conn_state)
2765 {
2766         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2767         const struct intel_digital_connector_state *intel_conn_state =
2768                 to_intel_digital_connector_state(conn_state);
2769         struct intel_connector *connector =
2770                 to_intel_connector(conn_state->connector);
2771
2772         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2773             !intel_dp_port_has_audio(i915, encoder->port))
2774                 return false;
2775
2776         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2777                 return connector->base.display_info.has_audio;
2778         else
2779                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2780 }
2781
2782 static int
2783 intel_dp_compute_output_format(struct intel_encoder *encoder,
2784                                struct intel_crtc_state *crtc_state,
2785                                struct drm_connector_state *conn_state,
2786                                bool respect_downstream_limits)
2787 {
2788         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2789         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2790         struct intel_connector *connector = intel_dp->attached_connector;
2791         const struct drm_display_info *info = &connector->base.display_info;
2792         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2793         bool ycbcr_420_only;
2794         int ret;
2795
2796         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2797
2798         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2799                 drm_dbg_kms(&i915->drm,
2800                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2801                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2802         } else {
2803                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2804         }
2805
2806         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2807
2808         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2809                                            respect_downstream_limits);
2810         if (ret) {
2811                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2812                     !connector->base.ycbcr_420_allowed ||
2813                     !drm_mode_is_420_also(info, adjusted_mode))
2814                         return ret;
2815
2816                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2817                 crtc_state->output_format = intel_dp_output_format(connector,
2818                                                                    crtc_state->sink_format);
2819                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2820                                                    respect_downstream_limits);
2821         }
2822
2823         return ret;
2824 }
2825
2826 void
2827 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2828                               struct intel_crtc_state *pipe_config,
2829                               struct drm_connector_state *conn_state)
2830 {
2831         pipe_config->has_audio =
2832                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2833                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2834
2835         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2836                                         intel_dp_is_uhbr(pipe_config);
2837 }
2838
2839 void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
2840 {
2841         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2842
2843         drm_connector_get(&connector->base);
2844         if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
2845                 drm_connector_put(&connector->base);
2846 }
2847
2848 void
2849 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
2850                                       struct intel_encoder *encoder,
2851                                       const struct intel_crtc_state *crtc_state)
2852 {
2853         struct intel_connector *connector;
2854         struct intel_digital_connector_state *conn_state;
2855         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2856         int i;
2857
2858         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2859                 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
2860
2861                 return;
2862         }
2863
2864         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
2865                 if (!conn_state->base.crtc)
2866                         continue;
2867
2868                 if (connector->mst_port == intel_dp)
2869                         intel_dp_queue_modeset_retry_work(connector);
2870         }
2871 }
2872
2873 int
2874 intel_dp_compute_config(struct intel_encoder *encoder,
2875                         struct intel_crtc_state *pipe_config,
2876                         struct drm_connector_state *conn_state)
2877 {
2878         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2879         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
2880         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2881         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2882         const struct drm_display_mode *fixed_mode;
2883         struct intel_connector *connector = intel_dp->attached_connector;
2884         int ret = 0, link_bpp_x16;
2885
2886         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2887                 pipe_config->has_pch_encoder = true;
2888
2889         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2890         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2891                 ret = intel_panel_compute_config(connector, adjusted_mode);
2892                 if (ret)
2893                         return ret;
2894         }
2895
2896         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2897                 return -EINVAL;
2898
2899         if (!connector->base.interlace_allowed &&
2900             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2901                 return -EINVAL;
2902
2903         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2904                 return -EINVAL;
2905
2906         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2907                 return -EINVAL;
2908
2909         /*
2910          * Try to respect downstream TMDS clock limits first, if
2911          * that fails assume the user might know something we don't.
2912          */
2913         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2914         if (ret)
2915                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2916         if (ret)
2917                 return ret;
2918
2919         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2920             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2921                 ret = intel_panel_fitting(pipe_config, conn_state);
2922                 if (ret)
2923                         return ret;
2924         }
2925
2926         pipe_config->limited_color_range =
2927                 intel_dp_limited_color_range(pipe_config, conn_state);
2928
2929         pipe_config->enhanced_framing =
2930                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2931
2932         if (pipe_config->dsc.compression_enable)
2933                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2934         else
2935                 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2936                                                               pipe_config->pipe_bpp));
2937
2938         if (intel_dp->mso_link_count) {
2939                 int n = intel_dp->mso_link_count;
2940                 int overlap = intel_dp->mso_pixel_overlap;
2941
2942                 pipe_config->splitter.enable = true;
2943                 pipe_config->splitter.link_count = n;
2944                 pipe_config->splitter.pixel_overlap = overlap;
2945
2946                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2947                             n, overlap);
2948
2949                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2950                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2951                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2952                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2953                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2954                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2955                 adjusted_mode->crtc_clock /= n;
2956         }
2957
2958         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2959
2960         intel_link_compute_m_n(link_bpp_x16,
2961                                pipe_config->lane_count,
2962                                adjusted_mode->crtc_clock,
2963                                pipe_config->port_clock,
2964                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2965                                &pipe_config->dp_m_n);
2966
2967         /* FIXME: abstract this better */
2968         if (pipe_config->splitter.enable)
2969                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2970
2971         if (!HAS_DDI(dev_priv))
2972                 g4x_dp_set_clock(encoder, pipe_config);
2973
2974         intel_vrr_compute_config(pipe_config, conn_state);
2975         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2976         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2977         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2978         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2979
2980         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
2981                                                         pipe_config);
2982 }
2983
2984 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2985                               int link_rate, int lane_count)
2986 {
2987         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2988         intel_dp->link_trained = false;
2989         intel_dp->link_rate = link_rate;
2990         intel_dp->lane_count = lane_count;
2991 }
2992
2993 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2994 {
2995         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2996         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2997 }
2998
2999 /* Enable backlight PWM and backlight PP control. */
3000 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3001                             const struct drm_connector_state *conn_state)
3002 {
3003         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3004         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3005
3006         if (!intel_dp_is_edp(intel_dp))
3007                 return;
3008
3009         drm_dbg_kms(&i915->drm, "\n");
3010
3011         intel_backlight_enable(crtc_state, conn_state);
3012         intel_pps_backlight_on(intel_dp);
3013 }
3014
3015 /* Disable backlight PP control and backlight PWM. */
3016 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3017 {
3018         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3019         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3020
3021         if (!intel_dp_is_edp(intel_dp))
3022                 return;
3023
3024         drm_dbg_kms(&i915->drm, "\n");
3025
3026         intel_pps_backlight_off(intel_dp);
3027         intel_backlight_disable(old_conn_state);
3028 }
3029
3030 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3031 {
3032         /*
3033          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3034          * be capable of signalling downstream hpd with a long pulse.
3035          * Whether or not that means D3 is safe to use is not clear,
3036          * but let's assume so until proven otherwise.
3037          *
3038          * FIXME should really check all downstream ports...
3039          */
3040         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3041                 drm_dp_is_branch(intel_dp->dpcd) &&
3042                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3043 }
3044
3045 static int
3046 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3047 {
3048         int err;
3049         u8 val;
3050
3051         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3052         if (err < 0)
3053                 return err;
3054
3055         if (set)
3056                 val |= flag;
3057         else
3058                 val &= ~flag;
3059
3060         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3061 }
3062
3063 static void
3064 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3065                                     bool enable)
3066 {
3067         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3068
3069         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3070                                          DP_DECOMPRESSION_EN, enable) < 0)
3071                 drm_dbg_kms(&i915->drm,
3072                             "Failed to %s sink decompression state\n",
3073                             str_enable_disable(enable));
3074 }
3075
3076 static void
3077 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3078                                   bool enable)
3079 {
3080         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3081         struct drm_dp_aux *aux = connector->port ?
3082                                  connector->port->passthrough_aux : NULL;
3083
3084         if (!aux)
3085                 return;
3086
3087         if (write_dsc_decompression_flag(aux,
3088                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3089                 drm_dbg_kms(&i915->drm,
3090                             "Failed to %s sink compression passthrough state\n",
3091                             str_enable_disable(enable));
3092 }
3093
3094 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3095                                       const struct intel_connector *connector,
3096                                       bool for_get_ref)
3097 {
3098         struct drm_i915_private *i915 = to_i915(state->base.dev);
3099         struct drm_connector *_connector_iter;
3100         struct drm_connector_state *old_conn_state;
3101         struct drm_connector_state *new_conn_state;
3102         int ref_count = 0;
3103         int i;
3104
3105         /*
3106          * On SST the decompression AUX device won't be shared, each connector
3107          * uses for this its own AUX targeting the sink device.
3108          */
3109         if (!connector->mst_port)
3110                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3111
3112         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3113                                            old_conn_state, new_conn_state, i) {
3114                 const struct intel_connector *
3115                         connector_iter = to_intel_connector(_connector_iter);
3116
3117                 if (connector_iter->mst_port != connector->mst_port)
3118                         continue;
3119
3120                 if (!connector_iter->dp.dsc_decompression_enabled)
3121                         continue;
3122
3123                 drm_WARN_ON(&i915->drm,
3124                             (for_get_ref && !new_conn_state->crtc) ||
3125                             (!for_get_ref && !old_conn_state->crtc));
3126
3127                 if (connector_iter->dp.dsc_decompression_aux ==
3128                     connector->dp.dsc_decompression_aux)
3129                         ref_count++;
3130         }
3131
3132         return ref_count;
3133 }
3134
3135 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3136                                      struct intel_connector *connector)
3137 {
3138         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3139
3140         connector->dp.dsc_decompression_enabled = true;
3141
3142         return ret;
3143 }
3144
3145 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3146                                      struct intel_connector *connector)
3147 {
3148         connector->dp.dsc_decompression_enabled = false;
3149
3150         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3151 }
3152
3153 /**
3154  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3155  * @state: atomic state
3156  * @connector: connector to enable the decompression for
3157  * @new_crtc_state: new state for the CRTC driving @connector
3158  *
3159  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3160  * register of the appropriate sink/branch device. On SST this is always the
3161  * sink device, whereas on MST based on each device's DSC capabilities it's
3162  * either the last branch device (enabling decompression in it) or both the
3163  * last branch device (enabling passthrough in it) and the sink device
3164  * (enabling decompression in it).
3165  */
3166 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3167                                         struct intel_connector *connector,
3168                                         const struct intel_crtc_state *new_crtc_state)
3169 {
3170         struct drm_i915_private *i915 = to_i915(state->base.dev);
3171
3172         if (!new_crtc_state->dsc.compression_enable)
3173                 return;
3174
3175         if (drm_WARN_ON(&i915->drm,
3176                         !connector->dp.dsc_decompression_aux ||
3177                         connector->dp.dsc_decompression_enabled))
3178                 return;
3179
3180         if (!intel_dp_dsc_aux_get_ref(state, connector))
3181                 return;
3182
3183         intel_dp_sink_set_dsc_passthrough(connector, true);
3184         intel_dp_sink_set_dsc_decompression(connector, true);
3185 }
3186
3187 /**
3188  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3189  * @state: atomic state
3190  * @connector: connector to disable the decompression for
3191  * @old_crtc_state: old state for the CRTC driving @connector
3192  *
3193  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3194  * register of the appropriate sink/branch device, corresponding to the
3195  * sequence in intel_dp_sink_enable_decompression().
3196  */
3197 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3198                                          struct intel_connector *connector,
3199                                          const struct intel_crtc_state *old_crtc_state)
3200 {
3201         struct drm_i915_private *i915 = to_i915(state->base.dev);
3202
3203         if (!old_crtc_state->dsc.compression_enable)
3204                 return;
3205
3206         if (drm_WARN_ON(&i915->drm,
3207                         !connector->dp.dsc_decompression_aux ||
3208                         !connector->dp.dsc_decompression_enabled))
3209                 return;
3210
3211         if (!intel_dp_dsc_aux_put_ref(state, connector))
3212                 return;
3213
3214         intel_dp_sink_set_dsc_decompression(connector, false);
3215         intel_dp_sink_set_dsc_passthrough(connector, false);
3216 }
3217
3218 static void
3219 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3220 {
3221         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3222         u8 oui[] = { 0x00, 0xaa, 0x01 };
3223         u8 buf[3] = {};
3224
3225         /*
3226          * During driver init, we want to be careful and avoid changing the source OUI if it's
3227          * already set to what we want, so as to avoid clearing any state by accident
3228          */
3229         if (careful) {
3230                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3231                         drm_err(&i915->drm, "Failed to read source OUI\n");
3232
3233                 if (memcmp(oui, buf, sizeof(oui)) == 0)
3234                         return;
3235         }
3236
3237         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3238                 drm_err(&i915->drm, "Failed to write source OUI\n");
3239
3240         intel_dp->last_oui_write = jiffies;
3241 }
3242
3243 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3244 {
3245         struct intel_connector *connector = intel_dp->attached_connector;
3246         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3247
3248         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3249                     connector->base.base.id, connector->base.name,
3250                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3251
3252         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3253                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3254 }
3255
3256 /* If the device supports it, try to set the power state appropriately */
3257 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3258 {
3259         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3260         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3261         int ret, i;
3262
3263         /* Should have a valid DPCD by this point */
3264         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3265                 return;
3266
3267         if (mode != DP_SET_POWER_D0) {
3268                 if (downstream_hpd_needs_d0(intel_dp))
3269                         return;
3270
3271                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3272         } else {
3273                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3274
3275                 lspcon_resume(dp_to_dig_port(intel_dp));
3276
3277                 /* Write the source OUI as early as possible */
3278                 if (intel_dp_is_edp(intel_dp))
3279                         intel_edp_init_source_oui(intel_dp, false);
3280
3281                 /*
3282                  * When turning on, we need to retry for 1ms to give the sink
3283                  * time to wake up.
3284                  */
3285                 for (i = 0; i < 3; i++) {
3286                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3287                         if (ret == 1)
3288                                 break;
3289                         msleep(1);
3290                 }
3291
3292                 if (ret == 1 && lspcon->active)
3293                         lspcon_wait_pcon_mode(lspcon);
3294         }
3295
3296         if (ret != 1)
3297                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3298                             encoder->base.base.id, encoder->base.name,
3299                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3300 }
3301
3302 static bool
3303 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3304
3305 /**
3306  * intel_dp_sync_state - sync the encoder state during init/resume
3307  * @encoder: intel encoder to sync
3308  * @crtc_state: state for the CRTC connected to the encoder
3309  *
3310  * Sync any state stored in the encoder wrt. HW state during driver init
3311  * and system resume.
3312  */
3313 void intel_dp_sync_state(struct intel_encoder *encoder,
3314                          const struct intel_crtc_state *crtc_state)
3315 {
3316         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3317         bool dpcd_updated = false;
3318
3319         /*
3320          * Don't clobber DPCD if it's been already read out during output
3321          * setup (eDP) or detect.
3322          */
3323         if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3324                 intel_dp_get_dpcd(intel_dp);
3325                 dpcd_updated = true;
3326         }
3327
3328         intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3329
3330         if (crtc_state)
3331                 intel_dp_reset_max_link_params(intel_dp);
3332 }
3333
3334 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3335                                     struct intel_crtc_state *crtc_state)
3336 {
3337         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3338         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3339         bool fastset = true;
3340
3341         /*
3342          * If BIOS has set an unsupported or non-standard link rate for some
3343          * reason force an encoder recompute and full modeset.
3344          */
3345         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3346                                 crtc_state->port_clock) < 0) {
3347                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3348                             encoder->base.base.id, encoder->base.name);
3349                 crtc_state->uapi.connectors_changed = true;
3350                 fastset = false;
3351         }
3352
3353         /*
3354          * FIXME hack to force full modeset when DSC is being used.
3355          *
3356          * As long as we do not have full state readout and config comparison
3357          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3358          * Remove once we have readout for DSC.
3359          */
3360         if (crtc_state->dsc.compression_enable) {
3361                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3362                             encoder->base.base.id, encoder->base.name);
3363                 crtc_state->uapi.mode_changed = true;
3364                 fastset = false;
3365         }
3366
3367         return fastset;
3368 }
3369
3370 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3371 {
3372         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3373
3374         /* Clear the cached register set to avoid using stale values */
3375
3376         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3377
3378         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3379                              intel_dp->pcon_dsc_dpcd,
3380                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3381                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3382                         DP_PCON_DSC_ENCODER);
3383
3384         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3385                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3386 }
3387
3388 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3389 {
3390         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3391         int i;
3392
3393         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3394                 if (frl_bw_mask & (1 << i))
3395                         return bw_gbps[i];
3396         }
3397         return 0;
3398 }
3399
3400 static int intel_dp_pcon_set_frl_mask(int max_frl)
3401 {
3402         switch (max_frl) {
3403         case 48:
3404                 return DP_PCON_FRL_BW_MASK_48GBPS;
3405         case 40:
3406                 return DP_PCON_FRL_BW_MASK_40GBPS;
3407         case 32:
3408                 return DP_PCON_FRL_BW_MASK_32GBPS;
3409         case 24:
3410                 return DP_PCON_FRL_BW_MASK_24GBPS;
3411         case 18:
3412                 return DP_PCON_FRL_BW_MASK_18GBPS;
3413         case 9:
3414                 return DP_PCON_FRL_BW_MASK_9GBPS;
3415         }
3416
3417         return 0;
3418 }
3419
3420 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3421 {
3422         struct intel_connector *intel_connector = intel_dp->attached_connector;
3423         struct drm_connector *connector = &intel_connector->base;
3424         int max_frl_rate;
3425         int max_lanes, rate_per_lane;
3426         int max_dsc_lanes, dsc_rate_per_lane;
3427
3428         max_lanes = connector->display_info.hdmi.max_lanes;
3429         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3430         max_frl_rate = max_lanes * rate_per_lane;
3431
3432         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3433                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3434                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3435                 if (max_dsc_lanes && dsc_rate_per_lane)
3436                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3437         }
3438
3439         return max_frl_rate;
3440 }
3441
3442 static bool
3443 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3444                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3445 {
3446         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3447             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3448             *frl_trained_mask >= max_frl_bw_mask)
3449                 return true;
3450
3451         return false;
3452 }
3453
3454 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3455 {
3456 #define TIMEOUT_FRL_READY_MS 500
3457 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3458
3459         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3460         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3461         u8 max_frl_bw_mask = 0, frl_trained_mask;
3462         bool is_active;
3463
3464         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3465         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3466
3467         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3468         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3469
3470         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3471
3472         if (max_frl_bw <= 0)
3473                 return -EINVAL;
3474
3475         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3476         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3477
3478         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3479                 goto frl_trained;
3480
3481         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3482         if (ret < 0)
3483                 return ret;
3484         /* Wait for PCON to be FRL Ready */
3485         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3486
3487         if (!is_active)
3488                 return -ETIMEDOUT;
3489
3490         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3491                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3492         if (ret < 0)
3493                 return ret;
3494         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3495                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3496         if (ret < 0)
3497                 return ret;
3498         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3499         if (ret < 0)
3500                 return ret;
3501         /*
3502          * Wait for FRL to be completed
3503          * Check if the HDMI Link is up and active.
3504          */
3505         wait_for(is_active =
3506                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3507                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3508
3509         if (!is_active)
3510                 return -ETIMEDOUT;
3511
3512 frl_trained:
3513         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3514         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3515         intel_dp->frl.is_trained = true;
3516         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3517
3518         return 0;
3519 }
3520
3521 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3522 {
3523         if (drm_dp_is_branch(intel_dp->dpcd) &&
3524             intel_dp_has_hdmi_sink(intel_dp) &&
3525             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3526                 return true;
3527
3528         return false;
3529 }
3530
3531 static
3532 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3533 {
3534         int ret;
3535         u8 buf = 0;
3536
3537         /* Set PCON source control mode */
3538         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3539
3540         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3541         if (ret < 0)
3542                 return ret;
3543
3544         /* Set HDMI LINK ENABLE */
3545         buf |= DP_PCON_ENABLE_HDMI_LINK;
3546         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3547         if (ret < 0)
3548                 return ret;
3549
3550         return 0;
3551 }
3552
3553 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3554 {
3555         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3556
3557         /*
3558          * Always go for FRL training if:
3559          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3560          * -sink is HDMI2.1
3561          */
3562         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3563             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3564             intel_dp->frl.is_trained)
3565                 return;
3566
3567         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3568                 int ret, mode;
3569
3570                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3571                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3572                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3573
3574                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3575                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3576         } else {
3577                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3578         }
3579 }
3580
3581 static int
3582 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3583 {
3584         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3585
3586         return intel_hdmi_dsc_get_slice_height(vactive);
3587 }
3588
3589 static int
3590 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3591                              const struct intel_crtc_state *crtc_state)
3592 {
3593         struct intel_connector *intel_connector = intel_dp->attached_connector;
3594         struct drm_connector *connector = &intel_connector->base;
3595         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3596         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3597         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3598         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3599
3600         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3601                                              pcon_max_slice_width,
3602                                              hdmi_max_slices, hdmi_throughput);
3603 }
3604
3605 static int
3606 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3607                           const struct intel_crtc_state *crtc_state,
3608                           int num_slices, int slice_width)
3609 {
3610         struct intel_connector *intel_connector = intel_dp->attached_connector;
3611         struct drm_connector *connector = &intel_connector->base;
3612         int output_format = crtc_state->output_format;
3613         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3614         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3615         int hdmi_max_chunk_bytes =
3616                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3617
3618         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3619                                       num_slices, output_format, hdmi_all_bpp,
3620                                       hdmi_max_chunk_bytes);
3621 }
3622
3623 void
3624 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3625                             const struct intel_crtc_state *crtc_state)
3626 {
3627         u8 pps_param[6];
3628         int slice_height;
3629         int slice_width;
3630         int num_slices;
3631         int bits_per_pixel;
3632         int ret;
3633         struct intel_connector *intel_connector = intel_dp->attached_connector;
3634         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3635         struct drm_connector *connector;
3636         bool hdmi_is_dsc_1_2;
3637
3638         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3639                 return;
3640
3641         if (!intel_connector)
3642                 return;
3643         connector = &intel_connector->base;
3644         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3645
3646         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3647             !hdmi_is_dsc_1_2)
3648                 return;
3649
3650         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3651         if (!slice_height)
3652                 return;
3653
3654         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3655         if (!num_slices)
3656                 return;
3657
3658         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3659                                    num_slices);
3660
3661         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3662                                                    num_slices, slice_width);
3663         if (!bits_per_pixel)
3664                 return;
3665
3666         pps_param[0] = slice_height & 0xFF;
3667         pps_param[1] = slice_height >> 8;
3668         pps_param[2] = slice_width & 0xFF;
3669         pps_param[3] = slice_width >> 8;
3670         pps_param[4] = bits_per_pixel & 0xFF;
3671         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3672
3673         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3674         if (ret < 0)
3675                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3676 }
3677
3678 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3679                                            const struct intel_crtc_state *crtc_state)
3680 {
3681         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3682         bool ycbcr444_to_420 = false;
3683         bool rgb_to_ycbcr = false;
3684         u8 tmp;
3685
3686         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3687                 return;
3688
3689         if (!drm_dp_is_branch(intel_dp->dpcd))
3690                 return;
3691
3692         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3693
3694         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3695                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3696                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3697                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3698
3699         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3700                 switch (crtc_state->output_format) {
3701                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3702                         break;
3703                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3704                         ycbcr444_to_420 = true;
3705                         break;
3706                 case INTEL_OUTPUT_FORMAT_RGB:
3707                         rgb_to_ycbcr = true;
3708                         ycbcr444_to_420 = true;
3709                         break;
3710                 default:
3711                         MISSING_CASE(crtc_state->output_format);
3712                         break;
3713                 }
3714         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3715                 switch (crtc_state->output_format) {
3716                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3717                         break;
3718                 case INTEL_OUTPUT_FORMAT_RGB:
3719                         rgb_to_ycbcr = true;
3720                         break;
3721                 default:
3722                         MISSING_CASE(crtc_state->output_format);
3723                         break;
3724                 }
3725         }
3726
3727         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3728
3729         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3730                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3731                 drm_dbg_kms(&i915->drm,
3732                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3733                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3734
3735         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3736
3737         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3738                 drm_dbg_kms(&i915->drm,
3739                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3740                             str_enable_disable(tmp));
3741 }
3742
3743 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3744 {
3745         u8 dprx = 0;
3746
3747         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3748                               &dprx) != 1)
3749                 return false;
3750         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3751 }
3752
3753 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3754                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3755 {
3756         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3757                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3758                 drm_err(aux->drm_dev,
3759                         "Failed to read DPCD register 0x%x\n",
3760                         DP_DSC_SUPPORT);
3761                 return;
3762         }
3763
3764         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3765                     DP_DSC_RECEIVER_CAP_SIZE,
3766                     dsc_dpcd);
3767 }
3768
3769 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3770 {
3771         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3772
3773         /*
3774          * Clear the cached register set to avoid using stale values
3775          * for the sinks that do not support DSC.
3776          */
3777         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3778
3779         /* Clear fec_capable to avoid using stale values */
3780         connector->dp.fec_capability = 0;
3781
3782         if (dpcd_rev < DP_DPCD_REV_14)
3783                 return;
3784
3785         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3786                                connector->dp.dsc_dpcd);
3787
3788         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3789                               &connector->dp.fec_capability) < 0) {
3790                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3791                 return;
3792         }
3793
3794         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3795                     connector->dp.fec_capability);
3796 }
3797
3798 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3799 {
3800         if (edp_dpcd_rev < DP_EDP_14)
3801                 return;
3802
3803         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3804 }
3805
3806 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3807                                      struct drm_display_mode *mode)
3808 {
3809         struct intel_dp *intel_dp = intel_attached_dp(connector);
3810         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3811         int n = intel_dp->mso_link_count;
3812         int overlap = intel_dp->mso_pixel_overlap;
3813
3814         if (!mode || !n)
3815                 return;
3816
3817         mode->hdisplay = (mode->hdisplay - overlap) * n;
3818         mode->hsync_start = (mode->hsync_start - overlap) * n;
3819         mode->hsync_end = (mode->hsync_end - overlap) * n;
3820         mode->htotal = (mode->htotal - overlap) * n;
3821         mode->clock *= n;
3822
3823         drm_mode_set_name(mode);
3824
3825         drm_dbg_kms(&i915->drm,
3826                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3827                     connector->base.base.id, connector->base.name,
3828                     DRM_MODE_ARG(mode));
3829 }
3830
3831 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3832 {
3833         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3834         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3835         struct intel_connector *connector = intel_dp->attached_connector;
3836
3837         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3838                 /*
3839                  * This is a big fat ugly hack.
3840                  *
3841                  * Some machines in UEFI boot mode provide us a VBT that has 18
3842                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3843                  * unknown we fail to light up. Yet the same BIOS boots up with
3844                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3845                  * max, not what it tells us to use.
3846                  *
3847                  * Note: This will still be broken if the eDP panel is not lit
3848                  * up by the BIOS, and thus we can't get the mode at module
3849                  * load.
3850                  */
3851                 drm_dbg_kms(&dev_priv->drm,
3852                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3853                             pipe_bpp, connector->panel.vbt.edp.bpp);
3854                 connector->panel.vbt.edp.bpp = pipe_bpp;
3855         }
3856 }
3857
3858 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3859 {
3860         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3861         struct intel_connector *connector = intel_dp->attached_connector;
3862         struct drm_display_info *info = &connector->base.display_info;
3863         u8 mso;
3864
3865         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3866                 return;
3867
3868         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3869                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3870                 return;
3871         }
3872
3873         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3874         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3875         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3876                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3877                 mso = 0;
3878         }
3879
3880         if (mso) {
3881                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3882                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3883                             info->mso_pixel_overlap);
3884                 if (!HAS_MSO(i915)) {
3885                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3886                         mso = 0;
3887                 }
3888         }
3889
3890         intel_dp->mso_link_count = mso;
3891         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3892 }
3893
3894 static bool
3895 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3896 {
3897         struct drm_i915_private *dev_priv =
3898                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3899
3900         /* this function is meant to be called only once */
3901         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3902
3903         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3904                 return false;
3905
3906         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3907                          drm_dp_is_branch(intel_dp->dpcd));
3908
3909         /*
3910          * Read the eDP display control registers.
3911          *
3912          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3913          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3914          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3915          * method). The display control registers should read zero if they're
3916          * not supported anyway.
3917          */
3918         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3919                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3920                              sizeof(intel_dp->edp_dpcd)) {
3921                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3922                             (int)sizeof(intel_dp->edp_dpcd),
3923                             intel_dp->edp_dpcd);
3924
3925                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3926         }
3927
3928         /*
3929          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3930          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3931          */
3932         intel_psr_init_dpcd(intel_dp);
3933
3934         /* Clear the default sink rates */
3935         intel_dp->num_sink_rates = 0;
3936
3937         /* Read the eDP 1.4+ supported link rates. */
3938         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3939                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3940                 int i;
3941
3942                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3943                                 sink_rates, sizeof(sink_rates));
3944
3945                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3946                         int val = le16_to_cpu(sink_rates[i]);
3947
3948                         if (val == 0)
3949                                 break;
3950
3951                         /* Value read multiplied by 200kHz gives the per-lane
3952                          * link rate in kHz. The source rates are, however,
3953                          * stored in terms of LS_Clk kHz. The full conversion
3954                          * back to symbols is
3955                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3956                          */
3957                         intel_dp->sink_rates[i] = (val * 200) / 10;
3958                 }
3959                 intel_dp->num_sink_rates = i;
3960         }
3961
3962         /*
3963          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3964          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3965          */
3966         if (intel_dp->num_sink_rates)
3967                 intel_dp->use_rate_select = true;
3968         else
3969                 intel_dp_set_sink_rates(intel_dp);
3970         intel_dp_set_max_sink_lane_count(intel_dp);
3971
3972         /* Read the eDP DSC DPCD registers */
3973         if (HAS_DSC(dev_priv))
3974                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3975                                            connector);
3976
3977         /*
3978          * If needed, program our source OUI so we can make various Intel-specific AUX services
3979          * available (such as HDR backlight controls)
3980          */
3981         intel_edp_init_source_oui(intel_dp, true);
3982
3983         return true;
3984 }
3985
3986 static bool
3987 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3988 {
3989         if (!intel_dp->attached_connector)
3990                 return false;
3991
3992         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3993                                           intel_dp->dpcd,
3994                                           &intel_dp->desc);
3995 }
3996
3997 void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
3998 {
3999         intel_dp_set_sink_rates(intel_dp);
4000         intel_dp_set_max_sink_lane_count(intel_dp);
4001         intel_dp_set_common_rates(intel_dp);
4002 }
4003
4004 static bool
4005 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4006 {
4007         int ret;
4008
4009         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4010                 return false;
4011
4012         /*
4013          * Don't clobber cached eDP rates. Also skip re-reading
4014          * the OUI/ID since we know it won't change.
4015          */
4016         if (!intel_dp_is_edp(intel_dp)) {
4017                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4018                                  drm_dp_is_branch(intel_dp->dpcd));
4019
4020                 intel_dp_update_sink_caps(intel_dp);
4021         }
4022
4023         if (intel_dp_has_sink_count(intel_dp)) {
4024                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4025                 if (ret < 0)
4026                         return false;
4027
4028                 /*
4029                  * Sink count can change between short pulse hpd hence
4030                  * a member variable in intel_dp will track any changes
4031                  * between short pulse interrupts.
4032                  */
4033                 intel_dp->sink_count = ret;
4034
4035                 /*
4036                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4037                  * a dongle is present but no display. Unless we require to know
4038                  * if a dongle is present or not, we don't need to update
4039                  * downstream port information. So, an early return here saves
4040                  * time from performing other operations which are not required.
4041                  */
4042                 if (!intel_dp->sink_count)
4043                         return false;
4044         }
4045
4046         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4047                                            intel_dp->downstream_ports) == 0;
4048 }
4049
4050 static bool
4051 intel_dp_can_mst(struct intel_dp *intel_dp)
4052 {
4053         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4054
4055         return i915->display.params.enable_dp_mst &&
4056                 intel_dp_mst_source_support(intel_dp) &&
4057                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4058 }
4059
4060 static void
4061 intel_dp_configure_mst(struct intel_dp *intel_dp)
4062 {
4063         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4064         struct intel_encoder *encoder =
4065                 &dp_to_dig_port(intel_dp)->base;
4066         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4067
4068         drm_dbg_kms(&i915->drm,
4069                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4070                     encoder->base.base.id, encoder->base.name,
4071                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4072                     str_yes_no(sink_can_mst),
4073                     str_yes_no(i915->display.params.enable_dp_mst));
4074
4075         if (!intel_dp_mst_source_support(intel_dp))
4076                 return;
4077
4078         intel_dp->is_mst = sink_can_mst &&
4079                 i915->display.params.enable_dp_mst;
4080
4081         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4082                                         intel_dp->is_mst);
4083 }
4084
4085 static bool
4086 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4087 {
4088         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4089 }
4090
4091 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4092 {
4093         int retry;
4094
4095         for (retry = 0; retry < 3; retry++) {
4096                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4097                                       &esi[1], 3) == 3)
4098                         return true;
4099         }
4100
4101         return false;
4102 }
4103
4104 bool
4105 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4106                        const struct drm_connector_state *conn_state)
4107 {
4108         /*
4109          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4110          * of Color Encoding Format and Content Color Gamut], in order to
4111          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4112          */
4113         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4114                 return true;
4115
4116         switch (conn_state->colorspace) {
4117         case DRM_MODE_COLORIMETRY_SYCC_601:
4118         case DRM_MODE_COLORIMETRY_OPYCC_601:
4119         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4120         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4121         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4122                 return true;
4123         default:
4124                 break;
4125         }
4126
4127         return false;
4128 }
4129
4130 static ssize_t
4131 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4132                                          const struct hdmi_drm_infoframe *drm_infoframe,
4133                                          struct dp_sdp *sdp,
4134                                          size_t size)
4135 {
4136         size_t length = sizeof(struct dp_sdp);
4137         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4138         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4139         ssize_t len;
4140
4141         if (size < length)
4142                 return -ENOSPC;
4143
4144         memset(sdp, 0, size);
4145
4146         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4147         if (len < 0) {
4148                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4149                 return -ENOSPC;
4150         }
4151
4152         if (len != infoframe_size) {
4153                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4154                 return -ENOSPC;
4155         }
4156
4157         /*
4158          * Set up the infoframe sdp packet for HDR static metadata.
4159          * Prepare VSC Header for SU as per DP 1.4a spec,
4160          * Table 2-100 and Table 2-101
4161          */
4162
4163         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4164         sdp->sdp_header.HB0 = 0;
4165         /*
4166          * Packet Type 80h + Non-audio INFOFRAME Type value
4167          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4168          * - 80h + Non-audio INFOFRAME Type value
4169          * - InfoFrame Type: 0x07
4170          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4171          */
4172         sdp->sdp_header.HB1 = drm_infoframe->type;
4173         /*
4174          * Least Significant Eight Bits of (Data Byte Count – 1)
4175          * infoframe_size - 1
4176          */
4177         sdp->sdp_header.HB2 = 0x1D;
4178         /* INFOFRAME SDP Version Number */
4179         sdp->sdp_header.HB3 = (0x13 << 2);
4180         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4181         sdp->db[0] = drm_infoframe->version;
4182         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4183         sdp->db[1] = drm_infoframe->length;
4184         /*
4185          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4186          * HDMI_INFOFRAME_HEADER_SIZE
4187          */
4188         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4189         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4190                HDMI_DRM_INFOFRAME_SIZE);
4191
4192         /*
4193          * Size of DP infoframe sdp packet for HDR static metadata consists of
4194          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4195          * - Two Data Blocks: 2 bytes
4196          *    CTA Header Byte2 (INFOFRAME Version Number)
4197          *    CTA Header Byte3 (Length of INFOFRAME)
4198          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4199          *
4200          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4201          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4202          * will pad rest of the size.
4203          */
4204         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4205 }
4206
4207 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4208                                const struct intel_crtc_state *crtc_state,
4209                                unsigned int type)
4210 {
4211         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4213         struct dp_sdp sdp = {};
4214         ssize_t len;
4215
4216         if ((crtc_state->infoframes.enable &
4217              intel_hdmi_infoframe_enable(type)) == 0)
4218                 return;
4219
4220         switch (type) {
4221         case DP_SDP_VSC:
4222                 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4223                 break;
4224         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4225                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4226                                                                &crtc_state->infoframes.drm.drm,
4227                                                                &sdp, sizeof(sdp));
4228                 break;
4229         default:
4230                 MISSING_CASE(type);
4231                 return;
4232         }
4233
4234         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4235                 return;
4236
4237         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4238 }
4239
4240 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4241                              bool enable,
4242                              const struct intel_crtc_state *crtc_state,
4243                              const struct drm_connector_state *conn_state)
4244 {
4245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4246         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4247         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4248                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4249                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4250         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4251
4252         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4253         if (!enable && HAS_DSC(dev_priv))
4254                 val &= ~VDIP_ENABLE_PPS;
4255
4256         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4257         if (!crtc_state->has_psr)
4258                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4259
4260         intel_de_write(dev_priv, reg, val);
4261         intel_de_posting_read(dev_priv, reg);
4262
4263         if (!enable)
4264                 return;
4265
4266         intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4267
4268         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4269 }
4270
4271 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4272                                    const void *buffer, size_t size)
4273 {
4274         const struct dp_sdp *sdp = buffer;
4275
4276         if (size < sizeof(struct dp_sdp))
4277                 return -EINVAL;
4278
4279         memset(vsc, 0, sizeof(*vsc));
4280
4281         if (sdp->sdp_header.HB0 != 0)
4282                 return -EINVAL;
4283
4284         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4285                 return -EINVAL;
4286
4287         vsc->sdp_type = sdp->sdp_header.HB1;
4288         vsc->revision = sdp->sdp_header.HB2;
4289         vsc->length = sdp->sdp_header.HB3;
4290
4291         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4292             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4293                 /*
4294                  * - HB2 = 0x2, HB3 = 0x8
4295                  *   VSC SDP supporting 3D stereo + PSR
4296                  * - HB2 = 0x4, HB3 = 0xe
4297                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4298                  *   first scan line of the SU region (applies to eDP v1.4b
4299                  *   and higher).
4300                  */
4301                 return 0;
4302         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4303                 /*
4304                  * - HB2 = 0x5, HB3 = 0x13
4305                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4306                  *   Format.
4307                  */
4308                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4309                 vsc->colorimetry = sdp->db[16] & 0xf;
4310                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4311
4312                 switch (sdp->db[17] & 0x7) {
4313                 case 0x0:
4314                         vsc->bpc = 6;
4315                         break;
4316                 case 0x1:
4317                         vsc->bpc = 8;
4318                         break;
4319                 case 0x2:
4320                         vsc->bpc = 10;
4321                         break;
4322                 case 0x3:
4323                         vsc->bpc = 12;
4324                         break;
4325                 case 0x4:
4326                         vsc->bpc = 16;
4327                         break;
4328                 default:
4329                         MISSING_CASE(sdp->db[17] & 0x7);
4330                         return -EINVAL;
4331                 }
4332
4333                 vsc->content_type = sdp->db[18] & 0x7;
4334         } else {
4335                 return -EINVAL;
4336         }
4337
4338         return 0;
4339 }
4340
4341 static int
4342 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4343                                            const void *buffer, size_t size)
4344 {
4345         int ret;
4346
4347         const struct dp_sdp *sdp = buffer;
4348
4349         if (size < sizeof(struct dp_sdp))
4350                 return -EINVAL;
4351
4352         if (sdp->sdp_header.HB0 != 0)
4353                 return -EINVAL;
4354
4355         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4356                 return -EINVAL;
4357
4358         /*
4359          * Least Significant Eight Bits of (Data Byte Count – 1)
4360          * 1Dh (i.e., Data Byte Count = 30 bytes).
4361          */
4362         if (sdp->sdp_header.HB2 != 0x1D)
4363                 return -EINVAL;
4364
4365         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4366         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4367                 return -EINVAL;
4368
4369         /* INFOFRAME SDP Version Number */
4370         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4371                 return -EINVAL;
4372
4373         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4374         if (sdp->db[0] != 1)
4375                 return -EINVAL;
4376
4377         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4378         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4379                 return -EINVAL;
4380
4381         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4382                                              HDMI_DRM_INFOFRAME_SIZE);
4383
4384         return ret;
4385 }
4386
4387 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4388                                   struct intel_crtc_state *crtc_state,
4389                                   struct drm_dp_vsc_sdp *vsc)
4390 {
4391         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4392         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4393         unsigned int type = DP_SDP_VSC;
4394         struct dp_sdp sdp = {};
4395         int ret;
4396
4397         if ((crtc_state->infoframes.enable &
4398              intel_hdmi_infoframe_enable(type)) == 0)
4399                 return;
4400
4401         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4402
4403         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4404
4405         if (ret)
4406                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4407 }
4408
4409 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4410                                                      struct intel_crtc_state *crtc_state,
4411                                                      struct hdmi_drm_infoframe *drm_infoframe)
4412 {
4413         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4414         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4415         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4416         struct dp_sdp sdp = {};
4417         int ret;
4418
4419         if ((crtc_state->infoframes.enable &
4420             intel_hdmi_infoframe_enable(type)) == 0)
4421                 return;
4422
4423         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4424                                  sizeof(sdp));
4425
4426         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4427                                                          sizeof(sdp));
4428
4429         if (ret)
4430                 drm_dbg_kms(&dev_priv->drm,
4431                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4432 }
4433
4434 void intel_read_dp_sdp(struct intel_encoder *encoder,
4435                        struct intel_crtc_state *crtc_state,
4436                        unsigned int type)
4437 {
4438         switch (type) {
4439         case DP_SDP_VSC:
4440                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4441                                       &crtc_state->infoframes.vsc);
4442                 break;
4443         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4444                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4445                                                          &crtc_state->infoframes.drm.drm);
4446                 break;
4447         default:
4448                 MISSING_CASE(type);
4449                 break;
4450         }
4451 }
4452
4453 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4454 {
4455         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4456         int status = 0;
4457         int test_link_rate;
4458         u8 test_lane_count, test_link_bw;
4459         /* (DP CTS 1.2)
4460          * 4.3.1.11
4461          */
4462         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4463         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4464                                    &test_lane_count);
4465
4466         if (status <= 0) {
4467                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4468                 return DP_TEST_NAK;
4469         }
4470         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4471
4472         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4473                                    &test_link_bw);
4474         if (status <= 0) {
4475                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4476                 return DP_TEST_NAK;
4477         }
4478         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4479
4480         /* Validate the requested link rate and lane count */
4481         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4482                                         test_lane_count))
4483                 return DP_TEST_NAK;
4484
4485         intel_dp->compliance.test_lane_count = test_lane_count;
4486         intel_dp->compliance.test_link_rate = test_link_rate;
4487
4488         return DP_TEST_ACK;
4489 }
4490
4491 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4492 {
4493         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4494         u8 test_pattern;
4495         u8 test_misc;
4496         __be16 h_width, v_height;
4497         int status = 0;
4498
4499         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4500         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4501                                    &test_pattern);
4502         if (status <= 0) {
4503                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4504                 return DP_TEST_NAK;
4505         }
4506         if (test_pattern != DP_COLOR_RAMP)
4507                 return DP_TEST_NAK;
4508
4509         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4510                                   &h_width, 2);
4511         if (status <= 0) {
4512                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4513                 return DP_TEST_NAK;
4514         }
4515
4516         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4517                                   &v_height, 2);
4518         if (status <= 0) {
4519                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4520                 return DP_TEST_NAK;
4521         }
4522
4523         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4524                                    &test_misc);
4525         if (status <= 0) {
4526                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4527                 return DP_TEST_NAK;
4528         }
4529         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4530                 return DP_TEST_NAK;
4531         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4532                 return DP_TEST_NAK;
4533         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4534         case DP_TEST_BIT_DEPTH_6:
4535                 intel_dp->compliance.test_data.bpc = 6;
4536                 break;
4537         case DP_TEST_BIT_DEPTH_8:
4538                 intel_dp->compliance.test_data.bpc = 8;
4539                 break;
4540         default:
4541                 return DP_TEST_NAK;
4542         }
4543
4544         intel_dp->compliance.test_data.video_pattern = test_pattern;
4545         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4546         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4547         /* Set test active flag here so userspace doesn't interrupt things */
4548         intel_dp->compliance.test_active = true;
4549
4550         return DP_TEST_ACK;
4551 }
4552
4553 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4554 {
4555         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4556         u8 test_result = DP_TEST_ACK;
4557         struct intel_connector *intel_connector = intel_dp->attached_connector;
4558         struct drm_connector *connector = &intel_connector->base;
4559
4560         if (intel_connector->detect_edid == NULL ||
4561             connector->edid_corrupt ||
4562             intel_dp->aux.i2c_defer_count > 6) {
4563                 /* Check EDID read for NACKs, DEFERs and corruption
4564                  * (DP CTS 1.2 Core r1.1)
4565                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4566                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4567                  *    4.2.2.6 : EDID corruption detected
4568                  * Use failsafe mode for all cases
4569                  */
4570                 if (intel_dp->aux.i2c_nack_count > 0 ||
4571                         intel_dp->aux.i2c_defer_count > 0)
4572                         drm_dbg_kms(&i915->drm,
4573                                     "EDID read had %d NACKs, %d DEFERs\n",
4574                                     intel_dp->aux.i2c_nack_count,
4575                                     intel_dp->aux.i2c_defer_count);
4576                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4577         } else {
4578                 /* FIXME: Get rid of drm_edid_raw() */
4579                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4580
4581                 /* We have to write the checksum of the last block read */
4582                 block += block->extensions;
4583
4584                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4585                                        block->checksum) <= 0)
4586                         drm_dbg_kms(&i915->drm,
4587                                     "Failed to write EDID checksum\n");
4588
4589                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4590                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4591         }
4592
4593         /* Set test active flag here so userspace doesn't interrupt things */
4594         intel_dp->compliance.test_active = true;
4595
4596         return test_result;
4597 }
4598
4599 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4600                                         const struct intel_crtc_state *crtc_state)
4601 {
4602         struct drm_i915_private *dev_priv =
4603                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4604         struct drm_dp_phy_test_params *data =
4605                         &intel_dp->compliance.test_data.phytest;
4606         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4607         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4608         enum pipe pipe = crtc->pipe;
4609         u32 pattern_val;
4610
4611         switch (data->phy_pattern) {
4612         case DP_LINK_QUAL_PATTERN_DISABLE:
4613                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4614                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4615                 if (DISPLAY_VER(dev_priv) >= 10)
4616                         intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4617                                      DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4618                                      DP_TP_CTL_LINK_TRAIN_NORMAL);
4619                 break;
4620         case DP_LINK_QUAL_PATTERN_D10_2:
4621                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4622                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4623                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4624                 break;
4625         case DP_LINK_QUAL_PATTERN_ERROR_RATE:
4626                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4627                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4628                                DDI_DP_COMP_CTL_ENABLE |
4629                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4630                 break;
4631         case DP_LINK_QUAL_PATTERN_PRBS7:
4632                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4633                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4634                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4635                 break;
4636         case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:
4637                 /*
4638                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4639                  * current firmware of DPR-100 could not set it, so hardcoding
4640                  * now for complaince test.
4641                  */
4642                 drm_dbg_kms(&dev_priv->drm,
4643                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4644                 pattern_val = 0x3e0f83e0;
4645                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4646                 pattern_val = 0x0f83e0f8;
4647                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4648                 pattern_val = 0x0000f83e;
4649                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4650                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4651                                DDI_DP_COMP_CTL_ENABLE |
4652                                DDI_DP_COMP_CTL_CUSTOM80);
4653                 break;
4654         case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:
4655                 /*
4656                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4657                  * current firmware of DPR-100 could not set it, so hardcoding
4658                  * now for complaince test.
4659                  */
4660                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4661                 pattern_val = 0xFB;
4662                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4663                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4664                                pattern_val);
4665                 break;
4666         case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
4667                 if (DISPLAY_VER(dev_priv) < 10)  {
4668                         drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");
4669                         break;
4670                 }
4671                 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");
4672                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4673                 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
4674                              DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,
4675                              DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);
4676                 break;
4677         default:
4678                 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");
4679         }
4680 }
4681
4682 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4683                                          const struct intel_crtc_state *crtc_state)
4684 {
4685         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4686         struct drm_dp_phy_test_params *data =
4687                 &intel_dp->compliance.test_data.phytest;
4688         u8 link_status[DP_LINK_STATUS_SIZE];
4689
4690         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4691                                              link_status) < 0) {
4692                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4693                 return;
4694         }
4695
4696         /* retrieve vswing & pre-emphasis setting */
4697         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4698                                   link_status);
4699
4700         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4701
4702         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4703
4704         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4705                           intel_dp->train_set, crtc_state->lane_count);
4706
4707         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4708                                     intel_dp->dpcd[DP_DPCD_REV]);
4709 }
4710
4711 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4712 {
4713         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4714         struct drm_dp_phy_test_params *data =
4715                 &intel_dp->compliance.test_data.phytest;
4716
4717         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4718                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4719                 return DP_TEST_NAK;
4720         }
4721
4722         /* Set test active flag here so userspace doesn't interrupt things */
4723         intel_dp->compliance.test_active = true;
4724
4725         return DP_TEST_ACK;
4726 }
4727
4728 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4729 {
4730         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4731         u8 response = DP_TEST_NAK;
4732         u8 request = 0;
4733         int status;
4734
4735         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4736         if (status <= 0) {
4737                 drm_dbg_kms(&i915->drm,
4738                             "Could not read test request from sink\n");
4739                 goto update_status;
4740         }
4741
4742         switch (request) {
4743         case DP_TEST_LINK_TRAINING:
4744                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4745                 response = intel_dp_autotest_link_training(intel_dp);
4746                 break;
4747         case DP_TEST_LINK_VIDEO_PATTERN:
4748                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4749                 response = intel_dp_autotest_video_pattern(intel_dp);
4750                 break;
4751         case DP_TEST_LINK_EDID_READ:
4752                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4753                 response = intel_dp_autotest_edid(intel_dp);
4754                 break;
4755         case DP_TEST_LINK_PHY_TEST_PATTERN:
4756                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4757                 response = intel_dp_autotest_phy_pattern(intel_dp);
4758                 break;
4759         default:
4760                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4761                             request);
4762                 break;
4763         }
4764
4765         if (response & DP_TEST_ACK)
4766                 intel_dp->compliance.test_type = request;
4767
4768 update_status:
4769         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4770         if (status <= 0)
4771                 drm_dbg_kms(&i915->drm,
4772                             "Could not write test response to sink\n");
4773 }
4774
4775 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4776                              u8 link_status[DP_LINK_STATUS_SIZE])
4777 {
4778         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4779         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4780         bool uhbr = intel_dp->link_rate >= 1000000;
4781         bool ok;
4782
4783         if (uhbr)
4784                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4785                                                           intel_dp->lane_count);
4786         else
4787                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4788
4789         if (ok)
4790                 return true;
4791
4792         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4793         drm_dbg_kms(&i915->drm,
4794                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4795                     encoder->base.base.id, encoder->base.name,
4796                     uhbr ? "128b/132b" : "8b/10b");
4797
4798         return false;
4799 }
4800
4801 static void
4802 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4803 {
4804         bool handled = false;
4805
4806         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4807
4808         if (esi[1] & DP_CP_IRQ) {
4809                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4810                 ack[1] |= DP_CP_IRQ;
4811         }
4812 }
4813
4814 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4815 {
4816         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4817         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4818         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4819         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4820
4821         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4822                              esi_link_status_size) != esi_link_status_size) {
4823                 drm_err(&i915->drm,
4824                         "[ENCODER:%d:%s] Failed to read link status\n",
4825                         encoder->base.base.id, encoder->base.name);
4826                 return false;
4827         }
4828
4829         return intel_dp_link_ok(intel_dp, link_status);
4830 }
4831
4832 /**
4833  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4834  * @intel_dp: Intel DP struct
4835  *
4836  * Read any pending MST interrupts, call MST core to handle these and ack the
4837  * interrupts. Check if the main and AUX link state is ok.
4838  *
4839  * Returns:
4840  * - %true if pending interrupts were serviced (or no interrupts were
4841  *   pending) w/o detecting an error condition.
4842  * - %false if an error condition - like AUX failure or a loss of link - is
4843  *   detected, or another condition - like a DP tunnel BW state change - needs
4844  *   servicing from the hotplug work.
4845  */
4846 static bool
4847 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4848 {
4849         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4850         bool link_ok = true;
4851         bool reprobe_needed = false;
4852
4853         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4854
4855         for (;;) {
4856                 u8 esi[4] = {};
4857                 u8 ack[4] = {};
4858
4859                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4860                         drm_dbg_kms(&i915->drm,
4861                                     "failed to get ESI - device may have failed\n");
4862                         link_ok = false;
4863
4864                         break;
4865                 }
4866
4867                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4868
4869                 if (intel_dp->active_mst_links > 0 && link_ok &&
4870                     esi[3] & LINK_STATUS_CHANGED) {
4871                         if (!intel_dp_mst_link_status(intel_dp))
4872                                 link_ok = false;
4873                         ack[3] |= LINK_STATUS_CHANGED;
4874                 }
4875
4876                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4877
4878                 if (esi[3] & DP_TUNNELING_IRQ) {
4879                         if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4880                                                      &intel_dp->aux))
4881                                 reprobe_needed = true;
4882                         ack[3] |= DP_TUNNELING_IRQ;
4883                 }
4884
4885                 if (!memchr_inv(ack, 0, sizeof(ack)))
4886                         break;
4887
4888                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4889                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4890
4891                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4892                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4893         }
4894
4895         return link_ok && !reprobe_needed;
4896 }
4897
4898 static void
4899 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4900 {
4901         bool is_active;
4902         u8 buf = 0;
4903
4904         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4905         if (intel_dp->frl.is_trained && !is_active) {
4906                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4907                         return;
4908
4909                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4910                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4911                         return;
4912
4913                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4914
4915                 intel_dp->frl.is_trained = false;
4916
4917                 /* Restart FRL training or fall back to TMDS mode */
4918                 intel_dp_check_frl_training(intel_dp);
4919         }
4920 }
4921
4922 static bool
4923 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4924 {
4925         u8 link_status[DP_LINK_STATUS_SIZE];
4926
4927         if (!intel_dp->link_trained)
4928                 return false;
4929
4930         /*
4931          * While PSR source HW is enabled, it will control main-link sending
4932          * frames, enabling and disabling it so trying to do a retrain will fail
4933          * as the link would or not be on or it could mix training patterns
4934          * and frame data at the same time causing retrain to fail.
4935          * Also when exiting PSR, HW will retrain the link anyways fixing
4936          * any link status error.
4937          */
4938         if (intel_psr_enabled(intel_dp))
4939                 return false;
4940
4941         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4942                                              link_status) < 0)
4943                 return false;
4944
4945         /*
4946          * Validate the cached values of intel_dp->link_rate and
4947          * intel_dp->lane_count before attempting to retrain.
4948          *
4949          * FIXME would be nice to user the crtc state here, but since
4950          * we need to call this from the short HPD handler that seems
4951          * a bit hard.
4952          */
4953         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4954                                         intel_dp->lane_count))
4955                 return false;
4956
4957         /* Retrain if link not ok */
4958         return !intel_dp_link_ok(intel_dp, link_status);
4959 }
4960
4961 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4962                                    const struct drm_connector_state *conn_state)
4963 {
4964         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4965         struct intel_encoder *encoder;
4966         enum pipe pipe;
4967
4968         if (!conn_state->best_encoder)
4969                 return false;
4970
4971         /* SST */
4972         encoder = &dp_to_dig_port(intel_dp)->base;
4973         if (conn_state->best_encoder == &encoder->base)
4974                 return true;
4975
4976         /* MST */
4977         for_each_pipe(i915, pipe) {
4978                 encoder = &intel_dp->mst_encoders[pipe]->base;
4979                 if (conn_state->best_encoder == &encoder->base)
4980                         return true;
4981         }
4982
4983         return false;
4984 }
4985
4986 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4987                               struct drm_modeset_acquire_ctx *ctx,
4988                               u8 *pipe_mask)
4989 {
4990         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4991         struct drm_connector_list_iter conn_iter;
4992         struct intel_connector *connector;
4993         int ret = 0;
4994
4995         *pipe_mask = 0;
4996
4997         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4998         for_each_intel_connector_iter(connector, &conn_iter) {
4999                 struct drm_connector_state *conn_state =
5000                         connector->base.state;
5001                 struct intel_crtc_state *crtc_state;
5002                 struct intel_crtc *crtc;
5003
5004                 if (!intel_dp_has_connector(intel_dp, conn_state))
5005                         continue;
5006
5007                 crtc = to_intel_crtc(conn_state->crtc);
5008                 if (!crtc)
5009                         continue;
5010
5011                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5012                 if (ret)
5013                         break;
5014
5015                 crtc_state = to_intel_crtc_state(crtc->base.state);
5016
5017                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5018
5019                 if (!crtc_state->hw.active)
5020                         continue;
5021
5022                 if (conn_state->commit)
5023                         drm_WARN_ON(&i915->drm,
5024                                     !wait_for_completion_timeout(&conn_state->commit->hw_done,
5025                                                                  msecs_to_jiffies(5000)));
5026
5027                 *pipe_mask |= BIT(crtc->pipe);
5028         }
5029         drm_connector_list_iter_end(&conn_iter);
5030
5031         return ret;
5032 }
5033
5034 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5035 {
5036         struct intel_connector *connector = intel_dp->attached_connector;
5037
5038         return connector->base.status == connector_status_connected ||
5039                 intel_dp->is_mst;
5040 }
5041
5042 int intel_dp_retrain_link(struct intel_encoder *encoder,
5043                           struct drm_modeset_acquire_ctx *ctx)
5044 {
5045         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5046         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5047         struct intel_crtc *crtc;
5048         u8 pipe_mask;
5049         int ret;
5050
5051         if (!intel_dp_is_connected(intel_dp))
5052                 return 0;
5053
5054         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5055                                ctx);
5056         if (ret)
5057                 return ret;
5058
5059         if (!intel_dp_needs_link_retrain(intel_dp))
5060                 return 0;
5061
5062         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5063         if (ret)
5064                 return ret;
5065
5066         if (pipe_mask == 0)
5067                 return 0;
5068
5069         if (!intel_dp_needs_link_retrain(intel_dp))
5070                 return 0;
5071
5072         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5073                     encoder->base.base.id, encoder->base.name);
5074
5075         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5076                 const struct intel_crtc_state *crtc_state =
5077                         to_intel_crtc_state(crtc->base.state);
5078
5079                 /* Suppress underruns caused by re-training */
5080                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5081                 if (crtc_state->has_pch_encoder)
5082                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5083                                                               intel_crtc_pch_transcoder(crtc), false);
5084         }
5085
5086         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5087                 const struct intel_crtc_state *crtc_state =
5088                         to_intel_crtc_state(crtc->base.state);
5089
5090                 /* retrain on the MST master transcoder */
5091                 if (DISPLAY_VER(dev_priv) >= 12 &&
5092                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5093                     !intel_dp_mst_is_master_trans(crtc_state))
5094                         continue;
5095
5096                 intel_dp_check_frl_training(intel_dp);
5097                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5098                 intel_dp_start_link_train(intel_dp, crtc_state);
5099                 intel_dp_stop_link_train(intel_dp, crtc_state);
5100                 break;
5101         }
5102
5103         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5104                 const struct intel_crtc_state *crtc_state =
5105                         to_intel_crtc_state(crtc->base.state);
5106
5107                 /* Keep underrun reporting disabled until things are stable */
5108                 intel_crtc_wait_for_next_vblank(crtc);
5109
5110                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5111                 if (crtc_state->has_pch_encoder)
5112                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5113                                                               intel_crtc_pch_transcoder(crtc), true);
5114         }
5115
5116         return 0;
5117 }
5118
5119 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5120                                   struct drm_modeset_acquire_ctx *ctx,
5121                                   u8 *pipe_mask)
5122 {
5123         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5124         struct drm_connector_list_iter conn_iter;
5125         struct intel_connector *connector;
5126         int ret = 0;
5127
5128         *pipe_mask = 0;
5129
5130         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5131         for_each_intel_connector_iter(connector, &conn_iter) {
5132                 struct drm_connector_state *conn_state =
5133                         connector->base.state;
5134                 struct intel_crtc_state *crtc_state;
5135                 struct intel_crtc *crtc;
5136
5137                 if (!intel_dp_has_connector(intel_dp, conn_state))
5138                         continue;
5139
5140                 crtc = to_intel_crtc(conn_state->crtc);
5141                 if (!crtc)
5142                         continue;
5143
5144                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5145                 if (ret)
5146                         break;
5147
5148                 crtc_state = to_intel_crtc_state(crtc->base.state);
5149
5150                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5151
5152                 if (!crtc_state->hw.active)
5153                         continue;
5154
5155                 if (conn_state->commit &&
5156                     !try_wait_for_completion(&conn_state->commit->hw_done))
5157                         continue;
5158
5159                 *pipe_mask |= BIT(crtc->pipe);
5160         }
5161         drm_connector_list_iter_end(&conn_iter);
5162
5163         return ret;
5164 }
5165
5166 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5167                                 struct drm_modeset_acquire_ctx *ctx)
5168 {
5169         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5170         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5171         struct intel_crtc *crtc;
5172         u8 pipe_mask;
5173         int ret;
5174
5175         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5176                                ctx);
5177         if (ret)
5178                 return ret;
5179
5180         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5181         if (ret)
5182                 return ret;
5183
5184         if (pipe_mask == 0)
5185                 return 0;
5186
5187         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5188                     encoder->base.base.id, encoder->base.name);
5189
5190         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5191                 const struct intel_crtc_state *crtc_state =
5192                         to_intel_crtc_state(crtc->base.state);
5193
5194                 /* test on the MST master transcoder */
5195                 if (DISPLAY_VER(dev_priv) >= 12 &&
5196                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5197                     !intel_dp_mst_is_master_trans(crtc_state))
5198                         continue;
5199
5200                 intel_dp_process_phy_request(intel_dp, crtc_state);
5201                 break;
5202         }
5203
5204         return 0;
5205 }
5206
5207 void intel_dp_phy_test(struct intel_encoder *encoder)
5208 {
5209         struct drm_modeset_acquire_ctx ctx;
5210         int ret;
5211
5212         drm_modeset_acquire_init(&ctx, 0);
5213
5214         for (;;) {
5215                 ret = intel_dp_do_phy_test(encoder, &ctx);
5216
5217                 if (ret == -EDEADLK) {
5218                         drm_modeset_backoff(&ctx);
5219                         continue;
5220                 }
5221
5222                 break;
5223         }
5224
5225         drm_modeset_drop_locks(&ctx);
5226         drm_modeset_acquire_fini(&ctx);
5227         drm_WARN(encoder->base.dev, ret,
5228                  "Acquiring modeset locks failed with %i\n", ret);
5229 }
5230
5231 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5232 {
5233         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5234         u8 val;
5235
5236         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5237                 return;
5238
5239         if (drm_dp_dpcd_readb(&intel_dp->aux,
5240                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5241                 return;
5242
5243         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5244
5245         if (val & DP_AUTOMATED_TEST_REQUEST)
5246                 intel_dp_handle_test_request(intel_dp);
5247
5248         if (val & DP_CP_IRQ)
5249                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5250
5251         if (val & DP_SINK_SPECIFIC_IRQ)
5252                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5253 }
5254
5255 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5256 {
5257         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5258         bool reprobe_needed = false;
5259         u8 val;
5260
5261         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5262                 return false;
5263
5264         if (drm_dp_dpcd_readb(&intel_dp->aux,
5265                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5266                 return false;
5267
5268         if ((val & DP_TUNNELING_IRQ) &&
5269             drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5270                                      &intel_dp->aux))
5271                 reprobe_needed = true;
5272
5273         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5274                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5275                 return reprobe_needed;
5276
5277         if (val & HDMI_LINK_STATUS_CHANGED)
5278                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5279
5280         return reprobe_needed;
5281 }
5282
5283 /*
5284  * According to DP spec
5285  * 5.1.2:
5286  *  1. Read DPCD
5287  *  2. Configure link according to Receiver Capabilities
5288  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5289  *  4. Check link status on receipt of hot-plug interrupt
5290  *
5291  * intel_dp_short_pulse -  handles short pulse interrupts
5292  * when full detection is not required.
5293  * Returns %true if short pulse is handled and full detection
5294  * is NOT required and %false otherwise.
5295  */
5296 static bool
5297 intel_dp_short_pulse(struct intel_dp *intel_dp)
5298 {
5299         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5300         u8 old_sink_count = intel_dp->sink_count;
5301         bool reprobe_needed = false;
5302         bool ret;
5303
5304         /*
5305          * Clearing compliance test variables to allow capturing
5306          * of values for next automated test request.
5307          */
5308         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5309
5310         /*
5311          * Now read the DPCD to see if it's actually running
5312          * If the current value of sink count doesn't match with
5313          * the value that was stored earlier or dpcd read failed
5314          * we need to do full detection
5315          */
5316         ret = intel_dp_get_dpcd(intel_dp);
5317
5318         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5319                 /* No need to proceed if we are going to do full detect */
5320                 return false;
5321         }
5322
5323         intel_dp_check_device_service_irq(intel_dp);
5324         reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5325
5326         /* Handle CEC interrupts, if any */
5327         drm_dp_cec_irq(&intel_dp->aux);
5328
5329         /* defer to the hotplug work for link retraining if needed */
5330         if (intel_dp_needs_link_retrain(intel_dp))
5331                 return false;
5332
5333         intel_psr_short_pulse(intel_dp);
5334
5335         switch (intel_dp->compliance.test_type) {
5336         case DP_TEST_LINK_TRAINING:
5337                 drm_dbg_kms(&dev_priv->drm,
5338                             "Link Training Compliance Test requested\n");
5339                 /* Send a Hotplug Uevent to userspace to start modeset */
5340                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5341                 break;
5342         case DP_TEST_LINK_PHY_TEST_PATTERN:
5343                 drm_dbg_kms(&dev_priv->drm,
5344                             "PHY test pattern Compliance Test requested\n");
5345                 /*
5346                  * Schedule long hpd to do the test
5347                  *
5348                  * FIXME get rid of the ad-hoc phy test modeset code
5349                  * and properly incorporate it into the normal modeset.
5350                  */
5351                 reprobe_needed = true;
5352         }
5353
5354         return !reprobe_needed;
5355 }
5356
5357 /* XXX this is probably wrong for multiple downstream ports */
5358 static enum drm_connector_status
5359 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5360 {
5361         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5362         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5363         u8 *dpcd = intel_dp->dpcd;
5364         u8 type;
5365
5366         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5367                 return connector_status_connected;
5368
5369         lspcon_resume(dig_port);
5370
5371         if (!intel_dp_get_dpcd(intel_dp))
5372                 return connector_status_disconnected;
5373
5374         /* if there's no downstream port, we're done */
5375         if (!drm_dp_is_branch(dpcd))
5376                 return connector_status_connected;
5377
5378         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5379         if (intel_dp_has_sink_count(intel_dp) &&
5380             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5381                 return intel_dp->sink_count ?
5382                 connector_status_connected : connector_status_disconnected;
5383         }
5384
5385         if (intel_dp_can_mst(intel_dp))
5386                 return connector_status_connected;
5387
5388         /* If no HPD, poke DDC gently */
5389         if (drm_probe_ddc(&intel_dp->aux.ddc))
5390                 return connector_status_connected;
5391
5392         /* Well we tried, say unknown for unreliable port types */
5393         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5394                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5395                 if (type == DP_DS_PORT_TYPE_VGA ||
5396                     type == DP_DS_PORT_TYPE_NON_EDID)
5397                         return connector_status_unknown;
5398         } else {
5399                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5400                         DP_DWN_STRM_PORT_TYPE_MASK;
5401                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5402                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5403                         return connector_status_unknown;
5404         }
5405
5406         /* Anything else is out of spec, warn and ignore */
5407         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5408         return connector_status_disconnected;
5409 }
5410
5411 static enum drm_connector_status
5412 edp_detect(struct intel_dp *intel_dp)
5413 {
5414         return connector_status_connected;
5415 }
5416
5417 void intel_digital_port_lock(struct intel_encoder *encoder)
5418 {
5419         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5420
5421         if (dig_port->lock)
5422                 dig_port->lock(dig_port);
5423 }
5424
5425 void intel_digital_port_unlock(struct intel_encoder *encoder)
5426 {
5427         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5428
5429         if (dig_port->unlock)
5430                 dig_port->unlock(dig_port);
5431 }
5432
5433 /*
5434  * intel_digital_port_connected_locked - is the specified port connected?
5435  * @encoder: intel_encoder
5436  *
5437  * In cases where there's a connector physically connected but it can't be used
5438  * by our hardware we also return false, since the rest of the driver should
5439  * pretty much treat the port as disconnected. This is relevant for type-C
5440  * (starting on ICL) where there's ownership involved.
5441  *
5442  * The caller must hold the lock acquired by calling intel_digital_port_lock()
5443  * when calling this function.
5444  *
5445  * Return %true if port is connected, %false otherwise.
5446  */
5447 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5448 {
5449         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5450         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5451         bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5452         bool is_connected = false;
5453         intel_wakeref_t wakeref;
5454
5455         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5456                 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5457
5458                 do {
5459                         is_connected = dig_port->connected(encoder);
5460                         if (is_connected || is_glitch_free)
5461                                 break;
5462                         usleep_range(10, 30);
5463                 } while (time_before(jiffies, wait_expires));
5464         }
5465
5466         return is_connected;
5467 }
5468
5469 bool intel_digital_port_connected(struct intel_encoder *encoder)
5470 {
5471         bool ret;
5472
5473         intel_digital_port_lock(encoder);
5474         ret = intel_digital_port_connected_locked(encoder);
5475         intel_digital_port_unlock(encoder);
5476
5477         return ret;
5478 }
5479
5480 static const struct drm_edid *
5481 intel_dp_get_edid(struct intel_dp *intel_dp)
5482 {
5483         struct intel_connector *connector = intel_dp->attached_connector;
5484         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5485
5486         /* Use panel fixed edid if we have one */
5487         if (fixed_edid) {
5488                 /* invalid edid */
5489                 if (IS_ERR(fixed_edid))
5490                         return NULL;
5491
5492                 return drm_edid_dup(fixed_edid);
5493         }
5494
5495         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5496 }
5497
5498 static void
5499 intel_dp_update_dfp(struct intel_dp *intel_dp,
5500                     const struct drm_edid *drm_edid)
5501 {
5502         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5503         struct intel_connector *connector = intel_dp->attached_connector;
5504
5505         intel_dp->dfp.max_bpc =
5506                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5507                                           intel_dp->downstream_ports, drm_edid);
5508
5509         intel_dp->dfp.max_dotclock =
5510                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5511                                                intel_dp->downstream_ports);
5512
5513         intel_dp->dfp.min_tmds_clock =
5514                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5515                                                  intel_dp->downstream_ports,
5516                                                  drm_edid);
5517         intel_dp->dfp.max_tmds_clock =
5518                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5519                                                  intel_dp->downstream_ports,
5520                                                  drm_edid);
5521
5522         intel_dp->dfp.pcon_max_frl_bw =
5523                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5524                                            intel_dp->downstream_ports);
5525
5526         drm_dbg_kms(&i915->drm,
5527                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5528                     connector->base.base.id, connector->base.name,
5529                     intel_dp->dfp.max_bpc,
5530                     intel_dp->dfp.max_dotclock,
5531                     intel_dp->dfp.min_tmds_clock,
5532                     intel_dp->dfp.max_tmds_clock,
5533                     intel_dp->dfp.pcon_max_frl_bw);
5534
5535         intel_dp_get_pcon_dsc_cap(intel_dp);
5536 }
5537
5538 static bool
5539 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5540 {
5541         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5542             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5543                 return true;
5544
5545         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5546             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5547                 return true;
5548
5549         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5550             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5551                 return true;
5552
5553         return false;
5554 }
5555
5556 static void
5557 intel_dp_update_420(struct intel_dp *intel_dp)
5558 {
5559         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5560         struct intel_connector *connector = intel_dp->attached_connector;
5561
5562         intel_dp->dfp.ycbcr420_passthrough =
5563                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5564                                                   intel_dp->downstream_ports);
5565         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5566         intel_dp->dfp.ycbcr_444_to_420 =
5567                 dp_to_dig_port(intel_dp)->lspcon.active ||
5568                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5569                                                         intel_dp->downstream_ports);
5570         intel_dp->dfp.rgb_to_ycbcr =
5571                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5572                                                           intel_dp->downstream_ports,
5573                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5574
5575         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5576
5577         drm_dbg_kms(&i915->drm,
5578                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5579                     connector->base.base.id, connector->base.name,
5580                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5581                     str_yes_no(connector->base.ycbcr_420_allowed),
5582                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5583 }
5584
5585 static void
5586 intel_dp_set_edid(struct intel_dp *intel_dp)
5587 {
5588         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5589         struct intel_connector *connector = intel_dp->attached_connector;
5590         const struct drm_edid *drm_edid;
5591         bool vrr_capable;
5592
5593         intel_dp_unset_edid(intel_dp);
5594         drm_edid = intel_dp_get_edid(intel_dp);
5595         connector->detect_edid = drm_edid;
5596
5597         /* Below we depend on display info having been updated */
5598         drm_edid_connector_update(&connector->base, drm_edid);
5599
5600         vrr_capable = intel_vrr_is_capable(connector);
5601         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5602                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5603         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5604
5605         intel_dp_update_dfp(intel_dp, drm_edid);
5606         intel_dp_update_420(intel_dp);
5607
5608         drm_dp_cec_attach(&intel_dp->aux,
5609                           connector->base.display_info.source_physical_address);
5610 }
5611
5612 static void
5613 intel_dp_unset_edid(struct intel_dp *intel_dp)
5614 {
5615         struct intel_connector *connector = intel_dp->attached_connector;
5616
5617         drm_dp_cec_unset_edid(&intel_dp->aux);
5618         drm_edid_free(connector->detect_edid);
5619         connector->detect_edid = NULL;
5620
5621         intel_dp->dfp.max_bpc = 0;
5622         intel_dp->dfp.max_dotclock = 0;
5623         intel_dp->dfp.min_tmds_clock = 0;
5624         intel_dp->dfp.max_tmds_clock = 0;
5625
5626         intel_dp->dfp.pcon_max_frl_bw = 0;
5627
5628         intel_dp->dfp.ycbcr_444_to_420 = false;
5629         connector->base.ycbcr_420_allowed = false;
5630
5631         drm_connector_set_vrr_capable_property(&connector->base,
5632                                                false);
5633 }
5634
5635 static void
5636 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5637 {
5638         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5639
5640         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5641         if (!HAS_DSC(i915))
5642                 return;
5643
5644         if (intel_dp_is_edp(intel_dp))
5645                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5646                                            connector);
5647         else
5648                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5649                                           connector);
5650 }
5651
5652 static int
5653 intel_dp_detect(struct drm_connector *connector,
5654                 struct drm_modeset_acquire_ctx *ctx,
5655                 bool force)
5656 {
5657         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5658         struct intel_connector *intel_connector =
5659                 to_intel_connector(connector);
5660         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5661         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5662         struct intel_encoder *encoder = &dig_port->base;
5663         enum drm_connector_status status;
5664         int ret;
5665
5666         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5667                     connector->base.id, connector->name);
5668         drm_WARN_ON(&dev_priv->drm,
5669                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5670
5671         if (!intel_display_device_enabled(dev_priv))
5672                 return connector_status_disconnected;
5673
5674         if (!intel_display_driver_check_access(dev_priv))
5675                 return connector->status;
5676
5677         /* Can't disconnect eDP */
5678         if (intel_dp_is_edp(intel_dp))
5679                 status = edp_detect(intel_dp);
5680         else if (intel_digital_port_connected(encoder))
5681                 status = intel_dp_detect_dpcd(intel_dp);
5682         else
5683                 status = connector_status_disconnected;
5684
5685         if (status == connector_status_disconnected) {
5686                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5687                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5688                 intel_dp->psr.sink_panel_replay_support = false;
5689
5690                 if (intel_dp->is_mst) {
5691                         drm_dbg_kms(&dev_priv->drm,
5692                                     "MST device may have disappeared %d vs %d\n",
5693                                     intel_dp->is_mst,
5694                                     intel_dp->mst_mgr.mst_state);
5695                         intel_dp->is_mst = false;
5696                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5697                                                         intel_dp->is_mst);
5698                 }
5699
5700                 intel_dp_tunnel_disconnect(intel_dp);
5701
5702                 goto out;
5703         }
5704
5705         ret = intel_dp_tunnel_detect(intel_dp, ctx);
5706         if (ret == -EDEADLK)
5707                 return ret;
5708
5709         if (ret == 1)
5710                 intel_connector->base.epoch_counter++;
5711
5712         if (!intel_dp_is_edp(intel_dp))
5713                 intel_psr_init_dpcd(intel_dp);
5714
5715         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5716
5717         intel_dp_configure_mst(intel_dp);
5718
5719         /*
5720          * TODO: Reset link params when switching to MST mode, until MST
5721          * supports link training fallback params.
5722          */
5723         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5724                 intel_dp_reset_max_link_params(intel_dp);
5725                 intel_dp->reset_link_params = false;
5726         }
5727
5728         intel_dp_print_rates(intel_dp);
5729
5730         if (intel_dp->is_mst) {
5731                 /*
5732                  * If we are in MST mode then this connector
5733                  * won't appear connected or have anything
5734                  * with EDID on it
5735                  */
5736                 status = connector_status_disconnected;
5737                 goto out;
5738         }
5739
5740         /*
5741          * Some external monitors do not signal loss of link synchronization
5742          * with an IRQ_HPD, so force a link status check.
5743          */
5744         if (!intel_dp_is_edp(intel_dp)) {
5745                 ret = intel_dp_retrain_link(encoder, ctx);
5746                 if (ret)
5747                         return ret;
5748         }
5749
5750         /*
5751          * Clearing NACK and defer counts to get their exact values
5752          * while reading EDID which are required by Compliance tests
5753          * 4.2.2.4 and 4.2.2.5
5754          */
5755         intel_dp->aux.i2c_nack_count = 0;
5756         intel_dp->aux.i2c_defer_count = 0;
5757
5758         intel_dp_set_edid(intel_dp);
5759         if (intel_dp_is_edp(intel_dp) ||
5760             to_intel_connector(connector)->detect_edid)
5761                 status = connector_status_connected;
5762
5763         intel_dp_check_device_service_irq(intel_dp);
5764
5765 out:
5766         if (status != connector_status_connected && !intel_dp->is_mst)
5767                 intel_dp_unset_edid(intel_dp);
5768
5769         if (!intel_dp_is_edp(intel_dp))
5770                 drm_dp_set_subconnector_property(connector,
5771                                                  status,
5772                                                  intel_dp->dpcd,
5773                                                  intel_dp->downstream_ports);
5774         return status;
5775 }
5776
5777 static void
5778 intel_dp_force(struct drm_connector *connector)
5779 {
5780         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5781         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5782         struct intel_encoder *intel_encoder = &dig_port->base;
5783         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5784
5785         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5786                     connector->base.id, connector->name);
5787
5788         if (!intel_display_driver_check_access(dev_priv))
5789                 return;
5790
5791         intel_dp_unset_edid(intel_dp);
5792
5793         if (connector->status != connector_status_connected)
5794                 return;
5795
5796         intel_dp_set_edid(intel_dp);
5797 }
5798
5799 static int intel_dp_get_modes(struct drm_connector *connector)
5800 {
5801         struct intel_connector *intel_connector = to_intel_connector(connector);
5802         int num_modes;
5803
5804         /* drm_edid_connector_update() done in ->detect() or ->force() */
5805         num_modes = drm_edid_connector_add_modes(connector);
5806
5807         /* Also add fixed mode, which may or may not be present in EDID */
5808         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5809                 num_modes += intel_panel_get_modes(intel_connector);
5810
5811         if (num_modes)
5812                 return num_modes;
5813
5814         if (!intel_connector->detect_edid) {
5815                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5816                 struct drm_display_mode *mode;
5817
5818                 mode = drm_dp_downstream_mode(connector->dev,
5819                                               intel_dp->dpcd,
5820                                               intel_dp->downstream_ports);
5821                 if (mode) {
5822                         drm_mode_probed_add(connector, mode);
5823                         num_modes++;
5824                 }
5825         }
5826
5827         return num_modes;
5828 }
5829
5830 static int
5831 intel_dp_connector_register(struct drm_connector *connector)
5832 {
5833         struct drm_i915_private *i915 = to_i915(connector->dev);
5834         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5835         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5836         struct intel_lspcon *lspcon = &dig_port->lspcon;
5837         int ret;
5838
5839         ret = intel_connector_register(connector);
5840         if (ret)
5841                 return ret;
5842
5843         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5844                     intel_dp->aux.name, connector->kdev->kobj.name);
5845
5846         intel_dp->aux.dev = connector->kdev;
5847         ret = drm_dp_aux_register(&intel_dp->aux);
5848         if (!ret)
5849                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5850
5851         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5852                 return ret;
5853
5854         /*
5855          * ToDo: Clean this up to handle lspcon init and resume more
5856          * efficiently and streamlined.
5857          */
5858         if (lspcon_init(dig_port)) {
5859                 lspcon_detect_hdr_capability(lspcon);
5860                 if (lspcon->hdr_supported)
5861                         drm_connector_attach_hdr_output_metadata_property(connector);
5862         }
5863
5864         return ret;
5865 }
5866
5867 static void
5868 intel_dp_connector_unregister(struct drm_connector *connector)
5869 {
5870         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5871
5872         drm_dp_cec_unregister_connector(&intel_dp->aux);
5873         drm_dp_aux_unregister(&intel_dp->aux);
5874         intel_connector_unregister(connector);
5875 }
5876
5877 void intel_dp_connector_sync_state(struct intel_connector *connector,
5878                                    const struct intel_crtc_state *crtc_state)
5879 {
5880         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5881
5882         if (crtc_state && crtc_state->dsc.compression_enable) {
5883                 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5884                 connector->dp.dsc_decompression_enabled = true;
5885         } else {
5886                 connector->dp.dsc_decompression_enabled = false;
5887         }
5888 }
5889
5890 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5891 {
5892         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5893         struct intel_dp *intel_dp = &dig_port->dp;
5894
5895         intel_dp_mst_encoder_cleanup(dig_port);
5896
5897         intel_dp_tunnel_destroy(intel_dp);
5898
5899         intel_pps_vdd_off_sync(intel_dp);
5900
5901         /*
5902          * Ensure power off delay is respected on module remove, so that we can
5903          * reduce delays at driver probe. See pps_init_timestamps().
5904          */
5905         intel_pps_wait_power_cycle(intel_dp);
5906
5907         intel_dp_aux_fini(intel_dp);
5908 }
5909
5910 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5911 {
5912         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5913
5914         intel_pps_vdd_off_sync(intel_dp);
5915
5916         intel_dp_tunnel_suspend(intel_dp);
5917 }
5918
5919 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5920 {
5921         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5922
5923         intel_pps_wait_power_cycle(intel_dp);
5924 }
5925
5926 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5927                                     int tile_group_id)
5928 {
5929         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5930         struct drm_connector_list_iter conn_iter;
5931         struct drm_connector *connector;
5932         int ret = 0;
5933
5934         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5935         drm_for_each_connector_iter(connector, &conn_iter) {
5936                 struct drm_connector_state *conn_state;
5937                 struct intel_crtc_state *crtc_state;
5938                 struct intel_crtc *crtc;
5939
5940                 if (!connector->has_tile ||
5941                     connector->tile_group->id != tile_group_id)
5942                         continue;
5943
5944                 conn_state = drm_atomic_get_connector_state(&state->base,
5945                                                             connector);
5946                 if (IS_ERR(conn_state)) {
5947                         ret = PTR_ERR(conn_state);
5948                         break;
5949                 }
5950
5951                 crtc = to_intel_crtc(conn_state->crtc);
5952
5953                 if (!crtc)
5954                         continue;
5955
5956                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5957                 crtc_state->uapi.mode_changed = true;
5958
5959                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5960                 if (ret)
5961                         break;
5962         }
5963         drm_connector_list_iter_end(&conn_iter);
5964
5965         return ret;
5966 }
5967
5968 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5969 {
5970         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5971         struct intel_crtc *crtc;
5972
5973         if (transcoders == 0)
5974                 return 0;
5975
5976         for_each_intel_crtc(&dev_priv->drm, crtc) {
5977                 struct intel_crtc_state *crtc_state;
5978                 int ret;
5979
5980                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5981                 if (IS_ERR(crtc_state))
5982                         return PTR_ERR(crtc_state);
5983
5984                 if (!crtc_state->hw.enable)
5985                         continue;
5986
5987                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5988                         continue;
5989
5990                 crtc_state->uapi.mode_changed = true;
5991
5992                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5993                 if (ret)
5994                         return ret;
5995
5996                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5997                 if (ret)
5998                         return ret;
5999
6000                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6001         }
6002
6003         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6004
6005         return 0;
6006 }
6007
6008 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6009                                       struct drm_connector *connector)
6010 {
6011         const struct drm_connector_state *old_conn_state =
6012                 drm_atomic_get_old_connector_state(&state->base, connector);
6013         const struct intel_crtc_state *old_crtc_state;
6014         struct intel_crtc *crtc;
6015         u8 transcoders;
6016
6017         crtc = to_intel_crtc(old_conn_state->crtc);
6018         if (!crtc)
6019                 return 0;
6020
6021         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6022
6023         if (!old_crtc_state->hw.active)
6024                 return 0;
6025
6026         transcoders = old_crtc_state->sync_mode_slaves_mask;
6027         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6028                 transcoders |= BIT(old_crtc_state->master_transcoder);
6029
6030         return intel_modeset_affected_transcoders(state,
6031                                                   transcoders);
6032 }
6033
6034 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6035                                            struct drm_atomic_state *_state)
6036 {
6037         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6038         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6039         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6040         struct intel_connector *intel_conn = to_intel_connector(conn);
6041         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6042         int ret;
6043
6044         ret = intel_digital_connector_atomic_check(conn, &state->base);
6045         if (ret)
6046                 return ret;
6047
6048         if (intel_dp_mst_source_support(intel_dp)) {
6049                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6050                 if (ret)
6051                         return ret;
6052         }
6053
6054         if (!intel_connector_needs_modeset(state, conn))
6055                 return 0;
6056
6057         ret = intel_dp_tunnel_atomic_check_state(state,
6058                                                  intel_dp,
6059                                                  intel_conn);
6060         if (ret)
6061                 return ret;
6062
6063         /*
6064          * We don't enable port sync on BDW due to missing w/as and
6065          * due to not having adjusted the modeset sequence appropriately.
6066          */
6067         if (DISPLAY_VER(dev_priv) < 9)
6068                 return 0;
6069
6070         if (conn->has_tile) {
6071                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6072                 if (ret)
6073                         return ret;
6074         }
6075
6076         return intel_modeset_synced_crtcs(state, conn);
6077 }
6078
6079 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6080                                        enum drm_connector_status hpd_state)
6081 {
6082         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6083         struct drm_i915_private *i915 = to_i915(connector->dev);
6084         bool hpd_high = hpd_state == connector_status_connected;
6085         unsigned int hpd_pin = encoder->hpd_pin;
6086         bool need_work = false;
6087
6088         spin_lock_irq(&i915->irq_lock);
6089         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6090                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6091
6092                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6093                 need_work = true;
6094         }
6095         spin_unlock_irq(&i915->irq_lock);
6096
6097         if (need_work)
6098                 intel_hpd_schedule_detection(i915);
6099 }
6100
6101 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6102         .force = intel_dp_force,
6103         .fill_modes = drm_helper_probe_single_connector_modes,
6104         .atomic_get_property = intel_digital_connector_atomic_get_property,
6105         .atomic_set_property = intel_digital_connector_atomic_set_property,
6106         .late_register = intel_dp_connector_register,
6107         .early_unregister = intel_dp_connector_unregister,
6108         .destroy = intel_connector_destroy,
6109         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6110         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6111         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6112 };
6113
6114 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6115         .detect_ctx = intel_dp_detect,
6116         .get_modes = intel_dp_get_modes,
6117         .mode_valid = intel_dp_mode_valid,
6118         .atomic_check = intel_dp_connector_atomic_check,
6119 };
6120
6121 enum irqreturn
6122 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6123 {
6124         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6125         struct intel_dp *intel_dp = &dig_port->dp;
6126         u8 dpcd[DP_RECEIVER_CAP_SIZE];
6127
6128         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6129             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6130                 /*
6131                  * vdd off can generate a long/short pulse on eDP which
6132                  * would require vdd on to handle it, and thus we
6133                  * would end up in an endless cycle of
6134                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6135                  */
6136                 drm_dbg_kms(&i915->drm,
6137                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6138                             long_hpd ? "long" : "short",
6139                             dig_port->base.base.base.id,
6140                             dig_port->base.base.name);
6141                 return IRQ_HANDLED;
6142         }
6143
6144         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6145                     dig_port->base.base.base.id,
6146                     dig_port->base.base.name,
6147                     long_hpd ? "long" : "short");
6148
6149         /*
6150          * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6151          * response to long HPD pulses. The DP hotplug handler does that,
6152          * however the hotplug handler may be blocked by another
6153          * connector's/encoder's hotplug handler. Since the TBT CM may not
6154          * complete the DP tunnel BW request for the latter connector/encoder
6155          * waiting for this encoder's DPRX read, perform a dummy read here.
6156          */
6157         if (long_hpd)
6158                 intel_dp_read_dprx_caps(intel_dp, dpcd);
6159
6160         if (long_hpd) {
6161                 intel_dp->reset_link_params = true;
6162                 return IRQ_NONE;
6163         }
6164
6165         if (intel_dp->is_mst) {
6166                 if (!intel_dp_check_mst_status(intel_dp))
6167                         return IRQ_NONE;
6168         } else if (!intel_dp_short_pulse(intel_dp)) {
6169                 return IRQ_NONE;
6170         }
6171
6172         return IRQ_HANDLED;
6173 }
6174
6175 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6176                                   const struct intel_bios_encoder_data *devdata,
6177                                   enum port port)
6178 {
6179         /*
6180          * eDP not supported on g4x. so bail out early just
6181          * for a bit extra safety in case the VBT is bonkers.
6182          */
6183         if (DISPLAY_VER(dev_priv) < 5)
6184                 return false;
6185
6186         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6187                 return true;
6188
6189         return devdata && intel_bios_encoder_supports_edp(devdata);
6190 }
6191
6192 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6193 {
6194         const struct intel_bios_encoder_data *devdata =
6195                 intel_bios_encoder_data_lookup(i915, port);
6196
6197         return _intel_dp_is_port_edp(i915, devdata, port);
6198 }
6199
6200 static bool
6201 has_gamut_metadata_dip(struct intel_encoder *encoder)
6202 {
6203         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6204         enum port port = encoder->port;
6205
6206         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6207                 return false;
6208
6209         if (DISPLAY_VER(i915) >= 11)
6210                 return true;
6211
6212         if (port == PORT_A)
6213                 return false;
6214
6215         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6216             DISPLAY_VER(i915) >= 9)
6217                 return true;
6218
6219         return false;
6220 }
6221
6222 static void
6223 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6224 {
6225         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6226         enum port port = dp_to_dig_port(intel_dp)->base.port;
6227
6228         if (!intel_dp_is_edp(intel_dp))
6229                 drm_connector_attach_dp_subconnector_property(connector);
6230
6231         if (!IS_G4X(dev_priv) && port != PORT_A)
6232                 intel_attach_force_audio_property(connector);
6233
6234         intel_attach_broadcast_rgb_property(connector);
6235         if (HAS_GMCH(dev_priv))
6236                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6237         else if (DISPLAY_VER(dev_priv) >= 5)
6238                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6239
6240         /* Register HDMI colorspace for case of lspcon */
6241         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6242                 drm_connector_attach_content_type_property(connector);
6243                 intel_attach_hdmi_colorspace_property(connector);
6244         } else {
6245                 intel_attach_dp_colorspace_property(connector);
6246         }
6247
6248         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6249                 drm_connector_attach_hdr_output_metadata_property(connector);
6250
6251         if (HAS_VRR(dev_priv))
6252                 drm_connector_attach_vrr_capable_property(connector);
6253 }
6254
6255 static void
6256 intel_edp_add_properties(struct intel_dp *intel_dp)
6257 {
6258         struct intel_connector *connector = intel_dp->attached_connector;
6259         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6260         const struct drm_display_mode *fixed_mode =
6261                 intel_panel_preferred_fixed_mode(connector);
6262
6263         intel_attach_scaling_mode_property(&connector->base);
6264
6265         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6266                                                        i915->display.vbt.orientation,
6267                                                        fixed_mode->hdisplay,
6268                                                        fixed_mode->vdisplay);
6269 }
6270
6271 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6272                                       struct intel_connector *connector)
6273 {
6274         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6275         enum pipe pipe = INVALID_PIPE;
6276
6277         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6278                 /*
6279                  * Figure out the current pipe for the initial backlight setup.
6280                  * If the current pipe isn't valid, try the PPS pipe, and if that
6281                  * fails just assume pipe A.
6282                  */
6283                 pipe = vlv_active_pipe(intel_dp);
6284
6285                 if (pipe != PIPE_A && pipe != PIPE_B)
6286                         pipe = intel_dp->pps.pps_pipe;
6287
6288                 if (pipe != PIPE_A && pipe != PIPE_B)
6289                         pipe = PIPE_A;
6290         }
6291
6292         intel_backlight_setup(connector, pipe);
6293 }
6294
6295 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6296                                      struct intel_connector *intel_connector)
6297 {
6298         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6299         struct drm_connector *connector = &intel_connector->base;
6300         struct drm_display_mode *fixed_mode;
6301         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6302         bool has_dpcd;
6303         const struct drm_edid *drm_edid;
6304
6305         if (!intel_dp_is_edp(intel_dp))
6306                 return true;
6307
6308         /*
6309          * On IBX/CPT we may get here with LVDS already registered. Since the
6310          * driver uses the only internal power sequencer available for both
6311          * eDP and LVDS bail out early in this case to prevent interfering
6312          * with an already powered-on LVDS power sequencer.
6313          */
6314         if (intel_get_lvds_encoder(dev_priv)) {
6315                 drm_WARN_ON(&dev_priv->drm,
6316                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6317                 drm_info(&dev_priv->drm,
6318                          "LVDS was detected, not registering eDP\n");
6319
6320                 return false;
6321         }
6322
6323         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6324                                     encoder->devdata);
6325
6326         if (!intel_pps_init(intel_dp)) {
6327                 drm_info(&dev_priv->drm,
6328                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6329                          encoder->base.base.id, encoder->base.name);
6330                 /*
6331                  * The BIOS may have still enabled VDD on the PPS even
6332                  * though it's unusable. Make sure we turn it back off
6333                  * and to release the power domain references/etc.
6334                  */
6335                 goto out_vdd_off;
6336         }
6337
6338         /*
6339          * Enable HPD sense for live status check.
6340          * intel_hpd_irq_setup() will turn it off again
6341          * if it's no longer needed later.
6342          *
6343          * The DPCD probe below will make sure VDD is on.
6344          */
6345         intel_hpd_enable_detection(encoder);
6346
6347         /* Cache DPCD and EDID for edp. */
6348         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6349
6350         if (!has_dpcd) {
6351                 /* if this fails, presume the device is a ghost */
6352                 drm_info(&dev_priv->drm,
6353                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6354                          encoder->base.base.id, encoder->base.name);
6355                 goto out_vdd_off;
6356         }
6357
6358         /*
6359          * VBT and straps are liars. Also check HPD as that seems
6360          * to be the most reliable piece of information available.
6361          *
6362          * ... expect on devices that forgot to hook HPD up for eDP
6363          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6364          * ports are attempting to use the same AUX CH, according to VBT.
6365          */
6366         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6367                 /*
6368                  * If this fails, presume the DPCD answer came
6369                  * from some other port using the same AUX CH.
6370                  *
6371                  * FIXME maybe cleaner to check this before the
6372                  * DPCD read? Would need sort out the VDD handling...
6373                  */
6374                 if (!intel_digital_port_connected(encoder)) {
6375                         drm_info(&dev_priv->drm,
6376                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6377                                  encoder->base.base.id, encoder->base.name);
6378                         goto out_vdd_off;
6379                 }
6380
6381                 /*
6382                  * Unfortunately even the HPD based detection fails on
6383                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6384                  * back to checking for a VGA branch device. Only do this
6385                  * on known affected platforms to minimize false positives.
6386                  */
6387                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6388                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6389                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6390                         drm_info(&dev_priv->drm,
6391                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6392                                  encoder->base.base.id, encoder->base.name);
6393                         goto out_vdd_off;
6394                 }
6395         }
6396
6397         mutex_lock(&dev_priv->drm.mode_config.mutex);
6398         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6399         if (!drm_edid) {
6400                 /* Fallback to EDID from ACPI OpRegion, if any */
6401                 drm_edid = intel_opregion_get_edid(intel_connector);
6402                 if (drm_edid)
6403                         drm_dbg_kms(&dev_priv->drm,
6404                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6405                                     connector->base.id, connector->name);
6406         }
6407         if (drm_edid) {
6408                 if (drm_edid_connector_update(connector, drm_edid) ||
6409                     !drm_edid_connector_add_modes(connector)) {
6410                         drm_edid_connector_update(connector, NULL);
6411                         drm_edid_free(drm_edid);
6412                         drm_edid = ERR_PTR(-EINVAL);
6413                 }
6414         } else {
6415                 drm_edid = ERR_PTR(-ENOENT);
6416         }
6417
6418         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6419                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6420
6421         intel_panel_add_edid_fixed_modes(intel_connector, true);
6422
6423         /* MSO requires information from the EDID */
6424         intel_edp_mso_init(intel_dp);
6425
6426         /* multiply the mode clock and horizontal timings for MSO */
6427         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6428                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6429
6430         /* fallback to VBT if available for eDP */
6431         if (!intel_panel_preferred_fixed_mode(intel_connector))
6432                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6433
6434         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6435
6436         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6437                 drm_info(&dev_priv->drm,
6438                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6439                          encoder->base.base.id, encoder->base.name);
6440                 goto out_vdd_off;
6441         }
6442
6443         intel_panel_init(intel_connector, drm_edid);
6444
6445         intel_edp_backlight_setup(intel_dp, intel_connector);
6446
6447         intel_edp_add_properties(intel_dp);
6448
6449         intel_pps_init_late(intel_dp);
6450
6451         return true;
6452
6453 out_vdd_off:
6454         intel_pps_vdd_off_sync(intel_dp);
6455
6456         return false;
6457 }
6458
6459 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6460 {
6461         struct intel_connector *intel_connector;
6462         struct drm_connector *connector;
6463
6464         intel_connector = container_of(work, typeof(*intel_connector),
6465                                        modeset_retry_work);
6466         connector = &intel_connector->base;
6467         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6468                     connector->name);
6469
6470         /* Grab the locks before changing connector property*/
6471         mutex_lock(&connector->dev->mode_config.mutex);
6472         /* Set connector link status to BAD and send a Uevent to notify
6473          * userspace to do a modeset.
6474          */
6475         drm_connector_set_link_status_property(connector,
6476                                                DRM_MODE_LINK_STATUS_BAD);
6477         mutex_unlock(&connector->dev->mode_config.mutex);
6478         /* Send Hotplug uevent so userspace can reprobe */
6479         drm_kms_helper_connector_hotplug_event(connector);
6480
6481         drm_connector_put(connector);
6482 }
6483
6484 void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6485 {
6486         INIT_WORK(&connector->modeset_retry_work,
6487                   intel_dp_modeset_retry_work_fn);
6488 }
6489
6490 bool
6491 intel_dp_init_connector(struct intel_digital_port *dig_port,
6492                         struct intel_connector *intel_connector)
6493 {
6494         struct drm_connector *connector = &intel_connector->base;
6495         struct intel_dp *intel_dp = &dig_port->dp;
6496         struct intel_encoder *intel_encoder = &dig_port->base;
6497         struct drm_device *dev = intel_encoder->base.dev;
6498         struct drm_i915_private *dev_priv = to_i915(dev);
6499         enum port port = intel_encoder->port;
6500         enum phy phy = intel_port_to_phy(dev_priv, port);
6501         int type;
6502
6503         /* Initialize the work for modeset in case of link train failure */
6504         intel_dp_init_modeset_retry_work(intel_connector);
6505
6506         if (drm_WARN(dev, dig_port->max_lanes < 1,
6507                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6508                      dig_port->max_lanes, intel_encoder->base.base.id,
6509                      intel_encoder->base.name))
6510                 return false;
6511
6512         intel_dp->reset_link_params = true;
6513         intel_dp->pps.pps_pipe = INVALID_PIPE;
6514         intel_dp->pps.active_pipe = INVALID_PIPE;
6515
6516         /* Preserve the current hw state. */
6517         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6518         intel_dp->attached_connector = intel_connector;
6519
6520         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6521                 /*
6522                  * Currently we don't support eDP on TypeC ports, although in
6523                  * theory it could work on TypeC legacy ports.
6524                  */
6525                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6526                 type = DRM_MODE_CONNECTOR_eDP;
6527                 intel_encoder->type = INTEL_OUTPUT_EDP;
6528
6529                 /* eDP only on port B and/or C on vlv/chv */
6530                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6531                                       IS_CHERRYVIEW(dev_priv)) &&
6532                                 port != PORT_B && port != PORT_C))
6533                         return false;
6534         } else {
6535                 type = DRM_MODE_CONNECTOR_DisplayPort;
6536         }
6537
6538         intel_dp_set_default_sink_rates(intel_dp);
6539         intel_dp_set_default_max_sink_lane_count(intel_dp);
6540
6541         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6542                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6543
6544         intel_dp_aux_init(intel_dp);
6545         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6546
6547         drm_dbg_kms(&dev_priv->drm,
6548                     "Adding %s connector on [ENCODER:%d:%s]\n",
6549                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6550                     intel_encoder->base.base.id, intel_encoder->base.name);
6551
6552         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6553                                     type, &intel_dp->aux.ddc);
6554         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6555
6556         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6557                 connector->interlace_allowed = true;
6558
6559         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6560         intel_connector->base.polled = intel_connector->polled;
6561
6562         intel_connector_attach_encoder(intel_connector, intel_encoder);
6563
6564         if (HAS_DDI(dev_priv))
6565                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6566         else
6567                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6568
6569         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6570                 intel_dp_aux_fini(intel_dp);
6571                 goto fail;
6572         }
6573
6574         intel_dp_set_source_rates(intel_dp);
6575         intel_dp_set_common_rates(intel_dp);
6576         intel_dp_reset_max_link_params(intel_dp);
6577
6578         /* init MST on ports that can support it */
6579         intel_dp_mst_encoder_init(dig_port,
6580                                   intel_connector->base.base.id);
6581
6582         intel_dp_add_properties(intel_dp, connector);
6583
6584         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6585                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6586                 if (ret)
6587                         drm_dbg_kms(&dev_priv->drm,
6588                                     "HDCP init failed, skipping.\n");
6589         }
6590
6591         intel_dp->colorimetry_support =
6592                 intel_dp_get_colorimetry_status(intel_dp);
6593
6594         intel_dp->frl.is_trained = false;
6595         intel_dp->frl.trained_rate_gbps = 0;
6596
6597         intel_psr_init(intel_dp);
6598
6599         return true;
6600
6601 fail:
6602         intel_display_power_flush_work(dev_priv);
6603         drm_connector_cleanup(connector);
6604
6605         return false;
6606 }
6607
6608 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6609 {
6610         struct intel_encoder *encoder;
6611
6612         if (!HAS_DISPLAY(dev_priv))
6613                 return;
6614
6615         for_each_intel_encoder(&dev_priv->drm, encoder) {
6616                 struct intel_dp *intel_dp;
6617
6618                 if (encoder->type != INTEL_OUTPUT_DDI)
6619                         continue;
6620
6621                 intel_dp = enc_to_intel_dp(encoder);
6622
6623                 if (!intel_dp_mst_source_support(intel_dp))
6624                         continue;
6625
6626                 if (intel_dp->is_mst)
6627                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6628         }
6629 }
6630
6631 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6632 {
6633         struct intel_encoder *encoder;
6634
6635         if (!HAS_DISPLAY(dev_priv))
6636                 return;
6637
6638         for_each_intel_encoder(&dev_priv->drm, encoder) {
6639                 struct intel_dp *intel_dp;
6640                 int ret;
6641
6642                 if (encoder->type != INTEL_OUTPUT_DDI)
6643                         continue;
6644
6645                 intel_dp = enc_to_intel_dp(encoder);
6646
6647                 if (!intel_dp_mst_source_support(intel_dp))
6648                         continue;
6649
6650                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6651                                                      true);
6652                 if (ret) {
6653                         intel_dp->is_mst = false;
6654                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6655                                                         false);
6656                 }
6657         }
6658 }