drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "g4x_dp.h"
  43 #include "i915_debugfs.h"
  44 #include "i915_drv.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_aux.h"
  52 #include "intel_dp_link_training.h"
  53 #include "intel_dp_mst.h"
  54 #include "intel_dpll.h"
  55 #include "intel_dpio_phy.h"
  56 #include "intel_fifo_underrun.h"
  57 #include "intel_hdcp.h"
  58 #include "intel_hdmi.h"
  59 #include "intel_hotplug.h"
  60 #include "intel_lspcon.h"
  61 #include "intel_lvds.h"
  62 #include "intel_panel.h"
  63 #include "intel_pps.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68 #include "intel_vrr.h"
  69
  70 #define DP_DPRX_ESI_LEN 14
  71
  72 /* DP DSC throughput values used for slice count calculations KPixels/s */
  73 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  75 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  76
  77 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  78 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  79
  80 /* Compliance test status bits  */
  81 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  82 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85
  86
  87 /* Constants for DP DSC configurations */
  88 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  89
  90 /* With Single pipe configuration, HW is capable of supporting maximum
  91  * of 4 slices per line.
  92  */
  93 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
  94
  95 /**
  96  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  97  * @intel_dp: DP struct
  98  *
  99  * If a CPU or PCH DP output is attached to an eDP panel, this function
 100  * will return true, and false otherwise.
 101  */
 102 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 103 {
 104         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 105
 106         return dig_port->base.type == INTEL_OUTPUT_EDP;
 107 }
 108
 109 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 110
 111 /* update sink rates from dpcd */
 112 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 113 {
 114         static const int dp_rates[] = {
 115                 162000, 270000, 540000, 810000
 116         };
 117         int i, max_rate;
 118         int max_lttpr_rate;
 119
 120         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 121                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 122                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 123
 124                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 125                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 126
 127                 return;
 128         }
 129
 130         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 131         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 132         if (max_lttpr_rate)
 133                 max_rate = min(max_rate, max_lttpr_rate);
 134
 135         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 136                 if (dp_rates[i] > max_rate)
 137                         break;
 138                 intel_dp->sink_rates[i] = dp_rates[i];
 139         }
 140
 141         intel_dp->num_sink_rates = i;
 142 }
 143
 144 /* Get length of rates array potentially limited by max_rate. */
 145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 146 {
 147         int i;
 148
 149         /* Limit results by potentially reduced max rate */
 150         for (i = 0; i < len; i++) {
 151                 if (rates[len - i - 1] <= max_rate)
 152                         return len - i;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /* Get length of common rates array potentially limited by max_rate. */
 159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 160                                           int max_rate)
 161 {
 162         return intel_dp_rate_limit_len(intel_dp->common_rates,
 163                                        intel_dp->num_common_rates, max_rate);
 164 }
 165
 166 /* Theoretical max between source and sink */
 167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 168 {
 169         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 170 }
 171
 172 /* Theoretical max between source and sink */
 173 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 174 {
 175         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 176         int source_max = dig_port->max_lanes;
 177         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 178         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 179         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 180
 181         if (lttpr_max)
 182                 sink_max = min(sink_max, lttpr_max);
 183
 184         return min3(source_max, sink_max, fia_max);
 185 }
 186
 187 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 188 {
 189         return intel_dp->max_link_lane_count;
 190 }
 191
 192 int
 193 intel_dp_link_required(int pixel_clock, int bpp)
 194 {
 195         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 196         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 197 }
 198
 199 int
 200 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 201 {
 202         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 203          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 204          * is transmitted every LS_Clk per lane, there is no need to account for
 205          * the channel encoding that is done in the PHY layer here.
 206          */
 207
 208         return max_link_clock * max_lanes;
 209 }
 210
 211 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 212 {
 213         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 214         struct intel_encoder *encoder = &intel_dig_port->base;
 215         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 216
 217         return DISPLAY_VER(dev_priv) >= 12 ||
 218                 (IS_DISPLAY_VER(dev_priv, 11) &&
 219                  encoder->port != PORT_A);
 220 }
 221
 222 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 223 {
 224         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 225         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 226         enum port port = dig_port->base.port;
 227
 228         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 229
 230         /* Low voltage SKUs are limited to max of 5.4G */
 231         if (voltage == VOLTAGE_INFO_0_85V)
 232                 return 540000;
 233
 234         /* For this SKU 8.1G is supported in all ports */
 235         if (IS_CNL_WITH_PORT_F(dev_priv))
 236                 return 810000;
 237
 238         /* For other SKUs, max rate on ports A and D is 5.4G */
 239         if (port == PORT_A || port == PORT_D)
 240                 return 540000;
 241
 242         return 810000;
 243 }
 244
 245 static int icl_max_source_rate(struct intel_dp *intel_dp)
 246 {
 247         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 248         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 249         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 250
 251         if (intel_phy_is_combo(dev_priv, phy) &&
 252             !intel_dp_is_edp(intel_dp))
 253                 return 540000;
 254
 255         return 810000;
 256 }
 257
 258 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 259 {
 260         if (intel_dp_is_edp(intel_dp))
 261                 return 540000;
 262
 263         return 810000;
 264 }
 265
 266 static void
 267 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 268 {
 269         /* The values must be in increasing order */
 270         static const int cnl_rates[] = {
 271                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 272         };
 273         static const int bxt_rates[] = {
 274                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 275         };
 276         static const int skl_rates[] = {
 277                 162000, 216000, 270000, 324000, 432000, 540000
 278         };
 279         static const int hsw_rates[] = {
 280                 162000, 270000, 540000
 281         };
 282         static const int g4x_rates[] = {
 283                 162000, 270000
 284         };
 285         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 286         struct intel_encoder *encoder = &dig_port->base;
 287         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 288         const int *source_rates;
 289         int size, max_rate = 0, vbt_max_rate;
 290
 291         /* This should only be done once */
 292         drm_WARN_ON(&dev_priv->drm,
 293                     intel_dp->source_rates || intel_dp->num_source_rates);
 294
 295         if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
 296                 source_rates = cnl_rates;
 297                 size = ARRAY_SIZE(cnl_rates);
 298                 if (IS_DISPLAY_VER(dev_priv, 10))
 299                         max_rate = cnl_max_source_rate(intel_dp);
 300                 else if (IS_JSL_EHL(dev_priv))
 301                         max_rate = ehl_max_source_rate(intel_dp);
 302                 else
 303                         max_rate = icl_max_source_rate(intel_dp);
 304         } else if (IS_GEN9_LP(dev_priv)) {
 305                 source_rates = bxt_rates;
 306                 size = ARRAY_SIZE(bxt_rates);
 307         } else if (IS_GEN9_BC(dev_priv)) {
 308                 source_rates = skl_rates;
 309                 size = ARRAY_SIZE(skl_rates);
 310         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 311                    IS_BROADWELL(dev_priv)) {
 312                 source_rates = hsw_rates;
 313                 size = ARRAY_SIZE(hsw_rates);
 314         } else {
 315                 source_rates = g4x_rates;
 316                 size = ARRAY_SIZE(g4x_rates);
 317         }
 318
 319         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 320         if (max_rate && vbt_max_rate)
 321                 max_rate = min(max_rate, vbt_max_rate);
 322         else if (vbt_max_rate)
 323                 max_rate = vbt_max_rate;
 324
 325         if (max_rate)
 326                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 327
 328         intel_dp->source_rates = source_rates;
 329         intel_dp->num_source_rates = size;
 330 }
 331
 332 static int intersect_rates(const int *source_rates, int source_len,
 333                            const int *sink_rates, int sink_len,
 334                            int *common_rates)
 335 {
 336         int i = 0, j = 0, k = 0;
 337
 338         while (i < source_len && j < sink_len) {
 339                 if (source_rates[i] == sink_rates[j]) {
 340                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 341                                 return k;
 342                         common_rates[k] = source_rates[i];
 343                         ++k;
 344                         ++i;
 345                         ++j;
 346                 } else if (source_rates[i] < sink_rates[j]) {
 347                         ++i;
 348                 } else {
 349                         ++j;
 350                 }
 351         }
 352         return k;
 353 }
 354
 355 /* return index of rate in rates array, or -1 if not found */
 356 static int intel_dp_rate_index(const int *rates, int len, int rate)
 357 {
 358         int i;
 359
 360         for (i = 0; i < len; i++)
 361                 if (rate == rates[i])
 362                         return i;
 363
 364         return -1;
 365 }
 366
 367 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 368 {
 369         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 370
 371         drm_WARN_ON(&i915->drm,
 372                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 373
 374         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 375                                                      intel_dp->num_source_rates,
 376                                                      intel_dp->sink_rates,
 377                                                      intel_dp->num_sink_rates,
 378                                                      intel_dp->common_rates);
 379
 380         /* Paranoia, there should always be something in common. */
 381         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 382                 intel_dp->common_rates[0] = 162000;
 383                 intel_dp->num_common_rates = 1;
 384         }
 385 }
 386
 387 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 388                                        u8 lane_count)
 389 {
 390         /*
 391          * FIXME: we need to synchronize the current link parameters with
 392          * hardware readout. Currently fast link training doesn't work on
 393          * boot-up.
 394          */
 395         if (link_rate == 0 ||
 396             link_rate > intel_dp->max_link_rate)
 397                 return false;
 398
 399         if (lane_count == 0 ||
 400             lane_count > intel_dp_max_lane_count(intel_dp))
 401                 return false;
 402
 403         return true;
 404 }
 405
 406 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 407                                                      int link_rate,
 408                                                      u8 lane_count)
 409 {
 410         const struct drm_display_mode *fixed_mode =
 411                 intel_dp->attached_connector->panel.fixed_mode;
 412         int mode_rate, max_rate;
 413
 414         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 415         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 416         if (mode_rate > max_rate)
 417                 return false;
 418
 419         return true;
 420 }
 421
 422 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 423                                             int link_rate, u8 lane_count)
 424 {
 425         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 426         int index;
 427
 428         /*
 429          * TODO: Enable fallback on MST links once MST link compute can handle
 430          * the fallback params.
 431          */
 432         if (intel_dp->is_mst) {
 433                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 434                 return -1;
 435         }
 436
 437         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 438                 drm_dbg_kms(&i915->drm,
 439                             "Retrying Link training for eDP with max parameters\n");
 440                 intel_dp->use_max_params = true;
 441                 return 0;
 442         }
 443
 444         index = intel_dp_rate_index(intel_dp->common_rates,
 445                                     intel_dp->num_common_rates,
 446                                     link_rate);
 447         if (index > 0) {
 448                 if (intel_dp_is_edp(intel_dp) &&
 449                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 450                                                               intel_dp->common_rates[index - 1],
 451                                                               lane_count)) {
 452                         drm_dbg_kms(&i915->drm,
 453                                     "Retrying Link training for eDP with same parameters\n");
 454                         return 0;
 455                 }
 456                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 457                 intel_dp->max_link_lane_count = lane_count;
 458         } else if (lane_count > 1) {
 459                 if (intel_dp_is_edp(intel_dp) &&
 460                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 461                                                               intel_dp_max_common_rate(intel_dp),
 462                                                               lane_count >> 1)) {
 463                         drm_dbg_kms(&i915->drm,
 464                                     "Retrying Link training for eDP with same parameters\n");
 465                         return 0;
 466                 }
 467                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 468                 intel_dp->max_link_lane_count = lane_count >> 1;
 469         } else {
 470                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 471                 return -1;
 472         }
 473
 474         return 0;
 475 }
 476
 477 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 478 {
 479         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 480                        DP_DSC_FEC_OVERHEAD_FACTOR);
 481 }
 482
 483 static int
 484 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 485 {
 486         if (DISPLAY_VER(i915) >= 11)
 487                 return 7680 * 8;
 488         else
 489                 return 6144 * 8;
 490 }
 491
 492 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 493                                        u32 link_clock, u32 lane_count,
 494                                        u32 mode_clock, u32 mode_hdisplay,
 495                                        bool bigjoiner)
 496 {
 497         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 498         int i;
 499
 500         /*
 501          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 502          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 503          * for SST -> TimeSlotsPerMTP is 1,
 504          * for MST -> TimeSlotsPerMTP has to be calculated
 505          */
 506         bits_per_pixel = (link_clock * lane_count * 8) /
 507                          intel_dp_mode_to_fec_clock(mode_clock);
 508         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 509
 510         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 511         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 512                 mode_hdisplay;
 513
 514         if (bigjoiner)
 515                 max_bpp_small_joiner_ram *= 2;
 516
 517         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 518                     max_bpp_small_joiner_ram);
 519
 520         /*
 521          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 522          * check, output bpp from small joiner RAM check)
 523          */
 524         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 525
 526         if (bigjoiner) {
 527                 u32 max_bpp_bigjoiner =
 528                         i915->max_cdclk_freq * 48 /
 529                         intel_dp_mode_to_fec_clock(mode_clock);
 530
 531                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 532                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 533         }
 534
 535         /* Error out if the max bpp is less than smallest allowed valid bpp */
 536         if (bits_per_pixel < valid_dsc_bpp[0]) {
 537                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 538                             bits_per_pixel, valid_dsc_bpp[0]);
 539                 return 0;
 540         }
 541
 542         /* Find the nearest match in the array of known BPPs from VESA */
 543         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 544                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 545                         break;
 546         }
 547         bits_per_pixel = valid_dsc_bpp[i];
 548
 549         /*
 550          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 551          * fractional part is 0
 552          */
 553         return bits_per_pixel << 4;
 554 }
 555
 556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 557                                        int mode_clock, int mode_hdisplay,
 558                                        bool bigjoiner)
 559 {
 560         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 561         u8 min_slice_count, i;
 562         int max_slice_width;
 563
 564         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 565                 min_slice_count = DIV_ROUND_UP(mode_clock,
 566                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 567         else
 568                 min_slice_count = DIV_ROUND_UP(mode_clock,
 569                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 570
 571         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 572         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 573                 drm_dbg_kms(&i915->drm,
 574                             "Unsupported slice width %d by DP DSC Sink device\n",
 575                             max_slice_width);
 576                 return 0;
 577         }
 578         /* Also take into account max slice width */
 579         min_slice_count = max_t(u8, min_slice_count,
 580                                 DIV_ROUND_UP(mode_hdisplay,
 581                                              max_slice_width));
 582
 583         /* Find the closest match to the valid slice count values */
 584         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 585                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 586
 587                 if (test_slice_count >
 588                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 589                         break;
 590
 591                 /* big joiner needs small joiner to be enabled */
 592                 if (bigjoiner && test_slice_count < 4)
 593                         continue;
 594
 595                 if (min_slice_count <= test_slice_count)
 596                         return test_slice_count;
 597         }
 598
 599         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 600                     min_slice_count);
 601         return 0;
 602 }
 603
 604 static enum intel_output_format
 605 intel_dp_output_format(struct drm_connector *connector,
 606                        const struct drm_display_mode *mode)
 607 {
 608         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 609         const struct drm_display_info *info = &connector->display_info;
 610
 611         if (!connector->ycbcr_420_allowed ||
 612             !drm_mode_is_420_only(info, mode))
 613                 return INTEL_OUTPUT_FORMAT_RGB;
 614
 615         if (intel_dp->dfp.rgb_to_ycbcr &&
 616             intel_dp->dfp.ycbcr_444_to_420)
 617                 return INTEL_OUTPUT_FORMAT_RGB;
 618
 619         if (intel_dp->dfp.ycbcr_444_to_420)
 620                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 621         else
 622                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 623 }
 624
 625 int intel_dp_min_bpp(enum intel_output_format output_format)
 626 {
 627         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 628                 return 6 * 3;
 629         else
 630                 return 8 * 3;
 631 }
 632
 633 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 634 {
 635         /*
 636          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 637          * format of the number of bytes per pixel will be half the number
 638          * of bytes of RGB pixel.
 639          */
 640         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 641                 bpp /= 2;
 642
 643         return bpp;
 644 }
 645
 646 static int
 647 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 648                              const struct drm_display_mode *mode)
 649 {
 650         enum intel_output_format output_format =
 651                 intel_dp_output_format(connector, mode);
 652
 653         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 654 }
 655
 656 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 657                                   int hdisplay)
 658 {
 659         /*
 660          * Older platforms don't like hdisplay==4096 with DP.
 661          *
 662          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 663          * and frame counter increment), but we don't get vblank interrupts,
 664          * and the pipe underruns immediately. The link also doesn't seem
 665          * to get trained properly.
 666          *
 667          * On CHV the vblank interrupts don't seem to disappear but
 668          * otherwise the symptoms are similar.
 669          *
 670          * TODO: confirm the behaviour on HSW+
 671          */
 672         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 673 }
 674
 675 static enum drm_mode_status
 676 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 677                                const struct drm_display_mode *mode,
 678                                int target_clock)
 679 {
 680         struct intel_dp *intel_dp = intel_attached_dp(connector);
 681         const struct drm_display_info *info = &connector->base.display_info;
 682         int tmds_clock;
 683
 684         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 685         if (intel_dp->dfp.pcon_max_frl_bw) {
 686                 int target_bw;
 687                 int max_frl_bw;
 688                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 689
 690                 target_bw = bpp * target_clock;
 691
 692                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 693
 694                 /* converting bw from Gbps to Kbps*/
 695                 max_frl_bw = max_frl_bw * 1000000;
 696
 697                 if (target_bw > max_frl_bw)
 698                         return MODE_CLOCK_HIGH;
 699
 700                 return MODE_OK;
 701         }
 702
 703         if (intel_dp->dfp.max_dotclock &&
 704             target_clock > intel_dp->dfp.max_dotclock)
 705                 return MODE_CLOCK_HIGH;
 706
 707         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 708         tmds_clock = target_clock;
 709         if (drm_mode_is_420_only(info, mode))
 710                 tmds_clock /= 2;
 711
 712         if (intel_dp->dfp.min_tmds_clock &&
 713             tmds_clock < intel_dp->dfp.min_tmds_clock)
 714                 return MODE_CLOCK_LOW;
 715         if (intel_dp->dfp.max_tmds_clock &&
 716             tmds_clock > intel_dp->dfp.max_tmds_clock)
 717                 return MODE_CLOCK_HIGH;
 718
 719         return MODE_OK;
 720 }
 721
 722 static enum drm_mode_status
 723 intel_dp_mode_valid(struct drm_connector *connector,
 724                     struct drm_display_mode *mode)
 725 {
 726         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 727         struct intel_connector *intel_connector = to_intel_connector(connector);
 728         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 729         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 730         int target_clock = mode->clock;
 731         int max_rate, mode_rate, max_lanes, max_link_clock;
 732         int max_dotclk = dev_priv->max_dotclk_freq;
 733         u16 dsc_max_output_bpp = 0;
 734         u8 dsc_slice_count = 0;
 735         enum drm_mode_status status;
 736         bool dsc = false, bigjoiner = false;
 737
 738         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 739                 return MODE_NO_DBLESCAN;
 740
 741         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 742                 return MODE_H_ILLEGAL;
 743
 744         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 745                 if (mode->hdisplay != fixed_mode->hdisplay)
 746                         return MODE_PANEL;
 747
 748                 if (mode->vdisplay != fixed_mode->vdisplay)
 749                         return MODE_PANEL;
 750
 751                 target_clock = fixed_mode->clock;
 752         }
 753
 754         if (mode->clock < 10000)
 755                 return MODE_CLOCK_LOW;
 756
 757         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 758             intel_dp_can_bigjoiner(intel_dp)) {
 759                 bigjoiner = true;
 760                 max_dotclk *= 2;
 761         }
 762         if (target_clock > max_dotclk)
 763                 return MODE_CLOCK_HIGH;
 764
 765         max_link_clock = intel_dp_max_link_rate(intel_dp);
 766         max_lanes = intel_dp_max_lane_count(intel_dp);
 767
 768         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 769         mode_rate = intel_dp_link_required(target_clock,
 770                                            intel_dp_mode_min_output_bpp(connector, mode));
 771
 772         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 773                 return MODE_H_ILLEGAL;
 774
 775         /*
 776          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 777          * integer value since we support only integer values of bpp.
 778          */
 779         if (DISPLAY_VER(dev_priv) >= 10 &&
 780             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 781                 if (intel_dp_is_edp(intel_dp)) {
 782                         dsc_max_output_bpp =
 783                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 784                         dsc_slice_count =
 785                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 786                                                                 true);
 787                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 788                         dsc_max_output_bpp =
 789                                 intel_dp_dsc_get_output_bpp(dev_priv,
 790                                                             max_link_clock,
 791                                                             max_lanes,
 792                                                             target_clock,
 793                                                             mode->hdisplay,
 794                                                             bigjoiner) >> 4;
 795                         dsc_slice_count =
 796                                 intel_dp_dsc_get_slice_count(intel_dp,
 797                                                              target_clock,
 798                                                              mode->hdisplay,
 799                                                              bigjoiner);
 800                 }
 801
 802                 dsc = dsc_max_output_bpp && dsc_slice_count;
 803         }
 804
 805         /* big joiner configuration needs DSC */
 806         if (bigjoiner && !dsc)
 807                 return MODE_CLOCK_HIGH;
 808
 809         if (mode_rate > max_rate && !dsc)
 810                 return MODE_CLOCK_HIGH;
 811
 812         status = intel_dp_mode_valid_downstream(intel_connector,
 813                                                 mode, target_clock);
 814         if (status != MODE_OK)
 815                 return status;
 816
 817         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 818 }
 819
 820 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
 821 {
 822         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 823
 824         return max_rate >= 540000;
 825 }
 826
 827 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
 828 {
 829         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 830
 831         return max_rate >= 810000;
 832 }
 833
 834 static void snprintf_int_array(char *str, size_t len,
 835                                const int *array, int nelem)
 836 {
 837         int i;
 838
 839         str[0] = '\0';
 840
 841         for (i = 0; i < nelem; i++) {
 842                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
 843                 if (r >= len)
 844                         return;
 845                 str += r;
 846                 len -= r;
 847         }
 848 }
 849
 850 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 851 {
 852         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 853         char str[128]; /* FIXME: too big for stack? */
 854
 855         if (!drm_debug_enabled(DRM_UT_KMS))
 856                 return;
 857
 858         snprintf_int_array(str, sizeof(str),
 859                            intel_dp->source_rates, intel_dp->num_source_rates);
 860         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
 861
 862         snprintf_int_array(str, sizeof(str),
 863                            intel_dp->sink_rates, intel_dp->num_sink_rates);
 864         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
 865
 866         snprintf_int_array(str, sizeof(str),
 867                            intel_dp->common_rates, intel_dp->num_common_rates);
 868         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
 869 }
 870
 871 int
 872 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 873 {
 874         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 875         int len;
 876
 877         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
 878         if (drm_WARN_ON(&i915->drm, len <= 0))
 879                 return 162000;
 880
 881         return intel_dp->common_rates[len - 1];
 882 }
 883
 884 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 885 {
 886         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 887         int i = intel_dp_rate_index(intel_dp->sink_rates,
 888                                     intel_dp->num_sink_rates, rate);
 889
 890         if (drm_WARN_ON(&i915->drm, i < 0))
 891                 i = 0;
 892
 893         return i;
 894 }
 895
 896 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 897                            u8 *link_bw, u8 *rate_select)
 898 {
 899         /* eDP 1.4 rate select method. */
 900         if (intel_dp->use_rate_select) {
 901                 *link_bw = 0;
 902                 *rate_select =
 903                         intel_dp_rate_select(intel_dp, port_clock);
 904         } else {
 905                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
 906                 *rate_select = 0;
 907         }
 908 }
 909
 910 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 911                                          const struct intel_crtc_state *pipe_config)
 912 {
 913         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 914
 915         /* On TGL, FEC is supported on all Pipes */
 916         if (DISPLAY_VER(dev_priv) >= 12)
 917                 return true;
 918
 919         if (IS_DISPLAY_VER(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
 920                 return true;
 921
 922         return false;
 923 }
 924
 925 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
 926                                   const struct intel_crtc_state *pipe_config)
 927 {
 928         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
 929                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
 930 }
 931
 932 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 933                                   const struct intel_crtc_state *crtc_state)
 934 {
 935         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
 936                 return false;
 937
 938         return intel_dsc_source_support(crtc_state) &&
 939                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 940 }
 941
 942 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
 943                                    const struct intel_crtc_state *crtc_state)
 944 {
 945         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 946                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
 947                  intel_dp->dfp.ycbcr_444_to_420);
 948 }
 949
 950 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
 951                                     const struct intel_crtc_state *crtc_state, int bpc)
 952 {
 953         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
 954
 955         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
 956                 clock /= 2;
 957
 958         return clock;
 959 }
 960
 961 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
 962                                            const struct intel_crtc_state *crtc_state, int bpc)
 963 {
 964         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
 965
 966         if (intel_dp->dfp.min_tmds_clock &&
 967             tmds_clock < intel_dp->dfp.min_tmds_clock)
 968                 return false;
 969
 970         if (intel_dp->dfp.max_tmds_clock &&
 971             tmds_clock > intel_dp->dfp.max_tmds_clock)
 972                 return false;
 973
 974         return true;
 975 }
 976
 977 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
 978                                               const struct intel_crtc_state *crtc_state,
 979                                               int bpc)
 980 {
 981
 982         return intel_hdmi_deep_color_possible(crtc_state, bpc,
 983                                               intel_dp->has_hdmi_sink,
 984                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
 985                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
 986 }
 987
 988 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 989                             const struct intel_crtc_state *crtc_state)
 990 {
 991         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 992         struct intel_connector *intel_connector = intel_dp->attached_connector;
 993         int bpp, bpc;
 994
 995         bpc = crtc_state->pipe_bpp / 3;
 996
 997         if (intel_dp->dfp.max_bpc)
 998                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
 999
1000         if (intel_dp->dfp.min_tmds_clock) {
1001                 for (; bpc >= 10; bpc -= 2) {
1002                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1003                                 break;
1004                 }
1005         }
1006
1007         bpp = bpc * 3;
1008         if (intel_dp_is_edp(intel_dp)) {
1009                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1010                 if (intel_connector->base.display_info.bpc == 0 &&
1011                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1012                         drm_dbg_kms(&dev_priv->drm,
1013                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1014                                     dev_priv->vbt.edp.bpp);
1015                         bpp = dev_priv->vbt.edp.bpp;
1016                 }
1017         }
1018
1019         return bpp;
1020 }
1021
1022 /* Adjust link config limits based on compliance test requests. */
1023 void
1024 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1025                                   struct intel_crtc_state *pipe_config,
1026                                   struct link_config_limits *limits)
1027 {
1028         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1029
1030         /* For DP Compliance we override the computed bpp for the pipe */
1031         if (intel_dp->compliance.test_data.bpc != 0) {
1032                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1033
1034                 limits->min_bpp = limits->max_bpp = bpp;
1035                 pipe_config->dither_force_disable = bpp == 6 * 3;
1036
1037                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1038         }
1039
1040         /* Use values requested by Compliance Test Request */
1041         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1042                 int index;
1043
1044                 /* Validate the compliance test data since max values
1045                  * might have changed due to link train fallback.
1046                  */
1047                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1048                                                intel_dp->compliance.test_lane_count)) {
1049                         index = intel_dp_rate_index(intel_dp->common_rates,
1050                                                     intel_dp->num_common_rates,
1051                                                     intel_dp->compliance.test_link_rate);
1052                         if (index >= 0)
1053                                 limits->min_clock = limits->max_clock = index;
1054                         limits->min_lane_count = limits->max_lane_count =
1055                                 intel_dp->compliance.test_lane_count;
1056                 }
1057         }
1058 }
1059
1060 /* Optimize link config in order: max bpp, min clock, min lanes */
1061 static int
1062 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1063                                   struct intel_crtc_state *pipe_config,
1064                                   const struct link_config_limits *limits)
1065 {
1066         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1067         int bpp, clock, lane_count;
1068         int mode_rate, link_clock, link_avail;
1069
1070         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1071                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1072
1073                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1074                                                    output_bpp);
1075
1076                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1077                         for (lane_count = limits->min_lane_count;
1078                              lane_count <= limits->max_lane_count;
1079                              lane_count <<= 1) {
1080                                 link_clock = intel_dp->common_rates[clock];
1081                                 link_avail = intel_dp_max_data_rate(link_clock,
1082                                                                     lane_count);
1083
1084                                 if (mode_rate <= link_avail) {
1085                                         pipe_config->lane_count = lane_count;
1086                                         pipe_config->pipe_bpp = bpp;
1087                                         pipe_config->port_clock = link_clock;
1088
1089                                         return 0;
1090                                 }
1091                         }
1092                 }
1093         }
1094
1095         return -EINVAL;
1096 }
1097
1098 /* Optimize link config in order: max bpp, min lanes, min clock */
1099 static int
1100 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1101                                   struct intel_crtc_state *pipe_config,
1102                                   const struct link_config_limits *limits)
1103 {
1104         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1105         int bpp, clock, lane_count;
1106         int mode_rate, link_clock, link_avail;
1107
1108         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1109                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1110
1111                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1112                                                    output_bpp);
1113
1114                 for (lane_count = limits->min_lane_count;
1115                      lane_count <= limits->max_lane_count;
1116                      lane_count <<= 1) {
1117                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1118                                 link_clock = intel_dp->common_rates[clock];
1119                                 link_avail = intel_dp_max_data_rate(link_clock,
1120                                                                     lane_count);
1121
1122                                 if (mode_rate <= link_avail) {
1123                                         pipe_config->lane_count = lane_count;
1124                                         pipe_config->pipe_bpp = bpp;
1125                                         pipe_config->port_clock = link_clock;
1126
1127                                         return 0;
1128                                 }
1129                         }
1130                 }
1131         }
1132
1133         return -EINVAL;
1134 }
1135
1136 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1137 {
1138         int i, num_bpc;
1139         u8 dsc_bpc[3] = {0};
1140
1141         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1142                                                        dsc_bpc);
1143         for (i = 0; i < num_bpc; i++) {
1144                 if (dsc_max_bpc >= dsc_bpc[i])
1145                         return dsc_bpc[i] * 3;
1146         }
1147
1148         return 0;
1149 }
1150
1151 #define DSC_SUPPORTED_VERSION_MIN               1
1152
1153 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1154                                        struct intel_crtc_state *crtc_state)
1155 {
1156         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1157         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1158         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1159         u8 line_buf_depth;
1160         int ret;
1161
1162         /*
1163          * RC_MODEL_SIZE is currently a constant across all configurations.
1164          *
1165          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1166          * DP_DSC_RC_BUF_SIZE for this.
1167          */
1168         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1169
1170         ret = intel_dsc_compute_params(encoder, crtc_state);
1171         if (ret)
1172                 return ret;
1173
1174         /*
1175          * Slice Height of 8 works for all currently available panels. So start
1176          * with that if pic_height is an integral multiple of 8. Eventually add
1177          * logic to try multiple slice heights.
1178          */
1179         if (vdsc_cfg->pic_height % 8 == 0)
1180                 vdsc_cfg->slice_height = 8;
1181         else if (vdsc_cfg->pic_height % 4 == 0)
1182                 vdsc_cfg->slice_height = 4;
1183         else
1184                 vdsc_cfg->slice_height = 2;
1185
1186         vdsc_cfg->dsc_version_major =
1187                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1188                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1189         vdsc_cfg->dsc_version_minor =
1190                 min(DSC_SUPPORTED_VERSION_MIN,
1191                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1192                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1193
1194         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1195                 DP_DSC_RGB;
1196
1197         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1198         if (!line_buf_depth) {
1199                 drm_dbg_kms(&i915->drm,
1200                             "DSC Sink Line Buffer Depth invalid\n");
1201                 return -EINVAL;
1202         }
1203
1204         if (vdsc_cfg->dsc_version_minor == 2)
1205                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1206                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1207         else
1208                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1209                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1210
1211         vdsc_cfg->block_pred_enable =
1212                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1213                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1214
1215         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1216 }
1217
1218 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1219                                        struct intel_crtc_state *pipe_config,
1220                                        struct drm_connector_state *conn_state,
1221                                        struct link_config_limits *limits)
1222 {
1223         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1224         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1225         const struct drm_display_mode *adjusted_mode =
1226                 &pipe_config->hw.adjusted_mode;
1227         u8 dsc_max_bpc;
1228         int pipe_bpp;
1229         int ret;
1230
1231         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1232                 intel_dp_supports_fec(intel_dp, pipe_config);
1233
1234         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1235                 return -EINVAL;
1236
1237         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1238         if (DISPLAY_VER(dev_priv) >= 12)
1239                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1240         else
1241                 dsc_max_bpc = min_t(u8, 10,
1242                                     conn_state->max_requested_bpc);
1243
1244         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1245
1246         /* Min Input BPC for ICL+ is 8 */
1247         if (pipe_bpp < 8 * 3) {
1248                 drm_dbg_kms(&dev_priv->drm,
1249                             "No DSC support for less than 8bpc\n");
1250                 return -EINVAL;
1251         }
1252
1253         /*
1254          * For now enable DSC for max bpp, max link rate, max lane count.
1255          * Optimize this later for the minimum possible link rate/lane count
1256          * with DSC enabled for the requested mode.
1257          */
1258         pipe_config->pipe_bpp = pipe_bpp;
1259         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1260         pipe_config->lane_count = limits->max_lane_count;
1261
1262         if (intel_dp_is_edp(intel_dp)) {
1263                 pipe_config->dsc.compressed_bpp =
1264                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1265                               pipe_config->pipe_bpp);
1266                 pipe_config->dsc.slice_count =
1267                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1268                                                         true);
1269         } else {
1270                 u16 dsc_max_output_bpp;
1271                 u8 dsc_dp_slice_count;
1272
1273                 dsc_max_output_bpp =
1274                         intel_dp_dsc_get_output_bpp(dev_priv,
1275                                                     pipe_config->port_clock,
1276                                                     pipe_config->lane_count,
1277                                                     adjusted_mode->crtc_clock,
1278                                                     adjusted_mode->crtc_hdisplay,
1279                                                     pipe_config->bigjoiner);
1280                 dsc_dp_slice_count =
1281                         intel_dp_dsc_get_slice_count(intel_dp,
1282                                                      adjusted_mode->crtc_clock,
1283                                                      adjusted_mode->crtc_hdisplay,
1284                                                      pipe_config->bigjoiner);
1285                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1286                         drm_dbg_kms(&dev_priv->drm,
1287                                     "Compressed BPP/Slice Count not supported\n");
1288                         return -EINVAL;
1289                 }
1290                 pipe_config->dsc.compressed_bpp = min_t(u16,
1291                                                                dsc_max_output_bpp >> 4,
1292                                                                pipe_config->pipe_bpp);
1293                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1294         }
1295         /*
1296          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1297          * is greater than the maximum Cdclock and if slice count is even
1298          * then we need to use 2 VDSC instances.
1299          */
1300         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1301             pipe_config->bigjoiner) {
1302                 if (pipe_config->dsc.slice_count < 2) {
1303                         drm_dbg_kms(&dev_priv->drm,
1304                                     "Cannot split stream to use 2 VDSC instances\n");
1305                         return -EINVAL;
1306                 }
1307
1308                 pipe_config->dsc.dsc_split = true;
1309         }
1310
1311         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1312         if (ret < 0) {
1313                 drm_dbg_kms(&dev_priv->drm,
1314                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1315                             "Compressed BPP = %d\n",
1316                             pipe_config->pipe_bpp,
1317                             pipe_config->dsc.compressed_bpp);
1318                 return ret;
1319         }
1320
1321         pipe_config->dsc.compression_enable = true;
1322         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1323                     "Compressed Bpp = %d Slice Count = %d\n",
1324                     pipe_config->pipe_bpp,
1325                     pipe_config->dsc.compressed_bpp,
1326                     pipe_config->dsc.slice_count);
1327
1328         return 0;
1329 }
1330
1331 static int
1332 intel_dp_compute_link_config(struct intel_encoder *encoder,
1333                              struct intel_crtc_state *pipe_config,
1334                              struct drm_connector_state *conn_state)
1335 {
1336         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1337         const struct drm_display_mode *adjusted_mode =
1338                 &pipe_config->hw.adjusted_mode;
1339         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1340         struct link_config_limits limits;
1341         int common_len;
1342         int ret;
1343
1344         common_len = intel_dp_common_len_rate_limit(intel_dp,
1345                                                     intel_dp->max_link_rate);
1346
1347         /* No common link rates between source and sink */
1348         drm_WARN_ON(encoder->base.dev, common_len <= 0);
1349
1350         limits.min_clock = 0;
1351         limits.max_clock = common_len - 1;
1352
1353         limits.min_lane_count = 1;
1354         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1355
1356         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1357         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1358
1359         if (intel_dp->use_max_params) {
1360                 /*
1361                  * Use the maximum clock and number of lanes the eDP panel
1362                  * advertizes being capable of in case the initial fast
1363                  * optimal params failed us. The panels are generally
1364                  * designed to support only a single clock and lane
1365                  * configuration, and typically on older panels these
1366                  * values correspond to the native resolution of the panel.
1367                  */
1368                 limits.min_lane_count = limits.max_lane_count;
1369                 limits.min_clock = limits.max_clock;
1370         }
1371
1372         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1373
1374         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1375                     "max rate %d max bpp %d pixel clock %iKHz\n",
1376                     limits.max_lane_count,
1377                     intel_dp->common_rates[limits.max_clock],
1378                     limits.max_bpp, adjusted_mode->crtc_clock);
1379
1380         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1381              adjusted_mode->crtc_hdisplay > 5120) &&
1382             intel_dp_can_bigjoiner(intel_dp))
1383                 pipe_config->bigjoiner = true;
1384
1385         if (intel_dp_is_edp(intel_dp))
1386                 /*
1387                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
1388                  * section A.1: "It is recommended that the minimum number of
1389                  * lanes be used, using the minimum link rate allowed for that
1390                  * lane configuration."
1391                  *
1392                  * Note that we fall back to the max clock and lane count for eDP
1393                  * panels that fail with the fast optimal settings (see
1394                  * intel_dp->use_max_params), in which case the fast vs. wide
1395                  * choice doesn't matter.
1396                  */
1397                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
1398         else
1399                 /* Optimize for slow and wide. */
1400                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1401
1402         /* enable compression if the mode doesn't fit available BW */
1403         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1404         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
1405                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1406                                                   conn_state, &limits);
1407                 if (ret < 0)
1408                         return ret;
1409         }
1410
1411         if (pipe_config->dsc.compression_enable) {
1412                 drm_dbg_kms(&i915->drm,
1413                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1414                             pipe_config->lane_count, pipe_config->port_clock,
1415                             pipe_config->pipe_bpp,
1416                             pipe_config->dsc.compressed_bpp);
1417
1418                 drm_dbg_kms(&i915->drm,
1419                             "DP link rate required %i available %i\n",
1420                             intel_dp_link_required(adjusted_mode->crtc_clock,
1421                                                    pipe_config->dsc.compressed_bpp),
1422                             intel_dp_max_data_rate(pipe_config->port_clock,
1423                                                    pipe_config->lane_count));
1424         } else {
1425                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1426                             pipe_config->lane_count, pipe_config->port_clock,
1427                             pipe_config->pipe_bpp);
1428
1429                 drm_dbg_kms(&i915->drm,
1430                             "DP link rate required %i available %i\n",
1431                             intel_dp_link_required(adjusted_mode->crtc_clock,
1432                                                    pipe_config->pipe_bpp),
1433                             intel_dp_max_data_rate(pipe_config->port_clock,
1434                                                    pipe_config->lane_count));
1435         }
1436         return 0;
1437 }
1438
1439 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1440                                   const struct drm_connector_state *conn_state)
1441 {
1442         const struct intel_digital_connector_state *intel_conn_state =
1443                 to_intel_digital_connector_state(conn_state);
1444         const struct drm_display_mode *adjusted_mode =
1445                 &crtc_state->hw.adjusted_mode;
1446
1447         /*
1448          * Our YCbCr output is always limited range.
1449          * crtc_state->limited_color_range only applies to RGB,
1450          * and it must never be set for YCbCr or we risk setting
1451          * some conflicting bits in PIPECONF which will mess up
1452          * the colors on the monitor.
1453          */
1454         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1455                 return false;
1456
1457         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1458                 /*
1459                  * See:
1460                  * CEA-861-E - 5.1 Default Encoding Parameters
1461                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1462                  */
1463                 return crtc_state->pipe_bpp != 18 &&
1464                         drm_default_rgb_quant_range(adjusted_mode) ==
1465                         HDMI_QUANTIZATION_RANGE_LIMITED;
1466         } else {
1467                 return intel_conn_state->broadcast_rgb ==
1468                         INTEL_BROADCAST_RGB_LIMITED;
1469         }
1470 }
1471
1472 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1473                                     enum port port)
1474 {
1475         if (IS_G4X(dev_priv))
1476                 return false;
1477         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1478                 return false;
1479
1480         return true;
1481 }
1482
1483 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1484                                              const struct drm_connector_state *conn_state,
1485                                              struct drm_dp_vsc_sdp *vsc)
1486 {
1487         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1488         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1489
1490         /*
1491          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1492          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1493          * Colorimetry Format indication.
1494          */
1495         vsc->revision = 0x5;
1496         vsc->length = 0x13;
1497
1498         /* DP 1.4a spec, Table 2-120 */
1499         switch (crtc_state->output_format) {
1500         case INTEL_OUTPUT_FORMAT_YCBCR444:
1501                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1502                 break;
1503         case INTEL_OUTPUT_FORMAT_YCBCR420:
1504                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1505                 break;
1506         case INTEL_OUTPUT_FORMAT_RGB:
1507         default:
1508                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1509         }
1510
1511         switch (conn_state->colorspace) {
1512         case DRM_MODE_COLORIMETRY_BT709_YCC:
1513                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1514                 break;
1515         case DRM_MODE_COLORIMETRY_XVYCC_601:
1516                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1517                 break;
1518         case DRM_MODE_COLORIMETRY_XVYCC_709:
1519                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1520                 break;
1521         case DRM_MODE_COLORIMETRY_SYCC_601:
1522                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1523                 break;
1524         case DRM_MODE_COLORIMETRY_OPYCC_601:
1525                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1526                 break;
1527         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1528                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1529                 break;
1530         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1531                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1532                 break;
1533         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1534                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1535                 break;
1536         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1537         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1538                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1539                 break;
1540         default:
1541                 /*
1542                  * RGB->YCBCR color conversion uses the BT.709
1543                  * color space.
1544                  */
1545                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1546                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1547                 else
1548                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1549                 break;
1550         }
1551
1552         vsc->bpc = crtc_state->pipe_bpp / 3;
1553
1554         /* only RGB pixelformat supports 6 bpc */
1555         drm_WARN_ON(&dev_priv->drm,
1556                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1557
1558         /* all YCbCr are always limited range */
1559         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1560         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1561 }
1562
1563 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1564                                      struct intel_crtc_state *crtc_state,
1565                                      const struct drm_connector_state *conn_state)
1566 {
1567         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1568
1569         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1570         if (crtc_state->has_psr)
1571                 return;
1572
1573         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1574                 return;
1575
1576         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1577         vsc->sdp_type = DP_SDP_VSC;
1578         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1579                                          &crtc_state->infoframes.vsc);
1580 }
1581
1582 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1583                                   const struct intel_crtc_state *crtc_state,
1584                                   const struct drm_connector_state *conn_state,
1585                                   struct drm_dp_vsc_sdp *vsc)
1586 {
1587         vsc->sdp_type = DP_SDP_VSC;
1588
1589         if (intel_dp->psr.psr2_enabled) {
1590                 if (intel_dp->psr.colorimetry_support &&
1591                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1592                         /* [PSR2, +Colorimetry] */
1593                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1594                                                          vsc);
1595                 } else {
1596                         /*
1597                          * [PSR2, -Colorimetry]
1598                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1599                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1600                          */
1601                         vsc->revision = 0x4;
1602                         vsc->length = 0xe;
1603                 }
1604         } else {
1605                 /*
1606                  * [PSR1]
1607                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1608                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1609                  * higher).
1610                  */
1611                 vsc->revision = 0x2;
1612                 vsc->length = 0x8;
1613         }
1614 }
1615
1616 static void
1617 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1618                                             struct intel_crtc_state *crtc_state,
1619                                             const struct drm_connector_state *conn_state)
1620 {
1621         int ret;
1622         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1623         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1624
1625         if (!conn_state->hdr_output_metadata)
1626                 return;
1627
1628         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1629
1630         if (ret) {
1631                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1632                 return;
1633         }
1634
1635         crtc_state->infoframes.enable |=
1636                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1637 }
1638
1639 static void
1640 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1641                              struct intel_crtc_state *pipe_config,
1642                              int output_bpp, bool constant_n)
1643 {
1644         struct intel_connector *intel_connector = intel_dp->attached_connector;
1645         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1646         int pixel_clock;
1647
1648         if (pipe_config->vrr.enable)
1649                 return;
1650
1651         /*
1652          * DRRS and PSR can't be enable together, so giving preference to PSR
1653          * as it allows more power-savings by complete shutting down display,
1654          * so to guarantee this, intel_dp_drrs_compute_config() must be called
1655          * after intel_psr_compute_config().
1656          */
1657         if (pipe_config->has_psr)
1658                 return;
1659
1660         if (!intel_connector->panel.downclock_mode ||
1661             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1662                 return;
1663
1664         pipe_config->has_drrs = true;
1665
1666         pixel_clock = intel_connector->panel.downclock_mode->clock;
1667         if (pipe_config->splitter.enable)
1668                 pixel_clock /= pipe_config->splitter.link_count;
1669
1670         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1671                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1672                                constant_n, pipe_config->fec_enable);
1673
1674         /* FIXME: abstract this better */
1675         if (pipe_config->splitter.enable)
1676                 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1677 }
1678
1679 int
1680 intel_dp_compute_config(struct intel_encoder *encoder,
1681                         struct intel_crtc_state *pipe_config,
1682                         struct drm_connector_state *conn_state)
1683 {
1684         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1685         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1686         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1687         enum port port = encoder->port;
1688         struct intel_connector *intel_connector = intel_dp->attached_connector;
1689         struct intel_digital_connector_state *intel_conn_state =
1690                 to_intel_digital_connector_state(conn_state);
1691         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1692         int ret = 0, output_bpp;
1693
1694         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1695                 pipe_config->has_pch_encoder = true;
1696
1697         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1698                                                             adjusted_mode);
1699
1700         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1701                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1702                 if (ret)
1703                         return ret;
1704         }
1705
1706         if (!intel_dp_port_has_audio(dev_priv, port))
1707                 pipe_config->has_audio = false;
1708         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1709                 pipe_config->has_audio = intel_dp->has_audio;
1710         else
1711                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1712
1713         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1714                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1715                                        adjusted_mode);
1716
1717                 if (HAS_GMCH(dev_priv))
1718                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1719                 else
1720                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
1721                 if (ret)
1722                         return ret;
1723         }
1724
1725         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1726                 return -EINVAL;
1727
1728         if (HAS_GMCH(dev_priv) &&
1729             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1730                 return -EINVAL;
1731
1732         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1733                 return -EINVAL;
1734
1735         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1736                 return -EINVAL;
1737
1738         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1739         if (ret < 0)
1740                 return ret;
1741
1742         pipe_config->limited_color_range =
1743                 intel_dp_limited_color_range(pipe_config, conn_state);
1744
1745         if (pipe_config->dsc.compression_enable)
1746                 output_bpp = pipe_config->dsc.compressed_bpp;
1747         else
1748                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1749                                                  pipe_config->pipe_bpp);
1750
1751         if (intel_dp->mso_link_count) {
1752                 int n = intel_dp->mso_link_count;
1753                 int overlap = intel_dp->mso_pixel_overlap;
1754
1755                 pipe_config->splitter.enable = true;
1756                 pipe_config->splitter.link_count = n;
1757                 pipe_config->splitter.pixel_overlap = overlap;
1758
1759                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1760                             n, overlap);
1761
1762                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1763                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1764                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1765                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1766                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1767                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1768                 adjusted_mode->crtc_clock /= n;
1769         }
1770
1771         intel_link_compute_m_n(output_bpp,
1772                                pipe_config->lane_count,
1773                                adjusted_mode->crtc_clock,
1774                                pipe_config->port_clock,
1775                                &pipe_config->dp_m_n,
1776                                constant_n, pipe_config->fec_enable);
1777
1778         /* FIXME: abstract this better */
1779         if (pipe_config->splitter.enable)
1780                 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1781
1782         if (!HAS_DDI(dev_priv))
1783                 g4x_dp_set_clock(encoder, pipe_config);
1784
1785         intel_vrr_compute_config(pipe_config, conn_state);
1786         intel_psr_compute_config(intel_dp, pipe_config);
1787         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1788                                      constant_n);
1789         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1790         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1791
1792         return 0;
1793 }
1794
1795 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1796                               int link_rate, int lane_count)
1797 {
1798         intel_dp->link_trained = false;
1799         intel_dp->link_rate = link_rate;
1800         intel_dp->lane_count = lane_count;
1801 }
1802
1803 /* Enable backlight PWM and backlight PP control. */
1804 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1805                             const struct drm_connector_state *conn_state)
1806 {
1807         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1808         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1809
1810         if (!intel_dp_is_edp(intel_dp))
1811                 return;
1812
1813         drm_dbg_kms(&i915->drm, "\n");
1814
1815         intel_panel_enable_backlight(crtc_state, conn_state);
1816         intel_pps_backlight_on(intel_dp);
1817 }
1818
1819 /* Disable backlight PP control and backlight PWM. */
1820 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1821 {
1822         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1823         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1824
1825         if (!intel_dp_is_edp(intel_dp))
1826                 return;
1827
1828         drm_dbg_kms(&i915->drm, "\n");
1829
1830         intel_pps_backlight_off(intel_dp);
1831         intel_panel_disable_backlight(old_conn_state);
1832 }
1833
1834 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1835 {
1836         /*
1837          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1838          * be capable of signalling downstream hpd with a long pulse.
1839          * Whether or not that means D3 is safe to use is not clear,
1840          * but let's assume so until proven otherwise.
1841          *
1842          * FIXME should really check all downstream ports...
1843          */
1844         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1845                 drm_dp_is_branch(intel_dp->dpcd) &&
1846                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1847 }
1848
1849 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1850                                            const struct intel_crtc_state *crtc_state,
1851                                            bool enable)
1852 {
1853         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1854         int ret;
1855
1856         if (!crtc_state->dsc.compression_enable)
1857                 return;
1858
1859         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1860                                  enable ? DP_DECOMPRESSION_EN : 0);
1861         if (ret < 0)
1862                 drm_dbg_kms(&i915->drm,
1863                             "Failed to %s sink decompression state\n",
1864                             enable ? "enable" : "disable");
1865 }
1866
1867 static void
1868 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1869 {
1870         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1871         u8 oui[] = { 0x00, 0xaa, 0x01 };
1872         u8 buf[3] = { 0 };
1873
1874         /*
1875          * During driver init, we want to be careful and avoid changing the source OUI if it's
1876          * already set to what we want, so as to avoid clearing any state by accident
1877          */
1878         if (careful) {
1879                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1880                         drm_err(&i915->drm, "Failed to read source OUI\n");
1881
1882                 if (memcmp(oui, buf, sizeof(oui)) == 0)
1883                         return;
1884         }
1885
1886         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1887                 drm_err(&i915->drm, "Failed to write source OUI\n");
1888 }
1889
1890 /* If the device supports it, try to set the power state appropriately */
1891 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1892 {
1893         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1894         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1895         int ret, i;
1896
1897         /* Should have a valid DPCD by this point */
1898         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1899                 return;
1900
1901         if (mode != DP_SET_POWER_D0) {
1902                 if (downstream_hpd_needs_d0(intel_dp))
1903                         return;
1904
1905                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1906         } else {
1907                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1908
1909                 lspcon_resume(dp_to_dig_port(intel_dp));
1910
1911                 /* Write the source OUI as early as possible */
1912                 if (intel_dp_is_edp(intel_dp))
1913                         intel_edp_init_source_oui(intel_dp, false);
1914
1915                 /*
1916                  * When turning on, we need to retry for 1ms to give the sink
1917                  * time to wake up.
1918                  */
1919                 for (i = 0; i < 3; i++) {
1920                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1921                         if (ret == 1)
1922                                 break;
1923                         msleep(1);
1924                 }
1925
1926                 if (ret == 1 && lspcon->active)
1927                         lspcon_wait_pcon_mode(lspcon);
1928         }
1929
1930         if (ret != 1)
1931                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1932                             encoder->base.base.id, encoder->base.name,
1933                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
1934 }
1935
1936 static bool
1937 intel_dp_get_dpcd(struct intel_dp *intel_dp);
1938
1939 /**
1940  * intel_dp_sync_state - sync the encoder state during init/resume
1941  * @encoder: intel encoder to sync
1942  * @crtc_state: state for the CRTC connected to the encoder
1943  *
1944  * Sync any state stored in the encoder wrt. HW state during driver init
1945  * and system resume.
1946  */
1947 void intel_dp_sync_state(struct intel_encoder *encoder,
1948                          const struct intel_crtc_state *crtc_state)
1949 {
1950         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1951
1952         /*
1953          * Don't clobber DPCD if it's been already read out during output
1954          * setup (eDP) or detect.
1955          */
1956         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1957                 intel_dp_get_dpcd(intel_dp);
1958
1959         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1960         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1961 }
1962
1963 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1964                                     struct intel_crtc_state *crtc_state)
1965 {
1966         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1967         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1968
1969         /*
1970          * If BIOS has set an unsupported or non-standard link rate for some
1971          * reason force an encoder recompute and full modeset.
1972          */
1973         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1974                                 crtc_state->port_clock) < 0) {
1975                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1976                 crtc_state->uapi.connectors_changed = true;
1977                 return false;
1978         }
1979
1980         /*
1981          * FIXME hack to force full modeset when DSC is being used.
1982          *
1983          * As long as we do not have full state readout and config comparison
1984          * of crtc_state->dsc, we have no way to ensure reliable fastset.
1985          * Remove once we have readout for DSC.
1986          */
1987         if (crtc_state->dsc.compression_enable) {
1988                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1989                 crtc_state->uapi.mode_changed = true;
1990                 return false;
1991         }
1992
1993         if (CAN_PSR(intel_dp)) {
1994                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1995                 crtc_state->uapi.mode_changed = true;
1996                 return false;
1997         }
1998
1999         return true;
2000 }
2001
2002 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2003 {
2004         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2005
2006         /* Clear the cached register set to avoid using stale values */
2007
2008         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2009
2010         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2011                              intel_dp->pcon_dsc_dpcd,
2012                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2013                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2014                         DP_PCON_DSC_ENCODER);
2015
2016         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2017                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2018 }
2019
2020 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2021 {
2022         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2023         int i;
2024
2025         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2026                 if (frl_bw_mask & (1 << i))
2027                         return bw_gbps[i];
2028         }
2029         return 0;
2030 }
2031
2032 static int intel_dp_pcon_set_frl_mask(int max_frl)
2033 {
2034         switch (max_frl) {
2035         case 48:
2036                 return DP_PCON_FRL_BW_MASK_48GBPS;
2037         case 40:
2038                 return DP_PCON_FRL_BW_MASK_40GBPS;
2039         case 32:
2040                 return DP_PCON_FRL_BW_MASK_32GBPS;
2041         case 24:
2042                 return DP_PCON_FRL_BW_MASK_24GBPS;
2043         case 18:
2044                 return DP_PCON_FRL_BW_MASK_18GBPS;
2045         case 9:
2046                 return DP_PCON_FRL_BW_MASK_9GBPS;
2047         }
2048
2049         return 0;
2050 }
2051
2052 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2053 {
2054         struct intel_connector *intel_connector = intel_dp->attached_connector;
2055         struct drm_connector *connector = &intel_connector->base;
2056         int max_frl_rate;
2057         int max_lanes, rate_per_lane;
2058         int max_dsc_lanes, dsc_rate_per_lane;
2059
2060         max_lanes = connector->display_info.hdmi.max_lanes;
2061         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2062         max_frl_rate = max_lanes * rate_per_lane;
2063
2064         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2065                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2066                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2067                 if (max_dsc_lanes && dsc_rate_per_lane)
2068                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2069         }
2070
2071         return max_frl_rate;
2072 }
2073
2074 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2075 {
2076 #define TIMEOUT_FRL_READY_MS 500
2077 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2078
2079         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2080         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2081         u8 max_frl_bw_mask = 0, frl_trained_mask;
2082         bool is_active;
2083
2084         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2085         if (ret < 0)
2086                 return ret;
2087
2088         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2089         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2090
2091         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2092         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2093
2094         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2095
2096         if (max_frl_bw <= 0)
2097                 return -EINVAL;
2098
2099         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2100         if (ret < 0)
2101                 return ret;
2102         /* Wait for PCON to be FRL Ready */
2103         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2104
2105         if (!is_active)
2106                 return -ETIMEDOUT;
2107
2108         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2109         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2110                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2111         if (ret < 0)
2112                 return ret;
2113         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2114                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2115         if (ret < 0)
2116                 return ret;
2117         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2118         if (ret < 0)
2119                 return ret;
2120         /*
2121          * Wait for FRL to be completed
2122          * Check if the HDMI Link is up and active.
2123          */
2124         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2125
2126         if (!is_active)
2127                 return -ETIMEDOUT;
2128
2129         /* Verify HDMI Link configuration shows FRL Mode */
2130         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2131             DP_PCON_HDMI_MODE_FRL) {
2132                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2133                 return -EINVAL;
2134         }
2135         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2136
2137         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2138         intel_dp->frl.is_trained = true;
2139         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2140
2141         return 0;
2142 }
2143
2144 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2145 {
2146         if (drm_dp_is_branch(intel_dp->dpcd) &&
2147             intel_dp->has_hdmi_sink &&
2148             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2149                 return true;
2150
2151         return false;
2152 }
2153
2154 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2155 {
2156         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2157
2158         /* Always go for FRL training if supported */
2159         if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2160             intel_dp->frl.is_trained)
2161                 return;
2162
2163         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2164                 int ret, mode;
2165
2166                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2167                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2168                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2169
2170                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2171                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2172         } else {
2173                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2174         }
2175 }
2176
2177 static int
2178 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2179 {
2180         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2181
2182         return intel_hdmi_dsc_get_slice_height(vactive);
2183 }
2184
2185 static int
2186 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2187                              const struct intel_crtc_state *crtc_state)
2188 {
2189         struct intel_connector *intel_connector = intel_dp->attached_connector;
2190         struct drm_connector *connector = &intel_connector->base;
2191         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2192         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2193         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2194         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2195
2196         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2197                                              pcon_max_slice_width,
2198                                              hdmi_max_slices, hdmi_throughput);
2199 }
2200
2201 static int
2202 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2203                           const struct intel_crtc_state *crtc_state,
2204                           int num_slices, int slice_width)
2205 {
2206         struct intel_connector *intel_connector = intel_dp->attached_connector;
2207         struct drm_connector *connector = &intel_connector->base;
2208         int output_format = crtc_state->output_format;
2209         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2210         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2211         int hdmi_max_chunk_bytes =
2212                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2213
2214         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2215                                       num_slices, output_format, hdmi_all_bpp,
2216                                       hdmi_max_chunk_bytes);
2217 }
2218
2219 void
2220 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2221                             const struct intel_crtc_state *crtc_state)
2222 {
2223         u8 pps_param[6];
2224         int slice_height;
2225         int slice_width;
2226         int num_slices;
2227         int bits_per_pixel;
2228         int ret;
2229         struct intel_connector *intel_connector = intel_dp->attached_connector;
2230         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2231         struct drm_connector *connector;
2232         bool hdmi_is_dsc_1_2;
2233
2234         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2235                 return;
2236
2237         if (!intel_connector)
2238                 return;
2239         connector = &intel_connector->base;
2240         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2241
2242         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2243             !hdmi_is_dsc_1_2)
2244                 return;
2245
2246         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2247         if (!slice_height)
2248                 return;
2249
2250         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2251         if (!num_slices)
2252                 return;
2253
2254         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2255                                    num_slices);
2256
2257         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2258                                                    num_slices, slice_width);
2259         if (!bits_per_pixel)
2260                 return;
2261
2262         pps_param[0] = slice_height & 0xFF;
2263         pps_param[1] = slice_height >> 8;
2264         pps_param[2] = slice_width & 0xFF;
2265         pps_param[3] = slice_width >> 8;
2266         pps_param[4] = bits_per_pixel & 0xFF;
2267         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2268
2269         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2270         if (ret < 0)
2271                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2272 }
2273
2274 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2275                                            const struct intel_crtc_state *crtc_state)
2276 {
2277         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2278         u8 tmp;
2279
2280         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2281                 return;
2282
2283         if (!drm_dp_is_branch(intel_dp->dpcd))
2284                 return;
2285
2286         tmp = intel_dp->has_hdmi_sink ?
2287                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2288
2289         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2290                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2291                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
2292                             enableddisabled(intel_dp->has_hdmi_sink));
2293
2294         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2295                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2296
2297         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2298                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2299                 drm_dbg_kms(&i915->drm,
2300                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
2301                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
2302
2303         tmp = 0;
2304         if (intel_dp->dfp.rgb_to_ycbcr) {
2305                 bool bt2020, bt709;
2306
2307                 /*
2308                  * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2309                  * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2310                  *
2311                  */
2312                 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2313
2314                 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2315                                                                    intel_dp->downstream_ports,
2316                                                                    DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2317                 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2318                                                                   intel_dp->downstream_ports,
2319                                                                   DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2320                 switch (crtc_state->infoframes.vsc.colorimetry) {
2321                 case DP_COLORIMETRY_BT2020_RGB:
2322                 case DP_COLORIMETRY_BT2020_YCC:
2323                         if (bt2020)
2324                                 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2325                         break;
2326                 case DP_COLORIMETRY_BT709_YCC:
2327                 case DP_COLORIMETRY_XVYCC_709:
2328                         if (bt709)
2329                                 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2330                         break;
2331                 default:
2332                         break;
2333                 }
2334         }
2335
2336         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2337                 drm_dbg_kms(&i915->drm,
2338                            "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
2339                            enableddisabled(tmp ? true : false));
2340 }
2341
2342
2343 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2344 {
2345         u8 dprx = 0;
2346
2347         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2348                               &dprx) != 1)
2349                 return false;
2350         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2351 }
2352
2353 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2354 {
2355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2356
2357         /*
2358          * Clear the cached register set to avoid using stale values
2359          * for the sinks that do not support DSC.
2360          */
2361         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2362
2363         /* Clear fec_capable to avoid using stale values */
2364         intel_dp->fec_capable = 0;
2365
2366         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2367         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2368             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2369                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2370                                      intel_dp->dsc_dpcd,
2371                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2372                         drm_err(&i915->drm,
2373                                 "Failed to read DPCD register 0x%x\n",
2374                                 DP_DSC_SUPPORT);
2375
2376                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2377                             (int)sizeof(intel_dp->dsc_dpcd),
2378                             intel_dp->dsc_dpcd);
2379
2380                 /* FEC is supported only on DP 1.4 */
2381                 if (!intel_dp_is_edp(intel_dp) &&
2382                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2383                                       &intel_dp->fec_capable) < 0)
2384                         drm_err(&i915->drm,
2385                                 "Failed to read FEC DPCD register\n");
2386
2387                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2388                             intel_dp->fec_capable);
2389         }
2390 }
2391
2392 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2393                                      struct drm_display_mode *mode)
2394 {
2395         struct intel_dp *intel_dp = intel_attached_dp(connector);
2396         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2397         int n = intel_dp->mso_link_count;
2398         int overlap = intel_dp->mso_pixel_overlap;
2399
2400         if (!mode || !n)
2401                 return;
2402
2403         mode->hdisplay = (mode->hdisplay - overlap) * n;
2404         mode->hsync_start = (mode->hsync_start - overlap) * n;
2405         mode->hsync_end = (mode->hsync_end - overlap) * n;
2406         mode->htotal = (mode->htotal - overlap) * n;
2407         mode->clock *= n;
2408
2409         drm_mode_set_name(mode);
2410
2411         drm_dbg_kms(&i915->drm,
2412                     "[CONNECTOR:%d:%s] using generated MSO mode: ",
2413                     connector->base.base.id, connector->base.name);
2414         drm_mode_debug_printmodeline(mode);
2415 }
2416
2417 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2418 {
2419         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2420         u8 mso;
2421
2422         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2423                 return;
2424
2425         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2426                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2427                 return;
2428         }
2429
2430         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2431         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2432         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2433                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2434                 mso = 0;
2435         }
2436
2437         if (mso) {
2438                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2439                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2440                 if (!HAS_MSO(i915)) {
2441                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2442                         mso = 0;
2443                 }
2444         }
2445
2446         intel_dp->mso_link_count = mso;
2447         intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2448 }
2449
2450 static bool
2451 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2452 {
2453         struct drm_i915_private *dev_priv =
2454                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2455
2456         /* this function is meant to be called only once */
2457         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2458
2459         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2460                 return false;
2461
2462         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2463                          drm_dp_is_branch(intel_dp->dpcd));
2464
2465         /*
2466          * Read the eDP display control registers.
2467          *
2468          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2469          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2470          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2471          * method). The display control registers should read zero if they're
2472          * not supported anyway.
2473          */
2474         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2475                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2476                              sizeof(intel_dp->edp_dpcd))
2477                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2478                             (int)sizeof(intel_dp->edp_dpcd),
2479                             intel_dp->edp_dpcd);
2480
2481         /*
2482          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2483          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2484          */
2485         intel_psr_init_dpcd(intel_dp);
2486
2487         /* Read the eDP 1.4+ supported link rates. */
2488         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2489                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2490                 int i;
2491
2492                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2493                                 sink_rates, sizeof(sink_rates));
2494
2495                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2496                         int val = le16_to_cpu(sink_rates[i]);
2497
2498                         if (val == 0)
2499                                 break;
2500
2501                         /* Value read multiplied by 200kHz gives the per-lane
2502                          * link rate in kHz. The source rates are, however,
2503                          * stored in terms of LS_Clk kHz. The full conversion
2504                          * back to symbols is
2505                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2506                          */
2507                         intel_dp->sink_rates[i] = (val * 200) / 10;
2508                 }
2509                 intel_dp->num_sink_rates = i;
2510         }
2511
2512         /*
2513          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2514          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2515          */
2516         if (intel_dp->num_sink_rates)
2517                 intel_dp->use_rate_select = true;
2518         else
2519                 intel_dp_set_sink_rates(intel_dp);
2520
2521         intel_dp_set_common_rates(intel_dp);
2522
2523         /* Read the eDP DSC DPCD registers */
2524         if (DISPLAY_VER(dev_priv) >= 10)
2525                 intel_dp_get_dsc_sink_cap(intel_dp);
2526
2527         /*
2528          * If needed, program our source OUI so we can make various Intel-specific AUX services
2529          * available (such as HDR backlight controls)
2530          */
2531         intel_edp_init_source_oui(intel_dp, true);
2532
2533         intel_edp_mso_init(intel_dp);
2534
2535         return true;
2536 }
2537
2538 static bool
2539 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2540 {
2541         if (!intel_dp->attached_connector)
2542                 return false;
2543
2544         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2545                                           intel_dp->dpcd,
2546                                           &intel_dp->desc);
2547 }
2548
2549 static bool
2550 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2551 {
2552         int ret;
2553
2554         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2555                 return false;
2556
2557         /*
2558          * Don't clobber cached eDP rates. Also skip re-reading
2559          * the OUI/ID since we know it won't change.
2560          */
2561         if (!intel_dp_is_edp(intel_dp)) {
2562                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2563                                  drm_dp_is_branch(intel_dp->dpcd));
2564
2565                 intel_dp_set_sink_rates(intel_dp);
2566                 intel_dp_set_common_rates(intel_dp);
2567         }
2568
2569         if (intel_dp_has_sink_count(intel_dp)) {
2570                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2571                 if (ret < 0)
2572                         return false;
2573
2574                 /*
2575                  * Sink count can change between short pulse hpd hence
2576                  * a member variable in intel_dp will track any changes
2577                  * between short pulse interrupts.
2578                  */
2579                 intel_dp->sink_count = ret;
2580
2581                 /*
2582                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2583                  * a dongle is present but no display. Unless we require to know
2584                  * if a dongle is present or not, we don't need to update
2585                  * downstream port information. So, an early return here saves
2586                  * time from performing other operations which are not required.
2587                  */
2588                 if (!intel_dp->sink_count)
2589                         return false;
2590         }
2591
2592         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2593                                            intel_dp->downstream_ports) == 0;
2594 }
2595
2596 static bool
2597 intel_dp_can_mst(struct intel_dp *intel_dp)
2598 {
2599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2600
2601         return i915->params.enable_dp_mst &&
2602                 intel_dp->can_mst &&
2603                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2604 }
2605
2606 static void
2607 intel_dp_configure_mst(struct intel_dp *intel_dp)
2608 {
2609         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2610         struct intel_encoder *encoder =
2611                 &dp_to_dig_port(intel_dp)->base;
2612         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2613
2614         drm_dbg_kms(&i915->drm,
2615                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2616                     encoder->base.base.id, encoder->base.name,
2617                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
2618                     yesno(i915->params.enable_dp_mst));
2619
2620         if (!intel_dp->can_mst)
2621                 return;
2622
2623         intel_dp->is_mst = sink_can_mst &&
2624                 i915->params.enable_dp_mst;
2625
2626         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2627                                         intel_dp->is_mst);
2628 }
2629
2630 static bool
2631 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2632 {
2633         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2634                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
2635                 DP_DPRX_ESI_LEN;
2636 }
2637
2638 bool
2639 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2640                        const struct drm_connector_state *conn_state)
2641 {
2642         /*
2643          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2644          * of Color Encoding Format and Content Color Gamut], in order to
2645          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2646          */
2647         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2648                 return true;
2649
2650         switch (conn_state->colorspace) {
2651         case DRM_MODE_COLORIMETRY_SYCC_601:
2652         case DRM_MODE_COLORIMETRY_OPYCC_601:
2653         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2654         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2655         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2656                 return true;
2657         default:
2658                 break;
2659         }
2660
2661         return false;
2662 }
2663
2664 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2665                                      struct dp_sdp *sdp, size_t size)
2666 {
2667         size_t length = sizeof(struct dp_sdp);
2668
2669         if (size < length)
2670                 return -ENOSPC;
2671
2672         memset(sdp, 0, size);
2673
2674         /*
2675          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2676          * VSC SDP Header Bytes
2677          */
2678         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2679         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2680         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2681         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2682
2683         /*
2684          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2685          * per DP 1.4a spec.
2686          */
2687         if (vsc->revision != 0x5)
2688                 goto out;
2689
2690         /* VSC SDP Payload for DB16 through DB18 */
2691         /* Pixel Encoding and Colorimetry Formats  */
2692         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2693         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2694
2695         switch (vsc->bpc) {
2696         case 6:
2697                 /* 6bpc: 0x0 */
2698                 break;
2699         case 8:
2700                 sdp->db[17] = 0x1; /* DB17[3:0] */
2701                 break;
2702         case 10:
2703                 sdp->db[17] = 0x2;
2704                 break;
2705         case 12:
2706                 sdp->db[17] = 0x3;
2707                 break;
2708         case 16:
2709                 sdp->db[17] = 0x4;
2710                 break;
2711         default:
2712                 MISSING_CASE(vsc->bpc);
2713                 break;
2714         }
2715         /* Dynamic Range and Component Bit Depth */
2716         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2717                 sdp->db[17] |= 0x80;  /* DB17[7] */
2718
2719         /* Content Type */
2720         sdp->db[18] = vsc->content_type & 0x7;
2721
2722 out:
2723         return length;
2724 }
2725
2726 static ssize_t
2727 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2728                                          struct dp_sdp *sdp,
2729                                          size_t size)
2730 {
2731         size_t length = sizeof(struct dp_sdp);
2732         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2733         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2734         ssize_t len;
2735
2736         if (size < length)
2737                 return -ENOSPC;
2738
2739         memset(sdp, 0, size);
2740
2741         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2742         if (len < 0) {
2743                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2744                 return -ENOSPC;
2745         }
2746
2747         if (len != infoframe_size) {
2748                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2749                 return -ENOSPC;
2750         }
2751
2752         /*
2753          * Set up the infoframe sdp packet for HDR static metadata.
2754          * Prepare VSC Header for SU as per DP 1.4a spec,
2755          * Table 2-100 and Table 2-101
2756          */
2757
2758         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2759         sdp->sdp_header.HB0 = 0;
2760         /*
2761          * Packet Type 80h + Non-audio INFOFRAME Type value
2762          * HDMI_INFOFRAME_TYPE_DRM: 0x87
2763          * - 80h + Non-audio INFOFRAME Type value
2764          * - InfoFrame Type: 0x07
2765          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2766          */
2767         sdp->sdp_header.HB1 = drm_infoframe->type;
2768         /*
2769          * Least Significant Eight Bits of (Data Byte Count – 1)
2770          * infoframe_size - 1
2771          */
2772         sdp->sdp_header.HB2 = 0x1D;
2773         /* INFOFRAME SDP Version Number */
2774         sdp->sdp_header.HB3 = (0x13 << 2);
2775         /* CTA Header Byte 2 (INFOFRAME Version Number) */
2776         sdp->db[0] = drm_infoframe->version;
2777         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2778         sdp->db[1] = drm_infoframe->length;
2779         /*
2780          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2781          * HDMI_INFOFRAME_HEADER_SIZE
2782          */
2783         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2784         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2785                HDMI_DRM_INFOFRAME_SIZE);
2786
2787         /*
2788          * Size of DP infoframe sdp packet for HDR static metadata consists of
2789          * - DP SDP Header(struct dp_sdp_header): 4 bytes
2790          * - Two Data Blocks: 2 bytes
2791          *    CTA Header Byte2 (INFOFRAME Version Number)
2792          *    CTA Header Byte3 (Length of INFOFRAME)
2793          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2794          *
2795          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2796          * infoframe size. But GEN11+ has larger than that size, write_infoframe
2797          * will pad rest of the size.
2798          */
2799         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2800 }
2801
2802 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2803                                const struct intel_crtc_state *crtc_state,
2804                                unsigned int type)
2805 {
2806         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2807         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2808         struct dp_sdp sdp = {};
2809         ssize_t len;
2810
2811         if ((crtc_state->infoframes.enable &
2812              intel_hdmi_infoframe_enable(type)) == 0)
2813                 return;
2814
2815         switch (type) {
2816         case DP_SDP_VSC:
2817                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2818                                             sizeof(sdp));
2819                 break;
2820         case HDMI_PACKET_TYPE_GAMUT_METADATA:
2821                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2822                                                                &sdp, sizeof(sdp));
2823                 break;
2824         default:
2825                 MISSING_CASE(type);
2826                 return;
2827         }
2828
2829         if (drm_WARN_ON(&dev_priv->drm, len < 0))
2830                 return;
2831
2832         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2833 }
2834
2835 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2836                             const struct intel_crtc_state *crtc_state,
2837                             struct drm_dp_vsc_sdp *vsc)
2838 {
2839         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841         struct dp_sdp sdp = {};
2842         ssize_t len;
2843
2844         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2845
2846         if (drm_WARN_ON(&dev_priv->drm, len < 0))
2847                 return;
2848
2849         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2850                                         &sdp, len);
2851 }
2852
2853 void intel_dp_set_infoframes(struct intel_encoder *encoder,
2854                              bool enable,
2855                              const struct intel_crtc_state *crtc_state,
2856                              const struct drm_connector_state *conn_state)
2857 {
2858         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2859         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2860         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2861         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2862                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2863                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2864         u32 val = intel_de_read(dev_priv, reg);
2865
2866         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
2867         /* When PSR is enabled, this routine doesn't disable VSC DIP */
2868         if (intel_psr_enabled(intel_dp))
2869                 val &= ~dip_enable;
2870         else
2871                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
2872
2873         if (!enable) {
2874                 intel_de_write(dev_priv, reg, val);
2875                 intel_de_posting_read(dev_priv, reg);
2876                 return;
2877         }
2878
2879         intel_de_write(dev_priv, reg, val);
2880         intel_de_posting_read(dev_priv, reg);
2881
2882         /* When PSR is enabled, VSC SDP is handled by PSR routine */
2883         if (!intel_psr_enabled(intel_dp))
2884                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2885
2886         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2887 }
2888
2889 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2890                                    const void *buffer, size_t size)
2891 {
2892         const struct dp_sdp *sdp = buffer;
2893
2894         if (size < sizeof(struct dp_sdp))
2895                 return -EINVAL;
2896
2897         memset(vsc, 0, size);
2898
2899         if (sdp->sdp_header.HB0 != 0)
2900                 return -EINVAL;
2901
2902         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2903                 return -EINVAL;
2904
2905         vsc->sdp_type = sdp->sdp_header.HB1;
2906         vsc->revision = sdp->sdp_header.HB2;
2907         vsc->length = sdp->sdp_header.HB3;
2908
2909         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2910             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2911                 /*
2912                  * - HB2 = 0x2, HB3 = 0x8
2913                  *   VSC SDP supporting 3D stereo + PSR
2914                  * - HB2 = 0x4, HB3 = 0xe
2915                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2916                  *   first scan line of the SU region (applies to eDP v1.4b
2917                  *   and higher).
2918                  */
2919                 return 0;
2920         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2921                 /*
2922                  * - HB2 = 0x5, HB3 = 0x13
2923                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2924                  *   Format.
2925                  */
2926                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2927                 vsc->colorimetry = sdp->db[16] & 0xf;
2928                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2929
2930                 switch (sdp->db[17] & 0x7) {
2931                 case 0x0:
2932                         vsc->bpc = 6;
2933                         break;
2934                 case 0x1:
2935                         vsc->bpc = 8;
2936                         break;
2937                 case 0x2:
2938                         vsc->bpc = 10;
2939                         break;
2940                 case 0x3:
2941                         vsc->bpc = 12;
2942                         break;
2943                 case 0x4:
2944                         vsc->bpc = 16;
2945                         break;
2946                 default:
2947                         MISSING_CASE(sdp->db[17] & 0x7);
2948                         return -EINVAL;
2949                 }
2950
2951                 vsc->content_type = sdp->db[18] & 0x7;
2952         } else {
2953                 return -EINVAL;
2954         }
2955
2956         return 0;
2957 }
2958
2959 static int
2960 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2961                                            const void *buffer, size_t size)
2962 {
2963         int ret;
2964
2965         const struct dp_sdp *sdp = buffer;
2966
2967         if (size < sizeof(struct dp_sdp))
2968                 return -EINVAL;
2969
2970         if (sdp->sdp_header.HB0 != 0)
2971                 return -EINVAL;
2972
2973         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2974                 return -EINVAL;
2975
2976         /*
2977          * Least Significant Eight Bits of (Data Byte Count – 1)
2978          * 1Dh (i.e., Data Byte Count = 30 bytes).
2979          */
2980         if (sdp->sdp_header.HB2 != 0x1D)
2981                 return -EINVAL;
2982
2983         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2984         if ((sdp->sdp_header.HB3 & 0x3) != 0)
2985                 return -EINVAL;
2986
2987         /* INFOFRAME SDP Version Number */
2988         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2989                 return -EINVAL;
2990
2991         /* CTA Header Byte 2 (INFOFRAME Version Number) */
2992         if (sdp->db[0] != 1)
2993                 return -EINVAL;
2994
2995         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2996         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
2997                 return -EINVAL;
2998
2999         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3000                                              HDMI_DRM_INFOFRAME_SIZE);
3001
3002         return ret;
3003 }
3004
3005 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3006                                   struct intel_crtc_state *crtc_state,
3007                                   struct drm_dp_vsc_sdp *vsc)
3008 {
3009         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3010         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3011         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3012         unsigned int type = DP_SDP_VSC;
3013         struct dp_sdp sdp = {};
3014         int ret;
3015
3016         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3017         if (intel_psr_enabled(intel_dp))
3018                 return;
3019
3020         if ((crtc_state->infoframes.enable &
3021              intel_hdmi_infoframe_enable(type)) == 0)
3022                 return;
3023
3024         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3025
3026         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3027
3028         if (ret)
3029                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3030 }
3031
3032 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3033                                                      struct intel_crtc_state *crtc_state,
3034                                                      struct hdmi_drm_infoframe *drm_infoframe)
3035 {
3036         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3038         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3039         struct dp_sdp sdp = {};
3040         int ret;
3041
3042         if ((crtc_state->infoframes.enable &
3043             intel_hdmi_infoframe_enable(type)) == 0)
3044                 return;
3045
3046         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3047                                  sizeof(sdp));
3048
3049         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3050                                                          sizeof(sdp));
3051
3052         if (ret)
3053                 drm_dbg_kms(&dev_priv->drm,
3054                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3055 }
3056
3057 void intel_read_dp_sdp(struct intel_encoder *encoder,
3058                        struct intel_crtc_state *crtc_state,
3059                        unsigned int type)
3060 {
3061         if (encoder->type != INTEL_OUTPUT_DDI)
3062                 return;
3063
3064         switch (type) {
3065         case DP_SDP_VSC:
3066                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3067                                       &crtc_state->infoframes.vsc);
3068                 break;
3069         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3070                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3071                                                          &crtc_state->infoframes.drm.drm);
3072                 break;
3073         default:
3074                 MISSING_CASE(type);
3075                 break;
3076         }
3077 }
3078
3079 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3080 {
3081         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3082         int status = 0;
3083         int test_link_rate;
3084         u8 test_lane_count, test_link_bw;
3085         /* (DP CTS 1.2)
3086          * 4.3.1.11
3087          */
3088         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3089         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3090                                    &test_lane_count);
3091
3092         if (status <= 0) {
3093                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3094                 return DP_TEST_NAK;
3095         }
3096         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3097
3098         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3099                                    &test_link_bw);
3100         if (status <= 0) {
3101                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3102                 return DP_TEST_NAK;
3103         }
3104         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3105
3106         /* Validate the requested link rate and lane count */
3107         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3108                                         test_lane_count))
3109                 return DP_TEST_NAK;
3110
3111         intel_dp->compliance.test_lane_count = test_lane_count;
3112         intel_dp->compliance.test_link_rate = test_link_rate;
3113
3114         return DP_TEST_ACK;
3115 }
3116
3117 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3118 {
3119         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3120         u8 test_pattern;
3121         u8 test_misc;
3122         __be16 h_width, v_height;
3123         int status = 0;
3124
3125         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3126         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3127                                    &test_pattern);
3128         if (status <= 0) {
3129                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3130                 return DP_TEST_NAK;
3131         }
3132         if (test_pattern != DP_COLOR_RAMP)
3133                 return DP_TEST_NAK;
3134
3135         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3136                                   &h_width, 2);
3137         if (status <= 0) {
3138                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3139                 return DP_TEST_NAK;
3140         }
3141
3142         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3143                                   &v_height, 2);
3144         if (status <= 0) {
3145                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3146                 return DP_TEST_NAK;
3147         }
3148
3149         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3150                                    &test_misc);
3151         if (status <= 0) {
3152                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3153                 return DP_TEST_NAK;
3154         }
3155         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3156                 return DP_TEST_NAK;
3157         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3158                 return DP_TEST_NAK;
3159         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3160         case DP_TEST_BIT_DEPTH_6:
3161                 intel_dp->compliance.test_data.bpc = 6;
3162                 break;
3163         case DP_TEST_BIT_DEPTH_8:
3164                 intel_dp->compliance.test_data.bpc = 8;
3165                 break;
3166         default:
3167                 return DP_TEST_NAK;
3168         }
3169
3170         intel_dp->compliance.test_data.video_pattern = test_pattern;
3171         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3172         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3173         /* Set test active flag here so userspace doesn't interrupt things */
3174         intel_dp->compliance.test_active = true;
3175
3176         return DP_TEST_ACK;
3177 }
3178
3179 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3180 {
3181         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3182         u8 test_result = DP_TEST_ACK;
3183         struct intel_connector *intel_connector = intel_dp->attached_connector;
3184         struct drm_connector *connector = &intel_connector->base;
3185
3186         if (intel_connector->detect_edid == NULL ||
3187             connector->edid_corrupt ||
3188             intel_dp->aux.i2c_defer_count > 6) {
3189                 /* Check EDID read for NACKs, DEFERs and corruption
3190                  * (DP CTS 1.2 Core r1.1)
3191                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3192                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3193                  *    4.2.2.6 : EDID corruption detected
3194                  * Use failsafe mode for all cases
3195                  */
3196                 if (intel_dp->aux.i2c_nack_count > 0 ||
3197                         intel_dp->aux.i2c_defer_count > 0)
3198                         drm_dbg_kms(&i915->drm,
3199                                     "EDID read had %d NACKs, %d DEFERs\n",
3200                                     intel_dp->aux.i2c_nack_count,
3201                                     intel_dp->aux.i2c_defer_count);
3202                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3203         } else {
3204                 struct edid *block = intel_connector->detect_edid;
3205
3206                 /* We have to write the checksum
3207                  * of the last block read
3208                  */
3209                 block += intel_connector->detect_edid->extensions;
3210
3211                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3212                                        block->checksum) <= 0)
3213                         drm_dbg_kms(&i915->drm,
3214                                     "Failed to write EDID checksum\n");
3215
3216                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3217                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3218         }
3219
3220         /* Set test active flag here so userspace doesn't interrupt things */
3221         intel_dp->compliance.test_active = true;
3222
3223         return test_result;
3224 }
3225
3226 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3227                                         const struct intel_crtc_state *crtc_state)
3228 {
3229         struct drm_i915_private *dev_priv =
3230                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3231         struct drm_dp_phy_test_params *data =
3232                         &intel_dp->compliance.test_data.phytest;
3233         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3234         enum pipe pipe = crtc->pipe;
3235         u32 pattern_val;
3236
3237         switch (data->phy_pattern) {
3238         case DP_PHY_TEST_PATTERN_NONE:
3239                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3240                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3241                 break;
3242         case DP_PHY_TEST_PATTERN_D10_2:
3243                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3244                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3245                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3246                 break;
3247         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3248                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3249                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3250                                DDI_DP_COMP_CTL_ENABLE |
3251                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3252                 break;
3253         case DP_PHY_TEST_PATTERN_PRBS7:
3254                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3255                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3256                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3257                 break;
3258         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3259                 /*
3260                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3261                  * current firmware of DPR-100 could not set it, so hardcoding
3262                  * now for complaince test.
3263                  */
3264                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3265                 pattern_val = 0x3e0f83e0;
3266                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3267                 pattern_val = 0x0f83e0f8;
3268                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3269                 pattern_val = 0x0000f83e;
3270                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3271                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3272                                DDI_DP_COMP_CTL_ENABLE |
3273                                DDI_DP_COMP_CTL_CUSTOM80);
3274                 break;
3275         case DP_PHY_TEST_PATTERN_CP2520:
3276                 /*
3277                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3278                  * current firmware of DPR-100 could not set it, so hardcoding
3279                  * now for complaince test.
3280                  */
3281                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3282                 pattern_val = 0xFB;
3283                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3284                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3285                                pattern_val);
3286                 break;
3287         default:
3288                 WARN(1, "Invalid Phy Test Pattern\n");
3289         }
3290 }
3291
3292 static void
3293 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3294                                   const struct intel_crtc_state *crtc_state)
3295 {
3296         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3297         struct drm_device *dev = dig_port->base.base.dev;
3298         struct drm_i915_private *dev_priv = to_i915(dev);
3299         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3300         enum pipe pipe = crtc->pipe;
3301         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3302
3303         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3304                                                  TRANS_DDI_FUNC_CTL(pipe));
3305         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3306         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3307
3308         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3309                                       TGL_TRANS_DDI_PORT_MASK);
3310         trans_conf_value &= ~PIPECONF_ENABLE;
3311         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3312
3313         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3314         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3315                        trans_ddi_func_ctl_value);
3316         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3317 }
3318
3319 static void
3320 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3321                                  const struct intel_crtc_state *crtc_state)
3322 {
3323         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3324         struct drm_device *dev = dig_port->base.base.dev;
3325         struct drm_i915_private *dev_priv = to_i915(dev);
3326         enum port port = dig_port->base.port;
3327         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3328         enum pipe pipe = crtc->pipe;
3329         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3330
3331         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3332                                                  TRANS_DDI_FUNC_CTL(pipe));
3333         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3334         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3335
3336         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3337                                     TGL_TRANS_DDI_SELECT_PORT(port);
3338         trans_conf_value |= PIPECONF_ENABLE;
3339         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3340
3341         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3342         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3343         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3344                        trans_ddi_func_ctl_value);
3345 }
3346
3347 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3348                                          const struct intel_crtc_state *crtc_state)
3349 {
3350         struct drm_dp_phy_test_params *data =
3351                 &intel_dp->compliance.test_data.phytest;
3352         u8 link_status[DP_LINK_STATUS_SIZE];
3353
3354         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3355                                              link_status) < 0) {
3356                 DRM_DEBUG_KMS("failed to get link status\n");
3357                 return;
3358         }
3359
3360         /* retrieve vswing & pre-emphasis setting */
3361         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3362                                   link_status);
3363
3364         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3365
3366         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3367
3368         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3369
3370         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3371
3372         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3373                                     link_status[DP_DPCD_REV]);
3374 }
3375
3376 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3377 {
3378         struct drm_dp_phy_test_params *data =
3379                 &intel_dp->compliance.test_data.phytest;
3380
3381         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3382                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3383                 return DP_TEST_NAK;
3384         }
3385
3386         /* Set test active flag here so userspace doesn't interrupt things */
3387         intel_dp->compliance.test_active = true;
3388
3389         return DP_TEST_ACK;
3390 }
3391
3392 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3393 {
3394         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3395         u8 response = DP_TEST_NAK;
3396         u8 request = 0;
3397         int status;
3398
3399         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3400         if (status <= 0) {
3401                 drm_dbg_kms(&i915->drm,
3402                             "Could not read test request from sink\n");
3403                 goto update_status;
3404         }
3405
3406         switch (request) {
3407         case DP_TEST_LINK_TRAINING:
3408                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3409                 response = intel_dp_autotest_link_training(intel_dp);
3410                 break;
3411         case DP_TEST_LINK_VIDEO_PATTERN:
3412                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3413                 response = intel_dp_autotest_video_pattern(intel_dp);
3414                 break;
3415         case DP_TEST_LINK_EDID_READ:
3416                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3417                 response = intel_dp_autotest_edid(intel_dp);
3418                 break;
3419         case DP_TEST_LINK_PHY_TEST_PATTERN:
3420                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3421                 response = intel_dp_autotest_phy_pattern(intel_dp);
3422                 break;
3423         default:
3424                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3425                             request);
3426                 break;
3427         }
3428
3429         if (response & DP_TEST_ACK)
3430                 intel_dp->compliance.test_type = request;
3431
3432 update_status:
3433         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3434         if (status <= 0)
3435                 drm_dbg_kms(&i915->drm,
3436                             "Could not write test response to sink\n");
3437 }
3438
3439 static void
3440 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3441 {
3442                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3443
3444                 if (esi[1] & DP_CP_IRQ) {
3445                         intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3446                         *handled = true;
3447                 }
3448 }
3449
3450 /**
3451  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3452  * @intel_dp: Intel DP struct
3453  *
3454  * Read any pending MST interrupts, call MST core to handle these and ack the
3455  * interrupts. Check if the main and AUX link state is ok.
3456  *
3457  * Returns:
3458  * - %true if pending interrupts were serviced (or no interrupts were
3459  *   pending) w/o detecting an error condition.
3460  * - %false if an error condition - like AUX failure or a loss of link - is
3461  *   detected, which needs servicing from the hotplug work.
3462  */
3463 static bool
3464 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3465 {
3466         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3467         bool link_ok = true;
3468
3469         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3470
3471         for (;;) {
3472                 u8 esi[DP_DPRX_ESI_LEN] = {};
3473                 bool handled;
3474                 int retry;
3475
3476                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3477                         drm_dbg_kms(&i915->drm,
3478                                     "failed to get ESI - device may have failed\n");
3479                         link_ok = false;
3480
3481                         break;
3482                 }
3483
3484                 /* check link status - esi[10] = 0x200c */
3485                 if (intel_dp->active_mst_links > 0 && link_ok &&
3486                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3487                         drm_dbg_kms(&i915->drm,
3488                                     "channel EQ not ok, retraining\n");
3489                         link_ok = false;
3490                 }
3491
3492                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3493
3494                 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3495
3496                 if (!handled)
3497                         break;
3498
3499                 for (retry = 0; retry < 3; retry++) {
3500                         int wret;
3501
3502                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3503                                                  DP_SINK_COUNT_ESI+1,
3504                                                  &esi[1], 3);
3505                         if (wret == 3)
3506                                 break;
3507                 }
3508         }
3509
3510         return link_ok;
3511 }
3512
3513 static void
3514 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3515 {
3516         bool is_active;
3517         u8 buf = 0;
3518
3519         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3520         if (intel_dp->frl.is_trained && !is_active) {
3521                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3522                         return;
3523
3524                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3525                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3526                         return;
3527
3528                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3529
3530                 /* Restart FRL training or fall back to TMDS mode */
3531                 intel_dp_check_frl_training(intel_dp);
3532         }
3533 }
3534
3535 static bool
3536 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3537 {
3538         u8 link_status[DP_LINK_STATUS_SIZE];
3539
3540         if (!intel_dp->link_trained)
3541                 return false;
3542
3543         /*
3544          * While PSR source HW is enabled, it will control main-link sending
3545          * frames, enabling and disabling it so trying to do a retrain will fail
3546          * as the link would or not be on or it could mix training patterns
3547          * and frame data at the same time causing retrain to fail.
3548          * Also when exiting PSR, HW will retrain the link anyways fixing
3549          * any link status error.
3550          */
3551         if (intel_psr_enabled(intel_dp))
3552                 return false;
3553
3554         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3555                                              link_status) < 0)
3556                 return false;
3557
3558         /*
3559          * Validate the cached values of intel_dp->link_rate and
3560          * intel_dp->lane_count before attempting to retrain.
3561          *
3562          * FIXME would be nice to user the crtc state here, but since
3563          * we need to call this from the short HPD handler that seems
3564          * a bit hard.
3565          */
3566         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3567                                         intel_dp->lane_count))
3568                 return false;
3569
3570         /* Retrain if Channel EQ or CR not ok */
3571         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3572 }
3573
3574 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3575                                    const struct drm_connector_state *conn_state)
3576 {
3577         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3578         struct intel_encoder *encoder;
3579         enum pipe pipe;
3580
3581         if (!conn_state->best_encoder)
3582                 return false;
3583
3584         /* SST */
3585         encoder = &dp_to_dig_port(intel_dp)->base;
3586         if (conn_state->best_encoder == &encoder->base)
3587                 return true;
3588
3589         /* MST */
3590         for_each_pipe(i915, pipe) {
3591                 encoder = &intel_dp->mst_encoders[pipe]->base;
3592                 if (conn_state->best_encoder == &encoder->base)
3593                         return true;
3594         }
3595
3596         return false;
3597 }
3598
3599 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3600                                       struct drm_modeset_acquire_ctx *ctx,
3601                                       u32 *crtc_mask)
3602 {
3603         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3604         struct drm_connector_list_iter conn_iter;
3605         struct intel_connector *connector;
3606         int ret = 0;
3607
3608         *crtc_mask = 0;
3609
3610         if (!intel_dp_needs_link_retrain(intel_dp))
3611                 return 0;
3612
3613         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3614         for_each_intel_connector_iter(connector, &conn_iter) {
3615                 struct drm_connector_state *conn_state =
3616                         connector->base.state;
3617                 struct intel_crtc_state *crtc_state;
3618                 struct intel_crtc *crtc;
3619
3620                 if (!intel_dp_has_connector(intel_dp, conn_state))
3621                         continue;
3622
3623                 crtc = to_intel_crtc(conn_state->crtc);
3624                 if (!crtc)
3625                         continue;
3626
3627                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3628                 if (ret)
3629                         break;
3630
3631                 crtc_state = to_intel_crtc_state(crtc->base.state);
3632
3633                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3634
3635                 if (!crtc_state->hw.active)
3636                         continue;
3637
3638                 if (conn_state->commit &&
3639                     !try_wait_for_completion(&conn_state->commit->hw_done))
3640                         continue;
3641
3642                 *crtc_mask |= drm_crtc_mask(&crtc->base);
3643         }
3644         drm_connector_list_iter_end(&conn_iter);
3645
3646         if (!intel_dp_needs_link_retrain(intel_dp))
3647                 *crtc_mask = 0;
3648
3649         return ret;
3650 }
3651
3652 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3653 {
3654         struct intel_connector *connector = intel_dp->attached_connector;
3655
3656         return connector->base.status == connector_status_connected ||
3657                 intel_dp->is_mst;
3658 }
3659
3660 int intel_dp_retrain_link(struct intel_encoder *encoder,
3661                           struct drm_modeset_acquire_ctx *ctx)
3662 {
3663         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3664         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3665         struct intel_crtc *crtc;
3666         u32 crtc_mask;
3667         int ret;
3668
3669         if (!intel_dp_is_connected(intel_dp))
3670                 return 0;
3671
3672         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3673                                ctx);
3674         if (ret)
3675                 return ret;
3676
3677         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3678         if (ret)
3679                 return ret;
3680
3681         if (crtc_mask == 0)
3682                 return 0;
3683
3684         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3685                     encoder->base.base.id, encoder->base.name);
3686
3687         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3688                 const struct intel_crtc_state *crtc_state =
3689                         to_intel_crtc_state(crtc->base.state);
3690
3691                 /* Suppress underruns caused by re-training */
3692                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3693                 if (crtc_state->has_pch_encoder)
3694                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3695                                                               intel_crtc_pch_transcoder(crtc), false);
3696         }
3697
3698         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3699                 const struct intel_crtc_state *crtc_state =
3700                         to_intel_crtc_state(crtc->base.state);
3701
3702                 /* retrain on the MST master transcoder */
3703                 if (DISPLAY_VER(dev_priv) >= 12 &&
3704                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3705                     !intel_dp_mst_is_master_trans(crtc_state))
3706                         continue;
3707
3708                 intel_dp_check_frl_training(intel_dp);
3709                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3710                 intel_dp_start_link_train(intel_dp, crtc_state);
3711                 intel_dp_stop_link_train(intel_dp, crtc_state);
3712                 break;
3713         }
3714
3715         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3716                 const struct intel_crtc_state *crtc_state =
3717                         to_intel_crtc_state(crtc->base.state);
3718
3719                 /* Keep underrun reporting disabled until things are stable */
3720                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3721
3722                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3723                 if (crtc_state->has_pch_encoder)
3724                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3725                                                               intel_crtc_pch_transcoder(crtc), true);
3726         }
3727
3728         return 0;
3729 }
3730
3731 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3732                                   struct drm_modeset_acquire_ctx *ctx,
3733                                   u32 *crtc_mask)
3734 {
3735         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3736         struct drm_connector_list_iter conn_iter;
3737         struct intel_connector *connector;
3738         int ret = 0;
3739
3740         *crtc_mask = 0;
3741
3742         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3743         for_each_intel_connector_iter(connector, &conn_iter) {
3744                 struct drm_connector_state *conn_state =
3745                         connector->base.state;
3746                 struct intel_crtc_state *crtc_state;
3747                 struct intel_crtc *crtc;
3748
3749                 if (!intel_dp_has_connector(intel_dp, conn_state))
3750                         continue;
3751
3752                 crtc = to_intel_crtc(conn_state->crtc);
3753                 if (!crtc)
3754                         continue;
3755
3756                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3757                 if (ret)
3758                         break;
3759
3760                 crtc_state = to_intel_crtc_state(crtc->base.state);
3761
3762                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3763
3764                 if (!crtc_state->hw.active)
3765                         continue;
3766
3767                 if (conn_state->commit &&
3768                     !try_wait_for_completion(&conn_state->commit->hw_done))
3769                         continue;
3770
3771                 *crtc_mask |= drm_crtc_mask(&crtc->base);
3772         }
3773         drm_connector_list_iter_end(&conn_iter);
3774
3775         return ret;
3776 }
3777
3778 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3779                                 struct drm_modeset_acquire_ctx *ctx)
3780 {
3781         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3782         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3783         struct intel_crtc *crtc;
3784         u32 crtc_mask;
3785         int ret;
3786
3787         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3788                                ctx);
3789         if (ret)
3790                 return ret;
3791
3792         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3793         if (ret)
3794                 return ret;
3795
3796         if (crtc_mask == 0)
3797                 return 0;
3798
3799         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3800                     encoder->base.base.id, encoder->base.name);
3801
3802         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3803                 const struct intel_crtc_state *crtc_state =
3804                         to_intel_crtc_state(crtc->base.state);
3805
3806                 /* test on the MST master transcoder */
3807                 if (DISPLAY_VER(dev_priv) >= 12 &&
3808                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3809                     !intel_dp_mst_is_master_trans(crtc_state))
3810                         continue;
3811
3812                 intel_dp_process_phy_request(intel_dp, crtc_state);
3813                 break;
3814         }
3815
3816         return 0;
3817 }
3818
3819 void intel_dp_phy_test(struct intel_encoder *encoder)
3820 {
3821         struct drm_modeset_acquire_ctx ctx;
3822         int ret;
3823
3824         drm_modeset_acquire_init(&ctx, 0);
3825
3826         for (;;) {
3827                 ret = intel_dp_do_phy_test(encoder, &ctx);
3828
3829                 if (ret == -EDEADLK) {
3830                         drm_modeset_backoff(&ctx);
3831                         continue;
3832                 }
3833
3834                 break;
3835         }
3836
3837         drm_modeset_drop_locks(&ctx);
3838         drm_modeset_acquire_fini(&ctx);
3839         drm_WARN(encoder->base.dev, ret,
3840                  "Acquiring modeset locks failed with %i\n", ret);
3841 }
3842
3843 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3844 {
3845         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3846         u8 val;
3847
3848         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3849                 return;
3850
3851         if (drm_dp_dpcd_readb(&intel_dp->aux,
3852                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3853                 return;
3854
3855         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3856
3857         if (val & DP_AUTOMATED_TEST_REQUEST)
3858                 intel_dp_handle_test_request(intel_dp);
3859
3860         if (val & DP_CP_IRQ)
3861                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3862
3863         if (val & DP_SINK_SPECIFIC_IRQ)
3864                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3865 }
3866
3867 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3868 {
3869         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3870         u8 val;
3871
3872         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3873                 return;
3874
3875         if (drm_dp_dpcd_readb(&intel_dp->aux,
3876                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
3877                 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
3878                 return;
3879         }
3880
3881         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3882                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
3883                 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
3884                 return;
3885         }
3886
3887         if (val & HDMI_LINK_STATUS_CHANGED)
3888                 intel_dp_handle_hdmi_link_status_change(intel_dp);
3889 }
3890
3891 /*
3892  * According to DP spec
3893  * 5.1.2:
3894  *  1. Read DPCD
3895  *  2. Configure link according to Receiver Capabilities
3896  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3897  *  4. Check link status on receipt of hot-plug interrupt
3898  *
3899  * intel_dp_short_pulse -  handles short pulse interrupts
3900  * when full detection is not required.
3901  * Returns %true if short pulse is handled and full detection
3902  * is NOT required and %false otherwise.
3903  */
3904 static bool
3905 intel_dp_short_pulse(struct intel_dp *intel_dp)
3906 {
3907         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3908         u8 old_sink_count = intel_dp->sink_count;
3909         bool ret;
3910
3911         /*
3912          * Clearing compliance test variables to allow capturing
3913          * of values for next automated test request.
3914          */
3915         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3916
3917         /*
3918          * Now read the DPCD to see if it's actually running
3919          * If the current value of sink count doesn't match with
3920          * the value that was stored earlier or dpcd read failed
3921          * we need to do full detection
3922          */
3923         ret = intel_dp_get_dpcd(intel_dp);
3924
3925         if ((old_sink_count != intel_dp->sink_count) || !ret) {
3926                 /* No need to proceed if we are going to do full detect */
3927                 return false;
3928         }
3929
3930         intel_dp_check_device_service_irq(intel_dp);
3931         intel_dp_check_link_service_irq(intel_dp);
3932
3933         /* Handle CEC interrupts, if any */
3934         drm_dp_cec_irq(&intel_dp->aux);
3935
3936         /* defer to the hotplug work for link retraining if needed */
3937         if (intel_dp_needs_link_retrain(intel_dp))
3938                 return false;
3939
3940         intel_psr_short_pulse(intel_dp);
3941
3942         switch (intel_dp->compliance.test_type) {
3943         case DP_TEST_LINK_TRAINING:
3944                 drm_dbg_kms(&dev_priv->drm,
3945                             "Link Training Compliance Test requested\n");
3946                 /* Send a Hotplug Uevent to userspace to start modeset */
3947                 drm_kms_helper_hotplug_event(&dev_priv->drm);
3948                 break;
3949         case DP_TEST_LINK_PHY_TEST_PATTERN:
3950                 drm_dbg_kms(&dev_priv->drm,
3951                             "PHY test pattern Compliance Test requested\n");
3952                 /*
3953                  * Schedule long hpd to do the test
3954                  *
3955                  * FIXME get rid of the ad-hoc phy test modeset code
3956                  * and properly incorporate it into the normal modeset.
3957                  */
3958                 return false;
3959         }
3960
3961         return true;
3962 }
3963
3964 /* XXX this is probably wrong for multiple downstream ports */
3965 static enum drm_connector_status
3966 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3967 {
3968         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3969         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3970         u8 *dpcd = intel_dp->dpcd;
3971         u8 type;
3972
3973         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3974                 return connector_status_connected;
3975
3976         lspcon_resume(dig_port);
3977
3978         if (!intel_dp_get_dpcd(intel_dp))
3979                 return connector_status_disconnected;
3980
3981         /* if there's no downstream port, we're done */
3982         if (!drm_dp_is_branch(dpcd))
3983                 return connector_status_connected;
3984
3985         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3986         if (intel_dp_has_sink_count(intel_dp) &&
3987             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3988                 return intel_dp->sink_count ?
3989                 connector_status_connected : connector_status_disconnected;
3990         }
3991
3992         if (intel_dp_can_mst(intel_dp))
3993                 return connector_status_connected;
3994
3995         /* If no HPD, poke DDC gently */
3996         if (drm_probe_ddc(&intel_dp->aux.ddc))
3997                 return connector_status_connected;
3998
3999         /* Well we tried, say unknown for unreliable port types */
4000         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4001                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4002                 if (type == DP_DS_PORT_TYPE_VGA ||
4003                     type == DP_DS_PORT_TYPE_NON_EDID)
4004                         return connector_status_unknown;
4005         } else {
4006                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4007                         DP_DWN_STRM_PORT_TYPE_MASK;
4008                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4009                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4010                         return connector_status_unknown;
4011         }
4012
4013         /* Anything else is out of spec, warn and ignore */
4014         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4015         return connector_status_disconnected;
4016 }
4017
4018 static enum drm_connector_status
4019 edp_detect(struct intel_dp *intel_dp)
4020 {
4021         return connector_status_connected;
4022 }
4023
4024 /*
4025  * intel_digital_port_connected - is the specified port connected?
4026  * @encoder: intel_encoder
4027  *
4028  * In cases where there's a connector physically connected but it can't be used
4029  * by our hardware we also return false, since the rest of the driver should
4030  * pretty much treat the port as disconnected. This is relevant for type-C
4031  * (starting on ICL) where there's ownership involved.
4032  *
4033  * Return %true if port is connected, %false otherwise.
4034  */
4035 bool intel_digital_port_connected(struct intel_encoder *encoder)
4036 {
4037         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4038         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4039         bool is_connected = false;
4040         intel_wakeref_t wakeref;
4041
4042         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4043                 is_connected = dig_port->connected(encoder);
4044
4045         return is_connected;
4046 }
4047
4048 static struct edid *
4049 intel_dp_get_edid(struct intel_dp *intel_dp)
4050 {
4051         struct intel_connector *intel_connector = intel_dp->attached_connector;
4052
4053         /* use cached edid if we have one */
4054         if (intel_connector->edid) {
4055                 /* invalid edid */
4056                 if (IS_ERR(intel_connector->edid))
4057                         return NULL;
4058
4059                 return drm_edid_duplicate(intel_connector->edid);
4060         } else
4061                 return drm_get_edid(&intel_connector->base,
4062                                     &intel_dp->aux.ddc);
4063 }
4064
4065 static void
4066 intel_dp_update_dfp(struct intel_dp *intel_dp,
4067                     const struct edid *edid)
4068 {
4069         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4070         struct intel_connector *connector = intel_dp->attached_connector;
4071
4072         intel_dp->dfp.max_bpc =
4073                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4074                                           intel_dp->downstream_ports, edid);
4075
4076         intel_dp->dfp.max_dotclock =
4077                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4078                                                intel_dp->downstream_ports);
4079
4080         intel_dp->dfp.min_tmds_clock =
4081                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4082                                                  intel_dp->downstream_ports,
4083                                                  edid);
4084         intel_dp->dfp.max_tmds_clock =
4085                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4086                                                  intel_dp->downstream_ports,
4087                                                  edid);
4088
4089         intel_dp->dfp.pcon_max_frl_bw =
4090                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4091                                            intel_dp->downstream_ports);
4092
4093         drm_dbg_kms(&i915->drm,
4094                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4095                     connector->base.base.id, connector->base.name,
4096                     intel_dp->dfp.max_bpc,
4097                     intel_dp->dfp.max_dotclock,
4098                     intel_dp->dfp.min_tmds_clock,
4099                     intel_dp->dfp.max_tmds_clock,
4100                     intel_dp->dfp.pcon_max_frl_bw);
4101
4102         intel_dp_get_pcon_dsc_cap(intel_dp);
4103 }
4104
4105 static void
4106 intel_dp_update_420(struct intel_dp *intel_dp)
4107 {
4108         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4109         struct intel_connector *connector = intel_dp->attached_connector;
4110         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4111
4112         /* No YCbCr output support on gmch platforms */
4113         if (HAS_GMCH(i915))
4114                 return;
4115
4116         /*
4117          * ILK doesn't seem capable of DP YCbCr output. The
4118          * displayed image is severly corrupted. SNB+ is fine.
4119          */
4120         if (IS_IRONLAKE(i915))
4121                 return;
4122
4123         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4124         ycbcr_420_passthrough =
4125                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4126                                                   intel_dp->downstream_ports);
4127         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4128         ycbcr_444_to_420 =
4129                 dp_to_dig_port(intel_dp)->lspcon.active ||
4130                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4131                                                         intel_dp->downstream_ports);
4132         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4133                                                                  intel_dp->downstream_ports,
4134                                                                  DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4135                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4136                                                                  DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4137
4138         if (DISPLAY_VER(i915) >= 11) {
4139                 /* Let PCON convert from RGB->YCbCr if possible */
4140                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4141                         intel_dp->dfp.rgb_to_ycbcr = true;
4142                         intel_dp->dfp.ycbcr_444_to_420 = true;
4143                         connector->base.ycbcr_420_allowed = true;
4144                 } else {
4145                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4146                         intel_dp->dfp.ycbcr_444_to_420 =
4147                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4148
4149                         connector->base.ycbcr_420_allowed =
4150                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4151                 }
4152         } else {
4153                 /* 4:4:4->4:2:0 conversion is the only way */
4154                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4155
4156                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4157         }
4158
4159         drm_dbg_kms(&i915->drm,
4160                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4161                     connector->base.base.id, connector->base.name,
4162                     yesno(intel_dp->dfp.rgb_to_ycbcr),
4163                     yesno(connector->base.ycbcr_420_allowed),
4164                     yesno(intel_dp->dfp.ycbcr_444_to_420));
4165 }
4166
4167 static void
4168 intel_dp_set_edid(struct intel_dp *intel_dp)
4169 {
4170         struct intel_connector *connector = intel_dp->attached_connector;
4171         struct edid *edid;
4172
4173         intel_dp_unset_edid(intel_dp);
4174         edid = intel_dp_get_edid(intel_dp);
4175         connector->detect_edid = edid;
4176
4177         intel_dp_update_dfp(intel_dp, edid);
4178         intel_dp_update_420(intel_dp);
4179
4180         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4181                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4182                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4183         }
4184
4185         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4186 }
4187
4188 static void
4189 intel_dp_unset_edid(struct intel_dp *intel_dp)
4190 {
4191         struct intel_connector *connector = intel_dp->attached_connector;
4192
4193         drm_dp_cec_unset_edid(&intel_dp->aux);
4194         kfree(connector->detect_edid);
4195         connector->detect_edid = NULL;
4196
4197         intel_dp->has_hdmi_sink = false;
4198         intel_dp->has_audio = false;
4199
4200         intel_dp->dfp.max_bpc = 0;
4201         intel_dp->dfp.max_dotclock = 0;
4202         intel_dp->dfp.min_tmds_clock = 0;
4203         intel_dp->dfp.max_tmds_clock = 0;
4204
4205         intel_dp->dfp.pcon_max_frl_bw = 0;
4206
4207         intel_dp->dfp.ycbcr_444_to_420 = false;
4208         connector->base.ycbcr_420_allowed = false;
4209 }
4210
4211 static int
4212 intel_dp_detect(struct drm_connector *connector,
4213                 struct drm_modeset_acquire_ctx *ctx,
4214                 bool force)
4215 {
4216         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4217         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4218         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4219         struct intel_encoder *encoder = &dig_port->base;
4220         enum drm_connector_status status;
4221
4222         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4223                     connector->base.id, connector->name);
4224         drm_WARN_ON(&dev_priv->drm,
4225                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4226
4227         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4228                 return connector_status_disconnected;
4229
4230         /* Can't disconnect eDP */
4231         if (intel_dp_is_edp(intel_dp))
4232                 status = edp_detect(intel_dp);
4233         else if (intel_digital_port_connected(encoder))
4234                 status = intel_dp_detect_dpcd(intel_dp);
4235         else
4236                 status = connector_status_disconnected;
4237
4238         if (status == connector_status_disconnected) {
4239                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4240                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4241
4242                 if (intel_dp->is_mst) {
4243                         drm_dbg_kms(&dev_priv->drm,
4244                                     "MST device may have disappeared %d vs %d\n",
4245                                     intel_dp->is_mst,
4246                                     intel_dp->mst_mgr.mst_state);
4247                         intel_dp->is_mst = false;
4248                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4249                                                         intel_dp->is_mst);
4250                 }
4251
4252                 goto out;
4253         }
4254
4255         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4256         if (DISPLAY_VER(dev_priv) >= 11)
4257                 intel_dp_get_dsc_sink_cap(intel_dp);
4258
4259         intel_dp_configure_mst(intel_dp);
4260
4261         /*
4262          * TODO: Reset link params when switching to MST mode, until MST
4263          * supports link training fallback params.
4264          */
4265         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4266                 /* Initial max link lane count */
4267                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4268
4269                 /* Initial max link rate */
4270                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4271
4272                 intel_dp->reset_link_params = false;
4273         }
4274
4275         intel_dp_print_rates(intel_dp);
4276
4277         if (intel_dp->is_mst) {
4278                 /*
4279                  * If we are in MST mode then this connector
4280                  * won't appear connected or have anything
4281                  * with EDID on it
4282                  */
4283                 status = connector_status_disconnected;
4284                 goto out;
4285         }
4286
4287         /*
4288          * Some external monitors do not signal loss of link synchronization
4289          * with an IRQ_HPD, so force a link status check.
4290          */
4291         if (!intel_dp_is_edp(intel_dp)) {
4292                 int ret;
4293
4294                 ret = intel_dp_retrain_link(encoder, ctx);
4295                 if (ret)
4296                         return ret;
4297         }
4298
4299         /*
4300          * Clearing NACK and defer counts to get their exact values
4301          * while reading EDID which are required by Compliance tests
4302          * 4.2.2.4 and 4.2.2.5
4303          */
4304         intel_dp->aux.i2c_nack_count = 0;
4305         intel_dp->aux.i2c_defer_count = 0;
4306
4307         intel_dp_set_edid(intel_dp);
4308         if (intel_dp_is_edp(intel_dp) ||
4309             to_intel_connector(connector)->detect_edid)
4310                 status = connector_status_connected;
4311
4312         intel_dp_check_device_service_irq(intel_dp);
4313
4314 out:
4315         if (status != connector_status_connected && !intel_dp->is_mst)
4316                 intel_dp_unset_edid(intel_dp);
4317
4318         /*
4319          * Make sure the refs for power wells enabled during detect are
4320          * dropped to avoid a new detect cycle triggered by HPD polling.
4321          */
4322         intel_display_power_flush_work(dev_priv);
4323
4324         if (!intel_dp_is_edp(intel_dp))
4325                 drm_dp_set_subconnector_property(connector,
4326                                                  status,
4327                                                  intel_dp->dpcd,
4328                                                  intel_dp->downstream_ports);
4329         return status;
4330 }
4331
4332 static void
4333 intel_dp_force(struct drm_connector *connector)
4334 {
4335         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4336         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4337         struct intel_encoder *intel_encoder = &dig_port->base;
4338         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4339         enum intel_display_power_domain aux_domain =
4340                 intel_aux_power_domain(dig_port);
4341         intel_wakeref_t wakeref;
4342
4343         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4344                     connector->base.id, connector->name);
4345         intel_dp_unset_edid(intel_dp);
4346
4347         if (connector->status != connector_status_connected)
4348                 return;
4349
4350         wakeref = intel_display_power_get(dev_priv, aux_domain);
4351
4352         intel_dp_set_edid(intel_dp);
4353
4354         intel_display_power_put(dev_priv, aux_domain, wakeref);
4355 }
4356
4357 static int intel_dp_get_modes(struct drm_connector *connector)
4358 {
4359         struct intel_connector *intel_connector = to_intel_connector(connector);
4360         struct edid *edid;
4361         int num_modes = 0;
4362
4363         edid = intel_connector->detect_edid;
4364         if (edid) {
4365                 num_modes = intel_connector_update_modes(connector, edid);
4366
4367                 if (intel_vrr_is_capable(connector))
4368                         drm_connector_set_vrr_capable_property(connector,
4369                                                                true);
4370         }
4371
4372         /* Also add fixed mode, which may or may not be present in EDID */
4373         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4374             intel_connector->panel.fixed_mode) {
4375                 struct drm_display_mode *mode;
4376
4377                 mode = drm_mode_duplicate(connector->dev,
4378                                           intel_connector->panel.fixed_mode);
4379                 if (mode) {
4380                         drm_mode_probed_add(connector, mode);
4381                         num_modes++;
4382                 }
4383         }
4384
4385         if (num_modes)
4386                 return num_modes;
4387
4388         if (!edid) {
4389                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4390                 struct drm_display_mode *mode;
4391
4392                 mode = drm_dp_downstream_mode(connector->dev,
4393                                               intel_dp->dpcd,
4394                                               intel_dp->downstream_ports);
4395                 if (mode) {
4396                         drm_mode_probed_add(connector, mode);
4397                         num_modes++;
4398                 }
4399         }
4400
4401         return num_modes;
4402 }
4403
4404 static int
4405 intel_dp_connector_register(struct drm_connector *connector)
4406 {
4407         struct drm_i915_private *i915 = to_i915(connector->dev);
4408         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4409         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4410         struct intel_lspcon *lspcon = &dig_port->lspcon;
4411         int ret;
4412
4413         ret = intel_connector_register(connector);
4414         if (ret)
4415                 return ret;
4416
4417         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4418                     intel_dp->aux.name, connector->kdev->kobj.name);
4419
4420         intel_dp->aux.dev = connector->kdev;
4421         ret = drm_dp_aux_register(&intel_dp->aux);
4422         if (!ret)
4423                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4424
4425         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4426                 return ret;
4427
4428         /*
4429          * ToDo: Clean this up to handle lspcon init and resume more
4430          * efficiently and streamlined.
4431          */
4432         if (lspcon_init(dig_port)) {
4433                 lspcon_detect_hdr_capability(lspcon);
4434                 if (lspcon->hdr_supported)
4435                         drm_object_attach_property(&connector->base,
4436                                                    connector->dev->mode_config.hdr_output_metadata_property,
4437                                                    0);
4438         }
4439
4440         return ret;
4441 }
4442
4443 static void
4444 intel_dp_connector_unregister(struct drm_connector *connector)
4445 {
4446         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4447
4448         drm_dp_cec_unregister_connector(&intel_dp->aux);
4449         drm_dp_aux_unregister(&intel_dp->aux);
4450         intel_connector_unregister(connector);
4451 }
4452
4453 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4454 {
4455         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4456         struct intel_dp *intel_dp = &dig_port->dp;
4457
4458         intel_dp_mst_encoder_cleanup(dig_port);
4459
4460         intel_pps_vdd_off_sync(intel_dp);
4461
4462         intel_dp_aux_fini(intel_dp);
4463 }
4464
4465 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4466 {
4467         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4468
4469         intel_pps_vdd_off_sync(intel_dp);
4470 }
4471
4472 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4473 {
4474         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4475
4476         intel_pps_wait_power_cycle(intel_dp);
4477 }
4478
4479 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4480                                     int tile_group_id)
4481 {
4482         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4483         struct drm_connector_list_iter conn_iter;
4484         struct drm_connector *connector;
4485         int ret = 0;
4486
4487         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4488         drm_for_each_connector_iter(connector, &conn_iter) {
4489                 struct drm_connector_state *conn_state;
4490                 struct intel_crtc_state *crtc_state;
4491                 struct intel_crtc *crtc;
4492
4493                 if (!connector->has_tile ||
4494                     connector->tile_group->id != tile_group_id)
4495                         continue;
4496
4497                 conn_state = drm_atomic_get_connector_state(&state->base,
4498                                                             connector);
4499                 if (IS_ERR(conn_state)) {
4500                         ret = PTR_ERR(conn_state);
4501                         break;
4502                 }
4503
4504                 crtc = to_intel_crtc(conn_state->crtc);
4505
4506                 if (!crtc)
4507                         continue;
4508
4509                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4510                 crtc_state->uapi.mode_changed = true;
4511
4512                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4513                 if (ret)
4514                         break;
4515         }
4516         drm_connector_list_iter_end(&conn_iter);
4517
4518         return ret;
4519 }
4520
4521 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4522 {
4523         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4524         struct intel_crtc *crtc;
4525
4526         if (transcoders == 0)
4527                 return 0;
4528
4529         for_each_intel_crtc(&dev_priv->drm, crtc) {
4530                 struct intel_crtc_state *crtc_state;
4531                 int ret;
4532
4533                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4534                 if (IS_ERR(crtc_state))
4535                         return PTR_ERR(crtc_state);
4536
4537                 if (!crtc_state->hw.enable)
4538                         continue;
4539
4540                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4541                         continue;
4542
4543                 crtc_state->uapi.mode_changed = true;
4544
4545                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4546                 if (ret)
4547                         return ret;
4548
4549                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4550                 if (ret)
4551                         return ret;
4552
4553                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4554         }
4555
4556         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4557
4558         return 0;
4559 }
4560
4561 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4562                                       struct drm_connector *connector)
4563 {
4564         const struct drm_connector_state *old_conn_state =
4565                 drm_atomic_get_old_connector_state(&state->base, connector);
4566         const struct intel_crtc_state *old_crtc_state;
4567         struct intel_crtc *crtc;
4568         u8 transcoders;
4569
4570         crtc = to_intel_crtc(old_conn_state->crtc);
4571         if (!crtc)
4572                 return 0;
4573
4574         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4575
4576         if (!old_crtc_state->hw.active)
4577                 return 0;
4578
4579         transcoders = old_crtc_state->sync_mode_slaves_mask;
4580         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4581                 transcoders |= BIT(old_crtc_state->master_transcoder);
4582
4583         return intel_modeset_affected_transcoders(state,
4584                                                   transcoders);
4585 }
4586
4587 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4588                                            struct drm_atomic_state *_state)
4589 {
4590         struct drm_i915_private *dev_priv = to_i915(conn->dev);
4591         struct intel_atomic_state *state = to_intel_atomic_state(_state);
4592         int ret;
4593
4594         ret = intel_digital_connector_atomic_check(conn, &state->base);
4595         if (ret)
4596                 return ret;
4597
4598         /*
4599          * We don't enable port sync on BDW due to missing w/as and
4600          * due to not having adjusted the modeset sequence appropriately.
4601          */
4602         if (DISPLAY_VER(dev_priv) < 9)
4603                 return 0;
4604
4605         if (!intel_connector_needs_modeset(state, conn))
4606                 return 0;
4607
4608         if (conn->has_tile) {
4609                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4610                 if (ret)
4611                         return ret;
4612         }
4613
4614         return intel_modeset_synced_crtcs(state, conn);
4615 }
4616
4617 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4618         .force = intel_dp_force,
4619         .fill_modes = drm_helper_probe_single_connector_modes,
4620         .atomic_get_property = intel_digital_connector_atomic_get_property,
4621         .atomic_set_property = intel_digital_connector_atomic_set_property,
4622         .late_register = intel_dp_connector_register,
4623         .early_unregister = intel_dp_connector_unregister,
4624         .destroy = intel_connector_destroy,
4625         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4626         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4627 };
4628
4629 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4630         .detect_ctx = intel_dp_detect,
4631         .get_modes = intel_dp_get_modes,
4632         .mode_valid = intel_dp_mode_valid,
4633         .atomic_check = intel_dp_connector_atomic_check,
4634 };
4635
4636 enum irqreturn
4637 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4638 {
4639         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4640         struct intel_dp *intel_dp = &dig_port->dp;
4641
4642         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4643             (long_hpd || !intel_pps_have_power(intel_dp))) {
4644                 /*
4645                  * vdd off can generate a long/short pulse on eDP which
4646                  * would require vdd on to handle it, and thus we
4647                  * would end up in an endless cycle of
4648                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4649                  */
4650                 drm_dbg_kms(&i915->drm,
4651                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4652                             long_hpd ? "long" : "short",
4653                             dig_port->base.base.base.id,
4654                             dig_port->base.base.name);
4655                 return IRQ_HANDLED;
4656         }
4657
4658         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4659                     dig_port->base.base.base.id,
4660                     dig_port->base.base.name,
4661                     long_hpd ? "long" : "short");
4662
4663         if (long_hpd) {
4664                 intel_dp->reset_link_params = true;
4665                 return IRQ_NONE;
4666         }
4667
4668         if (intel_dp->is_mst) {
4669                 if (!intel_dp_check_mst_status(intel_dp))
4670                         return IRQ_NONE;
4671         } else if (!intel_dp_short_pulse(intel_dp)) {
4672                 return IRQ_NONE;
4673         }
4674
4675         return IRQ_HANDLED;
4676 }
4677
4678 /* check the VBT to see whether the eDP is on another port */
4679 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4680 {
4681         /*
4682          * eDP not supported on g4x. so bail out early just
4683          * for a bit extra safety in case the VBT is bonkers.
4684          */
4685         if (DISPLAY_VER(dev_priv) < 5)
4686                 return false;
4687
4688         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4689                 return true;
4690
4691         return intel_bios_is_port_edp(dev_priv, port);
4692 }
4693
4694 static void
4695 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4696 {
4697         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4698         enum port port = dp_to_dig_port(intel_dp)->base.port;
4699
4700         if (!intel_dp_is_edp(intel_dp))
4701                 drm_connector_attach_dp_subconnector_property(connector);
4702
4703         if (!IS_G4X(dev_priv) && port != PORT_A)
4704                 intel_attach_force_audio_property(connector);
4705
4706         intel_attach_broadcast_rgb_property(connector);
4707         if (HAS_GMCH(dev_priv))
4708                 drm_connector_attach_max_bpc_property(connector, 6, 10);
4709         else if (DISPLAY_VER(dev_priv) >= 5)
4710                 drm_connector_attach_max_bpc_property(connector, 6, 12);
4711
4712         /* Register HDMI colorspace for case of lspcon */
4713         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4714                 drm_connector_attach_content_type_property(connector);
4715                 intel_attach_hdmi_colorspace_property(connector);
4716         } else {
4717                 intel_attach_dp_colorspace_property(connector);
4718         }
4719
4720         if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4721                 drm_object_attach_property(&connector->base,
4722                                            connector->dev->mode_config.hdr_output_metadata_property,
4723                                            0);
4724
4725         if (intel_dp_is_edp(intel_dp)) {
4726                 u32 allowed_scalers;
4727
4728                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4729                 if (!HAS_GMCH(dev_priv))
4730                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4731
4732                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4733
4734                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4735
4736         }
4737
4738         if (HAS_VRR(dev_priv))
4739                 drm_connector_attach_vrr_capable_property(connector);
4740 }
4741
4742 /**
4743  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4744  * @dev_priv: i915 device
4745  * @crtc_state: a pointer to the active intel_crtc_state
4746  * @refresh_rate: RR to be programmed
4747  *
4748  * This function gets called when refresh rate (RR) has to be changed from
4749  * one frequency to another. Switches can be between high and low RR
4750  * supported by the panel or to any other RR based on media playback (in
4751  * this case, RR value needs to be passed from user space).
4752  *
4753  * The caller of this function needs to take a lock on dev_priv->drrs.
4754  */
4755 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4756                                     const struct intel_crtc_state *crtc_state,
4757                                     int refresh_rate)
4758 {
4759         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4761         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4762
4763         if (refresh_rate <= 0) {
4764                 drm_dbg_kms(&dev_priv->drm,
4765                             "Refresh rate should be positive non-zero.\n");
4766                 return;
4767         }
4768
4769         if (intel_dp == NULL) {
4770                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4771                 return;
4772         }
4773
4774         if (!intel_crtc) {
4775                 drm_dbg_kms(&dev_priv->drm,
4776                             "DRRS: intel_crtc not initialized\n");
4777                 return;
4778         }
4779
4780         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4781                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4782                 return;
4783         }
4784
4785         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4786                         refresh_rate)
4787                 index = DRRS_LOW_RR;
4788
4789         if (index == dev_priv->drrs.refresh_rate_type) {
4790                 drm_dbg_kms(&dev_priv->drm,
4791                             "DRRS requested for previously set RR...ignoring\n");
4792                 return;
4793         }
4794
4795         if (!crtc_state->hw.active) {
4796                 drm_dbg_kms(&dev_priv->drm,
4797                             "eDP encoder disabled. CRTC not Active\n");
4798                 return;
4799         }
4800
4801         if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4802                 switch (index) {
4803                 case DRRS_HIGH_RR:
4804                         intel_dp_set_m_n(crtc_state, M1_N1);
4805                         break;
4806                 case DRRS_LOW_RR:
4807                         intel_dp_set_m_n(crtc_state, M2_N2);
4808                         break;
4809                 case DRRS_MAX_RR:
4810                 default:
4811                         drm_err(&dev_priv->drm,
4812                                 "Unsupported refreshrate type\n");
4813                 }
4814         } else if (DISPLAY_VER(dev_priv) > 6) {
4815                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4816                 u32 val;
4817
4818                 val = intel_de_read(dev_priv, reg);
4819                 if (index > DRRS_HIGH_RR) {
4820                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4821                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4822                         else
4823                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4824                 } else {
4825                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4826                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4827                         else
4828                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4829                 }
4830                 intel_de_write(dev_priv, reg, val);
4831         }
4832
4833         dev_priv->drrs.refresh_rate_type = index;
4834
4835         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4836                     refresh_rate);
4837 }
4838
4839 static void
4840 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4841 {
4842         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4843
4844         dev_priv->drrs.busy_frontbuffer_bits = 0;
4845         dev_priv->drrs.dp = intel_dp;
4846 }
4847
4848 /**
4849  * intel_edp_drrs_enable - init drrs struct if supported
4850  * @intel_dp: DP struct
4851  * @crtc_state: A pointer to the active crtc state.
4852  *
4853  * Initializes frontbuffer_bits and drrs.dp
4854  */
4855 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4856                            const struct intel_crtc_state *crtc_state)
4857 {
4858         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4859
4860         if (!crtc_state->has_drrs)
4861                 return;
4862
4863         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4864
4865         mutex_lock(&dev_priv->drrs.mutex);
4866
4867         if (dev_priv->drrs.dp) {
4868                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4869                 goto unlock;
4870         }
4871
4872         intel_edp_drrs_enable_locked(intel_dp);
4873
4874 unlock:
4875         mutex_unlock(&dev_priv->drrs.mutex);
4876 }
4877
4878 static void
4879 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4880                               const struct intel_crtc_state *crtc_state)
4881 {
4882         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4883
4884         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4885                 int refresh;
4886
4887                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4888                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4889         }
4890
4891         dev_priv->drrs.dp = NULL;
4892 }
4893
4894 /**
4895  * intel_edp_drrs_disable - Disable DRRS
4896  * @intel_dp: DP struct
4897  * @old_crtc_state: Pointer to old crtc_state.
4898  *
4899  */
4900 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4901                             const struct intel_crtc_state *old_crtc_state)
4902 {
4903         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904
4905         if (!old_crtc_state->has_drrs)
4906                 return;
4907
4908         mutex_lock(&dev_priv->drrs.mutex);
4909         if (!dev_priv->drrs.dp) {
4910                 mutex_unlock(&dev_priv->drrs.mutex);
4911                 return;
4912         }
4913
4914         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4915         mutex_unlock(&dev_priv->drrs.mutex);
4916
4917         cancel_delayed_work_sync(&dev_priv->drrs.work);
4918 }
4919
4920 /**
4921  * intel_edp_drrs_update - Update DRRS state
4922  * @intel_dp: Intel DP
4923  * @crtc_state: new CRTC state
4924  *
4925  * This function will update DRRS states, disabling or enabling DRRS when
4926  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4927  * intel_edp_drrs_enable() should be called instead.
4928  */
4929 void
4930 intel_edp_drrs_update(struct intel_dp *intel_dp,
4931                       const struct intel_crtc_state *crtc_state)
4932 {
4933         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4934
4935         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4936                 return;
4937
4938         mutex_lock(&dev_priv->drrs.mutex);
4939
4940         /* New state matches current one? */
4941         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4942                 goto unlock;
4943
4944         if (crtc_state->has_drrs)
4945                 intel_edp_drrs_enable_locked(intel_dp);
4946         else
4947                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4948
4949 unlock:
4950         mutex_unlock(&dev_priv->drrs.mutex);
4951 }
4952
4953 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4954 {
4955         struct drm_i915_private *dev_priv =
4956                 container_of(work, typeof(*dev_priv), drrs.work.work);
4957         struct intel_dp *intel_dp;
4958
4959         mutex_lock(&dev_priv->drrs.mutex);
4960
4961         intel_dp = dev_priv->drrs.dp;
4962
4963         if (!intel_dp)
4964                 goto unlock;
4965
4966         /*
4967          * The delayed work can race with an invalidate hence we need to
4968          * recheck.
4969          */
4970
4971         if (dev_priv->drrs.busy_frontbuffer_bits)
4972                 goto unlock;
4973
4974         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4975                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4976
4977                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4978                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4979         }
4980
4981 unlock:
4982         mutex_unlock(&dev_priv->drrs.mutex);
4983 }
4984
4985 /**
4986  * intel_edp_drrs_invalidate - Disable Idleness DRRS
4987  * @dev_priv: i915 device
4988  * @frontbuffer_bits: frontbuffer plane tracking bits
4989  *
4990  * This function gets called everytime rendering on the given planes start.
4991  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4992  *
4993  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4994  */
4995 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4996                                unsigned int frontbuffer_bits)
4997 {
4998         struct intel_dp *intel_dp;
4999         struct drm_crtc *crtc;
5000         enum pipe pipe;
5001
5002         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5003                 return;
5004
5005         cancel_delayed_work(&dev_priv->drrs.work);
5006
5007         mutex_lock(&dev_priv->drrs.mutex);
5008
5009         intel_dp = dev_priv->drrs.dp;
5010         if (!intel_dp) {
5011                 mutex_unlock(&dev_priv->drrs.mutex);
5012                 return;
5013         }
5014
5015         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5016         pipe = to_intel_crtc(crtc)->pipe;
5017
5018         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5019         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5020
5021         /* invalidate means busy screen hence upclock */
5022         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5023                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5024                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5025
5026         mutex_unlock(&dev_priv->drrs.mutex);
5027 }
5028
5029 /**
5030  * intel_edp_drrs_flush - Restart Idleness DRRS
5031  * @dev_priv: i915 device
5032  * @frontbuffer_bits: frontbuffer plane tracking bits
5033  *
5034  * This function gets called every time rendering on the given planes has
5035  * completed or flip on a crtc is completed. So DRRS should be upclocked
5036  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5037  * if no other planes are dirty.
5038  *
5039  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5040  */
5041 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5042                           unsigned int frontbuffer_bits)
5043 {
5044         struct intel_dp *intel_dp;
5045         struct drm_crtc *crtc;
5046         enum pipe pipe;
5047
5048         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5049                 return;
5050
5051         cancel_delayed_work(&dev_priv->drrs.work);
5052
5053         mutex_lock(&dev_priv->drrs.mutex);
5054
5055         intel_dp = dev_priv->drrs.dp;
5056         if (!intel_dp) {
5057                 mutex_unlock(&dev_priv->drrs.mutex);
5058                 return;
5059         }
5060
5061         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5062         pipe = to_intel_crtc(crtc)->pipe;
5063
5064         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5065         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5066
5067         /* flush means busy screen hence upclock */
5068         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5069                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5070                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5071
5072         /*
5073          * flush also means no more activity hence schedule downclock, if all
5074          * other fbs are quiescent too
5075          */
5076         if (!dev_priv->drrs.busy_frontbuffer_bits)
5077                 schedule_delayed_work(&dev_priv->drrs.work,
5078                                 msecs_to_jiffies(1000));
5079         mutex_unlock(&dev_priv->drrs.mutex);
5080 }
5081
5082 /**
5083  * DOC: Display Refresh Rate Switching (DRRS)
5084  *
5085  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5086  * which enables swtching between low and high refresh rates,
5087  * dynamically, based on the usage scenario. This feature is applicable
5088  * for internal panels.
5089  *
5090  * Indication that the panel supports DRRS is given by the panel EDID, which
5091  * would list multiple refresh rates for one resolution.
5092  *
5093  * DRRS is of 2 types - static and seamless.
5094  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5095  * (may appear as a blink on screen) and is used in dock-undock scenario.
5096  * Seamless DRRS involves changing RR without any visual effect to the user
5097  * and can be used during normal system usage. This is done by programming
5098  * certain registers.
5099  *
5100  * Support for static/seamless DRRS may be indicated in the VBT based on
5101  * inputs from the panel spec.
5102  *
5103  * DRRS saves power by switching to low RR based on usage scenarios.
5104  *
5105  * The implementation is based on frontbuffer tracking implementation.  When
5106  * there is a disturbance on the screen triggered by user activity or a periodic
5107  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5108  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5109  * made.
5110  *
5111  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5112  * and intel_edp_drrs_flush() are called.
5113  *
5114  * DRRS can be further extended to support other internal panels and also
5115  * the scenario of video playback wherein RR is set based on the rate
5116  * requested by userspace.
5117  */
5118
5119 /**
5120  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5121  * @connector: eDP connector
5122  * @fixed_mode: preferred mode of panel
5123  *
5124  * This function is  called only once at driver load to initialize basic
5125  * DRRS stuff.
5126  *
5127  * Returns:
5128  * Downclock mode if panel supports it, else return NULL.
5129  * DRRS support is determined by the presence of downclock mode (apart
5130  * from VBT setting).
5131  */
5132 static struct drm_display_mode *
5133 intel_dp_drrs_init(struct intel_connector *connector,
5134                    struct drm_display_mode *fixed_mode)
5135 {
5136         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5137         struct drm_display_mode *downclock_mode = NULL;
5138
5139         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5140         mutex_init(&dev_priv->drrs.mutex);
5141
5142         if (DISPLAY_VER(dev_priv) <= 6) {
5143                 drm_dbg_kms(&dev_priv->drm,
5144                             "DRRS supported for Gen7 and above\n");
5145                 return NULL;
5146         }
5147
5148         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5149                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5150                 return NULL;
5151         }
5152
5153         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5154         if (!downclock_mode) {
5155                 drm_dbg_kms(&dev_priv->drm,
5156                             "Downclock mode is not found. DRRS not supported\n");
5157                 return NULL;
5158         }
5159
5160         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5161
5162         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5163         drm_dbg_kms(&dev_priv->drm,
5164                     "seamless DRRS supported for eDP panel.\n");
5165         return downclock_mode;
5166 }
5167
5168 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5169                                      struct intel_connector *intel_connector)
5170 {
5171         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5172         struct drm_device *dev = &dev_priv->drm;
5173         struct drm_connector *connector = &intel_connector->base;
5174         struct drm_display_mode *fixed_mode = NULL;
5175         struct drm_display_mode *downclock_mode = NULL;
5176         bool has_dpcd;
5177         enum pipe pipe = INVALID_PIPE;
5178         struct edid *edid;
5179
5180         if (!intel_dp_is_edp(intel_dp))
5181                 return true;
5182
5183         /*
5184          * On IBX/CPT we may get here with LVDS already registered. Since the
5185          * driver uses the only internal power sequencer available for both
5186          * eDP and LVDS bail out early in this case to prevent interfering
5187          * with an already powered-on LVDS power sequencer.
5188          */
5189         if (intel_get_lvds_encoder(dev_priv)) {
5190                 drm_WARN_ON(dev,
5191                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5192                 drm_info(&dev_priv->drm,
5193                          "LVDS was detected, not registering eDP\n");
5194
5195                 return false;
5196         }
5197
5198         intel_pps_init(intel_dp);
5199
5200         /* Cache DPCD and EDID for edp. */
5201         has_dpcd = intel_edp_init_dpcd(intel_dp);
5202
5203         if (!has_dpcd) {
5204                 /* if this fails, presume the device is a ghost */
5205                 drm_info(&dev_priv->drm,
5206                          "failed to retrieve link info, disabling eDP\n");
5207                 goto out_vdd_off;
5208         }
5209
5210         mutex_lock(&dev->mode_config.mutex);
5211         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5212         if (edid) {
5213                 if (drm_add_edid_modes(connector, edid)) {
5214                         drm_connector_update_edid_property(connector, edid);
5215                 } else {
5216                         kfree(edid);
5217                         edid = ERR_PTR(-EINVAL);
5218                 }
5219         } else {
5220                 edid = ERR_PTR(-ENOENT);
5221         }
5222         intel_connector->edid = edid;
5223
5224         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5225         if (fixed_mode)
5226                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5227
5228         /* multiply the mode clock and horizontal timings for MSO */
5229         intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5230         intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5231
5232         /* fallback to VBT if available for eDP */
5233         if (!fixed_mode)
5234                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5235         mutex_unlock(&dev->mode_config.mutex);
5236
5237         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5238                 /*
5239                  * Figure out the current pipe for the initial backlight setup.
5240                  * If the current pipe isn't valid, try the PPS pipe, and if that
5241                  * fails just assume pipe A.
5242                  */
5243                 pipe = vlv_active_pipe(intel_dp);
5244
5245                 if (pipe != PIPE_A && pipe != PIPE_B)
5246                         pipe = intel_dp->pps.pps_pipe;
5247
5248                 if (pipe != PIPE_A && pipe != PIPE_B)
5249                         pipe = PIPE_A;
5250
5251                 drm_dbg_kms(&dev_priv->drm,
5252                             "using pipe %c for initial backlight setup\n",
5253                             pipe_name(pipe));
5254         }
5255
5256         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5257         intel_connector->panel.backlight.power = intel_pps_backlight_power;
5258         intel_panel_setup_backlight(connector, pipe);
5259
5260         if (fixed_mode) {
5261                 drm_connector_set_panel_orientation_with_quirk(connector,
5262                                 dev_priv->vbt.orientation,
5263                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
5264         }
5265
5266         return true;
5267
5268 out_vdd_off:
5269         intel_pps_vdd_off_sync(intel_dp);
5270
5271         return false;
5272 }
5273
5274 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5275 {
5276         struct intel_connector *intel_connector;
5277         struct drm_connector *connector;
5278
5279         intel_connector = container_of(work, typeof(*intel_connector),
5280                                        modeset_retry_work);
5281         connector = &intel_connector->base;
5282         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5283                       connector->name);
5284
5285         /* Grab the locks before changing connector property*/
5286         mutex_lock(&connector->dev->mode_config.mutex);
5287         /* Set connector link status to BAD and send a Uevent to notify
5288          * userspace to do a modeset.
5289          */
5290         drm_connector_set_link_status_property(connector,
5291                                                DRM_MODE_LINK_STATUS_BAD);
5292         mutex_unlock(&connector->dev->mode_config.mutex);
5293         /* Send Hotplug uevent so userspace can reprobe */
5294         drm_kms_helper_hotplug_event(connector->dev);
5295 }
5296
5297 bool
5298 intel_dp_init_connector(struct intel_digital_port *dig_port,
5299                         struct intel_connector *intel_connector)
5300 {
5301         struct drm_connector *connector = &intel_connector->base;
5302         struct intel_dp *intel_dp = &dig_port->dp;
5303         struct intel_encoder *intel_encoder = &dig_port->base;
5304         struct drm_device *dev = intel_encoder->base.dev;
5305         struct drm_i915_private *dev_priv = to_i915(dev);
5306         enum port port = intel_encoder->port;
5307         enum phy phy = intel_port_to_phy(dev_priv, port);
5308         int type;
5309
5310         /* Initialize the work for modeset in case of link train failure */
5311         INIT_WORK(&intel_connector->modeset_retry_work,
5312                   intel_dp_modeset_retry_work_fn);
5313
5314         if (drm_WARN(dev, dig_port->max_lanes < 1,
5315                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5316                      dig_port->max_lanes, intel_encoder->base.base.id,
5317                      intel_encoder->base.name))
5318                 return false;
5319
5320         intel_dp_set_source_rates(intel_dp);
5321
5322         intel_dp->reset_link_params = true;
5323         intel_dp->pps.pps_pipe = INVALID_PIPE;
5324         intel_dp->pps.active_pipe = INVALID_PIPE;
5325
5326         /* Preserve the current hw state. */
5327         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5328         intel_dp->attached_connector = intel_connector;
5329
5330         if (intel_dp_is_port_edp(dev_priv, port)) {
5331                 /*
5332                  * Currently we don't support eDP on TypeC ports, although in
5333                  * theory it could work on TypeC legacy ports.
5334                  */
5335                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5336                 type = DRM_MODE_CONNECTOR_eDP;
5337         } else {
5338                 type = DRM_MODE_CONNECTOR_DisplayPort;
5339         }
5340
5341         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5342                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5343
5344         /*
5345          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5346          * for DP the encoder type can be set by the caller to
5347          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5348          */
5349         if (type == DRM_MODE_CONNECTOR_eDP)
5350                 intel_encoder->type = INTEL_OUTPUT_EDP;
5351
5352         /* eDP only on port B and/or C on vlv/chv */
5353         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5354                               IS_CHERRYVIEW(dev_priv)) &&
5355                         intel_dp_is_edp(intel_dp) &&
5356                         port != PORT_B && port != PORT_C))
5357                 return false;
5358
5359         drm_dbg_kms(&dev_priv->drm,
5360                     "Adding %s connector on [ENCODER:%d:%s]\n",
5361                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5362                     intel_encoder->base.base.id, intel_encoder->base.name);
5363
5364         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5365         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5366
5367         if (!HAS_GMCH(dev_priv))
5368                 connector->interlace_allowed = true;
5369         connector->doublescan_allowed = 0;
5370
5371         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5372
5373         intel_dp_aux_init(intel_dp);
5374
5375         intel_connector_attach_encoder(intel_connector, intel_encoder);
5376
5377         if (HAS_DDI(dev_priv))
5378                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5379         else
5380                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5381
5382         /* init MST on ports that can support it */
5383         intel_dp_mst_encoder_init(dig_port,
5384                                   intel_connector->base.base.id);
5385
5386         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5387                 intel_dp_aux_fini(intel_dp);
5388                 intel_dp_mst_encoder_cleanup(dig_port);
5389                 goto fail;
5390         }
5391
5392         intel_dp_add_properties(intel_dp, connector);
5393
5394         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5395                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
5396                 if (ret)
5397                         drm_dbg_kms(&dev_priv->drm,
5398                                     "HDCP init failed, skipping.\n");
5399         }
5400
5401         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5402          * 0xd.  Failure to do so will result in spurious interrupts being
5403          * generated on the port when a cable is not attached.
5404          */
5405         if (IS_G45(dev_priv)) {
5406                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5407                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5408                                (temp & ~0xf) | 0xd);
5409         }
5410
5411         intel_dp->frl.is_trained = false;
5412         intel_dp->frl.trained_rate_gbps = 0;
5413
5414         intel_psr_init(intel_dp);
5415
5416         return true;
5417
5418 fail:
5419         drm_connector_cleanup(connector);
5420
5421         return false;
5422 }
5423
5424 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5425 {
5426         struct intel_encoder *encoder;
5427
5428         for_each_intel_encoder(&dev_priv->drm, encoder) {
5429                 struct intel_dp *intel_dp;
5430
5431                 if (encoder->type != INTEL_OUTPUT_DDI)
5432                         continue;
5433
5434                 intel_dp = enc_to_intel_dp(encoder);
5435
5436                 if (!intel_dp->can_mst)
5437                         continue;
5438
5439                 if (intel_dp->is_mst)
5440                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5441         }
5442 }
5443
5444 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5445 {
5446         struct intel_encoder *encoder;
5447
5448         for_each_intel_encoder(&dev_priv->drm, encoder) {
5449                 struct intel_dp *intel_dp;
5450                 int ret;
5451
5452                 if (encoder->type != INTEL_OUTPUT_DDI)
5453                         continue;
5454
5455                 intel_dp = enc_to_intel_dp(encoder);
5456
5457                 if (!intel_dp->can_mst)
5458                         continue;
5459
5460                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5461                                                      true);
5462                 if (ret) {
5463                         intel_dp->is_mst = false;
5464                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5465                                                         false);
5466                 }
5467         }
5468 }