drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "intel_atomic.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dp.h"
  50 #include "intel_dp_aux.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpll.h"
  54 #include "intel_dpio_phy.h"
  55 #include "intel_fifo_underrun.h"
  56 #include "intel_hdcp.h"
  57 #include "intel_hdmi.h"
  58 #include "intel_hotplug.h"
  59 #include "intel_lspcon.h"
  60 #include "intel_lvds.h"
  61 #include "intel_panel.h"
  62 #include "intel_pps.h"
  63 #include "intel_psr.h"
  64 #include "intel_sideband.h"
  65 #include "intel_tc.h"
  66 #include "intel_vdsc.h"
  67 #include "intel_vrr.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC throughput values used for slice count calculations KPixels/s */
  72 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  75
  76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  77 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  78
  79 /* Compliance test status bits  */
  80 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  81 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84
  85 struct dp_link_dpll {
  86         int clock;
  87         struct dpll dpll;
  88 };
  89
  90 static const struct dp_link_dpll g4x_dpll[] = {
  91         { 162000,
  92                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  93         { 270000,
  94                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  95 };
  96
  97 static const struct dp_link_dpll pch_dpll[] = {
  98         { 162000,
  99                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 100         { 270000,
 101                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 102 };
 103
 104 static const struct dp_link_dpll vlv_dpll[] = {
 105         { 162000,
 106                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 107         { 270000,
 108                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 109 };
 110
 111 /*
 112  * CHV supports eDP 1.4 that have  more link rates.
 113  * Below only provides the fixed rate but exclude variable rate.
 114  */
 115 static const struct dp_link_dpll chv_dpll[] = {
 116         /*
 117          * CHV requires to program fractional division for m2.
 118          * m2 is stored in fixed point format using formula below
 119          * (m2_int << 22) | m2_fraction
 120          */
 121         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 122                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 123         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 124                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 125 };
 126
 127 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
 128 {
 129         return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
 130 }
 131
 132 /* Constants for DP DSC configurations */
 133 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 134
 135 /* With Single pipe configuration, HW is capable of supporting maximum
 136  * of 4 slices per line.
 137  */
 138 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 139
 140 /**
 141  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 142  * @intel_dp: DP struct
 143  *
 144  * If a CPU or PCH DP output is attached to an eDP panel, this function
 145  * will return true, and false otherwise.
 146  */
 147 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 150
 151         return dig_port->base.type == INTEL_OUTPUT_EDP;
 152 }
 153
 154 static void intel_dp_link_down(struct intel_encoder *encoder,
 155                                const struct intel_crtc_state *old_crtc_state);
 156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 157
 158 /* update sink rates from dpcd */
 159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 160 {
 161         static const int dp_rates[] = {
 162                 162000, 270000, 540000, 810000
 163         };
 164         int i, max_rate;
 165         int max_lttpr_rate;
 166
 167         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 168                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 169                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 170
 171                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 172                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 173
 174                 return;
 175         }
 176
 177         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 178         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 179         if (max_lttpr_rate)
 180                 max_rate = min(max_rate, max_lttpr_rate);
 181
 182         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 183                 if (dp_rates[i] > max_rate)
 184                         break;
 185                 intel_dp->sink_rates[i] = dp_rates[i];
 186         }
 187
 188         intel_dp->num_sink_rates = i;
 189 }
 190
 191 /* Get length of rates array potentially limited by max_rate. */
 192 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 193 {
 194         int i;
 195
 196         /* Limit results by potentially reduced max rate */
 197         for (i = 0; i < len; i++) {
 198                 if (rates[len - i - 1] <= max_rate)
 199                         return len - i;
 200         }
 201
 202         return 0;
 203 }
 204
 205 /* Get length of common rates array potentially limited by max_rate. */
 206 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 207                                           int max_rate)
 208 {
 209         return intel_dp_rate_limit_len(intel_dp->common_rates,
 210                                        intel_dp->num_common_rates, max_rate);
 211 }
 212
 213 /* Theoretical max between source and sink */
 214 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 215 {
 216         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 217 }
 218
 219 /* Theoretical max between source and sink */
 220 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 221 {
 222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 223         int source_max = dig_port->max_lanes;
 224         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 225         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 226         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 227
 228         if (lttpr_max)
 229                 sink_max = min(sink_max, lttpr_max);
 230
 231         return min3(source_max, sink_max, fia_max);
 232 }
 233
 234 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 235 {
 236         return intel_dp->max_link_lane_count;
 237 }
 238
 239 int
 240 intel_dp_link_required(int pixel_clock, int bpp)
 241 {
 242         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 243         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 244 }
 245
 246 int
 247 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 248 {
 249         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 250          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 251          * is transmitted every LS_Clk per lane, there is no need to account for
 252          * the channel encoding that is done in the PHY layer here.
 253          */
 254
 255         return max_link_clock * max_lanes;
 256 }
 257
 258 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 259 {
 260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 261         struct intel_encoder *encoder = &intel_dig_port->base;
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263
 264         return INTEL_GEN(dev_priv) >= 12 ||
 265                 (INTEL_GEN(dev_priv) == 11 &&
 266                  encoder->port != PORT_A);
 267 }
 268
 269 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 270 {
 271         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 272         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 273         enum port port = dig_port->base.port;
 274
 275         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 276
 277         /* Low voltage SKUs are limited to max of 5.4G */
 278         if (voltage == VOLTAGE_INFO_0_85V)
 279                 return 540000;
 280
 281         /* For this SKU 8.1G is supported in all ports */
 282         if (IS_CNL_WITH_PORT_F(dev_priv))
 283                 return 810000;
 284
 285         /* For other SKUs, max rate on ports A and D is 5.4G */
 286         if (port == PORT_A || port == PORT_D)
 287                 return 540000;
 288
 289         return 810000;
 290 }
 291
 292 static int icl_max_source_rate(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 296         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 297
 298         if (intel_phy_is_combo(dev_priv, phy) &&
 299             !intel_dp_is_edp(intel_dp))
 300                 return 540000;
 301
 302         return 810000;
 303 }
 304
 305 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 306 {
 307         if (intel_dp_is_edp(intel_dp))
 308                 return 540000;
 309
 310         return 810000;
 311 }
 312
 313 static void
 314 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 315 {
 316         /* The values must be in increasing order */
 317         static const int cnl_rates[] = {
 318                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 319         };
 320         static const int bxt_rates[] = {
 321                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 322         };
 323         static const int skl_rates[] = {
 324                 162000, 216000, 270000, 324000, 432000, 540000
 325         };
 326         static const int hsw_rates[] = {
 327                 162000, 270000, 540000
 328         };
 329         static const int g4x_rates[] = {
 330                 162000, 270000
 331         };
 332         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 333         struct intel_encoder *encoder = &dig_port->base;
 334         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 335         const int *source_rates;
 336         int size, max_rate = 0, vbt_max_rate;
 337
 338         /* This should only be done once */
 339         drm_WARN_ON(&dev_priv->drm,
 340                     intel_dp->source_rates || intel_dp->num_source_rates);
 341
 342         if (INTEL_GEN(dev_priv) >= 10) {
 343                 source_rates = cnl_rates;
 344                 size = ARRAY_SIZE(cnl_rates);
 345                 if (IS_GEN(dev_priv, 10))
 346                         max_rate = cnl_max_source_rate(intel_dp);
 347                 else if (IS_JSL_EHL(dev_priv))
 348                         max_rate = ehl_max_source_rate(intel_dp);
 349                 else
 350                         max_rate = icl_max_source_rate(intel_dp);
 351         } else if (IS_GEN9_LP(dev_priv)) {
 352                 source_rates = bxt_rates;
 353                 size = ARRAY_SIZE(bxt_rates);
 354         } else if (IS_GEN9_BC(dev_priv)) {
 355                 source_rates = skl_rates;
 356                 size = ARRAY_SIZE(skl_rates);
 357         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 358                    IS_BROADWELL(dev_priv)) {
 359                 source_rates = hsw_rates;
 360                 size = ARRAY_SIZE(hsw_rates);
 361         } else {
 362                 source_rates = g4x_rates;
 363                 size = ARRAY_SIZE(g4x_rates);
 364         }
 365
 366         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 367         if (max_rate && vbt_max_rate)
 368                 max_rate = min(max_rate, vbt_max_rate);
 369         else if (vbt_max_rate)
 370                 max_rate = vbt_max_rate;
 371
 372         if (max_rate)
 373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 374
 375         intel_dp->source_rates = source_rates;
 376         intel_dp->num_source_rates = size;
 377 }
 378
 379 static int intersect_rates(const int *source_rates, int source_len,
 380                            const int *sink_rates, int sink_len,
 381                            int *common_rates)
 382 {
 383         int i = 0, j = 0, k = 0;
 384
 385         while (i < source_len && j < sink_len) {
 386                 if (source_rates[i] == sink_rates[j]) {
 387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 388                                 return k;
 389                         common_rates[k] = source_rates[i];
 390                         ++k;
 391                         ++i;
 392                         ++j;
 393                 } else if (source_rates[i] < sink_rates[j]) {
 394                         ++i;
 395                 } else {
 396                         ++j;
 397                 }
 398         }
 399         return k;
 400 }
 401
 402 /* return index of rate in rates array, or -1 if not found */
 403 static int intel_dp_rate_index(const int *rates, int len, int rate)
 404 {
 405         int i;
 406
 407         for (i = 0; i < len; i++)
 408                 if (rate == rates[i])
 409                         return i;
 410
 411         return -1;
 412 }
 413
 414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 415 {
 416         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 417
 418         drm_WARN_ON(&i915->drm,
 419                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 420
 421         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 422                                                      intel_dp->num_source_rates,
 423                                                      intel_dp->sink_rates,
 424                                                      intel_dp->num_sink_rates,
 425                                                      intel_dp->common_rates);
 426
 427         /* Paranoia, there should always be something in common. */
 428         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 429                 intel_dp->common_rates[0] = 162000;
 430                 intel_dp->num_common_rates = 1;
 431         }
 432 }
 433
 434 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 435                                        u8 lane_count)
 436 {
 437         /*
 438          * FIXME: we need to synchronize the current link parameters with
 439          * hardware readout. Currently fast link training doesn't work on
 440          * boot-up.
 441          */
 442         if (link_rate == 0 ||
 443             link_rate > intel_dp->max_link_rate)
 444                 return false;
 445
 446         if (lane_count == 0 ||
 447             lane_count > intel_dp_max_lane_count(intel_dp))
 448                 return false;
 449
 450         return true;
 451 }
 452
 453 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 454                                                      int link_rate,
 455                                                      u8 lane_count)
 456 {
 457         const struct drm_display_mode *fixed_mode =
 458                 intel_dp->attached_connector->panel.fixed_mode;
 459         int mode_rate, max_rate;
 460
 461         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 462         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 463         if (mode_rate > max_rate)
 464                 return false;
 465
 466         return true;
 467 }
 468
 469 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 470                                             int link_rate, u8 lane_count)
 471 {
 472         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 473         int index;
 474
 475         /*
 476          * TODO: Enable fallback on MST links once MST link compute can handle
 477          * the fallback params.
 478          */
 479         if (intel_dp->is_mst) {
 480                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 481                 return -1;
 482         }
 483
 484         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 485                 drm_dbg_kms(&i915->drm,
 486                             "Retrying Link training for eDP with max parameters\n");
 487                 intel_dp->use_max_params = true;
 488                 return 0;
 489         }
 490
 491         index = intel_dp_rate_index(intel_dp->common_rates,
 492                                     intel_dp->num_common_rates,
 493                                     link_rate);
 494         if (index > 0) {
 495                 if (intel_dp_is_edp(intel_dp) &&
 496                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 497                                                               intel_dp->common_rates[index - 1],
 498                                                               lane_count)) {
 499                         drm_dbg_kms(&i915->drm,
 500                                     "Retrying Link training for eDP with same parameters\n");
 501                         return 0;
 502                 }
 503                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 504                 intel_dp->max_link_lane_count = lane_count;
 505         } else if (lane_count > 1) {
 506                 if (intel_dp_is_edp(intel_dp) &&
 507                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 508                                                               intel_dp_max_common_rate(intel_dp),
 509                                                               lane_count >> 1)) {
 510                         drm_dbg_kms(&i915->drm,
 511                                     "Retrying Link training for eDP with same parameters\n");
 512                         return 0;
 513                 }
 514                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 515                 intel_dp->max_link_lane_count = lane_count >> 1;
 516         } else {
 517                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 518                 return -1;
 519         }
 520
 521         return 0;
 522 }
 523
 524 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 525 {
 526         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 527                        DP_DSC_FEC_OVERHEAD_FACTOR);
 528 }
 529
 530 static int
 531 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 532 {
 533         if (INTEL_GEN(i915) >= 11)
 534                 return 7680 * 8;
 535         else
 536                 return 6144 * 8;
 537 }
 538
 539 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 540                                        u32 link_clock, u32 lane_count,
 541                                        u32 mode_clock, u32 mode_hdisplay,
 542                                        bool bigjoiner)
 543 {
 544         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 545         int i;
 546
 547         /*
 548          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 549          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 550          * for SST -> TimeSlotsPerMTP is 1,
 551          * for MST -> TimeSlotsPerMTP has to be calculated
 552          */
 553         bits_per_pixel = (link_clock * lane_count * 8) /
 554                          intel_dp_mode_to_fec_clock(mode_clock);
 555         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 556
 557         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 558         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 559                 mode_hdisplay;
 560
 561         if (bigjoiner)
 562                 max_bpp_small_joiner_ram *= 2;
 563
 564         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 565                     max_bpp_small_joiner_ram);
 566
 567         /*
 568          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 569          * check, output bpp from small joiner RAM check)
 570          */
 571         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 572
 573         if (bigjoiner) {
 574                 u32 max_bpp_bigjoiner =
 575                         i915->max_cdclk_freq * 48 /
 576                         intel_dp_mode_to_fec_clock(mode_clock);
 577
 578                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 579                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 580         }
 581
 582         /* Error out if the max bpp is less than smallest allowed valid bpp */
 583         if (bits_per_pixel < valid_dsc_bpp[0]) {
 584                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 585                             bits_per_pixel, valid_dsc_bpp[0]);
 586                 return 0;
 587         }
 588
 589         /* Find the nearest match in the array of known BPPs from VESA */
 590         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 591                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 592                         break;
 593         }
 594         bits_per_pixel = valid_dsc_bpp[i];
 595
 596         /*
 597          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 598          * fractional part is 0
 599          */
 600         return bits_per_pixel << 4;
 601 }
 602
 603 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 604                                        int mode_clock, int mode_hdisplay,
 605                                        bool bigjoiner)
 606 {
 607         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 608         u8 min_slice_count, i;
 609         int max_slice_width;
 610
 611         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 612                 min_slice_count = DIV_ROUND_UP(mode_clock,
 613                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 614         else
 615                 min_slice_count = DIV_ROUND_UP(mode_clock,
 616                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 617
 618         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 619         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 620                 drm_dbg_kms(&i915->drm,
 621                             "Unsupported slice width %d by DP DSC Sink device\n",
 622                             max_slice_width);
 623                 return 0;
 624         }
 625         /* Also take into account max slice width */
 626         min_slice_count = max_t(u8, min_slice_count,
 627                                 DIV_ROUND_UP(mode_hdisplay,
 628                                              max_slice_width));
 629
 630         /* Find the closest match to the valid slice count values */
 631         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 632                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 633
 634                 if (test_slice_count >
 635                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 636                         break;
 637
 638                 /* big joiner needs small joiner to be enabled */
 639                 if (bigjoiner && test_slice_count < 4)
 640                         continue;
 641
 642                 if (min_slice_count <= test_slice_count)
 643                         return test_slice_count;
 644         }
 645
 646         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 647                     min_slice_count);
 648         return 0;
 649 }
 650
 651 static enum intel_output_format
 652 intel_dp_output_format(struct drm_connector *connector,
 653                        const struct drm_display_mode *mode)
 654 {
 655         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 656         const struct drm_display_info *info = &connector->display_info;
 657
 658         if (!connector->ycbcr_420_allowed ||
 659             !drm_mode_is_420_only(info, mode))
 660                 return INTEL_OUTPUT_FORMAT_RGB;
 661
 662         if (intel_dp->dfp.rgb_to_ycbcr &&
 663             intel_dp->dfp.ycbcr_444_to_420)
 664                 return INTEL_OUTPUT_FORMAT_RGB;
 665
 666         if (intel_dp->dfp.ycbcr_444_to_420)
 667                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 668         else
 669                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 670 }
 671
 672 int intel_dp_min_bpp(enum intel_output_format output_format)
 673 {
 674         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 675                 return 6 * 3;
 676         else
 677                 return 8 * 3;
 678 }
 679
 680 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 681 {
 682         /*
 683          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 684          * format of the number of bytes per pixel will be half the number
 685          * of bytes of RGB pixel.
 686          */
 687         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 688                 bpp /= 2;
 689
 690         return bpp;
 691 }
 692
 693 static int
 694 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 695                              const struct drm_display_mode *mode)
 696 {
 697         enum intel_output_format output_format =
 698                 intel_dp_output_format(connector, mode);
 699
 700         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 701 }
 702
 703 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 704                                   int hdisplay)
 705 {
 706         /*
 707          * Older platforms don't like hdisplay==4096 with DP.
 708          *
 709          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 710          * and frame counter increment), but we don't get vblank interrupts,
 711          * and the pipe underruns immediately. The link also doesn't seem
 712          * to get trained properly.
 713          *
 714          * On CHV the vblank interrupts don't seem to disappear but
 715          * otherwise the symptoms are similar.
 716          *
 717          * TODO: confirm the behaviour on HSW+
 718          */
 719         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 720 }
 721
 722 static enum drm_mode_status
 723 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 724                                const struct drm_display_mode *mode,
 725                                int target_clock)
 726 {
 727         struct intel_dp *intel_dp = intel_attached_dp(connector);
 728         const struct drm_display_info *info = &connector->base.display_info;
 729         int tmds_clock;
 730
 731         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 732         if (intel_dp->dfp.pcon_max_frl_bw) {
 733                 int target_bw;
 734                 int max_frl_bw;
 735                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 736
 737                 target_bw = bpp * target_clock;
 738
 739                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 740
 741                 /* converting bw from Gbps to Kbps*/
 742                 max_frl_bw = max_frl_bw * 1000000;
 743
 744                 if (target_bw > max_frl_bw)
 745                         return MODE_CLOCK_HIGH;
 746
 747                 return MODE_OK;
 748         }
 749
 750         if (intel_dp->dfp.max_dotclock &&
 751             target_clock > intel_dp->dfp.max_dotclock)
 752                 return MODE_CLOCK_HIGH;
 753
 754         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 755         tmds_clock = target_clock;
 756         if (drm_mode_is_420_only(info, mode))
 757                 tmds_clock /= 2;
 758
 759         if (intel_dp->dfp.min_tmds_clock &&
 760             tmds_clock < intel_dp->dfp.min_tmds_clock)
 761                 return MODE_CLOCK_LOW;
 762         if (intel_dp->dfp.max_tmds_clock &&
 763             tmds_clock > intel_dp->dfp.max_tmds_clock)
 764                 return MODE_CLOCK_HIGH;
 765
 766         return MODE_OK;
 767 }
 768
 769 static enum drm_mode_status
 770 intel_dp_mode_valid(struct drm_connector *connector,
 771                     struct drm_display_mode *mode)
 772 {
 773         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 774         struct intel_connector *intel_connector = to_intel_connector(connector);
 775         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 776         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 777         int target_clock = mode->clock;
 778         int max_rate, mode_rate, max_lanes, max_link_clock;
 779         int max_dotclk = dev_priv->max_dotclk_freq;
 780         u16 dsc_max_output_bpp = 0;
 781         u8 dsc_slice_count = 0;
 782         enum drm_mode_status status;
 783         bool dsc = false, bigjoiner = false;
 784
 785         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 786                 return MODE_NO_DBLESCAN;
 787
 788         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 789                 return MODE_H_ILLEGAL;
 790
 791         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 792                 if (mode->hdisplay != fixed_mode->hdisplay)
 793                         return MODE_PANEL;
 794
 795                 if (mode->vdisplay != fixed_mode->vdisplay)
 796                         return MODE_PANEL;
 797
 798                 target_clock = fixed_mode->clock;
 799         }
 800
 801         if (mode->clock < 10000)
 802                 return MODE_CLOCK_LOW;
 803
 804         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 805             intel_dp_can_bigjoiner(intel_dp)) {
 806                 bigjoiner = true;
 807                 max_dotclk *= 2;
 808         }
 809         if (target_clock > max_dotclk)
 810                 return MODE_CLOCK_HIGH;
 811
 812         max_link_clock = intel_dp_max_link_rate(intel_dp);
 813         max_lanes = intel_dp_max_lane_count(intel_dp);
 814
 815         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 816         mode_rate = intel_dp_link_required(target_clock,
 817                                            intel_dp_mode_min_output_bpp(connector, mode));
 818
 819         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 820                 return MODE_H_ILLEGAL;
 821
 822         /*
 823          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 824          * integer value since we support only integer values of bpp.
 825          */
 826         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 827             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 828                 if (intel_dp_is_edp(intel_dp)) {
 829                         dsc_max_output_bpp =
 830                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 831                         dsc_slice_count =
 832                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 833                                                                 true);
 834                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 835                         dsc_max_output_bpp =
 836                                 intel_dp_dsc_get_output_bpp(dev_priv,
 837                                                             max_link_clock,
 838                                                             max_lanes,
 839                                                             target_clock,
 840                                                             mode->hdisplay,
 841                                                             bigjoiner) >> 4;
 842                         dsc_slice_count =
 843                                 intel_dp_dsc_get_slice_count(intel_dp,
 844                                                              target_clock,
 845                                                              mode->hdisplay,
 846                                                              bigjoiner);
 847                 }
 848
 849                 dsc = dsc_max_output_bpp && dsc_slice_count;
 850         }
 851
 852         /* big joiner configuration needs DSC */
 853         if (bigjoiner && !dsc)
 854                 return MODE_CLOCK_HIGH;
 855
 856         if (mode_rate > max_rate && !dsc)
 857                 return MODE_CLOCK_HIGH;
 858
 859         status = intel_dp_mode_valid_downstream(intel_connector,
 860                                                 mode, target_clock);
 861         if (status != MODE_OK)
 862                 return status;
 863
 864         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 865 }
 866
 867 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
 868 {
 869         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 870
 871         return max_rate >= 540000;
 872 }
 873
 874 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
 875 {
 876         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 877
 878         return max_rate >= 810000;
 879 }
 880
 881 static void
 882 intel_dp_set_clock(struct intel_encoder *encoder,
 883                    struct intel_crtc_state *pipe_config)
 884 {
 885         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 886         const struct dp_link_dpll *divisor = NULL;
 887         int i, count = 0;
 888
 889         if (IS_G4X(dev_priv)) {
 890                 divisor = g4x_dpll;
 891                 count = ARRAY_SIZE(g4x_dpll);
 892         } else if (HAS_PCH_SPLIT(dev_priv)) {
 893                 divisor = pch_dpll;
 894                 count = ARRAY_SIZE(pch_dpll);
 895         } else if (IS_CHERRYVIEW(dev_priv)) {
 896                 divisor = chv_dpll;
 897                 count = ARRAY_SIZE(chv_dpll);
 898         } else if (IS_VALLEYVIEW(dev_priv)) {
 899                 divisor = vlv_dpll;
 900                 count = ARRAY_SIZE(vlv_dpll);
 901         }
 902
 903         if (divisor && count) {
 904                 for (i = 0; i < count; i++) {
 905                         if (pipe_config->port_clock == divisor[i].clock) {
 906                                 pipe_config->dpll = divisor[i].dpll;
 907                                 pipe_config->clock_set = true;
 908                                 break;
 909                         }
 910                 }
 911         }
 912 }
 913
 914 static void snprintf_int_array(char *str, size_t len,
 915                                const int *array, int nelem)
 916 {
 917         int i;
 918
 919         str[0] = '\0';
 920
 921         for (i = 0; i < nelem; i++) {
 922                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
 923                 if (r >= len)
 924                         return;
 925                 str += r;
 926                 len -= r;
 927         }
 928 }
 929
 930 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 931 {
 932         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 933         char str[128]; /* FIXME: too big for stack? */
 934
 935         if (!drm_debug_enabled(DRM_UT_KMS))
 936                 return;
 937
 938         snprintf_int_array(str, sizeof(str),
 939                            intel_dp->source_rates, intel_dp->num_source_rates);
 940         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
 941
 942         snprintf_int_array(str, sizeof(str),
 943                            intel_dp->sink_rates, intel_dp->num_sink_rates);
 944         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
 945
 946         snprintf_int_array(str, sizeof(str),
 947                            intel_dp->common_rates, intel_dp->num_common_rates);
 948         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
 949 }
 950
 951 int
 952 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 953 {
 954         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 955         int len;
 956
 957         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
 958         if (drm_WARN_ON(&i915->drm, len <= 0))
 959                 return 162000;
 960
 961         return intel_dp->common_rates[len - 1];
 962 }
 963
 964 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 965 {
 966         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 967         int i = intel_dp_rate_index(intel_dp->sink_rates,
 968                                     intel_dp->num_sink_rates, rate);
 969
 970         if (drm_WARN_ON(&i915->drm, i < 0))
 971                 i = 0;
 972
 973         return i;
 974 }
 975
 976 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 977                            u8 *link_bw, u8 *rate_select)
 978 {
 979         /* eDP 1.4 rate select method. */
 980         if (intel_dp->use_rate_select) {
 981                 *link_bw = 0;
 982                 *rate_select =
 983                         intel_dp_rate_select(intel_dp, port_clock);
 984         } else {
 985                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
 986                 *rate_select = 0;
 987         }
 988 }
 989
 990 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 991                                          const struct intel_crtc_state *pipe_config)
 992 {
 993         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 994
 995         /* On TGL, FEC is supported on all Pipes */
 996         if (INTEL_GEN(dev_priv) >= 12)
 997                 return true;
 998
 999         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1000                 return true;
1001
1002         return false;
1003 }
1004
1005 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1006                                   const struct intel_crtc_state *pipe_config)
1007 {
1008         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1009                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1010 }
1011
1012 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1013                                   const struct intel_crtc_state *crtc_state)
1014 {
1015         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1016                 return false;
1017
1018         return intel_dsc_source_support(crtc_state) &&
1019                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1020 }
1021
1022 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
1023                                    const struct intel_crtc_state *crtc_state)
1024 {
1025         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1026                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1027                  intel_dp->dfp.ycbcr_444_to_420);
1028 }
1029
1030 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
1031                                     const struct intel_crtc_state *crtc_state, int bpc)
1032 {
1033         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
1034
1035         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
1036                 clock /= 2;
1037
1038         return clock;
1039 }
1040
1041 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
1042                                            const struct intel_crtc_state *crtc_state, int bpc)
1043 {
1044         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
1045
1046         if (intel_dp->dfp.min_tmds_clock &&
1047             tmds_clock < intel_dp->dfp.min_tmds_clock)
1048                 return false;
1049
1050         if (intel_dp->dfp.max_tmds_clock &&
1051             tmds_clock > intel_dp->dfp.max_tmds_clock)
1052                 return false;
1053
1054         return true;
1055 }
1056
1057 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
1058                                               const struct intel_crtc_state *crtc_state,
1059                                               int bpc)
1060 {
1061
1062         return intel_hdmi_deep_color_possible(crtc_state, bpc,
1063                                               intel_dp->has_hdmi_sink,
1064                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1065                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
1066 }
1067
1068 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1069                             const struct intel_crtc_state *crtc_state)
1070 {
1071         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1072         struct intel_connector *intel_connector = intel_dp->attached_connector;
1073         int bpp, bpc;
1074
1075         bpc = crtc_state->pipe_bpp / 3;
1076
1077         if (intel_dp->dfp.max_bpc)
1078                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1079
1080         if (intel_dp->dfp.min_tmds_clock) {
1081                 for (; bpc >= 10; bpc -= 2) {
1082                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1083                                 break;
1084                 }
1085         }
1086
1087         bpp = bpc * 3;
1088         if (intel_dp_is_edp(intel_dp)) {
1089                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1090                 if (intel_connector->base.display_info.bpc == 0 &&
1091                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1092                         drm_dbg_kms(&dev_priv->drm,
1093                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1094                                     dev_priv->vbt.edp.bpp);
1095                         bpp = dev_priv->vbt.edp.bpp;
1096                 }
1097         }
1098
1099         return bpp;
1100 }
1101
1102 /* Adjust link config limits based on compliance test requests. */
1103 void
1104 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1105                                   struct intel_crtc_state *pipe_config,
1106                                   struct link_config_limits *limits)
1107 {
1108         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1109
1110         /* For DP Compliance we override the computed bpp for the pipe */
1111         if (intel_dp->compliance.test_data.bpc != 0) {
1112                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1113
1114                 limits->min_bpp = limits->max_bpp = bpp;
1115                 pipe_config->dither_force_disable = bpp == 6 * 3;
1116
1117                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1118         }
1119
1120         /* Use values requested by Compliance Test Request */
1121         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1122                 int index;
1123
1124                 /* Validate the compliance test data since max values
1125                  * might have changed due to link train fallback.
1126                  */
1127                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1128                                                intel_dp->compliance.test_lane_count)) {
1129                         index = intel_dp_rate_index(intel_dp->common_rates,
1130                                                     intel_dp->num_common_rates,
1131                                                     intel_dp->compliance.test_link_rate);
1132                         if (index >= 0)
1133                                 limits->min_clock = limits->max_clock = index;
1134                         limits->min_lane_count = limits->max_lane_count =
1135                                 intel_dp->compliance.test_lane_count;
1136                 }
1137         }
1138 }
1139
1140 /* Optimize link config in order: max bpp, min clock, min lanes */
1141 static int
1142 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1143                                   struct intel_crtc_state *pipe_config,
1144                                   const struct link_config_limits *limits)
1145 {
1146         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1147         int bpp, clock, lane_count;
1148         int mode_rate, link_clock, link_avail;
1149
1150         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1151                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1152
1153                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1154                                                    output_bpp);
1155
1156                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1157                         for (lane_count = limits->min_lane_count;
1158                              lane_count <= limits->max_lane_count;
1159                              lane_count <<= 1) {
1160                                 link_clock = intel_dp->common_rates[clock];
1161                                 link_avail = intel_dp_max_data_rate(link_clock,
1162                                                                     lane_count);
1163
1164                                 if (mode_rate <= link_avail) {
1165                                         pipe_config->lane_count = lane_count;
1166                                         pipe_config->pipe_bpp = bpp;
1167                                         pipe_config->port_clock = link_clock;
1168
1169                                         return 0;
1170                                 }
1171                         }
1172                 }
1173         }
1174
1175         return -EINVAL;
1176 }
1177
1178 /* Optimize link config in order: max bpp, min lanes, min clock */
1179 static int
1180 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1181                                   struct intel_crtc_state *pipe_config,
1182                                   const struct link_config_limits *limits)
1183 {
1184         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1185         int bpp, clock, lane_count;
1186         int mode_rate, link_clock, link_avail;
1187
1188         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1189                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1190
1191                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1192                                                    output_bpp);
1193
1194                 for (lane_count = limits->min_lane_count;
1195                      lane_count <= limits->max_lane_count;
1196                      lane_count <<= 1) {
1197                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1198                                 link_clock = intel_dp->common_rates[clock];
1199                                 link_avail = intel_dp_max_data_rate(link_clock,
1200                                                                     lane_count);
1201
1202                                 if (mode_rate <= link_avail) {
1203                                         pipe_config->lane_count = lane_count;
1204                                         pipe_config->pipe_bpp = bpp;
1205                                         pipe_config->port_clock = link_clock;
1206
1207                                         return 0;
1208                                 }
1209                         }
1210                 }
1211         }
1212
1213         return -EINVAL;
1214 }
1215
1216 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1217 {
1218         int i, num_bpc;
1219         u8 dsc_bpc[3] = {0};
1220
1221         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1222                                                        dsc_bpc);
1223         for (i = 0; i < num_bpc; i++) {
1224                 if (dsc_max_bpc >= dsc_bpc[i])
1225                         return dsc_bpc[i] * 3;
1226         }
1227
1228         return 0;
1229 }
1230
1231 #define DSC_SUPPORTED_VERSION_MIN               1
1232
1233 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1234                                        struct intel_crtc_state *crtc_state)
1235 {
1236         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1237         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1238         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1239         u8 line_buf_depth;
1240         int ret;
1241
1242         /*
1243          * RC_MODEL_SIZE is currently a constant across all configurations.
1244          *
1245          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1246          * DP_DSC_RC_BUF_SIZE for this.
1247          */
1248         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1249
1250         ret = intel_dsc_compute_params(encoder, crtc_state);
1251         if (ret)
1252                 return ret;
1253
1254         /*
1255          * Slice Height of 8 works for all currently available panels. So start
1256          * with that if pic_height is an integral multiple of 8. Eventually add
1257          * logic to try multiple slice heights.
1258          */
1259         if (vdsc_cfg->pic_height % 8 == 0)
1260                 vdsc_cfg->slice_height = 8;
1261         else if (vdsc_cfg->pic_height % 4 == 0)
1262                 vdsc_cfg->slice_height = 4;
1263         else
1264                 vdsc_cfg->slice_height = 2;
1265
1266         vdsc_cfg->dsc_version_major =
1267                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1268                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1269         vdsc_cfg->dsc_version_minor =
1270                 min(DSC_SUPPORTED_VERSION_MIN,
1271                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1272                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1273
1274         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1275                 DP_DSC_RGB;
1276
1277         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1278         if (!line_buf_depth) {
1279                 drm_dbg_kms(&i915->drm,
1280                             "DSC Sink Line Buffer Depth invalid\n");
1281                 return -EINVAL;
1282         }
1283
1284         if (vdsc_cfg->dsc_version_minor == 2)
1285                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1286                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1287         else
1288                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1289                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1290
1291         vdsc_cfg->block_pred_enable =
1292                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1293                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1294
1295         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1296 }
1297
1298 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1299                                        struct intel_crtc_state *pipe_config,
1300                                        struct drm_connector_state *conn_state,
1301                                        struct link_config_limits *limits)
1302 {
1303         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1304         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1305         const struct drm_display_mode *adjusted_mode =
1306                 &pipe_config->hw.adjusted_mode;
1307         u8 dsc_max_bpc;
1308         int pipe_bpp;
1309         int ret;
1310
1311         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1312                 intel_dp_supports_fec(intel_dp, pipe_config);
1313
1314         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1315                 return -EINVAL;
1316
1317         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1318         if (INTEL_GEN(dev_priv) >= 12)
1319                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1320         else
1321                 dsc_max_bpc = min_t(u8, 10,
1322                                     conn_state->max_requested_bpc);
1323
1324         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1325
1326         /* Min Input BPC for ICL+ is 8 */
1327         if (pipe_bpp < 8 * 3) {
1328                 drm_dbg_kms(&dev_priv->drm,
1329                             "No DSC support for less than 8bpc\n");
1330                 return -EINVAL;
1331         }
1332
1333         /*
1334          * For now enable DSC for max bpp, max link rate, max lane count.
1335          * Optimize this later for the minimum possible link rate/lane count
1336          * with DSC enabled for the requested mode.
1337          */
1338         pipe_config->pipe_bpp = pipe_bpp;
1339         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1340         pipe_config->lane_count = limits->max_lane_count;
1341
1342         if (intel_dp_is_edp(intel_dp)) {
1343                 pipe_config->dsc.compressed_bpp =
1344                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1345                               pipe_config->pipe_bpp);
1346                 pipe_config->dsc.slice_count =
1347                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1348                                                         true);
1349         } else {
1350                 u16 dsc_max_output_bpp;
1351                 u8 dsc_dp_slice_count;
1352
1353                 dsc_max_output_bpp =
1354                         intel_dp_dsc_get_output_bpp(dev_priv,
1355                                                     pipe_config->port_clock,
1356                                                     pipe_config->lane_count,
1357                                                     adjusted_mode->crtc_clock,
1358                                                     adjusted_mode->crtc_hdisplay,
1359                                                     pipe_config->bigjoiner);
1360                 dsc_dp_slice_count =
1361                         intel_dp_dsc_get_slice_count(intel_dp,
1362                                                      adjusted_mode->crtc_clock,
1363                                                      adjusted_mode->crtc_hdisplay,
1364                                                      pipe_config->bigjoiner);
1365                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1366                         drm_dbg_kms(&dev_priv->drm,
1367                                     "Compressed BPP/Slice Count not supported\n");
1368                         return -EINVAL;
1369                 }
1370                 pipe_config->dsc.compressed_bpp = min_t(u16,
1371                                                                dsc_max_output_bpp >> 4,
1372                                                                pipe_config->pipe_bpp);
1373                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1374         }
1375         /*
1376          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1377          * is greater than the maximum Cdclock and if slice count is even
1378          * then we need to use 2 VDSC instances.
1379          */
1380         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1381             pipe_config->bigjoiner) {
1382                 if (pipe_config->dsc.slice_count < 2) {
1383                         drm_dbg_kms(&dev_priv->drm,
1384                                     "Cannot split stream to use 2 VDSC instances\n");
1385                         return -EINVAL;
1386                 }
1387
1388                 pipe_config->dsc.dsc_split = true;
1389         }
1390
1391         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1392         if (ret < 0) {
1393                 drm_dbg_kms(&dev_priv->drm,
1394                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1395                             "Compressed BPP = %d\n",
1396                             pipe_config->pipe_bpp,
1397                             pipe_config->dsc.compressed_bpp);
1398                 return ret;
1399         }
1400
1401         pipe_config->dsc.compression_enable = true;
1402         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1403                     "Compressed Bpp = %d Slice Count = %d\n",
1404                     pipe_config->pipe_bpp,
1405                     pipe_config->dsc.compressed_bpp,
1406                     pipe_config->dsc.slice_count);
1407
1408         return 0;
1409 }
1410
1411 static int
1412 intel_dp_compute_link_config(struct intel_encoder *encoder,
1413                              struct intel_crtc_state *pipe_config,
1414                              struct drm_connector_state *conn_state)
1415 {
1416         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1417         const struct drm_display_mode *adjusted_mode =
1418                 &pipe_config->hw.adjusted_mode;
1419         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1420         struct link_config_limits limits;
1421         int common_len;
1422         int ret;
1423
1424         common_len = intel_dp_common_len_rate_limit(intel_dp,
1425                                                     intel_dp->max_link_rate);
1426
1427         /* No common link rates between source and sink */
1428         drm_WARN_ON(encoder->base.dev, common_len <= 0);
1429
1430         limits.min_clock = 0;
1431         limits.max_clock = common_len - 1;
1432
1433         limits.min_lane_count = 1;
1434         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1435
1436         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1437         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1438
1439         if (intel_dp->use_max_params) {
1440                 /*
1441                  * Use the maximum clock and number of lanes the eDP panel
1442                  * advertizes being capable of in case the initial fast
1443                  * optimal params failed us. The panels are generally
1444                  * designed to support only a single clock and lane
1445                  * configuration, and typically on older panels these
1446                  * values correspond to the native resolution of the panel.
1447                  */
1448                 limits.min_lane_count = limits.max_lane_count;
1449                 limits.min_clock = limits.max_clock;
1450         }
1451
1452         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1453
1454         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1455                     "max rate %d max bpp %d pixel clock %iKHz\n",
1456                     limits.max_lane_count,
1457                     intel_dp->common_rates[limits.max_clock],
1458                     limits.max_bpp, adjusted_mode->crtc_clock);
1459
1460         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1461              adjusted_mode->crtc_hdisplay > 5120) &&
1462             intel_dp_can_bigjoiner(intel_dp))
1463                 pipe_config->bigjoiner = true;
1464
1465         if (intel_dp_is_edp(intel_dp))
1466                 /*
1467                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
1468                  * section A.1: "It is recommended that the minimum number of
1469                  * lanes be used, using the minimum link rate allowed for that
1470                  * lane configuration."
1471                  *
1472                  * Note that we fall back to the max clock and lane count for eDP
1473                  * panels that fail with the fast optimal settings (see
1474                  * intel_dp->use_max_params), in which case the fast vs. wide
1475                  * choice doesn't matter.
1476                  */
1477                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
1478         else
1479                 /* Optimize for slow and wide. */
1480                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1481
1482         /* enable compression if the mode doesn't fit available BW */
1483         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1484         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
1485                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1486                                                   conn_state, &limits);
1487                 if (ret < 0)
1488                         return ret;
1489         }
1490
1491         if (pipe_config->dsc.compression_enable) {
1492                 drm_dbg_kms(&i915->drm,
1493                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1494                             pipe_config->lane_count, pipe_config->port_clock,
1495                             pipe_config->pipe_bpp,
1496                             pipe_config->dsc.compressed_bpp);
1497
1498                 drm_dbg_kms(&i915->drm,
1499                             "DP link rate required %i available %i\n",
1500                             intel_dp_link_required(adjusted_mode->crtc_clock,
1501                                                    pipe_config->dsc.compressed_bpp),
1502                             intel_dp_max_data_rate(pipe_config->port_clock,
1503                                                    pipe_config->lane_count));
1504         } else {
1505                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1506                             pipe_config->lane_count, pipe_config->port_clock,
1507                             pipe_config->pipe_bpp);
1508
1509                 drm_dbg_kms(&i915->drm,
1510                             "DP link rate required %i available %i\n",
1511                             intel_dp_link_required(adjusted_mode->crtc_clock,
1512                                                    pipe_config->pipe_bpp),
1513                             intel_dp_max_data_rate(pipe_config->port_clock,
1514                                                    pipe_config->lane_count));
1515         }
1516         return 0;
1517 }
1518
1519 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1520                                   const struct drm_connector_state *conn_state)
1521 {
1522         const struct intel_digital_connector_state *intel_conn_state =
1523                 to_intel_digital_connector_state(conn_state);
1524         const struct drm_display_mode *adjusted_mode =
1525                 &crtc_state->hw.adjusted_mode;
1526
1527         /*
1528          * Our YCbCr output is always limited range.
1529          * crtc_state->limited_color_range only applies to RGB,
1530          * and it must never be set for YCbCr or we risk setting
1531          * some conflicting bits in PIPECONF which will mess up
1532          * the colors on the monitor.
1533          */
1534         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1535                 return false;
1536
1537         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1538                 /*
1539                  * See:
1540                  * CEA-861-E - 5.1 Default Encoding Parameters
1541                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1542                  */
1543                 return crtc_state->pipe_bpp != 18 &&
1544                         drm_default_rgb_quant_range(adjusted_mode) ==
1545                         HDMI_QUANTIZATION_RANGE_LIMITED;
1546         } else {
1547                 return intel_conn_state->broadcast_rgb ==
1548                         INTEL_BROADCAST_RGB_LIMITED;
1549         }
1550 }
1551
1552 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1553                                     enum port port)
1554 {
1555         if (IS_G4X(dev_priv))
1556                 return false;
1557         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
1558                 return false;
1559
1560         return true;
1561 }
1562
1563 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1564                                              const struct drm_connector_state *conn_state,
1565                                              struct drm_dp_vsc_sdp *vsc)
1566 {
1567         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1568         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1569
1570         /*
1571          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1572          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1573          * Colorimetry Format indication.
1574          */
1575         vsc->revision = 0x5;
1576         vsc->length = 0x13;
1577
1578         /* DP 1.4a spec, Table 2-120 */
1579         switch (crtc_state->output_format) {
1580         case INTEL_OUTPUT_FORMAT_YCBCR444:
1581                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1582                 break;
1583         case INTEL_OUTPUT_FORMAT_YCBCR420:
1584                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1585                 break;
1586         case INTEL_OUTPUT_FORMAT_RGB:
1587         default:
1588                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1589         }
1590
1591         switch (conn_state->colorspace) {
1592         case DRM_MODE_COLORIMETRY_BT709_YCC:
1593                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1594                 break;
1595         case DRM_MODE_COLORIMETRY_XVYCC_601:
1596                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1597                 break;
1598         case DRM_MODE_COLORIMETRY_XVYCC_709:
1599                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1600                 break;
1601         case DRM_MODE_COLORIMETRY_SYCC_601:
1602                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1603                 break;
1604         case DRM_MODE_COLORIMETRY_OPYCC_601:
1605                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1606                 break;
1607         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1608                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1609                 break;
1610         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1611                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1612                 break;
1613         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1614                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1615                 break;
1616         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1617         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1618                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1619                 break;
1620         default:
1621                 /*
1622                  * RGB->YCBCR color conversion uses the BT.709
1623                  * color space.
1624                  */
1625                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1626                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1627                 else
1628                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1629                 break;
1630         }
1631
1632         vsc->bpc = crtc_state->pipe_bpp / 3;
1633
1634         /* only RGB pixelformat supports 6 bpc */
1635         drm_WARN_ON(&dev_priv->drm,
1636                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1637
1638         /* all YCbCr are always limited range */
1639         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1640         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1641 }
1642
1643 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1644                                      struct intel_crtc_state *crtc_state,
1645                                      const struct drm_connector_state *conn_state)
1646 {
1647         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1648
1649         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1650         if (crtc_state->has_psr)
1651                 return;
1652
1653         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1654                 return;
1655
1656         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1657         vsc->sdp_type = DP_SDP_VSC;
1658         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1659                                          &crtc_state->infoframes.vsc);
1660 }
1661
1662 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1663                                   const struct intel_crtc_state *crtc_state,
1664                                   const struct drm_connector_state *conn_state,
1665                                   struct drm_dp_vsc_sdp *vsc)
1666 {
1667         vsc->sdp_type = DP_SDP_VSC;
1668
1669         if (intel_dp->psr.psr2_enabled) {
1670                 if (intel_dp->psr.colorimetry_support &&
1671                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1672                         /* [PSR2, +Colorimetry] */
1673                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1674                                                          vsc);
1675                 } else {
1676                         /*
1677                          * [PSR2, -Colorimetry]
1678                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1679                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1680                          */
1681                         vsc->revision = 0x4;
1682                         vsc->length = 0xe;
1683                 }
1684         } else {
1685                 /*
1686                  * [PSR1]
1687                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1688                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1689                  * higher).
1690                  */
1691                 vsc->revision = 0x2;
1692                 vsc->length = 0x8;
1693         }
1694 }
1695
1696 static void
1697 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1698                                             struct intel_crtc_state *crtc_state,
1699                                             const struct drm_connector_state *conn_state)
1700 {
1701         int ret;
1702         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1703         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1704
1705         if (!conn_state->hdr_output_metadata)
1706                 return;
1707
1708         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1709
1710         if (ret) {
1711                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1712                 return;
1713         }
1714
1715         crtc_state->infoframes.enable |=
1716                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1717 }
1718
1719 static void
1720 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1721                              struct intel_crtc_state *pipe_config,
1722                              int output_bpp, bool constant_n)
1723 {
1724         struct intel_connector *intel_connector = intel_dp->attached_connector;
1725         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1726
1727         if (pipe_config->vrr.enable)
1728                 return;
1729
1730         /*
1731          * DRRS and PSR can't be enable together, so giving preference to PSR
1732          * as it allows more power-savings by complete shutting down display,
1733          * so to guarantee this, intel_dp_drrs_compute_config() must be called
1734          * after intel_psr_compute_config().
1735          */
1736         if (pipe_config->has_psr)
1737                 return;
1738
1739         if (!intel_connector->panel.downclock_mode ||
1740             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1741                 return;
1742
1743         pipe_config->has_drrs = true;
1744         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
1745                                intel_connector->panel.downclock_mode->clock,
1746                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1747                                constant_n, pipe_config->fec_enable);
1748 }
1749
1750 int
1751 intel_dp_compute_config(struct intel_encoder *encoder,
1752                         struct intel_crtc_state *pipe_config,
1753                         struct drm_connector_state *conn_state)
1754 {
1755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1756         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1757         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1758         enum port port = encoder->port;
1759         struct intel_connector *intel_connector = intel_dp->attached_connector;
1760         struct intel_digital_connector_state *intel_conn_state =
1761                 to_intel_digital_connector_state(conn_state);
1762         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1763         int ret = 0, output_bpp;
1764
1765         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1766                 pipe_config->has_pch_encoder = true;
1767
1768         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1769                                                             adjusted_mode);
1770
1771         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1772                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1773                 if (ret)
1774                         return ret;
1775         }
1776
1777         if (!intel_dp_port_has_audio(dev_priv, port))
1778                 pipe_config->has_audio = false;
1779         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1780                 pipe_config->has_audio = intel_dp->has_audio;
1781         else
1782                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1783
1784         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1785                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1786                                        adjusted_mode);
1787
1788                 if (HAS_GMCH(dev_priv))
1789                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1790                 else
1791                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
1792                 if (ret)
1793                         return ret;
1794         }
1795
1796         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1797                 return -EINVAL;
1798
1799         if (HAS_GMCH(dev_priv) &&
1800             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1801                 return -EINVAL;
1802
1803         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1804                 return -EINVAL;
1805
1806         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1807                 return -EINVAL;
1808
1809         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1810         if (ret < 0)
1811                 return ret;
1812
1813         pipe_config->limited_color_range =
1814                 intel_dp_limited_color_range(pipe_config, conn_state);
1815
1816         if (pipe_config->dsc.compression_enable)
1817                 output_bpp = pipe_config->dsc.compressed_bpp;
1818         else
1819                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1820                                                  pipe_config->pipe_bpp);
1821
1822         intel_link_compute_m_n(output_bpp,
1823                                pipe_config->lane_count,
1824                                adjusted_mode->crtc_clock,
1825                                pipe_config->port_clock,
1826                                &pipe_config->dp_m_n,
1827                                constant_n, pipe_config->fec_enable);
1828
1829         if (!HAS_DDI(dev_priv))
1830                 intel_dp_set_clock(encoder, pipe_config);
1831
1832         intel_vrr_compute_config(pipe_config, conn_state);
1833         intel_psr_compute_config(intel_dp, pipe_config);
1834         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1835                                      constant_n);
1836         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1837         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1838
1839         return 0;
1840 }
1841
1842 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1843                               int link_rate, int lane_count)
1844 {
1845         intel_dp->link_trained = false;
1846         intel_dp->link_rate = link_rate;
1847         intel_dp->lane_count = lane_count;
1848 }
1849
1850 static void intel_dp_prepare(struct intel_encoder *encoder,
1851                              const struct intel_crtc_state *pipe_config)
1852 {
1853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1854         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1855         enum port port = encoder->port;
1856         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1857         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1858
1859         intel_dp_set_link_params(intel_dp,
1860                                  pipe_config->port_clock,
1861                                  pipe_config->lane_count);
1862
1863         /*
1864          * There are four kinds of DP registers:
1865          *
1866          *      IBX PCH
1867          *      SNB CPU
1868          *      IVB CPU
1869          *      CPT PCH
1870          *
1871          * IBX PCH and CPU are the same for almost everything,
1872          * except that the CPU DP PLL is configured in this
1873          * register
1874          *
1875          * CPT PCH is quite different, having many bits moved
1876          * to the TRANS_DP_CTL register instead. That
1877          * configuration happens (oddly) in ilk_pch_enable
1878          */
1879
1880         /* Preserve the BIOS-computed detected bit. This is
1881          * supposed to be read-only.
1882          */
1883         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
1884
1885         /* Handle DP bits in common between all three register formats */
1886         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1887         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1888
1889         /* Split out the IBX/CPU vs CPT settings */
1890
1891         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1892                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1893                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1894                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1895                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1896                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1897
1898                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1899                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1900
1901                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
1902         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1903                 u32 trans_dp;
1904
1905                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1906
1907                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
1908                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1909                         trans_dp |= TRANS_DP_ENH_FRAMING;
1910                 else
1911                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1912                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
1913         } else {
1914                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1915                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1916
1917                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1918                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1919                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1920                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1921                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1922
1923                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1924                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1925
1926                 if (IS_CHERRYVIEW(dev_priv))
1927                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
1928                 else
1929                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
1930         }
1931 }
1932
1933
1934 /* Enable backlight PWM and backlight PP control. */
1935 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1936                             const struct drm_connector_state *conn_state)
1937 {
1938         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1939         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1940
1941         if (!intel_dp_is_edp(intel_dp))
1942                 return;
1943
1944         drm_dbg_kms(&i915->drm, "\n");
1945
1946         intel_panel_enable_backlight(crtc_state, conn_state);
1947         intel_pps_backlight_on(intel_dp);
1948 }
1949
1950 /* Disable backlight PP control and backlight PWM. */
1951 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1952 {
1953         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1954         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1955
1956         if (!intel_dp_is_edp(intel_dp))
1957                 return;
1958
1959         drm_dbg_kms(&i915->drm, "\n");
1960
1961         intel_pps_backlight_off(intel_dp);
1962         intel_panel_disable_backlight(old_conn_state);
1963 }
1964
1965 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
1966 {
1967         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1968         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1969         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
1970
1971         I915_STATE_WARN(cur_state != state,
1972                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
1973                         dig_port->base.base.base.id, dig_port->base.base.name,
1974                         onoff(state), onoff(cur_state));
1975 }
1976 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
1977
1978 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
1979 {
1980         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
1981
1982         I915_STATE_WARN(cur_state != state,
1983                         "eDP PLL state assertion failure (expected %s, current %s)\n",
1984                         onoff(state), onoff(cur_state));
1985 }
1986 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
1987 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
1988
1989 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
1990                            const struct intel_crtc_state *pipe_config)
1991 {
1992         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1993         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1994
1995         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1996         assert_dp_port_disabled(intel_dp);
1997         assert_edp_pll_disabled(dev_priv);
1998
1999         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
2000                     pipe_config->port_clock);
2001
2002         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2003
2004         if (pipe_config->port_clock == 162000)
2005                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2006         else
2007                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2008
2009         intel_de_write(dev_priv, DP_A, intel_dp->DP);
2010         intel_de_posting_read(dev_priv, DP_A);
2011         udelay(500);
2012
2013         /*
2014          * [DevILK] Work around required when enabling DP PLL
2015          * while a pipe is enabled going to FDI:
2016          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2017          * 2. Program DP PLL enable
2018          */
2019         if (IS_GEN(dev_priv, 5))
2020                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2021
2022         intel_dp->DP |= DP_PLL_ENABLE;
2023
2024         intel_de_write(dev_priv, DP_A, intel_dp->DP);
2025         intel_de_posting_read(dev_priv, DP_A);
2026         udelay(200);
2027 }
2028
2029 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
2030                             const struct intel_crtc_state *old_crtc_state)
2031 {
2032         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2033         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2034
2035         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2036         assert_dp_port_disabled(intel_dp);
2037         assert_edp_pll_enabled(dev_priv);
2038
2039         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
2040
2041         intel_dp->DP &= ~DP_PLL_ENABLE;
2042
2043         intel_de_write(dev_priv, DP_A, intel_dp->DP);
2044         intel_de_posting_read(dev_priv, DP_A);
2045         udelay(200);
2046 }
2047
2048 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2049 {
2050         /*
2051          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2052          * be capable of signalling downstream hpd with a long pulse.
2053          * Whether or not that means D3 is safe to use is not clear,
2054          * but let's assume so until proven otherwise.
2055          *
2056          * FIXME should really check all downstream ports...
2057          */
2058         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2059                 drm_dp_is_branch(intel_dp->dpcd) &&
2060                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2061 }
2062
2063 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2064                                            const struct intel_crtc_state *crtc_state,
2065                                            bool enable)
2066 {
2067         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2068         int ret;
2069
2070         if (!crtc_state->dsc.compression_enable)
2071                 return;
2072
2073         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2074                                  enable ? DP_DECOMPRESSION_EN : 0);
2075         if (ret < 0)
2076                 drm_dbg_kms(&i915->drm,
2077                             "Failed to %s sink decompression state\n",
2078                             enable ? "enable" : "disable");
2079 }
2080
2081 static void
2082 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2083 {
2084         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085         u8 oui[] = { 0x00, 0xaa, 0x01 };
2086         u8 buf[3] = { 0 };
2087
2088         /*
2089          * During driver init, we want to be careful and avoid changing the source OUI if it's
2090          * already set to what we want, so as to avoid clearing any state by accident
2091          */
2092         if (careful) {
2093                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2094                         drm_err(&i915->drm, "Failed to read source OUI\n");
2095
2096                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2097                         return;
2098         }
2099
2100         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2101                 drm_err(&i915->drm, "Failed to write source OUI\n");
2102 }
2103
2104 /* If the device supports it, try to set the power state appropriately */
2105 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2106 {
2107         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2108         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2109         int ret, i;
2110
2111         /* Should have a valid DPCD by this point */
2112         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2113                 return;
2114
2115         if (mode != DP_SET_POWER_D0) {
2116                 if (downstream_hpd_needs_d0(intel_dp))
2117                         return;
2118
2119                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2120         } else {
2121                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2122
2123                 lspcon_resume(dp_to_dig_port(intel_dp));
2124
2125                 /* Write the source OUI as early as possible */
2126                 if (intel_dp_is_edp(intel_dp))
2127                         intel_edp_init_source_oui(intel_dp, false);
2128
2129                 /*
2130                  * When turning on, we need to retry for 1ms to give the sink
2131                  * time to wake up.
2132                  */
2133                 for (i = 0; i < 3; i++) {
2134                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2135                         if (ret == 1)
2136                                 break;
2137                         msleep(1);
2138                 }
2139
2140                 if (ret == 1 && lspcon->active)
2141                         lspcon_wait_pcon_mode(lspcon);
2142         }
2143
2144         if (ret != 1)
2145                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2146                             encoder->base.base.id, encoder->base.name,
2147                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2148 }
2149
2150 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2151                                  enum port port, enum pipe *pipe)
2152 {
2153         enum pipe p;
2154
2155         for_each_pipe(dev_priv, p) {
2156                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
2157
2158                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2159                         *pipe = p;
2160                         return true;
2161                 }
2162         }
2163
2164         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
2165                     port_name(port));
2166
2167         /* must initialize pipe to something for the asserts */
2168         *pipe = PIPE_A;
2169
2170         return false;
2171 }
2172
2173 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2174                            i915_reg_t dp_reg, enum port port,
2175                            enum pipe *pipe)
2176 {
2177         bool ret;
2178         u32 val;
2179
2180         val = intel_de_read(dev_priv, dp_reg);
2181
2182         ret = val & DP_PORT_EN;
2183
2184         /* asserts want to know the pipe even if the port is disabled */
2185         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2186                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2187         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2188                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2189         else if (IS_CHERRYVIEW(dev_priv))
2190                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2191         else
2192                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2193
2194         return ret;
2195 }
2196
2197 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2198                                   enum pipe *pipe)
2199 {
2200         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2201         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2202         intel_wakeref_t wakeref;
2203         bool ret;
2204
2205         wakeref = intel_display_power_get_if_enabled(dev_priv,
2206                                                      encoder->power_domain);
2207         if (!wakeref)
2208                 return false;
2209
2210         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2211                                     encoder->port, pipe);
2212
2213         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2214
2215         return ret;
2216 }
2217
2218 static void intel_dp_get_config(struct intel_encoder *encoder,
2219                                 struct intel_crtc_state *pipe_config)
2220 {
2221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2222         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2223         u32 tmp, flags = 0;
2224         enum port port = encoder->port;
2225         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2226
2227         if (encoder->type == INTEL_OUTPUT_EDP)
2228                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2229         else
2230                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2231
2232         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
2233
2234         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2235
2236         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2237                 u32 trans_dp = intel_de_read(dev_priv,
2238                                              TRANS_DP_CTL(crtc->pipe));
2239
2240                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2241                         flags |= DRM_MODE_FLAG_PHSYNC;
2242                 else
2243                         flags |= DRM_MODE_FLAG_NHSYNC;
2244
2245                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2246                         flags |= DRM_MODE_FLAG_PVSYNC;
2247                 else
2248                         flags |= DRM_MODE_FLAG_NVSYNC;
2249         } else {
2250                 if (tmp & DP_SYNC_HS_HIGH)
2251                         flags |= DRM_MODE_FLAG_PHSYNC;
2252                 else
2253                         flags |= DRM_MODE_FLAG_NHSYNC;
2254
2255                 if (tmp & DP_SYNC_VS_HIGH)
2256                         flags |= DRM_MODE_FLAG_PVSYNC;
2257                 else
2258                         flags |= DRM_MODE_FLAG_NVSYNC;
2259         }
2260
2261         pipe_config->hw.adjusted_mode.flags |= flags;
2262
2263         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2264                 pipe_config->limited_color_range = true;
2265
2266         pipe_config->lane_count =
2267                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2268
2269         intel_dp_get_m_n(crtc, pipe_config);
2270
2271         if (port == PORT_A) {
2272                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2273                         pipe_config->port_clock = 162000;
2274                 else
2275                         pipe_config->port_clock = 270000;
2276         }
2277
2278         pipe_config->hw.adjusted_mode.crtc_clock =
2279                 intel_dotclock_calculate(pipe_config->port_clock,
2280                                          &pipe_config->dp_m_n);
2281
2282         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2283             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2284                 /*
2285                  * This is a big fat ugly hack.
2286                  *
2287                  * Some machines in UEFI boot mode provide us a VBT that has 18
2288                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2289                  * unknown we fail to light up. Yet the same BIOS boots up with
2290                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2291                  * max, not what it tells us to use.
2292                  *
2293                  * Note: This will still be broken if the eDP panel is not lit
2294                  * up by the BIOS, and thus we can't get the mode at module
2295                  * load.
2296                  */
2297                 drm_dbg_kms(&dev_priv->drm,
2298                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2299                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2300                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2301         }
2302 }
2303
2304 static bool
2305 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2306
2307 /**
2308  * intel_dp_sync_state - sync the encoder state during init/resume
2309  * @encoder: intel encoder to sync
2310  * @crtc_state: state for the CRTC connected to the encoder
2311  *
2312  * Sync any state stored in the encoder wrt. HW state during driver init
2313  * and system resume.
2314  */
2315 void intel_dp_sync_state(struct intel_encoder *encoder,
2316                          const struct intel_crtc_state *crtc_state)
2317 {
2318         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2319
2320         /*
2321          * Don't clobber DPCD if it's been already read out during output
2322          * setup (eDP) or detect.
2323          */
2324         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2325                 intel_dp_get_dpcd(intel_dp);
2326
2327         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2328         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2329 }
2330
2331 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2332                                     struct intel_crtc_state *crtc_state)
2333 {
2334         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2335         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2336
2337         /*
2338          * If BIOS has set an unsupported or non-standard link rate for some
2339          * reason force an encoder recompute and full modeset.
2340          */
2341         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2342                                 crtc_state->port_clock) < 0) {
2343                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2344                 crtc_state->uapi.connectors_changed = true;
2345                 return false;
2346         }
2347
2348         /*
2349          * FIXME hack to force full modeset when DSC is being used.
2350          *
2351          * As long as we do not have full state readout and config comparison
2352          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2353          * Remove once we have readout for DSC.
2354          */
2355         if (crtc_state->dsc.compression_enable) {
2356                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2357                 crtc_state->uapi.mode_changed = true;
2358                 return false;
2359         }
2360
2361         if (CAN_PSR(intel_dp)) {
2362                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2363                 crtc_state->uapi.mode_changed = true;
2364                 return false;
2365         }
2366
2367         return true;
2368 }
2369
2370 static void intel_disable_dp(struct intel_atomic_state *state,
2371                              struct intel_encoder *encoder,
2372                              const struct intel_crtc_state *old_crtc_state,
2373                              const struct drm_connector_state *old_conn_state)
2374 {
2375         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2376
2377         intel_dp->link_trained = false;
2378
2379         if (old_crtc_state->has_audio)
2380                 intel_audio_codec_disable(encoder,
2381                                           old_crtc_state, old_conn_state);
2382
2383         /* Make sure the panel is off before trying to change the mode. But also
2384          * ensure that we have vdd while we switch off the panel. */
2385         intel_pps_vdd_on(intel_dp);
2386         intel_edp_backlight_off(old_conn_state);
2387         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2388         intel_pps_off(intel_dp);
2389         intel_dp->frl.is_trained = false;
2390         intel_dp->frl.trained_rate_gbps = 0;
2391 }
2392
2393 static void g4x_disable_dp(struct intel_atomic_state *state,
2394                            struct intel_encoder *encoder,
2395                            const struct intel_crtc_state *old_crtc_state,
2396                            const struct drm_connector_state *old_conn_state)
2397 {
2398         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
2399 }
2400
2401 static void vlv_disable_dp(struct intel_atomic_state *state,
2402                            struct intel_encoder *encoder,
2403                            const struct intel_crtc_state *old_crtc_state,
2404                            const struct drm_connector_state *old_conn_state)
2405 {
2406         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
2407 }
2408
2409 static void g4x_post_disable_dp(struct intel_atomic_state *state,
2410                                 struct intel_encoder *encoder,
2411                                 const struct intel_crtc_state *old_crtc_state,
2412                                 const struct drm_connector_state *old_conn_state)
2413 {
2414         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2415         enum port port = encoder->port;
2416
2417         /*
2418          * Bspec does not list a specific disable sequence for g4x DP.
2419          * Follow the ilk+ sequence (disable pipe before the port) for
2420          * g4x DP as it does not suffer from underruns like the normal
2421          * g4x modeset sequence (disable pipe after the port).
2422          */
2423         intel_dp_link_down(encoder, old_crtc_state);
2424
2425         /* Only ilk+ has port A */
2426         if (port == PORT_A)
2427                 ilk_edp_pll_off(intel_dp, old_crtc_state);
2428 }
2429
2430 static void vlv_post_disable_dp(struct intel_atomic_state *state,
2431                                 struct intel_encoder *encoder,
2432                                 const struct intel_crtc_state *old_crtc_state,
2433                                 const struct drm_connector_state *old_conn_state)
2434 {
2435         intel_dp_link_down(encoder, old_crtc_state);
2436 }
2437
2438 static void chv_post_disable_dp(struct intel_atomic_state *state,
2439                                 struct intel_encoder *encoder,
2440                                 const struct intel_crtc_state *old_crtc_state,
2441                                 const struct drm_connector_state *old_conn_state)
2442 {
2443         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2444
2445         intel_dp_link_down(encoder, old_crtc_state);
2446
2447         vlv_dpio_get(dev_priv);
2448
2449         /* Assert data lane reset */
2450         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2451
2452         vlv_dpio_put(dev_priv);
2453 }
2454
2455 static void
2456 cpt_set_link_train(struct intel_dp *intel_dp,
2457                    const struct intel_crtc_state *crtc_state,
2458                    u8 dp_train_pat)
2459 {
2460         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2461         u32 *DP = &intel_dp->DP;
2462
2463         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2464
2465         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
2466         case DP_TRAINING_PATTERN_DISABLE:
2467                 *DP |= DP_LINK_TRAIN_OFF_CPT;
2468                 break;
2469         case DP_TRAINING_PATTERN_1:
2470                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2471                 break;
2472         case DP_TRAINING_PATTERN_2:
2473                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2474                 break;
2475         case DP_TRAINING_PATTERN_3:
2476                 drm_dbg_kms(&dev_priv->drm,
2477                             "TPS3 not supported, using TPS2 instead\n");
2478                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2479                 break;
2480         }
2481
2482         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2483         intel_de_posting_read(dev_priv, intel_dp->output_reg);
2484 }
2485
2486 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2487 {
2488         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2489
2490         /* Clear the cached register set to avoid using stale values */
2491
2492         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2493
2494         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2495                              intel_dp->pcon_dsc_dpcd,
2496                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2497                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2498                         DP_PCON_DSC_ENCODER);
2499
2500         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2501                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2502 }
2503
2504 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2505 {
2506         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2507         int i;
2508
2509         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2510                 if (frl_bw_mask & (1 << i))
2511                         return bw_gbps[i];
2512         }
2513         return 0;
2514 }
2515
2516 static int intel_dp_pcon_set_frl_mask(int max_frl)
2517 {
2518         switch (max_frl) {
2519         case 48:
2520                 return DP_PCON_FRL_BW_MASK_48GBPS;
2521         case 40:
2522                 return DP_PCON_FRL_BW_MASK_40GBPS;
2523         case 32:
2524                 return DP_PCON_FRL_BW_MASK_32GBPS;
2525         case 24:
2526                 return DP_PCON_FRL_BW_MASK_24GBPS;
2527         case 18:
2528                 return DP_PCON_FRL_BW_MASK_18GBPS;
2529         case 9:
2530                 return DP_PCON_FRL_BW_MASK_9GBPS;
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2537 {
2538         struct intel_connector *intel_connector = intel_dp->attached_connector;
2539         struct drm_connector *connector = &intel_connector->base;
2540         int max_frl_rate;
2541         int max_lanes, rate_per_lane;
2542         int max_dsc_lanes, dsc_rate_per_lane;
2543
2544         max_lanes = connector->display_info.hdmi.max_lanes;
2545         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2546         max_frl_rate = max_lanes * rate_per_lane;
2547
2548         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2549                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2550                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2551                 if (max_dsc_lanes && dsc_rate_per_lane)
2552                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2553         }
2554
2555         return max_frl_rate;
2556 }
2557
2558 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2559 {
2560 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
2561 #define PCON_CONCURRENT_MODE (1 > 0)
2562 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
2563 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
2564 #define TIMEOUT_FRL_READY_MS 500
2565 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2566
2567         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2568         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2569         u8 max_frl_bw_mask = 0, frl_trained_mask;
2570         bool is_active;
2571
2572         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2573         if (ret < 0)
2574                 return ret;
2575
2576         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2577         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2578
2579         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2580         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2581
2582         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2583
2584         if (max_frl_bw <= 0)
2585                 return -EINVAL;
2586
2587         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2588         if (ret < 0)
2589                 return ret;
2590         /* Wait for PCON to be FRL Ready */
2591         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2592
2593         if (!is_active)
2594                 return -ETIMEDOUT;
2595
2596         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2597         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
2598         if (ret < 0)
2599                 return ret;
2600         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
2601         if (ret < 0)
2602                 return ret;
2603         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2604         if (ret < 0)
2605                 return ret;
2606         /*
2607          * Wait for FRL to be completed
2608          * Check if the HDMI Link is up and active.
2609          */
2610         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2611
2612         if (!is_active)
2613                 return -ETIMEDOUT;
2614
2615         /* Verify HDMI Link configuration shows FRL Mode */
2616         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2617             DP_PCON_HDMI_MODE_FRL) {
2618                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2619                 return -EINVAL;
2620         }
2621         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2622
2623         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2624         intel_dp->frl.is_trained = true;
2625         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2626
2627         return 0;
2628 }
2629
2630 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2631 {
2632         if (drm_dp_is_branch(intel_dp->dpcd) &&
2633             intel_dp->has_hdmi_sink &&
2634             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2635                 return true;
2636
2637         return false;
2638 }
2639
2640 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2641 {
2642         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2643
2644         /* Always go for FRL training if supported */
2645         if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2646             intel_dp->frl.is_trained)
2647                 return;
2648
2649         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2650                 int ret, mode;
2651
2652                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2653                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2654                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2655
2656                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2657                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2658         } else {
2659                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2660         }
2661 }
2662
2663 static int
2664 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2665 {
2666         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2667
2668         return intel_hdmi_dsc_get_slice_height(vactive);
2669 }
2670
2671 static int
2672 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2673                              const struct intel_crtc_state *crtc_state)
2674 {
2675         struct intel_connector *intel_connector = intel_dp->attached_connector;
2676         struct drm_connector *connector = &intel_connector->base;
2677         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2678         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2679         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2680         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2681
2682         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2683                                              pcon_max_slice_width,
2684                                              hdmi_max_slices, hdmi_throughput);
2685 }
2686
2687 static int
2688 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2689                           const struct intel_crtc_state *crtc_state,
2690                           int num_slices, int slice_width)
2691 {
2692         struct intel_connector *intel_connector = intel_dp->attached_connector;
2693         struct drm_connector *connector = &intel_connector->base;
2694         int output_format = crtc_state->output_format;
2695         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2696         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2697         int hdmi_max_chunk_bytes =
2698                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2699
2700         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2701                                       num_slices, output_format, hdmi_all_bpp,
2702                                       hdmi_max_chunk_bytes);
2703 }
2704
2705 void
2706 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2707                             const struct intel_crtc_state *crtc_state)
2708 {
2709         u8 pps_param[6];
2710         int slice_height;
2711         int slice_width;
2712         int num_slices;
2713         int bits_per_pixel;
2714         int ret;
2715         struct intel_connector *intel_connector = intel_dp->attached_connector;
2716         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2717         struct drm_connector *connector;
2718         bool hdmi_is_dsc_1_2;
2719
2720         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2721                 return;
2722
2723         if (!intel_connector)
2724                 return;
2725         connector = &intel_connector->base;
2726         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2727
2728         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2729             !hdmi_is_dsc_1_2)
2730                 return;
2731
2732         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2733         if (!slice_height)
2734                 return;
2735
2736         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2737         if (!num_slices)
2738                 return;
2739
2740         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2741                                    num_slices);
2742
2743         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2744                                                    num_slices, slice_width);
2745         if (!bits_per_pixel)
2746                 return;
2747
2748         pps_param[0] = slice_height & 0xFF;
2749         pps_param[1] = slice_height >> 8;
2750         pps_param[2] = slice_width & 0xFF;
2751         pps_param[3] = slice_width >> 8;
2752         pps_param[4] = bits_per_pixel & 0xFF;
2753         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2754
2755         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2756         if (ret < 0)
2757                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2758 }
2759
2760 static void
2761 g4x_set_link_train(struct intel_dp *intel_dp,
2762                    const struct intel_crtc_state *crtc_state,
2763                    u8 dp_train_pat)
2764 {
2765         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2766         u32 *DP = &intel_dp->DP;
2767
2768         *DP &= ~DP_LINK_TRAIN_MASK;
2769
2770         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
2771         case DP_TRAINING_PATTERN_DISABLE:
2772                 *DP |= DP_LINK_TRAIN_OFF;
2773                 break;
2774         case DP_TRAINING_PATTERN_1:
2775                 *DP |= DP_LINK_TRAIN_PAT_1;
2776                 break;
2777         case DP_TRAINING_PATTERN_2:
2778                 *DP |= DP_LINK_TRAIN_PAT_2;
2779                 break;
2780         case DP_TRAINING_PATTERN_3:
2781                 drm_dbg_kms(&dev_priv->drm,
2782                             "TPS3 not supported, using TPS2 instead\n");
2783                 *DP |= DP_LINK_TRAIN_PAT_2;
2784                 break;
2785         }
2786
2787         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2788         intel_de_posting_read(dev_priv, intel_dp->output_reg);
2789 }
2790
2791 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2792                                  const struct intel_crtc_state *crtc_state)
2793 {
2794         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2795
2796         /* enable with pattern 1 (as per spec) */
2797
2798         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
2799                                                DP_TRAINING_PATTERN_1);
2800
2801         /*
2802          * Magic for VLV/CHV. We _must_ first set up the register
2803          * without actually enabling the port, and then do another
2804          * write to enable the port. Otherwise link training will
2805          * fail when the power sequencer is freshly used for this port.
2806          */
2807         intel_dp->DP |= DP_PORT_EN;
2808         if (crtc_state->has_audio)
2809                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2810
2811         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2812         intel_de_posting_read(dev_priv, intel_dp->output_reg);
2813 }
2814
2815 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2816                                            const struct intel_crtc_state *crtc_state)
2817 {
2818         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2819         u8 tmp;
2820
2821         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2822                 return;
2823
2824         if (!drm_dp_is_branch(intel_dp->dpcd))
2825                 return;
2826
2827         tmp = intel_dp->has_hdmi_sink ?
2828                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2829
2830         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2831                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2832                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
2833                             enableddisabled(intel_dp->has_hdmi_sink));
2834
2835         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2836                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2837
2838         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2839                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2840                 drm_dbg_kms(&i915->drm,
2841                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
2842                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
2843
2844         tmp = 0;
2845         if (intel_dp->dfp.rgb_to_ycbcr) {
2846                 bool bt2020, bt709;
2847
2848                 /*
2849                  * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2850                  * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2851                  *
2852                  */
2853                 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2854
2855                 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2856                                                                    intel_dp->downstream_ports,
2857                                                                    DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2858                 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2859                                                                   intel_dp->downstream_ports,
2860                                                                   DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2861                 switch (crtc_state->infoframes.vsc.colorimetry) {
2862                 case DP_COLORIMETRY_BT2020_RGB:
2863                 case DP_COLORIMETRY_BT2020_YCC:
2864                         if (bt2020)
2865                                 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2866                         break;
2867                 case DP_COLORIMETRY_BT709_YCC:
2868                 case DP_COLORIMETRY_XVYCC_709:
2869                         if (bt709)
2870                                 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2871                         break;
2872                 default:
2873                         break;
2874                 }
2875         }
2876
2877         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2878                 drm_dbg_kms(&i915->drm,
2879                            "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
2880                            enableddisabled(tmp ? true : false));
2881 }
2882
2883 static void intel_enable_dp(struct intel_atomic_state *state,
2884                             struct intel_encoder *encoder,
2885                             const struct intel_crtc_state *pipe_config,
2886                             const struct drm_connector_state *conn_state)
2887 {
2888         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2889         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2890         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2891         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
2892         enum pipe pipe = crtc->pipe;
2893         intel_wakeref_t wakeref;
2894
2895         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
2896                 return;
2897
2898         with_intel_pps_lock(intel_dp, wakeref) {
2899                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2900                         vlv_pps_init(encoder, pipe_config);
2901
2902                 intel_dp_enable_port(intel_dp, pipe_config);
2903
2904                 intel_pps_vdd_on_unlocked(intel_dp);
2905                 intel_pps_on_unlocked(intel_dp);
2906                 intel_pps_vdd_off_unlocked(intel_dp, true);
2907         }
2908
2909         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2910                 unsigned int lane_mask = 0x0;
2911
2912                 if (IS_CHERRYVIEW(dev_priv))
2913                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2914
2915                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2916                                     lane_mask);
2917         }
2918
2919         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2920         intel_dp_configure_protocol_converter(intel_dp, pipe_config);
2921         intel_dp_check_frl_training(intel_dp);
2922         intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
2923         intel_dp_start_link_train(intel_dp, pipe_config);
2924         intel_dp_stop_link_train(intel_dp, pipe_config);
2925
2926         if (pipe_config->has_audio) {
2927                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
2928                         pipe_name(pipe));
2929                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2930         }
2931 }
2932
2933 static void g4x_enable_dp(struct intel_atomic_state *state,
2934                           struct intel_encoder *encoder,
2935                           const struct intel_crtc_state *pipe_config,
2936                           const struct drm_connector_state *conn_state)
2937 {
2938         intel_enable_dp(state, encoder, pipe_config, conn_state);
2939         intel_edp_backlight_on(pipe_config, conn_state);
2940 }
2941
2942 static void vlv_enable_dp(struct intel_atomic_state *state,
2943                           struct intel_encoder *encoder,
2944                           const struct intel_crtc_state *pipe_config,
2945                           const struct drm_connector_state *conn_state)
2946 {
2947         intel_edp_backlight_on(pipe_config, conn_state);
2948 }
2949
2950 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
2951                               struct intel_encoder *encoder,
2952                               const struct intel_crtc_state *pipe_config,
2953                               const struct drm_connector_state *conn_state)
2954 {
2955         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2956         enum port port = encoder->port;
2957
2958         intel_dp_prepare(encoder, pipe_config);
2959
2960         /* Only ilk+ has port A */
2961         if (port == PORT_A)
2962                 ilk_edp_pll_on(intel_dp, pipe_config);
2963 }
2964
2965 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
2966                               struct intel_encoder *encoder,
2967                               const struct intel_crtc_state *pipe_config,
2968                               const struct drm_connector_state *conn_state)
2969 {
2970         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2971
2972         intel_enable_dp(state, encoder, pipe_config, conn_state);
2973 }
2974
2975 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
2976                                   struct intel_encoder *encoder,
2977                                   const struct intel_crtc_state *pipe_config,
2978                                   const struct drm_connector_state *conn_state)
2979 {
2980         intel_dp_prepare(encoder, pipe_config);
2981
2982         vlv_phy_pre_pll_enable(encoder, pipe_config);
2983 }
2984
2985 static void chv_pre_enable_dp(struct intel_atomic_state *state,
2986                               struct intel_encoder *encoder,
2987                               const struct intel_crtc_state *pipe_config,
2988                               const struct drm_connector_state *conn_state)
2989 {
2990         chv_phy_pre_encoder_enable(encoder, pipe_config);
2991
2992         intel_enable_dp(state, encoder, pipe_config, conn_state);
2993
2994         /* Second common lane will stay alive on its own now */
2995         chv_phy_release_cl2_override(encoder);
2996 }
2997
2998 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
2999                                   struct intel_encoder *encoder,
3000                                   const struct intel_crtc_state *pipe_config,
3001                                   const struct drm_connector_state *conn_state)
3002 {
3003         intel_dp_prepare(encoder, pipe_config);
3004
3005         chv_phy_pre_pll_enable(encoder, pipe_config);
3006 }
3007
3008 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3009                                     struct intel_encoder *encoder,
3010                                     const struct intel_crtc_state *old_crtc_state,
3011                                     const struct drm_connector_state *old_conn_state)
3012 {
3013         chv_phy_post_pll_disable(encoder, old_crtc_state);
3014 }
3015
3016 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
3017                                  const struct intel_crtc_state *crtc_state)
3018 {
3019         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3020 }
3021
3022 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
3023                                  const struct intel_crtc_state *crtc_state)
3024 {
3025         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3026 }
3027
3028 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
3029 {
3030         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3031 }
3032
3033 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
3034 {
3035         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3036 }
3037
3038 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
3039                                   const struct intel_crtc_state *crtc_state)
3040 {
3041         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3042         unsigned long demph_reg_value, preemph_reg_value,
3043                 uniqtranscale_reg_value;
3044         u8 train_set = intel_dp->train_set[0];
3045
3046         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3047         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3048                 preemph_reg_value = 0x0004000;
3049                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3051                         demph_reg_value = 0x2B405555;
3052                         uniqtranscale_reg_value = 0x552AB83A;
3053                         break;
3054                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3055                         demph_reg_value = 0x2B404040;
3056                         uniqtranscale_reg_value = 0x5548B83A;
3057                         break;
3058                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3059                         demph_reg_value = 0x2B245555;
3060                         uniqtranscale_reg_value = 0x5560B83A;
3061                         break;
3062                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3063                         demph_reg_value = 0x2B405555;
3064                         uniqtranscale_reg_value = 0x5598DA3A;
3065                         break;
3066                 default:
3067                         return;
3068                 }
3069                 break;
3070         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3071                 preemph_reg_value = 0x0002000;
3072                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3073                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3074                         demph_reg_value = 0x2B404040;
3075                         uniqtranscale_reg_value = 0x5552B83A;
3076                         break;
3077                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3078                         demph_reg_value = 0x2B404848;
3079                         uniqtranscale_reg_value = 0x5580B83A;
3080                         break;
3081                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3082                         demph_reg_value = 0x2B404040;
3083                         uniqtranscale_reg_value = 0x55ADDA3A;
3084                         break;
3085                 default:
3086                         return;
3087                 }
3088                 break;
3089         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3090                 preemph_reg_value = 0x0000000;
3091                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3092                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3093                         demph_reg_value = 0x2B305555;
3094                         uniqtranscale_reg_value = 0x5570B83A;
3095                         break;
3096                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3097                         demph_reg_value = 0x2B2B4040;
3098                         uniqtranscale_reg_value = 0x55ADDA3A;
3099                         break;
3100                 default:
3101                         return;
3102                 }
3103                 break;
3104         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3105                 preemph_reg_value = 0x0006000;
3106                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3107                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3108                         demph_reg_value = 0x1B405555;
3109                         uniqtranscale_reg_value = 0x55ADDA3A;
3110                         break;
3111                 default:
3112                         return;
3113                 }
3114                 break;
3115         default:
3116                 return;
3117         }
3118
3119         vlv_set_phy_signal_level(encoder, crtc_state,
3120                                  demph_reg_value, preemph_reg_value,
3121                                  uniqtranscale_reg_value, 0);
3122 }
3123
3124 static void chv_set_signal_levels(struct intel_dp *intel_dp,
3125                                   const struct intel_crtc_state *crtc_state)
3126 {
3127         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3128         u32 deemph_reg_value, margin_reg_value;
3129         bool uniq_trans_scale = false;
3130         u8 train_set = intel_dp->train_set[0];
3131
3132         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3133         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3134                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3136                         deemph_reg_value = 128;
3137                         margin_reg_value = 52;
3138                         break;
3139                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3140                         deemph_reg_value = 128;
3141                         margin_reg_value = 77;
3142                         break;
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3144                         deemph_reg_value = 128;
3145                         margin_reg_value = 102;
3146                         break;
3147                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3148                         deemph_reg_value = 128;
3149                         margin_reg_value = 154;
3150                         uniq_trans_scale = true;
3151                         break;
3152                 default:
3153                         return;
3154                 }
3155                 break;
3156         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3157                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3158                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3159                         deemph_reg_value = 85;
3160                         margin_reg_value = 78;
3161                         break;
3162                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3163                         deemph_reg_value = 85;
3164                         margin_reg_value = 116;
3165                         break;
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3167                         deemph_reg_value = 85;
3168                         margin_reg_value = 154;
3169                         break;
3170                 default:
3171                         return;
3172                 }
3173                 break;
3174         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3175                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3176                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3177                         deemph_reg_value = 64;
3178                         margin_reg_value = 104;
3179                         break;
3180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3181                         deemph_reg_value = 64;
3182                         margin_reg_value = 154;
3183                         break;
3184                 default:
3185                         return;
3186                 }
3187                 break;
3188         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3189                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191                         deemph_reg_value = 43;
3192                         margin_reg_value = 154;
3193                         break;
3194                 default:
3195                         return;
3196                 }
3197                 break;
3198         default:
3199                 return;
3200         }
3201
3202         chv_set_phy_signal_level(encoder, crtc_state,
3203                                  deemph_reg_value, margin_reg_value,
3204                                  uniq_trans_scale);
3205 }
3206
3207 static u32 g4x_signal_levels(u8 train_set)
3208 {
3209         u32 signal_levels = 0;
3210
3211         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3212         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3213         default:
3214                 signal_levels |= DP_VOLTAGE_0_4;
3215                 break;
3216         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3217                 signal_levels |= DP_VOLTAGE_0_6;
3218                 break;
3219         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3220                 signal_levels |= DP_VOLTAGE_0_8;
3221                 break;
3222         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3223                 signal_levels |= DP_VOLTAGE_1_2;
3224                 break;
3225         }
3226         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3227         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3228         default:
3229                 signal_levels |= DP_PRE_EMPHASIS_0;
3230                 break;
3231         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3232                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3233                 break;
3234         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3235                 signal_levels |= DP_PRE_EMPHASIS_6;
3236                 break;
3237         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3238                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3239                 break;
3240         }
3241         return signal_levels;
3242 }
3243
3244 static void
3245 g4x_set_signal_levels(struct intel_dp *intel_dp,
3246                       const struct intel_crtc_state *crtc_state)
3247 {
3248         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3249         u8 train_set = intel_dp->train_set[0];
3250         u32 signal_levels;
3251
3252         signal_levels = g4x_signal_levels(train_set);
3253
3254         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3255                     signal_levels);
3256
3257         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
3258         intel_dp->DP |= signal_levels;
3259
3260         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3261         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3262 }
3263
3264 /* SNB CPU eDP voltage swing and pre-emphasis control */
3265 static u32 snb_cpu_edp_signal_levels(u8 train_set)
3266 {
3267         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3268                                         DP_TRAIN_PRE_EMPHASIS_MASK);
3269
3270         switch (signal_levels) {
3271         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3272         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3273                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3274         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3275                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3276         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3277         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3278                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3279         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3280         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3281                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3282         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3283         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3284                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3285         default:
3286                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3287                               "0x%x\n", signal_levels);
3288                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3289         }
3290 }
3291
3292 static void
3293 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
3294                               const struct intel_crtc_state *crtc_state)
3295 {
3296         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3297         u8 train_set = intel_dp->train_set[0];
3298         u32 signal_levels;
3299
3300         signal_levels = snb_cpu_edp_signal_levels(train_set);
3301
3302         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3303                     signal_levels);
3304
3305         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3306         intel_dp->DP |= signal_levels;
3307
3308         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3309         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3310 }
3311
3312 /* IVB CPU eDP voltage swing and pre-emphasis control */
3313 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
3314 {
3315         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3316                                         DP_TRAIN_PRE_EMPHASIS_MASK);
3317
3318         switch (signal_levels) {
3319         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3320                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3321         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3322                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3323         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3324         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3325                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3326
3327         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3328                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3329         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3330                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3331
3332         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3333                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3334         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3335                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3336
3337         default:
3338                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3339                               "0x%x\n", signal_levels);
3340                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3341         }
3342 }
3343
3344 static void
3345 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
3346                               const struct intel_crtc_state *crtc_state)
3347 {
3348         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3349         u8 train_set = intel_dp->train_set[0];
3350         u32 signal_levels;
3351
3352         signal_levels = ivb_cpu_edp_signal_levels(train_set);
3353
3354         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3355                     signal_levels);
3356
3357         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3358         intel_dp->DP |= signal_levels;
3359
3360         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3361         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3362 }
3363
3364 static char dp_training_pattern_name(u8 train_pat)
3365 {
3366         switch (train_pat) {
3367         case DP_TRAINING_PATTERN_1:
3368         case DP_TRAINING_PATTERN_2:
3369         case DP_TRAINING_PATTERN_3:
3370                 return '0' + train_pat;
3371         case DP_TRAINING_PATTERN_4:
3372                 return '4';
3373         default:
3374                 MISSING_CASE(train_pat);
3375                 return '?';
3376         }
3377 }
3378
3379 void
3380 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3381                                        const struct intel_crtc_state *crtc_state,
3382                                        u8 dp_train_pat)
3383 {
3384         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3385         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3386         u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
3387
3388         if (train_pat != DP_TRAINING_PATTERN_DISABLE)
3389                 drm_dbg_kms(&dev_priv->drm,
3390                             "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
3391                             encoder->base.base.id, encoder->base.name,
3392                             dp_training_pattern_name(train_pat));
3393
3394         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
3395 }
3396
3397 static void
3398 intel_dp_link_down(struct intel_encoder *encoder,
3399                    const struct intel_crtc_state *old_crtc_state)
3400 {
3401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3402         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3403         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3404         enum port port = encoder->port;
3405         u32 DP = intel_dp->DP;
3406
3407         if (drm_WARN_ON(&dev_priv->drm,
3408                         (intel_de_read(dev_priv, intel_dp->output_reg) &
3409                          DP_PORT_EN) == 0))
3410                 return;
3411
3412         drm_dbg_kms(&dev_priv->drm, "\n");
3413
3414         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3415             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3416                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3417                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3418         } else {
3419                 DP &= ~DP_LINK_TRAIN_MASK;
3420                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3421         }
3422         intel_de_write(dev_priv, intel_dp->output_reg, DP);
3423         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3424
3425         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3426         intel_de_write(dev_priv, intel_dp->output_reg, DP);
3427         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3428
3429         /*
3430          * HW workaround for IBX, we need to move the port
3431          * to transcoder A after disabling it to allow the
3432          * matching HDMI port to be enabled on transcoder A.
3433          */
3434         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3435                 /*
3436                  * We get CPU/PCH FIFO underruns on the other pipe when
3437                  * doing the workaround. Sweep them under the rug.
3438                  */
3439                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3440                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3441
3442                 /* always enable with pattern 1 (as per spec) */
3443                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3444                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3445                         DP_LINK_TRAIN_PAT_1;
3446                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3447                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3448
3449                 DP &= ~DP_PORT_EN;
3450                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3451                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3452
3453                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3454                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3455                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3456         }
3457
3458         msleep(intel_dp->pps.panel_power_down_delay);
3459
3460         intel_dp->DP = DP;
3461
3462         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3463                 intel_wakeref_t wakeref;
3464
3465                 with_intel_pps_lock(intel_dp, wakeref)
3466                         intel_dp->pps.active_pipe = INVALID_PIPE;
3467         }
3468 }
3469
3470 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3471 {
3472         u8 dprx = 0;
3473
3474         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3475                               &dprx) != 1)
3476                 return false;
3477         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3478 }
3479
3480 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
3481 {
3482         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3483
3484         /*
3485          * Clear the cached register set to avoid using stale values
3486          * for the sinks that do not support DSC.
3487          */
3488         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
3489
3490         /* Clear fec_capable to avoid using stale values */
3491         intel_dp->fec_capable = 0;
3492
3493         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
3494         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
3495             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3496                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
3497                                      intel_dp->dsc_dpcd,
3498                                      sizeof(intel_dp->dsc_dpcd)) < 0)
3499                         drm_err(&i915->drm,
3500                                 "Failed to read DPCD register 0x%x\n",
3501                                 DP_DSC_SUPPORT);
3502
3503                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
3504                             (int)sizeof(intel_dp->dsc_dpcd),
3505                             intel_dp->dsc_dpcd);
3506
3507                 /* FEC is supported only on DP 1.4 */
3508                 if (!intel_dp_is_edp(intel_dp) &&
3509                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3510                                       &intel_dp->fec_capable) < 0)
3511                         drm_err(&i915->drm,
3512                                 "Failed to read FEC DPCD register\n");
3513
3514                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3515                             intel_dp->fec_capable);
3516         }
3517 }
3518
3519 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3520                                      struct drm_display_mode *mode)
3521 {
3522         struct intel_dp *intel_dp = intel_attached_dp(connector);
3523         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3524         int n = intel_dp->mso_link_count;
3525         int overlap = intel_dp->mso_pixel_overlap;
3526
3527         if (!mode || !n)
3528                 return;
3529
3530         mode->hdisplay = (mode->hdisplay - overlap) * n;
3531         mode->hsync_start = (mode->hsync_start - overlap) * n;
3532         mode->hsync_end = (mode->hsync_end - overlap) * n;
3533         mode->htotal = (mode->htotal - overlap) * n;
3534         mode->clock *= n;
3535
3536         drm_mode_set_name(mode);
3537
3538         drm_dbg_kms(&i915->drm,
3539                     "[CONNECTOR:%d:%s] using generated MSO mode: ",
3540                     connector->base.base.id, connector->base.name);
3541         drm_mode_debug_printmodeline(mode);
3542 }
3543
3544 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3545 {
3546         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3547         u8 mso;
3548
3549         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3550                 return;
3551
3552         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3553                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3554                 return;
3555         }
3556
3557         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3558         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3559         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3560                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3561                 mso = 0;
3562         }
3563
3564         if (mso) {
3565                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
3566                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
3567                 drm_err(&i915->drm, "No source MSO support, disabling\n");
3568                 mso = 0;
3569         }
3570
3571         intel_dp->mso_link_count = mso;
3572         intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
3573 }
3574
3575 static bool
3576 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3577 {
3578         struct drm_i915_private *dev_priv =
3579                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3580
3581         /* this function is meant to be called only once */
3582         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3583
3584         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3585                 return false;
3586
3587         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3588                          drm_dp_is_branch(intel_dp->dpcd));
3589
3590         /*
3591          * Read the eDP display control registers.
3592          *
3593          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3594          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3595          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3596          * method). The display control registers should read zero if they're
3597          * not supported anyway.
3598          */
3599         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3600                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3601                              sizeof(intel_dp->edp_dpcd))
3602                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3603                             (int)sizeof(intel_dp->edp_dpcd),
3604                             intel_dp->edp_dpcd);
3605
3606         /*
3607          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3608          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3609          */
3610         intel_psr_init_dpcd(intel_dp);
3611
3612         /* Read the eDP 1.4+ supported link rates. */
3613         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3614                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3615                 int i;
3616
3617                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3618                                 sink_rates, sizeof(sink_rates));
3619
3620                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3621                         int val = le16_to_cpu(sink_rates[i]);
3622
3623                         if (val == 0)
3624                                 break;
3625
3626                         /* Value read multiplied by 200kHz gives the per-lane
3627                          * link rate in kHz. The source rates are, however,
3628                          * stored in terms of LS_Clk kHz. The full conversion
3629                          * back to symbols is
3630                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3631                          */
3632                         intel_dp->sink_rates[i] = (val * 200) / 10;
3633                 }
3634                 intel_dp->num_sink_rates = i;
3635         }
3636
3637         /*
3638          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3639          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3640          */
3641         if (intel_dp->num_sink_rates)
3642                 intel_dp->use_rate_select = true;
3643         else
3644                 intel_dp_set_sink_rates(intel_dp);
3645
3646         intel_dp_set_common_rates(intel_dp);
3647
3648         /* Read the eDP DSC DPCD registers */
3649         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3650                 intel_dp_get_dsc_sink_cap(intel_dp);
3651
3652         /*
3653          * If needed, program our source OUI so we can make various Intel-specific AUX services
3654          * available (such as HDR backlight controls)
3655          */
3656         intel_edp_init_source_oui(intel_dp, true);
3657
3658         intel_edp_mso_init(intel_dp);
3659
3660         return true;
3661 }
3662
3663 static bool
3664 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3665 {
3666         if (!intel_dp->attached_connector)
3667                 return false;
3668
3669         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3670                                           intel_dp->dpcd,
3671                                           &intel_dp->desc);
3672 }
3673
3674 static bool
3675 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3676 {
3677         int ret;
3678
3679         intel_dp_lttpr_init(intel_dp);
3680
3681         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
3682                 return false;
3683
3684         /*
3685          * Don't clobber cached eDP rates. Also skip re-reading
3686          * the OUI/ID since we know it won't change.
3687          */
3688         if (!intel_dp_is_edp(intel_dp)) {
3689                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3690                                  drm_dp_is_branch(intel_dp->dpcd));
3691
3692                 intel_dp_set_sink_rates(intel_dp);
3693                 intel_dp_set_common_rates(intel_dp);
3694         }
3695
3696         if (intel_dp_has_sink_count(intel_dp)) {
3697                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3698                 if (ret < 0)
3699                         return false;
3700
3701                 /*
3702                  * Sink count can change between short pulse hpd hence
3703                  * a member variable in intel_dp will track any changes
3704                  * between short pulse interrupts.
3705                  */
3706                 intel_dp->sink_count = ret;
3707
3708                 /*
3709                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3710                  * a dongle is present but no display. Unless we require to know
3711                  * if a dongle is present or not, we don't need to update
3712                  * downstream port information. So, an early return here saves
3713                  * time from performing other operations which are not required.
3714                  */
3715                 if (!intel_dp->sink_count)
3716                         return false;
3717         }
3718
3719         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3720                                            intel_dp->downstream_ports) == 0;
3721 }
3722
3723 static bool
3724 intel_dp_can_mst(struct intel_dp *intel_dp)
3725 {
3726         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3727
3728         return i915->params.enable_dp_mst &&
3729                 intel_dp->can_mst &&
3730                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3731 }
3732
3733 static void
3734 intel_dp_configure_mst(struct intel_dp *intel_dp)
3735 {
3736         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3737         struct intel_encoder *encoder =
3738                 &dp_to_dig_port(intel_dp)->base;
3739         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3740
3741         drm_dbg_kms(&i915->drm,
3742                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3743                     encoder->base.base.id, encoder->base.name,
3744                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
3745                     yesno(i915->params.enable_dp_mst));
3746
3747         if (!intel_dp->can_mst)
3748                 return;
3749
3750         intel_dp->is_mst = sink_can_mst &&
3751                 i915->params.enable_dp_mst;
3752
3753         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3754                                         intel_dp->is_mst);
3755 }
3756
3757 static bool
3758 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3759 {
3760         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3761                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3762                 DP_DPRX_ESI_LEN;
3763 }
3764
3765 bool
3766 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3767                        const struct drm_connector_state *conn_state)
3768 {
3769         /*
3770          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3771          * of Color Encoding Format and Content Color Gamut], in order to
3772          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3773          */
3774         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3775                 return true;
3776
3777         switch (conn_state->colorspace) {
3778         case DRM_MODE_COLORIMETRY_SYCC_601:
3779         case DRM_MODE_COLORIMETRY_OPYCC_601:
3780         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3781         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3782         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3783                 return true;
3784         default:
3785                 break;
3786         }
3787
3788         return false;
3789 }
3790
3791 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3792                                      struct dp_sdp *sdp, size_t size)
3793 {
3794         size_t length = sizeof(struct dp_sdp);
3795
3796         if (size < length)
3797                 return -ENOSPC;
3798
3799         memset(sdp, 0, size);
3800
3801         /*
3802          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3803          * VSC SDP Header Bytes
3804          */
3805         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3806         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3807         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3808         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3809
3810         /*
3811          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3812          * per DP 1.4a spec.
3813          */
3814         if (vsc->revision != 0x5)
3815                 goto out;
3816
3817         /* VSC SDP Payload for DB16 through DB18 */
3818         /* Pixel Encoding and Colorimetry Formats  */
3819         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3820         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3821
3822         switch (vsc->bpc) {
3823         case 6:
3824                 /* 6bpc: 0x0 */
3825                 break;
3826         case 8:
3827                 sdp->db[17] = 0x1; /* DB17[3:0] */
3828                 break;
3829         case 10:
3830                 sdp->db[17] = 0x2;
3831                 break;
3832         case 12:
3833                 sdp->db[17] = 0x3;
3834                 break;
3835         case 16:
3836                 sdp->db[17] = 0x4;
3837                 break;
3838         default:
3839                 MISSING_CASE(vsc->bpc);
3840                 break;
3841         }
3842         /* Dynamic Range and Component Bit Depth */
3843         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3844                 sdp->db[17] |= 0x80;  /* DB17[7] */
3845
3846         /* Content Type */
3847         sdp->db[18] = vsc->content_type & 0x7;
3848
3849 out:
3850         return length;
3851 }
3852
3853 static ssize_t
3854 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
3855                                          struct dp_sdp *sdp,
3856                                          size_t size)
3857 {
3858         size_t length = sizeof(struct dp_sdp);
3859         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3860         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3861         ssize_t len;
3862
3863         if (size < length)
3864                 return -ENOSPC;
3865
3866         memset(sdp, 0, size);
3867
3868         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3869         if (len < 0) {
3870                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
3871                 return -ENOSPC;
3872         }
3873
3874         if (len != infoframe_size) {
3875                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
3876                 return -ENOSPC;
3877         }
3878
3879         /*
3880          * Set up the infoframe sdp packet for HDR static metadata.
3881          * Prepare VSC Header for SU as per DP 1.4a spec,
3882          * Table 2-100 and Table 2-101
3883          */
3884
3885         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3886         sdp->sdp_header.HB0 = 0;
3887         /*
3888          * Packet Type 80h + Non-audio INFOFRAME Type value
3889          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3890          * - 80h + Non-audio INFOFRAME Type value
3891          * - InfoFrame Type: 0x07
3892          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3893          */
3894         sdp->sdp_header.HB1 = drm_infoframe->type;
3895         /*
3896          * Least Significant Eight Bits of (Data Byte Count – 1)
3897          * infoframe_size - 1
3898          */
3899         sdp->sdp_header.HB2 = 0x1D;
3900         /* INFOFRAME SDP Version Number */
3901         sdp->sdp_header.HB3 = (0x13 << 2);
3902         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3903         sdp->db[0] = drm_infoframe->version;
3904         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3905         sdp->db[1] = drm_infoframe->length;
3906         /*
3907          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3908          * HDMI_INFOFRAME_HEADER_SIZE
3909          */
3910         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3911         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3912                HDMI_DRM_INFOFRAME_SIZE);
3913
3914         /*
3915          * Size of DP infoframe sdp packet for HDR static metadata consists of
3916          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3917          * - Two Data Blocks: 2 bytes
3918          *    CTA Header Byte2 (INFOFRAME Version Number)
3919          *    CTA Header Byte3 (Length of INFOFRAME)
3920          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3921          *
3922          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3923          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3924          * will pad rest of the size.
3925          */
3926         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3927 }
3928
3929 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3930                                const struct intel_crtc_state *crtc_state,
3931                                unsigned int type)
3932 {
3933         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3935         struct dp_sdp sdp = {};
3936         ssize_t len;
3937
3938         if ((crtc_state->infoframes.enable &
3939              intel_hdmi_infoframe_enable(type)) == 0)
3940                 return;
3941
3942         switch (type) {
3943         case DP_SDP_VSC:
3944                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3945                                             sizeof(sdp));
3946                 break;
3947         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3948                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
3949                                                                &sdp, sizeof(sdp));
3950                 break;
3951         default:
3952                 MISSING_CASE(type);
3953                 return;
3954         }
3955
3956         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3957                 return;
3958
3959         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3960 }
3961
3962 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3963                             const struct intel_crtc_state *crtc_state,
3964                             struct drm_dp_vsc_sdp *vsc)
3965 {
3966         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3967         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3968         struct dp_sdp sdp = {};
3969         ssize_t len;
3970
3971         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3972
3973         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3974                 return;
3975
3976         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3977                                         &sdp, len);
3978 }
3979
3980 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3981                              bool enable,
3982                              const struct intel_crtc_state *crtc_state,
3983                              const struct drm_connector_state *conn_state)
3984 {
3985         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3986         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3987         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3988         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3989                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3990                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3991         u32 val = intel_de_read(dev_priv, reg);
3992
3993         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3994         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3995         if (intel_psr_enabled(intel_dp))
3996                 val &= ~dip_enable;
3997         else
3998                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
3999
4000         if (!enable) {
4001                 intel_de_write(dev_priv, reg, val);
4002                 intel_de_posting_read(dev_priv, reg);
4003                 return;
4004         }
4005
4006         intel_de_write(dev_priv, reg, val);
4007         intel_de_posting_read(dev_priv, reg);
4008
4009         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4010         if (!intel_psr_enabled(intel_dp))
4011                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4012
4013         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4014 }
4015
4016 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4017                                    const void *buffer, size_t size)
4018 {
4019         const struct dp_sdp *sdp = buffer;
4020
4021         if (size < sizeof(struct dp_sdp))
4022                 return -EINVAL;
4023
4024         memset(vsc, 0, size);
4025
4026         if (sdp->sdp_header.HB0 != 0)
4027                 return -EINVAL;
4028
4029         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4030                 return -EINVAL;
4031
4032         vsc->sdp_type = sdp->sdp_header.HB1;
4033         vsc->revision = sdp->sdp_header.HB2;
4034         vsc->length = sdp->sdp_header.HB3;
4035
4036         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4037             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4038                 /*
4039                  * - HB2 = 0x2, HB3 = 0x8
4040                  *   VSC SDP supporting 3D stereo + PSR
4041                  * - HB2 = 0x4, HB3 = 0xe
4042                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4043                  *   first scan line of the SU region (applies to eDP v1.4b
4044                  *   and higher).
4045                  */
4046                 return 0;
4047         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4048                 /*
4049                  * - HB2 = 0x5, HB3 = 0x13
4050                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4051                  *   Format.
4052                  */
4053                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4054                 vsc->colorimetry = sdp->db[16] & 0xf;
4055                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4056
4057                 switch (sdp->db[17] & 0x7) {
4058                 case 0x0:
4059                         vsc->bpc = 6;
4060                         break;
4061                 case 0x1:
4062                         vsc->bpc = 8;
4063                         break;
4064                 case 0x2:
4065                         vsc->bpc = 10;
4066                         break;
4067                 case 0x3:
4068                         vsc->bpc = 12;
4069                         break;
4070                 case 0x4:
4071                         vsc->bpc = 16;
4072                         break;
4073                 default:
4074                         MISSING_CASE(sdp->db[17] & 0x7);
4075                         return -EINVAL;
4076                 }
4077
4078                 vsc->content_type = sdp->db[18] & 0x7;
4079         } else {
4080                 return -EINVAL;
4081         }
4082
4083         return 0;
4084 }
4085
4086 static int
4087 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4088                                            const void *buffer, size_t size)
4089 {
4090         int ret;
4091
4092         const struct dp_sdp *sdp = buffer;
4093
4094         if (size < sizeof(struct dp_sdp))
4095                 return -EINVAL;
4096
4097         if (sdp->sdp_header.HB0 != 0)
4098                 return -EINVAL;
4099
4100         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4101                 return -EINVAL;
4102
4103         /*
4104          * Least Significant Eight Bits of (Data Byte Count – 1)
4105          * 1Dh (i.e., Data Byte Count = 30 bytes).
4106          */
4107         if (sdp->sdp_header.HB2 != 0x1D)
4108                 return -EINVAL;
4109
4110         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4111         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4112                 return -EINVAL;
4113
4114         /* INFOFRAME SDP Version Number */
4115         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4116                 return -EINVAL;
4117
4118         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4119         if (sdp->db[0] != 1)
4120                 return -EINVAL;
4121
4122         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4123         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4124                 return -EINVAL;
4125
4126         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4127                                              HDMI_DRM_INFOFRAME_SIZE);
4128
4129         return ret;
4130 }
4131
4132 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4133                                   struct intel_crtc_state *crtc_state,
4134                                   struct drm_dp_vsc_sdp *vsc)
4135 {
4136         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4137         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4138         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4139         unsigned int type = DP_SDP_VSC;
4140         struct dp_sdp sdp = {};
4141         int ret;
4142
4143         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4144         if (intel_psr_enabled(intel_dp))
4145                 return;
4146
4147         if ((crtc_state->infoframes.enable &
4148              intel_hdmi_infoframe_enable(type)) == 0)
4149                 return;
4150
4151         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4152
4153         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4154
4155         if (ret)
4156                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4157 }
4158
4159 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4160                                                      struct intel_crtc_state *crtc_state,
4161                                                      struct hdmi_drm_infoframe *drm_infoframe)
4162 {
4163         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4165         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4166         struct dp_sdp sdp = {};
4167         int ret;
4168
4169         if ((crtc_state->infoframes.enable &
4170             intel_hdmi_infoframe_enable(type)) == 0)
4171                 return;
4172
4173         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4174                                  sizeof(sdp));
4175
4176         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4177                                                          sizeof(sdp));
4178
4179         if (ret)
4180                 drm_dbg_kms(&dev_priv->drm,
4181                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4182 }
4183
4184 void intel_read_dp_sdp(struct intel_encoder *encoder,
4185                        struct intel_crtc_state *crtc_state,
4186                        unsigned int type)
4187 {
4188         if (encoder->type != INTEL_OUTPUT_DDI)
4189                 return;
4190
4191         switch (type) {
4192         case DP_SDP_VSC:
4193                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4194                                       &crtc_state->infoframes.vsc);
4195                 break;
4196         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4197                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4198                                                          &crtc_state->infoframes.drm.drm);
4199                 break;
4200         default:
4201                 MISSING_CASE(type);
4202                 break;
4203         }
4204 }
4205
4206 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4207 {
4208         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4209         int status = 0;
4210         int test_link_rate;
4211         u8 test_lane_count, test_link_bw;
4212         /* (DP CTS 1.2)
4213          * 4.3.1.11
4214          */
4215         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4216         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4217                                    &test_lane_count);
4218
4219         if (status <= 0) {
4220                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4221                 return DP_TEST_NAK;
4222         }
4223         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4224
4225         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4226                                    &test_link_bw);
4227         if (status <= 0) {
4228                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4229                 return DP_TEST_NAK;
4230         }
4231         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4232
4233         /* Validate the requested link rate and lane count */
4234         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4235                                         test_lane_count))
4236                 return DP_TEST_NAK;
4237
4238         intel_dp->compliance.test_lane_count = test_lane_count;
4239         intel_dp->compliance.test_link_rate = test_link_rate;
4240
4241         return DP_TEST_ACK;
4242 }
4243
4244 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4245 {
4246         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4247         u8 test_pattern;
4248         u8 test_misc;
4249         __be16 h_width, v_height;
4250         int status = 0;
4251
4252         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4253         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4254                                    &test_pattern);
4255         if (status <= 0) {
4256                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4257                 return DP_TEST_NAK;
4258         }
4259         if (test_pattern != DP_COLOR_RAMP)
4260                 return DP_TEST_NAK;
4261
4262         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4263                                   &h_width, 2);
4264         if (status <= 0) {
4265                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4266                 return DP_TEST_NAK;
4267         }
4268
4269         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4270                                   &v_height, 2);
4271         if (status <= 0) {
4272                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4273                 return DP_TEST_NAK;
4274         }
4275
4276         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4277                                    &test_misc);
4278         if (status <= 0) {
4279                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4280                 return DP_TEST_NAK;
4281         }
4282         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4283                 return DP_TEST_NAK;
4284         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4285                 return DP_TEST_NAK;
4286         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4287         case DP_TEST_BIT_DEPTH_6:
4288                 intel_dp->compliance.test_data.bpc = 6;
4289                 break;
4290         case DP_TEST_BIT_DEPTH_8:
4291                 intel_dp->compliance.test_data.bpc = 8;
4292                 break;
4293         default:
4294                 return DP_TEST_NAK;
4295         }
4296
4297         intel_dp->compliance.test_data.video_pattern = test_pattern;
4298         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4299         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4300         /* Set test active flag here so userspace doesn't interrupt things */
4301         intel_dp->compliance.test_active = true;
4302
4303         return DP_TEST_ACK;
4304 }
4305
4306 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4307 {
4308         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4309         u8 test_result = DP_TEST_ACK;
4310         struct intel_connector *intel_connector = intel_dp->attached_connector;
4311         struct drm_connector *connector = &intel_connector->base;
4312
4313         if (intel_connector->detect_edid == NULL ||
4314             connector->edid_corrupt ||
4315             intel_dp->aux.i2c_defer_count > 6) {
4316                 /* Check EDID read for NACKs, DEFERs and corruption
4317                  * (DP CTS 1.2 Core r1.1)
4318                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4319                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4320                  *    4.2.2.6 : EDID corruption detected
4321                  * Use failsafe mode for all cases
4322                  */
4323                 if (intel_dp->aux.i2c_nack_count > 0 ||
4324                         intel_dp->aux.i2c_defer_count > 0)
4325                         drm_dbg_kms(&i915->drm,
4326                                     "EDID read had %d NACKs, %d DEFERs\n",
4327                                     intel_dp->aux.i2c_nack_count,
4328                                     intel_dp->aux.i2c_defer_count);
4329                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4330         } else {
4331                 struct edid *block = intel_connector->detect_edid;
4332
4333                 /* We have to write the checksum
4334                  * of the last block read
4335                  */
4336                 block += intel_connector->detect_edid->extensions;
4337
4338                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4339                                        block->checksum) <= 0)
4340                         drm_dbg_kms(&i915->drm,
4341                                     "Failed to write EDID checksum\n");
4342
4343                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4344                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4345         }
4346
4347         /* Set test active flag here so userspace doesn't interrupt things */
4348         intel_dp->compliance.test_active = true;
4349
4350         return test_result;
4351 }
4352
4353 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4354                                         const struct intel_crtc_state *crtc_state)
4355 {
4356         struct drm_i915_private *dev_priv =
4357                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4358         struct drm_dp_phy_test_params *data =
4359                         &intel_dp->compliance.test_data.phytest;
4360         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4361         enum pipe pipe = crtc->pipe;
4362         u32 pattern_val;
4363
4364         switch (data->phy_pattern) {
4365         case DP_PHY_TEST_PATTERN_NONE:
4366                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
4367                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4368                 break;
4369         case DP_PHY_TEST_PATTERN_D10_2:
4370                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
4371                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4372                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4373                 break;
4374         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
4375                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
4376                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4377                                DDI_DP_COMP_CTL_ENABLE |
4378                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4379                 break;
4380         case DP_PHY_TEST_PATTERN_PRBS7:
4381                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
4382                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4383                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4384                 break;
4385         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
4386                 /*
4387                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4388                  * current firmware of DPR-100 could not set it, so hardcoding
4389                  * now for complaince test.
4390                  */
4391                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4392                 pattern_val = 0x3e0f83e0;
4393                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4394                 pattern_val = 0x0f83e0f8;
4395                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4396                 pattern_val = 0x0000f83e;
4397                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4398                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4399                                DDI_DP_COMP_CTL_ENABLE |
4400                                DDI_DP_COMP_CTL_CUSTOM80);
4401                 break;
4402         case DP_PHY_TEST_PATTERN_CP2520:
4403                 /*
4404                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4405                  * current firmware of DPR-100 could not set it, so hardcoding
4406                  * now for complaince test.
4407                  */
4408                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
4409                 pattern_val = 0xFB;
4410                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4411                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4412                                pattern_val);
4413                 break;
4414         default:
4415                 WARN(1, "Invalid Phy Test Pattern\n");
4416         }
4417 }
4418
4419 static void
4420 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
4421                                   const struct intel_crtc_state *crtc_state)
4422 {
4423         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4424         struct drm_device *dev = dig_port->base.base.dev;
4425         struct drm_i915_private *dev_priv = to_i915(dev);
4426         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
4427         enum pipe pipe = crtc->pipe;
4428         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
4429
4430         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
4431                                                  TRANS_DDI_FUNC_CTL(pipe));
4432         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
4433         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
4434
4435         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
4436                                       TGL_TRANS_DDI_PORT_MASK);
4437         trans_conf_value &= ~PIPECONF_ENABLE;
4438         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
4439
4440         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
4441         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
4442                        trans_ddi_func_ctl_value);
4443         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
4444 }
4445
4446 static void
4447 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
4448                                  const struct intel_crtc_state *crtc_state)
4449 {
4450         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4451         struct drm_device *dev = dig_port->base.base.dev;
4452         struct drm_i915_private *dev_priv = to_i915(dev);
4453         enum port port = dig_port->base.port;
4454         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
4455         enum pipe pipe = crtc->pipe;
4456         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
4457
4458         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
4459                                                  TRANS_DDI_FUNC_CTL(pipe));
4460         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
4461         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
4462
4463         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
4464                                     TGL_TRANS_DDI_SELECT_PORT(port);
4465         trans_conf_value |= PIPECONF_ENABLE;
4466         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
4467
4468         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
4469         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
4470         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
4471                        trans_ddi_func_ctl_value);
4472 }
4473
4474 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4475                                          const struct intel_crtc_state *crtc_state)
4476 {
4477         struct drm_dp_phy_test_params *data =
4478                 &intel_dp->compliance.test_data.phytest;
4479         u8 link_status[DP_LINK_STATUS_SIZE];
4480
4481         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4482                                              link_status) < 0) {
4483                 DRM_DEBUG_KMS("failed to get link status\n");
4484                 return;
4485         }
4486
4487         /* retrieve vswing & pre-emphasis setting */
4488         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4489                                   link_status);
4490
4491         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
4492
4493         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4494
4495         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4496
4497         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
4498
4499         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4500                                     link_status[DP_DPCD_REV]);
4501 }
4502
4503 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4504 {
4505         struct drm_dp_phy_test_params *data =
4506                 &intel_dp->compliance.test_data.phytest;
4507
4508         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4509                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
4510                 return DP_TEST_NAK;
4511         }
4512
4513         /* Set test active flag here so userspace doesn't interrupt things */
4514         intel_dp->compliance.test_active = true;
4515
4516         return DP_TEST_ACK;
4517 }
4518
4519 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4520 {
4521         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4522         u8 response = DP_TEST_NAK;
4523         u8 request = 0;
4524         int status;
4525
4526         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4527         if (status <= 0) {
4528                 drm_dbg_kms(&i915->drm,
4529                             "Could not read test request from sink\n");
4530                 goto update_status;
4531         }
4532
4533         switch (request) {
4534         case DP_TEST_LINK_TRAINING:
4535                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4536                 response = intel_dp_autotest_link_training(intel_dp);
4537                 break;
4538         case DP_TEST_LINK_VIDEO_PATTERN:
4539                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4540                 response = intel_dp_autotest_video_pattern(intel_dp);
4541                 break;
4542         case DP_TEST_LINK_EDID_READ:
4543                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4544                 response = intel_dp_autotest_edid(intel_dp);
4545                 break;
4546         case DP_TEST_LINK_PHY_TEST_PATTERN:
4547                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4548                 response = intel_dp_autotest_phy_pattern(intel_dp);
4549                 break;
4550         default:
4551                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4552                             request);
4553                 break;
4554         }
4555
4556         if (response & DP_TEST_ACK)
4557                 intel_dp->compliance.test_type = request;
4558
4559 update_status:
4560         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4561         if (status <= 0)
4562                 drm_dbg_kms(&i915->drm,
4563                             "Could not write test response to sink\n");
4564 }
4565
4566 static void
4567 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
4568 {
4569                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
4570
4571                 if (esi[1] & DP_CP_IRQ) {
4572                         intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4573                         *handled = true;
4574                 }
4575 }
4576
4577 /**
4578  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4579  * @intel_dp: Intel DP struct
4580  *
4581  * Read any pending MST interrupts, call MST core to handle these and ack the
4582  * interrupts. Check if the main and AUX link state is ok.
4583  *
4584  * Returns:
4585  * - %true if pending interrupts were serviced (or no interrupts were
4586  *   pending) w/o detecting an error condition.
4587  * - %false if an error condition - like AUX failure or a loss of link - is
4588  *   detected, which needs servicing from the hotplug work.
4589  */
4590 static bool
4591 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4592 {
4593         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4594         bool link_ok = true;
4595
4596         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4597
4598         for (;;) {
4599                 u8 esi[DP_DPRX_ESI_LEN] = {};
4600                 bool handled;
4601                 int retry;
4602
4603                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4604                         drm_dbg_kms(&i915->drm,
4605                                     "failed to get ESI - device may have failed\n");
4606                         link_ok = false;
4607
4608                         break;
4609                 }
4610
4611                 /* check link status - esi[10] = 0x200c */
4612                 if (intel_dp->active_mst_links > 0 && link_ok &&
4613                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4614                         drm_dbg_kms(&i915->drm,
4615                                     "channel EQ not ok, retraining\n");
4616                         link_ok = false;
4617                 }
4618
4619                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
4620
4621                 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
4622
4623                 if (!handled)
4624                         break;
4625
4626                 for (retry = 0; retry < 3; retry++) {
4627                         int wret;
4628
4629                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4630                                                  DP_SINK_COUNT_ESI+1,
4631                                                  &esi[1], 3);
4632                         if (wret == 3)
4633                                 break;
4634                 }
4635         }
4636
4637         return link_ok;
4638 }
4639
4640 static void
4641 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4642 {
4643         bool is_active;
4644         u8 buf = 0;
4645
4646         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4647         if (intel_dp->frl.is_trained && !is_active) {
4648                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4649                         return;
4650
4651                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4652                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4653                         return;
4654
4655                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4656
4657                 /* Restart FRL training or fall back to TMDS mode */
4658                 intel_dp_check_frl_training(intel_dp);
4659         }
4660 }
4661
4662 static bool
4663 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4664 {
4665         u8 link_status[DP_LINK_STATUS_SIZE];
4666
4667         if (!intel_dp->link_trained)
4668                 return false;
4669
4670         /*
4671          * While PSR source HW is enabled, it will control main-link sending
4672          * frames, enabling and disabling it so trying to do a retrain will fail
4673          * as the link would or not be on or it could mix training patterns
4674          * and frame data at the same time causing retrain to fail.
4675          * Also when exiting PSR, HW will retrain the link anyways fixing
4676          * any link status error.
4677          */
4678         if (intel_psr_enabled(intel_dp))
4679                 return false;
4680
4681         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4682                                              link_status) < 0)
4683                 return false;
4684
4685         /*
4686          * Validate the cached values of intel_dp->link_rate and
4687          * intel_dp->lane_count before attempting to retrain.
4688          *
4689          * FIXME would be nice to user the crtc state here, but since
4690          * we need to call this from the short HPD handler that seems
4691          * a bit hard.
4692          */
4693         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4694                                         intel_dp->lane_count))
4695                 return false;
4696
4697         /* Retrain if Channel EQ or CR not ok */
4698         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4699 }
4700
4701 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4702                                    const struct drm_connector_state *conn_state)
4703 {
4704         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4705         struct intel_encoder *encoder;
4706         enum pipe pipe;
4707
4708         if (!conn_state->best_encoder)
4709                 return false;
4710
4711         /* SST */
4712         encoder = &dp_to_dig_port(intel_dp)->base;
4713         if (conn_state->best_encoder == &encoder->base)
4714                 return true;
4715
4716         /* MST */
4717         for_each_pipe(i915, pipe) {
4718                 encoder = &intel_dp->mst_encoders[pipe]->base;
4719                 if (conn_state->best_encoder == &encoder->base)
4720                         return true;
4721         }
4722
4723         return false;
4724 }
4725
4726 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4727                                       struct drm_modeset_acquire_ctx *ctx,
4728                                       u32 *crtc_mask)
4729 {
4730         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4731         struct drm_connector_list_iter conn_iter;
4732         struct intel_connector *connector;
4733         int ret = 0;
4734
4735         *crtc_mask = 0;
4736
4737         if (!intel_dp_needs_link_retrain(intel_dp))
4738                 return 0;
4739
4740         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4741         for_each_intel_connector_iter(connector, &conn_iter) {
4742                 struct drm_connector_state *conn_state =
4743                         connector->base.state;
4744                 struct intel_crtc_state *crtc_state;
4745                 struct intel_crtc *crtc;
4746
4747                 if (!intel_dp_has_connector(intel_dp, conn_state))
4748                         continue;
4749
4750                 crtc = to_intel_crtc(conn_state->crtc);
4751                 if (!crtc)
4752                         continue;
4753
4754                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4755                 if (ret)
4756                         break;
4757
4758                 crtc_state = to_intel_crtc_state(crtc->base.state);
4759
4760                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4761
4762                 if (!crtc_state->hw.active)
4763                         continue;
4764
4765                 if (conn_state->commit &&
4766                     !try_wait_for_completion(&conn_state->commit->hw_done))
4767                         continue;
4768
4769                 *crtc_mask |= drm_crtc_mask(&crtc->base);
4770         }
4771         drm_connector_list_iter_end(&conn_iter);
4772
4773         if (!intel_dp_needs_link_retrain(intel_dp))
4774                 *crtc_mask = 0;
4775
4776         return ret;
4777 }
4778
4779 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4780 {
4781         struct intel_connector *connector = intel_dp->attached_connector;
4782
4783         return connector->base.status == connector_status_connected ||
4784                 intel_dp->is_mst;
4785 }
4786
4787 int intel_dp_retrain_link(struct intel_encoder *encoder,
4788                           struct drm_modeset_acquire_ctx *ctx)
4789 {
4790         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4791         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4792         struct intel_crtc *crtc;
4793         u32 crtc_mask;
4794         int ret;
4795
4796         if (!intel_dp_is_connected(intel_dp))
4797                 return 0;
4798
4799         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4800                                ctx);
4801         if (ret)
4802                 return ret;
4803
4804         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
4805         if (ret)
4806                 return ret;
4807
4808         if (crtc_mask == 0)
4809                 return 0;
4810
4811         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4812                     encoder->base.base.id, encoder->base.name);
4813
4814         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4815                 const struct intel_crtc_state *crtc_state =
4816                         to_intel_crtc_state(crtc->base.state);
4817
4818                 /* Suppress underruns caused by re-training */
4819                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4820                 if (crtc_state->has_pch_encoder)
4821                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4822                                                               intel_crtc_pch_transcoder(crtc), false);
4823         }
4824
4825         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4826                 const struct intel_crtc_state *crtc_state =
4827                         to_intel_crtc_state(crtc->base.state);
4828
4829                 /* retrain on the MST master transcoder */
4830                 if (INTEL_GEN(dev_priv) >= 12 &&
4831                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4832                     !intel_dp_mst_is_master_trans(crtc_state))
4833                         continue;
4834
4835                 intel_dp_check_frl_training(intel_dp);
4836                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4837                 intel_dp_start_link_train(intel_dp, crtc_state);
4838                 intel_dp_stop_link_train(intel_dp, crtc_state);
4839                 break;
4840         }
4841
4842         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4843                 const struct intel_crtc_state *crtc_state =
4844                         to_intel_crtc_state(crtc->base.state);
4845
4846                 /* Keep underrun reporting disabled until things are stable */
4847                 intel_wait_for_vblank(dev_priv, crtc->pipe);
4848
4849                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4850                 if (crtc_state->has_pch_encoder)
4851                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4852                                                               intel_crtc_pch_transcoder(crtc), true);
4853         }
4854
4855         return 0;
4856 }
4857
4858 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4859                                   struct drm_modeset_acquire_ctx *ctx,
4860                                   u32 *crtc_mask)
4861 {
4862         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4863         struct drm_connector_list_iter conn_iter;
4864         struct intel_connector *connector;
4865         int ret = 0;
4866
4867         *crtc_mask = 0;
4868
4869         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4870         for_each_intel_connector_iter(connector, &conn_iter) {
4871                 struct drm_connector_state *conn_state =
4872                         connector->base.state;
4873                 struct intel_crtc_state *crtc_state;
4874                 struct intel_crtc *crtc;
4875
4876                 if (!intel_dp_has_connector(intel_dp, conn_state))
4877                         continue;
4878
4879                 crtc = to_intel_crtc(conn_state->crtc);
4880                 if (!crtc)
4881                         continue;
4882
4883                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4884                 if (ret)
4885                         break;
4886
4887                 crtc_state = to_intel_crtc_state(crtc->base.state);
4888
4889                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4890
4891                 if (!crtc_state->hw.active)
4892                         continue;
4893
4894                 if (conn_state->commit &&
4895                     !try_wait_for_completion(&conn_state->commit->hw_done))
4896                         continue;
4897
4898                 *crtc_mask |= drm_crtc_mask(&crtc->base);
4899         }
4900         drm_connector_list_iter_end(&conn_iter);
4901
4902         return ret;
4903 }
4904
4905 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4906                                 struct drm_modeset_acquire_ctx *ctx)
4907 {
4908         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4909         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4910         struct intel_crtc *crtc;
4911         u32 crtc_mask;
4912         int ret;
4913
4914         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4915                                ctx);
4916         if (ret)
4917                 return ret;
4918
4919         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
4920         if (ret)
4921                 return ret;
4922
4923         if (crtc_mask == 0)
4924                 return 0;
4925
4926         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4927                     encoder->base.base.id, encoder->base.name);
4928
4929         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4930                 const struct intel_crtc_state *crtc_state =
4931                         to_intel_crtc_state(crtc->base.state);
4932
4933                 /* test on the MST master transcoder */
4934                 if (INTEL_GEN(dev_priv) >= 12 &&
4935                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4936                     !intel_dp_mst_is_master_trans(crtc_state))
4937                         continue;
4938
4939                 intel_dp_process_phy_request(intel_dp, crtc_state);
4940                 break;
4941         }
4942
4943         return 0;
4944 }
4945
4946 void intel_dp_phy_test(struct intel_encoder *encoder)
4947 {
4948         struct drm_modeset_acquire_ctx ctx;
4949         int ret;
4950
4951         drm_modeset_acquire_init(&ctx, 0);
4952
4953         for (;;) {
4954                 ret = intel_dp_do_phy_test(encoder, &ctx);
4955
4956                 if (ret == -EDEADLK) {
4957                         drm_modeset_backoff(&ctx);
4958                         continue;
4959                 }
4960
4961                 break;
4962         }
4963
4964         drm_modeset_drop_locks(&ctx);
4965         drm_modeset_acquire_fini(&ctx);
4966         drm_WARN(encoder->base.dev, ret,
4967                  "Acquiring modeset locks failed with %i\n", ret);
4968 }
4969
4970 /*
4971  * If display is now connected check links status,
4972  * there has been known issues of link loss triggering
4973  * long pulse.
4974  *
4975  * Some sinks (eg. ASUS PB287Q) seem to perform some
4976  * weird HPD ping pong during modesets. So we can apparently
4977  * end up with HPD going low during a modeset, and then
4978  * going back up soon after. And once that happens we must
4979  * retrain the link to get a picture. That's in case no
4980  * userspace component reacted to intermittent HPD dip.
4981  */
4982 static enum intel_hotplug_state
4983 intel_dp_hotplug(struct intel_encoder *encoder,
4984                  struct intel_connector *connector)
4985 {
4986         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4987         struct drm_modeset_acquire_ctx ctx;
4988         enum intel_hotplug_state state;
4989         int ret;
4990
4991         if (intel_dp->compliance.test_active &&
4992             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4993                 intel_dp_phy_test(encoder);
4994                 /* just do the PHY test and nothing else */
4995                 return INTEL_HOTPLUG_UNCHANGED;
4996         }
4997
4998         state = intel_encoder_hotplug(encoder, connector);
4999
5000         drm_modeset_acquire_init(&ctx, 0);
5001
5002         for (;;) {
5003                 ret = intel_dp_retrain_link(encoder, &ctx);
5004
5005                 if (ret == -EDEADLK) {
5006                         drm_modeset_backoff(&ctx);
5007                         continue;
5008                 }
5009
5010                 break;
5011         }
5012
5013         drm_modeset_drop_locks(&ctx);
5014         drm_modeset_acquire_fini(&ctx);
5015         drm_WARN(encoder->base.dev, ret,
5016                  "Acquiring modeset locks failed with %i\n", ret);
5017
5018         /*
5019          * Keeping it consistent with intel_ddi_hotplug() and
5020          * intel_hdmi_hotplug().
5021          */
5022         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5023                 state = INTEL_HOTPLUG_RETRY;
5024
5025         return state;
5026 }
5027
5028 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5029 {
5030         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5031         u8 val;
5032
5033         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5034                 return;
5035
5036         if (drm_dp_dpcd_readb(&intel_dp->aux,
5037                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5038                 return;
5039
5040         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5041
5042         if (val & DP_AUTOMATED_TEST_REQUEST)
5043                 intel_dp_handle_test_request(intel_dp);
5044
5045         if (val & DP_CP_IRQ)
5046                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5047
5048         if (val & DP_SINK_SPECIFIC_IRQ)
5049                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5050 }
5051
5052 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5053 {
5054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5055         u8 val;
5056
5057         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5058                 return;
5059
5060         if (drm_dp_dpcd_readb(&intel_dp->aux,
5061                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
5062                 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
5063                 return;
5064         }
5065
5066         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5067                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
5068                 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
5069                 return;
5070         }
5071
5072         if (val & HDMI_LINK_STATUS_CHANGED)
5073                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5074 }
5075
5076 /*
5077  * According to DP spec
5078  * 5.1.2:
5079  *  1. Read DPCD
5080  *  2. Configure link according to Receiver Capabilities
5081  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5082  *  4. Check link status on receipt of hot-plug interrupt
5083  *
5084  * intel_dp_short_pulse -  handles short pulse interrupts
5085  * when full detection is not required.
5086  * Returns %true if short pulse is handled and full detection
5087  * is NOT required and %false otherwise.
5088  */
5089 static bool
5090 intel_dp_short_pulse(struct intel_dp *intel_dp)
5091 {
5092         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5093         u8 old_sink_count = intel_dp->sink_count;
5094         bool ret;
5095
5096         /*
5097          * Clearing compliance test variables to allow capturing
5098          * of values for next automated test request.
5099          */
5100         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5101
5102         /*
5103          * Now read the DPCD to see if it's actually running
5104          * If the current value of sink count doesn't match with
5105          * the value that was stored earlier or dpcd read failed
5106          * we need to do full detection
5107          */
5108         ret = intel_dp_get_dpcd(intel_dp);
5109
5110         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5111                 /* No need to proceed if we are going to do full detect */
5112                 return false;
5113         }
5114
5115         intel_dp_check_device_service_irq(intel_dp);
5116         intel_dp_check_link_service_irq(intel_dp);
5117
5118         /* Handle CEC interrupts, if any */
5119         drm_dp_cec_irq(&intel_dp->aux);
5120
5121         /* defer to the hotplug work for link retraining if needed */
5122         if (intel_dp_needs_link_retrain(intel_dp))
5123                 return false;
5124
5125         intel_psr_short_pulse(intel_dp);
5126
5127         switch (intel_dp->compliance.test_type) {
5128         case DP_TEST_LINK_TRAINING:
5129                 drm_dbg_kms(&dev_priv->drm,
5130                             "Link Training Compliance Test requested\n");
5131                 /* Send a Hotplug Uevent to userspace to start modeset */
5132                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5133                 break;
5134         case DP_TEST_LINK_PHY_TEST_PATTERN:
5135                 drm_dbg_kms(&dev_priv->drm,
5136                             "PHY test pattern Compliance Test requested\n");
5137                 /*
5138                  * Schedule long hpd to do the test
5139                  *
5140                  * FIXME get rid of the ad-hoc phy test modeset code
5141                  * and properly incorporate it into the normal modeset.
5142                  */
5143                 return false;
5144         }
5145
5146         return true;
5147 }
5148
5149 /* XXX this is probably wrong for multiple downstream ports */
5150 static enum drm_connector_status
5151 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5152 {
5153         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5154         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5155         u8 *dpcd = intel_dp->dpcd;
5156         u8 type;
5157
5158         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5159                 return connector_status_connected;
5160
5161         lspcon_resume(dig_port);
5162
5163         if (!intel_dp_get_dpcd(intel_dp))
5164                 return connector_status_disconnected;
5165
5166         /* if there's no downstream port, we're done */
5167         if (!drm_dp_is_branch(dpcd))
5168                 return connector_status_connected;
5169
5170         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5171         if (intel_dp_has_sink_count(intel_dp) &&
5172             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5173                 return intel_dp->sink_count ?
5174                 connector_status_connected : connector_status_disconnected;
5175         }
5176
5177         if (intel_dp_can_mst(intel_dp))
5178                 return connector_status_connected;
5179
5180         /* If no HPD, poke DDC gently */
5181         if (drm_probe_ddc(&intel_dp->aux.ddc))
5182                 return connector_status_connected;
5183
5184         /* Well we tried, say unknown for unreliable port types */
5185         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5186                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5187                 if (type == DP_DS_PORT_TYPE_VGA ||
5188                     type == DP_DS_PORT_TYPE_NON_EDID)
5189                         return connector_status_unknown;
5190         } else {
5191                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5192                         DP_DWN_STRM_PORT_TYPE_MASK;
5193                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5194                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5195                         return connector_status_unknown;
5196         }
5197
5198         /* Anything else is out of spec, warn and ignore */
5199         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5200         return connector_status_disconnected;
5201 }
5202
5203 static enum drm_connector_status
5204 edp_detect(struct intel_dp *intel_dp)
5205 {
5206         return connector_status_connected;
5207 }
5208
5209 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5210 {
5211         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5212         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
5213
5214         return intel_de_read(dev_priv, SDEISR) & bit;
5215 }
5216
5217 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5218 {
5219         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5220         u32 bit;
5221
5222         switch (encoder->hpd_pin) {
5223         case HPD_PORT_B:
5224                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5225                 break;
5226         case HPD_PORT_C:
5227                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5228                 break;
5229         case HPD_PORT_D:
5230                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5231                 break;
5232         default:
5233                 MISSING_CASE(encoder->hpd_pin);
5234                 return false;
5235         }
5236
5237         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5238 }
5239
5240 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5241 {
5242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5243         u32 bit;
5244
5245         switch (encoder->hpd_pin) {
5246         case HPD_PORT_B:
5247                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5248                 break;
5249         case HPD_PORT_C:
5250                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5251                 break;
5252         case HPD_PORT_D:
5253                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5254                 break;
5255         default:
5256                 MISSING_CASE(encoder->hpd_pin);
5257                 return false;
5258         }
5259
5260         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5261 }
5262
5263 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5264 {
5265         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5266         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5267
5268         return intel_de_read(dev_priv, DEISR) & bit;
5269 }
5270
5271 /*
5272  * intel_digital_port_connected - is the specified port connected?
5273  * @encoder: intel_encoder
5274  *
5275  * In cases where there's a connector physically connected but it can't be used
5276  * by our hardware we also return false, since the rest of the driver should
5277  * pretty much treat the port as disconnected. This is relevant for type-C
5278  * (starting on ICL) where there's ownership involved.
5279  *
5280  * Return %true if port is connected, %false otherwise.
5281  */
5282 bool intel_digital_port_connected(struct intel_encoder *encoder)
5283 {
5284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5285         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5286         bool is_connected = false;
5287         intel_wakeref_t wakeref;
5288
5289         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5290                 is_connected = dig_port->connected(encoder);
5291
5292         return is_connected;
5293 }
5294
5295 static struct edid *
5296 intel_dp_get_edid(struct intel_dp *intel_dp)
5297 {
5298         struct intel_connector *intel_connector = intel_dp->attached_connector;
5299
5300         /* use cached edid if we have one */
5301         if (intel_connector->edid) {
5302                 /* invalid edid */
5303                 if (IS_ERR(intel_connector->edid))
5304                         return NULL;
5305
5306                 return drm_edid_duplicate(intel_connector->edid);
5307         } else
5308                 return drm_get_edid(&intel_connector->base,
5309                                     &intel_dp->aux.ddc);
5310 }
5311
5312 static void
5313 intel_dp_update_dfp(struct intel_dp *intel_dp,
5314                     const struct edid *edid)
5315 {
5316         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5317         struct intel_connector *connector = intel_dp->attached_connector;
5318
5319         intel_dp->dfp.max_bpc =
5320                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5321                                           intel_dp->downstream_ports, edid);
5322
5323         intel_dp->dfp.max_dotclock =
5324                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5325                                                intel_dp->downstream_ports);
5326
5327         intel_dp->dfp.min_tmds_clock =
5328                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5329                                                  intel_dp->downstream_ports,
5330                                                  edid);
5331         intel_dp->dfp.max_tmds_clock =
5332                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5333                                                  intel_dp->downstream_ports,
5334                                                  edid);
5335
5336         intel_dp->dfp.pcon_max_frl_bw =
5337                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5338                                            intel_dp->downstream_ports);
5339
5340         drm_dbg_kms(&i915->drm,
5341                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5342                     connector->base.base.id, connector->base.name,
5343                     intel_dp->dfp.max_bpc,
5344                     intel_dp->dfp.max_dotclock,
5345                     intel_dp->dfp.min_tmds_clock,
5346                     intel_dp->dfp.max_tmds_clock,
5347                     intel_dp->dfp.pcon_max_frl_bw);
5348
5349         intel_dp_get_pcon_dsc_cap(intel_dp);
5350 }
5351
5352 static void
5353 intel_dp_update_420(struct intel_dp *intel_dp)
5354 {
5355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5356         struct intel_connector *connector = intel_dp->attached_connector;
5357         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
5358
5359         /* No YCbCr output support on gmch platforms */
5360         if (HAS_GMCH(i915))
5361                 return;
5362
5363         /*
5364          * ILK doesn't seem capable of DP YCbCr output. The
5365          * displayed image is severly corrupted. SNB+ is fine.
5366          */
5367         if (IS_GEN(i915, 5))
5368                 return;
5369
5370         is_branch = drm_dp_is_branch(intel_dp->dpcd);
5371         ycbcr_420_passthrough =
5372                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5373                                                   intel_dp->downstream_ports);
5374         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5375         ycbcr_444_to_420 =
5376                 dp_to_dig_port(intel_dp)->lspcon.active ||
5377                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5378                                                         intel_dp->downstream_ports);
5379         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5380                                                                  intel_dp->downstream_ports,
5381                                                                  DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
5382                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
5383                                                                  DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
5384
5385         if (INTEL_GEN(i915) >= 11) {
5386                 /* Let PCON convert from RGB->YCbCr if possible */
5387                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
5388                         intel_dp->dfp.rgb_to_ycbcr = true;
5389                         intel_dp->dfp.ycbcr_444_to_420 = true;
5390                         connector->base.ycbcr_420_allowed = true;
5391                 } else {
5392                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
5393                         intel_dp->dfp.ycbcr_444_to_420 =
5394                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
5395
5396                         connector->base.ycbcr_420_allowed =
5397                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
5398                 }
5399         } else {
5400                 /* 4:4:4->4:2:0 conversion is the only way */
5401                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
5402
5403                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
5404         }
5405
5406         drm_dbg_kms(&i915->drm,
5407                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5408                     connector->base.base.id, connector->base.name,
5409                     yesno(intel_dp->dfp.rgb_to_ycbcr),
5410                     yesno(connector->base.ycbcr_420_allowed),
5411                     yesno(intel_dp->dfp.ycbcr_444_to_420));
5412 }
5413
5414 static void
5415 intel_dp_set_edid(struct intel_dp *intel_dp)
5416 {
5417         struct intel_connector *connector = intel_dp->attached_connector;
5418         struct edid *edid;
5419
5420         intel_dp_unset_edid(intel_dp);
5421         edid = intel_dp_get_edid(intel_dp);
5422         connector->detect_edid = edid;
5423
5424         intel_dp_update_dfp(intel_dp, edid);
5425         intel_dp_update_420(intel_dp);
5426
5427         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
5428                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
5429                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5430         }
5431
5432         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5433 }
5434
5435 static void
5436 intel_dp_unset_edid(struct intel_dp *intel_dp)
5437 {
5438         struct intel_connector *connector = intel_dp->attached_connector;
5439
5440         drm_dp_cec_unset_edid(&intel_dp->aux);
5441         kfree(connector->detect_edid);
5442         connector->detect_edid = NULL;
5443
5444         intel_dp->has_hdmi_sink = false;
5445         intel_dp->has_audio = false;
5446
5447         intel_dp->dfp.max_bpc = 0;
5448         intel_dp->dfp.max_dotclock = 0;
5449         intel_dp->dfp.min_tmds_clock = 0;
5450         intel_dp->dfp.max_tmds_clock = 0;
5451
5452         intel_dp->dfp.pcon_max_frl_bw = 0;
5453
5454         intel_dp->dfp.ycbcr_444_to_420 = false;
5455         connector->base.ycbcr_420_allowed = false;
5456 }
5457
5458 static int
5459 intel_dp_detect(struct drm_connector *connector,
5460                 struct drm_modeset_acquire_ctx *ctx,
5461                 bool force)
5462 {
5463         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5464         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5465         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5466         struct intel_encoder *encoder = &dig_port->base;
5467         enum drm_connector_status status;
5468
5469         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5470                     connector->base.id, connector->name);
5471         drm_WARN_ON(&dev_priv->drm,
5472                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5473
5474         if (!INTEL_DISPLAY_ENABLED(dev_priv))
5475                 return connector_status_disconnected;
5476
5477         /* Can't disconnect eDP */
5478         if (intel_dp_is_edp(intel_dp))
5479                 status = edp_detect(intel_dp);
5480         else if (intel_digital_port_connected(encoder))
5481                 status = intel_dp_detect_dpcd(intel_dp);
5482         else
5483                 status = connector_status_disconnected;
5484
5485         if (status == connector_status_disconnected) {
5486                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5487                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5488
5489                 if (intel_dp->is_mst) {
5490                         drm_dbg_kms(&dev_priv->drm,
5491                                     "MST device may have disappeared %d vs %d\n",
5492                                     intel_dp->is_mst,
5493                                     intel_dp->mst_mgr.mst_state);
5494                         intel_dp->is_mst = false;
5495                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5496                                                         intel_dp->is_mst);
5497                 }
5498
5499                 goto out;
5500         }
5501
5502         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5503         if (INTEL_GEN(dev_priv) >= 11)
5504                 intel_dp_get_dsc_sink_cap(intel_dp);
5505
5506         intel_dp_configure_mst(intel_dp);
5507
5508         /*
5509          * TODO: Reset link params when switching to MST mode, until MST
5510          * supports link training fallback params.
5511          */
5512         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5513                 /* Initial max link lane count */
5514                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5515
5516                 /* Initial max link rate */
5517                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5518
5519                 intel_dp->reset_link_params = false;
5520         }
5521
5522         intel_dp_print_rates(intel_dp);
5523
5524         if (intel_dp->is_mst) {
5525                 /*
5526                  * If we are in MST mode then this connector
5527                  * won't appear connected or have anything
5528                  * with EDID on it
5529                  */
5530                 status = connector_status_disconnected;
5531                 goto out;
5532         }
5533
5534         /*
5535          * Some external monitors do not signal loss of link synchronization
5536          * with an IRQ_HPD, so force a link status check.
5537          */
5538         if (!intel_dp_is_edp(intel_dp)) {
5539                 int ret;
5540
5541                 ret = intel_dp_retrain_link(encoder, ctx);
5542                 if (ret)
5543                         return ret;
5544         }
5545
5546         /*
5547          * Clearing NACK and defer counts to get their exact values
5548          * while reading EDID which are required by Compliance tests
5549          * 4.2.2.4 and 4.2.2.5
5550          */
5551         intel_dp->aux.i2c_nack_count = 0;
5552         intel_dp->aux.i2c_defer_count = 0;
5553
5554         intel_dp_set_edid(intel_dp);
5555         if (intel_dp_is_edp(intel_dp) ||
5556             to_intel_connector(connector)->detect_edid)
5557                 status = connector_status_connected;
5558
5559         intel_dp_check_device_service_irq(intel_dp);
5560
5561 out:
5562         if (status != connector_status_connected && !intel_dp->is_mst)
5563                 intel_dp_unset_edid(intel_dp);
5564
5565         /*
5566          * Make sure the refs for power wells enabled during detect are
5567          * dropped to avoid a new detect cycle triggered by HPD polling.
5568          */
5569         intel_display_power_flush_work(dev_priv);
5570
5571         if (!intel_dp_is_edp(intel_dp))
5572                 drm_dp_set_subconnector_property(connector,
5573                                                  status,
5574                                                  intel_dp->dpcd,
5575                                                  intel_dp->downstream_ports);
5576         return status;
5577 }
5578
5579 static void
5580 intel_dp_force(struct drm_connector *connector)
5581 {
5582         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5583         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5584         struct intel_encoder *intel_encoder = &dig_port->base;
5585         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5586         enum intel_display_power_domain aux_domain =
5587                 intel_aux_power_domain(dig_port);
5588         intel_wakeref_t wakeref;
5589
5590         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5591                     connector->base.id, connector->name);
5592         intel_dp_unset_edid(intel_dp);
5593
5594         if (connector->status != connector_status_connected)
5595                 return;
5596
5597         wakeref = intel_display_power_get(dev_priv, aux_domain);
5598
5599         intel_dp_set_edid(intel_dp);
5600
5601         intel_display_power_put(dev_priv, aux_domain, wakeref);
5602 }
5603
5604 static int intel_dp_get_modes(struct drm_connector *connector)
5605 {
5606         struct intel_connector *intel_connector = to_intel_connector(connector);
5607         struct edid *edid;
5608         int num_modes = 0;
5609
5610         edid = intel_connector->detect_edid;
5611         if (edid) {
5612                 num_modes = intel_connector_update_modes(connector, edid);
5613
5614                 if (intel_vrr_is_capable(connector))
5615                         drm_connector_set_vrr_capable_property(connector,
5616                                                                true);
5617         }
5618
5619         /* Also add fixed mode, which may or may not be present in EDID */
5620         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
5621             intel_connector->panel.fixed_mode) {
5622                 struct drm_display_mode *mode;
5623
5624                 mode = drm_mode_duplicate(connector->dev,
5625                                           intel_connector->panel.fixed_mode);
5626                 if (mode) {
5627                         drm_mode_probed_add(connector, mode);
5628                         num_modes++;
5629                 }
5630         }
5631
5632         if (num_modes)
5633                 return num_modes;
5634
5635         if (!edid) {
5636                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5637                 struct drm_display_mode *mode;
5638
5639                 mode = drm_dp_downstream_mode(connector->dev,
5640                                               intel_dp->dpcd,
5641                                               intel_dp->downstream_ports);
5642                 if (mode) {
5643                         drm_mode_probed_add(connector, mode);
5644                         num_modes++;
5645                 }
5646         }
5647
5648         return num_modes;
5649 }
5650
5651 static int
5652 intel_dp_connector_register(struct drm_connector *connector)
5653 {
5654         struct drm_i915_private *i915 = to_i915(connector->dev);
5655         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5656         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5657         struct intel_lspcon *lspcon = &dig_port->lspcon;
5658         int ret;
5659
5660         ret = intel_connector_register(connector);
5661         if (ret)
5662                 return ret;
5663
5664         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5665                     intel_dp->aux.name, connector->kdev->kobj.name);
5666
5667         intel_dp->aux.dev = connector->kdev;
5668         ret = drm_dp_aux_register(&intel_dp->aux);
5669         if (!ret)
5670                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5671
5672         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
5673                 return ret;
5674
5675         /*
5676          * ToDo: Clean this up to handle lspcon init and resume more
5677          * efficiently and streamlined.
5678          */
5679         if (lspcon_init(dig_port)) {
5680                 lspcon_detect_hdr_capability(lspcon);
5681                 if (lspcon->hdr_supported)
5682                         drm_object_attach_property(&connector->base,
5683                                                    connector->dev->mode_config.hdr_output_metadata_property,
5684                                                    0);
5685         }
5686
5687         return ret;
5688 }
5689
5690 static void
5691 intel_dp_connector_unregister(struct drm_connector *connector)
5692 {
5693         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5694
5695         drm_dp_cec_unregister_connector(&intel_dp->aux);
5696         drm_dp_aux_unregister(&intel_dp->aux);
5697         intel_connector_unregister(connector);
5698 }
5699
5700 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5701 {
5702         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5703         struct intel_dp *intel_dp = &dig_port->dp;
5704
5705         intel_dp_mst_encoder_cleanup(dig_port);
5706
5707         intel_pps_vdd_off_sync(intel_dp);
5708
5709         intel_dp_aux_fini(intel_dp);
5710 }
5711
5712 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5713 {
5714         intel_dp_encoder_flush_work(encoder);
5715
5716         drm_encoder_cleanup(encoder);
5717         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
5718 }
5719
5720 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5721 {
5722         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5723
5724         intel_pps_vdd_off_sync(intel_dp);
5725 }
5726
5727 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5728 {
5729         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5730
5731         intel_pps_wait_power_cycle(intel_dp);
5732 }
5733
5734 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5735 {
5736         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5737         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5738         enum pipe pipe;
5739
5740         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5741                                   encoder->port, &pipe))
5742                 return pipe;
5743
5744         return INVALID_PIPE;
5745 }
5746
5747 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5748 {
5749         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5750         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
5751
5752         if (!HAS_DDI(dev_priv))
5753                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5754
5755         intel_dp->reset_link_params = true;
5756
5757         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5758                 intel_wakeref_t wakeref;
5759
5760                 with_intel_pps_lock(intel_dp, wakeref)
5761                         intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5762         }
5763
5764         intel_pps_encoder_reset(intel_dp);
5765 }
5766
5767 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5768                                     int tile_group_id)
5769 {
5770         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5771         struct drm_connector_list_iter conn_iter;
5772         struct drm_connector *connector;
5773         int ret = 0;
5774
5775         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5776         drm_for_each_connector_iter(connector, &conn_iter) {
5777                 struct drm_connector_state *conn_state;
5778                 struct intel_crtc_state *crtc_state;
5779                 struct intel_crtc *crtc;
5780
5781                 if (!connector->has_tile ||
5782                     connector->tile_group->id != tile_group_id)
5783                         continue;
5784
5785                 conn_state = drm_atomic_get_connector_state(&state->base,
5786                                                             connector);
5787                 if (IS_ERR(conn_state)) {
5788                         ret = PTR_ERR(conn_state);
5789                         break;
5790                 }
5791
5792                 crtc = to_intel_crtc(conn_state->crtc);
5793
5794                 if (!crtc)
5795                         continue;
5796
5797                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5798                 crtc_state->uapi.mode_changed = true;
5799
5800                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5801                 if (ret)
5802                         break;
5803         }
5804         drm_connector_list_iter_end(&conn_iter);
5805
5806         return ret;
5807 }
5808
5809 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5810 {
5811         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5812         struct intel_crtc *crtc;
5813
5814         if (transcoders == 0)
5815                 return 0;
5816
5817         for_each_intel_crtc(&dev_priv->drm, crtc) {
5818                 struct intel_crtc_state *crtc_state;
5819                 int ret;
5820
5821                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5822                 if (IS_ERR(crtc_state))
5823                         return PTR_ERR(crtc_state);
5824
5825                 if (!crtc_state->hw.enable)
5826                         continue;
5827
5828                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5829                         continue;
5830
5831                 crtc_state->uapi.mode_changed = true;
5832
5833                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5834                 if (ret)
5835                         return ret;
5836
5837                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5838                 if (ret)
5839                         return ret;
5840
5841                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5842         }
5843
5844         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5845
5846         return 0;
5847 }
5848
5849 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5850                                       struct drm_connector *connector)
5851 {
5852         const struct drm_connector_state *old_conn_state =
5853                 drm_atomic_get_old_connector_state(&state->base, connector);
5854         const struct intel_crtc_state *old_crtc_state;
5855         struct intel_crtc *crtc;
5856         u8 transcoders;
5857
5858         crtc = to_intel_crtc(old_conn_state->crtc);
5859         if (!crtc)
5860                 return 0;
5861
5862         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5863
5864         if (!old_crtc_state->hw.active)
5865                 return 0;
5866
5867         transcoders = old_crtc_state->sync_mode_slaves_mask;
5868         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5869                 transcoders |= BIT(old_crtc_state->master_transcoder);
5870
5871         return intel_modeset_affected_transcoders(state,
5872                                                   transcoders);
5873 }
5874
5875 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5876                                            struct drm_atomic_state *_state)
5877 {
5878         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5879         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5880         int ret;
5881
5882         ret = intel_digital_connector_atomic_check(conn, &state->base);
5883         if (ret)
5884                 return ret;
5885
5886         /*
5887          * We don't enable port sync on BDW due to missing w/as and
5888          * due to not having adjusted the modeset sequence appropriately.
5889          */
5890         if (INTEL_GEN(dev_priv) < 9)
5891                 return 0;
5892
5893         if (!intel_connector_needs_modeset(state, conn))
5894                 return 0;
5895
5896         if (conn->has_tile) {
5897                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5898                 if (ret)
5899                         return ret;
5900         }
5901
5902         return intel_modeset_synced_crtcs(state, conn);
5903 }
5904
5905 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5906         .force = intel_dp_force,
5907         .fill_modes = drm_helper_probe_single_connector_modes,
5908         .atomic_get_property = intel_digital_connector_atomic_get_property,
5909         .atomic_set_property = intel_digital_connector_atomic_set_property,
5910         .late_register = intel_dp_connector_register,
5911         .early_unregister = intel_dp_connector_unregister,
5912         .destroy = intel_connector_destroy,
5913         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5914         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5915 };
5916
5917 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5918         .detect_ctx = intel_dp_detect,
5919         .get_modes = intel_dp_get_modes,
5920         .mode_valid = intel_dp_mode_valid,
5921         .atomic_check = intel_dp_connector_atomic_check,
5922 };
5923
5924 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5925         .reset = intel_dp_encoder_reset,
5926         .destroy = intel_dp_encoder_destroy,
5927 };
5928
5929 enum irqreturn
5930 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5931 {
5932         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5933         struct intel_dp *intel_dp = &dig_port->dp;
5934
5935         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5936             (long_hpd || !intel_pps_have_power(intel_dp))) {
5937                 /*
5938                  * vdd off can generate a long/short pulse on eDP which
5939                  * would require vdd on to handle it, and thus we
5940                  * would end up in an endless cycle of
5941                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5942                  */
5943                 drm_dbg_kms(&i915->drm,
5944                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5945                             long_hpd ? "long" : "short",
5946                             dig_port->base.base.base.id,
5947                             dig_port->base.base.name);
5948                 return IRQ_HANDLED;
5949         }
5950
5951         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5952                     dig_port->base.base.base.id,
5953                     dig_port->base.base.name,
5954                     long_hpd ? "long" : "short");
5955
5956         if (long_hpd) {
5957                 intel_dp->reset_link_params = true;
5958                 return IRQ_NONE;
5959         }
5960
5961         if (intel_dp->is_mst) {
5962                 if (!intel_dp_check_mst_status(intel_dp))
5963                         return IRQ_NONE;
5964         } else if (!intel_dp_short_pulse(intel_dp)) {
5965                 return IRQ_NONE;
5966         }
5967
5968         return IRQ_HANDLED;
5969 }
5970
5971 /* check the VBT to see whether the eDP is on another port */
5972 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5973 {
5974         /*
5975          * eDP not supported on g4x. so bail out early just
5976          * for a bit extra safety in case the VBT is bonkers.
5977          */
5978         if (INTEL_GEN(dev_priv) < 5)
5979                 return false;
5980
5981         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5982                 return true;
5983
5984         return intel_bios_is_port_edp(dev_priv, port);
5985 }
5986
5987 static void
5988 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5989 {
5990         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5991         enum port port = dp_to_dig_port(intel_dp)->base.port;
5992
5993         if (!intel_dp_is_edp(intel_dp))
5994                 drm_connector_attach_dp_subconnector_property(connector);
5995
5996         if (!IS_G4X(dev_priv) && port != PORT_A)
5997                 intel_attach_force_audio_property(connector);
5998
5999         intel_attach_broadcast_rgb_property(connector);
6000         if (HAS_GMCH(dev_priv))
6001                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6002         else if (INTEL_GEN(dev_priv) >= 5)
6003                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6004
6005         /* Register HDMI colorspace for case of lspcon */
6006         if (intel_bios_is_lspcon_present(dev_priv, port)) {
6007                 drm_connector_attach_content_type_property(connector);
6008                 intel_attach_hdmi_colorspace_property(connector);
6009         } else {
6010                 intel_attach_dp_colorspace_property(connector);
6011         }
6012
6013         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6014                 drm_object_attach_property(&connector->base,
6015                                            connector->dev->mode_config.hdr_output_metadata_property,
6016                                            0);
6017
6018         if (intel_dp_is_edp(intel_dp)) {
6019                 u32 allowed_scalers;
6020
6021                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6022                 if (!HAS_GMCH(dev_priv))
6023                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6024
6025                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6026
6027                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6028
6029         }
6030
6031         if (HAS_VRR(dev_priv))
6032                 drm_connector_attach_vrr_capable_property(connector);
6033 }
6034
6035 /**
6036  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6037  * @dev_priv: i915 device
6038  * @crtc_state: a pointer to the active intel_crtc_state
6039  * @refresh_rate: RR to be programmed
6040  *
6041  * This function gets called when refresh rate (RR) has to be changed from
6042  * one frequency to another. Switches can be between high and low RR
6043  * supported by the panel or to any other RR based on media playback (in
6044  * this case, RR value needs to be passed from user space).
6045  *
6046  * The caller of this function needs to take a lock on dev_priv->drrs.
6047  */
6048 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6049                                     const struct intel_crtc_state *crtc_state,
6050                                     int refresh_rate)
6051 {
6052         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
6054         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6055
6056         if (refresh_rate <= 0) {
6057                 drm_dbg_kms(&dev_priv->drm,
6058                             "Refresh rate should be positive non-zero.\n");
6059                 return;
6060         }
6061
6062         if (intel_dp == NULL) {
6063                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
6064                 return;
6065         }
6066
6067         if (!intel_crtc) {
6068                 drm_dbg_kms(&dev_priv->drm,
6069                             "DRRS: intel_crtc not initialized\n");
6070                 return;
6071         }
6072
6073         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6074                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
6075                 return;
6076         }
6077
6078         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
6079                         refresh_rate)
6080                 index = DRRS_LOW_RR;
6081
6082         if (index == dev_priv->drrs.refresh_rate_type) {
6083                 drm_dbg_kms(&dev_priv->drm,
6084                             "DRRS requested for previously set RR...ignoring\n");
6085                 return;
6086         }
6087
6088         if (!crtc_state->hw.active) {
6089                 drm_dbg_kms(&dev_priv->drm,
6090                             "eDP encoder disabled. CRTC not Active\n");
6091                 return;
6092         }
6093
6094         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6095                 switch (index) {
6096                 case DRRS_HIGH_RR:
6097                         intel_dp_set_m_n(crtc_state, M1_N1);
6098                         break;
6099                 case DRRS_LOW_RR:
6100                         intel_dp_set_m_n(crtc_state, M2_N2);
6101                         break;
6102                 case DRRS_MAX_RR:
6103                 default:
6104                         drm_err(&dev_priv->drm,
6105                                 "Unsupported refreshrate type\n");
6106                 }
6107         } else if (INTEL_GEN(dev_priv) > 6) {
6108                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6109                 u32 val;
6110
6111                 val = intel_de_read(dev_priv, reg);
6112                 if (index > DRRS_HIGH_RR) {
6113                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6114                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6115                         else
6116                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6117                 } else {
6118                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6119                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6120                         else
6121                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6122                 }
6123                 intel_de_write(dev_priv, reg, val);
6124         }
6125
6126         dev_priv->drrs.refresh_rate_type = index;
6127
6128         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
6129                     refresh_rate);
6130 }
6131
6132 static void
6133 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
6134 {
6135         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6136
6137         dev_priv->drrs.busy_frontbuffer_bits = 0;
6138         dev_priv->drrs.dp = intel_dp;
6139 }
6140
6141 /**
6142  * intel_edp_drrs_enable - init drrs struct if supported
6143  * @intel_dp: DP struct
6144  * @crtc_state: A pointer to the active crtc state.
6145  *
6146  * Initializes frontbuffer_bits and drrs.dp
6147  */
6148 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6149                            const struct intel_crtc_state *crtc_state)
6150 {
6151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6152
6153         if (!crtc_state->has_drrs)
6154                 return;
6155
6156         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
6157
6158         mutex_lock(&dev_priv->drrs.mutex);
6159
6160         if (dev_priv->drrs.dp) {
6161                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
6162                 goto unlock;
6163         }
6164
6165         intel_edp_drrs_enable_locked(intel_dp);
6166
6167 unlock:
6168         mutex_unlock(&dev_priv->drrs.mutex);
6169 }
6170
6171 static void
6172 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
6173                               const struct intel_crtc_state *crtc_state)
6174 {
6175         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6176
6177         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
6178                 int refresh;
6179
6180                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
6181                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
6182         }
6183
6184         dev_priv->drrs.dp = NULL;
6185 }
6186
6187 /**
6188  * intel_edp_drrs_disable - Disable DRRS
6189  * @intel_dp: DP struct
6190  * @old_crtc_state: Pointer to old crtc_state.
6191  *
6192  */
6193 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6194                             const struct intel_crtc_state *old_crtc_state)
6195 {
6196         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6197
6198         if (!old_crtc_state->has_drrs)
6199                 return;
6200
6201         mutex_lock(&dev_priv->drrs.mutex);
6202         if (!dev_priv->drrs.dp) {
6203                 mutex_unlock(&dev_priv->drrs.mutex);
6204                 return;
6205         }
6206
6207         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
6208         mutex_unlock(&dev_priv->drrs.mutex);
6209
6210         cancel_delayed_work_sync(&dev_priv->drrs.work);
6211 }
6212
6213 /**
6214  * intel_edp_drrs_update - Update DRRS state
6215  * @intel_dp: Intel DP
6216  * @crtc_state: new CRTC state
6217  *
6218  * This function will update DRRS states, disabling or enabling DRRS when
6219  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
6220  * intel_edp_drrs_enable() should be called instead.
6221  */
6222 void
6223 intel_edp_drrs_update(struct intel_dp *intel_dp,
6224                       const struct intel_crtc_state *crtc_state)
6225 {
6226         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6227
6228         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
6229                 return;
6230
6231         mutex_lock(&dev_priv->drrs.mutex);
6232
6233         /* New state matches current one? */
6234         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
6235                 goto unlock;
6236
6237         if (crtc_state->has_drrs)
6238                 intel_edp_drrs_enable_locked(intel_dp);
6239         else
6240                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
6241
6242 unlock:
6243         mutex_unlock(&dev_priv->drrs.mutex);
6244 }
6245
6246 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6247 {
6248         struct drm_i915_private *dev_priv =
6249                 container_of(work, typeof(*dev_priv), drrs.work.work);
6250         struct intel_dp *intel_dp;
6251
6252         mutex_lock(&dev_priv->drrs.mutex);
6253
6254         intel_dp = dev_priv->drrs.dp;
6255
6256         if (!intel_dp)
6257                 goto unlock;
6258
6259         /*
6260          * The delayed work can race with an invalidate hence we need to
6261          * recheck.
6262          */
6263
6264         if (dev_priv->drrs.busy_frontbuffer_bits)
6265                 goto unlock;
6266
6267         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6268                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6269
6270                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6271                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
6272         }
6273
6274 unlock:
6275         mutex_unlock(&dev_priv->drrs.mutex);
6276 }
6277
6278 /**
6279  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6280  * @dev_priv: i915 device
6281  * @frontbuffer_bits: frontbuffer plane tracking bits
6282  *
6283  * This function gets called everytime rendering on the given planes start.
6284  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6285  *
6286  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6287  */
6288 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6289                                unsigned int frontbuffer_bits)
6290 {
6291         struct intel_dp *intel_dp;
6292         struct drm_crtc *crtc;
6293         enum pipe pipe;
6294
6295         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6296                 return;
6297
6298         cancel_delayed_work(&dev_priv->drrs.work);
6299
6300         mutex_lock(&dev_priv->drrs.mutex);
6301
6302         intel_dp = dev_priv->drrs.dp;
6303         if (!intel_dp) {
6304                 mutex_unlock(&dev_priv->drrs.mutex);
6305                 return;
6306         }
6307
6308         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6309         pipe = to_intel_crtc(crtc)->pipe;
6310
6311         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6312         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6313
6314         /* invalidate means busy screen hence upclock */
6315         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6316                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6317                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
6318
6319         mutex_unlock(&dev_priv->drrs.mutex);
6320 }
6321
6322 /**
6323  * intel_edp_drrs_flush - Restart Idleness DRRS
6324  * @dev_priv: i915 device
6325  * @frontbuffer_bits: frontbuffer plane tracking bits
6326  *
6327  * This function gets called every time rendering on the given planes has
6328  * completed or flip on a crtc is completed. So DRRS should be upclocked
6329  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6330  * if no other planes are dirty.
6331  *
6332  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6333  */
6334 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6335                           unsigned int frontbuffer_bits)
6336 {
6337         struct intel_dp *intel_dp;
6338         struct drm_crtc *crtc;
6339         enum pipe pipe;
6340
6341         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6342                 return;
6343
6344         cancel_delayed_work(&dev_priv->drrs.work);
6345
6346         mutex_lock(&dev_priv->drrs.mutex);
6347
6348         intel_dp = dev_priv->drrs.dp;
6349         if (!intel_dp) {
6350                 mutex_unlock(&dev_priv->drrs.mutex);
6351                 return;
6352         }
6353
6354         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6355         pipe = to_intel_crtc(crtc)->pipe;
6356
6357         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6358         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6359
6360         /* flush means busy screen hence upclock */
6361         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6362                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6363                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
6364
6365         /*
6366          * flush also means no more activity hence schedule downclock, if all
6367          * other fbs are quiescent too
6368          */
6369         if (!dev_priv->drrs.busy_frontbuffer_bits)
6370                 schedule_delayed_work(&dev_priv->drrs.work,
6371                                 msecs_to_jiffies(1000));
6372         mutex_unlock(&dev_priv->drrs.mutex);
6373 }
6374
6375 /**
6376  * DOC: Display Refresh Rate Switching (DRRS)
6377  *
6378  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6379  * which enables swtching between low and high refresh rates,
6380  * dynamically, based on the usage scenario. This feature is applicable
6381  * for internal panels.
6382  *
6383  * Indication that the panel supports DRRS is given by the panel EDID, which
6384  * would list multiple refresh rates for one resolution.
6385  *
6386  * DRRS is of 2 types - static and seamless.
6387  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6388  * (may appear as a blink on screen) and is used in dock-undock scenario.
6389  * Seamless DRRS involves changing RR without any visual effect to the user
6390  * and can be used during normal system usage. This is done by programming
6391  * certain registers.
6392  *
6393  * Support for static/seamless DRRS may be indicated in the VBT based on
6394  * inputs from the panel spec.
6395  *
6396  * DRRS saves power by switching to low RR based on usage scenarios.
6397  *
6398  * The implementation is based on frontbuffer tracking implementation.  When
6399  * there is a disturbance on the screen triggered by user activity or a periodic
6400  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6401  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6402  * made.
6403  *
6404  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6405  * and intel_edp_drrs_flush() are called.
6406  *
6407  * DRRS can be further extended to support other internal panels and also
6408  * the scenario of video playback wherein RR is set based on the rate
6409  * requested by userspace.
6410  */
6411
6412 /**
6413  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6414  * @connector: eDP connector
6415  * @fixed_mode: preferred mode of panel
6416  *
6417  * This function is  called only once at driver load to initialize basic
6418  * DRRS stuff.
6419  *
6420  * Returns:
6421  * Downclock mode if panel supports it, else return NULL.
6422  * DRRS support is determined by the presence of downclock mode (apart
6423  * from VBT setting).
6424  */
6425 static struct drm_display_mode *
6426 intel_dp_drrs_init(struct intel_connector *connector,
6427                    struct drm_display_mode *fixed_mode)
6428 {
6429         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6430         struct drm_display_mode *downclock_mode = NULL;
6431
6432         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6433         mutex_init(&dev_priv->drrs.mutex);
6434
6435         if (INTEL_GEN(dev_priv) <= 6) {
6436                 drm_dbg_kms(&dev_priv->drm,
6437                             "DRRS supported for Gen7 and above\n");
6438                 return NULL;
6439         }
6440
6441         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6442                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
6443                 return NULL;
6444         }
6445
6446         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
6447         if (!downclock_mode) {
6448                 drm_dbg_kms(&dev_priv->drm,
6449                             "Downclock mode is not found. DRRS not supported\n");
6450                 return NULL;
6451         }
6452
6453         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6454
6455         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6456         drm_dbg_kms(&dev_priv->drm,
6457                     "seamless DRRS supported for eDP panel.\n");
6458         return downclock_mode;
6459 }
6460
6461 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6462                                      struct intel_connector *intel_connector)
6463 {
6464         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6465         struct drm_device *dev = &dev_priv->drm;
6466         struct drm_connector *connector = &intel_connector->base;
6467         struct drm_display_mode *fixed_mode = NULL;
6468         struct drm_display_mode *downclock_mode = NULL;
6469         bool has_dpcd;
6470         enum pipe pipe = INVALID_PIPE;
6471         struct edid *edid;
6472
6473         if (!intel_dp_is_edp(intel_dp))
6474                 return true;
6475
6476         /*
6477          * On IBX/CPT we may get here with LVDS already registered. Since the
6478          * driver uses the only internal power sequencer available for both
6479          * eDP and LVDS bail out early in this case to prevent interfering
6480          * with an already powered-on LVDS power sequencer.
6481          */
6482         if (intel_get_lvds_encoder(dev_priv)) {
6483                 drm_WARN_ON(dev,
6484                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6485                 drm_info(&dev_priv->drm,
6486                          "LVDS was detected, not registering eDP\n");
6487
6488                 return false;
6489         }
6490
6491         intel_pps_init(intel_dp);
6492
6493         /* Cache DPCD and EDID for edp. */
6494         has_dpcd = intel_edp_init_dpcd(intel_dp);
6495
6496         if (!has_dpcd) {
6497                 /* if this fails, presume the device is a ghost */
6498                 drm_info(&dev_priv->drm,
6499                          "failed to retrieve link info, disabling eDP\n");
6500                 goto out_vdd_off;
6501         }
6502
6503         mutex_lock(&dev->mode_config.mutex);
6504         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6505         if (edid) {
6506                 if (drm_add_edid_modes(connector, edid)) {
6507                         drm_connector_update_edid_property(connector, edid);
6508                 } else {
6509                         kfree(edid);
6510                         edid = ERR_PTR(-EINVAL);
6511                 }
6512         } else {
6513                 edid = ERR_PTR(-ENOENT);
6514         }
6515         intel_connector->edid = edid;
6516
6517         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
6518         if (fixed_mode)
6519                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
6520
6521         /* multiply the mode clock and horizontal timings for MSO */
6522         intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6523         intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
6524
6525         /* fallback to VBT if available for eDP */
6526         if (!fixed_mode)
6527                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
6528         mutex_unlock(&dev->mode_config.mutex);
6529
6530         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6531                 /*
6532                  * Figure out the current pipe for the initial backlight setup.
6533                  * If the current pipe isn't valid, try the PPS pipe, and if that
6534                  * fails just assume pipe A.
6535                  */
6536                 pipe = vlv_active_pipe(intel_dp);
6537
6538                 if (pipe != PIPE_A && pipe != PIPE_B)
6539                         pipe = intel_dp->pps.pps_pipe;
6540
6541                 if (pipe != PIPE_A && pipe != PIPE_B)
6542                         pipe = PIPE_A;
6543
6544                 drm_dbg_kms(&dev_priv->drm,
6545                             "using pipe %c for initial backlight setup\n",
6546                             pipe_name(pipe));
6547         }
6548
6549         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6550         intel_connector->panel.backlight.power = intel_pps_backlight_power;
6551         intel_panel_setup_backlight(connector, pipe);
6552
6553         if (fixed_mode) {
6554                 drm_connector_set_panel_orientation_with_quirk(connector,
6555                                 dev_priv->vbt.orientation,
6556                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
6557         }
6558
6559         return true;
6560
6561 out_vdd_off:
6562         intel_pps_vdd_off_sync(intel_dp);
6563
6564         return false;
6565 }
6566
6567 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6568 {
6569         struct intel_connector *intel_connector;
6570         struct drm_connector *connector;
6571
6572         intel_connector = container_of(work, typeof(*intel_connector),
6573                                        modeset_retry_work);
6574         connector = &intel_connector->base;
6575         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6576                       connector->name);
6577
6578         /* Grab the locks before changing connector property*/
6579         mutex_lock(&connector->dev->mode_config.mutex);
6580         /* Set connector link status to BAD and send a Uevent to notify
6581          * userspace to do a modeset.
6582          */
6583         drm_connector_set_link_status_property(connector,
6584                                                DRM_MODE_LINK_STATUS_BAD);
6585         mutex_unlock(&connector->dev->mode_config.mutex);
6586         /* Send Hotplug uevent so userspace can reprobe */
6587         drm_kms_helper_hotplug_event(connector->dev);
6588 }
6589
6590 bool
6591 intel_dp_init_connector(struct intel_digital_port *dig_port,
6592                         struct intel_connector *intel_connector)
6593 {
6594         struct drm_connector *connector = &intel_connector->base;
6595         struct intel_dp *intel_dp = &dig_port->dp;
6596         struct intel_encoder *intel_encoder = &dig_port->base;
6597         struct drm_device *dev = intel_encoder->base.dev;
6598         struct drm_i915_private *dev_priv = to_i915(dev);
6599         enum port port = intel_encoder->port;
6600         enum phy phy = intel_port_to_phy(dev_priv, port);
6601         int type;
6602
6603         /* Initialize the work for modeset in case of link train failure */
6604         INIT_WORK(&intel_connector->modeset_retry_work,
6605                   intel_dp_modeset_retry_work_fn);
6606
6607         if (drm_WARN(dev, dig_port->max_lanes < 1,
6608                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6609                      dig_port->max_lanes, intel_encoder->base.base.id,
6610                      intel_encoder->base.name))
6611                 return false;
6612
6613         intel_dp_set_source_rates(intel_dp);
6614
6615         intel_dp->reset_link_params = true;
6616         intel_dp->pps.pps_pipe = INVALID_PIPE;
6617         intel_dp->pps.active_pipe = INVALID_PIPE;
6618
6619         /* Preserve the current hw state. */
6620         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6621         intel_dp->attached_connector = intel_connector;
6622
6623         if (intel_dp_is_port_edp(dev_priv, port)) {
6624                 /*
6625                  * Currently we don't support eDP on TypeC ports, although in
6626                  * theory it could work on TypeC legacy ports.
6627                  */
6628                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6629                 type = DRM_MODE_CONNECTOR_eDP;
6630         } else {
6631                 type = DRM_MODE_CONNECTOR_DisplayPort;
6632         }
6633
6634         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6635                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6636
6637         /*
6638          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6639          * for DP the encoder type can be set by the caller to
6640          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6641          */
6642         if (type == DRM_MODE_CONNECTOR_eDP)
6643                 intel_encoder->type = INTEL_OUTPUT_EDP;
6644
6645         /* eDP only on port B and/or C on vlv/chv */
6646         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6647                               IS_CHERRYVIEW(dev_priv)) &&
6648                         intel_dp_is_edp(intel_dp) &&
6649                         port != PORT_B && port != PORT_C))
6650                 return false;
6651
6652         drm_dbg_kms(&dev_priv->drm,
6653                     "Adding %s connector on [ENCODER:%d:%s]\n",
6654                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6655                     intel_encoder->base.base.id, intel_encoder->base.name);
6656
6657         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6658         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6659
6660         if (!HAS_GMCH(dev_priv))
6661                 connector->interlace_allowed = true;
6662         connector->doublescan_allowed = 0;
6663
6664         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6665
6666         intel_dp_aux_init(intel_dp);
6667
6668         intel_connector_attach_encoder(intel_connector, intel_encoder);
6669
6670         if (HAS_DDI(dev_priv))
6671                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6672         else
6673                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6674
6675         /* init MST on ports that can support it */
6676         intel_dp_mst_encoder_init(dig_port,
6677                                   intel_connector->base.base.id);
6678
6679         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6680                 intel_dp_aux_fini(intel_dp);
6681                 intel_dp_mst_encoder_cleanup(dig_port);
6682                 goto fail;
6683         }
6684
6685         intel_dp_add_properties(intel_dp, connector);
6686
6687         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6688                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
6689                 if (ret)
6690                         drm_dbg_kms(&dev_priv->drm,
6691                                     "HDCP init failed, skipping.\n");
6692         }
6693
6694         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6695          * 0xd.  Failure to do so will result in spurious interrupts being
6696          * generated on the port when a cable is not attached.
6697          */
6698         if (IS_G45(dev_priv)) {
6699                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
6700                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
6701                                (temp & ~0xf) | 0xd);
6702         }
6703
6704         intel_dp->frl.is_trained = false;
6705         intel_dp->frl.trained_rate_gbps = 0;
6706
6707         intel_psr_init(intel_dp);
6708
6709         return true;
6710
6711 fail:
6712         drm_connector_cleanup(connector);
6713
6714         return false;
6715 }
6716
6717 bool intel_dp_init(struct drm_i915_private *dev_priv,
6718                    i915_reg_t output_reg,
6719                    enum port port)
6720 {
6721         struct intel_digital_port *dig_port;
6722         struct intel_encoder *intel_encoder;
6723         struct drm_encoder *encoder;
6724         struct intel_connector *intel_connector;
6725
6726         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
6727         if (!dig_port)
6728                 return false;
6729
6730         intel_connector = intel_connector_alloc();
6731         if (!intel_connector)
6732                 goto err_connector_alloc;
6733
6734         intel_encoder = &dig_port->base;
6735         encoder = &intel_encoder->base;
6736
6737         mutex_init(&dig_port->hdcp_mutex);
6738
6739         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6740                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6741                              "DP %c", port_name(port)))
6742                 goto err_encoder_init;
6743
6744         intel_encoder->hotplug = intel_dp_hotplug;
6745         intel_encoder->compute_config = intel_dp_compute_config;
6746         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6747         intel_encoder->get_config = intel_dp_get_config;
6748         intel_encoder->sync_state = intel_dp_sync_state;
6749         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
6750         intel_encoder->update_pipe = intel_panel_update_backlight;
6751         intel_encoder->suspend = intel_dp_encoder_suspend;
6752         intel_encoder->shutdown = intel_dp_encoder_shutdown;
6753         if (IS_CHERRYVIEW(dev_priv)) {
6754                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6755                 intel_encoder->pre_enable = chv_pre_enable_dp;
6756                 intel_encoder->enable = vlv_enable_dp;
6757                 intel_encoder->disable = vlv_disable_dp;
6758                 intel_encoder->post_disable = chv_post_disable_dp;
6759                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6760         } else if (IS_VALLEYVIEW(dev_priv)) {
6761                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6762                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6763                 intel_encoder->enable = vlv_enable_dp;
6764                 intel_encoder->disable = vlv_disable_dp;
6765                 intel_encoder->post_disable = vlv_post_disable_dp;
6766         } else {
6767                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6768                 intel_encoder->enable = g4x_enable_dp;
6769                 intel_encoder->disable = g4x_disable_dp;
6770                 intel_encoder->post_disable = g4x_post_disable_dp;
6771         }
6772
6773         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
6774             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
6775                 dig_port->dp.set_link_train = cpt_set_link_train;
6776         else
6777                 dig_port->dp.set_link_train = g4x_set_link_train;
6778
6779         if (IS_CHERRYVIEW(dev_priv))
6780                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
6781         else if (IS_VALLEYVIEW(dev_priv))
6782                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
6783         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
6784                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
6785         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
6786                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
6787         else
6788                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
6789
6790         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
6791             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
6792                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
6793                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
6794         } else {
6795                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
6796                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
6797         }
6798
6799         dig_port->dp.output_reg = output_reg;
6800         dig_port->max_lanes = 4;
6801
6802         intel_encoder->type = INTEL_OUTPUT_DP;
6803         intel_encoder->power_domain = intel_port_to_power_domain(port);
6804         if (IS_CHERRYVIEW(dev_priv)) {
6805                 if (port == PORT_D)
6806                         intel_encoder->pipe_mask = BIT(PIPE_C);
6807                 else
6808                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
6809         } else {
6810                 intel_encoder->pipe_mask = ~0;
6811         }
6812         intel_encoder->cloneable = 0;
6813         intel_encoder->port = port;
6814         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6815
6816         dig_port->hpd_pulse = intel_dp_hpd_pulse;
6817
6818         if (HAS_GMCH(dev_priv)) {
6819                 if (IS_GM45(dev_priv))
6820                         dig_port->connected = gm45_digital_port_connected;
6821                 else
6822                         dig_port->connected = g4x_digital_port_connected;
6823         } else {
6824                 if (port == PORT_A)
6825                         dig_port->connected = ilk_digital_port_connected;
6826                 else
6827                         dig_port->connected = ibx_digital_port_connected;
6828         }
6829
6830         if (port != PORT_A)
6831                 intel_infoframe_init(dig_port);
6832
6833         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
6834         if (!intel_dp_init_connector(dig_port, intel_connector))
6835                 goto err_init_connector;
6836
6837         return true;
6838
6839 err_init_connector:
6840         drm_encoder_cleanup(encoder);
6841 err_encoder_init:
6842         kfree(intel_connector);
6843 err_connector_alloc:
6844         kfree(dig_port);
6845         return false;
6846 }
6847
6848 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6849 {
6850         struct intel_encoder *encoder;
6851
6852         for_each_intel_encoder(&dev_priv->drm, encoder) {
6853                 struct intel_dp *intel_dp;
6854
6855                 if (encoder->type != INTEL_OUTPUT_DDI)
6856                         continue;
6857
6858                 intel_dp = enc_to_intel_dp(encoder);
6859
6860                 if (!intel_dp->can_mst)
6861                         continue;
6862
6863                 if (intel_dp->is_mst)
6864                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6865         }
6866 }
6867
6868 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6869 {
6870         struct intel_encoder *encoder;
6871
6872         for_each_intel_encoder(&dev_priv->drm, encoder) {
6873                 struct intel_dp *intel_dp;
6874                 int ret;
6875
6876                 if (encoder->type != INTEL_OUTPUT_DDI)
6877                         continue;
6878
6879                 intel_dp = enc_to_intel_dp(encoder);
6880
6881                 if (!intel_dp->can_mst)
6882                         continue;
6883
6884                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6885                                                      true);
6886                 if (ret) {
6887                         intel_dp->is_mst = false;
6888                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6889                                                         false);
6890                 }
6891         }
6892 }