2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/string_helpers.h>
33 #include <linux/timekeeping.h>
34 #include <linux/types.h>
36 #include <asm/byteorder.h>
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/display/drm_dsc_helper.h>
40 #include <drm/display/drm_hdmi_helper.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_probe_helper.h>
50 #include "intel_atomic.h"
51 #include "intel_audio.h"
52 #include "intel_backlight.h"
53 #include "intel_combo_phy_regs.h"
54 #include "intel_connector.h"
55 #include "intel_crtc.h"
56 #include "intel_cx0_phy.h"
57 #include "intel_ddi.h"
59 #include "intel_display_types.h"
61 #include "intel_dp_aux.h"
62 #include "intel_dp_hdcp.h"
63 #include "intel_dp_link_training.h"
64 #include "intel_dp_mst.h"
65 #include "intel_dpio_phy.h"
66 #include "intel_dpll.h"
67 #include "intel_fifo_underrun.h"
68 #include "intel_hdcp.h"
69 #include "intel_hdmi.h"
70 #include "intel_hotplug.h"
71 #include "intel_hotplug_irq.h"
72 #include "intel_lspcon.h"
73 #include "intel_lvds.h"
74 #include "intel_panel.h"
75 #include "intel_pch_display.h"
76 #include "intel_pps.h"
77 #include "intel_psr.h"
79 #include "intel_vdsc.h"
80 #include "intel_vrr.h"
81 #include "intel_crtc_state_dump.h"
83 /* DP DSC throughput values used for slice count calculations KPixels/s */
84 #define DP_DSC_PEAK_PIXEL_RATE 2720000
85 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
86 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
88 /* DP DSC FEC Overhead factor = 1/(0.972261) */
89 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
91 /* Compliance test status bits */
92 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
93 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
94 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
95 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
98 /* Constants for DP DSC configurations */
99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
101 /* With Single pipe configuration, HW is capable of supporting maximum
102 * of 4 slices per line.
104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108 * @intel_dp: DP struct
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
111 * will return true, and false otherwise.
113 * This function is not safe to use prior to encoder type being set.
115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
119 return dig_port->base.type == INTEL_OUTPUT_EDP;
122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
124 /* Is link rate UHBR and thus 128b/132b? */
125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
127 return crtc_state->port_clock >= 1000000;
130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
132 intel_dp->sink_rates[0] = 162000;
133 intel_dp->num_sink_rates = 1;
136 /* update sink rates from dpcd */
137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
139 static const int dp_rates[] = {
140 162000, 270000, 540000, 810000
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
146 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
147 static const int quirk_rates[] = { 162000, 270000, 324000 };
149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
156 * Sink rates for 8b/10b.
158 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
159 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
161 max_rate = min(max_rate, max_lttpr_rate);
163 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
164 if (dp_rates[i] > max_rate)
166 intel_dp->sink_rates[i] = dp_rates[i];
170 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
173 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
176 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
178 drm_dp_dpcd_readb(&intel_dp->aux,
179 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
181 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
182 /* We have a repeater */
183 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
184 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
185 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
186 DP_PHY_REPEATER_128B132B_SUPPORTED) {
187 /* Repeater supports 128b/132b, valid UHBR rates */
188 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
189 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
191 /* Does not support 128b/132b */
196 if (uhbr_rates & DP_UHBR10)
197 intel_dp->sink_rates[i++] = 1000000;
198 if (uhbr_rates & DP_UHBR13_5)
199 intel_dp->sink_rates[i++] = 1350000;
200 if (uhbr_rates & DP_UHBR20)
201 intel_dp->sink_rates[i++] = 2000000;
204 intel_dp->num_sink_rates = i;
207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
209 struct intel_connector *connector = intel_dp->attached_connector;
210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
211 struct intel_encoder *encoder = &intel_dig_port->base;
213 intel_dp_set_dpcd_sink_rates(intel_dp);
215 if (intel_dp->num_sink_rates)
218 drm_err(&dp_to_i915(intel_dp)->drm,
219 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
220 connector->base.base.id, connector->base.name,
221 encoder->base.base.id, encoder->base.name);
223 intel_dp_set_default_sink_rates(intel_dp);
226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
228 intel_dp->max_sink_lane_count = 1;
231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
233 struct intel_connector *connector = intel_dp->attached_connector;
234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
235 struct intel_encoder *encoder = &intel_dig_port->base;
237 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
239 switch (intel_dp->max_sink_lane_count) {
246 drm_err(&dp_to_i915(intel_dp)->drm,
247 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
248 connector->base.base.id, connector->base.name,
249 encoder->base.base.id, encoder->base.name,
250 intel_dp->max_sink_lane_count);
252 intel_dp_set_default_max_sink_lane_count(intel_dp);
255 /* Get length of rates array potentially limited by max_rate. */
256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
260 /* Limit results by potentially reduced max rate */
261 for (i = 0; i < len; i++) {
262 if (rates[len - i - 1] <= max_rate)
269 /* Get length of common rates array potentially limited by max_rate. */
270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
273 return intel_dp_rate_limit_len(intel_dp->common_rates,
274 intel_dp->num_common_rates, max_rate);
277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
279 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
280 index < 0 || index >= intel_dp->num_common_rates))
283 return intel_dp->common_rates[index];
286 /* Theoretical max between source and sink */
287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
289 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
294 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
295 int max_lanes = dig_port->max_lanes;
298 max_lanes = min(max_lanes, vbt_max_lanes);
303 /* Theoretical max between source and sink */
304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307 int source_max = intel_dp_max_source_lane_count(dig_port);
308 int sink_max = intel_dp->max_sink_lane_count;
309 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
310 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
313 sink_max = min(sink_max, lttpr_max);
315 return min3(source_max, sink_max, fia_max);
318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
320 switch (intel_dp->max_link_lane_count) {
324 return intel_dp->max_link_lane_count;
326 MISSING_CASE(intel_dp->max_link_lane_count);
332 * The required data bandwidth for a mode with given pixel clock and bpp. This
333 * is the required net bandwidth independent of the data bandwidth efficiency.
336 intel_dp_link_required(int pixel_clock, int bpp)
338 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
339 return DIV_ROUND_UP(pixel_clock * bpp, 8);
343 * Given a link rate and lanes, get the data bandwidth.
345 * Data bandwidth is the actual payload rate, which depends on the data
346 * bandwidth efficiency and the link rate.
348 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
349 * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
350 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
351 * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
352 * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
353 * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
355 * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
356 * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
357 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
358 * does not match the symbol clock, the port clock (not even if you think in
359 * terms of a byte clock), nor the data bandwidth. It only matches the link bit
360 * rate in units of 10000 bps.
363 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
365 if (max_link_rate >= 1000000) {
367 * UHBR rates always use 128b/132b channel encoding, and have
368 * 97.71% data bandwidth efficiency. Consider max_link_rate the
369 * link bit rate in units of 10000 bps.
371 int max_link_rate_kbps = max_link_rate * 10;
373 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
374 max_link_rate = max_link_rate_kbps / 8;
378 * Lower than UHBR rates always use 8b/10b channel encoding, and have
379 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
380 * out to be a nop by coincidence, and can be skipped:
382 * int max_link_rate_kbps = max_link_rate * 10;
383 * max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
384 * max_link_rate = max_link_rate_kbps / 8;
387 return max_link_rate * max_lanes;
390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
393 struct intel_encoder *encoder = &intel_dig_port->base;
394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
396 return DISPLAY_VER(dev_priv) >= 12 ||
397 (DISPLAY_VER(dev_priv) == 11 &&
398 encoder->port != PORT_A);
401 static int dg2_max_source_rate(struct intel_dp *intel_dp)
403 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
406 static int icl_max_source_rate(struct intel_dp *intel_dp)
408 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
409 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
410 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
412 if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
418 static int ehl_max_source_rate(struct intel_dp *intel_dp)
420 if (intel_dp_is_edp(intel_dp))
426 static int mtl_max_source_rate(struct intel_dp *intel_dp)
428 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
429 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
430 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
432 if (intel_is_c10phy(i915, phy))
433 return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
440 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
443 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
445 if (intel_dp_is_edp(intel_dp)) {
446 struct intel_connector *connector = intel_dp->attached_connector;
447 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
449 if (max_rate && edp_max_rate)
450 max_rate = min(max_rate, edp_max_rate);
451 else if (edp_max_rate)
452 max_rate = edp_max_rate;
459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
461 /* The values must be in increasing order */
462 static const int mtl_rates[] = {
463 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
464 810000, 1000000, 1350000, 2000000,
466 static const int icl_rates[] = {
467 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
470 static const int bxt_rates[] = {
471 162000, 216000, 243000, 270000, 324000, 432000, 540000
473 static const int skl_rates[] = {
474 162000, 216000, 270000, 324000, 432000, 540000
476 static const int hsw_rates[] = {
477 162000, 270000, 540000
479 static const int g4x_rates[] = {
482 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
483 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
484 const int *source_rates;
485 int size, max_rate = 0, vbt_max_rate;
487 /* This should only be done once */
488 drm_WARN_ON(&dev_priv->drm,
489 intel_dp->source_rates || intel_dp->num_source_rates);
491 if (DISPLAY_VER(dev_priv) >= 14) {
492 source_rates = mtl_rates;
493 size = ARRAY_SIZE(mtl_rates);
494 max_rate = mtl_max_source_rate(intel_dp);
495 } else if (DISPLAY_VER(dev_priv) >= 11) {
496 source_rates = icl_rates;
497 size = ARRAY_SIZE(icl_rates);
498 if (IS_DG2(dev_priv))
499 max_rate = dg2_max_source_rate(intel_dp);
500 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
501 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
503 else if (IS_JSL_EHL(dev_priv))
504 max_rate = ehl_max_source_rate(intel_dp);
506 max_rate = icl_max_source_rate(intel_dp);
507 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
508 source_rates = bxt_rates;
509 size = ARRAY_SIZE(bxt_rates);
510 } else if (DISPLAY_VER(dev_priv) == 9) {
511 source_rates = skl_rates;
512 size = ARRAY_SIZE(skl_rates);
513 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
514 IS_BROADWELL(dev_priv)) {
515 source_rates = hsw_rates;
516 size = ARRAY_SIZE(hsw_rates);
518 source_rates = g4x_rates;
519 size = ARRAY_SIZE(g4x_rates);
522 vbt_max_rate = vbt_max_link_rate(intel_dp);
523 if (max_rate && vbt_max_rate)
524 max_rate = min(max_rate, vbt_max_rate);
525 else if (vbt_max_rate)
526 max_rate = vbt_max_rate;
529 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
531 intel_dp->source_rates = source_rates;
532 intel_dp->num_source_rates = size;
535 static int intersect_rates(const int *source_rates, int source_len,
536 const int *sink_rates, int sink_len,
539 int i = 0, j = 0, k = 0;
541 while (i < source_len && j < sink_len) {
542 if (source_rates[i] == sink_rates[j]) {
543 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
545 common_rates[k] = source_rates[i];
549 } else if (source_rates[i] < sink_rates[j]) {
558 /* return index of rate in rates array, or -1 if not found */
559 static int intel_dp_rate_index(const int *rates, int len, int rate)
563 for (i = 0; i < len; i++)
564 if (rate == rates[i])
570 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
572 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
574 drm_WARN_ON(&i915->drm,
575 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
577 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
578 intel_dp->num_source_rates,
579 intel_dp->sink_rates,
580 intel_dp->num_sink_rates,
581 intel_dp->common_rates);
583 /* Paranoia, there should always be something in common. */
584 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
585 intel_dp->common_rates[0] = 162000;
586 intel_dp->num_common_rates = 1;
590 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
594 * FIXME: we need to synchronize the current link parameters with
595 * hardware readout. Currently fast link training doesn't work on
598 if (link_rate == 0 ||
599 link_rate > intel_dp->max_link_rate)
602 if (lane_count == 0 ||
603 lane_count > intel_dp_max_lane_count(intel_dp))
609 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
613 /* FIXME figure out what we actually want here */
614 const struct drm_display_mode *fixed_mode =
615 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
616 int mode_rate, max_rate;
618 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
619 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
620 if (mode_rate > max_rate)
626 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
627 int link_rate, u8 lane_count)
629 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
633 * TODO: Enable fallback on MST links once MST link compute can handle
634 * the fallback params.
636 if (intel_dp->is_mst) {
637 drm_err(&i915->drm, "Link Training Unsuccessful\n");
641 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
642 drm_dbg_kms(&i915->drm,
643 "Retrying Link training for eDP with max parameters\n");
644 intel_dp->use_max_params = true;
648 index = intel_dp_rate_index(intel_dp->common_rates,
649 intel_dp->num_common_rates,
652 if (intel_dp_is_edp(intel_dp) &&
653 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
654 intel_dp_common_rate(intel_dp, index - 1),
656 drm_dbg_kms(&i915->drm,
657 "Retrying Link training for eDP with same parameters\n");
660 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
661 intel_dp->max_link_lane_count = lane_count;
662 } else if (lane_count > 1) {
663 if (intel_dp_is_edp(intel_dp) &&
664 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
665 intel_dp_max_common_rate(intel_dp),
667 drm_dbg_kms(&i915->drm,
668 "Retrying Link training for eDP with same parameters\n");
671 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
672 intel_dp->max_link_lane_count = lane_count >> 1;
674 drm_err(&i915->drm, "Link Training Unsuccessful\n");
681 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
683 return div_u64(mul_u32_u32(mode_clock, 1000000U),
684 DP_DSC_FEC_OVERHEAD_FACTOR);
688 small_joiner_ram_size_bits(struct drm_i915_private *i915)
690 if (DISPLAY_VER(i915) >= 13)
692 else if (DISPLAY_VER(i915) >= 11)
698 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
700 u32 bits_per_pixel = bpp;
703 /* Error out if the max bpp is less than smallest allowed valid bpp */
704 if (bits_per_pixel < valid_dsc_bpp[0]) {
705 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
706 bits_per_pixel, valid_dsc_bpp[0]);
710 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
711 if (DISPLAY_VER(i915) >= 13) {
712 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
715 * According to BSpec, 27 is the max DSC output bpp,
716 * 8 is the min DSC output bpp
718 bits_per_pixel = clamp_t(u32, bits_per_pixel, 8, 27);
720 /* Find the nearest match in the array of known BPPs from VESA */
721 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
722 if (bits_per_pixel < valid_dsc_bpp[i + 1])
725 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
726 bits_per_pixel, valid_dsc_bpp[i]);
728 bits_per_pixel = valid_dsc_bpp[i];
731 return bits_per_pixel;
734 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
735 u32 link_clock, u32 lane_count,
736 u32 mode_clock, u32 mode_hdisplay,
741 u32 bits_per_pixel, max_bpp_small_joiner_ram;
744 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
745 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
746 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
747 * for MST -> TimeSlots has to be calculated, based on mode requirements
749 * Due to FEC overhead, the available bw is reduced to 97.2261%.
750 * To support the given mode:
751 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
752 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
753 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
754 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
755 * (ModeClock / FEC Overhead)
756 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
757 * (ModeClock / FEC Overhead * 8)
759 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
760 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
762 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
763 "total bw %u pixel clock %u\n",
764 bits_per_pixel, timeslots,
765 (link_clock * lane_count * 8),
766 intel_dp_mode_to_fec_clock(mode_clock));
768 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
769 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
773 max_bpp_small_joiner_ram *= 2;
776 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
777 * check, output bpp from small joiner RAM check)
779 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
782 u32 max_bpp_bigjoiner =
783 i915->display.cdclk.max_cdclk_freq * 48 /
784 intel_dp_mode_to_fec_clock(mode_clock);
786 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
789 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
792 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
793 * fractional part is 0
795 return bits_per_pixel << 4;
798 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
799 int mode_clock, int mode_hdisplay,
802 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
803 u8 min_slice_count, i;
806 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
807 min_slice_count = DIV_ROUND_UP(mode_clock,
808 DP_DSC_MAX_ENC_THROUGHPUT_0);
810 min_slice_count = DIV_ROUND_UP(mode_clock,
811 DP_DSC_MAX_ENC_THROUGHPUT_1);
814 * Due to some DSC engine BW limitations, we need to enable second
815 * slice and VDSC engine, whenever we approach close enough to max CDCLK
817 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
818 min_slice_count = max_t(u8, min_slice_count, 2);
820 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
821 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
822 drm_dbg_kms(&i915->drm,
823 "Unsupported slice width %d by DP DSC Sink device\n",
827 /* Also take into account max slice width */
828 min_slice_count = max_t(u8, min_slice_count,
829 DIV_ROUND_UP(mode_hdisplay,
832 /* Find the closest match to the valid slice count values */
833 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
834 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
836 if (test_slice_count >
837 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
840 /* big joiner needs small joiner to be enabled */
841 if (bigjoiner && test_slice_count < 4)
844 if (min_slice_count <= test_slice_count)
845 return test_slice_count;
848 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
853 static bool source_can_output(struct intel_dp *intel_dp,
854 enum intel_output_format format)
856 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
859 case INTEL_OUTPUT_FORMAT_RGB:
862 case INTEL_OUTPUT_FORMAT_YCBCR444:
864 * No YCbCr output support on gmch platforms.
865 * Also, ILK doesn't seem capable of DP YCbCr output.
866 * The displayed image is severly corrupted. SNB+ is fine.
868 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
870 case INTEL_OUTPUT_FORMAT_YCBCR420:
871 /* Platform < Gen 11 cannot output YCbCr420 format */
872 return DISPLAY_VER(i915) >= 11;
875 MISSING_CASE(format);
881 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
882 enum intel_output_format sink_format)
884 if (!drm_dp_is_branch(intel_dp->dpcd))
887 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
888 return intel_dp->dfp.rgb_to_ycbcr;
890 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
891 return intel_dp->dfp.rgb_to_ycbcr &&
892 intel_dp->dfp.ycbcr_444_to_420;
898 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
899 enum intel_output_format sink_format)
901 if (!drm_dp_is_branch(intel_dp->dpcd))
904 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
905 return intel_dp->dfp.ycbcr_444_to_420;
910 static enum intel_output_format
911 intel_dp_output_format(struct intel_connector *connector,
912 enum intel_output_format sink_format)
914 struct intel_dp *intel_dp = intel_attached_dp(connector);
915 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
916 enum intel_output_format output_format;
918 if (intel_dp->force_dsc_output_format)
919 return intel_dp->force_dsc_output_format;
921 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
922 dfp_can_convert_from_rgb(intel_dp, sink_format))
923 output_format = INTEL_OUTPUT_FORMAT_RGB;
925 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
926 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
927 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
930 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
932 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
934 return output_format;
937 int intel_dp_min_bpp(enum intel_output_format output_format)
939 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
945 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
948 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
949 * format of the number of bytes per pixel will be half the number
950 * of bytes of RGB pixel.
952 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
958 static enum intel_output_format
959 intel_dp_sink_format(struct intel_connector *connector,
960 const struct drm_display_mode *mode)
962 const struct drm_display_info *info = &connector->base.display_info;
964 if (drm_mode_is_420_only(info, mode))
965 return INTEL_OUTPUT_FORMAT_YCBCR420;
967 return INTEL_OUTPUT_FORMAT_RGB;
971 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
972 const struct drm_display_mode *mode)
974 enum intel_output_format output_format, sink_format;
976 sink_format = intel_dp_sink_format(connector, mode);
978 output_format = intel_dp_output_format(connector, sink_format);
980 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
983 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
987 * Older platforms don't like hdisplay==4096 with DP.
989 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
990 * and frame counter increment), but we don't get vblank interrupts,
991 * and the pipe underruns immediately. The link also doesn't seem
992 * to get trained properly.
994 * On CHV the vblank interrupts don't seem to disappear but
995 * otherwise the symptoms are similar.
997 * TODO: confirm the behaviour on HSW+
999 return hdisplay == 4096 && !HAS_DDI(dev_priv);
1002 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1004 struct intel_connector *connector = intel_dp->attached_connector;
1005 const struct drm_display_info *info = &connector->base.display_info;
1006 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1008 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1009 if (max_tmds_clock && info->max_tmds_clock)
1010 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1012 return max_tmds_clock;
1015 static enum drm_mode_status
1016 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1018 enum intel_output_format sink_format,
1019 bool respect_downstream_limits)
1021 int tmds_clock, min_tmds_clock, max_tmds_clock;
1023 if (!respect_downstream_limits)
1026 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1028 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1029 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1031 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1032 return MODE_CLOCK_LOW;
1034 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1035 return MODE_CLOCK_HIGH;
1040 static enum drm_mode_status
1041 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1042 const struct drm_display_mode *mode,
1045 struct intel_dp *intel_dp = intel_attached_dp(connector);
1046 const struct drm_display_info *info = &connector->base.display_info;
1047 enum drm_mode_status status;
1048 enum intel_output_format sink_format;
1050 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1051 if (intel_dp->dfp.pcon_max_frl_bw) {
1054 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1056 target_bw = bpp * target_clock;
1058 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1060 /* converting bw from Gbps to Kbps*/
1061 max_frl_bw = max_frl_bw * 1000000;
1063 if (target_bw > max_frl_bw)
1064 return MODE_CLOCK_HIGH;
1069 if (intel_dp->dfp.max_dotclock &&
1070 target_clock > intel_dp->dfp.max_dotclock)
1071 return MODE_CLOCK_HIGH;
1073 sink_format = intel_dp_sink_format(connector, mode);
1075 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1076 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1077 8, sink_format, true);
1079 if (status != MODE_OK) {
1080 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1081 !connector->base.ycbcr_420_allowed ||
1082 !drm_mode_is_420_also(info, mode))
1084 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1085 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1086 8, sink_format, true);
1087 if (status != MODE_OK)
1094 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1095 int hdisplay, int clock)
1097 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1099 if (!intel_dp_can_bigjoiner(intel_dp))
1102 return clock > i915->max_dotclk_freq || hdisplay > 5120;
1105 static enum drm_mode_status
1106 intel_dp_mode_valid(struct drm_connector *_connector,
1107 struct drm_display_mode *mode)
1109 struct intel_connector *connector = to_intel_connector(_connector);
1110 struct intel_dp *intel_dp = intel_attached_dp(connector);
1111 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1112 const struct drm_display_mode *fixed_mode;
1113 int target_clock = mode->clock;
1114 int max_rate, mode_rate, max_lanes, max_link_clock;
1115 int max_dotclk = dev_priv->max_dotclk_freq;
1116 u16 dsc_max_output_bpp = 0;
1117 u8 dsc_slice_count = 0;
1118 enum drm_mode_status status;
1119 bool dsc = false, bigjoiner = false;
1121 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1122 return MODE_H_ILLEGAL;
1124 fixed_mode = intel_panel_fixed_mode(connector, mode);
1125 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1126 status = intel_panel_mode_valid(connector, mode);
1127 if (status != MODE_OK)
1130 target_clock = fixed_mode->clock;
1133 if (mode->clock < 10000)
1134 return MODE_CLOCK_LOW;
1136 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1140 if (target_clock > max_dotclk)
1141 return MODE_CLOCK_HIGH;
1143 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1144 return MODE_H_ILLEGAL;
1146 max_link_clock = intel_dp_max_link_rate(intel_dp);
1147 max_lanes = intel_dp_max_lane_count(intel_dp);
1149 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1150 mode_rate = intel_dp_link_required(target_clock,
1151 intel_dp_mode_min_output_bpp(connector, mode));
1153 if (HAS_DSC(dev_priv) &&
1154 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1156 * TBD pass the connector BPC,
1157 * for now U8_MAX so that max BPC on that platform would be picked
1159 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1162 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1163 * integer value since we support only integer values of bpp.
1165 if (intel_dp_is_edp(intel_dp)) {
1166 dsc_max_output_bpp =
1167 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1169 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1171 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1172 dsc_max_output_bpp =
1173 intel_dp_dsc_get_output_bpp(dev_priv,
1181 intel_dp_dsc_get_slice_count(intel_dp,
1187 dsc = dsc_max_output_bpp && dsc_slice_count;
1191 * Big joiner configuration needs DSC for TGL which is not true for
1192 * XE_LPD where uncompressed joiner is supported.
1194 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1195 return MODE_CLOCK_HIGH;
1197 if (mode_rate > max_rate && !dsc)
1198 return MODE_CLOCK_HIGH;
1200 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1201 if (status != MODE_OK)
1204 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1207 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1209 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1212 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1214 return DISPLAY_VER(i915) >= 10;
1217 static void snprintf_int_array(char *str, size_t len,
1218 const int *array, int nelem)
1224 for (i = 0; i < nelem; i++) {
1225 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1233 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1235 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1236 char str[128]; /* FIXME: too big for stack? */
1238 if (!drm_debug_enabled(DRM_UT_KMS))
1241 snprintf_int_array(str, sizeof(str),
1242 intel_dp->source_rates, intel_dp->num_source_rates);
1243 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1245 snprintf_int_array(str, sizeof(str),
1246 intel_dp->sink_rates, intel_dp->num_sink_rates);
1247 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1249 snprintf_int_array(str, sizeof(str),
1250 intel_dp->common_rates, intel_dp->num_common_rates);
1251 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1255 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1259 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1261 return intel_dp_common_rate(intel_dp, len - 1);
1264 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1266 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1267 int i = intel_dp_rate_index(intel_dp->sink_rates,
1268 intel_dp->num_sink_rates, rate);
1270 if (drm_WARN_ON(&i915->drm, i < 0))
1276 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1277 u8 *link_bw, u8 *rate_select)
1279 /* eDP 1.4 rate select method. */
1280 if (intel_dp->use_rate_select) {
1283 intel_dp_rate_select(intel_dp, port_clock);
1285 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1290 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1292 struct intel_connector *connector = intel_dp->attached_connector;
1294 return connector->base.display_info.is_hdmi;
1297 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1298 const struct intel_crtc_state *pipe_config)
1300 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1302 /* On TGL, FEC is supported on all Pipes */
1303 if (DISPLAY_VER(dev_priv) >= 12)
1306 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1312 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1313 const struct intel_crtc_state *pipe_config)
1315 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1316 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1319 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1320 const struct intel_crtc_state *crtc_state)
1322 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1325 return intel_dsc_source_support(crtc_state) &&
1326 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1329 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1330 const struct intel_crtc_state *crtc_state,
1331 int bpc, bool respect_downstream_limits)
1333 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1336 * Current bpc could already be below 8bpc due to
1337 * FDI bandwidth constraints or other limits.
1338 * HDMI minimum is 8bpc however.
1343 * We will never exceed downstream TMDS clock limits while
1344 * attempting deep color. If the user insists on forcing an
1345 * out of spec mode they will have to be satisfied with 8bpc.
1347 if (!respect_downstream_limits)
1350 for (; bpc >= 8; bpc -= 2) {
1351 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1352 intel_dp_has_hdmi_sink(intel_dp)) &&
1353 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1354 respect_downstream_limits) == MODE_OK)
1361 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1362 const struct intel_crtc_state *crtc_state,
1363 bool respect_downstream_limits)
1365 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1366 struct intel_connector *intel_connector = intel_dp->attached_connector;
1369 bpc = crtc_state->pipe_bpp / 3;
1371 if (intel_dp->dfp.max_bpc)
1372 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1374 if (intel_dp->dfp.min_tmds_clock) {
1377 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1378 respect_downstream_limits);
1379 if (max_hdmi_bpc < 0)
1382 bpc = min(bpc, max_hdmi_bpc);
1386 if (intel_dp_is_edp(intel_dp)) {
1387 /* Get bpp from vbt only for panels that dont have bpp in edid */
1388 if (intel_connector->base.display_info.bpc == 0 &&
1389 intel_connector->panel.vbt.edp.bpp &&
1390 intel_connector->panel.vbt.edp.bpp < bpp) {
1391 drm_dbg_kms(&dev_priv->drm,
1392 "clamping bpp for eDP panel to BIOS-provided %i\n",
1393 intel_connector->panel.vbt.edp.bpp);
1394 bpp = intel_connector->panel.vbt.edp.bpp;
1401 /* Adjust link config limits based on compliance test requests. */
1403 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1404 struct intel_crtc_state *pipe_config,
1405 struct link_config_limits *limits)
1407 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1409 /* For DP Compliance we override the computed bpp for the pipe */
1410 if (intel_dp->compliance.test_data.bpc != 0) {
1411 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1413 limits->min_bpp = limits->max_bpp = bpp;
1414 pipe_config->dither_force_disable = bpp == 6 * 3;
1416 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1419 /* Use values requested by Compliance Test Request */
1420 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1423 /* Validate the compliance test data since max values
1424 * might have changed due to link train fallback.
1426 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1427 intel_dp->compliance.test_lane_count)) {
1428 index = intel_dp_rate_index(intel_dp->common_rates,
1429 intel_dp->num_common_rates,
1430 intel_dp->compliance.test_link_rate);
1432 limits->min_rate = limits->max_rate =
1433 intel_dp->compliance.test_link_rate;
1434 limits->min_lane_count = limits->max_lane_count =
1435 intel_dp->compliance.test_lane_count;
1440 static bool has_seamless_m_n(struct intel_connector *connector)
1442 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1445 * Seamless M/N reprogramming only implemented
1446 * for BDW+ double buffered M/N registers so far.
1448 return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1449 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1452 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1453 const struct drm_connector_state *conn_state)
1455 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1456 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1458 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1459 if (has_seamless_m_n(connector))
1460 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1462 return adjusted_mode->crtc_clock;
1465 /* Optimize link config in order: max bpp, min clock, min lanes */
1467 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1468 struct intel_crtc_state *pipe_config,
1469 const struct drm_connector_state *conn_state,
1470 const struct link_config_limits *limits)
1472 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1473 int mode_rate, link_rate, link_avail;
1475 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1476 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1478 mode_rate = intel_dp_link_required(clock, output_bpp);
1480 for (i = 0; i < intel_dp->num_common_rates; i++) {
1481 link_rate = intel_dp_common_rate(intel_dp, i);
1482 if (link_rate < limits->min_rate ||
1483 link_rate > limits->max_rate)
1486 for (lane_count = limits->min_lane_count;
1487 lane_count <= limits->max_lane_count;
1489 link_avail = intel_dp_max_data_rate(link_rate,
1492 if (mode_rate <= link_avail) {
1493 pipe_config->lane_count = lane_count;
1494 pipe_config->pipe_bpp = bpp;
1495 pipe_config->port_clock = link_rate;
1506 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1508 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1510 u8 dsc_bpc[3] = {0};
1513 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1514 if (DISPLAY_VER(i915) >= 12)
1515 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1517 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1519 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1521 for (i = 0; i < num_bpc; i++) {
1522 if (dsc_max_bpc >= dsc_bpc[i])
1523 return dsc_bpc[i] * 3;
1529 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1531 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1533 return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1536 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1538 return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1542 static int intel_dp_get_slice_height(int vactive)
1547 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1548 * lines is an optimal slice height, but any size can be used as long as
1549 * vertical active integer multiple and maximum vertical slice count
1550 * requirements are met.
1552 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1553 if (vactive % slice_height == 0)
1554 return slice_height;
1557 * Highly unlikely we reach here as most of the resolutions will end up
1558 * finding appropriate slice_height in above loop but returning
1559 * slice_height as 2 here as it should work with all resolutions.
1564 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1565 struct intel_crtc_state *crtc_state)
1567 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1568 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1569 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1574 * RC_MODEL_SIZE is currently a constant across all configurations.
1576 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1577 * DP_DSC_RC_BUF_SIZE for this.
1579 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1580 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1582 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1584 ret = intel_dsc_compute_params(crtc_state);
1588 vdsc_cfg->dsc_version_major =
1589 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1590 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1591 vdsc_cfg->dsc_version_minor =
1592 min(intel_dp_source_dsc_version_minor(intel_dp),
1593 intel_dp_sink_dsc_version_minor(intel_dp));
1594 if (vdsc_cfg->convert_rgb)
1595 vdsc_cfg->convert_rgb =
1596 intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1599 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1600 if (!line_buf_depth) {
1601 drm_dbg_kms(&i915->drm,
1602 "DSC Sink Line Buffer Depth invalid\n");
1606 if (vdsc_cfg->dsc_version_minor == 2)
1607 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1608 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1610 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1611 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1613 vdsc_cfg->block_pred_enable =
1614 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1615 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1617 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1620 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
1621 enum intel_output_format output_format)
1625 switch (output_format) {
1626 case INTEL_OUTPUT_FORMAT_RGB:
1627 sink_dsc_format = DP_DSC_RGB;
1629 case INTEL_OUTPUT_FORMAT_YCBCR444:
1630 sink_dsc_format = DP_DSC_YCbCr444;
1632 case INTEL_OUTPUT_FORMAT_YCBCR420:
1633 if (min(intel_dp_source_dsc_version_minor(intel_dp),
1634 intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
1636 sink_dsc_format = DP_DSC_YCbCr420_Native;
1642 return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
1645 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1646 struct intel_crtc_state *pipe_config,
1647 struct drm_connector_state *conn_state,
1648 struct link_config_limits *limits,
1650 bool compute_pipe_bpp)
1652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1653 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1654 const struct drm_display_mode *adjusted_mode =
1655 &pipe_config->hw.adjusted_mode;
1659 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1660 intel_dp_supports_fec(intel_dp, pipe_config);
1662 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1665 if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
1668 if (compute_pipe_bpp)
1669 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1671 pipe_bpp = pipe_config->pipe_bpp;
1673 if (intel_dp->force_dsc_bpc) {
1674 pipe_bpp = intel_dp->force_dsc_bpc * 3;
1675 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1678 /* Min Input BPC for ICL+ is 8 */
1679 if (pipe_bpp < 8 * 3) {
1680 drm_dbg_kms(&dev_priv->drm,
1681 "No DSC support for less than 8bpc\n");
1686 * For now enable DSC for max bpp, max link rate, max lane count.
1687 * Optimize this later for the minimum possible link rate/lane count
1688 * with DSC enabled for the requested mode.
1690 pipe_config->pipe_bpp = pipe_bpp;
1691 pipe_config->port_clock = limits->max_rate;
1692 pipe_config->lane_count = limits->max_lane_count;
1694 if (intel_dp_is_edp(intel_dp)) {
1695 pipe_config->dsc.compressed_bpp =
1696 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1697 pipe_config->pipe_bpp);
1698 pipe_config->dsc.slice_count =
1699 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1701 if (!pipe_config->dsc.slice_count) {
1702 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
1703 pipe_config->dsc.slice_count);
1707 u16 dsc_max_output_bpp = 0;
1708 u8 dsc_dp_slice_count;
1710 if (compute_pipe_bpp) {
1711 dsc_max_output_bpp =
1712 intel_dp_dsc_get_output_bpp(dev_priv,
1713 pipe_config->port_clock,
1714 pipe_config->lane_count,
1715 adjusted_mode->crtc_clock,
1716 adjusted_mode->crtc_hdisplay,
1717 pipe_config->bigjoiner_pipes,
1721 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1722 * supported PPS value can be 63.9375 and with the further
1723 * mention that bpp should be programmed double the target bpp
1724 * restricting our target bpp to be 31.9375 at max
1726 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1727 dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1729 if (!dsc_max_output_bpp) {
1730 drm_dbg_kms(&dev_priv->drm,
1731 "Compressed BPP not supported\n");
1735 dsc_dp_slice_count =
1736 intel_dp_dsc_get_slice_count(intel_dp,
1737 adjusted_mode->crtc_clock,
1738 adjusted_mode->crtc_hdisplay,
1739 pipe_config->bigjoiner_pipes);
1740 if (!dsc_dp_slice_count) {
1741 drm_dbg_kms(&dev_priv->drm,
1742 "Compressed Slice Count not supported\n");
1747 * compute pipe bpp is set to false for DP MST DSC case
1748 * and compressed_bpp is calculated same time once
1749 * vpci timeslots are allocated, because overall bpp
1750 * calculation procedure is bit different for MST case.
1752 if (compute_pipe_bpp) {
1753 pipe_config->dsc.compressed_bpp = min_t(u16,
1754 dsc_max_output_bpp >> 4,
1755 pipe_config->pipe_bpp);
1757 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1758 drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1759 pipe_config->dsc.compressed_bpp,
1760 pipe_config->dsc.slice_count);
1763 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1764 * is greater than the maximum Cdclock and if slice count is even
1765 * then we need to use 2 VDSC instances.
1767 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
1768 pipe_config->dsc.dsc_split = true;
1770 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1772 drm_dbg_kms(&dev_priv->drm,
1773 "Cannot compute valid DSC parameters for Input Bpp = %d "
1774 "Compressed BPP = %d\n",
1775 pipe_config->pipe_bpp,
1776 pipe_config->dsc.compressed_bpp);
1780 pipe_config->dsc.compression_enable = true;
1781 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1782 "Compressed Bpp = %d Slice Count = %d\n",
1783 pipe_config->pipe_bpp,
1784 pipe_config->dsc.compressed_bpp,
1785 pipe_config->dsc.slice_count);
1791 intel_dp_compute_link_config(struct intel_encoder *encoder,
1792 struct intel_crtc_state *pipe_config,
1793 struct drm_connector_state *conn_state,
1794 bool respect_downstream_limits)
1796 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1797 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1798 const struct drm_display_mode *adjusted_mode =
1799 &pipe_config->hw.adjusted_mode;
1800 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1801 struct link_config_limits limits;
1802 bool joiner_needs_dsc = false;
1805 limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1806 limits.max_rate = intel_dp_max_link_rate(intel_dp);
1808 limits.min_lane_count = 1;
1809 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1811 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1812 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1814 if (intel_dp->use_max_params) {
1816 * Use the maximum clock and number of lanes the eDP panel
1817 * advertizes being capable of in case the initial fast
1818 * optimal params failed us. The panels are generally
1819 * designed to support only a single clock and lane
1820 * configuration, and typically on older panels these
1821 * values correspond to the native resolution of the panel.
1823 limits.min_lane_count = limits.max_lane_count;
1824 limits.min_rate = limits.max_rate;
1827 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1829 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1830 "max rate %d max bpp %d pixel clock %iKHz\n",
1831 limits.max_lane_count, limits.max_rate,
1832 limits.max_bpp, adjusted_mode->crtc_clock);
1834 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1835 adjusted_mode->crtc_clock))
1836 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1839 * Pipe joiner needs compression up to display 12 due to bandwidth
1840 * limitation. DG2 onwards pipe joiner can be enabled without
1843 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1846 * Optimize for slow and wide for everything, because there are some
1847 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1849 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1851 if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1852 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1853 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1854 str_yes_no(intel_dp->force_dsc_en));
1855 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1856 conn_state, &limits, 64, true);
1861 if (pipe_config->dsc.compression_enable) {
1862 drm_dbg_kms(&i915->drm,
1863 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1864 pipe_config->lane_count, pipe_config->port_clock,
1865 pipe_config->pipe_bpp,
1866 pipe_config->dsc.compressed_bpp);
1868 drm_dbg_kms(&i915->drm,
1869 "DP link rate required %i available %i\n",
1870 intel_dp_link_required(adjusted_mode->crtc_clock,
1871 pipe_config->dsc.compressed_bpp),
1872 intel_dp_max_data_rate(pipe_config->port_clock,
1873 pipe_config->lane_count));
1875 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1876 pipe_config->lane_count, pipe_config->port_clock,
1877 pipe_config->pipe_bpp);
1879 drm_dbg_kms(&i915->drm,
1880 "DP link rate required %i available %i\n",
1881 intel_dp_link_required(adjusted_mode->crtc_clock,
1882 pipe_config->pipe_bpp),
1883 intel_dp_max_data_rate(pipe_config->port_clock,
1884 pipe_config->lane_count));
1889 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1890 const struct drm_connector_state *conn_state)
1892 const struct intel_digital_connector_state *intel_conn_state =
1893 to_intel_digital_connector_state(conn_state);
1894 const struct drm_display_mode *adjusted_mode =
1895 &crtc_state->hw.adjusted_mode;
1898 * Our YCbCr output is always limited range.
1899 * crtc_state->limited_color_range only applies to RGB,
1900 * and it must never be set for YCbCr or we risk setting
1901 * some conflicting bits in TRANSCONF which will mess up
1902 * the colors on the monitor.
1904 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1907 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1910 * CEA-861-E - 5.1 Default Encoding Parameters
1911 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1913 return crtc_state->pipe_bpp != 18 &&
1914 drm_default_rgb_quant_range(adjusted_mode) ==
1915 HDMI_QUANTIZATION_RANGE_LIMITED;
1917 return intel_conn_state->broadcast_rgb ==
1918 INTEL_BROADCAST_RGB_LIMITED;
1922 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1925 if (IS_G4X(dev_priv))
1927 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1933 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1934 const struct drm_connector_state *conn_state,
1935 struct drm_dp_vsc_sdp *vsc)
1937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1938 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1941 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1942 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1943 * Colorimetry Format indication.
1945 vsc->revision = 0x5;
1948 /* DP 1.4a spec, Table 2-120 */
1949 switch (crtc_state->output_format) {
1950 case INTEL_OUTPUT_FORMAT_YCBCR444:
1951 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1953 case INTEL_OUTPUT_FORMAT_YCBCR420:
1954 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1956 case INTEL_OUTPUT_FORMAT_RGB:
1958 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1961 switch (conn_state->colorspace) {
1962 case DRM_MODE_COLORIMETRY_BT709_YCC:
1963 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1965 case DRM_MODE_COLORIMETRY_XVYCC_601:
1966 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1968 case DRM_MODE_COLORIMETRY_XVYCC_709:
1969 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1971 case DRM_MODE_COLORIMETRY_SYCC_601:
1972 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1974 case DRM_MODE_COLORIMETRY_OPYCC_601:
1975 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1977 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1978 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1980 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1981 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1983 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1984 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1986 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1987 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1988 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1992 * RGB->YCBCR color conversion uses the BT.709
1995 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1996 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1998 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2002 vsc->bpc = crtc_state->pipe_bpp / 3;
2004 /* only RGB pixelformat supports 6 bpc */
2005 drm_WARN_ON(&dev_priv->drm,
2006 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2008 /* all YCbCr are always limited range */
2009 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2010 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2013 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2014 struct intel_crtc_state *crtc_state,
2015 const struct drm_connector_state *conn_state)
2017 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2019 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2020 if (crtc_state->has_psr)
2023 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2026 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2027 vsc->sdp_type = DP_SDP_VSC;
2028 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2029 &crtc_state->infoframes.vsc);
2032 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2033 const struct intel_crtc_state *crtc_state,
2034 const struct drm_connector_state *conn_state,
2035 struct drm_dp_vsc_sdp *vsc)
2037 vsc->sdp_type = DP_SDP_VSC;
2039 if (crtc_state->has_psr2) {
2040 if (intel_dp->psr.colorimetry_support &&
2041 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2042 /* [PSR2, +Colorimetry] */
2043 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2047 * [PSR2, -Colorimetry]
2048 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2049 * 3D stereo + PSR/PSR2 + Y-coordinate.
2051 vsc->revision = 0x4;
2057 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2058 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2061 vsc->revision = 0x2;
2067 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2068 struct intel_crtc_state *crtc_state,
2069 const struct drm_connector_state *conn_state)
2072 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2073 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2075 if (!conn_state->hdr_output_metadata)
2078 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2081 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2085 crtc_state->infoframes.enable |=
2086 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2089 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2090 enum transcoder cpu_transcoder)
2092 if (HAS_DOUBLE_BUFFERED_M_N(i915))
2095 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2098 static bool can_enable_drrs(struct intel_connector *connector,
2099 const struct intel_crtc_state *pipe_config,
2100 const struct drm_display_mode *downclock_mode)
2102 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2104 if (pipe_config->vrr.enable)
2108 * DRRS and PSR can't be enable together, so giving preference to PSR
2109 * as it allows more power-savings by complete shutting down display,
2110 * so to guarantee this, intel_drrs_compute_config() must be called
2111 * after intel_psr_compute_config().
2113 if (pipe_config->has_psr)
2116 /* FIXME missing FDI M2/N2 etc. */
2117 if (pipe_config->has_pch_encoder)
2120 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2123 return downclock_mode &&
2124 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2128 intel_dp_drrs_compute_config(struct intel_connector *connector,
2129 struct intel_crtc_state *pipe_config,
2132 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2133 const struct drm_display_mode *downclock_mode =
2134 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2137 if (has_seamless_m_n(connector))
2138 pipe_config->seamless_m_n = true;
2140 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2141 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2142 intel_zero_m_n(&pipe_config->dp_m2_n2);
2146 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2147 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2149 pipe_config->has_drrs = true;
2151 pixel_clock = downclock_mode->clock;
2152 if (pipe_config->splitter.enable)
2153 pixel_clock /= pipe_config->splitter.link_count;
2155 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2156 pipe_config->port_clock, &pipe_config->dp_m2_n2,
2157 pipe_config->fec_enable);
2159 /* FIXME: abstract this better */
2160 if (pipe_config->splitter.enable)
2161 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2164 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2165 const struct drm_connector_state *conn_state)
2167 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2169 struct intel_connector *connector = intel_dp->attached_connector;
2170 const struct intel_digital_connector_state *intel_conn_state =
2171 to_intel_digital_connector_state(conn_state);
2173 if (!intel_dp_port_has_audio(i915, encoder->port))
2176 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2177 return connector->base.display_info.has_audio;
2179 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2183 intel_dp_compute_output_format(struct intel_encoder *encoder,
2184 struct intel_crtc_state *crtc_state,
2185 struct drm_connector_state *conn_state,
2186 bool respect_downstream_limits)
2188 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2189 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2190 struct intel_connector *connector = intel_dp->attached_connector;
2191 const struct drm_display_info *info = &connector->base.display_info;
2192 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2193 bool ycbcr_420_only;
2196 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2198 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2199 drm_dbg_kms(&i915->drm,
2200 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2201 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2203 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2206 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2208 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2209 respect_downstream_limits);
2211 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2212 !connector->base.ycbcr_420_allowed ||
2213 !drm_mode_is_420_also(info, adjusted_mode))
2216 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2217 crtc_state->output_format = intel_dp_output_format(connector,
2218 crtc_state->sink_format);
2219 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2220 respect_downstream_limits);
2227 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2228 struct intel_crtc_state *pipe_config,
2229 struct drm_connector_state *conn_state)
2231 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2232 struct drm_connector *connector = conn_state->connector;
2234 pipe_config->sdp_split_enable =
2235 intel_dp_has_audio(encoder, conn_state) &&
2236 intel_dp_is_uhbr(pipe_config);
2238 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2239 connector->base.id, connector->name,
2240 str_yes_no(pipe_config->sdp_split_enable));
2244 intel_dp_compute_config(struct intel_encoder *encoder,
2245 struct intel_crtc_state *pipe_config,
2246 struct drm_connector_state *conn_state)
2248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2249 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2250 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2251 const struct drm_display_mode *fixed_mode;
2252 struct intel_connector *connector = intel_dp->attached_connector;
2253 int ret = 0, output_bpp;
2255 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2256 pipe_config->has_pch_encoder = true;
2258 pipe_config->has_audio =
2259 intel_dp_has_audio(encoder, conn_state) &&
2260 intel_audio_compute_config(encoder, pipe_config, conn_state);
2262 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2263 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2264 ret = intel_panel_compute_config(connector, adjusted_mode);
2269 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2272 if (!connector->base.interlace_allowed &&
2273 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2276 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2279 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2283 * Try to respect downstream TMDS clock limits first, if
2284 * that fails assume the user might know something we don't.
2286 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2288 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2292 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2293 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2294 ret = intel_panel_fitting(pipe_config, conn_state);
2299 pipe_config->limited_color_range =
2300 intel_dp_limited_color_range(pipe_config, conn_state);
2302 if (pipe_config->dsc.compression_enable)
2303 output_bpp = pipe_config->dsc.compressed_bpp;
2305 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2306 pipe_config->pipe_bpp);
2308 if (intel_dp->mso_link_count) {
2309 int n = intel_dp->mso_link_count;
2310 int overlap = intel_dp->mso_pixel_overlap;
2312 pipe_config->splitter.enable = true;
2313 pipe_config->splitter.link_count = n;
2314 pipe_config->splitter.pixel_overlap = overlap;
2316 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2319 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2320 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2321 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2322 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2323 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2324 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2325 adjusted_mode->crtc_clock /= n;
2328 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2330 intel_link_compute_m_n(output_bpp,
2331 pipe_config->lane_count,
2332 adjusted_mode->crtc_clock,
2333 pipe_config->port_clock,
2334 &pipe_config->dp_m_n,
2335 pipe_config->fec_enable);
2337 /* FIXME: abstract this better */
2338 if (pipe_config->splitter.enable)
2339 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2341 if (!HAS_DDI(dev_priv))
2342 g4x_dp_set_clock(encoder, pipe_config);
2344 intel_vrr_compute_config(pipe_config, conn_state);
2345 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2346 intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2347 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2348 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2353 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2354 int link_rate, int lane_count)
2356 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2357 intel_dp->link_trained = false;
2358 intel_dp->link_rate = link_rate;
2359 intel_dp->lane_count = lane_count;
2362 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2364 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2365 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2368 /* Enable backlight PWM and backlight PP control. */
2369 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2370 const struct drm_connector_state *conn_state)
2372 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2373 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2375 if (!intel_dp_is_edp(intel_dp))
2378 drm_dbg_kms(&i915->drm, "\n");
2380 intel_backlight_enable(crtc_state, conn_state);
2381 intel_pps_backlight_on(intel_dp);
2384 /* Disable backlight PP control and backlight PWM. */
2385 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2387 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2388 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2390 if (!intel_dp_is_edp(intel_dp))
2393 drm_dbg_kms(&i915->drm, "\n");
2395 intel_pps_backlight_off(intel_dp);
2396 intel_backlight_disable(old_conn_state);
2399 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2402 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2403 * be capable of signalling downstream hpd with a long pulse.
2404 * Whether or not that means D3 is safe to use is not clear,
2405 * but let's assume so until proven otherwise.
2407 * FIXME should really check all downstream ports...
2409 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2410 drm_dp_is_branch(intel_dp->dpcd) &&
2411 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2414 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2415 const struct intel_crtc_state *crtc_state,
2418 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2421 if (!crtc_state->dsc.compression_enable)
2424 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2425 enable ? DP_DECOMPRESSION_EN : 0);
2427 drm_dbg_kms(&i915->drm,
2428 "Failed to %s sink decompression state\n",
2429 str_enable_disable(enable));
2433 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2435 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2436 u8 oui[] = { 0x00, 0xaa, 0x01 };
2440 * During driver init, we want to be careful and avoid changing the source OUI if it's
2441 * already set to what we want, so as to avoid clearing any state by accident
2444 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2445 drm_err(&i915->drm, "Failed to read source OUI\n");
2447 if (memcmp(oui, buf, sizeof(oui)) == 0)
2451 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2452 drm_err(&i915->drm, "Failed to write source OUI\n");
2454 intel_dp->last_oui_write = jiffies;
2457 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2459 struct intel_connector *connector = intel_dp->attached_connector;
2460 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2462 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2463 connector->base.base.id, connector->base.name,
2464 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2466 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2467 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2470 /* If the device supports it, try to set the power state appropriately */
2471 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2473 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2474 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2477 /* Should have a valid DPCD by this point */
2478 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2481 if (mode != DP_SET_POWER_D0) {
2482 if (downstream_hpd_needs_d0(intel_dp))
2485 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2487 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2489 lspcon_resume(dp_to_dig_port(intel_dp));
2491 /* Write the source OUI as early as possible */
2492 if (intel_dp_is_edp(intel_dp))
2493 intel_edp_init_source_oui(intel_dp, false);
2496 * When turning on, we need to retry for 1ms to give the sink
2499 for (i = 0; i < 3; i++) {
2500 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2506 if (ret == 1 && lspcon->active)
2507 lspcon_wait_pcon_mode(lspcon);
2511 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2512 encoder->base.base.id, encoder->base.name,
2513 mode == DP_SET_POWER_D0 ? "D0" : "D3");
2517 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2520 * intel_dp_sync_state - sync the encoder state during init/resume
2521 * @encoder: intel encoder to sync
2522 * @crtc_state: state for the CRTC connected to the encoder
2524 * Sync any state stored in the encoder wrt. HW state during driver init
2525 * and system resume.
2527 void intel_dp_sync_state(struct intel_encoder *encoder,
2528 const struct intel_crtc_state *crtc_state)
2530 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2536 * Don't clobber DPCD if it's been already read out during output
2537 * setup (eDP) or detect.
2539 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2540 intel_dp_get_dpcd(intel_dp);
2542 intel_dp_reset_max_link_params(intel_dp);
2545 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2546 struct intel_crtc_state *crtc_state)
2548 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2550 bool fastset = true;
2553 * If BIOS has set an unsupported or non-standard link rate for some
2554 * reason force an encoder recompute and full modeset.
2556 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2557 crtc_state->port_clock) < 0) {
2558 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2559 encoder->base.base.id, encoder->base.name);
2560 crtc_state->uapi.connectors_changed = true;
2565 * FIXME hack to force full modeset when DSC is being used.
2567 * As long as we do not have full state readout and config comparison
2568 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2569 * Remove once we have readout for DSC.
2571 if (crtc_state->dsc.compression_enable) {
2572 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2573 encoder->base.base.id, encoder->base.name);
2574 crtc_state->uapi.mode_changed = true;
2578 if (CAN_PSR(intel_dp)) {
2579 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2580 encoder->base.base.id, encoder->base.name);
2581 crtc_state->uapi.mode_changed = true;
2588 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2590 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2592 /* Clear the cached register set to avoid using stale values */
2594 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2596 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2597 intel_dp->pcon_dsc_dpcd,
2598 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2599 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2600 DP_PCON_DSC_ENCODER);
2602 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2603 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2606 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2608 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2611 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2612 if (frl_bw_mask & (1 << i))
2618 static int intel_dp_pcon_set_frl_mask(int max_frl)
2622 return DP_PCON_FRL_BW_MASK_48GBPS;
2624 return DP_PCON_FRL_BW_MASK_40GBPS;
2626 return DP_PCON_FRL_BW_MASK_32GBPS;
2628 return DP_PCON_FRL_BW_MASK_24GBPS;
2630 return DP_PCON_FRL_BW_MASK_18GBPS;
2632 return DP_PCON_FRL_BW_MASK_9GBPS;
2638 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2640 struct intel_connector *intel_connector = intel_dp->attached_connector;
2641 struct drm_connector *connector = &intel_connector->base;
2643 int max_lanes, rate_per_lane;
2644 int max_dsc_lanes, dsc_rate_per_lane;
2646 max_lanes = connector->display_info.hdmi.max_lanes;
2647 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2648 max_frl_rate = max_lanes * rate_per_lane;
2650 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2651 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2652 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2653 if (max_dsc_lanes && dsc_rate_per_lane)
2654 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2657 return max_frl_rate;
2661 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2662 u8 max_frl_bw_mask, u8 *frl_trained_mask)
2664 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2665 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2666 *frl_trained_mask >= max_frl_bw_mask)
2672 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2674 #define TIMEOUT_FRL_READY_MS 500
2675 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2677 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2678 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2679 u8 max_frl_bw_mask = 0, frl_trained_mask;
2682 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2683 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2685 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2686 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2688 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2690 if (max_frl_bw <= 0)
2693 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2694 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2696 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2699 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2702 /* Wait for PCON to be FRL Ready */
2703 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2708 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2709 DP_PCON_ENABLE_SEQUENTIAL_LINK);
2712 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2713 DP_PCON_FRL_LINK_TRAIN_NORMAL);
2716 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2720 * Wait for FRL to be completed
2721 * Check if the HDMI Link is up and active.
2723 wait_for(is_active =
2724 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2725 TIMEOUT_HDMI_LINK_ACTIVE_MS);
2731 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2732 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2733 intel_dp->frl.is_trained = true;
2734 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2739 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2741 if (drm_dp_is_branch(intel_dp->dpcd) &&
2742 intel_dp_has_hdmi_sink(intel_dp) &&
2743 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2750 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2755 /* Set PCON source control mode */
2756 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2758 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2762 /* Set HDMI LINK ENABLE */
2763 buf |= DP_PCON_ENABLE_HDMI_LINK;
2764 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2771 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2773 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2776 * Always go for FRL training if:
2777 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2780 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2781 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2782 intel_dp->frl.is_trained)
2785 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2788 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2789 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2790 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2792 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2793 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2795 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2800 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2802 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2804 return intel_hdmi_dsc_get_slice_height(vactive);
2808 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2809 const struct intel_crtc_state *crtc_state)
2811 struct intel_connector *intel_connector = intel_dp->attached_connector;
2812 struct drm_connector *connector = &intel_connector->base;
2813 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2814 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2815 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2816 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2818 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2819 pcon_max_slice_width,
2820 hdmi_max_slices, hdmi_throughput);
2824 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2825 const struct intel_crtc_state *crtc_state,
2826 int num_slices, int slice_width)
2828 struct intel_connector *intel_connector = intel_dp->attached_connector;
2829 struct drm_connector *connector = &intel_connector->base;
2830 int output_format = crtc_state->output_format;
2831 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2832 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2833 int hdmi_max_chunk_bytes =
2834 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2836 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2837 num_slices, output_format, hdmi_all_bpp,
2838 hdmi_max_chunk_bytes);
2842 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2843 const struct intel_crtc_state *crtc_state)
2851 struct intel_connector *intel_connector = intel_dp->attached_connector;
2852 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2853 struct drm_connector *connector;
2854 bool hdmi_is_dsc_1_2;
2856 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2859 if (!intel_connector)
2861 connector = &intel_connector->base;
2862 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2864 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2868 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2872 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2876 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2879 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2880 num_slices, slice_width);
2881 if (!bits_per_pixel)
2884 pps_param[0] = slice_height & 0xFF;
2885 pps_param[1] = slice_height >> 8;
2886 pps_param[2] = slice_width & 0xFF;
2887 pps_param[3] = slice_width >> 8;
2888 pps_param[4] = bits_per_pixel & 0xFF;
2889 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2891 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2893 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2896 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2897 const struct intel_crtc_state *crtc_state)
2899 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2900 bool ycbcr444_to_420 = false;
2901 bool rgb_to_ycbcr = false;
2904 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2907 if (!drm_dp_is_branch(intel_dp->dpcd))
2910 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2912 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2913 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2914 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2915 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
2917 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2918 switch (crtc_state->output_format) {
2919 case INTEL_OUTPUT_FORMAT_YCBCR420:
2921 case INTEL_OUTPUT_FORMAT_YCBCR444:
2922 ycbcr444_to_420 = true;
2924 case INTEL_OUTPUT_FORMAT_RGB:
2925 rgb_to_ycbcr = true;
2926 ycbcr444_to_420 = true;
2929 MISSING_CASE(crtc_state->output_format);
2932 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
2933 switch (crtc_state->output_format) {
2934 case INTEL_OUTPUT_FORMAT_YCBCR444:
2936 case INTEL_OUTPUT_FORMAT_RGB:
2937 rgb_to_ycbcr = true;
2940 MISSING_CASE(crtc_state->output_format);
2945 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2947 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2948 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2949 drm_dbg_kms(&i915->drm,
2950 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2951 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2953 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2955 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2956 drm_dbg_kms(&i915->drm,
2957 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2958 str_enable_disable(tmp));
2961 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2965 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2968 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2971 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2973 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2976 * Clear the cached register set to avoid using stale values
2977 * for the sinks that do not support DSC.
2979 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2981 /* Clear fec_capable to avoid using stale values */
2982 intel_dp->fec_capable = 0;
2984 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2985 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2986 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2987 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2989 sizeof(intel_dp->dsc_dpcd)) < 0)
2991 "Failed to read DPCD register 0x%x\n",
2994 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2995 (int)sizeof(intel_dp->dsc_dpcd),
2996 intel_dp->dsc_dpcd);
2998 /* FEC is supported only on DP 1.4 */
2999 if (!intel_dp_is_edp(intel_dp) &&
3000 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3001 &intel_dp->fec_capable) < 0)
3003 "Failed to read FEC DPCD register\n");
3005 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3006 intel_dp->fec_capable);
3010 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3011 struct drm_display_mode *mode)
3013 struct intel_dp *intel_dp = intel_attached_dp(connector);
3014 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3015 int n = intel_dp->mso_link_count;
3016 int overlap = intel_dp->mso_pixel_overlap;
3021 mode->hdisplay = (mode->hdisplay - overlap) * n;
3022 mode->hsync_start = (mode->hsync_start - overlap) * n;
3023 mode->hsync_end = (mode->hsync_end - overlap) * n;
3024 mode->htotal = (mode->htotal - overlap) * n;
3027 drm_mode_set_name(mode);
3029 drm_dbg_kms(&i915->drm,
3030 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3031 connector->base.base.id, connector->base.name,
3032 DRM_MODE_ARG(mode));
3035 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3038 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3039 struct intel_connector *connector = intel_dp->attached_connector;
3041 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3043 * This is a big fat ugly hack.
3045 * Some machines in UEFI boot mode provide us a VBT that has 18
3046 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3047 * unknown we fail to light up. Yet the same BIOS boots up with
3048 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3049 * max, not what it tells us to use.
3051 * Note: This will still be broken if the eDP panel is not lit
3052 * up by the BIOS, and thus we can't get the mode at module
3055 drm_dbg_kms(&dev_priv->drm,
3056 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3057 pipe_bpp, connector->panel.vbt.edp.bpp);
3058 connector->panel.vbt.edp.bpp = pipe_bpp;
3062 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3064 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3065 struct intel_connector *connector = intel_dp->attached_connector;
3066 struct drm_display_info *info = &connector->base.display_info;
3069 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3072 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3073 drm_err(&i915->drm, "Failed to read MSO cap\n");
3077 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3078 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3079 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3080 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3085 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3086 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3087 info->mso_pixel_overlap);
3088 if (!HAS_MSO(i915)) {
3089 drm_err(&i915->drm, "No source MSO support, disabling\n");
3094 intel_dp->mso_link_count = mso;
3095 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3099 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3101 struct drm_i915_private *dev_priv =
3102 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3104 /* this function is meant to be called only once */
3105 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3107 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3110 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3111 drm_dp_is_branch(intel_dp->dpcd));
3114 * Read the eDP display control registers.
3116 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3117 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3118 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3119 * method). The display control registers should read zero if they're
3120 * not supported anyway.
3122 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3123 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3124 sizeof(intel_dp->edp_dpcd)) {
3125 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3126 (int)sizeof(intel_dp->edp_dpcd),
3127 intel_dp->edp_dpcd);
3129 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3133 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3134 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3136 intel_psr_init_dpcd(intel_dp);
3138 /* Clear the default sink rates */
3139 intel_dp->num_sink_rates = 0;
3141 /* Read the eDP 1.4+ supported link rates. */
3142 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3143 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3146 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3147 sink_rates, sizeof(sink_rates));
3149 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3150 int val = le16_to_cpu(sink_rates[i]);
3155 /* Value read multiplied by 200kHz gives the per-lane
3156 * link rate in kHz. The source rates are, however,
3157 * stored in terms of LS_Clk kHz. The full conversion
3158 * back to symbols is
3159 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3161 intel_dp->sink_rates[i] = (val * 200) / 10;
3163 intel_dp->num_sink_rates = i;
3167 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3168 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3170 if (intel_dp->num_sink_rates)
3171 intel_dp->use_rate_select = true;
3173 intel_dp_set_sink_rates(intel_dp);
3174 intel_dp_set_max_sink_lane_count(intel_dp);
3176 /* Read the eDP DSC DPCD registers */
3177 if (HAS_DSC(dev_priv))
3178 intel_dp_get_dsc_sink_cap(intel_dp);
3181 * If needed, program our source OUI so we can make various Intel-specific AUX services
3182 * available (such as HDR backlight controls)
3184 intel_edp_init_source_oui(intel_dp, true);
3190 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3192 if (!intel_dp->attached_connector)
3195 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3201 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3205 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3209 * Don't clobber cached eDP rates. Also skip re-reading
3210 * the OUI/ID since we know it won't change.
3212 if (!intel_dp_is_edp(intel_dp)) {
3213 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3214 drm_dp_is_branch(intel_dp->dpcd));
3216 intel_dp_set_sink_rates(intel_dp);
3217 intel_dp_set_max_sink_lane_count(intel_dp);
3218 intel_dp_set_common_rates(intel_dp);
3221 if (intel_dp_has_sink_count(intel_dp)) {
3222 ret = drm_dp_read_sink_count(&intel_dp->aux);
3227 * Sink count can change between short pulse hpd hence
3228 * a member variable in intel_dp will track any changes
3229 * between short pulse interrupts.
3231 intel_dp->sink_count = ret;
3234 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3235 * a dongle is present but no display. Unless we require to know
3236 * if a dongle is present or not, we don't need to update
3237 * downstream port information. So, an early return here saves
3238 * time from performing other operations which are not required.
3240 if (!intel_dp->sink_count)
3244 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3245 intel_dp->downstream_ports) == 0;
3249 intel_dp_can_mst(struct intel_dp *intel_dp)
3251 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3253 return i915->params.enable_dp_mst &&
3254 intel_dp_mst_source_support(intel_dp) &&
3255 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3259 intel_dp_configure_mst(struct intel_dp *intel_dp)
3261 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3262 struct intel_encoder *encoder =
3263 &dp_to_dig_port(intel_dp)->base;
3264 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3266 drm_dbg_kms(&i915->drm,
3267 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3268 encoder->base.base.id, encoder->base.name,
3269 str_yes_no(intel_dp_mst_source_support(intel_dp)),
3270 str_yes_no(sink_can_mst),
3271 str_yes_no(i915->params.enable_dp_mst));
3273 if (!intel_dp_mst_source_support(intel_dp))
3276 intel_dp->is_mst = sink_can_mst &&
3277 i915->params.enable_dp_mst;
3279 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3284 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3286 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3289 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3293 for (retry = 0; retry < 3; retry++) {
3294 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3303 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3304 const struct drm_connector_state *conn_state)
3307 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3308 * of Color Encoding Format and Content Color Gamut], in order to
3309 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3311 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3314 switch (conn_state->colorspace) {
3315 case DRM_MODE_COLORIMETRY_SYCC_601:
3316 case DRM_MODE_COLORIMETRY_OPYCC_601:
3317 case DRM_MODE_COLORIMETRY_BT2020_YCC:
3318 case DRM_MODE_COLORIMETRY_BT2020_RGB:
3319 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3328 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3329 struct dp_sdp *sdp, size_t size)
3331 size_t length = sizeof(struct dp_sdp);
3336 memset(sdp, 0, size);
3339 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3340 * VSC SDP Header Bytes
3342 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3343 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3344 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3345 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3348 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3351 if (vsc->revision != 0x5)
3354 /* VSC SDP Payload for DB16 through DB18 */
3355 /* Pixel Encoding and Colorimetry Formats */
3356 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3357 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3364 sdp->db[17] = 0x1; /* DB17[3:0] */
3376 MISSING_CASE(vsc->bpc);
3379 /* Dynamic Range and Component Bit Depth */
3380 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3381 sdp->db[17] |= 0x80; /* DB17[7] */
3384 sdp->db[18] = vsc->content_type & 0x7;
3391 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3392 const struct hdmi_drm_infoframe *drm_infoframe,
3396 size_t length = sizeof(struct dp_sdp);
3397 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3398 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3404 memset(sdp, 0, size);
3406 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3408 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3412 if (len != infoframe_size) {
3413 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3418 * Set up the infoframe sdp packet for HDR static metadata.
3419 * Prepare VSC Header for SU as per DP 1.4a spec,
3420 * Table 2-100 and Table 2-101
3423 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3424 sdp->sdp_header.HB0 = 0;
3426 * Packet Type 80h + Non-audio INFOFRAME Type value
3427 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3428 * - 80h + Non-audio INFOFRAME Type value
3429 * - InfoFrame Type: 0x07
3430 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3432 sdp->sdp_header.HB1 = drm_infoframe->type;
3434 * Least Significant Eight Bits of (Data Byte Count – 1)
3435 * infoframe_size - 1
3437 sdp->sdp_header.HB2 = 0x1D;
3438 /* INFOFRAME SDP Version Number */
3439 sdp->sdp_header.HB3 = (0x13 << 2);
3440 /* CTA Header Byte 2 (INFOFRAME Version Number) */
3441 sdp->db[0] = drm_infoframe->version;
3442 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3443 sdp->db[1] = drm_infoframe->length;
3445 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3446 * HDMI_INFOFRAME_HEADER_SIZE
3448 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3449 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3450 HDMI_DRM_INFOFRAME_SIZE);
3453 * Size of DP infoframe sdp packet for HDR static metadata consists of
3454 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3455 * - Two Data Blocks: 2 bytes
3456 * CTA Header Byte2 (INFOFRAME Version Number)
3457 * CTA Header Byte3 (Length of INFOFRAME)
3458 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3460 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3461 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3462 * will pad rest of the size.
3464 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3467 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3468 const struct intel_crtc_state *crtc_state,
3471 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3473 struct dp_sdp sdp = {};
3476 if ((crtc_state->infoframes.enable &
3477 intel_hdmi_infoframe_enable(type)) == 0)
3482 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3485 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3486 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3487 &crtc_state->infoframes.drm.drm,
3495 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3498 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3501 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3502 const struct intel_crtc_state *crtc_state,
3503 const struct drm_dp_vsc_sdp *vsc)
3505 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3507 struct dp_sdp sdp = {};
3510 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3512 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3515 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3519 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3521 const struct intel_crtc_state *crtc_state,
3522 const struct drm_connector_state *conn_state)
3524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3525 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3526 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3527 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3528 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3529 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3531 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3532 /* When PSR is enabled, this routine doesn't disable VSC DIP */
3533 if (!crtc_state->has_psr)
3534 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3536 intel_de_write(dev_priv, reg, val);
3537 intel_de_posting_read(dev_priv, reg);
3542 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3543 if (!crtc_state->has_psr)
3544 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3546 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3549 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3550 const void *buffer, size_t size)
3552 const struct dp_sdp *sdp = buffer;
3554 if (size < sizeof(struct dp_sdp))
3557 memset(vsc, 0, sizeof(*vsc));
3559 if (sdp->sdp_header.HB0 != 0)
3562 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3565 vsc->sdp_type = sdp->sdp_header.HB1;
3566 vsc->revision = sdp->sdp_header.HB2;
3567 vsc->length = sdp->sdp_header.HB3;
3569 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3570 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3572 * - HB2 = 0x2, HB3 = 0x8
3573 * VSC SDP supporting 3D stereo + PSR
3574 * - HB2 = 0x4, HB3 = 0xe
3575 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3576 * first scan line of the SU region (applies to eDP v1.4b
3580 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3582 * - HB2 = 0x5, HB3 = 0x13
3583 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3586 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3587 vsc->colorimetry = sdp->db[16] & 0xf;
3588 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3590 switch (sdp->db[17] & 0x7) {
3607 MISSING_CASE(sdp->db[17] & 0x7);
3611 vsc->content_type = sdp->db[18] & 0x7;
3620 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3621 const void *buffer, size_t size)
3625 const struct dp_sdp *sdp = buffer;
3627 if (size < sizeof(struct dp_sdp))
3630 if (sdp->sdp_header.HB0 != 0)
3633 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3637 * Least Significant Eight Bits of (Data Byte Count – 1)
3638 * 1Dh (i.e., Data Byte Count = 30 bytes).
3640 if (sdp->sdp_header.HB2 != 0x1D)
3643 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3644 if ((sdp->sdp_header.HB3 & 0x3) != 0)
3647 /* INFOFRAME SDP Version Number */
3648 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3651 /* CTA Header Byte 2 (INFOFRAME Version Number) */
3652 if (sdp->db[0] != 1)
3655 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3656 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3659 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3660 HDMI_DRM_INFOFRAME_SIZE);
3665 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3666 struct intel_crtc_state *crtc_state,
3667 struct drm_dp_vsc_sdp *vsc)
3669 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3671 unsigned int type = DP_SDP_VSC;
3672 struct dp_sdp sdp = {};
3675 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3676 if (crtc_state->has_psr)
3679 if ((crtc_state->infoframes.enable &
3680 intel_hdmi_infoframe_enable(type)) == 0)
3683 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3685 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3688 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3691 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3692 struct intel_crtc_state *crtc_state,
3693 struct hdmi_drm_infoframe *drm_infoframe)
3695 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3697 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3698 struct dp_sdp sdp = {};
3701 if ((crtc_state->infoframes.enable &
3702 intel_hdmi_infoframe_enable(type)) == 0)
3705 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3708 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3712 drm_dbg_kms(&dev_priv->drm,
3713 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3716 void intel_read_dp_sdp(struct intel_encoder *encoder,
3717 struct intel_crtc_state *crtc_state,
3722 intel_read_dp_vsc_sdp(encoder, crtc_state,
3723 &crtc_state->infoframes.vsc);
3725 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3726 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3727 &crtc_state->infoframes.drm.drm);
3735 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3737 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3740 u8 test_lane_count, test_link_bw;
3744 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3745 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3749 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3752 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3754 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3757 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3760 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3762 /* Validate the requested link rate and lane count */
3763 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3767 intel_dp->compliance.test_lane_count = test_lane_count;
3768 intel_dp->compliance.test_link_rate = test_link_rate;
3773 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3775 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3778 __be16 h_width, v_height;
3781 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3782 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3785 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3788 if (test_pattern != DP_COLOR_RAMP)
3791 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3794 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3798 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3801 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3805 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3808 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3811 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3813 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3815 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3816 case DP_TEST_BIT_DEPTH_6:
3817 intel_dp->compliance.test_data.bpc = 6;
3819 case DP_TEST_BIT_DEPTH_8:
3820 intel_dp->compliance.test_data.bpc = 8;
3826 intel_dp->compliance.test_data.video_pattern = test_pattern;
3827 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3828 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3829 /* Set test active flag here so userspace doesn't interrupt things */
3830 intel_dp->compliance.test_active = true;
3835 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3837 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3838 u8 test_result = DP_TEST_ACK;
3839 struct intel_connector *intel_connector = intel_dp->attached_connector;
3840 struct drm_connector *connector = &intel_connector->base;
3842 if (intel_connector->detect_edid == NULL ||
3843 connector->edid_corrupt ||
3844 intel_dp->aux.i2c_defer_count > 6) {
3845 /* Check EDID read for NACKs, DEFERs and corruption
3846 * (DP CTS 1.2 Core r1.1)
3847 * 4.2.2.4 : Failed EDID read, I2C_NAK
3848 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3849 * 4.2.2.6 : EDID corruption detected
3850 * Use failsafe mode for all cases
3852 if (intel_dp->aux.i2c_nack_count > 0 ||
3853 intel_dp->aux.i2c_defer_count > 0)
3854 drm_dbg_kms(&i915->drm,
3855 "EDID read had %d NACKs, %d DEFERs\n",
3856 intel_dp->aux.i2c_nack_count,
3857 intel_dp->aux.i2c_defer_count);
3858 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3860 /* FIXME: Get rid of drm_edid_raw() */
3861 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
3863 /* We have to write the checksum of the last block read */
3864 block += block->extensions;
3866 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3867 block->checksum) <= 0)
3868 drm_dbg_kms(&i915->drm,
3869 "Failed to write EDID checksum\n");
3871 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3872 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3875 /* Set test active flag here so userspace doesn't interrupt things */
3876 intel_dp->compliance.test_active = true;
3881 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3882 const struct intel_crtc_state *crtc_state)
3884 struct drm_i915_private *dev_priv =
3885 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3886 struct drm_dp_phy_test_params *data =
3887 &intel_dp->compliance.test_data.phytest;
3888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3889 enum pipe pipe = crtc->pipe;
3892 switch (data->phy_pattern) {
3893 case DP_PHY_TEST_PATTERN_NONE:
3894 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3895 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3897 case DP_PHY_TEST_PATTERN_D10_2:
3898 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3899 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3900 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3902 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3903 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3904 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3905 DDI_DP_COMP_CTL_ENABLE |
3906 DDI_DP_COMP_CTL_SCRAMBLED_0);
3908 case DP_PHY_TEST_PATTERN_PRBS7:
3909 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3910 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3911 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3913 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3915 * FIXME: Ideally pattern should come from DPCD 0x250. As
3916 * current firmware of DPR-100 could not set it, so hardcoding
3917 * now for complaince test.
3919 drm_dbg_kms(&dev_priv->drm,
3920 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3921 pattern_val = 0x3e0f83e0;
3922 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3923 pattern_val = 0x0f83e0f8;
3924 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3925 pattern_val = 0x0000f83e;
3926 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3927 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3928 DDI_DP_COMP_CTL_ENABLE |
3929 DDI_DP_COMP_CTL_CUSTOM80);
3931 case DP_PHY_TEST_PATTERN_CP2520:
3933 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3934 * current firmware of DPR-100 could not set it, so hardcoding
3935 * now for complaince test.
3937 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3939 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3940 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3944 WARN(1, "Invalid Phy Test Pattern\n");
3948 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3949 const struct intel_crtc_state *crtc_state)
3951 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3952 struct drm_dp_phy_test_params *data =
3953 &intel_dp->compliance.test_data.phytest;
3954 u8 link_status[DP_LINK_STATUS_SIZE];
3956 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3958 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3962 /* retrieve vswing & pre-emphasis setting */
3963 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3966 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3968 intel_dp_phy_pattern_update(intel_dp, crtc_state);
3970 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3971 intel_dp->train_set, crtc_state->lane_count);
3973 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3974 link_status[DP_DPCD_REV]);
3977 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3979 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3980 struct drm_dp_phy_test_params *data =
3981 &intel_dp->compliance.test_data.phytest;
3983 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3984 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3988 /* Set test active flag here so userspace doesn't interrupt things */
3989 intel_dp->compliance.test_active = true;
3994 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3996 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3997 u8 response = DP_TEST_NAK;
4001 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4003 drm_dbg_kms(&i915->drm,
4004 "Could not read test request from sink\n");
4009 case DP_TEST_LINK_TRAINING:
4010 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4011 response = intel_dp_autotest_link_training(intel_dp);
4013 case DP_TEST_LINK_VIDEO_PATTERN:
4014 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4015 response = intel_dp_autotest_video_pattern(intel_dp);
4017 case DP_TEST_LINK_EDID_READ:
4018 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4019 response = intel_dp_autotest_edid(intel_dp);
4021 case DP_TEST_LINK_PHY_TEST_PATTERN:
4022 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4023 response = intel_dp_autotest_phy_pattern(intel_dp);
4026 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4031 if (response & DP_TEST_ACK)
4032 intel_dp->compliance.test_type = request;
4035 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4037 drm_dbg_kms(&i915->drm,
4038 "Could not write test response to sink\n");
4041 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4042 u8 link_status[DP_LINK_STATUS_SIZE])
4044 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4045 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4046 bool uhbr = intel_dp->link_rate >= 1000000;
4050 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4051 intel_dp->lane_count);
4053 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4058 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4059 drm_dbg_kms(&i915->drm,
4060 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4061 encoder->base.base.id, encoder->base.name,
4062 uhbr ? "128b/132b" : "8b/10b");
4068 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4070 bool handled = false;
4072 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4074 if (esi[1] & DP_CP_IRQ) {
4075 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4076 ack[1] |= DP_CP_IRQ;
4080 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4082 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4083 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4084 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4085 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4087 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4088 esi_link_status_size) != esi_link_status_size) {
4090 "[ENCODER:%d:%s] Failed to read link status\n",
4091 encoder->base.base.id, encoder->base.name);
4095 return intel_dp_link_ok(intel_dp, link_status);
4099 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4100 * @intel_dp: Intel DP struct
4102 * Read any pending MST interrupts, call MST core to handle these and ack the
4103 * interrupts. Check if the main and AUX link state is ok.
4106 * - %true if pending interrupts were serviced (or no interrupts were
4107 * pending) w/o detecting an error condition.
4108 * - %false if an error condition - like AUX failure or a loss of link - is
4109 * detected, which needs servicing from the hotplug work.
4112 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4114 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4115 bool link_ok = true;
4117 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4123 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4124 drm_dbg_kms(&i915->drm,
4125 "failed to get ESI - device may have failed\n");
4131 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4133 if (intel_dp->active_mst_links > 0 && link_ok &&
4134 esi[3] & LINK_STATUS_CHANGED) {
4135 if (!intel_dp_mst_link_status(intel_dp))
4137 ack[3] |= LINK_STATUS_CHANGED;
4140 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4142 if (!memchr_inv(ack, 0, sizeof(ack)))
4145 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4146 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4148 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4149 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4156 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4161 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4162 if (intel_dp->frl.is_trained && !is_active) {
4163 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4166 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
4167 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4170 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4172 intel_dp->frl.is_trained = false;
4174 /* Restart FRL training or fall back to TMDS mode */
4175 intel_dp_check_frl_training(intel_dp);
4180 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4182 u8 link_status[DP_LINK_STATUS_SIZE];
4184 if (!intel_dp->link_trained)
4188 * While PSR source HW is enabled, it will control main-link sending
4189 * frames, enabling and disabling it so trying to do a retrain will fail
4190 * as the link would or not be on or it could mix training patterns
4191 * and frame data at the same time causing retrain to fail.
4192 * Also when exiting PSR, HW will retrain the link anyways fixing
4193 * any link status error.
4195 if (intel_psr_enabled(intel_dp))
4198 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4203 * Validate the cached values of intel_dp->link_rate and
4204 * intel_dp->lane_count before attempting to retrain.
4206 * FIXME would be nice to user the crtc state here, but since
4207 * we need to call this from the short HPD handler that seems
4210 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4211 intel_dp->lane_count))
4214 /* Retrain if link not ok */
4215 return !intel_dp_link_ok(intel_dp, link_status);
4218 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4219 const struct drm_connector_state *conn_state)
4221 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4222 struct intel_encoder *encoder;
4225 if (!conn_state->best_encoder)
4229 encoder = &dp_to_dig_port(intel_dp)->base;
4230 if (conn_state->best_encoder == &encoder->base)
4234 for_each_pipe(i915, pipe) {
4235 encoder = &intel_dp->mst_encoders[pipe]->base;
4236 if (conn_state->best_encoder == &encoder->base)
4243 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4244 struct drm_modeset_acquire_ctx *ctx,
4247 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4248 struct drm_connector_list_iter conn_iter;
4249 struct intel_connector *connector;
4254 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4255 for_each_intel_connector_iter(connector, &conn_iter) {
4256 struct drm_connector_state *conn_state =
4257 connector->base.state;
4258 struct intel_crtc_state *crtc_state;
4259 struct intel_crtc *crtc;
4261 if (!intel_dp_has_connector(intel_dp, conn_state))
4264 crtc = to_intel_crtc(conn_state->crtc);
4268 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4272 crtc_state = to_intel_crtc_state(crtc->base.state);
4274 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4276 if (!crtc_state->hw.active)
4279 if (conn_state->commit &&
4280 !try_wait_for_completion(&conn_state->commit->hw_done))
4283 *pipe_mask |= BIT(crtc->pipe);
4285 drm_connector_list_iter_end(&conn_iter);
4290 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4292 struct intel_connector *connector = intel_dp->attached_connector;
4294 return connector->base.status == connector_status_connected ||
4298 int intel_dp_retrain_link(struct intel_encoder *encoder,
4299 struct drm_modeset_acquire_ctx *ctx)
4301 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4302 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4303 struct intel_crtc *crtc;
4307 if (!intel_dp_is_connected(intel_dp))
4310 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4315 if (!intel_dp_needs_link_retrain(intel_dp))
4318 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
4325 if (!intel_dp_needs_link_retrain(intel_dp))
4328 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4329 encoder->base.base.id, encoder->base.name);
4331 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4332 const struct intel_crtc_state *crtc_state =
4333 to_intel_crtc_state(crtc->base.state);
4335 /* Suppress underruns caused by re-training */
4336 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4337 if (crtc_state->has_pch_encoder)
4338 intel_set_pch_fifo_underrun_reporting(dev_priv,
4339 intel_crtc_pch_transcoder(crtc), false);
4342 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4343 const struct intel_crtc_state *crtc_state =
4344 to_intel_crtc_state(crtc->base.state);
4346 /* retrain on the MST master transcoder */
4347 if (DISPLAY_VER(dev_priv) >= 12 &&
4348 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4349 !intel_dp_mst_is_master_trans(crtc_state))
4352 intel_dp_check_frl_training(intel_dp);
4353 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4354 intel_dp_start_link_train(intel_dp, crtc_state);
4355 intel_dp_stop_link_train(intel_dp, crtc_state);
4359 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4360 const struct intel_crtc_state *crtc_state =
4361 to_intel_crtc_state(crtc->base.state);
4363 /* Keep underrun reporting disabled until things are stable */
4364 intel_crtc_wait_for_next_vblank(crtc);
4366 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4367 if (crtc_state->has_pch_encoder)
4368 intel_set_pch_fifo_underrun_reporting(dev_priv,
4369 intel_crtc_pch_transcoder(crtc), true);
4375 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4376 struct drm_modeset_acquire_ctx *ctx,
4379 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4380 struct drm_connector_list_iter conn_iter;
4381 struct intel_connector *connector;
4386 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4387 for_each_intel_connector_iter(connector, &conn_iter) {
4388 struct drm_connector_state *conn_state =
4389 connector->base.state;
4390 struct intel_crtc_state *crtc_state;
4391 struct intel_crtc *crtc;
4393 if (!intel_dp_has_connector(intel_dp, conn_state))
4396 crtc = to_intel_crtc(conn_state->crtc);
4400 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4404 crtc_state = to_intel_crtc_state(crtc->base.state);
4406 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4408 if (!crtc_state->hw.active)
4411 if (conn_state->commit &&
4412 !try_wait_for_completion(&conn_state->commit->hw_done))
4415 *pipe_mask |= BIT(crtc->pipe);
4417 drm_connector_list_iter_end(&conn_iter);
4422 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4423 struct drm_modeset_acquire_ctx *ctx)
4425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4426 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4427 struct intel_crtc *crtc;
4431 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4436 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4443 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4444 encoder->base.base.id, encoder->base.name);
4446 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4447 const struct intel_crtc_state *crtc_state =
4448 to_intel_crtc_state(crtc->base.state);
4450 /* test on the MST master transcoder */
4451 if (DISPLAY_VER(dev_priv) >= 12 &&
4452 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4453 !intel_dp_mst_is_master_trans(crtc_state))
4456 intel_dp_process_phy_request(intel_dp, crtc_state);
4463 void intel_dp_phy_test(struct intel_encoder *encoder)
4465 struct drm_modeset_acquire_ctx ctx;
4468 drm_modeset_acquire_init(&ctx, 0);
4471 ret = intel_dp_do_phy_test(encoder, &ctx);
4473 if (ret == -EDEADLK) {
4474 drm_modeset_backoff(&ctx);
4481 drm_modeset_drop_locks(&ctx);
4482 drm_modeset_acquire_fini(&ctx);
4483 drm_WARN(encoder->base.dev, ret,
4484 "Acquiring modeset locks failed with %i\n", ret);
4487 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4489 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4492 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4495 if (drm_dp_dpcd_readb(&intel_dp->aux,
4496 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4499 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4501 if (val & DP_AUTOMATED_TEST_REQUEST)
4502 intel_dp_handle_test_request(intel_dp);
4504 if (val & DP_CP_IRQ)
4505 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4507 if (val & DP_SINK_SPECIFIC_IRQ)
4508 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4511 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4515 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4518 if (drm_dp_dpcd_readb(&intel_dp->aux,
4519 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4522 if (drm_dp_dpcd_writeb(&intel_dp->aux,
4523 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4526 if (val & HDMI_LINK_STATUS_CHANGED)
4527 intel_dp_handle_hdmi_link_status_change(intel_dp);
4531 * According to DP spec
4534 * 2. Configure link according to Receiver Capabilities
4535 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4536 * 4. Check link status on receipt of hot-plug interrupt
4538 * intel_dp_short_pulse - handles short pulse interrupts
4539 * when full detection is not required.
4540 * Returns %true if short pulse is handled and full detection
4541 * is NOT required and %false otherwise.
4544 intel_dp_short_pulse(struct intel_dp *intel_dp)
4546 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4547 u8 old_sink_count = intel_dp->sink_count;
4551 * Clearing compliance test variables to allow capturing
4552 * of values for next automated test request.
4554 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4557 * Now read the DPCD to see if it's actually running
4558 * If the current value of sink count doesn't match with
4559 * the value that was stored earlier or dpcd read failed
4560 * we need to do full detection
4562 ret = intel_dp_get_dpcd(intel_dp);
4564 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4565 /* No need to proceed if we are going to do full detect */
4569 intel_dp_check_device_service_irq(intel_dp);
4570 intel_dp_check_link_service_irq(intel_dp);
4572 /* Handle CEC interrupts, if any */
4573 drm_dp_cec_irq(&intel_dp->aux);
4575 /* defer to the hotplug work for link retraining if needed */
4576 if (intel_dp_needs_link_retrain(intel_dp))
4579 intel_psr_short_pulse(intel_dp);
4581 switch (intel_dp->compliance.test_type) {
4582 case DP_TEST_LINK_TRAINING:
4583 drm_dbg_kms(&dev_priv->drm,
4584 "Link Training Compliance Test requested\n");
4585 /* Send a Hotplug Uevent to userspace to start modeset */
4586 drm_kms_helper_hotplug_event(&dev_priv->drm);
4588 case DP_TEST_LINK_PHY_TEST_PATTERN:
4589 drm_dbg_kms(&dev_priv->drm,
4590 "PHY test pattern Compliance Test requested\n");
4592 * Schedule long hpd to do the test
4594 * FIXME get rid of the ad-hoc phy test modeset code
4595 * and properly incorporate it into the normal modeset.
4603 /* XXX this is probably wrong for multiple downstream ports */
4604 static enum drm_connector_status
4605 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4607 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4608 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4609 u8 *dpcd = intel_dp->dpcd;
4612 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4613 return connector_status_connected;
4615 lspcon_resume(dig_port);
4617 if (!intel_dp_get_dpcd(intel_dp))
4618 return connector_status_disconnected;
4620 /* if there's no downstream port, we're done */
4621 if (!drm_dp_is_branch(dpcd))
4622 return connector_status_connected;
4624 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4625 if (intel_dp_has_sink_count(intel_dp) &&
4626 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4627 return intel_dp->sink_count ?
4628 connector_status_connected : connector_status_disconnected;
4631 if (intel_dp_can_mst(intel_dp))
4632 return connector_status_connected;
4634 /* If no HPD, poke DDC gently */
4635 if (drm_probe_ddc(&intel_dp->aux.ddc))
4636 return connector_status_connected;
4638 /* Well we tried, say unknown for unreliable port types */
4639 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4640 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4641 if (type == DP_DS_PORT_TYPE_VGA ||
4642 type == DP_DS_PORT_TYPE_NON_EDID)
4643 return connector_status_unknown;
4645 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4646 DP_DWN_STRM_PORT_TYPE_MASK;
4647 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4648 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4649 return connector_status_unknown;
4652 /* Anything else is out of spec, warn and ignore */
4653 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4654 return connector_status_disconnected;
4657 static enum drm_connector_status
4658 edp_detect(struct intel_dp *intel_dp)
4660 return connector_status_connected;
4664 * intel_digital_port_connected - is the specified port connected?
4665 * @encoder: intel_encoder
4667 * In cases where there's a connector physically connected but it can't be used
4668 * by our hardware we also return false, since the rest of the driver should
4669 * pretty much treat the port as disconnected. This is relevant for type-C
4670 * (starting on ICL) where there's ownership involved.
4672 * Return %true if port is connected, %false otherwise.
4674 bool intel_digital_port_connected(struct intel_encoder *encoder)
4676 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4677 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4678 bool is_connected = false;
4679 intel_wakeref_t wakeref;
4681 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4682 is_connected = dig_port->connected(encoder);
4684 return is_connected;
4687 static const struct drm_edid *
4688 intel_dp_get_edid(struct intel_dp *intel_dp)
4690 struct intel_connector *connector = intel_dp->attached_connector;
4691 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
4693 /* Use panel fixed edid if we have one */
4696 if (IS_ERR(fixed_edid))
4699 return drm_edid_dup(fixed_edid);
4702 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
4706 intel_dp_update_dfp(struct intel_dp *intel_dp,
4707 const struct drm_edid *drm_edid)
4709 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4710 struct intel_connector *connector = intel_dp->attached_connector;
4711 const struct edid *edid;
4713 /* FIXME: Get rid of drm_edid_raw() */
4714 edid = drm_edid_raw(drm_edid);
4716 intel_dp->dfp.max_bpc =
4717 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4718 intel_dp->downstream_ports, edid);
4720 intel_dp->dfp.max_dotclock =
4721 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4722 intel_dp->downstream_ports);
4724 intel_dp->dfp.min_tmds_clock =
4725 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4726 intel_dp->downstream_ports,
4728 intel_dp->dfp.max_tmds_clock =
4729 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4730 intel_dp->downstream_ports,
4733 intel_dp->dfp.pcon_max_frl_bw =
4734 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4735 intel_dp->downstream_ports);
4737 drm_dbg_kms(&i915->drm,
4738 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4739 connector->base.base.id, connector->base.name,
4740 intel_dp->dfp.max_bpc,
4741 intel_dp->dfp.max_dotclock,
4742 intel_dp->dfp.min_tmds_clock,
4743 intel_dp->dfp.max_tmds_clock,
4744 intel_dp->dfp.pcon_max_frl_bw);
4746 intel_dp_get_pcon_dsc_cap(intel_dp);
4750 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
4752 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
4753 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
4756 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
4757 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4760 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
4761 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4768 intel_dp_update_420(struct intel_dp *intel_dp)
4770 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4771 struct intel_connector *connector = intel_dp->attached_connector;
4773 intel_dp->dfp.ycbcr420_passthrough =
4774 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4775 intel_dp->downstream_ports);
4776 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4777 intel_dp->dfp.ycbcr_444_to_420 =
4778 dp_to_dig_port(intel_dp)->lspcon.active ||
4779 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4780 intel_dp->downstream_ports);
4781 intel_dp->dfp.rgb_to_ycbcr =
4782 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4783 intel_dp->downstream_ports,
4784 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4786 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
4788 drm_dbg_kms(&i915->drm,
4789 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4790 connector->base.base.id, connector->base.name,
4791 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4792 str_yes_no(connector->base.ycbcr_420_allowed),
4793 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4797 intel_dp_set_edid(struct intel_dp *intel_dp)
4799 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4800 struct intel_connector *connector = intel_dp->attached_connector;
4801 const struct drm_edid *drm_edid;
4802 const struct edid *edid;
4805 intel_dp_unset_edid(intel_dp);
4806 drm_edid = intel_dp_get_edid(intel_dp);
4807 connector->detect_edid = drm_edid;
4809 /* Below we depend on display info having been updated */
4810 drm_edid_connector_update(&connector->base, drm_edid);
4812 vrr_capable = intel_vrr_is_capable(connector);
4813 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4814 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4815 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4817 intel_dp_update_dfp(intel_dp, drm_edid);
4818 intel_dp_update_420(intel_dp);
4820 /* FIXME: Get rid of drm_edid_raw() */
4821 edid = drm_edid_raw(drm_edid);
4823 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4827 intel_dp_unset_edid(struct intel_dp *intel_dp)
4829 struct intel_connector *connector = intel_dp->attached_connector;
4831 drm_dp_cec_unset_edid(&intel_dp->aux);
4832 drm_edid_free(connector->detect_edid);
4833 connector->detect_edid = NULL;
4835 intel_dp->dfp.max_bpc = 0;
4836 intel_dp->dfp.max_dotclock = 0;
4837 intel_dp->dfp.min_tmds_clock = 0;
4838 intel_dp->dfp.max_tmds_clock = 0;
4840 intel_dp->dfp.pcon_max_frl_bw = 0;
4842 intel_dp->dfp.ycbcr_444_to_420 = false;
4843 connector->base.ycbcr_420_allowed = false;
4845 drm_connector_set_vrr_capable_property(&connector->base,
4850 intel_dp_detect(struct drm_connector *connector,
4851 struct drm_modeset_acquire_ctx *ctx,
4854 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4855 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4856 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4857 struct intel_encoder *encoder = &dig_port->base;
4858 enum drm_connector_status status;
4860 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4861 connector->base.id, connector->name);
4862 drm_WARN_ON(&dev_priv->drm,
4863 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4865 if (!INTEL_DISPLAY_ENABLED(dev_priv))
4866 return connector_status_disconnected;
4868 /* Can't disconnect eDP */
4869 if (intel_dp_is_edp(intel_dp))
4870 status = edp_detect(intel_dp);
4871 else if (intel_digital_port_connected(encoder))
4872 status = intel_dp_detect_dpcd(intel_dp);
4874 status = connector_status_disconnected;
4876 if (status == connector_status_disconnected) {
4877 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4878 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4880 if (intel_dp->is_mst) {
4881 drm_dbg_kms(&dev_priv->drm,
4882 "MST device may have disappeared %d vs %d\n",
4884 intel_dp->mst_mgr.mst_state);
4885 intel_dp->is_mst = false;
4886 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4893 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4894 if (HAS_DSC(dev_priv))
4895 intel_dp_get_dsc_sink_cap(intel_dp);
4897 intel_dp_configure_mst(intel_dp);
4900 * TODO: Reset link params when switching to MST mode, until MST
4901 * supports link training fallback params.
4903 if (intel_dp->reset_link_params || intel_dp->is_mst) {
4904 intel_dp_reset_max_link_params(intel_dp);
4905 intel_dp->reset_link_params = false;
4908 intel_dp_print_rates(intel_dp);
4910 if (intel_dp->is_mst) {
4912 * If we are in MST mode then this connector
4913 * won't appear connected or have anything
4916 status = connector_status_disconnected;
4921 * Some external monitors do not signal loss of link synchronization
4922 * with an IRQ_HPD, so force a link status check.
4924 if (!intel_dp_is_edp(intel_dp)) {
4927 ret = intel_dp_retrain_link(encoder, ctx);
4933 * Clearing NACK and defer counts to get their exact values
4934 * while reading EDID which are required by Compliance tests
4935 * 4.2.2.4 and 4.2.2.5
4937 intel_dp->aux.i2c_nack_count = 0;
4938 intel_dp->aux.i2c_defer_count = 0;
4940 intel_dp_set_edid(intel_dp);
4941 if (intel_dp_is_edp(intel_dp) ||
4942 to_intel_connector(connector)->detect_edid)
4943 status = connector_status_connected;
4945 intel_dp_check_device_service_irq(intel_dp);
4948 if (status != connector_status_connected && !intel_dp->is_mst)
4949 intel_dp_unset_edid(intel_dp);
4952 * Make sure the refs for power wells enabled during detect are
4953 * dropped to avoid a new detect cycle triggered by HPD polling.
4955 intel_display_power_flush_work(dev_priv);
4957 if (!intel_dp_is_edp(intel_dp))
4958 drm_dp_set_subconnector_property(connector,
4961 intel_dp->downstream_ports);
4966 intel_dp_force(struct drm_connector *connector)
4968 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4969 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4970 struct intel_encoder *intel_encoder = &dig_port->base;
4971 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4972 enum intel_display_power_domain aux_domain =
4973 intel_aux_power_domain(dig_port);
4974 intel_wakeref_t wakeref;
4976 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4977 connector->base.id, connector->name);
4978 intel_dp_unset_edid(intel_dp);
4980 if (connector->status != connector_status_connected)
4983 wakeref = intel_display_power_get(dev_priv, aux_domain);
4985 intel_dp_set_edid(intel_dp);
4987 intel_display_power_put(dev_priv, aux_domain, wakeref);
4990 static int intel_dp_get_modes(struct drm_connector *connector)
4992 struct intel_connector *intel_connector = to_intel_connector(connector);
4995 /* drm_edid_connector_update() done in ->detect() or ->force() */
4996 num_modes = drm_edid_connector_add_modes(connector);
4998 /* Also add fixed mode, which may or may not be present in EDID */
4999 if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5000 num_modes += intel_panel_get_modes(intel_connector);
5005 if (!intel_connector->detect_edid) {
5006 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5007 struct drm_display_mode *mode;
5009 mode = drm_dp_downstream_mode(connector->dev,
5011 intel_dp->downstream_ports);
5013 drm_mode_probed_add(connector, mode);
5022 intel_dp_connector_register(struct drm_connector *connector)
5024 struct drm_i915_private *i915 = to_i915(connector->dev);
5025 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5026 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5027 struct intel_lspcon *lspcon = &dig_port->lspcon;
5030 ret = intel_connector_register(connector);
5034 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5035 intel_dp->aux.name, connector->kdev->kobj.name);
5037 intel_dp->aux.dev = connector->kdev;
5038 ret = drm_dp_aux_register(&intel_dp->aux);
5040 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5042 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5046 * ToDo: Clean this up to handle lspcon init and resume more
5047 * efficiently and streamlined.
5049 if (lspcon_init(dig_port)) {
5050 lspcon_detect_hdr_capability(lspcon);
5051 if (lspcon->hdr_supported)
5052 drm_connector_attach_hdr_output_metadata_property(connector);
5059 intel_dp_connector_unregister(struct drm_connector *connector)
5061 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5063 drm_dp_cec_unregister_connector(&intel_dp->aux);
5064 drm_dp_aux_unregister(&intel_dp->aux);
5065 intel_connector_unregister(connector);
5068 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5070 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5071 struct intel_dp *intel_dp = &dig_port->dp;
5073 intel_dp_mst_encoder_cleanup(dig_port);
5075 intel_pps_vdd_off_sync(intel_dp);
5078 * Ensure power off delay is respected on module remove, so that we can
5079 * reduce delays at driver probe. See pps_init_timestamps().
5081 intel_pps_wait_power_cycle(intel_dp);
5083 intel_dp_aux_fini(intel_dp);
5086 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5088 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5090 intel_pps_vdd_off_sync(intel_dp);
5093 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5095 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5097 intel_pps_wait_power_cycle(intel_dp);
5100 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5103 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5104 struct drm_connector_list_iter conn_iter;
5105 struct drm_connector *connector;
5108 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5109 drm_for_each_connector_iter(connector, &conn_iter) {
5110 struct drm_connector_state *conn_state;
5111 struct intel_crtc_state *crtc_state;
5112 struct intel_crtc *crtc;
5114 if (!connector->has_tile ||
5115 connector->tile_group->id != tile_group_id)
5118 conn_state = drm_atomic_get_connector_state(&state->base,
5120 if (IS_ERR(conn_state)) {
5121 ret = PTR_ERR(conn_state);
5125 crtc = to_intel_crtc(conn_state->crtc);
5130 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5131 crtc_state->uapi.mode_changed = true;
5133 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5137 drm_connector_list_iter_end(&conn_iter);
5142 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5144 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5145 struct intel_crtc *crtc;
5147 if (transcoders == 0)
5150 for_each_intel_crtc(&dev_priv->drm, crtc) {
5151 struct intel_crtc_state *crtc_state;
5154 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5155 if (IS_ERR(crtc_state))
5156 return PTR_ERR(crtc_state);
5158 if (!crtc_state->hw.enable)
5161 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5164 crtc_state->uapi.mode_changed = true;
5166 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5170 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5174 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5177 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5182 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5183 struct drm_connector *connector)
5185 const struct drm_connector_state *old_conn_state =
5186 drm_atomic_get_old_connector_state(&state->base, connector);
5187 const struct intel_crtc_state *old_crtc_state;
5188 struct intel_crtc *crtc;
5191 crtc = to_intel_crtc(old_conn_state->crtc);
5195 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5197 if (!old_crtc_state->hw.active)
5200 transcoders = old_crtc_state->sync_mode_slaves_mask;
5201 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5202 transcoders |= BIT(old_crtc_state->master_transcoder);
5204 return intel_modeset_affected_transcoders(state,
5208 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5209 struct drm_atomic_state *_state)
5211 struct drm_i915_private *dev_priv = to_i915(conn->dev);
5212 struct intel_atomic_state *state = to_intel_atomic_state(_state);
5213 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5214 struct intel_connector *intel_conn = to_intel_connector(conn);
5215 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5218 ret = intel_digital_connector_atomic_check(conn, &state->base);
5222 if (intel_dp_mst_source_support(intel_dp)) {
5223 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5229 * We don't enable port sync on BDW due to missing w/as and
5230 * due to not having adjusted the modeset sequence appropriately.
5232 if (DISPLAY_VER(dev_priv) < 9)
5235 if (!intel_connector_needs_modeset(state, conn))
5238 if (conn->has_tile) {
5239 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5244 return intel_modeset_synced_crtcs(state, conn);
5247 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5249 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5250 struct drm_i915_private *i915 = to_i915(connector->dev);
5252 spin_lock_irq(&i915->irq_lock);
5253 i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5254 spin_unlock_irq(&i915->irq_lock);
5255 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
5258 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5259 .force = intel_dp_force,
5260 .fill_modes = drm_helper_probe_single_connector_modes,
5261 .atomic_get_property = intel_digital_connector_atomic_get_property,
5262 .atomic_set_property = intel_digital_connector_atomic_set_property,
5263 .late_register = intel_dp_connector_register,
5264 .early_unregister = intel_dp_connector_unregister,
5265 .destroy = intel_connector_destroy,
5266 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5267 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5268 .oob_hotplug_event = intel_dp_oob_hotplug_event,
5271 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5272 .detect_ctx = intel_dp_detect,
5273 .get_modes = intel_dp_get_modes,
5274 .mode_valid = intel_dp_mode_valid,
5275 .atomic_check = intel_dp_connector_atomic_check,
5279 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5281 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5282 struct intel_dp *intel_dp = &dig_port->dp;
5284 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5285 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5287 * vdd off can generate a long/short pulse on eDP which
5288 * would require vdd on to handle it, and thus we
5289 * would end up in an endless cycle of
5290 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5292 drm_dbg_kms(&i915->drm,
5293 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5294 long_hpd ? "long" : "short",
5295 dig_port->base.base.base.id,
5296 dig_port->base.base.name);
5300 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5301 dig_port->base.base.base.id,
5302 dig_port->base.base.name,
5303 long_hpd ? "long" : "short");
5306 intel_dp->reset_link_params = true;
5310 if (intel_dp->is_mst) {
5311 if (!intel_dp_check_mst_status(intel_dp))
5313 } else if (!intel_dp_short_pulse(intel_dp)) {
5320 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5321 const struct intel_bios_encoder_data *devdata,
5325 * eDP not supported on g4x. so bail out early just
5326 * for a bit extra safety in case the VBT is bonkers.
5328 if (DISPLAY_VER(dev_priv) < 5)
5331 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5334 return devdata && intel_bios_encoder_supports_edp(devdata);
5337 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5339 const struct intel_bios_encoder_data *devdata =
5340 intel_bios_encoder_data_lookup(i915, port);
5342 return _intel_dp_is_port_edp(i915, devdata, port);
5346 has_gamut_metadata_dip(struct intel_encoder *encoder)
5348 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5349 enum port port = encoder->port;
5351 if (intel_bios_encoder_is_lspcon(encoder->devdata))
5354 if (DISPLAY_VER(i915) >= 11)
5360 if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5361 DISPLAY_VER(i915) >= 9)
5368 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5370 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5371 enum port port = dp_to_dig_port(intel_dp)->base.port;
5373 if (!intel_dp_is_edp(intel_dp))
5374 drm_connector_attach_dp_subconnector_property(connector);
5376 if (!IS_G4X(dev_priv) && port != PORT_A)
5377 intel_attach_force_audio_property(connector);
5379 intel_attach_broadcast_rgb_property(connector);
5380 if (HAS_GMCH(dev_priv))
5381 drm_connector_attach_max_bpc_property(connector, 6, 10);
5382 else if (DISPLAY_VER(dev_priv) >= 5)
5383 drm_connector_attach_max_bpc_property(connector, 6, 12);
5385 /* Register HDMI colorspace for case of lspcon */
5386 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5387 drm_connector_attach_content_type_property(connector);
5388 intel_attach_hdmi_colorspace_property(connector);
5390 intel_attach_dp_colorspace_property(connector);
5393 if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5394 drm_connector_attach_hdr_output_metadata_property(connector);
5396 if (HAS_VRR(dev_priv))
5397 drm_connector_attach_vrr_capable_property(connector);
5401 intel_edp_add_properties(struct intel_dp *intel_dp)
5403 struct intel_connector *connector = intel_dp->attached_connector;
5404 struct drm_i915_private *i915 = to_i915(connector->base.dev);
5405 const struct drm_display_mode *fixed_mode =
5406 intel_panel_preferred_fixed_mode(connector);
5408 intel_attach_scaling_mode_property(&connector->base);
5410 drm_connector_set_panel_orientation_with_quirk(&connector->base,
5411 i915->display.vbt.orientation,
5412 fixed_mode->hdisplay,
5413 fixed_mode->vdisplay);
5416 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5417 struct intel_connector *connector)
5419 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5420 enum pipe pipe = INVALID_PIPE;
5422 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5424 * Figure out the current pipe for the initial backlight setup.
5425 * If the current pipe isn't valid, try the PPS pipe, and if that
5426 * fails just assume pipe A.
5428 pipe = vlv_active_pipe(intel_dp);
5430 if (pipe != PIPE_A && pipe != PIPE_B)
5431 pipe = intel_dp->pps.pps_pipe;
5433 if (pipe != PIPE_A && pipe != PIPE_B)
5437 intel_backlight_setup(connector, pipe);
5440 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5441 struct intel_connector *intel_connector)
5443 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5444 struct drm_connector *connector = &intel_connector->base;
5445 struct drm_display_mode *fixed_mode;
5446 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5448 const struct drm_edid *drm_edid;
5450 if (!intel_dp_is_edp(intel_dp))
5454 * On IBX/CPT we may get here with LVDS already registered. Since the
5455 * driver uses the only internal power sequencer available for both
5456 * eDP and LVDS bail out early in this case to prevent interfering
5457 * with an already powered-on LVDS power sequencer.
5459 if (intel_get_lvds_encoder(dev_priv)) {
5460 drm_WARN_ON(&dev_priv->drm,
5461 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5462 drm_info(&dev_priv->drm,
5463 "LVDS was detected, not registering eDP\n");
5468 intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5471 if (!intel_pps_init(intel_dp)) {
5472 drm_info(&dev_priv->drm,
5473 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
5474 encoder->base.base.id, encoder->base.name);
5476 * The BIOS may have still enabled VDD on the PPS even
5477 * though it's unusable. Make sure we turn it back off
5478 * and to release the power domain references/etc.
5484 * Enable HPD sense for live status check.
5485 * intel_hpd_irq_setup() will turn it off again
5486 * if it's no longer needed later.
5488 * The DPCD probe below will make sure VDD is on.
5490 intel_hpd_enable_detection(encoder);
5492 /* Cache DPCD and EDID for edp. */
5493 has_dpcd = intel_edp_init_dpcd(intel_dp);
5496 /* if this fails, presume the device is a ghost */
5497 drm_info(&dev_priv->drm,
5498 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5499 encoder->base.base.id, encoder->base.name);
5504 * VBT and straps are liars. Also check HPD as that seems
5505 * to be the most reliable piece of information available.
5507 if (!intel_digital_port_connected(encoder)) {
5509 * If this fails, presume the DPCD answer came
5510 * from some other port using the same AUX CH.
5512 * FIXME maybe cleaner to check this before the
5513 * DPCD read? Would need sort out the VDD handling...
5515 drm_info(&dev_priv->drm,
5516 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
5517 encoder->base.base.id, encoder->base.name);
5521 mutex_lock(&dev_priv->drm.mode_config.mutex);
5522 drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
5524 /* Fallback to EDID from ACPI OpRegion, if any */
5525 drm_edid = intel_opregion_get_edid(intel_connector);
5527 drm_dbg_kms(&dev_priv->drm,
5528 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5529 connector->base.id, connector->name);
5532 if (drm_edid_connector_update(connector, drm_edid) ||
5533 !drm_edid_connector_add_modes(connector)) {
5534 drm_edid_connector_update(connector, NULL);
5535 drm_edid_free(drm_edid);
5536 drm_edid = ERR_PTR(-EINVAL);
5539 drm_edid = ERR_PTR(-ENOENT);
5542 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
5543 IS_ERR(drm_edid) ? NULL : drm_edid);
5545 intel_panel_add_edid_fixed_modes(intel_connector, true);
5547 /* MSO requires information from the EDID */
5548 intel_edp_mso_init(intel_dp);
5550 /* multiply the mode clock and horizontal timings for MSO */
5551 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5552 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5554 /* fallback to VBT if available for eDP */
5555 if (!intel_panel_preferred_fixed_mode(intel_connector))
5556 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5558 mutex_unlock(&dev_priv->drm.mode_config.mutex);
5560 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5561 drm_info(&dev_priv->drm,
5562 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5563 encoder->base.base.id, encoder->base.name);
5567 intel_panel_init(intel_connector, drm_edid);
5569 intel_edp_backlight_setup(intel_dp, intel_connector);
5571 intel_edp_add_properties(intel_dp);
5573 intel_pps_init_late(intel_dp);
5578 intel_pps_vdd_off_sync(intel_dp);
5583 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5585 struct intel_connector *intel_connector;
5586 struct drm_connector *connector;
5588 intel_connector = container_of(work, typeof(*intel_connector),
5589 modeset_retry_work);
5590 connector = &intel_connector->base;
5591 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5594 /* Grab the locks before changing connector property*/
5595 mutex_lock(&connector->dev->mode_config.mutex);
5596 /* Set connector link status to BAD and send a Uevent to notify
5597 * userspace to do a modeset.
5599 drm_connector_set_link_status_property(connector,
5600 DRM_MODE_LINK_STATUS_BAD);
5601 mutex_unlock(&connector->dev->mode_config.mutex);
5602 /* Send Hotplug uevent so userspace can reprobe */
5603 drm_kms_helper_connector_hotplug_event(connector);
5607 intel_dp_init_connector(struct intel_digital_port *dig_port,
5608 struct intel_connector *intel_connector)
5610 struct drm_connector *connector = &intel_connector->base;
5611 struct intel_dp *intel_dp = &dig_port->dp;
5612 struct intel_encoder *intel_encoder = &dig_port->base;
5613 struct drm_device *dev = intel_encoder->base.dev;
5614 struct drm_i915_private *dev_priv = to_i915(dev);
5615 enum port port = intel_encoder->port;
5616 enum phy phy = intel_port_to_phy(dev_priv, port);
5619 /* Initialize the work for modeset in case of link train failure */
5620 INIT_WORK(&intel_connector->modeset_retry_work,
5621 intel_dp_modeset_retry_work_fn);
5623 if (drm_WARN(dev, dig_port->max_lanes < 1,
5624 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5625 dig_port->max_lanes, intel_encoder->base.base.id,
5626 intel_encoder->base.name))
5629 intel_dp->reset_link_params = true;
5630 intel_dp->pps.pps_pipe = INVALID_PIPE;
5631 intel_dp->pps.active_pipe = INVALID_PIPE;
5633 /* Preserve the current hw state. */
5634 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5635 intel_dp->attached_connector = intel_connector;
5637 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
5639 * Currently we don't support eDP on TypeC ports, although in
5640 * theory it could work on TypeC legacy ports.
5642 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5643 type = DRM_MODE_CONNECTOR_eDP;
5644 intel_encoder->type = INTEL_OUTPUT_EDP;
5646 /* eDP only on port B and/or C on vlv/chv */
5647 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5648 IS_CHERRYVIEW(dev_priv)) &&
5649 port != PORT_B && port != PORT_C))
5652 type = DRM_MODE_CONNECTOR_DisplayPort;
5655 intel_dp_set_default_sink_rates(intel_dp);
5656 intel_dp_set_default_max_sink_lane_count(intel_dp);
5658 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5659 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5661 drm_dbg_kms(&dev_priv->drm,
5662 "Adding %s connector on [ENCODER:%d:%s]\n",
5663 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5664 intel_encoder->base.base.id, intel_encoder->base.name);
5666 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5667 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5669 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
5670 connector->interlace_allowed = true;
5672 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5674 intel_dp_aux_init(intel_dp);
5676 intel_connector_attach_encoder(intel_connector, intel_encoder);
5678 if (HAS_DDI(dev_priv))
5679 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5681 intel_connector->get_hw_state = intel_connector_get_hw_state;
5683 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5684 intel_dp_aux_fini(intel_dp);
5688 intel_dp_set_source_rates(intel_dp);
5689 intel_dp_set_common_rates(intel_dp);
5690 intel_dp_reset_max_link_params(intel_dp);
5692 /* init MST on ports that can support it */
5693 intel_dp_mst_encoder_init(dig_port,
5694 intel_connector->base.base.id);
5696 intel_dp_add_properties(intel_dp, connector);
5698 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5699 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5701 drm_dbg_kms(&dev_priv->drm,
5702 "HDCP init failed, skipping.\n");
5705 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5706 * 0xd. Failure to do so will result in spurious interrupts being
5707 * generated on the port when a cable is not attached.
5709 if (IS_G45(dev_priv)) {
5710 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5711 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5712 (temp & ~0xf) | 0xd);
5715 intel_dp->frl.is_trained = false;
5716 intel_dp->frl.trained_rate_gbps = 0;
5718 intel_psr_init(intel_dp);
5723 intel_display_power_flush_work(dev_priv);
5724 drm_connector_cleanup(connector);
5729 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5731 struct intel_encoder *encoder;
5733 if (!HAS_DISPLAY(dev_priv))
5736 for_each_intel_encoder(&dev_priv->drm, encoder) {
5737 struct intel_dp *intel_dp;
5739 if (encoder->type != INTEL_OUTPUT_DDI)
5742 intel_dp = enc_to_intel_dp(encoder);
5744 if (!intel_dp_mst_source_support(intel_dp))
5747 if (intel_dp->is_mst)
5748 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5752 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5754 struct intel_encoder *encoder;
5756 if (!HAS_DISPLAY(dev_priv))
5759 for_each_intel_encoder(&dev_priv->drm, encoder) {
5760 struct intel_dp *intel_dp;
5763 if (encoder->type != INTEL_OUTPUT_DDI)
5766 intel_dp = enc_to_intel_dp(encoder);
5768 if (!intel_dp_mst_source_support(intel_dp))
5771 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5774 intel_dp->is_mst = false;
5775 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,