2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include <drm/drm_probe_helper.h>
44 #include "i915_debugfs.h"
46 #include "i915_trace.h"
47 #include "intel_atomic.h"
48 #include "intel_audio.h"
49 #include "intel_connector.h"
50 #include "intel_ddi.h"
51 #include "intel_display_types.h"
53 #include "intel_dp_link_training.h"
54 #include "intel_dp_mst.h"
55 #include "intel_dpio_phy.h"
56 #include "intel_fifo_underrun.h"
57 #include "intel_hdcp.h"
58 #include "intel_hdmi.h"
59 #include "intel_hotplug.h"
60 #include "intel_lspcon.h"
61 #include "intel_lvds.h"
62 #include "intel_panel.h"
63 #include "intel_psr.h"
64 #include "intel_sideband.h"
66 #include "intel_vdsc.h"
68 #define DP_DPRX_ESI_LEN 14
70 /* DP DSC throughput values used for slice count calculations KPixels/s */
71 #define DP_DSC_PEAK_PIXEL_RATE 2720000
72 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
73 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
75 /* DP DSC FEC Overhead factor = 1/(0.972261) */
76 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
78 /* Compliance test status bits */
79 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
80 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
81 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
82 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
89 static const struct dp_link_dpll g4x_dpll[] = {
91 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
93 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
96 static const struct dp_link_dpll pch_dpll[] = {
98 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
100 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
103 static const struct dp_link_dpll vlv_dpll[] = {
105 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
107 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
111 * CHV supports eDP 1.4 that have more link rates.
112 * Below only provides the fixed rate but exclude variable rate.
114 static const struct dp_link_dpll chv_dpll[] = {
116 * CHV requires to program fractional division for m2.
117 * m2 is stored in fixed point format using formula below
118 * (m2_int << 22) | m2_fraction
120 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
121 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
122 { 270000, /* m2_int = 27, m2_fraction = 0 */
123 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
126 /* Constants for DP DSC configurations */
127 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
129 /* With Single pipe configuration, HW is capable of supporting maximum
130 * of 4 slices per line.
132 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
135 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
136 * @intel_dp: DP struct
138 * If a CPU or PCH DP output is attached to an eDP panel, this function
139 * will return true, and false otherwise.
141 bool intel_dp_is_edp(struct intel_dp *intel_dp)
143 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
148 static void intel_dp_link_down(struct intel_encoder *encoder,
149 const struct intel_crtc_state *old_crtc_state);
150 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
151 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
152 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
153 const struct intel_crtc_state *crtc_state);
154 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
158 /* update sink rates from dpcd */
159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
161 static const int dp_rates[] = {
162 162000, 270000, 540000, 810000
166 if (drm_dp_has_quirk(&intel_dp->desc, 0,
167 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
168 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
169 static const int quirk_rates[] = { 162000, 270000, 324000 };
171 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
172 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
179 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
180 if (dp_rates[i] > max_rate)
182 intel_dp->sink_rates[i] = dp_rates[i];
185 intel_dp->num_sink_rates = i;
188 /* Get length of rates array potentially limited by max_rate. */
189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
193 /* Limit results by potentially reduced max rate */
194 for (i = 0; i < len; i++) {
195 if (rates[len - i - 1] <= max_rate)
202 /* Get length of common rates array potentially limited by max_rate. */
203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
206 return intel_dp_rate_limit_len(intel_dp->common_rates,
207 intel_dp->num_common_rates, max_rate);
210 /* Theoretical max between source and sink */
211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
213 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
216 /* Theoretical max between source and sink */
217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
220 int source_max = intel_dig_port->max_lanes;
221 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
222 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
224 return min3(source_max, sink_max, fia_max);
227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
229 return intel_dp->max_link_lane_count;
233 intel_dp_link_required(int pixel_clock, int bpp)
235 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
236 return DIV_ROUND_UP(pixel_clock * bpp, 8);
240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
242 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
243 * link rate that is generally expressed in Gbps. Since, 8 bits of data
244 * is transmitted every LS_Clk per lane, there is no need to account for
245 * the channel encoding that is done in the PHY layer here.
248 return max_link_clock * max_lanes;
252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
255 struct intel_encoder *encoder = &intel_dig_port->base;
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
257 int max_dotclk = dev_priv->max_dotclk_freq;
260 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
262 if (type != DP_DS_PORT_TYPE_VGA)
265 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
266 intel_dp->downstream_ports);
268 if (ds_max_dotclk != 0)
269 max_dotclk = min(max_dotclk, ds_max_dotclk);
274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
276 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
277 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
278 enum port port = dig_port->base.port;
280 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
282 /* Low voltage SKUs are limited to max of 5.4G */
283 if (voltage == VOLTAGE_INFO_0_85V)
286 /* For this SKU 8.1G is supported in all ports */
287 if (IS_CNL_WITH_PORT_F(dev_priv))
290 /* For other SKUs, max rate on ports A and D is 5.4G */
291 if (port == PORT_A || port == PORT_D)
297 static int icl_max_source_rate(struct intel_dp *intel_dp)
299 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
300 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
301 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
303 if (intel_phy_is_combo(dev_priv, phy) &&
304 !IS_ELKHARTLAKE(dev_priv) &&
305 !intel_dp_is_edp(intel_dp))
312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
314 /* The values must be in increasing order */
315 static const int cnl_rates[] = {
316 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
318 static const int bxt_rates[] = {
319 162000, 216000, 243000, 270000, 324000, 432000, 540000
321 static const int skl_rates[] = {
322 162000, 216000, 270000, 324000, 432000, 540000
324 static const int hsw_rates[] = {
325 162000, 270000, 540000
327 static const int g4x_rates[] = {
330 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
331 struct intel_encoder *encoder = &dig_port->base;
332 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
333 const int *source_rates;
334 int size, max_rate = 0, vbt_max_rate;
336 /* This should only be done once */
337 drm_WARN_ON(&dev_priv->drm,
338 intel_dp->source_rates || intel_dp->num_source_rates);
340 if (INTEL_GEN(dev_priv) >= 10) {
341 source_rates = cnl_rates;
342 size = ARRAY_SIZE(cnl_rates);
343 if (IS_GEN(dev_priv, 10))
344 max_rate = cnl_max_source_rate(intel_dp);
346 max_rate = icl_max_source_rate(intel_dp);
347 } else if (IS_GEN9_LP(dev_priv)) {
348 source_rates = bxt_rates;
349 size = ARRAY_SIZE(bxt_rates);
350 } else if (IS_GEN9_BC(dev_priv)) {
351 source_rates = skl_rates;
352 size = ARRAY_SIZE(skl_rates);
353 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
354 IS_BROADWELL(dev_priv)) {
355 source_rates = hsw_rates;
356 size = ARRAY_SIZE(hsw_rates);
358 source_rates = g4x_rates;
359 size = ARRAY_SIZE(g4x_rates);
362 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
363 if (max_rate && vbt_max_rate)
364 max_rate = min(max_rate, vbt_max_rate);
365 else if (vbt_max_rate)
366 max_rate = vbt_max_rate;
369 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
371 intel_dp->source_rates = source_rates;
372 intel_dp->num_source_rates = size;
375 static int intersect_rates(const int *source_rates, int source_len,
376 const int *sink_rates, int sink_len,
379 int i = 0, j = 0, k = 0;
381 while (i < source_len && j < sink_len) {
382 if (source_rates[i] == sink_rates[j]) {
383 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
385 common_rates[k] = source_rates[i];
389 } else if (source_rates[i] < sink_rates[j]) {
398 /* return index of rate in rates array, or -1 if not found */
399 static int intel_dp_rate_index(const int *rates, int len, int rate)
403 for (i = 0; i < len; i++)
404 if (rate == rates[i])
410 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
412 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
414 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
415 intel_dp->num_source_rates,
416 intel_dp->sink_rates,
417 intel_dp->num_sink_rates,
418 intel_dp->common_rates);
420 /* Paranoia, there should always be something in common. */
421 if (WARN_ON(intel_dp->num_common_rates == 0)) {
422 intel_dp->common_rates[0] = 162000;
423 intel_dp->num_common_rates = 1;
427 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
431 * FIXME: we need to synchronize the current link parameters with
432 * hardware readout. Currently fast link training doesn't work on
435 if (link_rate == 0 ||
436 link_rate > intel_dp->max_link_rate)
439 if (lane_count == 0 ||
440 lane_count > intel_dp_max_lane_count(intel_dp))
446 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
450 const struct drm_display_mode *fixed_mode =
451 intel_dp->attached_connector->panel.fixed_mode;
452 int mode_rate, max_rate;
454 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
455 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
456 if (mode_rate > max_rate)
462 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
463 int link_rate, u8 lane_count)
465 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
468 index = intel_dp_rate_index(intel_dp->common_rates,
469 intel_dp->num_common_rates,
472 if (intel_dp_is_edp(intel_dp) &&
473 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
474 intel_dp->common_rates[index - 1],
476 drm_dbg_kms(&i915->drm,
477 "Retrying Link training for eDP with same parameters\n");
480 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
481 intel_dp->max_link_lane_count = lane_count;
482 } else if (lane_count > 1) {
483 if (intel_dp_is_edp(intel_dp) &&
484 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
485 intel_dp_max_common_rate(intel_dp),
487 drm_dbg_kms(&i915->drm,
488 "Retrying Link training for eDP with same parameters\n");
491 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
492 intel_dp->max_link_lane_count = lane_count >> 1;
494 drm_err(&i915->drm, "Link Training Unsuccessful\n");
501 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
503 return div_u64(mul_u32_u32(mode_clock, 1000000U),
504 DP_DSC_FEC_OVERHEAD_FACTOR);
508 small_joiner_ram_size_bits(struct drm_i915_private *i915)
510 if (INTEL_GEN(i915) >= 11)
516 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
517 u32 link_clock, u32 lane_count,
518 u32 mode_clock, u32 mode_hdisplay)
520 u32 bits_per_pixel, max_bpp_small_joiner_ram;
524 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
525 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
526 * for SST -> TimeSlotsPerMTP is 1,
527 * for MST -> TimeSlotsPerMTP has to be calculated
529 bits_per_pixel = (link_clock * lane_count * 8) /
530 intel_dp_mode_to_fec_clock(mode_clock);
531 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
533 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
534 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
536 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
537 max_bpp_small_joiner_ram);
540 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
541 * check, output bpp from small joiner RAM check)
543 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
545 /* Error out if the max bpp is less than smallest allowed valid bpp */
546 if (bits_per_pixel < valid_dsc_bpp[0]) {
547 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
548 bits_per_pixel, valid_dsc_bpp[0]);
552 /* Find the nearest match in the array of known BPPs from VESA */
553 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
554 if (bits_per_pixel < valid_dsc_bpp[i + 1])
557 bits_per_pixel = valid_dsc_bpp[i];
560 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
561 * fractional part is 0
563 return bits_per_pixel << 4;
566 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
567 int mode_clock, int mode_hdisplay)
569 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
570 u8 min_slice_count, i;
573 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
574 min_slice_count = DIV_ROUND_UP(mode_clock,
575 DP_DSC_MAX_ENC_THROUGHPUT_0);
577 min_slice_count = DIV_ROUND_UP(mode_clock,
578 DP_DSC_MAX_ENC_THROUGHPUT_1);
580 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
581 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
582 drm_dbg_kms(&i915->drm,
583 "Unsupported slice width %d by DP DSC Sink device\n",
587 /* Also take into account max slice width */
588 min_slice_count = min_t(u8, min_slice_count,
589 DIV_ROUND_UP(mode_hdisplay,
592 /* Find the closest match to the valid slice count values */
593 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
594 if (valid_dsc_slicecount[i] >
595 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
598 if (min_slice_count <= valid_dsc_slicecount[i])
599 return valid_dsc_slicecount[i];
602 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
607 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
611 * Older platforms don't like hdisplay==4096 with DP.
613 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
614 * and frame counter increment), but we don't get vblank interrupts,
615 * and the pipe underruns immediately. The link also doesn't seem
616 * to get trained properly.
618 * On CHV the vblank interrupts don't seem to disappear but
619 * otherwise the symptoms are similar.
621 * TODO: confirm the behaviour on HSW+
623 return hdisplay == 4096 && !HAS_DDI(dev_priv);
626 static enum drm_mode_status
627 intel_dp_mode_valid(struct drm_connector *connector,
628 struct drm_display_mode *mode)
630 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
631 struct intel_connector *intel_connector = to_intel_connector(connector);
632 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
633 struct drm_i915_private *dev_priv = to_i915(connector->dev);
634 int target_clock = mode->clock;
635 int max_rate, mode_rate, max_lanes, max_link_clock;
637 u16 dsc_max_output_bpp = 0;
638 u8 dsc_slice_count = 0;
640 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
641 return MODE_NO_DBLESCAN;
643 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
645 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
646 if (mode->hdisplay > fixed_mode->hdisplay)
649 if (mode->vdisplay > fixed_mode->vdisplay)
652 target_clock = fixed_mode->clock;
655 max_link_clock = intel_dp_max_link_rate(intel_dp);
656 max_lanes = intel_dp_max_lane_count(intel_dp);
658 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
659 mode_rate = intel_dp_link_required(target_clock, 18);
661 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
662 return MODE_H_ILLEGAL;
665 * Output bpp is stored in 6.4 format so right shift by 4 to get the
666 * integer value since we support only integer values of bpp.
668 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
669 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
670 if (intel_dp_is_edp(intel_dp)) {
672 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
674 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
676 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
678 intel_dp_dsc_get_output_bpp(dev_priv,
682 mode->hdisplay) >> 4;
684 intel_dp_dsc_get_slice_count(intel_dp,
690 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
691 target_clock > max_dotclk)
692 return MODE_CLOCK_HIGH;
694 if (mode->clock < 10000)
695 return MODE_CLOCK_LOW;
697 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
698 return MODE_H_ILLEGAL;
700 return intel_mode_valid_max_plane_size(dev_priv, mode);
703 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
710 for (i = 0; i < src_bytes; i++)
711 v |= ((u32)src[i]) << ((3 - i) * 8);
715 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
720 for (i = 0; i < dst_bytes; i++)
721 dst[i] = src >> ((3-i) * 8);
725 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
727 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
728 bool force_disable_vdd);
730 intel_dp_pps_init(struct intel_dp *intel_dp);
732 static intel_wakeref_t
733 pps_lock(struct intel_dp *intel_dp)
735 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
736 intel_wakeref_t wakeref;
739 * See intel_power_sequencer_reset() why we need
740 * a power domain reference here.
742 wakeref = intel_display_power_get(dev_priv,
743 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
745 mutex_lock(&dev_priv->pps_mutex);
750 static intel_wakeref_t
751 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
755 mutex_unlock(&dev_priv->pps_mutex);
756 intel_display_power_put(dev_priv,
757 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
762 #define with_pps_lock(dp, wf) \
763 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
766 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
768 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
769 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
770 enum pipe pipe = intel_dp->pps_pipe;
771 bool pll_enabled, release_cl_override = false;
772 enum dpio_phy phy = DPIO_PHY(pipe);
773 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
776 if (drm_WARN(&dev_priv->drm,
777 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
778 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
779 pipe_name(pipe), intel_dig_port->base.base.base.id,
780 intel_dig_port->base.base.name))
783 drm_dbg_kms(&dev_priv->drm,
784 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
785 pipe_name(pipe), intel_dig_port->base.base.base.id,
786 intel_dig_port->base.base.name);
788 /* Preserve the BIOS-computed detected bit. This is
789 * supposed to be read-only.
791 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
792 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
793 DP |= DP_PORT_WIDTH(1);
794 DP |= DP_LINK_TRAIN_PAT_1;
796 if (IS_CHERRYVIEW(dev_priv))
797 DP |= DP_PIPE_SEL_CHV(pipe);
799 DP |= DP_PIPE_SEL(pipe);
801 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
804 * The DPLL for the pipe must be enabled for this to work.
805 * So enable temporarily it if it's not already enabled.
808 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
809 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
811 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
812 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
813 drm_err(&dev_priv->drm,
814 "Failed to force on pll for pipe %c!\n",
821 * Similar magic as in intel_dp_enable_port().
822 * We _must_ do this port enable + disable trick
823 * to make this power sequencer lock onto the port.
824 * Otherwise even VDD force bit won't work.
826 intel_de_write(dev_priv, intel_dp->output_reg, DP);
827 intel_de_posting_read(dev_priv, intel_dp->output_reg);
829 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
830 intel_de_posting_read(dev_priv, intel_dp->output_reg);
832 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
833 intel_de_posting_read(dev_priv, intel_dp->output_reg);
836 vlv_force_pll_off(dev_priv, pipe);
838 if (release_cl_override)
839 chv_phy_powergate_ch(dev_priv, phy, ch, false);
843 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
845 struct intel_encoder *encoder;
846 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
849 * We don't have power sequencer currently.
850 * Pick one that's not used by other ports.
852 for_each_intel_dp(&dev_priv->drm, encoder) {
853 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
855 if (encoder->type == INTEL_OUTPUT_EDP) {
856 drm_WARN_ON(&dev_priv->drm,
857 intel_dp->active_pipe != INVALID_PIPE &&
858 intel_dp->active_pipe !=
861 if (intel_dp->pps_pipe != INVALID_PIPE)
862 pipes &= ~(1 << intel_dp->pps_pipe);
864 drm_WARN_ON(&dev_priv->drm,
865 intel_dp->pps_pipe != INVALID_PIPE);
867 if (intel_dp->active_pipe != INVALID_PIPE)
868 pipes &= ~(1 << intel_dp->active_pipe);
875 return ffs(pipes) - 1;
879 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
881 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
882 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
885 lockdep_assert_held(&dev_priv->pps_mutex);
887 /* We should never land here with regular DP ports */
888 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
890 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
891 intel_dp->active_pipe != intel_dp->pps_pipe);
893 if (intel_dp->pps_pipe != INVALID_PIPE)
894 return intel_dp->pps_pipe;
896 pipe = vlv_find_free_pps(dev_priv);
899 * Didn't find one. This should not happen since there
900 * are two power sequencers and up to two eDP ports.
902 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
905 vlv_steal_power_sequencer(dev_priv, pipe);
906 intel_dp->pps_pipe = pipe;
908 drm_dbg_kms(&dev_priv->drm,
909 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
910 pipe_name(intel_dp->pps_pipe),
911 intel_dig_port->base.base.base.id,
912 intel_dig_port->base.base.name);
914 /* init power sequencer on this pipe and port */
915 intel_dp_init_panel_power_sequencer(intel_dp);
916 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
919 * Even vdd force doesn't work until we've made
920 * the power sequencer lock in on the port.
922 vlv_power_sequencer_kick(intel_dp);
924 return intel_dp->pps_pipe;
928 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
930 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
931 int backlight_controller = dev_priv->vbt.backlight.controller;
933 lockdep_assert_held(&dev_priv->pps_mutex);
935 /* We should never land here with regular DP ports */
936 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
938 if (!intel_dp->pps_reset)
939 return backlight_controller;
941 intel_dp->pps_reset = false;
944 * Only the HW needs to be reprogrammed, the SW state is fixed and
945 * has been setup during connector init.
947 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
949 return backlight_controller;
952 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
955 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
958 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
961 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
964 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
967 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
974 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
976 vlv_pipe_check pipe_check)
980 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
981 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
982 PANEL_PORT_SELECT_MASK;
984 if (port_sel != PANEL_PORT_SELECT_VLV(port))
987 if (!pipe_check(dev_priv, pipe))
997 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
999 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1000 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1001 enum port port = intel_dig_port->base.port;
1003 lockdep_assert_held(&dev_priv->pps_mutex);
1005 /* try to find a pipe with this port selected */
1006 /* first pick one where the panel is on */
1007 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1008 vlv_pipe_has_pp_on);
1009 /* didn't find one? pick one where vdd is on */
1010 if (intel_dp->pps_pipe == INVALID_PIPE)
1011 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1012 vlv_pipe_has_vdd_on);
1013 /* didn't find one? pick one with just the correct port */
1014 if (intel_dp->pps_pipe == INVALID_PIPE)
1015 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1018 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1019 if (intel_dp->pps_pipe == INVALID_PIPE) {
1020 drm_dbg_kms(&dev_priv->drm,
1021 "no initial power sequencer for [ENCODER:%d:%s]\n",
1022 intel_dig_port->base.base.base.id,
1023 intel_dig_port->base.base.name);
1027 drm_dbg_kms(&dev_priv->drm,
1028 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1029 intel_dig_port->base.base.base.id,
1030 intel_dig_port->base.base.name,
1031 pipe_name(intel_dp->pps_pipe));
1033 intel_dp_init_panel_power_sequencer(intel_dp);
1034 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1037 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1039 struct intel_encoder *encoder;
1041 if (drm_WARN_ON(&dev_priv->drm,
1042 !(IS_VALLEYVIEW(dev_priv) ||
1043 IS_CHERRYVIEW(dev_priv) ||
1044 IS_GEN9_LP(dev_priv))))
1048 * We can't grab pps_mutex here due to deadlock with power_domain
1049 * mutex when power_domain functions are called while holding pps_mutex.
1050 * That also means that in order to use pps_pipe the code needs to
1051 * hold both a power domain reference and pps_mutex, and the power domain
1052 * reference get/put must be done while _not_ holding pps_mutex.
1053 * pps_{lock,unlock}() do these steps in the correct order, so one
1054 * should use them always.
1057 for_each_intel_dp(&dev_priv->drm, encoder) {
1058 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1060 drm_WARN_ON(&dev_priv->drm,
1061 intel_dp->active_pipe != INVALID_PIPE);
1063 if (encoder->type != INTEL_OUTPUT_EDP)
1066 if (IS_GEN9_LP(dev_priv))
1067 intel_dp->pps_reset = true;
1069 intel_dp->pps_pipe = INVALID_PIPE;
1073 struct pps_registers {
1081 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1082 struct pps_registers *regs)
1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1087 memset(regs, 0, sizeof(*regs));
1089 if (IS_GEN9_LP(dev_priv))
1090 pps_idx = bxt_power_sequencer_idx(intel_dp);
1091 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1092 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1094 regs->pp_ctrl = PP_CONTROL(pps_idx);
1095 regs->pp_stat = PP_STATUS(pps_idx);
1096 regs->pp_on = PP_ON_DELAYS(pps_idx);
1097 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1099 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1100 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1101 regs->pp_div = INVALID_MMIO_REG;
1103 regs->pp_div = PP_DIVISOR(pps_idx);
1107 _pp_ctrl_reg(struct intel_dp *intel_dp)
1109 struct pps_registers regs;
1111 intel_pps_get_registers(intel_dp, ®s);
1113 return regs.pp_ctrl;
1117 _pp_stat_reg(struct intel_dp *intel_dp)
1119 struct pps_registers regs;
1121 intel_pps_get_registers(intel_dp, ®s);
1123 return regs.pp_stat;
1126 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1127 This function only applicable when panel PM state is not to be tracked */
1128 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1131 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1133 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1134 intel_wakeref_t wakeref;
1136 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1139 with_pps_lock(intel_dp, wakeref) {
1140 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1141 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1142 i915_reg_t pp_ctrl_reg, pp_div_reg;
1145 pp_ctrl_reg = PP_CONTROL(pipe);
1146 pp_div_reg = PP_DIVISOR(pipe);
1147 pp_div = intel_de_read(dev_priv, pp_div_reg);
1148 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1150 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1151 intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1152 intel_de_write(dev_priv, pp_ctrl_reg,
1154 msleep(intel_dp->panel_power_cycle_delay);
1161 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1163 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1165 lockdep_assert_held(&dev_priv->pps_mutex);
1167 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1168 intel_dp->pps_pipe == INVALID_PIPE)
1171 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1174 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1176 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1178 lockdep_assert_held(&dev_priv->pps_mutex);
1180 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1181 intel_dp->pps_pipe == INVALID_PIPE)
1184 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1188 intel_dp_check_edp(struct intel_dp *intel_dp)
1190 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1192 if (!intel_dp_is_edp(intel_dp))
1195 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1196 drm_WARN(&dev_priv->drm, 1,
1197 "eDP powered off while attempting aux channel communication.\n");
1198 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1199 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1200 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1205 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1207 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1209 const unsigned int timeout_ms = 10;
1213 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1214 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1215 msecs_to_jiffies_timeout(timeout_ms));
1217 /* just trace the final value */
1218 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1222 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1223 intel_dp->aux.name, timeout_ms, status);
1229 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1231 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237 * The clock divider is based off the hrawclk, and would like to run at
1238 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1240 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1243 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1245 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1246 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1253 * The clock divider is based off the cdclk or PCH rawclk, and would
1254 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1255 * divide by 2000 and use that
1257 if (dig_port->aux_ch == AUX_CH_A)
1258 freq = dev_priv->cdclk.hw.cdclk;
1260 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1261 return DIV_ROUND_CLOSEST(freq, 2000);
1264 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1266 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1267 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1269 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1270 /* Workaround for non-ULT HSW */
1278 return ilk_get_aux_clock_divider(intel_dp, index);
1281 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1284 * SKL doesn't need us to program the AUX clock divider (Hardware will
1285 * derive the clock from CDCLK automatically). We still implement the
1286 * get_aux_clock_divider vfunc to plug-in into the existing code.
1288 return index ? 0 : 1;
1291 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1293 u32 aux_clock_divider)
1295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296 struct drm_i915_private *dev_priv =
1297 to_i915(intel_dig_port->base.base.dev);
1298 u32 precharge, timeout;
1300 if (IS_GEN(dev_priv, 6))
1305 if (IS_BROADWELL(dev_priv))
1306 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1308 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1310 return DP_AUX_CH_CTL_SEND_BUSY |
1311 DP_AUX_CH_CTL_DONE |
1312 DP_AUX_CH_CTL_INTERRUPT |
1313 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1315 DP_AUX_CH_CTL_RECEIVE_ERROR |
1316 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1317 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1318 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1321 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1326 struct drm_i915_private *i915 =
1327 to_i915(intel_dig_port->base.base.dev);
1328 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1331 ret = DP_AUX_CH_CTL_SEND_BUSY |
1332 DP_AUX_CH_CTL_DONE |
1333 DP_AUX_CH_CTL_INTERRUPT |
1334 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1335 DP_AUX_CH_CTL_TIME_OUT_MAX |
1336 DP_AUX_CH_CTL_RECEIVE_ERROR |
1337 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1338 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1339 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1341 if (intel_phy_is_tc(i915, phy) &&
1342 intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1343 ret |= DP_AUX_CH_CTL_TBT_IO;
1349 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1350 const u8 *send, int send_bytes,
1351 u8 *recv, int recv_size,
1352 u32 aux_send_ctl_flags)
1354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355 struct drm_i915_private *i915 =
1356 to_i915(intel_dig_port->base.base.dev);
1357 struct intel_uncore *uncore = &i915->uncore;
1358 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1359 bool is_tc_port = intel_phy_is_tc(i915, phy);
1360 i915_reg_t ch_ctl, ch_data[5];
1361 u32 aux_clock_divider;
1362 enum intel_display_power_domain aux_domain =
1363 intel_aux_power_domain(intel_dig_port);
1364 intel_wakeref_t aux_wakeref;
1365 intel_wakeref_t pps_wakeref;
1366 int i, ret, recv_bytes;
1371 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1372 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1373 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1376 intel_tc_port_lock(intel_dig_port);
1378 aux_wakeref = intel_display_power_get(i915, aux_domain);
1379 pps_wakeref = pps_lock(intel_dp);
1382 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1383 * In such cases we want to leave VDD enabled and it's up to upper layers
1384 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1387 vdd = edp_panel_vdd_on(intel_dp);
1389 /* dp aux is extremely sensitive to irq latency, hence request the
1390 * lowest possible wakeup latency and so prevent the cpu from going into
1391 * deep sleep states.
1393 cpu_latency_qos_update_request(&i915->pm_qos, 0);
1395 intel_dp_check_edp(intel_dp);
1397 /* Try to wait for any previous AUX channel activity */
1398 for (try = 0; try < 3; try++) {
1399 status = intel_uncore_read_notrace(uncore, ch_ctl);
1400 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1404 /* just trace the final value */
1405 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1408 const u32 status = intel_uncore_read(uncore, ch_ctl);
1410 if (status != intel_dp->aux_busy_last_status) {
1411 drm_WARN(&i915->drm, 1,
1412 "%s: not started (status 0x%08x)\n",
1413 intel_dp->aux.name, status);
1414 intel_dp->aux_busy_last_status = status;
1421 /* Only 5 data registers! */
1422 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1427 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1428 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1432 send_ctl |= aux_send_ctl_flags;
1434 /* Must try at least 3 times according to DP spec */
1435 for (try = 0; try < 5; try++) {
1436 /* Load the send data into the aux channel data registers */
1437 for (i = 0; i < send_bytes; i += 4)
1438 intel_uncore_write(uncore,
1440 intel_dp_pack_aux(send + i,
1443 /* Send the command and wait for it to complete */
1444 intel_uncore_write(uncore, ch_ctl, send_ctl);
1446 status = intel_dp_aux_wait_done(intel_dp);
1448 /* Clear done status and any errors */
1449 intel_uncore_write(uncore,
1452 DP_AUX_CH_CTL_DONE |
1453 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1454 DP_AUX_CH_CTL_RECEIVE_ERROR);
1456 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1457 * 400us delay required for errors and timeouts
1458 * Timeout errors from the HW already meet this
1459 * requirement so skip to next iteration
1461 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1464 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1465 usleep_range(400, 500);
1468 if (status & DP_AUX_CH_CTL_DONE)
1473 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1474 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1475 intel_dp->aux.name, status);
1481 /* Check for timeout or receive error.
1482 * Timeouts occur when the sink is not connected
1484 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1485 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1486 intel_dp->aux.name, status);
1491 /* Timeouts occur when the device isn't connected, so they're
1492 * "normal" -- don't fill the kernel log with these */
1493 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1494 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1495 intel_dp->aux.name, status);
1500 /* Unload any bytes sent back from the other side */
1501 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1502 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1505 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1506 * We have no idea of what happened so we return -EBUSY so
1507 * drm layer takes care for the necessary retries.
1509 if (recv_bytes == 0 || recv_bytes > 20) {
1510 drm_dbg_kms(&i915->drm,
1511 "%s: Forbidden recv_bytes = %d on aux transaction\n",
1512 intel_dp->aux.name, recv_bytes);
1517 if (recv_bytes > recv_size)
1518 recv_bytes = recv_size;
1520 for (i = 0; i < recv_bytes; i += 4)
1521 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1522 recv + i, recv_bytes - i);
1526 cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1529 edp_panel_vdd_off(intel_dp, false);
1531 pps_unlock(intel_dp, pps_wakeref);
1532 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1535 intel_tc_port_unlock(intel_dig_port);
1540 #define BARE_ADDRESS_SIZE 3
1541 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1544 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1545 const struct drm_dp_aux_msg *msg)
1547 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1548 txbuf[1] = (msg->address >> 8) & 0xff;
1549 txbuf[2] = msg->address & 0xff;
1550 txbuf[3] = msg->size - 1;
1554 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1556 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1557 u8 txbuf[20], rxbuf[20];
1558 size_t txsize, rxsize;
1561 intel_dp_aux_header(txbuf, msg);
1563 switch (msg->request & ~DP_AUX_I2C_MOT) {
1564 case DP_AUX_NATIVE_WRITE:
1565 case DP_AUX_I2C_WRITE:
1566 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1567 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1568 rxsize = 2; /* 0 or 1 data bytes */
1570 if (WARN_ON(txsize > 20))
1573 WARN_ON(!msg->buffer != !msg->size);
1576 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1578 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1581 msg->reply = rxbuf[0] >> 4;
1584 /* Number of bytes written in a short write. */
1585 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1587 /* Return payload size. */
1593 case DP_AUX_NATIVE_READ:
1594 case DP_AUX_I2C_READ:
1595 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1596 rxsize = msg->size + 1;
1598 if (WARN_ON(rxsize > 20))
1601 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1604 msg->reply = rxbuf[0] >> 4;
1606 * Assume happy day, and copy the data. The caller is
1607 * expected to check msg->reply before touching it.
1609 * Return payload size.
1612 memcpy(msg->buffer, rxbuf + 1, ret);
1625 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1627 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1628 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1629 enum aux_ch aux_ch = dig_port->aux_ch;
1635 return DP_AUX_CH_CTL(aux_ch);
1637 MISSING_CASE(aux_ch);
1638 return DP_AUX_CH_CTL(AUX_CH_B);
1642 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1644 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1645 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1646 enum aux_ch aux_ch = dig_port->aux_ch;
1652 return DP_AUX_CH_DATA(aux_ch, index);
1654 MISSING_CASE(aux_ch);
1655 return DP_AUX_CH_DATA(AUX_CH_B, index);
1659 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1661 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1662 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1663 enum aux_ch aux_ch = dig_port->aux_ch;
1667 return DP_AUX_CH_CTL(aux_ch);
1671 return PCH_DP_AUX_CH_CTL(aux_ch);
1673 MISSING_CASE(aux_ch);
1674 return DP_AUX_CH_CTL(AUX_CH_A);
1678 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1680 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1681 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1682 enum aux_ch aux_ch = dig_port->aux_ch;
1686 return DP_AUX_CH_DATA(aux_ch, index);
1690 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1692 MISSING_CASE(aux_ch);
1693 return DP_AUX_CH_DATA(AUX_CH_A, index);
1697 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1699 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1701 enum aux_ch aux_ch = dig_port->aux_ch;
1711 return DP_AUX_CH_CTL(aux_ch);
1713 MISSING_CASE(aux_ch);
1714 return DP_AUX_CH_CTL(AUX_CH_A);
1718 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1720 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1721 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1722 enum aux_ch aux_ch = dig_port->aux_ch;
1732 return DP_AUX_CH_DATA(aux_ch, index);
1734 MISSING_CASE(aux_ch);
1735 return DP_AUX_CH_DATA(AUX_CH_A, index);
1740 intel_dp_aux_fini(struct intel_dp *intel_dp)
1742 kfree(intel_dp->aux.name);
1746 intel_dp_aux_init(struct intel_dp *intel_dp)
1748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750 struct intel_encoder *encoder = &dig_port->base;
1752 if (INTEL_GEN(dev_priv) >= 9) {
1753 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1754 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1755 } else if (HAS_PCH_SPLIT(dev_priv)) {
1756 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1757 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1759 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1760 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1763 if (INTEL_GEN(dev_priv) >= 9)
1764 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1765 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1766 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1767 else if (HAS_PCH_SPLIT(dev_priv))
1768 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1770 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1772 if (INTEL_GEN(dev_priv) >= 9)
1773 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1775 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1777 drm_dp_aux_init(&intel_dp->aux);
1779 /* Failure to allocate our preferred name is not critical */
1780 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1781 aux_ch_name(dig_port->aux_ch),
1782 port_name(encoder->port));
1783 intel_dp->aux.transfer = intel_dp_aux_transfer;
1786 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1788 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1790 return max_rate >= 540000;
1793 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1795 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1797 return max_rate >= 810000;
1801 intel_dp_set_clock(struct intel_encoder *encoder,
1802 struct intel_crtc_state *pipe_config)
1804 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1805 const struct dp_link_dpll *divisor = NULL;
1808 if (IS_G4X(dev_priv)) {
1810 count = ARRAY_SIZE(g4x_dpll);
1811 } else if (HAS_PCH_SPLIT(dev_priv)) {
1813 count = ARRAY_SIZE(pch_dpll);
1814 } else if (IS_CHERRYVIEW(dev_priv)) {
1816 count = ARRAY_SIZE(chv_dpll);
1817 } else if (IS_VALLEYVIEW(dev_priv)) {
1819 count = ARRAY_SIZE(vlv_dpll);
1822 if (divisor && count) {
1823 for (i = 0; i < count; i++) {
1824 if (pipe_config->port_clock == divisor[i].clock) {
1825 pipe_config->dpll = divisor[i].dpll;
1826 pipe_config->clock_set = true;
1833 static void snprintf_int_array(char *str, size_t len,
1834 const int *array, int nelem)
1840 for (i = 0; i < nelem; i++) {
1841 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1849 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1851 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1852 char str[128]; /* FIXME: too big for stack? */
1854 if (!drm_debug_enabled(DRM_UT_KMS))
1857 snprintf_int_array(str, sizeof(str),
1858 intel_dp->source_rates, intel_dp->num_source_rates);
1859 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1861 snprintf_int_array(str, sizeof(str),
1862 intel_dp->sink_rates, intel_dp->num_sink_rates);
1863 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1865 snprintf_int_array(str, sizeof(str),
1866 intel_dp->common_rates, intel_dp->num_common_rates);
1867 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1871 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1875 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1876 if (WARN_ON(len <= 0))
1879 return intel_dp->common_rates[len - 1];
1882 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1884 int i = intel_dp_rate_index(intel_dp->sink_rates,
1885 intel_dp->num_sink_rates, rate);
1893 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1894 u8 *link_bw, u8 *rate_select)
1896 /* eDP 1.4 rate select method. */
1897 if (intel_dp->use_rate_select) {
1900 intel_dp_rate_select(intel_dp, port_clock);
1902 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1907 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1908 const struct intel_crtc_state *pipe_config)
1910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1912 /* On TGL, FEC is supported on all Pipes */
1913 if (INTEL_GEN(dev_priv) >= 12)
1916 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1922 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1923 const struct intel_crtc_state *pipe_config)
1925 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1926 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1929 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1930 const struct intel_crtc_state *crtc_state)
1932 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1934 if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1937 return intel_dsc_source_support(encoder, crtc_state) &&
1938 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1941 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1942 struct intel_crtc_state *pipe_config)
1944 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1945 struct intel_connector *intel_connector = intel_dp->attached_connector;
1948 bpp = pipe_config->pipe_bpp;
1949 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1952 bpp = min(bpp, 3*bpc);
1954 if (intel_dp_is_edp(intel_dp)) {
1955 /* Get bpp from vbt only for panels that dont have bpp in edid */
1956 if (intel_connector->base.display_info.bpc == 0 &&
1957 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1958 drm_dbg_kms(&dev_priv->drm,
1959 "clamping bpp for eDP panel to BIOS-provided %i\n",
1960 dev_priv->vbt.edp.bpp);
1961 bpp = dev_priv->vbt.edp.bpp;
1968 /* Adjust link config limits based on compliance test requests. */
1970 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1971 struct intel_crtc_state *pipe_config,
1972 struct link_config_limits *limits)
1974 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1976 /* For DP Compliance we override the computed bpp for the pipe */
1977 if (intel_dp->compliance.test_data.bpc != 0) {
1978 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1980 limits->min_bpp = limits->max_bpp = bpp;
1981 pipe_config->dither_force_disable = bpp == 6 * 3;
1983 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1986 /* Use values requested by Compliance Test Request */
1987 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1990 /* Validate the compliance test data since max values
1991 * might have changed due to link train fallback.
1993 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1994 intel_dp->compliance.test_lane_count)) {
1995 index = intel_dp_rate_index(intel_dp->common_rates,
1996 intel_dp->num_common_rates,
1997 intel_dp->compliance.test_link_rate);
1999 limits->min_clock = limits->max_clock = index;
2000 limits->min_lane_count = limits->max_lane_count =
2001 intel_dp->compliance.test_lane_count;
2006 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2009 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2010 * format of the number of bytes per pixel will be half the number
2011 * of bytes of RGB pixel.
2013 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2019 /* Optimize link config in order: max bpp, min clock, min lanes */
2021 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2022 struct intel_crtc_state *pipe_config,
2023 const struct link_config_limits *limits)
2025 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2026 int bpp, clock, lane_count;
2027 int mode_rate, link_clock, link_avail;
2029 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2030 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2032 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2035 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2036 for (lane_count = limits->min_lane_count;
2037 lane_count <= limits->max_lane_count;
2039 link_clock = intel_dp->common_rates[clock];
2040 link_avail = intel_dp_max_data_rate(link_clock,
2043 if (mode_rate <= link_avail) {
2044 pipe_config->lane_count = lane_count;
2045 pipe_config->pipe_bpp = bpp;
2046 pipe_config->port_clock = link_clock;
2057 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2060 u8 dsc_bpc[3] = {0};
2062 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2064 for (i = 0; i < num_bpc; i++) {
2065 if (dsc_max_bpc >= dsc_bpc[i])
2066 return dsc_bpc[i] * 3;
2072 #define DSC_SUPPORTED_VERSION_MIN 1
2074 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2075 struct intel_crtc_state *crtc_state)
2077 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2078 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2079 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2083 ret = intel_dsc_compute_params(encoder, crtc_state);
2088 * Slice Height of 8 works for all currently available panels. So start
2089 * with that if pic_height is an integral multiple of 8. Eventually add
2090 * logic to try multiple slice heights.
2092 if (vdsc_cfg->pic_height % 8 == 0)
2093 vdsc_cfg->slice_height = 8;
2094 else if (vdsc_cfg->pic_height % 4 == 0)
2095 vdsc_cfg->slice_height = 4;
2097 vdsc_cfg->slice_height = 2;
2099 vdsc_cfg->dsc_version_major =
2100 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2101 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2102 vdsc_cfg->dsc_version_minor =
2103 min(DSC_SUPPORTED_VERSION_MIN,
2104 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2105 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2107 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2110 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2111 if (!line_buf_depth) {
2112 drm_dbg_kms(&i915->drm,
2113 "DSC Sink Line Buffer Depth invalid\n");
2117 if (vdsc_cfg->dsc_version_minor == 2)
2118 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2119 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2121 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2122 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2124 vdsc_cfg->block_pred_enable =
2125 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2126 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2128 return drm_dsc_compute_rc_parameters(vdsc_cfg);
2131 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2132 struct intel_crtc_state *pipe_config,
2133 struct drm_connector_state *conn_state,
2134 struct link_config_limits *limits)
2136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2137 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2138 const struct drm_display_mode *adjusted_mode =
2139 &pipe_config->hw.adjusted_mode;
2144 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2145 intel_dp_supports_fec(intel_dp, pipe_config);
2147 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2150 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2151 if (INTEL_GEN(dev_priv) >= 12)
2152 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2154 dsc_max_bpc = min_t(u8, 10,
2155 conn_state->max_requested_bpc);
2157 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2159 /* Min Input BPC for ICL+ is 8 */
2160 if (pipe_bpp < 8 * 3) {
2161 drm_dbg_kms(&dev_priv->drm,
2162 "No DSC support for less than 8bpc\n");
2167 * For now enable DSC for max bpp, max link rate, max lane count.
2168 * Optimize this later for the minimum possible link rate/lane count
2169 * with DSC enabled for the requested mode.
2171 pipe_config->pipe_bpp = pipe_bpp;
2172 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2173 pipe_config->lane_count = limits->max_lane_count;
2175 if (intel_dp_is_edp(intel_dp)) {
2176 pipe_config->dsc.compressed_bpp =
2177 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2178 pipe_config->pipe_bpp);
2179 pipe_config->dsc.slice_count =
2180 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2183 u16 dsc_max_output_bpp;
2184 u8 dsc_dp_slice_count;
2186 dsc_max_output_bpp =
2187 intel_dp_dsc_get_output_bpp(dev_priv,
2188 pipe_config->port_clock,
2189 pipe_config->lane_count,
2190 adjusted_mode->crtc_clock,
2191 adjusted_mode->crtc_hdisplay);
2192 dsc_dp_slice_count =
2193 intel_dp_dsc_get_slice_count(intel_dp,
2194 adjusted_mode->crtc_clock,
2195 adjusted_mode->crtc_hdisplay);
2196 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2197 drm_dbg_kms(&dev_priv->drm,
2198 "Compressed BPP/Slice Count not supported\n");
2201 pipe_config->dsc.compressed_bpp = min_t(u16,
2202 dsc_max_output_bpp >> 4,
2203 pipe_config->pipe_bpp);
2204 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2207 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2208 * is greater than the maximum Cdclock and if slice count is even
2209 * then we need to use 2 VDSC instances.
2211 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2212 if (pipe_config->dsc.slice_count > 1) {
2213 pipe_config->dsc.dsc_split = true;
2215 drm_dbg_kms(&dev_priv->drm,
2216 "Cannot split stream to use 2 VDSC instances\n");
2221 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2223 drm_dbg_kms(&dev_priv->drm,
2224 "Cannot compute valid DSC parameters for Input Bpp = %d "
2225 "Compressed BPP = %d\n",
2226 pipe_config->pipe_bpp,
2227 pipe_config->dsc.compressed_bpp);
2231 pipe_config->dsc.compression_enable = true;
2232 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2233 "Compressed Bpp = %d Slice Count = %d\n",
2234 pipe_config->pipe_bpp,
2235 pipe_config->dsc.compressed_bpp,
2236 pipe_config->dsc.slice_count);
2241 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2243 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2250 intel_dp_compute_link_config(struct intel_encoder *encoder,
2251 struct intel_crtc_state *pipe_config,
2252 struct drm_connector_state *conn_state)
2254 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2255 const struct drm_display_mode *adjusted_mode =
2256 &pipe_config->hw.adjusted_mode;
2257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2258 struct link_config_limits limits;
2262 common_len = intel_dp_common_len_rate_limit(intel_dp,
2263 intel_dp->max_link_rate);
2265 /* No common link rates between source and sink */
2266 drm_WARN_ON(encoder->base.dev, common_len <= 0);
2268 limits.min_clock = 0;
2269 limits.max_clock = common_len - 1;
2271 limits.min_lane_count = 1;
2272 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2274 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2275 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2277 if (intel_dp_is_edp(intel_dp)) {
2279 * Use the maximum clock and number of lanes the eDP panel
2280 * advertizes being capable of. The panels are generally
2281 * designed to support only a single clock and lane
2282 * configuration, and typically these values correspond to the
2283 * native resolution of the panel.
2285 limits.min_lane_count = limits.max_lane_count;
2286 limits.min_clock = limits.max_clock;
2289 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2291 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2292 "max rate %d max bpp %d pixel clock %iKHz\n",
2293 limits.max_lane_count,
2294 intel_dp->common_rates[limits.max_clock],
2295 limits.max_bpp, adjusted_mode->crtc_clock);
2298 * Optimize for slow and wide. This is the place to add alternative
2299 * optimization policy.
2301 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2303 /* enable compression if the mode doesn't fit available BW */
2304 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2305 if (ret || intel_dp->force_dsc_en) {
2306 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2307 conn_state, &limits);
2312 if (pipe_config->dsc.compression_enable) {
2313 drm_dbg_kms(&i915->drm,
2314 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2315 pipe_config->lane_count, pipe_config->port_clock,
2316 pipe_config->pipe_bpp,
2317 pipe_config->dsc.compressed_bpp);
2319 drm_dbg_kms(&i915->drm,
2320 "DP link rate required %i available %i\n",
2321 intel_dp_link_required(adjusted_mode->crtc_clock,
2322 pipe_config->dsc.compressed_bpp),
2323 intel_dp_max_data_rate(pipe_config->port_clock,
2324 pipe_config->lane_count));
2326 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2327 pipe_config->lane_count, pipe_config->port_clock,
2328 pipe_config->pipe_bpp);
2330 drm_dbg_kms(&i915->drm,
2331 "DP link rate required %i available %i\n",
2332 intel_dp_link_required(adjusted_mode->crtc_clock,
2333 pipe_config->pipe_bpp),
2334 intel_dp_max_data_rate(pipe_config->port_clock,
2335 pipe_config->lane_count));
2341 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2342 struct intel_crtc_state *crtc_state,
2343 const struct drm_connector_state *conn_state)
2345 struct drm_connector *connector = conn_state->connector;
2346 const struct drm_display_info *info = &connector->display_info;
2347 const struct drm_display_mode *adjusted_mode =
2348 &crtc_state->hw.adjusted_mode;
2350 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2351 !intel_dp_get_colorimetry_status(intel_dp) ||
2352 !connector->ycbcr_420_allowed)
2355 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2357 return intel_pch_panel_fitting(crtc_state, conn_state);
2360 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2361 const struct drm_connector_state *conn_state)
2363 const struct intel_digital_connector_state *intel_conn_state =
2364 to_intel_digital_connector_state(conn_state);
2365 const struct drm_display_mode *adjusted_mode =
2366 &crtc_state->hw.adjusted_mode;
2369 * Our YCbCr output is always limited range.
2370 * crtc_state->limited_color_range only applies to RGB,
2371 * and it must never be set for YCbCr or we risk setting
2372 * some conflicting bits in PIPECONF which will mess up
2373 * the colors on the monitor.
2375 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2378 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2381 * CEA-861-E - 5.1 Default Encoding Parameters
2382 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2384 return crtc_state->pipe_bpp != 18 &&
2385 drm_default_rgb_quant_range(adjusted_mode) ==
2386 HDMI_QUANTIZATION_RANGE_LIMITED;
2388 return intel_conn_state->broadcast_rgb ==
2389 INTEL_BROADCAST_RGB_LIMITED;
2393 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2396 if (IS_G4X(dev_priv))
2398 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2404 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2405 const struct drm_connector_state *conn_state,
2406 struct drm_dp_vsc_sdp *vsc)
2408 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2412 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2413 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2414 * Colorimetry Format indication.
2416 vsc->revision = 0x5;
2419 /* DP 1.4a spec, Table 2-120 */
2420 switch (crtc_state->output_format) {
2421 case INTEL_OUTPUT_FORMAT_YCBCR444:
2422 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2424 case INTEL_OUTPUT_FORMAT_YCBCR420:
2425 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2427 case INTEL_OUTPUT_FORMAT_RGB:
2429 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2432 switch (conn_state->colorspace) {
2433 case DRM_MODE_COLORIMETRY_BT709_YCC:
2434 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2436 case DRM_MODE_COLORIMETRY_XVYCC_601:
2437 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2439 case DRM_MODE_COLORIMETRY_XVYCC_709:
2440 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2442 case DRM_MODE_COLORIMETRY_SYCC_601:
2443 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2445 case DRM_MODE_COLORIMETRY_OPYCC_601:
2446 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2448 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2449 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2451 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2452 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2454 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2455 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2457 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2458 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2459 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2463 * RGB->YCBCR color conversion uses the BT.709
2466 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2467 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2469 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2473 vsc->bpc = crtc_state->pipe_bpp / 3;
2475 /* only RGB pixelformat supports 6 bpc */
2476 drm_WARN_ON(&dev_priv->drm,
2477 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2479 /* all YCbCr are always limited range */
2480 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2481 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2484 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2485 struct intel_crtc_state *crtc_state,
2486 const struct drm_connector_state *conn_state)
2488 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2490 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2491 if (crtc_state->has_psr)
2494 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2497 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2498 vsc->sdp_type = DP_SDP_VSC;
2499 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2500 &crtc_state->infoframes.vsc);
2503 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2504 const struct intel_crtc_state *crtc_state,
2505 const struct drm_connector_state *conn_state,
2506 struct drm_dp_vsc_sdp *vsc)
2508 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2510 vsc->sdp_type = DP_SDP_VSC;
2512 if (dev_priv->psr.psr2_enabled) {
2513 if (dev_priv->psr.colorimetry_support &&
2514 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2515 /* [PSR2, +Colorimetry] */
2516 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2520 * [PSR2, -Colorimetry]
2521 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2522 * 3D stereo + PSR/PSR2 + Y-coordinate.
2524 vsc->revision = 0x4;
2530 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2531 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2534 vsc->revision = 0x2;
2540 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2541 struct intel_crtc_state *crtc_state,
2542 const struct drm_connector_state *conn_state)
2545 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2546 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2548 if (!conn_state->hdr_output_metadata)
2551 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2554 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2558 crtc_state->infoframes.enable |=
2559 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2563 intel_dp_compute_config(struct intel_encoder *encoder,
2564 struct intel_crtc_state *pipe_config,
2565 struct drm_connector_state *conn_state)
2567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2568 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2569 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2570 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2571 enum port port = encoder->port;
2572 struct intel_connector *intel_connector = intel_dp->attached_connector;
2573 struct intel_digital_connector_state *intel_conn_state =
2574 to_intel_digital_connector_state(conn_state);
2575 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2576 DP_DPCD_QUIRK_CONSTANT_N);
2577 int ret = 0, output_bpp;
2579 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2580 pipe_config->has_pch_encoder = true;
2582 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2585 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2587 ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
2592 pipe_config->has_drrs = false;
2593 if (!intel_dp_port_has_audio(dev_priv, port))
2594 pipe_config->has_audio = false;
2595 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2596 pipe_config->has_audio = intel_dp->has_audio;
2598 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2600 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2601 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2604 if (HAS_GMCH(dev_priv))
2605 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2607 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2612 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2615 if (HAS_GMCH(dev_priv) &&
2616 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2619 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2622 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2625 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2629 pipe_config->limited_color_range =
2630 intel_dp_limited_color_range(pipe_config, conn_state);
2632 if (pipe_config->dsc.compression_enable)
2633 output_bpp = pipe_config->dsc.compressed_bpp;
2635 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2637 intel_link_compute_m_n(output_bpp,
2638 pipe_config->lane_count,
2639 adjusted_mode->crtc_clock,
2640 pipe_config->port_clock,
2641 &pipe_config->dp_m_n,
2642 constant_n, pipe_config->fec_enable);
2644 if (intel_connector->panel.downclock_mode != NULL &&
2645 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2646 pipe_config->has_drrs = true;
2647 intel_link_compute_m_n(output_bpp,
2648 pipe_config->lane_count,
2649 intel_connector->panel.downclock_mode->clock,
2650 pipe_config->port_clock,
2651 &pipe_config->dp_m2_n2,
2652 constant_n, pipe_config->fec_enable);
2655 if (!HAS_DDI(dev_priv))
2656 intel_dp_set_clock(encoder, pipe_config);
2658 intel_psr_compute_config(intel_dp, pipe_config);
2659 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2660 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2665 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2666 int link_rate, u8 lane_count,
2669 intel_dp->link_trained = false;
2670 intel_dp->link_rate = link_rate;
2671 intel_dp->lane_count = lane_count;
2672 intel_dp->link_mst = link_mst;
2675 static void intel_dp_prepare(struct intel_encoder *encoder,
2676 const struct intel_crtc_state *pipe_config)
2678 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2680 enum port port = encoder->port;
2681 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2682 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2684 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2685 pipe_config->lane_count,
2686 intel_crtc_has_type(pipe_config,
2687 INTEL_OUTPUT_DP_MST));
2690 * There are four kinds of DP registers:
2697 * IBX PCH and CPU are the same for almost everything,
2698 * except that the CPU DP PLL is configured in this
2701 * CPT PCH is quite different, having many bits moved
2702 * to the TRANS_DP_CTL register instead. That
2703 * configuration happens (oddly) in ilk_pch_enable
2706 /* Preserve the BIOS-computed detected bit. This is
2707 * supposed to be read-only.
2709 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2711 /* Handle DP bits in common between all three register formats */
2712 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2713 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2715 /* Split out the IBX/CPU vs CPT settings */
2717 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2718 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2719 intel_dp->DP |= DP_SYNC_HS_HIGH;
2720 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2721 intel_dp->DP |= DP_SYNC_VS_HIGH;
2722 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2724 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2725 intel_dp->DP |= DP_ENHANCED_FRAMING;
2727 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2728 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2731 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2733 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2734 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2735 trans_dp |= TRANS_DP_ENH_FRAMING;
2737 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2738 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2740 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2741 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2743 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2744 intel_dp->DP |= DP_SYNC_HS_HIGH;
2745 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2746 intel_dp->DP |= DP_SYNC_VS_HIGH;
2747 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2749 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2750 intel_dp->DP |= DP_ENHANCED_FRAMING;
2752 if (IS_CHERRYVIEW(dev_priv))
2753 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2755 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2759 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2760 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2762 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2763 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2765 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2766 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2768 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2770 static void wait_panel_status(struct intel_dp *intel_dp,
2774 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2775 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2777 lockdep_assert_held(&dev_priv->pps_mutex);
2779 intel_pps_verify_state(intel_dp);
2781 pp_stat_reg = _pp_stat_reg(intel_dp);
2782 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2784 drm_dbg_kms(&dev_priv->drm,
2785 "mask %08x value %08x status %08x control %08x\n",
2787 intel_de_read(dev_priv, pp_stat_reg),
2788 intel_de_read(dev_priv, pp_ctrl_reg));
2790 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2792 drm_err(&dev_priv->drm,
2793 "Panel status timeout: status %08x control %08x\n",
2794 intel_de_read(dev_priv, pp_stat_reg),
2795 intel_de_read(dev_priv, pp_ctrl_reg));
2797 drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2800 static void wait_panel_on(struct intel_dp *intel_dp)
2802 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2804 drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2805 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2808 static void wait_panel_off(struct intel_dp *intel_dp)
2810 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2812 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2813 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2816 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2818 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2819 ktime_t panel_power_on_time;
2820 s64 panel_power_off_duration;
2822 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2824 /* take the difference of currrent time and panel power off time
2825 * and then make panel wait for t11_t12 if needed. */
2826 panel_power_on_time = ktime_get_boottime();
2827 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2829 /* When we disable the VDD override bit last we have to do the manual
2831 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2832 wait_remaining_ms_from_jiffies(jiffies,
2833 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2835 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2838 static void wait_backlight_on(struct intel_dp *intel_dp)
2840 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2841 intel_dp->backlight_on_delay);
2844 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2846 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2847 intel_dp->backlight_off_delay);
2850 /* Read the current pp_control value, unlocking the register if it
2854 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2856 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2859 lockdep_assert_held(&dev_priv->pps_mutex);
2861 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2862 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2863 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2864 control &= ~PANEL_UNLOCK_MASK;
2865 control |= PANEL_UNLOCK_REGS;
2871 * Must be paired with edp_panel_vdd_off().
2872 * Must hold pps_mutex around the whole on/off sequence.
2873 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2875 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2877 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2878 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2880 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2881 bool need_to_disable = !intel_dp->want_panel_vdd;
2883 lockdep_assert_held(&dev_priv->pps_mutex);
2885 if (!intel_dp_is_edp(intel_dp))
2888 cancel_delayed_work(&intel_dp->panel_vdd_work);
2889 intel_dp->want_panel_vdd = true;
2891 if (edp_have_panel_vdd(intel_dp))
2892 return need_to_disable;
2894 intel_display_power_get(dev_priv,
2895 intel_aux_power_domain(intel_dig_port));
2897 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2898 intel_dig_port->base.base.base.id,
2899 intel_dig_port->base.base.name);
2901 if (!edp_have_panel_power(intel_dp))
2902 wait_panel_power_cycle(intel_dp);
2904 pp = ilk_get_pp_control(intel_dp);
2905 pp |= EDP_FORCE_VDD;
2907 pp_stat_reg = _pp_stat_reg(intel_dp);
2908 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2910 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2911 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2912 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2913 intel_de_read(dev_priv, pp_stat_reg),
2914 intel_de_read(dev_priv, pp_ctrl_reg));
2916 * If the panel wasn't on, delay before accessing aux channel
2918 if (!edp_have_panel_power(intel_dp)) {
2919 drm_dbg_kms(&dev_priv->drm,
2920 "[ENCODER:%d:%s] panel power wasn't enabled\n",
2921 intel_dig_port->base.base.base.id,
2922 intel_dig_port->base.base.name);
2923 msleep(intel_dp->panel_power_up_delay);
2926 return need_to_disable;
2930 * Must be paired with intel_edp_panel_vdd_off() or
2931 * intel_edp_panel_off().
2932 * Nested calls to these functions are not allowed since
2933 * we drop the lock. Caller must use some higher level
2934 * locking to prevent nested calls from other threads.
2936 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2938 intel_wakeref_t wakeref;
2941 if (!intel_dp_is_edp(intel_dp))
2945 with_pps_lock(intel_dp, wakeref)
2946 vdd = edp_panel_vdd_on(intel_dp);
2947 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2948 dp_to_dig_port(intel_dp)->base.base.base.id,
2949 dp_to_dig_port(intel_dp)->base.base.name);
2952 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2954 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2955 struct intel_digital_port *intel_dig_port =
2956 dp_to_dig_port(intel_dp);
2958 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2960 lockdep_assert_held(&dev_priv->pps_mutex);
2962 drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2964 if (!edp_have_panel_vdd(intel_dp))
2967 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2968 intel_dig_port->base.base.base.id,
2969 intel_dig_port->base.base.name);
2971 pp = ilk_get_pp_control(intel_dp);
2972 pp &= ~EDP_FORCE_VDD;
2974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2975 pp_stat_reg = _pp_stat_reg(intel_dp);
2977 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2978 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2980 /* Make sure sequencer is idle before allowing subsequent activity */
2981 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2982 intel_de_read(dev_priv, pp_stat_reg),
2983 intel_de_read(dev_priv, pp_ctrl_reg));
2985 if ((pp & PANEL_POWER_ON) == 0)
2986 intel_dp->panel_power_off_time = ktime_get_boottime();
2988 intel_display_power_put_unchecked(dev_priv,
2989 intel_aux_power_domain(intel_dig_port));
2992 static void edp_panel_vdd_work(struct work_struct *__work)
2994 struct intel_dp *intel_dp =
2995 container_of(to_delayed_work(__work),
2996 struct intel_dp, panel_vdd_work);
2997 intel_wakeref_t wakeref;
2999 with_pps_lock(intel_dp, wakeref) {
3000 if (!intel_dp->want_panel_vdd)
3001 edp_panel_vdd_off_sync(intel_dp);
3005 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3007 unsigned long delay;
3010 * Queue the timer to fire a long time from now (relative to the power
3011 * down delay) to keep the panel power up across a sequence of
3014 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3015 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3019 * Must be paired with edp_panel_vdd_on().
3020 * Must hold pps_mutex around the whole on/off sequence.
3021 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3023 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3025 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3027 lockdep_assert_held(&dev_priv->pps_mutex);
3029 if (!intel_dp_is_edp(intel_dp))
3032 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3033 dp_to_dig_port(intel_dp)->base.base.base.id,
3034 dp_to_dig_port(intel_dp)->base.base.name);
3036 intel_dp->want_panel_vdd = false;
3039 edp_panel_vdd_off_sync(intel_dp);
3041 edp_panel_vdd_schedule_off(intel_dp);
3044 static void edp_panel_on(struct intel_dp *intel_dp)
3046 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3048 i915_reg_t pp_ctrl_reg;
3050 lockdep_assert_held(&dev_priv->pps_mutex);
3052 if (!intel_dp_is_edp(intel_dp))
3055 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3056 dp_to_dig_port(intel_dp)->base.base.base.id,
3057 dp_to_dig_port(intel_dp)->base.base.name);
3059 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3060 "[ENCODER:%d:%s] panel power already on\n",
3061 dp_to_dig_port(intel_dp)->base.base.base.id,
3062 dp_to_dig_port(intel_dp)->base.base.name))
3065 wait_panel_power_cycle(intel_dp);
3067 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3068 pp = ilk_get_pp_control(intel_dp);
3069 if (IS_GEN(dev_priv, 5)) {
3070 /* ILK workaround: disable reset around power sequence */
3071 pp &= ~PANEL_POWER_RESET;
3072 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3073 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3076 pp |= PANEL_POWER_ON;
3077 if (!IS_GEN(dev_priv, 5))
3078 pp |= PANEL_POWER_RESET;
3080 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3081 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3083 wait_panel_on(intel_dp);
3084 intel_dp->last_power_on = jiffies;
3086 if (IS_GEN(dev_priv, 5)) {
3087 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3088 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3089 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3093 void intel_edp_panel_on(struct intel_dp *intel_dp)
3095 intel_wakeref_t wakeref;
3097 if (!intel_dp_is_edp(intel_dp))
3100 with_pps_lock(intel_dp, wakeref)
3101 edp_panel_on(intel_dp);
3105 static void edp_panel_off(struct intel_dp *intel_dp)
3107 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3110 i915_reg_t pp_ctrl_reg;
3112 lockdep_assert_held(&dev_priv->pps_mutex);
3114 if (!intel_dp_is_edp(intel_dp))
3117 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3118 dig_port->base.base.base.id, dig_port->base.base.name);
3120 drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3121 "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3122 dig_port->base.base.base.id, dig_port->base.base.name);
3124 pp = ilk_get_pp_control(intel_dp);
3125 /* We need to switch off panel power _and_ force vdd, for otherwise some
3126 * panels get very unhappy and cease to work. */
3127 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3130 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3132 intel_dp->want_panel_vdd = false;
3134 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3135 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3137 wait_panel_off(intel_dp);
3138 intel_dp->panel_power_off_time = ktime_get_boottime();
3140 /* We got a reference when we enabled the VDD. */
3141 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3144 void intel_edp_panel_off(struct intel_dp *intel_dp)
3146 intel_wakeref_t wakeref;
3148 if (!intel_dp_is_edp(intel_dp))
3151 with_pps_lock(intel_dp, wakeref)
3152 edp_panel_off(intel_dp);
3155 /* Enable backlight in the panel power control. */
3156 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3158 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3159 intel_wakeref_t wakeref;
3162 * If we enable the backlight right away following a panel power
3163 * on, we may see slight flicker as the panel syncs with the eDP
3164 * link. So delay a bit to make sure the image is solid before
3165 * allowing it to appear.
3167 wait_backlight_on(intel_dp);
3169 with_pps_lock(intel_dp, wakeref) {
3170 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3173 pp = ilk_get_pp_control(intel_dp);
3174 pp |= EDP_BLC_ENABLE;
3176 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3177 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3181 /* Enable backlight PWM and backlight PP control. */
3182 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3183 const struct drm_connector_state *conn_state)
3185 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3186 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3188 if (!intel_dp_is_edp(intel_dp))
3191 drm_dbg_kms(&i915->drm, "\n");
3193 intel_panel_enable_backlight(crtc_state, conn_state);
3194 _intel_edp_backlight_on(intel_dp);
3197 /* Disable backlight in the panel power control. */
3198 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3200 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3201 intel_wakeref_t wakeref;
3203 if (!intel_dp_is_edp(intel_dp))
3206 with_pps_lock(intel_dp, wakeref) {
3207 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3210 pp = ilk_get_pp_control(intel_dp);
3211 pp &= ~EDP_BLC_ENABLE;
3213 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3214 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3217 intel_dp->last_backlight_off = jiffies;
3218 edp_wait_backlight_off(intel_dp);
3221 /* Disable backlight PP control and backlight PWM. */
3222 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3224 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3225 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3227 if (!intel_dp_is_edp(intel_dp))
3230 drm_dbg_kms(&i915->drm, "\n");
3232 _intel_edp_backlight_off(intel_dp);
3233 intel_panel_disable_backlight(old_conn_state);
3237 * Hook for controlling the panel power control backlight through the bl_power
3238 * sysfs attribute. Take care to handle multiple calls.
3240 static void intel_edp_backlight_power(struct intel_connector *connector,
3243 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3244 struct intel_dp *intel_dp = intel_attached_dp(connector);
3245 intel_wakeref_t wakeref;
3249 with_pps_lock(intel_dp, wakeref)
3250 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3251 if (is_enabled == enable)
3254 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3255 enable ? "enable" : "disable");
3258 _intel_edp_backlight_on(intel_dp);
3260 _intel_edp_backlight_off(intel_dp);
3263 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3265 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3266 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3267 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3269 I915_STATE_WARN(cur_state != state,
3270 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3271 dig_port->base.base.base.id, dig_port->base.base.name,
3272 onoff(state), onoff(cur_state));
3274 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3276 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3278 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3280 I915_STATE_WARN(cur_state != state,
3281 "eDP PLL state assertion failure (expected %s, current %s)\n",
3282 onoff(state), onoff(cur_state));
3284 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3285 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3287 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3288 const struct intel_crtc_state *pipe_config)
3290 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3291 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3293 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3294 assert_dp_port_disabled(intel_dp);
3295 assert_edp_pll_disabled(dev_priv);
3297 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3298 pipe_config->port_clock);
3300 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3302 if (pipe_config->port_clock == 162000)
3303 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3305 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3307 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3308 intel_de_posting_read(dev_priv, DP_A);
3312 * [DevILK] Work around required when enabling DP PLL
3313 * while a pipe is enabled going to FDI:
3314 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3315 * 2. Program DP PLL enable
3317 if (IS_GEN(dev_priv, 5))
3318 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3320 intel_dp->DP |= DP_PLL_ENABLE;
3322 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3323 intel_de_posting_read(dev_priv, DP_A);
3327 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3328 const struct intel_crtc_state *old_crtc_state)
3330 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3333 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3334 assert_dp_port_disabled(intel_dp);
3335 assert_edp_pll_enabled(dev_priv);
3337 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3339 intel_dp->DP &= ~DP_PLL_ENABLE;
3341 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3342 intel_de_posting_read(dev_priv, DP_A);
3346 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3349 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3350 * be capable of signalling downstream hpd with a long pulse.
3351 * Whether or not that means D3 is safe to use is not clear,
3352 * but let's assume so until proven otherwise.
3354 * FIXME should really check all downstream ports...
3356 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3357 drm_dp_is_branch(intel_dp->dpcd) &&
3358 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3361 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3362 const struct intel_crtc_state *crtc_state,
3365 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3368 if (!crtc_state->dsc.compression_enable)
3371 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3372 enable ? DP_DECOMPRESSION_EN : 0);
3374 drm_dbg_kms(&i915->drm,
3375 "Failed to %s sink decompression state\n",
3376 enable ? "enable" : "disable");
3379 /* If the sink supports it, try to set the power state appropriately */
3380 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3382 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3385 /* Should have a valid DPCD by this point */
3386 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3389 if (mode != DRM_MODE_DPMS_ON) {
3390 if (downstream_hpd_needs_d0(intel_dp))
3393 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3396 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3399 * When turning on, we need to retry for 1ms to give the sink
3402 for (i = 0; i < 3; i++) {
3403 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3410 if (ret == 1 && lspcon->active)
3411 lspcon_wait_pcon_mode(lspcon);
3415 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3416 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3419 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3420 enum port port, enum pipe *pipe)
3424 for_each_pipe(dev_priv, p) {
3425 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3427 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3433 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3436 /* must initialize pipe to something for the asserts */
3442 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3443 i915_reg_t dp_reg, enum port port,
3449 val = intel_de_read(dev_priv, dp_reg);
3451 ret = val & DP_PORT_EN;
3453 /* asserts want to know the pipe even if the port is disabled */
3454 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3455 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3456 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3457 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3458 else if (IS_CHERRYVIEW(dev_priv))
3459 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3461 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3466 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3469 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3470 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3471 intel_wakeref_t wakeref;
3474 wakeref = intel_display_power_get_if_enabled(dev_priv,
3475 encoder->power_domain);
3479 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3480 encoder->port, pipe);
3482 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3487 static void intel_dp_get_config(struct intel_encoder *encoder,
3488 struct intel_crtc_state *pipe_config)
3490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3491 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3493 enum port port = encoder->port;
3494 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3496 if (encoder->type == INTEL_OUTPUT_EDP)
3497 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3499 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3501 tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3503 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3505 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3506 u32 trans_dp = intel_de_read(dev_priv,
3507 TRANS_DP_CTL(crtc->pipe));
3509 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3510 flags |= DRM_MODE_FLAG_PHSYNC;
3512 flags |= DRM_MODE_FLAG_NHSYNC;
3514 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3515 flags |= DRM_MODE_FLAG_PVSYNC;
3517 flags |= DRM_MODE_FLAG_NVSYNC;
3519 if (tmp & DP_SYNC_HS_HIGH)
3520 flags |= DRM_MODE_FLAG_PHSYNC;
3522 flags |= DRM_MODE_FLAG_NHSYNC;
3524 if (tmp & DP_SYNC_VS_HIGH)
3525 flags |= DRM_MODE_FLAG_PVSYNC;
3527 flags |= DRM_MODE_FLAG_NVSYNC;
3530 pipe_config->hw.adjusted_mode.flags |= flags;
3532 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3533 pipe_config->limited_color_range = true;
3535 pipe_config->lane_count =
3536 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3538 intel_dp_get_m_n(crtc, pipe_config);
3540 if (port == PORT_A) {
3541 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3542 pipe_config->port_clock = 162000;
3544 pipe_config->port_clock = 270000;
3547 pipe_config->hw.adjusted_mode.crtc_clock =
3548 intel_dotclock_calculate(pipe_config->port_clock,
3549 &pipe_config->dp_m_n);
3551 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3552 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3554 * This is a big fat ugly hack.
3556 * Some machines in UEFI boot mode provide us a VBT that has 18
3557 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3558 * unknown we fail to light up. Yet the same BIOS boots up with
3559 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3560 * max, not what it tells us to use.
3562 * Note: This will still be broken if the eDP panel is not lit
3563 * up by the BIOS, and thus we can't get the mode at module
3566 drm_dbg_kms(&dev_priv->drm,
3567 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3568 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3569 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3573 static void intel_disable_dp(struct intel_atomic_state *state,
3574 struct intel_encoder *encoder,
3575 const struct intel_crtc_state *old_crtc_state,
3576 const struct drm_connector_state *old_conn_state)
3578 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3580 intel_dp->link_trained = false;
3582 if (old_crtc_state->has_audio)
3583 intel_audio_codec_disable(encoder,
3584 old_crtc_state, old_conn_state);
3586 /* Make sure the panel is off before trying to change the mode. But also
3587 * ensure that we have vdd while we switch off the panel. */
3588 intel_edp_panel_vdd_on(intel_dp);
3589 intel_edp_backlight_off(old_conn_state);
3590 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3591 intel_edp_panel_off(intel_dp);
3594 static void g4x_disable_dp(struct intel_atomic_state *state,
3595 struct intel_encoder *encoder,
3596 const struct intel_crtc_state *old_crtc_state,
3597 const struct drm_connector_state *old_conn_state)
3599 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3602 static void vlv_disable_dp(struct intel_atomic_state *state,
3603 struct intel_encoder *encoder,
3604 const struct intel_crtc_state *old_crtc_state,
3605 const struct drm_connector_state *old_conn_state)
3607 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3610 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3611 struct intel_encoder *encoder,
3612 const struct intel_crtc_state *old_crtc_state,
3613 const struct drm_connector_state *old_conn_state)
3615 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3616 enum port port = encoder->port;
3619 * Bspec does not list a specific disable sequence for g4x DP.
3620 * Follow the ilk+ sequence (disable pipe before the port) for
3621 * g4x DP as it does not suffer from underruns like the normal
3622 * g4x modeset sequence (disable pipe after the port).
3624 intel_dp_link_down(encoder, old_crtc_state);
3626 /* Only ilk+ has port A */
3628 ilk_edp_pll_off(intel_dp, old_crtc_state);
3631 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3632 struct intel_encoder *encoder,
3633 const struct intel_crtc_state *old_crtc_state,
3634 const struct drm_connector_state *old_conn_state)
3636 intel_dp_link_down(encoder, old_crtc_state);
3639 static void chv_post_disable_dp(struct intel_atomic_state *state,
3640 struct intel_encoder *encoder,
3641 const struct intel_crtc_state *old_crtc_state,
3642 const struct drm_connector_state *old_conn_state)
3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3646 intel_dp_link_down(encoder, old_crtc_state);
3648 vlv_dpio_get(dev_priv);
3650 /* Assert data lane reset */
3651 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3653 vlv_dpio_put(dev_priv);
3657 cpt_set_link_train(struct intel_dp *intel_dp,
3660 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3661 u32 *DP = &intel_dp->DP;
3663 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3665 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3666 case DP_TRAINING_PATTERN_DISABLE:
3667 *DP |= DP_LINK_TRAIN_OFF_CPT;
3669 case DP_TRAINING_PATTERN_1:
3670 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3672 case DP_TRAINING_PATTERN_2:
3673 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3675 case DP_TRAINING_PATTERN_3:
3676 drm_dbg_kms(&dev_priv->drm,
3677 "TPS3 not supported, using TPS2 instead\n");
3678 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3682 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3683 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3687 g4x_set_link_train(struct intel_dp *intel_dp,
3690 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3691 u32 *DP = &intel_dp->DP;
3693 *DP &= ~DP_LINK_TRAIN_MASK;
3695 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3696 case DP_TRAINING_PATTERN_DISABLE:
3697 *DP |= DP_LINK_TRAIN_OFF;
3699 case DP_TRAINING_PATTERN_1:
3700 *DP |= DP_LINK_TRAIN_PAT_1;
3702 case DP_TRAINING_PATTERN_2:
3703 *DP |= DP_LINK_TRAIN_PAT_2;
3705 case DP_TRAINING_PATTERN_3:
3706 drm_dbg_kms(&dev_priv->drm,
3707 "TPS3 not supported, using TPS2 instead\n");
3708 *DP |= DP_LINK_TRAIN_PAT_2;
3712 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3713 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3716 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3717 const struct intel_crtc_state *old_crtc_state)
3719 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3721 /* enable with pattern 1 (as per spec) */
3723 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3726 * Magic for VLV/CHV. We _must_ first set up the register
3727 * without actually enabling the port, and then do another
3728 * write to enable the port. Otherwise link training will
3729 * fail when the power sequencer is freshly used for this port.
3731 intel_dp->DP |= DP_PORT_EN;
3732 if (old_crtc_state->has_audio)
3733 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3735 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3736 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3739 static void intel_enable_dp(struct intel_atomic_state *state,
3740 struct intel_encoder *encoder,
3741 const struct intel_crtc_state *pipe_config,
3742 const struct drm_connector_state *conn_state)
3744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3745 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3746 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3747 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3748 enum pipe pipe = crtc->pipe;
3749 intel_wakeref_t wakeref;
3751 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3754 with_pps_lock(intel_dp, wakeref) {
3755 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3756 vlv_init_panel_power_sequencer(encoder, pipe_config);
3758 intel_dp_enable_port(intel_dp, pipe_config);
3760 edp_panel_vdd_on(intel_dp);
3761 edp_panel_on(intel_dp);
3762 edp_panel_vdd_off(intel_dp, true);
3765 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3766 unsigned int lane_mask = 0x0;
3768 if (IS_CHERRYVIEW(dev_priv))
3769 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3771 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3775 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3776 intel_dp_start_link_train(intel_dp);
3777 intel_dp_stop_link_train(intel_dp);
3779 if (pipe_config->has_audio) {
3780 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3782 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3786 static void g4x_enable_dp(struct intel_atomic_state *state,
3787 struct intel_encoder *encoder,
3788 const struct intel_crtc_state *pipe_config,
3789 const struct drm_connector_state *conn_state)
3791 intel_enable_dp(state, encoder, pipe_config, conn_state);
3792 intel_edp_backlight_on(pipe_config, conn_state);
3795 static void vlv_enable_dp(struct intel_atomic_state *state,
3796 struct intel_encoder *encoder,
3797 const struct intel_crtc_state *pipe_config,
3798 const struct drm_connector_state *conn_state)
3800 intel_edp_backlight_on(pipe_config, conn_state);
3803 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3804 struct intel_encoder *encoder,
3805 const struct intel_crtc_state *pipe_config,
3806 const struct drm_connector_state *conn_state)
3808 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3809 enum port port = encoder->port;
3811 intel_dp_prepare(encoder, pipe_config);
3813 /* Only ilk+ has port A */
3815 ilk_edp_pll_on(intel_dp, pipe_config);
3818 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3820 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3821 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3822 enum pipe pipe = intel_dp->pps_pipe;
3823 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3825 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3827 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3830 edp_panel_vdd_off_sync(intel_dp);
3833 * VLV seems to get confused when multiple power sequencers
3834 * have the same port selected (even if only one has power/vdd
3835 * enabled). The failure manifests as vlv_wait_port_ready() failing
3836 * CHV on the other hand doesn't seem to mind having the same port
3837 * selected in multiple power sequencers, but let's clear the
3838 * port select always when logically disconnecting a power sequencer
3841 drm_dbg_kms(&dev_priv->drm,
3842 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3843 pipe_name(pipe), intel_dig_port->base.base.base.id,
3844 intel_dig_port->base.base.name);
3845 intel_de_write(dev_priv, pp_on_reg, 0);
3846 intel_de_posting_read(dev_priv, pp_on_reg);
3848 intel_dp->pps_pipe = INVALID_PIPE;
3851 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3854 struct intel_encoder *encoder;
3856 lockdep_assert_held(&dev_priv->pps_mutex);
3858 for_each_intel_dp(&dev_priv->drm, encoder) {
3859 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3861 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3862 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3863 pipe_name(pipe), encoder->base.base.id,
3864 encoder->base.name);
3866 if (intel_dp->pps_pipe != pipe)
3869 drm_dbg_kms(&dev_priv->drm,
3870 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3871 pipe_name(pipe), encoder->base.base.id,
3872 encoder->base.name);
3874 /* make sure vdd is off before we steal it */
3875 vlv_detach_power_sequencer(intel_dp);
3879 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3880 const struct intel_crtc_state *crtc_state)
3882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3883 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3886 lockdep_assert_held(&dev_priv->pps_mutex);
3888 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3890 if (intel_dp->pps_pipe != INVALID_PIPE &&
3891 intel_dp->pps_pipe != crtc->pipe) {
3893 * If another power sequencer was being used on this
3894 * port previously make sure to turn off vdd there while
3895 * we still have control of it.
3897 vlv_detach_power_sequencer(intel_dp);
3901 * We may be stealing the power
3902 * sequencer from another port.
3904 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3906 intel_dp->active_pipe = crtc->pipe;
3908 if (!intel_dp_is_edp(intel_dp))
3911 /* now it's all ours */
3912 intel_dp->pps_pipe = crtc->pipe;
3914 drm_dbg_kms(&dev_priv->drm,
3915 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3916 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3917 encoder->base.name);
3919 /* init power sequencer on this pipe and port */
3920 intel_dp_init_panel_power_sequencer(intel_dp);
3921 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3924 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3925 struct intel_encoder *encoder,
3926 const struct intel_crtc_state *pipe_config,
3927 const struct drm_connector_state *conn_state)
3929 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3931 intel_enable_dp(state, encoder, pipe_config, conn_state);
3934 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3935 struct intel_encoder *encoder,
3936 const struct intel_crtc_state *pipe_config,
3937 const struct drm_connector_state *conn_state)
3939 intel_dp_prepare(encoder, pipe_config);
3941 vlv_phy_pre_pll_enable(encoder, pipe_config);
3944 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3945 struct intel_encoder *encoder,
3946 const struct intel_crtc_state *pipe_config,
3947 const struct drm_connector_state *conn_state)
3949 chv_phy_pre_encoder_enable(encoder, pipe_config);
3951 intel_enable_dp(state, encoder, pipe_config, conn_state);
3953 /* Second common lane will stay alive on its own now */
3954 chv_phy_release_cl2_override(encoder);
3957 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3958 struct intel_encoder *encoder,
3959 const struct intel_crtc_state *pipe_config,
3960 const struct drm_connector_state *conn_state)
3962 intel_dp_prepare(encoder, pipe_config);
3964 chv_phy_pre_pll_enable(encoder, pipe_config);
3967 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3968 struct intel_encoder *encoder,
3969 const struct intel_crtc_state *old_crtc_state,
3970 const struct drm_connector_state *old_conn_state)
3972 chv_phy_post_pll_disable(encoder, old_crtc_state);
3976 * Fetch AUX CH registers 0x202 - 0x207 which contain
3977 * link status information
3980 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3982 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3983 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3986 /* These are source-specific values. */
3988 intel_dp_voltage_max(struct intel_dp *intel_dp)
3990 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3991 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3992 enum port port = encoder->port;
3994 if (HAS_DDI(dev_priv))
3995 return intel_ddi_dp_voltage_max(encoder);
3996 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3997 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3998 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3999 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4000 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
4001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4003 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4007 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4009 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4010 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4011 enum port port = encoder->port;
4013 if (HAS_DDI(dev_priv)) {
4014 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4015 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4016 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4018 return DP_TRAIN_PRE_EMPH_LEVEL_3;
4019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4020 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4022 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4025 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4027 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4028 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4030 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4033 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4035 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4038 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4039 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4040 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4042 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4044 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4047 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4052 static void vlv_set_signal_levels(struct intel_dp *intel_dp)
4054 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4055 unsigned long demph_reg_value, preemph_reg_value,
4056 uniqtranscale_reg_value;
4057 u8 train_set = intel_dp->train_set[0];
4059 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4060 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4061 preemph_reg_value = 0x0004000;
4062 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4064 demph_reg_value = 0x2B405555;
4065 uniqtranscale_reg_value = 0x552AB83A;
4067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4068 demph_reg_value = 0x2B404040;
4069 uniqtranscale_reg_value = 0x5548B83A;
4071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4072 demph_reg_value = 0x2B245555;
4073 uniqtranscale_reg_value = 0x5560B83A;
4075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4076 demph_reg_value = 0x2B405555;
4077 uniqtranscale_reg_value = 0x5598DA3A;
4083 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4084 preemph_reg_value = 0x0002000;
4085 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4087 demph_reg_value = 0x2B404040;
4088 uniqtranscale_reg_value = 0x5552B83A;
4090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4091 demph_reg_value = 0x2B404848;
4092 uniqtranscale_reg_value = 0x5580B83A;
4094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4095 demph_reg_value = 0x2B404040;
4096 uniqtranscale_reg_value = 0x55ADDA3A;
4102 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4103 preemph_reg_value = 0x0000000;
4104 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4106 demph_reg_value = 0x2B305555;
4107 uniqtranscale_reg_value = 0x5570B83A;
4109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4110 demph_reg_value = 0x2B2B4040;
4111 uniqtranscale_reg_value = 0x55ADDA3A;
4117 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4118 preemph_reg_value = 0x0006000;
4119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4121 demph_reg_value = 0x1B405555;
4122 uniqtranscale_reg_value = 0x55ADDA3A;
4132 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4133 uniqtranscale_reg_value, 0);
4136 static void chv_set_signal_levels(struct intel_dp *intel_dp)
4138 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4139 u32 deemph_reg_value, margin_reg_value;
4140 bool uniq_trans_scale = false;
4141 u8 train_set = intel_dp->train_set[0];
4143 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4144 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4145 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4147 deemph_reg_value = 128;
4148 margin_reg_value = 52;
4150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4151 deemph_reg_value = 128;
4152 margin_reg_value = 77;
4154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4155 deemph_reg_value = 128;
4156 margin_reg_value = 102;
4158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4159 deemph_reg_value = 128;
4160 margin_reg_value = 154;
4161 uniq_trans_scale = true;
4167 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4168 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4169 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4170 deemph_reg_value = 85;
4171 margin_reg_value = 78;
4173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4174 deemph_reg_value = 85;
4175 margin_reg_value = 116;
4177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4178 deemph_reg_value = 85;
4179 margin_reg_value = 154;
4185 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4186 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4188 deemph_reg_value = 64;
4189 margin_reg_value = 104;
4191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4192 deemph_reg_value = 64;
4193 margin_reg_value = 154;
4199 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4202 deemph_reg_value = 43;
4203 margin_reg_value = 154;
4213 chv_set_phy_signal_level(encoder, deemph_reg_value,
4214 margin_reg_value, uniq_trans_scale);
4217 static u32 g4x_signal_levels(u8 train_set)
4219 u32 signal_levels = 0;
4221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4224 signal_levels |= DP_VOLTAGE_0_4;
4226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4227 signal_levels |= DP_VOLTAGE_0_6;
4229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4230 signal_levels |= DP_VOLTAGE_0_8;
4232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4233 signal_levels |= DP_VOLTAGE_1_2;
4236 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4237 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4239 signal_levels |= DP_PRE_EMPHASIS_0;
4241 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4242 signal_levels |= DP_PRE_EMPHASIS_3_5;
4244 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4245 signal_levels |= DP_PRE_EMPHASIS_6;
4247 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4248 signal_levels |= DP_PRE_EMPHASIS_9_5;
4251 return signal_levels;
4255 g4x_set_signal_levels(struct intel_dp *intel_dp)
4257 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4258 u8 train_set = intel_dp->train_set[0];
4261 signal_levels = g4x_signal_levels(train_set);
4263 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4266 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4267 intel_dp->DP |= signal_levels;
4269 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4270 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4273 /* SNB CPU eDP voltage swing and pre-emphasis control */
4274 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4276 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4277 DP_TRAIN_PRE_EMPHASIS_MASK);
4279 switch (signal_levels) {
4280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4282 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4284 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4287 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4290 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4293 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4295 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4296 "0x%x\n", signal_levels);
4297 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4302 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4304 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4305 u8 train_set = intel_dp->train_set[0];
4308 signal_levels = snb_cpu_edp_signal_levels(train_set);
4310 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4313 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4314 intel_dp->DP |= signal_levels;
4316 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4317 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4320 /* IVB CPU eDP voltage swing and pre-emphasis control */
4321 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4323 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4324 DP_TRAIN_PRE_EMPHASIS_MASK);
4326 switch (signal_levels) {
4327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4328 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4330 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4332 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4335 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4337 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4340 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4342 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4345 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4346 "0x%x\n", signal_levels);
4347 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4352 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4354 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4355 u8 train_set = intel_dp->train_set[0];
4358 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4360 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4363 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4364 intel_dp->DP |= signal_levels;
4366 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4367 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4370 void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4372 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4373 u8 train_set = intel_dp->train_set[0];
4375 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4376 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4377 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4378 drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4379 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4380 DP_TRAIN_PRE_EMPHASIS_SHIFT,
4381 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4384 intel_dp->set_signal_levels(intel_dp);
4388 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4391 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4392 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4394 if (dp_train_pat & train_pat_mask)
4395 drm_dbg_kms(&dev_priv->drm,
4396 "Using DP training pattern TPS%d\n",
4397 dp_train_pat & train_pat_mask);
4399 intel_dp->set_link_train(intel_dp, dp_train_pat);
4402 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4404 if (intel_dp->set_idle_link_train)
4405 intel_dp->set_idle_link_train(intel_dp);
4409 intel_dp_link_down(struct intel_encoder *encoder,
4410 const struct intel_crtc_state *old_crtc_state)
4412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4413 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4414 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4415 enum port port = encoder->port;
4416 u32 DP = intel_dp->DP;
4418 if (drm_WARN_ON(&dev_priv->drm,
4419 (intel_de_read(dev_priv, intel_dp->output_reg) &
4423 drm_dbg_kms(&dev_priv->drm, "\n");
4425 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4426 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4427 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4428 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4430 DP &= ~DP_LINK_TRAIN_MASK;
4431 DP |= DP_LINK_TRAIN_PAT_IDLE;
4433 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4434 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4436 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4437 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4438 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4441 * HW workaround for IBX, we need to move the port
4442 * to transcoder A after disabling it to allow the
4443 * matching HDMI port to be enabled on transcoder A.
4445 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4447 * We get CPU/PCH FIFO underruns on the other pipe when
4448 * doing the workaround. Sweep them under the rug.
4450 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4451 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4453 /* always enable with pattern 1 (as per spec) */
4454 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4455 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4456 DP_LINK_TRAIN_PAT_1;
4457 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4458 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4461 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4462 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4464 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4465 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4466 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4469 msleep(intel_dp->panel_power_down_delay);
4473 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4474 intel_wakeref_t wakeref;
4476 with_pps_lock(intel_dp, wakeref)
4477 intel_dp->active_pipe = INVALID_PIPE;
4482 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4484 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4488 * Prior to DP1.3 the bit represented by
4489 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4490 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4491 * the true capability of the panel. The only way to check is to
4492 * then compare 0000h and 2200h.
4494 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4495 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4498 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4499 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4501 "DPCD failed read at extended capabilities\n");
4505 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4506 drm_dbg_kms(&i915->drm,
4507 "DPCD extended DPCD rev less than base DPCD rev\n");
4511 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4514 drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4515 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4517 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4521 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4523 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4525 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4526 sizeof(intel_dp->dpcd)) < 0)
4527 return false; /* aux transfer failed */
4529 intel_dp_extended_receiver_capabilities(intel_dp);
4531 drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4534 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4537 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4541 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4544 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4547 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4549 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4552 * Clear the cached register set to avoid using stale values
4553 * for the sinks that do not support DSC.
4555 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4557 /* Clear fec_capable to avoid using stale values */
4558 intel_dp->fec_capable = 0;
4560 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4561 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4562 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4563 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4565 sizeof(intel_dp->dsc_dpcd)) < 0)
4567 "Failed to read DPCD register 0x%x\n",
4570 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4571 (int)sizeof(intel_dp->dsc_dpcd),
4572 intel_dp->dsc_dpcd);
4574 /* FEC is supported only on DP 1.4 */
4575 if (!intel_dp_is_edp(intel_dp) &&
4576 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4577 &intel_dp->fec_capable) < 0)
4579 "Failed to read FEC DPCD register\n");
4581 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4582 intel_dp->fec_capable);
4587 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4589 struct drm_i915_private *dev_priv =
4590 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4592 /* this function is meant to be called only once */
4593 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4595 if (!intel_dp_read_dpcd(intel_dp))
4598 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4599 drm_dp_is_branch(intel_dp->dpcd));
4602 * Read the eDP display control registers.
4604 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4605 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4606 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4607 * method). The display control registers should read zero if they're
4608 * not supported anyway.
4610 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4611 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4612 sizeof(intel_dp->edp_dpcd))
4613 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4614 (int)sizeof(intel_dp->edp_dpcd),
4615 intel_dp->edp_dpcd);
4618 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4619 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4621 intel_psr_init_dpcd(intel_dp);
4623 /* Read the eDP 1.4+ supported link rates. */
4624 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4625 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4628 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4629 sink_rates, sizeof(sink_rates));
4631 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4632 int val = le16_to_cpu(sink_rates[i]);
4637 /* Value read multiplied by 200kHz gives the per-lane
4638 * link rate in kHz. The source rates are, however,
4639 * stored in terms of LS_Clk kHz. The full conversion
4640 * back to symbols is
4641 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4643 intel_dp->sink_rates[i] = (val * 200) / 10;
4645 intel_dp->num_sink_rates = i;
4649 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4650 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4652 if (intel_dp->num_sink_rates)
4653 intel_dp->use_rate_select = true;
4655 intel_dp_set_sink_rates(intel_dp);
4657 intel_dp_set_common_rates(intel_dp);
4659 /* Read the eDP DSC DPCD registers */
4660 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4661 intel_dp_get_dsc_sink_cap(intel_dp);
4668 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4670 if (!intel_dp_read_dpcd(intel_dp))
4674 * Don't clobber cached eDP rates. Also skip re-reading
4675 * the OUI/ID since we know it won't change.
4677 if (!intel_dp_is_edp(intel_dp)) {
4678 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4679 drm_dp_is_branch(intel_dp->dpcd));
4681 intel_dp_set_sink_rates(intel_dp);
4682 intel_dp_set_common_rates(intel_dp);
4686 * Some eDP panels do not set a valid value for sink count, that is why
4687 * it don't care about read it here and in intel_edp_init_dpcd().
4689 if (!intel_dp_is_edp(intel_dp) &&
4690 !drm_dp_has_quirk(&intel_dp->desc, 0,
4691 DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4695 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4700 * Sink count can change between short pulse hpd hence
4701 * a member variable in intel_dp will track any changes
4702 * between short pulse interrupts.
4704 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4707 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4708 * a dongle is present but no display. Unless we require to know
4709 * if a dongle is present or not, we don't need to update
4710 * downstream port information. So, an early return here saves
4711 * time from performing other operations which are not required.
4713 if (!intel_dp->sink_count)
4717 if (!drm_dp_is_branch(intel_dp->dpcd))
4718 return true; /* native DP sink */
4720 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4721 return true; /* no per-port downstream info */
4723 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4724 intel_dp->downstream_ports,
4725 DP_MAX_DOWNSTREAM_PORTS) < 0)
4726 return false; /* downstream port status fetch failed */
4732 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4736 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4739 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4742 return mstm_cap & DP_MST_CAP;
4746 intel_dp_can_mst(struct intel_dp *intel_dp)
4748 return i915_modparams.enable_dp_mst &&
4749 intel_dp->can_mst &&
4750 intel_dp_sink_can_mst(intel_dp);
4754 intel_dp_configure_mst(struct intel_dp *intel_dp)
4756 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4757 struct intel_encoder *encoder =
4758 &dp_to_dig_port(intel_dp)->base;
4759 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4761 drm_dbg_kms(&i915->drm,
4762 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4763 encoder->base.base.id, encoder->base.name,
4764 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4765 yesno(i915_modparams.enable_dp_mst));
4767 if (!intel_dp->can_mst)
4770 intel_dp->is_mst = sink_can_mst &&
4771 i915_modparams.enable_dp_mst;
4773 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4778 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4780 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4781 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4786 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4787 const struct drm_connector_state *conn_state)
4790 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4791 * of Color Encoding Format and Content Color Gamut], in order to
4792 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4794 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4797 switch (conn_state->colorspace) {
4798 case DRM_MODE_COLORIMETRY_SYCC_601:
4799 case DRM_MODE_COLORIMETRY_OPYCC_601:
4800 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4801 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4802 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4811 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4812 struct dp_sdp *sdp, size_t size)
4814 size_t length = sizeof(struct dp_sdp);
4819 memset(sdp, 0, size);
4822 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4823 * VSC SDP Header Bytes
4825 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4826 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4827 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4828 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4831 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
4834 if (vsc->revision != 0x5)
4837 /* VSC SDP Payload for DB16 through DB18 */
4838 /* Pixel Encoding and Colorimetry Formats */
4839 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4840 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4847 sdp->db[17] = 0x1; /* DB17[3:0] */
4859 MISSING_CASE(vsc->bpc);
4862 /* Dynamic Range and Component Bit Depth */
4863 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4864 sdp->db[17] |= 0x80; /* DB17[7] */
4867 sdp->db[18] = vsc->content_type & 0x7;
4874 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4878 size_t length = sizeof(struct dp_sdp);
4879 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4880 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4886 memset(sdp, 0, size);
4888 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4890 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4894 if (len != infoframe_size) {
4895 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4900 * Set up the infoframe sdp packet for HDR static metadata.
4901 * Prepare VSC Header for SU as per DP 1.4a spec,
4902 * Table 2-100 and Table 2-101
4905 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4906 sdp->sdp_header.HB0 = 0;
4908 * Packet Type 80h + Non-audio INFOFRAME Type value
4909 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4910 * - 80h + Non-audio INFOFRAME Type value
4911 * - InfoFrame Type: 0x07
4912 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4914 sdp->sdp_header.HB1 = drm_infoframe->type;
4916 * Least Significant Eight Bits of (Data Byte Count – 1)
4917 * infoframe_size - 1
4919 sdp->sdp_header.HB2 = 0x1D;
4920 /* INFOFRAME SDP Version Number */
4921 sdp->sdp_header.HB3 = (0x13 << 2);
4922 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4923 sdp->db[0] = drm_infoframe->version;
4924 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4925 sdp->db[1] = drm_infoframe->length;
4927 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4928 * HDMI_INFOFRAME_HEADER_SIZE
4930 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4931 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4932 HDMI_DRM_INFOFRAME_SIZE);
4935 * Size of DP infoframe sdp packet for HDR static metadata consists of
4936 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4937 * - Two Data Blocks: 2 bytes
4938 * CTA Header Byte2 (INFOFRAME Version Number)
4939 * CTA Header Byte3 (Length of INFOFRAME)
4940 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4942 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4943 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4944 * will pad rest of the size.
4946 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4949 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4950 const struct intel_crtc_state *crtc_state,
4953 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4955 struct dp_sdp sdp = {};
4958 if ((crtc_state->infoframes.enable &
4959 intel_hdmi_infoframe_enable(type)) == 0)
4964 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4967 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4968 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4976 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4979 intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4982 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4983 const struct intel_crtc_state *crtc_state,
4984 struct drm_dp_vsc_sdp *vsc)
4986 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4987 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4988 struct dp_sdp sdp = {};
4991 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4993 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4996 intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5000 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5002 const struct intel_crtc_state *crtc_state,
5003 const struct drm_connector_state *conn_state)
5005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5006 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5007 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5008 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5009 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5010 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5011 u32 val = intel_de_read(dev_priv, reg);
5013 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5014 /* When PSR is enabled, this routine doesn't disable VSC DIP */
5015 if (intel_psr_enabled(intel_dp))
5018 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5021 intel_de_write(dev_priv, reg, val);
5022 intel_de_posting_read(dev_priv, reg);
5026 intel_de_write(dev_priv, reg, val);
5027 intel_de_posting_read(dev_priv, reg);
5029 /* When PSR is enabled, VSC SDP is handled by PSR routine */
5030 if (!intel_psr_enabled(intel_dp))
5031 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5033 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5036 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5037 const void *buffer, size_t size)
5039 const struct dp_sdp *sdp = buffer;
5041 if (size < sizeof(struct dp_sdp))
5044 memset(vsc, 0, size);
5046 if (sdp->sdp_header.HB0 != 0)
5049 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5052 vsc->sdp_type = sdp->sdp_header.HB1;
5053 vsc->revision = sdp->sdp_header.HB2;
5054 vsc->length = sdp->sdp_header.HB3;
5056 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5057 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5059 * - HB2 = 0x2, HB3 = 0x8
5060 * VSC SDP supporting 3D stereo + PSR
5061 * - HB2 = 0x4, HB3 = 0xe
5062 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5063 * first scan line of the SU region (applies to eDP v1.4b
5067 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5069 * - HB2 = 0x5, HB3 = 0x13
5070 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5073 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5074 vsc->colorimetry = sdp->db[16] & 0xf;
5075 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5077 switch (sdp->db[17] & 0x7) {
5094 MISSING_CASE(sdp->db[17] & 0x7);
5098 vsc->content_type = sdp->db[18] & 0x7;
5107 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5108 const void *buffer, size_t size)
5112 const struct dp_sdp *sdp = buffer;
5114 if (size < sizeof(struct dp_sdp))
5117 if (sdp->sdp_header.HB0 != 0)
5120 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5124 * Least Significant Eight Bits of (Data Byte Count – 1)
5125 * 1Dh (i.e., Data Byte Count = 30 bytes).
5127 if (sdp->sdp_header.HB2 != 0x1D)
5130 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5131 if ((sdp->sdp_header.HB3 & 0x3) != 0)
5134 /* INFOFRAME SDP Version Number */
5135 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5138 /* CTA Header Byte 2 (INFOFRAME Version Number) */
5139 if (sdp->db[0] != 1)
5142 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5143 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5146 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5147 HDMI_DRM_INFOFRAME_SIZE);
5152 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5153 struct intel_crtc_state *crtc_state,
5154 struct drm_dp_vsc_sdp *vsc)
5156 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5157 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5158 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5159 unsigned int type = DP_SDP_VSC;
5160 struct dp_sdp sdp = {};
5163 /* When PSR is enabled, VSC SDP is handled by PSR routine */
5164 if (intel_psr_enabled(intel_dp))
5167 if ((crtc_state->infoframes.enable &
5168 intel_hdmi_infoframe_enable(type)) == 0)
5171 intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5173 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5176 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5179 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5180 struct intel_crtc_state *crtc_state,
5181 struct hdmi_drm_infoframe *drm_infoframe)
5183 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5185 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5186 struct dp_sdp sdp = {};
5189 if ((crtc_state->infoframes.enable &
5190 intel_hdmi_infoframe_enable(type)) == 0)
5193 intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5196 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5200 drm_dbg_kms(&dev_priv->drm,
5201 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5204 void intel_read_dp_sdp(struct intel_encoder *encoder,
5205 struct intel_crtc_state *crtc_state,
5210 intel_read_dp_vsc_sdp(encoder, crtc_state,
5211 &crtc_state->infoframes.vsc);
5213 case HDMI_PACKET_TYPE_GAMUT_METADATA:
5214 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5215 &crtc_state->infoframes.drm.drm);
5223 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5225 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5228 u8 test_lane_count, test_link_bw;
5232 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5233 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5237 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5240 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5242 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5245 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5248 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5250 /* Validate the requested link rate and lane count */
5251 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5255 intel_dp->compliance.test_lane_count = test_lane_count;
5256 intel_dp->compliance.test_link_rate = test_link_rate;
5261 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5263 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5266 __be16 h_width, v_height;
5269 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5270 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5273 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5276 if (test_pattern != DP_COLOR_RAMP)
5279 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5282 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5286 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5289 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5293 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5296 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5299 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5301 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5303 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5304 case DP_TEST_BIT_DEPTH_6:
5305 intel_dp->compliance.test_data.bpc = 6;
5307 case DP_TEST_BIT_DEPTH_8:
5308 intel_dp->compliance.test_data.bpc = 8;
5314 intel_dp->compliance.test_data.video_pattern = test_pattern;
5315 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5316 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5317 /* Set test active flag here so userspace doesn't interrupt things */
5318 intel_dp->compliance.test_active = true;
5323 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5325 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5326 u8 test_result = DP_TEST_ACK;
5327 struct intel_connector *intel_connector = intel_dp->attached_connector;
5328 struct drm_connector *connector = &intel_connector->base;
5330 if (intel_connector->detect_edid == NULL ||
5331 connector->edid_corrupt ||
5332 intel_dp->aux.i2c_defer_count > 6) {
5333 /* Check EDID read for NACKs, DEFERs and corruption
5334 * (DP CTS 1.2 Core r1.1)
5335 * 4.2.2.4 : Failed EDID read, I2C_NAK
5336 * 4.2.2.5 : Failed EDID read, I2C_DEFER
5337 * 4.2.2.6 : EDID corruption detected
5338 * Use failsafe mode for all cases
5340 if (intel_dp->aux.i2c_nack_count > 0 ||
5341 intel_dp->aux.i2c_defer_count > 0)
5342 drm_dbg_kms(&i915->drm,
5343 "EDID read had %d NACKs, %d DEFERs\n",
5344 intel_dp->aux.i2c_nack_count,
5345 intel_dp->aux.i2c_defer_count);
5346 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5348 struct edid *block = intel_connector->detect_edid;
5350 /* We have to write the checksum
5351 * of the last block read
5353 block += intel_connector->detect_edid->extensions;
5355 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5356 block->checksum) <= 0)
5357 drm_dbg_kms(&i915->drm,
5358 "Failed to write EDID checksum\n");
5360 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5361 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5364 /* Set test active flag here so userspace doesn't interrupt things */
5365 intel_dp->compliance.test_active = true;
5370 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5372 struct drm_dp_phy_test_params *data =
5373 &intel_dp->compliance.test_data.phytest;
5375 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5376 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5381 * link_mst is set to false to avoid executing mst related code
5382 * during compliance testing.
5384 intel_dp->link_mst = false;
5389 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5391 struct drm_i915_private *dev_priv =
5392 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5394 struct drm_dp_phy_test_params *data =
5395 &intel_dp->compliance.test_data.phytest;
5396 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5397 enum pipe pipe = crtc->pipe;
5400 switch (data->phy_pattern) {
5401 case DP_PHY_TEST_PATTERN_NONE:
5402 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5403 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5405 case DP_PHY_TEST_PATTERN_D10_2:
5406 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5407 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5408 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5410 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5411 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5412 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5413 DDI_DP_COMP_CTL_ENABLE |
5414 DDI_DP_COMP_CTL_SCRAMBLED_0);
5416 case DP_PHY_TEST_PATTERN_PRBS7:
5417 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5418 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5419 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5421 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5423 * FIXME: Ideally pattern should come from DPCD 0x250. As
5424 * current firmware of DPR-100 could not set it, so hardcoding
5425 * now for complaince test.
5427 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5428 pattern_val = 0x3e0f83e0;
5429 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5430 pattern_val = 0x0f83e0f8;
5431 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5432 pattern_val = 0x0000f83e;
5433 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5434 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5435 DDI_DP_COMP_CTL_ENABLE |
5436 DDI_DP_COMP_CTL_CUSTOM80);
5438 case DP_PHY_TEST_PATTERN_CP2520:
5440 * FIXME: Ideally pattern should come from DPCD 0x24A. As
5441 * current firmware of DPR-100 could not set it, so hardcoding
5442 * now for complaince test.
5444 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5446 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5447 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5451 WARN(1, "Invalid Phy Test Pattern\n");
5456 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5458 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5459 struct drm_device *dev = intel_dig_port->base.base.dev;
5460 struct drm_i915_private *dev_priv = to_i915(dev);
5461 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5462 enum pipe pipe = crtc->pipe;
5463 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5465 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5466 TRANS_DDI_FUNC_CTL(pipe));
5467 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5468 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5470 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5471 TGL_TRANS_DDI_PORT_MASK);
5472 trans_conf_value &= ~PIPECONF_ENABLE;
5473 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5475 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5476 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5477 trans_ddi_func_ctl_value);
5478 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5482 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5484 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5485 struct drm_device *dev = intel_dig_port->base.base.dev;
5486 struct drm_i915_private *dev_priv = to_i915(dev);
5487 enum port port = intel_dig_port->base.port;
5488 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5489 enum pipe pipe = crtc->pipe;
5490 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5492 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5493 TRANS_DDI_FUNC_CTL(pipe));
5494 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5495 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5497 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5498 TGL_TRANS_DDI_SELECT_PORT(port);
5499 trans_conf_value |= PIPECONF_ENABLE;
5500 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5502 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5503 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5504 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5505 trans_ddi_func_ctl_value);
5508 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5510 struct drm_dp_phy_test_params *data =
5511 &intel_dp->compliance.test_data.phytest;
5512 u8 link_status[DP_LINK_STATUS_SIZE];
5514 if (!intel_dp_get_link_status(intel_dp, link_status)) {
5515 DRM_DEBUG_KMS("failed to get link status\n");
5519 /* retrieve vswing & pre-emphasis setting */
5520 intel_dp_get_adjust_train(intel_dp, link_status);
5522 intel_dp_autotest_phy_ddi_disable(intel_dp);
5524 intel_dp_set_signal_levels(intel_dp);
5526 intel_dp_phy_pattern_update(intel_dp);
5528 intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5530 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5531 link_status[DP_DPCD_REV]);
5534 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5538 test_result = intel_dp_prepare_phytest(intel_dp);
5539 if (test_result != DP_TEST_ACK)
5540 DRM_ERROR("Phy test preparation failed\n");
5542 intel_dp_process_phy_request(intel_dp);
5547 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5549 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5550 u8 response = DP_TEST_NAK;
5554 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5556 drm_dbg_kms(&i915->drm,
5557 "Could not read test request from sink\n");
5562 case DP_TEST_LINK_TRAINING:
5563 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5564 response = intel_dp_autotest_link_training(intel_dp);
5566 case DP_TEST_LINK_VIDEO_PATTERN:
5567 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5568 response = intel_dp_autotest_video_pattern(intel_dp);
5570 case DP_TEST_LINK_EDID_READ:
5571 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5572 response = intel_dp_autotest_edid(intel_dp);
5574 case DP_TEST_LINK_PHY_TEST_PATTERN:
5575 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5576 response = intel_dp_autotest_phy_pattern(intel_dp);
5579 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5584 if (response & DP_TEST_ACK)
5585 intel_dp->compliance.test_type = request;
5588 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5590 drm_dbg_kms(&i915->drm,
5591 "Could not write test response to sink\n");
5595 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5597 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5598 bool need_retrain = false;
5600 if (!intel_dp->is_mst)
5603 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5606 u8 esi[DP_DPRX_ESI_LEN] = {};
5610 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5612 drm_dbg_kms(&i915->drm,
5613 "failed to get ESI - device may have failed\n");
5617 /* check link status - esi[10] = 0x200c */
5618 if (intel_dp->active_mst_links > 0 && !need_retrain &&
5619 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5620 drm_dbg_kms(&i915->drm,
5621 "channel EQ not ok, retraining\n");
5622 need_retrain = true;
5625 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5627 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5631 for (retry = 0; retry < 3; retry++) {
5634 wret = drm_dp_dpcd_write(&intel_dp->aux,
5635 DP_SINK_COUNT_ESI+1,
5642 return need_retrain;
5646 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5648 u8 link_status[DP_LINK_STATUS_SIZE];
5650 if (!intel_dp->link_trained)
5654 * While PSR source HW is enabled, it will control main-link sending
5655 * frames, enabling and disabling it so trying to do a retrain will fail
5656 * as the link would or not be on or it could mix training patterns
5657 * and frame data at the same time causing retrain to fail.
5658 * Also when exiting PSR, HW will retrain the link anyways fixing
5659 * any link status error.
5661 if (intel_psr_enabled(intel_dp))
5664 if (!intel_dp_get_link_status(intel_dp, link_status))
5668 * Validate the cached values of intel_dp->link_rate and
5669 * intel_dp->lane_count before attempting to retrain.
5671 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5672 intel_dp->lane_count))
5675 /* Retrain if Channel EQ or CR not ok */
5676 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5679 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5680 const struct drm_connector_state *conn_state)
5682 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5683 struct intel_encoder *encoder;
5686 if (!conn_state->best_encoder)
5690 encoder = &dp_to_dig_port(intel_dp)->base;
5691 if (conn_state->best_encoder == &encoder->base)
5695 for_each_pipe(i915, pipe) {
5696 encoder = &intel_dp->mst_encoders[pipe]->base;
5697 if (conn_state->best_encoder == &encoder->base)
5704 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5705 struct drm_modeset_acquire_ctx *ctx,
5708 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5709 struct drm_connector_list_iter conn_iter;
5710 struct intel_connector *connector;
5715 if (!intel_dp_needs_link_retrain(intel_dp))
5718 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5719 for_each_intel_connector_iter(connector, &conn_iter) {
5720 struct drm_connector_state *conn_state =
5721 connector->base.state;
5722 struct intel_crtc_state *crtc_state;
5723 struct intel_crtc *crtc;
5725 if (!intel_dp_has_connector(intel_dp, conn_state))
5728 crtc = to_intel_crtc(conn_state->crtc);
5732 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5736 crtc_state = to_intel_crtc_state(crtc->base.state);
5738 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5740 if (!crtc_state->hw.active)
5743 if (conn_state->commit &&
5744 !try_wait_for_completion(&conn_state->commit->hw_done))
5747 *crtc_mask |= drm_crtc_mask(&crtc->base);
5749 drm_connector_list_iter_end(&conn_iter);
5751 if (!intel_dp_needs_link_retrain(intel_dp))
5757 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5759 struct intel_connector *connector = intel_dp->attached_connector;
5761 return connector->base.status == connector_status_connected ||
5765 int intel_dp_retrain_link(struct intel_encoder *encoder,
5766 struct drm_modeset_acquire_ctx *ctx)
5768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5769 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5770 struct intel_crtc *crtc;
5774 if (!intel_dp_is_connected(intel_dp))
5777 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5782 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5789 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5790 encoder->base.base.id, encoder->base.name);
5792 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5793 const struct intel_crtc_state *crtc_state =
5794 to_intel_crtc_state(crtc->base.state);
5796 /* Suppress underruns caused by re-training */
5797 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5798 if (crtc_state->has_pch_encoder)
5799 intel_set_pch_fifo_underrun_reporting(dev_priv,
5800 intel_crtc_pch_transcoder(crtc), false);
5803 intel_dp_start_link_train(intel_dp);
5804 intel_dp_stop_link_train(intel_dp);
5806 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5807 const struct intel_crtc_state *crtc_state =
5808 to_intel_crtc_state(crtc->base.state);
5810 /* Keep underrun reporting disabled until things are stable */
5811 intel_wait_for_vblank(dev_priv, crtc->pipe);
5813 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5814 if (crtc_state->has_pch_encoder)
5815 intel_set_pch_fifo_underrun_reporting(dev_priv,
5816 intel_crtc_pch_transcoder(crtc), true);
5823 * If display is now connected check links status,
5824 * there has been known issues of link loss triggering
5827 * Some sinks (eg. ASUS PB287Q) seem to perform some
5828 * weird HPD ping pong during modesets. So we can apparently
5829 * end up with HPD going low during a modeset, and then
5830 * going back up soon after. And once that happens we must
5831 * retrain the link to get a picture. That's in case no
5832 * userspace component reacted to intermittent HPD dip.
5834 static enum intel_hotplug_state
5835 intel_dp_hotplug(struct intel_encoder *encoder,
5836 struct intel_connector *connector)
5838 struct drm_modeset_acquire_ctx ctx;
5839 enum intel_hotplug_state state;
5842 state = intel_encoder_hotplug(encoder, connector);
5844 drm_modeset_acquire_init(&ctx, 0);
5847 ret = intel_dp_retrain_link(encoder, &ctx);
5849 if (ret == -EDEADLK) {
5850 drm_modeset_backoff(&ctx);
5857 drm_modeset_drop_locks(&ctx);
5858 drm_modeset_acquire_fini(&ctx);
5859 drm_WARN(encoder->base.dev, ret,
5860 "Acquiring modeset locks failed with %i\n", ret);
5863 * Keeping it consistent with intel_ddi_hotplug() and
5864 * intel_hdmi_hotplug().
5866 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5867 state = INTEL_HOTPLUG_RETRY;
5872 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5874 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5877 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5880 if (drm_dp_dpcd_readb(&intel_dp->aux,
5881 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5884 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5886 if (val & DP_AUTOMATED_TEST_REQUEST)
5887 intel_dp_handle_test_request(intel_dp);
5889 if (val & DP_CP_IRQ)
5890 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5892 if (val & DP_SINK_SPECIFIC_IRQ)
5893 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5897 * According to DP spec
5900 * 2. Configure link according to Receiver Capabilities
5901 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5902 * 4. Check link status on receipt of hot-plug interrupt
5904 * intel_dp_short_pulse - handles short pulse interrupts
5905 * when full detection is not required.
5906 * Returns %true if short pulse is handled and full detection
5907 * is NOT required and %false otherwise.
5910 intel_dp_short_pulse(struct intel_dp *intel_dp)
5912 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5913 u8 old_sink_count = intel_dp->sink_count;
5917 * Clearing compliance test variables to allow capturing
5918 * of values for next automated test request.
5920 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5923 * Now read the DPCD to see if it's actually running
5924 * If the current value of sink count doesn't match with
5925 * the value that was stored earlier or dpcd read failed
5926 * we need to do full detection
5928 ret = intel_dp_get_dpcd(intel_dp);
5930 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5931 /* No need to proceed if we are going to do full detect */
5935 intel_dp_check_service_irq(intel_dp);
5937 /* Handle CEC interrupts, if any */
5938 drm_dp_cec_irq(&intel_dp->aux);
5940 /* defer to the hotplug work for link retraining if needed */
5941 if (intel_dp_needs_link_retrain(intel_dp))
5944 intel_psr_short_pulse(intel_dp);
5946 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5947 drm_dbg_kms(&dev_priv->drm,
5948 "Link Training Compliance Test requested\n");
5949 /* Send a Hotplug Uevent to userspace to start modeset */
5950 drm_kms_helper_hotplug_event(&dev_priv->drm);
5956 /* XXX this is probably wrong for multiple downstream ports */
5957 static enum drm_connector_status
5958 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5960 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5961 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5962 u8 *dpcd = intel_dp->dpcd;
5965 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5966 return connector_status_connected;
5969 lspcon_resume(lspcon);
5971 if (!intel_dp_get_dpcd(intel_dp))
5972 return connector_status_disconnected;
5974 /* if there's no downstream port, we're done */
5975 if (!drm_dp_is_branch(dpcd))
5976 return connector_status_connected;
5978 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5979 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5980 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5982 return intel_dp->sink_count ?
5983 connector_status_connected : connector_status_disconnected;
5986 if (intel_dp_can_mst(intel_dp))
5987 return connector_status_connected;
5989 /* If no HPD, poke DDC gently */
5990 if (drm_probe_ddc(&intel_dp->aux.ddc))
5991 return connector_status_connected;
5993 /* Well we tried, say unknown for unreliable port types */
5994 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5995 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5996 if (type == DP_DS_PORT_TYPE_VGA ||
5997 type == DP_DS_PORT_TYPE_NON_EDID)
5998 return connector_status_unknown;
6000 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6001 DP_DWN_STRM_PORT_TYPE_MASK;
6002 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6003 type == DP_DWN_STRM_PORT_TYPE_OTHER)
6004 return connector_status_unknown;
6007 /* Anything else is out of spec, warn and ignore */
6008 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6009 return connector_status_disconnected;
6012 static enum drm_connector_status
6013 edp_detect(struct intel_dp *intel_dp)
6015 return connector_status_connected;
6018 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6020 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6021 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6023 return intel_de_read(dev_priv, SDEISR) & bit;
6026 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6028 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6031 switch (encoder->hpd_pin) {
6033 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6036 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6039 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6042 MISSING_CASE(encoder->hpd_pin);
6046 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6049 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6054 switch (encoder->hpd_pin) {
6056 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6059 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6062 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6065 MISSING_CASE(encoder->hpd_pin);
6069 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6072 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6075 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6077 return intel_de_read(dev_priv, DEISR) & bit;
6081 * intel_digital_port_connected - is the specified port connected?
6082 * @encoder: intel_encoder
6084 * In cases where there's a connector physically connected but it can't be used
6085 * by our hardware we also return false, since the rest of the driver should
6086 * pretty much treat the port as disconnected. This is relevant for type-C
6087 * (starting on ICL) where there's ownership involved.
6089 * Return %true if port is connected, %false otherwise.
6091 bool intel_digital_port_connected(struct intel_encoder *encoder)
6093 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6094 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6095 bool is_connected = false;
6096 intel_wakeref_t wakeref;
6098 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6099 is_connected = dig_port->connected(encoder);
6101 return is_connected;
6104 static struct edid *
6105 intel_dp_get_edid(struct intel_dp *intel_dp)
6107 struct intel_connector *intel_connector = intel_dp->attached_connector;
6109 /* use cached edid if we have one */
6110 if (intel_connector->edid) {
6112 if (IS_ERR(intel_connector->edid))
6115 return drm_edid_duplicate(intel_connector->edid);
6117 return drm_get_edid(&intel_connector->base,
6118 &intel_dp->aux.ddc);
6122 intel_dp_set_edid(struct intel_dp *intel_dp)
6124 struct intel_connector *intel_connector = intel_dp->attached_connector;
6127 intel_dp_unset_edid(intel_dp);
6128 edid = intel_dp_get_edid(intel_dp);
6129 intel_connector->detect_edid = edid;
6131 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6132 drm_dp_cec_set_edid(&intel_dp->aux, edid);
6133 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6137 intel_dp_unset_edid(struct intel_dp *intel_dp)
6139 struct intel_connector *intel_connector = intel_dp->attached_connector;
6141 drm_dp_cec_unset_edid(&intel_dp->aux);
6142 kfree(intel_connector->detect_edid);
6143 intel_connector->detect_edid = NULL;
6145 intel_dp->has_audio = false;
6146 intel_dp->edid_quirks = 0;
6150 intel_dp_detect(struct drm_connector *connector,
6151 struct drm_modeset_acquire_ctx *ctx,
6154 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6155 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6156 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6157 struct intel_encoder *encoder = &dig_port->base;
6158 enum drm_connector_status status;
6160 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6161 connector->base.id, connector->name);
6162 drm_WARN_ON(&dev_priv->drm,
6163 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6165 /* Can't disconnect eDP */
6166 if (intel_dp_is_edp(intel_dp))
6167 status = edp_detect(intel_dp);
6168 else if (intel_digital_port_connected(encoder))
6169 status = intel_dp_detect_dpcd(intel_dp);
6171 status = connector_status_disconnected;
6173 if (status == connector_status_disconnected) {
6174 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6175 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6177 if (intel_dp->is_mst) {
6178 drm_dbg_kms(&dev_priv->drm,
6179 "MST device may have disappeared %d vs %d\n",
6181 intel_dp->mst_mgr.mst_state);
6182 intel_dp->is_mst = false;
6183 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6190 if (intel_dp->reset_link_params) {
6191 /* Initial max link lane count */
6192 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6194 /* Initial max link rate */
6195 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6197 intel_dp->reset_link_params = false;
6200 intel_dp_print_rates(intel_dp);
6202 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6203 if (INTEL_GEN(dev_priv) >= 11)
6204 intel_dp_get_dsc_sink_cap(intel_dp);
6206 intel_dp_configure_mst(intel_dp);
6208 if (intel_dp->is_mst) {
6210 * If we are in MST mode then this connector
6211 * won't appear connected or have anything
6214 status = connector_status_disconnected;
6219 * Some external monitors do not signal loss of link synchronization
6220 * with an IRQ_HPD, so force a link status check.
6222 if (!intel_dp_is_edp(intel_dp)) {
6225 ret = intel_dp_retrain_link(encoder, ctx);
6231 * Clearing NACK and defer counts to get their exact values
6232 * while reading EDID which are required by Compliance tests
6233 * 4.2.2.4 and 4.2.2.5
6235 intel_dp->aux.i2c_nack_count = 0;
6236 intel_dp->aux.i2c_defer_count = 0;
6238 intel_dp_set_edid(intel_dp);
6239 if (intel_dp_is_edp(intel_dp) ||
6240 to_intel_connector(connector)->detect_edid)
6241 status = connector_status_connected;
6243 intel_dp_check_service_irq(intel_dp);
6246 if (status != connector_status_connected && !intel_dp->is_mst)
6247 intel_dp_unset_edid(intel_dp);
6250 * Make sure the refs for power wells enabled during detect are
6251 * dropped to avoid a new detect cycle triggered by HPD polling.
6253 intel_display_power_flush_work(dev_priv);
6259 intel_dp_force(struct drm_connector *connector)
6261 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6262 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6263 struct intel_encoder *intel_encoder = &dig_port->base;
6264 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6265 enum intel_display_power_domain aux_domain =
6266 intel_aux_power_domain(dig_port);
6267 intel_wakeref_t wakeref;
6269 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6270 connector->base.id, connector->name);
6271 intel_dp_unset_edid(intel_dp);
6273 if (connector->status != connector_status_connected)
6276 wakeref = intel_display_power_get(dev_priv, aux_domain);
6278 intel_dp_set_edid(intel_dp);
6280 intel_display_power_put(dev_priv, aux_domain, wakeref);
6283 static int intel_dp_get_modes(struct drm_connector *connector)
6285 struct intel_connector *intel_connector = to_intel_connector(connector);
6288 edid = intel_connector->detect_edid;
6290 int ret = intel_connector_update_modes(connector, edid);
6295 /* if eDP has no EDID, fall back to fixed mode */
6296 if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6297 intel_connector->panel.fixed_mode) {
6298 struct drm_display_mode *mode;
6300 mode = drm_mode_duplicate(connector->dev,
6301 intel_connector->panel.fixed_mode);
6303 drm_mode_probed_add(connector, mode);
6312 intel_dp_connector_register(struct drm_connector *connector)
6314 struct drm_i915_private *i915 = to_i915(connector->dev);
6315 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6318 ret = intel_connector_register(connector);
6322 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6323 intel_dp->aux.name, connector->kdev->kobj.name);
6325 intel_dp->aux.dev = connector->kdev;
6326 ret = drm_dp_aux_register(&intel_dp->aux);
6328 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6333 intel_dp_connector_unregister(struct drm_connector *connector)
6335 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6337 drm_dp_cec_unregister_connector(&intel_dp->aux);
6338 drm_dp_aux_unregister(&intel_dp->aux);
6339 intel_connector_unregister(connector);
6342 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6344 struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6345 struct intel_dp *intel_dp = &intel_dig_port->dp;
6347 intel_dp_mst_encoder_cleanup(intel_dig_port);
6348 if (intel_dp_is_edp(intel_dp)) {
6349 intel_wakeref_t wakeref;
6351 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6353 * vdd might still be enabled do to the delayed vdd off.
6354 * Make sure vdd is actually turned off here.
6356 with_pps_lock(intel_dp, wakeref)
6357 edp_panel_vdd_off_sync(intel_dp);
6359 if (intel_dp->edp_notifier.notifier_call) {
6360 unregister_reboot_notifier(&intel_dp->edp_notifier);
6361 intel_dp->edp_notifier.notifier_call = NULL;
6365 intel_dp_aux_fini(intel_dp);
6368 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6370 intel_dp_encoder_flush_work(encoder);
6372 drm_encoder_cleanup(encoder);
6373 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6376 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6378 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6379 intel_wakeref_t wakeref;
6381 if (!intel_dp_is_edp(intel_dp))
6385 * vdd might still be enabled do to the delayed vdd off.
6386 * Make sure vdd is actually turned off here.
6388 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6389 with_pps_lock(intel_dp, wakeref)
6390 edp_panel_vdd_off_sync(intel_dp);
6393 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6397 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6398 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6399 msecs_to_jiffies(timeout));
6402 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6406 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6409 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6410 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6411 static const struct drm_dp_aux_msg msg = {
6412 .request = DP_AUX_NATIVE_WRITE,
6413 .address = DP_AUX_HDCP_AKSV,
6414 .size = DRM_HDCP_KSV_LEN,
6416 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6420 /* Output An first, that's easy */
6421 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6422 an, DRM_HDCP_AN_LEN);
6423 if (dpcd_ret != DRM_HDCP_AN_LEN) {
6424 drm_dbg_kms(&i915->drm,
6425 "Failed to write An over DP/AUX (%zd)\n",
6427 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6431 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6432 * order to get it on the wire, we need to create the AUX header as if
6433 * we were writing the data, and then tickle the hardware to output the
6434 * data once the header is sent out.
6436 intel_dp_aux_header(txbuf, &msg);
6438 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6439 rxbuf, sizeof(rxbuf),
6440 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6442 drm_dbg_kms(&i915->drm,
6443 "Write Aksv over DP/AUX failed (%d)\n", ret);
6445 } else if (ret == 0) {
6446 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6450 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6451 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6452 drm_dbg_kms(&i915->drm,
6453 "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6460 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6463 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6466 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6468 if (ret != DRM_HDCP_KSV_LEN) {
6469 drm_dbg_kms(&i915->drm,
6470 "Read Bksv from DP/AUX failed (%zd)\n", ret);
6471 return ret >= 0 ? -EIO : ret;
6476 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6479 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6483 * For some reason the HDMI and DP HDCP specs call this register
6484 * definition by different names. In the HDMI spec, it's called BSTATUS,
6485 * but in DP it's called BINFO.
6487 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6488 bstatus, DRM_HDCP_BSTATUS_LEN);
6489 if (ret != DRM_HDCP_BSTATUS_LEN) {
6490 drm_dbg_kms(&i915->drm,
6491 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6492 return ret >= 0 ? -EIO : ret;
6498 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6501 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6504 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6507 drm_dbg_kms(&i915->drm,
6508 "Read bcaps from DP/AUX failed (%zd)\n", ret);
6509 return ret >= 0 ? -EIO : ret;
6516 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6517 bool *repeater_present)
6522 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6526 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6531 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6534 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6537 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6538 ri_prime, DRM_HDCP_RI_LEN);
6539 if (ret != DRM_HDCP_RI_LEN) {
6540 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6542 return ret >= 0 ? -EIO : ret;
6548 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6551 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6555 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6558 drm_dbg_kms(&i915->drm,
6559 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6560 return ret >= 0 ? -EIO : ret;
6562 *ksv_ready = bstatus & DP_BSTATUS_READY;
6567 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6568 int num_downstream, u8 *ksv_fifo)
6570 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6574 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6575 for (i = 0; i < num_downstream; i += 3) {
6576 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6577 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6578 DP_AUX_HDCP_KSV_FIFO,
6579 ksv_fifo + i * DRM_HDCP_KSV_LEN,
6582 drm_dbg_kms(&i915->drm,
6583 "Read ksv[%d] from DP/AUX failed (%zd)\n",
6585 return ret >= 0 ? -EIO : ret;
6592 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6595 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6598 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6601 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6602 DP_AUX_HDCP_V_PRIME(i), part,
6603 DRM_HDCP_V_PRIME_PART_LEN);
6604 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6605 drm_dbg_kms(&i915->drm,
6606 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6607 return ret >= 0 ? -EIO : ret;
6613 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6616 /* Not used for single stream DisplayPort setups */
6621 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6623 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6627 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6630 drm_dbg_kms(&i915->drm,
6631 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6635 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6639 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6645 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6649 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6653 struct hdcp2_dp_errata_stream_type {
6658 struct hdcp2_dp_msg_data {
6661 bool msg_detectable;
6663 u32 timeout2; /* Added for non_paired situation */
6666 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6667 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6668 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6669 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6670 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6672 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6674 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6675 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6676 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6677 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6678 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6679 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6680 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6681 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6682 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6683 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6685 { HDCP_2_2_REP_SEND_RECVID_LIST,
6686 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6687 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6688 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6690 { HDCP_2_2_REP_STREAM_MANAGE,
6691 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6693 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6694 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6695 /* local define to shovel this through the write_2_2 interface */
6696 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
6697 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6698 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6703 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6706 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6709 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6710 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6711 HDCP_2_2_DP_RXSTATUS_LEN);
6712 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6713 drm_dbg_kms(&i915->drm,
6714 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6715 return ret >= 0 ? -EIO : ret;
6722 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6723 u8 msg_id, bool *msg_ready)
6729 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6734 case HDCP_2_2_AKE_SEND_HPRIME:
6735 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6738 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6739 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6742 case HDCP_2_2_REP_SEND_RECVID_LIST:
6743 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6747 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6755 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6756 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6758 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6759 struct intel_dp *dp = &intel_dig_port->dp;
6760 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6761 u8 msg_id = hdcp2_msg_data->msg_id;
6763 bool msg_ready = false;
6765 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6766 timeout = hdcp2_msg_data->timeout2;
6768 timeout = hdcp2_msg_data->timeout;
6771 * There is no way to detect the CERT, LPRIME and STREAM_READY
6772 * availability. So Wait for timeout and read the msg.
6774 if (!hdcp2_msg_data->msg_detectable) {
6779 * As we want to check the msg availability at timeout, Ignoring
6780 * the timeout at wait for CP_IRQ.
6782 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6783 ret = hdcp2_detect_msg_availability(intel_dig_port,
6784 msg_id, &msg_ready);
6790 drm_dbg_kms(&i915->drm,
6791 "msg_id %d, ret %d, timeout(mSec): %d\n",
6792 hdcp2_msg_data->msg_id, ret, timeout);
6797 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6801 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6802 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6803 return &hdcp2_dp_msg_data[i];
6809 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6810 void *buf, size_t size)
6812 struct intel_dp *dp = &intel_dig_port->dp;
6813 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6814 unsigned int offset;
6816 ssize_t ret, bytes_to_write, len;
6817 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6819 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6820 if (!hdcp2_msg_data)
6823 offset = hdcp2_msg_data->offset;
6825 /* No msg_id in DP HDCP2.2 msgs */
6826 bytes_to_write = size - 1;
6829 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6831 while (bytes_to_write) {
6832 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6833 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6835 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6836 offset, (void *)byte, len);
6840 bytes_to_write -= ret;
6849 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6851 u8 rx_info[HDCP_2_2_RXINFO_LEN];
6855 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6856 DP_HDCP_2_2_REG_RXINFO_OFFSET,
6857 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6858 if (ret != HDCP_2_2_RXINFO_LEN)
6859 return ret >= 0 ? -EIO : ret;
6861 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6862 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6864 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6865 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6867 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6868 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6869 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6875 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6876 u8 msg_id, void *buf, size_t size)
6878 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6879 unsigned int offset;
6881 ssize_t ret, bytes_to_recv, len;
6882 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6884 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6885 if (!hdcp2_msg_data)
6887 offset = hdcp2_msg_data->offset;
6889 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6893 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6894 ret = get_receiver_id_list_size(intel_dig_port);
6900 bytes_to_recv = size - 1;
6902 /* DP adaptation msgs has no msg_id */
6905 while (bytes_to_recv) {
6906 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6907 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6909 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6912 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
6917 bytes_to_recv -= ret;
6928 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6929 bool is_repeater, u8 content_type)
6932 struct hdcp2_dp_errata_stream_type stream_type_msg;
6938 * Errata for DP: As Stream type is used for encryption, Receiver
6939 * should be communicated with stream type for the decryption of the
6941 * Repeater will be communicated with stream type as a part of it's
6942 * auth later in time.
6944 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6945 stream_type_msg.stream_type = content_type;
6947 ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6948 sizeof(stream_type_msg));
6950 return ret < 0 ? ret : 0;
6955 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6960 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6964 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6965 ret = HDCP_REAUTH_REQUEST;
6966 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6967 ret = HDCP_LINK_INTEGRITY_FAILURE;
6968 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6969 ret = HDCP_TOPOLOGY_CHANGE;
6975 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6982 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6983 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6984 rx_caps, HDCP_2_2_RXCAPS_LEN);
6985 if (ret != HDCP_2_2_RXCAPS_LEN)
6986 return ret >= 0 ? -EIO : ret;
6988 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6989 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6995 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6996 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6997 .read_bksv = intel_dp_hdcp_read_bksv,
6998 .read_bstatus = intel_dp_hdcp_read_bstatus,
6999 .repeater_present = intel_dp_hdcp_repeater_present,
7000 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
7001 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
7002 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
7003 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
7004 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
7005 .check_link = intel_dp_hdcp_check_link,
7006 .hdcp_capable = intel_dp_hdcp_capable,
7007 .write_2_2_msg = intel_dp_hdcp2_write_msg,
7008 .read_2_2_msg = intel_dp_hdcp2_read_msg,
7009 .config_stream_type = intel_dp_hdcp2_config_stream_type,
7010 .check_2_2_link = intel_dp_hdcp2_check_link,
7011 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
7012 .protocol = HDCP_PROTOCOL_DP,
7015 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7017 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7018 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7020 lockdep_assert_held(&dev_priv->pps_mutex);
7022 if (!edp_have_panel_vdd(intel_dp))
7026 * The VDD bit needs a power domain reference, so if the bit is
7027 * already enabled when we boot or resume, grab this reference and
7028 * schedule a vdd off, so we don't hold on to the reference
7031 drm_dbg_kms(&dev_priv->drm,
7032 "VDD left on by BIOS, adjusting state tracking\n");
7033 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7035 edp_panel_vdd_schedule_off(intel_dp);
7038 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7040 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7041 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7044 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7045 encoder->port, &pipe))
7048 return INVALID_PIPE;
7051 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7053 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7054 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7055 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7056 intel_wakeref_t wakeref;
7058 if (!HAS_DDI(dev_priv))
7059 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7062 lspcon_resume(lspcon);
7064 intel_dp->reset_link_params = true;
7066 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7067 !intel_dp_is_edp(intel_dp))
7070 with_pps_lock(intel_dp, wakeref) {
7071 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7072 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7074 if (intel_dp_is_edp(intel_dp)) {
7076 * Reinit the power sequencer, in case BIOS did
7077 * something nasty with it.
7079 intel_dp_pps_init(intel_dp);
7080 intel_edp_panel_vdd_sanitize(intel_dp);
7085 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7088 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7089 struct drm_connector_list_iter conn_iter;
7090 struct drm_connector *connector;
7093 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7094 drm_for_each_connector_iter(connector, &conn_iter) {
7095 struct drm_connector_state *conn_state;
7096 struct intel_crtc_state *crtc_state;
7097 struct intel_crtc *crtc;
7099 if (!connector->has_tile ||
7100 connector->tile_group->id != tile_group_id)
7103 conn_state = drm_atomic_get_connector_state(&state->base,
7105 if (IS_ERR(conn_state)) {
7106 ret = PTR_ERR(conn_state);
7110 crtc = to_intel_crtc(conn_state->crtc);
7115 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7116 crtc_state->uapi.mode_changed = true;
7118 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7122 drm_connector_list_iter_end(&conn_iter);
7127 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7129 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7130 struct intel_crtc *crtc;
7132 if (transcoders == 0)
7135 for_each_intel_crtc(&dev_priv->drm, crtc) {
7136 struct intel_crtc_state *crtc_state;
7139 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7140 if (IS_ERR(crtc_state))
7141 return PTR_ERR(crtc_state);
7143 if (!crtc_state->hw.enable)
7146 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7149 crtc_state->uapi.mode_changed = true;
7151 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7155 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7159 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7162 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7167 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7168 struct drm_connector *connector)
7170 const struct drm_connector_state *old_conn_state =
7171 drm_atomic_get_old_connector_state(&state->base, connector);
7172 const struct intel_crtc_state *old_crtc_state;
7173 struct intel_crtc *crtc;
7176 crtc = to_intel_crtc(old_conn_state->crtc);
7180 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7182 if (!old_crtc_state->hw.active)
7185 transcoders = old_crtc_state->sync_mode_slaves_mask;
7186 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7187 transcoders |= BIT(old_crtc_state->master_transcoder);
7189 return intel_modeset_affected_transcoders(state,
7193 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7194 struct drm_atomic_state *_state)
7196 struct drm_i915_private *dev_priv = to_i915(conn->dev);
7197 struct intel_atomic_state *state = to_intel_atomic_state(_state);
7200 ret = intel_digital_connector_atomic_check(conn, &state->base);
7205 * We don't enable port sync on BDW due to missing w/as and
7206 * due to not having adjusted the modeset sequence appropriately.
7208 if (INTEL_GEN(dev_priv) < 9)
7211 if (!intel_connector_needs_modeset(state, conn))
7214 if (conn->has_tile) {
7215 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7220 return intel_modeset_synced_crtcs(state, conn);
7223 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7224 .force = intel_dp_force,
7225 .fill_modes = drm_helper_probe_single_connector_modes,
7226 .atomic_get_property = intel_digital_connector_atomic_get_property,
7227 .atomic_set_property = intel_digital_connector_atomic_set_property,
7228 .late_register = intel_dp_connector_register,
7229 .early_unregister = intel_dp_connector_unregister,
7230 .destroy = intel_connector_destroy,
7231 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7232 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7235 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7236 .detect_ctx = intel_dp_detect,
7237 .get_modes = intel_dp_get_modes,
7238 .mode_valid = intel_dp_mode_valid,
7239 .atomic_check = intel_dp_connector_atomic_check,
7242 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7243 .reset = intel_dp_encoder_reset,
7244 .destroy = intel_dp_encoder_destroy,
7247 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7249 intel_wakeref_t wakeref;
7250 bool have_power = false;
7252 with_pps_lock(intel_dp, wakeref) {
7253 have_power = edp_have_panel_power(intel_dp) &&
7254 edp_have_panel_vdd(intel_dp);
7261 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7263 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7264 struct intel_dp *intel_dp = &intel_dig_port->dp;
7266 if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7267 (long_hpd || !intel_edp_have_power(intel_dp))) {
7269 * vdd off can generate a long/short pulse on eDP which
7270 * would require vdd on to handle it, and thus we
7271 * would end up in an endless cycle of
7272 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7274 drm_dbg_kms(&i915->drm,
7275 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7276 long_hpd ? "long" : "short",
7277 intel_dig_port->base.base.base.id,
7278 intel_dig_port->base.base.name);
7282 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7283 intel_dig_port->base.base.base.id,
7284 intel_dig_port->base.base.name,
7285 long_hpd ? "long" : "short");
7288 intel_dp->reset_link_params = true;
7292 if (intel_dp->is_mst) {
7293 switch (intel_dp_check_mst_status(intel_dp)) {
7296 * If we were in MST mode, and device is not
7297 * there, get out of MST mode
7299 drm_dbg_kms(&i915->drm,
7300 "MST device may have disappeared %d vs %d\n",
7302 intel_dp->mst_mgr.mst_state);
7303 intel_dp->is_mst = false;
7304 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7315 if (!intel_dp->is_mst) {
7318 handled = intel_dp_short_pulse(intel_dp);
7327 /* check the VBT to see whether the eDP is on another port */
7328 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7331 * eDP not supported on g4x. so bail out early just
7332 * for a bit extra safety in case the VBT is bonkers.
7334 if (INTEL_GEN(dev_priv) < 5)
7337 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7340 return intel_bios_is_port_edp(dev_priv, port);
7344 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7346 struct drm_i915_private *dev_priv = to_i915(connector->dev);
7347 enum port port = dp_to_dig_port(intel_dp)->base.port;
7349 if (!IS_G4X(dev_priv) && port != PORT_A)
7350 intel_attach_force_audio_property(connector);
7352 intel_attach_broadcast_rgb_property(connector);
7353 if (HAS_GMCH(dev_priv))
7354 drm_connector_attach_max_bpc_property(connector, 6, 10);
7355 else if (INTEL_GEN(dev_priv) >= 5)
7356 drm_connector_attach_max_bpc_property(connector, 6, 12);
7358 intel_attach_colorspace_property(connector);
7360 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7361 drm_object_attach_property(&connector->base,
7362 connector->dev->mode_config.hdr_output_metadata_property,
7365 if (intel_dp_is_edp(intel_dp)) {
7366 u32 allowed_scalers;
7368 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7369 if (!HAS_GMCH(dev_priv))
7370 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7372 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7374 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7379 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7381 intel_dp->panel_power_off_time = ktime_get_boottime();
7382 intel_dp->last_power_on = jiffies;
7383 intel_dp->last_backlight_off = jiffies;
7387 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7389 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7390 u32 pp_on, pp_off, pp_ctl;
7391 struct pps_registers regs;
7393 intel_pps_get_registers(intel_dp, ®s);
7395 pp_ctl = ilk_get_pp_control(intel_dp);
7397 /* Ensure PPS is unlocked */
7398 if (!HAS_DDI(dev_priv))
7399 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7401 pp_on = intel_de_read(dev_priv, regs.pp_on);
7402 pp_off = intel_de_read(dev_priv, regs.pp_off);
7404 /* Pull timing values out of registers */
7405 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7406 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7407 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7408 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7410 if (i915_mmio_reg_valid(regs.pp_div)) {
7413 pp_div = intel_de_read(dev_priv, regs.pp_div);
7415 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7417 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7422 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7424 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7426 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7430 intel_pps_verify_state(struct intel_dp *intel_dp)
7432 struct edp_power_seq hw;
7433 struct edp_power_seq *sw = &intel_dp->pps_delays;
7435 intel_pps_readout_hw_state(intel_dp, &hw);
7437 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7438 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7439 DRM_ERROR("PPS state mismatch\n");
7440 intel_pps_dump_state("sw", sw);
7441 intel_pps_dump_state("hw", &hw);
7446 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7448 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7449 struct edp_power_seq cur, vbt, spec,
7450 *final = &intel_dp->pps_delays;
7452 lockdep_assert_held(&dev_priv->pps_mutex);
7454 /* already initialized? */
7455 if (final->t11_t12 != 0)
7458 intel_pps_readout_hw_state(intel_dp, &cur);
7460 intel_pps_dump_state("cur", &cur);
7462 vbt = dev_priv->vbt.edp.pps;
7463 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7464 * of 500ms appears to be too short. Ocassionally the panel
7465 * just fails to power back on. Increasing the delay to 800ms
7466 * seems sufficient to avoid this problem.
7468 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7469 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7470 drm_dbg_kms(&dev_priv->drm,
7471 "Increasing T12 panel delay as per the quirk to %d\n",
7474 /* T11_T12 delay is special and actually in units of 100ms, but zero
7475 * based in the hw (so we need to add 100 ms). But the sw vbt
7476 * table multiplies it with 1000 to make it in units of 100usec,
7478 vbt.t11_t12 += 100 * 10;
7480 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7481 * our hw here, which are all in 100usec. */
7482 spec.t1_t3 = 210 * 10;
7483 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7484 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7485 spec.t10 = 500 * 10;
7486 /* This one is special and actually in units of 100ms, but zero
7487 * based in the hw (so we need to add 100 ms). But the sw vbt
7488 * table multiplies it with 1000 to make it in units of 100usec,
7490 spec.t11_t12 = (510 + 100) * 10;
7492 intel_pps_dump_state("vbt", &vbt);
7494 /* Use the max of the register settings and vbt. If both are
7495 * unset, fall back to the spec limits. */
7496 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
7498 max(cur.field, vbt.field))
7499 assign_final(t1_t3);
7503 assign_final(t11_t12);
7506 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
7507 intel_dp->panel_power_up_delay = get_delay(t1_t3);
7508 intel_dp->backlight_on_delay = get_delay(t8);
7509 intel_dp->backlight_off_delay = get_delay(t9);
7510 intel_dp->panel_power_down_delay = get_delay(t10);
7511 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7514 drm_dbg_kms(&dev_priv->drm,
7515 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7516 intel_dp->panel_power_up_delay,
7517 intel_dp->panel_power_down_delay,
7518 intel_dp->panel_power_cycle_delay);
7520 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7521 intel_dp->backlight_on_delay,
7522 intel_dp->backlight_off_delay);
7525 * We override the HW backlight delays to 1 because we do manual waits
7526 * on them. For T8, even BSpec recommends doing it. For T9, if we
7527 * don't do this, we'll end up waiting for the backlight off delay
7528 * twice: once when we do the manual sleep, and once when we disable
7529 * the panel and wait for the PP_STATUS bit to become zero.
7535 * HW has only a 100msec granularity for t11_t12 so round it up
7538 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7542 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7543 bool force_disable_vdd)
7545 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7546 u32 pp_on, pp_off, port_sel = 0;
7547 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7548 struct pps_registers regs;
7549 enum port port = dp_to_dig_port(intel_dp)->base.port;
7550 const struct edp_power_seq *seq = &intel_dp->pps_delays;
7552 lockdep_assert_held(&dev_priv->pps_mutex);
7554 intel_pps_get_registers(intel_dp, ®s);
7557 * On some VLV machines the BIOS can leave the VDD
7558 * enabled even on power sequencers which aren't
7559 * hooked up to any port. This would mess up the
7560 * power domain tracking the first time we pick
7561 * one of these power sequencers for use since
7562 * edp_panel_vdd_on() would notice that the VDD was
7563 * already on and therefore wouldn't grab the power
7564 * domain reference. Disable VDD first to avoid this.
7565 * This also avoids spuriously turning the VDD on as
7566 * soon as the new power sequencer gets initialized.
7568 if (force_disable_vdd) {
7569 u32 pp = ilk_get_pp_control(intel_dp);
7571 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7572 "Panel power already on\n");
7574 if (pp & EDP_FORCE_VDD)
7575 drm_dbg_kms(&dev_priv->drm,
7576 "VDD already on, disabling first\n");
7578 pp &= ~EDP_FORCE_VDD;
7580 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7583 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7584 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7585 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7586 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7588 /* Haswell doesn't have any port selection bits for the panel
7589 * power sequencer any more. */
7590 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7591 port_sel = PANEL_PORT_SELECT_VLV(port);
7592 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7595 port_sel = PANEL_PORT_SELECT_DPA;
7598 port_sel = PANEL_PORT_SELECT_DPC;
7601 port_sel = PANEL_PORT_SELECT_DPD;
7611 intel_de_write(dev_priv, regs.pp_on, pp_on);
7612 intel_de_write(dev_priv, regs.pp_off, pp_off);
7615 * Compute the divisor for the pp clock, simply match the Bspec formula.
7617 if (i915_mmio_reg_valid(regs.pp_div)) {
7618 intel_de_write(dev_priv, regs.pp_div,
7619 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7623 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7624 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7625 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7626 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7629 drm_dbg_kms(&dev_priv->drm,
7630 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7631 intel_de_read(dev_priv, regs.pp_on),
7632 intel_de_read(dev_priv, regs.pp_off),
7633 i915_mmio_reg_valid(regs.pp_div) ?
7634 intel_de_read(dev_priv, regs.pp_div) :
7635 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7638 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7640 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7642 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7643 vlv_initial_power_sequencer_setup(intel_dp);
7645 intel_dp_init_panel_power_sequencer(intel_dp);
7646 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7651 * intel_dp_set_drrs_state - program registers for RR switch to take effect
7652 * @dev_priv: i915 device
7653 * @crtc_state: a pointer to the active intel_crtc_state
7654 * @refresh_rate: RR to be programmed
7656 * This function gets called when refresh rate (RR) has to be changed from
7657 * one frequency to another. Switches can be between high and low RR
7658 * supported by the panel or to any other RR based on media playback (in
7659 * this case, RR value needs to be passed from user space).
7661 * The caller of this function needs to take a lock on dev_priv->drrs.
7663 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7664 const struct intel_crtc_state *crtc_state,
7667 struct intel_dp *intel_dp = dev_priv->drrs.dp;
7668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7669 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7671 if (refresh_rate <= 0) {
7672 drm_dbg_kms(&dev_priv->drm,
7673 "Refresh rate should be positive non-zero.\n");
7677 if (intel_dp == NULL) {
7678 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7683 drm_dbg_kms(&dev_priv->drm,
7684 "DRRS: intel_crtc not initialized\n");
7688 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7689 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7693 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7695 index = DRRS_LOW_RR;
7697 if (index == dev_priv->drrs.refresh_rate_type) {
7698 drm_dbg_kms(&dev_priv->drm,
7699 "DRRS requested for previously set RR...ignoring\n");
7703 if (!crtc_state->hw.active) {
7704 drm_dbg_kms(&dev_priv->drm,
7705 "eDP encoder disabled. CRTC not Active\n");
7709 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7712 intel_dp_set_m_n(crtc_state, M1_N1);
7715 intel_dp_set_m_n(crtc_state, M2_N2);
7719 drm_err(&dev_priv->drm,
7720 "Unsupported refreshrate type\n");
7722 } else if (INTEL_GEN(dev_priv) > 6) {
7723 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7726 val = intel_de_read(dev_priv, reg);
7727 if (index > DRRS_HIGH_RR) {
7728 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7729 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7731 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7733 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7734 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7736 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7738 intel_de_write(dev_priv, reg, val);
7741 dev_priv->drrs.refresh_rate_type = index;
7743 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7748 * intel_edp_drrs_enable - init drrs struct if supported
7749 * @intel_dp: DP struct
7750 * @crtc_state: A pointer to the active crtc state.
7752 * Initializes frontbuffer_bits and drrs.dp
7754 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7755 const struct intel_crtc_state *crtc_state)
7757 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7759 if (!crtc_state->has_drrs) {
7760 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7764 if (dev_priv->psr.enabled) {
7765 drm_dbg_kms(&dev_priv->drm,
7766 "PSR enabled. Not enabling DRRS.\n");
7770 mutex_lock(&dev_priv->drrs.mutex);
7771 if (dev_priv->drrs.dp) {
7772 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7776 dev_priv->drrs.busy_frontbuffer_bits = 0;
7778 dev_priv->drrs.dp = intel_dp;
7781 mutex_unlock(&dev_priv->drrs.mutex);
7785 * intel_edp_drrs_disable - Disable DRRS
7786 * @intel_dp: DP struct
7787 * @old_crtc_state: Pointer to old crtc_state.
7790 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7791 const struct intel_crtc_state *old_crtc_state)
7793 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7795 if (!old_crtc_state->has_drrs)
7798 mutex_lock(&dev_priv->drrs.mutex);
7799 if (!dev_priv->drrs.dp) {
7800 mutex_unlock(&dev_priv->drrs.mutex);
7804 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7805 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7806 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7808 dev_priv->drrs.dp = NULL;
7809 mutex_unlock(&dev_priv->drrs.mutex);
7811 cancel_delayed_work_sync(&dev_priv->drrs.work);
7814 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7816 struct drm_i915_private *dev_priv =
7817 container_of(work, typeof(*dev_priv), drrs.work.work);
7818 struct intel_dp *intel_dp;
7820 mutex_lock(&dev_priv->drrs.mutex);
7822 intel_dp = dev_priv->drrs.dp;
7828 * The delayed work can race with an invalidate hence we need to
7832 if (dev_priv->drrs.busy_frontbuffer_bits)
7835 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7836 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7838 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7839 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7843 mutex_unlock(&dev_priv->drrs.mutex);
7847 * intel_edp_drrs_invalidate - Disable Idleness DRRS
7848 * @dev_priv: i915 device
7849 * @frontbuffer_bits: frontbuffer plane tracking bits
7851 * This function gets called everytime rendering on the given planes start.
7852 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7854 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7856 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7857 unsigned int frontbuffer_bits)
7859 struct drm_crtc *crtc;
7862 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7865 cancel_delayed_work(&dev_priv->drrs.work);
7867 mutex_lock(&dev_priv->drrs.mutex);
7868 if (!dev_priv->drrs.dp) {
7869 mutex_unlock(&dev_priv->drrs.mutex);
7873 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7874 pipe = to_intel_crtc(crtc)->pipe;
7876 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7877 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7879 /* invalidate means busy screen hence upclock */
7880 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7881 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7882 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7884 mutex_unlock(&dev_priv->drrs.mutex);
7888 * intel_edp_drrs_flush - Restart Idleness DRRS
7889 * @dev_priv: i915 device
7890 * @frontbuffer_bits: frontbuffer plane tracking bits
7892 * This function gets called every time rendering on the given planes has
7893 * completed or flip on a crtc is completed. So DRRS should be upclocked
7894 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7895 * if no other planes are dirty.
7897 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7899 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7900 unsigned int frontbuffer_bits)
7902 struct drm_crtc *crtc;
7905 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7908 cancel_delayed_work(&dev_priv->drrs.work);
7910 mutex_lock(&dev_priv->drrs.mutex);
7911 if (!dev_priv->drrs.dp) {
7912 mutex_unlock(&dev_priv->drrs.mutex);
7916 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7917 pipe = to_intel_crtc(crtc)->pipe;
7919 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7920 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7922 /* flush means busy screen hence upclock */
7923 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7924 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7925 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7928 * flush also means no more activity hence schedule downclock, if all
7929 * other fbs are quiescent too
7931 if (!dev_priv->drrs.busy_frontbuffer_bits)
7932 schedule_delayed_work(&dev_priv->drrs.work,
7933 msecs_to_jiffies(1000));
7934 mutex_unlock(&dev_priv->drrs.mutex);
7938 * DOC: Display Refresh Rate Switching (DRRS)
7940 * Display Refresh Rate Switching (DRRS) is a power conservation feature
7941 * which enables swtching between low and high refresh rates,
7942 * dynamically, based on the usage scenario. This feature is applicable
7943 * for internal panels.
7945 * Indication that the panel supports DRRS is given by the panel EDID, which
7946 * would list multiple refresh rates for one resolution.
7948 * DRRS is of 2 types - static and seamless.
7949 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7950 * (may appear as a blink on screen) and is used in dock-undock scenario.
7951 * Seamless DRRS involves changing RR without any visual effect to the user
7952 * and can be used during normal system usage. This is done by programming
7953 * certain registers.
7955 * Support for static/seamless DRRS may be indicated in the VBT based on
7956 * inputs from the panel spec.
7958 * DRRS saves power by switching to low RR based on usage scenarios.
7960 * The implementation is based on frontbuffer tracking implementation. When
7961 * there is a disturbance on the screen triggered by user activity or a periodic
7962 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7963 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7966 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7967 * and intel_edp_drrs_flush() are called.
7969 * DRRS can be further extended to support other internal panels and also
7970 * the scenario of video playback wherein RR is set based on the rate
7971 * requested by userspace.
7975 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7976 * @connector: eDP connector
7977 * @fixed_mode: preferred mode of panel
7979 * This function is called only once at driver load to initialize basic
7983 * Downclock mode if panel supports it, else return NULL.
7984 * DRRS support is determined by the presence of downclock mode (apart
7985 * from VBT setting).
7987 static struct drm_display_mode *
7988 intel_dp_drrs_init(struct intel_connector *connector,
7989 struct drm_display_mode *fixed_mode)
7991 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7992 struct drm_display_mode *downclock_mode = NULL;
7994 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7995 mutex_init(&dev_priv->drrs.mutex);
7997 if (INTEL_GEN(dev_priv) <= 6) {
7998 drm_dbg_kms(&dev_priv->drm,
7999 "DRRS supported for Gen7 and above\n");
8003 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8004 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8008 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8009 if (!downclock_mode) {
8010 drm_dbg_kms(&dev_priv->drm,
8011 "Downclock mode is not found. DRRS not supported\n");
8015 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8017 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8018 drm_dbg_kms(&dev_priv->drm,
8019 "seamless DRRS supported for eDP panel.\n");
8020 return downclock_mode;
8023 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8024 struct intel_connector *intel_connector)
8026 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8027 struct drm_device *dev = &dev_priv->drm;
8028 struct drm_connector *connector = &intel_connector->base;
8029 struct drm_display_mode *fixed_mode = NULL;
8030 struct drm_display_mode *downclock_mode = NULL;
8032 enum pipe pipe = INVALID_PIPE;
8033 intel_wakeref_t wakeref;
8036 if (!intel_dp_is_edp(intel_dp))
8039 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8042 * On IBX/CPT we may get here with LVDS already registered. Since the
8043 * driver uses the only internal power sequencer available for both
8044 * eDP and LVDS bail out early in this case to prevent interfering
8045 * with an already powered-on LVDS power sequencer.
8047 if (intel_get_lvds_encoder(dev_priv)) {
8049 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8050 drm_info(&dev_priv->drm,
8051 "LVDS was detected, not registering eDP\n");
8056 with_pps_lock(intel_dp, wakeref) {
8057 intel_dp_init_panel_power_timestamps(intel_dp);
8058 intel_dp_pps_init(intel_dp);
8059 intel_edp_panel_vdd_sanitize(intel_dp);
8062 /* Cache DPCD and EDID for edp. */
8063 has_dpcd = intel_edp_init_dpcd(intel_dp);
8066 /* if this fails, presume the device is a ghost */
8067 drm_info(&dev_priv->drm,
8068 "failed to retrieve link info, disabling eDP\n");
8072 mutex_lock(&dev->mode_config.mutex);
8073 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8075 if (drm_add_edid_modes(connector, edid)) {
8076 drm_connector_update_edid_property(connector, edid);
8077 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8080 edid = ERR_PTR(-EINVAL);
8083 edid = ERR_PTR(-ENOENT);
8085 intel_connector->edid = edid;
8087 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8089 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8091 /* fallback to VBT if available for eDP */
8093 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8094 mutex_unlock(&dev->mode_config.mutex);
8096 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8097 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8098 register_reboot_notifier(&intel_dp->edp_notifier);
8101 * Figure out the current pipe for the initial backlight setup.
8102 * If the current pipe isn't valid, try the PPS pipe, and if that
8103 * fails just assume pipe A.
8105 pipe = vlv_active_pipe(intel_dp);
8107 if (pipe != PIPE_A && pipe != PIPE_B)
8108 pipe = intel_dp->pps_pipe;
8110 if (pipe != PIPE_A && pipe != PIPE_B)
8113 drm_dbg_kms(&dev_priv->drm,
8114 "using pipe %c for initial backlight setup\n",
8118 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8119 intel_connector->panel.backlight.power = intel_edp_backlight_power;
8120 intel_panel_setup_backlight(connector, pipe);
8123 drm_connector_set_panel_orientation_with_quirk(connector,
8124 dev_priv->vbt.orientation,
8125 fixed_mode->hdisplay, fixed_mode->vdisplay);
8131 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8133 * vdd might still be enabled do to the delayed vdd off.
8134 * Make sure vdd is actually turned off here.
8136 with_pps_lock(intel_dp, wakeref)
8137 edp_panel_vdd_off_sync(intel_dp);
8142 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8144 struct intel_connector *intel_connector;
8145 struct drm_connector *connector;
8147 intel_connector = container_of(work, typeof(*intel_connector),
8148 modeset_retry_work);
8149 connector = &intel_connector->base;
8150 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8153 /* Grab the locks before changing connector property*/
8154 mutex_lock(&connector->dev->mode_config.mutex);
8155 /* Set connector link status to BAD and send a Uevent to notify
8156 * userspace to do a modeset.
8158 drm_connector_set_link_status_property(connector,
8159 DRM_MODE_LINK_STATUS_BAD);
8160 mutex_unlock(&connector->dev->mode_config.mutex);
8161 /* Send Hotplug uevent so userspace can reprobe */
8162 drm_kms_helper_hotplug_event(connector->dev);
8166 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8167 struct intel_connector *intel_connector)
8169 struct drm_connector *connector = &intel_connector->base;
8170 struct intel_dp *intel_dp = &intel_dig_port->dp;
8171 struct intel_encoder *intel_encoder = &intel_dig_port->base;
8172 struct drm_device *dev = intel_encoder->base.dev;
8173 struct drm_i915_private *dev_priv = to_i915(dev);
8174 enum port port = intel_encoder->port;
8175 enum phy phy = intel_port_to_phy(dev_priv, port);
8178 /* Initialize the work for modeset in case of link train failure */
8179 INIT_WORK(&intel_connector->modeset_retry_work,
8180 intel_dp_modeset_retry_work_fn);
8182 if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8183 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8184 intel_dig_port->max_lanes, intel_encoder->base.base.id,
8185 intel_encoder->base.name))
8188 intel_dp_set_source_rates(intel_dp);
8190 intel_dp->reset_link_params = true;
8191 intel_dp->pps_pipe = INVALID_PIPE;
8192 intel_dp->active_pipe = INVALID_PIPE;
8194 /* Preserve the current hw state. */
8195 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8196 intel_dp->attached_connector = intel_connector;
8198 if (intel_dp_is_port_edp(dev_priv, port)) {
8200 * Currently we don't support eDP on TypeC ports, although in
8201 * theory it could work on TypeC legacy ports.
8203 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8204 type = DRM_MODE_CONNECTOR_eDP;
8206 type = DRM_MODE_CONNECTOR_DisplayPort;
8209 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8210 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8213 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8214 * for DP the encoder type can be set by the caller to
8215 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8217 if (type == DRM_MODE_CONNECTOR_eDP)
8218 intel_encoder->type = INTEL_OUTPUT_EDP;
8220 /* eDP only on port B and/or C on vlv/chv */
8221 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8222 IS_CHERRYVIEW(dev_priv)) &&
8223 intel_dp_is_edp(intel_dp) &&
8224 port != PORT_B && port != PORT_C))
8227 drm_dbg_kms(&dev_priv->drm,
8228 "Adding %s connector on [ENCODER:%d:%s]\n",
8229 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8230 intel_encoder->base.base.id, intel_encoder->base.name);
8232 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8233 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8235 if (!HAS_GMCH(dev_priv))
8236 connector->interlace_allowed = true;
8237 connector->doublescan_allowed = 0;
8239 if (INTEL_GEN(dev_priv) >= 11)
8240 connector->ycbcr_420_allowed = true;
8242 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8243 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8245 intel_dp_aux_init(intel_dp);
8247 intel_connector_attach_encoder(intel_connector, intel_encoder);
8249 if (HAS_DDI(dev_priv))
8250 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8252 intel_connector->get_hw_state = intel_connector_get_hw_state;
8254 /* init MST on ports that can support it */
8255 intel_dp_mst_encoder_init(intel_dig_port,
8256 intel_connector->base.base.id);
8258 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8259 intel_dp_aux_fini(intel_dp);
8260 intel_dp_mst_encoder_cleanup(intel_dig_port);
8264 intel_dp_add_properties(intel_dp, connector);
8266 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8267 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8269 drm_dbg_kms(&dev_priv->drm,
8270 "HDCP init failed, skipping.\n");
8273 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8274 * 0xd. Failure to do so will result in spurious interrupts being
8275 * generated on the port when a cable is not attached.
8277 if (IS_G45(dev_priv)) {
8278 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8279 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8280 (temp & ~0xf) | 0xd);
8286 drm_connector_cleanup(connector);
8291 bool intel_dp_init(struct drm_i915_private *dev_priv,
8292 i915_reg_t output_reg,
8295 struct intel_digital_port *intel_dig_port;
8296 struct intel_encoder *intel_encoder;
8297 struct drm_encoder *encoder;
8298 struct intel_connector *intel_connector;
8300 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8301 if (!intel_dig_port)
8304 intel_connector = intel_connector_alloc();
8305 if (!intel_connector)
8306 goto err_connector_alloc;
8308 intel_encoder = &intel_dig_port->base;
8309 encoder = &intel_encoder->base;
8311 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8312 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8313 "DP %c", port_name(port)))
8314 goto err_encoder_init;
8316 intel_encoder->hotplug = intel_dp_hotplug;
8317 intel_encoder->compute_config = intel_dp_compute_config;
8318 intel_encoder->get_hw_state = intel_dp_get_hw_state;
8319 intel_encoder->get_config = intel_dp_get_config;
8320 intel_encoder->update_pipe = intel_panel_update_backlight;
8321 intel_encoder->suspend = intel_dp_encoder_suspend;
8322 if (IS_CHERRYVIEW(dev_priv)) {
8323 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8324 intel_encoder->pre_enable = chv_pre_enable_dp;
8325 intel_encoder->enable = vlv_enable_dp;
8326 intel_encoder->disable = vlv_disable_dp;
8327 intel_encoder->post_disable = chv_post_disable_dp;
8328 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8329 } else if (IS_VALLEYVIEW(dev_priv)) {
8330 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8331 intel_encoder->pre_enable = vlv_pre_enable_dp;
8332 intel_encoder->enable = vlv_enable_dp;
8333 intel_encoder->disable = vlv_disable_dp;
8334 intel_encoder->post_disable = vlv_post_disable_dp;
8336 intel_encoder->pre_enable = g4x_pre_enable_dp;
8337 intel_encoder->enable = g4x_enable_dp;
8338 intel_encoder->disable = g4x_disable_dp;
8339 intel_encoder->post_disable = g4x_post_disable_dp;
8342 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8343 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8344 intel_dig_port->dp.set_link_train = cpt_set_link_train;
8346 intel_dig_port->dp.set_link_train = g4x_set_link_train;
8348 if (IS_CHERRYVIEW(dev_priv))
8349 intel_dig_port->dp.set_signal_levels = chv_set_signal_levels;
8350 else if (IS_VALLEYVIEW(dev_priv))
8351 intel_dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8352 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8353 intel_dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8354 else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8355 intel_dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8357 intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8359 intel_dig_port->dp.output_reg = output_reg;
8360 intel_dig_port->max_lanes = 4;
8361 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
8362 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
8364 intel_encoder->type = INTEL_OUTPUT_DP;
8365 intel_encoder->power_domain = intel_port_to_power_domain(port);
8366 if (IS_CHERRYVIEW(dev_priv)) {
8368 intel_encoder->pipe_mask = BIT(PIPE_C);
8370 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8372 intel_encoder->pipe_mask = ~0;
8374 intel_encoder->cloneable = 0;
8375 intel_encoder->port = port;
8377 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8379 if (HAS_GMCH(dev_priv)) {
8380 if (IS_GM45(dev_priv))
8381 intel_dig_port->connected = gm45_digital_port_connected;
8383 intel_dig_port->connected = g4x_digital_port_connected;
8386 intel_dig_port->connected = ilk_digital_port_connected;
8388 intel_dig_port->connected = ibx_digital_port_connected;
8392 intel_infoframe_init(intel_dig_port);
8394 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8395 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8396 goto err_init_connector;
8401 drm_encoder_cleanup(encoder);
8403 kfree(intel_connector);
8404 err_connector_alloc:
8405 kfree(intel_dig_port);
8409 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8411 struct intel_encoder *encoder;
8413 for_each_intel_encoder(&dev_priv->drm, encoder) {
8414 struct intel_dp *intel_dp;
8416 if (encoder->type != INTEL_OUTPUT_DDI)
8419 intel_dp = enc_to_intel_dp(encoder);
8421 if (!intel_dp->can_mst)
8424 if (intel_dp->is_mst)
8425 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8429 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8431 struct intel_encoder *encoder;
8433 for_each_intel_encoder(&dev_priv->drm, encoder) {
8434 struct intel_dp *intel_dp;
8437 if (encoder->type != INTEL_OUTPUT_DDI)
8440 intel_dp = enc_to_intel_dp(encoder);
8442 if (!intel_dp->can_mst)
8445 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8448 intel_dp->is_mst = false;
8449 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,