2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
43 #include "i915_debugfs.h"
45 #include "intel_atomic.h"
46 #include "intel_audio.h"
47 #include "intel_connector.h"
48 #include "intel_ddi.h"
49 #include "intel_display_types.h"
51 #include "intel_dp_aux.h"
52 #include "intel_dp_link_training.h"
53 #include "intel_dp_mst.h"
54 #include "intel_dpll.h"
55 #include "intel_dpio_phy.h"
56 #include "intel_fifo_underrun.h"
57 #include "intel_hdcp.h"
58 #include "intel_hdmi.h"
59 #include "intel_hotplug.h"
60 #include "intel_lspcon.h"
61 #include "intel_lvds.h"
62 #include "intel_panel.h"
63 #include "intel_pps.h"
64 #include "intel_psr.h"
65 #include "intel_sideband.h"
67 #include "intel_vdsc.h"
68 #include "intel_vrr.h"
70 #define DP_DPRX_ESI_LEN 14
72 /* DP DSC throughput values used for slice count calculations KPixels/s */
73 #define DP_DSC_PEAK_PIXEL_RATE 2720000
74 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
75 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
77 /* DP DSC FEC Overhead factor = 1/(0.972261) */
78 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
80 /* Compliance test status bits */
81 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
82 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
83 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
84 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
87 /* Constants for DP DSC configurations */
88 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
90 /* With Single pipe configuration, HW is capable of supporting maximum
91 * of 4 slices per line.
93 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
96 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
102 bool intel_dp_is_edp(struct intel_dp *intel_dp)
104 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
106 return dig_port->base.type == INTEL_OUTPUT_EDP;
109 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
111 /* update sink rates from dpcd */
112 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
114 static const int dp_rates[] = {
115 162000, 270000, 540000, 810000
120 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
121 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
122 static const int quirk_rates[] = { 162000, 270000, 324000 };
124 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
125 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
130 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
131 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
133 max_rate = min(max_rate, max_lttpr_rate);
135 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
136 if (dp_rates[i] > max_rate)
138 intel_dp->sink_rates[i] = dp_rates[i];
141 intel_dp->num_sink_rates = i;
144 /* Get length of rates array potentially limited by max_rate. */
145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
149 /* Limit results by potentially reduced max rate */
150 for (i = 0; i < len; i++) {
151 if (rates[len - i - 1] <= max_rate)
158 /* Get length of common rates array potentially limited by max_rate. */
159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
162 return intel_dp_rate_limit_len(intel_dp->common_rates,
163 intel_dp->num_common_rates, max_rate);
166 /* Theoretical max between source and sink */
167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
169 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
172 /* Theoretical max between source and sink */
173 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
175 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
176 int source_max = dig_port->max_lanes;
177 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
178 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
179 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
182 sink_max = min(sink_max, lttpr_max);
184 return min3(source_max, sink_max, fia_max);
187 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
189 return intel_dp->max_link_lane_count;
193 intel_dp_link_required(int pixel_clock, int bpp)
195 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
196 return DIV_ROUND_UP(pixel_clock * bpp, 8);
200 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
202 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
203 * link rate that is generally expressed in Gbps. Since, 8 bits of data
204 * is transmitted every LS_Clk per lane, there is no need to account for
205 * the channel encoding that is done in the PHY layer here.
208 return max_link_clock * max_lanes;
211 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
214 struct intel_encoder *encoder = &intel_dig_port->base;
215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
217 return INTEL_GEN(dev_priv) >= 12 ||
218 (INTEL_GEN(dev_priv) == 11 &&
219 encoder->port != PORT_A);
222 static int cnl_max_source_rate(struct intel_dp *intel_dp)
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
226 enum port port = dig_port->base.port;
228 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
230 /* Low voltage SKUs are limited to max of 5.4G */
231 if (voltage == VOLTAGE_INFO_0_85V)
234 /* For this SKU 8.1G is supported in all ports */
235 if (IS_CNL_WITH_PORT_F(dev_priv))
238 /* For other SKUs, max rate on ports A and D is 5.4G */
239 if (port == PORT_A || port == PORT_D)
245 static int icl_max_source_rate(struct intel_dp *intel_dp)
247 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
248 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
249 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
251 if (intel_phy_is_combo(dev_priv, phy) &&
252 !intel_dp_is_edp(intel_dp))
258 static int ehl_max_source_rate(struct intel_dp *intel_dp)
260 if (intel_dp_is_edp(intel_dp))
267 intel_dp_set_source_rates(struct intel_dp *intel_dp)
269 /* The values must be in increasing order */
270 static const int cnl_rates[] = {
271 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
273 static const int bxt_rates[] = {
274 162000, 216000, 243000, 270000, 324000, 432000, 540000
276 static const int skl_rates[] = {
277 162000, 216000, 270000, 324000, 432000, 540000
279 static const int hsw_rates[] = {
280 162000, 270000, 540000
282 static const int g4x_rates[] = {
285 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
286 struct intel_encoder *encoder = &dig_port->base;
287 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
288 const int *source_rates;
289 int size, max_rate = 0, vbt_max_rate;
291 /* This should only be done once */
292 drm_WARN_ON(&dev_priv->drm,
293 intel_dp->source_rates || intel_dp->num_source_rates);
295 if (INTEL_GEN(dev_priv) >= 10) {
296 source_rates = cnl_rates;
297 size = ARRAY_SIZE(cnl_rates);
298 if (IS_GEN(dev_priv, 10))
299 max_rate = cnl_max_source_rate(intel_dp);
300 else if (IS_JSL_EHL(dev_priv))
301 max_rate = ehl_max_source_rate(intel_dp);
303 max_rate = icl_max_source_rate(intel_dp);
304 } else if (IS_GEN9_LP(dev_priv)) {
305 source_rates = bxt_rates;
306 size = ARRAY_SIZE(bxt_rates);
307 } else if (IS_GEN9_BC(dev_priv)) {
308 source_rates = skl_rates;
309 size = ARRAY_SIZE(skl_rates);
310 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
311 IS_BROADWELL(dev_priv)) {
312 source_rates = hsw_rates;
313 size = ARRAY_SIZE(hsw_rates);
315 source_rates = g4x_rates;
316 size = ARRAY_SIZE(g4x_rates);
319 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
320 if (max_rate && vbt_max_rate)
321 max_rate = min(max_rate, vbt_max_rate);
322 else if (vbt_max_rate)
323 max_rate = vbt_max_rate;
326 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
328 intel_dp->source_rates = source_rates;
329 intel_dp->num_source_rates = size;
332 static int intersect_rates(const int *source_rates, int source_len,
333 const int *sink_rates, int sink_len,
336 int i = 0, j = 0, k = 0;
338 while (i < source_len && j < sink_len) {
339 if (source_rates[i] == sink_rates[j]) {
340 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
342 common_rates[k] = source_rates[i];
346 } else if (source_rates[i] < sink_rates[j]) {
355 /* return index of rate in rates array, or -1 if not found */
356 static int intel_dp_rate_index(const int *rates, int len, int rate)
360 for (i = 0; i < len; i++)
361 if (rate == rates[i])
367 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
369 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
371 drm_WARN_ON(&i915->drm,
372 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
374 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
375 intel_dp->num_source_rates,
376 intel_dp->sink_rates,
377 intel_dp->num_sink_rates,
378 intel_dp->common_rates);
380 /* Paranoia, there should always be something in common. */
381 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
382 intel_dp->common_rates[0] = 162000;
383 intel_dp->num_common_rates = 1;
387 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
391 * FIXME: we need to synchronize the current link parameters with
392 * hardware readout. Currently fast link training doesn't work on
395 if (link_rate == 0 ||
396 link_rate > intel_dp->max_link_rate)
399 if (lane_count == 0 ||
400 lane_count > intel_dp_max_lane_count(intel_dp))
406 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
410 const struct drm_display_mode *fixed_mode =
411 intel_dp->attached_connector->panel.fixed_mode;
412 int mode_rate, max_rate;
414 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
415 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
416 if (mode_rate > max_rate)
422 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
423 int link_rate, u8 lane_count)
425 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
429 * TODO: Enable fallback on MST links once MST link compute can handle
430 * the fallback params.
432 if (intel_dp->is_mst) {
433 drm_err(&i915->drm, "Link Training Unsuccessful\n");
437 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
438 drm_dbg_kms(&i915->drm,
439 "Retrying Link training for eDP with max parameters\n");
440 intel_dp->use_max_params = true;
444 index = intel_dp_rate_index(intel_dp->common_rates,
445 intel_dp->num_common_rates,
448 if (intel_dp_is_edp(intel_dp) &&
449 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
450 intel_dp->common_rates[index - 1],
452 drm_dbg_kms(&i915->drm,
453 "Retrying Link training for eDP with same parameters\n");
456 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
457 intel_dp->max_link_lane_count = lane_count;
458 } else if (lane_count > 1) {
459 if (intel_dp_is_edp(intel_dp) &&
460 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
461 intel_dp_max_common_rate(intel_dp),
463 drm_dbg_kms(&i915->drm,
464 "Retrying Link training for eDP with same parameters\n");
467 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
468 intel_dp->max_link_lane_count = lane_count >> 1;
470 drm_err(&i915->drm, "Link Training Unsuccessful\n");
477 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
479 return div_u64(mul_u32_u32(mode_clock, 1000000U),
480 DP_DSC_FEC_OVERHEAD_FACTOR);
484 small_joiner_ram_size_bits(struct drm_i915_private *i915)
486 if (INTEL_GEN(i915) >= 11)
492 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
493 u32 link_clock, u32 lane_count,
494 u32 mode_clock, u32 mode_hdisplay,
497 u32 bits_per_pixel, max_bpp_small_joiner_ram;
501 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
502 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
503 * for SST -> TimeSlotsPerMTP is 1,
504 * for MST -> TimeSlotsPerMTP has to be calculated
506 bits_per_pixel = (link_clock * lane_count * 8) /
507 intel_dp_mode_to_fec_clock(mode_clock);
508 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
510 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
511 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
515 max_bpp_small_joiner_ram *= 2;
517 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
518 max_bpp_small_joiner_ram);
521 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
522 * check, output bpp from small joiner RAM check)
524 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
527 u32 max_bpp_bigjoiner =
528 i915->max_cdclk_freq * 48 /
529 intel_dp_mode_to_fec_clock(mode_clock);
531 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
532 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
535 /* Error out if the max bpp is less than smallest allowed valid bpp */
536 if (bits_per_pixel < valid_dsc_bpp[0]) {
537 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
538 bits_per_pixel, valid_dsc_bpp[0]);
542 /* Find the nearest match in the array of known BPPs from VESA */
543 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
544 if (bits_per_pixel < valid_dsc_bpp[i + 1])
547 bits_per_pixel = valid_dsc_bpp[i];
550 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
551 * fractional part is 0
553 return bits_per_pixel << 4;
556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
557 int mode_clock, int mode_hdisplay,
560 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
561 u8 min_slice_count, i;
564 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
565 min_slice_count = DIV_ROUND_UP(mode_clock,
566 DP_DSC_MAX_ENC_THROUGHPUT_0);
568 min_slice_count = DIV_ROUND_UP(mode_clock,
569 DP_DSC_MAX_ENC_THROUGHPUT_1);
571 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
572 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
573 drm_dbg_kms(&i915->drm,
574 "Unsupported slice width %d by DP DSC Sink device\n",
578 /* Also take into account max slice width */
579 min_slice_count = max_t(u8, min_slice_count,
580 DIV_ROUND_UP(mode_hdisplay,
583 /* Find the closest match to the valid slice count values */
584 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
585 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
587 if (test_slice_count >
588 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
591 /* big joiner needs small joiner to be enabled */
592 if (bigjoiner && test_slice_count < 4)
595 if (min_slice_count <= test_slice_count)
596 return test_slice_count;
599 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
604 static enum intel_output_format
605 intel_dp_output_format(struct drm_connector *connector,
606 const struct drm_display_mode *mode)
608 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
609 const struct drm_display_info *info = &connector->display_info;
611 if (!connector->ycbcr_420_allowed ||
612 !drm_mode_is_420_only(info, mode))
613 return INTEL_OUTPUT_FORMAT_RGB;
615 if (intel_dp->dfp.rgb_to_ycbcr &&
616 intel_dp->dfp.ycbcr_444_to_420)
617 return INTEL_OUTPUT_FORMAT_RGB;
619 if (intel_dp->dfp.ycbcr_444_to_420)
620 return INTEL_OUTPUT_FORMAT_YCBCR444;
622 return INTEL_OUTPUT_FORMAT_YCBCR420;
625 int intel_dp_min_bpp(enum intel_output_format output_format)
627 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
633 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
636 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
637 * format of the number of bytes per pixel will be half the number
638 * of bytes of RGB pixel.
640 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
647 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
648 const struct drm_display_mode *mode)
650 enum intel_output_format output_format =
651 intel_dp_output_format(connector, mode);
653 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
656 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
660 * Older platforms don't like hdisplay==4096 with DP.
662 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
663 * and frame counter increment), but we don't get vblank interrupts,
664 * and the pipe underruns immediately. The link also doesn't seem
665 * to get trained properly.
667 * On CHV the vblank interrupts don't seem to disappear but
668 * otherwise the symptoms are similar.
670 * TODO: confirm the behaviour on HSW+
672 return hdisplay == 4096 && !HAS_DDI(dev_priv);
675 static enum drm_mode_status
676 intel_dp_mode_valid_downstream(struct intel_connector *connector,
677 const struct drm_display_mode *mode,
680 struct intel_dp *intel_dp = intel_attached_dp(connector);
681 const struct drm_display_info *info = &connector->base.display_info;
684 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
685 if (intel_dp->dfp.pcon_max_frl_bw) {
688 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
690 target_bw = bpp * target_clock;
692 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
694 /* converting bw from Gbps to Kbps*/
695 max_frl_bw = max_frl_bw * 1000000;
697 if (target_bw > max_frl_bw)
698 return MODE_CLOCK_HIGH;
703 if (intel_dp->dfp.max_dotclock &&
704 target_clock > intel_dp->dfp.max_dotclock)
705 return MODE_CLOCK_HIGH;
707 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
708 tmds_clock = target_clock;
709 if (drm_mode_is_420_only(info, mode))
712 if (intel_dp->dfp.min_tmds_clock &&
713 tmds_clock < intel_dp->dfp.min_tmds_clock)
714 return MODE_CLOCK_LOW;
715 if (intel_dp->dfp.max_tmds_clock &&
716 tmds_clock > intel_dp->dfp.max_tmds_clock)
717 return MODE_CLOCK_HIGH;
722 static enum drm_mode_status
723 intel_dp_mode_valid(struct drm_connector *connector,
724 struct drm_display_mode *mode)
726 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
727 struct intel_connector *intel_connector = to_intel_connector(connector);
728 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
729 struct drm_i915_private *dev_priv = to_i915(connector->dev);
730 int target_clock = mode->clock;
731 int max_rate, mode_rate, max_lanes, max_link_clock;
732 int max_dotclk = dev_priv->max_dotclk_freq;
733 u16 dsc_max_output_bpp = 0;
734 u8 dsc_slice_count = 0;
735 enum drm_mode_status status;
736 bool dsc = false, bigjoiner = false;
738 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
739 return MODE_NO_DBLESCAN;
741 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
742 return MODE_H_ILLEGAL;
744 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
745 if (mode->hdisplay != fixed_mode->hdisplay)
748 if (mode->vdisplay != fixed_mode->vdisplay)
751 target_clock = fixed_mode->clock;
754 if (mode->clock < 10000)
755 return MODE_CLOCK_LOW;
757 if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
758 intel_dp_can_bigjoiner(intel_dp)) {
762 if (target_clock > max_dotclk)
763 return MODE_CLOCK_HIGH;
765 max_link_clock = intel_dp_max_link_rate(intel_dp);
766 max_lanes = intel_dp_max_lane_count(intel_dp);
768 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
769 mode_rate = intel_dp_link_required(target_clock,
770 intel_dp_mode_min_output_bpp(connector, mode));
772 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
773 return MODE_H_ILLEGAL;
776 * Output bpp is stored in 6.4 format so right shift by 4 to get the
777 * integer value since we support only integer values of bpp.
779 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
780 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
781 if (intel_dp_is_edp(intel_dp)) {
783 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
785 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
787 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
789 intel_dp_dsc_get_output_bpp(dev_priv,
796 intel_dp_dsc_get_slice_count(intel_dp,
802 dsc = dsc_max_output_bpp && dsc_slice_count;
805 /* big joiner configuration needs DSC */
806 if (bigjoiner && !dsc)
807 return MODE_CLOCK_HIGH;
809 if (mode_rate > max_rate && !dsc)
810 return MODE_CLOCK_HIGH;
812 status = intel_dp_mode_valid_downstream(intel_connector,
814 if (status != MODE_OK)
817 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
820 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
822 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
824 return max_rate >= 540000;
827 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
829 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
831 return max_rate >= 810000;
834 static void snprintf_int_array(char *str, size_t len,
835 const int *array, int nelem)
841 for (i = 0; i < nelem; i++) {
842 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
850 static void intel_dp_print_rates(struct intel_dp *intel_dp)
852 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
853 char str[128]; /* FIXME: too big for stack? */
855 if (!drm_debug_enabled(DRM_UT_KMS))
858 snprintf_int_array(str, sizeof(str),
859 intel_dp->source_rates, intel_dp->num_source_rates);
860 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
862 snprintf_int_array(str, sizeof(str),
863 intel_dp->sink_rates, intel_dp->num_sink_rates);
864 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
866 snprintf_int_array(str, sizeof(str),
867 intel_dp->common_rates, intel_dp->num_common_rates);
868 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
872 intel_dp_max_link_rate(struct intel_dp *intel_dp)
874 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
877 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
878 if (drm_WARN_ON(&i915->drm, len <= 0))
881 return intel_dp->common_rates[len - 1];
884 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
886 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
887 int i = intel_dp_rate_index(intel_dp->sink_rates,
888 intel_dp->num_sink_rates, rate);
890 if (drm_WARN_ON(&i915->drm, i < 0))
896 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
897 u8 *link_bw, u8 *rate_select)
899 /* eDP 1.4 rate select method. */
900 if (intel_dp->use_rate_select) {
903 intel_dp_rate_select(intel_dp, port_clock);
905 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
910 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
911 const struct intel_crtc_state *pipe_config)
913 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
915 /* On TGL, FEC is supported on all Pipes */
916 if (INTEL_GEN(dev_priv) >= 12)
919 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
925 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
926 const struct intel_crtc_state *pipe_config)
928 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
929 drm_dp_sink_supports_fec(intel_dp->fec_capable);
932 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
933 const struct intel_crtc_state *crtc_state)
935 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
938 return intel_dsc_source_support(crtc_state) &&
939 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
942 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
943 const struct intel_crtc_state *crtc_state)
945 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
946 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
947 intel_dp->dfp.ycbcr_444_to_420);
950 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
951 const struct intel_crtc_state *crtc_state, int bpc)
953 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
955 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
961 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
962 const struct intel_crtc_state *crtc_state, int bpc)
964 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
966 if (intel_dp->dfp.min_tmds_clock &&
967 tmds_clock < intel_dp->dfp.min_tmds_clock)
970 if (intel_dp->dfp.max_tmds_clock &&
971 tmds_clock > intel_dp->dfp.max_tmds_clock)
977 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
978 const struct intel_crtc_state *crtc_state,
982 return intel_hdmi_deep_color_possible(crtc_state, bpc,
983 intel_dp->has_hdmi_sink,
984 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
985 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
988 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
989 const struct intel_crtc_state *crtc_state)
991 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
992 struct intel_connector *intel_connector = intel_dp->attached_connector;
995 bpc = crtc_state->pipe_bpp / 3;
997 if (intel_dp->dfp.max_bpc)
998 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1000 if (intel_dp->dfp.min_tmds_clock) {
1001 for (; bpc >= 10; bpc -= 2) {
1002 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1008 if (intel_dp_is_edp(intel_dp)) {
1009 /* Get bpp from vbt only for panels that dont have bpp in edid */
1010 if (intel_connector->base.display_info.bpc == 0 &&
1011 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1012 drm_dbg_kms(&dev_priv->drm,
1013 "clamping bpp for eDP panel to BIOS-provided %i\n",
1014 dev_priv->vbt.edp.bpp);
1015 bpp = dev_priv->vbt.edp.bpp;
1022 /* Adjust link config limits based on compliance test requests. */
1024 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1025 struct intel_crtc_state *pipe_config,
1026 struct link_config_limits *limits)
1028 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1030 /* For DP Compliance we override the computed bpp for the pipe */
1031 if (intel_dp->compliance.test_data.bpc != 0) {
1032 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1034 limits->min_bpp = limits->max_bpp = bpp;
1035 pipe_config->dither_force_disable = bpp == 6 * 3;
1037 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1040 /* Use values requested by Compliance Test Request */
1041 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1044 /* Validate the compliance test data since max values
1045 * might have changed due to link train fallback.
1047 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1048 intel_dp->compliance.test_lane_count)) {
1049 index = intel_dp_rate_index(intel_dp->common_rates,
1050 intel_dp->num_common_rates,
1051 intel_dp->compliance.test_link_rate);
1053 limits->min_clock = limits->max_clock = index;
1054 limits->min_lane_count = limits->max_lane_count =
1055 intel_dp->compliance.test_lane_count;
1060 /* Optimize link config in order: max bpp, min clock, min lanes */
1062 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1063 struct intel_crtc_state *pipe_config,
1064 const struct link_config_limits *limits)
1066 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1067 int bpp, clock, lane_count;
1068 int mode_rate, link_clock, link_avail;
1070 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1071 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1073 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1076 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1077 for (lane_count = limits->min_lane_count;
1078 lane_count <= limits->max_lane_count;
1080 link_clock = intel_dp->common_rates[clock];
1081 link_avail = intel_dp_max_data_rate(link_clock,
1084 if (mode_rate <= link_avail) {
1085 pipe_config->lane_count = lane_count;
1086 pipe_config->pipe_bpp = bpp;
1087 pipe_config->port_clock = link_clock;
1098 /* Optimize link config in order: max bpp, min lanes, min clock */
1100 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1101 struct intel_crtc_state *pipe_config,
1102 const struct link_config_limits *limits)
1104 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1105 int bpp, clock, lane_count;
1106 int mode_rate, link_clock, link_avail;
1108 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1109 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1111 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1114 for (lane_count = limits->min_lane_count;
1115 lane_count <= limits->max_lane_count;
1117 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1118 link_clock = intel_dp->common_rates[clock];
1119 link_avail = intel_dp_max_data_rate(link_clock,
1122 if (mode_rate <= link_avail) {
1123 pipe_config->lane_count = lane_count;
1124 pipe_config->pipe_bpp = bpp;
1125 pipe_config->port_clock = link_clock;
1136 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1139 u8 dsc_bpc[3] = {0};
1141 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1143 for (i = 0; i < num_bpc; i++) {
1144 if (dsc_max_bpc >= dsc_bpc[i])
1145 return dsc_bpc[i] * 3;
1151 #define DSC_SUPPORTED_VERSION_MIN 1
1153 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1154 struct intel_crtc_state *crtc_state)
1156 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1157 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1158 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1163 * RC_MODEL_SIZE is currently a constant across all configurations.
1165 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1166 * DP_DSC_RC_BUF_SIZE for this.
1168 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1170 ret = intel_dsc_compute_params(encoder, crtc_state);
1175 * Slice Height of 8 works for all currently available panels. So start
1176 * with that if pic_height is an integral multiple of 8. Eventually add
1177 * logic to try multiple slice heights.
1179 if (vdsc_cfg->pic_height % 8 == 0)
1180 vdsc_cfg->slice_height = 8;
1181 else if (vdsc_cfg->pic_height % 4 == 0)
1182 vdsc_cfg->slice_height = 4;
1184 vdsc_cfg->slice_height = 2;
1186 vdsc_cfg->dsc_version_major =
1187 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1188 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1189 vdsc_cfg->dsc_version_minor =
1190 min(DSC_SUPPORTED_VERSION_MIN,
1191 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1192 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1194 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1197 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1198 if (!line_buf_depth) {
1199 drm_dbg_kms(&i915->drm,
1200 "DSC Sink Line Buffer Depth invalid\n");
1204 if (vdsc_cfg->dsc_version_minor == 2)
1205 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1206 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1208 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1209 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1211 vdsc_cfg->block_pred_enable =
1212 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1213 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1215 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1218 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1219 struct intel_crtc_state *pipe_config,
1220 struct drm_connector_state *conn_state,
1221 struct link_config_limits *limits)
1223 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1224 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1225 const struct drm_display_mode *adjusted_mode =
1226 &pipe_config->hw.adjusted_mode;
1231 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1232 intel_dp_supports_fec(intel_dp, pipe_config);
1234 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1237 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1238 if (INTEL_GEN(dev_priv) >= 12)
1239 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1241 dsc_max_bpc = min_t(u8, 10,
1242 conn_state->max_requested_bpc);
1244 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1246 /* Min Input BPC for ICL+ is 8 */
1247 if (pipe_bpp < 8 * 3) {
1248 drm_dbg_kms(&dev_priv->drm,
1249 "No DSC support for less than 8bpc\n");
1254 * For now enable DSC for max bpp, max link rate, max lane count.
1255 * Optimize this later for the minimum possible link rate/lane count
1256 * with DSC enabled for the requested mode.
1258 pipe_config->pipe_bpp = pipe_bpp;
1259 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1260 pipe_config->lane_count = limits->max_lane_count;
1262 if (intel_dp_is_edp(intel_dp)) {
1263 pipe_config->dsc.compressed_bpp =
1264 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1265 pipe_config->pipe_bpp);
1266 pipe_config->dsc.slice_count =
1267 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1270 u16 dsc_max_output_bpp;
1271 u8 dsc_dp_slice_count;
1273 dsc_max_output_bpp =
1274 intel_dp_dsc_get_output_bpp(dev_priv,
1275 pipe_config->port_clock,
1276 pipe_config->lane_count,
1277 adjusted_mode->crtc_clock,
1278 adjusted_mode->crtc_hdisplay,
1279 pipe_config->bigjoiner);
1280 dsc_dp_slice_count =
1281 intel_dp_dsc_get_slice_count(intel_dp,
1282 adjusted_mode->crtc_clock,
1283 adjusted_mode->crtc_hdisplay,
1284 pipe_config->bigjoiner);
1285 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1286 drm_dbg_kms(&dev_priv->drm,
1287 "Compressed BPP/Slice Count not supported\n");
1290 pipe_config->dsc.compressed_bpp = min_t(u16,
1291 dsc_max_output_bpp >> 4,
1292 pipe_config->pipe_bpp);
1293 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1296 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1297 * is greater than the maximum Cdclock and if slice count is even
1298 * then we need to use 2 VDSC instances.
1300 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1301 pipe_config->bigjoiner) {
1302 if (pipe_config->dsc.slice_count < 2) {
1303 drm_dbg_kms(&dev_priv->drm,
1304 "Cannot split stream to use 2 VDSC instances\n");
1308 pipe_config->dsc.dsc_split = true;
1311 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1313 drm_dbg_kms(&dev_priv->drm,
1314 "Cannot compute valid DSC parameters for Input Bpp = %d "
1315 "Compressed BPP = %d\n",
1316 pipe_config->pipe_bpp,
1317 pipe_config->dsc.compressed_bpp);
1321 pipe_config->dsc.compression_enable = true;
1322 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1323 "Compressed Bpp = %d Slice Count = %d\n",
1324 pipe_config->pipe_bpp,
1325 pipe_config->dsc.compressed_bpp,
1326 pipe_config->dsc.slice_count);
1332 intel_dp_compute_link_config(struct intel_encoder *encoder,
1333 struct intel_crtc_state *pipe_config,
1334 struct drm_connector_state *conn_state)
1336 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1337 const struct drm_display_mode *adjusted_mode =
1338 &pipe_config->hw.adjusted_mode;
1339 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1340 struct link_config_limits limits;
1344 common_len = intel_dp_common_len_rate_limit(intel_dp,
1345 intel_dp->max_link_rate);
1347 /* No common link rates between source and sink */
1348 drm_WARN_ON(encoder->base.dev, common_len <= 0);
1350 limits.min_clock = 0;
1351 limits.max_clock = common_len - 1;
1353 limits.min_lane_count = 1;
1354 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1356 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1357 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1359 if (intel_dp->use_max_params) {
1361 * Use the maximum clock and number of lanes the eDP panel
1362 * advertizes being capable of in case the initial fast
1363 * optimal params failed us. The panels are generally
1364 * designed to support only a single clock and lane
1365 * configuration, and typically on older panels these
1366 * values correspond to the native resolution of the panel.
1368 limits.min_lane_count = limits.max_lane_count;
1369 limits.min_clock = limits.max_clock;
1372 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1374 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1375 "max rate %d max bpp %d pixel clock %iKHz\n",
1376 limits.max_lane_count,
1377 intel_dp->common_rates[limits.max_clock],
1378 limits.max_bpp, adjusted_mode->crtc_clock);
1380 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1381 adjusted_mode->crtc_hdisplay > 5120) &&
1382 intel_dp_can_bigjoiner(intel_dp))
1383 pipe_config->bigjoiner = true;
1385 if (intel_dp_is_edp(intel_dp))
1387 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
1388 * section A.1: "It is recommended that the minimum number of
1389 * lanes be used, using the minimum link rate allowed for that
1390 * lane configuration."
1392 * Note that we fall back to the max clock and lane count for eDP
1393 * panels that fail with the fast optimal settings (see
1394 * intel_dp->use_max_params), in which case the fast vs. wide
1395 * choice doesn't matter.
1397 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
1399 /* Optimize for slow and wide. */
1400 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1402 /* enable compression if the mode doesn't fit available BW */
1403 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1404 if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
1405 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1406 conn_state, &limits);
1411 if (pipe_config->dsc.compression_enable) {
1412 drm_dbg_kms(&i915->drm,
1413 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1414 pipe_config->lane_count, pipe_config->port_clock,
1415 pipe_config->pipe_bpp,
1416 pipe_config->dsc.compressed_bpp);
1418 drm_dbg_kms(&i915->drm,
1419 "DP link rate required %i available %i\n",
1420 intel_dp_link_required(adjusted_mode->crtc_clock,
1421 pipe_config->dsc.compressed_bpp),
1422 intel_dp_max_data_rate(pipe_config->port_clock,
1423 pipe_config->lane_count));
1425 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1426 pipe_config->lane_count, pipe_config->port_clock,
1427 pipe_config->pipe_bpp);
1429 drm_dbg_kms(&i915->drm,
1430 "DP link rate required %i available %i\n",
1431 intel_dp_link_required(adjusted_mode->crtc_clock,
1432 pipe_config->pipe_bpp),
1433 intel_dp_max_data_rate(pipe_config->port_clock,
1434 pipe_config->lane_count));
1439 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1440 const struct drm_connector_state *conn_state)
1442 const struct intel_digital_connector_state *intel_conn_state =
1443 to_intel_digital_connector_state(conn_state);
1444 const struct drm_display_mode *adjusted_mode =
1445 &crtc_state->hw.adjusted_mode;
1448 * Our YCbCr output is always limited range.
1449 * crtc_state->limited_color_range only applies to RGB,
1450 * and it must never be set for YCbCr or we risk setting
1451 * some conflicting bits in PIPECONF which will mess up
1452 * the colors on the monitor.
1454 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1457 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1460 * CEA-861-E - 5.1 Default Encoding Parameters
1461 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1463 return crtc_state->pipe_bpp != 18 &&
1464 drm_default_rgb_quant_range(adjusted_mode) ==
1465 HDMI_QUANTIZATION_RANGE_LIMITED;
1467 return intel_conn_state->broadcast_rgb ==
1468 INTEL_BROADCAST_RGB_LIMITED;
1472 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1475 if (IS_G4X(dev_priv))
1477 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
1483 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1484 const struct drm_connector_state *conn_state,
1485 struct drm_dp_vsc_sdp *vsc)
1487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1491 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1492 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1493 * Colorimetry Format indication.
1495 vsc->revision = 0x5;
1498 /* DP 1.4a spec, Table 2-120 */
1499 switch (crtc_state->output_format) {
1500 case INTEL_OUTPUT_FORMAT_YCBCR444:
1501 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1503 case INTEL_OUTPUT_FORMAT_YCBCR420:
1504 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1506 case INTEL_OUTPUT_FORMAT_RGB:
1508 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1511 switch (conn_state->colorspace) {
1512 case DRM_MODE_COLORIMETRY_BT709_YCC:
1513 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1515 case DRM_MODE_COLORIMETRY_XVYCC_601:
1516 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1518 case DRM_MODE_COLORIMETRY_XVYCC_709:
1519 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1521 case DRM_MODE_COLORIMETRY_SYCC_601:
1522 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1524 case DRM_MODE_COLORIMETRY_OPYCC_601:
1525 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1527 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1528 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1530 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1531 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1533 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1534 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1536 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1537 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1538 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1542 * RGB->YCBCR color conversion uses the BT.709
1545 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1546 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1548 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1552 vsc->bpc = crtc_state->pipe_bpp / 3;
1554 /* only RGB pixelformat supports 6 bpc */
1555 drm_WARN_ON(&dev_priv->drm,
1556 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1558 /* all YCbCr are always limited range */
1559 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1560 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1563 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1564 struct intel_crtc_state *crtc_state,
1565 const struct drm_connector_state *conn_state)
1567 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1569 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1570 if (crtc_state->has_psr)
1573 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1576 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1577 vsc->sdp_type = DP_SDP_VSC;
1578 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1579 &crtc_state->infoframes.vsc);
1582 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1583 const struct intel_crtc_state *crtc_state,
1584 const struct drm_connector_state *conn_state,
1585 struct drm_dp_vsc_sdp *vsc)
1587 vsc->sdp_type = DP_SDP_VSC;
1589 if (intel_dp->psr.psr2_enabled) {
1590 if (intel_dp->psr.colorimetry_support &&
1591 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1592 /* [PSR2, +Colorimetry] */
1593 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1597 * [PSR2, -Colorimetry]
1598 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1599 * 3D stereo + PSR/PSR2 + Y-coordinate.
1601 vsc->revision = 0x4;
1607 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1608 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1611 vsc->revision = 0x2;
1617 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1618 struct intel_crtc_state *crtc_state,
1619 const struct drm_connector_state *conn_state)
1622 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1623 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1625 if (!conn_state->hdr_output_metadata)
1628 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1631 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1635 crtc_state->infoframes.enable |=
1636 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1640 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1641 struct intel_crtc_state *pipe_config,
1642 int output_bpp, bool constant_n)
1644 struct intel_connector *intel_connector = intel_dp->attached_connector;
1645 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1648 if (pipe_config->vrr.enable)
1652 * DRRS and PSR can't be enable together, so giving preference to PSR
1653 * as it allows more power-savings by complete shutting down display,
1654 * so to guarantee this, intel_dp_drrs_compute_config() must be called
1655 * after intel_psr_compute_config().
1657 if (pipe_config->has_psr)
1660 if (!intel_connector->panel.downclock_mode ||
1661 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1664 pipe_config->has_drrs = true;
1666 pixel_clock = intel_connector->panel.downclock_mode->clock;
1667 if (pipe_config->splitter.enable)
1668 pixel_clock /= pipe_config->splitter.link_count;
1670 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1671 pipe_config->port_clock, &pipe_config->dp_m2_n2,
1672 constant_n, pipe_config->fec_enable);
1674 /* FIXME: abstract this better */
1675 if (pipe_config->splitter.enable)
1676 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1680 intel_dp_compute_config(struct intel_encoder *encoder,
1681 struct intel_crtc_state *pipe_config,
1682 struct drm_connector_state *conn_state)
1684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1685 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1687 enum port port = encoder->port;
1688 struct intel_connector *intel_connector = intel_dp->attached_connector;
1689 struct intel_digital_connector_state *intel_conn_state =
1690 to_intel_digital_connector_state(conn_state);
1691 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1692 int ret = 0, output_bpp;
1694 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1695 pipe_config->has_pch_encoder = true;
1697 pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1700 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1701 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1706 if (!intel_dp_port_has_audio(dev_priv, port))
1707 pipe_config->has_audio = false;
1708 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1709 pipe_config->has_audio = intel_dp->has_audio;
1711 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1713 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1714 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1717 if (HAS_GMCH(dev_priv))
1718 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1720 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1725 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1728 if (HAS_GMCH(dev_priv) &&
1729 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1732 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1735 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1738 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1742 pipe_config->limited_color_range =
1743 intel_dp_limited_color_range(pipe_config, conn_state);
1745 if (pipe_config->dsc.compression_enable)
1746 output_bpp = pipe_config->dsc.compressed_bpp;
1748 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1749 pipe_config->pipe_bpp);
1751 if (intel_dp->mso_link_count) {
1752 int n = intel_dp->mso_link_count;
1753 int overlap = intel_dp->mso_pixel_overlap;
1755 pipe_config->splitter.enable = true;
1756 pipe_config->splitter.link_count = n;
1757 pipe_config->splitter.pixel_overlap = overlap;
1759 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1762 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1763 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1764 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1765 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1766 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1767 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1768 adjusted_mode->crtc_clock /= n;
1771 intel_link_compute_m_n(output_bpp,
1772 pipe_config->lane_count,
1773 adjusted_mode->crtc_clock,
1774 pipe_config->port_clock,
1775 &pipe_config->dp_m_n,
1776 constant_n, pipe_config->fec_enable);
1778 /* FIXME: abstract this better */
1779 if (pipe_config->splitter.enable)
1780 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1782 if (!HAS_DDI(dev_priv))
1783 g4x_dp_set_clock(encoder, pipe_config);
1785 intel_vrr_compute_config(pipe_config, conn_state);
1786 intel_psr_compute_config(intel_dp, pipe_config);
1787 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1789 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1790 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1795 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1796 int link_rate, int lane_count)
1798 intel_dp->link_trained = false;
1799 intel_dp->link_rate = link_rate;
1800 intel_dp->lane_count = lane_count;
1803 /* Enable backlight PWM and backlight PP control. */
1804 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1805 const struct drm_connector_state *conn_state)
1807 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1808 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1810 if (!intel_dp_is_edp(intel_dp))
1813 drm_dbg_kms(&i915->drm, "\n");
1815 intel_panel_enable_backlight(crtc_state, conn_state);
1816 intel_pps_backlight_on(intel_dp);
1819 /* Disable backlight PP control and backlight PWM. */
1820 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1822 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1823 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1825 if (!intel_dp_is_edp(intel_dp))
1828 drm_dbg_kms(&i915->drm, "\n");
1830 intel_pps_backlight_off(intel_dp);
1831 intel_panel_disable_backlight(old_conn_state);
1834 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1837 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1838 * be capable of signalling downstream hpd with a long pulse.
1839 * Whether or not that means D3 is safe to use is not clear,
1840 * but let's assume so until proven otherwise.
1842 * FIXME should really check all downstream ports...
1844 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1845 drm_dp_is_branch(intel_dp->dpcd) &&
1846 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1849 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1850 const struct intel_crtc_state *crtc_state,
1853 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1856 if (!crtc_state->dsc.compression_enable)
1859 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1860 enable ? DP_DECOMPRESSION_EN : 0);
1862 drm_dbg_kms(&i915->drm,
1863 "Failed to %s sink decompression state\n",
1864 enable ? "enable" : "disable");
1868 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1870 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1871 u8 oui[] = { 0x00, 0xaa, 0x01 };
1875 * During driver init, we want to be careful and avoid changing the source OUI if it's
1876 * already set to what we want, so as to avoid clearing any state by accident
1879 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1880 drm_err(&i915->drm, "Failed to read source OUI\n");
1882 if (memcmp(oui, buf, sizeof(oui)) == 0)
1886 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1887 drm_err(&i915->drm, "Failed to write source OUI\n");
1890 /* If the device supports it, try to set the power state appropriately */
1891 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1893 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1894 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1897 /* Should have a valid DPCD by this point */
1898 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1901 if (mode != DP_SET_POWER_D0) {
1902 if (downstream_hpd_needs_d0(intel_dp))
1905 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1907 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1909 lspcon_resume(dp_to_dig_port(intel_dp));
1911 /* Write the source OUI as early as possible */
1912 if (intel_dp_is_edp(intel_dp))
1913 intel_edp_init_source_oui(intel_dp, false);
1916 * When turning on, we need to retry for 1ms to give the sink
1919 for (i = 0; i < 3; i++) {
1920 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1926 if (ret == 1 && lspcon->active)
1927 lspcon_wait_pcon_mode(lspcon);
1931 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1932 encoder->base.base.id, encoder->base.name,
1933 mode == DP_SET_POWER_D0 ? "D0" : "D3");
1937 intel_dp_get_dpcd(struct intel_dp *intel_dp);
1940 * intel_dp_sync_state - sync the encoder state during init/resume
1941 * @encoder: intel encoder to sync
1942 * @crtc_state: state for the CRTC connected to the encoder
1944 * Sync any state stored in the encoder wrt. HW state during driver init
1945 * and system resume.
1947 void intel_dp_sync_state(struct intel_encoder *encoder,
1948 const struct intel_crtc_state *crtc_state)
1950 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1953 * Don't clobber DPCD if it's been already read out during output
1954 * setup (eDP) or detect.
1956 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1957 intel_dp_get_dpcd(intel_dp);
1959 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1960 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1963 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1964 struct intel_crtc_state *crtc_state)
1966 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1967 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1970 * If BIOS has set an unsupported or non-standard link rate for some
1971 * reason force an encoder recompute and full modeset.
1973 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1974 crtc_state->port_clock) < 0) {
1975 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1976 crtc_state->uapi.connectors_changed = true;
1981 * FIXME hack to force full modeset when DSC is being used.
1983 * As long as we do not have full state readout and config comparison
1984 * of crtc_state->dsc, we have no way to ensure reliable fastset.
1985 * Remove once we have readout for DSC.
1987 if (crtc_state->dsc.compression_enable) {
1988 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1989 crtc_state->uapi.mode_changed = true;
1993 if (CAN_PSR(intel_dp)) {
1994 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1995 crtc_state->uapi.mode_changed = true;
2002 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2004 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2006 /* Clear the cached register set to avoid using stale values */
2008 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2010 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2011 intel_dp->pcon_dsc_dpcd,
2012 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2013 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2014 DP_PCON_DSC_ENCODER);
2016 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2017 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2020 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2022 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2025 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2026 if (frl_bw_mask & (1 << i))
2032 static int intel_dp_pcon_set_frl_mask(int max_frl)
2036 return DP_PCON_FRL_BW_MASK_48GBPS;
2038 return DP_PCON_FRL_BW_MASK_40GBPS;
2040 return DP_PCON_FRL_BW_MASK_32GBPS;
2042 return DP_PCON_FRL_BW_MASK_24GBPS;
2044 return DP_PCON_FRL_BW_MASK_18GBPS;
2046 return DP_PCON_FRL_BW_MASK_9GBPS;
2052 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2054 struct intel_connector *intel_connector = intel_dp->attached_connector;
2055 struct drm_connector *connector = &intel_connector->base;
2057 int max_lanes, rate_per_lane;
2058 int max_dsc_lanes, dsc_rate_per_lane;
2060 max_lanes = connector->display_info.hdmi.max_lanes;
2061 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2062 max_frl_rate = max_lanes * rate_per_lane;
2064 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2065 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2066 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2067 if (max_dsc_lanes && dsc_rate_per_lane)
2068 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2071 return max_frl_rate;
2074 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2076 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
2077 #define PCON_CONCURRENT_MODE (1 > 0)
2078 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
2079 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
2080 #define TIMEOUT_FRL_READY_MS 500
2081 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2083 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2084 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2085 u8 max_frl_bw_mask = 0, frl_trained_mask;
2088 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2092 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2093 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2095 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2096 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2098 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2100 if (max_frl_bw <= 0)
2103 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2106 /* Wait for PCON to be FRL Ready */
2107 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2112 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2113 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
2116 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
2119 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2123 * Wait for FRL to be completed
2124 * Check if the HDMI Link is up and active.
2126 wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2131 /* Verify HDMI Link configuration shows FRL Mode */
2132 if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2133 DP_PCON_HDMI_MODE_FRL) {
2134 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2137 drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2139 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2140 intel_dp->frl.is_trained = true;
2141 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2146 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2148 if (drm_dp_is_branch(intel_dp->dpcd) &&
2149 intel_dp->has_hdmi_sink &&
2150 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2156 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2158 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2160 /* Always go for FRL training if supported */
2161 if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2162 intel_dp->frl.is_trained)
2165 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2168 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2169 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2170 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2172 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2173 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2175 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2180 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2182 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2184 return intel_hdmi_dsc_get_slice_height(vactive);
2188 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2189 const struct intel_crtc_state *crtc_state)
2191 struct intel_connector *intel_connector = intel_dp->attached_connector;
2192 struct drm_connector *connector = &intel_connector->base;
2193 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2194 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2195 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2196 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2198 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2199 pcon_max_slice_width,
2200 hdmi_max_slices, hdmi_throughput);
2204 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2205 const struct intel_crtc_state *crtc_state,
2206 int num_slices, int slice_width)
2208 struct intel_connector *intel_connector = intel_dp->attached_connector;
2209 struct drm_connector *connector = &intel_connector->base;
2210 int output_format = crtc_state->output_format;
2211 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2212 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2213 int hdmi_max_chunk_bytes =
2214 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2216 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2217 num_slices, output_format, hdmi_all_bpp,
2218 hdmi_max_chunk_bytes);
2222 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2223 const struct intel_crtc_state *crtc_state)
2231 struct intel_connector *intel_connector = intel_dp->attached_connector;
2232 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2233 struct drm_connector *connector;
2234 bool hdmi_is_dsc_1_2;
2236 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2239 if (!intel_connector)
2241 connector = &intel_connector->base;
2242 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2244 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2248 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2252 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2256 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2259 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2260 num_slices, slice_width);
2261 if (!bits_per_pixel)
2264 pps_param[0] = slice_height & 0xFF;
2265 pps_param[1] = slice_height >> 8;
2266 pps_param[2] = slice_width & 0xFF;
2267 pps_param[3] = slice_width >> 8;
2268 pps_param[4] = bits_per_pixel & 0xFF;
2269 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2271 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2273 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2276 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2277 const struct intel_crtc_state *crtc_state)
2279 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2282 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2285 if (!drm_dp_is_branch(intel_dp->dpcd))
2288 tmp = intel_dp->has_hdmi_sink ?
2289 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2291 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2292 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2293 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
2294 enableddisabled(intel_dp->has_hdmi_sink));
2296 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2297 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2299 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2300 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2301 drm_dbg_kms(&i915->drm,
2302 "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
2303 enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
2306 if (intel_dp->dfp.rgb_to_ycbcr) {
2310 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2311 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2314 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2316 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2317 intel_dp->downstream_ports,
2318 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2319 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2320 intel_dp->downstream_ports,
2321 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2322 switch (crtc_state->infoframes.vsc.colorimetry) {
2323 case DP_COLORIMETRY_BT2020_RGB:
2324 case DP_COLORIMETRY_BT2020_YCC:
2326 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2328 case DP_COLORIMETRY_BT709_YCC:
2329 case DP_COLORIMETRY_XVYCC_709:
2331 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2338 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2339 drm_dbg_kms(&i915->drm,
2340 "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
2341 enableddisabled(tmp ? true : false));
2345 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2349 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2352 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2355 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2357 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2360 * Clear the cached register set to avoid using stale values
2361 * for the sinks that do not support DSC.
2363 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2365 /* Clear fec_capable to avoid using stale values */
2366 intel_dp->fec_capable = 0;
2368 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2369 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2370 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2371 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2373 sizeof(intel_dp->dsc_dpcd)) < 0)
2375 "Failed to read DPCD register 0x%x\n",
2378 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2379 (int)sizeof(intel_dp->dsc_dpcd),
2380 intel_dp->dsc_dpcd);
2382 /* FEC is supported only on DP 1.4 */
2383 if (!intel_dp_is_edp(intel_dp) &&
2384 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2385 &intel_dp->fec_capable) < 0)
2387 "Failed to read FEC DPCD register\n");
2389 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2390 intel_dp->fec_capable);
2394 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2395 struct drm_display_mode *mode)
2397 struct intel_dp *intel_dp = intel_attached_dp(connector);
2398 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2399 int n = intel_dp->mso_link_count;
2400 int overlap = intel_dp->mso_pixel_overlap;
2405 mode->hdisplay = (mode->hdisplay - overlap) * n;
2406 mode->hsync_start = (mode->hsync_start - overlap) * n;
2407 mode->hsync_end = (mode->hsync_end - overlap) * n;
2408 mode->htotal = (mode->htotal - overlap) * n;
2411 drm_mode_set_name(mode);
2413 drm_dbg_kms(&i915->drm,
2414 "[CONNECTOR:%d:%s] using generated MSO mode: ",
2415 connector->base.base.id, connector->base.name);
2416 drm_mode_debug_printmodeline(mode);
2419 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2421 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2424 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2427 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2428 drm_err(&i915->drm, "Failed to read MSO cap\n");
2432 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2433 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2434 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2435 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2440 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2441 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2442 if (!HAS_MSO(i915)) {
2443 drm_err(&i915->drm, "No source MSO support, disabling\n");
2448 intel_dp->mso_link_count = mso;
2449 intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2453 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2455 struct drm_i915_private *dev_priv =
2456 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2458 /* this function is meant to be called only once */
2459 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2461 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2464 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2465 drm_dp_is_branch(intel_dp->dpcd));
2468 * Read the eDP display control registers.
2470 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2471 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2472 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2473 * method). The display control registers should read zero if they're
2474 * not supported anyway.
2476 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2477 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2478 sizeof(intel_dp->edp_dpcd))
2479 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2480 (int)sizeof(intel_dp->edp_dpcd),
2481 intel_dp->edp_dpcd);
2484 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2485 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2487 intel_psr_init_dpcd(intel_dp);
2489 /* Read the eDP 1.4+ supported link rates. */
2490 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2491 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2494 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2495 sink_rates, sizeof(sink_rates));
2497 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2498 int val = le16_to_cpu(sink_rates[i]);
2503 /* Value read multiplied by 200kHz gives the per-lane
2504 * link rate in kHz. The source rates are, however,
2505 * stored in terms of LS_Clk kHz. The full conversion
2506 * back to symbols is
2507 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2509 intel_dp->sink_rates[i] = (val * 200) / 10;
2511 intel_dp->num_sink_rates = i;
2515 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2516 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2518 if (intel_dp->num_sink_rates)
2519 intel_dp->use_rate_select = true;
2521 intel_dp_set_sink_rates(intel_dp);
2523 intel_dp_set_common_rates(intel_dp);
2525 /* Read the eDP DSC DPCD registers */
2526 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2527 intel_dp_get_dsc_sink_cap(intel_dp);
2530 * If needed, program our source OUI so we can make various Intel-specific AUX services
2531 * available (such as HDR backlight controls)
2533 intel_edp_init_source_oui(intel_dp, true);
2535 intel_edp_mso_init(intel_dp);
2541 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2543 if (!intel_dp->attached_connector)
2546 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2552 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2556 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2560 * Don't clobber cached eDP rates. Also skip re-reading
2561 * the OUI/ID since we know it won't change.
2563 if (!intel_dp_is_edp(intel_dp)) {
2564 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2565 drm_dp_is_branch(intel_dp->dpcd));
2567 intel_dp_set_sink_rates(intel_dp);
2568 intel_dp_set_common_rates(intel_dp);
2571 if (intel_dp_has_sink_count(intel_dp)) {
2572 ret = drm_dp_read_sink_count(&intel_dp->aux);
2577 * Sink count can change between short pulse hpd hence
2578 * a member variable in intel_dp will track any changes
2579 * between short pulse interrupts.
2581 intel_dp->sink_count = ret;
2584 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2585 * a dongle is present but no display. Unless we require to know
2586 * if a dongle is present or not, we don't need to update
2587 * downstream port information. So, an early return here saves
2588 * time from performing other operations which are not required.
2590 if (!intel_dp->sink_count)
2594 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2595 intel_dp->downstream_ports) == 0;
2599 intel_dp_can_mst(struct intel_dp *intel_dp)
2601 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2603 return i915->params.enable_dp_mst &&
2604 intel_dp->can_mst &&
2605 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2609 intel_dp_configure_mst(struct intel_dp *intel_dp)
2611 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2612 struct intel_encoder *encoder =
2613 &dp_to_dig_port(intel_dp)->base;
2614 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2616 drm_dbg_kms(&i915->drm,
2617 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2618 encoder->base.base.id, encoder->base.name,
2619 yesno(intel_dp->can_mst), yesno(sink_can_mst),
2620 yesno(i915->params.enable_dp_mst));
2622 if (!intel_dp->can_mst)
2625 intel_dp->is_mst = sink_can_mst &&
2626 i915->params.enable_dp_mst;
2628 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2633 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2635 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2636 sink_irq_vector, DP_DPRX_ESI_LEN) ==
2641 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2642 const struct drm_connector_state *conn_state)
2645 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2646 * of Color Encoding Format and Content Color Gamut], in order to
2647 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2649 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2652 switch (conn_state->colorspace) {
2653 case DRM_MODE_COLORIMETRY_SYCC_601:
2654 case DRM_MODE_COLORIMETRY_OPYCC_601:
2655 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2656 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2657 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2666 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2667 struct dp_sdp *sdp, size_t size)
2669 size_t length = sizeof(struct dp_sdp);
2674 memset(sdp, 0, size);
2677 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2678 * VSC SDP Header Bytes
2680 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2681 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2682 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2683 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2686 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2689 if (vsc->revision != 0x5)
2692 /* VSC SDP Payload for DB16 through DB18 */
2693 /* Pixel Encoding and Colorimetry Formats */
2694 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2695 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2702 sdp->db[17] = 0x1; /* DB17[3:0] */
2714 MISSING_CASE(vsc->bpc);
2717 /* Dynamic Range and Component Bit Depth */
2718 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2719 sdp->db[17] |= 0x80; /* DB17[7] */
2722 sdp->db[18] = vsc->content_type & 0x7;
2729 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2733 size_t length = sizeof(struct dp_sdp);
2734 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2735 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2741 memset(sdp, 0, size);
2743 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2745 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2749 if (len != infoframe_size) {
2750 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2755 * Set up the infoframe sdp packet for HDR static metadata.
2756 * Prepare VSC Header for SU as per DP 1.4a spec,
2757 * Table 2-100 and Table 2-101
2760 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2761 sdp->sdp_header.HB0 = 0;
2763 * Packet Type 80h + Non-audio INFOFRAME Type value
2764 * HDMI_INFOFRAME_TYPE_DRM: 0x87
2765 * - 80h + Non-audio INFOFRAME Type value
2766 * - InfoFrame Type: 0x07
2767 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2769 sdp->sdp_header.HB1 = drm_infoframe->type;
2771 * Least Significant Eight Bits of (Data Byte Count – 1)
2772 * infoframe_size - 1
2774 sdp->sdp_header.HB2 = 0x1D;
2775 /* INFOFRAME SDP Version Number */
2776 sdp->sdp_header.HB3 = (0x13 << 2);
2777 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2778 sdp->db[0] = drm_infoframe->version;
2779 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2780 sdp->db[1] = drm_infoframe->length;
2782 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2783 * HDMI_INFOFRAME_HEADER_SIZE
2785 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2786 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2787 HDMI_DRM_INFOFRAME_SIZE);
2790 * Size of DP infoframe sdp packet for HDR static metadata consists of
2791 * - DP SDP Header(struct dp_sdp_header): 4 bytes
2792 * - Two Data Blocks: 2 bytes
2793 * CTA Header Byte2 (INFOFRAME Version Number)
2794 * CTA Header Byte3 (Length of INFOFRAME)
2795 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2797 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2798 * infoframe size. But GEN11+ has larger than that size, write_infoframe
2799 * will pad rest of the size.
2801 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2804 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2805 const struct intel_crtc_state *crtc_state,
2808 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2809 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2810 struct dp_sdp sdp = {};
2813 if ((crtc_state->infoframes.enable &
2814 intel_hdmi_infoframe_enable(type)) == 0)
2819 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2822 case HDMI_PACKET_TYPE_GAMUT_METADATA:
2823 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2831 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2834 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2837 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2838 const struct intel_crtc_state *crtc_state,
2839 struct drm_dp_vsc_sdp *vsc)
2841 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2843 struct dp_sdp sdp = {};
2846 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2848 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2851 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2855 void intel_dp_set_infoframes(struct intel_encoder *encoder,
2857 const struct intel_crtc_state *crtc_state,
2858 const struct drm_connector_state *conn_state)
2860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2861 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2862 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2863 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2864 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2865 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2866 u32 val = intel_de_read(dev_priv, reg);
2868 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
2869 /* When PSR is enabled, this routine doesn't disable VSC DIP */
2870 if (intel_psr_enabled(intel_dp))
2873 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
2876 intel_de_write(dev_priv, reg, val);
2877 intel_de_posting_read(dev_priv, reg);
2881 intel_de_write(dev_priv, reg, val);
2882 intel_de_posting_read(dev_priv, reg);
2884 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2885 if (!intel_psr_enabled(intel_dp))
2886 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2888 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2891 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2892 const void *buffer, size_t size)
2894 const struct dp_sdp *sdp = buffer;
2896 if (size < sizeof(struct dp_sdp))
2899 memset(vsc, 0, size);
2901 if (sdp->sdp_header.HB0 != 0)
2904 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2907 vsc->sdp_type = sdp->sdp_header.HB1;
2908 vsc->revision = sdp->sdp_header.HB2;
2909 vsc->length = sdp->sdp_header.HB3;
2911 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2912 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2914 * - HB2 = 0x2, HB3 = 0x8
2915 * VSC SDP supporting 3D stereo + PSR
2916 * - HB2 = 0x4, HB3 = 0xe
2917 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2918 * first scan line of the SU region (applies to eDP v1.4b
2922 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2924 * - HB2 = 0x5, HB3 = 0x13
2925 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2928 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2929 vsc->colorimetry = sdp->db[16] & 0xf;
2930 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2932 switch (sdp->db[17] & 0x7) {
2949 MISSING_CASE(sdp->db[17] & 0x7);
2953 vsc->content_type = sdp->db[18] & 0x7;
2962 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2963 const void *buffer, size_t size)
2967 const struct dp_sdp *sdp = buffer;
2969 if (size < sizeof(struct dp_sdp))
2972 if (sdp->sdp_header.HB0 != 0)
2975 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2979 * Least Significant Eight Bits of (Data Byte Count – 1)
2980 * 1Dh (i.e., Data Byte Count = 30 bytes).
2982 if (sdp->sdp_header.HB2 != 0x1D)
2985 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2986 if ((sdp->sdp_header.HB3 & 0x3) != 0)
2989 /* INFOFRAME SDP Version Number */
2990 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2993 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2994 if (sdp->db[0] != 1)
2997 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2998 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3001 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3002 HDMI_DRM_INFOFRAME_SIZE);
3007 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3008 struct intel_crtc_state *crtc_state,
3009 struct drm_dp_vsc_sdp *vsc)
3011 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3012 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3014 unsigned int type = DP_SDP_VSC;
3015 struct dp_sdp sdp = {};
3018 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3019 if (intel_psr_enabled(intel_dp))
3022 if ((crtc_state->infoframes.enable &
3023 intel_hdmi_infoframe_enable(type)) == 0)
3026 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3028 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3031 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3034 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3035 struct intel_crtc_state *crtc_state,
3036 struct hdmi_drm_infoframe *drm_infoframe)
3038 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3040 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3041 struct dp_sdp sdp = {};
3044 if ((crtc_state->infoframes.enable &
3045 intel_hdmi_infoframe_enable(type)) == 0)
3048 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3051 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3055 drm_dbg_kms(&dev_priv->drm,
3056 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3059 void intel_read_dp_sdp(struct intel_encoder *encoder,
3060 struct intel_crtc_state *crtc_state,
3063 if (encoder->type != INTEL_OUTPUT_DDI)
3068 intel_read_dp_vsc_sdp(encoder, crtc_state,
3069 &crtc_state->infoframes.vsc);
3071 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3072 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3073 &crtc_state->infoframes.drm.drm);
3081 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3083 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3086 u8 test_lane_count, test_link_bw;
3090 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3091 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3095 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3098 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3100 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3103 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3106 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3108 /* Validate the requested link rate and lane count */
3109 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3113 intel_dp->compliance.test_lane_count = test_lane_count;
3114 intel_dp->compliance.test_link_rate = test_link_rate;
3119 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3121 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3124 __be16 h_width, v_height;
3127 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3128 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3131 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3134 if (test_pattern != DP_COLOR_RAMP)
3137 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3140 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3144 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3147 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3151 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3154 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3157 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3159 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3161 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3162 case DP_TEST_BIT_DEPTH_6:
3163 intel_dp->compliance.test_data.bpc = 6;
3165 case DP_TEST_BIT_DEPTH_8:
3166 intel_dp->compliance.test_data.bpc = 8;
3172 intel_dp->compliance.test_data.video_pattern = test_pattern;
3173 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3174 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3175 /* Set test active flag here so userspace doesn't interrupt things */
3176 intel_dp->compliance.test_active = true;
3181 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3183 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3184 u8 test_result = DP_TEST_ACK;
3185 struct intel_connector *intel_connector = intel_dp->attached_connector;
3186 struct drm_connector *connector = &intel_connector->base;
3188 if (intel_connector->detect_edid == NULL ||
3189 connector->edid_corrupt ||
3190 intel_dp->aux.i2c_defer_count > 6) {
3191 /* Check EDID read for NACKs, DEFERs and corruption
3192 * (DP CTS 1.2 Core r1.1)
3193 * 4.2.2.4 : Failed EDID read, I2C_NAK
3194 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3195 * 4.2.2.6 : EDID corruption detected
3196 * Use failsafe mode for all cases
3198 if (intel_dp->aux.i2c_nack_count > 0 ||
3199 intel_dp->aux.i2c_defer_count > 0)
3200 drm_dbg_kms(&i915->drm,
3201 "EDID read had %d NACKs, %d DEFERs\n",
3202 intel_dp->aux.i2c_nack_count,
3203 intel_dp->aux.i2c_defer_count);
3204 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3206 struct edid *block = intel_connector->detect_edid;
3208 /* We have to write the checksum
3209 * of the last block read
3211 block += intel_connector->detect_edid->extensions;
3213 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3214 block->checksum) <= 0)
3215 drm_dbg_kms(&i915->drm,
3216 "Failed to write EDID checksum\n");
3218 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3219 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3222 /* Set test active flag here so userspace doesn't interrupt things */
3223 intel_dp->compliance.test_active = true;
3228 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3229 const struct intel_crtc_state *crtc_state)
3231 struct drm_i915_private *dev_priv =
3232 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3233 struct drm_dp_phy_test_params *data =
3234 &intel_dp->compliance.test_data.phytest;
3235 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3236 enum pipe pipe = crtc->pipe;
3239 switch (data->phy_pattern) {
3240 case DP_PHY_TEST_PATTERN_NONE:
3241 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3242 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3244 case DP_PHY_TEST_PATTERN_D10_2:
3245 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3246 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3247 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3249 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3250 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3251 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3252 DDI_DP_COMP_CTL_ENABLE |
3253 DDI_DP_COMP_CTL_SCRAMBLED_0);
3255 case DP_PHY_TEST_PATTERN_PRBS7:
3256 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3257 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3258 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3260 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3262 * FIXME: Ideally pattern should come from DPCD 0x250. As
3263 * current firmware of DPR-100 could not set it, so hardcoding
3264 * now for complaince test.
3266 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3267 pattern_val = 0x3e0f83e0;
3268 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3269 pattern_val = 0x0f83e0f8;
3270 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3271 pattern_val = 0x0000f83e;
3272 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3273 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3274 DDI_DP_COMP_CTL_ENABLE |
3275 DDI_DP_COMP_CTL_CUSTOM80);
3277 case DP_PHY_TEST_PATTERN_CP2520:
3279 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3280 * current firmware of DPR-100 could not set it, so hardcoding
3281 * now for complaince test.
3283 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3285 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3286 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3290 WARN(1, "Invalid Phy Test Pattern\n");
3295 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3296 const struct intel_crtc_state *crtc_state)
3298 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3299 struct drm_device *dev = dig_port->base.base.dev;
3300 struct drm_i915_private *dev_priv = to_i915(dev);
3301 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3302 enum pipe pipe = crtc->pipe;
3303 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3305 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3306 TRANS_DDI_FUNC_CTL(pipe));
3307 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3308 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3310 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3311 TGL_TRANS_DDI_PORT_MASK);
3312 trans_conf_value &= ~PIPECONF_ENABLE;
3313 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3315 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3316 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3317 trans_ddi_func_ctl_value);
3318 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3322 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3323 const struct intel_crtc_state *crtc_state)
3325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3326 struct drm_device *dev = dig_port->base.base.dev;
3327 struct drm_i915_private *dev_priv = to_i915(dev);
3328 enum port port = dig_port->base.port;
3329 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3330 enum pipe pipe = crtc->pipe;
3331 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3333 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3334 TRANS_DDI_FUNC_CTL(pipe));
3335 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3336 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3338 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3339 TGL_TRANS_DDI_SELECT_PORT(port);
3340 trans_conf_value |= PIPECONF_ENABLE;
3341 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3343 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3344 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3345 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3346 trans_ddi_func_ctl_value);
3349 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3350 const struct intel_crtc_state *crtc_state)
3352 struct drm_dp_phy_test_params *data =
3353 &intel_dp->compliance.test_data.phytest;
3354 u8 link_status[DP_LINK_STATUS_SIZE];
3356 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3358 DRM_DEBUG_KMS("failed to get link status\n");
3362 /* retrieve vswing & pre-emphasis setting */
3363 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3366 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3368 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3370 intel_dp_phy_pattern_update(intel_dp, crtc_state);
3372 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3374 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3375 link_status[DP_DPCD_REV]);
3378 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3380 struct drm_dp_phy_test_params *data =
3381 &intel_dp->compliance.test_data.phytest;
3383 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3384 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3388 /* Set test active flag here so userspace doesn't interrupt things */
3389 intel_dp->compliance.test_active = true;
3394 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3396 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3397 u8 response = DP_TEST_NAK;
3401 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3403 drm_dbg_kms(&i915->drm,
3404 "Could not read test request from sink\n");
3409 case DP_TEST_LINK_TRAINING:
3410 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3411 response = intel_dp_autotest_link_training(intel_dp);
3413 case DP_TEST_LINK_VIDEO_PATTERN:
3414 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3415 response = intel_dp_autotest_video_pattern(intel_dp);
3417 case DP_TEST_LINK_EDID_READ:
3418 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3419 response = intel_dp_autotest_edid(intel_dp);
3421 case DP_TEST_LINK_PHY_TEST_PATTERN:
3422 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3423 response = intel_dp_autotest_phy_pattern(intel_dp);
3426 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3431 if (response & DP_TEST_ACK)
3432 intel_dp->compliance.test_type = request;
3435 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3437 drm_dbg_kms(&i915->drm,
3438 "Could not write test response to sink\n");
3442 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3444 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3446 if (esi[1] & DP_CP_IRQ) {
3447 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3453 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3454 * @intel_dp: Intel DP struct
3456 * Read any pending MST interrupts, call MST core to handle these and ack the
3457 * interrupts. Check if the main and AUX link state is ok.
3460 * - %true if pending interrupts were serviced (or no interrupts were
3461 * pending) w/o detecting an error condition.
3462 * - %false if an error condition - like AUX failure or a loss of link - is
3463 * detected, which needs servicing from the hotplug work.
3466 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3468 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3469 bool link_ok = true;
3471 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3474 u8 esi[DP_DPRX_ESI_LEN] = {};
3478 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3479 drm_dbg_kms(&i915->drm,
3480 "failed to get ESI - device may have failed\n");
3486 /* check link status - esi[10] = 0x200c */
3487 if (intel_dp->active_mst_links > 0 && link_ok &&
3488 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3489 drm_dbg_kms(&i915->drm,
3490 "channel EQ not ok, retraining\n");
3494 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3496 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3501 for (retry = 0; retry < 3; retry++) {
3504 wret = drm_dp_dpcd_write(&intel_dp->aux,
3505 DP_SINK_COUNT_ESI+1,
3516 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3521 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3522 if (intel_dp->frl.is_trained && !is_active) {
3523 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3526 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
3527 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3530 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3532 /* Restart FRL training or fall back to TMDS mode */
3533 intel_dp_check_frl_training(intel_dp);
3538 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3540 u8 link_status[DP_LINK_STATUS_SIZE];
3542 if (!intel_dp->link_trained)
3546 * While PSR source HW is enabled, it will control main-link sending
3547 * frames, enabling and disabling it so trying to do a retrain will fail
3548 * as the link would or not be on or it could mix training patterns
3549 * and frame data at the same time causing retrain to fail.
3550 * Also when exiting PSR, HW will retrain the link anyways fixing
3551 * any link status error.
3553 if (intel_psr_enabled(intel_dp))
3556 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3561 * Validate the cached values of intel_dp->link_rate and
3562 * intel_dp->lane_count before attempting to retrain.
3564 * FIXME would be nice to user the crtc state here, but since
3565 * we need to call this from the short HPD handler that seems
3568 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3569 intel_dp->lane_count))
3572 /* Retrain if Channel EQ or CR not ok */
3573 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3576 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3577 const struct drm_connector_state *conn_state)
3579 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3580 struct intel_encoder *encoder;
3583 if (!conn_state->best_encoder)
3587 encoder = &dp_to_dig_port(intel_dp)->base;
3588 if (conn_state->best_encoder == &encoder->base)
3592 for_each_pipe(i915, pipe) {
3593 encoder = &intel_dp->mst_encoders[pipe]->base;
3594 if (conn_state->best_encoder == &encoder->base)
3601 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3602 struct drm_modeset_acquire_ctx *ctx,
3605 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3606 struct drm_connector_list_iter conn_iter;
3607 struct intel_connector *connector;
3612 if (!intel_dp_needs_link_retrain(intel_dp))
3615 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3616 for_each_intel_connector_iter(connector, &conn_iter) {
3617 struct drm_connector_state *conn_state =
3618 connector->base.state;
3619 struct intel_crtc_state *crtc_state;
3620 struct intel_crtc *crtc;
3622 if (!intel_dp_has_connector(intel_dp, conn_state))
3625 crtc = to_intel_crtc(conn_state->crtc);
3629 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3633 crtc_state = to_intel_crtc_state(crtc->base.state);
3635 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3637 if (!crtc_state->hw.active)
3640 if (conn_state->commit &&
3641 !try_wait_for_completion(&conn_state->commit->hw_done))
3644 *crtc_mask |= drm_crtc_mask(&crtc->base);
3646 drm_connector_list_iter_end(&conn_iter);
3648 if (!intel_dp_needs_link_retrain(intel_dp))
3654 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3656 struct intel_connector *connector = intel_dp->attached_connector;
3658 return connector->base.status == connector_status_connected ||
3662 int intel_dp_retrain_link(struct intel_encoder *encoder,
3663 struct drm_modeset_acquire_ctx *ctx)
3665 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3666 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3667 struct intel_crtc *crtc;
3671 if (!intel_dp_is_connected(intel_dp))
3674 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3679 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3686 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3687 encoder->base.base.id, encoder->base.name);
3689 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3690 const struct intel_crtc_state *crtc_state =
3691 to_intel_crtc_state(crtc->base.state);
3693 /* Suppress underruns caused by re-training */
3694 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3695 if (crtc_state->has_pch_encoder)
3696 intel_set_pch_fifo_underrun_reporting(dev_priv,
3697 intel_crtc_pch_transcoder(crtc), false);
3700 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3701 const struct intel_crtc_state *crtc_state =
3702 to_intel_crtc_state(crtc->base.state);
3704 /* retrain on the MST master transcoder */
3705 if (INTEL_GEN(dev_priv) >= 12 &&
3706 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3707 !intel_dp_mst_is_master_trans(crtc_state))
3710 intel_dp_check_frl_training(intel_dp);
3711 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3712 intel_dp_start_link_train(intel_dp, crtc_state);
3713 intel_dp_stop_link_train(intel_dp, crtc_state);
3717 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3718 const struct intel_crtc_state *crtc_state =
3719 to_intel_crtc_state(crtc->base.state);
3721 /* Keep underrun reporting disabled until things are stable */
3722 intel_wait_for_vblank(dev_priv, crtc->pipe);
3724 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3725 if (crtc_state->has_pch_encoder)
3726 intel_set_pch_fifo_underrun_reporting(dev_priv,
3727 intel_crtc_pch_transcoder(crtc), true);
3733 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3734 struct drm_modeset_acquire_ctx *ctx,
3737 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3738 struct drm_connector_list_iter conn_iter;
3739 struct intel_connector *connector;
3744 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3745 for_each_intel_connector_iter(connector, &conn_iter) {
3746 struct drm_connector_state *conn_state =
3747 connector->base.state;
3748 struct intel_crtc_state *crtc_state;
3749 struct intel_crtc *crtc;
3751 if (!intel_dp_has_connector(intel_dp, conn_state))
3754 crtc = to_intel_crtc(conn_state->crtc);
3758 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3762 crtc_state = to_intel_crtc_state(crtc->base.state);
3764 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3766 if (!crtc_state->hw.active)
3769 if (conn_state->commit &&
3770 !try_wait_for_completion(&conn_state->commit->hw_done))
3773 *crtc_mask |= drm_crtc_mask(&crtc->base);
3775 drm_connector_list_iter_end(&conn_iter);
3780 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3781 struct drm_modeset_acquire_ctx *ctx)
3783 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3784 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3785 struct intel_crtc *crtc;
3789 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3794 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3801 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3802 encoder->base.base.id, encoder->base.name);
3804 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3805 const struct intel_crtc_state *crtc_state =
3806 to_intel_crtc_state(crtc->base.state);
3808 /* test on the MST master transcoder */
3809 if (INTEL_GEN(dev_priv) >= 12 &&
3810 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3811 !intel_dp_mst_is_master_trans(crtc_state))
3814 intel_dp_process_phy_request(intel_dp, crtc_state);
3821 void intel_dp_phy_test(struct intel_encoder *encoder)
3823 struct drm_modeset_acquire_ctx ctx;
3826 drm_modeset_acquire_init(&ctx, 0);
3829 ret = intel_dp_do_phy_test(encoder, &ctx);
3831 if (ret == -EDEADLK) {
3832 drm_modeset_backoff(&ctx);
3839 drm_modeset_drop_locks(&ctx);
3840 drm_modeset_acquire_fini(&ctx);
3841 drm_WARN(encoder->base.dev, ret,
3842 "Acquiring modeset locks failed with %i\n", ret);
3845 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3847 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3850 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3853 if (drm_dp_dpcd_readb(&intel_dp->aux,
3854 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3857 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3859 if (val & DP_AUTOMATED_TEST_REQUEST)
3860 intel_dp_handle_test_request(intel_dp);
3862 if (val & DP_CP_IRQ)
3863 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3865 if (val & DP_SINK_SPECIFIC_IRQ)
3866 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3869 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3871 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3874 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3877 if (drm_dp_dpcd_readb(&intel_dp->aux,
3878 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
3879 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
3883 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3884 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
3885 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
3889 if (val & HDMI_LINK_STATUS_CHANGED)
3890 intel_dp_handle_hdmi_link_status_change(intel_dp);
3894 * According to DP spec
3897 * 2. Configure link according to Receiver Capabilities
3898 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3899 * 4. Check link status on receipt of hot-plug interrupt
3901 * intel_dp_short_pulse - handles short pulse interrupts
3902 * when full detection is not required.
3903 * Returns %true if short pulse is handled and full detection
3904 * is NOT required and %false otherwise.
3907 intel_dp_short_pulse(struct intel_dp *intel_dp)
3909 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3910 u8 old_sink_count = intel_dp->sink_count;
3914 * Clearing compliance test variables to allow capturing
3915 * of values for next automated test request.
3917 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3920 * Now read the DPCD to see if it's actually running
3921 * If the current value of sink count doesn't match with
3922 * the value that was stored earlier or dpcd read failed
3923 * we need to do full detection
3925 ret = intel_dp_get_dpcd(intel_dp);
3927 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3928 /* No need to proceed if we are going to do full detect */
3932 intel_dp_check_device_service_irq(intel_dp);
3933 intel_dp_check_link_service_irq(intel_dp);
3935 /* Handle CEC interrupts, if any */
3936 drm_dp_cec_irq(&intel_dp->aux);
3938 /* defer to the hotplug work for link retraining if needed */
3939 if (intel_dp_needs_link_retrain(intel_dp))
3942 intel_psr_short_pulse(intel_dp);
3944 switch (intel_dp->compliance.test_type) {
3945 case DP_TEST_LINK_TRAINING:
3946 drm_dbg_kms(&dev_priv->drm,
3947 "Link Training Compliance Test requested\n");
3948 /* Send a Hotplug Uevent to userspace to start modeset */
3949 drm_kms_helper_hotplug_event(&dev_priv->drm);
3951 case DP_TEST_LINK_PHY_TEST_PATTERN:
3952 drm_dbg_kms(&dev_priv->drm,
3953 "PHY test pattern Compliance Test requested\n");
3955 * Schedule long hpd to do the test
3957 * FIXME get rid of the ad-hoc phy test modeset code
3958 * and properly incorporate it into the normal modeset.
3966 /* XXX this is probably wrong for multiple downstream ports */
3967 static enum drm_connector_status
3968 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3970 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3971 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3972 u8 *dpcd = intel_dp->dpcd;
3975 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3976 return connector_status_connected;
3978 lspcon_resume(dig_port);
3980 if (!intel_dp_get_dpcd(intel_dp))
3981 return connector_status_disconnected;
3983 /* if there's no downstream port, we're done */
3984 if (!drm_dp_is_branch(dpcd))
3985 return connector_status_connected;
3987 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3988 if (intel_dp_has_sink_count(intel_dp) &&
3989 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3990 return intel_dp->sink_count ?
3991 connector_status_connected : connector_status_disconnected;
3994 if (intel_dp_can_mst(intel_dp))
3995 return connector_status_connected;
3997 /* If no HPD, poke DDC gently */
3998 if (drm_probe_ddc(&intel_dp->aux.ddc))
3999 return connector_status_connected;
4001 /* Well we tried, say unknown for unreliable port types */
4002 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4003 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4004 if (type == DP_DS_PORT_TYPE_VGA ||
4005 type == DP_DS_PORT_TYPE_NON_EDID)
4006 return connector_status_unknown;
4008 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4009 DP_DWN_STRM_PORT_TYPE_MASK;
4010 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4011 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4012 return connector_status_unknown;
4015 /* Anything else is out of spec, warn and ignore */
4016 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4017 return connector_status_disconnected;
4020 static enum drm_connector_status
4021 edp_detect(struct intel_dp *intel_dp)
4023 return connector_status_connected;
4027 * intel_digital_port_connected - is the specified port connected?
4028 * @encoder: intel_encoder
4030 * In cases where there's a connector physically connected but it can't be used
4031 * by our hardware we also return false, since the rest of the driver should
4032 * pretty much treat the port as disconnected. This is relevant for type-C
4033 * (starting on ICL) where there's ownership involved.
4035 * Return %true if port is connected, %false otherwise.
4037 bool intel_digital_port_connected(struct intel_encoder *encoder)
4039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4040 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4041 bool is_connected = false;
4042 intel_wakeref_t wakeref;
4044 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4045 is_connected = dig_port->connected(encoder);
4047 return is_connected;
4050 static struct edid *
4051 intel_dp_get_edid(struct intel_dp *intel_dp)
4053 struct intel_connector *intel_connector = intel_dp->attached_connector;
4055 /* use cached edid if we have one */
4056 if (intel_connector->edid) {
4058 if (IS_ERR(intel_connector->edid))
4061 return drm_edid_duplicate(intel_connector->edid);
4063 return drm_get_edid(&intel_connector->base,
4064 &intel_dp->aux.ddc);
4068 intel_dp_update_dfp(struct intel_dp *intel_dp,
4069 const struct edid *edid)
4071 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4072 struct intel_connector *connector = intel_dp->attached_connector;
4074 intel_dp->dfp.max_bpc =
4075 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4076 intel_dp->downstream_ports, edid);
4078 intel_dp->dfp.max_dotclock =
4079 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4080 intel_dp->downstream_ports);
4082 intel_dp->dfp.min_tmds_clock =
4083 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4084 intel_dp->downstream_ports,
4086 intel_dp->dfp.max_tmds_clock =
4087 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4088 intel_dp->downstream_ports,
4091 intel_dp->dfp.pcon_max_frl_bw =
4092 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4093 intel_dp->downstream_ports);
4095 drm_dbg_kms(&i915->drm,
4096 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4097 connector->base.base.id, connector->base.name,
4098 intel_dp->dfp.max_bpc,
4099 intel_dp->dfp.max_dotclock,
4100 intel_dp->dfp.min_tmds_clock,
4101 intel_dp->dfp.max_tmds_clock,
4102 intel_dp->dfp.pcon_max_frl_bw);
4104 intel_dp_get_pcon_dsc_cap(intel_dp);
4108 intel_dp_update_420(struct intel_dp *intel_dp)
4110 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4111 struct intel_connector *connector = intel_dp->attached_connector;
4112 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4114 /* No YCbCr output support on gmch platforms */
4119 * ILK doesn't seem capable of DP YCbCr output. The
4120 * displayed image is severly corrupted. SNB+ is fine.
4122 if (IS_GEN(i915, 5))
4125 is_branch = drm_dp_is_branch(intel_dp->dpcd);
4126 ycbcr_420_passthrough =
4127 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4128 intel_dp->downstream_ports);
4129 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4131 dp_to_dig_port(intel_dp)->lspcon.active ||
4132 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4133 intel_dp->downstream_ports);
4134 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4135 intel_dp->downstream_ports,
4136 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4137 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4138 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4140 if (INTEL_GEN(i915) >= 11) {
4141 /* Let PCON convert from RGB->YCbCr if possible */
4142 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4143 intel_dp->dfp.rgb_to_ycbcr = true;
4144 intel_dp->dfp.ycbcr_444_to_420 = true;
4145 connector->base.ycbcr_420_allowed = true;
4147 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4148 intel_dp->dfp.ycbcr_444_to_420 =
4149 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4151 connector->base.ycbcr_420_allowed =
4152 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4155 /* 4:4:4->4:2:0 conversion is the only way */
4156 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4158 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4161 drm_dbg_kms(&i915->drm,
4162 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4163 connector->base.base.id, connector->base.name,
4164 yesno(intel_dp->dfp.rgb_to_ycbcr),
4165 yesno(connector->base.ycbcr_420_allowed),
4166 yesno(intel_dp->dfp.ycbcr_444_to_420));
4170 intel_dp_set_edid(struct intel_dp *intel_dp)
4172 struct intel_connector *connector = intel_dp->attached_connector;
4175 intel_dp_unset_edid(intel_dp);
4176 edid = intel_dp_get_edid(intel_dp);
4177 connector->detect_edid = edid;
4179 intel_dp_update_dfp(intel_dp, edid);
4180 intel_dp_update_420(intel_dp);
4182 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4183 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4184 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4187 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4191 intel_dp_unset_edid(struct intel_dp *intel_dp)
4193 struct intel_connector *connector = intel_dp->attached_connector;
4195 drm_dp_cec_unset_edid(&intel_dp->aux);
4196 kfree(connector->detect_edid);
4197 connector->detect_edid = NULL;
4199 intel_dp->has_hdmi_sink = false;
4200 intel_dp->has_audio = false;
4202 intel_dp->dfp.max_bpc = 0;
4203 intel_dp->dfp.max_dotclock = 0;
4204 intel_dp->dfp.min_tmds_clock = 0;
4205 intel_dp->dfp.max_tmds_clock = 0;
4207 intel_dp->dfp.pcon_max_frl_bw = 0;
4209 intel_dp->dfp.ycbcr_444_to_420 = false;
4210 connector->base.ycbcr_420_allowed = false;
4214 intel_dp_detect(struct drm_connector *connector,
4215 struct drm_modeset_acquire_ctx *ctx,
4218 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4219 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4220 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4221 struct intel_encoder *encoder = &dig_port->base;
4222 enum drm_connector_status status;
4224 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4225 connector->base.id, connector->name);
4226 drm_WARN_ON(&dev_priv->drm,
4227 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4229 if (!INTEL_DISPLAY_ENABLED(dev_priv))
4230 return connector_status_disconnected;
4232 /* Can't disconnect eDP */
4233 if (intel_dp_is_edp(intel_dp))
4234 status = edp_detect(intel_dp);
4235 else if (intel_digital_port_connected(encoder))
4236 status = intel_dp_detect_dpcd(intel_dp);
4238 status = connector_status_disconnected;
4240 if (status == connector_status_disconnected) {
4241 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4242 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4244 if (intel_dp->is_mst) {
4245 drm_dbg_kms(&dev_priv->drm,
4246 "MST device may have disappeared %d vs %d\n",
4248 intel_dp->mst_mgr.mst_state);
4249 intel_dp->is_mst = false;
4250 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4257 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4258 if (INTEL_GEN(dev_priv) >= 11)
4259 intel_dp_get_dsc_sink_cap(intel_dp);
4261 intel_dp_configure_mst(intel_dp);
4264 * TODO: Reset link params when switching to MST mode, until MST
4265 * supports link training fallback params.
4267 if (intel_dp->reset_link_params || intel_dp->is_mst) {
4268 /* Initial max link lane count */
4269 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4271 /* Initial max link rate */
4272 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4274 intel_dp->reset_link_params = false;
4277 intel_dp_print_rates(intel_dp);
4279 if (intel_dp->is_mst) {
4281 * If we are in MST mode then this connector
4282 * won't appear connected or have anything
4285 status = connector_status_disconnected;
4290 * Some external monitors do not signal loss of link synchronization
4291 * with an IRQ_HPD, so force a link status check.
4293 if (!intel_dp_is_edp(intel_dp)) {
4296 ret = intel_dp_retrain_link(encoder, ctx);
4302 * Clearing NACK and defer counts to get their exact values
4303 * while reading EDID which are required by Compliance tests
4304 * 4.2.2.4 and 4.2.2.5
4306 intel_dp->aux.i2c_nack_count = 0;
4307 intel_dp->aux.i2c_defer_count = 0;
4309 intel_dp_set_edid(intel_dp);
4310 if (intel_dp_is_edp(intel_dp) ||
4311 to_intel_connector(connector)->detect_edid)
4312 status = connector_status_connected;
4314 intel_dp_check_device_service_irq(intel_dp);
4317 if (status != connector_status_connected && !intel_dp->is_mst)
4318 intel_dp_unset_edid(intel_dp);
4321 * Make sure the refs for power wells enabled during detect are
4322 * dropped to avoid a new detect cycle triggered by HPD polling.
4324 intel_display_power_flush_work(dev_priv);
4326 if (!intel_dp_is_edp(intel_dp))
4327 drm_dp_set_subconnector_property(connector,
4330 intel_dp->downstream_ports);
4335 intel_dp_force(struct drm_connector *connector)
4337 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4338 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4339 struct intel_encoder *intel_encoder = &dig_port->base;
4340 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4341 enum intel_display_power_domain aux_domain =
4342 intel_aux_power_domain(dig_port);
4343 intel_wakeref_t wakeref;
4345 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4346 connector->base.id, connector->name);
4347 intel_dp_unset_edid(intel_dp);
4349 if (connector->status != connector_status_connected)
4352 wakeref = intel_display_power_get(dev_priv, aux_domain);
4354 intel_dp_set_edid(intel_dp);
4356 intel_display_power_put(dev_priv, aux_domain, wakeref);
4359 static int intel_dp_get_modes(struct drm_connector *connector)
4361 struct intel_connector *intel_connector = to_intel_connector(connector);
4365 edid = intel_connector->detect_edid;
4367 num_modes = intel_connector_update_modes(connector, edid);
4369 if (intel_vrr_is_capable(connector))
4370 drm_connector_set_vrr_capable_property(connector,
4374 /* Also add fixed mode, which may or may not be present in EDID */
4375 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4376 intel_connector->panel.fixed_mode) {
4377 struct drm_display_mode *mode;
4379 mode = drm_mode_duplicate(connector->dev,
4380 intel_connector->panel.fixed_mode);
4382 drm_mode_probed_add(connector, mode);
4391 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4392 struct drm_display_mode *mode;
4394 mode = drm_dp_downstream_mode(connector->dev,
4396 intel_dp->downstream_ports);
4398 drm_mode_probed_add(connector, mode);
4407 intel_dp_connector_register(struct drm_connector *connector)
4409 struct drm_i915_private *i915 = to_i915(connector->dev);
4410 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4411 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4412 struct intel_lspcon *lspcon = &dig_port->lspcon;
4415 ret = intel_connector_register(connector);
4419 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4420 intel_dp->aux.name, connector->kdev->kobj.name);
4422 intel_dp->aux.dev = connector->kdev;
4423 ret = drm_dp_aux_register(&intel_dp->aux);
4425 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4427 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4431 * ToDo: Clean this up to handle lspcon init and resume more
4432 * efficiently and streamlined.
4434 if (lspcon_init(dig_port)) {
4435 lspcon_detect_hdr_capability(lspcon);
4436 if (lspcon->hdr_supported)
4437 drm_object_attach_property(&connector->base,
4438 connector->dev->mode_config.hdr_output_metadata_property,
4446 intel_dp_connector_unregister(struct drm_connector *connector)
4448 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4450 drm_dp_cec_unregister_connector(&intel_dp->aux);
4451 drm_dp_aux_unregister(&intel_dp->aux);
4452 intel_connector_unregister(connector);
4455 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4457 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4458 struct intel_dp *intel_dp = &dig_port->dp;
4460 intel_dp_mst_encoder_cleanup(dig_port);
4462 intel_pps_vdd_off_sync(intel_dp);
4464 intel_dp_aux_fini(intel_dp);
4467 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4469 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4471 intel_pps_vdd_off_sync(intel_dp);
4474 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4476 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4478 intel_pps_wait_power_cycle(intel_dp);
4481 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4484 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4485 struct drm_connector_list_iter conn_iter;
4486 struct drm_connector *connector;
4489 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4490 drm_for_each_connector_iter(connector, &conn_iter) {
4491 struct drm_connector_state *conn_state;
4492 struct intel_crtc_state *crtc_state;
4493 struct intel_crtc *crtc;
4495 if (!connector->has_tile ||
4496 connector->tile_group->id != tile_group_id)
4499 conn_state = drm_atomic_get_connector_state(&state->base,
4501 if (IS_ERR(conn_state)) {
4502 ret = PTR_ERR(conn_state);
4506 crtc = to_intel_crtc(conn_state->crtc);
4511 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4512 crtc_state->uapi.mode_changed = true;
4514 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4518 drm_connector_list_iter_end(&conn_iter);
4523 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4525 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4526 struct intel_crtc *crtc;
4528 if (transcoders == 0)
4531 for_each_intel_crtc(&dev_priv->drm, crtc) {
4532 struct intel_crtc_state *crtc_state;
4535 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4536 if (IS_ERR(crtc_state))
4537 return PTR_ERR(crtc_state);
4539 if (!crtc_state->hw.enable)
4542 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4545 crtc_state->uapi.mode_changed = true;
4547 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4551 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4555 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4558 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4563 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4564 struct drm_connector *connector)
4566 const struct drm_connector_state *old_conn_state =
4567 drm_atomic_get_old_connector_state(&state->base, connector);
4568 const struct intel_crtc_state *old_crtc_state;
4569 struct intel_crtc *crtc;
4572 crtc = to_intel_crtc(old_conn_state->crtc);
4576 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4578 if (!old_crtc_state->hw.active)
4581 transcoders = old_crtc_state->sync_mode_slaves_mask;
4582 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4583 transcoders |= BIT(old_crtc_state->master_transcoder);
4585 return intel_modeset_affected_transcoders(state,
4589 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4590 struct drm_atomic_state *_state)
4592 struct drm_i915_private *dev_priv = to_i915(conn->dev);
4593 struct intel_atomic_state *state = to_intel_atomic_state(_state);
4596 ret = intel_digital_connector_atomic_check(conn, &state->base);
4601 * We don't enable port sync on BDW due to missing w/as and
4602 * due to not having adjusted the modeset sequence appropriately.
4604 if (INTEL_GEN(dev_priv) < 9)
4607 if (!intel_connector_needs_modeset(state, conn))
4610 if (conn->has_tile) {
4611 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4616 return intel_modeset_synced_crtcs(state, conn);
4619 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4620 .force = intel_dp_force,
4621 .fill_modes = drm_helper_probe_single_connector_modes,
4622 .atomic_get_property = intel_digital_connector_atomic_get_property,
4623 .atomic_set_property = intel_digital_connector_atomic_set_property,
4624 .late_register = intel_dp_connector_register,
4625 .early_unregister = intel_dp_connector_unregister,
4626 .destroy = intel_connector_destroy,
4627 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4628 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4631 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4632 .detect_ctx = intel_dp_detect,
4633 .get_modes = intel_dp_get_modes,
4634 .mode_valid = intel_dp_mode_valid,
4635 .atomic_check = intel_dp_connector_atomic_check,
4639 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4641 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4642 struct intel_dp *intel_dp = &dig_port->dp;
4644 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4645 (long_hpd || !intel_pps_have_power(intel_dp))) {
4647 * vdd off can generate a long/short pulse on eDP which
4648 * would require vdd on to handle it, and thus we
4649 * would end up in an endless cycle of
4650 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4652 drm_dbg_kms(&i915->drm,
4653 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4654 long_hpd ? "long" : "short",
4655 dig_port->base.base.base.id,
4656 dig_port->base.base.name);
4660 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4661 dig_port->base.base.base.id,
4662 dig_port->base.base.name,
4663 long_hpd ? "long" : "short");
4666 intel_dp->reset_link_params = true;
4670 if (intel_dp->is_mst) {
4671 if (!intel_dp_check_mst_status(intel_dp))
4673 } else if (!intel_dp_short_pulse(intel_dp)) {
4680 /* check the VBT to see whether the eDP is on another port */
4681 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4684 * eDP not supported on g4x. so bail out early just
4685 * for a bit extra safety in case the VBT is bonkers.
4687 if (INTEL_GEN(dev_priv) < 5)
4690 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
4693 return intel_bios_is_port_edp(dev_priv, port);
4697 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4699 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4700 enum port port = dp_to_dig_port(intel_dp)->base.port;
4702 if (!intel_dp_is_edp(intel_dp))
4703 drm_connector_attach_dp_subconnector_property(connector);
4705 if (!IS_G4X(dev_priv) && port != PORT_A)
4706 intel_attach_force_audio_property(connector);
4708 intel_attach_broadcast_rgb_property(connector);
4709 if (HAS_GMCH(dev_priv))
4710 drm_connector_attach_max_bpc_property(connector, 6, 10);
4711 else if (INTEL_GEN(dev_priv) >= 5)
4712 drm_connector_attach_max_bpc_property(connector, 6, 12);
4714 /* Register HDMI colorspace for case of lspcon */
4715 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4716 drm_connector_attach_content_type_property(connector);
4717 intel_attach_hdmi_colorspace_property(connector);
4719 intel_attach_dp_colorspace_property(connector);
4722 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
4723 drm_object_attach_property(&connector->base,
4724 connector->dev->mode_config.hdr_output_metadata_property,
4727 if (intel_dp_is_edp(intel_dp)) {
4728 u32 allowed_scalers;
4730 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4731 if (!HAS_GMCH(dev_priv))
4732 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4734 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4736 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4740 if (HAS_VRR(dev_priv))
4741 drm_connector_attach_vrr_capable_property(connector);
4745 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4746 * @dev_priv: i915 device
4747 * @crtc_state: a pointer to the active intel_crtc_state
4748 * @refresh_rate: RR to be programmed
4750 * This function gets called when refresh rate (RR) has to be changed from
4751 * one frequency to another. Switches can be between high and low RR
4752 * supported by the panel or to any other RR based on media playback (in
4753 * this case, RR value needs to be passed from user space).
4755 * The caller of this function needs to take a lock on dev_priv->drrs.
4757 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4758 const struct intel_crtc_state *crtc_state,
4761 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4763 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4765 if (refresh_rate <= 0) {
4766 drm_dbg_kms(&dev_priv->drm,
4767 "Refresh rate should be positive non-zero.\n");
4771 if (intel_dp == NULL) {
4772 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4777 drm_dbg_kms(&dev_priv->drm,
4778 "DRRS: intel_crtc not initialized\n");
4782 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4783 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4787 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4789 index = DRRS_LOW_RR;
4791 if (index == dev_priv->drrs.refresh_rate_type) {
4792 drm_dbg_kms(&dev_priv->drm,
4793 "DRRS requested for previously set RR...ignoring\n");
4797 if (!crtc_state->hw.active) {
4798 drm_dbg_kms(&dev_priv->drm,
4799 "eDP encoder disabled. CRTC not Active\n");
4803 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4806 intel_dp_set_m_n(crtc_state, M1_N1);
4809 intel_dp_set_m_n(crtc_state, M2_N2);
4813 drm_err(&dev_priv->drm,
4814 "Unsupported refreshrate type\n");
4816 } else if (INTEL_GEN(dev_priv) > 6) {
4817 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4820 val = intel_de_read(dev_priv, reg);
4821 if (index > DRRS_HIGH_RR) {
4822 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4823 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4825 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4827 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4828 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4830 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4832 intel_de_write(dev_priv, reg, val);
4835 dev_priv->drrs.refresh_rate_type = index;
4837 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4842 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4844 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4846 dev_priv->drrs.busy_frontbuffer_bits = 0;
4847 dev_priv->drrs.dp = intel_dp;
4851 * intel_edp_drrs_enable - init drrs struct if supported
4852 * @intel_dp: DP struct
4853 * @crtc_state: A pointer to the active crtc state.
4855 * Initializes frontbuffer_bits and drrs.dp
4857 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4858 const struct intel_crtc_state *crtc_state)
4860 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4862 if (!crtc_state->has_drrs)
4865 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4867 mutex_lock(&dev_priv->drrs.mutex);
4869 if (dev_priv->drrs.dp) {
4870 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4874 intel_edp_drrs_enable_locked(intel_dp);
4877 mutex_unlock(&dev_priv->drrs.mutex);
4881 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4882 const struct intel_crtc_state *crtc_state)
4884 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4886 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4889 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4890 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4893 dev_priv->drrs.dp = NULL;
4897 * intel_edp_drrs_disable - Disable DRRS
4898 * @intel_dp: DP struct
4899 * @old_crtc_state: Pointer to old crtc_state.
4902 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4903 const struct intel_crtc_state *old_crtc_state)
4905 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4907 if (!old_crtc_state->has_drrs)
4910 mutex_lock(&dev_priv->drrs.mutex);
4911 if (!dev_priv->drrs.dp) {
4912 mutex_unlock(&dev_priv->drrs.mutex);
4916 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4917 mutex_unlock(&dev_priv->drrs.mutex);
4919 cancel_delayed_work_sync(&dev_priv->drrs.work);
4923 * intel_edp_drrs_update - Update DRRS state
4924 * @intel_dp: Intel DP
4925 * @crtc_state: new CRTC state
4927 * This function will update DRRS states, disabling or enabling DRRS when
4928 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4929 * intel_edp_drrs_enable() should be called instead.
4932 intel_edp_drrs_update(struct intel_dp *intel_dp,
4933 const struct intel_crtc_state *crtc_state)
4935 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4937 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4940 mutex_lock(&dev_priv->drrs.mutex);
4942 /* New state matches current one? */
4943 if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4946 if (crtc_state->has_drrs)
4947 intel_edp_drrs_enable_locked(intel_dp);
4949 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4952 mutex_unlock(&dev_priv->drrs.mutex);
4955 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4957 struct drm_i915_private *dev_priv =
4958 container_of(work, typeof(*dev_priv), drrs.work.work);
4959 struct intel_dp *intel_dp;
4961 mutex_lock(&dev_priv->drrs.mutex);
4963 intel_dp = dev_priv->drrs.dp;
4969 * The delayed work can race with an invalidate hence we need to
4973 if (dev_priv->drrs.busy_frontbuffer_bits)
4976 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4977 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4979 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4980 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4984 mutex_unlock(&dev_priv->drrs.mutex);
4988 * intel_edp_drrs_invalidate - Disable Idleness DRRS
4989 * @dev_priv: i915 device
4990 * @frontbuffer_bits: frontbuffer plane tracking bits
4992 * This function gets called everytime rendering on the given planes start.
4993 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4995 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4997 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4998 unsigned int frontbuffer_bits)
5000 struct intel_dp *intel_dp;
5001 struct drm_crtc *crtc;
5004 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5007 cancel_delayed_work(&dev_priv->drrs.work);
5009 mutex_lock(&dev_priv->drrs.mutex);
5011 intel_dp = dev_priv->drrs.dp;
5013 mutex_unlock(&dev_priv->drrs.mutex);
5017 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5018 pipe = to_intel_crtc(crtc)->pipe;
5020 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5021 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5023 /* invalidate means busy screen hence upclock */
5024 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5025 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5026 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5028 mutex_unlock(&dev_priv->drrs.mutex);
5032 * intel_edp_drrs_flush - Restart Idleness DRRS
5033 * @dev_priv: i915 device
5034 * @frontbuffer_bits: frontbuffer plane tracking bits
5036 * This function gets called every time rendering on the given planes has
5037 * completed or flip on a crtc is completed. So DRRS should be upclocked
5038 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5039 * if no other planes are dirty.
5041 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5043 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5044 unsigned int frontbuffer_bits)
5046 struct intel_dp *intel_dp;
5047 struct drm_crtc *crtc;
5050 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5053 cancel_delayed_work(&dev_priv->drrs.work);
5055 mutex_lock(&dev_priv->drrs.mutex);
5057 intel_dp = dev_priv->drrs.dp;
5059 mutex_unlock(&dev_priv->drrs.mutex);
5063 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5064 pipe = to_intel_crtc(crtc)->pipe;
5066 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5067 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5069 /* flush means busy screen hence upclock */
5070 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5071 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5072 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5075 * flush also means no more activity hence schedule downclock, if all
5076 * other fbs are quiescent too
5078 if (!dev_priv->drrs.busy_frontbuffer_bits)
5079 schedule_delayed_work(&dev_priv->drrs.work,
5080 msecs_to_jiffies(1000));
5081 mutex_unlock(&dev_priv->drrs.mutex);
5085 * DOC: Display Refresh Rate Switching (DRRS)
5087 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5088 * which enables swtching between low and high refresh rates,
5089 * dynamically, based on the usage scenario. This feature is applicable
5090 * for internal panels.
5092 * Indication that the panel supports DRRS is given by the panel EDID, which
5093 * would list multiple refresh rates for one resolution.
5095 * DRRS is of 2 types - static and seamless.
5096 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5097 * (may appear as a blink on screen) and is used in dock-undock scenario.
5098 * Seamless DRRS involves changing RR without any visual effect to the user
5099 * and can be used during normal system usage. This is done by programming
5100 * certain registers.
5102 * Support for static/seamless DRRS may be indicated in the VBT based on
5103 * inputs from the panel spec.
5105 * DRRS saves power by switching to low RR based on usage scenarios.
5107 * The implementation is based on frontbuffer tracking implementation. When
5108 * there is a disturbance on the screen triggered by user activity or a periodic
5109 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5110 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5113 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5114 * and intel_edp_drrs_flush() are called.
5116 * DRRS can be further extended to support other internal panels and also
5117 * the scenario of video playback wherein RR is set based on the rate
5118 * requested by userspace.
5122 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5123 * @connector: eDP connector
5124 * @fixed_mode: preferred mode of panel
5126 * This function is called only once at driver load to initialize basic
5130 * Downclock mode if panel supports it, else return NULL.
5131 * DRRS support is determined by the presence of downclock mode (apart
5132 * from VBT setting).
5134 static struct drm_display_mode *
5135 intel_dp_drrs_init(struct intel_connector *connector,
5136 struct drm_display_mode *fixed_mode)
5138 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5139 struct drm_display_mode *downclock_mode = NULL;
5141 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5142 mutex_init(&dev_priv->drrs.mutex);
5144 if (INTEL_GEN(dev_priv) <= 6) {
5145 drm_dbg_kms(&dev_priv->drm,
5146 "DRRS supported for Gen7 and above\n");
5150 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5151 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5155 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5156 if (!downclock_mode) {
5157 drm_dbg_kms(&dev_priv->drm,
5158 "Downclock mode is not found. DRRS not supported\n");
5162 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5164 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5165 drm_dbg_kms(&dev_priv->drm,
5166 "seamless DRRS supported for eDP panel.\n");
5167 return downclock_mode;
5170 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5171 struct intel_connector *intel_connector)
5173 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5174 struct drm_device *dev = &dev_priv->drm;
5175 struct drm_connector *connector = &intel_connector->base;
5176 struct drm_display_mode *fixed_mode = NULL;
5177 struct drm_display_mode *downclock_mode = NULL;
5179 enum pipe pipe = INVALID_PIPE;
5182 if (!intel_dp_is_edp(intel_dp))
5186 * On IBX/CPT we may get here with LVDS already registered. Since the
5187 * driver uses the only internal power sequencer available for both
5188 * eDP and LVDS bail out early in this case to prevent interfering
5189 * with an already powered-on LVDS power sequencer.
5191 if (intel_get_lvds_encoder(dev_priv)) {
5193 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5194 drm_info(&dev_priv->drm,
5195 "LVDS was detected, not registering eDP\n");
5200 intel_pps_init(intel_dp);
5202 /* Cache DPCD and EDID for edp. */
5203 has_dpcd = intel_edp_init_dpcd(intel_dp);
5206 /* if this fails, presume the device is a ghost */
5207 drm_info(&dev_priv->drm,
5208 "failed to retrieve link info, disabling eDP\n");
5212 mutex_lock(&dev->mode_config.mutex);
5213 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5215 if (drm_add_edid_modes(connector, edid)) {
5216 drm_connector_update_edid_property(connector, edid);
5219 edid = ERR_PTR(-EINVAL);
5222 edid = ERR_PTR(-ENOENT);
5224 intel_connector->edid = edid;
5226 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5228 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5230 /* multiply the mode clock and horizontal timings for MSO */
5231 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5232 intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5234 /* fallback to VBT if available for eDP */
5236 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5237 mutex_unlock(&dev->mode_config.mutex);
5239 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5241 * Figure out the current pipe for the initial backlight setup.
5242 * If the current pipe isn't valid, try the PPS pipe, and if that
5243 * fails just assume pipe A.
5245 pipe = vlv_active_pipe(intel_dp);
5247 if (pipe != PIPE_A && pipe != PIPE_B)
5248 pipe = intel_dp->pps.pps_pipe;
5250 if (pipe != PIPE_A && pipe != PIPE_B)
5253 drm_dbg_kms(&dev_priv->drm,
5254 "using pipe %c for initial backlight setup\n",
5258 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5259 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5260 intel_panel_setup_backlight(connector, pipe);
5263 drm_connector_set_panel_orientation_with_quirk(connector,
5264 dev_priv->vbt.orientation,
5265 fixed_mode->hdisplay, fixed_mode->vdisplay);
5271 intel_pps_vdd_off_sync(intel_dp);
5276 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5278 struct intel_connector *intel_connector;
5279 struct drm_connector *connector;
5281 intel_connector = container_of(work, typeof(*intel_connector),
5282 modeset_retry_work);
5283 connector = &intel_connector->base;
5284 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5287 /* Grab the locks before changing connector property*/
5288 mutex_lock(&connector->dev->mode_config.mutex);
5289 /* Set connector link status to BAD and send a Uevent to notify
5290 * userspace to do a modeset.
5292 drm_connector_set_link_status_property(connector,
5293 DRM_MODE_LINK_STATUS_BAD);
5294 mutex_unlock(&connector->dev->mode_config.mutex);
5295 /* Send Hotplug uevent so userspace can reprobe */
5296 drm_kms_helper_hotplug_event(connector->dev);
5300 intel_dp_init_connector(struct intel_digital_port *dig_port,
5301 struct intel_connector *intel_connector)
5303 struct drm_connector *connector = &intel_connector->base;
5304 struct intel_dp *intel_dp = &dig_port->dp;
5305 struct intel_encoder *intel_encoder = &dig_port->base;
5306 struct drm_device *dev = intel_encoder->base.dev;
5307 struct drm_i915_private *dev_priv = to_i915(dev);
5308 enum port port = intel_encoder->port;
5309 enum phy phy = intel_port_to_phy(dev_priv, port);
5312 /* Initialize the work for modeset in case of link train failure */
5313 INIT_WORK(&intel_connector->modeset_retry_work,
5314 intel_dp_modeset_retry_work_fn);
5316 if (drm_WARN(dev, dig_port->max_lanes < 1,
5317 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5318 dig_port->max_lanes, intel_encoder->base.base.id,
5319 intel_encoder->base.name))
5322 intel_dp_set_source_rates(intel_dp);
5324 intel_dp->reset_link_params = true;
5325 intel_dp->pps.pps_pipe = INVALID_PIPE;
5326 intel_dp->pps.active_pipe = INVALID_PIPE;
5328 /* Preserve the current hw state. */
5329 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5330 intel_dp->attached_connector = intel_connector;
5332 if (intel_dp_is_port_edp(dev_priv, port)) {
5334 * Currently we don't support eDP on TypeC ports, although in
5335 * theory it could work on TypeC legacy ports.
5337 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5338 type = DRM_MODE_CONNECTOR_eDP;
5340 type = DRM_MODE_CONNECTOR_DisplayPort;
5343 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5344 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5347 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5348 * for DP the encoder type can be set by the caller to
5349 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5351 if (type == DRM_MODE_CONNECTOR_eDP)
5352 intel_encoder->type = INTEL_OUTPUT_EDP;
5354 /* eDP only on port B and/or C on vlv/chv */
5355 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5356 IS_CHERRYVIEW(dev_priv)) &&
5357 intel_dp_is_edp(intel_dp) &&
5358 port != PORT_B && port != PORT_C))
5361 drm_dbg_kms(&dev_priv->drm,
5362 "Adding %s connector on [ENCODER:%d:%s]\n",
5363 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5364 intel_encoder->base.base.id, intel_encoder->base.name);
5366 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5367 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5369 if (!HAS_GMCH(dev_priv))
5370 connector->interlace_allowed = true;
5371 connector->doublescan_allowed = 0;
5373 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5375 intel_dp_aux_init(intel_dp);
5377 intel_connector_attach_encoder(intel_connector, intel_encoder);
5379 if (HAS_DDI(dev_priv))
5380 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5382 intel_connector->get_hw_state = intel_connector_get_hw_state;
5384 /* init MST on ports that can support it */
5385 intel_dp_mst_encoder_init(dig_port,
5386 intel_connector->base.base.id);
5388 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5389 intel_dp_aux_fini(intel_dp);
5390 intel_dp_mst_encoder_cleanup(dig_port);
5394 intel_dp_add_properties(intel_dp, connector);
5396 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5397 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
5399 drm_dbg_kms(&dev_priv->drm,
5400 "HDCP init failed, skipping.\n");
5403 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5404 * 0xd. Failure to do so will result in spurious interrupts being
5405 * generated on the port when a cable is not attached.
5407 if (IS_G45(dev_priv)) {
5408 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5409 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5410 (temp & ~0xf) | 0xd);
5413 intel_dp->frl.is_trained = false;
5414 intel_dp->frl.trained_rate_gbps = 0;
5416 intel_psr_init(intel_dp);
5421 drm_connector_cleanup(connector);
5426 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5428 struct intel_encoder *encoder;
5430 for_each_intel_encoder(&dev_priv->drm, encoder) {
5431 struct intel_dp *intel_dp;
5433 if (encoder->type != INTEL_OUTPUT_DDI)
5436 intel_dp = enc_to_intel_dp(encoder);
5438 if (!intel_dp->can_mst)
5441 if (intel_dp->is_mst)
5442 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5446 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5448 struct intel_encoder *encoder;
5450 for_each_intel_encoder(&dev_priv->drm, encoder) {
5451 struct intel_dp *intel_dp;
5454 if (encoder->type != INTEL_OUTPUT_DDI)
5457 intel_dp = enc_to_intel_dp(encoder);
5459 if (!intel_dp->can_mst)
5462 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5465 intel_dp->is_mst = false;
5466 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,