drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_probe_helper.h>
  44
  45 #include "g4x_dp.h"
  46 #include "i915_debugfs.h"
  47 #include "i915_drv.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_backlight.h"
  51 #include "intel_combo_phy_regs.h"
  52 #include "intel_connector.h"
  53 #include "intel_crtc.h"
  54 #include "intel_ddi.h"
  55 #include "intel_de.h"
  56 #include "intel_display_types.h"
  57 #include "intel_dp.h"
  58 #include "intel_dp_aux.h"
  59 #include "intel_dp_hdcp.h"
  60 #include "intel_dp_link_training.h"
  61 #include "intel_dp_mst.h"
  62 #include "intel_dpio_phy.h"
  63 #include "intel_dpll.h"
  64 #include "intel_fifo_underrun.h"
  65 #include "intel_hdcp.h"
  66 #include "intel_hdmi.h"
  67 #include "intel_hotplug.h"
  68 #include "intel_lspcon.h"
  69 #include "intel_lvds.h"
  70 #include "intel_panel.h"
  71 #include "intel_pch_display.h"
  72 #include "intel_pps.h"
  73 #include "intel_psr.h"
  74 #include "intel_tc.h"
  75 #include "intel_vdsc.h"
  76 #include "intel_vrr.h"
  77
  78 /* DP DSC throughput values used for slice count calculations KPixels/s */
  79 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  80 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  81 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  82
  83 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  84 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  85
  86 /* Compliance test status bits  */
  87 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  88 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  89 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  90 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  91
  92
  93 /* Constants for DP DSC configurations */
  94 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  95
  96 /* With Single pipe configuration, HW is capable of supporting maximum
  97  * of 4 slices per line.
  98  */
  99 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 100
 101 /**
 102  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 103  * @intel_dp: DP struct
 104  *
 105  * If a CPU or PCH DP output is attached to an eDP panel, this function
 106  * will return true, and false otherwise.
 107  *
 108  * This function is not safe to use prior to encoder type being set.
 109  */
 110 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 113
 114         return dig_port->base.type == INTEL_OUTPUT_EDP;
 115 }
 116
 117 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 118 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 119
 120 /* Is link rate UHBR and thus 128b/132b? */
 121 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 122 {
 123         return crtc_state->port_clock >= 1000000;
 124 }
 125
 126 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 127 {
 128         intel_dp->sink_rates[0] = 162000;
 129         intel_dp->num_sink_rates = 1;
 130 }
 131
 132 /* update sink rates from dpcd */
 133 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 134 {
 135         static const int dp_rates[] = {
 136                 162000, 270000, 540000, 810000
 137         };
 138         int i, max_rate;
 139         int max_lttpr_rate;
 140
 141         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 142                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 143                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 144
 145                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 146                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 147
 148                 return;
 149         }
 150
 151         /*
 152          * Sink rates for 8b/10b.
 153          */
 154         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 155         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 156         if (max_lttpr_rate)
 157                 max_rate = min(max_rate, max_lttpr_rate);
 158
 159         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 160                 if (dp_rates[i] > max_rate)
 161                         break;
 162                 intel_dp->sink_rates[i] = dp_rates[i];
 163         }
 164
 165         /*
 166          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 167          * rates and 10 Gbps.
 168          */
 169         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 170                 u8 uhbr_rates = 0;
 171
 172                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 173
 174                 drm_dp_dpcd_readb(&intel_dp->aux,
 175                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 176
 177                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 178                         /* We have a repeater */
 179                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 180                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 181                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 182                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 183                                 /* Repeater supports 128b/132b, valid UHBR rates */
 184                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 185                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 186                         } else {
 187                                 /* Does not support 128b/132b */
 188                                 uhbr_rates = 0;
 189                         }
 190                 }
 191
 192                 if (uhbr_rates & DP_UHBR10)
 193                         intel_dp->sink_rates[i++] = 1000000;
 194                 if (uhbr_rates & DP_UHBR13_5)
 195                         intel_dp->sink_rates[i++] = 1350000;
 196                 if (uhbr_rates & DP_UHBR20)
 197                         intel_dp->sink_rates[i++] = 2000000;
 198         }
 199
 200         intel_dp->num_sink_rates = i;
 201 }
 202
 203 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 204 {
 205         struct intel_connector *connector = intel_dp->attached_connector;
 206         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 207         struct intel_encoder *encoder = &intel_dig_port->base;
 208
 209         intel_dp_set_dpcd_sink_rates(intel_dp);
 210
 211         if (intel_dp->num_sink_rates)
 212                 return;
 213
 214         drm_err(&dp_to_i915(intel_dp)->drm,
 215                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 216                 connector->base.base.id, connector->base.name,
 217                 encoder->base.base.id, encoder->base.name);
 218
 219         intel_dp_set_default_sink_rates(intel_dp);
 220 }
 221
 222 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 223 {
 224         intel_dp->max_sink_lane_count = 1;
 225 }
 226
 227 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 228 {
 229         struct intel_connector *connector = intel_dp->attached_connector;
 230         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 231         struct intel_encoder *encoder = &intel_dig_port->base;
 232
 233         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 234
 235         switch (intel_dp->max_sink_lane_count) {
 236         case 1:
 237         case 2:
 238         case 4:
 239                 return;
 240         }
 241
 242         drm_err(&dp_to_i915(intel_dp)->drm,
 243                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 244                 connector->base.base.id, connector->base.name,
 245                 encoder->base.base.id, encoder->base.name,
 246                 intel_dp->max_sink_lane_count);
 247
 248         intel_dp_set_default_max_sink_lane_count(intel_dp);
 249 }
 250
 251 /* Get length of rates array potentially limited by max_rate. */
 252 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 253 {
 254         int i;
 255
 256         /* Limit results by potentially reduced max rate */
 257         for (i = 0; i < len; i++) {
 258                 if (rates[len - i - 1] <= max_rate)
 259                         return len - i;
 260         }
 261
 262         return 0;
 263 }
 264
 265 /* Get length of common rates array potentially limited by max_rate. */
 266 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 267                                           int max_rate)
 268 {
 269         return intel_dp_rate_limit_len(intel_dp->common_rates,
 270                                        intel_dp->num_common_rates, max_rate);
 271 }
 272
 273 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 274 {
 275         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 276                         index < 0 || index >= intel_dp->num_common_rates))
 277                 return 162000;
 278
 279         return intel_dp->common_rates[index];
 280 }
 281
 282 /* Theoretical max between source and sink */
 283 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 284 {
 285         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 286 }
 287
 288 /* Theoretical max between source and sink */
 289 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 290 {
 291         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 292         int source_max = dig_port->max_lanes;
 293         int sink_max = intel_dp->max_sink_lane_count;
 294         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 295         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 296
 297         if (lttpr_max)
 298                 sink_max = min(sink_max, lttpr_max);
 299
 300         return min3(source_max, sink_max, fia_max);
 301 }
 302
 303 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 304 {
 305         switch (intel_dp->max_link_lane_count) {
 306         case 1:
 307         case 2:
 308         case 4:
 309                 return intel_dp->max_link_lane_count;
 310         default:
 311                 MISSING_CASE(intel_dp->max_link_lane_count);
 312                 return 1;
 313         }
 314 }
 315
 316 /*
 317  * The required data bandwidth for a mode with given pixel clock and bpp. This
 318  * is the required net bandwidth independent of the data bandwidth efficiency.
 319  */
 320 int
 321 intel_dp_link_required(int pixel_clock, int bpp)
 322 {
 323         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 324         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 325 }
 326
 327 /*
 328  * Given a link rate and lanes, get the data bandwidth.
 329  *
 330  * Data bandwidth is the actual payload rate, which depends on the data
 331  * bandwidth efficiency and the link rate.
 332  *
 333  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 334  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 335  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 336  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 337  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 338  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 339  *
 340  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 341  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 342  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 343  * does not match the symbol clock, the port clock (not even if you think in
 344  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 345  * rate in units of 10000 bps.
 346  */
 347 int
 348 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 349 {
 350         if (max_link_rate >= 1000000) {
 351                 /*
 352                  * UHBR rates always use 128b/132b channel encoding, and have
 353                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 354                  * link bit rate in units of 10000 bps.
 355                  */
 356                 int max_link_rate_kbps = max_link_rate * 10;
 357
 358                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 359                 max_link_rate = max_link_rate_kbps / 8;
 360         }
 361
 362         /*
 363          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 364          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 365          * out to be a nop by coincidence, and can be skipped:
 366          *
 367          *      int max_link_rate_kbps = max_link_rate * 10;
 368          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 369          *      max_link_rate = max_link_rate_kbps / 8;
 370          */
 371
 372         return max_link_rate * max_lanes;
 373 }
 374
 375 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 376 {
 377         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 378         struct intel_encoder *encoder = &intel_dig_port->base;
 379         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 380
 381         return DISPLAY_VER(dev_priv) >= 12 ||
 382                 (DISPLAY_VER(dev_priv) == 11 &&
 383                  encoder->port != PORT_A);
 384 }
 385
 386 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 387 {
 388         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 389 }
 390
 391 static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
 392 {
 393         u32 voltage;
 394
 395         voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
 396
 397         return voltage == VOLTAGE_INFO_0_85V;
 398 }
 399
 400 static int icl_max_source_rate(struct intel_dp *intel_dp)
 401 {
 402         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 403         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 404         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 405
 406         if (intel_phy_is_combo(dev_priv, phy) &&
 407             (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 408                 return 540000;
 409
 410         return 810000;
 411 }
 412
 413 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 414 {
 415         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 416         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 417         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 418
 419         if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
 420                 return 540000;
 421
 422         return 810000;
 423 }
 424
 425 static int dg1_max_source_rate(struct intel_dp *intel_dp)
 426 {
 427         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 428         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 429         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 430
 431         if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 432                 return 540000;
 433
 434         return 810000;
 435 }
 436
 437 static void
 438 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 439 {
 440         /* The values must be in increasing order */
 441         static const int icl_rates[] = {
 442                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 443                 1000000, 1350000,
 444         };
 445         static const int bxt_rates[] = {
 446                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 447         };
 448         static const int skl_rates[] = {
 449                 162000, 216000, 270000, 324000, 432000, 540000
 450         };
 451         static const int hsw_rates[] = {
 452                 162000, 270000, 540000
 453         };
 454         static const int g4x_rates[] = {
 455                 162000, 270000
 456         };
 457         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 458         struct intel_encoder *encoder = &dig_port->base;
 459         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 460         const int *source_rates;
 461         int size, max_rate = 0, vbt_max_rate;
 462
 463         /* This should only be done once */
 464         drm_WARN_ON(&dev_priv->drm,
 465                     intel_dp->source_rates || intel_dp->num_source_rates);
 466
 467         if (DISPLAY_VER(dev_priv) >= 11) {
 468                 source_rates = icl_rates;
 469                 size = ARRAY_SIZE(icl_rates);
 470                 if (IS_DG2(dev_priv))
 471                         max_rate = dg2_max_source_rate(intel_dp);
 472                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 473                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 474                         max_rate = dg1_max_source_rate(intel_dp);
 475                 else if (IS_JSL_EHL(dev_priv))
 476                         max_rate = ehl_max_source_rate(intel_dp);
 477                 else
 478                         max_rate = icl_max_source_rate(intel_dp);
 479         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 480                 source_rates = bxt_rates;
 481                 size = ARRAY_SIZE(bxt_rates);
 482         } else if (DISPLAY_VER(dev_priv) == 9) {
 483                 source_rates = skl_rates;
 484                 size = ARRAY_SIZE(skl_rates);
 485         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 486                    IS_BROADWELL(dev_priv)) {
 487                 source_rates = hsw_rates;
 488                 size = ARRAY_SIZE(hsw_rates);
 489         } else {
 490                 source_rates = g4x_rates;
 491                 size = ARRAY_SIZE(g4x_rates);
 492         }
 493
 494         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 495         if (max_rate && vbt_max_rate)
 496                 max_rate = min(max_rate, vbt_max_rate);
 497         else if (vbt_max_rate)
 498                 max_rate = vbt_max_rate;
 499
 500         if (max_rate)
 501                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 502
 503         intel_dp->source_rates = source_rates;
 504         intel_dp->num_source_rates = size;
 505 }
 506
 507 static int intersect_rates(const int *source_rates, int source_len,
 508                            const int *sink_rates, int sink_len,
 509                            int *common_rates)
 510 {
 511         int i = 0, j = 0, k = 0;
 512
 513         while (i < source_len && j < sink_len) {
 514                 if (source_rates[i] == sink_rates[j]) {
 515                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 516                                 return k;
 517                         common_rates[k] = source_rates[i];
 518                         ++k;
 519                         ++i;
 520                         ++j;
 521                 } else if (source_rates[i] < sink_rates[j]) {
 522                         ++i;
 523                 } else {
 524                         ++j;
 525                 }
 526         }
 527         return k;
 528 }
 529
 530 /* return index of rate in rates array, or -1 if not found */
 531 static int intel_dp_rate_index(const int *rates, int len, int rate)
 532 {
 533         int i;
 534
 535         for (i = 0; i < len; i++)
 536                 if (rate == rates[i])
 537                         return i;
 538
 539         return -1;
 540 }
 541
 542 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 543 {
 544         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 545
 546         drm_WARN_ON(&i915->drm,
 547                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 548
 549         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 550                                                      intel_dp->num_source_rates,
 551                                                      intel_dp->sink_rates,
 552                                                      intel_dp->num_sink_rates,
 553                                                      intel_dp->common_rates);
 554
 555         /* Paranoia, there should always be something in common. */
 556         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 557                 intel_dp->common_rates[0] = 162000;
 558                 intel_dp->num_common_rates = 1;
 559         }
 560 }
 561
 562 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 563                                        u8 lane_count)
 564 {
 565         /*
 566          * FIXME: we need to synchronize the current link parameters with
 567          * hardware readout. Currently fast link training doesn't work on
 568          * boot-up.
 569          */
 570         if (link_rate == 0 ||
 571             link_rate > intel_dp->max_link_rate)
 572                 return false;
 573
 574         if (lane_count == 0 ||
 575             lane_count > intel_dp_max_lane_count(intel_dp))
 576                 return false;
 577
 578         return true;
 579 }
 580
 581 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 582                                                      int link_rate,
 583                                                      u8 lane_count)
 584 {
 585         /* FIXME figure out what we actually want here */
 586         const struct drm_display_mode *fixed_mode =
 587                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 588         int mode_rate, max_rate;
 589
 590         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 591         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 592         if (mode_rate > max_rate)
 593                 return false;
 594
 595         return true;
 596 }
 597
 598 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 599                                             int link_rate, u8 lane_count)
 600 {
 601         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 602         int index;
 603
 604         /*
 605          * TODO: Enable fallback on MST links once MST link compute can handle
 606          * the fallback params.
 607          */
 608         if (intel_dp->is_mst) {
 609                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 610                 return -1;
 611         }
 612
 613         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 614                 drm_dbg_kms(&i915->drm,
 615                             "Retrying Link training for eDP with max parameters\n");
 616                 intel_dp->use_max_params = true;
 617                 return 0;
 618         }
 619
 620         index = intel_dp_rate_index(intel_dp->common_rates,
 621                                     intel_dp->num_common_rates,
 622                                     link_rate);
 623         if (index > 0) {
 624                 if (intel_dp_is_edp(intel_dp) &&
 625                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 626                                                               intel_dp_common_rate(intel_dp, index - 1),
 627                                                               lane_count)) {
 628                         drm_dbg_kms(&i915->drm,
 629                                     "Retrying Link training for eDP with same parameters\n");
 630                         return 0;
 631                 }
 632                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 633                 intel_dp->max_link_lane_count = lane_count;
 634         } else if (lane_count > 1) {
 635                 if (intel_dp_is_edp(intel_dp) &&
 636                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 637                                                               intel_dp_max_common_rate(intel_dp),
 638                                                               lane_count >> 1)) {
 639                         drm_dbg_kms(&i915->drm,
 640                                     "Retrying Link training for eDP with same parameters\n");
 641                         return 0;
 642                 }
 643                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 644                 intel_dp->max_link_lane_count = lane_count >> 1;
 645         } else {
 646                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 647                 return -1;
 648         }
 649
 650         return 0;
 651 }
 652
 653 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 654 {
 655         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 656                        DP_DSC_FEC_OVERHEAD_FACTOR);
 657 }
 658
 659 static int
 660 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 661 {
 662         if (DISPLAY_VER(i915) >= 13)
 663                 return 17280 * 8;
 664         else if (DISPLAY_VER(i915) >= 11)
 665                 return 7680 * 8;
 666         else
 667                 return 6144 * 8;
 668 }
 669
 670 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 671                                        u32 link_clock, u32 lane_count,
 672                                        u32 mode_clock, u32 mode_hdisplay,
 673                                        bool bigjoiner,
 674                                        u32 pipe_bpp)
 675 {
 676         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 677         int i;
 678
 679         /*
 680          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 681          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 682          * for SST -> TimeSlotsPerMTP is 1,
 683          * for MST -> TimeSlotsPerMTP has to be calculated
 684          */
 685         bits_per_pixel = (link_clock * lane_count * 8) /
 686                          intel_dp_mode_to_fec_clock(mode_clock);
 687         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 688
 689         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 690         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 691                 mode_hdisplay;
 692
 693         if (bigjoiner)
 694                 max_bpp_small_joiner_ram *= 2;
 695
 696         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 697                     max_bpp_small_joiner_ram);
 698
 699         /*
 700          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 701          * check, output bpp from small joiner RAM check)
 702          */
 703         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 704
 705         if (bigjoiner) {
 706                 u32 max_bpp_bigjoiner =
 707                         i915->max_cdclk_freq * 48 /
 708                         intel_dp_mode_to_fec_clock(mode_clock);
 709
 710                 drm_dbg_kms(&i915->drm, "Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 711                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 712         }
 713
 714         /* Error out if the max bpp is less than smallest allowed valid bpp */
 715         if (bits_per_pixel < valid_dsc_bpp[0]) {
 716                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 717                             bits_per_pixel, valid_dsc_bpp[0]);
 718                 return 0;
 719         }
 720
 721         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 722         if (DISPLAY_VER(i915) >= 13) {
 723                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 724         } else {
 725                 /* Find the nearest match in the array of known BPPs from VESA */
 726                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 727                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 728                                 break;
 729                 }
 730                 bits_per_pixel = valid_dsc_bpp[i];
 731         }
 732
 733         /*
 734          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 735          * fractional part is 0
 736          */
 737         return bits_per_pixel << 4;
 738 }
 739
 740 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 741                                        int mode_clock, int mode_hdisplay,
 742                                        bool bigjoiner)
 743 {
 744         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 745         u8 min_slice_count, i;
 746         int max_slice_width;
 747
 748         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 749                 min_slice_count = DIV_ROUND_UP(mode_clock,
 750                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 751         else
 752                 min_slice_count = DIV_ROUND_UP(mode_clock,
 753                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 754
 755         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 756         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 757                 drm_dbg_kms(&i915->drm,
 758                             "Unsupported slice width %d by DP DSC Sink device\n",
 759                             max_slice_width);
 760                 return 0;
 761         }
 762         /* Also take into account max slice width */
 763         min_slice_count = max_t(u8, min_slice_count,
 764                                 DIV_ROUND_UP(mode_hdisplay,
 765                                              max_slice_width));
 766
 767         /* Find the closest match to the valid slice count values */
 768         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 769                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 770
 771                 if (test_slice_count >
 772                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 773                         break;
 774
 775                 /* big joiner needs small joiner to be enabled */
 776                 if (bigjoiner && test_slice_count < 4)
 777                         continue;
 778
 779                 if (min_slice_count <= test_slice_count)
 780                         return test_slice_count;
 781         }
 782
 783         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 784                     min_slice_count);
 785         return 0;
 786 }
 787
 788 static enum intel_output_format
 789 intel_dp_output_format(struct intel_connector *connector,
 790                        bool ycbcr_420_output)
 791 {
 792         struct intel_dp *intel_dp = intel_attached_dp(connector);
 793
 794         if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 795                 return INTEL_OUTPUT_FORMAT_RGB;
 796
 797         if (intel_dp->dfp.rgb_to_ycbcr &&
 798             intel_dp->dfp.ycbcr_444_to_420)
 799                 return INTEL_OUTPUT_FORMAT_RGB;
 800
 801         if (intel_dp->dfp.ycbcr_444_to_420)
 802                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 803         else
 804                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 805 }
 806
 807 int intel_dp_min_bpp(enum intel_output_format output_format)
 808 {
 809         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 810                 return 6 * 3;
 811         else
 812                 return 8 * 3;
 813 }
 814
 815 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 816 {
 817         /*
 818          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 819          * format of the number of bytes per pixel will be half the number
 820          * of bytes of RGB pixel.
 821          */
 822         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 823                 bpp /= 2;
 824
 825         return bpp;
 826 }
 827
 828 static int
 829 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 830                              const struct drm_display_mode *mode)
 831 {
 832         const struct drm_display_info *info = &connector->base.display_info;
 833         enum intel_output_format output_format =
 834                 intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 835
 836         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 837 }
 838
 839 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 840                                   int hdisplay)
 841 {
 842         /*
 843          * Older platforms don't like hdisplay==4096 with DP.
 844          *
 845          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 846          * and frame counter increment), but we don't get vblank interrupts,
 847          * and the pipe underruns immediately. The link also doesn't seem
 848          * to get trained properly.
 849          *
 850          * On CHV the vblank interrupts don't seem to disappear but
 851          * otherwise the symptoms are similar.
 852          *
 853          * TODO: confirm the behaviour on HSW+
 854          */
 855         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 856 }
 857
 858 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 859 {
 860         struct intel_connector *connector = intel_dp->attached_connector;
 861         const struct drm_display_info *info = &connector->base.display_info;
 862         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
 863
 864         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
 865         if (max_tmds_clock && info->max_tmds_clock)
 866                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
 867
 868         return max_tmds_clock;
 869 }
 870
 871 static enum drm_mode_status
 872 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 873                           int clock, int bpc, bool ycbcr420_output,
 874                           bool respect_downstream_limits)
 875 {
 876         int tmds_clock, min_tmds_clock, max_tmds_clock;
 877
 878         if (!respect_downstream_limits)
 879                 return MODE_OK;
 880
 881         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 882
 883         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
 884         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
 885
 886         if (min_tmds_clock && tmds_clock < min_tmds_clock)
 887                 return MODE_CLOCK_LOW;
 888
 889         if (max_tmds_clock && tmds_clock > max_tmds_clock)
 890                 return MODE_CLOCK_HIGH;
 891
 892         return MODE_OK;
 893 }
 894
 895 static enum drm_mode_status
 896 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 897                                const struct drm_display_mode *mode,
 898                                int target_clock)
 899 {
 900         struct intel_dp *intel_dp = intel_attached_dp(connector);
 901         const struct drm_display_info *info = &connector->base.display_info;
 902         enum drm_mode_status status;
 903         bool ycbcr_420_only;
 904
 905         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 906         if (intel_dp->dfp.pcon_max_frl_bw) {
 907                 int target_bw;
 908                 int max_frl_bw;
 909                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 910
 911                 target_bw = bpp * target_clock;
 912
 913                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 914
 915                 /* converting bw from Gbps to Kbps*/
 916                 max_frl_bw = max_frl_bw * 1000000;
 917
 918                 if (target_bw > max_frl_bw)
 919                         return MODE_CLOCK_HIGH;
 920
 921                 return MODE_OK;
 922         }
 923
 924         if (intel_dp->dfp.max_dotclock &&
 925             target_clock > intel_dp->dfp.max_dotclock)
 926                 return MODE_CLOCK_HIGH;
 927
 928         ycbcr_420_only = drm_mode_is_420_only(info, mode);
 929
 930         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 931         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 932                                            8, ycbcr_420_only, true);
 933
 934         if (status != MODE_OK) {
 935                 if (ycbcr_420_only ||
 936                     !connector->base.ycbcr_420_allowed ||
 937                     !drm_mode_is_420_also(info, mode))
 938                         return status;
 939
 940                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 941                                                    8, true, true);
 942                 if (status != MODE_OK)
 943                         return status;
 944         }
 945
 946         return MODE_OK;
 947 }
 948
 949 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 950                                     int hdisplay, int clock)
 951 {
 952         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 953
 954         if (!intel_dp_can_bigjoiner(intel_dp))
 955                 return false;
 956
 957         return clock > i915->max_dotclk_freq || hdisplay > 5120;
 958 }
 959
 960 static enum drm_mode_status
 961 intel_dp_mode_valid(struct drm_connector *_connector,
 962                     struct drm_display_mode *mode)
 963 {
 964         struct intel_connector *connector = to_intel_connector(_connector);
 965         struct intel_dp *intel_dp = intel_attached_dp(connector);
 966         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 967         const struct drm_display_mode *fixed_mode;
 968         int target_clock = mode->clock;
 969         int max_rate, mode_rate, max_lanes, max_link_clock;
 970         int max_dotclk = dev_priv->max_dotclk_freq;
 971         u16 dsc_max_output_bpp = 0;
 972         u8 dsc_slice_count = 0;
 973         enum drm_mode_status status;
 974         bool dsc = false, bigjoiner = false;
 975
 976         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 977                 return MODE_NO_DBLESCAN;
 978
 979         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 980                 return MODE_H_ILLEGAL;
 981
 982         fixed_mode = intel_panel_fixed_mode(connector, mode);
 983         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 984                 status = intel_panel_mode_valid(connector, mode);
 985                 if (status != MODE_OK)
 986                         return status;
 987
 988                 target_clock = fixed_mode->clock;
 989         }
 990
 991         if (mode->clock < 10000)
 992                 return MODE_CLOCK_LOW;
 993
 994         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 995                 bigjoiner = true;
 996                 max_dotclk *= 2;
 997         }
 998         if (target_clock > max_dotclk)
 999                 return MODE_CLOCK_HIGH;
1000
1001         max_link_clock = intel_dp_max_link_rate(intel_dp);
1002         max_lanes = intel_dp_max_lane_count(intel_dp);
1003
1004         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1005         mode_rate = intel_dp_link_required(target_clock,
1006                                            intel_dp_mode_min_output_bpp(connector, mode));
1007
1008         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1009                 return MODE_H_ILLEGAL;
1010
1011         /*
1012          * Output bpp is stored in 6.4 format so right shift by 4 to get the
1013          * integer value since we support only integer values of bpp.
1014          */
1015         if (DISPLAY_VER(dev_priv) >= 10 &&
1016             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1017                 /*
1018                  * TBD pass the connector BPC,
1019                  * for now U8_MAX so that max BPC on that platform would be picked
1020                  */
1021                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1022
1023                 if (intel_dp_is_edp(intel_dp)) {
1024                         dsc_max_output_bpp =
1025                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1026                         dsc_slice_count =
1027                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1028                                                                 true);
1029                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1030                         dsc_max_output_bpp =
1031                                 intel_dp_dsc_get_output_bpp(dev_priv,
1032                                                             max_link_clock,
1033                                                             max_lanes,
1034                                                             target_clock,
1035                                                             mode->hdisplay,
1036                                                             bigjoiner,
1037                                                             pipe_bpp) >> 4;
1038                         dsc_slice_count =
1039                                 intel_dp_dsc_get_slice_count(intel_dp,
1040                                                              target_clock,
1041                                                              mode->hdisplay,
1042                                                              bigjoiner);
1043                 }
1044
1045                 dsc = dsc_max_output_bpp && dsc_slice_count;
1046         }
1047
1048         /*
1049          * Big joiner configuration needs DSC for TGL which is not true for
1050          * XE_LPD where uncompressed joiner is supported.
1051          */
1052         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1053                 return MODE_CLOCK_HIGH;
1054
1055         if (mode_rate > max_rate && !dsc)
1056                 return MODE_CLOCK_HIGH;
1057
1058         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1059         if (status != MODE_OK)
1060                 return status;
1061
1062         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1063 }
1064
1065 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1066 {
1067         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1068 }
1069
1070 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1071 {
1072         return DISPLAY_VER(i915) >= 10;
1073 }
1074
1075 static void snprintf_int_array(char *str, size_t len,
1076                                const int *array, int nelem)
1077 {
1078         int i;
1079
1080         str[0] = '\0';
1081
1082         for (i = 0; i < nelem; i++) {
1083                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1084                 if (r >= len)
1085                         return;
1086                 str += r;
1087                 len -= r;
1088         }
1089 }
1090
1091 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1092 {
1093         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1094         char str[128]; /* FIXME: too big for stack? */
1095
1096         if (!drm_debug_enabled(DRM_UT_KMS))
1097                 return;
1098
1099         snprintf_int_array(str, sizeof(str),
1100                            intel_dp->source_rates, intel_dp->num_source_rates);
1101         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1102
1103         snprintf_int_array(str, sizeof(str),
1104                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1105         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1106
1107         snprintf_int_array(str, sizeof(str),
1108                            intel_dp->common_rates, intel_dp->num_common_rates);
1109         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1110 }
1111
1112 int
1113 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1114 {
1115         int len;
1116
1117         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1118
1119         return intel_dp_common_rate(intel_dp, len - 1);
1120 }
1121
1122 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1123 {
1124         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1125         int i = intel_dp_rate_index(intel_dp->sink_rates,
1126                                     intel_dp->num_sink_rates, rate);
1127
1128         if (drm_WARN_ON(&i915->drm, i < 0))
1129                 i = 0;
1130
1131         return i;
1132 }
1133
1134 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1135                            u8 *link_bw, u8 *rate_select)
1136 {
1137         /* eDP 1.4 rate select method. */
1138         if (intel_dp->use_rate_select) {
1139                 *link_bw = 0;
1140                 *rate_select =
1141                         intel_dp_rate_select(intel_dp, port_clock);
1142         } else {
1143                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1144                 *rate_select = 0;
1145         }
1146 }
1147
1148 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1149                                          const struct intel_crtc_state *pipe_config)
1150 {
1151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152
1153         /* On TGL, FEC is supported on all Pipes */
1154         if (DISPLAY_VER(dev_priv) >= 12)
1155                 return true;
1156
1157         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1158                 return true;
1159
1160         return false;
1161 }
1162
1163 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1164                                   const struct intel_crtc_state *pipe_config)
1165 {
1166         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1167                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1168 }
1169
1170 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1171                                   const struct intel_crtc_state *crtc_state)
1172 {
1173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1174                 return false;
1175
1176         return intel_dsc_source_support(crtc_state) &&
1177                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1178 }
1179
1180 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1181                                  const struct intel_crtc_state *crtc_state)
1182 {
1183         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1184                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1185                  intel_dp->dfp.ycbcr_444_to_420);
1186 }
1187
1188 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1189                                      const struct intel_crtc_state *crtc_state,
1190                                      int bpc, bool respect_downstream_limits)
1191 {
1192         bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1193         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1194
1195         /*
1196          * Current bpc could already be below 8bpc due to
1197          * FDI bandwidth constraints or other limits.
1198          * HDMI minimum is 8bpc however.
1199          */
1200         bpc = max(bpc, 8);
1201
1202         /*
1203          * We will never exceed downstream TMDS clock limits while
1204          * attempting deep color. If the user insists on forcing an
1205          * out of spec mode they will have to be satisfied with 8bpc.
1206          */
1207         if (!respect_downstream_limits)
1208                 bpc = 8;
1209
1210         for (; bpc >= 8; bpc -= 2) {
1211                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1212                                             intel_dp->has_hdmi_sink, ycbcr420_output) &&
1213                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1214                                               respect_downstream_limits) == MODE_OK)
1215                         return bpc;
1216         }
1217
1218         return -EINVAL;
1219 }
1220
1221 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1222                             const struct intel_crtc_state *crtc_state,
1223                             bool respect_downstream_limits)
1224 {
1225         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1226         struct intel_connector *intel_connector = intel_dp->attached_connector;
1227         int bpp, bpc;
1228
1229         bpc = crtc_state->pipe_bpp / 3;
1230
1231         if (intel_dp->dfp.max_bpc)
1232                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1233
1234         if (intel_dp->dfp.min_tmds_clock) {
1235                 int max_hdmi_bpc;
1236
1237                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1238                                                          respect_downstream_limits);
1239                 if (max_hdmi_bpc < 0)
1240                         return 0;
1241
1242                 bpc = min(bpc, max_hdmi_bpc);
1243         }
1244
1245         bpp = bpc * 3;
1246         if (intel_dp_is_edp(intel_dp)) {
1247                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1248                 if (intel_connector->base.display_info.bpc == 0 &&
1249                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1250                         drm_dbg_kms(&dev_priv->drm,
1251                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1252                                     dev_priv->vbt.edp.bpp);
1253                         bpp = dev_priv->vbt.edp.bpp;
1254                 }
1255         }
1256
1257         return bpp;
1258 }
1259
1260 /* Adjust link config limits based on compliance test requests. */
1261 void
1262 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1263                                   struct intel_crtc_state *pipe_config,
1264                                   struct link_config_limits *limits)
1265 {
1266         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1267
1268         /* For DP Compliance we override the computed bpp for the pipe */
1269         if (intel_dp->compliance.test_data.bpc != 0) {
1270                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1271
1272                 limits->min_bpp = limits->max_bpp = bpp;
1273                 pipe_config->dither_force_disable = bpp == 6 * 3;
1274
1275                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1276         }
1277
1278         /* Use values requested by Compliance Test Request */
1279         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1280                 int index;
1281
1282                 /* Validate the compliance test data since max values
1283                  * might have changed due to link train fallback.
1284                  */
1285                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1286                                                intel_dp->compliance.test_lane_count)) {
1287                         index = intel_dp_rate_index(intel_dp->common_rates,
1288                                                     intel_dp->num_common_rates,
1289                                                     intel_dp->compliance.test_link_rate);
1290                         if (index >= 0)
1291                                 limits->min_rate = limits->max_rate =
1292                                         intel_dp->compliance.test_link_rate;
1293                         limits->min_lane_count = limits->max_lane_count =
1294                                 intel_dp->compliance.test_lane_count;
1295                 }
1296         }
1297 }
1298
1299 /* Optimize link config in order: max bpp, min clock, min lanes */
1300 static int
1301 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1302                                   struct intel_crtc_state *pipe_config,
1303                                   const struct link_config_limits *limits)
1304 {
1305         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1306         int bpp, i, lane_count;
1307         int mode_rate, link_rate, link_avail;
1308
1309         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1310                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1311
1312                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1313                                                    output_bpp);
1314
1315                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1316                         link_rate = intel_dp_common_rate(intel_dp, i);
1317                         if (link_rate < limits->min_rate ||
1318                             link_rate > limits->max_rate)
1319                                 continue;
1320
1321                         for (lane_count = limits->min_lane_count;
1322                              lane_count <= limits->max_lane_count;
1323                              lane_count <<= 1) {
1324                                 link_avail = intel_dp_max_data_rate(link_rate,
1325                                                                     lane_count);
1326
1327                                 if (mode_rate <= link_avail) {
1328                                         pipe_config->lane_count = lane_count;
1329                                         pipe_config->pipe_bpp = bpp;
1330                                         pipe_config->port_clock = link_rate;
1331
1332                                         return 0;
1333                                 }
1334                         }
1335                 }
1336         }
1337
1338         return -EINVAL;
1339 }
1340
1341 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1342 {
1343         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1344         int i, num_bpc;
1345         u8 dsc_bpc[3] = {0};
1346         u8 dsc_max_bpc;
1347
1348         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1349         if (DISPLAY_VER(i915) >= 12)
1350                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1351         else
1352                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1353
1354         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1355                                                        dsc_bpc);
1356         for (i = 0; i < num_bpc; i++) {
1357                 if (dsc_max_bpc >= dsc_bpc[i])
1358                         return dsc_bpc[i] * 3;
1359         }
1360
1361         return 0;
1362 }
1363
1364 #define DSC_SUPPORTED_VERSION_MIN               1
1365
1366 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1367                                        struct intel_crtc_state *crtc_state)
1368 {
1369         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1370         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1371         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1372         u8 line_buf_depth;
1373         int ret;
1374
1375         /*
1376          * RC_MODEL_SIZE is currently a constant across all configurations.
1377          *
1378          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1379          * DP_DSC_RC_BUF_SIZE for this.
1380          */
1381         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1382
1383         /*
1384          * Slice Height of 8 works for all currently available panels. So start
1385          * with that if pic_height is an integral multiple of 8. Eventually add
1386          * logic to try multiple slice heights.
1387          */
1388         if (vdsc_cfg->pic_height % 8 == 0)
1389                 vdsc_cfg->slice_height = 8;
1390         else if (vdsc_cfg->pic_height % 4 == 0)
1391                 vdsc_cfg->slice_height = 4;
1392         else
1393                 vdsc_cfg->slice_height = 2;
1394
1395         ret = intel_dsc_compute_params(crtc_state);
1396         if (ret)
1397                 return ret;
1398
1399         vdsc_cfg->dsc_version_major =
1400                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1401                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1402         vdsc_cfg->dsc_version_minor =
1403                 min(DSC_SUPPORTED_VERSION_MIN,
1404                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1405                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1406
1407         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1408                 DP_DSC_RGB;
1409
1410         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1411         if (!line_buf_depth) {
1412                 drm_dbg_kms(&i915->drm,
1413                             "DSC Sink Line Buffer Depth invalid\n");
1414                 return -EINVAL;
1415         }
1416
1417         if (vdsc_cfg->dsc_version_minor == 2)
1418                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1419                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1420         else
1421                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1422                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1423
1424         vdsc_cfg->block_pred_enable =
1425                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1426                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1427
1428         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1429 }
1430
1431 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1432                                        struct intel_crtc_state *pipe_config,
1433                                        struct drm_connector_state *conn_state,
1434                                        struct link_config_limits *limits)
1435 {
1436         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1437         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1438         const struct drm_display_mode *adjusted_mode =
1439                 &pipe_config->hw.adjusted_mode;
1440         int pipe_bpp;
1441         int ret;
1442
1443         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1444                 intel_dp_supports_fec(intel_dp, pipe_config);
1445
1446         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1447                 return -EINVAL;
1448
1449         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1450
1451         /* Min Input BPC for ICL+ is 8 */
1452         if (pipe_bpp < 8 * 3) {
1453                 drm_dbg_kms(&dev_priv->drm,
1454                             "No DSC support for less than 8bpc\n");
1455                 return -EINVAL;
1456         }
1457
1458         /*
1459          * For now enable DSC for max bpp, max link rate, max lane count.
1460          * Optimize this later for the minimum possible link rate/lane count
1461          * with DSC enabled for the requested mode.
1462          */
1463         pipe_config->pipe_bpp = pipe_bpp;
1464         pipe_config->port_clock = limits->max_rate;
1465         pipe_config->lane_count = limits->max_lane_count;
1466
1467         if (intel_dp_is_edp(intel_dp)) {
1468                 pipe_config->dsc.compressed_bpp =
1469                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1470                               pipe_config->pipe_bpp);
1471                 pipe_config->dsc.slice_count =
1472                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1473                                                         true);
1474         } else {
1475                 u16 dsc_max_output_bpp;
1476                 u8 dsc_dp_slice_count;
1477
1478                 dsc_max_output_bpp =
1479                         intel_dp_dsc_get_output_bpp(dev_priv,
1480                                                     pipe_config->port_clock,
1481                                                     pipe_config->lane_count,
1482                                                     adjusted_mode->crtc_clock,
1483                                                     adjusted_mode->crtc_hdisplay,
1484                                                     pipe_config->bigjoiner_pipes,
1485                                                     pipe_bpp);
1486                 dsc_dp_slice_count =
1487                         intel_dp_dsc_get_slice_count(intel_dp,
1488                                                      adjusted_mode->crtc_clock,
1489                                                      adjusted_mode->crtc_hdisplay,
1490                                                      pipe_config->bigjoiner_pipes);
1491                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1492                         drm_dbg_kms(&dev_priv->drm,
1493                                     "Compressed BPP/Slice Count not supported\n");
1494                         return -EINVAL;
1495                 }
1496                 pipe_config->dsc.compressed_bpp = min_t(u16,
1497                                                                dsc_max_output_bpp >> 4,
1498                                                                pipe_config->pipe_bpp);
1499                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1500         }
1501
1502         /* As of today we support DSC for only RGB */
1503         if (intel_dp->force_dsc_bpp) {
1504                 if (intel_dp->force_dsc_bpp >= 8 &&
1505                     intel_dp->force_dsc_bpp < pipe_bpp) {
1506                         drm_dbg_kms(&dev_priv->drm,
1507                                     "DSC BPP forced to %d",
1508                                     intel_dp->force_dsc_bpp);
1509                         pipe_config->dsc.compressed_bpp =
1510                                                 intel_dp->force_dsc_bpp;
1511                 } else {
1512                         drm_dbg_kms(&dev_priv->drm,
1513                                     "Invalid DSC BPP %d",
1514                                     intel_dp->force_dsc_bpp);
1515                 }
1516         }
1517
1518         /*
1519          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1520          * is greater than the maximum Cdclock and if slice count is even
1521          * then we need to use 2 VDSC instances.
1522          */
1523         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1524             pipe_config->bigjoiner_pipes) {
1525                 if (pipe_config->dsc.slice_count < 2) {
1526                         drm_dbg_kms(&dev_priv->drm,
1527                                     "Cannot split stream to use 2 VDSC instances\n");
1528                         return -EINVAL;
1529                 }
1530
1531                 pipe_config->dsc.dsc_split = true;
1532         }
1533
1534         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1535         if (ret < 0) {
1536                 drm_dbg_kms(&dev_priv->drm,
1537                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1538                             "Compressed BPP = %d\n",
1539                             pipe_config->pipe_bpp,
1540                             pipe_config->dsc.compressed_bpp);
1541                 return ret;
1542         }
1543
1544         pipe_config->dsc.compression_enable = true;
1545         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1546                     "Compressed Bpp = %d Slice Count = %d\n",
1547                     pipe_config->pipe_bpp,
1548                     pipe_config->dsc.compressed_bpp,
1549                     pipe_config->dsc.slice_count);
1550
1551         return 0;
1552 }
1553
1554 static int
1555 intel_dp_compute_link_config(struct intel_encoder *encoder,
1556                              struct intel_crtc_state *pipe_config,
1557                              struct drm_connector_state *conn_state,
1558                              bool respect_downstream_limits)
1559 {
1560         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1561         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1562         const struct drm_display_mode *adjusted_mode =
1563                 &pipe_config->hw.adjusted_mode;
1564         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1565         struct link_config_limits limits;
1566         bool joiner_needs_dsc = false;
1567         int ret;
1568
1569         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1570         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1571
1572         limits.min_lane_count = 1;
1573         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1574
1575         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1576         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1577
1578         if (intel_dp->use_max_params) {
1579                 /*
1580                  * Use the maximum clock and number of lanes the eDP panel
1581                  * advertizes being capable of in case the initial fast
1582                  * optimal params failed us. The panels are generally
1583                  * designed to support only a single clock and lane
1584                  * configuration, and typically on older panels these
1585                  * values correspond to the native resolution of the panel.
1586                  */
1587                 limits.min_lane_count = limits.max_lane_count;
1588                 limits.min_rate = limits.max_rate;
1589         }
1590
1591         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1592
1593         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1594                     "max rate %d max bpp %d pixel clock %iKHz\n",
1595                     limits.max_lane_count, limits.max_rate,
1596                     limits.max_bpp, adjusted_mode->crtc_clock);
1597
1598         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1599                                     adjusted_mode->crtc_clock))
1600                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1601
1602         /*
1603          * Pipe joiner needs compression up to display 12 due to bandwidth
1604          * limitation. DG2 onwards pipe joiner can be enabled without
1605          * compression.
1606          */
1607         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1608
1609         /*
1610          * Optimize for slow and wide for everything, because there are some
1611          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1612          */
1613         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1614
1615         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1616                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1617                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1618                             str_yes_no(intel_dp->force_dsc_en));
1619                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1620                                                   conn_state, &limits);
1621                 if (ret < 0)
1622                         return ret;
1623         }
1624
1625         if (pipe_config->dsc.compression_enable) {
1626                 drm_dbg_kms(&i915->drm,
1627                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1628                             pipe_config->lane_count, pipe_config->port_clock,
1629                             pipe_config->pipe_bpp,
1630                             pipe_config->dsc.compressed_bpp);
1631
1632                 drm_dbg_kms(&i915->drm,
1633                             "DP link rate required %i available %i\n",
1634                             intel_dp_link_required(adjusted_mode->crtc_clock,
1635                                                    pipe_config->dsc.compressed_bpp),
1636                             intel_dp_max_data_rate(pipe_config->port_clock,
1637                                                    pipe_config->lane_count));
1638         } else {
1639                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1640                             pipe_config->lane_count, pipe_config->port_clock,
1641                             pipe_config->pipe_bpp);
1642
1643                 drm_dbg_kms(&i915->drm,
1644                             "DP link rate required %i available %i\n",
1645                             intel_dp_link_required(adjusted_mode->crtc_clock,
1646                                                    pipe_config->pipe_bpp),
1647                             intel_dp_max_data_rate(pipe_config->port_clock,
1648                                                    pipe_config->lane_count));
1649         }
1650         return 0;
1651 }
1652
1653 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1654                                   const struct drm_connector_state *conn_state)
1655 {
1656         const struct intel_digital_connector_state *intel_conn_state =
1657                 to_intel_digital_connector_state(conn_state);
1658         const struct drm_display_mode *adjusted_mode =
1659                 &crtc_state->hw.adjusted_mode;
1660
1661         /*
1662          * Our YCbCr output is always limited range.
1663          * crtc_state->limited_color_range only applies to RGB,
1664          * and it must never be set for YCbCr or we risk setting
1665          * some conflicting bits in PIPECONF which will mess up
1666          * the colors on the monitor.
1667          */
1668         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1669                 return false;
1670
1671         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1672                 /*
1673                  * See:
1674                  * CEA-861-E - 5.1 Default Encoding Parameters
1675                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1676                  */
1677                 return crtc_state->pipe_bpp != 18 &&
1678                         drm_default_rgb_quant_range(adjusted_mode) ==
1679                         HDMI_QUANTIZATION_RANGE_LIMITED;
1680         } else {
1681                 return intel_conn_state->broadcast_rgb ==
1682                         INTEL_BROADCAST_RGB_LIMITED;
1683         }
1684 }
1685
1686 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1687                                     enum port port)
1688 {
1689         if (IS_G4X(dev_priv))
1690                 return false;
1691         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1692                 return false;
1693
1694         return true;
1695 }
1696
1697 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1698                                              const struct drm_connector_state *conn_state,
1699                                              struct drm_dp_vsc_sdp *vsc)
1700 {
1701         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1702         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1703
1704         /*
1705          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1706          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1707          * Colorimetry Format indication.
1708          */
1709         vsc->revision = 0x5;
1710         vsc->length = 0x13;
1711
1712         /* DP 1.4a spec, Table 2-120 */
1713         switch (crtc_state->output_format) {
1714         case INTEL_OUTPUT_FORMAT_YCBCR444:
1715                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1716                 break;
1717         case INTEL_OUTPUT_FORMAT_YCBCR420:
1718                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1719                 break;
1720         case INTEL_OUTPUT_FORMAT_RGB:
1721         default:
1722                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1723         }
1724
1725         switch (conn_state->colorspace) {
1726         case DRM_MODE_COLORIMETRY_BT709_YCC:
1727                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1728                 break;
1729         case DRM_MODE_COLORIMETRY_XVYCC_601:
1730                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1731                 break;
1732         case DRM_MODE_COLORIMETRY_XVYCC_709:
1733                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1734                 break;
1735         case DRM_MODE_COLORIMETRY_SYCC_601:
1736                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1737                 break;
1738         case DRM_MODE_COLORIMETRY_OPYCC_601:
1739                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1740                 break;
1741         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1742                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1743                 break;
1744         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1745                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1746                 break;
1747         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1748                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1749                 break;
1750         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1751         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1752                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1753                 break;
1754         default:
1755                 /*
1756                  * RGB->YCBCR color conversion uses the BT.709
1757                  * color space.
1758                  */
1759                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1760                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1761                 else
1762                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1763                 break;
1764         }
1765
1766         vsc->bpc = crtc_state->pipe_bpp / 3;
1767
1768         /* only RGB pixelformat supports 6 bpc */
1769         drm_WARN_ON(&dev_priv->drm,
1770                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1771
1772         /* all YCbCr are always limited range */
1773         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1774         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1775 }
1776
1777 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1778                                      struct intel_crtc_state *crtc_state,
1779                                      const struct drm_connector_state *conn_state)
1780 {
1781         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1782
1783         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1784         if (crtc_state->has_psr)
1785                 return;
1786
1787         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1788                 return;
1789
1790         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1791         vsc->sdp_type = DP_SDP_VSC;
1792         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1793                                          &crtc_state->infoframes.vsc);
1794 }
1795
1796 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1797                                   const struct intel_crtc_state *crtc_state,
1798                                   const struct drm_connector_state *conn_state,
1799                                   struct drm_dp_vsc_sdp *vsc)
1800 {
1801         vsc->sdp_type = DP_SDP_VSC;
1802
1803         if (crtc_state->has_psr2) {
1804                 if (intel_dp->psr.colorimetry_support &&
1805                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1806                         /* [PSR2, +Colorimetry] */
1807                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1808                                                          vsc);
1809                 } else {
1810                         /*
1811                          * [PSR2, -Colorimetry]
1812                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1813                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1814                          */
1815                         vsc->revision = 0x4;
1816                         vsc->length = 0xe;
1817                 }
1818         } else {
1819                 /*
1820                  * [PSR1]
1821                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1822                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1823                  * higher).
1824                  */
1825                 vsc->revision = 0x2;
1826                 vsc->length = 0x8;
1827         }
1828 }
1829
1830 static void
1831 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1832                                             struct intel_crtc_state *crtc_state,
1833                                             const struct drm_connector_state *conn_state)
1834 {
1835         int ret;
1836         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1837         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1838
1839         if (!conn_state->hdr_output_metadata)
1840                 return;
1841
1842         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1843
1844         if (ret) {
1845                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1846                 return;
1847         }
1848
1849         crtc_state->infoframes.enable |=
1850                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1851 }
1852
1853 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1854                                     enum transcoder cpu_transcoder)
1855 {
1856         /* M1/N1 is double buffered */
1857         if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
1858                 return true;
1859
1860         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1861 }
1862
1863 static bool can_enable_drrs(struct intel_connector *connector,
1864                             const struct intel_crtc_state *pipe_config,
1865                             const struct drm_display_mode *downclock_mode)
1866 {
1867         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1868
1869         if (pipe_config->vrr.enable)
1870                 return false;
1871
1872         /*
1873          * DRRS and PSR can't be enable together, so giving preference to PSR
1874          * as it allows more power-savings by complete shutting down display,
1875          * so to guarantee this, intel_drrs_compute_config() must be called
1876          * after intel_psr_compute_config().
1877          */
1878         if (pipe_config->has_psr)
1879                 return false;
1880
1881         /* FIXME missing FDI M2/N2 etc. */
1882         if (pipe_config->has_pch_encoder)
1883                 return false;
1884
1885         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1886                 return false;
1887
1888         return downclock_mode &&
1889                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1890 }
1891
1892 static void
1893 intel_dp_drrs_compute_config(struct intel_connector *connector,
1894                              struct intel_crtc_state *pipe_config,
1895                              int output_bpp, bool constant_n)
1896 {
1897         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1898         const struct drm_display_mode *downclock_mode =
1899                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1900         int pixel_clock;
1901
1902         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1903                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1904                         intel_zero_m_n(&pipe_config->dp_m2_n2);
1905                 return;
1906         }
1907
1908         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1909                 pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
1910
1911         pipe_config->has_drrs = true;
1912
1913         pixel_clock = downclock_mode->clock;
1914         if (pipe_config->splitter.enable)
1915                 pixel_clock /= pipe_config->splitter.link_count;
1916
1917         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1918                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1919                                constant_n, pipe_config->fec_enable);
1920
1921         /* FIXME: abstract this better */
1922         if (pipe_config->splitter.enable)
1923                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1924 }
1925
1926 static bool intel_dp_has_audio(struct intel_encoder *encoder,
1927                                const struct intel_crtc_state *crtc_state,
1928                                const struct drm_connector_state *conn_state)
1929 {
1930         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1931         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1932         const struct intel_digital_connector_state *intel_conn_state =
1933                 to_intel_digital_connector_state(conn_state);
1934
1935         if (!intel_dp_port_has_audio(i915, encoder->port))
1936                 return false;
1937
1938         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1939                 return intel_dp->has_audio;
1940         else
1941                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1942 }
1943
1944 static int
1945 intel_dp_compute_output_format(struct intel_encoder *encoder,
1946                                struct intel_crtc_state *crtc_state,
1947                                struct drm_connector_state *conn_state,
1948                                bool respect_downstream_limits)
1949 {
1950         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1951         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1952         struct intel_connector *connector = intel_dp->attached_connector;
1953         const struct drm_display_info *info = &connector->base.display_info;
1954         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1955         bool ycbcr_420_only;
1956         int ret;
1957
1958         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1959
1960         crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1961
1962         if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
1963                 drm_dbg_kms(&i915->drm,
1964                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
1965                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
1966         }
1967
1968         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1969                                            respect_downstream_limits);
1970         if (ret) {
1971                 if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
1972                     !connector->base.ycbcr_420_allowed ||
1973                     !drm_mode_is_420_also(info, adjusted_mode))
1974                         return ret;
1975
1976                 crtc_state->output_format = intel_dp_output_format(connector, true);
1977                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1978                                                    respect_downstream_limits);
1979         }
1980
1981         return ret;
1982 }
1983
1984 int
1985 intel_dp_compute_config(struct intel_encoder *encoder,
1986                         struct intel_crtc_state *pipe_config,
1987                         struct drm_connector_state *conn_state)
1988 {
1989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1990         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1991         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1992         const struct drm_display_mode *fixed_mode;
1993         struct intel_connector *connector = intel_dp->attached_connector;
1994         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1995         int ret = 0, output_bpp;
1996
1997         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
1998                 pipe_config->has_pch_encoder = true;
1999
2000         pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2001
2002         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2003         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2004                 ret = intel_panel_compute_config(connector, adjusted_mode);
2005                 if (ret)
2006                         return ret;
2007         }
2008
2009         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2010                 return -EINVAL;
2011
2012         if (HAS_GMCH(dev_priv) &&
2013             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2014                 return -EINVAL;
2015
2016         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2017                 return -EINVAL;
2018
2019         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2020                 return -EINVAL;
2021
2022         /*
2023          * Try to respect downstream TMDS clock limits first, if
2024          * that fails assume the user might know something we don't.
2025          */
2026         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2027         if (ret)
2028                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2029         if (ret)
2030                 return ret;
2031
2032         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2033             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2034                 ret = intel_panel_fitting(pipe_config, conn_state);
2035                 if (ret)
2036                         return ret;
2037         }
2038
2039         pipe_config->limited_color_range =
2040                 intel_dp_limited_color_range(pipe_config, conn_state);
2041
2042         if (pipe_config->dsc.compression_enable)
2043                 output_bpp = pipe_config->dsc.compressed_bpp;
2044         else
2045                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2046                                                  pipe_config->pipe_bpp);
2047
2048         if (intel_dp->mso_link_count) {
2049                 int n = intel_dp->mso_link_count;
2050                 int overlap = intel_dp->mso_pixel_overlap;
2051
2052                 pipe_config->splitter.enable = true;
2053                 pipe_config->splitter.link_count = n;
2054                 pipe_config->splitter.pixel_overlap = overlap;
2055
2056                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2057                             n, overlap);
2058
2059                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2060                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2061                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2062                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2063                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2064                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2065                 adjusted_mode->crtc_clock /= n;
2066         }
2067
2068         intel_link_compute_m_n(output_bpp,
2069                                pipe_config->lane_count,
2070                                adjusted_mode->crtc_clock,
2071                                pipe_config->port_clock,
2072                                &pipe_config->dp_m_n,
2073                                constant_n, pipe_config->fec_enable);
2074
2075         /* FIXME: abstract this better */
2076         if (pipe_config->splitter.enable)
2077                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2078
2079         if (!HAS_DDI(dev_priv))
2080                 g4x_dp_set_clock(encoder, pipe_config);
2081
2082         intel_vrr_compute_config(pipe_config, conn_state);
2083         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2084         intel_dp_drrs_compute_config(connector, pipe_config,
2085                                      output_bpp, constant_n);
2086         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2087         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2088
2089         return 0;
2090 }
2091
2092 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2093                               int link_rate, int lane_count)
2094 {
2095         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2096         intel_dp->link_trained = false;
2097         intel_dp->link_rate = link_rate;
2098         intel_dp->lane_count = lane_count;
2099 }
2100
2101 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2102 {
2103         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2104         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2105 }
2106
2107 /* Enable backlight PWM and backlight PP control. */
2108 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2109                             const struct drm_connector_state *conn_state)
2110 {
2111         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2112         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2113
2114         if (!intel_dp_is_edp(intel_dp))
2115                 return;
2116
2117         drm_dbg_kms(&i915->drm, "\n");
2118
2119         intel_backlight_enable(crtc_state, conn_state);
2120         intel_pps_backlight_on(intel_dp);
2121 }
2122
2123 /* Disable backlight PP control and backlight PWM. */
2124 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2125 {
2126         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2127         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2128
2129         if (!intel_dp_is_edp(intel_dp))
2130                 return;
2131
2132         drm_dbg_kms(&i915->drm, "\n");
2133
2134         intel_pps_backlight_off(intel_dp);
2135         intel_backlight_disable(old_conn_state);
2136 }
2137
2138 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2139 {
2140         /*
2141          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2142          * be capable of signalling downstream hpd with a long pulse.
2143          * Whether or not that means D3 is safe to use is not clear,
2144          * but let's assume so until proven otherwise.
2145          *
2146          * FIXME should really check all downstream ports...
2147          */
2148         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2149                 drm_dp_is_branch(intel_dp->dpcd) &&
2150                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2151 }
2152
2153 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2154                                            const struct intel_crtc_state *crtc_state,
2155                                            bool enable)
2156 {
2157         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2158         int ret;
2159
2160         if (!crtc_state->dsc.compression_enable)
2161                 return;
2162
2163         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2164                                  enable ? DP_DECOMPRESSION_EN : 0);
2165         if (ret < 0)
2166                 drm_dbg_kms(&i915->drm,
2167                             "Failed to %s sink decompression state\n",
2168                             str_enable_disable(enable));
2169 }
2170
2171 static void
2172 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2173 {
2174         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2175         u8 oui[] = { 0x00, 0xaa, 0x01 };
2176         u8 buf[3] = { 0 };
2177
2178         /*
2179          * During driver init, we want to be careful and avoid changing the source OUI if it's
2180          * already set to what we want, so as to avoid clearing any state by accident
2181          */
2182         if (careful) {
2183                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2184                         drm_err(&i915->drm, "Failed to read source OUI\n");
2185
2186                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2187                         return;
2188         }
2189
2190         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2191                 drm_err(&i915->drm, "Failed to write source OUI\n");
2192
2193         intel_dp->last_oui_write = jiffies;
2194 }
2195
2196 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2197 {
2198         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2199
2200         drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2201         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2202 }
2203
2204 /* If the device supports it, try to set the power state appropriately */
2205 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2206 {
2207         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2208         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2209         int ret, i;
2210
2211         /* Should have a valid DPCD by this point */
2212         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2213                 return;
2214
2215         if (mode != DP_SET_POWER_D0) {
2216                 if (downstream_hpd_needs_d0(intel_dp))
2217                         return;
2218
2219                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2220         } else {
2221                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2222
2223                 lspcon_resume(dp_to_dig_port(intel_dp));
2224
2225                 /* Write the source OUI as early as possible */
2226                 if (intel_dp_is_edp(intel_dp))
2227                         intel_edp_init_source_oui(intel_dp, false);
2228
2229                 /*
2230                  * When turning on, we need to retry for 1ms to give the sink
2231                  * time to wake up.
2232                  */
2233                 for (i = 0; i < 3; i++) {
2234                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2235                         if (ret == 1)
2236                                 break;
2237                         msleep(1);
2238                 }
2239
2240                 if (ret == 1 && lspcon->active)
2241                         lspcon_wait_pcon_mode(lspcon);
2242         }
2243
2244         if (ret != 1)
2245                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2246                             encoder->base.base.id, encoder->base.name,
2247                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2248 }
2249
2250 static bool
2251 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2252
2253 /**
2254  * intel_dp_sync_state - sync the encoder state during init/resume
2255  * @encoder: intel encoder to sync
2256  * @crtc_state: state for the CRTC connected to the encoder
2257  *
2258  * Sync any state stored in the encoder wrt. HW state during driver init
2259  * and system resume.
2260  */
2261 void intel_dp_sync_state(struct intel_encoder *encoder,
2262                          const struct intel_crtc_state *crtc_state)
2263 {
2264         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2265
2266         if (!crtc_state)
2267                 return;
2268
2269         /*
2270          * Don't clobber DPCD if it's been already read out during output
2271          * setup (eDP) or detect.
2272          */
2273         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2274                 intel_dp_get_dpcd(intel_dp);
2275
2276         intel_dp_reset_max_link_params(intel_dp);
2277 }
2278
2279 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2280                                     struct intel_crtc_state *crtc_state)
2281 {
2282         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2283         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2284
2285         /*
2286          * If BIOS has set an unsupported or non-standard link rate for some
2287          * reason force an encoder recompute and full modeset.
2288          */
2289         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2290                                 crtc_state->port_clock) < 0) {
2291                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2292                 crtc_state->uapi.connectors_changed = true;
2293                 return false;
2294         }
2295
2296         /*
2297          * FIXME hack to force full modeset when DSC is being used.
2298          *
2299          * As long as we do not have full state readout and config comparison
2300          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2301          * Remove once we have readout for DSC.
2302          */
2303         if (crtc_state->dsc.compression_enable) {
2304                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2305                 crtc_state->uapi.mode_changed = true;
2306                 return false;
2307         }
2308
2309         if (CAN_PSR(intel_dp)) {
2310                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2311                 crtc_state->uapi.mode_changed = true;
2312                 return false;
2313         }
2314
2315         return true;
2316 }
2317
2318 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2319 {
2320         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2321
2322         /* Clear the cached register set to avoid using stale values */
2323
2324         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2325
2326         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2327                              intel_dp->pcon_dsc_dpcd,
2328                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2329                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2330                         DP_PCON_DSC_ENCODER);
2331
2332         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2333                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2334 }
2335
2336 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2337 {
2338         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2339         int i;
2340
2341         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2342                 if (frl_bw_mask & (1 << i))
2343                         return bw_gbps[i];
2344         }
2345         return 0;
2346 }
2347
2348 static int intel_dp_pcon_set_frl_mask(int max_frl)
2349 {
2350         switch (max_frl) {
2351         case 48:
2352                 return DP_PCON_FRL_BW_MASK_48GBPS;
2353         case 40:
2354                 return DP_PCON_FRL_BW_MASK_40GBPS;
2355         case 32:
2356                 return DP_PCON_FRL_BW_MASK_32GBPS;
2357         case 24:
2358                 return DP_PCON_FRL_BW_MASK_24GBPS;
2359         case 18:
2360                 return DP_PCON_FRL_BW_MASK_18GBPS;
2361         case 9:
2362                 return DP_PCON_FRL_BW_MASK_9GBPS;
2363         }
2364
2365         return 0;
2366 }
2367
2368 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2369 {
2370         struct intel_connector *intel_connector = intel_dp->attached_connector;
2371         struct drm_connector *connector = &intel_connector->base;
2372         int max_frl_rate;
2373         int max_lanes, rate_per_lane;
2374         int max_dsc_lanes, dsc_rate_per_lane;
2375
2376         max_lanes = connector->display_info.hdmi.max_lanes;
2377         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2378         max_frl_rate = max_lanes * rate_per_lane;
2379
2380         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2381                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2382                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2383                 if (max_dsc_lanes && dsc_rate_per_lane)
2384                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2385         }
2386
2387         return max_frl_rate;
2388 }
2389
2390 static bool
2391 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2392                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2393 {
2394         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2395             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2396             *frl_trained_mask >= max_frl_bw_mask)
2397                 return true;
2398
2399         return false;
2400 }
2401
2402 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2403 {
2404 #define TIMEOUT_FRL_READY_MS 500
2405 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2406
2407         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2408         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2409         u8 max_frl_bw_mask = 0, frl_trained_mask;
2410         bool is_active;
2411
2412         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2413         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2414
2415         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2416         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2417
2418         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2419
2420         if (max_frl_bw <= 0)
2421                 return -EINVAL;
2422
2423         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2424         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2425
2426         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2427                 goto frl_trained;
2428
2429         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2430         if (ret < 0)
2431                 return ret;
2432         /* Wait for PCON to be FRL Ready */
2433         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2434
2435         if (!is_active)
2436                 return -ETIMEDOUT;
2437
2438         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2439                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2440         if (ret < 0)
2441                 return ret;
2442         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2443                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2444         if (ret < 0)
2445                 return ret;
2446         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2447         if (ret < 0)
2448                 return ret;
2449         /*
2450          * Wait for FRL to be completed
2451          * Check if the HDMI Link is up and active.
2452          */
2453         wait_for(is_active =
2454                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2455                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2456
2457         if (!is_active)
2458                 return -ETIMEDOUT;
2459
2460 frl_trained:
2461         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2462         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2463         intel_dp->frl.is_trained = true;
2464         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2465
2466         return 0;
2467 }
2468
2469 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2470 {
2471         if (drm_dp_is_branch(intel_dp->dpcd) &&
2472             intel_dp->has_hdmi_sink &&
2473             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2474                 return true;
2475
2476         return false;
2477 }
2478
2479 static
2480 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2481 {
2482         int ret;
2483         u8 buf = 0;
2484
2485         /* Set PCON source control mode */
2486         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2487
2488         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2489         if (ret < 0)
2490                 return ret;
2491
2492         /* Set HDMI LINK ENABLE */
2493         buf |= DP_PCON_ENABLE_HDMI_LINK;
2494         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2495         if (ret < 0)
2496                 return ret;
2497
2498         return 0;
2499 }
2500
2501 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2502 {
2503         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2504
2505         /*
2506          * Always go for FRL training if:
2507          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2508          * -sink is HDMI2.1
2509          */
2510         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2511             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2512             intel_dp->frl.is_trained)
2513                 return;
2514
2515         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2516                 int ret, mode;
2517
2518                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2519                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2520                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2521
2522                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2523                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2524         } else {
2525                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2526         }
2527 }
2528
2529 static int
2530 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2531 {
2532         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2533
2534         return intel_hdmi_dsc_get_slice_height(vactive);
2535 }
2536
2537 static int
2538 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2539                              const struct intel_crtc_state *crtc_state)
2540 {
2541         struct intel_connector *intel_connector = intel_dp->attached_connector;
2542         struct drm_connector *connector = &intel_connector->base;
2543         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2544         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2545         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2546         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2547
2548         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2549                                              pcon_max_slice_width,
2550                                              hdmi_max_slices, hdmi_throughput);
2551 }
2552
2553 static int
2554 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2555                           const struct intel_crtc_state *crtc_state,
2556                           int num_slices, int slice_width)
2557 {
2558         struct intel_connector *intel_connector = intel_dp->attached_connector;
2559         struct drm_connector *connector = &intel_connector->base;
2560         int output_format = crtc_state->output_format;
2561         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2562         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2563         int hdmi_max_chunk_bytes =
2564                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2565
2566         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2567                                       num_slices, output_format, hdmi_all_bpp,
2568                                       hdmi_max_chunk_bytes);
2569 }
2570
2571 void
2572 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2573                             const struct intel_crtc_state *crtc_state)
2574 {
2575         u8 pps_param[6];
2576         int slice_height;
2577         int slice_width;
2578         int num_slices;
2579         int bits_per_pixel;
2580         int ret;
2581         struct intel_connector *intel_connector = intel_dp->attached_connector;
2582         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2583         struct drm_connector *connector;
2584         bool hdmi_is_dsc_1_2;
2585
2586         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2587                 return;
2588
2589         if (!intel_connector)
2590                 return;
2591         connector = &intel_connector->base;
2592         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2593
2594         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2595             !hdmi_is_dsc_1_2)
2596                 return;
2597
2598         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2599         if (!slice_height)
2600                 return;
2601
2602         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2603         if (!num_slices)
2604                 return;
2605
2606         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2607                                    num_slices);
2608
2609         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2610                                                    num_slices, slice_width);
2611         if (!bits_per_pixel)
2612                 return;
2613
2614         pps_param[0] = slice_height & 0xFF;
2615         pps_param[1] = slice_height >> 8;
2616         pps_param[2] = slice_width & 0xFF;
2617         pps_param[3] = slice_width >> 8;
2618         pps_param[4] = bits_per_pixel & 0xFF;
2619         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2620
2621         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2622         if (ret < 0)
2623                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2624 }
2625
2626 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2627                                            const struct intel_crtc_state *crtc_state)
2628 {
2629         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2630         u8 tmp;
2631
2632         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2633                 return;
2634
2635         if (!drm_dp_is_branch(intel_dp->dpcd))
2636                 return;
2637
2638         tmp = intel_dp->has_hdmi_sink ?
2639                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2640
2641         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2642                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2643                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2644                             str_enable_disable(intel_dp->has_hdmi_sink));
2645
2646         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2647                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2648
2649         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2650                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2651                 drm_dbg_kms(&i915->drm,
2652                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2653                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2654
2655         tmp = intel_dp->dfp.rgb_to_ycbcr ?
2656                 DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2657
2658         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2659                 drm_dbg_kms(&i915->drm,
2660                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2661                            str_enable_disable(tmp));
2662 }
2663
2664
2665 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2666 {
2667         u8 dprx = 0;
2668
2669         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2670                               &dprx) != 1)
2671                 return false;
2672         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2673 }
2674
2675 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2676 {
2677         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2678
2679         /*
2680          * Clear the cached register set to avoid using stale values
2681          * for the sinks that do not support DSC.
2682          */
2683         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2684
2685         /* Clear fec_capable to avoid using stale values */
2686         intel_dp->fec_capable = 0;
2687
2688         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2689         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2690             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2691                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2692                                      intel_dp->dsc_dpcd,
2693                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2694                         drm_err(&i915->drm,
2695                                 "Failed to read DPCD register 0x%x\n",
2696                                 DP_DSC_SUPPORT);
2697
2698                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2699                             (int)sizeof(intel_dp->dsc_dpcd),
2700                             intel_dp->dsc_dpcd);
2701
2702                 /* FEC is supported only on DP 1.4 */
2703                 if (!intel_dp_is_edp(intel_dp) &&
2704                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2705                                       &intel_dp->fec_capable) < 0)
2706                         drm_err(&i915->drm,
2707                                 "Failed to read FEC DPCD register\n");
2708
2709                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2710                             intel_dp->fec_capable);
2711         }
2712 }
2713
2714 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2715                                      struct drm_display_mode *mode)
2716 {
2717         struct intel_dp *intel_dp = intel_attached_dp(connector);
2718         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2719         int n = intel_dp->mso_link_count;
2720         int overlap = intel_dp->mso_pixel_overlap;
2721
2722         if (!mode || !n)
2723                 return;
2724
2725         mode->hdisplay = (mode->hdisplay - overlap) * n;
2726         mode->hsync_start = (mode->hsync_start - overlap) * n;
2727         mode->hsync_end = (mode->hsync_end - overlap) * n;
2728         mode->htotal = (mode->htotal - overlap) * n;
2729         mode->clock *= n;
2730
2731         drm_mode_set_name(mode);
2732
2733         drm_dbg_kms(&i915->drm,
2734                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2735                     connector->base.base.id, connector->base.name,
2736                     DRM_MODE_ARG(mode));
2737 }
2738
2739 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2740 {
2741         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2742         struct intel_connector *connector = intel_dp->attached_connector;
2743         struct drm_display_info *info = &connector->base.display_info;
2744         u8 mso;
2745
2746         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2747                 return;
2748
2749         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2750                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2751                 return;
2752         }
2753
2754         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2755         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2756         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2757                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2758                 mso = 0;
2759         }
2760
2761         if (mso) {
2762                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2763                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2764                             info->mso_pixel_overlap);
2765                 if (!HAS_MSO(i915)) {
2766                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2767                         mso = 0;
2768                 }
2769         }
2770
2771         intel_dp->mso_link_count = mso;
2772         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2773 }
2774
2775 static bool
2776 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2777 {
2778         struct drm_i915_private *dev_priv =
2779                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2780
2781         /* this function is meant to be called only once */
2782         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2783
2784         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2785                 return false;
2786
2787         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2788                          drm_dp_is_branch(intel_dp->dpcd));
2789
2790         /*
2791          * Read the eDP display control registers.
2792          *
2793          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2794          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2795          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2796          * method). The display control registers should read zero if they're
2797          * not supported anyway.
2798          */
2799         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2800                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2801                              sizeof(intel_dp->edp_dpcd)) {
2802                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2803                             (int)sizeof(intel_dp->edp_dpcd),
2804                             intel_dp->edp_dpcd);
2805
2806                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2807         }
2808
2809         /*
2810          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2811          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2812          */
2813         intel_psr_init_dpcd(intel_dp);
2814
2815         /* Clear the default sink rates */
2816         intel_dp->num_sink_rates = 0;
2817
2818         /* Read the eDP 1.4+ supported link rates. */
2819         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2820                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2821                 int i;
2822
2823                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2824                                 sink_rates, sizeof(sink_rates));
2825
2826                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2827                         int val = le16_to_cpu(sink_rates[i]);
2828
2829                         if (val == 0)
2830                                 break;
2831
2832                         /* Value read multiplied by 200kHz gives the per-lane
2833                          * link rate in kHz. The source rates are, however,
2834                          * stored in terms of LS_Clk kHz. The full conversion
2835                          * back to symbols is
2836                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2837                          */
2838                         intel_dp->sink_rates[i] = (val * 200) / 10;
2839                 }
2840                 intel_dp->num_sink_rates = i;
2841         }
2842
2843         /*
2844          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2845          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2846          */
2847         if (intel_dp->num_sink_rates)
2848                 intel_dp->use_rate_select = true;
2849         else
2850                 intel_dp_set_sink_rates(intel_dp);
2851         intel_dp_set_max_sink_lane_count(intel_dp);
2852
2853         intel_dp_set_common_rates(intel_dp);
2854         intel_dp_reset_max_link_params(intel_dp);
2855
2856         /* Read the eDP DSC DPCD registers */
2857         if (DISPLAY_VER(dev_priv) >= 10)
2858                 intel_dp_get_dsc_sink_cap(intel_dp);
2859
2860         /*
2861          * If needed, program our source OUI so we can make various Intel-specific AUX services
2862          * available (such as HDR backlight controls)
2863          */
2864         intel_edp_init_source_oui(intel_dp, true);
2865
2866         return true;
2867 }
2868
2869 static bool
2870 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2871 {
2872         if (!intel_dp->attached_connector)
2873                 return false;
2874
2875         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2876                                           intel_dp->dpcd,
2877                                           &intel_dp->desc);
2878 }
2879
2880 static bool
2881 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2882 {
2883         int ret;
2884
2885         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2886                 return false;
2887
2888         /*
2889          * Don't clobber cached eDP rates. Also skip re-reading
2890          * the OUI/ID since we know it won't change.
2891          */
2892         if (!intel_dp_is_edp(intel_dp)) {
2893                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2894                                  drm_dp_is_branch(intel_dp->dpcd));
2895
2896                 intel_dp_set_sink_rates(intel_dp);
2897                 intel_dp_set_max_sink_lane_count(intel_dp);
2898                 intel_dp_set_common_rates(intel_dp);
2899         }
2900
2901         if (intel_dp_has_sink_count(intel_dp)) {
2902                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2903                 if (ret < 0)
2904                         return false;
2905
2906                 /*
2907                  * Sink count can change between short pulse hpd hence
2908                  * a member variable in intel_dp will track any changes
2909                  * between short pulse interrupts.
2910                  */
2911                 intel_dp->sink_count = ret;
2912
2913                 /*
2914                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2915                  * a dongle is present but no display. Unless we require to know
2916                  * if a dongle is present or not, we don't need to update
2917                  * downstream port information. So, an early return here saves
2918                  * time from performing other operations which are not required.
2919                  */
2920                 if (!intel_dp->sink_count)
2921                         return false;
2922         }
2923
2924         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2925                                            intel_dp->downstream_ports) == 0;
2926 }
2927
2928 static bool
2929 intel_dp_can_mst(struct intel_dp *intel_dp)
2930 {
2931         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2932
2933         return i915->params.enable_dp_mst &&
2934                 intel_dp_mst_source_support(intel_dp) &&
2935                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2936 }
2937
2938 static void
2939 intel_dp_configure_mst(struct intel_dp *intel_dp)
2940 {
2941         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2942         struct intel_encoder *encoder =
2943                 &dp_to_dig_port(intel_dp)->base;
2944         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2945
2946         drm_dbg_kms(&i915->drm,
2947                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2948                     encoder->base.base.id, encoder->base.name,
2949                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
2950                     str_yes_no(sink_can_mst),
2951                     str_yes_no(i915->params.enable_dp_mst));
2952
2953         if (!intel_dp_mst_source_support(intel_dp))
2954                 return;
2955
2956         intel_dp->is_mst = sink_can_mst &&
2957                 i915->params.enable_dp_mst;
2958
2959         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2960                                         intel_dp->is_mst);
2961 }
2962
2963 static bool
2964 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
2965 {
2966         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
2967 }
2968
2969 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
2970 {
2971         int retry;
2972
2973         for (retry = 0; retry < 3; retry++) {
2974                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
2975                                       &esi[1], 3) == 3)
2976                         return true;
2977         }
2978
2979         return false;
2980 }
2981
2982 bool
2983 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2984                        const struct drm_connector_state *conn_state)
2985 {
2986         /*
2987          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2988          * of Color Encoding Format and Content Color Gamut], in order to
2989          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2990          */
2991         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2992                 return true;
2993
2994         switch (conn_state->colorspace) {
2995         case DRM_MODE_COLORIMETRY_SYCC_601:
2996         case DRM_MODE_COLORIMETRY_OPYCC_601:
2997         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2998         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2999         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3000                 return true;
3001         default:
3002                 break;
3003         }
3004
3005         return false;
3006 }
3007
3008 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3009                                      struct dp_sdp *sdp, size_t size)
3010 {
3011         size_t length = sizeof(struct dp_sdp);
3012
3013         if (size < length)
3014                 return -ENOSPC;
3015
3016         memset(sdp, 0, size);
3017
3018         /*
3019          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3020          * VSC SDP Header Bytes
3021          */
3022         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3023         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3024         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3025         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3026
3027         /*
3028          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3029          * per DP 1.4a spec.
3030          */
3031         if (vsc->revision != 0x5)
3032                 goto out;
3033
3034         /* VSC SDP Payload for DB16 through DB18 */
3035         /* Pixel Encoding and Colorimetry Formats  */
3036         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3037         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3038
3039         switch (vsc->bpc) {
3040         case 6:
3041                 /* 6bpc: 0x0 */
3042                 break;
3043         case 8:
3044                 sdp->db[17] = 0x1; /* DB17[3:0] */
3045                 break;
3046         case 10:
3047                 sdp->db[17] = 0x2;
3048                 break;
3049         case 12:
3050                 sdp->db[17] = 0x3;
3051                 break;
3052         case 16:
3053                 sdp->db[17] = 0x4;
3054                 break;
3055         default:
3056                 MISSING_CASE(vsc->bpc);
3057                 break;
3058         }
3059         /* Dynamic Range and Component Bit Depth */
3060         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3061                 sdp->db[17] |= 0x80;  /* DB17[7] */
3062
3063         /* Content Type */
3064         sdp->db[18] = vsc->content_type & 0x7;
3065
3066 out:
3067         return length;
3068 }
3069
3070 static ssize_t
3071 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3072                                          const struct hdmi_drm_infoframe *drm_infoframe,
3073                                          struct dp_sdp *sdp,
3074                                          size_t size)
3075 {
3076         size_t length = sizeof(struct dp_sdp);
3077         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3078         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3079         ssize_t len;
3080
3081         if (size < length)
3082                 return -ENOSPC;
3083
3084         memset(sdp, 0, size);
3085
3086         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3087         if (len < 0) {
3088                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3089                 return -ENOSPC;
3090         }
3091
3092         if (len != infoframe_size) {
3093                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3094                 return -ENOSPC;
3095         }
3096
3097         /*
3098          * Set up the infoframe sdp packet for HDR static metadata.
3099          * Prepare VSC Header for SU as per DP 1.4a spec,
3100          * Table 2-100 and Table 2-101
3101          */
3102
3103         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3104         sdp->sdp_header.HB0 = 0;
3105         /*
3106          * Packet Type 80h + Non-audio INFOFRAME Type value
3107          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3108          * - 80h + Non-audio INFOFRAME Type value
3109          * - InfoFrame Type: 0x07
3110          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3111          */
3112         sdp->sdp_header.HB1 = drm_infoframe->type;
3113         /*
3114          * Least Significant Eight Bits of (Data Byte Count – 1)
3115          * infoframe_size - 1
3116          */
3117         sdp->sdp_header.HB2 = 0x1D;
3118         /* INFOFRAME SDP Version Number */
3119         sdp->sdp_header.HB3 = (0x13 << 2);
3120         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3121         sdp->db[0] = drm_infoframe->version;
3122         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3123         sdp->db[1] = drm_infoframe->length;
3124         /*
3125          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3126          * HDMI_INFOFRAME_HEADER_SIZE
3127          */
3128         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3129         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3130                HDMI_DRM_INFOFRAME_SIZE);
3131
3132         /*
3133          * Size of DP infoframe sdp packet for HDR static metadata consists of
3134          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3135          * - Two Data Blocks: 2 bytes
3136          *    CTA Header Byte2 (INFOFRAME Version Number)
3137          *    CTA Header Byte3 (Length of INFOFRAME)
3138          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3139          *
3140          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3141          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3142          * will pad rest of the size.
3143          */
3144         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3145 }
3146
3147 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3148                                const struct intel_crtc_state *crtc_state,
3149                                unsigned int type)
3150 {
3151         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3152         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3153         struct dp_sdp sdp = {};
3154         ssize_t len;
3155
3156         if ((crtc_state->infoframes.enable &
3157              intel_hdmi_infoframe_enable(type)) == 0)
3158                 return;
3159
3160         switch (type) {
3161         case DP_SDP_VSC:
3162                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3163                                             sizeof(sdp));
3164                 break;
3165         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3166                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3167                                                                &crtc_state->infoframes.drm.drm,
3168                                                                &sdp, sizeof(sdp));
3169                 break;
3170         default:
3171                 MISSING_CASE(type);
3172                 return;
3173         }
3174
3175         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3176                 return;
3177
3178         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3179 }
3180
3181 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3182                             const struct intel_crtc_state *crtc_state,
3183                             const struct drm_dp_vsc_sdp *vsc)
3184 {
3185         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3186         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3187         struct dp_sdp sdp = {};
3188         ssize_t len;
3189
3190         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3191
3192         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3193                 return;
3194
3195         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3196                                         &sdp, len);
3197 }
3198
3199 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3200                              bool enable,
3201                              const struct intel_crtc_state *crtc_state,
3202                              const struct drm_connector_state *conn_state)
3203 {
3204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3205         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3206         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3207                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3208                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3209         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3210
3211         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3212         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3213         if (!crtc_state->has_psr)
3214                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3215
3216         intel_de_write(dev_priv, reg, val);
3217         intel_de_posting_read(dev_priv, reg);
3218
3219         if (!enable)
3220                 return;
3221
3222         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3223         if (!crtc_state->has_psr)
3224                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3225
3226         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3227 }
3228
3229 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3230                                    const void *buffer, size_t size)
3231 {
3232         const struct dp_sdp *sdp = buffer;
3233
3234         if (size < sizeof(struct dp_sdp))
3235                 return -EINVAL;
3236
3237         memset(vsc, 0, sizeof(*vsc));
3238
3239         if (sdp->sdp_header.HB0 != 0)
3240                 return -EINVAL;
3241
3242         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3243                 return -EINVAL;
3244
3245         vsc->sdp_type = sdp->sdp_header.HB1;
3246         vsc->revision = sdp->sdp_header.HB2;
3247         vsc->length = sdp->sdp_header.HB3;
3248
3249         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3250             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3251                 /*
3252                  * - HB2 = 0x2, HB3 = 0x8
3253                  *   VSC SDP supporting 3D stereo + PSR
3254                  * - HB2 = 0x4, HB3 = 0xe
3255                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3256                  *   first scan line of the SU region (applies to eDP v1.4b
3257                  *   and higher).
3258                  */
3259                 return 0;
3260         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3261                 /*
3262                  * - HB2 = 0x5, HB3 = 0x13
3263                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3264                  *   Format.
3265                  */
3266                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3267                 vsc->colorimetry = sdp->db[16] & 0xf;
3268                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3269
3270                 switch (sdp->db[17] & 0x7) {
3271                 case 0x0:
3272                         vsc->bpc = 6;
3273                         break;
3274                 case 0x1:
3275                         vsc->bpc = 8;
3276                         break;
3277                 case 0x2:
3278                         vsc->bpc = 10;
3279                         break;
3280                 case 0x3:
3281                         vsc->bpc = 12;
3282                         break;
3283                 case 0x4:
3284                         vsc->bpc = 16;
3285                         break;
3286                 default:
3287                         MISSING_CASE(sdp->db[17] & 0x7);
3288                         return -EINVAL;
3289                 }
3290
3291                 vsc->content_type = sdp->db[18] & 0x7;
3292         } else {
3293                 return -EINVAL;
3294         }
3295
3296         return 0;
3297 }
3298
3299 static int
3300 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3301                                            const void *buffer, size_t size)
3302 {
3303         int ret;
3304
3305         const struct dp_sdp *sdp = buffer;
3306
3307         if (size < sizeof(struct dp_sdp))
3308                 return -EINVAL;
3309
3310         if (sdp->sdp_header.HB0 != 0)
3311                 return -EINVAL;
3312
3313         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3314                 return -EINVAL;
3315
3316         /*
3317          * Least Significant Eight Bits of (Data Byte Count – 1)
3318          * 1Dh (i.e., Data Byte Count = 30 bytes).
3319          */
3320         if (sdp->sdp_header.HB2 != 0x1D)
3321                 return -EINVAL;
3322
3323         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3324         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3325                 return -EINVAL;
3326
3327         /* INFOFRAME SDP Version Number */
3328         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3329                 return -EINVAL;
3330
3331         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3332         if (sdp->db[0] != 1)
3333                 return -EINVAL;
3334
3335         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3336         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3337                 return -EINVAL;
3338
3339         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3340                                              HDMI_DRM_INFOFRAME_SIZE);
3341
3342         return ret;
3343 }
3344
3345 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3346                                   struct intel_crtc_state *crtc_state,
3347                                   struct drm_dp_vsc_sdp *vsc)
3348 {
3349         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3351         unsigned int type = DP_SDP_VSC;
3352         struct dp_sdp sdp = {};
3353         int ret;
3354
3355         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3356         if (crtc_state->has_psr)
3357                 return;
3358
3359         if ((crtc_state->infoframes.enable &
3360              intel_hdmi_infoframe_enable(type)) == 0)
3361                 return;
3362
3363         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3364
3365         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3366
3367         if (ret)
3368                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3369 }
3370
3371 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3372                                                      struct intel_crtc_state *crtc_state,
3373                                                      struct hdmi_drm_infoframe *drm_infoframe)
3374 {
3375         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3377         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3378         struct dp_sdp sdp = {};
3379         int ret;
3380
3381         if ((crtc_state->infoframes.enable &
3382             intel_hdmi_infoframe_enable(type)) == 0)
3383                 return;
3384
3385         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3386                                  sizeof(sdp));
3387
3388         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3389                                                          sizeof(sdp));
3390
3391         if (ret)
3392                 drm_dbg_kms(&dev_priv->drm,
3393                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3394 }
3395
3396 void intel_read_dp_sdp(struct intel_encoder *encoder,
3397                        struct intel_crtc_state *crtc_state,
3398                        unsigned int type)
3399 {
3400         switch (type) {
3401         case DP_SDP_VSC:
3402                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3403                                       &crtc_state->infoframes.vsc);
3404                 break;
3405         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3406                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3407                                                          &crtc_state->infoframes.drm.drm);
3408                 break;
3409         default:
3410                 MISSING_CASE(type);
3411                 break;
3412         }
3413 }
3414
3415 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3416 {
3417         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3418         int status = 0;
3419         int test_link_rate;
3420         u8 test_lane_count, test_link_bw;
3421         /* (DP CTS 1.2)
3422          * 4.3.1.11
3423          */
3424         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3425         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3426                                    &test_lane_count);
3427
3428         if (status <= 0) {
3429                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3430                 return DP_TEST_NAK;
3431         }
3432         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3433
3434         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3435                                    &test_link_bw);
3436         if (status <= 0) {
3437                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3438                 return DP_TEST_NAK;
3439         }
3440         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3441
3442         /* Validate the requested link rate and lane count */
3443         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3444                                         test_lane_count))
3445                 return DP_TEST_NAK;
3446
3447         intel_dp->compliance.test_lane_count = test_lane_count;
3448         intel_dp->compliance.test_link_rate = test_link_rate;
3449
3450         return DP_TEST_ACK;
3451 }
3452
3453 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3454 {
3455         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3456         u8 test_pattern;
3457         u8 test_misc;
3458         __be16 h_width, v_height;
3459         int status = 0;
3460
3461         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3462         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3463                                    &test_pattern);
3464         if (status <= 0) {
3465                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3466                 return DP_TEST_NAK;
3467         }
3468         if (test_pattern != DP_COLOR_RAMP)
3469                 return DP_TEST_NAK;
3470
3471         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3472                                   &h_width, 2);
3473         if (status <= 0) {
3474                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3475                 return DP_TEST_NAK;
3476         }
3477
3478         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3479                                   &v_height, 2);
3480         if (status <= 0) {
3481                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3482                 return DP_TEST_NAK;
3483         }
3484
3485         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3486                                    &test_misc);
3487         if (status <= 0) {
3488                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3489                 return DP_TEST_NAK;
3490         }
3491         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3492                 return DP_TEST_NAK;
3493         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3494                 return DP_TEST_NAK;
3495         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3496         case DP_TEST_BIT_DEPTH_6:
3497                 intel_dp->compliance.test_data.bpc = 6;
3498                 break;
3499         case DP_TEST_BIT_DEPTH_8:
3500                 intel_dp->compliance.test_data.bpc = 8;
3501                 break;
3502         default:
3503                 return DP_TEST_NAK;
3504         }
3505
3506         intel_dp->compliance.test_data.video_pattern = test_pattern;
3507         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3508         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3509         /* Set test active flag here so userspace doesn't interrupt things */
3510         intel_dp->compliance.test_active = true;
3511
3512         return DP_TEST_ACK;
3513 }
3514
3515 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3516 {
3517         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3518         u8 test_result = DP_TEST_ACK;
3519         struct intel_connector *intel_connector = intel_dp->attached_connector;
3520         struct drm_connector *connector = &intel_connector->base;
3521
3522         if (intel_connector->detect_edid == NULL ||
3523             connector->edid_corrupt ||
3524             intel_dp->aux.i2c_defer_count > 6) {
3525                 /* Check EDID read for NACKs, DEFERs and corruption
3526                  * (DP CTS 1.2 Core r1.1)
3527                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3528                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3529                  *    4.2.2.6 : EDID corruption detected
3530                  * Use failsafe mode for all cases
3531                  */
3532                 if (intel_dp->aux.i2c_nack_count > 0 ||
3533                         intel_dp->aux.i2c_defer_count > 0)
3534                         drm_dbg_kms(&i915->drm,
3535                                     "EDID read had %d NACKs, %d DEFERs\n",
3536                                     intel_dp->aux.i2c_nack_count,
3537                                     intel_dp->aux.i2c_defer_count);
3538                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3539         } else {
3540                 struct edid *block = intel_connector->detect_edid;
3541
3542                 /* We have to write the checksum
3543                  * of the last block read
3544                  */
3545                 block += intel_connector->detect_edid->extensions;
3546
3547                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3548                                        block->checksum) <= 0)
3549                         drm_dbg_kms(&i915->drm,
3550                                     "Failed to write EDID checksum\n");
3551
3552                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3553                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3554         }
3555
3556         /* Set test active flag here so userspace doesn't interrupt things */
3557         intel_dp->compliance.test_active = true;
3558
3559         return test_result;
3560 }
3561
3562 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3563                                         const struct intel_crtc_state *crtc_state)
3564 {
3565         struct drm_i915_private *dev_priv =
3566                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3567         struct drm_dp_phy_test_params *data =
3568                         &intel_dp->compliance.test_data.phytest;
3569         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3570         enum pipe pipe = crtc->pipe;
3571         u32 pattern_val;
3572
3573         switch (data->phy_pattern) {
3574         case DP_PHY_TEST_PATTERN_NONE:
3575                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3576                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3577                 break;
3578         case DP_PHY_TEST_PATTERN_D10_2:
3579                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3580                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3581                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3582                 break;
3583         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3584                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3585                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3586                                DDI_DP_COMP_CTL_ENABLE |
3587                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3588                 break;
3589         case DP_PHY_TEST_PATTERN_PRBS7:
3590                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3591                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3592                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3593                 break;
3594         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3595                 /*
3596                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3597                  * current firmware of DPR-100 could not set it, so hardcoding
3598                  * now for complaince test.
3599                  */
3600                 drm_dbg_kms(&dev_priv->drm,
3601                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3602                 pattern_val = 0x3e0f83e0;
3603                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3604                 pattern_val = 0x0f83e0f8;
3605                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3606                 pattern_val = 0x0000f83e;
3607                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3608                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3609                                DDI_DP_COMP_CTL_ENABLE |
3610                                DDI_DP_COMP_CTL_CUSTOM80);
3611                 break;
3612         case DP_PHY_TEST_PATTERN_CP2520:
3613                 /*
3614                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3615                  * current firmware of DPR-100 could not set it, so hardcoding
3616                  * now for complaince test.
3617                  */
3618                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3619                 pattern_val = 0xFB;
3620                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3621                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3622                                pattern_val);
3623                 break;
3624         default:
3625                 WARN(1, "Invalid Phy Test Pattern\n");
3626         }
3627 }
3628
3629 static void
3630 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3631                                   const struct intel_crtc_state *crtc_state)
3632 {
3633         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3634         struct drm_device *dev = dig_port->base.base.dev;
3635         struct drm_i915_private *dev_priv = to_i915(dev);
3636         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3637         enum pipe pipe = crtc->pipe;
3638         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3639
3640         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3641                                                  TRANS_DDI_FUNC_CTL(pipe));
3642         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3643         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3644
3645         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3646                                       TGL_TRANS_DDI_PORT_MASK);
3647         trans_conf_value &= ~PIPECONF_ENABLE;
3648         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3649
3650         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3651         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3652                        trans_ddi_func_ctl_value);
3653         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3654 }
3655
3656 static void
3657 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3658                                  const struct intel_crtc_state *crtc_state)
3659 {
3660         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3661         struct drm_device *dev = dig_port->base.base.dev;
3662         struct drm_i915_private *dev_priv = to_i915(dev);
3663         enum port port = dig_port->base.port;
3664         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3665         enum pipe pipe = crtc->pipe;
3666         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3667
3668         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3669                                                  TRANS_DDI_FUNC_CTL(pipe));
3670         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3671         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3672
3673         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3674                                     TGL_TRANS_DDI_SELECT_PORT(port);
3675         trans_conf_value |= PIPECONF_ENABLE;
3676         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3677
3678         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3679         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3680         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3681                        trans_ddi_func_ctl_value);
3682 }
3683
3684 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3685                                          const struct intel_crtc_state *crtc_state)
3686 {
3687         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3688         struct drm_dp_phy_test_params *data =
3689                 &intel_dp->compliance.test_data.phytest;
3690         u8 link_status[DP_LINK_STATUS_SIZE];
3691
3692         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3693                                              link_status) < 0) {
3694                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3695                 return;
3696         }
3697
3698         /* retrieve vswing & pre-emphasis setting */
3699         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3700                                   link_status);
3701
3702         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3703
3704         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3705
3706         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3707
3708         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3709
3710         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3711                           intel_dp->train_set, crtc_state->lane_count);
3712
3713         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3714                                     link_status[DP_DPCD_REV]);
3715 }
3716
3717 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3718 {
3719         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3720         struct drm_dp_phy_test_params *data =
3721                 &intel_dp->compliance.test_data.phytest;
3722
3723         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3724                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3725                 return DP_TEST_NAK;
3726         }
3727
3728         /* Set test active flag here so userspace doesn't interrupt things */
3729         intel_dp->compliance.test_active = true;
3730
3731         return DP_TEST_ACK;
3732 }
3733
3734 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3735 {
3736         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3737         u8 response = DP_TEST_NAK;
3738         u8 request = 0;
3739         int status;
3740
3741         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3742         if (status <= 0) {
3743                 drm_dbg_kms(&i915->drm,
3744                             "Could not read test request from sink\n");
3745                 goto update_status;
3746         }
3747
3748         switch (request) {
3749         case DP_TEST_LINK_TRAINING:
3750                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3751                 response = intel_dp_autotest_link_training(intel_dp);
3752                 break;
3753         case DP_TEST_LINK_VIDEO_PATTERN:
3754                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3755                 response = intel_dp_autotest_video_pattern(intel_dp);
3756                 break;
3757         case DP_TEST_LINK_EDID_READ:
3758                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3759                 response = intel_dp_autotest_edid(intel_dp);
3760                 break;
3761         case DP_TEST_LINK_PHY_TEST_PATTERN:
3762                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3763                 response = intel_dp_autotest_phy_pattern(intel_dp);
3764                 break;
3765         default:
3766                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3767                             request);
3768                 break;
3769         }
3770
3771         if (response & DP_TEST_ACK)
3772                 intel_dp->compliance.test_type = request;
3773
3774 update_status:
3775         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3776         if (status <= 0)
3777                 drm_dbg_kms(&i915->drm,
3778                             "Could not write test response to sink\n");
3779 }
3780
3781 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3782                              u8 link_status[DP_LINK_STATUS_SIZE])
3783 {
3784         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3785         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3786         bool uhbr = intel_dp->link_rate >= 1000000;
3787         bool ok;
3788
3789         if (uhbr)
3790                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3791                                                           intel_dp->lane_count);
3792         else
3793                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3794
3795         if (ok)
3796                 return true;
3797
3798         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3799         drm_dbg_kms(&i915->drm,
3800                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
3801                     encoder->base.base.id, encoder->base.name,
3802                     uhbr ? "128b/132b" : "8b/10b");
3803
3804         return false;
3805 }
3806
3807 static void
3808 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3809 {
3810         bool handled = false;
3811
3812         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3813         if (handled)
3814                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3815
3816         if (esi[1] & DP_CP_IRQ) {
3817                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3818                 ack[1] |= DP_CP_IRQ;
3819         }
3820 }
3821
3822 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3823 {
3824         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3825         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3826         u8 link_status[DP_LINK_STATUS_SIZE] = {};
3827         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3828
3829         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3830                              esi_link_status_size) != esi_link_status_size) {
3831                 drm_err(&i915->drm,
3832                         "[ENCODER:%d:%s] Failed to read link status\n",
3833                         encoder->base.base.id, encoder->base.name);
3834                 return false;
3835         }
3836
3837         return intel_dp_link_ok(intel_dp, link_status);
3838 }
3839
3840 /**
3841  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3842  * @intel_dp: Intel DP struct
3843  *
3844  * Read any pending MST interrupts, call MST core to handle these and ack the
3845  * interrupts. Check if the main and AUX link state is ok.
3846  *
3847  * Returns:
3848  * - %true if pending interrupts were serviced (or no interrupts were
3849  *   pending) w/o detecting an error condition.
3850  * - %false if an error condition - like AUX failure or a loss of link - is
3851  *   detected, which needs servicing from the hotplug work.
3852  */
3853 static bool
3854 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3855 {
3856         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3857         bool link_ok = true;
3858
3859         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3860
3861         for (;;) {
3862                 u8 esi[4] = {};
3863                 u8 ack[4] = {};
3864
3865                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3866                         drm_dbg_kms(&i915->drm,
3867                                     "failed to get ESI - device may have failed\n");
3868                         link_ok = false;
3869
3870                         break;
3871                 }
3872
3873                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3874
3875                 if (intel_dp->active_mst_links > 0 && link_ok &&
3876                     esi[3] & LINK_STATUS_CHANGED) {
3877                         if (!intel_dp_mst_link_status(intel_dp))
3878                                 link_ok = false;
3879                         ack[3] |= LINK_STATUS_CHANGED;
3880                 }
3881
3882                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3883
3884                 if (!memchr_inv(ack, 0, sizeof(ack)))
3885                         break;
3886
3887                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3888                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3889         }
3890
3891         return link_ok;
3892 }
3893
3894 static void
3895 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3896 {
3897         bool is_active;
3898         u8 buf = 0;
3899
3900         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3901         if (intel_dp->frl.is_trained && !is_active) {
3902                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3903                         return;
3904
3905                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3906                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3907                         return;
3908
3909                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3910
3911                 /* Restart FRL training or fall back to TMDS mode */
3912                 intel_dp_check_frl_training(intel_dp);
3913         }
3914 }
3915
3916 static bool
3917 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3918 {
3919         u8 link_status[DP_LINK_STATUS_SIZE];
3920
3921         if (!intel_dp->link_trained)
3922                 return false;
3923
3924         /*
3925          * While PSR source HW is enabled, it will control main-link sending
3926          * frames, enabling and disabling it so trying to do a retrain will fail
3927          * as the link would or not be on or it could mix training patterns
3928          * and frame data at the same time causing retrain to fail.
3929          * Also when exiting PSR, HW will retrain the link anyways fixing
3930          * any link status error.
3931          */
3932         if (intel_psr_enabled(intel_dp))
3933                 return false;
3934
3935         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3936                                              link_status) < 0)
3937                 return false;
3938
3939         /*
3940          * Validate the cached values of intel_dp->link_rate and
3941          * intel_dp->lane_count before attempting to retrain.
3942          *
3943          * FIXME would be nice to user the crtc state here, but since
3944          * we need to call this from the short HPD handler that seems
3945          * a bit hard.
3946          */
3947         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3948                                         intel_dp->lane_count))
3949                 return false;
3950
3951         /* Retrain if link not ok */
3952         return !intel_dp_link_ok(intel_dp, link_status);
3953 }
3954
3955 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3956                                    const struct drm_connector_state *conn_state)
3957 {
3958         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3959         struct intel_encoder *encoder;
3960         enum pipe pipe;
3961
3962         if (!conn_state->best_encoder)
3963                 return false;
3964
3965         /* SST */
3966         encoder = &dp_to_dig_port(intel_dp)->base;
3967         if (conn_state->best_encoder == &encoder->base)
3968                 return true;
3969
3970         /* MST */
3971         for_each_pipe(i915, pipe) {
3972                 encoder = &intel_dp->mst_encoders[pipe]->base;
3973                 if (conn_state->best_encoder == &encoder->base)
3974                         return true;
3975         }
3976
3977         return false;
3978 }
3979
3980 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3981                                       struct drm_modeset_acquire_ctx *ctx,
3982                                       u8 *pipe_mask)
3983 {
3984         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3985         struct drm_connector_list_iter conn_iter;
3986         struct intel_connector *connector;
3987         int ret = 0;
3988
3989         *pipe_mask = 0;
3990
3991         if (!intel_dp_needs_link_retrain(intel_dp))
3992                 return 0;
3993
3994         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3995         for_each_intel_connector_iter(connector, &conn_iter) {
3996                 struct drm_connector_state *conn_state =
3997                         connector->base.state;
3998                 struct intel_crtc_state *crtc_state;
3999                 struct intel_crtc *crtc;
4000
4001                 if (!intel_dp_has_connector(intel_dp, conn_state))
4002                         continue;
4003
4004                 crtc = to_intel_crtc(conn_state->crtc);
4005                 if (!crtc)
4006                         continue;
4007
4008                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4009                 if (ret)
4010                         break;
4011
4012                 crtc_state = to_intel_crtc_state(crtc->base.state);
4013
4014                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4015
4016                 if (!crtc_state->hw.active)
4017                         continue;
4018
4019                 if (conn_state->commit &&
4020                     !try_wait_for_completion(&conn_state->commit->hw_done))
4021                         continue;
4022
4023                 *pipe_mask |= BIT(crtc->pipe);
4024         }
4025         drm_connector_list_iter_end(&conn_iter);
4026
4027         if (!intel_dp_needs_link_retrain(intel_dp))
4028                 *pipe_mask = 0;
4029
4030         return ret;
4031 }
4032
4033 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4034 {
4035         struct intel_connector *connector = intel_dp->attached_connector;
4036
4037         return connector->base.status == connector_status_connected ||
4038                 intel_dp->is_mst;
4039 }
4040
4041 int intel_dp_retrain_link(struct intel_encoder *encoder,
4042                           struct drm_modeset_acquire_ctx *ctx)
4043 {
4044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4045         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4046         struct intel_crtc *crtc;
4047         u8 pipe_mask;
4048         int ret;
4049
4050         if (!intel_dp_is_connected(intel_dp))
4051                 return 0;
4052
4053         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4054                                ctx);
4055         if (ret)
4056                 return ret;
4057
4058         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4059         if (ret)
4060                 return ret;
4061
4062         if (pipe_mask == 0)
4063                 return 0;
4064
4065         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4066                     encoder->base.base.id, encoder->base.name);
4067
4068         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4069                 const struct intel_crtc_state *crtc_state =
4070                         to_intel_crtc_state(crtc->base.state);
4071
4072                 /* Suppress underruns caused by re-training */
4073                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4074                 if (crtc_state->has_pch_encoder)
4075                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4076                                                               intel_crtc_pch_transcoder(crtc), false);
4077         }
4078
4079         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4080                 const struct intel_crtc_state *crtc_state =
4081                         to_intel_crtc_state(crtc->base.state);
4082
4083                 /* retrain on the MST master transcoder */
4084                 if (DISPLAY_VER(dev_priv) >= 12 &&
4085                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4086                     !intel_dp_mst_is_master_trans(crtc_state))
4087                         continue;
4088
4089                 intel_dp_check_frl_training(intel_dp);
4090                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4091                 intel_dp_start_link_train(intel_dp, crtc_state);
4092                 intel_dp_stop_link_train(intel_dp, crtc_state);
4093                 break;
4094         }
4095
4096         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4097                 const struct intel_crtc_state *crtc_state =
4098                         to_intel_crtc_state(crtc->base.state);
4099
4100                 /* Keep underrun reporting disabled until things are stable */
4101                 intel_crtc_wait_for_next_vblank(crtc);
4102
4103                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4104                 if (crtc_state->has_pch_encoder)
4105                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4106                                                               intel_crtc_pch_transcoder(crtc), true);
4107         }
4108
4109         return 0;
4110 }
4111
4112 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4113                                   struct drm_modeset_acquire_ctx *ctx,
4114                                   u8 *pipe_mask)
4115 {
4116         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4117         struct drm_connector_list_iter conn_iter;
4118         struct intel_connector *connector;
4119         int ret = 0;
4120
4121         *pipe_mask = 0;
4122
4123         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4124         for_each_intel_connector_iter(connector, &conn_iter) {
4125                 struct drm_connector_state *conn_state =
4126                         connector->base.state;
4127                 struct intel_crtc_state *crtc_state;
4128                 struct intel_crtc *crtc;
4129
4130                 if (!intel_dp_has_connector(intel_dp, conn_state))
4131                         continue;
4132
4133                 crtc = to_intel_crtc(conn_state->crtc);
4134                 if (!crtc)
4135                         continue;
4136
4137                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4138                 if (ret)
4139                         break;
4140
4141                 crtc_state = to_intel_crtc_state(crtc->base.state);
4142
4143                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4144
4145                 if (!crtc_state->hw.active)
4146                         continue;
4147
4148                 if (conn_state->commit &&
4149                     !try_wait_for_completion(&conn_state->commit->hw_done))
4150                         continue;
4151
4152                 *pipe_mask |= BIT(crtc->pipe);
4153         }
4154         drm_connector_list_iter_end(&conn_iter);
4155
4156         return ret;
4157 }
4158
4159 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4160                                 struct drm_modeset_acquire_ctx *ctx)
4161 {
4162         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4163         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4164         struct intel_crtc *crtc;
4165         u8 pipe_mask;
4166         int ret;
4167
4168         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4169                                ctx);
4170         if (ret)
4171                 return ret;
4172
4173         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4174         if (ret)
4175                 return ret;
4176
4177         if (pipe_mask == 0)
4178                 return 0;
4179
4180         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4181                     encoder->base.base.id, encoder->base.name);
4182
4183         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4184                 const struct intel_crtc_state *crtc_state =
4185                         to_intel_crtc_state(crtc->base.state);
4186
4187                 /* test on the MST master transcoder */
4188                 if (DISPLAY_VER(dev_priv) >= 12 &&
4189                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4190                     !intel_dp_mst_is_master_trans(crtc_state))
4191                         continue;
4192
4193                 intel_dp_process_phy_request(intel_dp, crtc_state);
4194                 break;
4195         }
4196
4197         return 0;
4198 }
4199
4200 void intel_dp_phy_test(struct intel_encoder *encoder)
4201 {
4202         struct drm_modeset_acquire_ctx ctx;
4203         int ret;
4204
4205         drm_modeset_acquire_init(&ctx, 0);
4206
4207         for (;;) {
4208                 ret = intel_dp_do_phy_test(encoder, &ctx);
4209
4210                 if (ret == -EDEADLK) {
4211                         drm_modeset_backoff(&ctx);
4212                         continue;
4213                 }
4214
4215                 break;
4216         }
4217
4218         drm_modeset_drop_locks(&ctx);
4219         drm_modeset_acquire_fini(&ctx);
4220         drm_WARN(encoder->base.dev, ret,
4221                  "Acquiring modeset locks failed with %i\n", ret);
4222 }
4223
4224 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4225 {
4226         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4227         u8 val;
4228
4229         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4230                 return;
4231
4232         if (drm_dp_dpcd_readb(&intel_dp->aux,
4233                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4234                 return;
4235
4236         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4237
4238         if (val & DP_AUTOMATED_TEST_REQUEST)
4239                 intel_dp_handle_test_request(intel_dp);
4240
4241         if (val & DP_CP_IRQ)
4242                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4243
4244         if (val & DP_SINK_SPECIFIC_IRQ)
4245                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4246 }
4247
4248 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4249 {
4250         u8 val;
4251
4252         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4253                 return;
4254
4255         if (drm_dp_dpcd_readb(&intel_dp->aux,
4256                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4257                 return;
4258
4259         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4260                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4261                 return;
4262
4263         if (val & HDMI_LINK_STATUS_CHANGED)
4264                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4265 }
4266
4267 /*
4268  * According to DP spec
4269  * 5.1.2:
4270  *  1. Read DPCD
4271  *  2. Configure link according to Receiver Capabilities
4272  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4273  *  4. Check link status on receipt of hot-plug interrupt
4274  *
4275  * intel_dp_short_pulse -  handles short pulse interrupts
4276  * when full detection is not required.
4277  * Returns %true if short pulse is handled and full detection
4278  * is NOT required and %false otherwise.
4279  */
4280 static bool
4281 intel_dp_short_pulse(struct intel_dp *intel_dp)
4282 {
4283         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4284         u8 old_sink_count = intel_dp->sink_count;
4285         bool ret;
4286
4287         /*
4288          * Clearing compliance test variables to allow capturing
4289          * of values for next automated test request.
4290          */
4291         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4292
4293         /*
4294          * Now read the DPCD to see if it's actually running
4295          * If the current value of sink count doesn't match with
4296          * the value that was stored earlier or dpcd read failed
4297          * we need to do full detection
4298          */
4299         ret = intel_dp_get_dpcd(intel_dp);
4300
4301         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4302                 /* No need to proceed if we are going to do full detect */
4303                 return false;
4304         }
4305
4306         intel_dp_check_device_service_irq(intel_dp);
4307         intel_dp_check_link_service_irq(intel_dp);
4308
4309         /* Handle CEC interrupts, if any */
4310         drm_dp_cec_irq(&intel_dp->aux);
4311
4312         /* defer to the hotplug work for link retraining if needed */
4313         if (intel_dp_needs_link_retrain(intel_dp))
4314                 return false;
4315
4316         intel_psr_short_pulse(intel_dp);
4317
4318         switch (intel_dp->compliance.test_type) {
4319         case DP_TEST_LINK_TRAINING:
4320                 drm_dbg_kms(&dev_priv->drm,
4321                             "Link Training Compliance Test requested\n");
4322                 /* Send a Hotplug Uevent to userspace to start modeset */
4323                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4324                 break;
4325         case DP_TEST_LINK_PHY_TEST_PATTERN:
4326                 drm_dbg_kms(&dev_priv->drm,
4327                             "PHY test pattern Compliance Test requested\n");
4328                 /*
4329                  * Schedule long hpd to do the test
4330                  *
4331                  * FIXME get rid of the ad-hoc phy test modeset code
4332                  * and properly incorporate it into the normal modeset.
4333                  */
4334                 return false;
4335         }
4336
4337         return true;
4338 }
4339
4340 /* XXX this is probably wrong for multiple downstream ports */
4341 static enum drm_connector_status
4342 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4343 {
4344         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4345         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4346         u8 *dpcd = intel_dp->dpcd;
4347         u8 type;
4348
4349         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4350                 return connector_status_connected;
4351
4352         lspcon_resume(dig_port);
4353
4354         if (!intel_dp_get_dpcd(intel_dp))
4355                 return connector_status_disconnected;
4356
4357         /* if there's no downstream port, we're done */
4358         if (!drm_dp_is_branch(dpcd))
4359                 return connector_status_connected;
4360
4361         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4362         if (intel_dp_has_sink_count(intel_dp) &&
4363             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4364                 return intel_dp->sink_count ?
4365                 connector_status_connected : connector_status_disconnected;
4366         }
4367
4368         if (intel_dp_can_mst(intel_dp))
4369                 return connector_status_connected;
4370
4371         /* If no HPD, poke DDC gently */
4372         if (drm_probe_ddc(&intel_dp->aux.ddc))
4373                 return connector_status_connected;
4374
4375         /* Well we tried, say unknown for unreliable port types */
4376         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4377                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4378                 if (type == DP_DS_PORT_TYPE_VGA ||
4379                     type == DP_DS_PORT_TYPE_NON_EDID)
4380                         return connector_status_unknown;
4381         } else {
4382                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4383                         DP_DWN_STRM_PORT_TYPE_MASK;
4384                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4385                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4386                         return connector_status_unknown;
4387         }
4388
4389         /* Anything else is out of spec, warn and ignore */
4390         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4391         return connector_status_disconnected;
4392 }
4393
4394 static enum drm_connector_status
4395 edp_detect(struct intel_dp *intel_dp)
4396 {
4397         return connector_status_connected;
4398 }
4399
4400 /*
4401  * intel_digital_port_connected - is the specified port connected?
4402  * @encoder: intel_encoder
4403  *
4404  * In cases where there's a connector physically connected but it can't be used
4405  * by our hardware we also return false, since the rest of the driver should
4406  * pretty much treat the port as disconnected. This is relevant for type-C
4407  * (starting on ICL) where there's ownership involved.
4408  *
4409  * Return %true if port is connected, %false otherwise.
4410  */
4411 bool intel_digital_port_connected(struct intel_encoder *encoder)
4412 {
4413         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4414         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4415         bool is_connected = false;
4416         intel_wakeref_t wakeref;
4417
4418         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4419                 is_connected = dig_port->connected(encoder);
4420
4421         return is_connected;
4422 }
4423
4424 static struct edid *
4425 intel_dp_get_edid(struct intel_dp *intel_dp)
4426 {
4427         struct intel_connector *intel_connector = intel_dp->attached_connector;
4428
4429         /* use cached edid if we have one */
4430         if (intel_connector->edid) {
4431                 /* invalid edid */
4432                 if (IS_ERR(intel_connector->edid))
4433                         return NULL;
4434
4435                 return drm_edid_duplicate(intel_connector->edid);
4436         } else
4437                 return drm_get_edid(&intel_connector->base,
4438                                     &intel_dp->aux.ddc);
4439 }
4440
4441 static void
4442 intel_dp_update_dfp(struct intel_dp *intel_dp,
4443                     const struct edid *edid)
4444 {
4445         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4446         struct intel_connector *connector = intel_dp->attached_connector;
4447
4448         intel_dp->dfp.max_bpc =
4449                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4450                                           intel_dp->downstream_ports, edid);
4451
4452         intel_dp->dfp.max_dotclock =
4453                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4454                                                intel_dp->downstream_ports);
4455
4456         intel_dp->dfp.min_tmds_clock =
4457                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4458                                                  intel_dp->downstream_ports,
4459                                                  edid);
4460         intel_dp->dfp.max_tmds_clock =
4461                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4462                                                  intel_dp->downstream_ports,
4463                                                  edid);
4464
4465         intel_dp->dfp.pcon_max_frl_bw =
4466                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4467                                            intel_dp->downstream_ports);
4468
4469         drm_dbg_kms(&i915->drm,
4470                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4471                     connector->base.base.id, connector->base.name,
4472                     intel_dp->dfp.max_bpc,
4473                     intel_dp->dfp.max_dotclock,
4474                     intel_dp->dfp.min_tmds_clock,
4475                     intel_dp->dfp.max_tmds_clock,
4476                     intel_dp->dfp.pcon_max_frl_bw);
4477
4478         intel_dp_get_pcon_dsc_cap(intel_dp);
4479 }
4480
4481 static void
4482 intel_dp_update_420(struct intel_dp *intel_dp)
4483 {
4484         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4485         struct intel_connector *connector = intel_dp->attached_connector;
4486         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4487
4488         /* No YCbCr output support on gmch platforms */
4489         if (HAS_GMCH(i915))
4490                 return;
4491
4492         /*
4493          * ILK doesn't seem capable of DP YCbCr output. The
4494          * displayed image is severly corrupted. SNB+ is fine.
4495          */
4496         if (IS_IRONLAKE(i915))
4497                 return;
4498
4499         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4500         ycbcr_420_passthrough =
4501                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4502                                                   intel_dp->downstream_ports);
4503         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4504         ycbcr_444_to_420 =
4505                 dp_to_dig_port(intel_dp)->lspcon.active ||
4506                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4507                                                         intel_dp->downstream_ports);
4508         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4509                                                                  intel_dp->downstream_ports,
4510                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4511
4512         if (DISPLAY_VER(i915) >= 11) {
4513                 /* Let PCON convert from RGB->YCbCr if possible */
4514                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4515                         intel_dp->dfp.rgb_to_ycbcr = true;
4516                         intel_dp->dfp.ycbcr_444_to_420 = true;
4517                         connector->base.ycbcr_420_allowed = true;
4518                 } else {
4519                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4520                         intel_dp->dfp.ycbcr_444_to_420 =
4521                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4522
4523                         connector->base.ycbcr_420_allowed =
4524                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4525                 }
4526         } else {
4527                 /* 4:4:4->4:2:0 conversion is the only way */
4528                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4529
4530                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4531         }
4532
4533         drm_dbg_kms(&i915->drm,
4534                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4535                     connector->base.base.id, connector->base.name,
4536                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4537                     str_yes_no(connector->base.ycbcr_420_allowed),
4538                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4539 }
4540
4541 static void
4542 intel_dp_set_edid(struct intel_dp *intel_dp)
4543 {
4544         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4545         struct intel_connector *connector = intel_dp->attached_connector;
4546         struct edid *edid;
4547         bool vrr_capable;
4548
4549         intel_dp_unset_edid(intel_dp);
4550         edid = intel_dp_get_edid(intel_dp);
4551         connector->detect_edid = edid;
4552
4553         vrr_capable = intel_vrr_is_capable(&connector->base);
4554         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4555                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4556         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4557
4558         intel_dp_update_dfp(intel_dp, edid);
4559         intel_dp_update_420(intel_dp);
4560
4561         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4562                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4563                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4564         }
4565
4566         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4567 }
4568
4569 static void
4570 intel_dp_unset_edid(struct intel_dp *intel_dp)
4571 {
4572         struct intel_connector *connector = intel_dp->attached_connector;
4573
4574         drm_dp_cec_unset_edid(&intel_dp->aux);
4575         kfree(connector->detect_edid);
4576         connector->detect_edid = NULL;
4577
4578         intel_dp->has_hdmi_sink = false;
4579         intel_dp->has_audio = false;
4580
4581         intel_dp->dfp.max_bpc = 0;
4582         intel_dp->dfp.max_dotclock = 0;
4583         intel_dp->dfp.min_tmds_clock = 0;
4584         intel_dp->dfp.max_tmds_clock = 0;
4585
4586         intel_dp->dfp.pcon_max_frl_bw = 0;
4587
4588         intel_dp->dfp.ycbcr_444_to_420 = false;
4589         connector->base.ycbcr_420_allowed = false;
4590
4591         drm_connector_set_vrr_capable_property(&connector->base,
4592                                                false);
4593 }
4594
4595 static int
4596 intel_dp_detect(struct drm_connector *connector,
4597                 struct drm_modeset_acquire_ctx *ctx,
4598                 bool force)
4599 {
4600         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4601         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4602         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4603         struct intel_encoder *encoder = &dig_port->base;
4604         enum drm_connector_status status;
4605
4606         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4607                     connector->base.id, connector->name);
4608         drm_WARN_ON(&dev_priv->drm,
4609                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4610
4611         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4612                 return connector_status_disconnected;
4613
4614         /* Can't disconnect eDP */
4615         if (intel_dp_is_edp(intel_dp))
4616                 status = edp_detect(intel_dp);
4617         else if (intel_digital_port_connected(encoder))
4618                 status = intel_dp_detect_dpcd(intel_dp);
4619         else
4620                 status = connector_status_disconnected;
4621
4622         if (status == connector_status_disconnected) {
4623                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4624                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4625
4626                 if (intel_dp->is_mst) {
4627                         drm_dbg_kms(&dev_priv->drm,
4628                                     "MST device may have disappeared %d vs %d\n",
4629                                     intel_dp->is_mst,
4630                                     intel_dp->mst_mgr.mst_state);
4631                         intel_dp->is_mst = false;
4632                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4633                                                         intel_dp->is_mst);
4634                 }
4635
4636                 goto out;
4637         }
4638
4639         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4640         if (DISPLAY_VER(dev_priv) >= 11)
4641                 intel_dp_get_dsc_sink_cap(intel_dp);
4642
4643         intel_dp_configure_mst(intel_dp);
4644
4645         /*
4646          * TODO: Reset link params when switching to MST mode, until MST
4647          * supports link training fallback params.
4648          */
4649         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4650                 intel_dp_reset_max_link_params(intel_dp);
4651                 intel_dp->reset_link_params = false;
4652         }
4653
4654         intel_dp_print_rates(intel_dp);
4655
4656         if (intel_dp->is_mst) {
4657                 /*
4658                  * If we are in MST mode then this connector
4659                  * won't appear connected or have anything
4660                  * with EDID on it
4661                  */
4662                 status = connector_status_disconnected;
4663                 goto out;
4664         }
4665
4666         /*
4667          * Some external monitors do not signal loss of link synchronization
4668          * with an IRQ_HPD, so force a link status check.
4669          */
4670         if (!intel_dp_is_edp(intel_dp)) {
4671                 int ret;
4672
4673                 ret = intel_dp_retrain_link(encoder, ctx);
4674                 if (ret)
4675                         return ret;
4676         }
4677
4678         /*
4679          * Clearing NACK and defer counts to get their exact values
4680          * while reading EDID which are required by Compliance tests
4681          * 4.2.2.4 and 4.2.2.5
4682          */
4683         intel_dp->aux.i2c_nack_count = 0;
4684         intel_dp->aux.i2c_defer_count = 0;
4685
4686         intel_dp_set_edid(intel_dp);
4687         if (intel_dp_is_edp(intel_dp) ||
4688             to_intel_connector(connector)->detect_edid)
4689                 status = connector_status_connected;
4690
4691         intel_dp_check_device_service_irq(intel_dp);
4692
4693 out:
4694         if (status != connector_status_connected && !intel_dp->is_mst)
4695                 intel_dp_unset_edid(intel_dp);
4696
4697         /*
4698          * Make sure the refs for power wells enabled during detect are
4699          * dropped to avoid a new detect cycle triggered by HPD polling.
4700          */
4701         intel_display_power_flush_work(dev_priv);
4702
4703         if (!intel_dp_is_edp(intel_dp))
4704                 drm_dp_set_subconnector_property(connector,
4705                                                  status,
4706                                                  intel_dp->dpcd,
4707                                                  intel_dp->downstream_ports);
4708         return status;
4709 }
4710
4711 static void
4712 intel_dp_force(struct drm_connector *connector)
4713 {
4714         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4715         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4716         struct intel_encoder *intel_encoder = &dig_port->base;
4717         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4718         enum intel_display_power_domain aux_domain =
4719                 intel_aux_power_domain(dig_port);
4720         intel_wakeref_t wakeref;
4721
4722         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4723                     connector->base.id, connector->name);
4724         intel_dp_unset_edid(intel_dp);
4725
4726         if (connector->status != connector_status_connected)
4727                 return;
4728
4729         wakeref = intel_display_power_get(dev_priv, aux_domain);
4730
4731         intel_dp_set_edid(intel_dp);
4732
4733         intel_display_power_put(dev_priv, aux_domain, wakeref);
4734 }
4735
4736 static int intel_dp_get_modes(struct drm_connector *connector)
4737 {
4738         struct intel_connector *intel_connector = to_intel_connector(connector);
4739         struct edid *edid;
4740         int num_modes = 0;
4741
4742         edid = intel_connector->detect_edid;
4743         if (edid)
4744                 num_modes = intel_connector_update_modes(connector, edid);
4745
4746         /* Also add fixed mode, which may or may not be present in EDID */
4747         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4748                 num_modes += intel_panel_get_modes(intel_connector);
4749
4750         if (num_modes)
4751                 return num_modes;
4752
4753         if (!edid) {
4754                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4755                 struct drm_display_mode *mode;
4756
4757                 mode = drm_dp_downstream_mode(connector->dev,
4758                                               intel_dp->dpcd,
4759                                               intel_dp->downstream_ports);
4760                 if (mode) {
4761                         drm_mode_probed_add(connector, mode);
4762                         num_modes++;
4763                 }
4764         }
4765
4766         return num_modes;
4767 }
4768
4769 static int
4770 intel_dp_connector_register(struct drm_connector *connector)
4771 {
4772         struct drm_i915_private *i915 = to_i915(connector->dev);
4773         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4774         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4775         struct intel_lspcon *lspcon = &dig_port->lspcon;
4776         int ret;
4777
4778         ret = intel_connector_register(connector);
4779         if (ret)
4780                 return ret;
4781
4782         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4783                     intel_dp->aux.name, connector->kdev->kobj.name);
4784
4785         intel_dp->aux.dev = connector->kdev;
4786         ret = drm_dp_aux_register(&intel_dp->aux);
4787         if (!ret)
4788                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4789
4790         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4791                 return ret;
4792
4793         /*
4794          * ToDo: Clean this up to handle lspcon init and resume more
4795          * efficiently and streamlined.
4796          */
4797         if (lspcon_init(dig_port)) {
4798                 lspcon_detect_hdr_capability(lspcon);
4799                 if (lspcon->hdr_supported)
4800                         drm_connector_attach_hdr_output_metadata_property(connector);
4801         }
4802
4803         return ret;
4804 }
4805
4806 static void
4807 intel_dp_connector_unregister(struct drm_connector *connector)
4808 {
4809         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4810
4811         drm_dp_cec_unregister_connector(&intel_dp->aux);
4812         drm_dp_aux_unregister(&intel_dp->aux);
4813         intel_connector_unregister(connector);
4814 }
4815
4816 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4817 {
4818         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4819         struct intel_dp *intel_dp = &dig_port->dp;
4820
4821         intel_dp_mst_encoder_cleanup(dig_port);
4822
4823         intel_pps_vdd_off_sync(intel_dp);
4824
4825         intel_dp_aux_fini(intel_dp);
4826 }
4827
4828 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4829 {
4830         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4831
4832         intel_pps_vdd_off_sync(intel_dp);
4833 }
4834
4835 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4836 {
4837         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4838
4839         intel_pps_wait_power_cycle(intel_dp);
4840 }
4841
4842 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4843                                     int tile_group_id)
4844 {
4845         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4846         struct drm_connector_list_iter conn_iter;
4847         struct drm_connector *connector;
4848         int ret = 0;
4849
4850         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4851         drm_for_each_connector_iter(connector, &conn_iter) {
4852                 struct drm_connector_state *conn_state;
4853                 struct intel_crtc_state *crtc_state;
4854                 struct intel_crtc *crtc;
4855
4856                 if (!connector->has_tile ||
4857                     connector->tile_group->id != tile_group_id)
4858                         continue;
4859
4860                 conn_state = drm_atomic_get_connector_state(&state->base,
4861                                                             connector);
4862                 if (IS_ERR(conn_state)) {
4863                         ret = PTR_ERR(conn_state);
4864                         break;
4865                 }
4866
4867                 crtc = to_intel_crtc(conn_state->crtc);
4868
4869                 if (!crtc)
4870                         continue;
4871
4872                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4873                 crtc_state->uapi.mode_changed = true;
4874
4875                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4876                 if (ret)
4877                         break;
4878         }
4879         drm_connector_list_iter_end(&conn_iter);
4880
4881         return ret;
4882 }
4883
4884 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4885 {
4886         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4887         struct intel_crtc *crtc;
4888
4889         if (transcoders == 0)
4890                 return 0;
4891
4892         for_each_intel_crtc(&dev_priv->drm, crtc) {
4893                 struct intel_crtc_state *crtc_state;
4894                 int ret;
4895
4896                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4897                 if (IS_ERR(crtc_state))
4898                         return PTR_ERR(crtc_state);
4899
4900                 if (!crtc_state->hw.enable)
4901                         continue;
4902
4903                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4904                         continue;
4905
4906                 crtc_state->uapi.mode_changed = true;
4907
4908                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4909                 if (ret)
4910                         return ret;
4911
4912                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4913                 if (ret)
4914                         return ret;
4915
4916                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4917         }
4918
4919         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4920
4921         return 0;
4922 }
4923
4924 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4925                                       struct drm_connector *connector)
4926 {
4927         const struct drm_connector_state *old_conn_state =
4928                 drm_atomic_get_old_connector_state(&state->base, connector);
4929         const struct intel_crtc_state *old_crtc_state;
4930         struct intel_crtc *crtc;
4931         u8 transcoders;
4932
4933         crtc = to_intel_crtc(old_conn_state->crtc);
4934         if (!crtc)
4935                 return 0;
4936
4937         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4938
4939         if (!old_crtc_state->hw.active)
4940                 return 0;
4941
4942         transcoders = old_crtc_state->sync_mode_slaves_mask;
4943         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4944                 transcoders |= BIT(old_crtc_state->master_transcoder);
4945
4946         return intel_modeset_affected_transcoders(state,
4947                                                   transcoders);
4948 }
4949
4950 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4951                                            struct drm_atomic_state *_state)
4952 {
4953         struct drm_i915_private *dev_priv = to_i915(conn->dev);
4954         struct intel_atomic_state *state = to_intel_atomic_state(_state);
4955         int ret;
4956
4957         ret = intel_digital_connector_atomic_check(conn, &state->base);
4958         if (ret)
4959                 return ret;
4960
4961         /*
4962          * We don't enable port sync on BDW due to missing w/as and
4963          * due to not having adjusted the modeset sequence appropriately.
4964          */
4965         if (DISPLAY_VER(dev_priv) < 9)
4966                 return 0;
4967
4968         if (!intel_connector_needs_modeset(state, conn))
4969                 return 0;
4970
4971         if (conn->has_tile) {
4972                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4973                 if (ret)
4974                         return ret;
4975         }
4976
4977         return intel_modeset_synced_crtcs(state, conn);
4978 }
4979
4980 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
4981 {
4982         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
4983         struct drm_i915_private *i915 = to_i915(connector->dev);
4984
4985         spin_lock_irq(&i915->irq_lock);
4986         i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
4987         spin_unlock_irq(&i915->irq_lock);
4988         queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
4989 }
4990
4991 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4992         .force = intel_dp_force,
4993         .fill_modes = drm_helper_probe_single_connector_modes,
4994         .atomic_get_property = intel_digital_connector_atomic_get_property,
4995         .atomic_set_property = intel_digital_connector_atomic_set_property,
4996         .late_register = intel_dp_connector_register,
4997         .early_unregister = intel_dp_connector_unregister,
4998         .destroy = intel_connector_destroy,
4999         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5000         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5001         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5002 };
5003
5004 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5005         .detect_ctx = intel_dp_detect,
5006         .get_modes = intel_dp_get_modes,
5007         .mode_valid = intel_dp_mode_valid,
5008         .atomic_check = intel_dp_connector_atomic_check,
5009 };
5010
5011 enum irqreturn
5012 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5013 {
5014         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5015         struct intel_dp *intel_dp = &dig_port->dp;
5016
5017         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5018             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5019                 /*
5020                  * vdd off can generate a long/short pulse on eDP which
5021                  * would require vdd on to handle it, and thus we
5022                  * would end up in an endless cycle of
5023                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5024                  */
5025                 drm_dbg_kms(&i915->drm,
5026                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5027                             long_hpd ? "long" : "short",
5028                             dig_port->base.base.base.id,
5029                             dig_port->base.base.name);
5030                 return IRQ_HANDLED;
5031         }
5032
5033         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5034                     dig_port->base.base.base.id,
5035                     dig_port->base.base.name,
5036                     long_hpd ? "long" : "short");
5037
5038         if (long_hpd) {
5039                 intel_dp->reset_link_params = true;
5040                 return IRQ_NONE;
5041         }
5042
5043         if (intel_dp->is_mst) {
5044                 if (!intel_dp_check_mst_status(intel_dp))
5045                         return IRQ_NONE;
5046         } else if (!intel_dp_short_pulse(intel_dp)) {
5047                 return IRQ_NONE;
5048         }
5049
5050         return IRQ_HANDLED;
5051 }
5052
5053 /* check the VBT to see whether the eDP is on another port */
5054 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5055 {
5056         /*
5057          * eDP not supported on g4x. so bail out early just
5058          * for a bit extra safety in case the VBT is bonkers.
5059          */
5060         if (DISPLAY_VER(dev_priv) < 5)
5061                 return false;
5062
5063         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5064                 return true;
5065
5066         return intel_bios_is_port_edp(dev_priv, port);
5067 }
5068
5069 static bool
5070 has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5071 {
5072         if (intel_bios_is_lspcon_present(i915, port))
5073                 return false;
5074
5075         if (DISPLAY_VER(i915) >= 11)
5076                 return true;
5077
5078         if (port == PORT_A)
5079                 return false;
5080
5081         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5082             DISPLAY_VER(i915) >= 9)
5083                 return true;
5084
5085         return false;
5086 }
5087
5088 static void
5089 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5090 {
5091         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5092         enum port port = dp_to_dig_port(intel_dp)->base.port;
5093
5094         if (!intel_dp_is_edp(intel_dp))
5095                 drm_connector_attach_dp_subconnector_property(connector);
5096
5097         if (!IS_G4X(dev_priv) && port != PORT_A)
5098                 intel_attach_force_audio_property(connector);
5099
5100         intel_attach_broadcast_rgb_property(connector);
5101         if (HAS_GMCH(dev_priv))
5102                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5103         else if (DISPLAY_VER(dev_priv) >= 5)
5104                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5105
5106         /* Register HDMI colorspace for case of lspcon */
5107         if (intel_bios_is_lspcon_present(dev_priv, port)) {
5108                 drm_connector_attach_content_type_property(connector);
5109                 intel_attach_hdmi_colorspace_property(connector);
5110         } else {
5111                 intel_attach_dp_colorspace_property(connector);
5112         }
5113
5114         if (has_gamut_metadata_dip(dev_priv, port))
5115                 drm_connector_attach_hdr_output_metadata_property(connector);
5116
5117         if (intel_dp_is_edp(intel_dp)) {
5118                 u32 allowed_scalers;
5119
5120                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5121                 if (!HAS_GMCH(dev_priv))
5122                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5123
5124                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5125
5126                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5127
5128         }
5129
5130         if (HAS_VRR(dev_priv))
5131                 drm_connector_attach_vrr_capable_property(connector);
5132 }
5133
5134 static void
5135 intel_edp_add_properties(struct intel_dp *intel_dp)
5136 {
5137         struct intel_connector *connector = intel_dp->attached_connector;
5138         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5139         const struct drm_display_mode *fixed_mode =
5140                 intel_panel_preferred_fixed_mode(connector);
5141
5142         if (!fixed_mode)
5143                 return;
5144
5145         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5146                                                        i915->vbt.orientation,
5147                                                        fixed_mode->hdisplay,
5148                                                        fixed_mode->vdisplay);
5149 }
5150
5151 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5152                                      struct intel_connector *intel_connector)
5153 {
5154         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5155         struct drm_device *dev = &dev_priv->drm;
5156         struct drm_connector *connector = &intel_connector->base;
5157         struct drm_display_mode *fixed_mode;
5158         bool has_dpcd;
5159         enum pipe pipe = INVALID_PIPE;
5160         struct edid *edid;
5161
5162         if (!intel_dp_is_edp(intel_dp))
5163                 return true;
5164
5165         /*
5166          * On IBX/CPT we may get here with LVDS already registered. Since the
5167          * driver uses the only internal power sequencer available for both
5168          * eDP and LVDS bail out early in this case to prevent interfering
5169          * with an already powered-on LVDS power sequencer.
5170          */
5171         if (intel_get_lvds_encoder(dev_priv)) {
5172                 drm_WARN_ON(dev,
5173                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5174                 drm_info(&dev_priv->drm,
5175                          "LVDS was detected, not registering eDP\n");
5176
5177                 return false;
5178         }
5179
5180         intel_pps_init(intel_dp);
5181
5182         /* Cache DPCD and EDID for edp. */
5183         has_dpcd = intel_edp_init_dpcd(intel_dp);
5184
5185         if (!has_dpcd) {
5186                 /* if this fails, presume the device is a ghost */
5187                 drm_info(&dev_priv->drm,
5188                          "failed to retrieve link info, disabling eDP\n");
5189                 goto out_vdd_off;
5190         }
5191
5192         mutex_lock(&dev->mode_config.mutex);
5193         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5194         if (!edid) {
5195                 /* Fallback to EDID from ACPI OpRegion, if any */
5196                 edid = intel_opregion_get_edid(intel_connector);
5197                 if (edid)
5198                         drm_dbg_kms(&dev_priv->drm,
5199                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5200                                     connector->base.id, connector->name);
5201         }
5202         if (edid) {
5203                 if (drm_add_edid_modes(connector, edid)) {
5204                         drm_connector_update_edid_property(connector, edid);
5205                 } else {
5206                         kfree(edid);
5207                         edid = ERR_PTR(-EINVAL);
5208                 }
5209         } else {
5210                 edid = ERR_PTR(-ENOENT);
5211         }
5212         intel_connector->edid = edid;
5213
5214         intel_panel_add_edid_fixed_modes(intel_connector,
5215                                          dev_priv->vbt.drrs_type != DRRS_TYPE_NONE);
5216
5217         /* MSO requires information from the EDID */
5218         intel_edp_mso_init(intel_dp);
5219
5220         /* multiply the mode clock and horizontal timings for MSO */
5221         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5222                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5223
5224         /* fallback to VBT if available for eDP */
5225         if (!intel_panel_preferred_fixed_mode(intel_connector))
5226                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5227
5228         mutex_unlock(&dev->mode_config.mutex);
5229
5230         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5231                 /*
5232                  * Figure out the current pipe for the initial backlight setup.
5233                  * If the current pipe isn't valid, try the PPS pipe, and if that
5234                  * fails just assume pipe A.
5235                  */
5236                 pipe = vlv_active_pipe(intel_dp);
5237
5238                 if (pipe != PIPE_A && pipe != PIPE_B)
5239                         pipe = intel_dp->pps.pps_pipe;
5240
5241                 if (pipe != PIPE_A && pipe != PIPE_B)
5242                         pipe = PIPE_A;
5243
5244                 drm_dbg_kms(&dev_priv->drm,
5245                             "using pipe %c for initial backlight setup\n",
5246                             pipe_name(pipe));
5247         }
5248
5249         intel_panel_init(intel_connector);
5250
5251         if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
5252                 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5253         intel_backlight_setup(intel_connector, pipe);
5254
5255         intel_edp_add_properties(intel_dp);
5256
5257         return true;
5258
5259 out_vdd_off:
5260         intel_pps_vdd_off_sync(intel_dp);
5261
5262         return false;
5263 }
5264
5265 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5266 {
5267         struct intel_connector *intel_connector;
5268         struct drm_connector *connector;
5269
5270         intel_connector = container_of(work, typeof(*intel_connector),
5271                                        modeset_retry_work);
5272         connector = &intel_connector->base;
5273         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5274                     connector->name);
5275
5276         /* Grab the locks before changing connector property*/
5277         mutex_lock(&connector->dev->mode_config.mutex);
5278         /* Set connector link status to BAD and send a Uevent to notify
5279          * userspace to do a modeset.
5280          */
5281         drm_connector_set_link_status_property(connector,
5282                                                DRM_MODE_LINK_STATUS_BAD);
5283         mutex_unlock(&connector->dev->mode_config.mutex);
5284         /* Send Hotplug uevent so userspace can reprobe */
5285         drm_kms_helper_connector_hotplug_event(connector);
5286 }
5287
5288 bool
5289 intel_dp_init_connector(struct intel_digital_port *dig_port,
5290                         struct intel_connector *intel_connector)
5291 {
5292         struct drm_connector *connector = &intel_connector->base;
5293         struct intel_dp *intel_dp = &dig_port->dp;
5294         struct intel_encoder *intel_encoder = &dig_port->base;
5295         struct drm_device *dev = intel_encoder->base.dev;
5296         struct drm_i915_private *dev_priv = to_i915(dev);
5297         enum port port = intel_encoder->port;
5298         enum phy phy = intel_port_to_phy(dev_priv, port);
5299         int type;
5300
5301         /* Initialize the work for modeset in case of link train failure */
5302         INIT_WORK(&intel_connector->modeset_retry_work,
5303                   intel_dp_modeset_retry_work_fn);
5304
5305         if (drm_WARN(dev, dig_port->max_lanes < 1,
5306                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5307                      dig_port->max_lanes, intel_encoder->base.base.id,
5308                      intel_encoder->base.name))
5309                 return false;
5310
5311         intel_dp->reset_link_params = true;
5312         intel_dp->pps.pps_pipe = INVALID_PIPE;
5313         intel_dp->pps.active_pipe = INVALID_PIPE;
5314
5315         /* Preserve the current hw state. */
5316         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5317         intel_dp->attached_connector = intel_connector;
5318
5319         if (intel_dp_is_port_edp(dev_priv, port)) {
5320                 /*
5321                  * Currently we don't support eDP on TypeC ports, although in
5322                  * theory it could work on TypeC legacy ports.
5323                  */
5324                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5325                 type = DRM_MODE_CONNECTOR_eDP;
5326                 intel_encoder->type = INTEL_OUTPUT_EDP;
5327
5328                 /* eDP only on port B and/or C on vlv/chv */
5329                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5330                                       IS_CHERRYVIEW(dev_priv)) &&
5331                                 port != PORT_B && port != PORT_C))
5332                         return false;
5333         } else {
5334                 type = DRM_MODE_CONNECTOR_DisplayPort;
5335         }
5336
5337         intel_dp_set_source_rates(intel_dp);
5338         intel_dp_set_default_sink_rates(intel_dp);
5339         intel_dp_set_default_max_sink_lane_count(intel_dp);
5340         intel_dp_set_common_rates(intel_dp);
5341         intel_dp_reset_max_link_params(intel_dp);
5342
5343         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5344                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5345
5346         drm_dbg_kms(&dev_priv->drm,
5347                     "Adding %s connector on [ENCODER:%d:%s]\n",
5348                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5349                     intel_encoder->base.base.id, intel_encoder->base.name);
5350
5351         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5352         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5353
5354         if (!HAS_GMCH(dev_priv))
5355                 connector->interlace_allowed = true;
5356         connector->doublescan_allowed = 0;
5357
5358         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5359
5360         intel_dp_aux_init(intel_dp);
5361
5362         intel_connector_attach_encoder(intel_connector, intel_encoder);
5363
5364         if (HAS_DDI(dev_priv))
5365                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5366         else
5367                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5368
5369         /* init MST on ports that can support it */
5370         intel_dp_mst_encoder_init(dig_port,
5371                                   intel_connector->base.base.id);
5372
5373         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5374                 intel_dp_aux_fini(intel_dp);
5375                 intel_dp_mst_encoder_cleanup(dig_port);
5376                 goto fail;
5377         }
5378
5379         intel_dp_add_properties(intel_dp, connector);
5380
5381         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5382                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5383                 if (ret)
5384                         drm_dbg_kms(&dev_priv->drm,
5385                                     "HDCP init failed, skipping.\n");
5386         }
5387
5388         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5389          * 0xd.  Failure to do so will result in spurious interrupts being
5390          * generated on the port when a cable is not attached.
5391          */
5392         if (IS_G45(dev_priv)) {
5393                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5394                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5395                                (temp & ~0xf) | 0xd);
5396         }
5397
5398         intel_dp->frl.is_trained = false;
5399         intel_dp->frl.trained_rate_gbps = 0;
5400
5401         intel_psr_init(intel_dp);
5402
5403         return true;
5404
5405 fail:
5406         drm_connector_cleanup(connector);
5407
5408         return false;
5409 }
5410
5411 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5412 {
5413         struct intel_encoder *encoder;
5414
5415         if (!HAS_DISPLAY(dev_priv))
5416                 return;
5417
5418         for_each_intel_encoder(&dev_priv->drm, encoder) {
5419                 struct intel_dp *intel_dp;
5420
5421                 if (encoder->type != INTEL_OUTPUT_DDI)
5422                         continue;
5423
5424                 intel_dp = enc_to_intel_dp(encoder);
5425
5426                 if (!intel_dp_mst_source_support(intel_dp))
5427                         continue;
5428
5429                 if (intel_dp->is_mst)
5430                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5431         }
5432 }
5433
5434 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5435 {
5436         struct intel_encoder *encoder;
5437
5438         if (!HAS_DISPLAY(dev_priv))
5439                 return;
5440
5441         for_each_intel_encoder(&dev_priv->drm, encoder) {
5442                 struct intel_dp *intel_dp;
5443                 int ret;
5444
5445                 if (encoder->type != INTEL_OUTPUT_DDI)
5446                         continue;
5447
5448                 intel_dp = enc_to_intel_dp(encoder);
5449
5450                 if (!intel_dp_mst_source_support(intel_dp))
5451                         continue;
5452
5453                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5454                                                      true);
5455                 if (ret) {
5456                         intel_dp->is_mst = false;
5457                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5458                                                         false);
5459                 }
5460         }
5461 }