drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/timekeeping.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/dp/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_probe_helper.h>
  42
  43 #include "g4x_dp.h"
  44 #include "i915_debugfs.h"
  45 #include "i915_drv.h"
  46 #include "intel_atomic.h"
  47 #include "intel_audio.h"
  48 #include "intel_backlight.h"
  49 #include "intel_combo_phy_regs.h"
  50 #include "intel_connector.h"
  51 #include "intel_crtc.h"
  52 #include "intel_ddi.h"
  53 #include "intel_de.h"
  54 #include "intel_display_types.h"
  55 #include "intel_dp.h"
  56 #include "intel_dp_aux.h"
  57 #include "intel_dp_hdcp.h"
  58 #include "intel_dp_link_training.h"
  59 #include "intel_dp_mst.h"
  60 #include "intel_dpio_phy.h"
  61 #include "intel_dpll.h"
  62 #include "intel_drrs.h"
  63 #include "intel_fifo_underrun.h"
  64 #include "intel_hdcp.h"
  65 #include "intel_hdmi.h"
  66 #include "intel_hotplug.h"
  67 #include "intel_lspcon.h"
  68 #include "intel_lvds.h"
  69 #include "intel_panel.h"
  70 #include "intel_pps.h"
  71 #include "intel_psr.h"
  72 #include "intel_tc.h"
  73 #include "intel_vdsc.h"
  74 #include "intel_vrr.h"
  75
  76 /* DP DSC throughput values used for slice count calculations KPixels/s */
  77 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  78 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  79 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  80
  81 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  82 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  83
  84 /* Compliance test status bits  */
  85 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  86 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  88 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  89
  90
  91 /* Constants for DP DSC configurations */
  92 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  93
  94 /* With Single pipe configuration, HW is capable of supporting maximum
  95  * of 4 slices per line.
  96  */
  97 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
  98
  99 /**
 100  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 101  * @intel_dp: DP struct
 102  *
 103  * If a CPU or PCH DP output is attached to an eDP panel, this function
 104  * will return true, and false otherwise.
 105  *
 106  * This function is not safe to use prior to encoder type being set.
 107  */
 108 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 109 {
 110         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 111
 112         return dig_port->base.type == INTEL_OUTPUT_EDP;
 113 }
 114
 115 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 116 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 117
 118 /* Is link rate UHBR and thus 128b/132b? */
 119 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 120 {
 121         return crtc_state->port_clock >= 1000000;
 122 }
 123
 124 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 125 {
 126         intel_dp->sink_rates[0] = 162000;
 127         intel_dp->num_sink_rates = 1;
 128 }
 129
 130 /* update sink rates from dpcd */
 131 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 132 {
 133         static const int dp_rates[] = {
 134                 162000, 270000, 540000, 810000
 135         };
 136         int i, max_rate;
 137         int max_lttpr_rate;
 138
 139         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 140                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 141                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 142
 143                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 144                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 145
 146                 return;
 147         }
 148
 149         /*
 150          * Sink rates for 8b/10b.
 151          */
 152         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 153         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 154         if (max_lttpr_rate)
 155                 max_rate = min(max_rate, max_lttpr_rate);
 156
 157         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 158                 if (dp_rates[i] > max_rate)
 159                         break;
 160                 intel_dp->sink_rates[i] = dp_rates[i];
 161         }
 162
 163         /*
 164          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 165          * rates and 10 Gbps.
 166          */
 167         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 168                 u8 uhbr_rates = 0;
 169
 170                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 171
 172                 drm_dp_dpcd_readb(&intel_dp->aux,
 173                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 174
 175                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 176                         /* We have a repeater */
 177                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 178                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 179                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 180                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 181                                 /* Repeater supports 128b/132b, valid UHBR rates */
 182                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 183                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 184                         } else {
 185                                 /* Does not support 128b/132b */
 186                                 uhbr_rates = 0;
 187                         }
 188                 }
 189
 190                 if (uhbr_rates & DP_UHBR10)
 191                         intel_dp->sink_rates[i++] = 1000000;
 192                 if (uhbr_rates & DP_UHBR13_5)
 193                         intel_dp->sink_rates[i++] = 1350000;
 194                 if (uhbr_rates & DP_UHBR20)
 195                         intel_dp->sink_rates[i++] = 2000000;
 196         }
 197
 198         intel_dp->num_sink_rates = i;
 199 }
 200
 201 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 202 {
 203         struct intel_connector *connector = intel_dp->attached_connector;
 204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 205         struct intel_encoder *encoder = &intel_dig_port->base;
 206
 207         intel_dp_set_dpcd_sink_rates(intel_dp);
 208
 209         if (intel_dp->num_sink_rates)
 210                 return;
 211
 212         drm_err(&dp_to_i915(intel_dp)->drm,
 213                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 214                 connector->base.base.id, connector->base.name,
 215                 encoder->base.base.id, encoder->base.name);
 216
 217         intel_dp_set_default_sink_rates(intel_dp);
 218 }
 219
 220 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 221 {
 222         intel_dp->max_sink_lane_count = 1;
 223 }
 224
 225 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 226 {
 227         struct intel_connector *connector = intel_dp->attached_connector;
 228         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 229         struct intel_encoder *encoder = &intel_dig_port->base;
 230
 231         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 232
 233         switch (intel_dp->max_sink_lane_count) {
 234         case 1:
 235         case 2:
 236         case 4:
 237                 return;
 238         }
 239
 240         drm_err(&dp_to_i915(intel_dp)->drm,
 241                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 242                 connector->base.base.id, connector->base.name,
 243                 encoder->base.base.id, encoder->base.name,
 244                 intel_dp->max_sink_lane_count);
 245
 246         intel_dp_set_default_max_sink_lane_count(intel_dp);
 247 }
 248
 249 /* Get length of rates array potentially limited by max_rate. */
 250 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 251 {
 252         int i;
 253
 254         /* Limit results by potentially reduced max rate */
 255         for (i = 0; i < len; i++) {
 256                 if (rates[len - i - 1] <= max_rate)
 257                         return len - i;
 258         }
 259
 260         return 0;
 261 }
 262
 263 /* Get length of common rates array potentially limited by max_rate. */
 264 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 265                                           int max_rate)
 266 {
 267         return intel_dp_rate_limit_len(intel_dp->common_rates,
 268                                        intel_dp->num_common_rates, max_rate);
 269 }
 270
 271 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 272 {
 273         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 274                         index < 0 || index >= intel_dp->num_common_rates))
 275                 return 162000;
 276
 277         return intel_dp->common_rates[index];
 278 }
 279
 280 /* Theoretical max between source and sink */
 281 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 282 {
 283         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 284 }
 285
 286 /* Theoretical max between source and sink */
 287 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 288 {
 289         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 290         int source_max = dig_port->max_lanes;
 291         int sink_max = intel_dp->max_sink_lane_count;
 292         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 293         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 294
 295         if (lttpr_max)
 296                 sink_max = min(sink_max, lttpr_max);
 297
 298         return min3(source_max, sink_max, fia_max);
 299 }
 300
 301 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 302 {
 303         switch (intel_dp->max_link_lane_count) {
 304         case 1:
 305         case 2:
 306         case 4:
 307                 return intel_dp->max_link_lane_count;
 308         default:
 309                 MISSING_CASE(intel_dp->max_link_lane_count);
 310                 return 1;
 311         }
 312 }
 313
 314 /*
 315  * The required data bandwidth for a mode with given pixel clock and bpp. This
 316  * is the required net bandwidth independent of the data bandwidth efficiency.
 317  */
 318 int
 319 intel_dp_link_required(int pixel_clock, int bpp)
 320 {
 321         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 322         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 323 }
 324
 325 /*
 326  * Given a link rate and lanes, get the data bandwidth.
 327  *
 328  * Data bandwidth is the actual payload rate, which depends on the data
 329  * bandwidth efficiency and the link rate.
 330  *
 331  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 332  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 333  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 334  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 335  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 336  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 337  *
 338  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 339  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 340  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 341  * does not match the symbol clock, the port clock (not even if you think in
 342  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 343  * rate in units of 10000 bps.
 344  */
 345 int
 346 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 347 {
 348         if (max_link_rate >= 1000000) {
 349                 /*
 350                  * UHBR rates always use 128b/132b channel encoding, and have
 351                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 352                  * link bit rate in units of 10000 bps.
 353                  */
 354                 int max_link_rate_kbps = max_link_rate * 10;
 355
 356                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 357                 max_link_rate = max_link_rate_kbps / 8;
 358         }
 359
 360         /*
 361          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 362          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 363          * out to be a nop by coincidence, and can be skipped:
 364          *
 365          *      int max_link_rate_kbps = max_link_rate * 10;
 366          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 367          *      max_link_rate = max_link_rate_kbps / 8;
 368          */
 369
 370         return max_link_rate * max_lanes;
 371 }
 372
 373 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 374 {
 375         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 376         struct intel_encoder *encoder = &intel_dig_port->base;
 377         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 378
 379         return DISPLAY_VER(dev_priv) >= 12 ||
 380                 (DISPLAY_VER(dev_priv) == 11 &&
 381                  encoder->port != PORT_A);
 382 }
 383
 384 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 385 {
 386         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 387 }
 388
 389 static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
 390 {
 391         u32 voltage;
 392
 393         voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
 394
 395         return voltage == VOLTAGE_INFO_0_85V;
 396 }
 397
 398 static int icl_max_source_rate(struct intel_dp *intel_dp)
 399 {
 400         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 401         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 402         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 403
 404         if (intel_phy_is_combo(dev_priv, phy) &&
 405             (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
 406                 return 540000;
 407
 408         return 810000;
 409 }
 410
 411 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 412 {
 413         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 414         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 415         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 416
 417         if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
 418                 return 540000;
 419
 420         return 810000;
 421 }
 422
 423 static int dg1_max_source_rate(struct intel_dp *intel_dp)
 424 {
 425         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 426         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 427         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 428
 429         if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
 430                 return 540000;
 431
 432         return 810000;
 433 }
 434
 435 static void
 436 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 437 {
 438         /* The values must be in increasing order */
 439         static const int icl_rates[] = {
 440                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 441                 1000000, 1350000,
 442         };
 443         static const int bxt_rates[] = {
 444                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 445         };
 446         static const int skl_rates[] = {
 447                 162000, 216000, 270000, 324000, 432000, 540000
 448         };
 449         static const int hsw_rates[] = {
 450                 162000, 270000, 540000
 451         };
 452         static const int g4x_rates[] = {
 453                 162000, 270000
 454         };
 455         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 456         struct intel_encoder *encoder = &dig_port->base;
 457         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 458         const int *source_rates;
 459         int size, max_rate = 0, vbt_max_rate;
 460
 461         /* This should only be done once */
 462         drm_WARN_ON(&dev_priv->drm,
 463                     intel_dp->source_rates || intel_dp->num_source_rates);
 464
 465         if (DISPLAY_VER(dev_priv) >= 11) {
 466                 source_rates = icl_rates;
 467                 size = ARRAY_SIZE(icl_rates);
 468                 if (IS_DG2(dev_priv))
 469                         max_rate = dg2_max_source_rate(intel_dp);
 470                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 471                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 472                         max_rate = dg1_max_source_rate(intel_dp);
 473                 else if (IS_JSL_EHL(dev_priv))
 474                         max_rate = ehl_max_source_rate(intel_dp);
 475                 else
 476                         max_rate = icl_max_source_rate(intel_dp);
 477         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 478                 source_rates = bxt_rates;
 479                 size = ARRAY_SIZE(bxt_rates);
 480         } else if (DISPLAY_VER(dev_priv) == 9) {
 481                 source_rates = skl_rates;
 482                 size = ARRAY_SIZE(skl_rates);
 483         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 484                    IS_BROADWELL(dev_priv)) {
 485                 source_rates = hsw_rates;
 486                 size = ARRAY_SIZE(hsw_rates);
 487         } else {
 488                 source_rates = g4x_rates;
 489                 size = ARRAY_SIZE(g4x_rates);
 490         }
 491
 492         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 493         if (max_rate && vbt_max_rate)
 494                 max_rate = min(max_rate, vbt_max_rate);
 495         else if (vbt_max_rate)
 496                 max_rate = vbt_max_rate;
 497
 498         if (max_rate)
 499                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 500
 501         intel_dp->source_rates = source_rates;
 502         intel_dp->num_source_rates = size;
 503 }
 504
 505 static int intersect_rates(const int *source_rates, int source_len,
 506                            const int *sink_rates, int sink_len,
 507                            int *common_rates)
 508 {
 509         int i = 0, j = 0, k = 0;
 510
 511         while (i < source_len && j < sink_len) {
 512                 if (source_rates[i] == sink_rates[j]) {
 513                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 514                                 return k;
 515                         common_rates[k] = source_rates[i];
 516                         ++k;
 517                         ++i;
 518                         ++j;
 519                 } else if (source_rates[i] < sink_rates[j]) {
 520                         ++i;
 521                 } else {
 522                         ++j;
 523                 }
 524         }
 525         return k;
 526 }
 527
 528 /* return index of rate in rates array, or -1 if not found */
 529 static int intel_dp_rate_index(const int *rates, int len, int rate)
 530 {
 531         int i;
 532
 533         for (i = 0; i < len; i++)
 534                 if (rate == rates[i])
 535                         return i;
 536
 537         return -1;
 538 }
 539
 540 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 541 {
 542         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 543
 544         drm_WARN_ON(&i915->drm,
 545                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 546
 547         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 548                                                      intel_dp->num_source_rates,
 549                                                      intel_dp->sink_rates,
 550                                                      intel_dp->num_sink_rates,
 551                                                      intel_dp->common_rates);
 552
 553         /* Paranoia, there should always be something in common. */
 554         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 555                 intel_dp->common_rates[0] = 162000;
 556                 intel_dp->num_common_rates = 1;
 557         }
 558 }
 559
 560 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 561                                        u8 lane_count)
 562 {
 563         /*
 564          * FIXME: we need to synchronize the current link parameters with
 565          * hardware readout. Currently fast link training doesn't work on
 566          * boot-up.
 567          */
 568         if (link_rate == 0 ||
 569             link_rate > intel_dp->max_link_rate)
 570                 return false;
 571
 572         if (lane_count == 0 ||
 573             lane_count > intel_dp_max_lane_count(intel_dp))
 574                 return false;
 575
 576         return true;
 577 }
 578
 579 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 580                                                      int link_rate,
 581                                                      u8 lane_count)
 582 {
 583         const struct drm_display_mode *fixed_mode =
 584                 intel_dp->attached_connector->panel.fixed_mode;
 585         int mode_rate, max_rate;
 586
 587         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 588         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 589         if (mode_rate > max_rate)
 590                 return false;
 591
 592         return true;
 593 }
 594
 595 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 596                                             int link_rate, u8 lane_count)
 597 {
 598         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 599         int index;
 600
 601         /*
 602          * TODO: Enable fallback on MST links once MST link compute can handle
 603          * the fallback params.
 604          */
 605         if (intel_dp->is_mst) {
 606                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 607                 return -1;
 608         }
 609
 610         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 611                 drm_dbg_kms(&i915->drm,
 612                             "Retrying Link training for eDP with max parameters\n");
 613                 intel_dp->use_max_params = true;
 614                 return 0;
 615         }
 616
 617         index = intel_dp_rate_index(intel_dp->common_rates,
 618                                     intel_dp->num_common_rates,
 619                                     link_rate);
 620         if (index > 0) {
 621                 if (intel_dp_is_edp(intel_dp) &&
 622                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 623                                                               intel_dp_common_rate(intel_dp, index - 1),
 624                                                               lane_count)) {
 625                         drm_dbg_kms(&i915->drm,
 626                                     "Retrying Link training for eDP with same parameters\n");
 627                         return 0;
 628                 }
 629                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 630                 intel_dp->max_link_lane_count = lane_count;
 631         } else if (lane_count > 1) {
 632                 if (intel_dp_is_edp(intel_dp) &&
 633                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 634                                                               intel_dp_max_common_rate(intel_dp),
 635                                                               lane_count >> 1)) {
 636                         drm_dbg_kms(&i915->drm,
 637                                     "Retrying Link training for eDP with same parameters\n");
 638                         return 0;
 639                 }
 640                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 641                 intel_dp->max_link_lane_count = lane_count >> 1;
 642         } else {
 643                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 644                 return -1;
 645         }
 646
 647         return 0;
 648 }
 649
 650 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 651 {
 652         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 653                        DP_DSC_FEC_OVERHEAD_FACTOR);
 654 }
 655
 656 static int
 657 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 658 {
 659         if (DISPLAY_VER(i915) >= 13)
 660                 return 17280 * 8;
 661         else if (DISPLAY_VER(i915) >= 11)
 662                 return 7680 * 8;
 663         else
 664                 return 6144 * 8;
 665 }
 666
 667 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 668                                        u32 link_clock, u32 lane_count,
 669                                        u32 mode_clock, u32 mode_hdisplay,
 670                                        bool bigjoiner,
 671                                        u32 pipe_bpp)
 672 {
 673         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 674         int i;
 675
 676         /*
 677          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 678          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 679          * for SST -> TimeSlotsPerMTP is 1,
 680          * for MST -> TimeSlotsPerMTP has to be calculated
 681          */
 682         bits_per_pixel = (link_clock * lane_count * 8) /
 683                          intel_dp_mode_to_fec_clock(mode_clock);
 684         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 685
 686         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 687         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 688                 mode_hdisplay;
 689
 690         if (bigjoiner)
 691                 max_bpp_small_joiner_ram *= 2;
 692
 693         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 694                     max_bpp_small_joiner_ram);
 695
 696         /*
 697          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 698          * check, output bpp from small joiner RAM check)
 699          */
 700         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 701
 702         if (bigjoiner) {
 703                 u32 max_bpp_bigjoiner =
 704                         i915->max_cdclk_freq * 48 /
 705                         intel_dp_mode_to_fec_clock(mode_clock);
 706
 707                 drm_dbg_kms(&i915->drm, "Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 708                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 709         }
 710
 711         /* Error out if the max bpp is less than smallest allowed valid bpp */
 712         if (bits_per_pixel < valid_dsc_bpp[0]) {
 713                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 714                             bits_per_pixel, valid_dsc_bpp[0]);
 715                 return 0;
 716         }
 717
 718         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 719         if (DISPLAY_VER(i915) >= 13) {
 720                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 721         } else {
 722                 /* Find the nearest match in the array of known BPPs from VESA */
 723                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 724                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 725                                 break;
 726                 }
 727                 bits_per_pixel = valid_dsc_bpp[i];
 728         }
 729
 730         /*
 731          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 732          * fractional part is 0
 733          */
 734         return bits_per_pixel << 4;
 735 }
 736
 737 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 738                                        int mode_clock, int mode_hdisplay,
 739                                        bool bigjoiner)
 740 {
 741         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 742         u8 min_slice_count, i;
 743         int max_slice_width;
 744
 745         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 746                 min_slice_count = DIV_ROUND_UP(mode_clock,
 747                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 748         else
 749                 min_slice_count = DIV_ROUND_UP(mode_clock,
 750                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 751
 752         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 753         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 754                 drm_dbg_kms(&i915->drm,
 755                             "Unsupported slice width %d by DP DSC Sink device\n",
 756                             max_slice_width);
 757                 return 0;
 758         }
 759         /* Also take into account max slice width */
 760         min_slice_count = max_t(u8, min_slice_count,
 761                                 DIV_ROUND_UP(mode_hdisplay,
 762                                              max_slice_width));
 763
 764         /* Find the closest match to the valid slice count values */
 765         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 766                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 767
 768                 if (test_slice_count >
 769                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 770                         break;
 771
 772                 /* big joiner needs small joiner to be enabled */
 773                 if (bigjoiner && test_slice_count < 4)
 774                         continue;
 775
 776                 if (min_slice_count <= test_slice_count)
 777                         return test_slice_count;
 778         }
 779
 780         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 781                     min_slice_count);
 782         return 0;
 783 }
 784
 785 static enum intel_output_format
 786 intel_dp_output_format(struct drm_connector *connector,
 787                        const struct drm_display_mode *mode)
 788 {
 789         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 790         const struct drm_display_info *info = &connector->display_info;
 791
 792         if (!connector->ycbcr_420_allowed ||
 793             !drm_mode_is_420_only(info, mode))
 794                 return INTEL_OUTPUT_FORMAT_RGB;
 795
 796         if (intel_dp->dfp.rgb_to_ycbcr &&
 797             intel_dp->dfp.ycbcr_444_to_420)
 798                 return INTEL_OUTPUT_FORMAT_RGB;
 799
 800         if (intel_dp->dfp.ycbcr_444_to_420)
 801                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 802         else
 803                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 804 }
 805
 806 int intel_dp_min_bpp(enum intel_output_format output_format)
 807 {
 808         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 809                 return 6 * 3;
 810         else
 811                 return 8 * 3;
 812 }
 813
 814 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 815 {
 816         /*
 817          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 818          * format of the number of bytes per pixel will be half the number
 819          * of bytes of RGB pixel.
 820          */
 821         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 822                 bpp /= 2;
 823
 824         return bpp;
 825 }
 826
 827 static int
 828 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 829                              const struct drm_display_mode *mode)
 830 {
 831         enum intel_output_format output_format =
 832                 intel_dp_output_format(connector, mode);
 833
 834         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 835 }
 836
 837 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 838                                   int hdisplay)
 839 {
 840         /*
 841          * Older platforms don't like hdisplay==4096 with DP.
 842          *
 843          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 844          * and frame counter increment), but we don't get vblank interrupts,
 845          * and the pipe underruns immediately. The link also doesn't seem
 846          * to get trained properly.
 847          *
 848          * On CHV the vblank interrupts don't seem to disappear but
 849          * otherwise the symptoms are similar.
 850          *
 851          * TODO: confirm the behaviour on HSW+
 852          */
 853         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 854 }
 855
 856 static enum drm_mode_status
 857 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 858                                const struct drm_display_mode *mode,
 859                                int target_clock)
 860 {
 861         struct intel_dp *intel_dp = intel_attached_dp(connector);
 862         const struct drm_display_info *info = &connector->base.display_info;
 863         int tmds_clock;
 864
 865         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 866         if (intel_dp->dfp.pcon_max_frl_bw) {
 867                 int target_bw;
 868                 int max_frl_bw;
 869                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 870
 871                 target_bw = bpp * target_clock;
 872
 873                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 874
 875                 /* converting bw from Gbps to Kbps*/
 876                 max_frl_bw = max_frl_bw * 1000000;
 877
 878                 if (target_bw > max_frl_bw)
 879                         return MODE_CLOCK_HIGH;
 880
 881                 return MODE_OK;
 882         }
 883
 884         if (intel_dp->dfp.max_dotclock &&
 885             target_clock > intel_dp->dfp.max_dotclock)
 886                 return MODE_CLOCK_HIGH;
 887
 888         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 889         tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
 890                                            drm_mode_is_420_only(info, mode));
 891
 892         if (intel_dp->dfp.min_tmds_clock &&
 893             tmds_clock < intel_dp->dfp.min_tmds_clock)
 894                 return MODE_CLOCK_LOW;
 895         if (intel_dp->dfp.max_tmds_clock &&
 896             tmds_clock > intel_dp->dfp.max_tmds_clock)
 897                 return MODE_CLOCK_HIGH;
 898
 899         return MODE_OK;
 900 }
 901
 902 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 903                                     int hdisplay, int clock)
 904 {
 905         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 906
 907         if (!intel_dp_can_bigjoiner(intel_dp))
 908                 return false;
 909
 910         return clock > i915->max_dotclk_freq || hdisplay > 5120;
 911 }
 912
 913 static enum drm_mode_status
 914 intel_dp_mode_valid(struct drm_connector *connector,
 915                     struct drm_display_mode *mode)
 916 {
 917         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 918         struct intel_connector *intel_connector = to_intel_connector(connector);
 919         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 920         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 921         int target_clock = mode->clock;
 922         int max_rate, mode_rate, max_lanes, max_link_clock;
 923         int max_dotclk = dev_priv->max_dotclk_freq;
 924         u16 dsc_max_output_bpp = 0;
 925         u8 dsc_slice_count = 0;
 926         enum drm_mode_status status;
 927         bool dsc = false, bigjoiner = false;
 928
 929         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 930                 return MODE_NO_DBLESCAN;
 931
 932         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 933                 return MODE_H_ILLEGAL;
 934
 935         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 936                 status = intel_panel_mode_valid(intel_connector, mode);
 937                 if (status != MODE_OK)
 938                         return status;
 939
 940                 target_clock = fixed_mode->clock;
 941         }
 942
 943         if (mode->clock < 10000)
 944                 return MODE_CLOCK_LOW;
 945
 946         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 947                 bigjoiner = true;
 948                 max_dotclk *= 2;
 949         }
 950         if (target_clock > max_dotclk)
 951                 return MODE_CLOCK_HIGH;
 952
 953         max_link_clock = intel_dp_max_link_rate(intel_dp);
 954         max_lanes = intel_dp_max_lane_count(intel_dp);
 955
 956         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 957         mode_rate = intel_dp_link_required(target_clock,
 958                                            intel_dp_mode_min_output_bpp(connector, mode));
 959
 960         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 961                 return MODE_H_ILLEGAL;
 962
 963         /*
 964          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 965          * integer value since we support only integer values of bpp.
 966          */
 967         if (DISPLAY_VER(dev_priv) >= 10 &&
 968             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 969                 /*
 970                  * TBD pass the connector BPC,
 971                  * for now U8_MAX so that max BPC on that platform would be picked
 972                  */
 973                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
 974
 975                 if (intel_dp_is_edp(intel_dp)) {
 976                         dsc_max_output_bpp =
 977                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 978                         dsc_slice_count =
 979                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 980                                                                 true);
 981                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 982                         dsc_max_output_bpp =
 983                                 intel_dp_dsc_get_output_bpp(dev_priv,
 984                                                             max_link_clock,
 985                                                             max_lanes,
 986                                                             target_clock,
 987                                                             mode->hdisplay,
 988                                                             bigjoiner,
 989                                                             pipe_bpp) >> 4;
 990                         dsc_slice_count =
 991                                 intel_dp_dsc_get_slice_count(intel_dp,
 992                                                              target_clock,
 993                                                              mode->hdisplay,
 994                                                              bigjoiner);
 995                 }
 996
 997                 dsc = dsc_max_output_bpp && dsc_slice_count;
 998         }
 999
1000         /*
1001          * Big joiner configuration needs DSC for TGL which is not true for
1002          * XE_LPD where uncompressed joiner is supported.
1003          */
1004         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1005                 return MODE_CLOCK_HIGH;
1006
1007         if (mode_rate > max_rate && !dsc)
1008                 return MODE_CLOCK_HIGH;
1009
1010         status = intel_dp_mode_valid_downstream(intel_connector,
1011                                                 mode, target_clock);
1012         if (status != MODE_OK)
1013                 return status;
1014
1015         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1016 }
1017
1018 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1019 {
1020         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1021 }
1022
1023 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1024 {
1025         return DISPLAY_VER(i915) >= 10;
1026 }
1027
1028 static void snprintf_int_array(char *str, size_t len,
1029                                const int *array, int nelem)
1030 {
1031         int i;
1032
1033         str[0] = '\0';
1034
1035         for (i = 0; i < nelem; i++) {
1036                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1037                 if (r >= len)
1038                         return;
1039                 str += r;
1040                 len -= r;
1041         }
1042 }
1043
1044 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1045 {
1046         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1047         char str[128]; /* FIXME: too big for stack? */
1048
1049         if (!drm_debug_enabled(DRM_UT_KMS))
1050                 return;
1051
1052         snprintf_int_array(str, sizeof(str),
1053                            intel_dp->source_rates, intel_dp->num_source_rates);
1054         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1055
1056         snprintf_int_array(str, sizeof(str),
1057                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1058         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1059
1060         snprintf_int_array(str, sizeof(str),
1061                            intel_dp->common_rates, intel_dp->num_common_rates);
1062         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1063 }
1064
1065 int
1066 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1067 {
1068         int len;
1069
1070         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1071
1072         return intel_dp_common_rate(intel_dp, len - 1);
1073 }
1074
1075 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1076 {
1077         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1078         int i = intel_dp_rate_index(intel_dp->sink_rates,
1079                                     intel_dp->num_sink_rates, rate);
1080
1081         if (drm_WARN_ON(&i915->drm, i < 0))
1082                 i = 0;
1083
1084         return i;
1085 }
1086
1087 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1088                            u8 *link_bw, u8 *rate_select)
1089 {
1090         /* eDP 1.4 rate select method. */
1091         if (intel_dp->use_rate_select) {
1092                 *link_bw = 0;
1093                 *rate_select =
1094                         intel_dp_rate_select(intel_dp, port_clock);
1095         } else {
1096                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1097                 *rate_select = 0;
1098         }
1099 }
1100
1101 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1102                                          const struct intel_crtc_state *pipe_config)
1103 {
1104         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1105
1106         /* On TGL, FEC is supported on all Pipes */
1107         if (DISPLAY_VER(dev_priv) >= 12)
1108                 return true;
1109
1110         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1111                 return true;
1112
1113         return false;
1114 }
1115
1116 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1117                                   const struct intel_crtc_state *pipe_config)
1118 {
1119         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1120                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1121 }
1122
1123 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1124                                   const struct intel_crtc_state *crtc_state)
1125 {
1126         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1127                 return false;
1128
1129         return intel_dsc_source_support(crtc_state) &&
1130                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1131 }
1132
1133 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
1134                                    const struct intel_crtc_state *crtc_state)
1135 {
1136         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1137                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1138                  intel_dp->dfp.ycbcr_444_to_420);
1139 }
1140
1141 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
1142                                            const struct intel_crtc_state *crtc_state, int bpc)
1143 {
1144         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1145         int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
1146                                                intel_dp_hdmi_ycbcr420(intel_dp, crtc_state));
1147
1148         if (intel_dp->dfp.min_tmds_clock &&
1149             tmds_clock < intel_dp->dfp.min_tmds_clock)
1150                 return false;
1151
1152         if (intel_dp->dfp.max_tmds_clock &&
1153             tmds_clock > intel_dp->dfp.max_tmds_clock)
1154                 return false;
1155
1156         return true;
1157 }
1158
1159 static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
1160                                        const struct intel_crtc_state *crtc_state,
1161                                        int bpc)
1162 {
1163
1164         return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
1165                                        intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1166                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
1167 }
1168
1169 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1170                             const struct intel_crtc_state *crtc_state)
1171 {
1172         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1173         struct intel_connector *intel_connector = intel_dp->attached_connector;
1174         int bpp, bpc;
1175
1176         bpc = crtc_state->pipe_bpp / 3;
1177
1178         if (intel_dp->dfp.max_bpc)
1179                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1180
1181         if (intel_dp->dfp.min_tmds_clock) {
1182                 for (; bpc >= 10; bpc -= 2) {
1183                         if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
1184                                 break;
1185                 }
1186         }
1187
1188         bpp = bpc * 3;
1189         if (intel_dp_is_edp(intel_dp)) {
1190                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1191                 if (intel_connector->base.display_info.bpc == 0 &&
1192                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1193                         drm_dbg_kms(&dev_priv->drm,
1194                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1195                                     dev_priv->vbt.edp.bpp);
1196                         bpp = dev_priv->vbt.edp.bpp;
1197                 }
1198         }
1199
1200         return bpp;
1201 }
1202
1203 /* Adjust link config limits based on compliance test requests. */
1204 void
1205 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1206                                   struct intel_crtc_state *pipe_config,
1207                                   struct link_config_limits *limits)
1208 {
1209         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1210
1211         /* For DP Compliance we override the computed bpp for the pipe */
1212         if (intel_dp->compliance.test_data.bpc != 0) {
1213                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1214
1215                 limits->min_bpp = limits->max_bpp = bpp;
1216                 pipe_config->dither_force_disable = bpp == 6 * 3;
1217
1218                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1219         }
1220
1221         /* Use values requested by Compliance Test Request */
1222         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1223                 int index;
1224
1225                 /* Validate the compliance test data since max values
1226                  * might have changed due to link train fallback.
1227                  */
1228                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1229                                                intel_dp->compliance.test_lane_count)) {
1230                         index = intel_dp_rate_index(intel_dp->common_rates,
1231                                                     intel_dp->num_common_rates,
1232                                                     intel_dp->compliance.test_link_rate);
1233                         if (index >= 0)
1234                                 limits->min_rate = limits->max_rate =
1235                                         intel_dp->compliance.test_link_rate;
1236                         limits->min_lane_count = limits->max_lane_count =
1237                                 intel_dp->compliance.test_lane_count;
1238                 }
1239         }
1240 }
1241
1242 /* Optimize link config in order: max bpp, min clock, min lanes */
1243 static int
1244 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1245                                   struct intel_crtc_state *pipe_config,
1246                                   const struct link_config_limits *limits)
1247 {
1248         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1249         int bpp, i, lane_count;
1250         int mode_rate, link_rate, link_avail;
1251
1252         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1253                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1254
1255                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1256                                                    output_bpp);
1257
1258                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1259                         link_rate = intel_dp_common_rate(intel_dp, i);
1260                         if (link_rate < limits->min_rate ||
1261                             link_rate > limits->max_rate)
1262                                 continue;
1263
1264                         for (lane_count = limits->min_lane_count;
1265                              lane_count <= limits->max_lane_count;
1266                              lane_count <<= 1) {
1267                                 link_avail = intel_dp_max_data_rate(link_rate,
1268                                                                     lane_count);
1269
1270                                 if (mode_rate <= link_avail) {
1271                                         pipe_config->lane_count = lane_count;
1272                                         pipe_config->pipe_bpp = bpp;
1273                                         pipe_config->port_clock = link_rate;
1274
1275                                         return 0;
1276                                 }
1277                         }
1278                 }
1279         }
1280
1281         return -EINVAL;
1282 }
1283
1284 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1285 {
1286         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1287         int i, num_bpc;
1288         u8 dsc_bpc[3] = {0};
1289         u8 dsc_max_bpc;
1290
1291         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1292         if (DISPLAY_VER(i915) >= 12)
1293                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1294         else
1295                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1296
1297         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1298                                                        dsc_bpc);
1299         for (i = 0; i < num_bpc; i++) {
1300                 if (dsc_max_bpc >= dsc_bpc[i])
1301                         return dsc_bpc[i] * 3;
1302         }
1303
1304         return 0;
1305 }
1306
1307 #define DSC_SUPPORTED_VERSION_MIN               1
1308
1309 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1310                                        struct intel_crtc_state *crtc_state)
1311 {
1312         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1313         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1314         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1315         u8 line_buf_depth;
1316         int ret;
1317
1318         /*
1319          * RC_MODEL_SIZE is currently a constant across all configurations.
1320          *
1321          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1322          * DP_DSC_RC_BUF_SIZE for this.
1323          */
1324         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1325
1326         /*
1327          * Slice Height of 8 works for all currently available panels. So start
1328          * with that if pic_height is an integral multiple of 8. Eventually add
1329          * logic to try multiple slice heights.
1330          */
1331         if (vdsc_cfg->pic_height % 8 == 0)
1332                 vdsc_cfg->slice_height = 8;
1333         else if (vdsc_cfg->pic_height % 4 == 0)
1334                 vdsc_cfg->slice_height = 4;
1335         else
1336                 vdsc_cfg->slice_height = 2;
1337
1338         ret = intel_dsc_compute_params(crtc_state);
1339         if (ret)
1340                 return ret;
1341
1342         vdsc_cfg->dsc_version_major =
1343                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1344                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1345         vdsc_cfg->dsc_version_minor =
1346                 min(DSC_SUPPORTED_VERSION_MIN,
1347                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1348                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1349
1350         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1351                 DP_DSC_RGB;
1352
1353         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1354         if (!line_buf_depth) {
1355                 drm_dbg_kms(&i915->drm,
1356                             "DSC Sink Line Buffer Depth invalid\n");
1357                 return -EINVAL;
1358         }
1359
1360         if (vdsc_cfg->dsc_version_minor == 2)
1361                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1362                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1363         else
1364                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1365                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1366
1367         vdsc_cfg->block_pred_enable =
1368                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1369                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1370
1371         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1372 }
1373
1374 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1375                                        struct intel_crtc_state *pipe_config,
1376                                        struct drm_connector_state *conn_state,
1377                                        struct link_config_limits *limits)
1378 {
1379         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1380         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1381         const struct drm_display_mode *adjusted_mode =
1382                 &pipe_config->hw.adjusted_mode;
1383         int pipe_bpp;
1384         int ret;
1385
1386         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1387                 intel_dp_supports_fec(intel_dp, pipe_config);
1388
1389         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1390                 return -EINVAL;
1391
1392         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1393
1394         /* Min Input BPC for ICL+ is 8 */
1395         if (pipe_bpp < 8 * 3) {
1396                 drm_dbg_kms(&dev_priv->drm,
1397                             "No DSC support for less than 8bpc\n");
1398                 return -EINVAL;
1399         }
1400
1401         /*
1402          * For now enable DSC for max bpp, max link rate, max lane count.
1403          * Optimize this later for the minimum possible link rate/lane count
1404          * with DSC enabled for the requested mode.
1405          */
1406         pipe_config->pipe_bpp = pipe_bpp;
1407         pipe_config->port_clock = limits->max_rate;
1408         pipe_config->lane_count = limits->max_lane_count;
1409
1410         if (intel_dp_is_edp(intel_dp)) {
1411                 pipe_config->dsc.compressed_bpp =
1412                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1413                               pipe_config->pipe_bpp);
1414                 pipe_config->dsc.slice_count =
1415                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1416                                                         true);
1417         } else {
1418                 u16 dsc_max_output_bpp;
1419                 u8 dsc_dp_slice_count;
1420
1421                 dsc_max_output_bpp =
1422                         intel_dp_dsc_get_output_bpp(dev_priv,
1423                                                     pipe_config->port_clock,
1424                                                     pipe_config->lane_count,
1425                                                     adjusted_mode->crtc_clock,
1426                                                     adjusted_mode->crtc_hdisplay,
1427                                                     pipe_config->bigjoiner,
1428                                                     pipe_bpp);
1429                 dsc_dp_slice_count =
1430                         intel_dp_dsc_get_slice_count(intel_dp,
1431                                                      adjusted_mode->crtc_clock,
1432                                                      adjusted_mode->crtc_hdisplay,
1433                                                      pipe_config->bigjoiner);
1434                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1435                         drm_dbg_kms(&dev_priv->drm,
1436                                     "Compressed BPP/Slice Count not supported\n");
1437                         return -EINVAL;
1438                 }
1439                 pipe_config->dsc.compressed_bpp = min_t(u16,
1440                                                                dsc_max_output_bpp >> 4,
1441                                                                pipe_config->pipe_bpp);
1442                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1443         }
1444
1445         /* As of today we support DSC for only RGB */
1446         if (intel_dp->force_dsc_bpp) {
1447                 if (intel_dp->force_dsc_bpp >= 8 &&
1448                     intel_dp->force_dsc_bpp < pipe_bpp) {
1449                         drm_dbg_kms(&dev_priv->drm,
1450                                     "DSC BPP forced to %d",
1451                                     intel_dp->force_dsc_bpp);
1452                         pipe_config->dsc.compressed_bpp =
1453                                                 intel_dp->force_dsc_bpp;
1454                 } else {
1455                         drm_dbg_kms(&dev_priv->drm,
1456                                     "Invalid DSC BPP %d",
1457                                     intel_dp->force_dsc_bpp);
1458                 }
1459         }
1460
1461         /*
1462          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1463          * is greater than the maximum Cdclock and if slice count is even
1464          * then we need to use 2 VDSC instances.
1465          */
1466         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1467             pipe_config->bigjoiner) {
1468                 if (pipe_config->dsc.slice_count < 2) {
1469                         drm_dbg_kms(&dev_priv->drm,
1470                                     "Cannot split stream to use 2 VDSC instances\n");
1471                         return -EINVAL;
1472                 }
1473
1474                 pipe_config->dsc.dsc_split = true;
1475         }
1476
1477         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1478         if (ret < 0) {
1479                 drm_dbg_kms(&dev_priv->drm,
1480                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1481                             "Compressed BPP = %d\n",
1482                             pipe_config->pipe_bpp,
1483                             pipe_config->dsc.compressed_bpp);
1484                 return ret;
1485         }
1486
1487         pipe_config->dsc.compression_enable = true;
1488         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1489                     "Compressed Bpp = %d Slice Count = %d\n",
1490                     pipe_config->pipe_bpp,
1491                     pipe_config->dsc.compressed_bpp,
1492                     pipe_config->dsc.slice_count);
1493
1494         return 0;
1495 }
1496
1497 static int
1498 intel_dp_compute_link_config(struct intel_encoder *encoder,
1499                              struct intel_crtc_state *pipe_config,
1500                              struct drm_connector_state *conn_state)
1501 {
1502         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1503         const struct drm_display_mode *adjusted_mode =
1504                 &pipe_config->hw.adjusted_mode;
1505         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1506         struct link_config_limits limits;
1507         int ret;
1508
1509         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1510         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1511
1512         limits.min_lane_count = 1;
1513         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1514
1515         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1516         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1517
1518         if (intel_dp->use_max_params) {
1519                 /*
1520                  * Use the maximum clock and number of lanes the eDP panel
1521                  * advertizes being capable of in case the initial fast
1522                  * optimal params failed us. The panels are generally
1523                  * designed to support only a single clock and lane
1524                  * configuration, and typically on older panels these
1525                  * values correspond to the native resolution of the panel.
1526                  */
1527                 limits.min_lane_count = limits.max_lane_count;
1528                 limits.min_rate = limits.max_rate;
1529         }
1530
1531         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1532
1533         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1534                     "max rate %d max bpp %d pixel clock %iKHz\n",
1535                     limits.max_lane_count, limits.max_rate,
1536                     limits.max_bpp, adjusted_mode->crtc_clock);
1537
1538         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1539                                     adjusted_mode->crtc_clock))
1540                 pipe_config->bigjoiner = true;
1541
1542         /*
1543          * Optimize for slow and wide for everything, because there are some
1544          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1545          */
1546         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1547
1548         /*
1549          * Pipe joiner needs compression upto display12 due to BW limitation. DG2
1550          * onwards pipe joiner can be enabled without compression.
1551          */
1552         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1553         if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 &&
1554                                               pipe_config->bigjoiner)) {
1555                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1556                                                   conn_state, &limits);
1557                 if (ret < 0)
1558                         return ret;
1559         }
1560
1561         if (pipe_config->dsc.compression_enable) {
1562                 drm_dbg_kms(&i915->drm,
1563                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1564                             pipe_config->lane_count, pipe_config->port_clock,
1565                             pipe_config->pipe_bpp,
1566                             pipe_config->dsc.compressed_bpp);
1567
1568                 drm_dbg_kms(&i915->drm,
1569                             "DP link rate required %i available %i\n",
1570                             intel_dp_link_required(adjusted_mode->crtc_clock,
1571                                                    pipe_config->dsc.compressed_bpp),
1572                             intel_dp_max_data_rate(pipe_config->port_clock,
1573                                                    pipe_config->lane_count));
1574         } else {
1575                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1576                             pipe_config->lane_count, pipe_config->port_clock,
1577                             pipe_config->pipe_bpp);
1578
1579                 drm_dbg_kms(&i915->drm,
1580                             "DP link rate required %i available %i\n",
1581                             intel_dp_link_required(adjusted_mode->crtc_clock,
1582                                                    pipe_config->pipe_bpp),
1583                             intel_dp_max_data_rate(pipe_config->port_clock,
1584                                                    pipe_config->lane_count));
1585         }
1586         return 0;
1587 }
1588
1589 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1590                                   const struct drm_connector_state *conn_state)
1591 {
1592         const struct intel_digital_connector_state *intel_conn_state =
1593                 to_intel_digital_connector_state(conn_state);
1594         const struct drm_display_mode *adjusted_mode =
1595                 &crtc_state->hw.adjusted_mode;
1596
1597         /*
1598          * Our YCbCr output is always limited range.
1599          * crtc_state->limited_color_range only applies to RGB,
1600          * and it must never be set for YCbCr or we risk setting
1601          * some conflicting bits in PIPECONF which will mess up
1602          * the colors on the monitor.
1603          */
1604         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1605                 return false;
1606
1607         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1608                 /*
1609                  * See:
1610                  * CEA-861-E - 5.1 Default Encoding Parameters
1611                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1612                  */
1613                 return crtc_state->pipe_bpp != 18 &&
1614                         drm_default_rgb_quant_range(adjusted_mode) ==
1615                         HDMI_QUANTIZATION_RANGE_LIMITED;
1616         } else {
1617                 return intel_conn_state->broadcast_rgb ==
1618                         INTEL_BROADCAST_RGB_LIMITED;
1619         }
1620 }
1621
1622 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1623                                     enum port port)
1624 {
1625         if (IS_G4X(dev_priv))
1626                 return false;
1627         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1628                 return false;
1629
1630         return true;
1631 }
1632
1633 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1634                                              const struct drm_connector_state *conn_state,
1635                                              struct drm_dp_vsc_sdp *vsc)
1636 {
1637         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1639
1640         /*
1641          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1642          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1643          * Colorimetry Format indication.
1644          */
1645         vsc->revision = 0x5;
1646         vsc->length = 0x13;
1647
1648         /* DP 1.4a spec, Table 2-120 */
1649         switch (crtc_state->output_format) {
1650         case INTEL_OUTPUT_FORMAT_YCBCR444:
1651                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1652                 break;
1653         case INTEL_OUTPUT_FORMAT_YCBCR420:
1654                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1655                 break;
1656         case INTEL_OUTPUT_FORMAT_RGB:
1657         default:
1658                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1659         }
1660
1661         switch (conn_state->colorspace) {
1662         case DRM_MODE_COLORIMETRY_BT709_YCC:
1663                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1664                 break;
1665         case DRM_MODE_COLORIMETRY_XVYCC_601:
1666                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1667                 break;
1668         case DRM_MODE_COLORIMETRY_XVYCC_709:
1669                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1670                 break;
1671         case DRM_MODE_COLORIMETRY_SYCC_601:
1672                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1673                 break;
1674         case DRM_MODE_COLORIMETRY_OPYCC_601:
1675                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1676                 break;
1677         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1678                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1679                 break;
1680         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1681                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1682                 break;
1683         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1684                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1685                 break;
1686         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1687         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1688                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1689                 break;
1690         default:
1691                 /*
1692                  * RGB->YCBCR color conversion uses the BT.709
1693                  * color space.
1694                  */
1695                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1696                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1697                 else
1698                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1699                 break;
1700         }
1701
1702         vsc->bpc = crtc_state->pipe_bpp / 3;
1703
1704         /* only RGB pixelformat supports 6 bpc */
1705         drm_WARN_ON(&dev_priv->drm,
1706                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1707
1708         /* all YCbCr are always limited range */
1709         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1710         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1711 }
1712
1713 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1714                                      struct intel_crtc_state *crtc_state,
1715                                      const struct drm_connector_state *conn_state)
1716 {
1717         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1718
1719         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1720         if (crtc_state->has_psr)
1721                 return;
1722
1723         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1724                 return;
1725
1726         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1727         vsc->sdp_type = DP_SDP_VSC;
1728         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1729                                          &crtc_state->infoframes.vsc);
1730 }
1731
1732 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1733                                   const struct intel_crtc_state *crtc_state,
1734                                   const struct drm_connector_state *conn_state,
1735                                   struct drm_dp_vsc_sdp *vsc)
1736 {
1737         vsc->sdp_type = DP_SDP_VSC;
1738
1739         if (crtc_state->has_psr2) {
1740                 if (intel_dp->psr.colorimetry_support &&
1741                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1742                         /* [PSR2, +Colorimetry] */
1743                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1744                                                          vsc);
1745                 } else {
1746                         /*
1747                          * [PSR2, -Colorimetry]
1748                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1749                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1750                          */
1751                         vsc->revision = 0x4;
1752                         vsc->length = 0xe;
1753                 }
1754         } else {
1755                 /*
1756                  * [PSR1]
1757                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1758                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1759                  * higher).
1760                  */
1761                 vsc->revision = 0x2;
1762                 vsc->length = 0x8;
1763         }
1764 }
1765
1766 static void
1767 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1768                                             struct intel_crtc_state *crtc_state,
1769                                             const struct drm_connector_state *conn_state)
1770 {
1771         int ret;
1772         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1773         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1774
1775         if (!conn_state->hdr_output_metadata)
1776                 return;
1777
1778         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1779
1780         if (ret) {
1781                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1782                 return;
1783         }
1784
1785         crtc_state->infoframes.enable |=
1786                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1787 }
1788
1789 int
1790 intel_dp_compute_config(struct intel_encoder *encoder,
1791                         struct intel_crtc_state *pipe_config,
1792                         struct drm_connector_state *conn_state)
1793 {
1794         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1795         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1796         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1797         enum port port = encoder->port;
1798         struct intel_connector *intel_connector = intel_dp->attached_connector;
1799         struct intel_digital_connector_state *intel_conn_state =
1800                 to_intel_digital_connector_state(conn_state);
1801         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1802         int ret = 0, output_bpp;
1803
1804         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1805                 pipe_config->has_pch_encoder = true;
1806
1807         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1808                                                             adjusted_mode);
1809
1810         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1811                 ret = intel_panel_fitting(pipe_config, conn_state);
1812                 if (ret)
1813                         return ret;
1814         }
1815
1816         if (!intel_dp_port_has_audio(dev_priv, port))
1817                 pipe_config->has_audio = false;
1818         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1819                 pipe_config->has_audio = intel_dp->has_audio;
1820         else
1821                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1822
1823         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1824                 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1825                 if (ret)
1826                         return ret;
1827
1828                 ret = intel_panel_fitting(pipe_config, conn_state);
1829                 if (ret)
1830                         return ret;
1831         }
1832
1833         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1834                 return -EINVAL;
1835
1836         if (HAS_GMCH(dev_priv) &&
1837             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1838                 return -EINVAL;
1839
1840         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1841                 return -EINVAL;
1842
1843         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1844                 return -EINVAL;
1845
1846         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1847         if (ret < 0)
1848                 return ret;
1849
1850         pipe_config->limited_color_range =
1851                 intel_dp_limited_color_range(pipe_config, conn_state);
1852
1853         if (pipe_config->dsc.compression_enable)
1854                 output_bpp = pipe_config->dsc.compressed_bpp;
1855         else
1856                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1857                                                  pipe_config->pipe_bpp);
1858
1859         if (intel_dp->mso_link_count) {
1860                 int n = intel_dp->mso_link_count;
1861                 int overlap = intel_dp->mso_pixel_overlap;
1862
1863                 pipe_config->splitter.enable = true;
1864                 pipe_config->splitter.link_count = n;
1865                 pipe_config->splitter.pixel_overlap = overlap;
1866
1867                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1868                             n, overlap);
1869
1870                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1871                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1872                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1873                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1874                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1875                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1876                 adjusted_mode->crtc_clock /= n;
1877         }
1878
1879         intel_link_compute_m_n(output_bpp,
1880                                pipe_config->lane_count,
1881                                adjusted_mode->crtc_clock,
1882                                pipe_config->port_clock,
1883                                &pipe_config->dp_m_n,
1884                                constant_n, pipe_config->fec_enable);
1885
1886         /* FIXME: abstract this better */
1887         if (pipe_config->splitter.enable)
1888                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
1889
1890         if (!HAS_DDI(dev_priv))
1891                 g4x_dp_set_clock(encoder, pipe_config);
1892
1893         intel_vrr_compute_config(pipe_config, conn_state);
1894         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
1895         intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1896                                   constant_n);
1897         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1898         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1899
1900         return 0;
1901 }
1902
1903 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1904                               int link_rate, int lane_count)
1905 {
1906         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
1907         intel_dp->link_trained = false;
1908         intel_dp->link_rate = link_rate;
1909         intel_dp->lane_count = lane_count;
1910 }
1911
1912 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
1913 {
1914         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1915         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1916 }
1917
1918 /* Enable backlight PWM and backlight PP control. */
1919 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1920                             const struct drm_connector_state *conn_state)
1921 {
1922         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1923         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1924
1925         if (!intel_dp_is_edp(intel_dp))
1926                 return;
1927
1928         drm_dbg_kms(&i915->drm, "\n");
1929
1930         intel_backlight_enable(crtc_state, conn_state);
1931         intel_pps_backlight_on(intel_dp);
1932 }
1933
1934 /* Disable backlight PP control and backlight PWM. */
1935 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1936 {
1937         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1938         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1939
1940         if (!intel_dp_is_edp(intel_dp))
1941                 return;
1942
1943         drm_dbg_kms(&i915->drm, "\n");
1944
1945         intel_pps_backlight_off(intel_dp);
1946         intel_backlight_disable(old_conn_state);
1947 }
1948
1949 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1950 {
1951         /*
1952          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1953          * be capable of signalling downstream hpd with a long pulse.
1954          * Whether or not that means D3 is safe to use is not clear,
1955          * but let's assume so until proven otherwise.
1956          *
1957          * FIXME should really check all downstream ports...
1958          */
1959         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1960                 drm_dp_is_branch(intel_dp->dpcd) &&
1961                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1962 }
1963
1964 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1965                                            const struct intel_crtc_state *crtc_state,
1966                                            bool enable)
1967 {
1968         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1969         int ret;
1970
1971         if (!crtc_state->dsc.compression_enable)
1972                 return;
1973
1974         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1975                                  enable ? DP_DECOMPRESSION_EN : 0);
1976         if (ret < 0)
1977                 drm_dbg_kms(&i915->drm,
1978                             "Failed to %s sink decompression state\n",
1979                             enabledisable(enable));
1980 }
1981
1982 static void
1983 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1984 {
1985         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1986         u8 oui[] = { 0x00, 0xaa, 0x01 };
1987         u8 buf[3] = { 0 };
1988
1989         /*
1990          * During driver init, we want to be careful and avoid changing the source OUI if it's
1991          * already set to what we want, so as to avoid clearing any state by accident
1992          */
1993         if (careful) {
1994                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1995                         drm_err(&i915->drm, "Failed to read source OUI\n");
1996
1997                 if (memcmp(oui, buf, sizeof(oui)) == 0)
1998                         return;
1999         }
2000
2001         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2002                 drm_err(&i915->drm, "Failed to write source OUI\n");
2003
2004         intel_dp->last_oui_write = jiffies;
2005 }
2006
2007 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2008 {
2009         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2010
2011         drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2012         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2013 }
2014
2015 /* If the device supports it, try to set the power state appropriately */
2016 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2017 {
2018         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2019         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2020         int ret, i;
2021
2022         /* Should have a valid DPCD by this point */
2023         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2024                 return;
2025
2026         if (mode != DP_SET_POWER_D0) {
2027                 if (downstream_hpd_needs_d0(intel_dp))
2028                         return;
2029
2030                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2031         } else {
2032                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2033
2034                 lspcon_resume(dp_to_dig_port(intel_dp));
2035
2036                 /* Write the source OUI as early as possible */
2037                 if (intel_dp_is_edp(intel_dp))
2038                         intel_edp_init_source_oui(intel_dp, false);
2039
2040                 /*
2041                  * When turning on, we need to retry for 1ms to give the sink
2042                  * time to wake up.
2043                  */
2044                 for (i = 0; i < 3; i++) {
2045                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2046                         if (ret == 1)
2047                                 break;
2048                         msleep(1);
2049                 }
2050
2051                 if (ret == 1 && lspcon->active)
2052                         lspcon_wait_pcon_mode(lspcon);
2053         }
2054
2055         if (ret != 1)
2056                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2057                             encoder->base.base.id, encoder->base.name,
2058                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2059 }
2060
2061 static bool
2062 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2063
2064 /**
2065  * intel_dp_sync_state - sync the encoder state during init/resume
2066  * @encoder: intel encoder to sync
2067  * @crtc_state: state for the CRTC connected to the encoder
2068  *
2069  * Sync any state stored in the encoder wrt. HW state during driver init
2070  * and system resume.
2071  */
2072 void intel_dp_sync_state(struct intel_encoder *encoder,
2073                          const struct intel_crtc_state *crtc_state)
2074 {
2075         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2076
2077         if (!crtc_state)
2078                 return;
2079
2080         /*
2081          * Don't clobber DPCD if it's been already read out during output
2082          * setup (eDP) or detect.
2083          */
2084         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2085                 intel_dp_get_dpcd(intel_dp);
2086
2087         intel_dp_reset_max_link_params(intel_dp);
2088 }
2089
2090 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2091                                     struct intel_crtc_state *crtc_state)
2092 {
2093         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2094         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2095
2096         /*
2097          * If BIOS has set an unsupported or non-standard link rate for some
2098          * reason force an encoder recompute and full modeset.
2099          */
2100         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2101                                 crtc_state->port_clock) < 0) {
2102                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2103                 crtc_state->uapi.connectors_changed = true;
2104                 return false;
2105         }
2106
2107         /*
2108          * FIXME hack to force full modeset when DSC is being used.
2109          *
2110          * As long as we do not have full state readout and config comparison
2111          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2112          * Remove once we have readout for DSC.
2113          */
2114         if (crtc_state->dsc.compression_enable) {
2115                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2116                 crtc_state->uapi.mode_changed = true;
2117                 return false;
2118         }
2119
2120         if (CAN_PSR(intel_dp)) {
2121                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2122                 crtc_state->uapi.mode_changed = true;
2123                 return false;
2124         }
2125
2126         return true;
2127 }
2128
2129 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2130 {
2131         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2132
2133         /* Clear the cached register set to avoid using stale values */
2134
2135         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2136
2137         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2138                              intel_dp->pcon_dsc_dpcd,
2139                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2140                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2141                         DP_PCON_DSC_ENCODER);
2142
2143         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2144                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2145 }
2146
2147 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2148 {
2149         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2150         int i;
2151
2152         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2153                 if (frl_bw_mask & (1 << i))
2154                         return bw_gbps[i];
2155         }
2156         return 0;
2157 }
2158
2159 static int intel_dp_pcon_set_frl_mask(int max_frl)
2160 {
2161         switch (max_frl) {
2162         case 48:
2163                 return DP_PCON_FRL_BW_MASK_48GBPS;
2164         case 40:
2165                 return DP_PCON_FRL_BW_MASK_40GBPS;
2166         case 32:
2167                 return DP_PCON_FRL_BW_MASK_32GBPS;
2168         case 24:
2169                 return DP_PCON_FRL_BW_MASK_24GBPS;
2170         case 18:
2171                 return DP_PCON_FRL_BW_MASK_18GBPS;
2172         case 9:
2173                 return DP_PCON_FRL_BW_MASK_9GBPS;
2174         }
2175
2176         return 0;
2177 }
2178
2179 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2180 {
2181         struct intel_connector *intel_connector = intel_dp->attached_connector;
2182         struct drm_connector *connector = &intel_connector->base;
2183         int max_frl_rate;
2184         int max_lanes, rate_per_lane;
2185         int max_dsc_lanes, dsc_rate_per_lane;
2186
2187         max_lanes = connector->display_info.hdmi.max_lanes;
2188         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2189         max_frl_rate = max_lanes * rate_per_lane;
2190
2191         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2192                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2193                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2194                 if (max_dsc_lanes && dsc_rate_per_lane)
2195                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2196         }
2197
2198         return max_frl_rate;
2199 }
2200
2201 static bool
2202 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2203                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2204 {
2205         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2206             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2207             *frl_trained_mask >= max_frl_bw_mask)
2208                 return true;
2209
2210         return false;
2211 }
2212
2213 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2214 {
2215 #define TIMEOUT_FRL_READY_MS 500
2216 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2217
2218         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2219         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2220         u8 max_frl_bw_mask = 0, frl_trained_mask;
2221         bool is_active;
2222
2223         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2224         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2225
2226         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2227         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2228
2229         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2230
2231         if (max_frl_bw <= 0)
2232                 return -EINVAL;
2233
2234         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2235         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2236
2237         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2238                 goto frl_trained;
2239
2240         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2241         if (ret < 0)
2242                 return ret;
2243         /* Wait for PCON to be FRL Ready */
2244         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2245
2246         if (!is_active)
2247                 return -ETIMEDOUT;
2248
2249         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2250                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2251         if (ret < 0)
2252                 return ret;
2253         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2254                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2255         if (ret < 0)
2256                 return ret;
2257         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2258         if (ret < 0)
2259                 return ret;
2260         /*
2261          * Wait for FRL to be completed
2262          * Check if the HDMI Link is up and active.
2263          */
2264         wait_for(is_active =
2265                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2266                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2267
2268         if (!is_active)
2269                 return -ETIMEDOUT;
2270
2271 frl_trained:
2272         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2273         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2274         intel_dp->frl.is_trained = true;
2275         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2276
2277         return 0;
2278 }
2279
2280 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2281 {
2282         if (drm_dp_is_branch(intel_dp->dpcd) &&
2283             intel_dp->has_hdmi_sink &&
2284             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2285                 return true;
2286
2287         return false;
2288 }
2289
2290 static
2291 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2292 {
2293         int ret;
2294         u8 buf = 0;
2295
2296         /* Set PCON source control mode */
2297         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2298
2299         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2300         if (ret < 0)
2301                 return ret;
2302
2303         /* Set HDMI LINK ENABLE */
2304         buf |= DP_PCON_ENABLE_HDMI_LINK;
2305         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2306         if (ret < 0)
2307                 return ret;
2308
2309         return 0;
2310 }
2311
2312 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2313 {
2314         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2315
2316         /*
2317          * Always go for FRL training if:
2318          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2319          * -sink is HDMI2.1
2320          */
2321         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2322             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2323             intel_dp->frl.is_trained)
2324                 return;
2325
2326         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2327                 int ret, mode;
2328
2329                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2330                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2331                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2332
2333                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2334                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2335         } else {
2336                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2337         }
2338 }
2339
2340 static int
2341 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2342 {
2343         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2344
2345         return intel_hdmi_dsc_get_slice_height(vactive);
2346 }
2347
2348 static int
2349 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2350                              const struct intel_crtc_state *crtc_state)
2351 {
2352         struct intel_connector *intel_connector = intel_dp->attached_connector;
2353         struct drm_connector *connector = &intel_connector->base;
2354         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2355         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2356         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2357         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2358
2359         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2360                                              pcon_max_slice_width,
2361                                              hdmi_max_slices, hdmi_throughput);
2362 }
2363
2364 static int
2365 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2366                           const struct intel_crtc_state *crtc_state,
2367                           int num_slices, int slice_width)
2368 {
2369         struct intel_connector *intel_connector = intel_dp->attached_connector;
2370         struct drm_connector *connector = &intel_connector->base;
2371         int output_format = crtc_state->output_format;
2372         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2373         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2374         int hdmi_max_chunk_bytes =
2375                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2376
2377         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2378                                       num_slices, output_format, hdmi_all_bpp,
2379                                       hdmi_max_chunk_bytes);
2380 }
2381
2382 void
2383 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2384                             const struct intel_crtc_state *crtc_state)
2385 {
2386         u8 pps_param[6];
2387         int slice_height;
2388         int slice_width;
2389         int num_slices;
2390         int bits_per_pixel;
2391         int ret;
2392         struct intel_connector *intel_connector = intel_dp->attached_connector;
2393         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2394         struct drm_connector *connector;
2395         bool hdmi_is_dsc_1_2;
2396
2397         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2398                 return;
2399
2400         if (!intel_connector)
2401                 return;
2402         connector = &intel_connector->base;
2403         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2404
2405         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2406             !hdmi_is_dsc_1_2)
2407                 return;
2408
2409         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2410         if (!slice_height)
2411                 return;
2412
2413         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2414         if (!num_slices)
2415                 return;
2416
2417         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2418                                    num_slices);
2419
2420         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2421                                                    num_slices, slice_width);
2422         if (!bits_per_pixel)
2423                 return;
2424
2425         pps_param[0] = slice_height & 0xFF;
2426         pps_param[1] = slice_height >> 8;
2427         pps_param[2] = slice_width & 0xFF;
2428         pps_param[3] = slice_width >> 8;
2429         pps_param[4] = bits_per_pixel & 0xFF;
2430         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2431
2432         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2433         if (ret < 0)
2434                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2435 }
2436
2437 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2438                                            const struct intel_crtc_state *crtc_state)
2439 {
2440         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2441         u8 tmp;
2442
2443         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2444                 return;
2445
2446         if (!drm_dp_is_branch(intel_dp->dpcd))
2447                 return;
2448
2449         tmp = intel_dp->has_hdmi_sink ?
2450                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2451
2452         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2453                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2454                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2455                             enabledisable(intel_dp->has_hdmi_sink));
2456
2457         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2458                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2459
2460         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2461                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2462                 drm_dbg_kms(&i915->drm,
2463                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2464                             enabledisable(intel_dp->dfp.ycbcr_444_to_420));
2465
2466         tmp = 0;
2467         if (intel_dp->dfp.rgb_to_ycbcr) {
2468                 bool bt2020, bt709;
2469
2470                 /*
2471                  * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2472                  * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2473                  *
2474                  */
2475                 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2476
2477                 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2478                                                                    intel_dp->downstream_ports,
2479                                                                    DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2480                 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2481                                                                   intel_dp->downstream_ports,
2482                                                                   DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2483                 switch (crtc_state->infoframes.vsc.colorimetry) {
2484                 case DP_COLORIMETRY_BT2020_RGB:
2485                 case DP_COLORIMETRY_BT2020_YCC:
2486                         if (bt2020)
2487                                 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2488                         break;
2489                 case DP_COLORIMETRY_BT709_YCC:
2490                 case DP_COLORIMETRY_XVYCC_709:
2491                         if (bt709)
2492                                 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2493                         break;
2494                 default:
2495                         break;
2496                 }
2497         }
2498
2499         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2500                 drm_dbg_kms(&i915->drm,
2501                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2502                            enabledisable(tmp));
2503 }
2504
2505
2506 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2507 {
2508         u8 dprx = 0;
2509
2510         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2511                               &dprx) != 1)
2512                 return false;
2513         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2514 }
2515
2516 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2517 {
2518         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2519
2520         /*
2521          * Clear the cached register set to avoid using stale values
2522          * for the sinks that do not support DSC.
2523          */
2524         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2525
2526         /* Clear fec_capable to avoid using stale values */
2527         intel_dp->fec_capable = 0;
2528
2529         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2530         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2531             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2532                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2533                                      intel_dp->dsc_dpcd,
2534                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2535                         drm_err(&i915->drm,
2536                                 "Failed to read DPCD register 0x%x\n",
2537                                 DP_DSC_SUPPORT);
2538
2539                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2540                             (int)sizeof(intel_dp->dsc_dpcd),
2541                             intel_dp->dsc_dpcd);
2542
2543                 /* FEC is supported only on DP 1.4 */
2544                 if (!intel_dp_is_edp(intel_dp) &&
2545                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2546                                       &intel_dp->fec_capable) < 0)
2547                         drm_err(&i915->drm,
2548                                 "Failed to read FEC DPCD register\n");
2549
2550                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2551                             intel_dp->fec_capable);
2552         }
2553 }
2554
2555 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2556                                      struct drm_display_mode *mode)
2557 {
2558         struct intel_dp *intel_dp = intel_attached_dp(connector);
2559         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2560         int n = intel_dp->mso_link_count;
2561         int overlap = intel_dp->mso_pixel_overlap;
2562
2563         if (!mode || !n)
2564                 return;
2565
2566         mode->hdisplay = (mode->hdisplay - overlap) * n;
2567         mode->hsync_start = (mode->hsync_start - overlap) * n;
2568         mode->hsync_end = (mode->hsync_end - overlap) * n;
2569         mode->htotal = (mode->htotal - overlap) * n;
2570         mode->clock *= n;
2571
2572         drm_mode_set_name(mode);
2573
2574         drm_dbg_kms(&i915->drm,
2575                     "[CONNECTOR:%d:%s] using generated MSO mode: ",
2576                     connector->base.base.id, connector->base.name);
2577         drm_mode_debug_printmodeline(mode);
2578 }
2579
2580 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2581 {
2582         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2583         struct intel_connector *connector = intel_dp->attached_connector;
2584         struct drm_display_info *info = &connector->base.display_info;
2585         u8 mso;
2586
2587         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2588                 return;
2589
2590         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2591                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2592                 return;
2593         }
2594
2595         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2596         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2597         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2598                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2599                 mso = 0;
2600         }
2601
2602         if (mso) {
2603                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2604                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2605                             info->mso_pixel_overlap);
2606                 if (!HAS_MSO(i915)) {
2607                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2608                         mso = 0;
2609                 }
2610         }
2611
2612         intel_dp->mso_link_count = mso;
2613         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2614 }
2615
2616 static bool
2617 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2618 {
2619         struct drm_i915_private *dev_priv =
2620                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2621
2622         /* this function is meant to be called only once */
2623         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2624
2625         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2626                 return false;
2627
2628         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2629                          drm_dp_is_branch(intel_dp->dpcd));
2630
2631         /*
2632          * Read the eDP display control registers.
2633          *
2634          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2635          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2636          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2637          * method). The display control registers should read zero if they're
2638          * not supported anyway.
2639          */
2640         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2641                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2642                              sizeof(intel_dp->edp_dpcd)) {
2643                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2644                             (int)sizeof(intel_dp->edp_dpcd),
2645                             intel_dp->edp_dpcd);
2646
2647                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2648         }
2649
2650         /*
2651          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2652          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2653          */
2654         intel_psr_init_dpcd(intel_dp);
2655
2656         /* Clear the default sink rates */
2657         intel_dp->num_sink_rates = 0;
2658
2659         /* Read the eDP 1.4+ supported link rates. */
2660         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2661                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2662                 int i;
2663
2664                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2665                                 sink_rates, sizeof(sink_rates));
2666
2667                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2668                         int val = le16_to_cpu(sink_rates[i]);
2669
2670                         if (val == 0)
2671                                 break;
2672
2673                         /* Value read multiplied by 200kHz gives the per-lane
2674                          * link rate in kHz. The source rates are, however,
2675                          * stored in terms of LS_Clk kHz. The full conversion
2676                          * back to symbols is
2677                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2678                          */
2679                         intel_dp->sink_rates[i] = (val * 200) / 10;
2680                 }
2681                 intel_dp->num_sink_rates = i;
2682         }
2683
2684         /*
2685          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2686          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2687          */
2688         if (intel_dp->num_sink_rates)
2689                 intel_dp->use_rate_select = true;
2690         else
2691                 intel_dp_set_sink_rates(intel_dp);
2692         intel_dp_set_max_sink_lane_count(intel_dp);
2693
2694         intel_dp_set_common_rates(intel_dp);
2695         intel_dp_reset_max_link_params(intel_dp);
2696
2697         /* Read the eDP DSC DPCD registers */
2698         if (DISPLAY_VER(dev_priv) >= 10)
2699                 intel_dp_get_dsc_sink_cap(intel_dp);
2700
2701         /*
2702          * If needed, program our source OUI so we can make various Intel-specific AUX services
2703          * available (such as HDR backlight controls)
2704          */
2705         intel_edp_init_source_oui(intel_dp, true);
2706
2707         return true;
2708 }
2709
2710 static bool
2711 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2712 {
2713         if (!intel_dp->attached_connector)
2714                 return false;
2715
2716         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2717                                           intel_dp->dpcd,
2718                                           &intel_dp->desc);
2719 }
2720
2721 static bool
2722 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2723 {
2724         int ret;
2725
2726         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2727                 return false;
2728
2729         /*
2730          * Don't clobber cached eDP rates. Also skip re-reading
2731          * the OUI/ID since we know it won't change.
2732          */
2733         if (!intel_dp_is_edp(intel_dp)) {
2734                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2735                                  drm_dp_is_branch(intel_dp->dpcd));
2736
2737                 intel_dp_set_sink_rates(intel_dp);
2738                 intel_dp_set_max_sink_lane_count(intel_dp);
2739                 intel_dp_set_common_rates(intel_dp);
2740         }
2741
2742         if (intel_dp_has_sink_count(intel_dp)) {
2743                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2744                 if (ret < 0)
2745                         return false;
2746
2747                 /*
2748                  * Sink count can change between short pulse hpd hence
2749                  * a member variable in intel_dp will track any changes
2750                  * between short pulse interrupts.
2751                  */
2752                 intel_dp->sink_count = ret;
2753
2754                 /*
2755                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2756                  * a dongle is present but no display. Unless we require to know
2757                  * if a dongle is present or not, we don't need to update
2758                  * downstream port information. So, an early return here saves
2759                  * time from performing other operations which are not required.
2760                  */
2761                 if (!intel_dp->sink_count)
2762                         return false;
2763         }
2764
2765         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2766                                            intel_dp->downstream_ports) == 0;
2767 }
2768
2769 static bool
2770 intel_dp_can_mst(struct intel_dp *intel_dp)
2771 {
2772         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2773
2774         return i915->params.enable_dp_mst &&
2775                 intel_dp_mst_source_support(intel_dp) &&
2776                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2777 }
2778
2779 static void
2780 intel_dp_configure_mst(struct intel_dp *intel_dp)
2781 {
2782         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2783         struct intel_encoder *encoder =
2784                 &dp_to_dig_port(intel_dp)->base;
2785         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2786
2787         drm_dbg_kms(&i915->drm,
2788                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2789                     encoder->base.base.id, encoder->base.name,
2790                     yesno(intel_dp_mst_source_support(intel_dp)), yesno(sink_can_mst),
2791                     yesno(i915->params.enable_dp_mst));
2792
2793         if (!intel_dp_mst_source_support(intel_dp))
2794                 return;
2795
2796         intel_dp->is_mst = sink_can_mst &&
2797                 i915->params.enable_dp_mst;
2798
2799         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2800                                         intel_dp->is_mst);
2801 }
2802
2803 static bool
2804 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
2805 {
2806         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
2807 }
2808
2809 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
2810 {
2811         int retry;
2812
2813         for (retry = 0; retry < 3; retry++) {
2814                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
2815                                       &esi[1], 3) == 3)
2816                         return true;
2817         }
2818
2819         return false;
2820 }
2821
2822 bool
2823 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2824                        const struct drm_connector_state *conn_state)
2825 {
2826         /*
2827          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2828          * of Color Encoding Format and Content Color Gamut], in order to
2829          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2830          */
2831         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2832                 return true;
2833
2834         switch (conn_state->colorspace) {
2835         case DRM_MODE_COLORIMETRY_SYCC_601:
2836         case DRM_MODE_COLORIMETRY_OPYCC_601:
2837         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2838         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2839         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2840                 return true;
2841         default:
2842                 break;
2843         }
2844
2845         return false;
2846 }
2847
2848 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2849                                      struct dp_sdp *sdp, size_t size)
2850 {
2851         size_t length = sizeof(struct dp_sdp);
2852
2853         if (size < length)
2854                 return -ENOSPC;
2855
2856         memset(sdp, 0, size);
2857
2858         /*
2859          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2860          * VSC SDP Header Bytes
2861          */
2862         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2863         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2864         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2865         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2866
2867         /*
2868          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2869          * per DP 1.4a spec.
2870          */
2871         if (vsc->revision != 0x5)
2872                 goto out;
2873
2874         /* VSC SDP Payload for DB16 through DB18 */
2875         /* Pixel Encoding and Colorimetry Formats  */
2876         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2877         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2878
2879         switch (vsc->bpc) {
2880         case 6:
2881                 /* 6bpc: 0x0 */
2882                 break;
2883         case 8:
2884                 sdp->db[17] = 0x1; /* DB17[3:0] */
2885                 break;
2886         case 10:
2887                 sdp->db[17] = 0x2;
2888                 break;
2889         case 12:
2890                 sdp->db[17] = 0x3;
2891                 break;
2892         case 16:
2893                 sdp->db[17] = 0x4;
2894                 break;
2895         default:
2896                 MISSING_CASE(vsc->bpc);
2897                 break;
2898         }
2899         /* Dynamic Range and Component Bit Depth */
2900         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2901                 sdp->db[17] |= 0x80;  /* DB17[7] */
2902
2903         /* Content Type */
2904         sdp->db[18] = vsc->content_type & 0x7;
2905
2906 out:
2907         return length;
2908 }
2909
2910 static ssize_t
2911 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
2912                                          const struct hdmi_drm_infoframe *drm_infoframe,
2913                                          struct dp_sdp *sdp,
2914                                          size_t size)
2915 {
2916         size_t length = sizeof(struct dp_sdp);
2917         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2918         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2919         ssize_t len;
2920
2921         if (size < length)
2922                 return -ENOSPC;
2923
2924         memset(sdp, 0, size);
2925
2926         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2927         if (len < 0) {
2928                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
2929                 return -ENOSPC;
2930         }
2931
2932         if (len != infoframe_size) {
2933                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
2934                 return -ENOSPC;
2935         }
2936
2937         /*
2938          * Set up the infoframe sdp packet for HDR static metadata.
2939          * Prepare VSC Header for SU as per DP 1.4a spec,
2940          * Table 2-100 and Table 2-101
2941          */
2942
2943         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2944         sdp->sdp_header.HB0 = 0;
2945         /*
2946          * Packet Type 80h + Non-audio INFOFRAME Type value
2947          * HDMI_INFOFRAME_TYPE_DRM: 0x87
2948          * - 80h + Non-audio INFOFRAME Type value
2949          * - InfoFrame Type: 0x07
2950          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2951          */
2952         sdp->sdp_header.HB1 = drm_infoframe->type;
2953         /*
2954          * Least Significant Eight Bits of (Data Byte Count – 1)
2955          * infoframe_size - 1
2956          */
2957         sdp->sdp_header.HB2 = 0x1D;
2958         /* INFOFRAME SDP Version Number */
2959         sdp->sdp_header.HB3 = (0x13 << 2);
2960         /* CTA Header Byte 2 (INFOFRAME Version Number) */
2961         sdp->db[0] = drm_infoframe->version;
2962         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2963         sdp->db[1] = drm_infoframe->length;
2964         /*
2965          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2966          * HDMI_INFOFRAME_HEADER_SIZE
2967          */
2968         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2969         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2970                HDMI_DRM_INFOFRAME_SIZE);
2971
2972         /*
2973          * Size of DP infoframe sdp packet for HDR static metadata consists of
2974          * - DP SDP Header(struct dp_sdp_header): 4 bytes
2975          * - Two Data Blocks: 2 bytes
2976          *    CTA Header Byte2 (INFOFRAME Version Number)
2977          *    CTA Header Byte3 (Length of INFOFRAME)
2978          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2979          *
2980          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2981          * infoframe size. But GEN11+ has larger than that size, write_infoframe
2982          * will pad rest of the size.
2983          */
2984         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2985 }
2986
2987 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2988                                const struct intel_crtc_state *crtc_state,
2989                                unsigned int type)
2990 {
2991         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2993         struct dp_sdp sdp = {};
2994         ssize_t len;
2995
2996         if ((crtc_state->infoframes.enable &
2997              intel_hdmi_infoframe_enable(type)) == 0)
2998                 return;
2999
3000         switch (type) {
3001         case DP_SDP_VSC:
3002                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3003                                             sizeof(sdp));
3004                 break;
3005         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3006                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3007                                                                &crtc_state->infoframes.drm.drm,
3008                                                                &sdp, sizeof(sdp));
3009                 break;
3010         default:
3011                 MISSING_CASE(type);
3012                 return;
3013         }
3014
3015         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3016                 return;
3017
3018         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3019 }
3020
3021 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3022                             const struct intel_crtc_state *crtc_state,
3023                             const struct drm_dp_vsc_sdp *vsc)
3024 {
3025         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3026         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3027         struct dp_sdp sdp = {};
3028         ssize_t len;
3029
3030         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3031
3032         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3033                 return;
3034
3035         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3036                                         &sdp, len);
3037 }
3038
3039 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3040                              bool enable,
3041                              const struct intel_crtc_state *crtc_state,
3042                              const struct drm_connector_state *conn_state)
3043 {
3044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3045         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3046         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3047                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3048                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3049         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3050
3051         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3052         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3053         if (!crtc_state->has_psr)
3054                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3055
3056         intel_de_write(dev_priv, reg, val);
3057         intel_de_posting_read(dev_priv, reg);
3058
3059         if (!enable)
3060                 return;
3061
3062         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3063         if (!crtc_state->has_psr)
3064                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3065
3066         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3067 }
3068
3069 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3070                                    const void *buffer, size_t size)
3071 {
3072         const struct dp_sdp *sdp = buffer;
3073
3074         if (size < sizeof(struct dp_sdp))
3075                 return -EINVAL;
3076
3077         memset(vsc, 0, sizeof(*vsc));
3078
3079         if (sdp->sdp_header.HB0 != 0)
3080                 return -EINVAL;
3081
3082         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3083                 return -EINVAL;
3084
3085         vsc->sdp_type = sdp->sdp_header.HB1;
3086         vsc->revision = sdp->sdp_header.HB2;
3087         vsc->length = sdp->sdp_header.HB3;
3088
3089         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3090             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3091                 /*
3092                  * - HB2 = 0x2, HB3 = 0x8
3093                  *   VSC SDP supporting 3D stereo + PSR
3094                  * - HB2 = 0x4, HB3 = 0xe
3095                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3096                  *   first scan line of the SU region (applies to eDP v1.4b
3097                  *   and higher).
3098                  */
3099                 return 0;
3100         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3101                 /*
3102                  * - HB2 = 0x5, HB3 = 0x13
3103                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3104                  *   Format.
3105                  */
3106                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3107                 vsc->colorimetry = sdp->db[16] & 0xf;
3108                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3109
3110                 switch (sdp->db[17] & 0x7) {
3111                 case 0x0:
3112                         vsc->bpc = 6;
3113                         break;
3114                 case 0x1:
3115                         vsc->bpc = 8;
3116                         break;
3117                 case 0x2:
3118                         vsc->bpc = 10;
3119                         break;
3120                 case 0x3:
3121                         vsc->bpc = 12;
3122                         break;
3123                 case 0x4:
3124                         vsc->bpc = 16;
3125                         break;
3126                 default:
3127                         MISSING_CASE(sdp->db[17] & 0x7);
3128                         return -EINVAL;
3129                 }
3130
3131                 vsc->content_type = sdp->db[18] & 0x7;
3132         } else {
3133                 return -EINVAL;
3134         }
3135
3136         return 0;
3137 }
3138
3139 static int
3140 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3141                                            const void *buffer, size_t size)
3142 {
3143         int ret;
3144
3145         const struct dp_sdp *sdp = buffer;
3146
3147         if (size < sizeof(struct dp_sdp))
3148                 return -EINVAL;
3149
3150         if (sdp->sdp_header.HB0 != 0)
3151                 return -EINVAL;
3152
3153         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3154                 return -EINVAL;
3155
3156         /*
3157          * Least Significant Eight Bits of (Data Byte Count – 1)
3158          * 1Dh (i.e., Data Byte Count = 30 bytes).
3159          */
3160         if (sdp->sdp_header.HB2 != 0x1D)
3161                 return -EINVAL;
3162
3163         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3164         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3165                 return -EINVAL;
3166
3167         /* INFOFRAME SDP Version Number */
3168         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3169                 return -EINVAL;
3170
3171         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3172         if (sdp->db[0] != 1)
3173                 return -EINVAL;
3174
3175         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3176         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3177                 return -EINVAL;
3178
3179         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3180                                              HDMI_DRM_INFOFRAME_SIZE);
3181
3182         return ret;
3183 }
3184
3185 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3186                                   struct intel_crtc_state *crtc_state,
3187                                   struct drm_dp_vsc_sdp *vsc)
3188 {
3189         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3190         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3191         unsigned int type = DP_SDP_VSC;
3192         struct dp_sdp sdp = {};
3193         int ret;
3194
3195         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3196         if (crtc_state->has_psr)
3197                 return;
3198
3199         if ((crtc_state->infoframes.enable &
3200              intel_hdmi_infoframe_enable(type)) == 0)
3201                 return;
3202
3203         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3204
3205         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3206
3207         if (ret)
3208                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3209 }
3210
3211 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3212                                                      struct intel_crtc_state *crtc_state,
3213                                                      struct hdmi_drm_infoframe *drm_infoframe)
3214 {
3215         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3216         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3217         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3218         struct dp_sdp sdp = {};
3219         int ret;
3220
3221         if ((crtc_state->infoframes.enable &
3222             intel_hdmi_infoframe_enable(type)) == 0)
3223                 return;
3224
3225         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3226                                  sizeof(sdp));
3227
3228         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3229                                                          sizeof(sdp));
3230
3231         if (ret)
3232                 drm_dbg_kms(&dev_priv->drm,
3233                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3234 }
3235
3236 void intel_read_dp_sdp(struct intel_encoder *encoder,
3237                        struct intel_crtc_state *crtc_state,
3238                        unsigned int type)
3239 {
3240         switch (type) {
3241         case DP_SDP_VSC:
3242                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3243                                       &crtc_state->infoframes.vsc);
3244                 break;
3245         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3246                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3247                                                          &crtc_state->infoframes.drm.drm);
3248                 break;
3249         default:
3250                 MISSING_CASE(type);
3251                 break;
3252         }
3253 }
3254
3255 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3256 {
3257         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3258         int status = 0;
3259         int test_link_rate;
3260         u8 test_lane_count, test_link_bw;
3261         /* (DP CTS 1.2)
3262          * 4.3.1.11
3263          */
3264         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3265         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3266                                    &test_lane_count);
3267
3268         if (status <= 0) {
3269                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3270                 return DP_TEST_NAK;
3271         }
3272         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3273
3274         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3275                                    &test_link_bw);
3276         if (status <= 0) {
3277                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3278                 return DP_TEST_NAK;
3279         }
3280         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3281
3282         /* Validate the requested link rate and lane count */
3283         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3284                                         test_lane_count))
3285                 return DP_TEST_NAK;
3286
3287         intel_dp->compliance.test_lane_count = test_lane_count;
3288         intel_dp->compliance.test_link_rate = test_link_rate;
3289
3290         return DP_TEST_ACK;
3291 }
3292
3293 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3294 {
3295         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3296         u8 test_pattern;
3297         u8 test_misc;
3298         __be16 h_width, v_height;
3299         int status = 0;
3300
3301         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3302         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3303                                    &test_pattern);
3304         if (status <= 0) {
3305                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3306                 return DP_TEST_NAK;
3307         }
3308         if (test_pattern != DP_COLOR_RAMP)
3309                 return DP_TEST_NAK;
3310
3311         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3312                                   &h_width, 2);
3313         if (status <= 0) {
3314                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3315                 return DP_TEST_NAK;
3316         }
3317
3318         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3319                                   &v_height, 2);
3320         if (status <= 0) {
3321                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3322                 return DP_TEST_NAK;
3323         }
3324
3325         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3326                                    &test_misc);
3327         if (status <= 0) {
3328                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3329                 return DP_TEST_NAK;
3330         }
3331         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3332                 return DP_TEST_NAK;
3333         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3334                 return DP_TEST_NAK;
3335         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3336         case DP_TEST_BIT_DEPTH_6:
3337                 intel_dp->compliance.test_data.bpc = 6;
3338                 break;
3339         case DP_TEST_BIT_DEPTH_8:
3340                 intel_dp->compliance.test_data.bpc = 8;
3341                 break;
3342         default:
3343                 return DP_TEST_NAK;
3344         }
3345
3346         intel_dp->compliance.test_data.video_pattern = test_pattern;
3347         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3348         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3349         /* Set test active flag here so userspace doesn't interrupt things */
3350         intel_dp->compliance.test_active = true;
3351
3352         return DP_TEST_ACK;
3353 }
3354
3355 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3356 {
3357         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3358         u8 test_result = DP_TEST_ACK;
3359         struct intel_connector *intel_connector = intel_dp->attached_connector;
3360         struct drm_connector *connector = &intel_connector->base;
3361
3362         if (intel_connector->detect_edid == NULL ||
3363             connector->edid_corrupt ||
3364             intel_dp->aux.i2c_defer_count > 6) {
3365                 /* Check EDID read for NACKs, DEFERs and corruption
3366                  * (DP CTS 1.2 Core r1.1)
3367                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3368                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3369                  *    4.2.2.6 : EDID corruption detected
3370                  * Use failsafe mode for all cases
3371                  */
3372                 if (intel_dp->aux.i2c_nack_count > 0 ||
3373                         intel_dp->aux.i2c_defer_count > 0)
3374                         drm_dbg_kms(&i915->drm,
3375                                     "EDID read had %d NACKs, %d DEFERs\n",
3376                                     intel_dp->aux.i2c_nack_count,
3377                                     intel_dp->aux.i2c_defer_count);
3378                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3379         } else {
3380                 struct edid *block = intel_connector->detect_edid;
3381
3382                 /* We have to write the checksum
3383                  * of the last block read
3384                  */
3385                 block += intel_connector->detect_edid->extensions;
3386
3387                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3388                                        block->checksum) <= 0)
3389                         drm_dbg_kms(&i915->drm,
3390                                     "Failed to write EDID checksum\n");
3391
3392                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3393                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3394         }
3395
3396         /* Set test active flag here so userspace doesn't interrupt things */
3397         intel_dp->compliance.test_active = true;
3398
3399         return test_result;
3400 }
3401
3402 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3403                                         const struct intel_crtc_state *crtc_state)
3404 {
3405         struct drm_i915_private *dev_priv =
3406                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3407         struct drm_dp_phy_test_params *data =
3408                         &intel_dp->compliance.test_data.phytest;
3409         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3410         enum pipe pipe = crtc->pipe;
3411         u32 pattern_val;
3412
3413         switch (data->phy_pattern) {
3414         case DP_PHY_TEST_PATTERN_NONE:
3415                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3416                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3417                 break;
3418         case DP_PHY_TEST_PATTERN_D10_2:
3419                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3420                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3421                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3422                 break;
3423         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3424                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3425                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3426                                DDI_DP_COMP_CTL_ENABLE |
3427                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3428                 break;
3429         case DP_PHY_TEST_PATTERN_PRBS7:
3430                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3431                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3432                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3433                 break;
3434         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3435                 /*
3436                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3437                  * current firmware of DPR-100 could not set it, so hardcoding
3438                  * now for complaince test.
3439                  */
3440                 drm_dbg_kms(&dev_priv->drm,
3441                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3442                 pattern_val = 0x3e0f83e0;
3443                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3444                 pattern_val = 0x0f83e0f8;
3445                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3446                 pattern_val = 0x0000f83e;
3447                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3448                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3449                                DDI_DP_COMP_CTL_ENABLE |
3450                                DDI_DP_COMP_CTL_CUSTOM80);
3451                 break;
3452         case DP_PHY_TEST_PATTERN_CP2520:
3453                 /*
3454                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3455                  * current firmware of DPR-100 could not set it, so hardcoding
3456                  * now for complaince test.
3457                  */
3458                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3459                 pattern_val = 0xFB;
3460                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3461                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3462                                pattern_val);
3463                 break;
3464         default:
3465                 WARN(1, "Invalid Phy Test Pattern\n");
3466         }
3467 }
3468
3469 static void
3470 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3471                                   const struct intel_crtc_state *crtc_state)
3472 {
3473         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3474         struct drm_device *dev = dig_port->base.base.dev;
3475         struct drm_i915_private *dev_priv = to_i915(dev);
3476         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3477         enum pipe pipe = crtc->pipe;
3478         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3479
3480         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3481                                                  TRANS_DDI_FUNC_CTL(pipe));
3482         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3483         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3484
3485         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3486                                       TGL_TRANS_DDI_PORT_MASK);
3487         trans_conf_value &= ~PIPECONF_ENABLE;
3488         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3489
3490         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3491         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3492                        trans_ddi_func_ctl_value);
3493         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3494 }
3495
3496 static void
3497 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3498                                  const struct intel_crtc_state *crtc_state)
3499 {
3500         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3501         struct drm_device *dev = dig_port->base.base.dev;
3502         struct drm_i915_private *dev_priv = to_i915(dev);
3503         enum port port = dig_port->base.port;
3504         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3505         enum pipe pipe = crtc->pipe;
3506         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3507
3508         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3509                                                  TRANS_DDI_FUNC_CTL(pipe));
3510         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3511         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3512
3513         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3514                                     TGL_TRANS_DDI_SELECT_PORT(port);
3515         trans_conf_value |= PIPECONF_ENABLE;
3516         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3517
3518         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3519         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3520         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3521                        trans_ddi_func_ctl_value);
3522 }
3523
3524 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3525                                          const struct intel_crtc_state *crtc_state)
3526 {
3527         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3528         struct drm_dp_phy_test_params *data =
3529                 &intel_dp->compliance.test_data.phytest;
3530         u8 link_status[DP_LINK_STATUS_SIZE];
3531
3532         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3533                                              link_status) < 0) {
3534                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3535                 return;
3536         }
3537
3538         /* retrieve vswing & pre-emphasis setting */
3539         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3540                                   link_status);
3541
3542         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3543
3544         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3545
3546         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3547
3548         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3549
3550         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3551                           intel_dp->train_set, crtc_state->lane_count);
3552
3553         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3554                                     link_status[DP_DPCD_REV]);
3555 }
3556
3557 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3558 {
3559         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3560         struct drm_dp_phy_test_params *data =
3561                 &intel_dp->compliance.test_data.phytest;
3562
3563         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3564                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3565                 return DP_TEST_NAK;
3566         }
3567
3568         /* Set test active flag here so userspace doesn't interrupt things */
3569         intel_dp->compliance.test_active = true;
3570
3571         return DP_TEST_ACK;
3572 }
3573
3574 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3575 {
3576         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3577         u8 response = DP_TEST_NAK;
3578         u8 request = 0;
3579         int status;
3580
3581         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3582         if (status <= 0) {
3583                 drm_dbg_kms(&i915->drm,
3584                             "Could not read test request from sink\n");
3585                 goto update_status;
3586         }
3587
3588         switch (request) {
3589         case DP_TEST_LINK_TRAINING:
3590                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3591                 response = intel_dp_autotest_link_training(intel_dp);
3592                 break;
3593         case DP_TEST_LINK_VIDEO_PATTERN:
3594                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3595                 response = intel_dp_autotest_video_pattern(intel_dp);
3596                 break;
3597         case DP_TEST_LINK_EDID_READ:
3598                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3599                 response = intel_dp_autotest_edid(intel_dp);
3600                 break;
3601         case DP_TEST_LINK_PHY_TEST_PATTERN:
3602                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3603                 response = intel_dp_autotest_phy_pattern(intel_dp);
3604                 break;
3605         default:
3606                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3607                             request);
3608                 break;
3609         }
3610
3611         if (response & DP_TEST_ACK)
3612                 intel_dp->compliance.test_type = request;
3613
3614 update_status:
3615         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3616         if (status <= 0)
3617                 drm_dbg_kms(&i915->drm,
3618                             "Could not write test response to sink\n");
3619 }
3620
3621 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3622                              u8 link_status[DP_LINK_STATUS_SIZE])
3623 {
3624         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3625         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3626         bool uhbr = intel_dp->link_rate >= 1000000;
3627         bool ok;
3628
3629         if (uhbr)
3630                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3631                                                           intel_dp->lane_count);
3632         else
3633                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3634
3635         if (ok)
3636                 return true;
3637
3638         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3639         drm_dbg_kms(&i915->drm,
3640                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
3641                     encoder->base.base.id, encoder->base.name,
3642                     uhbr ? "128b/132b" : "8b/10b");
3643
3644         return false;
3645 }
3646
3647 static void
3648 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3649 {
3650         bool handled = false;
3651
3652         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3653         if (handled)
3654                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3655
3656         if (esi[1] & DP_CP_IRQ) {
3657                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3658                 ack[1] |= DP_CP_IRQ;
3659         }
3660 }
3661
3662 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3663 {
3664         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3665         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3666         u8 link_status[DP_LINK_STATUS_SIZE] = {};
3667         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3668
3669         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3670                              esi_link_status_size) != esi_link_status_size) {
3671                 drm_err(&i915->drm,
3672                         "[ENCODER:%d:%s] Failed to read link status\n",
3673                         encoder->base.base.id, encoder->base.name);
3674                 return false;
3675         }
3676
3677         return intel_dp_link_ok(intel_dp, link_status);
3678 }
3679
3680 /**
3681  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3682  * @intel_dp: Intel DP struct
3683  *
3684  * Read any pending MST interrupts, call MST core to handle these and ack the
3685  * interrupts. Check if the main and AUX link state is ok.
3686  *
3687  * Returns:
3688  * - %true if pending interrupts were serviced (or no interrupts were
3689  *   pending) w/o detecting an error condition.
3690  * - %false if an error condition - like AUX failure or a loss of link - is
3691  *   detected, which needs servicing from the hotplug work.
3692  */
3693 static bool
3694 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3695 {
3696         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3697         bool link_ok = true;
3698
3699         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3700
3701         for (;;) {
3702                 u8 esi[4] = {};
3703                 u8 ack[4] = {};
3704
3705                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3706                         drm_dbg_kms(&i915->drm,
3707                                     "failed to get ESI - device may have failed\n");
3708                         link_ok = false;
3709
3710                         break;
3711                 }
3712
3713                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3714
3715                 if (intel_dp->active_mst_links > 0 && link_ok &&
3716                     esi[3] & LINK_STATUS_CHANGED) {
3717                         if (!intel_dp_mst_link_status(intel_dp))
3718                                 link_ok = false;
3719                         ack[3] |= LINK_STATUS_CHANGED;
3720                 }
3721
3722                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3723
3724                 if (!memchr_inv(ack, 0, sizeof(ack)))
3725                         break;
3726
3727                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3728                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3729         }
3730
3731         return link_ok;
3732 }
3733
3734 static void
3735 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3736 {
3737         bool is_active;
3738         u8 buf = 0;
3739
3740         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3741         if (intel_dp->frl.is_trained && !is_active) {
3742                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3743                         return;
3744
3745                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3746                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3747                         return;
3748
3749                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3750
3751                 /* Restart FRL training or fall back to TMDS mode */
3752                 intel_dp_check_frl_training(intel_dp);
3753         }
3754 }
3755
3756 static bool
3757 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3758 {
3759         u8 link_status[DP_LINK_STATUS_SIZE];
3760
3761         if (!intel_dp->link_trained)
3762                 return false;
3763
3764         /*
3765          * While PSR source HW is enabled, it will control main-link sending
3766          * frames, enabling and disabling it so trying to do a retrain will fail
3767          * as the link would or not be on or it could mix training patterns
3768          * and frame data at the same time causing retrain to fail.
3769          * Also when exiting PSR, HW will retrain the link anyways fixing
3770          * any link status error.
3771          */
3772         if (intel_psr_enabled(intel_dp))
3773                 return false;
3774
3775         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3776                                              link_status) < 0)
3777                 return false;
3778
3779         /*
3780          * Validate the cached values of intel_dp->link_rate and
3781          * intel_dp->lane_count before attempting to retrain.
3782          *
3783          * FIXME would be nice to user the crtc state here, but since
3784          * we need to call this from the short HPD handler that seems
3785          * a bit hard.
3786          */
3787         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3788                                         intel_dp->lane_count))
3789                 return false;
3790
3791         /* Retrain if link not ok */
3792         return !intel_dp_link_ok(intel_dp, link_status);
3793 }
3794
3795 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3796                                    const struct drm_connector_state *conn_state)
3797 {
3798         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3799         struct intel_encoder *encoder;
3800         enum pipe pipe;
3801
3802         if (!conn_state->best_encoder)
3803                 return false;
3804
3805         /* SST */
3806         encoder = &dp_to_dig_port(intel_dp)->base;
3807         if (conn_state->best_encoder == &encoder->base)
3808                 return true;
3809
3810         /* MST */
3811         for_each_pipe(i915, pipe) {
3812                 encoder = &intel_dp->mst_encoders[pipe]->base;
3813                 if (conn_state->best_encoder == &encoder->base)
3814                         return true;
3815         }
3816
3817         return false;
3818 }
3819
3820 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3821                                       struct drm_modeset_acquire_ctx *ctx,
3822                                       u8 *pipe_mask)
3823 {
3824         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3825         struct drm_connector_list_iter conn_iter;
3826         struct intel_connector *connector;
3827         int ret = 0;
3828
3829         *pipe_mask = 0;
3830
3831         if (!intel_dp_needs_link_retrain(intel_dp))
3832                 return 0;
3833
3834         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3835         for_each_intel_connector_iter(connector, &conn_iter) {
3836                 struct drm_connector_state *conn_state =
3837                         connector->base.state;
3838                 struct intel_crtc_state *crtc_state;
3839                 struct intel_crtc *crtc;
3840
3841                 if (!intel_dp_has_connector(intel_dp, conn_state))
3842                         continue;
3843
3844                 crtc = to_intel_crtc(conn_state->crtc);
3845                 if (!crtc)
3846                         continue;
3847
3848                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3849                 if (ret)
3850                         break;
3851
3852                 crtc_state = to_intel_crtc_state(crtc->base.state);
3853
3854                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3855
3856                 if (!crtc_state->hw.active)
3857                         continue;
3858
3859                 if (conn_state->commit &&
3860                     !try_wait_for_completion(&conn_state->commit->hw_done))
3861                         continue;
3862
3863                 *pipe_mask |= BIT(crtc->pipe);
3864         }
3865         drm_connector_list_iter_end(&conn_iter);
3866
3867         if (!intel_dp_needs_link_retrain(intel_dp))
3868                 *pipe_mask = 0;
3869
3870         return ret;
3871 }
3872
3873 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3874 {
3875         struct intel_connector *connector = intel_dp->attached_connector;
3876
3877         return connector->base.status == connector_status_connected ||
3878                 intel_dp->is_mst;
3879 }
3880
3881 int intel_dp_retrain_link(struct intel_encoder *encoder,
3882                           struct drm_modeset_acquire_ctx *ctx)
3883 {
3884         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3885         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3886         struct intel_crtc *crtc;
3887         u8 pipe_mask;
3888         int ret;
3889
3890         if (!intel_dp_is_connected(intel_dp))
3891                 return 0;
3892
3893         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3894                                ctx);
3895         if (ret)
3896                 return ret;
3897
3898         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
3899         if (ret)
3900                 return ret;
3901
3902         if (pipe_mask == 0)
3903                 return 0;
3904
3905         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3906                     encoder->base.base.id, encoder->base.name);
3907
3908         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
3909                 const struct intel_crtc_state *crtc_state =
3910                         to_intel_crtc_state(crtc->base.state);
3911
3912                 /* Suppress underruns caused by re-training */
3913                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3914                 if (crtc_state->has_pch_encoder)
3915                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3916                                                               intel_crtc_pch_transcoder(crtc), false);
3917         }
3918
3919         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
3920                 const struct intel_crtc_state *crtc_state =
3921                         to_intel_crtc_state(crtc->base.state);
3922
3923                 /* retrain on the MST master transcoder */
3924                 if (DISPLAY_VER(dev_priv) >= 12 &&
3925                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3926                     !intel_dp_mst_is_master_trans(crtc_state))
3927                         continue;
3928
3929                 intel_dp_check_frl_training(intel_dp);
3930                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3931                 intel_dp_start_link_train(intel_dp, crtc_state);
3932                 intel_dp_stop_link_train(intel_dp, crtc_state);
3933                 break;
3934         }
3935
3936         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
3937                 const struct intel_crtc_state *crtc_state =
3938                         to_intel_crtc_state(crtc->base.state);
3939
3940                 /* Keep underrun reporting disabled until things are stable */
3941                 intel_crtc_wait_for_next_vblank(crtc);
3942
3943                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3944                 if (crtc_state->has_pch_encoder)
3945                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3946                                                               intel_crtc_pch_transcoder(crtc), true);
3947         }
3948
3949         return 0;
3950 }
3951
3952 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3953                                   struct drm_modeset_acquire_ctx *ctx,
3954                                   u8 *pipe_mask)
3955 {
3956         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3957         struct drm_connector_list_iter conn_iter;
3958         struct intel_connector *connector;
3959         int ret = 0;
3960
3961         *pipe_mask = 0;
3962
3963         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3964         for_each_intel_connector_iter(connector, &conn_iter) {
3965                 struct drm_connector_state *conn_state =
3966                         connector->base.state;
3967                 struct intel_crtc_state *crtc_state;
3968                 struct intel_crtc *crtc;
3969
3970                 if (!intel_dp_has_connector(intel_dp, conn_state))
3971                         continue;
3972
3973                 crtc = to_intel_crtc(conn_state->crtc);
3974                 if (!crtc)
3975                         continue;
3976
3977                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3978                 if (ret)
3979                         break;
3980
3981                 crtc_state = to_intel_crtc_state(crtc->base.state);
3982
3983                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3984
3985                 if (!crtc_state->hw.active)
3986                         continue;
3987
3988                 if (conn_state->commit &&
3989                     !try_wait_for_completion(&conn_state->commit->hw_done))
3990                         continue;
3991
3992                 *pipe_mask |= BIT(crtc->pipe);
3993         }
3994         drm_connector_list_iter_end(&conn_iter);
3995
3996         return ret;
3997 }
3998
3999 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4000                                 struct drm_modeset_acquire_ctx *ctx)
4001 {
4002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4003         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4004         struct intel_crtc *crtc;
4005         u8 pipe_mask;
4006         int ret;
4007
4008         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4009                                ctx);
4010         if (ret)
4011                 return ret;
4012
4013         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4014         if (ret)
4015                 return ret;
4016
4017         if (pipe_mask == 0)
4018                 return 0;
4019
4020         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4021                     encoder->base.base.id, encoder->base.name);
4022
4023         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4024                 const struct intel_crtc_state *crtc_state =
4025                         to_intel_crtc_state(crtc->base.state);
4026
4027                 /* test on the MST master transcoder */
4028                 if (DISPLAY_VER(dev_priv) >= 12 &&
4029                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4030                     !intel_dp_mst_is_master_trans(crtc_state))
4031                         continue;
4032
4033                 intel_dp_process_phy_request(intel_dp, crtc_state);
4034                 break;
4035         }
4036
4037         return 0;
4038 }
4039
4040 void intel_dp_phy_test(struct intel_encoder *encoder)
4041 {
4042         struct drm_modeset_acquire_ctx ctx;
4043         int ret;
4044
4045         drm_modeset_acquire_init(&ctx, 0);
4046
4047         for (;;) {
4048                 ret = intel_dp_do_phy_test(encoder, &ctx);
4049
4050                 if (ret == -EDEADLK) {
4051                         drm_modeset_backoff(&ctx);
4052                         continue;
4053                 }
4054
4055                 break;
4056         }
4057
4058         drm_modeset_drop_locks(&ctx);
4059         drm_modeset_acquire_fini(&ctx);
4060         drm_WARN(encoder->base.dev, ret,
4061                  "Acquiring modeset locks failed with %i\n", ret);
4062 }
4063
4064 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4065 {
4066         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4067         u8 val;
4068
4069         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4070                 return;
4071
4072         if (drm_dp_dpcd_readb(&intel_dp->aux,
4073                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4074                 return;
4075
4076         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4077
4078         if (val & DP_AUTOMATED_TEST_REQUEST)
4079                 intel_dp_handle_test_request(intel_dp);
4080
4081         if (val & DP_CP_IRQ)
4082                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4083
4084         if (val & DP_SINK_SPECIFIC_IRQ)
4085                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4086 }
4087
4088 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4089 {
4090         u8 val;
4091
4092         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4093                 return;
4094
4095         if (drm_dp_dpcd_readb(&intel_dp->aux,
4096                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4097                 return;
4098
4099         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4100                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4101                 return;
4102
4103         if (val & HDMI_LINK_STATUS_CHANGED)
4104                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4105 }
4106
4107 /*
4108  * According to DP spec
4109  * 5.1.2:
4110  *  1. Read DPCD
4111  *  2. Configure link according to Receiver Capabilities
4112  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4113  *  4. Check link status on receipt of hot-plug interrupt
4114  *
4115  * intel_dp_short_pulse -  handles short pulse interrupts
4116  * when full detection is not required.
4117  * Returns %true if short pulse is handled and full detection
4118  * is NOT required and %false otherwise.
4119  */
4120 static bool
4121 intel_dp_short_pulse(struct intel_dp *intel_dp)
4122 {
4123         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4124         u8 old_sink_count = intel_dp->sink_count;
4125         bool ret;
4126
4127         /*
4128          * Clearing compliance test variables to allow capturing
4129          * of values for next automated test request.
4130          */
4131         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4132
4133         /*
4134          * Now read the DPCD to see if it's actually running
4135          * If the current value of sink count doesn't match with
4136          * the value that was stored earlier or dpcd read failed
4137          * we need to do full detection
4138          */
4139         ret = intel_dp_get_dpcd(intel_dp);
4140
4141         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4142                 /* No need to proceed if we are going to do full detect */
4143                 return false;
4144         }
4145
4146         intel_dp_check_device_service_irq(intel_dp);
4147         intel_dp_check_link_service_irq(intel_dp);
4148
4149         /* Handle CEC interrupts, if any */
4150         drm_dp_cec_irq(&intel_dp->aux);
4151
4152         /* defer to the hotplug work for link retraining if needed */
4153         if (intel_dp_needs_link_retrain(intel_dp))
4154                 return false;
4155
4156         intel_psr_short_pulse(intel_dp);
4157
4158         switch (intel_dp->compliance.test_type) {
4159         case DP_TEST_LINK_TRAINING:
4160                 drm_dbg_kms(&dev_priv->drm,
4161                             "Link Training Compliance Test requested\n");
4162                 /* Send a Hotplug Uevent to userspace to start modeset */
4163                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4164                 break;
4165         case DP_TEST_LINK_PHY_TEST_PATTERN:
4166                 drm_dbg_kms(&dev_priv->drm,
4167                             "PHY test pattern Compliance Test requested\n");
4168                 /*
4169                  * Schedule long hpd to do the test
4170                  *
4171                  * FIXME get rid of the ad-hoc phy test modeset code
4172                  * and properly incorporate it into the normal modeset.
4173                  */
4174                 return false;
4175         }
4176
4177         return true;
4178 }
4179
4180 /* XXX this is probably wrong for multiple downstream ports */
4181 static enum drm_connector_status
4182 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4183 {
4184         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4185         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4186         u8 *dpcd = intel_dp->dpcd;
4187         u8 type;
4188
4189         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4190                 return connector_status_connected;
4191
4192         lspcon_resume(dig_port);
4193
4194         if (!intel_dp_get_dpcd(intel_dp))
4195                 return connector_status_disconnected;
4196
4197         /* if there's no downstream port, we're done */
4198         if (!drm_dp_is_branch(dpcd))
4199                 return connector_status_connected;
4200
4201         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4202         if (intel_dp_has_sink_count(intel_dp) &&
4203             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4204                 return intel_dp->sink_count ?
4205                 connector_status_connected : connector_status_disconnected;
4206         }
4207
4208         if (intel_dp_can_mst(intel_dp))
4209                 return connector_status_connected;
4210
4211         /* If no HPD, poke DDC gently */
4212         if (drm_probe_ddc(&intel_dp->aux.ddc))
4213                 return connector_status_connected;
4214
4215         /* Well we tried, say unknown for unreliable port types */
4216         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4217                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4218                 if (type == DP_DS_PORT_TYPE_VGA ||
4219                     type == DP_DS_PORT_TYPE_NON_EDID)
4220                         return connector_status_unknown;
4221         } else {
4222                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4223                         DP_DWN_STRM_PORT_TYPE_MASK;
4224                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4225                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4226                         return connector_status_unknown;
4227         }
4228
4229         /* Anything else is out of spec, warn and ignore */
4230         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4231         return connector_status_disconnected;
4232 }
4233
4234 static enum drm_connector_status
4235 edp_detect(struct intel_dp *intel_dp)
4236 {
4237         return connector_status_connected;
4238 }
4239
4240 /*
4241  * intel_digital_port_connected - is the specified port connected?
4242  * @encoder: intel_encoder
4243  *
4244  * In cases where there's a connector physically connected but it can't be used
4245  * by our hardware we also return false, since the rest of the driver should
4246  * pretty much treat the port as disconnected. This is relevant for type-C
4247  * (starting on ICL) where there's ownership involved.
4248  *
4249  * Return %true if port is connected, %false otherwise.
4250  */
4251 bool intel_digital_port_connected(struct intel_encoder *encoder)
4252 {
4253         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4254         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4255         bool is_connected = false;
4256         intel_wakeref_t wakeref;
4257
4258         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4259                 is_connected = dig_port->connected(encoder);
4260
4261         return is_connected;
4262 }
4263
4264 static struct edid *
4265 intel_dp_get_edid(struct intel_dp *intel_dp)
4266 {
4267         struct intel_connector *intel_connector = intel_dp->attached_connector;
4268
4269         /* use cached edid if we have one */
4270         if (intel_connector->edid) {
4271                 /* invalid edid */
4272                 if (IS_ERR(intel_connector->edid))
4273                         return NULL;
4274
4275                 return drm_edid_duplicate(intel_connector->edid);
4276         } else
4277                 return drm_get_edid(&intel_connector->base,
4278                                     &intel_dp->aux.ddc);
4279 }
4280
4281 static void
4282 intel_dp_update_dfp(struct intel_dp *intel_dp,
4283                     const struct edid *edid)
4284 {
4285         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4286         struct intel_connector *connector = intel_dp->attached_connector;
4287
4288         intel_dp->dfp.max_bpc =
4289                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4290                                           intel_dp->downstream_ports, edid);
4291
4292         intel_dp->dfp.max_dotclock =
4293                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4294                                                intel_dp->downstream_ports);
4295
4296         intel_dp->dfp.min_tmds_clock =
4297                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4298                                                  intel_dp->downstream_ports,
4299                                                  edid);
4300         intel_dp->dfp.max_tmds_clock =
4301                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4302                                                  intel_dp->downstream_ports,
4303                                                  edid);
4304
4305         intel_dp->dfp.pcon_max_frl_bw =
4306                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4307                                            intel_dp->downstream_ports);
4308
4309         drm_dbg_kms(&i915->drm,
4310                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4311                     connector->base.base.id, connector->base.name,
4312                     intel_dp->dfp.max_bpc,
4313                     intel_dp->dfp.max_dotclock,
4314                     intel_dp->dfp.min_tmds_clock,
4315                     intel_dp->dfp.max_tmds_clock,
4316                     intel_dp->dfp.pcon_max_frl_bw);
4317
4318         intel_dp_get_pcon_dsc_cap(intel_dp);
4319 }
4320
4321 static void
4322 intel_dp_update_420(struct intel_dp *intel_dp)
4323 {
4324         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4325         struct intel_connector *connector = intel_dp->attached_connector;
4326         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4327
4328         /* No YCbCr output support on gmch platforms */
4329         if (HAS_GMCH(i915))
4330                 return;
4331
4332         /*
4333          * ILK doesn't seem capable of DP YCbCr output. The
4334          * displayed image is severly corrupted. SNB+ is fine.
4335          */
4336         if (IS_IRONLAKE(i915))
4337                 return;
4338
4339         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4340         ycbcr_420_passthrough =
4341                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4342                                                   intel_dp->downstream_ports);
4343         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4344         ycbcr_444_to_420 =
4345                 dp_to_dig_port(intel_dp)->lspcon.active ||
4346                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4347                                                         intel_dp->downstream_ports);
4348         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4349                                                                  intel_dp->downstream_ports,
4350                                                                  DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4351                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4352                                                                  DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4353
4354         if (DISPLAY_VER(i915) >= 11) {
4355                 /* Let PCON convert from RGB->YCbCr if possible */
4356                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4357                         intel_dp->dfp.rgb_to_ycbcr = true;
4358                         intel_dp->dfp.ycbcr_444_to_420 = true;
4359                         connector->base.ycbcr_420_allowed = true;
4360                 } else {
4361                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4362                         intel_dp->dfp.ycbcr_444_to_420 =
4363                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4364
4365                         connector->base.ycbcr_420_allowed =
4366                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4367                 }
4368         } else {
4369                 /* 4:4:4->4:2:0 conversion is the only way */
4370                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4371
4372                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4373         }
4374
4375         drm_dbg_kms(&i915->drm,
4376                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4377                     connector->base.base.id, connector->base.name,
4378                     yesno(intel_dp->dfp.rgb_to_ycbcr),
4379                     yesno(connector->base.ycbcr_420_allowed),
4380                     yesno(intel_dp->dfp.ycbcr_444_to_420));
4381 }
4382
4383 static void
4384 intel_dp_set_edid(struct intel_dp *intel_dp)
4385 {
4386         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4387         struct intel_connector *connector = intel_dp->attached_connector;
4388         struct edid *edid;
4389         bool vrr_capable;
4390
4391         intel_dp_unset_edid(intel_dp);
4392         edid = intel_dp_get_edid(intel_dp);
4393         connector->detect_edid = edid;
4394
4395         vrr_capable = intel_vrr_is_capable(&connector->base);
4396         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4397                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4398         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4399
4400         intel_dp_update_dfp(intel_dp, edid);
4401         intel_dp_update_420(intel_dp);
4402
4403         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4404                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4405                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4406         }
4407
4408         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4409 }
4410
4411 static void
4412 intel_dp_unset_edid(struct intel_dp *intel_dp)
4413 {
4414         struct intel_connector *connector = intel_dp->attached_connector;
4415
4416         drm_dp_cec_unset_edid(&intel_dp->aux);
4417         kfree(connector->detect_edid);
4418         connector->detect_edid = NULL;
4419
4420         intel_dp->has_hdmi_sink = false;
4421         intel_dp->has_audio = false;
4422
4423         intel_dp->dfp.max_bpc = 0;
4424         intel_dp->dfp.max_dotclock = 0;
4425         intel_dp->dfp.min_tmds_clock = 0;
4426         intel_dp->dfp.max_tmds_clock = 0;
4427
4428         intel_dp->dfp.pcon_max_frl_bw = 0;
4429
4430         intel_dp->dfp.ycbcr_444_to_420 = false;
4431         connector->base.ycbcr_420_allowed = false;
4432
4433         drm_connector_set_vrr_capable_property(&connector->base,
4434                                                false);
4435 }
4436
4437 static int
4438 intel_dp_detect(struct drm_connector *connector,
4439                 struct drm_modeset_acquire_ctx *ctx,
4440                 bool force)
4441 {
4442         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4443         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4444         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4445         struct intel_encoder *encoder = &dig_port->base;
4446         enum drm_connector_status status;
4447
4448         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4449                     connector->base.id, connector->name);
4450         drm_WARN_ON(&dev_priv->drm,
4451                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4452
4453         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4454                 return connector_status_disconnected;
4455
4456         /* Can't disconnect eDP */
4457         if (intel_dp_is_edp(intel_dp))
4458                 status = edp_detect(intel_dp);
4459         else if (intel_digital_port_connected(encoder))
4460                 status = intel_dp_detect_dpcd(intel_dp);
4461         else
4462                 status = connector_status_disconnected;
4463
4464         if (status == connector_status_disconnected) {
4465                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4466                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4467
4468                 if (intel_dp->is_mst) {
4469                         drm_dbg_kms(&dev_priv->drm,
4470                                     "MST device may have disappeared %d vs %d\n",
4471                                     intel_dp->is_mst,
4472                                     intel_dp->mst_mgr.mst_state);
4473                         intel_dp->is_mst = false;
4474                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4475                                                         intel_dp->is_mst);
4476                 }
4477
4478                 goto out;
4479         }
4480
4481         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4482         if (DISPLAY_VER(dev_priv) >= 11)
4483                 intel_dp_get_dsc_sink_cap(intel_dp);
4484
4485         intel_dp_configure_mst(intel_dp);
4486
4487         /*
4488          * TODO: Reset link params when switching to MST mode, until MST
4489          * supports link training fallback params.
4490          */
4491         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4492                 intel_dp_reset_max_link_params(intel_dp);
4493                 intel_dp->reset_link_params = false;
4494         }
4495
4496         intel_dp_print_rates(intel_dp);
4497
4498         if (intel_dp->is_mst) {
4499                 /*
4500                  * If we are in MST mode then this connector
4501                  * won't appear connected or have anything
4502                  * with EDID on it
4503                  */
4504                 status = connector_status_disconnected;
4505                 goto out;
4506         }
4507
4508         /*
4509          * Some external monitors do not signal loss of link synchronization
4510          * with an IRQ_HPD, so force a link status check.
4511          */
4512         if (!intel_dp_is_edp(intel_dp)) {
4513                 int ret;
4514
4515                 ret = intel_dp_retrain_link(encoder, ctx);
4516                 if (ret)
4517                         return ret;
4518         }
4519
4520         /*
4521          * Clearing NACK and defer counts to get their exact values
4522          * while reading EDID which are required by Compliance tests
4523          * 4.2.2.4 and 4.2.2.5
4524          */
4525         intel_dp->aux.i2c_nack_count = 0;
4526         intel_dp->aux.i2c_defer_count = 0;
4527
4528         intel_dp_set_edid(intel_dp);
4529         if (intel_dp_is_edp(intel_dp) ||
4530             to_intel_connector(connector)->detect_edid)
4531                 status = connector_status_connected;
4532
4533         intel_dp_check_device_service_irq(intel_dp);
4534
4535 out:
4536         if (status != connector_status_connected && !intel_dp->is_mst)
4537                 intel_dp_unset_edid(intel_dp);
4538
4539         /*
4540          * Make sure the refs for power wells enabled during detect are
4541          * dropped to avoid a new detect cycle triggered by HPD polling.
4542          */
4543         intel_display_power_flush_work(dev_priv);
4544
4545         if (!intel_dp_is_edp(intel_dp))
4546                 drm_dp_set_subconnector_property(connector,
4547                                                  status,
4548                                                  intel_dp->dpcd,
4549                                                  intel_dp->downstream_ports);
4550         return status;
4551 }
4552
4553 static void
4554 intel_dp_force(struct drm_connector *connector)
4555 {
4556         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4557         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4558         struct intel_encoder *intel_encoder = &dig_port->base;
4559         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4560         enum intel_display_power_domain aux_domain =
4561                 intel_aux_power_domain(dig_port);
4562         intel_wakeref_t wakeref;
4563
4564         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4565                     connector->base.id, connector->name);
4566         intel_dp_unset_edid(intel_dp);
4567
4568         if (connector->status != connector_status_connected)
4569                 return;
4570
4571         wakeref = intel_display_power_get(dev_priv, aux_domain);
4572
4573         intel_dp_set_edid(intel_dp);
4574
4575         intel_display_power_put(dev_priv, aux_domain, wakeref);
4576 }
4577
4578 static int intel_dp_get_modes(struct drm_connector *connector)
4579 {
4580         struct intel_connector *intel_connector = to_intel_connector(connector);
4581         struct edid *edid;
4582         int num_modes = 0;
4583
4584         edid = intel_connector->detect_edid;
4585         if (edid)
4586                 num_modes = intel_connector_update_modes(connector, edid);
4587
4588         /* Also add fixed mode, which may or may not be present in EDID */
4589         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4590             intel_connector->panel.fixed_mode) {
4591                 struct drm_display_mode *mode;
4592
4593                 mode = drm_mode_duplicate(connector->dev,
4594                                           intel_connector->panel.fixed_mode);
4595                 if (mode) {
4596                         drm_mode_probed_add(connector, mode);
4597                         num_modes++;
4598                 }
4599         }
4600
4601         if (num_modes)
4602                 return num_modes;
4603
4604         if (!edid) {
4605                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4606                 struct drm_display_mode *mode;
4607
4608                 mode = drm_dp_downstream_mode(connector->dev,
4609                                               intel_dp->dpcd,
4610                                               intel_dp->downstream_ports);
4611                 if (mode) {
4612                         drm_mode_probed_add(connector, mode);
4613                         num_modes++;
4614                 }
4615         }
4616
4617         return num_modes;
4618 }
4619
4620 static int
4621 intel_dp_connector_register(struct drm_connector *connector)
4622 {
4623         struct drm_i915_private *i915 = to_i915(connector->dev);
4624         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4625         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4626         struct intel_lspcon *lspcon = &dig_port->lspcon;
4627         int ret;
4628
4629         ret = intel_connector_register(connector);
4630         if (ret)
4631                 return ret;
4632
4633         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4634                     intel_dp->aux.name, connector->kdev->kobj.name);
4635
4636         intel_dp->aux.dev = connector->kdev;
4637         ret = drm_dp_aux_register(&intel_dp->aux);
4638         if (!ret)
4639                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4640
4641         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4642                 return ret;
4643
4644         /*
4645          * ToDo: Clean this up to handle lspcon init and resume more
4646          * efficiently and streamlined.
4647          */
4648         if (lspcon_init(dig_port)) {
4649                 lspcon_detect_hdr_capability(lspcon);
4650                 if (lspcon->hdr_supported)
4651                         drm_object_attach_property(&connector->base,
4652                                                    connector->dev->mode_config.hdr_output_metadata_property,
4653                                                    0);
4654         }
4655
4656         return ret;
4657 }
4658
4659 static void
4660 intel_dp_connector_unregister(struct drm_connector *connector)
4661 {
4662         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4663
4664         drm_dp_cec_unregister_connector(&intel_dp->aux);
4665         drm_dp_aux_unregister(&intel_dp->aux);
4666         intel_connector_unregister(connector);
4667 }
4668
4669 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4670 {
4671         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4672         struct intel_dp *intel_dp = &dig_port->dp;
4673
4674         intel_dp_mst_encoder_cleanup(dig_port);
4675
4676         intel_pps_vdd_off_sync(intel_dp);
4677
4678         intel_dp_aux_fini(intel_dp);
4679 }
4680
4681 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4682 {
4683         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4684
4685         intel_pps_vdd_off_sync(intel_dp);
4686 }
4687
4688 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4689 {
4690         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4691
4692         intel_pps_wait_power_cycle(intel_dp);
4693 }
4694
4695 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4696                                     int tile_group_id)
4697 {
4698         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4699         struct drm_connector_list_iter conn_iter;
4700         struct drm_connector *connector;
4701         int ret = 0;
4702
4703         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4704         drm_for_each_connector_iter(connector, &conn_iter) {
4705                 struct drm_connector_state *conn_state;
4706                 struct intel_crtc_state *crtc_state;
4707                 struct intel_crtc *crtc;
4708
4709                 if (!connector->has_tile ||
4710                     connector->tile_group->id != tile_group_id)
4711                         continue;
4712
4713                 conn_state = drm_atomic_get_connector_state(&state->base,
4714                                                             connector);
4715                 if (IS_ERR(conn_state)) {
4716                         ret = PTR_ERR(conn_state);
4717                         break;
4718                 }
4719
4720                 crtc = to_intel_crtc(conn_state->crtc);
4721
4722                 if (!crtc)
4723                         continue;
4724
4725                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4726                 crtc_state->uapi.mode_changed = true;
4727
4728                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4729                 if (ret)
4730                         break;
4731         }
4732         drm_connector_list_iter_end(&conn_iter);
4733
4734         return ret;
4735 }
4736
4737 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4738 {
4739         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4740         struct intel_crtc *crtc;
4741
4742         if (transcoders == 0)
4743                 return 0;
4744
4745         for_each_intel_crtc(&dev_priv->drm, crtc) {
4746                 struct intel_crtc_state *crtc_state;
4747                 int ret;
4748
4749                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4750                 if (IS_ERR(crtc_state))
4751                         return PTR_ERR(crtc_state);
4752
4753                 if (!crtc_state->hw.enable)
4754                         continue;
4755
4756                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4757                         continue;
4758
4759                 crtc_state->uapi.mode_changed = true;
4760
4761                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4762                 if (ret)
4763                         return ret;
4764
4765                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4766                 if (ret)
4767                         return ret;
4768
4769                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4770         }
4771
4772         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4773
4774         return 0;
4775 }
4776
4777 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4778                                       struct drm_connector *connector)
4779 {
4780         const struct drm_connector_state *old_conn_state =
4781                 drm_atomic_get_old_connector_state(&state->base, connector);
4782         const struct intel_crtc_state *old_crtc_state;
4783         struct intel_crtc *crtc;
4784         u8 transcoders;
4785
4786         crtc = to_intel_crtc(old_conn_state->crtc);
4787         if (!crtc)
4788                 return 0;
4789
4790         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4791
4792         if (!old_crtc_state->hw.active)
4793                 return 0;
4794
4795         transcoders = old_crtc_state->sync_mode_slaves_mask;
4796         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4797                 transcoders |= BIT(old_crtc_state->master_transcoder);
4798
4799         return intel_modeset_affected_transcoders(state,
4800                                                   transcoders);
4801 }
4802
4803 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4804                                            struct drm_atomic_state *_state)
4805 {
4806         struct drm_i915_private *dev_priv = to_i915(conn->dev);
4807         struct intel_atomic_state *state = to_intel_atomic_state(_state);
4808         int ret;
4809
4810         ret = intel_digital_connector_atomic_check(conn, &state->base);
4811         if (ret)
4812                 return ret;
4813
4814         /*
4815          * We don't enable port sync on BDW due to missing w/as and
4816          * due to not having adjusted the modeset sequence appropriately.
4817          */
4818         if (DISPLAY_VER(dev_priv) < 9)
4819                 return 0;
4820
4821         if (!intel_connector_needs_modeset(state, conn))
4822                 return 0;
4823
4824         if (conn->has_tile) {
4825                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4826                 if (ret)
4827                         return ret;
4828         }
4829
4830         return intel_modeset_synced_crtcs(state, conn);
4831 }
4832
4833 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
4834 {
4835         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
4836         struct drm_i915_private *i915 = to_i915(connector->dev);
4837
4838         spin_lock_irq(&i915->irq_lock);
4839         i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
4840         spin_unlock_irq(&i915->irq_lock);
4841         queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
4842 }
4843
4844 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4845         .force = intel_dp_force,
4846         .fill_modes = drm_helper_probe_single_connector_modes,
4847         .atomic_get_property = intel_digital_connector_atomic_get_property,
4848         .atomic_set_property = intel_digital_connector_atomic_set_property,
4849         .late_register = intel_dp_connector_register,
4850         .early_unregister = intel_dp_connector_unregister,
4851         .destroy = intel_connector_destroy,
4852         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4853         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4854         .oob_hotplug_event = intel_dp_oob_hotplug_event,
4855 };
4856
4857 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4858         .detect_ctx = intel_dp_detect,
4859         .get_modes = intel_dp_get_modes,
4860         .mode_valid = intel_dp_mode_valid,
4861         .atomic_check = intel_dp_connector_atomic_check,
4862 };
4863
4864 enum irqreturn
4865 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4866 {
4867         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4868         struct intel_dp *intel_dp = &dig_port->dp;
4869
4870         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4871             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
4872                 /*
4873                  * vdd off can generate a long/short pulse on eDP which
4874                  * would require vdd on to handle it, and thus we
4875                  * would end up in an endless cycle of
4876                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4877                  */
4878                 drm_dbg_kms(&i915->drm,
4879                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4880                             long_hpd ? "long" : "short",
4881                             dig_port->base.base.base.id,
4882                             dig_port->base.base.name);
4883                 return IRQ_HANDLED;
4884         }
4885
4886         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4887                     dig_port->base.base.base.id,
4888                     dig_port->base.base.name,
4889                     long_hpd ? "long" : "short");
4890
4891         if (long_hpd) {
4892                 intel_dp->reset_link_params = true;
4893                 return IRQ_NONE;
4894         }
4895
4896         if (intel_dp->is_mst) {
4897                 if (!intel_dp_check_mst_status(intel_dp))
4898                         return IRQ_NONE;
4899         } else if (!intel_dp_short_pulse(intel_dp)) {
4900                 return IRQ_NONE;
4901         }
4902
4903         return IRQ_HANDLED;
4904 }
4905
4906 /* check the VBT to see whether the eDP is on another port */
4907 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4908 {
4909         /*
4910          * eDP not supported on g4x. so bail out early just
4911          * for a bit extra safety in case the VBT is bonkers.
4912          */
4913         if (DISPLAY_VER(dev_priv) < 5)
4914                 return false;
4915
4916         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4917                 return true;
4918
4919         return intel_bios_is_port_edp(dev_priv, port);
4920 }
4921
4922 static void
4923 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4924 {
4925         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4926         enum port port = dp_to_dig_port(intel_dp)->base.port;
4927
4928         if (!intel_dp_is_edp(intel_dp))
4929                 drm_connector_attach_dp_subconnector_property(connector);
4930
4931         if (!IS_G4X(dev_priv) && port != PORT_A)
4932                 intel_attach_force_audio_property(connector);
4933
4934         intel_attach_broadcast_rgb_property(connector);
4935         if (HAS_GMCH(dev_priv))
4936                 drm_connector_attach_max_bpc_property(connector, 6, 10);
4937         else if (DISPLAY_VER(dev_priv) >= 5)
4938                 drm_connector_attach_max_bpc_property(connector, 6, 12);
4939
4940         /* Register HDMI colorspace for case of lspcon */
4941         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4942                 drm_connector_attach_content_type_property(connector);
4943                 intel_attach_hdmi_colorspace_property(connector);
4944         } else {
4945                 intel_attach_dp_colorspace_property(connector);
4946         }
4947
4948         if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4949                 drm_object_attach_property(&connector->base,
4950                                            connector->dev->mode_config.hdr_output_metadata_property,
4951                                            0);
4952
4953         if (intel_dp_is_edp(intel_dp)) {
4954                 u32 allowed_scalers;
4955
4956                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4957                 if (!HAS_GMCH(dev_priv))
4958                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4959
4960                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4961
4962                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4963
4964         }
4965
4966         if (HAS_VRR(dev_priv))
4967                 drm_connector_attach_vrr_capable_property(connector);
4968 }
4969
4970 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4971                                      struct intel_connector *intel_connector)
4972 {
4973         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4974         struct drm_device *dev = &dev_priv->drm;
4975         struct drm_connector *connector = &intel_connector->base;
4976         struct drm_display_mode *fixed_mode = NULL;
4977         struct drm_display_mode *downclock_mode = NULL;
4978         bool has_dpcd;
4979         enum pipe pipe = INVALID_PIPE;
4980         struct edid *edid;
4981
4982         if (!intel_dp_is_edp(intel_dp))
4983                 return true;
4984
4985         /*
4986          * On IBX/CPT we may get here with LVDS already registered. Since the
4987          * driver uses the only internal power sequencer available for both
4988          * eDP and LVDS bail out early in this case to prevent interfering
4989          * with an already powered-on LVDS power sequencer.
4990          */
4991         if (intel_get_lvds_encoder(dev_priv)) {
4992                 drm_WARN_ON(dev,
4993                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
4994                 drm_info(&dev_priv->drm,
4995                          "LVDS was detected, not registering eDP\n");
4996
4997                 return false;
4998         }
4999
5000         intel_pps_init(intel_dp);
5001
5002         /* Cache DPCD and EDID for edp. */
5003         has_dpcd = intel_edp_init_dpcd(intel_dp);
5004
5005         if (!has_dpcd) {
5006                 /* if this fails, presume the device is a ghost */
5007                 drm_info(&dev_priv->drm,
5008                          "failed to retrieve link info, disabling eDP\n");
5009                 goto out_vdd_off;
5010         }
5011
5012         mutex_lock(&dev->mode_config.mutex);
5013         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5014         if (!edid) {
5015                 /* Fallback to EDID from ACPI OpRegion, if any */
5016                 edid = intel_opregion_get_edid(intel_connector);
5017                 if (edid)
5018                         drm_dbg_kms(&dev_priv->drm,
5019                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5020                                     connector->base.id, connector->name);
5021         }
5022         if (edid) {
5023                 if (drm_add_edid_modes(connector, edid)) {
5024                         drm_connector_update_edid_property(connector, edid);
5025                 } else {
5026                         kfree(edid);
5027                         edid = ERR_PTR(-EINVAL);
5028                 }
5029         } else {
5030                 edid = ERR_PTR(-ENOENT);
5031         }
5032         intel_connector->edid = edid;
5033
5034         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5035         if (fixed_mode)
5036                 downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
5037
5038         /* MSO requires information from the EDID */
5039         intel_edp_mso_init(intel_dp);
5040
5041         /* multiply the mode clock and horizontal timings for MSO */
5042         intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5043         intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5044
5045         /* fallback to VBT if available for eDP */
5046         if (!fixed_mode)
5047                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5048         mutex_unlock(&dev->mode_config.mutex);
5049
5050         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5051                 /*
5052                  * Figure out the current pipe for the initial backlight setup.
5053                  * If the current pipe isn't valid, try the PPS pipe, and if that
5054                  * fails just assume pipe A.
5055                  */
5056                 pipe = vlv_active_pipe(intel_dp);
5057
5058                 if (pipe != PIPE_A && pipe != PIPE_B)
5059                         pipe = intel_dp->pps.pps_pipe;
5060
5061                 if (pipe != PIPE_A && pipe != PIPE_B)
5062                         pipe = PIPE_A;
5063
5064                 drm_dbg_kms(&dev_priv->drm,
5065                             "using pipe %c for initial backlight setup\n",
5066                             pipe_name(pipe));
5067         }
5068
5069         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5070         if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
5071                 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5072         intel_backlight_setup(intel_connector, pipe);
5073
5074         if (fixed_mode) {
5075                 drm_connector_set_panel_orientation_with_quirk(connector,
5076                                 dev_priv->vbt.orientation,
5077                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
5078         }
5079
5080         return true;
5081
5082 out_vdd_off:
5083         intel_pps_vdd_off_sync(intel_dp);
5084
5085         return false;
5086 }
5087
5088 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5089 {
5090         struct intel_connector *intel_connector;
5091         struct drm_connector *connector;
5092
5093         intel_connector = container_of(work, typeof(*intel_connector),
5094                                        modeset_retry_work);
5095         connector = &intel_connector->base;
5096         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5097                     connector->name);
5098
5099         /* Grab the locks before changing connector property*/
5100         mutex_lock(&connector->dev->mode_config.mutex);
5101         /* Set connector link status to BAD and send a Uevent to notify
5102          * userspace to do a modeset.
5103          */
5104         drm_connector_set_link_status_property(connector,
5105                                                DRM_MODE_LINK_STATUS_BAD);
5106         mutex_unlock(&connector->dev->mode_config.mutex);
5107         /* Send Hotplug uevent so userspace can reprobe */
5108         drm_kms_helper_connector_hotplug_event(connector);
5109 }
5110
5111 bool
5112 intel_dp_init_connector(struct intel_digital_port *dig_port,
5113                         struct intel_connector *intel_connector)
5114 {
5115         struct drm_connector *connector = &intel_connector->base;
5116         struct intel_dp *intel_dp = &dig_port->dp;
5117         struct intel_encoder *intel_encoder = &dig_port->base;
5118         struct drm_device *dev = intel_encoder->base.dev;
5119         struct drm_i915_private *dev_priv = to_i915(dev);
5120         enum port port = intel_encoder->port;
5121         enum phy phy = intel_port_to_phy(dev_priv, port);
5122         int type;
5123
5124         /* Initialize the work for modeset in case of link train failure */
5125         INIT_WORK(&intel_connector->modeset_retry_work,
5126                   intel_dp_modeset_retry_work_fn);
5127
5128         if (drm_WARN(dev, dig_port->max_lanes < 1,
5129                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5130                      dig_port->max_lanes, intel_encoder->base.base.id,
5131                      intel_encoder->base.name))
5132                 return false;
5133
5134         intel_dp->reset_link_params = true;
5135         intel_dp->pps.pps_pipe = INVALID_PIPE;
5136         intel_dp->pps.active_pipe = INVALID_PIPE;
5137
5138         /* Preserve the current hw state. */
5139         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5140         intel_dp->attached_connector = intel_connector;
5141
5142         if (intel_dp_is_port_edp(dev_priv, port)) {
5143                 /*
5144                  * Currently we don't support eDP on TypeC ports, although in
5145                  * theory it could work on TypeC legacy ports.
5146                  */
5147                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5148                 type = DRM_MODE_CONNECTOR_eDP;
5149                 intel_encoder->type = INTEL_OUTPUT_EDP;
5150
5151                 /* eDP only on port B and/or C on vlv/chv */
5152                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5153                                       IS_CHERRYVIEW(dev_priv)) &&
5154                                 port != PORT_B && port != PORT_C))
5155                         return false;
5156         } else {
5157                 type = DRM_MODE_CONNECTOR_DisplayPort;
5158         }
5159
5160         intel_dp_set_source_rates(intel_dp);
5161         intel_dp_set_default_sink_rates(intel_dp);
5162         intel_dp_set_default_max_sink_lane_count(intel_dp);
5163         intel_dp_set_common_rates(intel_dp);
5164         intel_dp_reset_max_link_params(intel_dp);
5165
5166         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5167                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5168
5169         drm_dbg_kms(&dev_priv->drm,
5170                     "Adding %s connector on [ENCODER:%d:%s]\n",
5171                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5172                     intel_encoder->base.base.id, intel_encoder->base.name);
5173
5174         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5175         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5176
5177         if (!HAS_GMCH(dev_priv))
5178                 connector->interlace_allowed = true;
5179         connector->doublescan_allowed = 0;
5180
5181         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5182
5183         intel_dp_aux_init(intel_dp);
5184
5185         intel_connector_attach_encoder(intel_connector, intel_encoder);
5186
5187         if (HAS_DDI(dev_priv))
5188                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5189         else
5190                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5191
5192         /* init MST on ports that can support it */
5193         intel_dp_mst_encoder_init(dig_port,
5194                                   intel_connector->base.base.id);
5195
5196         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5197                 intel_dp_aux_fini(intel_dp);
5198                 intel_dp_mst_encoder_cleanup(dig_port);
5199                 goto fail;
5200         }
5201
5202         intel_dp_add_properties(intel_dp, connector);
5203
5204         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5205                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5206                 if (ret)
5207                         drm_dbg_kms(&dev_priv->drm,
5208                                     "HDCP init failed, skipping.\n");
5209         }
5210
5211         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5212          * 0xd.  Failure to do so will result in spurious interrupts being
5213          * generated on the port when a cable is not attached.
5214          */
5215         if (IS_G45(dev_priv)) {
5216                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5217                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5218                                (temp & ~0xf) | 0xd);
5219         }
5220
5221         intel_dp->frl.is_trained = false;
5222         intel_dp->frl.trained_rate_gbps = 0;
5223
5224         intel_psr_init(intel_dp);
5225
5226         return true;
5227
5228 fail:
5229         drm_connector_cleanup(connector);
5230
5231         return false;
5232 }
5233
5234 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5235 {
5236         struct intel_encoder *encoder;
5237
5238         if (!HAS_DISPLAY(dev_priv))
5239                 return;
5240
5241         for_each_intel_encoder(&dev_priv->drm, encoder) {
5242                 struct intel_dp *intel_dp;
5243
5244                 if (encoder->type != INTEL_OUTPUT_DDI)
5245                         continue;
5246
5247                 intel_dp = enc_to_intel_dp(encoder);
5248
5249                 if (!intel_dp_mst_source_support(intel_dp))
5250                         continue;
5251
5252                 if (intel_dp->is_mst)
5253                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5254         }
5255 }
5256
5257 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5258 {
5259         struct intel_encoder *encoder;
5260
5261         if (!HAS_DISPLAY(dev_priv))
5262                 return;
5263
5264         for_each_intel_encoder(&dev_priv->drm, encoder) {
5265                 struct intel_dp *intel_dp;
5266                 int ret;
5267
5268                 if (encoder->type != INTEL_OUTPUT_DDI)
5269                         continue;
5270
5271                 intel_dp = enc_to_intel_dp(encoder);
5272
5273                 if (!intel_dp_mst_source_support(intel_dp))
5274                         continue;
5275
5276                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5277                                                      true);
5278                 if (ret) {
5279                         intel_dp->is_mst = false;
5280                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5281                                                         false);
5282                 }
5283         }
5284 }