2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/string_helpers.h>
33 #include <linux/timekeeping.h>
34 #include <linux/types.h>
36 #include <asm/byteorder.h>
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/display/drm_dsc_helper.h>
40 #include <drm/display/drm_hdmi_helper.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_probe_helper.h>
50 #include "intel_atomic.h"
51 #include "intel_audio.h"
52 #include "intel_backlight.h"
53 #include "intel_combo_phy_regs.h"
54 #include "intel_connector.h"
55 #include "intel_crtc.h"
56 #include "intel_cx0_phy.h"
57 #include "intel_ddi.h"
59 #include "intel_display_types.h"
61 #include "intel_dp_aux.h"
62 #include "intel_dp_hdcp.h"
63 #include "intel_dp_link_training.h"
64 #include "intel_dp_mst.h"
65 #include "intel_dpio_phy.h"
66 #include "intel_dpll.h"
67 #include "intel_fifo_underrun.h"
68 #include "intel_hdcp.h"
69 #include "intel_hdmi.h"
70 #include "intel_hotplug.h"
71 #include "intel_hotplug_irq.h"
72 #include "intel_lspcon.h"
73 #include "intel_lvds.h"
74 #include "intel_panel.h"
75 #include "intel_pch_display.h"
76 #include "intel_pps.h"
77 #include "intel_psr.h"
79 #include "intel_vdsc.h"
80 #include "intel_vrr.h"
81 #include "intel_crtc_state_dump.h"
83 /* DP DSC throughput values used for slice count calculations KPixels/s */
84 #define DP_DSC_PEAK_PIXEL_RATE 2720000
85 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
86 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
88 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
89 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
91 /* Compliance test status bits */
92 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
93 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
94 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
95 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
98 /* Constants for DP DSC configurations */
99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
101 /* With Single pipe configuration, HW is capable of supporting maximum
102 * of 4 slices per line.
104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108 * @intel_dp: DP struct
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
111 * will return true, and false otherwise.
113 * This function is not safe to use prior to encoder type being set.
115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
119 return dig_port->base.type == INTEL_OUTPUT_EDP;
122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
124 /* Is link rate UHBR and thus 128b/132b? */
125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
127 return drm_dp_is_uhbr_rate(crtc_state->port_clock);
131 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
132 * @rate: link rate in 10kbit/s units
134 * Returns the link symbol size in bits/symbol units depending on the link
135 * rate -> channel coding.
137 int intel_dp_link_symbol_size(int rate)
139 return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
143 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
144 * @rate: link rate in 10kbit/s units
146 * Returns the link symbol clock frequency in kHz units depending on the
147 * link rate and channel coding.
149 int intel_dp_link_symbol_clock(int rate)
151 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
154 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
156 intel_dp->sink_rates[0] = 162000;
157 intel_dp->num_sink_rates = 1;
160 /* update sink rates from dpcd */
161 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
163 static const int dp_rates[] = {
164 162000, 270000, 540000, 810000
169 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
170 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
171 static const int quirk_rates[] = { 162000, 270000, 324000 };
173 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
174 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
180 * Sink rates for 8b/10b.
182 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
183 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
185 max_rate = min(max_rate, max_lttpr_rate);
187 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
188 if (dp_rates[i] > max_rate)
190 intel_dp->sink_rates[i] = dp_rates[i];
194 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
197 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
200 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
202 drm_dp_dpcd_readb(&intel_dp->aux,
203 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
205 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
206 /* We have a repeater */
207 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
208 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
209 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
210 DP_PHY_REPEATER_128B132B_SUPPORTED) {
211 /* Repeater supports 128b/132b, valid UHBR rates */
212 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
213 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
215 /* Does not support 128b/132b */
220 if (uhbr_rates & DP_UHBR10)
221 intel_dp->sink_rates[i++] = 1000000;
222 if (uhbr_rates & DP_UHBR13_5)
223 intel_dp->sink_rates[i++] = 1350000;
224 if (uhbr_rates & DP_UHBR20)
225 intel_dp->sink_rates[i++] = 2000000;
228 intel_dp->num_sink_rates = i;
231 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
233 struct intel_connector *connector = intel_dp->attached_connector;
234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
235 struct intel_encoder *encoder = &intel_dig_port->base;
237 intel_dp_set_dpcd_sink_rates(intel_dp);
239 if (intel_dp->num_sink_rates)
242 drm_err(&dp_to_i915(intel_dp)->drm,
243 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
244 connector->base.base.id, connector->base.name,
245 encoder->base.base.id, encoder->base.name);
247 intel_dp_set_default_sink_rates(intel_dp);
250 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
252 intel_dp->max_sink_lane_count = 1;
255 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
257 struct intel_connector *connector = intel_dp->attached_connector;
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct intel_encoder *encoder = &intel_dig_port->base;
261 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
263 switch (intel_dp->max_sink_lane_count) {
270 drm_err(&dp_to_i915(intel_dp)->drm,
271 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
272 connector->base.base.id, connector->base.name,
273 encoder->base.base.id, encoder->base.name,
274 intel_dp->max_sink_lane_count);
276 intel_dp_set_default_max_sink_lane_count(intel_dp);
279 /* Get length of rates array potentially limited by max_rate. */
280 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
284 /* Limit results by potentially reduced max rate */
285 for (i = 0; i < len; i++) {
286 if (rates[len - i - 1] <= max_rate)
293 /* Get length of common rates array potentially limited by max_rate. */
294 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
297 return intel_dp_rate_limit_len(intel_dp->common_rates,
298 intel_dp->num_common_rates, max_rate);
301 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
303 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
304 index < 0 || index >= intel_dp->num_common_rates))
307 return intel_dp->common_rates[index];
310 /* Theoretical max between source and sink */
311 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
313 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
316 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
318 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
319 int max_lanes = dig_port->max_lanes;
322 max_lanes = min(max_lanes, vbt_max_lanes);
327 /* Theoretical max between source and sink */
328 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
330 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
331 int source_max = intel_dp_max_source_lane_count(dig_port);
332 int sink_max = intel_dp->max_sink_lane_count;
333 int lane_max = intel_tc_port_max_lane_count(dig_port);
334 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
337 sink_max = min(sink_max, lttpr_max);
339 return min3(source_max, sink_max, lane_max);
342 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
344 switch (intel_dp->max_link_lane_count) {
348 return intel_dp->max_link_lane_count;
350 MISSING_CASE(intel_dp->max_link_lane_count);
356 * The required data bandwidth for a mode with given pixel clock and bpp. This
357 * is the required net bandwidth independent of the data bandwidth efficiency.
359 * TODO: check if callers of this functions should use
360 * intel_dp_effective_data_rate() instead.
363 intel_dp_link_required(int pixel_clock, int bpp)
365 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
366 return DIV_ROUND_UP(pixel_clock * bpp, 8);
370 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
371 * @pixel_clock: pixel clock in kHz
372 * @bpp_x16: bits per pixel .4 fixed point format
373 * @bw_overhead: BW allocation overhead in 1ppm units
375 * Return the effective pixel data rate in kB/sec units taking into account
376 * the provided SSC, FEC, DSC BW allocation overhead.
378 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
381 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
386 * Given a link rate and lanes, get the data bandwidth.
388 * Data bandwidth is the actual payload rate, which depends on the data
389 * bandwidth efficiency and the link rate.
391 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
392 * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
393 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
394 * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
395 * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
396 * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
398 * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
399 * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
400 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
401 * does not match the symbol clock, the port clock (not even if you think in
402 * terms of a byte clock), nor the data bandwidth. It only matches the link bit
403 * rate in units of 10000 bps.
406 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
408 int ch_coding_efficiency =
409 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
410 int max_link_rate_kbps = max_link_rate * 10;
413 * UHBR rates always use 128b/132b channel encoding, and have
414 * 97.71% data bandwidth efficiency. Consider max_link_rate the
415 * link bit rate in units of 10000 bps.
418 * Lower than UHBR rates always use 8b/10b channel encoding, and have
419 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
420 * out to be a nop by coincidence:
422 * int max_link_rate_kbps = max_link_rate * 10;
423 * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10);
424 * max_link_rate = max_link_rate_kbps / 8;
426 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
427 ch_coding_efficiency),
431 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct intel_encoder *encoder = &intel_dig_port->base;
435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
437 return DISPLAY_VER(dev_priv) >= 12 ||
438 (DISPLAY_VER(dev_priv) == 11 &&
439 encoder->port != PORT_A);
442 static int dg2_max_source_rate(struct intel_dp *intel_dp)
444 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
447 static int icl_max_source_rate(struct intel_dp *intel_dp)
449 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
450 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
451 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
453 if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
459 static int ehl_max_source_rate(struct intel_dp *intel_dp)
461 if (intel_dp_is_edp(intel_dp))
467 static int mtl_max_source_rate(struct intel_dp *intel_dp)
469 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
470 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
471 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
473 if (intel_is_c10phy(i915, phy))
479 static int vbt_max_link_rate(struct intel_dp *intel_dp)
481 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
484 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
486 if (intel_dp_is_edp(intel_dp)) {
487 struct intel_connector *connector = intel_dp->attached_connector;
488 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
490 if (max_rate && edp_max_rate)
491 max_rate = min(max_rate, edp_max_rate);
492 else if (edp_max_rate)
493 max_rate = edp_max_rate;
500 intel_dp_set_source_rates(struct intel_dp *intel_dp)
502 /* The values must be in increasing order */
503 static const int mtl_rates[] = {
504 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
505 810000, 1000000, 1350000, 2000000,
507 static const int icl_rates[] = {
508 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
511 static const int bxt_rates[] = {
512 162000, 216000, 243000, 270000, 324000, 432000, 540000
514 static const int skl_rates[] = {
515 162000, 216000, 270000, 324000, 432000, 540000
517 static const int hsw_rates[] = {
518 162000, 270000, 540000
520 static const int g4x_rates[] = {
523 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
524 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
525 const int *source_rates;
526 int size, max_rate = 0, vbt_max_rate;
528 /* This should only be done once */
529 drm_WARN_ON(&dev_priv->drm,
530 intel_dp->source_rates || intel_dp->num_source_rates);
532 if (DISPLAY_VER(dev_priv) >= 14) {
533 source_rates = mtl_rates;
534 size = ARRAY_SIZE(mtl_rates);
535 max_rate = mtl_max_source_rate(intel_dp);
536 } else if (DISPLAY_VER(dev_priv) >= 11) {
537 source_rates = icl_rates;
538 size = ARRAY_SIZE(icl_rates);
539 if (IS_DG2(dev_priv))
540 max_rate = dg2_max_source_rate(intel_dp);
541 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
542 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
544 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
545 max_rate = ehl_max_source_rate(intel_dp);
547 max_rate = icl_max_source_rate(intel_dp);
548 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
549 source_rates = bxt_rates;
550 size = ARRAY_SIZE(bxt_rates);
551 } else if (DISPLAY_VER(dev_priv) == 9) {
552 source_rates = skl_rates;
553 size = ARRAY_SIZE(skl_rates);
554 } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
555 IS_BROADWELL(dev_priv)) {
556 source_rates = hsw_rates;
557 size = ARRAY_SIZE(hsw_rates);
559 source_rates = g4x_rates;
560 size = ARRAY_SIZE(g4x_rates);
563 vbt_max_rate = vbt_max_link_rate(intel_dp);
564 if (max_rate && vbt_max_rate)
565 max_rate = min(max_rate, vbt_max_rate);
566 else if (vbt_max_rate)
567 max_rate = vbt_max_rate;
570 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
572 intel_dp->source_rates = source_rates;
573 intel_dp->num_source_rates = size;
576 static int intersect_rates(const int *source_rates, int source_len,
577 const int *sink_rates, int sink_len,
580 int i = 0, j = 0, k = 0;
582 while (i < source_len && j < sink_len) {
583 if (source_rates[i] == sink_rates[j]) {
584 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
586 common_rates[k] = source_rates[i];
590 } else if (source_rates[i] < sink_rates[j]) {
599 /* return index of rate in rates array, or -1 if not found */
600 static int intel_dp_rate_index(const int *rates, int len, int rate)
604 for (i = 0; i < len; i++)
605 if (rate == rates[i])
611 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
613 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
615 drm_WARN_ON(&i915->drm,
616 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
618 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
619 intel_dp->num_source_rates,
620 intel_dp->sink_rates,
621 intel_dp->num_sink_rates,
622 intel_dp->common_rates);
624 /* Paranoia, there should always be something in common. */
625 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
626 intel_dp->common_rates[0] = 162000;
627 intel_dp->num_common_rates = 1;
631 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
635 * FIXME: we need to synchronize the current link parameters with
636 * hardware readout. Currently fast link training doesn't work on
639 if (link_rate == 0 ||
640 link_rate > intel_dp->max_link_rate)
643 if (lane_count == 0 ||
644 lane_count > intel_dp_max_lane_count(intel_dp))
650 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
654 /* FIXME figure out what we actually want here */
655 const struct drm_display_mode *fixed_mode =
656 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
657 int mode_rate, max_rate;
659 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
660 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
661 if (mode_rate > max_rate)
667 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
668 int link_rate, u8 lane_count)
670 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
674 * TODO: Enable fallback on MST links once MST link compute can handle
675 * the fallback params.
677 if (intel_dp->is_mst) {
678 drm_err(&i915->drm, "Link Training Unsuccessful\n");
682 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
683 drm_dbg_kms(&i915->drm,
684 "Retrying Link training for eDP with max parameters\n");
685 intel_dp->use_max_params = true;
689 index = intel_dp_rate_index(intel_dp->common_rates,
690 intel_dp->num_common_rates,
693 if (intel_dp_is_edp(intel_dp) &&
694 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
695 intel_dp_common_rate(intel_dp, index - 1),
697 drm_dbg_kms(&i915->drm,
698 "Retrying Link training for eDP with same parameters\n");
701 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
702 intel_dp->max_link_lane_count = lane_count;
703 } else if (lane_count > 1) {
704 if (intel_dp_is_edp(intel_dp) &&
705 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
706 intel_dp_max_common_rate(intel_dp),
708 drm_dbg_kms(&i915->drm,
709 "Retrying Link training for eDP with same parameters\n");
712 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
713 intel_dp->max_link_lane_count = lane_count >> 1;
715 drm_err(&i915->drm, "Link Training Unsuccessful\n");
722 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
724 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
728 int intel_dp_bw_fec_overhead(bool fec_enabled)
731 * TODO: Calculate the actual overhead for a given mode.
732 * The hard-coded 1/0.972261=2.853% overhead factor
733 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
734 * 0.453% DSC overhead. This is enough for a 3840 width mode,
735 * which has a DSC overhead of up to ~0.2%, but may not be
736 * enough for a 1024 width mode where this is ~0.8% (on a 4
737 * lane DP link, with 2 DSC slices and 8 bpp color depth).
739 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
743 small_joiner_ram_size_bits(struct drm_i915_private *i915)
745 if (DISPLAY_VER(i915) >= 13)
747 else if (DISPLAY_VER(i915) >= 11)
753 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
755 u32 bits_per_pixel = bpp;
758 /* Error out if the max bpp is less than smallest allowed valid bpp */
759 if (bits_per_pixel < valid_dsc_bpp[0]) {
760 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
761 bits_per_pixel, valid_dsc_bpp[0]);
765 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
766 if (DISPLAY_VER(i915) >= 13) {
767 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
770 * According to BSpec, 27 is the max DSC output bpp,
771 * 8 is the min DSC output bpp.
772 * While we can still clamp higher bpp values to 27, saving bandwidth,
773 * if it is required to oompress up to bpp < 8, means we can't do
774 * that and probably means we can't fit the required mode, even with
777 if (bits_per_pixel < 8) {
778 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
782 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
784 /* Find the nearest match in the array of known BPPs from VESA */
785 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
786 if (bits_per_pixel < valid_dsc_bpp[i + 1])
789 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
790 bits_per_pixel, valid_dsc_bpp[i]);
792 bits_per_pixel = valid_dsc_bpp[i];
795 return bits_per_pixel;
799 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
800 u32 mode_clock, u32 mode_hdisplay,
803 u32 max_bpp_small_joiner_ram;
805 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
806 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
809 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
810 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
812 u32 max_bpp_bigjoiner =
813 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
814 intel_dp_mode_to_fec_clock(mode_clock);
816 max_bpp_small_joiner_ram *= 2;
818 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
821 return max_bpp_small_joiner_ram;
824 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
825 u32 link_clock, u32 lane_count,
826 u32 mode_clock, u32 mode_hdisplay,
828 enum intel_output_format output_format,
832 u32 bits_per_pixel, joiner_max_bpp;
835 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
836 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
837 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
838 * for MST -> TimeSlots has to be calculated, based on mode requirements
840 * Due to FEC overhead, the available bw is reduced to 97.2261%.
841 * To support the given mode:
842 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
843 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
844 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
845 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
846 * (ModeClock / FEC Overhead)
847 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
848 * (ModeClock / FEC Overhead * 8)
850 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
851 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
853 /* Bandwidth required for 420 is half, that of 444 format */
854 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
858 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
859 * supported PPS value can be 63.9375 and with the further
860 * mention that for 420, 422 formats, bpp should be programmed double
861 * the target bpp restricting our target bpp to be 31.9375 at max.
863 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
864 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
866 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
867 "total bw %u pixel clock %u\n",
868 bits_per_pixel, timeslots,
869 (link_clock * lane_count * 8),
870 intel_dp_mode_to_fec_clock(mode_clock));
872 joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
873 mode_hdisplay, bigjoiner);
874 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
876 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
878 return bits_per_pixel;
881 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
882 int mode_clock, int mode_hdisplay,
885 struct drm_i915_private *i915 = to_i915(connector->base.dev);
886 u8 min_slice_count, i;
889 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
890 min_slice_count = DIV_ROUND_UP(mode_clock,
891 DP_DSC_MAX_ENC_THROUGHPUT_0);
893 min_slice_count = DIV_ROUND_UP(mode_clock,
894 DP_DSC_MAX_ENC_THROUGHPUT_1);
897 * Due to some DSC engine BW limitations, we need to enable second
898 * slice and VDSC engine, whenever we approach close enough to max CDCLK
900 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
901 min_slice_count = max_t(u8, min_slice_count, 2);
903 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
904 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
905 drm_dbg_kms(&i915->drm,
906 "Unsupported slice width %d by DP DSC Sink device\n",
910 /* Also take into account max slice width */
911 min_slice_count = max_t(u8, min_slice_count,
912 DIV_ROUND_UP(mode_hdisplay,
915 /* Find the closest match to the valid slice count values */
916 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
917 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
919 if (test_slice_count >
920 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
923 /* big joiner needs small joiner to be enabled */
924 if (bigjoiner && test_slice_count < 4)
927 if (min_slice_count <= test_slice_count)
928 return test_slice_count;
931 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
936 static bool source_can_output(struct intel_dp *intel_dp,
937 enum intel_output_format format)
939 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
942 case INTEL_OUTPUT_FORMAT_RGB:
945 case INTEL_OUTPUT_FORMAT_YCBCR444:
947 * No YCbCr output support on gmch platforms.
948 * Also, ILK doesn't seem capable of DP YCbCr output.
949 * The displayed image is severly corrupted. SNB+ is fine.
951 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
953 case INTEL_OUTPUT_FORMAT_YCBCR420:
954 /* Platform < Gen 11 cannot output YCbCr420 format */
955 return DISPLAY_VER(i915) >= 11;
958 MISSING_CASE(format);
964 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
965 enum intel_output_format sink_format)
967 if (!drm_dp_is_branch(intel_dp->dpcd))
970 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
971 return intel_dp->dfp.rgb_to_ycbcr;
973 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
974 return intel_dp->dfp.rgb_to_ycbcr &&
975 intel_dp->dfp.ycbcr_444_to_420;
981 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
982 enum intel_output_format sink_format)
984 if (!drm_dp_is_branch(intel_dp->dpcd))
987 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
988 return intel_dp->dfp.ycbcr_444_to_420;
994 dfp_can_convert(struct intel_dp *intel_dp,
995 enum intel_output_format output_format,
996 enum intel_output_format sink_format)
998 switch (output_format) {
999 case INTEL_OUTPUT_FORMAT_RGB:
1000 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1001 case INTEL_OUTPUT_FORMAT_YCBCR444:
1002 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1004 MISSING_CASE(output_format);
1011 static enum intel_output_format
1012 intel_dp_output_format(struct intel_connector *connector,
1013 enum intel_output_format sink_format)
1015 struct intel_dp *intel_dp = intel_attached_dp(connector);
1016 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1017 enum intel_output_format force_dsc_output_format =
1018 intel_dp->force_dsc_output_format;
1019 enum intel_output_format output_format;
1020 if (force_dsc_output_format) {
1021 if (source_can_output(intel_dp, force_dsc_output_format) &&
1022 (!drm_dp_is_branch(intel_dp->dpcd) ||
1023 sink_format != force_dsc_output_format ||
1024 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1025 return force_dsc_output_format;
1027 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1030 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1031 dfp_can_convert_from_rgb(intel_dp, sink_format))
1032 output_format = INTEL_OUTPUT_FORMAT_RGB;
1034 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1035 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1036 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1039 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1041 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1043 return output_format;
1046 int intel_dp_min_bpp(enum intel_output_format output_format)
1048 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1054 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1057 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1058 * format of the number of bytes per pixel will be half the number
1059 * of bytes of RGB pixel.
1061 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1067 static enum intel_output_format
1068 intel_dp_sink_format(struct intel_connector *connector,
1069 const struct drm_display_mode *mode)
1071 const struct drm_display_info *info = &connector->base.display_info;
1073 if (drm_mode_is_420_only(info, mode))
1074 return INTEL_OUTPUT_FORMAT_YCBCR420;
1076 return INTEL_OUTPUT_FORMAT_RGB;
1080 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1081 const struct drm_display_mode *mode)
1083 enum intel_output_format output_format, sink_format;
1085 sink_format = intel_dp_sink_format(connector, mode);
1087 output_format = intel_dp_output_format(connector, sink_format);
1089 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1092 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1096 * Older platforms don't like hdisplay==4096 with DP.
1098 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1099 * and frame counter increment), but we don't get vblank interrupts,
1100 * and the pipe underruns immediately. The link also doesn't seem
1101 * to get trained properly.
1103 * On CHV the vblank interrupts don't seem to disappear but
1104 * otherwise the symptoms are similar.
1106 * TODO: confirm the behaviour on HSW+
1108 return hdisplay == 4096 && !HAS_DDI(dev_priv);
1111 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1113 struct intel_connector *connector = intel_dp->attached_connector;
1114 const struct drm_display_info *info = &connector->base.display_info;
1115 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1117 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1118 if (max_tmds_clock && info->max_tmds_clock)
1119 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1121 return max_tmds_clock;
1124 static enum drm_mode_status
1125 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1127 enum intel_output_format sink_format,
1128 bool respect_downstream_limits)
1130 int tmds_clock, min_tmds_clock, max_tmds_clock;
1132 if (!respect_downstream_limits)
1135 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1137 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1138 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1140 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1141 return MODE_CLOCK_LOW;
1143 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1144 return MODE_CLOCK_HIGH;
1149 static enum drm_mode_status
1150 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1151 const struct drm_display_mode *mode,
1154 struct intel_dp *intel_dp = intel_attached_dp(connector);
1155 const struct drm_display_info *info = &connector->base.display_info;
1156 enum drm_mode_status status;
1157 enum intel_output_format sink_format;
1159 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1160 if (intel_dp->dfp.pcon_max_frl_bw) {
1163 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1165 target_bw = bpp * target_clock;
1167 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1169 /* converting bw from Gbps to Kbps*/
1170 max_frl_bw = max_frl_bw * 1000000;
1172 if (target_bw > max_frl_bw)
1173 return MODE_CLOCK_HIGH;
1178 if (intel_dp->dfp.max_dotclock &&
1179 target_clock > intel_dp->dfp.max_dotclock)
1180 return MODE_CLOCK_HIGH;
1182 sink_format = intel_dp_sink_format(connector, mode);
1184 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1185 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1186 8, sink_format, true);
1188 if (status != MODE_OK) {
1189 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1190 !connector->base.ycbcr_420_allowed ||
1191 !drm_mode_is_420_also(info, mode))
1193 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1194 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1195 8, sink_format, true);
1196 if (status != MODE_OK)
1203 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1204 int hdisplay, int clock)
1206 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208 if (!intel_dp_can_bigjoiner(intel_dp))
1211 return clock > i915->max_dotclk_freq || hdisplay > 5120;
1214 static enum drm_mode_status
1215 intel_dp_mode_valid(struct drm_connector *_connector,
1216 struct drm_display_mode *mode)
1218 struct intel_connector *connector = to_intel_connector(_connector);
1219 struct intel_dp *intel_dp = intel_attached_dp(connector);
1220 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1221 const struct drm_display_mode *fixed_mode;
1222 int target_clock = mode->clock;
1223 int max_rate, mode_rate, max_lanes, max_link_clock;
1224 int max_dotclk = dev_priv->max_dotclk_freq;
1225 u16 dsc_max_compressed_bpp = 0;
1226 u8 dsc_slice_count = 0;
1227 enum drm_mode_status status;
1228 bool dsc = false, bigjoiner = false;
1230 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1231 if (status != MODE_OK)
1234 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1235 return MODE_H_ILLEGAL;
1237 fixed_mode = intel_panel_fixed_mode(connector, mode);
1238 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1239 status = intel_panel_mode_valid(connector, mode);
1240 if (status != MODE_OK)
1243 target_clock = fixed_mode->clock;
1246 if (mode->clock < 10000)
1247 return MODE_CLOCK_LOW;
1249 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1253 if (target_clock > max_dotclk)
1254 return MODE_CLOCK_HIGH;
1256 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1257 return MODE_H_ILLEGAL;
1259 max_link_clock = intel_dp_max_link_rate(intel_dp);
1260 max_lanes = intel_dp_max_lane_count(intel_dp);
1262 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1263 mode_rate = intel_dp_link_required(target_clock,
1264 intel_dp_mode_min_output_bpp(connector, mode));
1266 if (HAS_DSC(dev_priv) &&
1267 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1268 enum intel_output_format sink_format, output_format;
1271 sink_format = intel_dp_sink_format(connector, mode);
1272 output_format = intel_dp_output_format(connector, sink_format);
1274 * TBD pass the connector BPC,
1275 * for now U8_MAX so that max BPC on that platform would be picked
1277 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1280 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1281 * integer value since we support only integer values of bpp.
1283 if (intel_dp_is_edp(intel_dp)) {
1284 dsc_max_compressed_bpp =
1285 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1287 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1289 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1290 dsc_max_compressed_bpp =
1291 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1300 intel_dp_dsc_get_slice_count(connector,
1306 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1310 * Big joiner configuration needs DSC for TGL which is not true for
1311 * XE_LPD where uncompressed joiner is supported.
1313 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1314 return MODE_CLOCK_HIGH;
1316 if (mode_rate > max_rate && !dsc)
1317 return MODE_CLOCK_HIGH;
1319 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1320 if (status != MODE_OK)
1323 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1326 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1328 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1331 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1333 return DISPLAY_VER(i915) >= 10;
1336 static void snprintf_int_array(char *str, size_t len,
1337 const int *array, int nelem)
1343 for (i = 0; i < nelem; i++) {
1344 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1352 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1354 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1355 char str[128]; /* FIXME: too big for stack? */
1357 if (!drm_debug_enabled(DRM_UT_KMS))
1360 snprintf_int_array(str, sizeof(str),
1361 intel_dp->source_rates, intel_dp->num_source_rates);
1362 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1364 snprintf_int_array(str, sizeof(str),
1365 intel_dp->sink_rates, intel_dp->num_sink_rates);
1366 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1368 snprintf_int_array(str, sizeof(str),
1369 intel_dp->common_rates, intel_dp->num_common_rates);
1370 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1374 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1378 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1380 return intel_dp_common_rate(intel_dp, len - 1);
1383 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1385 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1386 int i = intel_dp_rate_index(intel_dp->sink_rates,
1387 intel_dp->num_sink_rates, rate);
1389 if (drm_WARN_ON(&i915->drm, i < 0))
1395 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1396 u8 *link_bw, u8 *rate_select)
1398 /* eDP 1.4 rate select method. */
1399 if (intel_dp->use_rate_select) {
1402 intel_dp_rate_select(intel_dp, port_clock);
1404 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1409 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1411 struct intel_connector *connector = intel_dp->attached_connector;
1413 return connector->base.display_info.is_hdmi;
1416 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1417 const struct intel_crtc_state *pipe_config)
1419 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1420 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1422 if (DISPLAY_VER(dev_priv) >= 12)
1425 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1431 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1432 const struct intel_connector *connector,
1433 const struct intel_crtc_state *pipe_config)
1435 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1436 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1439 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1440 const struct intel_crtc_state *crtc_state)
1442 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1445 return intel_dsc_source_support(crtc_state) &&
1446 connector->dp.dsc_decompression_aux &&
1447 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1450 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1451 const struct intel_crtc_state *crtc_state,
1452 int bpc, bool respect_downstream_limits)
1454 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1457 * Current bpc could already be below 8bpc due to
1458 * FDI bandwidth constraints or other limits.
1459 * HDMI minimum is 8bpc however.
1464 * We will never exceed downstream TMDS clock limits while
1465 * attempting deep color. If the user insists on forcing an
1466 * out of spec mode they will have to be satisfied with 8bpc.
1468 if (!respect_downstream_limits)
1471 for (; bpc >= 8; bpc -= 2) {
1472 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1473 intel_dp_has_hdmi_sink(intel_dp)) &&
1474 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1475 respect_downstream_limits) == MODE_OK)
1482 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1483 const struct intel_crtc_state *crtc_state,
1484 bool respect_downstream_limits)
1486 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1487 struct intel_connector *intel_connector = intel_dp->attached_connector;
1490 bpc = crtc_state->pipe_bpp / 3;
1492 if (intel_dp->dfp.max_bpc)
1493 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1495 if (intel_dp->dfp.min_tmds_clock) {
1498 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1499 respect_downstream_limits);
1500 if (max_hdmi_bpc < 0)
1503 bpc = min(bpc, max_hdmi_bpc);
1507 if (intel_dp_is_edp(intel_dp)) {
1508 /* Get bpp from vbt only for panels that dont have bpp in edid */
1509 if (intel_connector->base.display_info.bpc == 0 &&
1510 intel_connector->panel.vbt.edp.bpp &&
1511 intel_connector->panel.vbt.edp.bpp < bpp) {
1512 drm_dbg_kms(&dev_priv->drm,
1513 "clamping bpp for eDP panel to BIOS-provided %i\n",
1514 intel_connector->panel.vbt.edp.bpp);
1515 bpp = intel_connector->panel.vbt.edp.bpp;
1522 /* Adjust link config limits based on compliance test requests. */
1524 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1525 struct intel_crtc_state *pipe_config,
1526 struct link_config_limits *limits)
1528 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1530 /* For DP Compliance we override the computed bpp for the pipe */
1531 if (intel_dp->compliance.test_data.bpc != 0) {
1532 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1534 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1535 pipe_config->dither_force_disable = bpp == 6 * 3;
1537 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1540 /* Use values requested by Compliance Test Request */
1541 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1544 /* Validate the compliance test data since max values
1545 * might have changed due to link train fallback.
1547 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1548 intel_dp->compliance.test_lane_count)) {
1549 index = intel_dp_rate_index(intel_dp->common_rates,
1550 intel_dp->num_common_rates,
1551 intel_dp->compliance.test_link_rate);
1553 limits->min_rate = limits->max_rate =
1554 intel_dp->compliance.test_link_rate;
1555 limits->min_lane_count = limits->max_lane_count =
1556 intel_dp->compliance.test_lane_count;
1561 static bool has_seamless_m_n(struct intel_connector *connector)
1563 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1566 * Seamless M/N reprogramming only implemented
1567 * for BDW+ double buffered M/N registers so far.
1569 return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1570 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1573 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1574 const struct drm_connector_state *conn_state)
1576 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1577 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1579 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1580 if (has_seamless_m_n(connector))
1581 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1583 return adjusted_mode->crtc_clock;
1586 /* Optimize link config in order: max bpp, min clock, min lanes */
1588 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1589 struct intel_crtc_state *pipe_config,
1590 const struct drm_connector_state *conn_state,
1591 const struct link_config_limits *limits)
1593 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1594 int mode_rate, link_rate, link_avail;
1596 for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1597 bpp >= to_bpp_int(limits->link.min_bpp_x16);
1599 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1601 mode_rate = intel_dp_link_required(clock, link_bpp);
1603 for (i = 0; i < intel_dp->num_common_rates; i++) {
1604 link_rate = intel_dp_common_rate(intel_dp, i);
1605 if (link_rate < limits->min_rate ||
1606 link_rate > limits->max_rate)
1609 for (lane_count = limits->min_lane_count;
1610 lane_count <= limits->max_lane_count;
1612 link_avail = intel_dp_max_data_rate(link_rate,
1615 if (mode_rate <= link_avail) {
1616 pipe_config->lane_count = lane_count;
1617 pipe_config->pipe_bpp = bpp;
1618 pipe_config->port_clock = link_rate;
1630 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1632 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1633 if (DISPLAY_VER(i915) >= 12)
1635 if (DISPLAY_VER(i915) == 11)
1641 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1644 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1649 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1654 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1656 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1658 for (i = 0; i < num_bpc; i++) {
1659 if (dsc_max_bpc >= dsc_bpc[i])
1660 return dsc_bpc[i] * 3;
1666 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1668 return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1671 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1673 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1677 static int intel_dp_get_slice_height(int vactive)
1682 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1683 * lines is an optimal slice height, but any size can be used as long as
1684 * vertical active integer multiple and maximum vertical slice count
1685 * requirements are met.
1687 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1688 if (vactive % slice_height == 0)
1689 return slice_height;
1692 * Highly unlikely we reach here as most of the resolutions will end up
1693 * finding appropriate slice_height in above loop but returning
1694 * slice_height as 2 here as it should work with all resolutions.
1699 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1700 struct intel_crtc_state *crtc_state)
1702 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1703 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1708 * RC_MODEL_SIZE is currently a constant across all configurations.
1710 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1711 * DP_DSC_RC_BUF_SIZE for this.
1713 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1714 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1716 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1718 ret = intel_dsc_compute_params(crtc_state);
1722 vdsc_cfg->dsc_version_major =
1723 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1724 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1725 vdsc_cfg->dsc_version_minor =
1726 min(intel_dp_source_dsc_version_minor(i915),
1727 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1728 if (vdsc_cfg->convert_rgb)
1729 vdsc_cfg->convert_rgb =
1730 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1733 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1734 if (!line_buf_depth) {
1735 drm_dbg_kms(&i915->drm,
1736 "DSC Sink Line Buffer Depth invalid\n");
1740 if (vdsc_cfg->dsc_version_minor == 2)
1741 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1742 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1744 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1745 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1747 vdsc_cfg->block_pred_enable =
1748 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1749 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1751 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1754 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1755 enum intel_output_format output_format)
1757 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1760 switch (output_format) {
1761 case INTEL_OUTPUT_FORMAT_RGB:
1762 sink_dsc_format = DP_DSC_RGB;
1764 case INTEL_OUTPUT_FORMAT_YCBCR444:
1765 sink_dsc_format = DP_DSC_YCbCr444;
1767 case INTEL_OUTPUT_FORMAT_YCBCR420:
1768 if (min(intel_dp_source_dsc_version_minor(i915),
1769 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1771 sink_dsc_format = DP_DSC_YCbCr420_Native;
1777 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1780 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1781 u32 lane_count, u32 mode_clock,
1782 enum intel_output_format output_format,
1785 u32 available_bw, required_bw;
1787 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1788 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1790 return available_bw > required_bw;
1793 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1794 struct intel_crtc_state *pipe_config,
1795 struct link_config_limits *limits,
1796 u16 compressed_bppx16,
1799 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1800 int link_rate, lane_count;
1803 for (i = 0; i < intel_dp->num_common_rates; i++) {
1804 link_rate = intel_dp_common_rate(intel_dp, i);
1805 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1808 for (lane_count = limits->min_lane_count;
1809 lane_count <= limits->max_lane_count;
1811 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1812 lane_count, adjusted_mode->clock,
1813 pipe_config->output_format,
1817 pipe_config->lane_count = lane_count;
1818 pipe_config->port_clock = link_rate;
1828 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1829 struct intel_crtc_state *pipe_config,
1832 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1837 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1838 * values as given in spec Table 2-157 DP v2.0
1840 switch (pipe_config->output_format) {
1841 case INTEL_OUTPUT_FORMAT_RGB:
1842 case INTEL_OUTPUT_FORMAT_YCBCR444:
1843 return (3 * bpc) << 4;
1844 case INTEL_OUTPUT_FORMAT_YCBCR420:
1845 return (3 * (bpc / 2)) << 4;
1847 MISSING_CASE(pipe_config->output_format);
1854 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1856 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1857 switch (pipe_config->output_format) {
1858 case INTEL_OUTPUT_FORMAT_RGB:
1859 case INTEL_OUTPUT_FORMAT_YCBCR444:
1861 case INTEL_OUTPUT_FORMAT_YCBCR420:
1864 MISSING_CASE(pipe_config->output_format);
1871 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1872 struct intel_crtc_state *pipe_config,
1875 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1876 pipe_config, bpc) >> 4;
1879 static int dsc_src_min_compressed_bpp(void)
1881 /* Min Compressed bpp supported by source is 8 */
1885 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1887 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1890 * Max Compressed bpp for Gen 13+ is 27bpp.
1891 * For earlier platform is 23bpp. (Bspec:49259).
1893 if (DISPLAY_VER(i915) < 13)
1900 * From a list of valid compressed bpps try different compressed bpp and find a
1901 * suitable link configuration that can support it.
1904 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1905 struct intel_crtc_state *pipe_config,
1906 struct link_config_limits *limits,
1914 /* Compressed BPP should be less than the Input DSC bpp */
1915 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1917 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1918 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1919 valid_dsc_bpp[i] > dsc_max_bpp)
1922 ret = dsc_compute_link_config(intel_dp,
1925 valid_dsc_bpp[i] << 4,
1928 pipe_config->dsc.compressed_bpp_x16 =
1929 to_bpp_x16(valid_dsc_bpp[i]);
1938 * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1939 * uncompressed bpp-1. So we start from max compressed bpp and see if any
1940 * link configuration is able to support that compressed bpp, if not we
1941 * step down and check for lower compressed bpp.
1944 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1945 const struct intel_connector *connector,
1946 struct intel_crtc_state *pipe_config,
1947 struct link_config_limits *limits,
1953 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1954 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1955 u16 compressed_bppx16;
1959 if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1962 bppx16_step = 16 / bppx16_incr;
1964 /* Compressed BPP should be less than the Input DSC bpp */
1965 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1966 dsc_min_bpp = dsc_min_bpp << 4;
1968 for (compressed_bppx16 = dsc_max_bpp;
1969 compressed_bppx16 >= dsc_min_bpp;
1970 compressed_bppx16 -= bppx16_step) {
1971 if (intel_dp->force_dsc_fractional_bpp_en &&
1972 !to_bpp_frac(compressed_bppx16))
1974 ret = dsc_compute_link_config(intel_dp,
1980 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1981 if (intel_dp->force_dsc_fractional_bpp_en &&
1982 to_bpp_frac(compressed_bppx16))
1983 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1991 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1992 const struct intel_connector *connector,
1993 struct intel_crtc_state *pipe_config,
1994 struct link_config_limits *limits,
1998 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1999 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2000 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2001 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2002 int dsc_joiner_max_bpp;
2004 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2005 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2006 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2007 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2009 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2010 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2013 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2015 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2016 adjusted_mode->hdisplay,
2017 pipe_config->bigjoiner_pipes);
2018 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2019 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2021 if (DISPLAY_VER(i915) >= 13)
2022 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2023 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2024 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2025 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2029 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2031 /* Min DSC Input BPC for ICL+ is 8 */
2032 return HAS_DSC(i915) ? 8 : 0;
2036 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2037 struct drm_connector_state *conn_state,
2038 struct link_config_limits *limits,
2041 u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2043 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2044 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2046 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2047 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2049 return pipe_bpp >= dsc_min_pipe_bpp &&
2050 pipe_bpp <= dsc_max_pipe_bpp;
2054 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2055 struct drm_connector_state *conn_state,
2056 struct link_config_limits *limits)
2058 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2061 if (!intel_dp->force_dsc_bpc)
2064 forced_bpp = intel_dp->force_dsc_bpc * 3;
2066 if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2067 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2071 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2072 intel_dp->force_dsc_bpc);
2077 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2078 struct intel_crtc_state *pipe_config,
2079 struct drm_connector_state *conn_state,
2080 struct link_config_limits *limits,
2083 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2084 const struct intel_connector *connector =
2085 to_intel_connector(conn_state->connector);
2086 u8 max_req_bpc = conn_state->max_requested_bpc;
2087 u8 dsc_max_bpc, dsc_max_bpp;
2088 u8 dsc_min_bpc, dsc_min_bpp;
2090 int forced_bpp, pipe_bpp;
2091 int num_bpc, i, ret;
2093 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2096 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2097 limits, forced_bpp, timeslots);
2099 pipe_config->pipe_bpp = forced_bpp;
2104 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2108 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2109 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2111 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2112 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2115 * Get the maximum DSC bpc that will be supported by any valid
2116 * link configuration and compressed bpp.
2118 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2119 for (i = 0; i < num_bpc; i++) {
2120 pipe_bpp = dsc_bpc[i] * 3;
2121 if (pipe_bpp < dsc_min_bpp)
2123 if (pipe_bpp > dsc_max_bpp)
2125 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2126 limits, pipe_bpp, timeslots);
2128 pipe_config->pipe_bpp = pipe_bpp;
2136 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2137 struct intel_crtc_state *pipe_config,
2138 struct drm_connector_state *conn_state,
2139 struct link_config_limits *limits)
2141 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2142 struct intel_connector *connector =
2143 to_intel_connector(conn_state->connector);
2144 int pipe_bpp, forced_bpp;
2145 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2146 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2148 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2151 pipe_bpp = forced_bpp;
2153 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2155 /* For eDP use max bpp that can be supported with DSC. */
2156 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2157 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2158 drm_dbg_kms(&i915->drm,
2159 "Computed BPC is not in DSC BPC limits\n");
2163 pipe_config->port_clock = limits->max_rate;
2164 pipe_config->lane_count = limits->max_lane_count;
2166 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2167 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2168 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2169 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2171 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2172 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2175 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2176 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2178 /* Compressed BPP should be less than the Input DSC bpp */
2179 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2181 pipe_config->dsc.compressed_bpp_x16 =
2182 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2184 pipe_config->pipe_bpp = pipe_bpp;
2189 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2190 struct intel_crtc_state *pipe_config,
2191 struct drm_connector_state *conn_state,
2192 struct link_config_limits *limits,
2194 bool compute_pipe_bpp)
2196 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2197 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2198 const struct intel_connector *connector =
2199 to_intel_connector(conn_state->connector);
2200 const struct drm_display_mode *adjusted_mode =
2201 &pipe_config->hw.adjusted_mode;
2204 pipe_config->fec_enable = pipe_config->fec_enable ||
2205 (!intel_dp_is_edp(intel_dp) &&
2206 intel_dp_supports_fec(intel_dp, connector, pipe_config));
2208 if (!intel_dp_supports_dsc(connector, pipe_config))
2211 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2215 * compute pipe bpp is set to false for DP MST DSC case
2216 * and compressed_bpp is calculated same time once
2217 * vpci timeslots are allocated, because overall bpp
2218 * calculation procedure is bit different for MST case.
2220 if (compute_pipe_bpp) {
2221 if (intel_dp_is_edp(intel_dp))
2222 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2223 conn_state, limits);
2225 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2226 conn_state, limits, timeslots);
2228 drm_dbg_kms(&dev_priv->drm,
2229 "No Valid pipe bpp for given mode ret = %d\n", ret);
2234 /* Calculate Slice count */
2235 if (intel_dp_is_edp(intel_dp)) {
2236 pipe_config->dsc.slice_count =
2237 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2239 if (!pipe_config->dsc.slice_count) {
2240 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2241 pipe_config->dsc.slice_count);
2245 u8 dsc_dp_slice_count;
2247 dsc_dp_slice_count =
2248 intel_dp_dsc_get_slice_count(connector,
2249 adjusted_mode->crtc_clock,
2250 adjusted_mode->crtc_hdisplay,
2251 pipe_config->bigjoiner_pipes);
2252 if (!dsc_dp_slice_count) {
2253 drm_dbg_kms(&dev_priv->drm,
2254 "Compressed Slice Count not supported\n");
2258 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2261 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2262 * is greater than the maximum Cdclock and if slice count is even
2263 * then we need to use 2 VDSC instances.
2265 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2266 pipe_config->dsc.dsc_split = true;
2268 ret = intel_dp_dsc_compute_params(connector, pipe_config);
2270 drm_dbg_kms(&dev_priv->drm,
2271 "Cannot compute valid DSC parameters for Input Bpp = %d"
2272 "Compressed BPP = " BPP_X16_FMT "\n",
2273 pipe_config->pipe_bpp,
2274 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2278 pipe_config->dsc.compression_enable = true;
2279 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2280 "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2281 pipe_config->pipe_bpp,
2282 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2283 pipe_config->dsc.slice_count);
2289 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2290 * @intel_dp: intel DP
2291 * @crtc_state: crtc state
2292 * @dsc: DSC compression mode
2293 * @limits: link configuration limits
2295 * Calculates the output link min, max bpp values in @limits based on the
2296 * pipe bpp range, @crtc_state and @dsc mode.
2298 * Returns %true in case of success.
2301 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2302 const struct intel_crtc_state *crtc_state,
2304 struct link_config_limits *limits)
2306 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2307 const struct drm_display_mode *adjusted_mode =
2308 &crtc_state->hw.adjusted_mode;
2309 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2310 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2311 int max_link_bpp_x16;
2313 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2314 to_bpp_x16(limits->pipe.max_bpp));
2317 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2319 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2322 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2325 * TODO: set the DSC link limits already here, atm these are
2326 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2327 * intel_dp_dsc_compute_pipe_bpp()
2329 limits->link.min_bpp_x16 = 0;
2332 limits->link.max_bpp_x16 = max_link_bpp_x16;
2334 drm_dbg_kms(&i915->drm,
2335 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2336 encoder->base.base.id, encoder->base.name,
2337 crtc->base.base.id, crtc->base.name,
2338 adjusted_mode->crtc_clock,
2340 limits->max_lane_count,
2342 limits->pipe.max_bpp,
2343 BPP_X16_ARGS(limits->link.max_bpp_x16));
2349 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2350 struct intel_crtc_state *crtc_state,
2351 bool respect_downstream_limits,
2353 struct link_config_limits *limits)
2355 limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2356 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2358 limits->min_lane_count = 1;
2359 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2361 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2362 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2363 respect_downstream_limits);
2365 if (intel_dp->use_max_params) {
2367 * Use the maximum clock and number of lanes the eDP panel
2368 * advertizes being capable of in case the initial fast
2369 * optimal params failed us. The panels are generally
2370 * designed to support only a single clock and lane
2371 * configuration, and typically on older panels these
2372 * values correspond to the native resolution of the panel.
2374 limits->min_lane_count = limits->max_lane_count;
2375 limits->min_rate = limits->max_rate;
2378 intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2380 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2387 intel_dp_compute_link_config(struct intel_encoder *encoder,
2388 struct intel_crtc_state *pipe_config,
2389 struct drm_connector_state *conn_state,
2390 bool respect_downstream_limits)
2392 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2393 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2394 const struct intel_connector *connector =
2395 to_intel_connector(conn_state->connector);
2396 const struct drm_display_mode *adjusted_mode =
2397 &pipe_config->hw.adjusted_mode;
2398 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2399 struct link_config_limits limits;
2400 bool joiner_needs_dsc = false;
2404 if (pipe_config->fec_enable &&
2405 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2408 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2409 adjusted_mode->crtc_clock))
2410 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2413 * Pipe joiner needs compression up to display 12 due to bandwidth
2414 * limitation. DG2 onwards pipe joiner can be enabled without
2417 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2419 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2420 !intel_dp_compute_config_limits(intel_dp, pipe_config,
2421 respect_downstream_limits,
2427 * Optimize for slow and wide for everything, because there are some
2428 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2430 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2431 conn_state, &limits);
2437 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2438 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2439 str_yes_no(intel_dp->force_dsc_en));
2441 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2442 respect_downstream_limits,
2447 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2448 conn_state, &limits, 64, true);
2453 if (pipe_config->dsc.compression_enable) {
2454 drm_dbg_kms(&i915->drm,
2455 "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
2456 pipe_config->lane_count, pipe_config->port_clock,
2457 pipe_config->pipe_bpp,
2458 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2460 drm_dbg_kms(&i915->drm,
2461 "DP link rate required %i available %i\n",
2462 intel_dp_link_required(adjusted_mode->crtc_clock,
2463 to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
2464 intel_dp_max_data_rate(pipe_config->port_clock,
2465 pipe_config->lane_count));
2467 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2468 pipe_config->lane_count, pipe_config->port_clock,
2469 pipe_config->pipe_bpp);
2471 drm_dbg_kms(&i915->drm,
2472 "DP link rate required %i available %i\n",
2473 intel_dp_link_required(adjusted_mode->crtc_clock,
2474 pipe_config->pipe_bpp),
2475 intel_dp_max_data_rate(pipe_config->port_clock,
2476 pipe_config->lane_count));
2481 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2482 const struct drm_connector_state *conn_state)
2484 const struct intel_digital_connector_state *intel_conn_state =
2485 to_intel_digital_connector_state(conn_state);
2486 const struct drm_display_mode *adjusted_mode =
2487 &crtc_state->hw.adjusted_mode;
2490 * Our YCbCr output is always limited range.
2491 * crtc_state->limited_color_range only applies to RGB,
2492 * and it must never be set for YCbCr or we risk setting
2493 * some conflicting bits in TRANSCONF which will mess up
2494 * the colors on the monitor.
2496 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2499 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2502 * CEA-861-E - 5.1 Default Encoding Parameters
2503 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2505 return crtc_state->pipe_bpp != 18 &&
2506 drm_default_rgb_quant_range(adjusted_mode) ==
2507 HDMI_QUANTIZATION_RANGE_LIMITED;
2509 return intel_conn_state->broadcast_rgb ==
2510 INTEL_BROADCAST_RGB_LIMITED;
2514 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2517 if (IS_G4X(dev_priv))
2519 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2525 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2526 const struct drm_connector_state *conn_state,
2527 struct drm_dp_vsc_sdp *vsc)
2529 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2530 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2532 if (crtc_state->has_panel_replay) {
2534 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2535 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2536 * Encoding/Colorimetry Format indication.
2538 vsc->revision = 0x7;
2541 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2542 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2543 * Colorimetry Format indication.
2545 vsc->revision = 0x5;
2550 /* DP 1.4a spec, Table 2-120 */
2551 switch (crtc_state->output_format) {
2552 case INTEL_OUTPUT_FORMAT_YCBCR444:
2553 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2555 case INTEL_OUTPUT_FORMAT_YCBCR420:
2556 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2558 case INTEL_OUTPUT_FORMAT_RGB:
2560 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2563 switch (conn_state->colorspace) {
2564 case DRM_MODE_COLORIMETRY_BT709_YCC:
2565 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2567 case DRM_MODE_COLORIMETRY_XVYCC_601:
2568 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2570 case DRM_MODE_COLORIMETRY_XVYCC_709:
2571 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2573 case DRM_MODE_COLORIMETRY_SYCC_601:
2574 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2576 case DRM_MODE_COLORIMETRY_OPYCC_601:
2577 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2579 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2580 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2582 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2583 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2585 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2586 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2588 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2589 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2590 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2594 * RGB->YCBCR color conversion uses the BT.709
2597 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2598 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2600 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2604 vsc->bpc = crtc_state->pipe_bpp / 3;
2606 /* only RGB pixelformat supports 6 bpc */
2607 drm_WARN_ON(&dev_priv->drm,
2608 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2610 /* all YCbCr are always limited range */
2611 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2612 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2615 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2616 struct intel_crtc_state *crtc_state,
2617 const struct drm_connector_state *conn_state)
2619 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2621 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2622 if (crtc_state->has_psr)
2625 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2628 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2629 vsc->sdp_type = DP_SDP_VSC;
2630 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2631 &crtc_state->infoframes.vsc);
2634 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2635 const struct intel_crtc_state *crtc_state,
2636 const struct drm_connector_state *conn_state,
2637 struct drm_dp_vsc_sdp *vsc)
2639 vsc->sdp_type = DP_SDP_VSC;
2641 if (crtc_state->has_psr2) {
2642 if (intel_dp->psr.colorimetry_support &&
2643 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2644 /* [PSR2, +Colorimetry] */
2645 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2649 * [PSR2, -Colorimetry]
2650 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2651 * 3D stereo + PSR/PSR2 + Y-coordinate.
2653 vsc->revision = 0x4;
2656 } else if (crtc_state->has_panel_replay) {
2657 if (intel_dp->psr.colorimetry_support &&
2658 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2659 /* [Panel Replay with colorimetry info] */
2660 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2664 * [Panel Replay without colorimetry info]
2665 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2666 * VSC SDP supporting 3D stereo + Panel Replay.
2668 vsc->revision = 0x6;
2674 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2675 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2678 vsc->revision = 0x2;
2684 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2685 struct intel_crtc_state *crtc_state,
2686 const struct drm_connector_state *conn_state)
2689 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2690 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2692 if (!conn_state->hdr_output_metadata)
2695 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2698 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2702 crtc_state->infoframes.enable |=
2703 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2706 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2707 enum transcoder cpu_transcoder)
2709 if (HAS_DOUBLE_BUFFERED_M_N(i915))
2712 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2715 static bool can_enable_drrs(struct intel_connector *connector,
2716 const struct intel_crtc_state *pipe_config,
2717 const struct drm_display_mode *downclock_mode)
2719 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2721 if (pipe_config->vrr.enable)
2725 * DRRS and PSR can't be enable together, so giving preference to PSR
2726 * as it allows more power-savings by complete shutting down display,
2727 * so to guarantee this, intel_drrs_compute_config() must be called
2728 * after intel_psr_compute_config().
2730 if (pipe_config->has_psr)
2733 /* FIXME missing FDI M2/N2 etc. */
2734 if (pipe_config->has_pch_encoder)
2737 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2740 return downclock_mode &&
2741 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2745 intel_dp_drrs_compute_config(struct intel_connector *connector,
2746 struct intel_crtc_state *pipe_config,
2749 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2750 const struct drm_display_mode *downclock_mode =
2751 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2754 if (has_seamless_m_n(connector))
2755 pipe_config->update_m_n = true;
2757 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2758 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2759 intel_zero_m_n(&pipe_config->dp_m2_n2);
2763 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2764 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2766 pipe_config->has_drrs = true;
2768 pixel_clock = downclock_mode->clock;
2769 if (pipe_config->splitter.enable)
2770 pixel_clock /= pipe_config->splitter.link_count;
2772 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2773 pipe_config->port_clock,
2774 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2775 &pipe_config->dp_m2_n2);
2777 /* FIXME: abstract this better */
2778 if (pipe_config->splitter.enable)
2779 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2782 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2783 struct intel_crtc_state *crtc_state,
2784 const struct drm_connector_state *conn_state)
2786 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2787 const struct intel_digital_connector_state *intel_conn_state =
2788 to_intel_digital_connector_state(conn_state);
2789 struct intel_connector *connector =
2790 to_intel_connector(conn_state->connector);
2792 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2793 !intel_dp_port_has_audio(i915, encoder->port))
2796 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2797 return connector->base.display_info.has_audio;
2799 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2803 intel_dp_compute_output_format(struct intel_encoder *encoder,
2804 struct intel_crtc_state *crtc_state,
2805 struct drm_connector_state *conn_state,
2806 bool respect_downstream_limits)
2808 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2809 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2810 struct intel_connector *connector = intel_dp->attached_connector;
2811 const struct drm_display_info *info = &connector->base.display_info;
2812 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2813 bool ycbcr_420_only;
2816 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2818 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2819 drm_dbg_kms(&i915->drm,
2820 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2821 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2823 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2826 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2828 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2829 respect_downstream_limits);
2831 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2832 !connector->base.ycbcr_420_allowed ||
2833 !drm_mode_is_420_also(info, adjusted_mode))
2836 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2837 crtc_state->output_format = intel_dp_output_format(connector,
2838 crtc_state->sink_format);
2839 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2840 respect_downstream_limits);
2847 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2848 struct intel_crtc_state *pipe_config,
2849 struct drm_connector_state *conn_state)
2851 pipe_config->has_audio =
2852 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2853 intel_audio_compute_config(encoder, pipe_config, conn_state);
2855 pipe_config->sdp_split_enable = pipe_config->has_audio &&
2856 intel_dp_is_uhbr(pipe_config);
2860 intel_dp_compute_config(struct intel_encoder *encoder,
2861 struct intel_crtc_state *pipe_config,
2862 struct drm_connector_state *conn_state)
2864 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2865 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2867 const struct drm_display_mode *fixed_mode;
2868 struct intel_connector *connector = intel_dp->attached_connector;
2869 int ret = 0, link_bpp_x16;
2871 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2872 pipe_config->has_pch_encoder = true;
2874 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2875 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2876 ret = intel_panel_compute_config(connector, adjusted_mode);
2881 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2884 if (!connector->base.interlace_allowed &&
2885 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2888 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2891 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2895 * Try to respect downstream TMDS clock limits first, if
2896 * that fails assume the user might know something we don't.
2898 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2900 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2904 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2905 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2906 ret = intel_panel_fitting(pipe_config, conn_state);
2911 pipe_config->limited_color_range =
2912 intel_dp_limited_color_range(pipe_config, conn_state);
2914 pipe_config->enhanced_framing =
2915 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2917 if (pipe_config->dsc.compression_enable)
2918 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2920 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2921 pipe_config->pipe_bpp));
2923 if (intel_dp->mso_link_count) {
2924 int n = intel_dp->mso_link_count;
2925 int overlap = intel_dp->mso_pixel_overlap;
2927 pipe_config->splitter.enable = true;
2928 pipe_config->splitter.link_count = n;
2929 pipe_config->splitter.pixel_overlap = overlap;
2931 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2934 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2935 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2936 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2937 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2938 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2939 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2940 adjusted_mode->crtc_clock /= n;
2943 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2945 intel_link_compute_m_n(link_bpp_x16,
2946 pipe_config->lane_count,
2947 adjusted_mode->crtc_clock,
2948 pipe_config->port_clock,
2949 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2950 &pipe_config->dp_m_n);
2952 /* FIXME: abstract this better */
2953 if (pipe_config->splitter.enable)
2954 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2956 if (!HAS_DDI(dev_priv))
2957 g4x_dp_set_clock(encoder, pipe_config);
2959 intel_vrr_compute_config(pipe_config, conn_state);
2960 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2961 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2962 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2963 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2968 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2969 int link_rate, int lane_count)
2971 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2972 intel_dp->link_trained = false;
2973 intel_dp->link_rate = link_rate;
2974 intel_dp->lane_count = lane_count;
2977 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2979 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2980 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2983 /* Enable backlight PWM and backlight PP control. */
2984 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2985 const struct drm_connector_state *conn_state)
2987 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2988 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2990 if (!intel_dp_is_edp(intel_dp))
2993 drm_dbg_kms(&i915->drm, "\n");
2995 intel_backlight_enable(crtc_state, conn_state);
2996 intel_pps_backlight_on(intel_dp);
2999 /* Disable backlight PP control and backlight PWM. */
3000 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3002 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3003 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3005 if (!intel_dp_is_edp(intel_dp))
3008 drm_dbg_kms(&i915->drm, "\n");
3010 intel_pps_backlight_off(intel_dp);
3011 intel_backlight_disable(old_conn_state);
3014 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3017 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3018 * be capable of signalling downstream hpd with a long pulse.
3019 * Whether or not that means D3 is safe to use is not clear,
3020 * but let's assume so until proven otherwise.
3022 * FIXME should really check all downstream ports...
3024 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3025 drm_dp_is_branch(intel_dp->dpcd) &&
3026 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3030 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3035 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3044 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3048 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3051 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3053 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3054 DP_DECOMPRESSION_EN, enable) < 0)
3055 drm_dbg_kms(&i915->drm,
3056 "Failed to %s sink decompression state\n",
3057 str_enable_disable(enable));
3061 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3064 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3065 struct drm_dp_aux *aux = connector->port ?
3066 connector->port->passthrough_aux : NULL;
3071 if (write_dsc_decompression_flag(aux,
3072 DP_DSC_PASSTHROUGH_EN, enable) < 0)
3073 drm_dbg_kms(&i915->drm,
3074 "Failed to %s sink compression passthrough state\n",
3075 str_enable_disable(enable));
3078 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3079 const struct intel_connector *connector,
3082 struct drm_i915_private *i915 = to_i915(state->base.dev);
3083 struct drm_connector *_connector_iter;
3084 struct drm_connector_state *old_conn_state;
3085 struct drm_connector_state *new_conn_state;
3090 * On SST the decompression AUX device won't be shared, each connector
3091 * uses for this its own AUX targeting the sink device.
3093 if (!connector->mst_port)
3094 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3096 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3097 old_conn_state, new_conn_state, i) {
3098 const struct intel_connector *
3099 connector_iter = to_intel_connector(_connector_iter);
3101 if (connector_iter->mst_port != connector->mst_port)
3104 if (!connector_iter->dp.dsc_decompression_enabled)
3107 drm_WARN_ON(&i915->drm,
3108 (for_get_ref && !new_conn_state->crtc) ||
3109 (!for_get_ref && !old_conn_state->crtc));
3111 if (connector_iter->dp.dsc_decompression_aux ==
3112 connector->dp.dsc_decompression_aux)
3119 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3120 struct intel_connector *connector)
3122 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3124 connector->dp.dsc_decompression_enabled = true;
3129 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3130 struct intel_connector *connector)
3132 connector->dp.dsc_decompression_enabled = false;
3134 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3138 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3139 * @state: atomic state
3140 * @connector: connector to enable the decompression for
3141 * @new_crtc_state: new state for the CRTC driving @connector
3143 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3144 * register of the appropriate sink/branch device. On SST this is always the
3145 * sink device, whereas on MST based on each device's DSC capabilities it's
3146 * either the last branch device (enabling decompression in it) or both the
3147 * last branch device (enabling passthrough in it) and the sink device
3148 * (enabling decompression in it).
3150 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3151 struct intel_connector *connector,
3152 const struct intel_crtc_state *new_crtc_state)
3154 struct drm_i915_private *i915 = to_i915(state->base.dev);
3156 if (!new_crtc_state->dsc.compression_enable)
3159 if (drm_WARN_ON(&i915->drm,
3160 !connector->dp.dsc_decompression_aux ||
3161 connector->dp.dsc_decompression_enabled))
3164 if (!intel_dp_dsc_aux_get_ref(state, connector))
3167 intel_dp_sink_set_dsc_passthrough(connector, true);
3168 intel_dp_sink_set_dsc_decompression(connector, true);
3172 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3173 * @state: atomic state
3174 * @connector: connector to disable the decompression for
3175 * @old_crtc_state: old state for the CRTC driving @connector
3177 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3178 * register of the appropriate sink/branch device, corresponding to the
3179 * sequence in intel_dp_sink_enable_decompression().
3181 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3182 struct intel_connector *connector,
3183 const struct intel_crtc_state *old_crtc_state)
3185 struct drm_i915_private *i915 = to_i915(state->base.dev);
3187 if (!old_crtc_state->dsc.compression_enable)
3190 if (drm_WARN_ON(&i915->drm,
3191 !connector->dp.dsc_decompression_aux ||
3192 !connector->dp.dsc_decompression_enabled))
3195 if (!intel_dp_dsc_aux_put_ref(state, connector))
3198 intel_dp_sink_set_dsc_decompression(connector, false);
3199 intel_dp_sink_set_dsc_passthrough(connector, false);
3203 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3205 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3206 u8 oui[] = { 0x00, 0xaa, 0x01 };
3210 * During driver init, we want to be careful and avoid changing the source OUI if it's
3211 * already set to what we want, so as to avoid clearing any state by accident
3214 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3215 drm_err(&i915->drm, "Failed to read source OUI\n");
3217 if (memcmp(oui, buf, sizeof(oui)) == 0)
3221 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3222 drm_err(&i915->drm, "Failed to write source OUI\n");
3224 intel_dp->last_oui_write = jiffies;
3227 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3229 struct intel_connector *connector = intel_dp->attached_connector;
3230 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3232 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3233 connector->base.base.id, connector->base.name,
3234 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3236 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3237 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3240 /* If the device supports it, try to set the power state appropriately */
3241 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3243 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3244 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3247 /* Should have a valid DPCD by this point */
3248 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3251 if (mode != DP_SET_POWER_D0) {
3252 if (downstream_hpd_needs_d0(intel_dp))
3255 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3257 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3259 lspcon_resume(dp_to_dig_port(intel_dp));
3261 /* Write the source OUI as early as possible */
3262 if (intel_dp_is_edp(intel_dp))
3263 intel_edp_init_source_oui(intel_dp, false);
3266 * When turning on, we need to retry for 1ms to give the sink
3269 for (i = 0; i < 3; i++) {
3270 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3276 if (ret == 1 && lspcon->active)
3277 lspcon_wait_pcon_mode(lspcon);
3281 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3282 encoder->base.base.id, encoder->base.name,
3283 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3287 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3290 * intel_dp_sync_state - sync the encoder state during init/resume
3291 * @encoder: intel encoder to sync
3292 * @crtc_state: state for the CRTC connected to the encoder
3294 * Sync any state stored in the encoder wrt. HW state during driver init
3295 * and system resume.
3297 void intel_dp_sync_state(struct intel_encoder *encoder,
3298 const struct intel_crtc_state *crtc_state)
3300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3306 * Don't clobber DPCD if it's been already read out during output
3307 * setup (eDP) or detect.
3309 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3310 intel_dp_get_dpcd(intel_dp);
3312 intel_dp_reset_max_link_params(intel_dp);
3315 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3316 struct intel_crtc_state *crtc_state)
3318 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3319 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3320 bool fastset = true;
3323 * If BIOS has set an unsupported or non-standard link rate for some
3324 * reason force an encoder recompute and full modeset.
3326 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3327 crtc_state->port_clock) < 0) {
3328 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3329 encoder->base.base.id, encoder->base.name);
3330 crtc_state->uapi.connectors_changed = true;
3335 * FIXME hack to force full modeset when DSC is being used.
3337 * As long as we do not have full state readout and config comparison
3338 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3339 * Remove once we have readout for DSC.
3341 if (crtc_state->dsc.compression_enable) {
3342 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3343 encoder->base.base.id, encoder->base.name);
3344 crtc_state->uapi.mode_changed = true;
3348 if (CAN_PSR(intel_dp)) {
3349 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
3350 encoder->base.base.id, encoder->base.name);
3351 crtc_state->uapi.mode_changed = true;
3358 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3360 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3362 /* Clear the cached register set to avoid using stale values */
3364 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3366 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3367 intel_dp->pcon_dsc_dpcd,
3368 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3369 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3370 DP_PCON_DSC_ENCODER);
3372 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3373 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3376 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3378 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3381 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3382 if (frl_bw_mask & (1 << i))
3388 static int intel_dp_pcon_set_frl_mask(int max_frl)
3392 return DP_PCON_FRL_BW_MASK_48GBPS;
3394 return DP_PCON_FRL_BW_MASK_40GBPS;
3396 return DP_PCON_FRL_BW_MASK_32GBPS;
3398 return DP_PCON_FRL_BW_MASK_24GBPS;
3400 return DP_PCON_FRL_BW_MASK_18GBPS;
3402 return DP_PCON_FRL_BW_MASK_9GBPS;
3408 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3410 struct intel_connector *intel_connector = intel_dp->attached_connector;
3411 struct drm_connector *connector = &intel_connector->base;
3413 int max_lanes, rate_per_lane;
3414 int max_dsc_lanes, dsc_rate_per_lane;
3416 max_lanes = connector->display_info.hdmi.max_lanes;
3417 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3418 max_frl_rate = max_lanes * rate_per_lane;
3420 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3421 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3422 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3423 if (max_dsc_lanes && dsc_rate_per_lane)
3424 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3427 return max_frl_rate;
3431 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3432 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3434 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3435 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3436 *frl_trained_mask >= max_frl_bw_mask)
3442 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3444 #define TIMEOUT_FRL_READY_MS 500
3445 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3447 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3448 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3449 u8 max_frl_bw_mask = 0, frl_trained_mask;
3452 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3453 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3455 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3456 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3458 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3460 if (max_frl_bw <= 0)
3463 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3464 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3466 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3469 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3472 /* Wait for PCON to be FRL Ready */
3473 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3478 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3479 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3482 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3483 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3486 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3490 * Wait for FRL to be completed
3491 * Check if the HDMI Link is up and active.
3493 wait_for(is_active =
3494 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3495 TIMEOUT_HDMI_LINK_ACTIVE_MS);
3501 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3502 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3503 intel_dp->frl.is_trained = true;
3504 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3509 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3511 if (drm_dp_is_branch(intel_dp->dpcd) &&
3512 intel_dp_has_hdmi_sink(intel_dp) &&
3513 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3520 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3525 /* Set PCON source control mode */
3526 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3528 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3532 /* Set HDMI LINK ENABLE */
3533 buf |= DP_PCON_ENABLE_HDMI_LINK;
3534 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3541 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3543 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3546 * Always go for FRL training if:
3547 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3550 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3551 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3552 intel_dp->frl.is_trained)
3555 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3558 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3559 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3560 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3562 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3563 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3565 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3570 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3572 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3574 return intel_hdmi_dsc_get_slice_height(vactive);
3578 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3579 const struct intel_crtc_state *crtc_state)
3581 struct intel_connector *intel_connector = intel_dp->attached_connector;
3582 struct drm_connector *connector = &intel_connector->base;
3583 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3584 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3585 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3586 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3588 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3589 pcon_max_slice_width,
3590 hdmi_max_slices, hdmi_throughput);
3594 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3595 const struct intel_crtc_state *crtc_state,
3596 int num_slices, int slice_width)
3598 struct intel_connector *intel_connector = intel_dp->attached_connector;
3599 struct drm_connector *connector = &intel_connector->base;
3600 int output_format = crtc_state->output_format;
3601 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3602 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3603 int hdmi_max_chunk_bytes =
3604 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3606 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3607 num_slices, output_format, hdmi_all_bpp,
3608 hdmi_max_chunk_bytes);
3612 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3613 const struct intel_crtc_state *crtc_state)
3621 struct intel_connector *intel_connector = intel_dp->attached_connector;
3622 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3623 struct drm_connector *connector;
3624 bool hdmi_is_dsc_1_2;
3626 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3629 if (!intel_connector)
3631 connector = &intel_connector->base;
3632 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3634 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3638 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3642 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3646 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3649 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3650 num_slices, slice_width);
3651 if (!bits_per_pixel)
3654 pps_param[0] = slice_height & 0xFF;
3655 pps_param[1] = slice_height >> 8;
3656 pps_param[2] = slice_width & 0xFF;
3657 pps_param[3] = slice_width >> 8;
3658 pps_param[4] = bits_per_pixel & 0xFF;
3659 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3661 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3663 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3666 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3667 const struct intel_crtc_state *crtc_state)
3669 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3670 bool ycbcr444_to_420 = false;
3671 bool rgb_to_ycbcr = false;
3674 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3677 if (!drm_dp_is_branch(intel_dp->dpcd))
3680 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3682 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3683 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3684 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3685 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3687 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3688 switch (crtc_state->output_format) {
3689 case INTEL_OUTPUT_FORMAT_YCBCR420:
3691 case INTEL_OUTPUT_FORMAT_YCBCR444:
3692 ycbcr444_to_420 = true;
3694 case INTEL_OUTPUT_FORMAT_RGB:
3695 rgb_to_ycbcr = true;
3696 ycbcr444_to_420 = true;
3699 MISSING_CASE(crtc_state->output_format);
3702 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3703 switch (crtc_state->output_format) {
3704 case INTEL_OUTPUT_FORMAT_YCBCR444:
3706 case INTEL_OUTPUT_FORMAT_RGB:
3707 rgb_to_ycbcr = true;
3710 MISSING_CASE(crtc_state->output_format);
3715 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3717 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3718 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3719 drm_dbg_kms(&i915->drm,
3720 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3721 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3723 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3725 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3726 drm_dbg_kms(&i915->drm,
3727 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3728 str_enable_disable(tmp));
3731 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3735 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3738 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3741 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3742 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3744 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3745 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3746 drm_err(aux->drm_dev,
3747 "Failed to read DPCD register 0x%x\n",
3752 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3753 DP_DSC_RECEIVER_CAP_SIZE,
3757 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3759 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3762 * Clear the cached register set to avoid using stale values
3763 * for the sinks that do not support DSC.
3765 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3767 /* Clear fec_capable to avoid using stale values */
3768 connector->dp.fec_capability = 0;
3770 if (dpcd_rev < DP_DPCD_REV_14)
3773 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3774 connector->dp.dsc_dpcd);
3776 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3777 &connector->dp.fec_capability) < 0) {
3778 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3782 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3783 connector->dp.fec_capability);
3786 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3788 if (edp_dpcd_rev < DP_EDP_14)
3791 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3794 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3795 struct drm_display_mode *mode)
3797 struct intel_dp *intel_dp = intel_attached_dp(connector);
3798 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3799 int n = intel_dp->mso_link_count;
3800 int overlap = intel_dp->mso_pixel_overlap;
3805 mode->hdisplay = (mode->hdisplay - overlap) * n;
3806 mode->hsync_start = (mode->hsync_start - overlap) * n;
3807 mode->hsync_end = (mode->hsync_end - overlap) * n;
3808 mode->htotal = (mode->htotal - overlap) * n;
3811 drm_mode_set_name(mode);
3813 drm_dbg_kms(&i915->drm,
3814 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3815 connector->base.base.id, connector->base.name,
3816 DRM_MODE_ARG(mode));
3819 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3821 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3822 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3823 struct intel_connector *connector = intel_dp->attached_connector;
3825 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3827 * This is a big fat ugly hack.
3829 * Some machines in UEFI boot mode provide us a VBT that has 18
3830 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3831 * unknown we fail to light up. Yet the same BIOS boots up with
3832 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3833 * max, not what it tells us to use.
3835 * Note: This will still be broken if the eDP panel is not lit
3836 * up by the BIOS, and thus we can't get the mode at module
3839 drm_dbg_kms(&dev_priv->drm,
3840 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3841 pipe_bpp, connector->panel.vbt.edp.bpp);
3842 connector->panel.vbt.edp.bpp = pipe_bpp;
3846 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3848 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3849 struct intel_connector *connector = intel_dp->attached_connector;
3850 struct drm_display_info *info = &connector->base.display_info;
3853 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3856 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3857 drm_err(&i915->drm, "Failed to read MSO cap\n");
3861 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3862 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3863 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3864 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3869 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3870 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3871 info->mso_pixel_overlap);
3872 if (!HAS_MSO(i915)) {
3873 drm_err(&i915->drm, "No source MSO support, disabling\n");
3878 intel_dp->mso_link_count = mso;
3879 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3883 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3885 struct drm_i915_private *dev_priv =
3886 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3888 /* this function is meant to be called only once */
3889 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3891 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3894 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3895 drm_dp_is_branch(intel_dp->dpcd));
3898 * Read the eDP display control registers.
3900 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3901 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3902 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3903 * method). The display control registers should read zero if they're
3904 * not supported anyway.
3906 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3907 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3908 sizeof(intel_dp->edp_dpcd)) {
3909 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3910 (int)sizeof(intel_dp->edp_dpcd),
3911 intel_dp->edp_dpcd);
3913 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3917 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3918 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3920 intel_psr_init_dpcd(intel_dp);
3922 /* Clear the default sink rates */
3923 intel_dp->num_sink_rates = 0;
3925 /* Read the eDP 1.4+ supported link rates. */
3926 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3927 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3930 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3931 sink_rates, sizeof(sink_rates));
3933 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3934 int val = le16_to_cpu(sink_rates[i]);
3939 /* Value read multiplied by 200kHz gives the per-lane
3940 * link rate in kHz. The source rates are, however,
3941 * stored in terms of LS_Clk kHz. The full conversion
3942 * back to symbols is
3943 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3945 intel_dp->sink_rates[i] = (val * 200) / 10;
3947 intel_dp->num_sink_rates = i;
3951 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3952 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3954 if (intel_dp->num_sink_rates)
3955 intel_dp->use_rate_select = true;
3957 intel_dp_set_sink_rates(intel_dp);
3958 intel_dp_set_max_sink_lane_count(intel_dp);
3960 /* Read the eDP DSC DPCD registers */
3961 if (HAS_DSC(dev_priv))
3962 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3966 * If needed, program our source OUI so we can make various Intel-specific AUX services
3967 * available (such as HDR backlight controls)
3969 intel_edp_init_source_oui(intel_dp, true);
3975 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3977 if (!intel_dp->attached_connector)
3980 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3986 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3990 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3994 * Don't clobber cached eDP rates. Also skip re-reading
3995 * the OUI/ID since we know it won't change.
3997 if (!intel_dp_is_edp(intel_dp)) {
3998 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3999 drm_dp_is_branch(intel_dp->dpcd));
4001 intel_dp_set_sink_rates(intel_dp);
4002 intel_dp_set_max_sink_lane_count(intel_dp);
4003 intel_dp_set_common_rates(intel_dp);
4006 if (intel_dp_has_sink_count(intel_dp)) {
4007 ret = drm_dp_read_sink_count(&intel_dp->aux);
4012 * Sink count can change between short pulse hpd hence
4013 * a member variable in intel_dp will track any changes
4014 * between short pulse interrupts.
4016 intel_dp->sink_count = ret;
4019 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4020 * a dongle is present but no display. Unless we require to know
4021 * if a dongle is present or not, we don't need to update
4022 * downstream port information. So, an early return here saves
4023 * time from performing other operations which are not required.
4025 if (!intel_dp->sink_count)
4029 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4030 intel_dp->downstream_ports) == 0;
4034 intel_dp_can_mst(struct intel_dp *intel_dp)
4036 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4038 return i915->display.params.enable_dp_mst &&
4039 intel_dp_mst_source_support(intel_dp) &&
4040 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4044 intel_dp_configure_mst(struct intel_dp *intel_dp)
4046 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4047 struct intel_encoder *encoder =
4048 &dp_to_dig_port(intel_dp)->base;
4049 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4051 drm_dbg_kms(&i915->drm,
4052 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4053 encoder->base.base.id, encoder->base.name,
4054 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4055 str_yes_no(sink_can_mst),
4056 str_yes_no(i915->display.params.enable_dp_mst));
4058 if (!intel_dp_mst_source_support(intel_dp))
4061 intel_dp->is_mst = sink_can_mst &&
4062 i915->display.params.enable_dp_mst;
4064 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4069 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4071 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4074 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4078 for (retry = 0; retry < 3; retry++) {
4079 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4088 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4089 const struct drm_connector_state *conn_state)
4092 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4093 * of Color Encoding Format and Content Color Gamut], in order to
4094 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4096 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4099 switch (conn_state->colorspace) {
4100 case DRM_MODE_COLORIMETRY_SYCC_601:
4101 case DRM_MODE_COLORIMETRY_OPYCC_601:
4102 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4103 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4104 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4113 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4114 struct dp_sdp *sdp, size_t size)
4116 size_t length = sizeof(struct dp_sdp);
4121 memset(sdp, 0, size);
4124 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4125 * VSC SDP Header Bytes
4127 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4128 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4129 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4130 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4132 if (vsc->revision == 0x6) {
4138 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
4139 * Format as per DP 1.4a spec and DP 2.0 respectively.
4141 if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
4144 /* VSC SDP Payload for DB16 through DB18 */
4145 /* Pixel Encoding and Colorimetry Formats */
4146 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4147 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4154 sdp->db[17] = 0x1; /* DB17[3:0] */
4166 MISSING_CASE(vsc->bpc);
4169 /* Dynamic Range and Component Bit Depth */
4170 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4171 sdp->db[17] |= 0x80; /* DB17[7] */
4174 sdp->db[18] = vsc->content_type & 0x7;
4181 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4182 const struct hdmi_drm_infoframe *drm_infoframe,
4186 size_t length = sizeof(struct dp_sdp);
4187 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4188 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4194 memset(sdp, 0, size);
4196 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4198 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4202 if (len != infoframe_size) {
4203 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4208 * Set up the infoframe sdp packet for HDR static metadata.
4209 * Prepare VSC Header for SU as per DP 1.4a spec,
4210 * Table 2-100 and Table 2-101
4213 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4214 sdp->sdp_header.HB0 = 0;
4216 * Packet Type 80h + Non-audio INFOFRAME Type value
4217 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4218 * - 80h + Non-audio INFOFRAME Type value
4219 * - InfoFrame Type: 0x07
4220 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4222 sdp->sdp_header.HB1 = drm_infoframe->type;
4224 * Least Significant Eight Bits of (Data Byte Count – 1)
4225 * infoframe_size - 1
4227 sdp->sdp_header.HB2 = 0x1D;
4228 /* INFOFRAME SDP Version Number */
4229 sdp->sdp_header.HB3 = (0x13 << 2);
4230 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4231 sdp->db[0] = drm_infoframe->version;
4232 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4233 sdp->db[1] = drm_infoframe->length;
4235 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4236 * HDMI_INFOFRAME_HEADER_SIZE
4238 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4239 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4240 HDMI_DRM_INFOFRAME_SIZE);
4243 * Size of DP infoframe sdp packet for HDR static metadata consists of
4244 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4245 * - Two Data Blocks: 2 bytes
4246 * CTA Header Byte2 (INFOFRAME Version Number)
4247 * CTA Header Byte3 (Length of INFOFRAME)
4248 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4250 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4251 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4252 * will pad rest of the size.
4254 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4257 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4258 const struct intel_crtc_state *crtc_state,
4261 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4263 struct dp_sdp sdp = {};
4266 if ((crtc_state->infoframes.enable &
4267 intel_hdmi_infoframe_enable(type)) == 0)
4272 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4275 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4276 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4277 &crtc_state->infoframes.drm.drm,
4285 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4288 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4291 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4292 const struct intel_crtc_state *crtc_state,
4293 const struct drm_dp_vsc_sdp *vsc)
4295 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4297 struct dp_sdp sdp = {};
4300 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4302 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4305 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
4309 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4311 const struct intel_crtc_state *crtc_state,
4312 const struct drm_connector_state *conn_state)
4314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4315 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4316 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4317 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4318 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4319 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4321 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4322 if (!enable && HAS_DSC(dev_priv))
4323 val &= ~VDIP_ENABLE_PPS;
4325 /* When PSR is enabled, this routine doesn't disable VSC DIP */
4326 if (!crtc_state->has_psr)
4327 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4329 intel_de_write(dev_priv, reg, val);
4330 intel_de_posting_read(dev_priv, reg);
4335 /* When PSR is enabled, VSC SDP is handled by PSR routine */
4336 if (!crtc_state->has_psr)
4337 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4339 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4342 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4343 const void *buffer, size_t size)
4345 const struct dp_sdp *sdp = buffer;
4347 if (size < sizeof(struct dp_sdp))
4350 memset(vsc, 0, sizeof(*vsc));
4352 if (sdp->sdp_header.HB0 != 0)
4355 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4358 vsc->sdp_type = sdp->sdp_header.HB1;
4359 vsc->revision = sdp->sdp_header.HB2;
4360 vsc->length = sdp->sdp_header.HB3;
4362 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4363 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4365 * - HB2 = 0x2, HB3 = 0x8
4366 * VSC SDP supporting 3D stereo + PSR
4367 * - HB2 = 0x4, HB3 = 0xe
4368 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4369 * first scan line of the SU region (applies to eDP v1.4b
4373 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4375 * - HB2 = 0x5, HB3 = 0x13
4376 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4379 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4380 vsc->colorimetry = sdp->db[16] & 0xf;
4381 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4383 switch (sdp->db[17] & 0x7) {
4400 MISSING_CASE(sdp->db[17] & 0x7);
4404 vsc->content_type = sdp->db[18] & 0x7;
4413 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4414 const void *buffer, size_t size)
4418 const struct dp_sdp *sdp = buffer;
4420 if (size < sizeof(struct dp_sdp))
4423 if (sdp->sdp_header.HB0 != 0)
4426 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4430 * Least Significant Eight Bits of (Data Byte Count – 1)
4431 * 1Dh (i.e., Data Byte Count = 30 bytes).
4433 if (sdp->sdp_header.HB2 != 0x1D)
4436 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4437 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4440 /* INFOFRAME SDP Version Number */
4441 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4444 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4445 if (sdp->db[0] != 1)
4448 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4449 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4452 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4453 HDMI_DRM_INFOFRAME_SIZE);
4458 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4459 struct intel_crtc_state *crtc_state,
4460 struct drm_dp_vsc_sdp *vsc)
4462 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4464 unsigned int type = DP_SDP_VSC;
4465 struct dp_sdp sdp = {};
4468 /* When PSR is enabled, VSC SDP is handled by PSR routine */
4469 if (crtc_state->has_psr)
4472 if ((crtc_state->infoframes.enable &
4473 intel_hdmi_infoframe_enable(type)) == 0)
4476 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4478 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4481 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4484 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4485 struct intel_crtc_state *crtc_state,
4486 struct hdmi_drm_infoframe *drm_infoframe)
4488 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4490 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4491 struct dp_sdp sdp = {};
4494 if ((crtc_state->infoframes.enable &
4495 intel_hdmi_infoframe_enable(type)) == 0)
4498 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4501 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4505 drm_dbg_kms(&dev_priv->drm,
4506 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4509 void intel_read_dp_sdp(struct intel_encoder *encoder,
4510 struct intel_crtc_state *crtc_state,
4515 intel_read_dp_vsc_sdp(encoder, crtc_state,
4516 &crtc_state->infoframes.vsc);
4518 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4519 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4520 &crtc_state->infoframes.drm.drm);
4528 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4530 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4533 u8 test_lane_count, test_link_bw;
4537 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4538 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4542 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4545 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4547 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4550 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4553 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4555 /* Validate the requested link rate and lane count */
4556 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4560 intel_dp->compliance.test_lane_count = test_lane_count;
4561 intel_dp->compliance.test_link_rate = test_link_rate;
4566 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4568 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4571 __be16 h_width, v_height;
4574 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4575 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4578 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4581 if (test_pattern != DP_COLOR_RAMP)
4584 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4587 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4591 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4594 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4598 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4601 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4604 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4606 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4608 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4609 case DP_TEST_BIT_DEPTH_6:
4610 intel_dp->compliance.test_data.bpc = 6;
4612 case DP_TEST_BIT_DEPTH_8:
4613 intel_dp->compliance.test_data.bpc = 8;
4619 intel_dp->compliance.test_data.video_pattern = test_pattern;
4620 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4621 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4622 /* Set test active flag here so userspace doesn't interrupt things */
4623 intel_dp->compliance.test_active = true;
4628 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4630 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4631 u8 test_result = DP_TEST_ACK;
4632 struct intel_connector *intel_connector = intel_dp->attached_connector;
4633 struct drm_connector *connector = &intel_connector->base;
4635 if (intel_connector->detect_edid == NULL ||
4636 connector->edid_corrupt ||
4637 intel_dp->aux.i2c_defer_count > 6) {
4638 /* Check EDID read for NACKs, DEFERs and corruption
4639 * (DP CTS 1.2 Core r1.1)
4640 * 4.2.2.4 : Failed EDID read, I2C_NAK
4641 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4642 * 4.2.2.6 : EDID corruption detected
4643 * Use failsafe mode for all cases
4645 if (intel_dp->aux.i2c_nack_count > 0 ||
4646 intel_dp->aux.i2c_defer_count > 0)
4647 drm_dbg_kms(&i915->drm,
4648 "EDID read had %d NACKs, %d DEFERs\n",
4649 intel_dp->aux.i2c_nack_count,
4650 intel_dp->aux.i2c_defer_count);
4651 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4653 /* FIXME: Get rid of drm_edid_raw() */
4654 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4656 /* We have to write the checksum of the last block read */
4657 block += block->extensions;
4659 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4660 block->checksum) <= 0)
4661 drm_dbg_kms(&i915->drm,
4662 "Failed to write EDID checksum\n");
4664 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4665 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4668 /* Set test active flag here so userspace doesn't interrupt things */
4669 intel_dp->compliance.test_active = true;
4674 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4675 const struct intel_crtc_state *crtc_state)
4677 struct drm_i915_private *dev_priv =
4678 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4679 struct drm_dp_phy_test_params *data =
4680 &intel_dp->compliance.test_data.phytest;
4681 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4682 enum pipe pipe = crtc->pipe;
4685 switch (data->phy_pattern) {
4686 case DP_PHY_TEST_PATTERN_NONE:
4687 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4688 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4690 case DP_PHY_TEST_PATTERN_D10_2:
4691 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4692 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4693 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4695 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
4696 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4697 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4698 DDI_DP_COMP_CTL_ENABLE |
4699 DDI_DP_COMP_CTL_SCRAMBLED_0);
4701 case DP_PHY_TEST_PATTERN_PRBS7:
4702 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4703 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4704 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4706 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
4708 * FIXME: Ideally pattern should come from DPCD 0x250. As
4709 * current firmware of DPR-100 could not set it, so hardcoding
4710 * now for complaince test.
4712 drm_dbg_kms(&dev_priv->drm,
4713 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4714 pattern_val = 0x3e0f83e0;
4715 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4716 pattern_val = 0x0f83e0f8;
4717 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4718 pattern_val = 0x0000f83e;
4719 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4720 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4721 DDI_DP_COMP_CTL_ENABLE |
4722 DDI_DP_COMP_CTL_CUSTOM80);
4724 case DP_PHY_TEST_PATTERN_CP2520:
4726 * FIXME: Ideally pattern should come from DPCD 0x24A. As
4727 * current firmware of DPR-100 could not set it, so hardcoding
4728 * now for complaince test.
4730 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4732 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4733 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4737 WARN(1, "Invalid Phy Test Pattern\n");
4741 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4742 const struct intel_crtc_state *crtc_state)
4744 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4745 struct drm_dp_phy_test_params *data =
4746 &intel_dp->compliance.test_data.phytest;
4747 u8 link_status[DP_LINK_STATUS_SIZE];
4749 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4751 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4755 /* retrieve vswing & pre-emphasis setting */
4756 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4759 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4761 intel_dp_phy_pattern_update(intel_dp, crtc_state);
4763 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4764 intel_dp->train_set, crtc_state->lane_count);
4766 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4767 link_status[DP_DPCD_REV]);
4770 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4772 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4773 struct drm_dp_phy_test_params *data =
4774 &intel_dp->compliance.test_data.phytest;
4776 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4777 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4781 /* Set test active flag here so userspace doesn't interrupt things */
4782 intel_dp->compliance.test_active = true;
4787 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4789 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4790 u8 response = DP_TEST_NAK;
4794 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4796 drm_dbg_kms(&i915->drm,
4797 "Could not read test request from sink\n");
4802 case DP_TEST_LINK_TRAINING:
4803 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4804 response = intel_dp_autotest_link_training(intel_dp);
4806 case DP_TEST_LINK_VIDEO_PATTERN:
4807 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4808 response = intel_dp_autotest_video_pattern(intel_dp);
4810 case DP_TEST_LINK_EDID_READ:
4811 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4812 response = intel_dp_autotest_edid(intel_dp);
4814 case DP_TEST_LINK_PHY_TEST_PATTERN:
4815 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4816 response = intel_dp_autotest_phy_pattern(intel_dp);
4819 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4824 if (response & DP_TEST_ACK)
4825 intel_dp->compliance.test_type = request;
4828 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4830 drm_dbg_kms(&i915->drm,
4831 "Could not write test response to sink\n");
4834 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4835 u8 link_status[DP_LINK_STATUS_SIZE])
4837 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4838 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4839 bool uhbr = intel_dp->link_rate >= 1000000;
4843 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4844 intel_dp->lane_count);
4846 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4851 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4852 drm_dbg_kms(&i915->drm,
4853 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4854 encoder->base.base.id, encoder->base.name,
4855 uhbr ? "128b/132b" : "8b/10b");
4861 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4863 bool handled = false;
4865 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4867 if (esi[1] & DP_CP_IRQ) {
4868 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4869 ack[1] |= DP_CP_IRQ;
4873 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4875 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4876 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4877 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4878 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4880 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4881 esi_link_status_size) != esi_link_status_size) {
4883 "[ENCODER:%d:%s] Failed to read link status\n",
4884 encoder->base.base.id, encoder->base.name);
4888 return intel_dp_link_ok(intel_dp, link_status);
4892 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4893 * @intel_dp: Intel DP struct
4895 * Read any pending MST interrupts, call MST core to handle these and ack the
4896 * interrupts. Check if the main and AUX link state is ok.
4899 * - %true if pending interrupts were serviced (or no interrupts were
4900 * pending) w/o detecting an error condition.
4901 * - %false if an error condition - like AUX failure or a loss of link - is
4902 * detected, which needs servicing from the hotplug work.
4905 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4907 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4908 bool link_ok = true;
4910 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4916 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4917 drm_dbg_kms(&i915->drm,
4918 "failed to get ESI - device may have failed\n");
4924 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4926 if (intel_dp->active_mst_links > 0 && link_ok &&
4927 esi[3] & LINK_STATUS_CHANGED) {
4928 if (!intel_dp_mst_link_status(intel_dp))
4930 ack[3] |= LINK_STATUS_CHANGED;
4933 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4935 if (!memchr_inv(ack, 0, sizeof(ack)))
4938 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4939 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4941 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4942 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4949 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4954 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4955 if (intel_dp->frl.is_trained && !is_active) {
4956 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4959 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
4960 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4963 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4965 intel_dp->frl.is_trained = false;
4967 /* Restart FRL training or fall back to TMDS mode */
4968 intel_dp_check_frl_training(intel_dp);
4973 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4975 u8 link_status[DP_LINK_STATUS_SIZE];
4977 if (!intel_dp->link_trained)
4981 * While PSR source HW is enabled, it will control main-link sending
4982 * frames, enabling and disabling it so trying to do a retrain will fail
4983 * as the link would or not be on or it could mix training patterns
4984 * and frame data at the same time causing retrain to fail.
4985 * Also when exiting PSR, HW will retrain the link anyways fixing
4986 * any link status error.
4988 if (intel_psr_enabled(intel_dp))
4991 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4996 * Validate the cached values of intel_dp->link_rate and
4997 * intel_dp->lane_count before attempting to retrain.
4999 * FIXME would be nice to user the crtc state here, but since
5000 * we need to call this from the short HPD handler that seems
5003 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5004 intel_dp->lane_count))
5007 /* Retrain if link not ok */
5008 return !intel_dp_link_ok(intel_dp, link_status);
5011 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5012 const struct drm_connector_state *conn_state)
5014 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5015 struct intel_encoder *encoder;
5018 if (!conn_state->best_encoder)
5022 encoder = &dp_to_dig_port(intel_dp)->base;
5023 if (conn_state->best_encoder == &encoder->base)
5027 for_each_pipe(i915, pipe) {
5028 encoder = &intel_dp->mst_encoders[pipe]->base;
5029 if (conn_state->best_encoder == &encoder->base)
5036 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5037 struct drm_modeset_acquire_ctx *ctx,
5040 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5041 struct drm_connector_list_iter conn_iter;
5042 struct intel_connector *connector;
5047 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5048 for_each_intel_connector_iter(connector, &conn_iter) {
5049 struct drm_connector_state *conn_state =
5050 connector->base.state;
5051 struct intel_crtc_state *crtc_state;
5052 struct intel_crtc *crtc;
5054 if (!intel_dp_has_connector(intel_dp, conn_state))
5057 crtc = to_intel_crtc(conn_state->crtc);
5061 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5065 crtc_state = to_intel_crtc_state(crtc->base.state);
5067 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5069 if (!crtc_state->hw.active)
5072 if (conn_state->commit &&
5073 !try_wait_for_completion(&conn_state->commit->hw_done))
5076 *pipe_mask |= BIT(crtc->pipe);
5078 drm_connector_list_iter_end(&conn_iter);
5083 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5085 struct intel_connector *connector = intel_dp->attached_connector;
5087 return connector->base.status == connector_status_connected ||
5091 int intel_dp_retrain_link(struct intel_encoder *encoder,
5092 struct drm_modeset_acquire_ctx *ctx)
5094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5095 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5096 struct intel_crtc *crtc;
5100 if (!intel_dp_is_connected(intel_dp))
5103 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5108 if (!intel_dp_needs_link_retrain(intel_dp))
5111 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5118 if (!intel_dp_needs_link_retrain(intel_dp))
5121 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5122 encoder->base.base.id, encoder->base.name);
5124 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5125 const struct intel_crtc_state *crtc_state =
5126 to_intel_crtc_state(crtc->base.state);
5128 /* Suppress underruns caused by re-training */
5129 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5130 if (crtc_state->has_pch_encoder)
5131 intel_set_pch_fifo_underrun_reporting(dev_priv,
5132 intel_crtc_pch_transcoder(crtc), false);
5135 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5136 const struct intel_crtc_state *crtc_state =
5137 to_intel_crtc_state(crtc->base.state);
5139 /* retrain on the MST master transcoder */
5140 if (DISPLAY_VER(dev_priv) >= 12 &&
5141 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5142 !intel_dp_mst_is_master_trans(crtc_state))
5145 intel_dp_check_frl_training(intel_dp);
5146 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5147 intel_dp_start_link_train(intel_dp, crtc_state);
5148 intel_dp_stop_link_train(intel_dp, crtc_state);
5152 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5153 const struct intel_crtc_state *crtc_state =
5154 to_intel_crtc_state(crtc->base.state);
5156 /* Keep underrun reporting disabled until things are stable */
5157 intel_crtc_wait_for_next_vblank(crtc);
5159 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5160 if (crtc_state->has_pch_encoder)
5161 intel_set_pch_fifo_underrun_reporting(dev_priv,
5162 intel_crtc_pch_transcoder(crtc), true);
5168 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5169 struct drm_modeset_acquire_ctx *ctx,
5172 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5173 struct drm_connector_list_iter conn_iter;
5174 struct intel_connector *connector;
5179 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5180 for_each_intel_connector_iter(connector, &conn_iter) {
5181 struct drm_connector_state *conn_state =
5182 connector->base.state;
5183 struct intel_crtc_state *crtc_state;
5184 struct intel_crtc *crtc;
5186 if (!intel_dp_has_connector(intel_dp, conn_state))
5189 crtc = to_intel_crtc(conn_state->crtc);
5193 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5197 crtc_state = to_intel_crtc_state(crtc->base.state);
5199 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5201 if (!crtc_state->hw.active)
5204 if (conn_state->commit &&
5205 !try_wait_for_completion(&conn_state->commit->hw_done))
5208 *pipe_mask |= BIT(crtc->pipe);
5210 drm_connector_list_iter_end(&conn_iter);
5215 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5216 struct drm_modeset_acquire_ctx *ctx)
5218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5220 struct intel_crtc *crtc;
5224 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5229 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5236 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5237 encoder->base.base.id, encoder->base.name);
5239 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5240 const struct intel_crtc_state *crtc_state =
5241 to_intel_crtc_state(crtc->base.state);
5243 /* test on the MST master transcoder */
5244 if (DISPLAY_VER(dev_priv) >= 12 &&
5245 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5246 !intel_dp_mst_is_master_trans(crtc_state))
5249 intel_dp_process_phy_request(intel_dp, crtc_state);
5256 void intel_dp_phy_test(struct intel_encoder *encoder)
5258 struct drm_modeset_acquire_ctx ctx;
5261 drm_modeset_acquire_init(&ctx, 0);
5264 ret = intel_dp_do_phy_test(encoder, &ctx);
5266 if (ret == -EDEADLK) {
5267 drm_modeset_backoff(&ctx);
5274 drm_modeset_drop_locks(&ctx);
5275 drm_modeset_acquire_fini(&ctx);
5276 drm_WARN(encoder->base.dev, ret,
5277 "Acquiring modeset locks failed with %i\n", ret);
5280 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5282 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5285 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5288 if (drm_dp_dpcd_readb(&intel_dp->aux,
5289 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5292 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5294 if (val & DP_AUTOMATED_TEST_REQUEST)
5295 intel_dp_handle_test_request(intel_dp);
5297 if (val & DP_CP_IRQ)
5298 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5300 if (val & DP_SINK_SPECIFIC_IRQ)
5301 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5304 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5308 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5311 if (drm_dp_dpcd_readb(&intel_dp->aux,
5312 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5315 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5316 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5319 if (val & HDMI_LINK_STATUS_CHANGED)
5320 intel_dp_handle_hdmi_link_status_change(intel_dp);
5324 * According to DP spec
5327 * 2. Configure link according to Receiver Capabilities
5328 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5329 * 4. Check link status on receipt of hot-plug interrupt
5331 * intel_dp_short_pulse - handles short pulse interrupts
5332 * when full detection is not required.
5333 * Returns %true if short pulse is handled and full detection
5334 * is NOT required and %false otherwise.
5337 intel_dp_short_pulse(struct intel_dp *intel_dp)
5339 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5340 u8 old_sink_count = intel_dp->sink_count;
5344 * Clearing compliance test variables to allow capturing
5345 * of values for next automated test request.
5347 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5350 * Now read the DPCD to see if it's actually running
5351 * If the current value of sink count doesn't match with
5352 * the value that was stored earlier or dpcd read failed
5353 * we need to do full detection
5355 ret = intel_dp_get_dpcd(intel_dp);
5357 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5358 /* No need to proceed if we are going to do full detect */
5362 intel_dp_check_device_service_irq(intel_dp);
5363 intel_dp_check_link_service_irq(intel_dp);
5365 /* Handle CEC interrupts, if any */
5366 drm_dp_cec_irq(&intel_dp->aux);
5368 /* defer to the hotplug work for link retraining if needed */
5369 if (intel_dp_needs_link_retrain(intel_dp))
5372 intel_psr_short_pulse(intel_dp);
5374 switch (intel_dp->compliance.test_type) {
5375 case DP_TEST_LINK_TRAINING:
5376 drm_dbg_kms(&dev_priv->drm,
5377 "Link Training Compliance Test requested\n");
5378 /* Send a Hotplug Uevent to userspace to start modeset */
5379 drm_kms_helper_hotplug_event(&dev_priv->drm);
5381 case DP_TEST_LINK_PHY_TEST_PATTERN:
5382 drm_dbg_kms(&dev_priv->drm,
5383 "PHY test pattern Compliance Test requested\n");
5385 * Schedule long hpd to do the test
5387 * FIXME get rid of the ad-hoc phy test modeset code
5388 * and properly incorporate it into the normal modeset.
5396 /* XXX this is probably wrong for multiple downstream ports */
5397 static enum drm_connector_status
5398 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5400 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5401 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5402 u8 *dpcd = intel_dp->dpcd;
5405 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5406 return connector_status_connected;
5408 lspcon_resume(dig_port);
5410 if (!intel_dp_get_dpcd(intel_dp))
5411 return connector_status_disconnected;
5413 /* if there's no downstream port, we're done */
5414 if (!drm_dp_is_branch(dpcd))
5415 return connector_status_connected;
5417 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5418 if (intel_dp_has_sink_count(intel_dp) &&
5419 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5420 return intel_dp->sink_count ?
5421 connector_status_connected : connector_status_disconnected;
5424 if (intel_dp_can_mst(intel_dp))
5425 return connector_status_connected;
5427 /* If no HPD, poke DDC gently */
5428 if (drm_probe_ddc(&intel_dp->aux.ddc))
5429 return connector_status_connected;
5431 /* Well we tried, say unknown for unreliable port types */
5432 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5433 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5434 if (type == DP_DS_PORT_TYPE_VGA ||
5435 type == DP_DS_PORT_TYPE_NON_EDID)
5436 return connector_status_unknown;
5438 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5439 DP_DWN_STRM_PORT_TYPE_MASK;
5440 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5441 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5442 return connector_status_unknown;
5445 /* Anything else is out of spec, warn and ignore */
5446 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5447 return connector_status_disconnected;
5450 static enum drm_connector_status
5451 edp_detect(struct intel_dp *intel_dp)
5453 return connector_status_connected;
5457 * intel_digital_port_connected - is the specified port connected?
5458 * @encoder: intel_encoder
5460 * In cases where there's a connector physically connected but it can't be used
5461 * by our hardware we also return false, since the rest of the driver should
5462 * pretty much treat the port as disconnected. This is relevant for type-C
5463 * (starting on ICL) where there's ownership involved.
5465 * Return %true if port is connected, %false otherwise.
5467 bool intel_digital_port_connected(struct intel_encoder *encoder)
5469 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5470 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5471 bool is_connected = false;
5472 intel_wakeref_t wakeref;
5474 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5475 is_connected = dig_port->connected(encoder);
5477 return is_connected;
5480 static const struct drm_edid *
5481 intel_dp_get_edid(struct intel_dp *intel_dp)
5483 struct intel_connector *connector = intel_dp->attached_connector;
5484 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5486 /* Use panel fixed edid if we have one */
5489 if (IS_ERR(fixed_edid))
5492 return drm_edid_dup(fixed_edid);
5495 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5499 intel_dp_update_dfp(struct intel_dp *intel_dp,
5500 const struct drm_edid *drm_edid)
5502 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5503 struct intel_connector *connector = intel_dp->attached_connector;
5505 intel_dp->dfp.max_bpc =
5506 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5507 intel_dp->downstream_ports, drm_edid);
5509 intel_dp->dfp.max_dotclock =
5510 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5511 intel_dp->downstream_ports);
5513 intel_dp->dfp.min_tmds_clock =
5514 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5515 intel_dp->downstream_ports,
5517 intel_dp->dfp.max_tmds_clock =
5518 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5519 intel_dp->downstream_ports,
5522 intel_dp->dfp.pcon_max_frl_bw =
5523 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5524 intel_dp->downstream_ports);
5526 drm_dbg_kms(&i915->drm,
5527 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5528 connector->base.base.id, connector->base.name,
5529 intel_dp->dfp.max_bpc,
5530 intel_dp->dfp.max_dotclock,
5531 intel_dp->dfp.min_tmds_clock,
5532 intel_dp->dfp.max_tmds_clock,
5533 intel_dp->dfp.pcon_max_frl_bw);
5535 intel_dp_get_pcon_dsc_cap(intel_dp);
5539 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5541 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5542 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5545 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5546 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5549 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5550 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5557 intel_dp_update_420(struct intel_dp *intel_dp)
5559 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5560 struct intel_connector *connector = intel_dp->attached_connector;
5562 intel_dp->dfp.ycbcr420_passthrough =
5563 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5564 intel_dp->downstream_ports);
5565 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5566 intel_dp->dfp.ycbcr_444_to_420 =
5567 dp_to_dig_port(intel_dp)->lspcon.active ||
5568 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5569 intel_dp->downstream_ports);
5570 intel_dp->dfp.rgb_to_ycbcr =
5571 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5572 intel_dp->downstream_ports,
5573 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5575 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5577 drm_dbg_kms(&i915->drm,
5578 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5579 connector->base.base.id, connector->base.name,
5580 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5581 str_yes_no(connector->base.ycbcr_420_allowed),
5582 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5586 intel_dp_set_edid(struct intel_dp *intel_dp)
5588 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5589 struct intel_connector *connector = intel_dp->attached_connector;
5590 const struct drm_edid *drm_edid;
5593 intel_dp_unset_edid(intel_dp);
5594 drm_edid = intel_dp_get_edid(intel_dp);
5595 connector->detect_edid = drm_edid;
5597 /* Below we depend on display info having been updated */
5598 drm_edid_connector_update(&connector->base, drm_edid);
5600 vrr_capable = intel_vrr_is_capable(connector);
5601 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5602 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5603 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5605 intel_dp_update_dfp(intel_dp, drm_edid);
5606 intel_dp_update_420(intel_dp);
5608 drm_dp_cec_attach(&intel_dp->aux,
5609 connector->base.display_info.source_physical_address);
5613 intel_dp_unset_edid(struct intel_dp *intel_dp)
5615 struct intel_connector *connector = intel_dp->attached_connector;
5617 drm_dp_cec_unset_edid(&intel_dp->aux);
5618 drm_edid_free(connector->detect_edid);
5619 connector->detect_edid = NULL;
5621 intel_dp->dfp.max_bpc = 0;
5622 intel_dp->dfp.max_dotclock = 0;
5623 intel_dp->dfp.min_tmds_clock = 0;
5624 intel_dp->dfp.max_tmds_clock = 0;
5626 intel_dp->dfp.pcon_max_frl_bw = 0;
5628 intel_dp->dfp.ycbcr_444_to_420 = false;
5629 connector->base.ycbcr_420_allowed = false;
5631 drm_connector_set_vrr_capable_property(&connector->base,
5636 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5638 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5640 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5644 if (intel_dp_is_edp(intel_dp))
5645 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5648 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5653 intel_dp_detect(struct drm_connector *connector,
5654 struct drm_modeset_acquire_ctx *ctx,
5657 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5658 struct intel_connector *intel_connector =
5659 to_intel_connector(connector);
5660 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5661 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5662 struct intel_encoder *encoder = &dig_port->base;
5663 enum drm_connector_status status;
5665 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5666 connector->base.id, connector->name);
5667 drm_WARN_ON(&dev_priv->drm,
5668 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5670 if (!intel_display_device_enabled(dev_priv))
5671 return connector_status_disconnected;
5673 /* Can't disconnect eDP */
5674 if (intel_dp_is_edp(intel_dp))
5675 status = edp_detect(intel_dp);
5676 else if (intel_digital_port_connected(encoder))
5677 status = intel_dp_detect_dpcd(intel_dp);
5679 status = connector_status_disconnected;
5681 if (status == connector_status_disconnected) {
5682 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5683 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5684 intel_dp->psr.sink_panel_replay_support = false;
5686 if (intel_dp->is_mst) {
5687 drm_dbg_kms(&dev_priv->drm,
5688 "MST device may have disappeared %d vs %d\n",
5690 intel_dp->mst_mgr.mst_state);
5691 intel_dp->is_mst = false;
5692 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5699 intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5701 intel_dp_configure_mst(intel_dp);
5704 * TODO: Reset link params when switching to MST mode, until MST
5705 * supports link training fallback params.
5707 if (intel_dp->reset_link_params || intel_dp->is_mst) {
5708 intel_dp_reset_max_link_params(intel_dp);
5709 intel_dp->reset_link_params = false;
5712 intel_dp_print_rates(intel_dp);
5714 if (intel_dp->is_mst) {
5716 * If we are in MST mode then this connector
5717 * won't appear connected or have anything
5720 status = connector_status_disconnected;
5725 * Some external monitors do not signal loss of link synchronization
5726 * with an IRQ_HPD, so force a link status check.
5728 if (!intel_dp_is_edp(intel_dp)) {
5731 ret = intel_dp_retrain_link(encoder, ctx);
5737 * Clearing NACK and defer counts to get their exact values
5738 * while reading EDID which are required by Compliance tests
5739 * 4.2.2.4 and 4.2.2.5
5741 intel_dp->aux.i2c_nack_count = 0;
5742 intel_dp->aux.i2c_defer_count = 0;
5744 intel_dp_set_edid(intel_dp);
5745 if (intel_dp_is_edp(intel_dp) ||
5746 to_intel_connector(connector)->detect_edid)
5747 status = connector_status_connected;
5749 intel_dp_check_device_service_irq(intel_dp);
5752 if (status != connector_status_connected && !intel_dp->is_mst)
5753 intel_dp_unset_edid(intel_dp);
5755 if (!intel_dp_is_edp(intel_dp))
5756 drm_dp_set_subconnector_property(connector,
5759 intel_dp->downstream_ports);
5764 intel_dp_force(struct drm_connector *connector)
5766 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5767 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5768 struct intel_encoder *intel_encoder = &dig_port->base;
5769 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5771 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5772 connector->base.id, connector->name);
5773 intel_dp_unset_edid(intel_dp);
5775 if (connector->status != connector_status_connected)
5778 intel_dp_set_edid(intel_dp);
5781 static int intel_dp_get_modes(struct drm_connector *connector)
5783 struct intel_connector *intel_connector = to_intel_connector(connector);
5786 /* drm_edid_connector_update() done in ->detect() or ->force() */
5787 num_modes = drm_edid_connector_add_modes(connector);
5789 /* Also add fixed mode, which may or may not be present in EDID */
5790 if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5791 num_modes += intel_panel_get_modes(intel_connector);
5796 if (!intel_connector->detect_edid) {
5797 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5798 struct drm_display_mode *mode;
5800 mode = drm_dp_downstream_mode(connector->dev,
5802 intel_dp->downstream_ports);
5804 drm_mode_probed_add(connector, mode);
5813 intel_dp_connector_register(struct drm_connector *connector)
5815 struct drm_i915_private *i915 = to_i915(connector->dev);
5816 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5817 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5818 struct intel_lspcon *lspcon = &dig_port->lspcon;
5821 ret = intel_connector_register(connector);
5825 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5826 intel_dp->aux.name, connector->kdev->kobj.name);
5828 intel_dp->aux.dev = connector->kdev;
5829 ret = drm_dp_aux_register(&intel_dp->aux);
5831 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5833 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5837 * ToDo: Clean this up to handle lspcon init and resume more
5838 * efficiently and streamlined.
5840 if (lspcon_init(dig_port)) {
5841 lspcon_detect_hdr_capability(lspcon);
5842 if (lspcon->hdr_supported)
5843 drm_connector_attach_hdr_output_metadata_property(connector);
5850 intel_dp_connector_unregister(struct drm_connector *connector)
5852 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5854 drm_dp_cec_unregister_connector(&intel_dp->aux);
5855 drm_dp_aux_unregister(&intel_dp->aux);
5856 intel_connector_unregister(connector);
5859 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5861 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5862 struct intel_dp *intel_dp = &dig_port->dp;
5864 intel_dp_mst_encoder_cleanup(dig_port);
5866 intel_pps_vdd_off_sync(intel_dp);
5869 * Ensure power off delay is respected on module remove, so that we can
5870 * reduce delays at driver probe. See pps_init_timestamps().
5872 intel_pps_wait_power_cycle(intel_dp);
5874 intel_dp_aux_fini(intel_dp);
5877 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5879 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5881 intel_pps_vdd_off_sync(intel_dp);
5884 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5886 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5888 intel_pps_wait_power_cycle(intel_dp);
5891 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5894 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5895 struct drm_connector_list_iter conn_iter;
5896 struct drm_connector *connector;
5899 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5900 drm_for_each_connector_iter(connector, &conn_iter) {
5901 struct drm_connector_state *conn_state;
5902 struct intel_crtc_state *crtc_state;
5903 struct intel_crtc *crtc;
5905 if (!connector->has_tile ||
5906 connector->tile_group->id != tile_group_id)
5909 conn_state = drm_atomic_get_connector_state(&state->base,
5911 if (IS_ERR(conn_state)) {
5912 ret = PTR_ERR(conn_state);
5916 crtc = to_intel_crtc(conn_state->crtc);
5921 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5922 crtc_state->uapi.mode_changed = true;
5924 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5928 drm_connector_list_iter_end(&conn_iter);
5933 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5935 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5936 struct intel_crtc *crtc;
5938 if (transcoders == 0)
5941 for_each_intel_crtc(&dev_priv->drm, crtc) {
5942 struct intel_crtc_state *crtc_state;
5945 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5946 if (IS_ERR(crtc_state))
5947 return PTR_ERR(crtc_state);
5949 if (!crtc_state->hw.enable)
5952 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5955 crtc_state->uapi.mode_changed = true;
5957 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5961 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5965 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5968 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5973 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5974 struct drm_connector *connector)
5976 const struct drm_connector_state *old_conn_state =
5977 drm_atomic_get_old_connector_state(&state->base, connector);
5978 const struct intel_crtc_state *old_crtc_state;
5979 struct intel_crtc *crtc;
5982 crtc = to_intel_crtc(old_conn_state->crtc);
5986 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5988 if (!old_crtc_state->hw.active)
5991 transcoders = old_crtc_state->sync_mode_slaves_mask;
5992 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5993 transcoders |= BIT(old_crtc_state->master_transcoder);
5995 return intel_modeset_affected_transcoders(state,
5999 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6000 struct drm_atomic_state *_state)
6002 struct drm_i915_private *dev_priv = to_i915(conn->dev);
6003 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6004 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6005 struct intel_connector *intel_conn = to_intel_connector(conn);
6006 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6009 ret = intel_digital_connector_atomic_check(conn, &state->base);
6013 if (intel_dp_mst_source_support(intel_dp)) {
6014 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6020 * We don't enable port sync on BDW due to missing w/as and
6021 * due to not having adjusted the modeset sequence appropriately.
6023 if (DISPLAY_VER(dev_priv) < 9)
6026 if (!intel_connector_needs_modeset(state, conn))
6029 if (conn->has_tile) {
6030 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6035 return intel_modeset_synced_crtcs(state, conn);
6038 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6039 enum drm_connector_status hpd_state)
6041 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6042 struct drm_i915_private *i915 = to_i915(connector->dev);
6043 bool hpd_high = hpd_state == connector_status_connected;
6044 unsigned int hpd_pin = encoder->hpd_pin;
6045 bool need_work = false;
6047 spin_lock_irq(&i915->irq_lock);
6048 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6049 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6051 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6054 spin_unlock_irq(&i915->irq_lock);
6057 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
6060 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6061 .force = intel_dp_force,
6062 .fill_modes = drm_helper_probe_single_connector_modes,
6063 .atomic_get_property = intel_digital_connector_atomic_get_property,
6064 .atomic_set_property = intel_digital_connector_atomic_set_property,
6065 .late_register = intel_dp_connector_register,
6066 .early_unregister = intel_dp_connector_unregister,
6067 .destroy = intel_connector_destroy,
6068 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6069 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6070 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6073 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6074 .detect_ctx = intel_dp_detect,
6075 .get_modes = intel_dp_get_modes,
6076 .mode_valid = intel_dp_mode_valid,
6077 .atomic_check = intel_dp_connector_atomic_check,
6081 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6083 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6084 struct intel_dp *intel_dp = &dig_port->dp;
6086 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6087 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6089 * vdd off can generate a long/short pulse on eDP which
6090 * would require vdd on to handle it, and thus we
6091 * would end up in an endless cycle of
6092 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6094 drm_dbg_kms(&i915->drm,
6095 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6096 long_hpd ? "long" : "short",
6097 dig_port->base.base.base.id,
6098 dig_port->base.base.name);
6102 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6103 dig_port->base.base.base.id,
6104 dig_port->base.base.name,
6105 long_hpd ? "long" : "short");
6108 intel_dp->reset_link_params = true;
6112 if (intel_dp->is_mst) {
6113 if (!intel_dp_check_mst_status(intel_dp))
6115 } else if (!intel_dp_short_pulse(intel_dp)) {
6122 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6123 const struct intel_bios_encoder_data *devdata,
6127 * eDP not supported on g4x. so bail out early just
6128 * for a bit extra safety in case the VBT is bonkers.
6130 if (DISPLAY_VER(dev_priv) < 5)
6133 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6136 return devdata && intel_bios_encoder_supports_edp(devdata);
6139 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6141 const struct intel_bios_encoder_data *devdata =
6142 intel_bios_encoder_data_lookup(i915, port);
6144 return _intel_dp_is_port_edp(i915, devdata, port);
6148 has_gamut_metadata_dip(struct intel_encoder *encoder)
6150 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6151 enum port port = encoder->port;
6153 if (intel_bios_encoder_is_lspcon(encoder->devdata))
6156 if (DISPLAY_VER(i915) >= 11)
6162 if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6163 DISPLAY_VER(i915) >= 9)
6170 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6172 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6173 enum port port = dp_to_dig_port(intel_dp)->base.port;
6175 if (!intel_dp_is_edp(intel_dp))
6176 drm_connector_attach_dp_subconnector_property(connector);
6178 if (!IS_G4X(dev_priv) && port != PORT_A)
6179 intel_attach_force_audio_property(connector);
6181 intel_attach_broadcast_rgb_property(connector);
6182 if (HAS_GMCH(dev_priv))
6183 drm_connector_attach_max_bpc_property(connector, 6, 10);
6184 else if (DISPLAY_VER(dev_priv) >= 5)
6185 drm_connector_attach_max_bpc_property(connector, 6, 12);
6187 /* Register HDMI colorspace for case of lspcon */
6188 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6189 drm_connector_attach_content_type_property(connector);
6190 intel_attach_hdmi_colorspace_property(connector);
6192 intel_attach_dp_colorspace_property(connector);
6195 if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6196 drm_connector_attach_hdr_output_metadata_property(connector);
6198 if (HAS_VRR(dev_priv))
6199 drm_connector_attach_vrr_capable_property(connector);
6203 intel_edp_add_properties(struct intel_dp *intel_dp)
6205 struct intel_connector *connector = intel_dp->attached_connector;
6206 struct drm_i915_private *i915 = to_i915(connector->base.dev);
6207 const struct drm_display_mode *fixed_mode =
6208 intel_panel_preferred_fixed_mode(connector);
6210 intel_attach_scaling_mode_property(&connector->base);
6212 drm_connector_set_panel_orientation_with_quirk(&connector->base,
6213 i915->display.vbt.orientation,
6214 fixed_mode->hdisplay,
6215 fixed_mode->vdisplay);
6218 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6219 struct intel_connector *connector)
6221 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6222 enum pipe pipe = INVALID_PIPE;
6224 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6226 * Figure out the current pipe for the initial backlight setup.
6227 * If the current pipe isn't valid, try the PPS pipe, and if that
6228 * fails just assume pipe A.
6230 pipe = vlv_active_pipe(intel_dp);
6232 if (pipe != PIPE_A && pipe != PIPE_B)
6233 pipe = intel_dp->pps.pps_pipe;
6235 if (pipe != PIPE_A && pipe != PIPE_B)
6239 intel_backlight_setup(connector, pipe);
6242 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6243 struct intel_connector *intel_connector)
6245 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6246 struct drm_connector *connector = &intel_connector->base;
6247 struct drm_display_mode *fixed_mode;
6248 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6250 const struct drm_edid *drm_edid;
6252 if (!intel_dp_is_edp(intel_dp))
6256 * On IBX/CPT we may get here with LVDS already registered. Since the
6257 * driver uses the only internal power sequencer available for both
6258 * eDP and LVDS bail out early in this case to prevent interfering
6259 * with an already powered-on LVDS power sequencer.
6261 if (intel_get_lvds_encoder(dev_priv)) {
6262 drm_WARN_ON(&dev_priv->drm,
6263 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6264 drm_info(&dev_priv->drm,
6265 "LVDS was detected, not registering eDP\n");
6270 intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6273 if (!intel_pps_init(intel_dp)) {
6274 drm_info(&dev_priv->drm,
6275 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6276 encoder->base.base.id, encoder->base.name);
6278 * The BIOS may have still enabled VDD on the PPS even
6279 * though it's unusable. Make sure we turn it back off
6280 * and to release the power domain references/etc.
6286 * Enable HPD sense for live status check.
6287 * intel_hpd_irq_setup() will turn it off again
6288 * if it's no longer needed later.
6290 * The DPCD probe below will make sure VDD is on.
6292 intel_hpd_enable_detection(encoder);
6294 /* Cache DPCD and EDID for edp. */
6295 has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6298 /* if this fails, presume the device is a ghost */
6299 drm_info(&dev_priv->drm,
6300 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6301 encoder->base.base.id, encoder->base.name);
6306 * VBT and straps are liars. Also check HPD as that seems
6307 * to be the most reliable piece of information available.
6309 * ... expect on devices that forgot to hook HPD up for eDP
6310 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6311 * ports are attempting to use the same AUX CH, according to VBT.
6313 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6315 * If this fails, presume the DPCD answer came
6316 * from some other port using the same AUX CH.
6318 * FIXME maybe cleaner to check this before the
6319 * DPCD read? Would need sort out the VDD handling...
6321 if (!intel_digital_port_connected(encoder)) {
6322 drm_info(&dev_priv->drm,
6323 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6324 encoder->base.base.id, encoder->base.name);
6329 * Unfortunately even the HPD based detection fails on
6330 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6331 * back to checking for a VGA branch device. Only do this
6332 * on known affected platforms to minimize false positives.
6334 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6335 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6336 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6337 drm_info(&dev_priv->drm,
6338 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6339 encoder->base.base.id, encoder->base.name);
6344 mutex_lock(&dev_priv->drm.mode_config.mutex);
6345 drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6347 /* Fallback to EDID from ACPI OpRegion, if any */
6348 drm_edid = intel_opregion_get_edid(intel_connector);
6350 drm_dbg_kms(&dev_priv->drm,
6351 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6352 connector->base.id, connector->name);
6355 if (drm_edid_connector_update(connector, drm_edid) ||
6356 !drm_edid_connector_add_modes(connector)) {
6357 drm_edid_connector_update(connector, NULL);
6358 drm_edid_free(drm_edid);
6359 drm_edid = ERR_PTR(-EINVAL);
6362 drm_edid = ERR_PTR(-ENOENT);
6365 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6366 IS_ERR(drm_edid) ? NULL : drm_edid);
6368 intel_panel_add_edid_fixed_modes(intel_connector, true);
6370 /* MSO requires information from the EDID */
6371 intel_edp_mso_init(intel_dp);
6373 /* multiply the mode clock and horizontal timings for MSO */
6374 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6375 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6377 /* fallback to VBT if available for eDP */
6378 if (!intel_panel_preferred_fixed_mode(intel_connector))
6379 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6381 mutex_unlock(&dev_priv->drm.mode_config.mutex);
6383 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6384 drm_info(&dev_priv->drm,
6385 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6386 encoder->base.base.id, encoder->base.name);
6390 intel_panel_init(intel_connector, drm_edid);
6392 intel_edp_backlight_setup(intel_dp, intel_connector);
6394 intel_edp_add_properties(intel_dp);
6396 intel_pps_init_late(intel_dp);
6401 intel_pps_vdd_off_sync(intel_dp);
6406 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6408 struct intel_connector *intel_connector;
6409 struct drm_connector *connector;
6411 intel_connector = container_of(work, typeof(*intel_connector),
6412 modeset_retry_work);
6413 connector = &intel_connector->base;
6414 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6417 /* Grab the locks before changing connector property*/
6418 mutex_lock(&connector->dev->mode_config.mutex);
6419 /* Set connector link status to BAD and send a Uevent to notify
6420 * userspace to do a modeset.
6422 drm_connector_set_link_status_property(connector,
6423 DRM_MODE_LINK_STATUS_BAD);
6424 mutex_unlock(&connector->dev->mode_config.mutex);
6425 /* Send Hotplug uevent so userspace can reprobe */
6426 drm_kms_helper_connector_hotplug_event(connector);
6430 intel_dp_init_connector(struct intel_digital_port *dig_port,
6431 struct intel_connector *intel_connector)
6433 struct drm_connector *connector = &intel_connector->base;
6434 struct intel_dp *intel_dp = &dig_port->dp;
6435 struct intel_encoder *intel_encoder = &dig_port->base;
6436 struct drm_device *dev = intel_encoder->base.dev;
6437 struct drm_i915_private *dev_priv = to_i915(dev);
6438 enum port port = intel_encoder->port;
6439 enum phy phy = intel_port_to_phy(dev_priv, port);
6442 /* Initialize the work for modeset in case of link train failure */
6443 INIT_WORK(&intel_connector->modeset_retry_work,
6444 intel_dp_modeset_retry_work_fn);
6446 if (drm_WARN(dev, dig_port->max_lanes < 1,
6447 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6448 dig_port->max_lanes, intel_encoder->base.base.id,
6449 intel_encoder->base.name))
6452 intel_dp->reset_link_params = true;
6453 intel_dp->pps.pps_pipe = INVALID_PIPE;
6454 intel_dp->pps.active_pipe = INVALID_PIPE;
6456 /* Preserve the current hw state. */
6457 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6458 intel_dp->attached_connector = intel_connector;
6460 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6462 * Currently we don't support eDP on TypeC ports, although in
6463 * theory it could work on TypeC legacy ports.
6465 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6466 type = DRM_MODE_CONNECTOR_eDP;
6467 intel_encoder->type = INTEL_OUTPUT_EDP;
6469 /* eDP only on port B and/or C on vlv/chv */
6470 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6471 IS_CHERRYVIEW(dev_priv)) &&
6472 port != PORT_B && port != PORT_C))
6475 type = DRM_MODE_CONNECTOR_DisplayPort;
6478 intel_dp_set_default_sink_rates(intel_dp);
6479 intel_dp_set_default_max_sink_lane_count(intel_dp);
6481 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6482 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6484 intel_dp_aux_init(intel_dp);
6485 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6487 drm_dbg_kms(&dev_priv->drm,
6488 "Adding %s connector on [ENCODER:%d:%s]\n",
6489 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6490 intel_encoder->base.base.id, intel_encoder->base.name);
6492 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6493 type, &intel_dp->aux.ddc);
6494 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6496 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6497 connector->interlace_allowed = true;
6499 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6501 intel_connector_attach_encoder(intel_connector, intel_encoder);
6503 if (HAS_DDI(dev_priv))
6504 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6506 intel_connector->get_hw_state = intel_connector_get_hw_state;
6508 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6509 intel_dp_aux_fini(intel_dp);
6513 intel_dp_set_source_rates(intel_dp);
6514 intel_dp_set_common_rates(intel_dp);
6515 intel_dp_reset_max_link_params(intel_dp);
6517 /* init MST on ports that can support it */
6518 intel_dp_mst_encoder_init(dig_port,
6519 intel_connector->base.base.id);
6521 intel_dp_add_properties(intel_dp, connector);
6523 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6524 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6526 drm_dbg_kms(&dev_priv->drm,
6527 "HDCP init failed, skipping.\n");
6530 intel_dp->frl.is_trained = false;
6531 intel_dp->frl.trained_rate_gbps = 0;
6533 intel_psr_init(intel_dp);
6538 intel_display_power_flush_work(dev_priv);
6539 drm_connector_cleanup(connector);
6544 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6546 struct intel_encoder *encoder;
6548 if (!HAS_DISPLAY(dev_priv))
6551 for_each_intel_encoder(&dev_priv->drm, encoder) {
6552 struct intel_dp *intel_dp;
6554 if (encoder->type != INTEL_OUTPUT_DDI)
6557 intel_dp = enc_to_intel_dp(encoder);
6559 if (!intel_dp_mst_source_support(intel_dp))
6562 if (intel_dp->is_mst)
6563 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6567 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6569 struct intel_encoder *encoder;
6571 if (!HAS_DISPLAY(dev_priv))
6574 for_each_intel_encoder(&dev_priv->drm, encoder) {
6575 struct intel_dp *intel_dp;
6578 if (encoder->type != INTEL_OUTPUT_DDI)
6581 intel_dp = enc_to_intel_dp(encoder);
6583 if (!intel_dp_mst_source_support(intel_dp))
6586 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6589 intel_dp->is_mst = false;
6590 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,