2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/i915_drm.h>
45 #include "i915_debugfs.h"
47 #include "i915_trace.h"
48 #include "intel_atomic.h"
49 #include "intel_audio.h"
50 #include "intel_connector.h"
51 #include "intel_ddi.h"
52 #include "intel_display_types.h"
54 #include "intel_dp_link_training.h"
55 #include "intel_dp_mst.h"
56 #include "intel_dpio_phy.h"
57 #include "intel_fifo_underrun.h"
58 #include "intel_hdcp.h"
59 #include "intel_hdmi.h"
60 #include "intel_hotplug.h"
61 #include "intel_lspcon.h"
62 #include "intel_lvds.h"
63 #include "intel_panel.h"
64 #include "intel_psr.h"
65 #include "intel_sideband.h"
67 #include "intel_vdsc.h"
69 #define DP_DPRX_ESI_LEN 14
71 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
72 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
74 /* DP DSC throughput values used for slice count calculations KPixels/s */
75 #define DP_DSC_PEAK_PIXEL_RATE 2720000
76 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
77 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
79 /* DP DSC FEC Overhead factor = 1/(0.972261) */
80 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
82 /* Compliance test status bits */
83 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
84 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
85 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
86 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
93 static const struct dp_link_dpll g4x_dpll[] = {
95 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
97 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
100 static const struct dp_link_dpll pch_dpll[] = {
102 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
104 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
107 static const struct dp_link_dpll vlv_dpll[] = {
109 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
111 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
115 * CHV supports eDP 1.4 that have more link rates.
116 * Below only provides the fixed rate but exclude variable rate.
118 static const struct dp_link_dpll chv_dpll[] = {
120 * CHV requires to program fractional division for m2.
121 * m2 is stored in fixed point format using formula below
122 * (m2_int << 22) | m2_fraction
124 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
125 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
126 { 270000, /* m2_int = 27, m2_fraction = 0 */
127 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
130 /* Constants for DP DSC configurations */
131 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
133 /* With Single pipe configuration, HW is capable of supporting maximum
134 * of 4 slices per line.
136 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
139 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
140 * @intel_dp: DP struct
142 * If a CPU or PCH DP output is attached to an eDP panel, this function
143 * will return true, and false otherwise.
145 bool intel_dp_is_edp(struct intel_dp *intel_dp)
147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
149 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
152 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
154 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
157 static void intel_dp_link_down(struct intel_encoder *encoder,
158 const struct intel_crtc_state *old_crtc_state);
159 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
160 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
161 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
162 const struct intel_crtc_state *crtc_state);
163 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
165 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
167 /* update sink rates from dpcd */
168 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
170 static const int dp_rates[] = {
171 162000, 270000, 540000, 810000
175 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
177 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
178 if (dp_rates[i] > max_rate)
180 intel_dp->sink_rates[i] = dp_rates[i];
183 intel_dp->num_sink_rates = i;
186 /* Get length of rates array potentially limited by max_rate. */
187 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
191 /* Limit results by potentially reduced max rate */
192 for (i = 0; i < len; i++) {
193 if (rates[len - i - 1] <= max_rate)
200 /* Get length of common rates array potentially limited by max_rate. */
201 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
204 return intel_dp_rate_limit_len(intel_dp->common_rates,
205 intel_dp->num_common_rates, max_rate);
208 /* Theoretical max between source and sink */
209 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
211 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
214 /* Theoretical max between source and sink */
215 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
217 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
218 int source_max = intel_dig_port->max_lanes;
219 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
220 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
222 return min3(source_max, sink_max, fia_max);
225 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
227 return intel_dp->max_link_lane_count;
231 intel_dp_link_required(int pixel_clock, int bpp)
233 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
234 return DIV_ROUND_UP(pixel_clock * bpp, 8);
238 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
240 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
241 * link rate that is generally expressed in Gbps. Since, 8 bits of data
242 * is transmitted every LS_Clk per lane, there is no need to account for
243 * the channel encoding that is done in the PHY layer here.
246 return max_link_clock * max_lanes;
250 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct intel_encoder *encoder = &intel_dig_port->base;
254 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
255 int max_dotclk = dev_priv->max_dotclk_freq;
258 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
260 if (type != DP_DS_PORT_TYPE_VGA)
263 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
264 intel_dp->downstream_ports);
266 if (ds_max_dotclk != 0)
267 max_dotclk = min(max_dotclk, ds_max_dotclk);
272 static int cnl_max_source_rate(struct intel_dp *intel_dp)
274 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
275 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
276 enum port port = dig_port->base.port;
278 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
280 /* Low voltage SKUs are limited to max of 5.4G */
281 if (voltage == VOLTAGE_INFO_0_85V)
284 /* For this SKU 8.1G is supported in all ports */
285 if (IS_CNL_WITH_PORT_F(dev_priv))
288 /* For other SKUs, max rate on ports A and D is 5.4G */
289 if (port == PORT_A || port == PORT_D)
295 static int icl_max_source_rate(struct intel_dp *intel_dp)
297 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
298 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
299 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
301 if (intel_phy_is_combo(dev_priv, phy) &&
302 !IS_ELKHARTLAKE(dev_priv) &&
303 !intel_dp_is_edp(intel_dp))
310 intel_dp_set_source_rates(struct intel_dp *intel_dp)
312 /* The values must be in increasing order */
313 static const int cnl_rates[] = {
314 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
316 static const int bxt_rates[] = {
317 162000, 216000, 243000, 270000, 324000, 432000, 540000
319 static const int skl_rates[] = {
320 162000, 216000, 270000, 324000, 432000, 540000
322 static const int hsw_rates[] = {
323 162000, 270000, 540000
325 static const int g4x_rates[] = {
328 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
329 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
330 const struct ddi_vbt_port_info *info =
331 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
332 const int *source_rates;
333 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
335 /* This should only be done once */
336 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
338 if (INTEL_GEN(dev_priv) >= 10) {
339 source_rates = cnl_rates;
340 size = ARRAY_SIZE(cnl_rates);
341 if (IS_GEN(dev_priv, 10))
342 max_rate = cnl_max_source_rate(intel_dp);
344 max_rate = icl_max_source_rate(intel_dp);
345 } else if (IS_GEN9_LP(dev_priv)) {
346 source_rates = bxt_rates;
347 size = ARRAY_SIZE(bxt_rates);
348 } else if (IS_GEN9_BC(dev_priv)) {
349 source_rates = skl_rates;
350 size = ARRAY_SIZE(skl_rates);
351 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
352 IS_BROADWELL(dev_priv)) {
353 source_rates = hsw_rates;
354 size = ARRAY_SIZE(hsw_rates);
356 source_rates = g4x_rates;
357 size = ARRAY_SIZE(g4x_rates);
360 if (max_rate && vbt_max_rate)
361 max_rate = min(max_rate, vbt_max_rate);
362 else if (vbt_max_rate)
363 max_rate = vbt_max_rate;
366 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
368 intel_dp->source_rates = source_rates;
369 intel_dp->num_source_rates = size;
372 static int intersect_rates(const int *source_rates, int source_len,
373 const int *sink_rates, int sink_len,
376 int i = 0, j = 0, k = 0;
378 while (i < source_len && j < sink_len) {
379 if (source_rates[i] == sink_rates[j]) {
380 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
382 common_rates[k] = source_rates[i];
386 } else if (source_rates[i] < sink_rates[j]) {
395 /* return index of rate in rates array, or -1 if not found */
396 static int intel_dp_rate_index(const int *rates, int len, int rate)
400 for (i = 0; i < len; i++)
401 if (rate == rates[i])
407 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
409 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
411 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
412 intel_dp->num_source_rates,
413 intel_dp->sink_rates,
414 intel_dp->num_sink_rates,
415 intel_dp->common_rates);
417 /* Paranoia, there should always be something in common. */
418 if (WARN_ON(intel_dp->num_common_rates == 0)) {
419 intel_dp->common_rates[0] = 162000;
420 intel_dp->num_common_rates = 1;
424 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
428 * FIXME: we need to synchronize the current link parameters with
429 * hardware readout. Currently fast link training doesn't work on
432 if (link_rate == 0 ||
433 link_rate > intel_dp->max_link_rate)
436 if (lane_count == 0 ||
437 lane_count > intel_dp_max_lane_count(intel_dp))
443 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
447 const struct drm_display_mode *fixed_mode =
448 intel_dp->attached_connector->panel.fixed_mode;
449 int mode_rate, max_rate;
451 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
452 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
453 if (mode_rate > max_rate)
459 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
460 int link_rate, u8 lane_count)
464 index = intel_dp_rate_index(intel_dp->common_rates,
465 intel_dp->num_common_rates,
468 if (intel_dp_is_edp(intel_dp) &&
469 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
470 intel_dp->common_rates[index - 1],
472 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
475 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
476 intel_dp->max_link_lane_count = lane_count;
477 } else if (lane_count > 1) {
478 if (intel_dp_is_edp(intel_dp) &&
479 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
480 intel_dp_max_common_rate(intel_dp),
482 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
485 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
486 intel_dp->max_link_lane_count = lane_count >> 1;
488 DRM_ERROR("Link Training Unsuccessful\n");
495 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
497 return div_u64(mul_u32_u32(mode_clock, 1000000U),
498 DP_DSC_FEC_OVERHEAD_FACTOR);
501 static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
502 u32 mode_clock, u32 mode_hdisplay)
504 u32 bits_per_pixel, max_bpp_small_joiner_ram;
508 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
509 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
510 * for SST -> TimeSlotsPerMTP is 1,
511 * for MST -> TimeSlotsPerMTP has to be calculated
513 bits_per_pixel = (link_clock * lane_count * 8) /
514 intel_dp_mode_to_fec_clock(mode_clock);
515 DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
517 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
518 max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
519 DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
522 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
523 * check, output bpp from small joiner RAM check)
525 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
527 /* Error out if the max bpp is less than smallest allowed valid bpp */
528 if (bits_per_pixel < valid_dsc_bpp[0]) {
529 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
530 bits_per_pixel, valid_dsc_bpp[0]);
534 /* Find the nearest match in the array of known BPPs from VESA */
535 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
536 if (bits_per_pixel < valid_dsc_bpp[i + 1])
539 bits_per_pixel = valid_dsc_bpp[i];
542 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
543 * fractional part is 0
545 return bits_per_pixel << 4;
548 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
549 int mode_clock, int mode_hdisplay)
551 u8 min_slice_count, i;
554 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
555 min_slice_count = DIV_ROUND_UP(mode_clock,
556 DP_DSC_MAX_ENC_THROUGHPUT_0);
558 min_slice_count = DIV_ROUND_UP(mode_clock,
559 DP_DSC_MAX_ENC_THROUGHPUT_1);
561 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
562 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
563 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
567 /* Also take into account max slice width */
568 min_slice_count = min_t(u8, min_slice_count,
569 DIV_ROUND_UP(mode_hdisplay,
572 /* Find the closest match to the valid slice count values */
573 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
574 if (valid_dsc_slicecount[i] >
575 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
578 if (min_slice_count <= valid_dsc_slicecount[i])
579 return valid_dsc_slicecount[i];
582 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
586 static enum drm_mode_status
587 intel_dp_mode_valid(struct drm_connector *connector,
588 struct drm_display_mode *mode)
590 struct intel_dp *intel_dp = intel_attached_dp(connector);
591 struct intel_connector *intel_connector = to_intel_connector(connector);
592 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
593 struct drm_i915_private *dev_priv = to_i915(connector->dev);
594 int target_clock = mode->clock;
595 int max_rate, mode_rate, max_lanes, max_link_clock;
597 u16 dsc_max_output_bpp = 0;
598 u8 dsc_slice_count = 0;
600 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
601 return MODE_NO_DBLESCAN;
603 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
605 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
606 if (mode->hdisplay > fixed_mode->hdisplay)
609 if (mode->vdisplay > fixed_mode->vdisplay)
612 target_clock = fixed_mode->clock;
615 max_link_clock = intel_dp_max_link_rate(intel_dp);
616 max_lanes = intel_dp_max_lane_count(intel_dp);
618 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
619 mode_rate = intel_dp_link_required(target_clock, 18);
622 * Output bpp is stored in 6.4 format so right shift by 4 to get the
623 * integer value since we support only integer values of bpp.
625 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
626 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
627 if (intel_dp_is_edp(intel_dp)) {
629 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
631 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
633 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
635 intel_dp_dsc_get_output_bpp(max_link_clock,
638 mode->hdisplay) >> 4;
640 intel_dp_dsc_get_slice_count(intel_dp,
646 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
647 target_clock > max_dotclk)
648 return MODE_CLOCK_HIGH;
650 if (mode->clock < 10000)
651 return MODE_CLOCK_LOW;
653 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
654 return MODE_H_ILLEGAL;
656 return intel_mode_valid_max_plane_size(dev_priv, mode);
659 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
666 for (i = 0; i < src_bytes; i++)
667 v |= ((u32)src[i]) << ((3 - i) * 8);
671 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
676 for (i = 0; i < dst_bytes; i++)
677 dst[i] = src >> ((3-i) * 8);
681 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
683 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
684 bool force_disable_vdd);
686 intel_dp_pps_init(struct intel_dp *intel_dp);
688 static intel_wakeref_t
689 pps_lock(struct intel_dp *intel_dp)
691 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
692 intel_wakeref_t wakeref;
695 * See intel_power_sequencer_reset() why we need
696 * a power domain reference here.
698 wakeref = intel_display_power_get(dev_priv,
699 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
701 mutex_lock(&dev_priv->pps_mutex);
706 static intel_wakeref_t
707 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
709 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
711 mutex_unlock(&dev_priv->pps_mutex);
712 intel_display_power_put(dev_priv,
713 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
718 #define with_pps_lock(dp, wf) \
719 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
722 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
724 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
725 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
726 enum pipe pipe = intel_dp->pps_pipe;
727 bool pll_enabled, release_cl_override = false;
728 enum dpio_phy phy = DPIO_PHY(pipe);
729 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
732 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
733 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
734 pipe_name(pipe), intel_dig_port->base.base.base.id,
735 intel_dig_port->base.base.name))
738 DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
739 pipe_name(pipe), intel_dig_port->base.base.base.id,
740 intel_dig_port->base.base.name);
742 /* Preserve the BIOS-computed detected bit. This is
743 * supposed to be read-only.
745 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
746 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
747 DP |= DP_PORT_WIDTH(1);
748 DP |= DP_LINK_TRAIN_PAT_1;
750 if (IS_CHERRYVIEW(dev_priv))
751 DP |= DP_PIPE_SEL_CHV(pipe);
753 DP |= DP_PIPE_SEL(pipe);
755 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
758 * The DPLL for the pipe must be enabled for this to work.
759 * So enable temporarily it if it's not already enabled.
762 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
763 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
765 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
766 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
767 DRM_ERROR("Failed to force on pll for pipe %c!\n",
774 * Similar magic as in intel_dp_enable_port().
775 * We _must_ do this port enable + disable trick
776 * to make this power sequencer lock onto the port.
777 * Otherwise even VDD force bit won't work.
779 I915_WRITE(intel_dp->output_reg, DP);
780 POSTING_READ(intel_dp->output_reg);
782 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
783 POSTING_READ(intel_dp->output_reg);
785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
786 POSTING_READ(intel_dp->output_reg);
789 vlv_force_pll_off(dev_priv, pipe);
791 if (release_cl_override)
792 chv_phy_powergate_ch(dev_priv, phy, ch, false);
796 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
798 struct intel_encoder *encoder;
799 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
802 * We don't have power sequencer currently.
803 * Pick one that's not used by other ports.
805 for_each_intel_dp(&dev_priv->drm, encoder) {
806 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
808 if (encoder->type == INTEL_OUTPUT_EDP) {
809 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
810 intel_dp->active_pipe != intel_dp->pps_pipe);
812 if (intel_dp->pps_pipe != INVALID_PIPE)
813 pipes &= ~(1 << intel_dp->pps_pipe);
815 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
817 if (intel_dp->active_pipe != INVALID_PIPE)
818 pipes &= ~(1 << intel_dp->active_pipe);
825 return ffs(pipes) - 1;
829 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
831 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
832 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
835 lockdep_assert_held(&dev_priv->pps_mutex);
837 /* We should never land here with regular DP ports */
838 WARN_ON(!intel_dp_is_edp(intel_dp));
840 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
841 intel_dp->active_pipe != intel_dp->pps_pipe);
843 if (intel_dp->pps_pipe != INVALID_PIPE)
844 return intel_dp->pps_pipe;
846 pipe = vlv_find_free_pps(dev_priv);
849 * Didn't find one. This should not happen since there
850 * are two power sequencers and up to two eDP ports.
852 if (WARN_ON(pipe == INVALID_PIPE))
855 vlv_steal_power_sequencer(dev_priv, pipe);
856 intel_dp->pps_pipe = pipe;
858 DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
859 pipe_name(intel_dp->pps_pipe),
860 intel_dig_port->base.base.base.id,
861 intel_dig_port->base.base.name);
863 /* init power sequencer on this pipe and port */
864 intel_dp_init_panel_power_sequencer(intel_dp);
865 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
868 * Even vdd force doesn't work until we've made
869 * the power sequencer lock in on the port.
871 vlv_power_sequencer_kick(intel_dp);
873 return intel_dp->pps_pipe;
877 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
879 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
880 int backlight_controller = dev_priv->vbt.backlight.controller;
882 lockdep_assert_held(&dev_priv->pps_mutex);
884 /* We should never land here with regular DP ports */
885 WARN_ON(!intel_dp_is_edp(intel_dp));
887 if (!intel_dp->pps_reset)
888 return backlight_controller;
890 intel_dp->pps_reset = false;
893 * Only the HW needs to be reprogrammed, the SW state is fixed and
894 * has been setup during connector init.
896 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
898 return backlight_controller;
901 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
904 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
907 return I915_READ(PP_STATUS(pipe)) & PP_ON;
910 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
913 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
916 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
923 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
925 vlv_pipe_check pipe_check)
929 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
930 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
931 PANEL_PORT_SELECT_MASK;
933 if (port_sel != PANEL_PORT_SELECT_VLV(port))
936 if (!pipe_check(dev_priv, pipe))
946 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
948 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
949 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
950 enum port port = intel_dig_port->base.port;
952 lockdep_assert_held(&dev_priv->pps_mutex);
954 /* try to find a pipe with this port selected */
955 /* first pick one where the panel is on */
956 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
958 /* didn't find one? pick one where vdd is on */
959 if (intel_dp->pps_pipe == INVALID_PIPE)
960 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
961 vlv_pipe_has_vdd_on);
962 /* didn't find one? pick one with just the correct port */
963 if (intel_dp->pps_pipe == INVALID_PIPE)
964 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
967 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
968 if (intel_dp->pps_pipe == INVALID_PIPE) {
969 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
970 intel_dig_port->base.base.base.id,
971 intel_dig_port->base.base.name);
975 DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
976 intel_dig_port->base.base.base.id,
977 intel_dig_port->base.base.name,
978 pipe_name(intel_dp->pps_pipe));
980 intel_dp_init_panel_power_sequencer(intel_dp);
981 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
984 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
986 struct intel_encoder *encoder;
988 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
989 !IS_GEN9_LP(dev_priv)))
993 * We can't grab pps_mutex here due to deadlock with power_domain
994 * mutex when power_domain functions are called while holding pps_mutex.
995 * That also means that in order to use pps_pipe the code needs to
996 * hold both a power domain reference and pps_mutex, and the power domain
997 * reference get/put must be done while _not_ holding pps_mutex.
998 * pps_{lock,unlock}() do these steps in the correct order, so one
999 * should use them always.
1002 for_each_intel_dp(&dev_priv->drm, encoder) {
1003 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1005 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1007 if (encoder->type != INTEL_OUTPUT_EDP)
1010 if (IS_GEN9_LP(dev_priv))
1011 intel_dp->pps_reset = true;
1013 intel_dp->pps_pipe = INVALID_PIPE;
1017 struct pps_registers {
1025 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1026 struct pps_registers *regs)
1028 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1031 memset(regs, 0, sizeof(*regs));
1033 if (IS_GEN9_LP(dev_priv))
1034 pps_idx = bxt_power_sequencer_idx(intel_dp);
1035 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1036 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1038 regs->pp_ctrl = PP_CONTROL(pps_idx);
1039 regs->pp_stat = PP_STATUS(pps_idx);
1040 regs->pp_on = PP_ON_DELAYS(pps_idx);
1041 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1043 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1044 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1045 regs->pp_div = INVALID_MMIO_REG;
1047 regs->pp_div = PP_DIVISOR(pps_idx);
1051 _pp_ctrl_reg(struct intel_dp *intel_dp)
1053 struct pps_registers regs;
1055 intel_pps_get_registers(intel_dp, ®s);
1057 return regs.pp_ctrl;
1061 _pp_stat_reg(struct intel_dp *intel_dp)
1063 struct pps_registers regs;
1065 intel_pps_get_registers(intel_dp, ®s);
1067 return regs.pp_stat;
1070 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1071 This function only applicable when panel PM state is not to be tracked */
1072 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1075 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1077 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1078 intel_wakeref_t wakeref;
1080 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1083 with_pps_lock(intel_dp, wakeref) {
1084 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1085 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1086 i915_reg_t pp_ctrl_reg, pp_div_reg;
1089 pp_ctrl_reg = PP_CONTROL(pipe);
1090 pp_div_reg = PP_DIVISOR(pipe);
1091 pp_div = I915_READ(pp_div_reg);
1092 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1094 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1095 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1096 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1097 msleep(intel_dp->panel_power_cycle_delay);
1104 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1106 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1108 lockdep_assert_held(&dev_priv->pps_mutex);
1110 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1111 intel_dp->pps_pipe == INVALID_PIPE)
1114 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1117 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1119 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1121 lockdep_assert_held(&dev_priv->pps_mutex);
1123 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1124 intel_dp->pps_pipe == INVALID_PIPE)
1127 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1131 intel_dp_check_edp(struct intel_dp *intel_dp)
1133 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1135 if (!intel_dp_is_edp(intel_dp))
1138 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1139 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1140 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1141 I915_READ(_pp_stat_reg(intel_dp)),
1142 I915_READ(_pp_ctrl_reg(intel_dp)));
1147 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1149 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1150 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1154 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1155 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1156 msecs_to_jiffies_timeout(10));
1158 /* just trace the final value */
1159 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1162 DRM_ERROR("dp aux hw did not signal timeout!\n");
1168 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1170 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1176 * The clock divider is based off the hrawclk, and would like to run at
1177 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1179 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1182 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1184 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1185 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1191 * The clock divider is based off the cdclk or PCH rawclk, and would
1192 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1193 * divide by 2000 and use that
1195 if (dig_port->aux_ch == AUX_CH_A)
1196 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1198 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1201 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1203 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1204 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1206 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1207 /* Workaround for non-ULT HSW */
1215 return ilk_get_aux_clock_divider(intel_dp, index);
1218 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1221 * SKL doesn't need us to program the AUX clock divider (Hardware will
1222 * derive the clock from CDCLK automatically). We still implement the
1223 * get_aux_clock_divider vfunc to plug-in into the existing code.
1225 return index ? 0 : 1;
1228 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1230 u32 aux_clock_divider)
1232 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1233 struct drm_i915_private *dev_priv =
1234 to_i915(intel_dig_port->base.base.dev);
1235 u32 precharge, timeout;
1237 if (IS_GEN(dev_priv, 6))
1242 if (IS_BROADWELL(dev_priv))
1243 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1245 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1247 return DP_AUX_CH_CTL_SEND_BUSY |
1248 DP_AUX_CH_CTL_DONE |
1249 DP_AUX_CH_CTL_INTERRUPT |
1250 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1252 DP_AUX_CH_CTL_RECEIVE_ERROR |
1253 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1254 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1255 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1258 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1265 ret = DP_AUX_CH_CTL_SEND_BUSY |
1266 DP_AUX_CH_CTL_DONE |
1267 DP_AUX_CH_CTL_INTERRUPT |
1268 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1269 DP_AUX_CH_CTL_TIME_OUT_MAX |
1270 DP_AUX_CH_CTL_RECEIVE_ERROR |
1271 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1272 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1273 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1275 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1276 ret |= DP_AUX_CH_CTL_TBT_IO;
1282 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1283 const u8 *send, int send_bytes,
1284 u8 *recv, int recv_size,
1285 u32 aux_send_ctl_flags)
1287 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1288 struct drm_i915_private *i915 =
1289 to_i915(intel_dig_port->base.base.dev);
1290 struct intel_uncore *uncore = &i915->uncore;
1291 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1292 bool is_tc_port = intel_phy_is_tc(i915, phy);
1293 i915_reg_t ch_ctl, ch_data[5];
1294 u32 aux_clock_divider;
1295 enum intel_display_power_domain aux_domain =
1296 intel_aux_power_domain(intel_dig_port);
1297 intel_wakeref_t aux_wakeref;
1298 intel_wakeref_t pps_wakeref;
1299 int i, ret, recv_bytes;
1304 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1305 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1306 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1309 intel_tc_port_lock(intel_dig_port);
1311 aux_wakeref = intel_display_power_get(i915, aux_domain);
1312 pps_wakeref = pps_lock(intel_dp);
1315 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1316 * In such cases we want to leave VDD enabled and it's up to upper layers
1317 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1320 vdd = edp_panel_vdd_on(intel_dp);
1322 /* dp aux is extremely sensitive to irq latency, hence request the
1323 * lowest possible wakeup latency and so prevent the cpu from going into
1324 * deep sleep states.
1326 pm_qos_update_request(&i915->pm_qos, 0);
1328 intel_dp_check_edp(intel_dp);
1330 /* Try to wait for any previous AUX channel activity */
1331 for (try = 0; try < 3; try++) {
1332 status = intel_uncore_read_notrace(uncore, ch_ctl);
1333 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1337 /* just trace the final value */
1338 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1341 static u32 last_status = -1;
1342 const u32 status = intel_uncore_read(uncore, ch_ctl);
1344 if (status != last_status) {
1345 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1347 last_status = status;
1354 /* Only 5 data registers! */
1355 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1360 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1361 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1365 send_ctl |= aux_send_ctl_flags;
1367 /* Must try at least 3 times according to DP spec */
1368 for (try = 0; try < 5; try++) {
1369 /* Load the send data into the aux channel data registers */
1370 for (i = 0; i < send_bytes; i += 4)
1371 intel_uncore_write(uncore,
1373 intel_dp_pack_aux(send + i,
1376 /* Send the command and wait for it to complete */
1377 intel_uncore_write(uncore, ch_ctl, send_ctl);
1379 status = intel_dp_aux_wait_done(intel_dp);
1381 /* Clear done status and any errors */
1382 intel_uncore_write(uncore,
1385 DP_AUX_CH_CTL_DONE |
1386 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1387 DP_AUX_CH_CTL_RECEIVE_ERROR);
1389 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1390 * 400us delay required for errors and timeouts
1391 * Timeout errors from the HW already meet this
1392 * requirement so skip to next iteration
1394 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1397 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1398 usleep_range(400, 500);
1401 if (status & DP_AUX_CH_CTL_DONE)
1406 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1407 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1413 /* Check for timeout or receive error.
1414 * Timeouts occur when the sink is not connected
1416 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1417 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1422 /* Timeouts occur when the device isn't connected, so they're
1423 * "normal" -- don't fill the kernel log with these */
1424 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1425 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1430 /* Unload any bytes sent back from the other side */
1431 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1432 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1435 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1436 * We have no idea of what happened so we return -EBUSY so
1437 * drm layer takes care for the necessary retries.
1439 if (recv_bytes == 0 || recv_bytes > 20) {
1440 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1446 if (recv_bytes > recv_size)
1447 recv_bytes = recv_size;
1449 for (i = 0; i < recv_bytes; i += 4)
1450 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1451 recv + i, recv_bytes - i);
1455 pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1458 edp_panel_vdd_off(intel_dp, false);
1460 pps_unlock(intel_dp, pps_wakeref);
1461 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1464 intel_tc_port_unlock(intel_dig_port);
1469 #define BARE_ADDRESS_SIZE 3
1470 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1473 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1474 const struct drm_dp_aux_msg *msg)
1476 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1477 txbuf[1] = (msg->address >> 8) & 0xff;
1478 txbuf[2] = msg->address & 0xff;
1479 txbuf[3] = msg->size - 1;
1483 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1485 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1486 u8 txbuf[20], rxbuf[20];
1487 size_t txsize, rxsize;
1490 intel_dp_aux_header(txbuf, msg);
1492 switch (msg->request & ~DP_AUX_I2C_MOT) {
1493 case DP_AUX_NATIVE_WRITE:
1494 case DP_AUX_I2C_WRITE:
1495 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1496 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1497 rxsize = 2; /* 0 or 1 data bytes */
1499 if (WARN_ON(txsize > 20))
1502 WARN_ON(!msg->buffer != !msg->size);
1505 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1507 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1510 msg->reply = rxbuf[0] >> 4;
1513 /* Number of bytes written in a short write. */
1514 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1516 /* Return payload size. */
1522 case DP_AUX_NATIVE_READ:
1523 case DP_AUX_I2C_READ:
1524 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1525 rxsize = msg->size + 1;
1527 if (WARN_ON(rxsize > 20))
1530 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1533 msg->reply = rxbuf[0] >> 4;
1535 * Assume happy day, and copy the data. The caller is
1536 * expected to check msg->reply before touching it.
1538 * Return payload size.
1541 memcpy(msg->buffer, rxbuf + 1, ret);
1554 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1556 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1557 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1558 enum aux_ch aux_ch = dig_port->aux_ch;
1564 return DP_AUX_CH_CTL(aux_ch);
1566 MISSING_CASE(aux_ch);
1567 return DP_AUX_CH_CTL(AUX_CH_B);
1571 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1573 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1575 enum aux_ch aux_ch = dig_port->aux_ch;
1581 return DP_AUX_CH_DATA(aux_ch, index);
1583 MISSING_CASE(aux_ch);
1584 return DP_AUX_CH_DATA(AUX_CH_B, index);
1588 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1590 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1591 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1592 enum aux_ch aux_ch = dig_port->aux_ch;
1596 return DP_AUX_CH_CTL(aux_ch);
1600 return PCH_DP_AUX_CH_CTL(aux_ch);
1602 MISSING_CASE(aux_ch);
1603 return DP_AUX_CH_CTL(AUX_CH_A);
1607 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1609 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1610 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1611 enum aux_ch aux_ch = dig_port->aux_ch;
1615 return DP_AUX_CH_DATA(aux_ch, index);
1619 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1621 MISSING_CASE(aux_ch);
1622 return DP_AUX_CH_DATA(AUX_CH_A, index);
1626 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1628 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1630 enum aux_ch aux_ch = dig_port->aux_ch;
1639 return DP_AUX_CH_CTL(aux_ch);
1641 MISSING_CASE(aux_ch);
1642 return DP_AUX_CH_CTL(AUX_CH_A);
1646 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1648 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1649 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1650 enum aux_ch aux_ch = dig_port->aux_ch;
1659 return DP_AUX_CH_DATA(aux_ch, index);
1661 MISSING_CASE(aux_ch);
1662 return DP_AUX_CH_DATA(AUX_CH_A, index);
1667 intel_dp_aux_fini(struct intel_dp *intel_dp)
1669 kfree(intel_dp->aux.name);
1673 intel_dp_aux_init(struct intel_dp *intel_dp)
1675 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1676 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1677 struct intel_encoder *encoder = &dig_port->base;
1679 if (INTEL_GEN(dev_priv) >= 9) {
1680 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1681 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1682 } else if (HAS_PCH_SPLIT(dev_priv)) {
1683 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1684 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1686 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1687 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1690 if (INTEL_GEN(dev_priv) >= 9)
1691 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1692 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1693 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1694 else if (HAS_PCH_SPLIT(dev_priv))
1695 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1697 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1699 if (INTEL_GEN(dev_priv) >= 9)
1700 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1702 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1704 drm_dp_aux_init(&intel_dp->aux);
1706 /* Failure to allocate our preferred name is not critical */
1707 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1708 port_name(encoder->port));
1709 intel_dp->aux.transfer = intel_dp_aux_transfer;
1712 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1714 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1716 return max_rate >= 540000;
1719 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1721 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1723 return max_rate >= 810000;
1727 intel_dp_set_clock(struct intel_encoder *encoder,
1728 struct intel_crtc_state *pipe_config)
1730 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1731 const struct dp_link_dpll *divisor = NULL;
1734 if (IS_G4X(dev_priv)) {
1736 count = ARRAY_SIZE(g4x_dpll);
1737 } else if (HAS_PCH_SPLIT(dev_priv)) {
1739 count = ARRAY_SIZE(pch_dpll);
1740 } else if (IS_CHERRYVIEW(dev_priv)) {
1742 count = ARRAY_SIZE(chv_dpll);
1743 } else if (IS_VALLEYVIEW(dev_priv)) {
1745 count = ARRAY_SIZE(vlv_dpll);
1748 if (divisor && count) {
1749 for (i = 0; i < count; i++) {
1750 if (pipe_config->port_clock == divisor[i].clock) {
1751 pipe_config->dpll = divisor[i].dpll;
1752 pipe_config->clock_set = true;
1759 static void snprintf_int_array(char *str, size_t len,
1760 const int *array, int nelem)
1766 for (i = 0; i < nelem; i++) {
1767 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1775 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1777 char str[128]; /* FIXME: too big for stack? */
1779 if ((drm_debug & DRM_UT_KMS) == 0)
1782 snprintf_int_array(str, sizeof(str),
1783 intel_dp->source_rates, intel_dp->num_source_rates);
1784 DRM_DEBUG_KMS("source rates: %s\n", str);
1786 snprintf_int_array(str, sizeof(str),
1787 intel_dp->sink_rates, intel_dp->num_sink_rates);
1788 DRM_DEBUG_KMS("sink rates: %s\n", str);
1790 snprintf_int_array(str, sizeof(str),
1791 intel_dp->common_rates, intel_dp->num_common_rates);
1792 DRM_DEBUG_KMS("common rates: %s\n", str);
1796 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1800 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1801 if (WARN_ON(len <= 0))
1804 return intel_dp->common_rates[len - 1];
1807 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1809 int i = intel_dp_rate_index(intel_dp->sink_rates,
1810 intel_dp->num_sink_rates, rate);
1818 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1819 u8 *link_bw, u8 *rate_select)
1821 /* eDP 1.4 rate select method. */
1822 if (intel_dp->use_rate_select) {
1825 intel_dp_rate_select(intel_dp, port_clock);
1827 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1832 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1833 const struct intel_crtc_state *pipe_config)
1835 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1837 /* On TGL, FEC is supported on all Pipes */
1838 if (INTEL_GEN(dev_priv) >= 12)
1841 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1847 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1848 const struct intel_crtc_state *pipe_config)
1850 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1851 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1854 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1855 const struct intel_crtc_state *pipe_config)
1857 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1859 /* On TGL, DSC is supported on all Pipes */
1860 if (INTEL_GEN(dev_priv) >= 12)
1863 if (INTEL_GEN(dev_priv) >= 10 &&
1864 pipe_config->cpu_transcoder != TRANSCODER_A)
1870 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1871 const struct intel_crtc_state *pipe_config)
1873 if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1876 return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1877 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1880 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1881 struct intel_crtc_state *pipe_config)
1883 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1884 struct intel_connector *intel_connector = intel_dp->attached_connector;
1887 bpp = pipe_config->pipe_bpp;
1888 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1891 bpp = min(bpp, 3*bpc);
1893 if (intel_dp_is_edp(intel_dp)) {
1894 /* Get bpp from vbt only for panels that dont have bpp in edid */
1895 if (intel_connector->base.display_info.bpc == 0 &&
1896 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1897 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1898 dev_priv->vbt.edp.bpp);
1899 bpp = dev_priv->vbt.edp.bpp;
1906 /* Adjust link config limits based on compliance test requests. */
1908 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1909 struct intel_crtc_state *pipe_config,
1910 struct link_config_limits *limits)
1912 /* For DP Compliance we override the computed bpp for the pipe */
1913 if (intel_dp->compliance.test_data.bpc != 0) {
1914 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1916 limits->min_bpp = limits->max_bpp = bpp;
1917 pipe_config->dither_force_disable = bpp == 6 * 3;
1919 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1922 /* Use values requested by Compliance Test Request */
1923 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1926 /* Validate the compliance test data since max values
1927 * might have changed due to link train fallback.
1929 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1930 intel_dp->compliance.test_lane_count)) {
1931 index = intel_dp_rate_index(intel_dp->common_rates,
1932 intel_dp->num_common_rates,
1933 intel_dp->compliance.test_link_rate);
1935 limits->min_clock = limits->max_clock = index;
1936 limits->min_lane_count = limits->max_lane_count =
1937 intel_dp->compliance.test_lane_count;
1942 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1945 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1946 * format of the number of bytes per pixel will be half the number
1947 * of bytes of RGB pixel.
1949 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1955 /* Optimize link config in order: max bpp, min clock, min lanes */
1957 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1958 struct intel_crtc_state *pipe_config,
1959 const struct link_config_limits *limits)
1961 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1962 int bpp, clock, lane_count;
1963 int mode_rate, link_clock, link_avail;
1965 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1966 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
1968 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1971 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1972 for (lane_count = limits->min_lane_count;
1973 lane_count <= limits->max_lane_count;
1975 link_clock = intel_dp->common_rates[clock];
1976 link_avail = intel_dp_max_data_rate(link_clock,
1979 if (mode_rate <= link_avail) {
1980 pipe_config->lane_count = lane_count;
1981 pipe_config->pipe_bpp = bpp;
1982 pipe_config->port_clock = link_clock;
1993 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1996 u8 dsc_bpc[3] = {0};
1998 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2000 for (i = 0; i < num_bpc; i++) {
2001 if (dsc_max_bpc >= dsc_bpc[i])
2002 return dsc_bpc[i] * 3;
2008 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2009 struct intel_crtc_state *pipe_config,
2010 struct drm_connector_state *conn_state,
2011 struct link_config_limits *limits)
2013 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2014 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2015 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2020 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2021 intel_dp_supports_fec(intel_dp, pipe_config);
2023 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2026 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2027 if (INTEL_GEN(dev_priv) >= 12)
2028 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2030 dsc_max_bpc = min_t(u8, 10,
2031 conn_state->max_requested_bpc);
2033 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2035 /* Min Input BPC for ICL+ is 8 */
2036 if (pipe_bpp < 8 * 3) {
2037 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2042 * For now enable DSC for max bpp, max link rate, max lane count.
2043 * Optimize this later for the minimum possible link rate/lane count
2044 * with DSC enabled for the requested mode.
2046 pipe_config->pipe_bpp = pipe_bpp;
2047 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2048 pipe_config->lane_count = limits->max_lane_count;
2050 if (intel_dp_is_edp(intel_dp)) {
2051 pipe_config->dsc_params.compressed_bpp =
2052 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2053 pipe_config->pipe_bpp);
2054 pipe_config->dsc_params.slice_count =
2055 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2058 u16 dsc_max_output_bpp;
2059 u8 dsc_dp_slice_count;
2061 dsc_max_output_bpp =
2062 intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
2063 pipe_config->lane_count,
2064 adjusted_mode->crtc_clock,
2065 adjusted_mode->crtc_hdisplay);
2066 dsc_dp_slice_count =
2067 intel_dp_dsc_get_slice_count(intel_dp,
2068 adjusted_mode->crtc_clock,
2069 adjusted_mode->crtc_hdisplay);
2070 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2071 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2074 pipe_config->dsc_params.compressed_bpp = min_t(u16,
2075 dsc_max_output_bpp >> 4,
2076 pipe_config->pipe_bpp);
2077 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
2080 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2081 * is greater than the maximum Cdclock and if slice count is even
2082 * then we need to use 2 VDSC instances.
2084 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2085 if (pipe_config->dsc_params.slice_count > 1) {
2086 pipe_config->dsc_params.dsc_split = true;
2088 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2093 ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
2095 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2096 "Compressed BPP = %d\n",
2097 pipe_config->pipe_bpp,
2098 pipe_config->dsc_params.compressed_bpp);
2102 pipe_config->dsc_params.compression_enable = true;
2103 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2104 "Compressed Bpp = %d Slice Count = %d\n",
2105 pipe_config->pipe_bpp,
2106 pipe_config->dsc_params.compressed_bpp,
2107 pipe_config->dsc_params.slice_count);
2112 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2114 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2121 intel_dp_compute_link_config(struct intel_encoder *encoder,
2122 struct intel_crtc_state *pipe_config,
2123 struct drm_connector_state *conn_state)
2125 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2126 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2127 struct link_config_limits limits;
2131 common_len = intel_dp_common_len_rate_limit(intel_dp,
2132 intel_dp->max_link_rate);
2134 /* No common link rates between source and sink */
2135 WARN_ON(common_len <= 0);
2137 limits.min_clock = 0;
2138 limits.max_clock = common_len - 1;
2140 limits.min_lane_count = 1;
2141 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2143 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2144 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2146 if (intel_dp_is_edp(intel_dp)) {
2148 * Use the maximum clock and number of lanes the eDP panel
2149 * advertizes being capable of. The panels are generally
2150 * designed to support only a single clock and lane
2151 * configuration, and typically these values correspond to the
2152 * native resolution of the panel.
2154 limits.min_lane_count = limits.max_lane_count;
2155 limits.min_clock = limits.max_clock;
2158 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2160 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2161 "max rate %d max bpp %d pixel clock %iKHz\n",
2162 limits.max_lane_count,
2163 intel_dp->common_rates[limits.max_clock],
2164 limits.max_bpp, adjusted_mode->crtc_clock);
2167 * Optimize for slow and wide. This is the place to add alternative
2168 * optimization policy.
2170 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2172 /* enable compression if the mode doesn't fit available BW */
2173 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2174 if (ret || intel_dp->force_dsc_en) {
2175 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2176 conn_state, &limits);
2181 if (pipe_config->dsc_params.compression_enable) {
2182 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2183 pipe_config->lane_count, pipe_config->port_clock,
2184 pipe_config->pipe_bpp,
2185 pipe_config->dsc_params.compressed_bpp);
2187 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2188 intel_dp_link_required(adjusted_mode->crtc_clock,
2189 pipe_config->dsc_params.compressed_bpp),
2190 intel_dp_max_data_rate(pipe_config->port_clock,
2191 pipe_config->lane_count));
2193 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2194 pipe_config->lane_count, pipe_config->port_clock,
2195 pipe_config->pipe_bpp);
2197 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2198 intel_dp_link_required(adjusted_mode->crtc_clock,
2199 pipe_config->pipe_bpp),
2200 intel_dp_max_data_rate(pipe_config->port_clock,
2201 pipe_config->lane_count));
2207 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2208 struct drm_connector *connector,
2209 struct intel_crtc_state *crtc_state)
2211 const struct drm_display_info *info = &connector->display_info;
2212 const struct drm_display_mode *adjusted_mode =
2213 &crtc_state->base.adjusted_mode;
2214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2217 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2218 !intel_dp_get_colorimetry_status(intel_dp) ||
2219 !connector->ycbcr_420_allowed)
2222 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2224 /* YCBCR 420 output conversion needs a scaler */
2225 ret = skl_update_scaler_crtc(crtc_state);
2227 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2231 intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2236 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2237 const struct drm_connector_state *conn_state)
2239 const struct intel_digital_connector_state *intel_conn_state =
2240 to_intel_digital_connector_state(conn_state);
2241 const struct drm_display_mode *adjusted_mode =
2242 &crtc_state->base.adjusted_mode;
2245 * Our YCbCr output is always limited range.
2246 * crtc_state->limited_color_range only applies to RGB,
2247 * and it must never be set for YCbCr or we risk setting
2248 * some conflicting bits in PIPECONF which will mess up
2249 * the colors on the monitor.
2251 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2254 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2257 * CEA-861-E - 5.1 Default Encoding Parameters
2258 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2260 return crtc_state->pipe_bpp != 18 &&
2261 drm_default_rgb_quant_range(adjusted_mode) ==
2262 HDMI_QUANTIZATION_RANGE_LIMITED;
2264 return intel_conn_state->broadcast_rgb ==
2265 INTEL_BROADCAST_RGB_LIMITED;
2270 intel_dp_compute_config(struct intel_encoder *encoder,
2271 struct intel_crtc_state *pipe_config,
2272 struct drm_connector_state *conn_state)
2274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2275 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2276 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2277 struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2278 enum port port = encoder->port;
2279 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2280 struct intel_connector *intel_connector = intel_dp->attached_connector;
2281 struct intel_digital_connector_state *intel_conn_state =
2282 to_intel_digital_connector_state(conn_state);
2283 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2284 DP_DPCD_QUIRK_CONSTANT_N);
2285 int ret = 0, output_bpp;
2287 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2288 pipe_config->has_pch_encoder = true;
2290 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2292 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2294 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2300 pipe_config->has_drrs = false;
2301 if (IS_G4X(dev_priv) || port == PORT_A)
2302 pipe_config->has_audio = false;
2303 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2304 pipe_config->has_audio = intel_dp->has_audio;
2306 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2308 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2309 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2312 if (INTEL_GEN(dev_priv) >= 9) {
2313 ret = skl_update_scaler_crtc(pipe_config);
2318 if (HAS_GMCH(dev_priv))
2319 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2320 conn_state->scaling_mode);
2322 intel_pch_panel_fitting(intel_crtc, pipe_config,
2323 conn_state->scaling_mode);
2326 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2329 if (HAS_GMCH(dev_priv) &&
2330 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2333 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2336 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2340 pipe_config->limited_color_range =
2341 intel_dp_limited_color_range(pipe_config, conn_state);
2343 if (pipe_config->dsc_params.compression_enable)
2344 output_bpp = pipe_config->dsc_params.compressed_bpp;
2346 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2348 intel_link_compute_m_n(output_bpp,
2349 pipe_config->lane_count,
2350 adjusted_mode->crtc_clock,
2351 pipe_config->port_clock,
2352 &pipe_config->dp_m_n,
2353 constant_n, pipe_config->fec_enable);
2355 if (intel_connector->panel.downclock_mode != NULL &&
2356 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2357 pipe_config->has_drrs = true;
2358 intel_link_compute_m_n(output_bpp,
2359 pipe_config->lane_count,
2360 intel_connector->panel.downclock_mode->clock,
2361 pipe_config->port_clock,
2362 &pipe_config->dp_m2_n2,
2363 constant_n, pipe_config->fec_enable);
2366 if (!HAS_DDI(dev_priv))
2367 intel_dp_set_clock(encoder, pipe_config);
2369 intel_psr_compute_config(intel_dp, pipe_config);
2371 intel_hdcp_transcoder_config(intel_connector,
2372 pipe_config->cpu_transcoder);
2377 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2378 int link_rate, u8 lane_count,
2381 intel_dp->link_trained = false;
2382 intel_dp->link_rate = link_rate;
2383 intel_dp->lane_count = lane_count;
2384 intel_dp->link_mst = link_mst;
2387 static void intel_dp_prepare(struct intel_encoder *encoder,
2388 const struct intel_crtc_state *pipe_config)
2390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2392 enum port port = encoder->port;
2393 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2394 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2396 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2397 pipe_config->lane_count,
2398 intel_crtc_has_type(pipe_config,
2399 INTEL_OUTPUT_DP_MST));
2401 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2402 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2405 * There are four kinds of DP registers:
2412 * IBX PCH and CPU are the same for almost everything,
2413 * except that the CPU DP PLL is configured in this
2416 * CPT PCH is quite different, having many bits moved
2417 * to the TRANS_DP_CTL register instead. That
2418 * configuration happens (oddly) in ironlake_pch_enable
2421 /* Preserve the BIOS-computed detected bit. This is
2422 * supposed to be read-only.
2424 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2426 /* Handle DP bits in common between all three register formats */
2427 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2428 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2430 /* Split out the IBX/CPU vs CPT settings */
2432 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2433 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2434 intel_dp->DP |= DP_SYNC_HS_HIGH;
2435 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2436 intel_dp->DP |= DP_SYNC_VS_HIGH;
2437 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2439 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2440 intel_dp->DP |= DP_ENHANCED_FRAMING;
2442 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2443 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2446 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2448 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2449 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2450 trans_dp |= TRANS_DP_ENH_FRAMING;
2452 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2453 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2455 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2456 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2458 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2459 intel_dp->DP |= DP_SYNC_HS_HIGH;
2460 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2461 intel_dp->DP |= DP_SYNC_VS_HIGH;
2462 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2464 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2465 intel_dp->DP |= DP_ENHANCED_FRAMING;
2467 if (IS_CHERRYVIEW(dev_priv))
2468 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2470 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2474 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2475 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2477 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2478 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2480 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2481 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2483 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2485 static void wait_panel_status(struct intel_dp *intel_dp,
2489 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2490 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2492 lockdep_assert_held(&dev_priv->pps_mutex);
2494 intel_pps_verify_state(intel_dp);
2496 pp_stat_reg = _pp_stat_reg(intel_dp);
2497 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2499 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2501 I915_READ(pp_stat_reg),
2502 I915_READ(pp_ctrl_reg));
2504 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2506 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2507 I915_READ(pp_stat_reg),
2508 I915_READ(pp_ctrl_reg));
2510 DRM_DEBUG_KMS("Wait complete\n");
2513 static void wait_panel_on(struct intel_dp *intel_dp)
2515 DRM_DEBUG_KMS("Wait for panel power on\n");
2516 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2519 static void wait_panel_off(struct intel_dp *intel_dp)
2521 DRM_DEBUG_KMS("Wait for panel power off time\n");
2522 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2525 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2527 ktime_t panel_power_on_time;
2528 s64 panel_power_off_duration;
2530 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2532 /* take the difference of currrent time and panel power off time
2533 * and then make panel wait for t11_t12 if needed. */
2534 panel_power_on_time = ktime_get_boottime();
2535 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2537 /* When we disable the VDD override bit last we have to do the manual
2539 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2540 wait_remaining_ms_from_jiffies(jiffies,
2541 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2543 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2546 static void wait_backlight_on(struct intel_dp *intel_dp)
2548 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2549 intel_dp->backlight_on_delay);
2552 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2554 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2555 intel_dp->backlight_off_delay);
2558 /* Read the current pp_control value, unlocking the register if it
2562 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2564 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2567 lockdep_assert_held(&dev_priv->pps_mutex);
2569 control = I915_READ(_pp_ctrl_reg(intel_dp));
2570 if (WARN_ON(!HAS_DDI(dev_priv) &&
2571 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2572 control &= ~PANEL_UNLOCK_MASK;
2573 control |= PANEL_UNLOCK_REGS;
2579 * Must be paired with edp_panel_vdd_off().
2580 * Must hold pps_mutex around the whole on/off sequence.
2581 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2583 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2585 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2588 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2589 bool need_to_disable = !intel_dp->want_panel_vdd;
2591 lockdep_assert_held(&dev_priv->pps_mutex);
2593 if (!intel_dp_is_edp(intel_dp))
2596 cancel_delayed_work(&intel_dp->panel_vdd_work);
2597 intel_dp->want_panel_vdd = true;
2599 if (edp_have_panel_vdd(intel_dp))
2600 return need_to_disable;
2602 intel_display_power_get(dev_priv,
2603 intel_aux_power_domain(intel_dig_port));
2605 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2606 intel_dig_port->base.base.base.id,
2607 intel_dig_port->base.base.name);
2609 if (!edp_have_panel_power(intel_dp))
2610 wait_panel_power_cycle(intel_dp);
2612 pp = ironlake_get_pp_control(intel_dp);
2613 pp |= EDP_FORCE_VDD;
2615 pp_stat_reg = _pp_stat_reg(intel_dp);
2616 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2618 I915_WRITE(pp_ctrl_reg, pp);
2619 POSTING_READ(pp_ctrl_reg);
2620 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2621 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2623 * If the panel wasn't on, delay before accessing aux channel
2625 if (!edp_have_panel_power(intel_dp)) {
2626 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2627 intel_dig_port->base.base.base.id,
2628 intel_dig_port->base.base.name);
2629 msleep(intel_dp->panel_power_up_delay);
2632 return need_to_disable;
2636 * Must be paired with intel_edp_panel_vdd_off() or
2637 * intel_edp_panel_off().
2638 * Nested calls to these functions are not allowed since
2639 * we drop the lock. Caller must use some higher level
2640 * locking to prevent nested calls from other threads.
2642 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2644 intel_wakeref_t wakeref;
2647 if (!intel_dp_is_edp(intel_dp))
2651 with_pps_lock(intel_dp, wakeref)
2652 vdd = edp_panel_vdd_on(intel_dp);
2653 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2654 dp_to_dig_port(intel_dp)->base.base.base.id,
2655 dp_to_dig_port(intel_dp)->base.base.name);
2658 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2660 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2661 struct intel_digital_port *intel_dig_port =
2662 dp_to_dig_port(intel_dp);
2664 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2666 lockdep_assert_held(&dev_priv->pps_mutex);
2668 WARN_ON(intel_dp->want_panel_vdd);
2670 if (!edp_have_panel_vdd(intel_dp))
2673 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2674 intel_dig_port->base.base.base.id,
2675 intel_dig_port->base.base.name);
2677 pp = ironlake_get_pp_control(intel_dp);
2678 pp &= ~EDP_FORCE_VDD;
2680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2681 pp_stat_reg = _pp_stat_reg(intel_dp);
2683 I915_WRITE(pp_ctrl_reg, pp);
2684 POSTING_READ(pp_ctrl_reg);
2686 /* Make sure sequencer is idle before allowing subsequent activity */
2687 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2688 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2690 if ((pp & PANEL_POWER_ON) == 0)
2691 intel_dp->panel_power_off_time = ktime_get_boottime();
2693 intel_display_power_put_unchecked(dev_priv,
2694 intel_aux_power_domain(intel_dig_port));
2697 static void edp_panel_vdd_work(struct work_struct *__work)
2699 struct intel_dp *intel_dp =
2700 container_of(to_delayed_work(__work),
2701 struct intel_dp, panel_vdd_work);
2702 intel_wakeref_t wakeref;
2704 with_pps_lock(intel_dp, wakeref) {
2705 if (!intel_dp->want_panel_vdd)
2706 edp_panel_vdd_off_sync(intel_dp);
2710 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2712 unsigned long delay;
2715 * Queue the timer to fire a long time from now (relative to the power
2716 * down delay) to keep the panel power up across a sequence of
2719 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2720 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2724 * Must be paired with edp_panel_vdd_on().
2725 * Must hold pps_mutex around the whole on/off sequence.
2726 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2728 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2730 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2732 lockdep_assert_held(&dev_priv->pps_mutex);
2734 if (!intel_dp_is_edp(intel_dp))
2737 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2738 dp_to_dig_port(intel_dp)->base.base.base.id,
2739 dp_to_dig_port(intel_dp)->base.base.name);
2741 intel_dp->want_panel_vdd = false;
2744 edp_panel_vdd_off_sync(intel_dp);
2746 edp_panel_vdd_schedule_off(intel_dp);
2749 static void edp_panel_on(struct intel_dp *intel_dp)
2751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2753 i915_reg_t pp_ctrl_reg;
2755 lockdep_assert_held(&dev_priv->pps_mutex);
2757 if (!intel_dp_is_edp(intel_dp))
2760 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2761 dp_to_dig_port(intel_dp)->base.base.base.id,
2762 dp_to_dig_port(intel_dp)->base.base.name);
2764 if (WARN(edp_have_panel_power(intel_dp),
2765 "[ENCODER:%d:%s] panel power already on\n",
2766 dp_to_dig_port(intel_dp)->base.base.base.id,
2767 dp_to_dig_port(intel_dp)->base.base.name))
2770 wait_panel_power_cycle(intel_dp);
2772 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2773 pp = ironlake_get_pp_control(intel_dp);
2774 if (IS_GEN(dev_priv, 5)) {
2775 /* ILK workaround: disable reset around power sequence */
2776 pp &= ~PANEL_POWER_RESET;
2777 I915_WRITE(pp_ctrl_reg, pp);
2778 POSTING_READ(pp_ctrl_reg);
2781 pp |= PANEL_POWER_ON;
2782 if (!IS_GEN(dev_priv, 5))
2783 pp |= PANEL_POWER_RESET;
2785 I915_WRITE(pp_ctrl_reg, pp);
2786 POSTING_READ(pp_ctrl_reg);
2788 wait_panel_on(intel_dp);
2789 intel_dp->last_power_on = jiffies;
2791 if (IS_GEN(dev_priv, 5)) {
2792 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2793 I915_WRITE(pp_ctrl_reg, pp);
2794 POSTING_READ(pp_ctrl_reg);
2798 void intel_edp_panel_on(struct intel_dp *intel_dp)
2800 intel_wakeref_t wakeref;
2802 if (!intel_dp_is_edp(intel_dp))
2805 with_pps_lock(intel_dp, wakeref)
2806 edp_panel_on(intel_dp);
2810 static void edp_panel_off(struct intel_dp *intel_dp)
2812 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2813 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2815 i915_reg_t pp_ctrl_reg;
2817 lockdep_assert_held(&dev_priv->pps_mutex);
2819 if (!intel_dp_is_edp(intel_dp))
2822 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2823 dig_port->base.base.base.id, dig_port->base.base.name);
2825 WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2826 dig_port->base.base.base.id, dig_port->base.base.name);
2828 pp = ironlake_get_pp_control(intel_dp);
2829 /* We need to switch off panel power _and_ force vdd, for otherwise some
2830 * panels get very unhappy and cease to work. */
2831 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2834 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2836 intel_dp->want_panel_vdd = false;
2838 I915_WRITE(pp_ctrl_reg, pp);
2839 POSTING_READ(pp_ctrl_reg);
2841 wait_panel_off(intel_dp);
2842 intel_dp->panel_power_off_time = ktime_get_boottime();
2844 /* We got a reference when we enabled the VDD. */
2845 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2848 void intel_edp_panel_off(struct intel_dp *intel_dp)
2850 intel_wakeref_t wakeref;
2852 if (!intel_dp_is_edp(intel_dp))
2855 with_pps_lock(intel_dp, wakeref)
2856 edp_panel_off(intel_dp);
2859 /* Enable backlight in the panel power control. */
2860 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2862 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2863 intel_wakeref_t wakeref;
2866 * If we enable the backlight right away following a panel power
2867 * on, we may see slight flicker as the panel syncs with the eDP
2868 * link. So delay a bit to make sure the image is solid before
2869 * allowing it to appear.
2871 wait_backlight_on(intel_dp);
2873 with_pps_lock(intel_dp, wakeref) {
2874 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2877 pp = ironlake_get_pp_control(intel_dp);
2878 pp |= EDP_BLC_ENABLE;
2880 I915_WRITE(pp_ctrl_reg, pp);
2881 POSTING_READ(pp_ctrl_reg);
2885 /* Enable backlight PWM and backlight PP control. */
2886 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2887 const struct drm_connector_state *conn_state)
2889 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2891 if (!intel_dp_is_edp(intel_dp))
2894 DRM_DEBUG_KMS("\n");
2896 intel_panel_enable_backlight(crtc_state, conn_state);
2897 _intel_edp_backlight_on(intel_dp);
2900 /* Disable backlight in the panel power control. */
2901 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2903 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2904 intel_wakeref_t wakeref;
2906 if (!intel_dp_is_edp(intel_dp))
2909 with_pps_lock(intel_dp, wakeref) {
2910 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2913 pp = ironlake_get_pp_control(intel_dp);
2914 pp &= ~EDP_BLC_ENABLE;
2916 I915_WRITE(pp_ctrl_reg, pp);
2917 POSTING_READ(pp_ctrl_reg);
2920 intel_dp->last_backlight_off = jiffies;
2921 edp_wait_backlight_off(intel_dp);
2924 /* Disable backlight PP control and backlight PWM. */
2925 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2927 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2929 if (!intel_dp_is_edp(intel_dp))
2932 DRM_DEBUG_KMS("\n");
2934 _intel_edp_backlight_off(intel_dp);
2935 intel_panel_disable_backlight(old_conn_state);
2939 * Hook for controlling the panel power control backlight through the bl_power
2940 * sysfs attribute. Take care to handle multiple calls.
2942 static void intel_edp_backlight_power(struct intel_connector *connector,
2945 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2946 intel_wakeref_t wakeref;
2950 with_pps_lock(intel_dp, wakeref)
2951 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2952 if (is_enabled == enable)
2955 DRM_DEBUG_KMS("panel power control backlight %s\n",
2956 enable ? "enable" : "disable");
2959 _intel_edp_backlight_on(intel_dp);
2961 _intel_edp_backlight_off(intel_dp);
2964 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2967 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2968 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2970 I915_STATE_WARN(cur_state != state,
2971 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
2972 dig_port->base.base.base.id, dig_port->base.base.name,
2973 onoff(state), onoff(cur_state));
2975 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2977 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2979 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2981 I915_STATE_WARN(cur_state != state,
2982 "eDP PLL state assertion failure (expected %s, current %s)\n",
2983 onoff(state), onoff(cur_state));
2985 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2986 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2988 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2989 const struct intel_crtc_state *pipe_config)
2991 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2994 assert_pipe_disabled(dev_priv, crtc->pipe);
2995 assert_dp_port_disabled(intel_dp);
2996 assert_edp_pll_disabled(dev_priv);
2998 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2999 pipe_config->port_clock);
3001 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3003 if (pipe_config->port_clock == 162000)
3004 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3006 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3008 I915_WRITE(DP_A, intel_dp->DP);
3013 * [DevILK] Work around required when enabling DP PLL
3014 * while a pipe is enabled going to FDI:
3015 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3016 * 2. Program DP PLL enable
3018 if (IS_GEN(dev_priv, 5))
3019 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3021 intel_dp->DP |= DP_PLL_ENABLE;
3023 I915_WRITE(DP_A, intel_dp->DP);
3028 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
3029 const struct intel_crtc_state *old_crtc_state)
3031 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3032 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3034 assert_pipe_disabled(dev_priv, crtc->pipe);
3035 assert_dp_port_disabled(intel_dp);
3036 assert_edp_pll_enabled(dev_priv);
3038 DRM_DEBUG_KMS("disabling eDP PLL\n");
3040 intel_dp->DP &= ~DP_PLL_ENABLE;
3042 I915_WRITE(DP_A, intel_dp->DP);
3047 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3050 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3051 * be capable of signalling downstream hpd with a long pulse.
3052 * Whether or not that means D3 is safe to use is not clear,
3053 * but let's assume so until proven otherwise.
3055 * FIXME should really check all downstream ports...
3057 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3058 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3059 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3062 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3063 const struct intel_crtc_state *crtc_state,
3068 if (!crtc_state->dsc_params.compression_enable)
3071 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3072 enable ? DP_DECOMPRESSION_EN : 0);
3074 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3075 enable ? "enable" : "disable");
3078 /* If the sink supports it, try to set the power state appropriately */
3079 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3083 /* Should have a valid DPCD by this point */
3084 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3087 if (mode != DRM_MODE_DPMS_ON) {
3088 if (downstream_hpd_needs_d0(intel_dp))
3091 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3094 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3097 * When turning on, we need to retry for 1ms to give the sink
3100 for (i = 0; i < 3; i++) {
3101 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3108 if (ret == 1 && lspcon->active)
3109 lspcon_wait_pcon_mode(lspcon);
3113 DRM_DEBUG_KMS("failed to %s sink power state\n",
3114 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3117 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3118 enum port port, enum pipe *pipe)
3122 for_each_pipe(dev_priv, p) {
3123 u32 val = I915_READ(TRANS_DP_CTL(p));
3125 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3131 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3133 /* must initialize pipe to something for the asserts */
3139 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3140 i915_reg_t dp_reg, enum port port,
3146 val = I915_READ(dp_reg);
3148 ret = val & DP_PORT_EN;
3150 /* asserts want to know the pipe even if the port is disabled */
3151 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3152 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3153 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3154 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3155 else if (IS_CHERRYVIEW(dev_priv))
3156 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3158 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3163 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3167 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3168 intel_wakeref_t wakeref;
3171 wakeref = intel_display_power_get_if_enabled(dev_priv,
3172 encoder->power_domain);
3176 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3177 encoder->port, pipe);
3179 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3184 static void intel_dp_get_config(struct intel_encoder *encoder,
3185 struct intel_crtc_state *pipe_config)
3187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3188 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3190 enum port port = encoder->port;
3191 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3193 if (encoder->type == INTEL_OUTPUT_EDP)
3194 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3196 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3198 tmp = I915_READ(intel_dp->output_reg);
3200 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3202 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3203 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3205 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3206 flags |= DRM_MODE_FLAG_PHSYNC;
3208 flags |= DRM_MODE_FLAG_NHSYNC;
3210 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3211 flags |= DRM_MODE_FLAG_PVSYNC;
3213 flags |= DRM_MODE_FLAG_NVSYNC;
3215 if (tmp & DP_SYNC_HS_HIGH)
3216 flags |= DRM_MODE_FLAG_PHSYNC;
3218 flags |= DRM_MODE_FLAG_NHSYNC;
3220 if (tmp & DP_SYNC_VS_HIGH)
3221 flags |= DRM_MODE_FLAG_PVSYNC;
3223 flags |= DRM_MODE_FLAG_NVSYNC;
3226 pipe_config->base.adjusted_mode.flags |= flags;
3228 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3229 pipe_config->limited_color_range = true;
3231 pipe_config->lane_count =
3232 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3234 intel_dp_get_m_n(crtc, pipe_config);
3236 if (port == PORT_A) {
3237 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3238 pipe_config->port_clock = 162000;
3240 pipe_config->port_clock = 270000;
3243 pipe_config->base.adjusted_mode.crtc_clock =
3244 intel_dotclock_calculate(pipe_config->port_clock,
3245 &pipe_config->dp_m_n);
3247 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3248 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3250 * This is a big fat ugly hack.
3252 * Some machines in UEFI boot mode provide us a VBT that has 18
3253 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3254 * unknown we fail to light up. Yet the same BIOS boots up with
3255 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3256 * max, not what it tells us to use.
3258 * Note: This will still be broken if the eDP panel is not lit
3259 * up by the BIOS, and thus we can't get the mode at module
3262 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3263 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3264 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3268 static void intel_disable_dp(struct intel_encoder *encoder,
3269 const struct intel_crtc_state *old_crtc_state,
3270 const struct drm_connector_state *old_conn_state)
3272 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3274 intel_dp->link_trained = false;
3276 if (old_crtc_state->has_audio)
3277 intel_audio_codec_disable(encoder,
3278 old_crtc_state, old_conn_state);
3280 /* Make sure the panel is off before trying to change the mode. But also
3281 * ensure that we have vdd while we switch off the panel. */
3282 intel_edp_panel_vdd_on(intel_dp);
3283 intel_edp_backlight_off(old_conn_state);
3284 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3285 intel_edp_panel_off(intel_dp);
3288 static void g4x_disable_dp(struct intel_encoder *encoder,
3289 const struct intel_crtc_state *old_crtc_state,
3290 const struct drm_connector_state *old_conn_state)
3292 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3295 static void vlv_disable_dp(struct intel_encoder *encoder,
3296 const struct intel_crtc_state *old_crtc_state,
3297 const struct drm_connector_state *old_conn_state)
3299 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3302 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3303 const struct intel_crtc_state *old_crtc_state,
3304 const struct drm_connector_state *old_conn_state)
3306 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3307 enum port port = encoder->port;
3310 * Bspec does not list a specific disable sequence for g4x DP.
3311 * Follow the ilk+ sequence (disable pipe before the port) for
3312 * g4x DP as it does not suffer from underruns like the normal
3313 * g4x modeset sequence (disable pipe after the port).
3315 intel_dp_link_down(encoder, old_crtc_state);
3317 /* Only ilk+ has port A */
3319 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3322 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3323 const struct intel_crtc_state *old_crtc_state,
3324 const struct drm_connector_state *old_conn_state)
3326 intel_dp_link_down(encoder, old_crtc_state);
3329 static void chv_post_disable_dp(struct intel_encoder *encoder,
3330 const struct intel_crtc_state *old_crtc_state,
3331 const struct drm_connector_state *old_conn_state)
3333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3335 intel_dp_link_down(encoder, old_crtc_state);
3337 vlv_dpio_get(dev_priv);
3339 /* Assert data lane reset */
3340 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3342 vlv_dpio_put(dev_priv);
3346 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3350 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3352 enum port port = intel_dig_port->base.port;
3353 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3355 if (dp_train_pat & train_pat_mask)
3356 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3357 dp_train_pat & train_pat_mask);
3359 if (HAS_DDI(dev_priv)) {
3360 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3362 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3363 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3365 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3367 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3368 switch (dp_train_pat & train_pat_mask) {
3369 case DP_TRAINING_PATTERN_DISABLE:
3370 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3373 case DP_TRAINING_PATTERN_1:
3374 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3376 case DP_TRAINING_PATTERN_2:
3377 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3379 case DP_TRAINING_PATTERN_3:
3380 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3382 case DP_TRAINING_PATTERN_4:
3383 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3386 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3388 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3389 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3390 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3392 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3393 case DP_TRAINING_PATTERN_DISABLE:
3394 *DP |= DP_LINK_TRAIN_OFF_CPT;
3396 case DP_TRAINING_PATTERN_1:
3397 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3399 case DP_TRAINING_PATTERN_2:
3400 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3402 case DP_TRAINING_PATTERN_3:
3403 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3404 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3409 *DP &= ~DP_LINK_TRAIN_MASK;
3411 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3412 case DP_TRAINING_PATTERN_DISABLE:
3413 *DP |= DP_LINK_TRAIN_OFF;
3415 case DP_TRAINING_PATTERN_1:
3416 *DP |= DP_LINK_TRAIN_PAT_1;
3418 case DP_TRAINING_PATTERN_2:
3419 *DP |= DP_LINK_TRAIN_PAT_2;
3421 case DP_TRAINING_PATTERN_3:
3422 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3423 *DP |= DP_LINK_TRAIN_PAT_2;
3429 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3430 const struct intel_crtc_state *old_crtc_state)
3432 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3434 /* enable with pattern 1 (as per spec) */
3436 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3439 * Magic for VLV/CHV. We _must_ first set up the register
3440 * without actually enabling the port, and then do another
3441 * write to enable the port. Otherwise link training will
3442 * fail when the power sequencer is freshly used for this port.
3444 intel_dp->DP |= DP_PORT_EN;
3445 if (old_crtc_state->has_audio)
3446 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3448 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3449 POSTING_READ(intel_dp->output_reg);
3452 static void intel_enable_dp(struct intel_encoder *encoder,
3453 const struct intel_crtc_state *pipe_config,
3454 const struct drm_connector_state *conn_state)
3456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3457 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3458 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3459 u32 dp_reg = I915_READ(intel_dp->output_reg);
3460 enum pipe pipe = crtc->pipe;
3461 intel_wakeref_t wakeref;
3463 if (WARN_ON(dp_reg & DP_PORT_EN))
3466 with_pps_lock(intel_dp, wakeref) {
3467 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3468 vlv_init_panel_power_sequencer(encoder, pipe_config);
3470 intel_dp_enable_port(intel_dp, pipe_config);
3472 edp_panel_vdd_on(intel_dp);
3473 edp_panel_on(intel_dp);
3474 edp_panel_vdd_off(intel_dp, true);
3477 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3478 unsigned int lane_mask = 0x0;
3480 if (IS_CHERRYVIEW(dev_priv))
3481 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3483 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3487 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3488 intel_dp_start_link_train(intel_dp);
3489 intel_dp_stop_link_train(intel_dp);
3491 if (pipe_config->has_audio) {
3492 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3494 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3498 static void g4x_enable_dp(struct intel_encoder *encoder,
3499 const struct intel_crtc_state *pipe_config,
3500 const struct drm_connector_state *conn_state)
3502 intel_enable_dp(encoder, pipe_config, conn_state);
3503 intel_edp_backlight_on(pipe_config, conn_state);
3506 static void vlv_enable_dp(struct intel_encoder *encoder,
3507 const struct intel_crtc_state *pipe_config,
3508 const struct drm_connector_state *conn_state)
3510 intel_edp_backlight_on(pipe_config, conn_state);
3513 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3514 const struct intel_crtc_state *pipe_config,
3515 const struct drm_connector_state *conn_state)
3517 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3518 enum port port = encoder->port;
3520 intel_dp_prepare(encoder, pipe_config);
3522 /* Only ilk+ has port A */
3524 ironlake_edp_pll_on(intel_dp, pipe_config);
3527 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3529 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3530 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3531 enum pipe pipe = intel_dp->pps_pipe;
3532 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3534 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3536 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3539 edp_panel_vdd_off_sync(intel_dp);
3542 * VLV seems to get confused when multiple power sequencers
3543 * have the same port selected (even if only one has power/vdd
3544 * enabled). The failure manifests as vlv_wait_port_ready() failing
3545 * CHV on the other hand doesn't seem to mind having the same port
3546 * selected in multiple power sequencers, but let's clear the
3547 * port select always when logically disconnecting a power sequencer
3550 DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3551 pipe_name(pipe), intel_dig_port->base.base.base.id,
3552 intel_dig_port->base.base.name);
3553 I915_WRITE(pp_on_reg, 0);
3554 POSTING_READ(pp_on_reg);
3556 intel_dp->pps_pipe = INVALID_PIPE;
3559 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3562 struct intel_encoder *encoder;
3564 lockdep_assert_held(&dev_priv->pps_mutex);
3566 for_each_intel_dp(&dev_priv->drm, encoder) {
3567 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3569 WARN(intel_dp->active_pipe == pipe,
3570 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3571 pipe_name(pipe), encoder->base.base.id,
3572 encoder->base.name);
3574 if (intel_dp->pps_pipe != pipe)
3577 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3578 pipe_name(pipe), encoder->base.base.id,
3579 encoder->base.name);
3581 /* make sure vdd is off before we steal it */
3582 vlv_detach_power_sequencer(intel_dp);
3586 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3587 const struct intel_crtc_state *crtc_state)
3589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3590 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3591 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3593 lockdep_assert_held(&dev_priv->pps_mutex);
3595 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3597 if (intel_dp->pps_pipe != INVALID_PIPE &&
3598 intel_dp->pps_pipe != crtc->pipe) {
3600 * If another power sequencer was being used on this
3601 * port previously make sure to turn off vdd there while
3602 * we still have control of it.
3604 vlv_detach_power_sequencer(intel_dp);
3608 * We may be stealing the power
3609 * sequencer from another port.
3611 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3613 intel_dp->active_pipe = crtc->pipe;
3615 if (!intel_dp_is_edp(intel_dp))
3618 /* now it's all ours */
3619 intel_dp->pps_pipe = crtc->pipe;
3621 DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3622 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3623 encoder->base.name);
3625 /* init power sequencer on this pipe and port */
3626 intel_dp_init_panel_power_sequencer(intel_dp);
3627 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3630 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3631 const struct intel_crtc_state *pipe_config,
3632 const struct drm_connector_state *conn_state)
3634 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3636 intel_enable_dp(encoder, pipe_config, conn_state);
3639 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3640 const struct intel_crtc_state *pipe_config,
3641 const struct drm_connector_state *conn_state)
3643 intel_dp_prepare(encoder, pipe_config);
3645 vlv_phy_pre_pll_enable(encoder, pipe_config);
3648 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3649 const struct intel_crtc_state *pipe_config,
3650 const struct drm_connector_state *conn_state)
3652 chv_phy_pre_encoder_enable(encoder, pipe_config);
3654 intel_enable_dp(encoder, pipe_config, conn_state);
3656 /* Second common lane will stay alive on its own now */
3657 chv_phy_release_cl2_override(encoder);
3660 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3661 const struct intel_crtc_state *pipe_config,
3662 const struct drm_connector_state *conn_state)
3664 intel_dp_prepare(encoder, pipe_config);
3666 chv_phy_pre_pll_enable(encoder, pipe_config);
3669 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3670 const struct intel_crtc_state *old_crtc_state,
3671 const struct drm_connector_state *old_conn_state)
3673 chv_phy_post_pll_disable(encoder, old_crtc_state);
3677 * Fetch AUX CH registers 0x202 - 0x207 which contain
3678 * link status information
3681 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3683 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3684 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3687 /* These are source-specific values. */
3689 intel_dp_voltage_max(struct intel_dp *intel_dp)
3691 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3692 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3693 enum port port = encoder->port;
3695 if (HAS_DDI(dev_priv))
3696 return intel_ddi_dp_voltage_max(encoder);
3697 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3698 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3699 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3700 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3701 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3702 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3704 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3708 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3710 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3711 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3712 enum port port = encoder->port;
3714 if (HAS_DDI(dev_priv)) {
3715 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3716 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3717 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3718 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3719 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3720 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3721 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3722 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3723 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3724 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3726 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3728 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3729 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3730 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3731 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3733 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3734 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3736 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3739 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3740 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3741 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3742 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3743 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3745 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3748 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3753 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3755 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3756 unsigned long demph_reg_value, preemph_reg_value,
3757 uniqtranscale_reg_value;
3758 u8 train_set = intel_dp->train_set[0];
3760 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3761 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3762 preemph_reg_value = 0x0004000;
3763 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3764 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3765 demph_reg_value = 0x2B405555;
3766 uniqtranscale_reg_value = 0x552AB83A;
3768 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3769 demph_reg_value = 0x2B404040;
3770 uniqtranscale_reg_value = 0x5548B83A;
3772 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3773 demph_reg_value = 0x2B245555;
3774 uniqtranscale_reg_value = 0x5560B83A;
3776 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3777 demph_reg_value = 0x2B405555;
3778 uniqtranscale_reg_value = 0x5598DA3A;
3784 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3785 preemph_reg_value = 0x0002000;
3786 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3787 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3788 demph_reg_value = 0x2B404040;
3789 uniqtranscale_reg_value = 0x5552B83A;
3791 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3792 demph_reg_value = 0x2B404848;
3793 uniqtranscale_reg_value = 0x5580B83A;
3795 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3796 demph_reg_value = 0x2B404040;
3797 uniqtranscale_reg_value = 0x55ADDA3A;
3803 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3804 preemph_reg_value = 0x0000000;
3805 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3806 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3807 demph_reg_value = 0x2B305555;
3808 uniqtranscale_reg_value = 0x5570B83A;
3810 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3811 demph_reg_value = 0x2B2B4040;
3812 uniqtranscale_reg_value = 0x55ADDA3A;
3818 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3819 preemph_reg_value = 0x0006000;
3820 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3821 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3822 demph_reg_value = 0x1B405555;
3823 uniqtranscale_reg_value = 0x55ADDA3A;
3833 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3834 uniqtranscale_reg_value, 0);
3839 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3841 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3842 u32 deemph_reg_value, margin_reg_value;
3843 bool uniq_trans_scale = false;
3844 u8 train_set = intel_dp->train_set[0];
3846 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3847 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3848 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3850 deemph_reg_value = 128;
3851 margin_reg_value = 52;
3853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3854 deemph_reg_value = 128;
3855 margin_reg_value = 77;
3857 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3858 deemph_reg_value = 128;
3859 margin_reg_value = 102;
3861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3862 deemph_reg_value = 128;
3863 margin_reg_value = 154;
3864 uniq_trans_scale = true;
3870 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3871 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3873 deemph_reg_value = 85;
3874 margin_reg_value = 78;
3876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3877 deemph_reg_value = 85;
3878 margin_reg_value = 116;
3880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3881 deemph_reg_value = 85;
3882 margin_reg_value = 154;
3888 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3889 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3891 deemph_reg_value = 64;
3892 margin_reg_value = 104;
3894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3895 deemph_reg_value = 64;
3896 margin_reg_value = 154;
3902 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3903 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3905 deemph_reg_value = 43;
3906 margin_reg_value = 154;
3916 chv_set_phy_signal_level(encoder, deemph_reg_value,
3917 margin_reg_value, uniq_trans_scale);
3923 g4x_signal_levels(u8 train_set)
3925 u32 signal_levels = 0;
3927 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3930 signal_levels |= DP_VOLTAGE_0_4;
3932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3933 signal_levels |= DP_VOLTAGE_0_6;
3935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3936 signal_levels |= DP_VOLTAGE_0_8;
3938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3939 signal_levels |= DP_VOLTAGE_1_2;
3942 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3943 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3945 signal_levels |= DP_PRE_EMPHASIS_0;
3947 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3948 signal_levels |= DP_PRE_EMPHASIS_3_5;
3950 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3951 signal_levels |= DP_PRE_EMPHASIS_6;
3953 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3954 signal_levels |= DP_PRE_EMPHASIS_9_5;
3957 return signal_levels;
3960 /* SNB CPU eDP voltage swing and pre-emphasis control */
3962 snb_cpu_edp_signal_levels(u8 train_set)
3964 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3965 DP_TRAIN_PRE_EMPHASIS_MASK);
3966 switch (signal_levels) {
3967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3969 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3971 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3974 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3977 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3980 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3982 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3983 "0x%x\n", signal_levels);
3984 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3988 /* IVB CPU eDP voltage swing and pre-emphasis control */
3990 ivb_cpu_edp_signal_levels(u8 train_set)
3992 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3993 DP_TRAIN_PRE_EMPHASIS_MASK);
3994 switch (signal_levels) {
3995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3996 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3998 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4000 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4002 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4003 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4005 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4008 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4010 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4013 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4014 "0x%x\n", signal_levels);
4015 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4020 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4022 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4023 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4024 enum port port = intel_dig_port->base.port;
4025 u32 signal_levels, mask = 0;
4026 u8 train_set = intel_dp->train_set[0];
4028 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4029 signal_levels = bxt_signal_levels(intel_dp);
4030 } else if (HAS_DDI(dev_priv)) {
4031 signal_levels = ddi_signal_levels(intel_dp);
4032 mask = DDI_BUF_EMP_MASK;
4033 } else if (IS_CHERRYVIEW(dev_priv)) {
4034 signal_levels = chv_signal_levels(intel_dp);
4035 } else if (IS_VALLEYVIEW(dev_priv)) {
4036 signal_levels = vlv_signal_levels(intel_dp);
4037 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4038 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4039 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4040 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4041 signal_levels = snb_cpu_edp_signal_levels(train_set);
4042 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4044 signal_levels = g4x_signal_levels(train_set);
4045 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4049 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4051 DRM_DEBUG_KMS("Using vswing level %d\n",
4052 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4053 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4054 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4055 DP_TRAIN_PRE_EMPHASIS_SHIFT);
4057 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4059 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4060 POSTING_READ(intel_dp->output_reg);
4064 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4067 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4068 struct drm_i915_private *dev_priv =
4069 to_i915(intel_dig_port->base.base.dev);
4071 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4073 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4074 POSTING_READ(intel_dp->output_reg);
4077 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4079 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4080 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4081 enum port port = intel_dig_port->base.port;
4084 if (!HAS_DDI(dev_priv))
4087 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4088 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4089 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4090 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4093 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4094 * reason we need to set idle transmission mode is to work around a HW
4095 * issue where we enable the pipe while not in idle link-training mode.
4096 * In this case there is requirement to wait for a minimum number of
4097 * idle patterns to be sent.
4099 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4102 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4103 DP_TP_STATUS_IDLE_DONE, 1))
4104 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4108 intel_dp_link_down(struct intel_encoder *encoder,
4109 const struct intel_crtc_state *old_crtc_state)
4111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4112 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4113 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4114 enum port port = encoder->port;
4115 u32 DP = intel_dp->DP;
4117 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4120 DRM_DEBUG_KMS("\n");
4122 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4123 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4124 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4125 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4127 DP &= ~DP_LINK_TRAIN_MASK;
4128 DP |= DP_LINK_TRAIN_PAT_IDLE;
4130 I915_WRITE(intel_dp->output_reg, DP);
4131 POSTING_READ(intel_dp->output_reg);
4133 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4134 I915_WRITE(intel_dp->output_reg, DP);
4135 POSTING_READ(intel_dp->output_reg);
4138 * HW workaround for IBX, we need to move the port
4139 * to transcoder A after disabling it to allow the
4140 * matching HDMI port to be enabled on transcoder A.
4142 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4144 * We get CPU/PCH FIFO underruns on the other pipe when
4145 * doing the workaround. Sweep them under the rug.
4147 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4148 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4150 /* always enable with pattern 1 (as per spec) */
4151 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4152 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4153 DP_LINK_TRAIN_PAT_1;
4154 I915_WRITE(intel_dp->output_reg, DP);
4155 POSTING_READ(intel_dp->output_reg);
4158 I915_WRITE(intel_dp->output_reg, DP);
4159 POSTING_READ(intel_dp->output_reg);
4161 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4162 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4163 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4166 msleep(intel_dp->panel_power_down_delay);
4170 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4171 intel_wakeref_t wakeref;
4173 with_pps_lock(intel_dp, wakeref)
4174 intel_dp->active_pipe = INVALID_PIPE;
4179 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4184 * Prior to DP1.3 the bit represented by
4185 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4186 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4187 * the true capability of the panel. The only way to check is to
4188 * then compare 0000h and 2200h.
4190 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4191 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4194 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4195 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4196 DRM_ERROR("DPCD failed read at extended capabilities\n");
4200 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4201 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4205 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4208 DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4209 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4211 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4215 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4217 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4218 sizeof(intel_dp->dpcd)) < 0)
4219 return false; /* aux transfer failed */
4221 intel_dp_extended_receiver_capabilities(intel_dp);
4223 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4225 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4228 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4232 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4235 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4238 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4241 * Clear the cached register set to avoid using stale values
4242 * for the sinks that do not support DSC.
4244 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4246 /* Clear fec_capable to avoid using stale values */
4247 intel_dp->fec_capable = 0;
4249 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4250 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4251 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4252 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4254 sizeof(intel_dp->dsc_dpcd)) < 0)
4255 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4258 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4259 (int)sizeof(intel_dp->dsc_dpcd),
4260 intel_dp->dsc_dpcd);
4262 /* FEC is supported only on DP 1.4 */
4263 if (!intel_dp_is_edp(intel_dp) &&
4264 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4265 &intel_dp->fec_capable) < 0)
4266 DRM_ERROR("Failed to read FEC DPCD register\n");
4268 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4273 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4275 struct drm_i915_private *dev_priv =
4276 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4278 /* this function is meant to be called only once */
4279 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4281 if (!intel_dp_read_dpcd(intel_dp))
4284 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4285 drm_dp_is_branch(intel_dp->dpcd));
4288 * Read the eDP display control registers.
4290 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4291 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4292 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4293 * method). The display control registers should read zero if they're
4294 * not supported anyway.
4296 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4297 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4298 sizeof(intel_dp->edp_dpcd))
4299 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4300 intel_dp->edp_dpcd);
4303 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4304 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4306 intel_psr_init_dpcd(intel_dp);
4308 /* Read the eDP 1.4+ supported link rates. */
4309 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4310 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4313 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4314 sink_rates, sizeof(sink_rates));
4316 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4317 int val = le16_to_cpu(sink_rates[i]);
4322 /* Value read multiplied by 200kHz gives the per-lane
4323 * link rate in kHz. The source rates are, however,
4324 * stored in terms of LS_Clk kHz. The full conversion
4325 * back to symbols is
4326 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4328 intel_dp->sink_rates[i] = (val * 200) / 10;
4330 intel_dp->num_sink_rates = i;
4334 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4335 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4337 if (intel_dp->num_sink_rates)
4338 intel_dp->use_rate_select = true;
4340 intel_dp_set_sink_rates(intel_dp);
4342 intel_dp_set_common_rates(intel_dp);
4344 /* Read the eDP DSC DPCD registers */
4345 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4346 intel_dp_get_dsc_sink_cap(intel_dp);
4353 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4355 if (!intel_dp_read_dpcd(intel_dp))
4359 * Don't clobber cached eDP rates. Also skip re-reading
4360 * the OUI/ID since we know it won't change.
4362 if (!intel_dp_is_edp(intel_dp)) {
4363 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4364 drm_dp_is_branch(intel_dp->dpcd));
4366 intel_dp_set_sink_rates(intel_dp);
4367 intel_dp_set_common_rates(intel_dp);
4371 * Some eDP panels do not set a valid value for sink count, that is why
4372 * it don't care about read it here and in intel_edp_init_dpcd().
4374 if (!intel_dp_is_edp(intel_dp) &&
4375 !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4379 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4384 * Sink count can change between short pulse hpd hence
4385 * a member variable in intel_dp will track any changes
4386 * between short pulse interrupts.
4388 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4391 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4392 * a dongle is present but no display. Unless we require to know
4393 * if a dongle is present or not, we don't need to update
4394 * downstream port information. So, an early return here saves
4395 * time from performing other operations which are not required.
4397 if (!intel_dp->sink_count)
4401 if (!drm_dp_is_branch(intel_dp->dpcd))
4402 return true; /* native DP sink */
4404 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4405 return true; /* no per-port downstream info */
4407 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4408 intel_dp->downstream_ports,
4409 DP_MAX_DOWNSTREAM_PORTS) < 0)
4410 return false; /* downstream port status fetch failed */
4416 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4420 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4423 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4426 return mstm_cap & DP_MST_CAP;
4430 intel_dp_can_mst(struct intel_dp *intel_dp)
4432 return i915_modparams.enable_dp_mst &&
4433 intel_dp->can_mst &&
4434 intel_dp_sink_can_mst(intel_dp);
4438 intel_dp_configure_mst(struct intel_dp *intel_dp)
4440 struct intel_encoder *encoder =
4441 &dp_to_dig_port(intel_dp)->base;
4442 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4444 DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support? port: %s, sink: %s, modparam: %s\n",
4445 encoder->base.base.id, encoder->base.name,
4446 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4447 yesno(i915_modparams.enable_dp_mst));
4449 if (!intel_dp->can_mst)
4452 intel_dp->is_mst = sink_can_mst &&
4453 i915_modparams.enable_dp_mst;
4455 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4460 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4462 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4463 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4468 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
4469 const struct intel_crtc_state *crtc_state)
4471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4472 struct dp_sdp vsc_sdp = {};
4474 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4475 vsc_sdp.sdp_header.HB0 = 0;
4476 vsc_sdp.sdp_header.HB1 = 0x7;
4479 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4480 * Colorimetry Format indication.
4482 vsc_sdp.sdp_header.HB2 = 0x5;
4485 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4486 * Colorimetry Format indication (HB2 = 05h).
4488 vsc_sdp.sdp_header.HB3 = 0x13;
4491 * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
4492 * DB16[3:0] DP 1.4a spec, Table 2-120
4494 vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
4495 /* RGB->YCBCR color conversion uses the BT.709 color space. */
4496 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4499 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4500 * the following Component Bit Depth values are defined:
4506 switch (crtc_state->pipe_bpp) {
4508 vsc_sdp.db[17] = 0x1;
4510 case 30: /* 10bpc */
4511 vsc_sdp.db[17] = 0x2;
4513 case 36: /* 12bpc */
4514 vsc_sdp.db[17] = 0x3;
4516 case 48: /* 16bpc */
4517 vsc_sdp.db[17] = 0x4;
4520 MISSING_CASE(crtc_state->pipe_bpp);
4525 * Dynamic Range (Bit 7)
4526 * 0 = VESA range, 1 = CTA range.
4527 * all YCbCr are always limited range
4529 vsc_sdp.db[17] |= 0x80;
4532 * Content Type (Bits 2:0)
4533 * 000b = Not defined.
4538 * All other values are RESERVED.
4539 * Note: See CTA-861-G for the definition and expected
4540 * processing by a stream sink for the above contect types.
4544 intel_dig_port->write_infoframe(&intel_dig_port->base,
4545 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4548 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
4549 const struct intel_crtc_state *crtc_state)
4551 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
4554 intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
4557 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4561 u8 test_lane_count, test_link_bw;
4565 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4566 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4570 DRM_DEBUG_KMS("Lane count read failed\n");
4573 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4575 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4578 DRM_DEBUG_KMS("Link Rate read failed\n");
4581 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4583 /* Validate the requested link rate and lane count */
4584 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4588 intel_dp->compliance.test_lane_count = test_lane_count;
4589 intel_dp->compliance.test_link_rate = test_link_rate;
4594 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4598 __be16 h_width, v_height;
4601 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4602 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4605 DRM_DEBUG_KMS("Test pattern read failed\n");
4608 if (test_pattern != DP_COLOR_RAMP)
4611 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4614 DRM_DEBUG_KMS("H Width read failed\n");
4618 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4621 DRM_DEBUG_KMS("V Height read failed\n");
4625 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4628 DRM_DEBUG_KMS("TEST MISC read failed\n");
4631 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4633 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4635 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4636 case DP_TEST_BIT_DEPTH_6:
4637 intel_dp->compliance.test_data.bpc = 6;
4639 case DP_TEST_BIT_DEPTH_8:
4640 intel_dp->compliance.test_data.bpc = 8;
4646 intel_dp->compliance.test_data.video_pattern = test_pattern;
4647 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4648 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4649 /* Set test active flag here so userspace doesn't interrupt things */
4650 intel_dp->compliance.test_active = 1;
4655 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4657 u8 test_result = DP_TEST_ACK;
4658 struct intel_connector *intel_connector = intel_dp->attached_connector;
4659 struct drm_connector *connector = &intel_connector->base;
4661 if (intel_connector->detect_edid == NULL ||
4662 connector->edid_corrupt ||
4663 intel_dp->aux.i2c_defer_count > 6) {
4664 /* Check EDID read for NACKs, DEFERs and corruption
4665 * (DP CTS 1.2 Core r1.1)
4666 * 4.2.2.4 : Failed EDID read, I2C_NAK
4667 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4668 * 4.2.2.6 : EDID corruption detected
4669 * Use failsafe mode for all cases
4671 if (intel_dp->aux.i2c_nack_count > 0 ||
4672 intel_dp->aux.i2c_defer_count > 0)
4673 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4674 intel_dp->aux.i2c_nack_count,
4675 intel_dp->aux.i2c_defer_count);
4676 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4678 struct edid *block = intel_connector->detect_edid;
4680 /* We have to write the checksum
4681 * of the last block read
4683 block += intel_connector->detect_edid->extensions;
4685 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4686 block->checksum) <= 0)
4687 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4689 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4690 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4693 /* Set test active flag here so userspace doesn't interrupt things */
4694 intel_dp->compliance.test_active = 1;
4699 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4701 u8 test_result = DP_TEST_NAK;
4705 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4707 u8 response = DP_TEST_NAK;
4711 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4713 DRM_DEBUG_KMS("Could not read test request from sink\n");
4718 case DP_TEST_LINK_TRAINING:
4719 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4720 response = intel_dp_autotest_link_training(intel_dp);
4722 case DP_TEST_LINK_VIDEO_PATTERN:
4723 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4724 response = intel_dp_autotest_video_pattern(intel_dp);
4726 case DP_TEST_LINK_EDID_READ:
4727 DRM_DEBUG_KMS("EDID test requested\n");
4728 response = intel_dp_autotest_edid(intel_dp);
4730 case DP_TEST_LINK_PHY_TEST_PATTERN:
4731 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4732 response = intel_dp_autotest_phy_pattern(intel_dp);
4735 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4739 if (response & DP_TEST_ACK)
4740 intel_dp->compliance.test_type = request;
4743 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4745 DRM_DEBUG_KMS("Could not write test response to sink\n");
4749 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4753 if (intel_dp->is_mst) {
4754 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4759 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4760 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4764 /* check link status - esi[10] = 0x200c */
4765 if (intel_dp->active_mst_links > 0 &&
4766 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4767 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4768 intel_dp_start_link_train(intel_dp);
4769 intel_dp_stop_link_train(intel_dp);
4772 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4773 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4776 for (retry = 0; retry < 3; retry++) {
4778 wret = drm_dp_dpcd_write(&intel_dp->aux,
4779 DP_SINK_COUNT_ESI+1,
4786 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4788 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4796 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4797 intel_dp->is_mst = false;
4798 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4806 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4808 u8 link_status[DP_LINK_STATUS_SIZE];
4810 if (!intel_dp->link_trained)
4814 * While PSR source HW is enabled, it will control main-link sending
4815 * frames, enabling and disabling it so trying to do a retrain will fail
4816 * as the link would or not be on or it could mix training patterns
4817 * and frame data at the same time causing retrain to fail.
4818 * Also when exiting PSR, HW will retrain the link anyways fixing
4819 * any link status error.
4821 if (intel_psr_enabled(intel_dp))
4824 if (!intel_dp_get_link_status(intel_dp, link_status))
4828 * Validate the cached values of intel_dp->link_rate and
4829 * intel_dp->lane_count before attempting to retrain.
4831 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4832 intel_dp->lane_count))
4835 /* Retrain if Channel EQ or CR not ok */
4836 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4839 int intel_dp_retrain_link(struct intel_encoder *encoder,
4840 struct drm_modeset_acquire_ctx *ctx)
4842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4844 struct intel_connector *connector = intel_dp->attached_connector;
4845 struct drm_connector_state *conn_state;
4846 struct intel_crtc_state *crtc_state;
4847 struct intel_crtc *crtc;
4850 /* FIXME handle the MST connectors as well */
4852 if (!connector || connector->base.status != connector_status_connected)
4855 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4860 conn_state = connector->base.state;
4862 crtc = to_intel_crtc(conn_state->crtc);
4866 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4870 crtc_state = to_intel_crtc_state(crtc->base.state);
4872 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4874 if (!crtc_state->base.active)
4877 if (conn_state->commit &&
4878 !try_wait_for_completion(&conn_state->commit->hw_done))
4881 if (!intel_dp_needs_link_retrain(intel_dp))
4884 /* Suppress underruns caused by re-training */
4885 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4886 if (crtc_state->has_pch_encoder)
4887 intel_set_pch_fifo_underrun_reporting(dev_priv,
4888 intel_crtc_pch_transcoder(crtc), false);
4890 intel_dp_start_link_train(intel_dp);
4891 intel_dp_stop_link_train(intel_dp);
4893 /* Keep underrun reporting disabled until things are stable */
4894 intel_wait_for_vblank(dev_priv, crtc->pipe);
4896 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4897 if (crtc_state->has_pch_encoder)
4898 intel_set_pch_fifo_underrun_reporting(dev_priv,
4899 intel_crtc_pch_transcoder(crtc), true);
4905 * If display is now connected check links status,
4906 * there has been known issues of link loss triggering
4909 * Some sinks (eg. ASUS PB287Q) seem to perform some
4910 * weird HPD ping pong during modesets. So we can apparently
4911 * end up with HPD going low during a modeset, and then
4912 * going back up soon after. And once that happens we must
4913 * retrain the link to get a picture. That's in case no
4914 * userspace component reacted to intermittent HPD dip.
4916 static enum intel_hotplug_state
4917 intel_dp_hotplug(struct intel_encoder *encoder,
4918 struct intel_connector *connector,
4921 struct drm_modeset_acquire_ctx ctx;
4922 enum intel_hotplug_state state;
4925 state = intel_encoder_hotplug(encoder, connector, irq_received);
4927 drm_modeset_acquire_init(&ctx, 0);
4930 ret = intel_dp_retrain_link(encoder, &ctx);
4932 if (ret == -EDEADLK) {
4933 drm_modeset_backoff(&ctx);
4940 drm_modeset_drop_locks(&ctx);
4941 drm_modeset_acquire_fini(&ctx);
4942 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4945 * Keeping it consistent with intel_ddi_hotplug() and
4946 * intel_hdmi_hotplug().
4948 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
4949 state = INTEL_HOTPLUG_RETRY;
4954 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4958 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4961 if (drm_dp_dpcd_readb(&intel_dp->aux,
4962 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4965 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4967 if (val & DP_AUTOMATED_TEST_REQUEST)
4968 intel_dp_handle_test_request(intel_dp);
4970 if (val & DP_CP_IRQ)
4971 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4973 if (val & DP_SINK_SPECIFIC_IRQ)
4974 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4978 * According to DP spec
4981 * 2. Configure link according to Receiver Capabilities
4982 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4983 * 4. Check link status on receipt of hot-plug interrupt
4985 * intel_dp_short_pulse - handles short pulse interrupts
4986 * when full detection is not required.
4987 * Returns %true if short pulse is handled and full detection
4988 * is NOT required and %false otherwise.
4991 intel_dp_short_pulse(struct intel_dp *intel_dp)
4993 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4994 u8 old_sink_count = intel_dp->sink_count;
4998 * Clearing compliance test variables to allow capturing
4999 * of values for next automated test request.
5001 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5004 * Now read the DPCD to see if it's actually running
5005 * If the current value of sink count doesn't match with
5006 * the value that was stored earlier or dpcd read failed
5007 * we need to do full detection
5009 ret = intel_dp_get_dpcd(intel_dp);
5011 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5012 /* No need to proceed if we are going to do full detect */
5016 intel_dp_check_service_irq(intel_dp);
5018 /* Handle CEC interrupts, if any */
5019 drm_dp_cec_irq(&intel_dp->aux);
5021 /* defer to the hotplug work for link retraining if needed */
5022 if (intel_dp_needs_link_retrain(intel_dp))
5025 intel_psr_short_pulse(intel_dp);
5027 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5028 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5029 /* Send a Hotplug Uevent to userspace to start modeset */
5030 drm_kms_helper_hotplug_event(&dev_priv->drm);
5036 /* XXX this is probably wrong for multiple downstream ports */
5037 static enum drm_connector_status
5038 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5040 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5041 u8 *dpcd = intel_dp->dpcd;
5044 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5045 return connector_status_connected;
5048 lspcon_resume(lspcon);
5050 if (!intel_dp_get_dpcd(intel_dp))
5051 return connector_status_disconnected;
5053 /* if there's no downstream port, we're done */
5054 if (!drm_dp_is_branch(dpcd))
5055 return connector_status_connected;
5057 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5058 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5059 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5061 return intel_dp->sink_count ?
5062 connector_status_connected : connector_status_disconnected;
5065 if (intel_dp_can_mst(intel_dp))
5066 return connector_status_connected;
5068 /* If no HPD, poke DDC gently */
5069 if (drm_probe_ddc(&intel_dp->aux.ddc))
5070 return connector_status_connected;
5072 /* Well we tried, say unknown for unreliable port types */
5073 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5074 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5075 if (type == DP_DS_PORT_TYPE_VGA ||
5076 type == DP_DS_PORT_TYPE_NON_EDID)
5077 return connector_status_unknown;
5079 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5080 DP_DWN_STRM_PORT_TYPE_MASK;
5081 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5082 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5083 return connector_status_unknown;
5086 /* Anything else is out of spec, warn and ignore */
5087 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5088 return connector_status_disconnected;
5091 static enum drm_connector_status
5092 edp_detect(struct intel_dp *intel_dp)
5094 return connector_status_connected;
5097 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5102 switch (encoder->hpd_pin) {
5104 bit = SDE_PORTB_HOTPLUG;
5107 bit = SDE_PORTC_HOTPLUG;
5110 bit = SDE_PORTD_HOTPLUG;
5113 MISSING_CASE(encoder->hpd_pin);
5117 return I915_READ(SDEISR) & bit;
5120 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5125 switch (encoder->hpd_pin) {
5127 bit = SDE_PORTB_HOTPLUG_CPT;
5130 bit = SDE_PORTC_HOTPLUG_CPT;
5133 bit = SDE_PORTD_HOTPLUG_CPT;
5136 MISSING_CASE(encoder->hpd_pin);
5140 return I915_READ(SDEISR) & bit;
5143 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5148 switch (encoder->hpd_pin) {
5150 bit = SDE_PORTA_HOTPLUG_SPT;
5153 bit = SDE_PORTE_HOTPLUG_SPT;
5156 return cpt_digital_port_connected(encoder);
5159 return I915_READ(SDEISR) & bit;
5162 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5167 switch (encoder->hpd_pin) {
5169 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5172 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5175 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5178 MISSING_CASE(encoder->hpd_pin);
5182 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5185 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5190 switch (encoder->hpd_pin) {
5192 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5195 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5198 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5201 MISSING_CASE(encoder->hpd_pin);
5205 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5208 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5212 if (encoder->hpd_pin == HPD_PORT_A)
5213 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5215 return ibx_digital_port_connected(encoder);
5218 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5222 if (encoder->hpd_pin == HPD_PORT_A)
5223 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5225 return cpt_digital_port_connected(encoder);
5228 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5232 if (encoder->hpd_pin == HPD_PORT_A)
5233 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5235 return cpt_digital_port_connected(encoder);
5238 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5242 if (encoder->hpd_pin == HPD_PORT_A)
5243 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5245 return cpt_digital_port_connected(encoder);
5248 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5253 switch (encoder->hpd_pin) {
5255 bit = BXT_DE_PORT_HP_DDIA;
5258 bit = BXT_DE_PORT_HP_DDIB;
5261 bit = BXT_DE_PORT_HP_DDIC;
5264 MISSING_CASE(encoder->hpd_pin);
5268 return I915_READ(GEN8_DE_PORT_ISR) & bit;
5271 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5272 struct intel_digital_port *intel_dig_port)
5274 enum port port = intel_dig_port->base.port;
5276 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5279 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5282 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5283 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5285 if (intel_phy_is_combo(dev_priv, phy))
5286 return icl_combo_port_connected(dev_priv, dig_port);
5287 else if (intel_phy_is_tc(dev_priv, phy))
5288 return intel_tc_port_connected(dig_port);
5290 MISSING_CASE(encoder->hpd_pin);
5296 * intel_digital_port_connected - is the specified port connected?
5297 * @encoder: intel_encoder
5299 * In cases where there's a connector physically connected but it can't be used
5300 * by our hardware we also return false, since the rest of the driver should
5301 * pretty much treat the port as disconnected. This is relevant for type-C
5302 * (starting on ICL) where there's ownership involved.
5304 * Return %true if port is connected, %false otherwise.
5306 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5310 if (HAS_GMCH(dev_priv)) {
5311 if (IS_GM45(dev_priv))
5312 return gm45_digital_port_connected(encoder);
5314 return g4x_digital_port_connected(encoder);
5317 if (INTEL_GEN(dev_priv) >= 11)
5318 return icl_digital_port_connected(encoder);
5319 else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5320 return spt_digital_port_connected(encoder);
5321 else if (IS_GEN9_LP(dev_priv))
5322 return bxt_digital_port_connected(encoder);
5323 else if (IS_GEN(dev_priv, 8))
5324 return bdw_digital_port_connected(encoder);
5325 else if (IS_GEN(dev_priv, 7))
5326 return ivb_digital_port_connected(encoder);
5327 else if (IS_GEN(dev_priv, 6))
5328 return snb_digital_port_connected(encoder);
5329 else if (IS_GEN(dev_priv, 5))
5330 return ilk_digital_port_connected(encoder);
5332 MISSING_CASE(INTEL_GEN(dev_priv));
5336 bool intel_digital_port_connected(struct intel_encoder *encoder)
5338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5339 bool is_connected = false;
5340 intel_wakeref_t wakeref;
5342 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5343 is_connected = __intel_digital_port_connected(encoder);
5345 return is_connected;
5348 static struct edid *
5349 intel_dp_get_edid(struct intel_dp *intel_dp)
5351 struct intel_connector *intel_connector = intel_dp->attached_connector;
5353 /* use cached edid if we have one */
5354 if (intel_connector->edid) {
5356 if (IS_ERR(intel_connector->edid))
5359 return drm_edid_duplicate(intel_connector->edid);
5361 return drm_get_edid(&intel_connector->base,
5362 &intel_dp->aux.ddc);
5366 intel_dp_set_edid(struct intel_dp *intel_dp)
5368 struct intel_connector *intel_connector = intel_dp->attached_connector;
5371 intel_dp_unset_edid(intel_dp);
5372 edid = intel_dp_get_edid(intel_dp);
5373 intel_connector->detect_edid = edid;
5375 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5376 drm_dp_cec_set_edid(&intel_dp->aux, edid);
5380 intel_dp_unset_edid(struct intel_dp *intel_dp)
5382 struct intel_connector *intel_connector = intel_dp->attached_connector;
5384 drm_dp_cec_unset_edid(&intel_dp->aux);
5385 kfree(intel_connector->detect_edid);
5386 intel_connector->detect_edid = NULL;
5388 intel_dp->has_audio = false;
5392 intel_dp_detect(struct drm_connector *connector,
5393 struct drm_modeset_acquire_ctx *ctx,
5396 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5397 struct intel_dp *intel_dp = intel_attached_dp(connector);
5398 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5399 struct intel_encoder *encoder = &dig_port->base;
5400 enum drm_connector_status status;
5402 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5403 connector->base.id, connector->name);
5404 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5406 /* Can't disconnect eDP */
5407 if (intel_dp_is_edp(intel_dp))
5408 status = edp_detect(intel_dp);
5409 else if (intel_digital_port_connected(encoder))
5410 status = intel_dp_detect_dpcd(intel_dp);
5412 status = connector_status_disconnected;
5414 if (status == connector_status_disconnected) {
5415 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5416 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5418 if (intel_dp->is_mst) {
5419 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5421 intel_dp->mst_mgr.mst_state);
5422 intel_dp->is_mst = false;
5423 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5430 if (intel_dp->reset_link_params) {
5431 /* Initial max link lane count */
5432 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5434 /* Initial max link rate */
5435 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5437 intel_dp->reset_link_params = false;
5440 intel_dp_print_rates(intel_dp);
5442 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5443 if (INTEL_GEN(dev_priv) >= 11)
5444 intel_dp_get_dsc_sink_cap(intel_dp);
5446 intel_dp_configure_mst(intel_dp);
5448 if (intel_dp->is_mst) {
5450 * If we are in MST mode then this connector
5451 * won't appear connected or have anything
5454 status = connector_status_disconnected;
5459 * Some external monitors do not signal loss of link synchronization
5460 * with an IRQ_HPD, so force a link status check.
5462 if (!intel_dp_is_edp(intel_dp)) {
5465 ret = intel_dp_retrain_link(encoder, ctx);
5471 * Clearing NACK and defer counts to get their exact values
5472 * while reading EDID which are required by Compliance tests
5473 * 4.2.2.4 and 4.2.2.5
5475 intel_dp->aux.i2c_nack_count = 0;
5476 intel_dp->aux.i2c_defer_count = 0;
5478 intel_dp_set_edid(intel_dp);
5479 if (intel_dp_is_edp(intel_dp) ||
5480 to_intel_connector(connector)->detect_edid)
5481 status = connector_status_connected;
5483 intel_dp_check_service_irq(intel_dp);
5486 if (status != connector_status_connected && !intel_dp->is_mst)
5487 intel_dp_unset_edid(intel_dp);
5493 intel_dp_force(struct drm_connector *connector)
5495 struct intel_dp *intel_dp = intel_attached_dp(connector);
5496 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5497 struct intel_encoder *intel_encoder = &dig_port->base;
5498 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5499 enum intel_display_power_domain aux_domain =
5500 intel_aux_power_domain(dig_port);
5501 intel_wakeref_t wakeref;
5503 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5504 connector->base.id, connector->name);
5505 intel_dp_unset_edid(intel_dp);
5507 if (connector->status != connector_status_connected)
5510 wakeref = intel_display_power_get(dev_priv, aux_domain);
5512 intel_dp_set_edid(intel_dp);
5514 intel_display_power_put(dev_priv, aux_domain, wakeref);
5517 static int intel_dp_get_modes(struct drm_connector *connector)
5519 struct intel_connector *intel_connector = to_intel_connector(connector);
5522 edid = intel_connector->detect_edid;
5524 int ret = intel_connector_update_modes(connector, edid);
5529 /* if eDP has no EDID, fall back to fixed mode */
5530 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5531 intel_connector->panel.fixed_mode) {
5532 struct drm_display_mode *mode;
5534 mode = drm_mode_duplicate(connector->dev,
5535 intel_connector->panel.fixed_mode);
5537 drm_mode_probed_add(connector, mode);
5546 intel_dp_connector_register(struct drm_connector *connector)
5548 struct intel_dp *intel_dp = intel_attached_dp(connector);
5549 struct drm_device *dev = connector->dev;
5552 ret = intel_connector_register(connector);
5556 i915_debugfs_connector_add(connector);
5558 DRM_DEBUG_KMS("registering %s bus for %s\n",
5559 intel_dp->aux.name, connector->kdev->kobj.name);
5561 intel_dp->aux.dev = connector->kdev;
5562 ret = drm_dp_aux_register(&intel_dp->aux);
5564 drm_dp_cec_register_connector(&intel_dp->aux,
5565 connector->name, dev->dev);
5570 intel_dp_connector_unregister(struct drm_connector *connector)
5572 struct intel_dp *intel_dp = intel_attached_dp(connector);
5574 drm_dp_cec_unregister_connector(&intel_dp->aux);
5575 drm_dp_aux_unregister(&intel_dp->aux);
5576 intel_connector_unregister(connector);
5579 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5581 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5582 struct intel_dp *intel_dp = &intel_dig_port->dp;
5584 intel_dp_mst_encoder_cleanup(intel_dig_port);
5585 if (intel_dp_is_edp(intel_dp)) {
5586 intel_wakeref_t wakeref;
5588 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5590 * vdd might still be enabled do to the delayed vdd off.
5591 * Make sure vdd is actually turned off here.
5593 with_pps_lock(intel_dp, wakeref)
5594 edp_panel_vdd_off_sync(intel_dp);
5596 if (intel_dp->edp_notifier.notifier_call) {
5597 unregister_reboot_notifier(&intel_dp->edp_notifier);
5598 intel_dp->edp_notifier.notifier_call = NULL;
5602 intel_dp_aux_fini(intel_dp);
5605 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5607 intel_dp_encoder_flush_work(encoder);
5609 drm_encoder_cleanup(encoder);
5610 kfree(enc_to_dig_port(encoder));
5613 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5615 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5616 intel_wakeref_t wakeref;
5618 if (!intel_dp_is_edp(intel_dp))
5622 * vdd might still be enabled do to the delayed vdd off.
5623 * Make sure vdd is actually turned off here.
5625 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5626 with_pps_lock(intel_dp, wakeref)
5627 edp_panel_vdd_off_sync(intel_dp);
5630 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5634 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5635 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5636 msecs_to_jiffies(timeout));
5639 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5643 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5646 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5647 static const struct drm_dp_aux_msg msg = {
5648 .request = DP_AUX_NATIVE_WRITE,
5649 .address = DP_AUX_HDCP_AKSV,
5650 .size = DRM_HDCP_KSV_LEN,
5652 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5656 /* Output An first, that's easy */
5657 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5658 an, DRM_HDCP_AN_LEN);
5659 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5660 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5662 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5666 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5667 * order to get it on the wire, we need to create the AUX header as if
5668 * we were writing the data, and then tickle the hardware to output the
5669 * data once the header is sent out.
5671 intel_dp_aux_header(txbuf, &msg);
5673 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5674 rxbuf, sizeof(rxbuf),
5675 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5677 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5679 } else if (ret == 0) {
5680 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5684 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5685 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5686 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5693 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5697 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5699 if (ret != DRM_HDCP_KSV_LEN) {
5700 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5701 return ret >= 0 ? -EIO : ret;
5706 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5711 * For some reason the HDMI and DP HDCP specs call this register
5712 * definition by different names. In the HDMI spec, it's called BSTATUS,
5713 * but in DP it's called BINFO.
5715 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5716 bstatus, DRM_HDCP_BSTATUS_LEN);
5717 if (ret != DRM_HDCP_BSTATUS_LEN) {
5718 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5719 return ret >= 0 ? -EIO : ret;
5725 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5730 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5733 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5734 return ret >= 0 ? -EIO : ret;
5741 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5742 bool *repeater_present)
5747 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5751 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5756 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5760 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5761 ri_prime, DRM_HDCP_RI_LEN);
5762 if (ret != DRM_HDCP_RI_LEN) {
5763 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5764 return ret >= 0 ? -EIO : ret;
5770 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5775 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5778 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5779 return ret >= 0 ? -EIO : ret;
5781 *ksv_ready = bstatus & DP_BSTATUS_READY;
5786 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5787 int num_downstream, u8 *ksv_fifo)
5792 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5793 for (i = 0; i < num_downstream; i += 3) {
5794 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5795 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5796 DP_AUX_HDCP_KSV_FIFO,
5797 ksv_fifo + i * DRM_HDCP_KSV_LEN,
5800 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5802 return ret >= 0 ? -EIO : ret;
5809 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5814 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5817 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5818 DP_AUX_HDCP_V_PRIME(i), part,
5819 DRM_HDCP_V_PRIME_PART_LEN);
5820 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5821 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5822 return ret >= 0 ? -EIO : ret;
5828 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5831 /* Not used for single stream DisplayPort setups */
5836 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5841 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5844 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5848 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5852 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5858 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5862 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5866 struct hdcp2_dp_errata_stream_type {
5871 struct hdcp2_dp_msg_data {
5874 bool msg_detectable;
5876 u32 timeout2; /* Added for non_paired situation */
5879 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
5880 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
5881 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5882 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
5883 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5885 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5887 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5888 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5889 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
5890 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
5891 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5892 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
5893 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
5894 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5895 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
5896 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5898 { HDCP_2_2_REP_SEND_RECVID_LIST,
5899 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5900 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
5901 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5903 { HDCP_2_2_REP_STREAM_MANAGE,
5904 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5906 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5907 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
5908 /* local define to shovel this through the write_2_2 interface */
5909 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
5910 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5911 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5916 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5921 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5922 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5923 HDCP_2_2_DP_RXSTATUS_LEN);
5924 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5925 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5926 return ret >= 0 ? -EIO : ret;
5933 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5934 u8 msg_id, bool *msg_ready)
5940 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5945 case HDCP_2_2_AKE_SEND_HPRIME:
5946 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5949 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5950 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5953 case HDCP_2_2_REP_SEND_RECVID_LIST:
5954 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5958 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5966 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5967 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
5969 struct intel_dp *dp = &intel_dig_port->dp;
5970 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5971 u8 msg_id = hdcp2_msg_data->msg_id;
5973 bool msg_ready = false;
5975 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5976 timeout = hdcp2_msg_data->timeout2;
5978 timeout = hdcp2_msg_data->timeout;
5981 * There is no way to detect the CERT, LPRIME and STREAM_READY
5982 * availability. So Wait for timeout and read the msg.
5984 if (!hdcp2_msg_data->msg_detectable) {
5989 * As we want to check the msg availability at timeout, Ignoring
5990 * the timeout at wait for CP_IRQ.
5992 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5993 ret = hdcp2_detect_msg_availability(intel_dig_port,
5994 msg_id, &msg_ready);
6000 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6001 hdcp2_msg_data->msg_id, ret, timeout);
6006 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6010 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6011 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6012 return &hdcp2_dp_msg_data[i];
6018 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6019 void *buf, size_t size)
6021 struct intel_dp *dp = &intel_dig_port->dp;
6022 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6023 unsigned int offset;
6025 ssize_t ret, bytes_to_write, len;
6026 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6028 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6029 if (!hdcp2_msg_data)
6032 offset = hdcp2_msg_data->offset;
6034 /* No msg_id in DP HDCP2.2 msgs */
6035 bytes_to_write = size - 1;
6038 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6040 while (bytes_to_write) {
6041 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6042 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6044 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6045 offset, (void *)byte, len);
6049 bytes_to_write -= ret;
6058 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6060 u8 rx_info[HDCP_2_2_RXINFO_LEN];
6064 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6065 DP_HDCP_2_2_REG_RXINFO_OFFSET,
6066 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6067 if (ret != HDCP_2_2_RXINFO_LEN)
6068 return ret >= 0 ? -EIO : ret;
6070 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6071 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6073 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6074 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6076 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6077 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6078 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6084 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6085 u8 msg_id, void *buf, size_t size)
6087 unsigned int offset;
6089 ssize_t ret, bytes_to_recv, len;
6090 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6092 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6093 if (!hdcp2_msg_data)
6095 offset = hdcp2_msg_data->offset;
6097 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6101 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6102 ret = get_receiver_id_list_size(intel_dig_port);
6108 bytes_to_recv = size - 1;
6110 /* DP adaptation msgs has no msg_id */
6113 while (bytes_to_recv) {
6114 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6115 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6117 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6120 DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6124 bytes_to_recv -= ret;
6135 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6136 bool is_repeater, u8 content_type)
6138 struct hdcp2_dp_errata_stream_type stream_type_msg;
6144 * Errata for DP: As Stream type is used for encryption, Receiver
6145 * should be communicated with stream type for the decryption of the
6147 * Repeater will be communicated with stream type as a part of it's
6148 * auth later in time.
6150 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6151 stream_type_msg.stream_type = content_type;
6153 return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6154 sizeof(stream_type_msg));
6158 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6163 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6167 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6168 ret = HDCP_REAUTH_REQUEST;
6169 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6170 ret = HDCP_LINK_INTEGRITY_FAILURE;
6171 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6172 ret = HDCP_TOPOLOGY_CHANGE;
6178 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6185 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6186 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6187 rx_caps, HDCP_2_2_RXCAPS_LEN);
6188 if (ret != HDCP_2_2_RXCAPS_LEN)
6189 return ret >= 0 ? -EIO : ret;
6191 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6192 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6198 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6199 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6200 .read_bksv = intel_dp_hdcp_read_bksv,
6201 .read_bstatus = intel_dp_hdcp_read_bstatus,
6202 .repeater_present = intel_dp_hdcp_repeater_present,
6203 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6204 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6205 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6206 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6207 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6208 .check_link = intel_dp_hdcp_check_link,
6209 .hdcp_capable = intel_dp_hdcp_capable,
6210 .write_2_2_msg = intel_dp_hdcp2_write_msg,
6211 .read_2_2_msg = intel_dp_hdcp2_read_msg,
6212 .config_stream_type = intel_dp_hdcp2_config_stream_type,
6213 .check_2_2_link = intel_dp_hdcp2_check_link,
6214 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6215 .protocol = HDCP_PROTOCOL_DP,
6218 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6220 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6221 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6223 lockdep_assert_held(&dev_priv->pps_mutex);
6225 if (!edp_have_panel_vdd(intel_dp))
6229 * The VDD bit needs a power domain reference, so if the bit is
6230 * already enabled when we boot or resume, grab this reference and
6231 * schedule a vdd off, so we don't hold on to the reference
6234 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6235 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6237 edp_panel_vdd_schedule_off(intel_dp);
6240 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6242 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6243 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6246 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6247 encoder->port, &pipe))
6250 return INVALID_PIPE;
6253 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6255 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6256 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6257 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6258 intel_wakeref_t wakeref;
6260 if (!HAS_DDI(dev_priv))
6261 intel_dp->DP = I915_READ(intel_dp->output_reg);
6264 lspcon_resume(lspcon);
6266 intel_dp->reset_link_params = true;
6268 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6269 !intel_dp_is_edp(intel_dp))
6272 with_pps_lock(intel_dp, wakeref) {
6273 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6274 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6276 if (intel_dp_is_edp(intel_dp)) {
6278 * Reinit the power sequencer, in case BIOS did
6279 * something nasty with it.
6281 intel_dp_pps_init(intel_dp);
6282 intel_edp_panel_vdd_sanitize(intel_dp);
6287 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6288 .force = intel_dp_force,
6289 .fill_modes = drm_helper_probe_single_connector_modes,
6290 .atomic_get_property = intel_digital_connector_atomic_get_property,
6291 .atomic_set_property = intel_digital_connector_atomic_set_property,
6292 .late_register = intel_dp_connector_register,
6293 .early_unregister = intel_dp_connector_unregister,
6294 .destroy = intel_connector_destroy,
6295 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6296 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6299 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6300 .detect_ctx = intel_dp_detect,
6301 .get_modes = intel_dp_get_modes,
6302 .mode_valid = intel_dp_mode_valid,
6303 .atomic_check = intel_digital_connector_atomic_check,
6306 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6307 .reset = intel_dp_encoder_reset,
6308 .destroy = intel_dp_encoder_destroy,
6312 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6314 struct intel_dp *intel_dp = &intel_dig_port->dp;
6316 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6318 * vdd off can generate a long pulse on eDP which
6319 * would require vdd on to handle it, and thus we
6320 * would end up in an endless cycle of
6321 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6323 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6324 intel_dig_port->base.base.base.id,
6325 intel_dig_port->base.base.name);
6329 DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6330 intel_dig_port->base.base.base.id,
6331 intel_dig_port->base.base.name,
6332 long_hpd ? "long" : "short");
6335 intel_dp->reset_link_params = true;
6339 if (intel_dp->is_mst) {
6340 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6342 * If we were in MST mode, and device is not
6343 * there, get out of MST mode
6345 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6346 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6347 intel_dp->is_mst = false;
6348 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6355 if (!intel_dp->is_mst) {
6358 handled = intel_dp_short_pulse(intel_dp);
6367 /* check the VBT to see whether the eDP is on another port */
6368 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6371 * eDP not supported on g4x. so bail out early just
6372 * for a bit extra safety in case the VBT is bonkers.
6374 if (INTEL_GEN(dev_priv) < 5)
6377 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6380 return intel_bios_is_port_edp(dev_priv, port);
6384 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6386 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6387 enum port port = dp_to_dig_port(intel_dp)->base.port;
6389 if (!IS_G4X(dev_priv) && port != PORT_A)
6390 intel_attach_force_audio_property(connector);
6392 intel_attach_broadcast_rgb_property(connector);
6393 if (HAS_GMCH(dev_priv))
6394 drm_connector_attach_max_bpc_property(connector, 6, 10);
6395 else if (INTEL_GEN(dev_priv) >= 5)
6396 drm_connector_attach_max_bpc_property(connector, 6, 12);
6398 if (intel_dp_is_edp(intel_dp)) {
6399 u32 allowed_scalers;
6401 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6402 if (!HAS_GMCH(dev_priv))
6403 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6405 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6407 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6412 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6414 intel_dp->panel_power_off_time = ktime_get_boottime();
6415 intel_dp->last_power_on = jiffies;
6416 intel_dp->last_backlight_off = jiffies;
6420 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6422 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6423 u32 pp_on, pp_off, pp_ctl;
6424 struct pps_registers regs;
6426 intel_pps_get_registers(intel_dp, ®s);
6428 pp_ctl = ironlake_get_pp_control(intel_dp);
6430 /* Ensure PPS is unlocked */
6431 if (!HAS_DDI(dev_priv))
6432 I915_WRITE(regs.pp_ctrl, pp_ctl);
6434 pp_on = I915_READ(regs.pp_on);
6435 pp_off = I915_READ(regs.pp_off);
6437 /* Pull timing values out of registers */
6438 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6439 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6440 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6441 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6443 if (i915_mmio_reg_valid(regs.pp_div)) {
6446 pp_div = I915_READ(regs.pp_div);
6448 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6450 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6455 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6457 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6459 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6463 intel_pps_verify_state(struct intel_dp *intel_dp)
6465 struct edp_power_seq hw;
6466 struct edp_power_seq *sw = &intel_dp->pps_delays;
6468 intel_pps_readout_hw_state(intel_dp, &hw);
6470 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6471 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6472 DRM_ERROR("PPS state mismatch\n");
6473 intel_pps_dump_state("sw", sw);
6474 intel_pps_dump_state("hw", &hw);
6479 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6481 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6482 struct edp_power_seq cur, vbt, spec,
6483 *final = &intel_dp->pps_delays;
6485 lockdep_assert_held(&dev_priv->pps_mutex);
6487 /* already initialized? */
6488 if (final->t11_t12 != 0)
6491 intel_pps_readout_hw_state(intel_dp, &cur);
6493 intel_pps_dump_state("cur", &cur);
6495 vbt = dev_priv->vbt.edp.pps;
6496 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6497 * of 500ms appears to be too short. Ocassionally the panel
6498 * just fails to power back on. Increasing the delay to 800ms
6499 * seems sufficient to avoid this problem.
6501 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6502 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6503 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6506 /* T11_T12 delay is special and actually in units of 100ms, but zero
6507 * based in the hw (so we need to add 100 ms). But the sw vbt
6508 * table multiplies it with 1000 to make it in units of 100usec,
6510 vbt.t11_t12 += 100 * 10;
6512 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6513 * our hw here, which are all in 100usec. */
6514 spec.t1_t3 = 210 * 10;
6515 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6516 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6517 spec.t10 = 500 * 10;
6518 /* This one is special and actually in units of 100ms, but zero
6519 * based in the hw (so we need to add 100 ms). But the sw vbt
6520 * table multiplies it with 1000 to make it in units of 100usec,
6522 spec.t11_t12 = (510 + 100) * 10;
6524 intel_pps_dump_state("vbt", &vbt);
6526 /* Use the max of the register settings and vbt. If both are
6527 * unset, fall back to the spec limits. */
6528 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6530 max(cur.field, vbt.field))
6531 assign_final(t1_t3);
6535 assign_final(t11_t12);
6538 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6539 intel_dp->panel_power_up_delay = get_delay(t1_t3);
6540 intel_dp->backlight_on_delay = get_delay(t8);
6541 intel_dp->backlight_off_delay = get_delay(t9);
6542 intel_dp->panel_power_down_delay = get_delay(t10);
6543 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6546 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6547 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6548 intel_dp->panel_power_cycle_delay);
6550 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6551 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6554 * We override the HW backlight delays to 1 because we do manual waits
6555 * on them. For T8, even BSpec recommends doing it. For T9, if we
6556 * don't do this, we'll end up waiting for the backlight off delay
6557 * twice: once when we do the manual sleep, and once when we disable
6558 * the panel and wait for the PP_STATUS bit to become zero.
6564 * HW has only a 100msec granularity for t11_t12 so round it up
6567 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6571 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6572 bool force_disable_vdd)
6574 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6575 u32 pp_on, pp_off, port_sel = 0;
6576 int div = dev_priv->rawclk_freq / 1000;
6577 struct pps_registers regs;
6578 enum port port = dp_to_dig_port(intel_dp)->base.port;
6579 const struct edp_power_seq *seq = &intel_dp->pps_delays;
6581 lockdep_assert_held(&dev_priv->pps_mutex);
6583 intel_pps_get_registers(intel_dp, ®s);
6586 * On some VLV machines the BIOS can leave the VDD
6587 * enabled even on power sequencers which aren't
6588 * hooked up to any port. This would mess up the
6589 * power domain tracking the first time we pick
6590 * one of these power sequencers for use since
6591 * edp_panel_vdd_on() would notice that the VDD was
6592 * already on and therefore wouldn't grab the power
6593 * domain reference. Disable VDD first to avoid this.
6594 * This also avoids spuriously turning the VDD on as
6595 * soon as the new power sequencer gets initialized.
6597 if (force_disable_vdd) {
6598 u32 pp = ironlake_get_pp_control(intel_dp);
6600 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6602 if (pp & EDP_FORCE_VDD)
6603 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6605 pp &= ~EDP_FORCE_VDD;
6607 I915_WRITE(regs.pp_ctrl, pp);
6610 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6611 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6612 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6613 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6615 /* Haswell doesn't have any port selection bits for the panel
6616 * power sequencer any more. */
6617 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6618 port_sel = PANEL_PORT_SELECT_VLV(port);
6619 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6622 port_sel = PANEL_PORT_SELECT_DPA;
6625 port_sel = PANEL_PORT_SELECT_DPC;
6628 port_sel = PANEL_PORT_SELECT_DPD;
6638 I915_WRITE(regs.pp_on, pp_on);
6639 I915_WRITE(regs.pp_off, pp_off);
6642 * Compute the divisor for the pp clock, simply match the Bspec formula.
6644 if (i915_mmio_reg_valid(regs.pp_div)) {
6645 I915_WRITE(regs.pp_div,
6646 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6647 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6651 pp_ctl = I915_READ(regs.pp_ctrl);
6652 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6653 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6654 I915_WRITE(regs.pp_ctrl, pp_ctl);
6657 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6658 I915_READ(regs.pp_on),
6659 I915_READ(regs.pp_off),
6660 i915_mmio_reg_valid(regs.pp_div) ?
6661 I915_READ(regs.pp_div) :
6662 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6665 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6667 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6669 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6670 vlv_initial_power_sequencer_setup(intel_dp);
6672 intel_dp_init_panel_power_sequencer(intel_dp);
6673 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6678 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6679 * @dev_priv: i915 device
6680 * @crtc_state: a pointer to the active intel_crtc_state
6681 * @refresh_rate: RR to be programmed
6683 * This function gets called when refresh rate (RR) has to be changed from
6684 * one frequency to another. Switches can be between high and low RR
6685 * supported by the panel or to any other RR based on media playback (in
6686 * this case, RR value needs to be passed from user space).
6688 * The caller of this function needs to take a lock on dev_priv->drrs.
6690 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6691 const struct intel_crtc_state *crtc_state,
6694 struct intel_dp *intel_dp = dev_priv->drrs.dp;
6695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6696 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6698 if (refresh_rate <= 0) {
6699 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6703 if (intel_dp == NULL) {
6704 DRM_DEBUG_KMS("DRRS not supported.\n");
6709 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6713 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6714 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6718 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6720 index = DRRS_LOW_RR;
6722 if (index == dev_priv->drrs.refresh_rate_type) {
6724 "DRRS requested for previously set RR...ignoring\n");
6728 if (!crtc_state->base.active) {
6729 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6733 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6736 intel_dp_set_m_n(crtc_state, M1_N1);
6739 intel_dp_set_m_n(crtc_state, M2_N2);
6743 DRM_ERROR("Unsupported refreshrate type\n");
6745 } else if (INTEL_GEN(dev_priv) > 6) {
6746 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6749 val = I915_READ(reg);
6750 if (index > DRRS_HIGH_RR) {
6751 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6752 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6754 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6756 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6757 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6759 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6761 I915_WRITE(reg, val);
6764 dev_priv->drrs.refresh_rate_type = index;
6766 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6770 * intel_edp_drrs_enable - init drrs struct if supported
6771 * @intel_dp: DP struct
6772 * @crtc_state: A pointer to the active crtc state.
6774 * Initializes frontbuffer_bits and drrs.dp
6776 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6777 const struct intel_crtc_state *crtc_state)
6779 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6781 if (!crtc_state->has_drrs) {
6782 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6786 if (dev_priv->psr.enabled) {
6787 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6791 mutex_lock(&dev_priv->drrs.mutex);
6792 if (dev_priv->drrs.dp) {
6793 DRM_DEBUG_KMS("DRRS already enabled\n");
6797 dev_priv->drrs.busy_frontbuffer_bits = 0;
6799 dev_priv->drrs.dp = intel_dp;
6802 mutex_unlock(&dev_priv->drrs.mutex);
6806 * intel_edp_drrs_disable - Disable DRRS
6807 * @intel_dp: DP struct
6808 * @old_crtc_state: Pointer to old crtc_state.
6811 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6812 const struct intel_crtc_state *old_crtc_state)
6814 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6816 if (!old_crtc_state->has_drrs)
6819 mutex_lock(&dev_priv->drrs.mutex);
6820 if (!dev_priv->drrs.dp) {
6821 mutex_unlock(&dev_priv->drrs.mutex);
6825 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6826 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6827 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6829 dev_priv->drrs.dp = NULL;
6830 mutex_unlock(&dev_priv->drrs.mutex);
6832 cancel_delayed_work_sync(&dev_priv->drrs.work);
6835 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6837 struct drm_i915_private *dev_priv =
6838 container_of(work, typeof(*dev_priv), drrs.work.work);
6839 struct intel_dp *intel_dp;
6841 mutex_lock(&dev_priv->drrs.mutex);
6843 intel_dp = dev_priv->drrs.dp;
6849 * The delayed work can race with an invalidate hence we need to
6853 if (dev_priv->drrs.busy_frontbuffer_bits)
6856 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6857 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6859 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6860 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6864 mutex_unlock(&dev_priv->drrs.mutex);
6868 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6869 * @dev_priv: i915 device
6870 * @frontbuffer_bits: frontbuffer plane tracking bits
6872 * This function gets called everytime rendering on the given planes start.
6873 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6875 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6877 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6878 unsigned int frontbuffer_bits)
6880 struct drm_crtc *crtc;
6883 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6886 cancel_delayed_work(&dev_priv->drrs.work);
6888 mutex_lock(&dev_priv->drrs.mutex);
6889 if (!dev_priv->drrs.dp) {
6890 mutex_unlock(&dev_priv->drrs.mutex);
6894 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6895 pipe = to_intel_crtc(crtc)->pipe;
6897 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6898 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6900 /* invalidate means busy screen hence upclock */
6901 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6902 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6903 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6905 mutex_unlock(&dev_priv->drrs.mutex);
6909 * intel_edp_drrs_flush - Restart Idleness DRRS
6910 * @dev_priv: i915 device
6911 * @frontbuffer_bits: frontbuffer plane tracking bits
6913 * This function gets called every time rendering on the given planes has
6914 * completed or flip on a crtc is completed. So DRRS should be upclocked
6915 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6916 * if no other planes are dirty.
6918 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6920 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6921 unsigned int frontbuffer_bits)
6923 struct drm_crtc *crtc;
6926 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6929 cancel_delayed_work(&dev_priv->drrs.work);
6931 mutex_lock(&dev_priv->drrs.mutex);
6932 if (!dev_priv->drrs.dp) {
6933 mutex_unlock(&dev_priv->drrs.mutex);
6937 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6938 pipe = to_intel_crtc(crtc)->pipe;
6940 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6941 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6943 /* flush means busy screen hence upclock */
6944 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6945 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6946 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6949 * flush also means no more activity hence schedule downclock, if all
6950 * other fbs are quiescent too
6952 if (!dev_priv->drrs.busy_frontbuffer_bits)
6953 schedule_delayed_work(&dev_priv->drrs.work,
6954 msecs_to_jiffies(1000));
6955 mutex_unlock(&dev_priv->drrs.mutex);
6959 * DOC: Display Refresh Rate Switching (DRRS)
6961 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6962 * which enables swtching between low and high refresh rates,
6963 * dynamically, based on the usage scenario. This feature is applicable
6964 * for internal panels.
6966 * Indication that the panel supports DRRS is given by the panel EDID, which
6967 * would list multiple refresh rates for one resolution.
6969 * DRRS is of 2 types - static and seamless.
6970 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6971 * (may appear as a blink on screen) and is used in dock-undock scenario.
6972 * Seamless DRRS involves changing RR without any visual effect to the user
6973 * and can be used during normal system usage. This is done by programming
6974 * certain registers.
6976 * Support for static/seamless DRRS may be indicated in the VBT based on
6977 * inputs from the panel spec.
6979 * DRRS saves power by switching to low RR based on usage scenarios.
6981 * The implementation is based on frontbuffer tracking implementation. When
6982 * there is a disturbance on the screen triggered by user activity or a periodic
6983 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6984 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6987 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6988 * and intel_edp_drrs_flush() are called.
6990 * DRRS can be further extended to support other internal panels and also
6991 * the scenario of video playback wherein RR is set based on the rate
6992 * requested by userspace.
6996 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6997 * @connector: eDP connector
6998 * @fixed_mode: preferred mode of panel
7000 * This function is called only once at driver load to initialize basic
7004 * Downclock mode if panel supports it, else return NULL.
7005 * DRRS support is determined by the presence of downclock mode (apart
7006 * from VBT setting).
7008 static struct drm_display_mode *
7009 intel_dp_drrs_init(struct intel_connector *connector,
7010 struct drm_display_mode *fixed_mode)
7012 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7013 struct drm_display_mode *downclock_mode = NULL;
7015 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7016 mutex_init(&dev_priv->drrs.mutex);
7018 if (INTEL_GEN(dev_priv) <= 6) {
7019 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7023 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7024 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7028 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7029 if (!downclock_mode) {
7030 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7034 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7036 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7037 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7038 return downclock_mode;
7041 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7042 struct intel_connector *intel_connector)
7044 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7045 struct drm_device *dev = &dev_priv->drm;
7046 struct drm_connector *connector = &intel_connector->base;
7047 struct drm_display_mode *fixed_mode = NULL;
7048 struct drm_display_mode *downclock_mode = NULL;
7050 enum pipe pipe = INVALID_PIPE;
7051 intel_wakeref_t wakeref;
7054 if (!intel_dp_is_edp(intel_dp))
7057 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7060 * On IBX/CPT we may get here with LVDS already registered. Since the
7061 * driver uses the only internal power sequencer available for both
7062 * eDP and LVDS bail out early in this case to prevent interfering
7063 * with an already powered-on LVDS power sequencer.
7065 if (intel_get_lvds_encoder(dev_priv)) {
7066 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7067 DRM_INFO("LVDS was detected, not registering eDP\n");
7072 with_pps_lock(intel_dp, wakeref) {
7073 intel_dp_init_panel_power_timestamps(intel_dp);
7074 intel_dp_pps_init(intel_dp);
7075 intel_edp_panel_vdd_sanitize(intel_dp);
7078 /* Cache DPCD and EDID for edp. */
7079 has_dpcd = intel_edp_init_dpcd(intel_dp);
7082 /* if this fails, presume the device is a ghost */
7083 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7087 mutex_lock(&dev->mode_config.mutex);
7088 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7090 if (drm_add_edid_modes(connector, edid)) {
7091 drm_connector_update_edid_property(connector,
7095 edid = ERR_PTR(-EINVAL);
7098 edid = ERR_PTR(-ENOENT);
7100 intel_connector->edid = edid;
7102 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7104 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7106 /* fallback to VBT if available for eDP */
7108 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7109 mutex_unlock(&dev->mode_config.mutex);
7111 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7112 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7113 register_reboot_notifier(&intel_dp->edp_notifier);
7116 * Figure out the current pipe for the initial backlight setup.
7117 * If the current pipe isn't valid, try the PPS pipe, and if that
7118 * fails just assume pipe A.
7120 pipe = vlv_active_pipe(intel_dp);
7122 if (pipe != PIPE_A && pipe != PIPE_B)
7123 pipe = intel_dp->pps_pipe;
7125 if (pipe != PIPE_A && pipe != PIPE_B)
7128 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7132 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7133 intel_connector->panel.backlight.power = intel_edp_backlight_power;
7134 intel_panel_setup_backlight(connector, pipe);
7137 drm_connector_init_panel_orientation_property(
7138 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7143 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7145 * vdd might still be enabled do to the delayed vdd off.
7146 * Make sure vdd is actually turned off here.
7148 with_pps_lock(intel_dp, wakeref)
7149 edp_panel_vdd_off_sync(intel_dp);
7154 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7156 struct intel_connector *intel_connector;
7157 struct drm_connector *connector;
7159 intel_connector = container_of(work, typeof(*intel_connector),
7160 modeset_retry_work);
7161 connector = &intel_connector->base;
7162 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7165 /* Grab the locks before changing connector property*/
7166 mutex_lock(&connector->dev->mode_config.mutex);
7167 /* Set connector link status to BAD and send a Uevent to notify
7168 * userspace to do a modeset.
7170 drm_connector_set_link_status_property(connector,
7171 DRM_MODE_LINK_STATUS_BAD);
7172 mutex_unlock(&connector->dev->mode_config.mutex);
7173 /* Send Hotplug uevent so userspace can reprobe */
7174 drm_kms_helper_hotplug_event(connector->dev);
7178 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7179 struct intel_connector *intel_connector)
7181 struct drm_connector *connector = &intel_connector->base;
7182 struct intel_dp *intel_dp = &intel_dig_port->dp;
7183 struct intel_encoder *intel_encoder = &intel_dig_port->base;
7184 struct drm_device *dev = intel_encoder->base.dev;
7185 struct drm_i915_private *dev_priv = to_i915(dev);
7186 enum port port = intel_encoder->port;
7187 enum phy phy = intel_port_to_phy(dev_priv, port);
7190 /* Initialize the work for modeset in case of link train failure */
7191 INIT_WORK(&intel_connector->modeset_retry_work,
7192 intel_dp_modeset_retry_work_fn);
7194 if (WARN(intel_dig_port->max_lanes < 1,
7195 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7196 intel_dig_port->max_lanes, intel_encoder->base.base.id,
7197 intel_encoder->base.name))
7200 intel_dp_set_source_rates(intel_dp);
7202 intel_dp->reset_link_params = true;
7203 intel_dp->pps_pipe = INVALID_PIPE;
7204 intel_dp->active_pipe = INVALID_PIPE;
7206 /* Preserve the current hw state. */
7207 intel_dp->DP = I915_READ(intel_dp->output_reg);
7208 intel_dp->attached_connector = intel_connector;
7210 if (intel_dp_is_port_edp(dev_priv, port)) {
7212 * Currently we don't support eDP on TypeC ports, although in
7213 * theory it could work on TypeC legacy ports.
7215 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7216 type = DRM_MODE_CONNECTOR_eDP;
7218 type = DRM_MODE_CONNECTOR_DisplayPort;
7221 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7222 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7225 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7226 * for DP the encoder type can be set by the caller to
7227 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7229 if (type == DRM_MODE_CONNECTOR_eDP)
7230 intel_encoder->type = INTEL_OUTPUT_EDP;
7232 /* eDP only on port B and/or C on vlv/chv */
7233 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7234 intel_dp_is_edp(intel_dp) &&
7235 port != PORT_B && port != PORT_C))
7238 DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7239 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7240 intel_encoder->base.base.id, intel_encoder->base.name);
7242 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7243 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7245 if (!HAS_GMCH(dev_priv))
7246 connector->interlace_allowed = true;
7247 connector->doublescan_allowed = 0;
7249 if (INTEL_GEN(dev_priv) >= 11)
7250 connector->ycbcr_420_allowed = true;
7252 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7254 intel_dp_aux_init(intel_dp);
7256 intel_connector_attach_encoder(intel_connector, intel_encoder);
7258 if (HAS_DDI(dev_priv))
7259 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7261 intel_connector->get_hw_state = intel_connector_get_hw_state;
7263 /* init MST on ports that can support it */
7264 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7265 (port == PORT_B || port == PORT_C ||
7266 port == PORT_D || port == PORT_F))
7267 intel_dp_mst_encoder_init(intel_dig_port,
7268 intel_connector->base.base.id);
7270 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7271 intel_dp_aux_fini(intel_dp);
7272 intel_dp_mst_encoder_cleanup(intel_dig_port);
7276 intel_dp_add_properties(intel_dp, connector);
7278 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7279 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7281 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7284 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7285 * 0xd. Failure to do so will result in spurious interrupts being
7286 * generated on the port when a cable is not attached.
7288 if (IS_G45(dev_priv)) {
7289 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7290 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7296 drm_connector_cleanup(connector);
7301 bool intel_dp_init(struct drm_i915_private *dev_priv,
7302 i915_reg_t output_reg,
7305 struct intel_digital_port *intel_dig_port;
7306 struct intel_encoder *intel_encoder;
7307 struct drm_encoder *encoder;
7308 struct intel_connector *intel_connector;
7310 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7311 if (!intel_dig_port)
7314 intel_connector = intel_connector_alloc();
7315 if (!intel_connector)
7316 goto err_connector_alloc;
7318 intel_encoder = &intel_dig_port->base;
7319 encoder = &intel_encoder->base;
7321 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7322 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7323 "DP %c", port_name(port)))
7324 goto err_encoder_init;
7326 intel_encoder->hotplug = intel_dp_hotplug;
7327 intel_encoder->compute_config = intel_dp_compute_config;
7328 intel_encoder->get_hw_state = intel_dp_get_hw_state;
7329 intel_encoder->get_config = intel_dp_get_config;
7330 intel_encoder->update_pipe = intel_panel_update_backlight;
7331 intel_encoder->suspend = intel_dp_encoder_suspend;
7332 if (IS_CHERRYVIEW(dev_priv)) {
7333 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7334 intel_encoder->pre_enable = chv_pre_enable_dp;
7335 intel_encoder->enable = vlv_enable_dp;
7336 intel_encoder->disable = vlv_disable_dp;
7337 intel_encoder->post_disable = chv_post_disable_dp;
7338 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7339 } else if (IS_VALLEYVIEW(dev_priv)) {
7340 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7341 intel_encoder->pre_enable = vlv_pre_enable_dp;
7342 intel_encoder->enable = vlv_enable_dp;
7343 intel_encoder->disable = vlv_disable_dp;
7344 intel_encoder->post_disable = vlv_post_disable_dp;
7346 intel_encoder->pre_enable = g4x_pre_enable_dp;
7347 intel_encoder->enable = g4x_enable_dp;
7348 intel_encoder->disable = g4x_disable_dp;
7349 intel_encoder->post_disable = g4x_post_disable_dp;
7352 intel_dig_port->dp.output_reg = output_reg;
7353 intel_dig_port->max_lanes = 4;
7355 intel_encoder->type = INTEL_OUTPUT_DP;
7356 intel_encoder->power_domain = intel_port_to_power_domain(port);
7357 if (IS_CHERRYVIEW(dev_priv)) {
7359 intel_encoder->crtc_mask = 1 << 2;
7361 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7363 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7365 intel_encoder->cloneable = 0;
7366 intel_encoder->port = port;
7368 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7371 intel_infoframe_init(intel_dig_port);
7373 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7374 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7375 goto err_init_connector;
7380 drm_encoder_cleanup(encoder);
7382 kfree(intel_connector);
7383 err_connector_alloc:
7384 kfree(intel_dig_port);
7388 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7390 struct intel_encoder *encoder;
7392 for_each_intel_encoder(&dev_priv->drm, encoder) {
7393 struct intel_dp *intel_dp;
7395 if (encoder->type != INTEL_OUTPUT_DDI)
7398 intel_dp = enc_to_intel_dp(&encoder->base);
7400 if (!intel_dp->can_mst)
7403 if (intel_dp->is_mst)
7404 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7408 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7410 struct intel_encoder *encoder;
7412 for_each_intel_encoder(&dev_priv->drm, encoder) {
7413 struct intel_dp *intel_dp;
7416 if (encoder->type != INTEL_OUTPUT_DDI)
7419 intel_dp = enc_to_intel_dp(&encoder->base);
7421 if (!intel_dp->can_mst)
7424 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7426 intel_dp->is_mst = false;
7427 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,