2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include <drm/drm_probe_helper.h>
44 #include "i915_debugfs.h"
46 #include "i915_trace.h"
47 #include "intel_atomic.h"
48 #include "intel_audio.h"
49 #include "intel_connector.h"
50 #include "intel_ddi.h"
51 #include "intel_display_types.h"
53 #include "intel_dp_link_training.h"
54 #include "intel_dp_mst.h"
55 #include "intel_dpio_phy.h"
56 #include "intel_fifo_underrun.h"
57 #include "intel_hdcp.h"
58 #include "intel_hdmi.h"
59 #include "intel_hotplug.h"
60 #include "intel_lspcon.h"
61 #include "intel_lvds.h"
62 #include "intel_panel.h"
63 #include "intel_psr.h"
64 #include "intel_sideband.h"
66 #include "intel_vdsc.h"
68 #define DP_DPRX_ESI_LEN 14
70 /* DP DSC throughput values used for slice count calculations KPixels/s */
71 #define DP_DSC_PEAK_PIXEL_RATE 2720000
72 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
73 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
75 /* DP DSC FEC Overhead factor = 1/(0.972261) */
76 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
78 /* Compliance test status bits */
79 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
80 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
81 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
82 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
89 static const struct dp_link_dpll g4x_dpll[] = {
91 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
93 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
96 static const struct dp_link_dpll pch_dpll[] = {
98 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
100 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
103 static const struct dp_link_dpll vlv_dpll[] = {
105 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
107 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
111 * CHV supports eDP 1.4 that have more link rates.
112 * Below only provides the fixed rate but exclude variable rate.
114 static const struct dp_link_dpll chv_dpll[] = {
116 * CHV requires to program fractional division for m2.
117 * m2 is stored in fixed point format using formula below
118 * (m2_int << 22) | m2_fraction
120 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
121 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
122 { 270000, /* m2_int = 27, m2_fraction = 0 */
123 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
126 /* Constants for DP DSC configurations */
127 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
129 /* With Single pipe configuration, HW is capable of supporting maximum
130 * of 4 slices per line.
132 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
135 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
136 * @intel_dp: DP struct
138 * If a CPU or PCH DP output is attached to an eDP panel, this function
139 * will return true, and false otherwise.
141 bool intel_dp_is_edp(struct intel_dp *intel_dp)
143 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
148 static void intel_dp_link_down(struct intel_encoder *encoder,
149 const struct intel_crtc_state *old_crtc_state);
150 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
151 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
152 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
153 const struct intel_crtc_state *crtc_state);
154 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
158 /* update sink rates from dpcd */
159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
161 static const int dp_rates[] = {
162 162000, 270000, 540000, 810000
166 if (drm_dp_has_quirk(&intel_dp->desc, 0,
167 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
168 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
169 static const int quirk_rates[] = { 162000, 270000, 324000 };
171 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
172 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
179 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
180 if (dp_rates[i] > max_rate)
182 intel_dp->sink_rates[i] = dp_rates[i];
185 intel_dp->num_sink_rates = i;
188 /* Get length of rates array potentially limited by max_rate. */
189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
193 /* Limit results by potentially reduced max rate */
194 for (i = 0; i < len; i++) {
195 if (rates[len - i - 1] <= max_rate)
202 /* Get length of common rates array potentially limited by max_rate. */
203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
206 return intel_dp_rate_limit_len(intel_dp->common_rates,
207 intel_dp->num_common_rates, max_rate);
210 /* Theoretical max between source and sink */
211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
213 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
216 /* Theoretical max between source and sink */
217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
220 int source_max = intel_dig_port->max_lanes;
221 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
222 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
224 return min3(source_max, sink_max, fia_max);
227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
229 return intel_dp->max_link_lane_count;
233 intel_dp_link_required(int pixel_clock, int bpp)
235 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
236 return DIV_ROUND_UP(pixel_clock * bpp, 8);
240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
242 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
243 * link rate that is generally expressed in Gbps. Since, 8 bits of data
244 * is transmitted every LS_Clk per lane, there is no need to account for
245 * the channel encoding that is done in the PHY layer here.
248 return max_link_clock * max_lanes;
252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
255 struct intel_encoder *encoder = &intel_dig_port->base;
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
257 int max_dotclk = dev_priv->max_dotclk_freq;
260 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
262 if (type != DP_DS_PORT_TYPE_VGA)
265 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
266 intel_dp->downstream_ports);
268 if (ds_max_dotclk != 0)
269 max_dotclk = min(max_dotclk, ds_max_dotclk);
274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
276 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
277 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
278 enum port port = dig_port->base.port;
280 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
282 /* Low voltage SKUs are limited to max of 5.4G */
283 if (voltage == VOLTAGE_INFO_0_85V)
286 /* For this SKU 8.1G is supported in all ports */
287 if (IS_CNL_WITH_PORT_F(dev_priv))
290 /* For other SKUs, max rate on ports A and D is 5.4G */
291 if (port == PORT_A || port == PORT_D)
297 static int icl_max_source_rate(struct intel_dp *intel_dp)
299 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
300 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
301 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
303 if (intel_phy_is_combo(dev_priv, phy) &&
304 !IS_ELKHARTLAKE(dev_priv) &&
305 !intel_dp_is_edp(intel_dp))
312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
314 /* The values must be in increasing order */
315 static const int cnl_rates[] = {
316 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
318 static const int bxt_rates[] = {
319 162000, 216000, 243000, 270000, 324000, 432000, 540000
321 static const int skl_rates[] = {
322 162000, 216000, 270000, 324000, 432000, 540000
324 static const int hsw_rates[] = {
325 162000, 270000, 540000
327 static const int g4x_rates[] = {
330 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
331 struct intel_encoder *encoder = &dig_port->base;
332 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
333 const int *source_rates;
334 int size, max_rate = 0, vbt_max_rate;
336 /* This should only be done once */
337 drm_WARN_ON(&dev_priv->drm,
338 intel_dp->source_rates || intel_dp->num_source_rates);
340 if (INTEL_GEN(dev_priv) >= 10) {
341 source_rates = cnl_rates;
342 size = ARRAY_SIZE(cnl_rates);
343 if (IS_GEN(dev_priv, 10))
344 max_rate = cnl_max_source_rate(intel_dp);
346 max_rate = icl_max_source_rate(intel_dp);
347 } else if (IS_GEN9_LP(dev_priv)) {
348 source_rates = bxt_rates;
349 size = ARRAY_SIZE(bxt_rates);
350 } else if (IS_GEN9_BC(dev_priv)) {
351 source_rates = skl_rates;
352 size = ARRAY_SIZE(skl_rates);
353 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
354 IS_BROADWELL(dev_priv)) {
355 source_rates = hsw_rates;
356 size = ARRAY_SIZE(hsw_rates);
358 source_rates = g4x_rates;
359 size = ARRAY_SIZE(g4x_rates);
362 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
363 if (max_rate && vbt_max_rate)
364 max_rate = min(max_rate, vbt_max_rate);
365 else if (vbt_max_rate)
366 max_rate = vbt_max_rate;
369 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
371 intel_dp->source_rates = source_rates;
372 intel_dp->num_source_rates = size;
375 static int intersect_rates(const int *source_rates, int source_len,
376 const int *sink_rates, int sink_len,
379 int i = 0, j = 0, k = 0;
381 while (i < source_len && j < sink_len) {
382 if (source_rates[i] == sink_rates[j]) {
383 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
385 common_rates[k] = source_rates[i];
389 } else if (source_rates[i] < sink_rates[j]) {
398 /* return index of rate in rates array, or -1 if not found */
399 static int intel_dp_rate_index(const int *rates, int len, int rate)
403 for (i = 0; i < len; i++)
404 if (rate == rates[i])
410 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
412 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
414 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
415 intel_dp->num_source_rates,
416 intel_dp->sink_rates,
417 intel_dp->num_sink_rates,
418 intel_dp->common_rates);
420 /* Paranoia, there should always be something in common. */
421 if (WARN_ON(intel_dp->num_common_rates == 0)) {
422 intel_dp->common_rates[0] = 162000;
423 intel_dp->num_common_rates = 1;
427 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
431 * FIXME: we need to synchronize the current link parameters with
432 * hardware readout. Currently fast link training doesn't work on
435 if (link_rate == 0 ||
436 link_rate > intel_dp->max_link_rate)
439 if (lane_count == 0 ||
440 lane_count > intel_dp_max_lane_count(intel_dp))
446 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
450 const struct drm_display_mode *fixed_mode =
451 intel_dp->attached_connector->panel.fixed_mode;
452 int mode_rate, max_rate;
454 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
455 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
456 if (mode_rate > max_rate)
462 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
463 int link_rate, u8 lane_count)
465 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
468 index = intel_dp_rate_index(intel_dp->common_rates,
469 intel_dp->num_common_rates,
472 if (intel_dp_is_edp(intel_dp) &&
473 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
474 intel_dp->common_rates[index - 1],
476 drm_dbg_kms(&i915->drm,
477 "Retrying Link training for eDP with same parameters\n");
480 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
481 intel_dp->max_link_lane_count = lane_count;
482 } else if (lane_count > 1) {
483 if (intel_dp_is_edp(intel_dp) &&
484 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
485 intel_dp_max_common_rate(intel_dp),
487 drm_dbg_kms(&i915->drm,
488 "Retrying Link training for eDP with same parameters\n");
491 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
492 intel_dp->max_link_lane_count = lane_count >> 1;
494 drm_err(&i915->drm, "Link Training Unsuccessful\n");
501 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
503 return div_u64(mul_u32_u32(mode_clock, 1000000U),
504 DP_DSC_FEC_OVERHEAD_FACTOR);
508 small_joiner_ram_size_bits(struct drm_i915_private *i915)
510 if (INTEL_GEN(i915) >= 11)
516 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
517 u32 link_clock, u32 lane_count,
518 u32 mode_clock, u32 mode_hdisplay)
520 u32 bits_per_pixel, max_bpp_small_joiner_ram;
524 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
525 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
526 * for SST -> TimeSlotsPerMTP is 1,
527 * for MST -> TimeSlotsPerMTP has to be calculated
529 bits_per_pixel = (link_clock * lane_count * 8) /
530 intel_dp_mode_to_fec_clock(mode_clock);
531 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
533 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
534 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
536 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
537 max_bpp_small_joiner_ram);
540 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
541 * check, output bpp from small joiner RAM check)
543 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
545 /* Error out if the max bpp is less than smallest allowed valid bpp */
546 if (bits_per_pixel < valid_dsc_bpp[0]) {
547 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
548 bits_per_pixel, valid_dsc_bpp[0]);
552 /* Find the nearest match in the array of known BPPs from VESA */
553 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
554 if (bits_per_pixel < valid_dsc_bpp[i + 1])
557 bits_per_pixel = valid_dsc_bpp[i];
560 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
561 * fractional part is 0
563 return bits_per_pixel << 4;
566 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
567 int mode_clock, int mode_hdisplay)
569 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
570 u8 min_slice_count, i;
573 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
574 min_slice_count = DIV_ROUND_UP(mode_clock,
575 DP_DSC_MAX_ENC_THROUGHPUT_0);
577 min_slice_count = DIV_ROUND_UP(mode_clock,
578 DP_DSC_MAX_ENC_THROUGHPUT_1);
580 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
581 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
582 drm_dbg_kms(&i915->drm,
583 "Unsupported slice width %d by DP DSC Sink device\n",
587 /* Also take into account max slice width */
588 min_slice_count = min_t(u8, min_slice_count,
589 DIV_ROUND_UP(mode_hdisplay,
592 /* Find the closest match to the valid slice count values */
593 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
594 if (valid_dsc_slicecount[i] >
595 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
598 if (min_slice_count <= valid_dsc_slicecount[i])
599 return valid_dsc_slicecount[i];
602 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
607 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
611 * Older platforms don't like hdisplay==4096 with DP.
613 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
614 * and frame counter increment), but we don't get vblank interrupts,
615 * and the pipe underruns immediately. The link also doesn't seem
616 * to get trained properly.
618 * On CHV the vblank interrupts don't seem to disappear but
619 * otherwise the symptoms are similar.
621 * TODO: confirm the behaviour on HSW+
623 return hdisplay == 4096 && !HAS_DDI(dev_priv);
626 static enum drm_mode_status
627 intel_dp_mode_valid(struct drm_connector *connector,
628 struct drm_display_mode *mode)
630 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
631 struct intel_connector *intel_connector = to_intel_connector(connector);
632 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
633 struct drm_i915_private *dev_priv = to_i915(connector->dev);
634 int target_clock = mode->clock;
635 int max_rate, mode_rate, max_lanes, max_link_clock;
637 u16 dsc_max_output_bpp = 0;
638 u8 dsc_slice_count = 0;
640 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
641 return MODE_NO_DBLESCAN;
643 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
645 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
646 if (mode->hdisplay > fixed_mode->hdisplay)
649 if (mode->vdisplay > fixed_mode->vdisplay)
652 target_clock = fixed_mode->clock;
655 max_link_clock = intel_dp_max_link_rate(intel_dp);
656 max_lanes = intel_dp_max_lane_count(intel_dp);
658 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
659 mode_rate = intel_dp_link_required(target_clock, 18);
661 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
662 return MODE_H_ILLEGAL;
665 * Output bpp is stored in 6.4 format so right shift by 4 to get the
666 * integer value since we support only integer values of bpp.
668 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
669 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
670 if (intel_dp_is_edp(intel_dp)) {
672 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
674 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
676 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
678 intel_dp_dsc_get_output_bpp(dev_priv,
682 mode->hdisplay) >> 4;
684 intel_dp_dsc_get_slice_count(intel_dp,
690 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
691 target_clock > max_dotclk)
692 return MODE_CLOCK_HIGH;
694 if (mode->clock < 10000)
695 return MODE_CLOCK_LOW;
697 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
698 return MODE_H_ILLEGAL;
700 return intel_mode_valid_max_plane_size(dev_priv, mode);
703 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
710 for (i = 0; i < src_bytes; i++)
711 v |= ((u32)src[i]) << ((3 - i) * 8);
715 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
720 for (i = 0; i < dst_bytes; i++)
721 dst[i] = src >> ((3-i) * 8);
725 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
727 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
728 bool force_disable_vdd);
730 intel_dp_pps_init(struct intel_dp *intel_dp);
732 static intel_wakeref_t
733 pps_lock(struct intel_dp *intel_dp)
735 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
736 intel_wakeref_t wakeref;
739 * See intel_power_sequencer_reset() why we need
740 * a power domain reference here.
742 wakeref = intel_display_power_get(dev_priv,
743 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
745 mutex_lock(&dev_priv->pps_mutex);
750 static intel_wakeref_t
751 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
755 mutex_unlock(&dev_priv->pps_mutex);
756 intel_display_power_put(dev_priv,
757 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
762 #define with_pps_lock(dp, wf) \
763 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
766 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
768 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
769 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
770 enum pipe pipe = intel_dp->pps_pipe;
771 bool pll_enabled, release_cl_override = false;
772 enum dpio_phy phy = DPIO_PHY(pipe);
773 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
776 if (drm_WARN(&dev_priv->drm,
777 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
778 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
779 pipe_name(pipe), intel_dig_port->base.base.base.id,
780 intel_dig_port->base.base.name))
783 drm_dbg_kms(&dev_priv->drm,
784 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
785 pipe_name(pipe), intel_dig_port->base.base.base.id,
786 intel_dig_port->base.base.name);
788 /* Preserve the BIOS-computed detected bit. This is
789 * supposed to be read-only.
791 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
792 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
793 DP |= DP_PORT_WIDTH(1);
794 DP |= DP_LINK_TRAIN_PAT_1;
796 if (IS_CHERRYVIEW(dev_priv))
797 DP |= DP_PIPE_SEL_CHV(pipe);
799 DP |= DP_PIPE_SEL(pipe);
801 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
804 * The DPLL for the pipe must be enabled for this to work.
805 * So enable temporarily it if it's not already enabled.
808 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
809 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
811 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
812 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
813 drm_err(&dev_priv->drm,
814 "Failed to force on pll for pipe %c!\n",
821 * Similar magic as in intel_dp_enable_port().
822 * We _must_ do this port enable + disable trick
823 * to make this power sequencer lock onto the port.
824 * Otherwise even VDD force bit won't work.
826 intel_de_write(dev_priv, intel_dp->output_reg, DP);
827 intel_de_posting_read(dev_priv, intel_dp->output_reg);
829 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
830 intel_de_posting_read(dev_priv, intel_dp->output_reg);
832 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
833 intel_de_posting_read(dev_priv, intel_dp->output_reg);
836 vlv_force_pll_off(dev_priv, pipe);
838 if (release_cl_override)
839 chv_phy_powergate_ch(dev_priv, phy, ch, false);
843 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
845 struct intel_encoder *encoder;
846 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
849 * We don't have power sequencer currently.
850 * Pick one that's not used by other ports.
852 for_each_intel_dp(&dev_priv->drm, encoder) {
853 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
855 if (encoder->type == INTEL_OUTPUT_EDP) {
856 drm_WARN_ON(&dev_priv->drm,
857 intel_dp->active_pipe != INVALID_PIPE &&
858 intel_dp->active_pipe !=
861 if (intel_dp->pps_pipe != INVALID_PIPE)
862 pipes &= ~(1 << intel_dp->pps_pipe);
864 drm_WARN_ON(&dev_priv->drm,
865 intel_dp->pps_pipe != INVALID_PIPE);
867 if (intel_dp->active_pipe != INVALID_PIPE)
868 pipes &= ~(1 << intel_dp->active_pipe);
875 return ffs(pipes) - 1;
879 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
881 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
882 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
885 lockdep_assert_held(&dev_priv->pps_mutex);
887 /* We should never land here with regular DP ports */
888 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
890 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
891 intel_dp->active_pipe != intel_dp->pps_pipe);
893 if (intel_dp->pps_pipe != INVALID_PIPE)
894 return intel_dp->pps_pipe;
896 pipe = vlv_find_free_pps(dev_priv);
899 * Didn't find one. This should not happen since there
900 * are two power sequencers and up to two eDP ports.
902 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
905 vlv_steal_power_sequencer(dev_priv, pipe);
906 intel_dp->pps_pipe = pipe;
908 drm_dbg_kms(&dev_priv->drm,
909 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
910 pipe_name(intel_dp->pps_pipe),
911 intel_dig_port->base.base.base.id,
912 intel_dig_port->base.base.name);
914 /* init power sequencer on this pipe and port */
915 intel_dp_init_panel_power_sequencer(intel_dp);
916 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
919 * Even vdd force doesn't work until we've made
920 * the power sequencer lock in on the port.
922 vlv_power_sequencer_kick(intel_dp);
924 return intel_dp->pps_pipe;
928 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
930 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
931 int backlight_controller = dev_priv->vbt.backlight.controller;
933 lockdep_assert_held(&dev_priv->pps_mutex);
935 /* We should never land here with regular DP ports */
936 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
938 if (!intel_dp->pps_reset)
939 return backlight_controller;
941 intel_dp->pps_reset = false;
944 * Only the HW needs to be reprogrammed, the SW state is fixed and
945 * has been setup during connector init.
947 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
949 return backlight_controller;
952 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
955 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
958 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
961 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
964 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
967 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
974 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
976 vlv_pipe_check pipe_check)
980 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
981 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
982 PANEL_PORT_SELECT_MASK;
984 if (port_sel != PANEL_PORT_SELECT_VLV(port))
987 if (!pipe_check(dev_priv, pipe))
997 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
999 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1000 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1001 enum port port = intel_dig_port->base.port;
1003 lockdep_assert_held(&dev_priv->pps_mutex);
1005 /* try to find a pipe with this port selected */
1006 /* first pick one where the panel is on */
1007 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1008 vlv_pipe_has_pp_on);
1009 /* didn't find one? pick one where vdd is on */
1010 if (intel_dp->pps_pipe == INVALID_PIPE)
1011 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1012 vlv_pipe_has_vdd_on);
1013 /* didn't find one? pick one with just the correct port */
1014 if (intel_dp->pps_pipe == INVALID_PIPE)
1015 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1018 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1019 if (intel_dp->pps_pipe == INVALID_PIPE) {
1020 drm_dbg_kms(&dev_priv->drm,
1021 "no initial power sequencer for [ENCODER:%d:%s]\n",
1022 intel_dig_port->base.base.base.id,
1023 intel_dig_port->base.base.name);
1027 drm_dbg_kms(&dev_priv->drm,
1028 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1029 intel_dig_port->base.base.base.id,
1030 intel_dig_port->base.base.name,
1031 pipe_name(intel_dp->pps_pipe));
1033 intel_dp_init_panel_power_sequencer(intel_dp);
1034 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1037 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1039 struct intel_encoder *encoder;
1041 if (drm_WARN_ON(&dev_priv->drm,
1042 !(IS_VALLEYVIEW(dev_priv) ||
1043 IS_CHERRYVIEW(dev_priv) ||
1044 IS_GEN9_LP(dev_priv))))
1048 * We can't grab pps_mutex here due to deadlock with power_domain
1049 * mutex when power_domain functions are called while holding pps_mutex.
1050 * That also means that in order to use pps_pipe the code needs to
1051 * hold both a power domain reference and pps_mutex, and the power domain
1052 * reference get/put must be done while _not_ holding pps_mutex.
1053 * pps_{lock,unlock}() do these steps in the correct order, so one
1054 * should use them always.
1057 for_each_intel_dp(&dev_priv->drm, encoder) {
1058 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1060 drm_WARN_ON(&dev_priv->drm,
1061 intel_dp->active_pipe != INVALID_PIPE);
1063 if (encoder->type != INTEL_OUTPUT_EDP)
1066 if (IS_GEN9_LP(dev_priv))
1067 intel_dp->pps_reset = true;
1069 intel_dp->pps_pipe = INVALID_PIPE;
1073 struct pps_registers {
1081 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1082 struct pps_registers *regs)
1084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1087 memset(regs, 0, sizeof(*regs));
1089 if (IS_GEN9_LP(dev_priv))
1090 pps_idx = bxt_power_sequencer_idx(intel_dp);
1091 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1092 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1094 regs->pp_ctrl = PP_CONTROL(pps_idx);
1095 regs->pp_stat = PP_STATUS(pps_idx);
1096 regs->pp_on = PP_ON_DELAYS(pps_idx);
1097 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1099 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1100 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1101 regs->pp_div = INVALID_MMIO_REG;
1103 regs->pp_div = PP_DIVISOR(pps_idx);
1107 _pp_ctrl_reg(struct intel_dp *intel_dp)
1109 struct pps_registers regs;
1111 intel_pps_get_registers(intel_dp, ®s);
1113 return regs.pp_ctrl;
1117 _pp_stat_reg(struct intel_dp *intel_dp)
1119 struct pps_registers regs;
1121 intel_pps_get_registers(intel_dp, ®s);
1123 return regs.pp_stat;
1126 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1127 This function only applicable when panel PM state is not to be tracked */
1128 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1131 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1133 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1134 intel_wakeref_t wakeref;
1136 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1139 with_pps_lock(intel_dp, wakeref) {
1140 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1141 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1142 i915_reg_t pp_ctrl_reg, pp_div_reg;
1145 pp_ctrl_reg = PP_CONTROL(pipe);
1146 pp_div_reg = PP_DIVISOR(pipe);
1147 pp_div = intel_de_read(dev_priv, pp_div_reg);
1148 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1150 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1151 intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1152 intel_de_write(dev_priv, pp_ctrl_reg,
1154 msleep(intel_dp->panel_power_cycle_delay);
1161 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1163 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1165 lockdep_assert_held(&dev_priv->pps_mutex);
1167 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1168 intel_dp->pps_pipe == INVALID_PIPE)
1171 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1174 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1176 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1178 lockdep_assert_held(&dev_priv->pps_mutex);
1180 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1181 intel_dp->pps_pipe == INVALID_PIPE)
1184 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1188 intel_dp_check_edp(struct intel_dp *intel_dp)
1190 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1192 if (!intel_dp_is_edp(intel_dp))
1195 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1196 drm_WARN(&dev_priv->drm, 1,
1197 "eDP powered off while attempting aux channel communication.\n");
1198 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1199 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1200 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1205 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1207 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1208 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1209 const unsigned int timeout_ms = 10;
1213 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1214 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1215 msecs_to_jiffies_timeout(timeout_ms));
1217 /* just trace the final value */
1218 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1222 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1223 intel_dp->aux.name, timeout_ms, status);
1229 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1231 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237 * The clock divider is based off the hrawclk, and would like to run at
1238 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1240 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1243 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1245 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1246 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1253 * The clock divider is based off the cdclk or PCH rawclk, and would
1254 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1255 * divide by 2000 and use that
1257 if (dig_port->aux_ch == AUX_CH_A)
1258 freq = dev_priv->cdclk.hw.cdclk;
1260 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1261 return DIV_ROUND_CLOSEST(freq, 2000);
1264 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1266 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1267 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1269 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1270 /* Workaround for non-ULT HSW */
1278 return ilk_get_aux_clock_divider(intel_dp, index);
1281 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1284 * SKL doesn't need us to program the AUX clock divider (Hardware will
1285 * derive the clock from CDCLK automatically). We still implement the
1286 * get_aux_clock_divider vfunc to plug-in into the existing code.
1288 return index ? 0 : 1;
1291 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1293 u32 aux_clock_divider)
1295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296 struct drm_i915_private *dev_priv =
1297 to_i915(intel_dig_port->base.base.dev);
1298 u32 precharge, timeout;
1300 if (IS_GEN(dev_priv, 6))
1305 if (IS_BROADWELL(dev_priv))
1306 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1308 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1310 return DP_AUX_CH_CTL_SEND_BUSY |
1311 DP_AUX_CH_CTL_DONE |
1312 DP_AUX_CH_CTL_INTERRUPT |
1313 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1315 DP_AUX_CH_CTL_RECEIVE_ERROR |
1316 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1317 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1318 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1321 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1326 struct drm_i915_private *i915 =
1327 to_i915(intel_dig_port->base.base.dev);
1328 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1331 ret = DP_AUX_CH_CTL_SEND_BUSY |
1332 DP_AUX_CH_CTL_DONE |
1333 DP_AUX_CH_CTL_INTERRUPT |
1334 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1335 DP_AUX_CH_CTL_TIME_OUT_MAX |
1336 DP_AUX_CH_CTL_RECEIVE_ERROR |
1337 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1338 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1339 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1341 if (intel_phy_is_tc(i915, phy) &&
1342 intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1343 ret |= DP_AUX_CH_CTL_TBT_IO;
1349 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1350 const u8 *send, int send_bytes,
1351 u8 *recv, int recv_size,
1352 u32 aux_send_ctl_flags)
1354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355 struct drm_i915_private *i915 =
1356 to_i915(intel_dig_port->base.base.dev);
1357 struct intel_uncore *uncore = &i915->uncore;
1358 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1359 bool is_tc_port = intel_phy_is_tc(i915, phy);
1360 i915_reg_t ch_ctl, ch_data[5];
1361 u32 aux_clock_divider;
1362 enum intel_display_power_domain aux_domain =
1363 intel_aux_power_domain(intel_dig_port);
1364 intel_wakeref_t aux_wakeref;
1365 intel_wakeref_t pps_wakeref;
1366 int i, ret, recv_bytes;
1371 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1372 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1373 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1376 intel_tc_port_lock(intel_dig_port);
1378 aux_wakeref = intel_display_power_get(i915, aux_domain);
1379 pps_wakeref = pps_lock(intel_dp);
1382 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1383 * In such cases we want to leave VDD enabled and it's up to upper layers
1384 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1387 vdd = edp_panel_vdd_on(intel_dp);
1389 /* dp aux is extremely sensitive to irq latency, hence request the
1390 * lowest possible wakeup latency and so prevent the cpu from going into
1391 * deep sleep states.
1393 cpu_latency_qos_update_request(&i915->pm_qos, 0);
1395 intel_dp_check_edp(intel_dp);
1397 /* Try to wait for any previous AUX channel activity */
1398 for (try = 0; try < 3; try++) {
1399 status = intel_uncore_read_notrace(uncore, ch_ctl);
1400 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1404 /* just trace the final value */
1405 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1408 const u32 status = intel_uncore_read(uncore, ch_ctl);
1410 if (status != intel_dp->aux_busy_last_status) {
1411 drm_WARN(&i915->drm, 1,
1412 "%s: not started (status 0x%08x)\n",
1413 intel_dp->aux.name, status);
1414 intel_dp->aux_busy_last_status = status;
1421 /* Only 5 data registers! */
1422 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1427 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1428 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1432 send_ctl |= aux_send_ctl_flags;
1434 /* Must try at least 3 times according to DP spec */
1435 for (try = 0; try < 5; try++) {
1436 /* Load the send data into the aux channel data registers */
1437 for (i = 0; i < send_bytes; i += 4)
1438 intel_uncore_write(uncore,
1440 intel_dp_pack_aux(send + i,
1443 /* Send the command and wait for it to complete */
1444 intel_uncore_write(uncore, ch_ctl, send_ctl);
1446 status = intel_dp_aux_wait_done(intel_dp);
1448 /* Clear done status and any errors */
1449 intel_uncore_write(uncore,
1452 DP_AUX_CH_CTL_DONE |
1453 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1454 DP_AUX_CH_CTL_RECEIVE_ERROR);
1456 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1457 * 400us delay required for errors and timeouts
1458 * Timeout errors from the HW already meet this
1459 * requirement so skip to next iteration
1461 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1464 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1465 usleep_range(400, 500);
1468 if (status & DP_AUX_CH_CTL_DONE)
1473 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1474 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1475 intel_dp->aux.name, status);
1481 /* Check for timeout or receive error.
1482 * Timeouts occur when the sink is not connected
1484 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1485 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1486 intel_dp->aux.name, status);
1491 /* Timeouts occur when the device isn't connected, so they're
1492 * "normal" -- don't fill the kernel log with these */
1493 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1494 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1495 intel_dp->aux.name, status);
1500 /* Unload any bytes sent back from the other side */
1501 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1502 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1505 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1506 * We have no idea of what happened so we return -EBUSY so
1507 * drm layer takes care for the necessary retries.
1509 if (recv_bytes == 0 || recv_bytes > 20) {
1510 drm_dbg_kms(&i915->drm,
1511 "%s: Forbidden recv_bytes = %d on aux transaction\n",
1512 intel_dp->aux.name, recv_bytes);
1517 if (recv_bytes > recv_size)
1518 recv_bytes = recv_size;
1520 for (i = 0; i < recv_bytes; i += 4)
1521 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1522 recv + i, recv_bytes - i);
1526 cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1529 edp_panel_vdd_off(intel_dp, false);
1531 pps_unlock(intel_dp, pps_wakeref);
1532 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1535 intel_tc_port_unlock(intel_dig_port);
1540 #define BARE_ADDRESS_SIZE 3
1541 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1544 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1545 const struct drm_dp_aux_msg *msg)
1547 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1548 txbuf[1] = (msg->address >> 8) & 0xff;
1549 txbuf[2] = msg->address & 0xff;
1550 txbuf[3] = msg->size - 1;
1554 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1556 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1557 u8 txbuf[20], rxbuf[20];
1558 size_t txsize, rxsize;
1561 intel_dp_aux_header(txbuf, msg);
1563 switch (msg->request & ~DP_AUX_I2C_MOT) {
1564 case DP_AUX_NATIVE_WRITE:
1565 case DP_AUX_I2C_WRITE:
1566 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1567 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1568 rxsize = 2; /* 0 or 1 data bytes */
1570 if (WARN_ON(txsize > 20))
1573 WARN_ON(!msg->buffer != !msg->size);
1576 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1578 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1581 msg->reply = rxbuf[0] >> 4;
1584 /* Number of bytes written in a short write. */
1585 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1587 /* Return payload size. */
1593 case DP_AUX_NATIVE_READ:
1594 case DP_AUX_I2C_READ:
1595 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1596 rxsize = msg->size + 1;
1598 if (WARN_ON(rxsize > 20))
1601 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1604 msg->reply = rxbuf[0] >> 4;
1606 * Assume happy day, and copy the data. The caller is
1607 * expected to check msg->reply before touching it.
1609 * Return payload size.
1612 memcpy(msg->buffer, rxbuf + 1, ret);
1625 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1627 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1628 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1629 enum aux_ch aux_ch = dig_port->aux_ch;
1635 return DP_AUX_CH_CTL(aux_ch);
1637 MISSING_CASE(aux_ch);
1638 return DP_AUX_CH_CTL(AUX_CH_B);
1642 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1644 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1645 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1646 enum aux_ch aux_ch = dig_port->aux_ch;
1652 return DP_AUX_CH_DATA(aux_ch, index);
1654 MISSING_CASE(aux_ch);
1655 return DP_AUX_CH_DATA(AUX_CH_B, index);
1659 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1661 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1662 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1663 enum aux_ch aux_ch = dig_port->aux_ch;
1667 return DP_AUX_CH_CTL(aux_ch);
1671 return PCH_DP_AUX_CH_CTL(aux_ch);
1673 MISSING_CASE(aux_ch);
1674 return DP_AUX_CH_CTL(AUX_CH_A);
1678 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1680 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1681 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1682 enum aux_ch aux_ch = dig_port->aux_ch;
1686 return DP_AUX_CH_DATA(aux_ch, index);
1690 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1692 MISSING_CASE(aux_ch);
1693 return DP_AUX_CH_DATA(AUX_CH_A, index);
1697 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1699 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1701 enum aux_ch aux_ch = dig_port->aux_ch;
1711 return DP_AUX_CH_CTL(aux_ch);
1713 MISSING_CASE(aux_ch);
1714 return DP_AUX_CH_CTL(AUX_CH_A);
1718 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1720 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1721 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1722 enum aux_ch aux_ch = dig_port->aux_ch;
1732 return DP_AUX_CH_DATA(aux_ch, index);
1734 MISSING_CASE(aux_ch);
1735 return DP_AUX_CH_DATA(AUX_CH_A, index);
1740 intel_dp_aux_fini(struct intel_dp *intel_dp)
1742 kfree(intel_dp->aux.name);
1746 intel_dp_aux_init(struct intel_dp *intel_dp)
1748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750 struct intel_encoder *encoder = &dig_port->base;
1752 if (INTEL_GEN(dev_priv) >= 9) {
1753 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1754 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1755 } else if (HAS_PCH_SPLIT(dev_priv)) {
1756 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1757 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1759 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1760 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1763 if (INTEL_GEN(dev_priv) >= 9)
1764 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1765 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1766 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1767 else if (HAS_PCH_SPLIT(dev_priv))
1768 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1770 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1772 if (INTEL_GEN(dev_priv) >= 9)
1773 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1775 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1777 drm_dp_aux_init(&intel_dp->aux);
1779 /* Failure to allocate our preferred name is not critical */
1780 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1781 aux_ch_name(dig_port->aux_ch),
1782 port_name(encoder->port));
1783 intel_dp->aux.transfer = intel_dp_aux_transfer;
1786 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1788 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1790 return max_rate >= 540000;
1793 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1795 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1797 return max_rate >= 810000;
1801 intel_dp_set_clock(struct intel_encoder *encoder,
1802 struct intel_crtc_state *pipe_config)
1804 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1805 const struct dp_link_dpll *divisor = NULL;
1808 if (IS_G4X(dev_priv)) {
1810 count = ARRAY_SIZE(g4x_dpll);
1811 } else if (HAS_PCH_SPLIT(dev_priv)) {
1813 count = ARRAY_SIZE(pch_dpll);
1814 } else if (IS_CHERRYVIEW(dev_priv)) {
1816 count = ARRAY_SIZE(chv_dpll);
1817 } else if (IS_VALLEYVIEW(dev_priv)) {
1819 count = ARRAY_SIZE(vlv_dpll);
1822 if (divisor && count) {
1823 for (i = 0; i < count; i++) {
1824 if (pipe_config->port_clock == divisor[i].clock) {
1825 pipe_config->dpll = divisor[i].dpll;
1826 pipe_config->clock_set = true;
1833 static void snprintf_int_array(char *str, size_t len,
1834 const int *array, int nelem)
1840 for (i = 0; i < nelem; i++) {
1841 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1849 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1851 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1852 char str[128]; /* FIXME: too big for stack? */
1854 if (!drm_debug_enabled(DRM_UT_KMS))
1857 snprintf_int_array(str, sizeof(str),
1858 intel_dp->source_rates, intel_dp->num_source_rates);
1859 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1861 snprintf_int_array(str, sizeof(str),
1862 intel_dp->sink_rates, intel_dp->num_sink_rates);
1863 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1865 snprintf_int_array(str, sizeof(str),
1866 intel_dp->common_rates, intel_dp->num_common_rates);
1867 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1871 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1875 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1876 if (WARN_ON(len <= 0))
1879 return intel_dp->common_rates[len - 1];
1882 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1884 int i = intel_dp_rate_index(intel_dp->sink_rates,
1885 intel_dp->num_sink_rates, rate);
1893 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1894 u8 *link_bw, u8 *rate_select)
1896 /* eDP 1.4 rate select method. */
1897 if (intel_dp->use_rate_select) {
1900 intel_dp_rate_select(intel_dp, port_clock);
1902 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1907 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1908 const struct intel_crtc_state *pipe_config)
1910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1912 /* On TGL, FEC is supported on all Pipes */
1913 if (INTEL_GEN(dev_priv) >= 12)
1916 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1922 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1923 const struct intel_crtc_state *pipe_config)
1925 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1926 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1929 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1930 const struct intel_crtc_state *crtc_state)
1932 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1934 if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1937 return intel_dsc_source_support(encoder, crtc_state) &&
1938 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1941 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1942 struct intel_crtc_state *pipe_config)
1944 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1945 struct intel_connector *intel_connector = intel_dp->attached_connector;
1948 bpp = pipe_config->pipe_bpp;
1949 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1952 bpp = min(bpp, 3*bpc);
1954 if (intel_dp_is_edp(intel_dp)) {
1955 /* Get bpp from vbt only for panels that dont have bpp in edid */
1956 if (intel_connector->base.display_info.bpc == 0 &&
1957 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1958 drm_dbg_kms(&dev_priv->drm,
1959 "clamping bpp for eDP panel to BIOS-provided %i\n",
1960 dev_priv->vbt.edp.bpp);
1961 bpp = dev_priv->vbt.edp.bpp;
1968 /* Adjust link config limits based on compliance test requests. */
1970 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1971 struct intel_crtc_state *pipe_config,
1972 struct link_config_limits *limits)
1974 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1976 /* For DP Compliance we override the computed bpp for the pipe */
1977 if (intel_dp->compliance.test_data.bpc != 0) {
1978 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1980 limits->min_bpp = limits->max_bpp = bpp;
1981 pipe_config->dither_force_disable = bpp == 6 * 3;
1983 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1986 /* Use values requested by Compliance Test Request */
1987 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1990 /* Validate the compliance test data since max values
1991 * might have changed due to link train fallback.
1993 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1994 intel_dp->compliance.test_lane_count)) {
1995 index = intel_dp_rate_index(intel_dp->common_rates,
1996 intel_dp->num_common_rates,
1997 intel_dp->compliance.test_link_rate);
1999 limits->min_clock = limits->max_clock = index;
2000 limits->min_lane_count = limits->max_lane_count =
2001 intel_dp->compliance.test_lane_count;
2006 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2009 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2010 * format of the number of bytes per pixel will be half the number
2011 * of bytes of RGB pixel.
2013 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2019 /* Optimize link config in order: max bpp, min clock, min lanes */
2021 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2022 struct intel_crtc_state *pipe_config,
2023 const struct link_config_limits *limits)
2025 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2026 int bpp, clock, lane_count;
2027 int mode_rate, link_clock, link_avail;
2029 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2030 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2032 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2035 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2036 for (lane_count = limits->min_lane_count;
2037 lane_count <= limits->max_lane_count;
2039 link_clock = intel_dp->common_rates[clock];
2040 link_avail = intel_dp_max_data_rate(link_clock,
2043 if (mode_rate <= link_avail) {
2044 pipe_config->lane_count = lane_count;
2045 pipe_config->pipe_bpp = bpp;
2046 pipe_config->port_clock = link_clock;
2057 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2060 u8 dsc_bpc[3] = {0};
2062 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2064 for (i = 0; i < num_bpc; i++) {
2065 if (dsc_max_bpc >= dsc_bpc[i])
2066 return dsc_bpc[i] * 3;
2072 #define DSC_SUPPORTED_VERSION_MIN 1
2074 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2075 struct intel_crtc_state *crtc_state)
2077 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2078 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2079 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2083 ret = intel_dsc_compute_params(encoder, crtc_state);
2088 * Slice Height of 8 works for all currently available panels. So start
2089 * with that if pic_height is an integral multiple of 8. Eventually add
2090 * logic to try multiple slice heights.
2092 if (vdsc_cfg->pic_height % 8 == 0)
2093 vdsc_cfg->slice_height = 8;
2094 else if (vdsc_cfg->pic_height % 4 == 0)
2095 vdsc_cfg->slice_height = 4;
2097 vdsc_cfg->slice_height = 2;
2099 vdsc_cfg->dsc_version_major =
2100 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2101 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2102 vdsc_cfg->dsc_version_minor =
2103 min(DSC_SUPPORTED_VERSION_MIN,
2104 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2105 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2107 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2110 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2111 if (!line_buf_depth) {
2112 drm_dbg_kms(&i915->drm,
2113 "DSC Sink Line Buffer Depth invalid\n");
2117 if (vdsc_cfg->dsc_version_minor == 2)
2118 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2119 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2121 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2122 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2124 vdsc_cfg->block_pred_enable =
2125 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2126 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2128 return drm_dsc_compute_rc_parameters(vdsc_cfg);
2131 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2132 struct intel_crtc_state *pipe_config,
2133 struct drm_connector_state *conn_state,
2134 struct link_config_limits *limits)
2136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2137 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2138 const struct drm_display_mode *adjusted_mode =
2139 &pipe_config->hw.adjusted_mode;
2144 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2145 intel_dp_supports_fec(intel_dp, pipe_config);
2147 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2150 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2151 if (INTEL_GEN(dev_priv) >= 12)
2152 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2154 dsc_max_bpc = min_t(u8, 10,
2155 conn_state->max_requested_bpc);
2157 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2159 /* Min Input BPC for ICL+ is 8 */
2160 if (pipe_bpp < 8 * 3) {
2161 drm_dbg_kms(&dev_priv->drm,
2162 "No DSC support for less than 8bpc\n");
2167 * For now enable DSC for max bpp, max link rate, max lane count.
2168 * Optimize this later for the minimum possible link rate/lane count
2169 * with DSC enabled for the requested mode.
2171 pipe_config->pipe_bpp = pipe_bpp;
2172 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2173 pipe_config->lane_count = limits->max_lane_count;
2175 if (intel_dp_is_edp(intel_dp)) {
2176 pipe_config->dsc.compressed_bpp =
2177 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2178 pipe_config->pipe_bpp);
2179 pipe_config->dsc.slice_count =
2180 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2183 u16 dsc_max_output_bpp;
2184 u8 dsc_dp_slice_count;
2186 dsc_max_output_bpp =
2187 intel_dp_dsc_get_output_bpp(dev_priv,
2188 pipe_config->port_clock,
2189 pipe_config->lane_count,
2190 adjusted_mode->crtc_clock,
2191 adjusted_mode->crtc_hdisplay);
2192 dsc_dp_slice_count =
2193 intel_dp_dsc_get_slice_count(intel_dp,
2194 adjusted_mode->crtc_clock,
2195 adjusted_mode->crtc_hdisplay);
2196 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2197 drm_dbg_kms(&dev_priv->drm,
2198 "Compressed BPP/Slice Count not supported\n");
2201 pipe_config->dsc.compressed_bpp = min_t(u16,
2202 dsc_max_output_bpp >> 4,
2203 pipe_config->pipe_bpp);
2204 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2207 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2208 * is greater than the maximum Cdclock and if slice count is even
2209 * then we need to use 2 VDSC instances.
2211 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2212 if (pipe_config->dsc.slice_count > 1) {
2213 pipe_config->dsc.dsc_split = true;
2215 drm_dbg_kms(&dev_priv->drm,
2216 "Cannot split stream to use 2 VDSC instances\n");
2221 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2223 drm_dbg_kms(&dev_priv->drm,
2224 "Cannot compute valid DSC parameters for Input Bpp = %d "
2225 "Compressed BPP = %d\n",
2226 pipe_config->pipe_bpp,
2227 pipe_config->dsc.compressed_bpp);
2231 pipe_config->dsc.compression_enable = true;
2232 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2233 "Compressed Bpp = %d Slice Count = %d\n",
2234 pipe_config->pipe_bpp,
2235 pipe_config->dsc.compressed_bpp,
2236 pipe_config->dsc.slice_count);
2241 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2243 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2250 intel_dp_compute_link_config(struct intel_encoder *encoder,
2251 struct intel_crtc_state *pipe_config,
2252 struct drm_connector_state *conn_state)
2254 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2255 const struct drm_display_mode *adjusted_mode =
2256 &pipe_config->hw.adjusted_mode;
2257 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2258 struct link_config_limits limits;
2262 common_len = intel_dp_common_len_rate_limit(intel_dp,
2263 intel_dp->max_link_rate);
2265 /* No common link rates between source and sink */
2266 drm_WARN_ON(encoder->base.dev, common_len <= 0);
2268 limits.min_clock = 0;
2269 limits.max_clock = common_len - 1;
2271 limits.min_lane_count = 1;
2272 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2274 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2275 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2277 if (intel_dp_is_edp(intel_dp)) {
2279 * Use the maximum clock and number of lanes the eDP panel
2280 * advertizes being capable of. The panels are generally
2281 * designed to support only a single clock and lane
2282 * configuration, and typically these values correspond to the
2283 * native resolution of the panel.
2285 limits.min_lane_count = limits.max_lane_count;
2286 limits.min_clock = limits.max_clock;
2289 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2291 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2292 "max rate %d max bpp %d pixel clock %iKHz\n",
2293 limits.max_lane_count,
2294 intel_dp->common_rates[limits.max_clock],
2295 limits.max_bpp, adjusted_mode->crtc_clock);
2298 * Optimize for slow and wide. This is the place to add alternative
2299 * optimization policy.
2301 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2303 /* enable compression if the mode doesn't fit available BW */
2304 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2305 if (ret || intel_dp->force_dsc_en) {
2306 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2307 conn_state, &limits);
2312 if (pipe_config->dsc.compression_enable) {
2313 drm_dbg_kms(&i915->drm,
2314 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2315 pipe_config->lane_count, pipe_config->port_clock,
2316 pipe_config->pipe_bpp,
2317 pipe_config->dsc.compressed_bpp);
2319 drm_dbg_kms(&i915->drm,
2320 "DP link rate required %i available %i\n",
2321 intel_dp_link_required(adjusted_mode->crtc_clock,
2322 pipe_config->dsc.compressed_bpp),
2323 intel_dp_max_data_rate(pipe_config->port_clock,
2324 pipe_config->lane_count));
2326 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2327 pipe_config->lane_count, pipe_config->port_clock,
2328 pipe_config->pipe_bpp);
2330 drm_dbg_kms(&i915->drm,
2331 "DP link rate required %i available %i\n",
2332 intel_dp_link_required(adjusted_mode->crtc_clock,
2333 pipe_config->pipe_bpp),
2334 intel_dp_max_data_rate(pipe_config->port_clock,
2335 pipe_config->lane_count));
2341 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2342 struct intel_crtc_state *crtc_state,
2343 const struct drm_connector_state *conn_state)
2345 struct drm_connector *connector = conn_state->connector;
2346 const struct drm_display_info *info = &connector->display_info;
2347 const struct drm_display_mode *adjusted_mode =
2348 &crtc_state->hw.adjusted_mode;
2350 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2351 !intel_dp_get_colorimetry_status(intel_dp) ||
2352 !connector->ycbcr_420_allowed)
2355 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2357 intel_pch_panel_fitting(crtc_state, conn_state);
2362 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2363 const struct drm_connector_state *conn_state)
2365 const struct intel_digital_connector_state *intel_conn_state =
2366 to_intel_digital_connector_state(conn_state);
2367 const struct drm_display_mode *adjusted_mode =
2368 &crtc_state->hw.adjusted_mode;
2371 * Our YCbCr output is always limited range.
2372 * crtc_state->limited_color_range only applies to RGB,
2373 * and it must never be set for YCbCr or we risk setting
2374 * some conflicting bits in PIPECONF which will mess up
2375 * the colors on the monitor.
2377 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2380 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2383 * CEA-861-E - 5.1 Default Encoding Parameters
2384 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2386 return crtc_state->pipe_bpp != 18 &&
2387 drm_default_rgb_quant_range(adjusted_mode) ==
2388 HDMI_QUANTIZATION_RANGE_LIMITED;
2390 return intel_conn_state->broadcast_rgb ==
2391 INTEL_BROADCAST_RGB_LIMITED;
2395 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2398 if (IS_G4X(dev_priv))
2400 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2406 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2407 const struct drm_connector_state *conn_state,
2408 struct drm_dp_vsc_sdp *vsc)
2410 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2414 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2415 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2416 * Colorimetry Format indication.
2418 vsc->revision = 0x5;
2421 /* DP 1.4a spec, Table 2-120 */
2422 switch (crtc_state->output_format) {
2423 case INTEL_OUTPUT_FORMAT_YCBCR444:
2424 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2426 case INTEL_OUTPUT_FORMAT_YCBCR420:
2427 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2429 case INTEL_OUTPUT_FORMAT_RGB:
2431 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2434 switch (conn_state->colorspace) {
2435 case DRM_MODE_COLORIMETRY_BT709_YCC:
2436 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2438 case DRM_MODE_COLORIMETRY_XVYCC_601:
2439 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2441 case DRM_MODE_COLORIMETRY_XVYCC_709:
2442 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2444 case DRM_MODE_COLORIMETRY_SYCC_601:
2445 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2447 case DRM_MODE_COLORIMETRY_OPYCC_601:
2448 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2450 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2451 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2453 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2454 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2456 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2457 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2459 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2460 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2461 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2465 * RGB->YCBCR color conversion uses the BT.709
2468 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2469 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2471 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2475 vsc->bpc = crtc_state->pipe_bpp / 3;
2477 /* only RGB pixelformat supports 6 bpc */
2478 drm_WARN_ON(&dev_priv->drm,
2479 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2481 /* all YCbCr are always limited range */
2482 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2483 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2486 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2487 struct intel_crtc_state *crtc_state,
2488 const struct drm_connector_state *conn_state)
2490 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2492 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2493 if (intel_psr_enabled(intel_dp))
2496 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2499 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2500 vsc->sdp_type = DP_SDP_VSC;
2501 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2502 &crtc_state->infoframes.vsc);
2506 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2507 struct intel_crtc_state *crtc_state,
2508 const struct drm_connector_state *conn_state)
2511 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2512 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2514 if (!conn_state->hdr_output_metadata)
2517 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2520 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2524 crtc_state->infoframes.enable |=
2525 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2529 intel_dp_compute_config(struct intel_encoder *encoder,
2530 struct intel_crtc_state *pipe_config,
2531 struct drm_connector_state *conn_state)
2533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2534 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2536 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2537 enum port port = encoder->port;
2538 struct intel_connector *intel_connector = intel_dp->attached_connector;
2539 struct intel_digital_connector_state *intel_conn_state =
2540 to_intel_digital_connector_state(conn_state);
2541 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2542 DP_DPCD_QUIRK_CONSTANT_N);
2543 int ret = 0, output_bpp;
2545 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2546 pipe_config->has_pch_encoder = true;
2548 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2551 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2553 ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
2558 pipe_config->has_drrs = false;
2559 if (!intel_dp_port_has_audio(dev_priv, port))
2560 pipe_config->has_audio = false;
2561 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2562 pipe_config->has_audio = intel_dp->has_audio;
2564 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2566 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2567 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2570 if (HAS_GMCH(dev_priv))
2571 intel_gmch_panel_fitting(pipe_config, conn_state);
2573 intel_pch_panel_fitting(pipe_config, conn_state);
2576 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2579 if (HAS_GMCH(dev_priv) &&
2580 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2583 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2586 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2589 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2593 pipe_config->limited_color_range =
2594 intel_dp_limited_color_range(pipe_config, conn_state);
2596 if (pipe_config->dsc.compression_enable)
2597 output_bpp = pipe_config->dsc.compressed_bpp;
2599 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2601 intel_link_compute_m_n(output_bpp,
2602 pipe_config->lane_count,
2603 adjusted_mode->crtc_clock,
2604 pipe_config->port_clock,
2605 &pipe_config->dp_m_n,
2606 constant_n, pipe_config->fec_enable);
2608 if (intel_connector->panel.downclock_mode != NULL &&
2609 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2610 pipe_config->has_drrs = true;
2611 intel_link_compute_m_n(output_bpp,
2612 pipe_config->lane_count,
2613 intel_connector->panel.downclock_mode->clock,
2614 pipe_config->port_clock,
2615 &pipe_config->dp_m2_n2,
2616 constant_n, pipe_config->fec_enable);
2619 if (!HAS_DDI(dev_priv))
2620 intel_dp_set_clock(encoder, pipe_config);
2622 intel_psr_compute_config(intel_dp, pipe_config);
2623 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2624 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2629 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2630 int link_rate, u8 lane_count,
2633 intel_dp->link_trained = false;
2634 intel_dp->link_rate = link_rate;
2635 intel_dp->lane_count = lane_count;
2636 intel_dp->link_mst = link_mst;
2639 static void intel_dp_prepare(struct intel_encoder *encoder,
2640 const struct intel_crtc_state *pipe_config)
2642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2643 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2644 enum port port = encoder->port;
2645 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2646 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2648 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2649 pipe_config->lane_count,
2650 intel_crtc_has_type(pipe_config,
2651 INTEL_OUTPUT_DP_MST));
2654 * There are four kinds of DP registers:
2661 * IBX PCH and CPU are the same for almost everything,
2662 * except that the CPU DP PLL is configured in this
2665 * CPT PCH is quite different, having many bits moved
2666 * to the TRANS_DP_CTL register instead. That
2667 * configuration happens (oddly) in ilk_pch_enable
2670 /* Preserve the BIOS-computed detected bit. This is
2671 * supposed to be read-only.
2673 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2675 /* Handle DP bits in common between all three register formats */
2676 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2677 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2679 /* Split out the IBX/CPU vs CPT settings */
2681 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2682 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2683 intel_dp->DP |= DP_SYNC_HS_HIGH;
2684 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2685 intel_dp->DP |= DP_SYNC_VS_HIGH;
2686 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2688 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2689 intel_dp->DP |= DP_ENHANCED_FRAMING;
2691 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2692 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2695 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2697 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2698 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2699 trans_dp |= TRANS_DP_ENH_FRAMING;
2701 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2702 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2704 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2705 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2707 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2708 intel_dp->DP |= DP_SYNC_HS_HIGH;
2709 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2710 intel_dp->DP |= DP_SYNC_VS_HIGH;
2711 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2713 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2714 intel_dp->DP |= DP_ENHANCED_FRAMING;
2716 if (IS_CHERRYVIEW(dev_priv))
2717 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2719 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2723 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2724 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2726 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2727 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2729 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2730 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2732 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2734 static void wait_panel_status(struct intel_dp *intel_dp,
2738 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2739 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2741 lockdep_assert_held(&dev_priv->pps_mutex);
2743 intel_pps_verify_state(intel_dp);
2745 pp_stat_reg = _pp_stat_reg(intel_dp);
2746 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2748 drm_dbg_kms(&dev_priv->drm,
2749 "mask %08x value %08x status %08x control %08x\n",
2751 intel_de_read(dev_priv, pp_stat_reg),
2752 intel_de_read(dev_priv, pp_ctrl_reg));
2754 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2756 drm_err(&dev_priv->drm,
2757 "Panel status timeout: status %08x control %08x\n",
2758 intel_de_read(dev_priv, pp_stat_reg),
2759 intel_de_read(dev_priv, pp_ctrl_reg));
2761 drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2764 static void wait_panel_on(struct intel_dp *intel_dp)
2766 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2768 drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2769 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2772 static void wait_panel_off(struct intel_dp *intel_dp)
2774 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2776 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2777 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2780 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2782 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2783 ktime_t panel_power_on_time;
2784 s64 panel_power_off_duration;
2786 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2788 /* take the difference of currrent time and panel power off time
2789 * and then make panel wait for t11_t12 if needed. */
2790 panel_power_on_time = ktime_get_boottime();
2791 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2793 /* When we disable the VDD override bit last we have to do the manual
2795 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2796 wait_remaining_ms_from_jiffies(jiffies,
2797 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2799 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2802 static void wait_backlight_on(struct intel_dp *intel_dp)
2804 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2805 intel_dp->backlight_on_delay);
2808 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2810 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2811 intel_dp->backlight_off_delay);
2814 /* Read the current pp_control value, unlocking the register if it
2818 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2820 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2823 lockdep_assert_held(&dev_priv->pps_mutex);
2825 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2826 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2827 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2828 control &= ~PANEL_UNLOCK_MASK;
2829 control |= PANEL_UNLOCK_REGS;
2835 * Must be paired with edp_panel_vdd_off().
2836 * Must hold pps_mutex around the whole on/off sequence.
2837 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2839 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2841 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2842 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2844 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2845 bool need_to_disable = !intel_dp->want_panel_vdd;
2847 lockdep_assert_held(&dev_priv->pps_mutex);
2849 if (!intel_dp_is_edp(intel_dp))
2852 cancel_delayed_work(&intel_dp->panel_vdd_work);
2853 intel_dp->want_panel_vdd = true;
2855 if (edp_have_panel_vdd(intel_dp))
2856 return need_to_disable;
2858 intel_display_power_get(dev_priv,
2859 intel_aux_power_domain(intel_dig_port));
2861 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2862 intel_dig_port->base.base.base.id,
2863 intel_dig_port->base.base.name);
2865 if (!edp_have_panel_power(intel_dp))
2866 wait_panel_power_cycle(intel_dp);
2868 pp = ilk_get_pp_control(intel_dp);
2869 pp |= EDP_FORCE_VDD;
2871 pp_stat_reg = _pp_stat_reg(intel_dp);
2872 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2874 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2875 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2876 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2877 intel_de_read(dev_priv, pp_stat_reg),
2878 intel_de_read(dev_priv, pp_ctrl_reg));
2880 * If the panel wasn't on, delay before accessing aux channel
2882 if (!edp_have_panel_power(intel_dp)) {
2883 drm_dbg_kms(&dev_priv->drm,
2884 "[ENCODER:%d:%s] panel power wasn't enabled\n",
2885 intel_dig_port->base.base.base.id,
2886 intel_dig_port->base.base.name);
2887 msleep(intel_dp->panel_power_up_delay);
2890 return need_to_disable;
2894 * Must be paired with intel_edp_panel_vdd_off() or
2895 * intel_edp_panel_off().
2896 * Nested calls to these functions are not allowed since
2897 * we drop the lock. Caller must use some higher level
2898 * locking to prevent nested calls from other threads.
2900 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2902 intel_wakeref_t wakeref;
2905 if (!intel_dp_is_edp(intel_dp))
2909 with_pps_lock(intel_dp, wakeref)
2910 vdd = edp_panel_vdd_on(intel_dp);
2911 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2912 dp_to_dig_port(intel_dp)->base.base.base.id,
2913 dp_to_dig_port(intel_dp)->base.base.name);
2916 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2918 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2919 struct intel_digital_port *intel_dig_port =
2920 dp_to_dig_port(intel_dp);
2922 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2924 lockdep_assert_held(&dev_priv->pps_mutex);
2926 drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2928 if (!edp_have_panel_vdd(intel_dp))
2931 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2932 intel_dig_port->base.base.base.id,
2933 intel_dig_port->base.base.name);
2935 pp = ilk_get_pp_control(intel_dp);
2936 pp &= ~EDP_FORCE_VDD;
2938 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2939 pp_stat_reg = _pp_stat_reg(intel_dp);
2941 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2942 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2944 /* Make sure sequencer is idle before allowing subsequent activity */
2945 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2946 intel_de_read(dev_priv, pp_stat_reg),
2947 intel_de_read(dev_priv, pp_ctrl_reg));
2949 if ((pp & PANEL_POWER_ON) == 0)
2950 intel_dp->panel_power_off_time = ktime_get_boottime();
2952 intel_display_power_put_unchecked(dev_priv,
2953 intel_aux_power_domain(intel_dig_port));
2956 static void edp_panel_vdd_work(struct work_struct *__work)
2958 struct intel_dp *intel_dp =
2959 container_of(to_delayed_work(__work),
2960 struct intel_dp, panel_vdd_work);
2961 intel_wakeref_t wakeref;
2963 with_pps_lock(intel_dp, wakeref) {
2964 if (!intel_dp->want_panel_vdd)
2965 edp_panel_vdd_off_sync(intel_dp);
2969 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2971 unsigned long delay;
2974 * Queue the timer to fire a long time from now (relative to the power
2975 * down delay) to keep the panel power up across a sequence of
2978 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2979 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2983 * Must be paired with edp_panel_vdd_on().
2984 * Must hold pps_mutex around the whole on/off sequence.
2985 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2987 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2989 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2991 lockdep_assert_held(&dev_priv->pps_mutex);
2993 if (!intel_dp_is_edp(intel_dp))
2996 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2997 dp_to_dig_port(intel_dp)->base.base.base.id,
2998 dp_to_dig_port(intel_dp)->base.base.name);
3000 intel_dp->want_panel_vdd = false;
3003 edp_panel_vdd_off_sync(intel_dp);
3005 edp_panel_vdd_schedule_off(intel_dp);
3008 static void edp_panel_on(struct intel_dp *intel_dp)
3010 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3012 i915_reg_t pp_ctrl_reg;
3014 lockdep_assert_held(&dev_priv->pps_mutex);
3016 if (!intel_dp_is_edp(intel_dp))
3019 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3020 dp_to_dig_port(intel_dp)->base.base.base.id,
3021 dp_to_dig_port(intel_dp)->base.base.name);
3023 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3024 "[ENCODER:%d:%s] panel power already on\n",
3025 dp_to_dig_port(intel_dp)->base.base.base.id,
3026 dp_to_dig_port(intel_dp)->base.base.name))
3029 wait_panel_power_cycle(intel_dp);
3031 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3032 pp = ilk_get_pp_control(intel_dp);
3033 if (IS_GEN(dev_priv, 5)) {
3034 /* ILK workaround: disable reset around power sequence */
3035 pp &= ~PANEL_POWER_RESET;
3036 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3037 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3040 pp |= PANEL_POWER_ON;
3041 if (!IS_GEN(dev_priv, 5))
3042 pp |= PANEL_POWER_RESET;
3044 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3045 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3047 wait_panel_on(intel_dp);
3048 intel_dp->last_power_on = jiffies;
3050 if (IS_GEN(dev_priv, 5)) {
3051 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3052 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3053 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3057 void intel_edp_panel_on(struct intel_dp *intel_dp)
3059 intel_wakeref_t wakeref;
3061 if (!intel_dp_is_edp(intel_dp))
3064 with_pps_lock(intel_dp, wakeref)
3065 edp_panel_on(intel_dp);
3069 static void edp_panel_off(struct intel_dp *intel_dp)
3071 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3072 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3074 i915_reg_t pp_ctrl_reg;
3076 lockdep_assert_held(&dev_priv->pps_mutex);
3078 if (!intel_dp_is_edp(intel_dp))
3081 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3082 dig_port->base.base.base.id, dig_port->base.base.name);
3084 drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3085 "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3086 dig_port->base.base.base.id, dig_port->base.base.name);
3088 pp = ilk_get_pp_control(intel_dp);
3089 /* We need to switch off panel power _and_ force vdd, for otherwise some
3090 * panels get very unhappy and cease to work. */
3091 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3094 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3096 intel_dp->want_panel_vdd = false;
3098 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3099 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3101 wait_panel_off(intel_dp);
3102 intel_dp->panel_power_off_time = ktime_get_boottime();
3104 /* We got a reference when we enabled the VDD. */
3105 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3108 void intel_edp_panel_off(struct intel_dp *intel_dp)
3110 intel_wakeref_t wakeref;
3112 if (!intel_dp_is_edp(intel_dp))
3115 with_pps_lock(intel_dp, wakeref)
3116 edp_panel_off(intel_dp);
3119 /* Enable backlight in the panel power control. */
3120 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3122 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3123 intel_wakeref_t wakeref;
3126 * If we enable the backlight right away following a panel power
3127 * on, we may see slight flicker as the panel syncs with the eDP
3128 * link. So delay a bit to make sure the image is solid before
3129 * allowing it to appear.
3131 wait_backlight_on(intel_dp);
3133 with_pps_lock(intel_dp, wakeref) {
3134 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3137 pp = ilk_get_pp_control(intel_dp);
3138 pp |= EDP_BLC_ENABLE;
3140 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3141 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3145 /* Enable backlight PWM and backlight PP control. */
3146 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3147 const struct drm_connector_state *conn_state)
3149 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3150 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3152 if (!intel_dp_is_edp(intel_dp))
3155 drm_dbg_kms(&i915->drm, "\n");
3157 intel_panel_enable_backlight(crtc_state, conn_state);
3158 _intel_edp_backlight_on(intel_dp);
3161 /* Disable backlight in the panel power control. */
3162 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3164 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3165 intel_wakeref_t wakeref;
3167 if (!intel_dp_is_edp(intel_dp))
3170 with_pps_lock(intel_dp, wakeref) {
3171 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3174 pp = ilk_get_pp_control(intel_dp);
3175 pp &= ~EDP_BLC_ENABLE;
3177 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3178 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3181 intel_dp->last_backlight_off = jiffies;
3182 edp_wait_backlight_off(intel_dp);
3185 /* Disable backlight PP control and backlight PWM. */
3186 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3188 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3189 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3191 if (!intel_dp_is_edp(intel_dp))
3194 drm_dbg_kms(&i915->drm, "\n");
3196 _intel_edp_backlight_off(intel_dp);
3197 intel_panel_disable_backlight(old_conn_state);
3201 * Hook for controlling the panel power control backlight through the bl_power
3202 * sysfs attribute. Take care to handle multiple calls.
3204 static void intel_edp_backlight_power(struct intel_connector *connector,
3207 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3208 struct intel_dp *intel_dp = intel_attached_dp(connector);
3209 intel_wakeref_t wakeref;
3213 with_pps_lock(intel_dp, wakeref)
3214 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3215 if (is_enabled == enable)
3218 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3219 enable ? "enable" : "disable");
3222 _intel_edp_backlight_on(intel_dp);
3224 _intel_edp_backlight_off(intel_dp);
3227 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3229 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3230 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3231 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3233 I915_STATE_WARN(cur_state != state,
3234 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3235 dig_port->base.base.base.id, dig_port->base.base.name,
3236 onoff(state), onoff(cur_state));
3238 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3240 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3242 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3244 I915_STATE_WARN(cur_state != state,
3245 "eDP PLL state assertion failure (expected %s, current %s)\n",
3246 onoff(state), onoff(cur_state));
3248 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3249 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3251 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3252 const struct intel_crtc_state *pipe_config)
3254 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3255 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3257 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3258 assert_dp_port_disabled(intel_dp);
3259 assert_edp_pll_disabled(dev_priv);
3261 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3262 pipe_config->port_clock);
3264 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3266 if (pipe_config->port_clock == 162000)
3267 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3269 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3271 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3272 intel_de_posting_read(dev_priv, DP_A);
3276 * [DevILK] Work around required when enabling DP PLL
3277 * while a pipe is enabled going to FDI:
3278 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3279 * 2. Program DP PLL enable
3281 if (IS_GEN(dev_priv, 5))
3282 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3284 intel_dp->DP |= DP_PLL_ENABLE;
3286 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3287 intel_de_posting_read(dev_priv, DP_A);
3291 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3292 const struct intel_crtc_state *old_crtc_state)
3294 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3297 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3298 assert_dp_port_disabled(intel_dp);
3299 assert_edp_pll_enabled(dev_priv);
3301 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3303 intel_dp->DP &= ~DP_PLL_ENABLE;
3305 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3306 intel_de_posting_read(dev_priv, DP_A);
3310 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3313 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3314 * be capable of signalling downstream hpd with a long pulse.
3315 * Whether or not that means D3 is safe to use is not clear,
3316 * but let's assume so until proven otherwise.
3318 * FIXME should really check all downstream ports...
3320 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3321 drm_dp_is_branch(intel_dp->dpcd) &&
3322 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3325 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3326 const struct intel_crtc_state *crtc_state,
3329 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3332 if (!crtc_state->dsc.compression_enable)
3335 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3336 enable ? DP_DECOMPRESSION_EN : 0);
3338 drm_dbg_kms(&i915->drm,
3339 "Failed to %s sink decompression state\n",
3340 enable ? "enable" : "disable");
3343 /* If the sink supports it, try to set the power state appropriately */
3344 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3346 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3349 /* Should have a valid DPCD by this point */
3350 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3353 if (mode != DRM_MODE_DPMS_ON) {
3354 if (downstream_hpd_needs_d0(intel_dp))
3357 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3360 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3363 * When turning on, we need to retry for 1ms to give the sink
3366 for (i = 0; i < 3; i++) {
3367 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3374 if (ret == 1 && lspcon->active)
3375 lspcon_wait_pcon_mode(lspcon);
3379 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3380 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3383 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3384 enum port port, enum pipe *pipe)
3388 for_each_pipe(dev_priv, p) {
3389 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3391 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3397 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3400 /* must initialize pipe to something for the asserts */
3406 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3407 i915_reg_t dp_reg, enum port port,
3413 val = intel_de_read(dev_priv, dp_reg);
3415 ret = val & DP_PORT_EN;
3417 /* asserts want to know the pipe even if the port is disabled */
3418 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3419 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3420 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3421 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3422 else if (IS_CHERRYVIEW(dev_priv))
3423 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3425 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3430 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3434 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3435 intel_wakeref_t wakeref;
3438 wakeref = intel_display_power_get_if_enabled(dev_priv,
3439 encoder->power_domain);
3443 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3444 encoder->port, pipe);
3446 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3451 static void intel_dp_get_config(struct intel_encoder *encoder,
3452 struct intel_crtc_state *pipe_config)
3454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3457 enum port port = encoder->port;
3458 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3460 if (encoder->type == INTEL_OUTPUT_EDP)
3461 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3463 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3465 tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3467 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3469 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3470 u32 trans_dp = intel_de_read(dev_priv,
3471 TRANS_DP_CTL(crtc->pipe));
3473 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3474 flags |= DRM_MODE_FLAG_PHSYNC;
3476 flags |= DRM_MODE_FLAG_NHSYNC;
3478 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3479 flags |= DRM_MODE_FLAG_PVSYNC;
3481 flags |= DRM_MODE_FLAG_NVSYNC;
3483 if (tmp & DP_SYNC_HS_HIGH)
3484 flags |= DRM_MODE_FLAG_PHSYNC;
3486 flags |= DRM_MODE_FLAG_NHSYNC;
3488 if (tmp & DP_SYNC_VS_HIGH)
3489 flags |= DRM_MODE_FLAG_PVSYNC;
3491 flags |= DRM_MODE_FLAG_NVSYNC;
3494 pipe_config->hw.adjusted_mode.flags |= flags;
3496 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3497 pipe_config->limited_color_range = true;
3499 pipe_config->lane_count =
3500 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3502 intel_dp_get_m_n(crtc, pipe_config);
3504 if (port == PORT_A) {
3505 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3506 pipe_config->port_clock = 162000;
3508 pipe_config->port_clock = 270000;
3511 pipe_config->hw.adjusted_mode.crtc_clock =
3512 intel_dotclock_calculate(pipe_config->port_clock,
3513 &pipe_config->dp_m_n);
3515 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3516 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3518 * This is a big fat ugly hack.
3520 * Some machines in UEFI boot mode provide us a VBT that has 18
3521 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3522 * unknown we fail to light up. Yet the same BIOS boots up with
3523 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3524 * max, not what it tells us to use.
3526 * Note: This will still be broken if the eDP panel is not lit
3527 * up by the BIOS, and thus we can't get the mode at module
3530 drm_dbg_kms(&dev_priv->drm,
3531 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3532 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3533 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3537 static void intel_disable_dp(struct intel_atomic_state *state,
3538 struct intel_encoder *encoder,
3539 const struct intel_crtc_state *old_crtc_state,
3540 const struct drm_connector_state *old_conn_state)
3542 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3544 intel_dp->link_trained = false;
3546 if (old_crtc_state->has_audio)
3547 intel_audio_codec_disable(encoder,
3548 old_crtc_state, old_conn_state);
3550 /* Make sure the panel is off before trying to change the mode. But also
3551 * ensure that we have vdd while we switch off the panel. */
3552 intel_edp_panel_vdd_on(intel_dp);
3553 intel_edp_backlight_off(old_conn_state);
3554 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3555 intel_edp_panel_off(intel_dp);
3558 static void g4x_disable_dp(struct intel_atomic_state *state,
3559 struct intel_encoder *encoder,
3560 const struct intel_crtc_state *old_crtc_state,
3561 const struct drm_connector_state *old_conn_state)
3563 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3566 static void vlv_disable_dp(struct intel_atomic_state *state,
3567 struct intel_encoder *encoder,
3568 const struct intel_crtc_state *old_crtc_state,
3569 const struct drm_connector_state *old_conn_state)
3571 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3574 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3575 struct intel_encoder *encoder,
3576 const struct intel_crtc_state *old_crtc_state,
3577 const struct drm_connector_state *old_conn_state)
3579 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3580 enum port port = encoder->port;
3583 * Bspec does not list a specific disable sequence for g4x DP.
3584 * Follow the ilk+ sequence (disable pipe before the port) for
3585 * g4x DP as it does not suffer from underruns like the normal
3586 * g4x modeset sequence (disable pipe after the port).
3588 intel_dp_link_down(encoder, old_crtc_state);
3590 /* Only ilk+ has port A */
3592 ilk_edp_pll_off(intel_dp, old_crtc_state);
3595 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3596 struct intel_encoder *encoder,
3597 const struct intel_crtc_state *old_crtc_state,
3598 const struct drm_connector_state *old_conn_state)
3600 intel_dp_link_down(encoder, old_crtc_state);
3603 static void chv_post_disable_dp(struct intel_atomic_state *state,
3604 struct intel_encoder *encoder,
3605 const struct intel_crtc_state *old_crtc_state,
3606 const struct drm_connector_state *old_conn_state)
3608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3610 intel_dp_link_down(encoder, old_crtc_state);
3612 vlv_dpio_get(dev_priv);
3614 /* Assert data lane reset */
3615 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3617 vlv_dpio_put(dev_priv);
3621 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3625 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3626 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3627 enum port port = intel_dig_port->base.port;
3628 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3630 if (dp_train_pat & train_pat_mask)
3631 drm_dbg_kms(&dev_priv->drm,
3632 "Using DP training pattern TPS%d\n",
3633 dp_train_pat & train_pat_mask);
3635 if (HAS_DDI(dev_priv)) {
3636 u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3638 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3639 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3641 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3643 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3644 switch (dp_train_pat & train_pat_mask) {
3645 case DP_TRAINING_PATTERN_DISABLE:
3646 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3649 case DP_TRAINING_PATTERN_1:
3650 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3652 case DP_TRAINING_PATTERN_2:
3653 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3655 case DP_TRAINING_PATTERN_3:
3656 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3658 case DP_TRAINING_PATTERN_4:
3659 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3662 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3664 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3665 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3666 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3668 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3669 case DP_TRAINING_PATTERN_DISABLE:
3670 *DP |= DP_LINK_TRAIN_OFF_CPT;
3672 case DP_TRAINING_PATTERN_1:
3673 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3675 case DP_TRAINING_PATTERN_2:
3676 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3678 case DP_TRAINING_PATTERN_3:
3679 drm_dbg_kms(&dev_priv->drm,
3680 "TPS3 not supported, using TPS2 instead\n");
3681 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3686 *DP &= ~DP_LINK_TRAIN_MASK;
3688 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3689 case DP_TRAINING_PATTERN_DISABLE:
3690 *DP |= DP_LINK_TRAIN_OFF;
3692 case DP_TRAINING_PATTERN_1:
3693 *DP |= DP_LINK_TRAIN_PAT_1;
3695 case DP_TRAINING_PATTERN_2:
3696 *DP |= DP_LINK_TRAIN_PAT_2;
3698 case DP_TRAINING_PATTERN_3:
3699 drm_dbg_kms(&dev_priv->drm,
3700 "TPS3 not supported, using TPS2 instead\n");
3701 *DP |= DP_LINK_TRAIN_PAT_2;
3707 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3708 const struct intel_crtc_state *old_crtc_state)
3710 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3712 /* enable with pattern 1 (as per spec) */
3714 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3717 * Magic for VLV/CHV. We _must_ first set up the register
3718 * without actually enabling the port, and then do another
3719 * write to enable the port. Otherwise link training will
3720 * fail when the power sequencer is freshly used for this port.
3722 intel_dp->DP |= DP_PORT_EN;
3723 if (old_crtc_state->has_audio)
3724 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3726 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3727 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3730 static void intel_enable_dp(struct intel_atomic_state *state,
3731 struct intel_encoder *encoder,
3732 const struct intel_crtc_state *pipe_config,
3733 const struct drm_connector_state *conn_state)
3735 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3736 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3737 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3738 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3739 enum pipe pipe = crtc->pipe;
3740 intel_wakeref_t wakeref;
3742 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3745 with_pps_lock(intel_dp, wakeref) {
3746 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3747 vlv_init_panel_power_sequencer(encoder, pipe_config);
3749 intel_dp_enable_port(intel_dp, pipe_config);
3751 edp_panel_vdd_on(intel_dp);
3752 edp_panel_on(intel_dp);
3753 edp_panel_vdd_off(intel_dp, true);
3756 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3757 unsigned int lane_mask = 0x0;
3759 if (IS_CHERRYVIEW(dev_priv))
3760 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3762 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3766 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3767 intel_dp_start_link_train(intel_dp);
3768 intel_dp_stop_link_train(intel_dp);
3770 if (pipe_config->has_audio) {
3771 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3773 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3777 static void g4x_enable_dp(struct intel_atomic_state *state,
3778 struct intel_encoder *encoder,
3779 const struct intel_crtc_state *pipe_config,
3780 const struct drm_connector_state *conn_state)
3782 intel_enable_dp(state, encoder, pipe_config, conn_state);
3783 intel_edp_backlight_on(pipe_config, conn_state);
3786 static void vlv_enable_dp(struct intel_atomic_state *state,
3787 struct intel_encoder *encoder,
3788 const struct intel_crtc_state *pipe_config,
3789 const struct drm_connector_state *conn_state)
3791 intel_edp_backlight_on(pipe_config, conn_state);
3794 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3795 struct intel_encoder *encoder,
3796 const struct intel_crtc_state *pipe_config,
3797 const struct drm_connector_state *conn_state)
3799 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3800 enum port port = encoder->port;
3802 intel_dp_prepare(encoder, pipe_config);
3804 /* Only ilk+ has port A */
3806 ilk_edp_pll_on(intel_dp, pipe_config);
3809 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3812 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3813 enum pipe pipe = intel_dp->pps_pipe;
3814 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3816 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3818 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3821 edp_panel_vdd_off_sync(intel_dp);
3824 * VLV seems to get confused when multiple power sequencers
3825 * have the same port selected (even if only one has power/vdd
3826 * enabled). The failure manifests as vlv_wait_port_ready() failing
3827 * CHV on the other hand doesn't seem to mind having the same port
3828 * selected in multiple power sequencers, but let's clear the
3829 * port select always when logically disconnecting a power sequencer
3832 drm_dbg_kms(&dev_priv->drm,
3833 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3834 pipe_name(pipe), intel_dig_port->base.base.base.id,
3835 intel_dig_port->base.base.name);
3836 intel_de_write(dev_priv, pp_on_reg, 0);
3837 intel_de_posting_read(dev_priv, pp_on_reg);
3839 intel_dp->pps_pipe = INVALID_PIPE;
3842 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3845 struct intel_encoder *encoder;
3847 lockdep_assert_held(&dev_priv->pps_mutex);
3849 for_each_intel_dp(&dev_priv->drm, encoder) {
3850 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3852 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3853 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3854 pipe_name(pipe), encoder->base.base.id,
3855 encoder->base.name);
3857 if (intel_dp->pps_pipe != pipe)
3860 drm_dbg_kms(&dev_priv->drm,
3861 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3862 pipe_name(pipe), encoder->base.base.id,
3863 encoder->base.name);
3865 /* make sure vdd is off before we steal it */
3866 vlv_detach_power_sequencer(intel_dp);
3870 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3871 const struct intel_crtc_state *crtc_state)
3873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3877 lockdep_assert_held(&dev_priv->pps_mutex);
3879 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3881 if (intel_dp->pps_pipe != INVALID_PIPE &&
3882 intel_dp->pps_pipe != crtc->pipe) {
3884 * If another power sequencer was being used on this
3885 * port previously make sure to turn off vdd there while
3886 * we still have control of it.
3888 vlv_detach_power_sequencer(intel_dp);
3892 * We may be stealing the power
3893 * sequencer from another port.
3895 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3897 intel_dp->active_pipe = crtc->pipe;
3899 if (!intel_dp_is_edp(intel_dp))
3902 /* now it's all ours */
3903 intel_dp->pps_pipe = crtc->pipe;
3905 drm_dbg_kms(&dev_priv->drm,
3906 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3907 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3908 encoder->base.name);
3910 /* init power sequencer on this pipe and port */
3911 intel_dp_init_panel_power_sequencer(intel_dp);
3912 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3915 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3916 struct intel_encoder *encoder,
3917 const struct intel_crtc_state *pipe_config,
3918 const struct drm_connector_state *conn_state)
3920 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3922 intel_enable_dp(state, encoder, pipe_config, conn_state);
3925 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3926 struct intel_encoder *encoder,
3927 const struct intel_crtc_state *pipe_config,
3928 const struct drm_connector_state *conn_state)
3930 intel_dp_prepare(encoder, pipe_config);
3932 vlv_phy_pre_pll_enable(encoder, pipe_config);
3935 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3936 struct intel_encoder *encoder,
3937 const struct intel_crtc_state *pipe_config,
3938 const struct drm_connector_state *conn_state)
3940 chv_phy_pre_encoder_enable(encoder, pipe_config);
3942 intel_enable_dp(state, encoder, pipe_config, conn_state);
3944 /* Second common lane will stay alive on its own now */
3945 chv_phy_release_cl2_override(encoder);
3948 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3949 struct intel_encoder *encoder,
3950 const struct intel_crtc_state *pipe_config,
3951 const struct drm_connector_state *conn_state)
3953 intel_dp_prepare(encoder, pipe_config);
3955 chv_phy_pre_pll_enable(encoder, pipe_config);
3958 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3959 struct intel_encoder *encoder,
3960 const struct intel_crtc_state *old_crtc_state,
3961 const struct drm_connector_state *old_conn_state)
3963 chv_phy_post_pll_disable(encoder, old_crtc_state);
3967 * Fetch AUX CH registers 0x202 - 0x207 which contain
3968 * link status information
3971 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3973 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3974 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3977 /* These are source-specific values. */
3979 intel_dp_voltage_max(struct intel_dp *intel_dp)
3981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3982 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3983 enum port port = encoder->port;
3985 if (HAS_DDI(dev_priv))
3986 return intel_ddi_dp_voltage_max(encoder);
3987 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3989 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3991 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3998 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4000 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4001 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4002 enum port port = encoder->port;
4004 if (HAS_DDI(dev_priv)) {
4005 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4006 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4007 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4009 return DP_TRAIN_PRE_EMPH_LEVEL_3;
4010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4011 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4013 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4016 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4018 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4021 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4024 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4026 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4029 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4031 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4033 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4035 return DP_TRAIN_PRE_EMPH_LEVEL_1;
4036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4038 return DP_TRAIN_PRE_EMPH_LEVEL_0;
4043 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
4045 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4046 unsigned long demph_reg_value, preemph_reg_value,
4047 uniqtranscale_reg_value;
4048 u8 train_set = intel_dp->train_set[0];
4050 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4051 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4052 preemph_reg_value = 0x0004000;
4053 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4055 demph_reg_value = 0x2B405555;
4056 uniqtranscale_reg_value = 0x552AB83A;
4058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4059 demph_reg_value = 0x2B404040;
4060 uniqtranscale_reg_value = 0x5548B83A;
4062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4063 demph_reg_value = 0x2B245555;
4064 uniqtranscale_reg_value = 0x5560B83A;
4066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4067 demph_reg_value = 0x2B405555;
4068 uniqtranscale_reg_value = 0x5598DA3A;
4074 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4075 preemph_reg_value = 0x0002000;
4076 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4078 demph_reg_value = 0x2B404040;
4079 uniqtranscale_reg_value = 0x5552B83A;
4081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4082 demph_reg_value = 0x2B404848;
4083 uniqtranscale_reg_value = 0x5580B83A;
4085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4086 demph_reg_value = 0x2B404040;
4087 uniqtranscale_reg_value = 0x55ADDA3A;
4093 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4094 preemph_reg_value = 0x0000000;
4095 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4097 demph_reg_value = 0x2B305555;
4098 uniqtranscale_reg_value = 0x5570B83A;
4100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4101 demph_reg_value = 0x2B2B4040;
4102 uniqtranscale_reg_value = 0x55ADDA3A;
4108 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4109 preemph_reg_value = 0x0006000;
4110 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4112 demph_reg_value = 0x1B405555;
4113 uniqtranscale_reg_value = 0x55ADDA3A;
4123 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4124 uniqtranscale_reg_value, 0);
4129 static u32 chv_signal_levels(struct intel_dp *intel_dp)
4131 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4132 u32 deemph_reg_value, margin_reg_value;
4133 bool uniq_trans_scale = false;
4134 u8 train_set = intel_dp->train_set[0];
4136 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4137 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4140 deemph_reg_value = 128;
4141 margin_reg_value = 52;
4143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4144 deemph_reg_value = 128;
4145 margin_reg_value = 77;
4147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4148 deemph_reg_value = 128;
4149 margin_reg_value = 102;
4151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4152 deemph_reg_value = 128;
4153 margin_reg_value = 154;
4154 uniq_trans_scale = true;
4160 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4161 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4163 deemph_reg_value = 85;
4164 margin_reg_value = 78;
4166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4167 deemph_reg_value = 85;
4168 margin_reg_value = 116;
4170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4171 deemph_reg_value = 85;
4172 margin_reg_value = 154;
4178 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4179 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4181 deemph_reg_value = 64;
4182 margin_reg_value = 104;
4184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4185 deemph_reg_value = 64;
4186 margin_reg_value = 154;
4192 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4193 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4195 deemph_reg_value = 43;
4196 margin_reg_value = 154;
4206 chv_set_phy_signal_level(encoder, deemph_reg_value,
4207 margin_reg_value, uniq_trans_scale);
4213 g4x_signal_levels(u8 train_set)
4215 u32 signal_levels = 0;
4217 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4220 signal_levels |= DP_VOLTAGE_0_4;
4222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4223 signal_levels |= DP_VOLTAGE_0_6;
4225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4226 signal_levels |= DP_VOLTAGE_0_8;
4228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4229 signal_levels |= DP_VOLTAGE_1_2;
4232 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4233 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4235 signal_levels |= DP_PRE_EMPHASIS_0;
4237 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4238 signal_levels |= DP_PRE_EMPHASIS_3_5;
4240 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4241 signal_levels |= DP_PRE_EMPHASIS_6;
4243 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4244 signal_levels |= DP_PRE_EMPHASIS_9_5;
4247 return signal_levels;
4250 /* SNB CPU eDP voltage swing and pre-emphasis control */
4252 snb_cpu_edp_signal_levels(u8 train_set)
4254 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4255 DP_TRAIN_PRE_EMPHASIS_MASK);
4256 switch (signal_levels) {
4257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4259 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4261 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4264 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4267 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4270 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4272 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4273 "0x%x\n", signal_levels);
4274 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4278 /* IVB CPU eDP voltage swing and pre-emphasis control */
4280 ivb_cpu_edp_signal_levels(u8 train_set)
4282 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4283 DP_TRAIN_PRE_EMPHASIS_MASK);
4284 switch (signal_levels) {
4285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4286 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4288 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4290 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4293 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4295 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4298 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4300 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4303 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4304 "0x%x\n", signal_levels);
4305 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4310 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4312 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4314 enum port port = intel_dig_port->base.port;
4315 u32 signal_levels, mask = 0;
4316 u8 train_set = intel_dp->train_set[0];
4318 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4319 signal_levels = bxt_signal_levels(intel_dp);
4320 } else if (HAS_DDI(dev_priv)) {
4321 signal_levels = ddi_signal_levels(intel_dp);
4322 mask = DDI_BUF_EMP_MASK;
4323 } else if (IS_CHERRYVIEW(dev_priv)) {
4324 signal_levels = chv_signal_levels(intel_dp);
4325 } else if (IS_VALLEYVIEW(dev_priv)) {
4326 signal_levels = vlv_signal_levels(intel_dp);
4327 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4328 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4329 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4330 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4331 signal_levels = snb_cpu_edp_signal_levels(train_set);
4332 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4334 signal_levels = g4x_signal_levels(train_set);
4335 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4339 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4342 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4343 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4344 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4345 drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4346 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4347 DP_TRAIN_PRE_EMPHASIS_SHIFT,
4348 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4351 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4353 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4354 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4358 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4362 struct drm_i915_private *dev_priv =
4363 to_i915(intel_dig_port->base.base.dev);
4365 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4367 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4368 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4371 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4373 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4375 enum port port = intel_dig_port->base.port;
4378 if (!HAS_DDI(dev_priv))
4381 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4382 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4383 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4384 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4387 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4388 * reason we need to set idle transmission mode is to work around a HW
4389 * issue where we enable the pipe while not in idle link-training mode.
4390 * In this case there is requirement to wait for a minimum number of
4391 * idle patterns to be sent.
4393 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4396 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4397 DP_TP_STATUS_IDLE_DONE, 1))
4398 drm_err(&dev_priv->drm,
4399 "Timed out waiting for DP idle patterns\n");
4403 intel_dp_link_down(struct intel_encoder *encoder,
4404 const struct intel_crtc_state *old_crtc_state)
4406 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4407 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4408 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4409 enum port port = encoder->port;
4410 u32 DP = intel_dp->DP;
4412 if (drm_WARN_ON(&dev_priv->drm,
4413 (intel_de_read(dev_priv, intel_dp->output_reg) &
4417 drm_dbg_kms(&dev_priv->drm, "\n");
4419 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4420 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4421 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4422 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4424 DP &= ~DP_LINK_TRAIN_MASK;
4425 DP |= DP_LINK_TRAIN_PAT_IDLE;
4427 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4428 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4430 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4431 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4432 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4435 * HW workaround for IBX, we need to move the port
4436 * to transcoder A after disabling it to allow the
4437 * matching HDMI port to be enabled on transcoder A.
4439 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4441 * We get CPU/PCH FIFO underruns on the other pipe when
4442 * doing the workaround. Sweep them under the rug.
4444 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4445 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4447 /* always enable with pattern 1 (as per spec) */
4448 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4449 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4450 DP_LINK_TRAIN_PAT_1;
4451 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4452 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4455 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4456 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4458 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4459 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4460 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4463 msleep(intel_dp->panel_power_down_delay);
4467 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4468 intel_wakeref_t wakeref;
4470 with_pps_lock(intel_dp, wakeref)
4471 intel_dp->active_pipe = INVALID_PIPE;
4476 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4478 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4482 * Prior to DP1.3 the bit represented by
4483 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4484 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4485 * the true capability of the panel. The only way to check is to
4486 * then compare 0000h and 2200h.
4488 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4489 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4492 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4493 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4495 "DPCD failed read at extended capabilities\n");
4499 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4500 drm_dbg_kms(&i915->drm,
4501 "DPCD extended DPCD rev less than base DPCD rev\n");
4505 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4508 drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4509 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4511 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4515 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4517 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4519 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4520 sizeof(intel_dp->dpcd)) < 0)
4521 return false; /* aux transfer failed */
4523 intel_dp_extended_receiver_capabilities(intel_dp);
4525 drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4528 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4531 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4535 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4538 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4541 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4543 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4546 * Clear the cached register set to avoid using stale values
4547 * for the sinks that do not support DSC.
4549 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4551 /* Clear fec_capable to avoid using stale values */
4552 intel_dp->fec_capable = 0;
4554 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4555 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4556 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4557 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4559 sizeof(intel_dp->dsc_dpcd)) < 0)
4561 "Failed to read DPCD register 0x%x\n",
4564 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4565 (int)sizeof(intel_dp->dsc_dpcd),
4566 intel_dp->dsc_dpcd);
4568 /* FEC is supported only on DP 1.4 */
4569 if (!intel_dp_is_edp(intel_dp) &&
4570 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4571 &intel_dp->fec_capable) < 0)
4573 "Failed to read FEC DPCD register\n");
4575 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4576 intel_dp->fec_capable);
4581 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4583 struct drm_i915_private *dev_priv =
4584 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4586 /* this function is meant to be called only once */
4587 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4589 if (!intel_dp_read_dpcd(intel_dp))
4592 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4593 drm_dp_is_branch(intel_dp->dpcd));
4596 * Read the eDP display control registers.
4598 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4599 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4600 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4601 * method). The display control registers should read zero if they're
4602 * not supported anyway.
4604 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4605 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4606 sizeof(intel_dp->edp_dpcd))
4607 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4608 (int)sizeof(intel_dp->edp_dpcd),
4609 intel_dp->edp_dpcd);
4612 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4613 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4615 intel_psr_init_dpcd(intel_dp);
4617 /* Read the eDP 1.4+ supported link rates. */
4618 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4619 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4622 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4623 sink_rates, sizeof(sink_rates));
4625 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4626 int val = le16_to_cpu(sink_rates[i]);
4631 /* Value read multiplied by 200kHz gives the per-lane
4632 * link rate in kHz. The source rates are, however,
4633 * stored in terms of LS_Clk kHz. The full conversion
4634 * back to symbols is
4635 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4637 intel_dp->sink_rates[i] = (val * 200) / 10;
4639 intel_dp->num_sink_rates = i;
4643 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4644 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4646 if (intel_dp->num_sink_rates)
4647 intel_dp->use_rate_select = true;
4649 intel_dp_set_sink_rates(intel_dp);
4651 intel_dp_set_common_rates(intel_dp);
4653 /* Read the eDP DSC DPCD registers */
4654 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4655 intel_dp_get_dsc_sink_cap(intel_dp);
4662 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4664 if (!intel_dp_read_dpcd(intel_dp))
4668 * Don't clobber cached eDP rates. Also skip re-reading
4669 * the OUI/ID since we know it won't change.
4671 if (!intel_dp_is_edp(intel_dp)) {
4672 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4673 drm_dp_is_branch(intel_dp->dpcd));
4675 intel_dp_set_sink_rates(intel_dp);
4676 intel_dp_set_common_rates(intel_dp);
4680 * Some eDP panels do not set a valid value for sink count, that is why
4681 * it don't care about read it here and in intel_edp_init_dpcd().
4683 if (!intel_dp_is_edp(intel_dp) &&
4684 !drm_dp_has_quirk(&intel_dp->desc, 0,
4685 DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4689 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4694 * Sink count can change between short pulse hpd hence
4695 * a member variable in intel_dp will track any changes
4696 * between short pulse interrupts.
4698 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4701 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4702 * a dongle is present but no display. Unless we require to know
4703 * if a dongle is present or not, we don't need to update
4704 * downstream port information. So, an early return here saves
4705 * time from performing other operations which are not required.
4707 if (!intel_dp->sink_count)
4711 if (!drm_dp_is_branch(intel_dp->dpcd))
4712 return true; /* native DP sink */
4714 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4715 return true; /* no per-port downstream info */
4717 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4718 intel_dp->downstream_ports,
4719 DP_MAX_DOWNSTREAM_PORTS) < 0)
4720 return false; /* downstream port status fetch failed */
4726 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4730 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4733 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4736 return mstm_cap & DP_MST_CAP;
4740 intel_dp_can_mst(struct intel_dp *intel_dp)
4742 return i915_modparams.enable_dp_mst &&
4743 intel_dp->can_mst &&
4744 intel_dp_sink_can_mst(intel_dp);
4748 intel_dp_configure_mst(struct intel_dp *intel_dp)
4750 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4751 struct intel_encoder *encoder =
4752 &dp_to_dig_port(intel_dp)->base;
4753 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4755 drm_dbg_kms(&i915->drm,
4756 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4757 encoder->base.base.id, encoder->base.name,
4758 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4759 yesno(i915_modparams.enable_dp_mst));
4761 if (!intel_dp->can_mst)
4764 intel_dp->is_mst = sink_can_mst &&
4765 i915_modparams.enable_dp_mst;
4767 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4772 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4774 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4775 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4780 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4781 const struct drm_connector_state *conn_state)
4784 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4785 * of Color Encoding Format and Content Color Gamut], in order to
4786 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4788 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4791 switch (conn_state->colorspace) {
4792 case DRM_MODE_COLORIMETRY_SYCC_601:
4793 case DRM_MODE_COLORIMETRY_OPYCC_601:
4794 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4795 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4796 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4805 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4806 struct dp_sdp *sdp, size_t size)
4808 size_t length = sizeof(struct dp_sdp);
4813 memset(sdp, 0, size);
4816 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4817 * VSC SDP Header Bytes
4819 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4820 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4821 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4822 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4824 /* VSC SDP Payload for DB16 through DB18 */
4825 /* Pixel Encoding and Colorimetry Formats */
4826 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4827 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4834 sdp->db[17] = 0x1; /* DB17[3:0] */
4846 MISSING_CASE(vsc->bpc);
4849 /* Dynamic Range and Component Bit Depth */
4850 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4851 sdp->db[17] |= 0x80; /* DB17[7] */
4854 sdp->db[18] = vsc->content_type & 0x7;
4860 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4864 size_t length = sizeof(struct dp_sdp);
4865 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4866 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4872 memset(sdp, 0, size);
4874 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4876 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4880 if (len != infoframe_size) {
4881 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4886 * Set up the infoframe sdp packet for HDR static metadata.
4887 * Prepare VSC Header for SU as per DP 1.4a spec,
4888 * Table 2-100 and Table 2-101
4891 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4892 sdp->sdp_header.HB0 = 0;
4894 * Packet Type 80h + Non-audio INFOFRAME Type value
4895 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4896 * - 80h + Non-audio INFOFRAME Type value
4897 * - InfoFrame Type: 0x07
4898 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4900 sdp->sdp_header.HB1 = drm_infoframe->type;
4902 * Least Significant Eight Bits of (Data Byte Count – 1)
4903 * infoframe_size - 1
4905 sdp->sdp_header.HB2 = 0x1D;
4906 /* INFOFRAME SDP Version Number */
4907 sdp->sdp_header.HB3 = (0x13 << 2);
4908 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4909 sdp->db[0] = drm_infoframe->version;
4910 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4911 sdp->db[1] = drm_infoframe->length;
4913 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4914 * HDMI_INFOFRAME_HEADER_SIZE
4916 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4917 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4918 HDMI_DRM_INFOFRAME_SIZE);
4921 * Size of DP infoframe sdp packet for HDR static metadata consists of
4922 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4923 * - Two Data Blocks: 2 bytes
4924 * CTA Header Byte2 (INFOFRAME Version Number)
4925 * CTA Header Byte3 (Length of INFOFRAME)
4926 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4928 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4929 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4930 * will pad rest of the size.
4932 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4935 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4936 const struct intel_crtc_state *crtc_state,
4939 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4940 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4941 struct dp_sdp sdp = {};
4944 if ((crtc_state->infoframes.enable &
4945 intel_hdmi_infoframe_enable(type)) == 0)
4950 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4953 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4954 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4962 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4965 intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4968 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4970 const struct intel_crtc_state *crtc_state,
4971 const struct drm_connector_state *conn_state)
4973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4974 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4975 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4976 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4977 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4978 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4979 u32 val = intel_de_read(dev_priv, reg);
4981 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
4982 /* When PSR is enabled, this routine doesn't disable VSC DIP */
4983 if (intel_psr_enabled(intel_dp))
4986 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
4989 intel_de_write(dev_priv, reg, val);
4990 intel_de_posting_read(dev_priv, reg);
4994 intel_de_write(dev_priv, reg, val);
4995 intel_de_posting_read(dev_priv, reg);
4997 /* When PSR is enabled, VSC SDP is handled by PSR routine */
4998 if (!intel_psr_enabled(intel_dp))
4999 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5001 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5005 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
5006 const struct intel_crtc_state *crtc_state,
5007 const struct drm_connector_state *conn_state)
5009 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5010 struct dp_sdp vsc_sdp = {};
5012 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
5013 vsc_sdp.sdp_header.HB0 = 0;
5014 vsc_sdp.sdp_header.HB1 = 0x7;
5017 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
5018 * Colorimetry Format indication.
5020 vsc_sdp.sdp_header.HB2 = 0x5;
5023 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
5024 * Colorimetry Format indication (HB2 = 05h).
5026 vsc_sdp.sdp_header.HB3 = 0x13;
5028 /* DP 1.4a spec, Table 2-120 */
5029 switch (crtc_state->output_format) {
5030 case INTEL_OUTPUT_FORMAT_YCBCR444:
5031 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
5033 case INTEL_OUTPUT_FORMAT_YCBCR420:
5034 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
5036 case INTEL_OUTPUT_FORMAT_RGB:
5038 /* RGB: DB16[7:4] = 0h */
5042 switch (conn_state->colorspace) {
5043 case DRM_MODE_COLORIMETRY_BT709_YCC:
5044 vsc_sdp.db[16] |= 0x1;
5046 case DRM_MODE_COLORIMETRY_XVYCC_601:
5047 vsc_sdp.db[16] |= 0x2;
5049 case DRM_MODE_COLORIMETRY_XVYCC_709:
5050 vsc_sdp.db[16] |= 0x3;
5052 case DRM_MODE_COLORIMETRY_SYCC_601:
5053 vsc_sdp.db[16] |= 0x4;
5055 case DRM_MODE_COLORIMETRY_OPYCC_601:
5056 vsc_sdp.db[16] |= 0x5;
5058 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5059 case DRM_MODE_COLORIMETRY_BT2020_RGB:
5060 vsc_sdp.db[16] |= 0x6;
5062 case DRM_MODE_COLORIMETRY_BT2020_YCC:
5063 vsc_sdp.db[16] |= 0x7;
5065 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
5066 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
5067 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
5070 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
5072 /* RGB->YCBCR color conversion uses the BT.709 color space. */
5073 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5074 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
5079 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
5080 * the following Component Bit Depth values are defined:
5086 switch (crtc_state->pipe_bpp) {
5088 vsc_sdp.db[17] = 0x1;
5090 case 30: /* 10bpc */
5091 vsc_sdp.db[17] = 0x2;
5093 case 36: /* 12bpc */
5094 vsc_sdp.db[17] = 0x3;
5096 case 48: /* 16bpc */
5097 vsc_sdp.db[17] = 0x4;
5100 MISSING_CASE(crtc_state->pipe_bpp);
5105 * Dynamic Range (Bit 7)
5106 * 0 = VESA range, 1 = CTA range.
5107 * all YCbCr are always limited range
5109 vsc_sdp.db[17] |= 0x80;
5112 * Content Type (Bits 2:0)
5113 * 000b = Not defined.
5118 * All other values are RESERVED.
5119 * Note: See CTA-861-G for the definition and expected
5120 * processing by a stream sink for the above contect types.
5124 intel_dig_port->write_infoframe(&intel_dig_port->base,
5125 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
5129 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
5130 const struct intel_crtc_state *crtc_state,
5131 const struct drm_connector_state *conn_state)
5133 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5135 struct dp_sdp infoframe_sdp = {};
5136 struct hdmi_drm_infoframe drm_infoframe = {};
5137 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5138 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5142 ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
5144 drm_dbg_kms(&i915->drm,
5145 "couldn't set HDR metadata in infoframe\n");
5149 len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
5151 drm_dbg_kms(&i915->drm,
5152 "buffer size is smaller than hdr metadata infoframe\n");
5156 if (len != infoframe_size) {
5157 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
5162 * Set up the infoframe sdp packet for HDR static metadata.
5163 * Prepare VSC Header for SU as per DP 1.4a spec,
5164 * Table 2-100 and Table 2-101
5167 /* Packet ID, 00h for non-Audio INFOFRAME */
5168 infoframe_sdp.sdp_header.HB0 = 0;
5170 * Packet Type 80h + Non-audio INFOFRAME Type value
5171 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
5173 infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
5175 * Least Significant Eight Bits of (Data Byte Count – 1)
5176 * infoframe_size - 1,
5178 infoframe_sdp.sdp_header.HB2 = 0x1D;
5179 /* INFOFRAME SDP Version Number */
5180 infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
5181 /* CTA Header Byte 2 (INFOFRAME Version Number) */
5182 infoframe_sdp.db[0] = drm_infoframe.version;
5183 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5184 infoframe_sdp.db[1] = drm_infoframe.length;
5186 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5187 * HDMI_INFOFRAME_HEADER_SIZE
5189 BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5190 memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5191 HDMI_DRM_INFOFRAME_SIZE);
5194 * Size of DP infoframe sdp packet for HDR static metadata is consist of
5195 * - DP SDP Header(struct dp_sdp_header): 4 bytes
5196 * - Two Data Blocks: 2 bytes
5197 * CTA Header Byte2 (INFOFRAME Version Number)
5198 * CTA Header Byte3 (Length of INFOFRAME)
5199 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5201 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5202 * infoframe size. But GEN11+ has larger than that size, write_infoframe
5203 * will pad rest of the size.
5205 intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
5206 HDMI_PACKET_TYPE_GAMUT_METADATA,
5208 sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
5211 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
5212 const struct intel_crtc_state *crtc_state,
5213 const struct drm_connector_state *conn_state)
5215 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
5218 intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
5221 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
5222 const struct intel_crtc_state *crtc_state,
5223 const struct drm_connector_state *conn_state)
5225 if (!conn_state->hdr_output_metadata)
5228 intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
5233 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5235 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5238 u8 test_lane_count, test_link_bw;
5242 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5243 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5247 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5250 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5252 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5255 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5258 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5260 /* Validate the requested link rate and lane count */
5261 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5265 intel_dp->compliance.test_lane_count = test_lane_count;
5266 intel_dp->compliance.test_link_rate = test_link_rate;
5271 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5273 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5276 __be16 h_width, v_height;
5279 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5280 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5283 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5286 if (test_pattern != DP_COLOR_RAMP)
5289 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5292 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5296 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5299 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5303 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5306 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5309 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5311 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5313 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5314 case DP_TEST_BIT_DEPTH_6:
5315 intel_dp->compliance.test_data.bpc = 6;
5317 case DP_TEST_BIT_DEPTH_8:
5318 intel_dp->compliance.test_data.bpc = 8;
5324 intel_dp->compliance.test_data.video_pattern = test_pattern;
5325 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5326 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5327 /* Set test active flag here so userspace doesn't interrupt things */
5328 intel_dp->compliance.test_active = true;
5333 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5335 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5336 u8 test_result = DP_TEST_ACK;
5337 struct intel_connector *intel_connector = intel_dp->attached_connector;
5338 struct drm_connector *connector = &intel_connector->base;
5340 if (intel_connector->detect_edid == NULL ||
5341 connector->edid_corrupt ||
5342 intel_dp->aux.i2c_defer_count > 6) {
5343 /* Check EDID read for NACKs, DEFERs and corruption
5344 * (DP CTS 1.2 Core r1.1)
5345 * 4.2.2.4 : Failed EDID read, I2C_NAK
5346 * 4.2.2.5 : Failed EDID read, I2C_DEFER
5347 * 4.2.2.6 : EDID corruption detected
5348 * Use failsafe mode for all cases
5350 if (intel_dp->aux.i2c_nack_count > 0 ||
5351 intel_dp->aux.i2c_defer_count > 0)
5352 drm_dbg_kms(&i915->drm,
5353 "EDID read had %d NACKs, %d DEFERs\n",
5354 intel_dp->aux.i2c_nack_count,
5355 intel_dp->aux.i2c_defer_count);
5356 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5358 struct edid *block = intel_connector->detect_edid;
5360 /* We have to write the checksum
5361 * of the last block read
5363 block += intel_connector->detect_edid->extensions;
5365 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5366 block->checksum) <= 0)
5367 drm_dbg_kms(&i915->drm,
5368 "Failed to write EDID checksum\n");
5370 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5371 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5374 /* Set test active flag here so userspace doesn't interrupt things */
5375 intel_dp->compliance.test_active = true;
5380 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5382 struct drm_dp_phy_test_params *data =
5383 &intel_dp->compliance.test_data.phytest;
5385 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5386 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5391 * link_mst is set to false to avoid executing mst related code
5392 * during compliance testing.
5394 intel_dp->link_mst = false;
5399 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5401 struct drm_i915_private *dev_priv =
5402 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5404 struct drm_dp_phy_test_params *data =
5405 &intel_dp->compliance.test_data.phytest;
5406 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5407 enum pipe pipe = crtc->pipe;
5410 switch (data->phy_pattern) {
5411 case DP_PHY_TEST_PATTERN_NONE:
5412 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5413 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5415 case DP_PHY_TEST_PATTERN_D10_2:
5416 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5417 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5418 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5420 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5421 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5422 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5423 DDI_DP_COMP_CTL_ENABLE |
5424 DDI_DP_COMP_CTL_SCRAMBLED_0);
5426 case DP_PHY_TEST_PATTERN_PRBS7:
5427 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5428 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5429 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5431 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5433 * FIXME: Ideally pattern should come from DPCD 0x250. As
5434 * current firmware of DPR-100 could not set it, so hardcoding
5435 * now for complaince test.
5437 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5438 pattern_val = 0x3e0f83e0;
5439 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5440 pattern_val = 0x0f83e0f8;
5441 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5442 pattern_val = 0x0000f83e;
5443 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5444 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5445 DDI_DP_COMP_CTL_ENABLE |
5446 DDI_DP_COMP_CTL_CUSTOM80);
5448 case DP_PHY_TEST_PATTERN_CP2520:
5450 * FIXME: Ideally pattern should come from DPCD 0x24A. As
5451 * current firmware of DPR-100 could not set it, so hardcoding
5452 * now for complaince test.
5454 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5456 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5457 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5461 WARN(1, "Invalid Phy Test Pattern\n");
5466 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5468 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5469 struct drm_device *dev = intel_dig_port->base.base.dev;
5470 struct drm_i915_private *dev_priv = to_i915(dev);
5471 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5472 enum pipe pipe = crtc->pipe;
5473 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5475 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5476 TRANS_DDI_FUNC_CTL(pipe));
5477 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5478 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5480 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5481 TGL_TRANS_DDI_PORT_MASK);
5482 trans_conf_value &= ~PIPECONF_ENABLE;
5483 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5485 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5486 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5487 trans_ddi_func_ctl_value);
5488 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5492 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5495 struct drm_device *dev = intel_dig_port->base.base.dev;
5496 struct drm_i915_private *dev_priv = to_i915(dev);
5497 enum port port = intel_dig_port->base.port;
5498 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5499 enum pipe pipe = crtc->pipe;
5500 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5502 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5503 TRANS_DDI_FUNC_CTL(pipe));
5504 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5505 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5507 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5508 TGL_TRANS_DDI_SELECT_PORT(port);
5509 trans_conf_value |= PIPECONF_ENABLE;
5510 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5512 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5513 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5514 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5515 trans_ddi_func_ctl_value);
5518 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5520 struct drm_dp_phy_test_params *data =
5521 &intel_dp->compliance.test_data.phytest;
5522 u8 link_status[DP_LINK_STATUS_SIZE];
5524 if (!intel_dp_get_link_status(intel_dp, link_status)) {
5525 DRM_DEBUG_KMS("failed to get link status\n");
5529 /* retrieve vswing & pre-emphasis setting */
5530 intel_dp_get_adjust_train(intel_dp, link_status);
5532 intel_dp_autotest_phy_ddi_disable(intel_dp);
5534 intel_dp_set_signal_levels(intel_dp);
5536 intel_dp_phy_pattern_update(intel_dp);
5538 intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5540 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5541 link_status[DP_DPCD_REV]);
5544 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5548 test_result = intel_dp_prepare_phytest(intel_dp);
5549 if (test_result != DP_TEST_ACK)
5550 DRM_ERROR("Phy test preparation failed\n");
5552 intel_dp_process_phy_request(intel_dp);
5557 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5559 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5560 u8 response = DP_TEST_NAK;
5564 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5566 drm_dbg_kms(&i915->drm,
5567 "Could not read test request from sink\n");
5572 case DP_TEST_LINK_TRAINING:
5573 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5574 response = intel_dp_autotest_link_training(intel_dp);
5576 case DP_TEST_LINK_VIDEO_PATTERN:
5577 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5578 response = intel_dp_autotest_video_pattern(intel_dp);
5580 case DP_TEST_LINK_EDID_READ:
5581 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5582 response = intel_dp_autotest_edid(intel_dp);
5584 case DP_TEST_LINK_PHY_TEST_PATTERN:
5585 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5586 response = intel_dp_autotest_phy_pattern(intel_dp);
5589 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5594 if (response & DP_TEST_ACK)
5595 intel_dp->compliance.test_type = request;
5598 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5600 drm_dbg_kms(&i915->drm,
5601 "Could not write test response to sink\n");
5605 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5607 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5608 bool need_retrain = false;
5610 if (!intel_dp->is_mst)
5613 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5616 u8 esi[DP_DPRX_ESI_LEN] = {};
5620 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5622 drm_dbg_kms(&i915->drm,
5623 "failed to get ESI - device may have failed\n");
5627 /* check link status - esi[10] = 0x200c */
5628 if (intel_dp->active_mst_links > 0 && !need_retrain &&
5629 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5630 drm_dbg_kms(&i915->drm,
5631 "channel EQ not ok, retraining\n");
5632 need_retrain = true;
5635 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5637 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5641 for (retry = 0; retry < 3; retry++) {
5644 wret = drm_dp_dpcd_write(&intel_dp->aux,
5645 DP_SINK_COUNT_ESI+1,
5652 return need_retrain;
5656 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5658 u8 link_status[DP_LINK_STATUS_SIZE];
5660 if (!intel_dp->link_trained)
5664 * While PSR source HW is enabled, it will control main-link sending
5665 * frames, enabling and disabling it so trying to do a retrain will fail
5666 * as the link would or not be on or it could mix training patterns
5667 * and frame data at the same time causing retrain to fail.
5668 * Also when exiting PSR, HW will retrain the link anyways fixing
5669 * any link status error.
5671 if (intel_psr_enabled(intel_dp))
5674 if (!intel_dp_get_link_status(intel_dp, link_status))
5678 * Validate the cached values of intel_dp->link_rate and
5679 * intel_dp->lane_count before attempting to retrain.
5681 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5682 intel_dp->lane_count))
5685 /* Retrain if Channel EQ or CR not ok */
5686 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5689 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5690 const struct drm_connector_state *conn_state)
5692 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5693 struct intel_encoder *encoder;
5696 if (!conn_state->best_encoder)
5700 encoder = &dp_to_dig_port(intel_dp)->base;
5701 if (conn_state->best_encoder == &encoder->base)
5705 for_each_pipe(i915, pipe) {
5706 encoder = &intel_dp->mst_encoders[pipe]->base;
5707 if (conn_state->best_encoder == &encoder->base)
5714 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5715 struct drm_modeset_acquire_ctx *ctx,
5718 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5719 struct drm_connector_list_iter conn_iter;
5720 struct intel_connector *connector;
5725 if (!intel_dp_needs_link_retrain(intel_dp))
5728 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5729 for_each_intel_connector_iter(connector, &conn_iter) {
5730 struct drm_connector_state *conn_state =
5731 connector->base.state;
5732 struct intel_crtc_state *crtc_state;
5733 struct intel_crtc *crtc;
5735 if (!intel_dp_has_connector(intel_dp, conn_state))
5738 crtc = to_intel_crtc(conn_state->crtc);
5742 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5746 crtc_state = to_intel_crtc_state(crtc->base.state);
5748 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5750 if (!crtc_state->hw.active)
5753 if (conn_state->commit &&
5754 !try_wait_for_completion(&conn_state->commit->hw_done))
5757 *crtc_mask |= drm_crtc_mask(&crtc->base);
5759 drm_connector_list_iter_end(&conn_iter);
5761 if (!intel_dp_needs_link_retrain(intel_dp))
5767 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5769 struct intel_connector *connector = intel_dp->attached_connector;
5771 return connector->base.status == connector_status_connected ||
5775 int intel_dp_retrain_link(struct intel_encoder *encoder,
5776 struct drm_modeset_acquire_ctx *ctx)
5778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5779 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5780 struct intel_crtc *crtc;
5784 if (!intel_dp_is_connected(intel_dp))
5787 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5792 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5799 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5800 encoder->base.base.id, encoder->base.name);
5802 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5803 const struct intel_crtc_state *crtc_state =
5804 to_intel_crtc_state(crtc->base.state);
5806 /* Suppress underruns caused by re-training */
5807 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5808 if (crtc_state->has_pch_encoder)
5809 intel_set_pch_fifo_underrun_reporting(dev_priv,
5810 intel_crtc_pch_transcoder(crtc), false);
5813 intel_dp_start_link_train(intel_dp);
5814 intel_dp_stop_link_train(intel_dp);
5816 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5817 const struct intel_crtc_state *crtc_state =
5818 to_intel_crtc_state(crtc->base.state);
5820 /* Keep underrun reporting disabled until things are stable */
5821 intel_wait_for_vblank(dev_priv, crtc->pipe);
5823 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5824 if (crtc_state->has_pch_encoder)
5825 intel_set_pch_fifo_underrun_reporting(dev_priv,
5826 intel_crtc_pch_transcoder(crtc), true);
5833 * If display is now connected check links status,
5834 * there has been known issues of link loss triggering
5837 * Some sinks (eg. ASUS PB287Q) seem to perform some
5838 * weird HPD ping pong during modesets. So we can apparently
5839 * end up with HPD going low during a modeset, and then
5840 * going back up soon after. And once that happens we must
5841 * retrain the link to get a picture. That's in case no
5842 * userspace component reacted to intermittent HPD dip.
5844 static enum intel_hotplug_state
5845 intel_dp_hotplug(struct intel_encoder *encoder,
5846 struct intel_connector *connector)
5848 struct drm_modeset_acquire_ctx ctx;
5849 enum intel_hotplug_state state;
5852 state = intel_encoder_hotplug(encoder, connector);
5854 drm_modeset_acquire_init(&ctx, 0);
5857 ret = intel_dp_retrain_link(encoder, &ctx);
5859 if (ret == -EDEADLK) {
5860 drm_modeset_backoff(&ctx);
5867 drm_modeset_drop_locks(&ctx);
5868 drm_modeset_acquire_fini(&ctx);
5869 drm_WARN(encoder->base.dev, ret,
5870 "Acquiring modeset locks failed with %i\n", ret);
5873 * Keeping it consistent with intel_ddi_hotplug() and
5874 * intel_hdmi_hotplug().
5876 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5877 state = INTEL_HOTPLUG_RETRY;
5882 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5884 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5887 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5890 if (drm_dp_dpcd_readb(&intel_dp->aux,
5891 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5894 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5896 if (val & DP_AUTOMATED_TEST_REQUEST)
5897 intel_dp_handle_test_request(intel_dp);
5899 if (val & DP_CP_IRQ)
5900 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5902 if (val & DP_SINK_SPECIFIC_IRQ)
5903 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5907 * According to DP spec
5910 * 2. Configure link according to Receiver Capabilities
5911 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5912 * 4. Check link status on receipt of hot-plug interrupt
5914 * intel_dp_short_pulse - handles short pulse interrupts
5915 * when full detection is not required.
5916 * Returns %true if short pulse is handled and full detection
5917 * is NOT required and %false otherwise.
5920 intel_dp_short_pulse(struct intel_dp *intel_dp)
5922 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5923 u8 old_sink_count = intel_dp->sink_count;
5927 * Clearing compliance test variables to allow capturing
5928 * of values for next automated test request.
5930 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5933 * Now read the DPCD to see if it's actually running
5934 * If the current value of sink count doesn't match with
5935 * the value that was stored earlier or dpcd read failed
5936 * we need to do full detection
5938 ret = intel_dp_get_dpcd(intel_dp);
5940 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5941 /* No need to proceed if we are going to do full detect */
5945 intel_dp_check_service_irq(intel_dp);
5947 /* Handle CEC interrupts, if any */
5948 drm_dp_cec_irq(&intel_dp->aux);
5950 /* defer to the hotplug work for link retraining if needed */
5951 if (intel_dp_needs_link_retrain(intel_dp))
5954 intel_psr_short_pulse(intel_dp);
5956 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5957 drm_dbg_kms(&dev_priv->drm,
5958 "Link Training Compliance Test requested\n");
5959 /* Send a Hotplug Uevent to userspace to start modeset */
5960 drm_kms_helper_hotplug_event(&dev_priv->drm);
5966 /* XXX this is probably wrong for multiple downstream ports */
5967 static enum drm_connector_status
5968 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5970 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5971 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5972 u8 *dpcd = intel_dp->dpcd;
5975 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5976 return connector_status_connected;
5979 lspcon_resume(lspcon);
5981 if (!intel_dp_get_dpcd(intel_dp))
5982 return connector_status_disconnected;
5984 /* if there's no downstream port, we're done */
5985 if (!drm_dp_is_branch(dpcd))
5986 return connector_status_connected;
5988 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5989 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5990 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5992 return intel_dp->sink_count ?
5993 connector_status_connected : connector_status_disconnected;
5996 if (intel_dp_can_mst(intel_dp))
5997 return connector_status_connected;
5999 /* If no HPD, poke DDC gently */
6000 if (drm_probe_ddc(&intel_dp->aux.ddc))
6001 return connector_status_connected;
6003 /* Well we tried, say unknown for unreliable port types */
6004 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6005 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6006 if (type == DP_DS_PORT_TYPE_VGA ||
6007 type == DP_DS_PORT_TYPE_NON_EDID)
6008 return connector_status_unknown;
6010 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6011 DP_DWN_STRM_PORT_TYPE_MASK;
6012 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6013 type == DP_DWN_STRM_PORT_TYPE_OTHER)
6014 return connector_status_unknown;
6017 /* Anything else is out of spec, warn and ignore */
6018 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6019 return connector_status_disconnected;
6022 static enum drm_connector_status
6023 edp_detect(struct intel_dp *intel_dp)
6025 return connector_status_connected;
6028 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6033 switch (encoder->hpd_pin) {
6035 bit = SDE_PORTB_HOTPLUG;
6038 bit = SDE_PORTC_HOTPLUG;
6041 bit = SDE_PORTD_HOTPLUG;
6044 MISSING_CASE(encoder->hpd_pin);
6048 return intel_de_read(dev_priv, SDEISR) & bit;
6051 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
6053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6056 switch (encoder->hpd_pin) {
6058 bit = SDE_PORTB_HOTPLUG_CPT;
6061 bit = SDE_PORTC_HOTPLUG_CPT;
6064 bit = SDE_PORTD_HOTPLUG_CPT;
6067 MISSING_CASE(encoder->hpd_pin);
6071 return intel_de_read(dev_priv, SDEISR) & bit;
6074 static bool spt_digital_port_connected(struct intel_encoder *encoder)
6076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6079 switch (encoder->hpd_pin) {
6081 bit = SDE_PORTA_HOTPLUG_SPT;
6084 bit = SDE_PORTE_HOTPLUG_SPT;
6087 return cpt_digital_port_connected(encoder);
6090 return intel_de_read(dev_priv, SDEISR) & bit;
6093 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6098 switch (encoder->hpd_pin) {
6100 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6103 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6106 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6109 MISSING_CASE(encoder->hpd_pin);
6113 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6116 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6121 switch (encoder->hpd_pin) {
6123 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6126 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6129 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6132 MISSING_CASE(encoder->hpd_pin);
6136 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6139 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6143 if (encoder->hpd_pin == HPD_PORT_A)
6144 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6146 return ibx_digital_port_connected(encoder);
6149 static bool snb_digital_port_connected(struct intel_encoder *encoder)
6151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6153 if (encoder->hpd_pin == HPD_PORT_A)
6154 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6156 return cpt_digital_port_connected(encoder);
6159 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
6161 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6163 if (encoder->hpd_pin == HPD_PORT_A)
6164 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
6166 return cpt_digital_port_connected(encoder);
6169 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
6171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6173 if (encoder->hpd_pin == HPD_PORT_A)
6174 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
6176 return cpt_digital_port_connected(encoder);
6179 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
6181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6184 switch (encoder->hpd_pin) {
6186 bit = BXT_DE_PORT_HP_DDIA;
6189 bit = BXT_DE_PORT_HP_DDIB;
6192 bit = BXT_DE_PORT_HP_DDIC;
6195 MISSING_CASE(encoder->hpd_pin);
6199 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
6202 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
6205 if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
6206 return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
6208 return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
6211 static bool icp_digital_port_connected(struct intel_encoder *encoder)
6213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6214 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6215 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
6217 if (intel_phy_is_combo(dev_priv, phy))
6218 return intel_combo_phy_connected(dev_priv, phy);
6219 else if (intel_phy_is_tc(dev_priv, phy))
6220 return intel_tc_port_connected(dig_port);
6222 MISSING_CASE(encoder->hpd_pin);
6228 * intel_digital_port_connected - is the specified port connected?
6229 * @encoder: intel_encoder
6231 * In cases where there's a connector physically connected but it can't be used
6232 * by our hardware we also return false, since the rest of the driver should
6233 * pretty much treat the port as disconnected. This is relevant for type-C
6234 * (starting on ICL) where there's ownership involved.
6236 * Return %true if port is connected, %false otherwise.
6238 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
6240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6242 if (HAS_GMCH(dev_priv)) {
6243 if (IS_GM45(dev_priv))
6244 return gm45_digital_port_connected(encoder);
6246 return g4x_digital_port_connected(encoder);
6249 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
6250 return icp_digital_port_connected(encoder);
6251 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
6252 return spt_digital_port_connected(encoder);
6253 else if (IS_GEN9_LP(dev_priv))
6254 return bxt_digital_port_connected(encoder);
6255 else if (IS_GEN(dev_priv, 8))
6256 return bdw_digital_port_connected(encoder);
6257 else if (IS_GEN(dev_priv, 7))
6258 return ivb_digital_port_connected(encoder);
6259 else if (IS_GEN(dev_priv, 6))
6260 return snb_digital_port_connected(encoder);
6261 else if (IS_GEN(dev_priv, 5))
6262 return ilk_digital_port_connected(encoder);
6264 MISSING_CASE(INTEL_GEN(dev_priv));
6268 bool intel_digital_port_connected(struct intel_encoder *encoder)
6270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6271 bool is_connected = false;
6272 intel_wakeref_t wakeref;
6274 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6275 is_connected = __intel_digital_port_connected(encoder);
6277 return is_connected;
6280 static struct edid *
6281 intel_dp_get_edid(struct intel_dp *intel_dp)
6283 struct intel_connector *intel_connector = intel_dp->attached_connector;
6285 /* use cached edid if we have one */
6286 if (intel_connector->edid) {
6288 if (IS_ERR(intel_connector->edid))
6291 return drm_edid_duplicate(intel_connector->edid);
6293 return drm_get_edid(&intel_connector->base,
6294 &intel_dp->aux.ddc);
6298 intel_dp_set_edid(struct intel_dp *intel_dp)
6300 struct intel_connector *intel_connector = intel_dp->attached_connector;
6303 intel_dp_unset_edid(intel_dp);
6304 edid = intel_dp_get_edid(intel_dp);
6305 intel_connector->detect_edid = edid;
6307 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6308 drm_dp_cec_set_edid(&intel_dp->aux, edid);
6309 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6313 intel_dp_unset_edid(struct intel_dp *intel_dp)
6315 struct intel_connector *intel_connector = intel_dp->attached_connector;
6317 drm_dp_cec_unset_edid(&intel_dp->aux);
6318 kfree(intel_connector->detect_edid);
6319 intel_connector->detect_edid = NULL;
6321 intel_dp->has_audio = false;
6322 intel_dp->edid_quirks = 0;
6326 intel_dp_detect(struct drm_connector *connector,
6327 struct drm_modeset_acquire_ctx *ctx,
6330 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6331 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6332 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6333 struct intel_encoder *encoder = &dig_port->base;
6334 enum drm_connector_status status;
6336 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6337 connector->base.id, connector->name);
6338 drm_WARN_ON(&dev_priv->drm,
6339 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6341 /* Can't disconnect eDP */
6342 if (intel_dp_is_edp(intel_dp))
6343 status = edp_detect(intel_dp);
6344 else if (intel_digital_port_connected(encoder))
6345 status = intel_dp_detect_dpcd(intel_dp);
6347 status = connector_status_disconnected;
6349 if (status == connector_status_disconnected) {
6350 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6351 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6353 if (intel_dp->is_mst) {
6354 drm_dbg_kms(&dev_priv->drm,
6355 "MST device may have disappeared %d vs %d\n",
6357 intel_dp->mst_mgr.mst_state);
6358 intel_dp->is_mst = false;
6359 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6366 if (intel_dp->reset_link_params) {
6367 /* Initial max link lane count */
6368 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6370 /* Initial max link rate */
6371 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6373 intel_dp->reset_link_params = false;
6376 intel_dp_print_rates(intel_dp);
6378 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6379 if (INTEL_GEN(dev_priv) >= 11)
6380 intel_dp_get_dsc_sink_cap(intel_dp);
6382 intel_dp_configure_mst(intel_dp);
6384 if (intel_dp->is_mst) {
6386 * If we are in MST mode then this connector
6387 * won't appear connected or have anything
6390 status = connector_status_disconnected;
6395 * Some external monitors do not signal loss of link synchronization
6396 * with an IRQ_HPD, so force a link status check.
6398 if (!intel_dp_is_edp(intel_dp)) {
6401 ret = intel_dp_retrain_link(encoder, ctx);
6407 * Clearing NACK and defer counts to get their exact values
6408 * while reading EDID which are required by Compliance tests
6409 * 4.2.2.4 and 4.2.2.5
6411 intel_dp->aux.i2c_nack_count = 0;
6412 intel_dp->aux.i2c_defer_count = 0;
6414 intel_dp_set_edid(intel_dp);
6415 if (intel_dp_is_edp(intel_dp) ||
6416 to_intel_connector(connector)->detect_edid)
6417 status = connector_status_connected;
6419 intel_dp_check_service_irq(intel_dp);
6422 if (status != connector_status_connected && !intel_dp->is_mst)
6423 intel_dp_unset_edid(intel_dp);
6426 * Make sure the refs for power wells enabled during detect are
6427 * dropped to avoid a new detect cycle triggered by HPD polling.
6429 intel_display_power_flush_work(dev_priv);
6435 intel_dp_force(struct drm_connector *connector)
6437 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6438 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6439 struct intel_encoder *intel_encoder = &dig_port->base;
6440 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6441 enum intel_display_power_domain aux_domain =
6442 intel_aux_power_domain(dig_port);
6443 intel_wakeref_t wakeref;
6445 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6446 connector->base.id, connector->name);
6447 intel_dp_unset_edid(intel_dp);
6449 if (connector->status != connector_status_connected)
6452 wakeref = intel_display_power_get(dev_priv, aux_domain);
6454 intel_dp_set_edid(intel_dp);
6456 intel_display_power_put(dev_priv, aux_domain, wakeref);
6459 static int intel_dp_get_modes(struct drm_connector *connector)
6461 struct intel_connector *intel_connector = to_intel_connector(connector);
6464 edid = intel_connector->detect_edid;
6466 int ret = intel_connector_update_modes(connector, edid);
6471 /* if eDP has no EDID, fall back to fixed mode */
6472 if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6473 intel_connector->panel.fixed_mode) {
6474 struct drm_display_mode *mode;
6476 mode = drm_mode_duplicate(connector->dev,
6477 intel_connector->panel.fixed_mode);
6479 drm_mode_probed_add(connector, mode);
6488 intel_dp_connector_register(struct drm_connector *connector)
6490 struct drm_i915_private *i915 = to_i915(connector->dev);
6491 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6494 ret = intel_connector_register(connector);
6498 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6499 intel_dp->aux.name, connector->kdev->kobj.name);
6501 intel_dp->aux.dev = connector->kdev;
6502 ret = drm_dp_aux_register(&intel_dp->aux);
6504 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6509 intel_dp_connector_unregister(struct drm_connector *connector)
6511 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6513 drm_dp_cec_unregister_connector(&intel_dp->aux);
6514 drm_dp_aux_unregister(&intel_dp->aux);
6515 intel_connector_unregister(connector);
6518 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6520 struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6521 struct intel_dp *intel_dp = &intel_dig_port->dp;
6523 intel_dp_mst_encoder_cleanup(intel_dig_port);
6524 if (intel_dp_is_edp(intel_dp)) {
6525 intel_wakeref_t wakeref;
6527 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6529 * vdd might still be enabled do to the delayed vdd off.
6530 * Make sure vdd is actually turned off here.
6532 with_pps_lock(intel_dp, wakeref)
6533 edp_panel_vdd_off_sync(intel_dp);
6535 if (intel_dp->edp_notifier.notifier_call) {
6536 unregister_reboot_notifier(&intel_dp->edp_notifier);
6537 intel_dp->edp_notifier.notifier_call = NULL;
6541 intel_dp_aux_fini(intel_dp);
6544 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6546 intel_dp_encoder_flush_work(encoder);
6548 drm_encoder_cleanup(encoder);
6549 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6552 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6554 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6555 intel_wakeref_t wakeref;
6557 if (!intel_dp_is_edp(intel_dp))
6561 * vdd might still be enabled do to the delayed vdd off.
6562 * Make sure vdd is actually turned off here.
6564 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6565 with_pps_lock(intel_dp, wakeref)
6566 edp_panel_vdd_off_sync(intel_dp);
6569 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6573 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6574 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6575 msecs_to_jiffies(timeout));
6578 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6582 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6585 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6586 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6587 static const struct drm_dp_aux_msg msg = {
6588 .request = DP_AUX_NATIVE_WRITE,
6589 .address = DP_AUX_HDCP_AKSV,
6590 .size = DRM_HDCP_KSV_LEN,
6592 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6596 /* Output An first, that's easy */
6597 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6598 an, DRM_HDCP_AN_LEN);
6599 if (dpcd_ret != DRM_HDCP_AN_LEN) {
6600 drm_dbg_kms(&i915->drm,
6601 "Failed to write An over DP/AUX (%zd)\n",
6603 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6607 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6608 * order to get it on the wire, we need to create the AUX header as if
6609 * we were writing the data, and then tickle the hardware to output the
6610 * data once the header is sent out.
6612 intel_dp_aux_header(txbuf, &msg);
6614 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6615 rxbuf, sizeof(rxbuf),
6616 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6618 drm_dbg_kms(&i915->drm,
6619 "Write Aksv over DP/AUX failed (%d)\n", ret);
6621 } else if (ret == 0) {
6622 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6626 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6627 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6628 drm_dbg_kms(&i915->drm,
6629 "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6636 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6639 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6642 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6644 if (ret != DRM_HDCP_KSV_LEN) {
6645 drm_dbg_kms(&i915->drm,
6646 "Read Bksv from DP/AUX failed (%zd)\n", ret);
6647 return ret >= 0 ? -EIO : ret;
6652 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6655 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6659 * For some reason the HDMI and DP HDCP specs call this register
6660 * definition by different names. In the HDMI spec, it's called BSTATUS,
6661 * but in DP it's called BINFO.
6663 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6664 bstatus, DRM_HDCP_BSTATUS_LEN);
6665 if (ret != DRM_HDCP_BSTATUS_LEN) {
6666 drm_dbg_kms(&i915->drm,
6667 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6668 return ret >= 0 ? -EIO : ret;
6674 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6677 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6680 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6683 drm_dbg_kms(&i915->drm,
6684 "Read bcaps from DP/AUX failed (%zd)\n", ret);
6685 return ret >= 0 ? -EIO : ret;
6692 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6693 bool *repeater_present)
6698 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6702 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6707 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6710 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6713 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6714 ri_prime, DRM_HDCP_RI_LEN);
6715 if (ret != DRM_HDCP_RI_LEN) {
6716 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6718 return ret >= 0 ? -EIO : ret;
6724 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6727 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6731 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6734 drm_dbg_kms(&i915->drm,
6735 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6736 return ret >= 0 ? -EIO : ret;
6738 *ksv_ready = bstatus & DP_BSTATUS_READY;
6743 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6744 int num_downstream, u8 *ksv_fifo)
6746 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6750 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6751 for (i = 0; i < num_downstream; i += 3) {
6752 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6753 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6754 DP_AUX_HDCP_KSV_FIFO,
6755 ksv_fifo + i * DRM_HDCP_KSV_LEN,
6758 drm_dbg_kms(&i915->drm,
6759 "Read ksv[%d] from DP/AUX failed (%zd)\n",
6761 return ret >= 0 ? -EIO : ret;
6768 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6771 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6774 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6777 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6778 DP_AUX_HDCP_V_PRIME(i), part,
6779 DRM_HDCP_V_PRIME_PART_LEN);
6780 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6781 drm_dbg_kms(&i915->drm,
6782 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6783 return ret >= 0 ? -EIO : ret;
6789 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6792 /* Not used for single stream DisplayPort setups */
6797 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6799 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6803 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6806 drm_dbg_kms(&i915->drm,
6807 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6811 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6815 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6821 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6825 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6829 struct hdcp2_dp_errata_stream_type {
6834 struct hdcp2_dp_msg_data {
6837 bool msg_detectable;
6839 u32 timeout2; /* Added for non_paired situation */
6842 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6843 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6844 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6845 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6846 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6848 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6850 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6851 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6852 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6853 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6854 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6855 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6856 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6857 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6858 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6859 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6861 { HDCP_2_2_REP_SEND_RECVID_LIST,
6862 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6863 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6864 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6866 { HDCP_2_2_REP_STREAM_MANAGE,
6867 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6869 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6870 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6871 /* local define to shovel this through the write_2_2 interface */
6872 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
6873 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6874 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6879 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6882 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6885 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6886 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6887 HDCP_2_2_DP_RXSTATUS_LEN);
6888 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6889 drm_dbg_kms(&i915->drm,
6890 "Read bstatus from DP/AUX failed (%zd)\n", ret);
6891 return ret >= 0 ? -EIO : ret;
6898 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6899 u8 msg_id, bool *msg_ready)
6905 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6910 case HDCP_2_2_AKE_SEND_HPRIME:
6911 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6914 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6915 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6918 case HDCP_2_2_REP_SEND_RECVID_LIST:
6919 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6923 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6931 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6932 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6934 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6935 struct intel_dp *dp = &intel_dig_port->dp;
6936 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6937 u8 msg_id = hdcp2_msg_data->msg_id;
6939 bool msg_ready = false;
6941 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6942 timeout = hdcp2_msg_data->timeout2;
6944 timeout = hdcp2_msg_data->timeout;
6947 * There is no way to detect the CERT, LPRIME and STREAM_READY
6948 * availability. So Wait for timeout and read the msg.
6950 if (!hdcp2_msg_data->msg_detectable) {
6955 * As we want to check the msg availability at timeout, Ignoring
6956 * the timeout at wait for CP_IRQ.
6958 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6959 ret = hdcp2_detect_msg_availability(intel_dig_port,
6960 msg_id, &msg_ready);
6966 drm_dbg_kms(&i915->drm,
6967 "msg_id %d, ret %d, timeout(mSec): %d\n",
6968 hdcp2_msg_data->msg_id, ret, timeout);
6973 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6977 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6978 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6979 return &hdcp2_dp_msg_data[i];
6985 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6986 void *buf, size_t size)
6988 struct intel_dp *dp = &intel_dig_port->dp;
6989 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6990 unsigned int offset;
6992 ssize_t ret, bytes_to_write, len;
6993 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6995 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6996 if (!hdcp2_msg_data)
6999 offset = hdcp2_msg_data->offset;
7001 /* No msg_id in DP HDCP2.2 msgs */
7002 bytes_to_write = size - 1;
7005 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
7007 while (bytes_to_write) {
7008 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
7009 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
7011 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
7012 offset, (void *)byte, len);
7016 bytes_to_write -= ret;
7025 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
7027 u8 rx_info[HDCP_2_2_RXINFO_LEN];
7031 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
7032 DP_HDCP_2_2_REG_RXINFO_OFFSET,
7033 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
7034 if (ret != HDCP_2_2_RXINFO_LEN)
7035 return ret >= 0 ? -EIO : ret;
7037 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
7038 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
7040 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
7041 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
7043 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
7044 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
7045 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
7051 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
7052 u8 msg_id, void *buf, size_t size)
7054 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7055 unsigned int offset;
7057 ssize_t ret, bytes_to_recv, len;
7058 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
7060 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
7061 if (!hdcp2_msg_data)
7063 offset = hdcp2_msg_data->offset;
7065 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
7069 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
7070 ret = get_receiver_id_list_size(intel_dig_port);
7076 bytes_to_recv = size - 1;
7078 /* DP adaptation msgs has no msg_id */
7081 while (bytes_to_recv) {
7082 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
7083 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
7085 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
7088 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
7093 bytes_to_recv -= ret;
7104 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
7105 bool is_repeater, u8 content_type)
7108 struct hdcp2_dp_errata_stream_type stream_type_msg;
7114 * Errata for DP: As Stream type is used for encryption, Receiver
7115 * should be communicated with stream type for the decryption of the
7117 * Repeater will be communicated with stream type as a part of it's
7118 * auth later in time.
7120 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
7121 stream_type_msg.stream_type = content_type;
7123 ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
7124 sizeof(stream_type_msg));
7126 return ret < 0 ? ret : 0;
7131 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
7136 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
7140 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
7141 ret = HDCP_REAUTH_REQUEST;
7142 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
7143 ret = HDCP_LINK_INTEGRITY_FAILURE;
7144 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
7145 ret = HDCP_TOPOLOGY_CHANGE;
7151 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
7158 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
7159 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
7160 rx_caps, HDCP_2_2_RXCAPS_LEN);
7161 if (ret != HDCP_2_2_RXCAPS_LEN)
7162 return ret >= 0 ? -EIO : ret;
7164 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
7165 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
7171 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
7172 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
7173 .read_bksv = intel_dp_hdcp_read_bksv,
7174 .read_bstatus = intel_dp_hdcp_read_bstatus,
7175 .repeater_present = intel_dp_hdcp_repeater_present,
7176 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
7177 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
7178 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
7179 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
7180 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
7181 .check_link = intel_dp_hdcp_check_link,
7182 .hdcp_capable = intel_dp_hdcp_capable,
7183 .write_2_2_msg = intel_dp_hdcp2_write_msg,
7184 .read_2_2_msg = intel_dp_hdcp2_read_msg,
7185 .config_stream_type = intel_dp_hdcp2_config_stream_type,
7186 .check_2_2_link = intel_dp_hdcp2_check_link,
7187 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
7188 .protocol = HDCP_PROTOCOL_DP,
7191 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7193 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7194 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7196 lockdep_assert_held(&dev_priv->pps_mutex);
7198 if (!edp_have_panel_vdd(intel_dp))
7202 * The VDD bit needs a power domain reference, so if the bit is
7203 * already enabled when we boot or resume, grab this reference and
7204 * schedule a vdd off, so we don't hold on to the reference
7207 drm_dbg_kms(&dev_priv->drm,
7208 "VDD left on by BIOS, adjusting state tracking\n");
7209 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7211 edp_panel_vdd_schedule_off(intel_dp);
7214 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7216 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7217 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7220 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7221 encoder->port, &pipe))
7224 return INVALID_PIPE;
7227 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7229 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7230 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7231 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7232 intel_wakeref_t wakeref;
7234 if (!HAS_DDI(dev_priv))
7235 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7238 lspcon_resume(lspcon);
7240 intel_dp->reset_link_params = true;
7242 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7243 !intel_dp_is_edp(intel_dp))
7246 with_pps_lock(intel_dp, wakeref) {
7247 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7248 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7250 if (intel_dp_is_edp(intel_dp)) {
7252 * Reinit the power sequencer, in case BIOS did
7253 * something nasty with it.
7255 intel_dp_pps_init(intel_dp);
7256 intel_edp_panel_vdd_sanitize(intel_dp);
7261 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7264 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7265 struct drm_connector_list_iter conn_iter;
7266 struct drm_connector *connector;
7269 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7270 drm_for_each_connector_iter(connector, &conn_iter) {
7271 struct drm_connector_state *conn_state;
7272 struct intel_crtc_state *crtc_state;
7273 struct intel_crtc *crtc;
7275 if (!connector->has_tile ||
7276 connector->tile_group->id != tile_group_id)
7279 conn_state = drm_atomic_get_connector_state(&state->base,
7281 if (IS_ERR(conn_state)) {
7282 ret = PTR_ERR(conn_state);
7286 crtc = to_intel_crtc(conn_state->crtc);
7291 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7292 crtc_state->uapi.mode_changed = true;
7294 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7298 drm_connector_list_iter_end(&conn_iter);
7303 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7305 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7306 struct intel_crtc *crtc;
7308 if (transcoders == 0)
7311 for_each_intel_crtc(&dev_priv->drm, crtc) {
7312 struct intel_crtc_state *crtc_state;
7315 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7316 if (IS_ERR(crtc_state))
7317 return PTR_ERR(crtc_state);
7319 if (!crtc_state->hw.enable)
7322 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7325 crtc_state->uapi.mode_changed = true;
7327 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7331 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7335 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7338 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7343 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7344 struct drm_connector *connector)
7346 const struct drm_connector_state *old_conn_state =
7347 drm_atomic_get_old_connector_state(&state->base, connector);
7348 const struct intel_crtc_state *old_crtc_state;
7349 struct intel_crtc *crtc;
7352 crtc = to_intel_crtc(old_conn_state->crtc);
7356 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7358 if (!old_crtc_state->hw.active)
7361 transcoders = old_crtc_state->sync_mode_slaves_mask;
7362 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7363 transcoders |= BIT(old_crtc_state->master_transcoder);
7365 return intel_modeset_affected_transcoders(state,
7369 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7370 struct drm_atomic_state *_state)
7372 struct drm_i915_private *dev_priv = to_i915(conn->dev);
7373 struct intel_atomic_state *state = to_intel_atomic_state(_state);
7376 ret = intel_digital_connector_atomic_check(conn, &state->base);
7381 * We don't enable port sync on BDW due to missing w/as and
7382 * due to not having adjusted the modeset sequence appropriately.
7384 if (INTEL_GEN(dev_priv) < 9)
7387 if (!intel_connector_needs_modeset(state, conn))
7390 if (conn->has_tile) {
7391 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7396 return intel_modeset_synced_crtcs(state, conn);
7399 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7400 .force = intel_dp_force,
7401 .fill_modes = drm_helper_probe_single_connector_modes,
7402 .atomic_get_property = intel_digital_connector_atomic_get_property,
7403 .atomic_set_property = intel_digital_connector_atomic_set_property,
7404 .late_register = intel_dp_connector_register,
7405 .early_unregister = intel_dp_connector_unregister,
7406 .destroy = intel_connector_destroy,
7407 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7408 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7411 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7412 .detect_ctx = intel_dp_detect,
7413 .get_modes = intel_dp_get_modes,
7414 .mode_valid = intel_dp_mode_valid,
7415 .atomic_check = intel_dp_connector_atomic_check,
7418 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7419 .reset = intel_dp_encoder_reset,
7420 .destroy = intel_dp_encoder_destroy,
7423 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7425 intel_wakeref_t wakeref;
7426 bool have_power = false;
7428 with_pps_lock(intel_dp, wakeref) {
7429 have_power = edp_have_panel_power(intel_dp) &&
7430 edp_have_panel_vdd(intel_dp);
7437 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7439 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7440 struct intel_dp *intel_dp = &intel_dig_port->dp;
7442 if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7443 (long_hpd || !intel_edp_have_power(intel_dp))) {
7445 * vdd off can generate a long/short pulse on eDP which
7446 * would require vdd on to handle it, and thus we
7447 * would end up in an endless cycle of
7448 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7450 drm_dbg_kms(&i915->drm,
7451 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7452 long_hpd ? "long" : "short",
7453 intel_dig_port->base.base.base.id,
7454 intel_dig_port->base.base.name);
7458 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7459 intel_dig_port->base.base.base.id,
7460 intel_dig_port->base.base.name,
7461 long_hpd ? "long" : "short");
7464 intel_dp->reset_link_params = true;
7468 if (intel_dp->is_mst) {
7469 switch (intel_dp_check_mst_status(intel_dp)) {
7472 * If we were in MST mode, and device is not
7473 * there, get out of MST mode
7475 drm_dbg_kms(&i915->drm,
7476 "MST device may have disappeared %d vs %d\n",
7478 intel_dp->mst_mgr.mst_state);
7479 intel_dp->is_mst = false;
7480 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7491 if (!intel_dp->is_mst) {
7494 handled = intel_dp_short_pulse(intel_dp);
7503 /* check the VBT to see whether the eDP is on another port */
7504 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7507 * eDP not supported on g4x. so bail out early just
7508 * for a bit extra safety in case the VBT is bonkers.
7510 if (INTEL_GEN(dev_priv) < 5)
7513 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7516 return intel_bios_is_port_edp(dev_priv, port);
7520 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7522 struct drm_i915_private *dev_priv = to_i915(connector->dev);
7523 enum port port = dp_to_dig_port(intel_dp)->base.port;
7525 if (!IS_G4X(dev_priv) && port != PORT_A)
7526 intel_attach_force_audio_property(connector);
7528 intel_attach_broadcast_rgb_property(connector);
7529 if (HAS_GMCH(dev_priv))
7530 drm_connector_attach_max_bpc_property(connector, 6, 10);
7531 else if (INTEL_GEN(dev_priv) >= 5)
7532 drm_connector_attach_max_bpc_property(connector, 6, 12);
7534 intel_attach_colorspace_property(connector);
7536 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7537 drm_object_attach_property(&connector->base,
7538 connector->dev->mode_config.hdr_output_metadata_property,
7541 if (intel_dp_is_edp(intel_dp)) {
7542 u32 allowed_scalers;
7544 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7545 if (!HAS_GMCH(dev_priv))
7546 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7548 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7550 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7555 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7557 intel_dp->panel_power_off_time = ktime_get_boottime();
7558 intel_dp->last_power_on = jiffies;
7559 intel_dp->last_backlight_off = jiffies;
7563 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7565 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7566 u32 pp_on, pp_off, pp_ctl;
7567 struct pps_registers regs;
7569 intel_pps_get_registers(intel_dp, ®s);
7571 pp_ctl = ilk_get_pp_control(intel_dp);
7573 /* Ensure PPS is unlocked */
7574 if (!HAS_DDI(dev_priv))
7575 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7577 pp_on = intel_de_read(dev_priv, regs.pp_on);
7578 pp_off = intel_de_read(dev_priv, regs.pp_off);
7580 /* Pull timing values out of registers */
7581 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7582 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7583 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7584 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7586 if (i915_mmio_reg_valid(regs.pp_div)) {
7589 pp_div = intel_de_read(dev_priv, regs.pp_div);
7591 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7593 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7598 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7600 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7602 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7606 intel_pps_verify_state(struct intel_dp *intel_dp)
7608 struct edp_power_seq hw;
7609 struct edp_power_seq *sw = &intel_dp->pps_delays;
7611 intel_pps_readout_hw_state(intel_dp, &hw);
7613 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7614 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7615 DRM_ERROR("PPS state mismatch\n");
7616 intel_pps_dump_state("sw", sw);
7617 intel_pps_dump_state("hw", &hw);
7622 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7624 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7625 struct edp_power_seq cur, vbt, spec,
7626 *final = &intel_dp->pps_delays;
7628 lockdep_assert_held(&dev_priv->pps_mutex);
7630 /* already initialized? */
7631 if (final->t11_t12 != 0)
7634 intel_pps_readout_hw_state(intel_dp, &cur);
7636 intel_pps_dump_state("cur", &cur);
7638 vbt = dev_priv->vbt.edp.pps;
7639 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7640 * of 500ms appears to be too short. Ocassionally the panel
7641 * just fails to power back on. Increasing the delay to 800ms
7642 * seems sufficient to avoid this problem.
7644 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7645 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7646 drm_dbg_kms(&dev_priv->drm,
7647 "Increasing T12 panel delay as per the quirk to %d\n",
7650 /* T11_T12 delay is special and actually in units of 100ms, but zero
7651 * based in the hw (so we need to add 100 ms). But the sw vbt
7652 * table multiplies it with 1000 to make it in units of 100usec,
7654 vbt.t11_t12 += 100 * 10;
7656 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7657 * our hw here, which are all in 100usec. */
7658 spec.t1_t3 = 210 * 10;
7659 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7660 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7661 spec.t10 = 500 * 10;
7662 /* This one is special and actually in units of 100ms, but zero
7663 * based in the hw (so we need to add 100 ms). But the sw vbt
7664 * table multiplies it with 1000 to make it in units of 100usec,
7666 spec.t11_t12 = (510 + 100) * 10;
7668 intel_pps_dump_state("vbt", &vbt);
7670 /* Use the max of the register settings and vbt. If both are
7671 * unset, fall back to the spec limits. */
7672 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
7674 max(cur.field, vbt.field))
7675 assign_final(t1_t3);
7679 assign_final(t11_t12);
7682 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
7683 intel_dp->panel_power_up_delay = get_delay(t1_t3);
7684 intel_dp->backlight_on_delay = get_delay(t8);
7685 intel_dp->backlight_off_delay = get_delay(t9);
7686 intel_dp->panel_power_down_delay = get_delay(t10);
7687 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7690 drm_dbg_kms(&dev_priv->drm,
7691 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7692 intel_dp->panel_power_up_delay,
7693 intel_dp->panel_power_down_delay,
7694 intel_dp->panel_power_cycle_delay);
7696 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7697 intel_dp->backlight_on_delay,
7698 intel_dp->backlight_off_delay);
7701 * We override the HW backlight delays to 1 because we do manual waits
7702 * on them. For T8, even BSpec recommends doing it. For T9, if we
7703 * don't do this, we'll end up waiting for the backlight off delay
7704 * twice: once when we do the manual sleep, and once when we disable
7705 * the panel and wait for the PP_STATUS bit to become zero.
7711 * HW has only a 100msec granularity for t11_t12 so round it up
7714 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7718 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7719 bool force_disable_vdd)
7721 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7722 u32 pp_on, pp_off, port_sel = 0;
7723 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7724 struct pps_registers regs;
7725 enum port port = dp_to_dig_port(intel_dp)->base.port;
7726 const struct edp_power_seq *seq = &intel_dp->pps_delays;
7728 lockdep_assert_held(&dev_priv->pps_mutex);
7730 intel_pps_get_registers(intel_dp, ®s);
7733 * On some VLV machines the BIOS can leave the VDD
7734 * enabled even on power sequencers which aren't
7735 * hooked up to any port. This would mess up the
7736 * power domain tracking the first time we pick
7737 * one of these power sequencers for use since
7738 * edp_panel_vdd_on() would notice that the VDD was
7739 * already on and therefore wouldn't grab the power
7740 * domain reference. Disable VDD first to avoid this.
7741 * This also avoids spuriously turning the VDD on as
7742 * soon as the new power sequencer gets initialized.
7744 if (force_disable_vdd) {
7745 u32 pp = ilk_get_pp_control(intel_dp);
7747 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7748 "Panel power already on\n");
7750 if (pp & EDP_FORCE_VDD)
7751 drm_dbg_kms(&dev_priv->drm,
7752 "VDD already on, disabling first\n");
7754 pp &= ~EDP_FORCE_VDD;
7756 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7759 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7760 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7761 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7762 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7764 /* Haswell doesn't have any port selection bits for the panel
7765 * power sequencer any more. */
7766 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7767 port_sel = PANEL_PORT_SELECT_VLV(port);
7768 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7771 port_sel = PANEL_PORT_SELECT_DPA;
7774 port_sel = PANEL_PORT_SELECT_DPC;
7777 port_sel = PANEL_PORT_SELECT_DPD;
7787 intel_de_write(dev_priv, regs.pp_on, pp_on);
7788 intel_de_write(dev_priv, regs.pp_off, pp_off);
7791 * Compute the divisor for the pp clock, simply match the Bspec formula.
7793 if (i915_mmio_reg_valid(regs.pp_div)) {
7794 intel_de_write(dev_priv, regs.pp_div,
7795 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7799 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7800 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7801 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7802 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7805 drm_dbg_kms(&dev_priv->drm,
7806 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7807 intel_de_read(dev_priv, regs.pp_on),
7808 intel_de_read(dev_priv, regs.pp_off),
7809 i915_mmio_reg_valid(regs.pp_div) ?
7810 intel_de_read(dev_priv, regs.pp_div) :
7811 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7814 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7816 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7818 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7819 vlv_initial_power_sequencer_setup(intel_dp);
7821 intel_dp_init_panel_power_sequencer(intel_dp);
7822 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7827 * intel_dp_set_drrs_state - program registers for RR switch to take effect
7828 * @dev_priv: i915 device
7829 * @crtc_state: a pointer to the active intel_crtc_state
7830 * @refresh_rate: RR to be programmed
7832 * This function gets called when refresh rate (RR) has to be changed from
7833 * one frequency to another. Switches can be between high and low RR
7834 * supported by the panel or to any other RR based on media playback (in
7835 * this case, RR value needs to be passed from user space).
7837 * The caller of this function needs to take a lock on dev_priv->drrs.
7839 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7840 const struct intel_crtc_state *crtc_state,
7843 struct intel_dp *intel_dp = dev_priv->drrs.dp;
7844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7845 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7847 if (refresh_rate <= 0) {
7848 drm_dbg_kms(&dev_priv->drm,
7849 "Refresh rate should be positive non-zero.\n");
7853 if (intel_dp == NULL) {
7854 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7859 drm_dbg_kms(&dev_priv->drm,
7860 "DRRS: intel_crtc not initialized\n");
7864 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7865 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7869 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7871 index = DRRS_LOW_RR;
7873 if (index == dev_priv->drrs.refresh_rate_type) {
7874 drm_dbg_kms(&dev_priv->drm,
7875 "DRRS requested for previously set RR...ignoring\n");
7879 if (!crtc_state->hw.active) {
7880 drm_dbg_kms(&dev_priv->drm,
7881 "eDP encoder disabled. CRTC not Active\n");
7885 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7888 intel_dp_set_m_n(crtc_state, M1_N1);
7891 intel_dp_set_m_n(crtc_state, M2_N2);
7895 drm_err(&dev_priv->drm,
7896 "Unsupported refreshrate type\n");
7898 } else if (INTEL_GEN(dev_priv) > 6) {
7899 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7902 val = intel_de_read(dev_priv, reg);
7903 if (index > DRRS_HIGH_RR) {
7904 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7905 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7907 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7909 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7910 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7912 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7914 intel_de_write(dev_priv, reg, val);
7917 dev_priv->drrs.refresh_rate_type = index;
7919 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7924 * intel_edp_drrs_enable - init drrs struct if supported
7925 * @intel_dp: DP struct
7926 * @crtc_state: A pointer to the active crtc state.
7928 * Initializes frontbuffer_bits and drrs.dp
7930 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7931 const struct intel_crtc_state *crtc_state)
7933 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7935 if (!crtc_state->has_drrs) {
7936 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7940 if (dev_priv->psr.enabled) {
7941 drm_dbg_kms(&dev_priv->drm,
7942 "PSR enabled. Not enabling DRRS.\n");
7946 mutex_lock(&dev_priv->drrs.mutex);
7947 if (dev_priv->drrs.dp) {
7948 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7952 dev_priv->drrs.busy_frontbuffer_bits = 0;
7954 dev_priv->drrs.dp = intel_dp;
7957 mutex_unlock(&dev_priv->drrs.mutex);
7961 * intel_edp_drrs_disable - Disable DRRS
7962 * @intel_dp: DP struct
7963 * @old_crtc_state: Pointer to old crtc_state.
7966 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7967 const struct intel_crtc_state *old_crtc_state)
7969 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7971 if (!old_crtc_state->has_drrs)
7974 mutex_lock(&dev_priv->drrs.mutex);
7975 if (!dev_priv->drrs.dp) {
7976 mutex_unlock(&dev_priv->drrs.mutex);
7980 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7981 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7982 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7984 dev_priv->drrs.dp = NULL;
7985 mutex_unlock(&dev_priv->drrs.mutex);
7987 cancel_delayed_work_sync(&dev_priv->drrs.work);
7990 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7992 struct drm_i915_private *dev_priv =
7993 container_of(work, typeof(*dev_priv), drrs.work.work);
7994 struct intel_dp *intel_dp;
7996 mutex_lock(&dev_priv->drrs.mutex);
7998 intel_dp = dev_priv->drrs.dp;
8004 * The delayed work can race with an invalidate hence we need to
8008 if (dev_priv->drrs.busy_frontbuffer_bits)
8011 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
8012 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8014 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8015 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
8019 mutex_unlock(&dev_priv->drrs.mutex);
8023 * intel_edp_drrs_invalidate - Disable Idleness DRRS
8024 * @dev_priv: i915 device
8025 * @frontbuffer_bits: frontbuffer plane tracking bits
8027 * This function gets called everytime rendering on the given planes start.
8028 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
8030 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8032 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
8033 unsigned int frontbuffer_bits)
8035 struct drm_crtc *crtc;
8038 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8041 cancel_delayed_work(&dev_priv->drrs.work);
8043 mutex_lock(&dev_priv->drrs.mutex);
8044 if (!dev_priv->drrs.dp) {
8045 mutex_unlock(&dev_priv->drrs.mutex);
8049 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
8050 pipe = to_intel_crtc(crtc)->pipe;
8052 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8053 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
8055 /* invalidate means busy screen hence upclock */
8056 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8057 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8058 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8060 mutex_unlock(&dev_priv->drrs.mutex);
8064 * intel_edp_drrs_flush - Restart Idleness DRRS
8065 * @dev_priv: i915 device
8066 * @frontbuffer_bits: frontbuffer plane tracking bits
8068 * This function gets called every time rendering on the given planes has
8069 * completed or flip on a crtc is completed. So DRRS should be upclocked
8070 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
8071 * if no other planes are dirty.
8073 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8075 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
8076 unsigned int frontbuffer_bits)
8078 struct drm_crtc *crtc;
8081 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8084 cancel_delayed_work(&dev_priv->drrs.work);
8086 mutex_lock(&dev_priv->drrs.mutex);
8087 if (!dev_priv->drrs.dp) {
8088 mutex_unlock(&dev_priv->drrs.mutex);
8092 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
8093 pipe = to_intel_crtc(crtc)->pipe;
8095 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8096 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
8098 /* flush means busy screen hence upclock */
8099 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8100 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8101 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8104 * flush also means no more activity hence schedule downclock, if all
8105 * other fbs are quiescent too
8107 if (!dev_priv->drrs.busy_frontbuffer_bits)
8108 schedule_delayed_work(&dev_priv->drrs.work,
8109 msecs_to_jiffies(1000));
8110 mutex_unlock(&dev_priv->drrs.mutex);
8114 * DOC: Display Refresh Rate Switching (DRRS)
8116 * Display Refresh Rate Switching (DRRS) is a power conservation feature
8117 * which enables swtching between low and high refresh rates,
8118 * dynamically, based on the usage scenario. This feature is applicable
8119 * for internal panels.
8121 * Indication that the panel supports DRRS is given by the panel EDID, which
8122 * would list multiple refresh rates for one resolution.
8124 * DRRS is of 2 types - static and seamless.
8125 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
8126 * (may appear as a blink on screen) and is used in dock-undock scenario.
8127 * Seamless DRRS involves changing RR without any visual effect to the user
8128 * and can be used during normal system usage. This is done by programming
8129 * certain registers.
8131 * Support for static/seamless DRRS may be indicated in the VBT based on
8132 * inputs from the panel spec.
8134 * DRRS saves power by switching to low RR based on usage scenarios.
8136 * The implementation is based on frontbuffer tracking implementation. When
8137 * there is a disturbance on the screen triggered by user activity or a periodic
8138 * system activity, DRRS is disabled (RR is changed to high RR). When there is
8139 * no movement on screen, after a timeout of 1 second, a switch to low RR is
8142 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8143 * and intel_edp_drrs_flush() are called.
8145 * DRRS can be further extended to support other internal panels and also
8146 * the scenario of video playback wherein RR is set based on the rate
8147 * requested by userspace.
8151 * intel_dp_drrs_init - Init basic DRRS work and mutex.
8152 * @connector: eDP connector
8153 * @fixed_mode: preferred mode of panel
8155 * This function is called only once at driver load to initialize basic
8159 * Downclock mode if panel supports it, else return NULL.
8160 * DRRS support is determined by the presence of downclock mode (apart
8161 * from VBT setting).
8163 static struct drm_display_mode *
8164 intel_dp_drrs_init(struct intel_connector *connector,
8165 struct drm_display_mode *fixed_mode)
8167 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8168 struct drm_display_mode *downclock_mode = NULL;
8170 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8171 mutex_init(&dev_priv->drrs.mutex);
8173 if (INTEL_GEN(dev_priv) <= 6) {
8174 drm_dbg_kms(&dev_priv->drm,
8175 "DRRS supported for Gen7 and above\n");
8179 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8180 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8184 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8185 if (!downclock_mode) {
8186 drm_dbg_kms(&dev_priv->drm,
8187 "Downclock mode is not found. DRRS not supported\n");
8191 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8193 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8194 drm_dbg_kms(&dev_priv->drm,
8195 "seamless DRRS supported for eDP panel.\n");
8196 return downclock_mode;
8199 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8200 struct intel_connector *intel_connector)
8202 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8203 struct drm_device *dev = &dev_priv->drm;
8204 struct drm_connector *connector = &intel_connector->base;
8205 struct drm_display_mode *fixed_mode = NULL;
8206 struct drm_display_mode *downclock_mode = NULL;
8208 enum pipe pipe = INVALID_PIPE;
8209 intel_wakeref_t wakeref;
8212 if (!intel_dp_is_edp(intel_dp))
8215 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8218 * On IBX/CPT we may get here with LVDS already registered. Since the
8219 * driver uses the only internal power sequencer available for both
8220 * eDP and LVDS bail out early in this case to prevent interfering
8221 * with an already powered-on LVDS power sequencer.
8223 if (intel_get_lvds_encoder(dev_priv)) {
8225 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8226 drm_info(&dev_priv->drm,
8227 "LVDS was detected, not registering eDP\n");
8232 with_pps_lock(intel_dp, wakeref) {
8233 intel_dp_init_panel_power_timestamps(intel_dp);
8234 intel_dp_pps_init(intel_dp);
8235 intel_edp_panel_vdd_sanitize(intel_dp);
8238 /* Cache DPCD and EDID for edp. */
8239 has_dpcd = intel_edp_init_dpcd(intel_dp);
8242 /* if this fails, presume the device is a ghost */
8243 drm_info(&dev_priv->drm,
8244 "failed to retrieve link info, disabling eDP\n");
8248 mutex_lock(&dev->mode_config.mutex);
8249 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8251 if (drm_add_edid_modes(connector, edid)) {
8252 drm_connector_update_edid_property(connector, edid);
8253 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8256 edid = ERR_PTR(-EINVAL);
8259 edid = ERR_PTR(-ENOENT);
8261 intel_connector->edid = edid;
8263 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8265 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8267 /* fallback to VBT if available for eDP */
8269 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8270 mutex_unlock(&dev->mode_config.mutex);
8272 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8273 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8274 register_reboot_notifier(&intel_dp->edp_notifier);
8277 * Figure out the current pipe for the initial backlight setup.
8278 * If the current pipe isn't valid, try the PPS pipe, and if that
8279 * fails just assume pipe A.
8281 pipe = vlv_active_pipe(intel_dp);
8283 if (pipe != PIPE_A && pipe != PIPE_B)
8284 pipe = intel_dp->pps_pipe;
8286 if (pipe != PIPE_A && pipe != PIPE_B)
8289 drm_dbg_kms(&dev_priv->drm,
8290 "using pipe %c for initial backlight setup\n",
8294 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8295 intel_connector->panel.backlight.power = intel_edp_backlight_power;
8296 intel_panel_setup_backlight(connector, pipe);
8299 drm_connector_set_panel_orientation_with_quirk(connector,
8300 dev_priv->vbt.orientation,
8301 fixed_mode->hdisplay, fixed_mode->vdisplay);
8307 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8309 * vdd might still be enabled do to the delayed vdd off.
8310 * Make sure vdd is actually turned off here.
8312 with_pps_lock(intel_dp, wakeref)
8313 edp_panel_vdd_off_sync(intel_dp);
8318 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8320 struct intel_connector *intel_connector;
8321 struct drm_connector *connector;
8323 intel_connector = container_of(work, typeof(*intel_connector),
8324 modeset_retry_work);
8325 connector = &intel_connector->base;
8326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8329 /* Grab the locks before changing connector property*/
8330 mutex_lock(&connector->dev->mode_config.mutex);
8331 /* Set connector link status to BAD and send a Uevent to notify
8332 * userspace to do a modeset.
8334 drm_connector_set_link_status_property(connector,
8335 DRM_MODE_LINK_STATUS_BAD);
8336 mutex_unlock(&connector->dev->mode_config.mutex);
8337 /* Send Hotplug uevent so userspace can reprobe */
8338 drm_kms_helper_hotplug_event(connector->dev);
8342 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8343 struct intel_connector *intel_connector)
8345 struct drm_connector *connector = &intel_connector->base;
8346 struct intel_dp *intel_dp = &intel_dig_port->dp;
8347 struct intel_encoder *intel_encoder = &intel_dig_port->base;
8348 struct drm_device *dev = intel_encoder->base.dev;
8349 struct drm_i915_private *dev_priv = to_i915(dev);
8350 enum port port = intel_encoder->port;
8351 enum phy phy = intel_port_to_phy(dev_priv, port);
8354 /* Initialize the work for modeset in case of link train failure */
8355 INIT_WORK(&intel_connector->modeset_retry_work,
8356 intel_dp_modeset_retry_work_fn);
8358 if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8359 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8360 intel_dig_port->max_lanes, intel_encoder->base.base.id,
8361 intel_encoder->base.name))
8364 intel_dp_set_source_rates(intel_dp);
8366 intel_dp->reset_link_params = true;
8367 intel_dp->pps_pipe = INVALID_PIPE;
8368 intel_dp->active_pipe = INVALID_PIPE;
8370 /* Preserve the current hw state. */
8371 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8372 intel_dp->attached_connector = intel_connector;
8374 if (intel_dp_is_port_edp(dev_priv, port)) {
8376 * Currently we don't support eDP on TypeC ports, although in
8377 * theory it could work on TypeC legacy ports.
8379 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8380 type = DRM_MODE_CONNECTOR_eDP;
8382 type = DRM_MODE_CONNECTOR_DisplayPort;
8385 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8386 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8389 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8390 * for DP the encoder type can be set by the caller to
8391 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8393 if (type == DRM_MODE_CONNECTOR_eDP)
8394 intel_encoder->type = INTEL_OUTPUT_EDP;
8396 /* eDP only on port B and/or C on vlv/chv */
8397 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8398 IS_CHERRYVIEW(dev_priv)) &&
8399 intel_dp_is_edp(intel_dp) &&
8400 port != PORT_B && port != PORT_C))
8403 drm_dbg_kms(&dev_priv->drm,
8404 "Adding %s connector on [ENCODER:%d:%s]\n",
8405 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8406 intel_encoder->base.base.id, intel_encoder->base.name);
8408 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8409 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8411 if (!HAS_GMCH(dev_priv))
8412 connector->interlace_allowed = true;
8413 connector->doublescan_allowed = 0;
8415 if (INTEL_GEN(dev_priv) >= 11)
8416 connector->ycbcr_420_allowed = true;
8418 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8419 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8421 intel_dp_aux_init(intel_dp);
8423 intel_connector_attach_encoder(intel_connector, intel_encoder);
8425 if (HAS_DDI(dev_priv))
8426 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8428 intel_connector->get_hw_state = intel_connector_get_hw_state;
8430 /* init MST on ports that can support it */
8431 intel_dp_mst_encoder_init(intel_dig_port,
8432 intel_connector->base.base.id);
8434 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8435 intel_dp_aux_fini(intel_dp);
8436 intel_dp_mst_encoder_cleanup(intel_dig_port);
8440 intel_dp_add_properties(intel_dp, connector);
8442 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8443 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8445 drm_dbg_kms(&dev_priv->drm,
8446 "HDCP init failed, skipping.\n");
8449 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8450 * 0xd. Failure to do so will result in spurious interrupts being
8451 * generated on the port when a cable is not attached.
8453 if (IS_G45(dev_priv)) {
8454 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8455 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8456 (temp & ~0xf) | 0xd);
8462 drm_connector_cleanup(connector);
8467 bool intel_dp_init(struct drm_i915_private *dev_priv,
8468 i915_reg_t output_reg,
8471 struct intel_digital_port *intel_dig_port;
8472 struct intel_encoder *intel_encoder;
8473 struct drm_encoder *encoder;
8474 struct intel_connector *intel_connector;
8476 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8477 if (!intel_dig_port)
8480 intel_connector = intel_connector_alloc();
8481 if (!intel_connector)
8482 goto err_connector_alloc;
8484 intel_encoder = &intel_dig_port->base;
8485 encoder = &intel_encoder->base;
8487 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8488 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8489 "DP %c", port_name(port)))
8490 goto err_encoder_init;
8492 intel_encoder->hotplug = intel_dp_hotplug;
8493 intel_encoder->compute_config = intel_dp_compute_config;
8494 intel_encoder->get_hw_state = intel_dp_get_hw_state;
8495 intel_encoder->get_config = intel_dp_get_config;
8496 intel_encoder->update_pipe = intel_panel_update_backlight;
8497 intel_encoder->suspend = intel_dp_encoder_suspend;
8498 if (IS_CHERRYVIEW(dev_priv)) {
8499 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8500 intel_encoder->pre_enable = chv_pre_enable_dp;
8501 intel_encoder->enable = vlv_enable_dp;
8502 intel_encoder->disable = vlv_disable_dp;
8503 intel_encoder->post_disable = chv_post_disable_dp;
8504 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8505 } else if (IS_VALLEYVIEW(dev_priv)) {
8506 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8507 intel_encoder->pre_enable = vlv_pre_enable_dp;
8508 intel_encoder->enable = vlv_enable_dp;
8509 intel_encoder->disable = vlv_disable_dp;
8510 intel_encoder->post_disable = vlv_post_disable_dp;
8512 intel_encoder->pre_enable = g4x_pre_enable_dp;
8513 intel_encoder->enable = g4x_enable_dp;
8514 intel_encoder->disable = g4x_disable_dp;
8515 intel_encoder->post_disable = g4x_post_disable_dp;
8518 intel_dig_port->dp.output_reg = output_reg;
8519 intel_dig_port->max_lanes = 4;
8520 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
8521 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
8523 intel_encoder->type = INTEL_OUTPUT_DP;
8524 intel_encoder->power_domain = intel_port_to_power_domain(port);
8525 if (IS_CHERRYVIEW(dev_priv)) {
8527 intel_encoder->pipe_mask = BIT(PIPE_C);
8529 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8531 intel_encoder->pipe_mask = ~0;
8533 intel_encoder->cloneable = 0;
8534 intel_encoder->port = port;
8536 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8539 intel_infoframe_init(intel_dig_port);
8541 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8542 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8543 goto err_init_connector;
8548 drm_encoder_cleanup(encoder);
8550 kfree(intel_connector);
8551 err_connector_alloc:
8552 kfree(intel_dig_port);
8556 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8558 struct intel_encoder *encoder;
8560 for_each_intel_encoder(&dev_priv->drm, encoder) {
8561 struct intel_dp *intel_dp;
8563 if (encoder->type != INTEL_OUTPUT_DDI)
8566 intel_dp = enc_to_intel_dp(encoder);
8568 if (!intel_dp->can_mst)
8571 if (intel_dp->is_mst)
8572 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8576 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8578 struct intel_encoder *encoder;
8580 for_each_intel_encoder(&dev_priv->drm, encoder) {
8581 struct intel_dp *intel_dp;
8584 if (encoder->type != INTEL_OUTPUT_DDI)
8587 intel_dp = enc_to_intel_dp(encoder);
8589 if (!intel_dp->can_mst)
8592 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8595 intel_dp->is_mst = false;
8596 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,