2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_probe_helper.h>
43 #include "i915_debugfs.h"
45 #include "i915_trace.h"
46 #include "intel_atomic.h"
47 #include "intel_audio.h"
48 #include "intel_connector.h"
49 #include "intel_ddi.h"
50 #include "intel_display_types.h"
52 #include "intel_dp_link_training.h"
53 #include "intel_dp_mst.h"
54 #include "intel_dpio_phy.h"
55 #include "intel_fifo_underrun.h"
56 #include "intel_hdcp.h"
57 #include "intel_hdmi.h"
58 #include "intel_hotplug.h"
59 #include "intel_lspcon.h"
60 #include "intel_lvds.h"
61 #include "intel_panel.h"
62 #include "intel_psr.h"
63 #include "intel_sideband.h"
65 #include "intel_vdsc.h"
67 #define DP_DPRX_ESI_LEN 14
69 /* DP DSC throughput values used for slice count calculations KPixels/s */
70 #define DP_DSC_PEAK_PIXEL_RATE 2720000
71 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
72 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
74 /* DP DSC FEC Overhead factor = 1/(0.972261) */
75 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
77 /* Compliance test status bits */
78 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
79 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
80 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
81 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
88 static const struct dp_link_dpll g4x_dpll[] = {
90 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
92 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
95 static const struct dp_link_dpll pch_dpll[] = {
97 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
99 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
102 static const struct dp_link_dpll vlv_dpll[] = {
104 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
106 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
110 * CHV supports eDP 1.4 that have more link rates.
111 * Below only provides the fixed rate but exclude variable rate.
113 static const struct dp_link_dpll chv_dpll[] = {
115 * CHV requires to program fractional division for m2.
116 * m2 is stored in fixed point format using formula below
117 * (m2_int << 22) | m2_fraction
119 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
120 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
121 { 270000, /* m2_int = 27, m2_fraction = 0 */
122 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
125 /* Constants for DP DSC configurations */
126 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
128 /* With Single pipe configuration, HW is capable of supporting maximum
129 * of 4 slices per line.
131 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
134 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
135 * @intel_dp: DP struct
137 * If a CPU or PCH DP output is attached to an eDP panel, this function
138 * will return true, and false otherwise.
140 bool intel_dp_is_edp(struct intel_dp *intel_dp)
142 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
144 return dig_port->base.type == INTEL_OUTPUT_EDP;
147 static void intel_dp_link_down(struct intel_encoder *encoder,
148 const struct intel_crtc_state *old_crtc_state);
149 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
150 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
151 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
152 const struct intel_crtc_state *crtc_state);
153 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
155 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
157 /* update sink rates from dpcd */
158 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
160 static const int dp_rates[] = {
161 162000, 270000, 540000, 810000
165 if (drm_dp_has_quirk(&intel_dp->desc, 0,
166 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
167 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
168 static const int quirk_rates[] = { 162000, 270000, 324000 };
170 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
171 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
176 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
178 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
179 if (dp_rates[i] > max_rate)
181 intel_dp->sink_rates[i] = dp_rates[i];
184 intel_dp->num_sink_rates = i;
187 /* Get length of rates array potentially limited by max_rate. */
188 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
192 /* Limit results by potentially reduced max rate */
193 for (i = 0; i < len; i++) {
194 if (rates[len - i - 1] <= max_rate)
201 /* Get length of common rates array potentially limited by max_rate. */
202 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
205 return intel_dp_rate_limit_len(intel_dp->common_rates,
206 intel_dp->num_common_rates, max_rate);
209 /* Theoretical max between source and sink */
210 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
212 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
215 /* Theoretical max between source and sink */
216 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
218 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
219 int source_max = dig_port->max_lanes;
220 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
221 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
223 return min3(source_max, sink_max, fia_max);
226 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
228 return intel_dp->max_link_lane_count;
232 intel_dp_link_required(int pixel_clock, int bpp)
234 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
235 return DIV_ROUND_UP(pixel_clock * bpp, 8);
239 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
241 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
242 * link rate that is generally expressed in Gbps. Since, 8 bits of data
243 * is transmitted every LS_Clk per lane, there is no need to account for
244 * the channel encoding that is done in the PHY layer here.
247 return max_link_clock * max_lanes;
251 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
254 struct intel_encoder *encoder = &dig_port->base;
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
256 int max_dotclk = dev_priv->max_dotclk_freq;
259 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
261 if (type != DP_DS_PORT_TYPE_VGA)
264 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
265 intel_dp->downstream_ports);
267 if (ds_max_dotclk != 0)
268 max_dotclk = min(max_dotclk, ds_max_dotclk);
273 static int cnl_max_source_rate(struct intel_dp *intel_dp)
275 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
276 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
277 enum port port = dig_port->base.port;
279 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
281 /* Low voltage SKUs are limited to max of 5.4G */
282 if (voltage == VOLTAGE_INFO_0_85V)
285 /* For this SKU 8.1G is supported in all ports */
286 if (IS_CNL_WITH_PORT_F(dev_priv))
289 /* For other SKUs, max rate on ports A and D is 5.4G */
290 if (port == PORT_A || port == PORT_D)
296 static int icl_max_source_rate(struct intel_dp *intel_dp)
298 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
299 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
300 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
302 if (intel_phy_is_combo(dev_priv, phy) &&
303 !IS_ELKHARTLAKE(dev_priv) &&
304 !intel_dp_is_edp(intel_dp))
311 intel_dp_set_source_rates(struct intel_dp *intel_dp)
313 /* The values must be in increasing order */
314 static const int cnl_rates[] = {
315 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
317 static const int bxt_rates[] = {
318 162000, 216000, 243000, 270000, 324000, 432000, 540000
320 static const int skl_rates[] = {
321 162000, 216000, 270000, 324000, 432000, 540000
323 static const int hsw_rates[] = {
324 162000, 270000, 540000
326 static const int g4x_rates[] = {
329 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
330 struct intel_encoder *encoder = &dig_port->base;
331 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
332 const int *source_rates;
333 int size, max_rate = 0, vbt_max_rate;
335 /* This should only be done once */
336 drm_WARN_ON(&dev_priv->drm,
337 intel_dp->source_rates || intel_dp->num_source_rates);
339 if (INTEL_GEN(dev_priv) >= 10) {
340 source_rates = cnl_rates;
341 size = ARRAY_SIZE(cnl_rates);
342 if (IS_GEN(dev_priv, 10))
343 max_rate = cnl_max_source_rate(intel_dp);
345 max_rate = icl_max_source_rate(intel_dp);
346 } else if (IS_GEN9_LP(dev_priv)) {
347 source_rates = bxt_rates;
348 size = ARRAY_SIZE(bxt_rates);
349 } else if (IS_GEN9_BC(dev_priv)) {
350 source_rates = skl_rates;
351 size = ARRAY_SIZE(skl_rates);
352 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
353 IS_BROADWELL(dev_priv)) {
354 source_rates = hsw_rates;
355 size = ARRAY_SIZE(hsw_rates);
357 source_rates = g4x_rates;
358 size = ARRAY_SIZE(g4x_rates);
361 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
362 if (max_rate && vbt_max_rate)
363 max_rate = min(max_rate, vbt_max_rate);
364 else if (vbt_max_rate)
365 max_rate = vbt_max_rate;
368 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
370 intel_dp->source_rates = source_rates;
371 intel_dp->num_source_rates = size;
374 static int intersect_rates(const int *source_rates, int source_len,
375 const int *sink_rates, int sink_len,
378 int i = 0, j = 0, k = 0;
380 while (i < source_len && j < sink_len) {
381 if (source_rates[i] == sink_rates[j]) {
382 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
384 common_rates[k] = source_rates[i];
388 } else if (source_rates[i] < sink_rates[j]) {
397 /* return index of rate in rates array, or -1 if not found */
398 static int intel_dp_rate_index(const int *rates, int len, int rate)
402 for (i = 0; i < len; i++)
403 if (rate == rates[i])
409 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
411 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
413 drm_WARN_ON(&i915->drm,
414 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
416 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
417 intel_dp->num_source_rates,
418 intel_dp->sink_rates,
419 intel_dp->num_sink_rates,
420 intel_dp->common_rates);
422 /* Paranoia, there should always be something in common. */
423 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
424 intel_dp->common_rates[0] = 162000;
425 intel_dp->num_common_rates = 1;
429 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
433 * FIXME: we need to synchronize the current link parameters with
434 * hardware readout. Currently fast link training doesn't work on
437 if (link_rate == 0 ||
438 link_rate > intel_dp->max_link_rate)
441 if (lane_count == 0 ||
442 lane_count > intel_dp_max_lane_count(intel_dp))
448 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
452 const struct drm_display_mode *fixed_mode =
453 intel_dp->attached_connector->panel.fixed_mode;
454 int mode_rate, max_rate;
456 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
457 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
458 if (mode_rate > max_rate)
464 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
465 int link_rate, u8 lane_count)
467 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
471 * TODO: Enable fallback on MST links once MST link compute can handle
472 * the fallback params.
474 if (intel_dp->is_mst) {
475 drm_err(&i915->drm, "Link Training Unsuccessful\n");
479 index = intel_dp_rate_index(intel_dp->common_rates,
480 intel_dp->num_common_rates,
483 if (intel_dp_is_edp(intel_dp) &&
484 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
485 intel_dp->common_rates[index - 1],
487 drm_dbg_kms(&i915->drm,
488 "Retrying Link training for eDP with same parameters\n");
491 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
492 intel_dp->max_link_lane_count = lane_count;
493 } else if (lane_count > 1) {
494 if (intel_dp_is_edp(intel_dp) &&
495 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
496 intel_dp_max_common_rate(intel_dp),
498 drm_dbg_kms(&i915->drm,
499 "Retrying Link training for eDP with same parameters\n");
502 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
503 intel_dp->max_link_lane_count = lane_count >> 1;
505 drm_err(&i915->drm, "Link Training Unsuccessful\n");
512 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
514 return div_u64(mul_u32_u32(mode_clock, 1000000U),
515 DP_DSC_FEC_OVERHEAD_FACTOR);
519 small_joiner_ram_size_bits(struct drm_i915_private *i915)
521 if (INTEL_GEN(i915) >= 11)
527 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
528 u32 link_clock, u32 lane_count,
529 u32 mode_clock, u32 mode_hdisplay)
531 u32 bits_per_pixel, max_bpp_small_joiner_ram;
535 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
536 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
537 * for SST -> TimeSlotsPerMTP is 1,
538 * for MST -> TimeSlotsPerMTP has to be calculated
540 bits_per_pixel = (link_clock * lane_count * 8) /
541 intel_dp_mode_to_fec_clock(mode_clock);
542 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
544 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
545 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
547 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
548 max_bpp_small_joiner_ram);
551 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
552 * check, output bpp from small joiner RAM check)
554 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
556 /* Error out if the max bpp is less than smallest allowed valid bpp */
557 if (bits_per_pixel < valid_dsc_bpp[0]) {
558 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
559 bits_per_pixel, valid_dsc_bpp[0]);
563 /* Find the nearest match in the array of known BPPs from VESA */
564 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
565 if (bits_per_pixel < valid_dsc_bpp[i + 1])
568 bits_per_pixel = valid_dsc_bpp[i];
571 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
572 * fractional part is 0
574 return bits_per_pixel << 4;
577 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
578 int mode_clock, int mode_hdisplay)
580 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
581 u8 min_slice_count, i;
584 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
585 min_slice_count = DIV_ROUND_UP(mode_clock,
586 DP_DSC_MAX_ENC_THROUGHPUT_0);
588 min_slice_count = DIV_ROUND_UP(mode_clock,
589 DP_DSC_MAX_ENC_THROUGHPUT_1);
591 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
592 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
593 drm_dbg_kms(&i915->drm,
594 "Unsupported slice width %d by DP DSC Sink device\n",
598 /* Also take into account max slice width */
599 min_slice_count = min_t(u8, min_slice_count,
600 DIV_ROUND_UP(mode_hdisplay,
603 /* Find the closest match to the valid slice count values */
604 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
605 if (valid_dsc_slicecount[i] >
606 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
609 if (min_slice_count <= valid_dsc_slicecount[i])
610 return valid_dsc_slicecount[i];
613 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
618 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
622 * Older platforms don't like hdisplay==4096 with DP.
624 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
625 * and frame counter increment), but we don't get vblank interrupts,
626 * and the pipe underruns immediately. The link also doesn't seem
627 * to get trained properly.
629 * On CHV the vblank interrupts don't seem to disappear but
630 * otherwise the symptoms are similar.
632 * TODO: confirm the behaviour on HSW+
634 return hdisplay == 4096 && !HAS_DDI(dev_priv);
637 static enum drm_mode_status
638 intel_dp_mode_valid(struct drm_connector *connector,
639 struct drm_display_mode *mode)
641 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
642 struct intel_connector *intel_connector = to_intel_connector(connector);
643 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
644 struct drm_i915_private *dev_priv = to_i915(connector->dev);
645 int target_clock = mode->clock;
646 int max_rate, mode_rate, max_lanes, max_link_clock;
648 u16 dsc_max_output_bpp = 0;
649 u8 dsc_slice_count = 0;
651 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
652 return MODE_NO_DBLESCAN;
654 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
656 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
657 if (mode->hdisplay > fixed_mode->hdisplay)
660 if (mode->vdisplay > fixed_mode->vdisplay)
663 target_clock = fixed_mode->clock;
666 max_link_clock = intel_dp_max_link_rate(intel_dp);
667 max_lanes = intel_dp_max_lane_count(intel_dp);
669 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
670 mode_rate = intel_dp_link_required(target_clock, 18);
672 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
673 return MODE_H_ILLEGAL;
676 * Output bpp is stored in 6.4 format so right shift by 4 to get the
677 * integer value since we support only integer values of bpp.
679 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
680 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
681 if (intel_dp_is_edp(intel_dp)) {
683 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
685 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
687 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
689 intel_dp_dsc_get_output_bpp(dev_priv,
693 mode->hdisplay) >> 4;
695 intel_dp_dsc_get_slice_count(intel_dp,
701 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
702 target_clock > max_dotclk)
703 return MODE_CLOCK_HIGH;
705 if (mode->clock < 10000)
706 return MODE_CLOCK_LOW;
708 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
709 return MODE_H_ILLEGAL;
711 return intel_mode_valid_max_plane_size(dev_priv, mode);
714 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
721 for (i = 0; i < src_bytes; i++)
722 v |= ((u32)src[i]) << ((3 - i) * 8);
726 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
731 for (i = 0; i < dst_bytes; i++)
732 dst[i] = src >> ((3-i) * 8);
736 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
738 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
739 bool force_disable_vdd);
741 intel_dp_pps_init(struct intel_dp *intel_dp);
743 static intel_wakeref_t
744 pps_lock(struct intel_dp *intel_dp)
746 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
747 intel_wakeref_t wakeref;
750 * See intel_power_sequencer_reset() why we need
751 * a power domain reference here.
753 wakeref = intel_display_power_get(dev_priv,
754 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
756 mutex_lock(&dev_priv->pps_mutex);
761 static intel_wakeref_t
762 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
764 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
766 mutex_unlock(&dev_priv->pps_mutex);
767 intel_display_power_put(dev_priv,
768 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
773 #define with_pps_lock(dp, wf) \
774 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
777 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
779 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
780 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
781 enum pipe pipe = intel_dp->pps_pipe;
782 bool pll_enabled, release_cl_override = false;
783 enum dpio_phy phy = DPIO_PHY(pipe);
784 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
787 if (drm_WARN(&dev_priv->drm,
788 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
789 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
790 pipe_name(pipe), dig_port->base.base.base.id,
791 dig_port->base.base.name))
794 drm_dbg_kms(&dev_priv->drm,
795 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
796 pipe_name(pipe), dig_port->base.base.base.id,
797 dig_port->base.base.name);
799 /* Preserve the BIOS-computed detected bit. This is
800 * supposed to be read-only.
802 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
803 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
804 DP |= DP_PORT_WIDTH(1);
805 DP |= DP_LINK_TRAIN_PAT_1;
807 if (IS_CHERRYVIEW(dev_priv))
808 DP |= DP_PIPE_SEL_CHV(pipe);
810 DP |= DP_PIPE_SEL(pipe);
812 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
815 * The DPLL for the pipe must be enabled for this to work.
816 * So enable temporarily it if it's not already enabled.
819 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
820 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
822 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
823 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
824 drm_err(&dev_priv->drm,
825 "Failed to force on pll for pipe %c!\n",
832 * Similar magic as in intel_dp_enable_port().
833 * We _must_ do this port enable + disable trick
834 * to make this power sequencer lock onto the port.
835 * Otherwise even VDD force bit won't work.
837 intel_de_write(dev_priv, intel_dp->output_reg, DP);
838 intel_de_posting_read(dev_priv, intel_dp->output_reg);
840 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
841 intel_de_posting_read(dev_priv, intel_dp->output_reg);
843 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
844 intel_de_posting_read(dev_priv, intel_dp->output_reg);
847 vlv_force_pll_off(dev_priv, pipe);
849 if (release_cl_override)
850 chv_phy_powergate_ch(dev_priv, phy, ch, false);
854 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
856 struct intel_encoder *encoder;
857 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
860 * We don't have power sequencer currently.
861 * Pick one that's not used by other ports.
863 for_each_intel_dp(&dev_priv->drm, encoder) {
864 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
866 if (encoder->type == INTEL_OUTPUT_EDP) {
867 drm_WARN_ON(&dev_priv->drm,
868 intel_dp->active_pipe != INVALID_PIPE &&
869 intel_dp->active_pipe !=
872 if (intel_dp->pps_pipe != INVALID_PIPE)
873 pipes &= ~(1 << intel_dp->pps_pipe);
875 drm_WARN_ON(&dev_priv->drm,
876 intel_dp->pps_pipe != INVALID_PIPE);
878 if (intel_dp->active_pipe != INVALID_PIPE)
879 pipes &= ~(1 << intel_dp->active_pipe);
886 return ffs(pipes) - 1;
890 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
892 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
893 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
896 lockdep_assert_held(&dev_priv->pps_mutex);
898 /* We should never land here with regular DP ports */
899 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
901 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
902 intel_dp->active_pipe != intel_dp->pps_pipe);
904 if (intel_dp->pps_pipe != INVALID_PIPE)
905 return intel_dp->pps_pipe;
907 pipe = vlv_find_free_pps(dev_priv);
910 * Didn't find one. This should not happen since there
911 * are two power sequencers and up to two eDP ports.
913 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
916 vlv_steal_power_sequencer(dev_priv, pipe);
917 intel_dp->pps_pipe = pipe;
919 drm_dbg_kms(&dev_priv->drm,
920 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
921 pipe_name(intel_dp->pps_pipe),
922 dig_port->base.base.base.id,
923 dig_port->base.base.name);
925 /* init power sequencer on this pipe and port */
926 intel_dp_init_panel_power_sequencer(intel_dp);
927 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
930 * Even vdd force doesn't work until we've made
931 * the power sequencer lock in on the port.
933 vlv_power_sequencer_kick(intel_dp);
935 return intel_dp->pps_pipe;
939 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
941 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
942 int backlight_controller = dev_priv->vbt.backlight.controller;
944 lockdep_assert_held(&dev_priv->pps_mutex);
946 /* We should never land here with regular DP ports */
947 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
949 if (!intel_dp->pps_reset)
950 return backlight_controller;
952 intel_dp->pps_reset = false;
955 * Only the HW needs to be reprogrammed, the SW state is fixed and
956 * has been setup during connector init.
958 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
960 return backlight_controller;
963 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
966 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
969 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
972 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
975 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
978 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
985 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
987 vlv_pipe_check pipe_check)
991 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
992 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
993 PANEL_PORT_SELECT_MASK;
995 if (port_sel != PANEL_PORT_SELECT_VLV(port))
998 if (!pipe_check(dev_priv, pipe))
1004 return INVALID_PIPE;
1008 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1010 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1011 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1012 enum port port = dig_port->base.port;
1014 lockdep_assert_held(&dev_priv->pps_mutex);
1016 /* try to find a pipe with this port selected */
1017 /* first pick one where the panel is on */
1018 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1019 vlv_pipe_has_pp_on);
1020 /* didn't find one? pick one where vdd is on */
1021 if (intel_dp->pps_pipe == INVALID_PIPE)
1022 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1023 vlv_pipe_has_vdd_on);
1024 /* didn't find one? pick one with just the correct port */
1025 if (intel_dp->pps_pipe == INVALID_PIPE)
1026 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1029 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1030 if (intel_dp->pps_pipe == INVALID_PIPE) {
1031 drm_dbg_kms(&dev_priv->drm,
1032 "no initial power sequencer for [ENCODER:%d:%s]\n",
1033 dig_port->base.base.base.id,
1034 dig_port->base.base.name);
1038 drm_dbg_kms(&dev_priv->drm,
1039 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1040 dig_port->base.base.base.id,
1041 dig_port->base.base.name,
1042 pipe_name(intel_dp->pps_pipe));
1044 intel_dp_init_panel_power_sequencer(intel_dp);
1045 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1048 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1050 struct intel_encoder *encoder;
1052 if (drm_WARN_ON(&dev_priv->drm,
1053 !(IS_VALLEYVIEW(dev_priv) ||
1054 IS_CHERRYVIEW(dev_priv) ||
1055 IS_GEN9_LP(dev_priv))))
1059 * We can't grab pps_mutex here due to deadlock with power_domain
1060 * mutex when power_domain functions are called while holding pps_mutex.
1061 * That also means that in order to use pps_pipe the code needs to
1062 * hold both a power domain reference and pps_mutex, and the power domain
1063 * reference get/put must be done while _not_ holding pps_mutex.
1064 * pps_{lock,unlock}() do these steps in the correct order, so one
1065 * should use them always.
1068 for_each_intel_dp(&dev_priv->drm, encoder) {
1069 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1071 drm_WARN_ON(&dev_priv->drm,
1072 intel_dp->active_pipe != INVALID_PIPE);
1074 if (encoder->type != INTEL_OUTPUT_EDP)
1077 if (IS_GEN9_LP(dev_priv))
1078 intel_dp->pps_reset = true;
1080 intel_dp->pps_pipe = INVALID_PIPE;
1084 struct pps_registers {
1092 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1093 struct pps_registers *regs)
1095 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098 memset(regs, 0, sizeof(*regs));
1100 if (IS_GEN9_LP(dev_priv))
1101 pps_idx = bxt_power_sequencer_idx(intel_dp);
1102 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1103 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1105 regs->pp_ctrl = PP_CONTROL(pps_idx);
1106 regs->pp_stat = PP_STATUS(pps_idx);
1107 regs->pp_on = PP_ON_DELAYS(pps_idx);
1108 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1110 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1111 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1112 regs->pp_div = INVALID_MMIO_REG;
1114 regs->pp_div = PP_DIVISOR(pps_idx);
1118 _pp_ctrl_reg(struct intel_dp *intel_dp)
1120 struct pps_registers regs;
1122 intel_pps_get_registers(intel_dp, ®s);
1124 return regs.pp_ctrl;
1128 _pp_stat_reg(struct intel_dp *intel_dp)
1130 struct pps_registers regs;
1132 intel_pps_get_registers(intel_dp, ®s);
1134 return regs.pp_stat;
1137 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1138 This function only applicable when panel PM state is not to be tracked */
1139 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1142 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1144 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1145 intel_wakeref_t wakeref;
1147 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1150 with_pps_lock(intel_dp, wakeref) {
1151 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1153 i915_reg_t pp_ctrl_reg, pp_div_reg;
1156 pp_ctrl_reg = PP_CONTROL(pipe);
1157 pp_div_reg = PP_DIVISOR(pipe);
1158 pp_div = intel_de_read(dev_priv, pp_div_reg);
1159 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1161 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1162 intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1163 intel_de_write(dev_priv, pp_ctrl_reg,
1165 msleep(intel_dp->panel_power_cycle_delay);
1172 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1174 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1176 lockdep_assert_held(&dev_priv->pps_mutex);
1178 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1179 intel_dp->pps_pipe == INVALID_PIPE)
1182 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1185 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1187 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1189 lockdep_assert_held(&dev_priv->pps_mutex);
1191 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1192 intel_dp->pps_pipe == INVALID_PIPE)
1195 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1199 intel_dp_check_edp(struct intel_dp *intel_dp)
1201 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1203 if (!intel_dp_is_edp(intel_dp))
1206 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1207 drm_WARN(&dev_priv->drm, 1,
1208 "eDP powered off while attempting aux channel communication.\n");
1209 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1210 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1211 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1216 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1218 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1219 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1220 const unsigned int timeout_ms = 10;
1224 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1225 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1226 msecs_to_jiffies_timeout(timeout_ms));
1228 /* just trace the final value */
1229 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1233 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1234 intel_dp->aux.name, timeout_ms, status);
1240 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1242 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1248 * The clock divider is based off the hrawclk, and would like to run at
1249 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1251 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1254 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1256 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1257 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1264 * The clock divider is based off the cdclk or PCH rawclk, and would
1265 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1266 * divide by 2000 and use that
1268 if (dig_port->aux_ch == AUX_CH_A)
1269 freq = dev_priv->cdclk.hw.cdclk;
1271 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1272 return DIV_ROUND_CLOSEST(freq, 2000);
1275 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1277 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1278 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1280 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1281 /* Workaround for non-ULT HSW */
1289 return ilk_get_aux_clock_divider(intel_dp, index);
1292 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1295 * SKL doesn't need us to program the AUX clock divider (Hardware will
1296 * derive the clock from CDCLK automatically). We still implement the
1297 * get_aux_clock_divider vfunc to plug-in into the existing code.
1299 return index ? 0 : 1;
1302 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1304 u32 aux_clock_divider)
1306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1307 struct drm_i915_private *dev_priv =
1308 to_i915(dig_port->base.base.dev);
1309 u32 precharge, timeout;
1311 if (IS_GEN(dev_priv, 6))
1316 if (IS_BROADWELL(dev_priv))
1317 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1319 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1321 return DP_AUX_CH_CTL_SEND_BUSY |
1322 DP_AUX_CH_CTL_DONE |
1323 DP_AUX_CH_CTL_INTERRUPT |
1324 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1326 DP_AUX_CH_CTL_RECEIVE_ERROR |
1327 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1328 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1329 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1332 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1336 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1337 struct drm_i915_private *i915 =
1338 to_i915(dig_port->base.base.dev);
1339 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1342 ret = DP_AUX_CH_CTL_SEND_BUSY |
1343 DP_AUX_CH_CTL_DONE |
1344 DP_AUX_CH_CTL_INTERRUPT |
1345 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1346 DP_AUX_CH_CTL_TIME_OUT_MAX |
1347 DP_AUX_CH_CTL_RECEIVE_ERROR |
1348 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1349 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1350 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1352 if (intel_phy_is_tc(i915, phy) &&
1353 dig_port->tc_mode == TC_PORT_TBT_ALT)
1354 ret |= DP_AUX_CH_CTL_TBT_IO;
1360 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1361 const u8 *send, int send_bytes,
1362 u8 *recv, int recv_size,
1363 u32 aux_send_ctl_flags)
1365 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1366 struct drm_i915_private *i915 =
1367 to_i915(dig_port->base.base.dev);
1368 struct intel_uncore *uncore = &i915->uncore;
1369 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1370 bool is_tc_port = intel_phy_is_tc(i915, phy);
1371 i915_reg_t ch_ctl, ch_data[5];
1372 u32 aux_clock_divider;
1373 enum intel_display_power_domain aux_domain;
1374 intel_wakeref_t aux_wakeref;
1375 intel_wakeref_t pps_wakeref;
1376 int i, ret, recv_bytes;
1381 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1382 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1383 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1386 intel_tc_port_lock(dig_port);
1388 aux_domain = intel_aux_power_domain(dig_port);
1390 aux_wakeref = intel_display_power_get(i915, aux_domain);
1391 pps_wakeref = pps_lock(intel_dp);
1394 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1395 * In such cases we want to leave VDD enabled and it's up to upper layers
1396 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1399 vdd = edp_panel_vdd_on(intel_dp);
1401 /* dp aux is extremely sensitive to irq latency, hence request the
1402 * lowest possible wakeup latency and so prevent the cpu from going into
1403 * deep sleep states.
1405 cpu_latency_qos_update_request(&i915->pm_qos, 0);
1407 intel_dp_check_edp(intel_dp);
1409 /* Try to wait for any previous AUX channel activity */
1410 for (try = 0; try < 3; try++) {
1411 status = intel_uncore_read_notrace(uncore, ch_ctl);
1412 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1416 /* just trace the final value */
1417 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1420 const u32 status = intel_uncore_read(uncore, ch_ctl);
1422 if (status != intel_dp->aux_busy_last_status) {
1423 drm_WARN(&i915->drm, 1,
1424 "%s: not started (status 0x%08x)\n",
1425 intel_dp->aux.name, status);
1426 intel_dp->aux_busy_last_status = status;
1433 /* Only 5 data registers! */
1434 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1439 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1440 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1444 send_ctl |= aux_send_ctl_flags;
1446 /* Must try at least 3 times according to DP spec */
1447 for (try = 0; try < 5; try++) {
1448 /* Load the send data into the aux channel data registers */
1449 for (i = 0; i < send_bytes; i += 4)
1450 intel_uncore_write(uncore,
1452 intel_dp_pack_aux(send + i,
1455 /* Send the command and wait for it to complete */
1456 intel_uncore_write(uncore, ch_ctl, send_ctl);
1458 status = intel_dp_aux_wait_done(intel_dp);
1460 /* Clear done status and any errors */
1461 intel_uncore_write(uncore,
1464 DP_AUX_CH_CTL_DONE |
1465 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1466 DP_AUX_CH_CTL_RECEIVE_ERROR);
1468 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1469 * 400us delay required for errors and timeouts
1470 * Timeout errors from the HW already meet this
1471 * requirement so skip to next iteration
1473 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1476 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1477 usleep_range(400, 500);
1480 if (status & DP_AUX_CH_CTL_DONE)
1485 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1486 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1487 intel_dp->aux.name, status);
1493 /* Check for timeout or receive error.
1494 * Timeouts occur when the sink is not connected
1496 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1497 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1498 intel_dp->aux.name, status);
1503 /* Timeouts occur when the device isn't connected, so they're
1504 * "normal" -- don't fill the kernel log with these */
1505 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1506 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1507 intel_dp->aux.name, status);
1512 /* Unload any bytes sent back from the other side */
1513 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1514 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1517 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1518 * We have no idea of what happened so we return -EBUSY so
1519 * drm layer takes care for the necessary retries.
1521 if (recv_bytes == 0 || recv_bytes > 20) {
1522 drm_dbg_kms(&i915->drm,
1523 "%s: Forbidden recv_bytes = %d on aux transaction\n",
1524 intel_dp->aux.name, recv_bytes);
1529 if (recv_bytes > recv_size)
1530 recv_bytes = recv_size;
1532 for (i = 0; i < recv_bytes; i += 4)
1533 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1534 recv + i, recv_bytes - i);
1538 cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1541 edp_panel_vdd_off(intel_dp, false);
1543 pps_unlock(intel_dp, pps_wakeref);
1544 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1547 intel_tc_port_unlock(dig_port);
1552 #define BARE_ADDRESS_SIZE 3
1553 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1556 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1557 const struct drm_dp_aux_msg *msg)
1559 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1560 txbuf[1] = (msg->address >> 8) & 0xff;
1561 txbuf[2] = msg->address & 0xff;
1562 txbuf[3] = msg->size - 1;
1565 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1568 * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1569 * select bit to inform the hardware to send the Aksv after our header
1570 * since we can't access that data from software.
1572 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1573 msg->address == DP_AUX_HDCP_AKSV)
1574 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1580 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1583 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1584 u8 txbuf[20], rxbuf[20];
1585 size_t txsize, rxsize;
1586 u32 flags = intel_dp_aux_xfer_flags(msg);
1589 intel_dp_aux_header(txbuf, msg);
1591 switch (msg->request & ~DP_AUX_I2C_MOT) {
1592 case DP_AUX_NATIVE_WRITE:
1593 case DP_AUX_I2C_WRITE:
1594 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1595 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1596 rxsize = 2; /* 0 or 1 data bytes */
1598 if (drm_WARN_ON(&i915->drm, txsize > 20))
1601 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1604 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1606 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1607 rxbuf, rxsize, flags);
1609 msg->reply = rxbuf[0] >> 4;
1612 /* Number of bytes written in a short write. */
1613 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1615 /* Return payload size. */
1621 case DP_AUX_NATIVE_READ:
1622 case DP_AUX_I2C_READ:
1623 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1624 rxsize = msg->size + 1;
1626 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1629 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1630 rxbuf, rxsize, flags);
1632 msg->reply = rxbuf[0] >> 4;
1634 * Assume happy day, and copy the data. The caller is
1635 * expected to check msg->reply before touching it.
1637 * Return payload size.
1640 memcpy(msg->buffer, rxbuf + 1, ret);
1653 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1655 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1656 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1657 enum aux_ch aux_ch = dig_port->aux_ch;
1663 return DP_AUX_CH_CTL(aux_ch);
1665 MISSING_CASE(aux_ch);
1666 return DP_AUX_CH_CTL(AUX_CH_B);
1670 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1672 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1673 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1674 enum aux_ch aux_ch = dig_port->aux_ch;
1680 return DP_AUX_CH_DATA(aux_ch, index);
1682 MISSING_CASE(aux_ch);
1683 return DP_AUX_CH_DATA(AUX_CH_B, index);
1687 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1689 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1690 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1691 enum aux_ch aux_ch = dig_port->aux_ch;
1695 return DP_AUX_CH_CTL(aux_ch);
1699 return PCH_DP_AUX_CH_CTL(aux_ch);
1701 MISSING_CASE(aux_ch);
1702 return DP_AUX_CH_CTL(AUX_CH_A);
1706 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1708 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1710 enum aux_ch aux_ch = dig_port->aux_ch;
1714 return DP_AUX_CH_DATA(aux_ch, index);
1718 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1720 MISSING_CASE(aux_ch);
1721 return DP_AUX_CH_DATA(AUX_CH_A, index);
1725 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1727 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1728 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1729 enum aux_ch aux_ch = dig_port->aux_ch;
1739 return DP_AUX_CH_CTL(aux_ch);
1741 MISSING_CASE(aux_ch);
1742 return DP_AUX_CH_CTL(AUX_CH_A);
1746 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750 enum aux_ch aux_ch = dig_port->aux_ch;
1760 return DP_AUX_CH_DATA(aux_ch, index);
1762 MISSING_CASE(aux_ch);
1763 return DP_AUX_CH_DATA(AUX_CH_A, index);
1768 intel_dp_aux_fini(struct intel_dp *intel_dp)
1770 kfree(intel_dp->aux.name);
1774 intel_dp_aux_init(struct intel_dp *intel_dp)
1776 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1777 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1778 struct intel_encoder *encoder = &dig_port->base;
1780 if (INTEL_GEN(dev_priv) >= 9) {
1781 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1782 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1783 } else if (HAS_PCH_SPLIT(dev_priv)) {
1784 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1785 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1787 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1788 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1791 if (INTEL_GEN(dev_priv) >= 9)
1792 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1793 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1794 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1795 else if (HAS_PCH_SPLIT(dev_priv))
1796 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1798 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1800 if (INTEL_GEN(dev_priv) >= 9)
1801 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1803 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1805 drm_dp_aux_init(&intel_dp->aux);
1807 /* Failure to allocate our preferred name is not critical */
1808 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1809 aux_ch_name(dig_port->aux_ch),
1810 port_name(encoder->port));
1811 intel_dp->aux.transfer = intel_dp_aux_transfer;
1814 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1816 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1818 return max_rate >= 540000;
1821 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1823 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1825 return max_rate >= 810000;
1829 intel_dp_set_clock(struct intel_encoder *encoder,
1830 struct intel_crtc_state *pipe_config)
1832 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1833 const struct dp_link_dpll *divisor = NULL;
1836 if (IS_G4X(dev_priv)) {
1838 count = ARRAY_SIZE(g4x_dpll);
1839 } else if (HAS_PCH_SPLIT(dev_priv)) {
1841 count = ARRAY_SIZE(pch_dpll);
1842 } else if (IS_CHERRYVIEW(dev_priv)) {
1844 count = ARRAY_SIZE(chv_dpll);
1845 } else if (IS_VALLEYVIEW(dev_priv)) {
1847 count = ARRAY_SIZE(vlv_dpll);
1850 if (divisor && count) {
1851 for (i = 0; i < count; i++) {
1852 if (pipe_config->port_clock == divisor[i].clock) {
1853 pipe_config->dpll = divisor[i].dpll;
1854 pipe_config->clock_set = true;
1861 static void snprintf_int_array(char *str, size_t len,
1862 const int *array, int nelem)
1868 for (i = 0; i < nelem; i++) {
1869 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1877 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1879 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1880 char str[128]; /* FIXME: too big for stack? */
1882 if (!drm_debug_enabled(DRM_UT_KMS))
1885 snprintf_int_array(str, sizeof(str),
1886 intel_dp->source_rates, intel_dp->num_source_rates);
1887 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1889 snprintf_int_array(str, sizeof(str),
1890 intel_dp->sink_rates, intel_dp->num_sink_rates);
1891 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1893 snprintf_int_array(str, sizeof(str),
1894 intel_dp->common_rates, intel_dp->num_common_rates);
1895 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1899 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1901 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1904 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1905 if (drm_WARN_ON(&i915->drm, len <= 0))
1908 return intel_dp->common_rates[len - 1];
1911 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1913 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1914 int i = intel_dp_rate_index(intel_dp->sink_rates,
1915 intel_dp->num_sink_rates, rate);
1917 if (drm_WARN_ON(&i915->drm, i < 0))
1923 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1924 u8 *link_bw, u8 *rate_select)
1926 /* eDP 1.4 rate select method. */
1927 if (intel_dp->use_rate_select) {
1930 intel_dp_rate_select(intel_dp, port_clock);
1932 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1937 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1938 const struct intel_crtc_state *pipe_config)
1940 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1942 /* On TGL, FEC is supported on all Pipes */
1943 if (INTEL_GEN(dev_priv) >= 12)
1946 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1952 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1953 const struct intel_crtc_state *pipe_config)
1955 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1956 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1959 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1960 const struct intel_crtc_state *crtc_state)
1962 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1964 if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1967 return intel_dsc_source_support(encoder, crtc_state) &&
1968 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1971 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1972 struct intel_crtc_state *pipe_config)
1974 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1975 struct intel_connector *intel_connector = intel_dp->attached_connector;
1978 bpp = pipe_config->pipe_bpp;
1979 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1982 bpp = min(bpp, 3*bpc);
1984 if (intel_dp_is_edp(intel_dp)) {
1985 /* Get bpp from vbt only for panels that dont have bpp in edid */
1986 if (intel_connector->base.display_info.bpc == 0 &&
1987 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1988 drm_dbg_kms(&dev_priv->drm,
1989 "clamping bpp for eDP panel to BIOS-provided %i\n",
1990 dev_priv->vbt.edp.bpp);
1991 bpp = dev_priv->vbt.edp.bpp;
1998 /* Adjust link config limits based on compliance test requests. */
2000 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2001 struct intel_crtc_state *pipe_config,
2002 struct link_config_limits *limits)
2004 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2006 /* For DP Compliance we override the computed bpp for the pipe */
2007 if (intel_dp->compliance.test_data.bpc != 0) {
2008 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2010 limits->min_bpp = limits->max_bpp = bpp;
2011 pipe_config->dither_force_disable = bpp == 6 * 3;
2013 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2016 /* Use values requested by Compliance Test Request */
2017 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2020 /* Validate the compliance test data since max values
2021 * might have changed due to link train fallback.
2023 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2024 intel_dp->compliance.test_lane_count)) {
2025 index = intel_dp_rate_index(intel_dp->common_rates,
2026 intel_dp->num_common_rates,
2027 intel_dp->compliance.test_link_rate);
2029 limits->min_clock = limits->max_clock = index;
2030 limits->min_lane_count = limits->max_lane_count =
2031 intel_dp->compliance.test_lane_count;
2036 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2039 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2040 * format of the number of bytes per pixel will be half the number
2041 * of bytes of RGB pixel.
2043 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2049 /* Optimize link config in order: max bpp, min clock, min lanes */
2051 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2052 struct intel_crtc_state *pipe_config,
2053 const struct link_config_limits *limits)
2055 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2056 int bpp, clock, lane_count;
2057 int mode_rate, link_clock, link_avail;
2059 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2060 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2062 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2065 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2066 for (lane_count = limits->min_lane_count;
2067 lane_count <= limits->max_lane_count;
2069 link_clock = intel_dp->common_rates[clock];
2070 link_avail = intel_dp_max_data_rate(link_clock,
2073 if (mode_rate <= link_avail) {
2074 pipe_config->lane_count = lane_count;
2075 pipe_config->pipe_bpp = bpp;
2076 pipe_config->port_clock = link_clock;
2087 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2090 u8 dsc_bpc[3] = {0};
2092 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2094 for (i = 0; i < num_bpc; i++) {
2095 if (dsc_max_bpc >= dsc_bpc[i])
2096 return dsc_bpc[i] * 3;
2102 #define DSC_SUPPORTED_VERSION_MIN 1
2104 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2105 struct intel_crtc_state *crtc_state)
2107 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2108 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2109 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2113 ret = intel_dsc_compute_params(encoder, crtc_state);
2118 * Slice Height of 8 works for all currently available panels. So start
2119 * with that if pic_height is an integral multiple of 8. Eventually add
2120 * logic to try multiple slice heights.
2122 if (vdsc_cfg->pic_height % 8 == 0)
2123 vdsc_cfg->slice_height = 8;
2124 else if (vdsc_cfg->pic_height % 4 == 0)
2125 vdsc_cfg->slice_height = 4;
2127 vdsc_cfg->slice_height = 2;
2129 vdsc_cfg->dsc_version_major =
2130 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2131 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2132 vdsc_cfg->dsc_version_minor =
2133 min(DSC_SUPPORTED_VERSION_MIN,
2134 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2135 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2137 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2140 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2141 if (!line_buf_depth) {
2142 drm_dbg_kms(&i915->drm,
2143 "DSC Sink Line Buffer Depth invalid\n");
2147 if (vdsc_cfg->dsc_version_minor == 2)
2148 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2149 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2151 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2152 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2154 vdsc_cfg->block_pred_enable =
2155 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2156 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2158 return drm_dsc_compute_rc_parameters(vdsc_cfg);
2161 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2162 struct intel_crtc_state *pipe_config,
2163 struct drm_connector_state *conn_state,
2164 struct link_config_limits *limits)
2166 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2167 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2168 const struct drm_display_mode *adjusted_mode =
2169 &pipe_config->hw.adjusted_mode;
2174 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2175 intel_dp_supports_fec(intel_dp, pipe_config);
2177 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2180 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2181 if (INTEL_GEN(dev_priv) >= 12)
2182 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2184 dsc_max_bpc = min_t(u8, 10,
2185 conn_state->max_requested_bpc);
2187 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2189 /* Min Input BPC for ICL+ is 8 */
2190 if (pipe_bpp < 8 * 3) {
2191 drm_dbg_kms(&dev_priv->drm,
2192 "No DSC support for less than 8bpc\n");
2197 * For now enable DSC for max bpp, max link rate, max lane count.
2198 * Optimize this later for the minimum possible link rate/lane count
2199 * with DSC enabled for the requested mode.
2201 pipe_config->pipe_bpp = pipe_bpp;
2202 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2203 pipe_config->lane_count = limits->max_lane_count;
2205 if (intel_dp_is_edp(intel_dp)) {
2206 pipe_config->dsc.compressed_bpp =
2207 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2208 pipe_config->pipe_bpp);
2209 pipe_config->dsc.slice_count =
2210 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2213 u16 dsc_max_output_bpp;
2214 u8 dsc_dp_slice_count;
2216 dsc_max_output_bpp =
2217 intel_dp_dsc_get_output_bpp(dev_priv,
2218 pipe_config->port_clock,
2219 pipe_config->lane_count,
2220 adjusted_mode->crtc_clock,
2221 adjusted_mode->crtc_hdisplay);
2222 dsc_dp_slice_count =
2223 intel_dp_dsc_get_slice_count(intel_dp,
2224 adjusted_mode->crtc_clock,
2225 adjusted_mode->crtc_hdisplay);
2226 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2227 drm_dbg_kms(&dev_priv->drm,
2228 "Compressed BPP/Slice Count not supported\n");
2231 pipe_config->dsc.compressed_bpp = min_t(u16,
2232 dsc_max_output_bpp >> 4,
2233 pipe_config->pipe_bpp);
2234 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2237 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2238 * is greater than the maximum Cdclock and if slice count is even
2239 * then we need to use 2 VDSC instances.
2241 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2242 if (pipe_config->dsc.slice_count > 1) {
2243 pipe_config->dsc.dsc_split = true;
2245 drm_dbg_kms(&dev_priv->drm,
2246 "Cannot split stream to use 2 VDSC instances\n");
2251 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2253 drm_dbg_kms(&dev_priv->drm,
2254 "Cannot compute valid DSC parameters for Input Bpp = %d "
2255 "Compressed BPP = %d\n",
2256 pipe_config->pipe_bpp,
2257 pipe_config->dsc.compressed_bpp);
2261 pipe_config->dsc.compression_enable = true;
2262 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2263 "Compressed Bpp = %d Slice Count = %d\n",
2264 pipe_config->pipe_bpp,
2265 pipe_config->dsc.compressed_bpp,
2266 pipe_config->dsc.slice_count);
2271 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2273 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2280 intel_dp_compute_link_config(struct intel_encoder *encoder,
2281 struct intel_crtc_state *pipe_config,
2282 struct drm_connector_state *conn_state)
2284 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2285 const struct drm_display_mode *adjusted_mode =
2286 &pipe_config->hw.adjusted_mode;
2287 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2288 struct link_config_limits limits;
2292 common_len = intel_dp_common_len_rate_limit(intel_dp,
2293 intel_dp->max_link_rate);
2295 /* No common link rates between source and sink */
2296 drm_WARN_ON(encoder->base.dev, common_len <= 0);
2298 limits.min_clock = 0;
2299 limits.max_clock = common_len - 1;
2301 limits.min_lane_count = 1;
2302 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2304 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2305 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2307 if (intel_dp_is_edp(intel_dp)) {
2309 * Use the maximum clock and number of lanes the eDP panel
2310 * advertizes being capable of. The panels are generally
2311 * designed to support only a single clock and lane
2312 * configuration, and typically these values correspond to the
2313 * native resolution of the panel.
2315 limits.min_lane_count = limits.max_lane_count;
2316 limits.min_clock = limits.max_clock;
2319 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2321 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2322 "max rate %d max bpp %d pixel clock %iKHz\n",
2323 limits.max_lane_count,
2324 intel_dp->common_rates[limits.max_clock],
2325 limits.max_bpp, adjusted_mode->crtc_clock);
2328 * Optimize for slow and wide. This is the place to add alternative
2329 * optimization policy.
2331 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2333 /* enable compression if the mode doesn't fit available BW */
2334 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2335 if (ret || intel_dp->force_dsc_en) {
2336 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2337 conn_state, &limits);
2342 if (pipe_config->dsc.compression_enable) {
2343 drm_dbg_kms(&i915->drm,
2344 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2345 pipe_config->lane_count, pipe_config->port_clock,
2346 pipe_config->pipe_bpp,
2347 pipe_config->dsc.compressed_bpp);
2349 drm_dbg_kms(&i915->drm,
2350 "DP link rate required %i available %i\n",
2351 intel_dp_link_required(adjusted_mode->crtc_clock,
2352 pipe_config->dsc.compressed_bpp),
2353 intel_dp_max_data_rate(pipe_config->port_clock,
2354 pipe_config->lane_count));
2356 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2357 pipe_config->lane_count, pipe_config->port_clock,
2358 pipe_config->pipe_bpp);
2360 drm_dbg_kms(&i915->drm,
2361 "DP link rate required %i available %i\n",
2362 intel_dp_link_required(adjusted_mode->crtc_clock,
2363 pipe_config->pipe_bpp),
2364 intel_dp_max_data_rate(pipe_config->port_clock,
2365 pipe_config->lane_count));
2371 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2372 struct intel_crtc_state *crtc_state,
2373 const struct drm_connector_state *conn_state)
2375 struct drm_connector *connector = conn_state->connector;
2376 const struct drm_display_info *info = &connector->display_info;
2377 const struct drm_display_mode *adjusted_mode =
2378 &crtc_state->hw.adjusted_mode;
2380 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2381 !intel_dp_get_colorimetry_status(intel_dp) ||
2382 !connector->ycbcr_420_allowed)
2385 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2387 return intel_pch_panel_fitting(crtc_state, conn_state);
2390 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2391 const struct drm_connector_state *conn_state)
2393 const struct intel_digital_connector_state *intel_conn_state =
2394 to_intel_digital_connector_state(conn_state);
2395 const struct drm_display_mode *adjusted_mode =
2396 &crtc_state->hw.adjusted_mode;
2399 * Our YCbCr output is always limited range.
2400 * crtc_state->limited_color_range only applies to RGB,
2401 * and it must never be set for YCbCr or we risk setting
2402 * some conflicting bits in PIPECONF which will mess up
2403 * the colors on the monitor.
2405 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2408 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2411 * CEA-861-E - 5.1 Default Encoding Parameters
2412 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2414 return crtc_state->pipe_bpp != 18 &&
2415 drm_default_rgb_quant_range(adjusted_mode) ==
2416 HDMI_QUANTIZATION_RANGE_LIMITED;
2418 return intel_conn_state->broadcast_rgb ==
2419 INTEL_BROADCAST_RGB_LIMITED;
2423 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2426 if (IS_G4X(dev_priv))
2428 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2434 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2435 const struct drm_connector_state *conn_state,
2436 struct drm_dp_vsc_sdp *vsc)
2438 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2442 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2443 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2444 * Colorimetry Format indication.
2446 vsc->revision = 0x5;
2449 /* DP 1.4a spec, Table 2-120 */
2450 switch (crtc_state->output_format) {
2451 case INTEL_OUTPUT_FORMAT_YCBCR444:
2452 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2454 case INTEL_OUTPUT_FORMAT_YCBCR420:
2455 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2457 case INTEL_OUTPUT_FORMAT_RGB:
2459 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2462 switch (conn_state->colorspace) {
2463 case DRM_MODE_COLORIMETRY_BT709_YCC:
2464 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2466 case DRM_MODE_COLORIMETRY_XVYCC_601:
2467 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2469 case DRM_MODE_COLORIMETRY_XVYCC_709:
2470 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2472 case DRM_MODE_COLORIMETRY_SYCC_601:
2473 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2475 case DRM_MODE_COLORIMETRY_OPYCC_601:
2476 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2478 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2479 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2481 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2482 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2484 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2485 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2487 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2488 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2489 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2493 * RGB->YCBCR color conversion uses the BT.709
2496 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2497 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2499 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2503 vsc->bpc = crtc_state->pipe_bpp / 3;
2505 /* only RGB pixelformat supports 6 bpc */
2506 drm_WARN_ON(&dev_priv->drm,
2507 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2509 /* all YCbCr are always limited range */
2510 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2511 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2514 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2515 struct intel_crtc_state *crtc_state,
2516 const struct drm_connector_state *conn_state)
2518 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2520 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2521 if (crtc_state->has_psr)
2524 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2527 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2528 vsc->sdp_type = DP_SDP_VSC;
2529 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2530 &crtc_state->infoframes.vsc);
2533 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2534 const struct intel_crtc_state *crtc_state,
2535 const struct drm_connector_state *conn_state,
2536 struct drm_dp_vsc_sdp *vsc)
2538 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2540 vsc->sdp_type = DP_SDP_VSC;
2542 if (dev_priv->psr.psr2_enabled) {
2543 if (dev_priv->psr.colorimetry_support &&
2544 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2545 /* [PSR2, +Colorimetry] */
2546 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2550 * [PSR2, -Colorimetry]
2551 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2552 * 3D stereo + PSR/PSR2 + Y-coordinate.
2554 vsc->revision = 0x4;
2560 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2561 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2564 vsc->revision = 0x2;
2570 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2571 struct intel_crtc_state *crtc_state,
2572 const struct drm_connector_state *conn_state)
2575 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2576 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2578 if (!conn_state->hdr_output_metadata)
2581 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2584 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2588 crtc_state->infoframes.enable |=
2589 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2593 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2594 struct intel_crtc_state *pipe_config,
2595 int output_bpp, bool constant_n)
2597 struct intel_connector *intel_connector = intel_dp->attached_connector;
2598 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2601 * DRRS and PSR can't be enable together, so giving preference to PSR
2602 * as it allows more power-savings by complete shutting down display,
2603 * so to guarantee this, intel_dp_drrs_compute_config() must be called
2604 * after intel_psr_compute_config().
2606 if (pipe_config->has_psr)
2609 if (!intel_connector->panel.downclock_mode ||
2610 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2613 pipe_config->has_drrs = true;
2614 intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2615 intel_connector->panel.downclock_mode->clock,
2616 pipe_config->port_clock, &pipe_config->dp_m2_n2,
2617 constant_n, pipe_config->fec_enable);
2621 intel_dp_compute_config(struct intel_encoder *encoder,
2622 struct intel_crtc_state *pipe_config,
2623 struct drm_connector_state *conn_state)
2625 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2626 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2627 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2628 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2629 enum port port = encoder->port;
2630 struct intel_connector *intel_connector = intel_dp->attached_connector;
2631 struct intel_digital_connector_state *intel_conn_state =
2632 to_intel_digital_connector_state(conn_state);
2633 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2634 DP_DPCD_QUIRK_CONSTANT_N);
2635 int ret = 0, output_bpp;
2637 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2638 pipe_config->has_pch_encoder = true;
2640 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2643 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2645 ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
2650 if (!intel_dp_port_has_audio(dev_priv, port))
2651 pipe_config->has_audio = false;
2652 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2653 pipe_config->has_audio = intel_dp->has_audio;
2655 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2657 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2658 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2661 if (HAS_GMCH(dev_priv))
2662 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2664 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2669 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2672 if (HAS_GMCH(dev_priv) &&
2673 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2676 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2679 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2682 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2686 pipe_config->limited_color_range =
2687 intel_dp_limited_color_range(pipe_config, conn_state);
2689 if (pipe_config->dsc.compression_enable)
2690 output_bpp = pipe_config->dsc.compressed_bpp;
2692 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2694 intel_link_compute_m_n(output_bpp,
2695 pipe_config->lane_count,
2696 adjusted_mode->crtc_clock,
2697 pipe_config->port_clock,
2698 &pipe_config->dp_m_n,
2699 constant_n, pipe_config->fec_enable);
2701 if (!HAS_DDI(dev_priv))
2702 intel_dp_set_clock(encoder, pipe_config);
2704 intel_psr_compute_config(intel_dp, pipe_config);
2705 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2707 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2708 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2713 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2714 int link_rate, u8 lane_count,
2717 intel_dp->link_trained = false;
2718 intel_dp->link_rate = link_rate;
2719 intel_dp->lane_count = lane_count;
2720 intel_dp->link_mst = link_mst;
2723 static void intel_dp_prepare(struct intel_encoder *encoder,
2724 const struct intel_crtc_state *pipe_config)
2726 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2727 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2728 enum port port = encoder->port;
2729 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2730 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2732 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2733 pipe_config->lane_count,
2734 intel_crtc_has_type(pipe_config,
2735 INTEL_OUTPUT_DP_MST));
2738 * There are four kinds of DP registers:
2745 * IBX PCH and CPU are the same for almost everything,
2746 * except that the CPU DP PLL is configured in this
2749 * CPT PCH is quite different, having many bits moved
2750 * to the TRANS_DP_CTL register instead. That
2751 * configuration happens (oddly) in ilk_pch_enable
2754 /* Preserve the BIOS-computed detected bit. This is
2755 * supposed to be read-only.
2757 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2759 /* Handle DP bits in common between all three register formats */
2760 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2761 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2763 /* Split out the IBX/CPU vs CPT settings */
2765 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2766 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2767 intel_dp->DP |= DP_SYNC_HS_HIGH;
2768 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2769 intel_dp->DP |= DP_SYNC_VS_HIGH;
2770 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2772 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2773 intel_dp->DP |= DP_ENHANCED_FRAMING;
2775 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2776 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2779 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2781 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2782 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2783 trans_dp |= TRANS_DP_ENH_FRAMING;
2785 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2786 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2788 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2789 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2791 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2792 intel_dp->DP |= DP_SYNC_HS_HIGH;
2793 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2794 intel_dp->DP |= DP_SYNC_VS_HIGH;
2795 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2797 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2798 intel_dp->DP |= DP_ENHANCED_FRAMING;
2800 if (IS_CHERRYVIEW(dev_priv))
2801 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2803 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2807 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2808 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2810 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2811 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2813 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2814 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2816 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2818 static void wait_panel_status(struct intel_dp *intel_dp,
2822 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2823 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2825 lockdep_assert_held(&dev_priv->pps_mutex);
2827 intel_pps_verify_state(intel_dp);
2829 pp_stat_reg = _pp_stat_reg(intel_dp);
2830 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2832 drm_dbg_kms(&dev_priv->drm,
2833 "mask %08x value %08x status %08x control %08x\n",
2835 intel_de_read(dev_priv, pp_stat_reg),
2836 intel_de_read(dev_priv, pp_ctrl_reg));
2838 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2840 drm_err(&dev_priv->drm,
2841 "Panel status timeout: status %08x control %08x\n",
2842 intel_de_read(dev_priv, pp_stat_reg),
2843 intel_de_read(dev_priv, pp_ctrl_reg));
2845 drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2848 static void wait_panel_on(struct intel_dp *intel_dp)
2850 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2852 drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2853 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2856 static void wait_panel_off(struct intel_dp *intel_dp)
2858 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2860 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2861 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2864 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2866 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2867 ktime_t panel_power_on_time;
2868 s64 panel_power_off_duration;
2870 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2872 /* take the difference of currrent time and panel power off time
2873 * and then make panel wait for t11_t12 if needed. */
2874 panel_power_on_time = ktime_get_boottime();
2875 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2877 /* When we disable the VDD override bit last we have to do the manual
2879 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2880 wait_remaining_ms_from_jiffies(jiffies,
2881 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2883 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2886 static void wait_backlight_on(struct intel_dp *intel_dp)
2888 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2889 intel_dp->backlight_on_delay);
2892 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2894 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2895 intel_dp->backlight_off_delay);
2898 /* Read the current pp_control value, unlocking the register if it
2902 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2904 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2907 lockdep_assert_held(&dev_priv->pps_mutex);
2909 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2910 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2911 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2912 control &= ~PANEL_UNLOCK_MASK;
2913 control |= PANEL_UNLOCK_REGS;
2919 * Must be paired with edp_panel_vdd_off().
2920 * Must hold pps_mutex around the whole on/off sequence.
2921 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2923 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2925 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2926 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2928 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2929 bool need_to_disable = !intel_dp->want_panel_vdd;
2931 lockdep_assert_held(&dev_priv->pps_mutex);
2933 if (!intel_dp_is_edp(intel_dp))
2936 cancel_delayed_work(&intel_dp->panel_vdd_work);
2937 intel_dp->want_panel_vdd = true;
2939 if (edp_have_panel_vdd(intel_dp))
2940 return need_to_disable;
2942 intel_display_power_get(dev_priv,
2943 intel_aux_power_domain(dig_port));
2945 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2946 dig_port->base.base.base.id,
2947 dig_port->base.base.name);
2949 if (!edp_have_panel_power(intel_dp))
2950 wait_panel_power_cycle(intel_dp);
2952 pp = ilk_get_pp_control(intel_dp);
2953 pp |= EDP_FORCE_VDD;
2955 pp_stat_reg = _pp_stat_reg(intel_dp);
2956 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2958 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2959 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2960 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2961 intel_de_read(dev_priv, pp_stat_reg),
2962 intel_de_read(dev_priv, pp_ctrl_reg));
2964 * If the panel wasn't on, delay before accessing aux channel
2966 if (!edp_have_panel_power(intel_dp)) {
2967 drm_dbg_kms(&dev_priv->drm,
2968 "[ENCODER:%d:%s] panel power wasn't enabled\n",
2969 dig_port->base.base.base.id,
2970 dig_port->base.base.name);
2971 msleep(intel_dp->panel_power_up_delay);
2974 return need_to_disable;
2978 * Must be paired with intel_edp_panel_vdd_off() or
2979 * intel_edp_panel_off().
2980 * Nested calls to these functions are not allowed since
2981 * we drop the lock. Caller must use some higher level
2982 * locking to prevent nested calls from other threads.
2984 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2986 intel_wakeref_t wakeref;
2989 if (!intel_dp_is_edp(intel_dp))
2993 with_pps_lock(intel_dp, wakeref)
2994 vdd = edp_panel_vdd_on(intel_dp);
2995 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2996 dp_to_dig_port(intel_dp)->base.base.base.id,
2997 dp_to_dig_port(intel_dp)->base.base.name);
3000 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3002 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3003 struct intel_digital_port *dig_port =
3004 dp_to_dig_port(intel_dp);
3006 i915_reg_t pp_stat_reg, pp_ctrl_reg;
3008 lockdep_assert_held(&dev_priv->pps_mutex);
3010 drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3012 if (!edp_have_panel_vdd(intel_dp))
3015 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3016 dig_port->base.base.base.id,
3017 dig_port->base.base.name);
3019 pp = ilk_get_pp_control(intel_dp);
3020 pp &= ~EDP_FORCE_VDD;
3022 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3023 pp_stat_reg = _pp_stat_reg(intel_dp);
3025 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3026 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3028 /* Make sure sequencer is idle before allowing subsequent activity */
3029 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3030 intel_de_read(dev_priv, pp_stat_reg),
3031 intel_de_read(dev_priv, pp_ctrl_reg));
3033 if ((pp & PANEL_POWER_ON) == 0)
3034 intel_dp->panel_power_off_time = ktime_get_boottime();
3036 intel_display_power_put_unchecked(dev_priv,
3037 intel_aux_power_domain(dig_port));
3040 static void edp_panel_vdd_work(struct work_struct *__work)
3042 struct intel_dp *intel_dp =
3043 container_of(to_delayed_work(__work),
3044 struct intel_dp, panel_vdd_work);
3045 intel_wakeref_t wakeref;
3047 with_pps_lock(intel_dp, wakeref) {
3048 if (!intel_dp->want_panel_vdd)
3049 edp_panel_vdd_off_sync(intel_dp);
3053 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3055 unsigned long delay;
3058 * Queue the timer to fire a long time from now (relative to the power
3059 * down delay) to keep the panel power up across a sequence of
3062 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3063 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3067 * Must be paired with edp_panel_vdd_on().
3068 * Must hold pps_mutex around the whole on/off sequence.
3069 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3071 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3073 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3075 lockdep_assert_held(&dev_priv->pps_mutex);
3077 if (!intel_dp_is_edp(intel_dp))
3080 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3081 dp_to_dig_port(intel_dp)->base.base.base.id,
3082 dp_to_dig_port(intel_dp)->base.base.name);
3084 intel_dp->want_panel_vdd = false;
3087 edp_panel_vdd_off_sync(intel_dp);
3089 edp_panel_vdd_schedule_off(intel_dp);
3092 static void edp_panel_on(struct intel_dp *intel_dp)
3094 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3096 i915_reg_t pp_ctrl_reg;
3098 lockdep_assert_held(&dev_priv->pps_mutex);
3100 if (!intel_dp_is_edp(intel_dp))
3103 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3104 dp_to_dig_port(intel_dp)->base.base.base.id,
3105 dp_to_dig_port(intel_dp)->base.base.name);
3107 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3108 "[ENCODER:%d:%s] panel power already on\n",
3109 dp_to_dig_port(intel_dp)->base.base.base.id,
3110 dp_to_dig_port(intel_dp)->base.base.name))
3113 wait_panel_power_cycle(intel_dp);
3115 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3116 pp = ilk_get_pp_control(intel_dp);
3117 if (IS_GEN(dev_priv, 5)) {
3118 /* ILK workaround: disable reset around power sequence */
3119 pp &= ~PANEL_POWER_RESET;
3120 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3121 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3124 pp |= PANEL_POWER_ON;
3125 if (!IS_GEN(dev_priv, 5))
3126 pp |= PANEL_POWER_RESET;
3128 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3129 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3131 wait_panel_on(intel_dp);
3132 intel_dp->last_power_on = jiffies;
3134 if (IS_GEN(dev_priv, 5)) {
3135 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3136 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3137 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3141 void intel_edp_panel_on(struct intel_dp *intel_dp)
3143 intel_wakeref_t wakeref;
3145 if (!intel_dp_is_edp(intel_dp))
3148 with_pps_lock(intel_dp, wakeref)
3149 edp_panel_on(intel_dp);
3153 static void edp_panel_off(struct intel_dp *intel_dp)
3155 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3156 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3158 i915_reg_t pp_ctrl_reg;
3160 lockdep_assert_held(&dev_priv->pps_mutex);
3162 if (!intel_dp_is_edp(intel_dp))
3165 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3166 dig_port->base.base.base.id, dig_port->base.base.name);
3168 drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3169 "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3170 dig_port->base.base.base.id, dig_port->base.base.name);
3172 pp = ilk_get_pp_control(intel_dp);
3173 /* We need to switch off panel power _and_ force vdd, for otherwise some
3174 * panels get very unhappy and cease to work. */
3175 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3178 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3180 intel_dp->want_panel_vdd = false;
3182 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3183 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3185 wait_panel_off(intel_dp);
3186 intel_dp->panel_power_off_time = ktime_get_boottime();
3188 /* We got a reference when we enabled the VDD. */
3189 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3192 void intel_edp_panel_off(struct intel_dp *intel_dp)
3194 intel_wakeref_t wakeref;
3196 if (!intel_dp_is_edp(intel_dp))
3199 with_pps_lock(intel_dp, wakeref)
3200 edp_panel_off(intel_dp);
3203 /* Enable backlight in the panel power control. */
3204 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3206 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3207 intel_wakeref_t wakeref;
3210 * If we enable the backlight right away following a panel power
3211 * on, we may see slight flicker as the panel syncs with the eDP
3212 * link. So delay a bit to make sure the image is solid before
3213 * allowing it to appear.
3215 wait_backlight_on(intel_dp);
3217 with_pps_lock(intel_dp, wakeref) {
3218 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3221 pp = ilk_get_pp_control(intel_dp);
3222 pp |= EDP_BLC_ENABLE;
3224 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3225 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3229 /* Enable backlight PWM and backlight PP control. */
3230 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3231 const struct drm_connector_state *conn_state)
3233 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3234 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3236 if (!intel_dp_is_edp(intel_dp))
3239 drm_dbg_kms(&i915->drm, "\n");
3241 intel_panel_enable_backlight(crtc_state, conn_state);
3242 _intel_edp_backlight_on(intel_dp);
3245 /* Disable backlight in the panel power control. */
3246 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3248 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3249 intel_wakeref_t wakeref;
3251 if (!intel_dp_is_edp(intel_dp))
3254 with_pps_lock(intel_dp, wakeref) {
3255 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3258 pp = ilk_get_pp_control(intel_dp);
3259 pp &= ~EDP_BLC_ENABLE;
3261 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3262 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3265 intel_dp->last_backlight_off = jiffies;
3266 edp_wait_backlight_off(intel_dp);
3269 /* Disable backlight PP control and backlight PWM. */
3270 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3272 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3273 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3275 if (!intel_dp_is_edp(intel_dp))
3278 drm_dbg_kms(&i915->drm, "\n");
3280 _intel_edp_backlight_off(intel_dp);
3281 intel_panel_disable_backlight(old_conn_state);
3285 * Hook for controlling the panel power control backlight through the bl_power
3286 * sysfs attribute. Take care to handle multiple calls.
3288 static void intel_edp_backlight_power(struct intel_connector *connector,
3291 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3292 struct intel_dp *intel_dp = intel_attached_dp(connector);
3293 intel_wakeref_t wakeref;
3297 with_pps_lock(intel_dp, wakeref)
3298 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3299 if (is_enabled == enable)
3302 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3303 enable ? "enable" : "disable");
3306 _intel_edp_backlight_on(intel_dp);
3308 _intel_edp_backlight_off(intel_dp);
3311 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3313 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3314 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3315 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3317 I915_STATE_WARN(cur_state != state,
3318 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3319 dig_port->base.base.base.id, dig_port->base.base.name,
3320 onoff(state), onoff(cur_state));
3322 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3324 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3326 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3328 I915_STATE_WARN(cur_state != state,
3329 "eDP PLL state assertion failure (expected %s, current %s)\n",
3330 onoff(state), onoff(cur_state));
3332 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3333 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3335 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3336 const struct intel_crtc_state *pipe_config)
3338 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3341 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3342 assert_dp_port_disabled(intel_dp);
3343 assert_edp_pll_disabled(dev_priv);
3345 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3346 pipe_config->port_clock);
3348 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3350 if (pipe_config->port_clock == 162000)
3351 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3353 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3355 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3356 intel_de_posting_read(dev_priv, DP_A);
3360 * [DevILK] Work around required when enabling DP PLL
3361 * while a pipe is enabled going to FDI:
3362 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3363 * 2. Program DP PLL enable
3365 if (IS_GEN(dev_priv, 5))
3366 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3368 intel_dp->DP |= DP_PLL_ENABLE;
3370 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3371 intel_de_posting_read(dev_priv, DP_A);
3375 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3376 const struct intel_crtc_state *old_crtc_state)
3378 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3379 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3381 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3382 assert_dp_port_disabled(intel_dp);
3383 assert_edp_pll_enabled(dev_priv);
3385 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3387 intel_dp->DP &= ~DP_PLL_ENABLE;
3389 intel_de_write(dev_priv, DP_A, intel_dp->DP);
3390 intel_de_posting_read(dev_priv, DP_A);
3394 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3397 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3398 * be capable of signalling downstream hpd with a long pulse.
3399 * Whether or not that means D3 is safe to use is not clear,
3400 * but let's assume so until proven otherwise.
3402 * FIXME should really check all downstream ports...
3404 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3405 drm_dp_is_branch(intel_dp->dpcd) &&
3406 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3409 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3410 const struct intel_crtc_state *crtc_state,
3413 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3416 if (!crtc_state->dsc.compression_enable)
3419 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3420 enable ? DP_DECOMPRESSION_EN : 0);
3422 drm_dbg_kms(&i915->drm,
3423 "Failed to %s sink decompression state\n",
3424 enable ? "enable" : "disable");
3427 /* If the sink supports it, try to set the power state appropriately */
3428 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3430 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3433 /* Should have a valid DPCD by this point */
3434 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3437 if (mode != DRM_MODE_DPMS_ON) {
3438 if (downstream_hpd_needs_d0(intel_dp))
3441 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3444 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3447 * When turning on, we need to retry for 1ms to give the sink
3450 for (i = 0; i < 3; i++) {
3451 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3458 if (ret == 1 && lspcon->active)
3459 lspcon_wait_pcon_mode(lspcon);
3463 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3464 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3467 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3468 enum port port, enum pipe *pipe)
3472 for_each_pipe(dev_priv, p) {
3473 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3475 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3481 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3484 /* must initialize pipe to something for the asserts */
3490 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3491 i915_reg_t dp_reg, enum port port,
3497 val = intel_de_read(dev_priv, dp_reg);
3499 ret = val & DP_PORT_EN;
3501 /* asserts want to know the pipe even if the port is disabled */
3502 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3503 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3504 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3505 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3506 else if (IS_CHERRYVIEW(dev_priv))
3507 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3509 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3514 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3519 intel_wakeref_t wakeref;
3522 wakeref = intel_display_power_get_if_enabled(dev_priv,
3523 encoder->power_domain);
3527 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3528 encoder->port, pipe);
3530 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3535 static void intel_dp_get_config(struct intel_encoder *encoder,
3536 struct intel_crtc_state *pipe_config)
3538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3539 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3541 enum port port = encoder->port;
3542 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3544 if (encoder->type == INTEL_OUTPUT_EDP)
3545 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3547 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3549 tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3551 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3553 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3554 u32 trans_dp = intel_de_read(dev_priv,
3555 TRANS_DP_CTL(crtc->pipe));
3557 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3558 flags |= DRM_MODE_FLAG_PHSYNC;
3560 flags |= DRM_MODE_FLAG_NHSYNC;
3562 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3563 flags |= DRM_MODE_FLAG_PVSYNC;
3565 flags |= DRM_MODE_FLAG_NVSYNC;
3567 if (tmp & DP_SYNC_HS_HIGH)
3568 flags |= DRM_MODE_FLAG_PHSYNC;
3570 flags |= DRM_MODE_FLAG_NHSYNC;
3572 if (tmp & DP_SYNC_VS_HIGH)
3573 flags |= DRM_MODE_FLAG_PVSYNC;
3575 flags |= DRM_MODE_FLAG_NVSYNC;
3578 pipe_config->hw.adjusted_mode.flags |= flags;
3580 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3581 pipe_config->limited_color_range = true;
3583 pipe_config->lane_count =
3584 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3586 intel_dp_get_m_n(crtc, pipe_config);
3588 if (port == PORT_A) {
3589 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3590 pipe_config->port_clock = 162000;
3592 pipe_config->port_clock = 270000;
3595 pipe_config->hw.adjusted_mode.crtc_clock =
3596 intel_dotclock_calculate(pipe_config->port_clock,
3597 &pipe_config->dp_m_n);
3599 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3600 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3602 * This is a big fat ugly hack.
3604 * Some machines in UEFI boot mode provide us a VBT that has 18
3605 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3606 * unknown we fail to light up. Yet the same BIOS boots up with
3607 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3608 * max, not what it tells us to use.
3610 * Note: This will still be broken if the eDP panel is not lit
3611 * up by the BIOS, and thus we can't get the mode at module
3614 drm_dbg_kms(&dev_priv->drm,
3615 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3616 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3617 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3621 static void intel_disable_dp(struct intel_atomic_state *state,
3622 struct intel_encoder *encoder,
3623 const struct intel_crtc_state *old_crtc_state,
3624 const struct drm_connector_state *old_conn_state)
3626 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3628 intel_dp->link_trained = false;
3630 if (old_crtc_state->has_audio)
3631 intel_audio_codec_disable(encoder,
3632 old_crtc_state, old_conn_state);
3634 /* Make sure the panel is off before trying to change the mode. But also
3635 * ensure that we have vdd while we switch off the panel. */
3636 intel_edp_panel_vdd_on(intel_dp);
3637 intel_edp_backlight_off(old_conn_state);
3638 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3639 intel_edp_panel_off(intel_dp);
3642 static void g4x_disable_dp(struct intel_atomic_state *state,
3643 struct intel_encoder *encoder,
3644 const struct intel_crtc_state *old_crtc_state,
3645 const struct drm_connector_state *old_conn_state)
3647 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3650 static void vlv_disable_dp(struct intel_atomic_state *state,
3651 struct intel_encoder *encoder,
3652 const struct intel_crtc_state *old_crtc_state,
3653 const struct drm_connector_state *old_conn_state)
3655 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3658 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3659 struct intel_encoder *encoder,
3660 const struct intel_crtc_state *old_crtc_state,
3661 const struct drm_connector_state *old_conn_state)
3663 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3664 enum port port = encoder->port;
3667 * Bspec does not list a specific disable sequence for g4x DP.
3668 * Follow the ilk+ sequence (disable pipe before the port) for
3669 * g4x DP as it does not suffer from underruns like the normal
3670 * g4x modeset sequence (disable pipe after the port).
3672 intel_dp_link_down(encoder, old_crtc_state);
3674 /* Only ilk+ has port A */
3676 ilk_edp_pll_off(intel_dp, old_crtc_state);
3679 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3680 struct intel_encoder *encoder,
3681 const struct intel_crtc_state *old_crtc_state,
3682 const struct drm_connector_state *old_conn_state)
3684 intel_dp_link_down(encoder, old_crtc_state);
3687 static void chv_post_disable_dp(struct intel_atomic_state *state,
3688 struct intel_encoder *encoder,
3689 const struct intel_crtc_state *old_crtc_state,
3690 const struct drm_connector_state *old_conn_state)
3692 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3694 intel_dp_link_down(encoder, old_crtc_state);
3696 vlv_dpio_get(dev_priv);
3698 /* Assert data lane reset */
3699 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3701 vlv_dpio_put(dev_priv);
3705 cpt_set_link_train(struct intel_dp *intel_dp,
3708 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3709 u32 *DP = &intel_dp->DP;
3711 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3713 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3714 case DP_TRAINING_PATTERN_DISABLE:
3715 *DP |= DP_LINK_TRAIN_OFF_CPT;
3717 case DP_TRAINING_PATTERN_1:
3718 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3720 case DP_TRAINING_PATTERN_2:
3721 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3723 case DP_TRAINING_PATTERN_3:
3724 drm_dbg_kms(&dev_priv->drm,
3725 "TPS3 not supported, using TPS2 instead\n");
3726 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3730 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3731 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3735 g4x_set_link_train(struct intel_dp *intel_dp,
3738 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3739 u32 *DP = &intel_dp->DP;
3741 *DP &= ~DP_LINK_TRAIN_MASK;
3743 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3744 case DP_TRAINING_PATTERN_DISABLE:
3745 *DP |= DP_LINK_TRAIN_OFF;
3747 case DP_TRAINING_PATTERN_1:
3748 *DP |= DP_LINK_TRAIN_PAT_1;
3750 case DP_TRAINING_PATTERN_2:
3751 *DP |= DP_LINK_TRAIN_PAT_2;
3753 case DP_TRAINING_PATTERN_3:
3754 drm_dbg_kms(&dev_priv->drm,
3755 "TPS3 not supported, using TPS2 instead\n");
3756 *DP |= DP_LINK_TRAIN_PAT_2;
3760 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3761 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3764 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3765 const struct intel_crtc_state *old_crtc_state)
3767 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3769 /* enable with pattern 1 (as per spec) */
3771 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3774 * Magic for VLV/CHV. We _must_ first set up the register
3775 * without actually enabling the port, and then do another
3776 * write to enable the port. Otherwise link training will
3777 * fail when the power sequencer is freshly used for this port.
3779 intel_dp->DP |= DP_PORT_EN;
3780 if (old_crtc_state->has_audio)
3781 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3783 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3784 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3787 static void intel_enable_dp(struct intel_atomic_state *state,
3788 struct intel_encoder *encoder,
3789 const struct intel_crtc_state *pipe_config,
3790 const struct drm_connector_state *conn_state)
3792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3793 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3794 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3795 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3796 enum pipe pipe = crtc->pipe;
3797 intel_wakeref_t wakeref;
3799 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3802 with_pps_lock(intel_dp, wakeref) {
3803 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3804 vlv_init_panel_power_sequencer(encoder, pipe_config);
3806 intel_dp_enable_port(intel_dp, pipe_config);
3808 edp_panel_vdd_on(intel_dp);
3809 edp_panel_on(intel_dp);
3810 edp_panel_vdd_off(intel_dp, true);
3813 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3814 unsigned int lane_mask = 0x0;
3816 if (IS_CHERRYVIEW(dev_priv))
3817 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3819 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3823 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3824 intel_dp_start_link_train(intel_dp);
3825 intel_dp_stop_link_train(intel_dp);
3827 if (pipe_config->has_audio) {
3828 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3830 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3834 static void g4x_enable_dp(struct intel_atomic_state *state,
3835 struct intel_encoder *encoder,
3836 const struct intel_crtc_state *pipe_config,
3837 const struct drm_connector_state *conn_state)
3839 intel_enable_dp(state, encoder, pipe_config, conn_state);
3840 intel_edp_backlight_on(pipe_config, conn_state);
3843 static void vlv_enable_dp(struct intel_atomic_state *state,
3844 struct intel_encoder *encoder,
3845 const struct intel_crtc_state *pipe_config,
3846 const struct drm_connector_state *conn_state)
3848 intel_edp_backlight_on(pipe_config, conn_state);
3851 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3852 struct intel_encoder *encoder,
3853 const struct intel_crtc_state *pipe_config,
3854 const struct drm_connector_state *conn_state)
3856 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3857 enum port port = encoder->port;
3859 intel_dp_prepare(encoder, pipe_config);
3861 /* Only ilk+ has port A */
3863 ilk_edp_pll_on(intel_dp, pipe_config);
3866 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3868 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3869 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3870 enum pipe pipe = intel_dp->pps_pipe;
3871 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3873 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3875 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3878 edp_panel_vdd_off_sync(intel_dp);
3881 * VLV seems to get confused when multiple power sequencers
3882 * have the same port selected (even if only one has power/vdd
3883 * enabled). The failure manifests as vlv_wait_port_ready() failing
3884 * CHV on the other hand doesn't seem to mind having the same port
3885 * selected in multiple power sequencers, but let's clear the
3886 * port select always when logically disconnecting a power sequencer
3889 drm_dbg_kms(&dev_priv->drm,
3890 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3891 pipe_name(pipe), dig_port->base.base.base.id,
3892 dig_port->base.base.name);
3893 intel_de_write(dev_priv, pp_on_reg, 0);
3894 intel_de_posting_read(dev_priv, pp_on_reg);
3896 intel_dp->pps_pipe = INVALID_PIPE;
3899 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3902 struct intel_encoder *encoder;
3904 lockdep_assert_held(&dev_priv->pps_mutex);
3906 for_each_intel_dp(&dev_priv->drm, encoder) {
3907 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3909 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3910 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3911 pipe_name(pipe), encoder->base.base.id,
3912 encoder->base.name);
3914 if (intel_dp->pps_pipe != pipe)
3917 drm_dbg_kms(&dev_priv->drm,
3918 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3919 pipe_name(pipe), encoder->base.base.id,
3920 encoder->base.name);
3922 /* make sure vdd is off before we steal it */
3923 vlv_detach_power_sequencer(intel_dp);
3927 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3928 const struct intel_crtc_state *crtc_state)
3930 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3931 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3932 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3934 lockdep_assert_held(&dev_priv->pps_mutex);
3936 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3938 if (intel_dp->pps_pipe != INVALID_PIPE &&
3939 intel_dp->pps_pipe != crtc->pipe) {
3941 * If another power sequencer was being used on this
3942 * port previously make sure to turn off vdd there while
3943 * we still have control of it.
3945 vlv_detach_power_sequencer(intel_dp);
3949 * We may be stealing the power
3950 * sequencer from another port.
3952 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3954 intel_dp->active_pipe = crtc->pipe;
3956 if (!intel_dp_is_edp(intel_dp))
3959 /* now it's all ours */
3960 intel_dp->pps_pipe = crtc->pipe;
3962 drm_dbg_kms(&dev_priv->drm,
3963 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3964 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3965 encoder->base.name);
3967 /* init power sequencer on this pipe and port */
3968 intel_dp_init_panel_power_sequencer(intel_dp);
3969 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3972 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3973 struct intel_encoder *encoder,
3974 const struct intel_crtc_state *pipe_config,
3975 const struct drm_connector_state *conn_state)
3977 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3979 intel_enable_dp(state, encoder, pipe_config, conn_state);
3982 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3983 struct intel_encoder *encoder,
3984 const struct intel_crtc_state *pipe_config,
3985 const struct drm_connector_state *conn_state)
3987 intel_dp_prepare(encoder, pipe_config);
3989 vlv_phy_pre_pll_enable(encoder, pipe_config);
3992 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3993 struct intel_encoder *encoder,
3994 const struct intel_crtc_state *pipe_config,
3995 const struct drm_connector_state *conn_state)
3997 chv_phy_pre_encoder_enable(encoder, pipe_config);
3999 intel_enable_dp(state, encoder, pipe_config, conn_state);
4001 /* Second common lane will stay alive on its own now */
4002 chv_phy_release_cl2_override(encoder);
4005 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4006 struct intel_encoder *encoder,
4007 const struct intel_crtc_state *pipe_config,
4008 const struct drm_connector_state *conn_state)
4010 intel_dp_prepare(encoder, pipe_config);
4012 chv_phy_pre_pll_enable(encoder, pipe_config);
4015 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4016 struct intel_encoder *encoder,
4017 const struct intel_crtc_state *old_crtc_state,
4018 const struct drm_connector_state *old_conn_state)
4020 chv_phy_post_pll_disable(encoder, old_crtc_state);
4024 * Fetch AUX CH registers 0x202 - 0x207 which contain
4025 * link status information
4028 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
4030 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
4031 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
4034 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
4036 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4039 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
4041 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4044 static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
4046 return DP_TRAIN_PRE_EMPH_LEVEL_2;
4049 static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
4051 return DP_TRAIN_PRE_EMPH_LEVEL_3;
4054 static void vlv_set_signal_levels(struct intel_dp *intel_dp)
4056 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4057 unsigned long demph_reg_value, preemph_reg_value,
4058 uniqtranscale_reg_value;
4059 u8 train_set = intel_dp->train_set[0];
4061 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4062 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4063 preemph_reg_value = 0x0004000;
4064 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4066 demph_reg_value = 0x2B405555;
4067 uniqtranscale_reg_value = 0x552AB83A;
4069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4070 demph_reg_value = 0x2B404040;
4071 uniqtranscale_reg_value = 0x5548B83A;
4073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4074 demph_reg_value = 0x2B245555;
4075 uniqtranscale_reg_value = 0x5560B83A;
4077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4078 demph_reg_value = 0x2B405555;
4079 uniqtranscale_reg_value = 0x5598DA3A;
4085 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4086 preemph_reg_value = 0x0002000;
4087 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4089 demph_reg_value = 0x2B404040;
4090 uniqtranscale_reg_value = 0x5552B83A;
4092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4093 demph_reg_value = 0x2B404848;
4094 uniqtranscale_reg_value = 0x5580B83A;
4096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4097 demph_reg_value = 0x2B404040;
4098 uniqtranscale_reg_value = 0x55ADDA3A;
4104 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4105 preemph_reg_value = 0x0000000;
4106 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4108 demph_reg_value = 0x2B305555;
4109 uniqtranscale_reg_value = 0x5570B83A;
4111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4112 demph_reg_value = 0x2B2B4040;
4113 uniqtranscale_reg_value = 0x55ADDA3A;
4119 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4120 preemph_reg_value = 0x0006000;
4121 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4123 demph_reg_value = 0x1B405555;
4124 uniqtranscale_reg_value = 0x55ADDA3A;
4134 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4135 uniqtranscale_reg_value, 0);
4138 static void chv_set_signal_levels(struct intel_dp *intel_dp)
4140 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4141 u32 deemph_reg_value, margin_reg_value;
4142 bool uniq_trans_scale = false;
4143 u8 train_set = intel_dp->train_set[0];
4145 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4146 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4147 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4149 deemph_reg_value = 128;
4150 margin_reg_value = 52;
4152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4153 deemph_reg_value = 128;
4154 margin_reg_value = 77;
4156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4157 deemph_reg_value = 128;
4158 margin_reg_value = 102;
4160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4161 deemph_reg_value = 128;
4162 margin_reg_value = 154;
4163 uniq_trans_scale = true;
4169 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4170 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4172 deemph_reg_value = 85;
4173 margin_reg_value = 78;
4175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4176 deemph_reg_value = 85;
4177 margin_reg_value = 116;
4179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4180 deemph_reg_value = 85;
4181 margin_reg_value = 154;
4187 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4188 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4190 deemph_reg_value = 64;
4191 margin_reg_value = 104;
4193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4194 deemph_reg_value = 64;
4195 margin_reg_value = 154;
4201 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4202 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4204 deemph_reg_value = 43;
4205 margin_reg_value = 154;
4215 chv_set_phy_signal_level(encoder, deemph_reg_value,
4216 margin_reg_value, uniq_trans_scale);
4219 static u32 g4x_signal_levels(u8 train_set)
4221 u32 signal_levels = 0;
4223 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4226 signal_levels |= DP_VOLTAGE_0_4;
4228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4229 signal_levels |= DP_VOLTAGE_0_6;
4231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4232 signal_levels |= DP_VOLTAGE_0_8;
4234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4235 signal_levels |= DP_VOLTAGE_1_2;
4238 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4239 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4241 signal_levels |= DP_PRE_EMPHASIS_0;
4243 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4244 signal_levels |= DP_PRE_EMPHASIS_3_5;
4246 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4247 signal_levels |= DP_PRE_EMPHASIS_6;
4249 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4250 signal_levels |= DP_PRE_EMPHASIS_9_5;
4253 return signal_levels;
4257 g4x_set_signal_levels(struct intel_dp *intel_dp)
4259 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4260 u8 train_set = intel_dp->train_set[0];
4263 signal_levels = g4x_signal_levels(train_set);
4265 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4268 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4269 intel_dp->DP |= signal_levels;
4271 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4272 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4275 /* SNB CPU eDP voltage swing and pre-emphasis control */
4276 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4278 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4279 DP_TRAIN_PRE_EMPHASIS_MASK);
4281 switch (signal_levels) {
4282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4284 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4286 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4289 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4292 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4295 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4297 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4298 "0x%x\n", signal_levels);
4299 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4304 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4306 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4307 u8 train_set = intel_dp->train_set[0];
4310 signal_levels = snb_cpu_edp_signal_levels(train_set);
4312 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4315 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4316 intel_dp->DP |= signal_levels;
4318 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4319 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4322 /* IVB CPU eDP voltage swing and pre-emphasis control */
4323 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4325 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4326 DP_TRAIN_PRE_EMPHASIS_MASK);
4328 switch (signal_levels) {
4329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4330 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4332 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4335 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4338 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4340 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4343 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4345 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4348 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4349 "0x%x\n", signal_levels);
4350 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4355 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4357 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4358 u8 train_set = intel_dp->train_set[0];
4361 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4363 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4366 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4367 intel_dp->DP |= signal_levels;
4369 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4370 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4373 void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4375 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4376 u8 train_set = intel_dp->train_set[0];
4378 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4379 train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4380 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4381 drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4382 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4383 DP_TRAIN_PRE_EMPHASIS_SHIFT,
4384 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4387 intel_dp->set_signal_levels(intel_dp);
4391 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4394 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4395 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4397 if (dp_train_pat & train_pat_mask)
4398 drm_dbg_kms(&dev_priv->drm,
4399 "Using DP training pattern TPS%d\n",
4400 dp_train_pat & train_pat_mask);
4402 intel_dp->set_link_train(intel_dp, dp_train_pat);
4405 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4407 if (intel_dp->set_idle_link_train)
4408 intel_dp->set_idle_link_train(intel_dp);
4412 intel_dp_link_down(struct intel_encoder *encoder,
4413 const struct intel_crtc_state *old_crtc_state)
4415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4416 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4417 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4418 enum port port = encoder->port;
4419 u32 DP = intel_dp->DP;
4421 if (drm_WARN_ON(&dev_priv->drm,
4422 (intel_de_read(dev_priv, intel_dp->output_reg) &
4426 drm_dbg_kms(&dev_priv->drm, "\n");
4428 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4429 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4430 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4431 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4433 DP &= ~DP_LINK_TRAIN_MASK;
4434 DP |= DP_LINK_TRAIN_PAT_IDLE;
4436 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4437 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4439 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4440 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4441 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4444 * HW workaround for IBX, we need to move the port
4445 * to transcoder A after disabling it to allow the
4446 * matching HDMI port to be enabled on transcoder A.
4448 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4450 * We get CPU/PCH FIFO underruns on the other pipe when
4451 * doing the workaround. Sweep them under the rug.
4453 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4454 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4456 /* always enable with pattern 1 (as per spec) */
4457 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4458 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4459 DP_LINK_TRAIN_PAT_1;
4460 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4461 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4464 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4465 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4467 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4468 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4469 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4472 msleep(intel_dp->panel_power_down_delay);
4476 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4477 intel_wakeref_t wakeref;
4479 with_pps_lock(intel_dp, wakeref)
4480 intel_dp->active_pipe = INVALID_PIPE;
4484 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4488 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4491 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4494 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4496 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4499 * Clear the cached register set to avoid using stale values
4500 * for the sinks that do not support DSC.
4502 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4504 /* Clear fec_capable to avoid using stale values */
4505 intel_dp->fec_capable = 0;
4507 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4508 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4509 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4510 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4512 sizeof(intel_dp->dsc_dpcd)) < 0)
4514 "Failed to read DPCD register 0x%x\n",
4517 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4518 (int)sizeof(intel_dp->dsc_dpcd),
4519 intel_dp->dsc_dpcd);
4521 /* FEC is supported only on DP 1.4 */
4522 if (!intel_dp_is_edp(intel_dp) &&
4523 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4524 &intel_dp->fec_capable) < 0)
4526 "Failed to read FEC DPCD register\n");
4528 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4529 intel_dp->fec_capable);
4534 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4536 struct drm_i915_private *dev_priv =
4537 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4539 /* this function is meant to be called only once */
4540 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4542 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4545 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4546 drm_dp_is_branch(intel_dp->dpcd));
4549 * Read the eDP display control registers.
4551 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4552 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4553 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4554 * method). The display control registers should read zero if they're
4555 * not supported anyway.
4557 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4558 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4559 sizeof(intel_dp->edp_dpcd))
4560 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4561 (int)sizeof(intel_dp->edp_dpcd),
4562 intel_dp->edp_dpcd);
4565 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4566 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4568 intel_psr_init_dpcd(intel_dp);
4570 /* Read the eDP 1.4+ supported link rates. */
4571 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4572 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4575 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4576 sink_rates, sizeof(sink_rates));
4578 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4579 int val = le16_to_cpu(sink_rates[i]);
4584 /* Value read multiplied by 200kHz gives the per-lane
4585 * link rate in kHz. The source rates are, however,
4586 * stored in terms of LS_Clk kHz. The full conversion
4587 * back to symbols is
4588 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4590 intel_dp->sink_rates[i] = (val * 200) / 10;
4592 intel_dp->num_sink_rates = i;
4596 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4597 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4599 if (intel_dp->num_sink_rates)
4600 intel_dp->use_rate_select = true;
4602 intel_dp_set_sink_rates(intel_dp);
4604 intel_dp_set_common_rates(intel_dp);
4606 /* Read the eDP DSC DPCD registers */
4607 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4608 intel_dp_get_dsc_sink_cap(intel_dp);
4614 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4616 if (!intel_dp->attached_connector)
4619 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4625 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4629 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
4633 * Don't clobber cached eDP rates. Also skip re-reading
4634 * the OUI/ID since we know it won't change.
4636 if (!intel_dp_is_edp(intel_dp)) {
4637 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4638 drm_dp_is_branch(intel_dp->dpcd));
4640 intel_dp_set_sink_rates(intel_dp);
4641 intel_dp_set_common_rates(intel_dp);
4644 if (intel_dp_has_sink_count(intel_dp)) {
4645 ret = drm_dp_read_sink_count(&intel_dp->aux);
4650 * Sink count can change between short pulse hpd hence
4651 * a member variable in intel_dp will track any changes
4652 * between short pulse interrupts.
4654 intel_dp->sink_count = ret;
4657 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4658 * a dongle is present but no display. Unless we require to know
4659 * if a dongle is present or not, we don't need to update
4660 * downstream port information. So, an early return here saves
4661 * time from performing other operations which are not required.
4663 if (!intel_dp->sink_count)
4667 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4668 intel_dp->downstream_ports) == 0;
4672 intel_dp_can_mst(struct intel_dp *intel_dp)
4674 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4676 return i915->params.enable_dp_mst &&
4677 intel_dp->can_mst &&
4678 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4682 intel_dp_configure_mst(struct intel_dp *intel_dp)
4684 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4685 struct intel_encoder *encoder =
4686 &dp_to_dig_port(intel_dp)->base;
4687 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4689 drm_dbg_kms(&i915->drm,
4690 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4691 encoder->base.base.id, encoder->base.name,
4692 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4693 yesno(i915->params.enable_dp_mst));
4695 if (!intel_dp->can_mst)
4698 intel_dp->is_mst = sink_can_mst &&
4699 i915->params.enable_dp_mst;
4701 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4706 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4708 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4709 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4714 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4715 const struct drm_connector_state *conn_state)
4718 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4719 * of Color Encoding Format and Content Color Gamut], in order to
4720 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4722 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4725 switch (conn_state->colorspace) {
4726 case DRM_MODE_COLORIMETRY_SYCC_601:
4727 case DRM_MODE_COLORIMETRY_OPYCC_601:
4728 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4729 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4730 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4739 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4740 struct dp_sdp *sdp, size_t size)
4742 size_t length = sizeof(struct dp_sdp);
4747 memset(sdp, 0, size);
4750 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4751 * VSC SDP Header Bytes
4753 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4754 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4755 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4756 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4759 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
4762 if (vsc->revision != 0x5)
4765 /* VSC SDP Payload for DB16 through DB18 */
4766 /* Pixel Encoding and Colorimetry Formats */
4767 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4768 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4775 sdp->db[17] = 0x1; /* DB17[3:0] */
4787 MISSING_CASE(vsc->bpc);
4790 /* Dynamic Range and Component Bit Depth */
4791 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4792 sdp->db[17] |= 0x80; /* DB17[7] */
4795 sdp->db[18] = vsc->content_type & 0x7;
4802 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4806 size_t length = sizeof(struct dp_sdp);
4807 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4808 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4814 memset(sdp, 0, size);
4816 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4818 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4822 if (len != infoframe_size) {
4823 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4828 * Set up the infoframe sdp packet for HDR static metadata.
4829 * Prepare VSC Header for SU as per DP 1.4a spec,
4830 * Table 2-100 and Table 2-101
4833 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4834 sdp->sdp_header.HB0 = 0;
4836 * Packet Type 80h + Non-audio INFOFRAME Type value
4837 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4838 * - 80h + Non-audio INFOFRAME Type value
4839 * - InfoFrame Type: 0x07
4840 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4842 sdp->sdp_header.HB1 = drm_infoframe->type;
4844 * Least Significant Eight Bits of (Data Byte Count – 1)
4845 * infoframe_size - 1
4847 sdp->sdp_header.HB2 = 0x1D;
4848 /* INFOFRAME SDP Version Number */
4849 sdp->sdp_header.HB3 = (0x13 << 2);
4850 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4851 sdp->db[0] = drm_infoframe->version;
4852 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4853 sdp->db[1] = drm_infoframe->length;
4855 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4856 * HDMI_INFOFRAME_HEADER_SIZE
4858 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4859 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4860 HDMI_DRM_INFOFRAME_SIZE);
4863 * Size of DP infoframe sdp packet for HDR static metadata consists of
4864 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4865 * - Two Data Blocks: 2 bytes
4866 * CTA Header Byte2 (INFOFRAME Version Number)
4867 * CTA Header Byte3 (Length of INFOFRAME)
4868 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4870 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4871 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4872 * will pad rest of the size.
4874 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4877 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4878 const struct intel_crtc_state *crtc_state,
4881 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4883 struct dp_sdp sdp = {};
4886 if ((crtc_state->infoframes.enable &
4887 intel_hdmi_infoframe_enable(type)) == 0)
4892 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4895 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4896 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4904 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4907 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4910 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4911 const struct intel_crtc_state *crtc_state,
4912 struct drm_dp_vsc_sdp *vsc)
4914 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4916 struct dp_sdp sdp = {};
4919 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4921 if (drm_WARN_ON(&dev_priv->drm, len < 0))
4924 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
4928 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4930 const struct intel_crtc_state *crtc_state,
4931 const struct drm_connector_state *conn_state)
4933 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4935 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4936 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4937 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4938 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4939 u32 val = intel_de_read(dev_priv, reg);
4941 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
4942 /* When PSR is enabled, this routine doesn't disable VSC DIP */
4943 if (intel_psr_enabled(intel_dp))
4946 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
4949 intel_de_write(dev_priv, reg, val);
4950 intel_de_posting_read(dev_priv, reg);
4954 intel_de_write(dev_priv, reg, val);
4955 intel_de_posting_read(dev_priv, reg);
4957 /* When PSR is enabled, VSC SDP is handled by PSR routine */
4958 if (!intel_psr_enabled(intel_dp))
4959 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4961 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4964 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4965 const void *buffer, size_t size)
4967 const struct dp_sdp *sdp = buffer;
4969 if (size < sizeof(struct dp_sdp))
4972 memset(vsc, 0, size);
4974 if (sdp->sdp_header.HB0 != 0)
4977 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4980 vsc->sdp_type = sdp->sdp_header.HB1;
4981 vsc->revision = sdp->sdp_header.HB2;
4982 vsc->length = sdp->sdp_header.HB3;
4984 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4985 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4987 * - HB2 = 0x2, HB3 = 0x8
4988 * VSC SDP supporting 3D stereo + PSR
4989 * - HB2 = 0x4, HB3 = 0xe
4990 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4991 * first scan line of the SU region (applies to eDP v1.4b
4995 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4997 * - HB2 = 0x5, HB3 = 0x13
4998 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5001 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5002 vsc->colorimetry = sdp->db[16] & 0xf;
5003 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5005 switch (sdp->db[17] & 0x7) {
5022 MISSING_CASE(sdp->db[17] & 0x7);
5026 vsc->content_type = sdp->db[18] & 0x7;
5035 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5036 const void *buffer, size_t size)
5040 const struct dp_sdp *sdp = buffer;
5042 if (size < sizeof(struct dp_sdp))
5045 if (sdp->sdp_header.HB0 != 0)
5048 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5052 * Least Significant Eight Bits of (Data Byte Count – 1)
5053 * 1Dh (i.e., Data Byte Count = 30 bytes).
5055 if (sdp->sdp_header.HB2 != 0x1D)
5058 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5059 if ((sdp->sdp_header.HB3 & 0x3) != 0)
5062 /* INFOFRAME SDP Version Number */
5063 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5066 /* CTA Header Byte 2 (INFOFRAME Version Number) */
5067 if (sdp->db[0] != 1)
5070 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5071 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5074 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5075 HDMI_DRM_INFOFRAME_SIZE);
5080 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5081 struct intel_crtc_state *crtc_state,
5082 struct drm_dp_vsc_sdp *vsc)
5084 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5087 unsigned int type = DP_SDP_VSC;
5088 struct dp_sdp sdp = {};
5091 /* When PSR is enabled, VSC SDP is handled by PSR routine */
5092 if (intel_psr_enabled(intel_dp))
5095 if ((crtc_state->infoframes.enable &
5096 intel_hdmi_infoframe_enable(type)) == 0)
5099 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5101 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5104 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5107 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5108 struct intel_crtc_state *crtc_state,
5109 struct hdmi_drm_infoframe *drm_infoframe)
5111 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5113 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5114 struct dp_sdp sdp = {};
5117 if ((crtc_state->infoframes.enable &
5118 intel_hdmi_infoframe_enable(type)) == 0)
5121 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5124 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5128 drm_dbg_kms(&dev_priv->drm,
5129 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5132 void intel_read_dp_sdp(struct intel_encoder *encoder,
5133 struct intel_crtc_state *crtc_state,
5136 if (encoder->type != INTEL_OUTPUT_DDI)
5141 intel_read_dp_vsc_sdp(encoder, crtc_state,
5142 &crtc_state->infoframes.vsc);
5144 case HDMI_PACKET_TYPE_GAMUT_METADATA:
5145 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5146 &crtc_state->infoframes.drm.drm);
5154 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5156 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5159 u8 test_lane_count, test_link_bw;
5163 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5164 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5168 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5171 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5173 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5176 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5179 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5181 /* Validate the requested link rate and lane count */
5182 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5186 intel_dp->compliance.test_lane_count = test_lane_count;
5187 intel_dp->compliance.test_link_rate = test_link_rate;
5192 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5194 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5197 __be16 h_width, v_height;
5200 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5201 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5204 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5207 if (test_pattern != DP_COLOR_RAMP)
5210 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5213 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5217 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5220 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5224 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5227 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5230 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5232 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5234 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5235 case DP_TEST_BIT_DEPTH_6:
5236 intel_dp->compliance.test_data.bpc = 6;
5238 case DP_TEST_BIT_DEPTH_8:
5239 intel_dp->compliance.test_data.bpc = 8;
5245 intel_dp->compliance.test_data.video_pattern = test_pattern;
5246 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5247 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5248 /* Set test active flag here so userspace doesn't interrupt things */
5249 intel_dp->compliance.test_active = true;
5254 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5256 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5257 u8 test_result = DP_TEST_ACK;
5258 struct intel_connector *intel_connector = intel_dp->attached_connector;
5259 struct drm_connector *connector = &intel_connector->base;
5261 if (intel_connector->detect_edid == NULL ||
5262 connector->edid_corrupt ||
5263 intel_dp->aux.i2c_defer_count > 6) {
5264 /* Check EDID read for NACKs, DEFERs and corruption
5265 * (DP CTS 1.2 Core r1.1)
5266 * 4.2.2.4 : Failed EDID read, I2C_NAK
5267 * 4.2.2.5 : Failed EDID read, I2C_DEFER
5268 * 4.2.2.6 : EDID corruption detected
5269 * Use failsafe mode for all cases
5271 if (intel_dp->aux.i2c_nack_count > 0 ||
5272 intel_dp->aux.i2c_defer_count > 0)
5273 drm_dbg_kms(&i915->drm,
5274 "EDID read had %d NACKs, %d DEFERs\n",
5275 intel_dp->aux.i2c_nack_count,
5276 intel_dp->aux.i2c_defer_count);
5277 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5279 struct edid *block = intel_connector->detect_edid;
5281 /* We have to write the checksum
5282 * of the last block read
5284 block += intel_connector->detect_edid->extensions;
5286 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5287 block->checksum) <= 0)
5288 drm_dbg_kms(&i915->drm,
5289 "Failed to write EDID checksum\n");
5291 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5292 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5295 /* Set test active flag here so userspace doesn't interrupt things */
5296 intel_dp->compliance.test_active = true;
5301 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5303 struct drm_dp_phy_test_params *data =
5304 &intel_dp->compliance.test_data.phytest;
5306 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5307 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5312 * link_mst is set to false to avoid executing mst related code
5313 * during compliance testing.
5315 intel_dp->link_mst = false;
5320 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5322 struct drm_i915_private *dev_priv =
5323 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5324 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5325 struct drm_dp_phy_test_params *data =
5326 &intel_dp->compliance.test_data.phytest;
5327 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5328 enum pipe pipe = crtc->pipe;
5331 switch (data->phy_pattern) {
5332 case DP_PHY_TEST_PATTERN_NONE:
5333 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5334 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5336 case DP_PHY_TEST_PATTERN_D10_2:
5337 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5338 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5339 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5341 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5342 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5343 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5344 DDI_DP_COMP_CTL_ENABLE |
5345 DDI_DP_COMP_CTL_SCRAMBLED_0);
5347 case DP_PHY_TEST_PATTERN_PRBS7:
5348 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5349 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5350 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5352 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5354 * FIXME: Ideally pattern should come from DPCD 0x250. As
5355 * current firmware of DPR-100 could not set it, so hardcoding
5356 * now for complaince test.
5358 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5359 pattern_val = 0x3e0f83e0;
5360 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5361 pattern_val = 0x0f83e0f8;
5362 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5363 pattern_val = 0x0000f83e;
5364 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5365 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5366 DDI_DP_COMP_CTL_ENABLE |
5367 DDI_DP_COMP_CTL_CUSTOM80);
5369 case DP_PHY_TEST_PATTERN_CP2520:
5371 * FIXME: Ideally pattern should come from DPCD 0x24A. As
5372 * current firmware of DPR-100 could not set it, so hardcoding
5373 * now for complaince test.
5375 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5377 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5378 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5382 WARN(1, "Invalid Phy Test Pattern\n");
5387 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5389 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5390 struct drm_device *dev = dig_port->base.base.dev;
5391 struct drm_i915_private *dev_priv = to_i915(dev);
5392 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5393 enum pipe pipe = crtc->pipe;
5394 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5396 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5397 TRANS_DDI_FUNC_CTL(pipe));
5398 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5399 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5401 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5402 TGL_TRANS_DDI_PORT_MASK);
5403 trans_conf_value &= ~PIPECONF_ENABLE;
5404 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5406 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5407 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5408 trans_ddi_func_ctl_value);
5409 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5413 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5415 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5416 struct drm_device *dev = dig_port->base.base.dev;
5417 struct drm_i915_private *dev_priv = to_i915(dev);
5418 enum port port = dig_port->base.port;
5419 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5420 enum pipe pipe = crtc->pipe;
5421 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5423 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5424 TRANS_DDI_FUNC_CTL(pipe));
5425 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5426 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5428 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5429 TGL_TRANS_DDI_SELECT_PORT(port);
5430 trans_conf_value |= PIPECONF_ENABLE;
5431 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5433 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5434 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5435 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5436 trans_ddi_func_ctl_value);
5439 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5441 struct drm_dp_phy_test_params *data =
5442 &intel_dp->compliance.test_data.phytest;
5443 u8 link_status[DP_LINK_STATUS_SIZE];
5445 if (!intel_dp_get_link_status(intel_dp, link_status)) {
5446 DRM_DEBUG_KMS("failed to get link status\n");
5450 /* retrieve vswing & pre-emphasis setting */
5451 intel_dp_get_adjust_train(intel_dp, link_status);
5453 intel_dp_autotest_phy_ddi_disable(intel_dp);
5455 intel_dp_set_signal_levels(intel_dp);
5457 intel_dp_phy_pattern_update(intel_dp);
5459 intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5461 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5462 link_status[DP_DPCD_REV]);
5465 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5469 test_result = intel_dp_prepare_phytest(intel_dp);
5470 if (test_result != DP_TEST_ACK)
5471 DRM_ERROR("Phy test preparation failed\n");
5473 intel_dp_process_phy_request(intel_dp);
5478 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5480 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5481 u8 response = DP_TEST_NAK;
5485 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5487 drm_dbg_kms(&i915->drm,
5488 "Could not read test request from sink\n");
5493 case DP_TEST_LINK_TRAINING:
5494 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5495 response = intel_dp_autotest_link_training(intel_dp);
5497 case DP_TEST_LINK_VIDEO_PATTERN:
5498 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5499 response = intel_dp_autotest_video_pattern(intel_dp);
5501 case DP_TEST_LINK_EDID_READ:
5502 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5503 response = intel_dp_autotest_edid(intel_dp);
5505 case DP_TEST_LINK_PHY_TEST_PATTERN:
5506 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5507 response = intel_dp_autotest_phy_pattern(intel_dp);
5510 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5515 if (response & DP_TEST_ACK)
5516 intel_dp->compliance.test_type = request;
5519 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5521 drm_dbg_kms(&i915->drm,
5522 "Could not write test response to sink\n");
5526 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5527 * @intel_dp: Intel DP struct
5529 * Read any pending MST interrupts, call MST core to handle these and ack the
5530 * interrupts. Check if the main and AUX link state is ok.
5533 * - %true if pending interrupts were serviced (or no interrupts were
5534 * pending) w/o detecting an error condition.
5535 * - %false if an error condition - like AUX failure or a loss of link - is
5536 * detected, which needs servicing from the hotplug work.
5539 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5541 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5542 bool link_ok = true;
5544 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5547 u8 esi[DP_DPRX_ESI_LEN] = {};
5551 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5552 drm_dbg_kms(&i915->drm,
5553 "failed to get ESI - device may have failed\n");
5559 /* check link status - esi[10] = 0x200c */
5560 if (intel_dp->active_mst_links > 0 && link_ok &&
5561 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5562 drm_dbg_kms(&i915->drm,
5563 "channel EQ not ok, retraining\n");
5567 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5569 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5573 for (retry = 0; retry < 3; retry++) {
5576 wret = drm_dp_dpcd_write(&intel_dp->aux,
5577 DP_SINK_COUNT_ESI+1,
5588 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5590 u8 link_status[DP_LINK_STATUS_SIZE];
5592 if (!intel_dp->link_trained)
5596 * While PSR source HW is enabled, it will control main-link sending
5597 * frames, enabling and disabling it so trying to do a retrain will fail
5598 * as the link would or not be on or it could mix training patterns
5599 * and frame data at the same time causing retrain to fail.
5600 * Also when exiting PSR, HW will retrain the link anyways fixing
5601 * any link status error.
5603 if (intel_psr_enabled(intel_dp))
5606 if (!intel_dp_get_link_status(intel_dp, link_status))
5610 * Validate the cached values of intel_dp->link_rate and
5611 * intel_dp->lane_count before attempting to retrain.
5613 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5614 intel_dp->lane_count))
5617 /* Retrain if Channel EQ or CR not ok */
5618 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5621 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5622 const struct drm_connector_state *conn_state)
5624 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5625 struct intel_encoder *encoder;
5628 if (!conn_state->best_encoder)
5632 encoder = &dp_to_dig_port(intel_dp)->base;
5633 if (conn_state->best_encoder == &encoder->base)
5637 for_each_pipe(i915, pipe) {
5638 encoder = &intel_dp->mst_encoders[pipe]->base;
5639 if (conn_state->best_encoder == &encoder->base)
5646 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5647 struct drm_modeset_acquire_ctx *ctx,
5650 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5651 struct drm_connector_list_iter conn_iter;
5652 struct intel_connector *connector;
5657 if (!intel_dp_needs_link_retrain(intel_dp))
5660 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5661 for_each_intel_connector_iter(connector, &conn_iter) {
5662 struct drm_connector_state *conn_state =
5663 connector->base.state;
5664 struct intel_crtc_state *crtc_state;
5665 struct intel_crtc *crtc;
5667 if (!intel_dp_has_connector(intel_dp, conn_state))
5670 crtc = to_intel_crtc(conn_state->crtc);
5674 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5678 crtc_state = to_intel_crtc_state(crtc->base.state);
5680 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5682 if (!crtc_state->hw.active)
5685 if (conn_state->commit &&
5686 !try_wait_for_completion(&conn_state->commit->hw_done))
5689 *crtc_mask |= drm_crtc_mask(&crtc->base);
5691 drm_connector_list_iter_end(&conn_iter);
5693 if (!intel_dp_needs_link_retrain(intel_dp))
5699 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5701 struct intel_connector *connector = intel_dp->attached_connector;
5703 return connector->base.status == connector_status_connected ||
5707 int intel_dp_retrain_link(struct intel_encoder *encoder,
5708 struct drm_modeset_acquire_ctx *ctx)
5710 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5711 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5712 struct intel_crtc *crtc;
5716 if (!intel_dp_is_connected(intel_dp))
5719 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5724 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5731 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5732 encoder->base.base.id, encoder->base.name);
5734 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5735 const struct intel_crtc_state *crtc_state =
5736 to_intel_crtc_state(crtc->base.state);
5738 /* Suppress underruns caused by re-training */
5739 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5740 if (crtc_state->has_pch_encoder)
5741 intel_set_pch_fifo_underrun_reporting(dev_priv,
5742 intel_crtc_pch_transcoder(crtc), false);
5745 intel_dp_start_link_train(intel_dp);
5746 intel_dp_stop_link_train(intel_dp);
5748 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5749 const struct intel_crtc_state *crtc_state =
5750 to_intel_crtc_state(crtc->base.state);
5752 /* Keep underrun reporting disabled until things are stable */
5753 intel_wait_for_vblank(dev_priv, crtc->pipe);
5755 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5756 if (crtc_state->has_pch_encoder)
5757 intel_set_pch_fifo_underrun_reporting(dev_priv,
5758 intel_crtc_pch_transcoder(crtc), true);
5765 * If display is now connected check links status,
5766 * there has been known issues of link loss triggering
5769 * Some sinks (eg. ASUS PB287Q) seem to perform some
5770 * weird HPD ping pong during modesets. So we can apparently
5771 * end up with HPD going low during a modeset, and then
5772 * going back up soon after. And once that happens we must
5773 * retrain the link to get a picture. That's in case no
5774 * userspace component reacted to intermittent HPD dip.
5776 static enum intel_hotplug_state
5777 intel_dp_hotplug(struct intel_encoder *encoder,
5778 struct intel_connector *connector)
5780 struct drm_modeset_acquire_ctx ctx;
5781 enum intel_hotplug_state state;
5784 state = intel_encoder_hotplug(encoder, connector);
5786 drm_modeset_acquire_init(&ctx, 0);
5789 ret = intel_dp_retrain_link(encoder, &ctx);
5791 if (ret == -EDEADLK) {
5792 drm_modeset_backoff(&ctx);
5799 drm_modeset_drop_locks(&ctx);
5800 drm_modeset_acquire_fini(&ctx);
5801 drm_WARN(encoder->base.dev, ret,
5802 "Acquiring modeset locks failed with %i\n", ret);
5805 * Keeping it consistent with intel_ddi_hotplug() and
5806 * intel_hdmi_hotplug().
5808 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5809 state = INTEL_HOTPLUG_RETRY;
5814 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5816 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5819 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5822 if (drm_dp_dpcd_readb(&intel_dp->aux,
5823 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5826 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5828 if (val & DP_AUTOMATED_TEST_REQUEST)
5829 intel_dp_handle_test_request(intel_dp);
5831 if (val & DP_CP_IRQ)
5832 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5834 if (val & DP_SINK_SPECIFIC_IRQ)
5835 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5839 * According to DP spec
5842 * 2. Configure link according to Receiver Capabilities
5843 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5844 * 4. Check link status on receipt of hot-plug interrupt
5846 * intel_dp_short_pulse - handles short pulse interrupts
5847 * when full detection is not required.
5848 * Returns %true if short pulse is handled and full detection
5849 * is NOT required and %false otherwise.
5852 intel_dp_short_pulse(struct intel_dp *intel_dp)
5854 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5855 u8 old_sink_count = intel_dp->sink_count;
5859 * Clearing compliance test variables to allow capturing
5860 * of values for next automated test request.
5862 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5865 * Now read the DPCD to see if it's actually running
5866 * If the current value of sink count doesn't match with
5867 * the value that was stored earlier or dpcd read failed
5868 * we need to do full detection
5870 ret = intel_dp_get_dpcd(intel_dp);
5872 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5873 /* No need to proceed if we are going to do full detect */
5877 intel_dp_check_service_irq(intel_dp);
5879 /* Handle CEC interrupts, if any */
5880 drm_dp_cec_irq(&intel_dp->aux);
5882 /* defer to the hotplug work for link retraining if needed */
5883 if (intel_dp_needs_link_retrain(intel_dp))
5886 intel_psr_short_pulse(intel_dp);
5888 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5889 drm_dbg_kms(&dev_priv->drm,
5890 "Link Training Compliance Test requested\n");
5891 /* Send a Hotplug Uevent to userspace to start modeset */
5892 drm_kms_helper_hotplug_event(&dev_priv->drm);
5898 /* XXX this is probably wrong for multiple downstream ports */
5899 static enum drm_connector_status
5900 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5902 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5903 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5904 u8 *dpcd = intel_dp->dpcd;
5907 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5908 return connector_status_connected;
5911 lspcon_resume(lspcon);
5913 if (!intel_dp_get_dpcd(intel_dp))
5914 return connector_status_disconnected;
5916 /* if there's no downstream port, we're done */
5917 if (!drm_dp_is_branch(dpcd))
5918 return connector_status_connected;
5920 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5921 if (intel_dp_has_sink_count(intel_dp) &&
5922 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5923 return intel_dp->sink_count ?
5924 connector_status_connected : connector_status_disconnected;
5927 if (intel_dp_can_mst(intel_dp))
5928 return connector_status_connected;
5930 /* If no HPD, poke DDC gently */
5931 if (drm_probe_ddc(&intel_dp->aux.ddc))
5932 return connector_status_connected;
5934 /* Well we tried, say unknown for unreliable port types */
5935 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5936 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5937 if (type == DP_DS_PORT_TYPE_VGA ||
5938 type == DP_DS_PORT_TYPE_NON_EDID)
5939 return connector_status_unknown;
5941 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5942 DP_DWN_STRM_PORT_TYPE_MASK;
5943 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5944 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5945 return connector_status_unknown;
5948 /* Anything else is out of spec, warn and ignore */
5949 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5950 return connector_status_disconnected;
5953 static enum drm_connector_status
5954 edp_detect(struct intel_dp *intel_dp)
5956 return connector_status_connected;
5959 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5962 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
5964 return intel_de_read(dev_priv, SDEISR) & bit;
5967 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5972 switch (encoder->hpd_pin) {
5974 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5977 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5980 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5983 MISSING_CASE(encoder->hpd_pin);
5987 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5990 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5992 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5995 switch (encoder->hpd_pin) {
5997 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6000 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6003 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6006 MISSING_CASE(encoder->hpd_pin);
6010 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6013 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6015 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6016 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6018 return intel_de_read(dev_priv, DEISR) & bit;
6022 * intel_digital_port_connected - is the specified port connected?
6023 * @encoder: intel_encoder
6025 * In cases where there's a connector physically connected but it can't be used
6026 * by our hardware we also return false, since the rest of the driver should
6027 * pretty much treat the port as disconnected. This is relevant for type-C
6028 * (starting on ICL) where there's ownership involved.
6030 * Return %true if port is connected, %false otherwise.
6032 bool intel_digital_port_connected(struct intel_encoder *encoder)
6034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6035 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6036 bool is_connected = false;
6037 intel_wakeref_t wakeref;
6039 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6040 is_connected = dig_port->connected(encoder);
6042 return is_connected;
6045 static struct edid *
6046 intel_dp_get_edid(struct intel_dp *intel_dp)
6048 struct intel_connector *intel_connector = intel_dp->attached_connector;
6050 /* use cached edid if we have one */
6051 if (intel_connector->edid) {
6053 if (IS_ERR(intel_connector->edid))
6056 return drm_edid_duplicate(intel_connector->edid);
6058 return drm_get_edid(&intel_connector->base,
6059 &intel_dp->aux.ddc);
6063 intel_dp_set_edid(struct intel_dp *intel_dp)
6065 struct intel_connector *intel_connector = intel_dp->attached_connector;
6068 intel_dp_unset_edid(intel_dp);
6069 edid = intel_dp_get_edid(intel_dp);
6070 intel_connector->detect_edid = edid;
6072 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6073 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6074 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6077 drm_dp_cec_set_edid(&intel_dp->aux, edid);
6078 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6082 intel_dp_unset_edid(struct intel_dp *intel_dp)
6084 struct intel_connector *intel_connector = intel_dp->attached_connector;
6086 drm_dp_cec_unset_edid(&intel_dp->aux);
6087 kfree(intel_connector->detect_edid);
6088 intel_connector->detect_edid = NULL;
6090 intel_dp->has_hdmi_sink = false;
6091 intel_dp->has_audio = false;
6092 intel_dp->edid_quirks = 0;
6096 intel_dp_detect(struct drm_connector *connector,
6097 struct drm_modeset_acquire_ctx *ctx,
6100 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6101 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6102 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6103 struct intel_encoder *encoder = &dig_port->base;
6104 enum drm_connector_status status;
6106 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6107 connector->base.id, connector->name);
6108 drm_WARN_ON(&dev_priv->drm,
6109 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6111 if (!INTEL_DISPLAY_ENABLED(dev_priv))
6112 return connector_status_disconnected;
6114 /* Can't disconnect eDP */
6115 if (intel_dp_is_edp(intel_dp))
6116 status = edp_detect(intel_dp);
6117 else if (intel_digital_port_connected(encoder))
6118 status = intel_dp_detect_dpcd(intel_dp);
6120 status = connector_status_disconnected;
6122 if (status == connector_status_disconnected) {
6123 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6124 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6126 if (intel_dp->is_mst) {
6127 drm_dbg_kms(&dev_priv->drm,
6128 "MST device may have disappeared %d vs %d\n",
6130 intel_dp->mst_mgr.mst_state);
6131 intel_dp->is_mst = false;
6132 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6139 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6140 if (INTEL_GEN(dev_priv) >= 11)
6141 intel_dp_get_dsc_sink_cap(intel_dp);
6143 intel_dp_configure_mst(intel_dp);
6146 * TODO: Reset link params when switching to MST mode, until MST
6147 * supports link training fallback params.
6149 if (intel_dp->reset_link_params || intel_dp->is_mst) {
6150 /* Initial max link lane count */
6151 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6153 /* Initial max link rate */
6154 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6156 intel_dp->reset_link_params = false;
6159 intel_dp_print_rates(intel_dp);
6161 if (intel_dp->is_mst) {
6163 * If we are in MST mode then this connector
6164 * won't appear connected or have anything
6167 status = connector_status_disconnected;
6172 * Some external monitors do not signal loss of link synchronization
6173 * with an IRQ_HPD, so force a link status check.
6175 if (!intel_dp_is_edp(intel_dp)) {
6178 ret = intel_dp_retrain_link(encoder, ctx);
6184 * Clearing NACK and defer counts to get their exact values
6185 * while reading EDID which are required by Compliance tests
6186 * 4.2.2.4 and 4.2.2.5
6188 intel_dp->aux.i2c_nack_count = 0;
6189 intel_dp->aux.i2c_defer_count = 0;
6191 intel_dp_set_edid(intel_dp);
6192 if (intel_dp_is_edp(intel_dp) ||
6193 to_intel_connector(connector)->detect_edid)
6194 status = connector_status_connected;
6196 intel_dp_check_service_irq(intel_dp);
6199 if (status != connector_status_connected && !intel_dp->is_mst)
6200 intel_dp_unset_edid(intel_dp);
6203 * Make sure the refs for power wells enabled during detect are
6204 * dropped to avoid a new detect cycle triggered by HPD polling.
6206 intel_display_power_flush_work(dev_priv);
6208 if (!intel_dp_is_edp(intel_dp))
6209 drm_dp_set_subconnector_property(connector,
6212 intel_dp->downstream_ports);
6217 intel_dp_force(struct drm_connector *connector)
6219 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6220 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6221 struct intel_encoder *intel_encoder = &dig_port->base;
6222 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6223 enum intel_display_power_domain aux_domain =
6224 intel_aux_power_domain(dig_port);
6225 intel_wakeref_t wakeref;
6227 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6228 connector->base.id, connector->name);
6229 intel_dp_unset_edid(intel_dp);
6231 if (connector->status != connector_status_connected)
6234 wakeref = intel_display_power_get(dev_priv, aux_domain);
6236 intel_dp_set_edid(intel_dp);
6238 intel_display_power_put(dev_priv, aux_domain, wakeref);
6241 static int intel_dp_get_modes(struct drm_connector *connector)
6243 struct intel_connector *intel_connector = to_intel_connector(connector);
6246 edid = intel_connector->detect_edid;
6248 int ret = intel_connector_update_modes(connector, edid);
6253 /* if eDP has no EDID, fall back to fixed mode */
6254 if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6255 intel_connector->panel.fixed_mode) {
6256 struct drm_display_mode *mode;
6258 mode = drm_mode_duplicate(connector->dev,
6259 intel_connector->panel.fixed_mode);
6261 drm_mode_probed_add(connector, mode);
6270 intel_dp_connector_register(struct drm_connector *connector)
6272 struct drm_i915_private *i915 = to_i915(connector->dev);
6273 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6276 ret = intel_connector_register(connector);
6280 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6281 intel_dp->aux.name, connector->kdev->kobj.name);
6283 intel_dp->aux.dev = connector->kdev;
6284 ret = drm_dp_aux_register(&intel_dp->aux);
6286 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6291 intel_dp_connector_unregister(struct drm_connector *connector)
6293 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6295 drm_dp_cec_unregister_connector(&intel_dp->aux);
6296 drm_dp_aux_unregister(&intel_dp->aux);
6297 intel_connector_unregister(connector);
6300 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6302 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6303 struct intel_dp *intel_dp = &dig_port->dp;
6305 intel_dp_mst_encoder_cleanup(dig_port);
6306 if (intel_dp_is_edp(intel_dp)) {
6307 intel_wakeref_t wakeref;
6309 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6311 * vdd might still be enabled do to the delayed vdd off.
6312 * Make sure vdd is actually turned off here.
6314 with_pps_lock(intel_dp, wakeref)
6315 edp_panel_vdd_off_sync(intel_dp);
6317 if (intel_dp->edp_notifier.notifier_call) {
6318 unregister_reboot_notifier(&intel_dp->edp_notifier);
6319 intel_dp->edp_notifier.notifier_call = NULL;
6323 intel_dp_aux_fini(intel_dp);
6326 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6328 intel_dp_encoder_flush_work(encoder);
6330 drm_encoder_cleanup(encoder);
6331 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6334 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6336 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6337 intel_wakeref_t wakeref;
6339 if (!intel_dp_is_edp(intel_dp))
6343 * vdd might still be enabled do to the delayed vdd off.
6344 * Make sure vdd is actually turned off here.
6346 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6347 with_pps_lock(intel_dp, wakeref)
6348 edp_panel_vdd_off_sync(intel_dp);
6351 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6353 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6354 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6356 lockdep_assert_held(&dev_priv->pps_mutex);
6358 if (!edp_have_panel_vdd(intel_dp))
6362 * The VDD bit needs a power domain reference, so if the bit is
6363 * already enabled when we boot or resume, grab this reference and
6364 * schedule a vdd off, so we don't hold on to the reference
6367 drm_dbg_kms(&dev_priv->drm,
6368 "VDD left on by BIOS, adjusting state tracking\n");
6369 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6371 edp_panel_vdd_schedule_off(intel_dp);
6374 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6376 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6377 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6380 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6381 encoder->port, &pipe))
6384 return INVALID_PIPE;
6387 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6389 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6390 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
6391 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6392 intel_wakeref_t wakeref;
6394 if (!HAS_DDI(dev_priv))
6395 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6398 lspcon_resume(lspcon);
6400 intel_dp->reset_link_params = true;
6402 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6403 !intel_dp_is_edp(intel_dp))
6406 with_pps_lock(intel_dp, wakeref) {
6407 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6408 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6410 if (intel_dp_is_edp(intel_dp)) {
6412 * Reinit the power sequencer, in case BIOS did
6413 * something nasty with it.
6415 intel_dp_pps_init(intel_dp);
6416 intel_edp_panel_vdd_sanitize(intel_dp);
6421 static int intel_modeset_tile_group(struct intel_atomic_state *state,
6424 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6425 struct drm_connector_list_iter conn_iter;
6426 struct drm_connector *connector;
6429 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6430 drm_for_each_connector_iter(connector, &conn_iter) {
6431 struct drm_connector_state *conn_state;
6432 struct intel_crtc_state *crtc_state;
6433 struct intel_crtc *crtc;
6435 if (!connector->has_tile ||
6436 connector->tile_group->id != tile_group_id)
6439 conn_state = drm_atomic_get_connector_state(&state->base,
6441 if (IS_ERR(conn_state)) {
6442 ret = PTR_ERR(conn_state);
6446 crtc = to_intel_crtc(conn_state->crtc);
6451 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6452 crtc_state->uapi.mode_changed = true;
6454 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6458 drm_connector_list_iter_end(&conn_iter);
6463 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6465 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6466 struct intel_crtc *crtc;
6468 if (transcoders == 0)
6471 for_each_intel_crtc(&dev_priv->drm, crtc) {
6472 struct intel_crtc_state *crtc_state;
6475 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6476 if (IS_ERR(crtc_state))
6477 return PTR_ERR(crtc_state);
6479 if (!crtc_state->hw.enable)
6482 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6485 crtc_state->uapi.mode_changed = true;
6487 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6491 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6495 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6498 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6503 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6504 struct drm_connector *connector)
6506 const struct drm_connector_state *old_conn_state =
6507 drm_atomic_get_old_connector_state(&state->base, connector);
6508 const struct intel_crtc_state *old_crtc_state;
6509 struct intel_crtc *crtc;
6512 crtc = to_intel_crtc(old_conn_state->crtc);
6516 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6518 if (!old_crtc_state->hw.active)
6521 transcoders = old_crtc_state->sync_mode_slaves_mask;
6522 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6523 transcoders |= BIT(old_crtc_state->master_transcoder);
6525 return intel_modeset_affected_transcoders(state,
6529 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6530 struct drm_atomic_state *_state)
6532 struct drm_i915_private *dev_priv = to_i915(conn->dev);
6533 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6536 ret = intel_digital_connector_atomic_check(conn, &state->base);
6541 * We don't enable port sync on BDW due to missing w/as and
6542 * due to not having adjusted the modeset sequence appropriately.
6544 if (INTEL_GEN(dev_priv) < 9)
6547 if (!intel_connector_needs_modeset(state, conn))
6550 if (conn->has_tile) {
6551 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6556 return intel_modeset_synced_crtcs(state, conn);
6559 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6560 .force = intel_dp_force,
6561 .fill_modes = drm_helper_probe_single_connector_modes,
6562 .atomic_get_property = intel_digital_connector_atomic_get_property,
6563 .atomic_set_property = intel_digital_connector_atomic_set_property,
6564 .late_register = intel_dp_connector_register,
6565 .early_unregister = intel_dp_connector_unregister,
6566 .destroy = intel_connector_destroy,
6567 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6568 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6571 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6572 .detect_ctx = intel_dp_detect,
6573 .get_modes = intel_dp_get_modes,
6574 .mode_valid = intel_dp_mode_valid,
6575 .atomic_check = intel_dp_connector_atomic_check,
6578 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6579 .reset = intel_dp_encoder_reset,
6580 .destroy = intel_dp_encoder_destroy,
6583 static bool intel_edp_have_power(struct intel_dp *intel_dp)
6585 intel_wakeref_t wakeref;
6586 bool have_power = false;
6588 with_pps_lock(intel_dp, wakeref) {
6589 have_power = edp_have_panel_power(intel_dp) &&
6590 edp_have_panel_vdd(intel_dp);
6597 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6599 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6600 struct intel_dp *intel_dp = &dig_port->dp;
6602 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6603 (long_hpd || !intel_edp_have_power(intel_dp))) {
6605 * vdd off can generate a long/short pulse on eDP which
6606 * would require vdd on to handle it, and thus we
6607 * would end up in an endless cycle of
6608 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6610 drm_dbg_kms(&i915->drm,
6611 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6612 long_hpd ? "long" : "short",
6613 dig_port->base.base.base.id,
6614 dig_port->base.base.name);
6618 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6619 dig_port->base.base.base.id,
6620 dig_port->base.base.name,
6621 long_hpd ? "long" : "short");
6624 intel_dp->reset_link_params = true;
6628 if (intel_dp->is_mst) {
6629 if (!intel_dp_check_mst_status(intel_dp))
6631 } else if (!intel_dp_short_pulse(intel_dp)) {
6638 /* check the VBT to see whether the eDP is on another port */
6639 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6642 * eDP not supported on g4x. so bail out early just
6643 * for a bit extra safety in case the VBT is bonkers.
6645 if (INTEL_GEN(dev_priv) < 5)
6648 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6651 return intel_bios_is_port_edp(dev_priv, port);
6655 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6657 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6658 enum port port = dp_to_dig_port(intel_dp)->base.port;
6660 if (!intel_dp_is_edp(intel_dp))
6661 drm_connector_attach_dp_subconnector_property(connector);
6663 if (!IS_G4X(dev_priv) && port != PORT_A)
6664 intel_attach_force_audio_property(connector);
6666 intel_attach_broadcast_rgb_property(connector);
6667 if (HAS_GMCH(dev_priv))
6668 drm_connector_attach_max_bpc_property(connector, 6, 10);
6669 else if (INTEL_GEN(dev_priv) >= 5)
6670 drm_connector_attach_max_bpc_property(connector, 6, 12);
6672 intel_attach_colorspace_property(connector);
6674 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6675 drm_object_attach_property(&connector->base,
6676 connector->dev->mode_config.hdr_output_metadata_property,
6679 if (intel_dp_is_edp(intel_dp)) {
6680 u32 allowed_scalers;
6682 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6683 if (!HAS_GMCH(dev_priv))
6684 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6686 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6688 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6693 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6695 intel_dp->panel_power_off_time = ktime_get_boottime();
6696 intel_dp->last_power_on = jiffies;
6697 intel_dp->last_backlight_off = jiffies;
6701 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6703 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6704 u32 pp_on, pp_off, pp_ctl;
6705 struct pps_registers regs;
6707 intel_pps_get_registers(intel_dp, ®s);
6709 pp_ctl = ilk_get_pp_control(intel_dp);
6711 /* Ensure PPS is unlocked */
6712 if (!HAS_DDI(dev_priv))
6713 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
6715 pp_on = intel_de_read(dev_priv, regs.pp_on);
6716 pp_off = intel_de_read(dev_priv, regs.pp_off);
6718 /* Pull timing values out of registers */
6719 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6720 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6721 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6722 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6724 if (i915_mmio_reg_valid(regs.pp_div)) {
6727 pp_div = intel_de_read(dev_priv, regs.pp_div);
6729 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6731 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6736 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6738 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6740 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6744 intel_pps_verify_state(struct intel_dp *intel_dp)
6746 struct edp_power_seq hw;
6747 struct edp_power_seq *sw = &intel_dp->pps_delays;
6749 intel_pps_readout_hw_state(intel_dp, &hw);
6751 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6752 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6753 DRM_ERROR("PPS state mismatch\n");
6754 intel_pps_dump_state("sw", sw);
6755 intel_pps_dump_state("hw", &hw);
6760 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6762 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6763 struct edp_power_seq cur, vbt, spec,
6764 *final = &intel_dp->pps_delays;
6766 lockdep_assert_held(&dev_priv->pps_mutex);
6768 /* already initialized? */
6769 if (final->t11_t12 != 0)
6772 intel_pps_readout_hw_state(intel_dp, &cur);
6774 intel_pps_dump_state("cur", &cur);
6776 vbt = dev_priv->vbt.edp.pps;
6777 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6778 * of 500ms appears to be too short. Ocassionally the panel
6779 * just fails to power back on. Increasing the delay to 800ms
6780 * seems sufficient to avoid this problem.
6782 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6783 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6784 drm_dbg_kms(&dev_priv->drm,
6785 "Increasing T12 panel delay as per the quirk to %d\n",
6788 /* T11_T12 delay is special and actually in units of 100ms, but zero
6789 * based in the hw (so we need to add 100 ms). But the sw vbt
6790 * table multiplies it with 1000 to make it in units of 100usec,
6792 vbt.t11_t12 += 100 * 10;
6794 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6795 * our hw here, which are all in 100usec. */
6796 spec.t1_t3 = 210 * 10;
6797 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6798 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6799 spec.t10 = 500 * 10;
6800 /* This one is special and actually in units of 100ms, but zero
6801 * based in the hw (so we need to add 100 ms). But the sw vbt
6802 * table multiplies it with 1000 to make it in units of 100usec,
6804 spec.t11_t12 = (510 + 100) * 10;
6806 intel_pps_dump_state("vbt", &vbt);
6808 /* Use the max of the register settings and vbt. If both are
6809 * unset, fall back to the spec limits. */
6810 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6812 max(cur.field, vbt.field))
6813 assign_final(t1_t3);
6817 assign_final(t11_t12);
6820 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6821 intel_dp->panel_power_up_delay = get_delay(t1_t3);
6822 intel_dp->backlight_on_delay = get_delay(t8);
6823 intel_dp->backlight_off_delay = get_delay(t9);
6824 intel_dp->panel_power_down_delay = get_delay(t10);
6825 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6828 drm_dbg_kms(&dev_priv->drm,
6829 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
6830 intel_dp->panel_power_up_delay,
6831 intel_dp->panel_power_down_delay,
6832 intel_dp->panel_power_cycle_delay);
6834 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
6835 intel_dp->backlight_on_delay,
6836 intel_dp->backlight_off_delay);
6839 * We override the HW backlight delays to 1 because we do manual waits
6840 * on them. For T8, even BSpec recommends doing it. For T9, if we
6841 * don't do this, we'll end up waiting for the backlight off delay
6842 * twice: once when we do the manual sleep, and once when we disable
6843 * the panel and wait for the PP_STATUS bit to become zero.
6849 * HW has only a 100msec granularity for t11_t12 so round it up
6852 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6856 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6857 bool force_disable_vdd)
6859 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6860 u32 pp_on, pp_off, port_sel = 0;
6861 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
6862 struct pps_registers regs;
6863 enum port port = dp_to_dig_port(intel_dp)->base.port;
6864 const struct edp_power_seq *seq = &intel_dp->pps_delays;
6866 lockdep_assert_held(&dev_priv->pps_mutex);
6868 intel_pps_get_registers(intel_dp, ®s);
6871 * On some VLV machines the BIOS can leave the VDD
6872 * enabled even on power sequencers which aren't
6873 * hooked up to any port. This would mess up the
6874 * power domain tracking the first time we pick
6875 * one of these power sequencers for use since
6876 * edp_panel_vdd_on() would notice that the VDD was
6877 * already on and therefore wouldn't grab the power
6878 * domain reference. Disable VDD first to avoid this.
6879 * This also avoids spuriously turning the VDD on as
6880 * soon as the new power sequencer gets initialized.
6882 if (force_disable_vdd) {
6883 u32 pp = ilk_get_pp_control(intel_dp);
6885 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
6886 "Panel power already on\n");
6888 if (pp & EDP_FORCE_VDD)
6889 drm_dbg_kms(&dev_priv->drm,
6890 "VDD already on, disabling first\n");
6892 pp &= ~EDP_FORCE_VDD;
6894 intel_de_write(dev_priv, regs.pp_ctrl, pp);
6897 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6898 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6899 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6900 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6902 /* Haswell doesn't have any port selection bits for the panel
6903 * power sequencer any more. */
6904 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6905 port_sel = PANEL_PORT_SELECT_VLV(port);
6906 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6909 port_sel = PANEL_PORT_SELECT_DPA;
6912 port_sel = PANEL_PORT_SELECT_DPC;
6915 port_sel = PANEL_PORT_SELECT_DPD;
6925 intel_de_write(dev_priv, regs.pp_on, pp_on);
6926 intel_de_write(dev_priv, regs.pp_off, pp_off);
6929 * Compute the divisor for the pp clock, simply match the Bspec formula.
6931 if (i915_mmio_reg_valid(regs.pp_div)) {
6932 intel_de_write(dev_priv, regs.pp_div,
6933 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6937 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
6938 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6939 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6940 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
6943 drm_dbg_kms(&dev_priv->drm,
6944 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6945 intel_de_read(dev_priv, regs.pp_on),
6946 intel_de_read(dev_priv, regs.pp_off),
6947 i915_mmio_reg_valid(regs.pp_div) ?
6948 intel_de_read(dev_priv, regs.pp_div) :
6949 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6952 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6954 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6956 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6957 vlv_initial_power_sequencer_setup(intel_dp);
6959 intel_dp_init_panel_power_sequencer(intel_dp);
6960 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6965 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6966 * @dev_priv: i915 device
6967 * @crtc_state: a pointer to the active intel_crtc_state
6968 * @refresh_rate: RR to be programmed
6970 * This function gets called when refresh rate (RR) has to be changed from
6971 * one frequency to another. Switches can be between high and low RR
6972 * supported by the panel or to any other RR based on media playback (in
6973 * this case, RR value needs to be passed from user space).
6975 * The caller of this function needs to take a lock on dev_priv->drrs.
6977 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6978 const struct intel_crtc_state *crtc_state,
6981 struct intel_dp *intel_dp = dev_priv->drrs.dp;
6982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
6983 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6985 if (refresh_rate <= 0) {
6986 drm_dbg_kms(&dev_priv->drm,
6987 "Refresh rate should be positive non-zero.\n");
6991 if (intel_dp == NULL) {
6992 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
6997 drm_dbg_kms(&dev_priv->drm,
6998 "DRRS: intel_crtc not initialized\n");
7002 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7003 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7007 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7009 index = DRRS_LOW_RR;
7011 if (index == dev_priv->drrs.refresh_rate_type) {
7012 drm_dbg_kms(&dev_priv->drm,
7013 "DRRS requested for previously set RR...ignoring\n");
7017 if (!crtc_state->hw.active) {
7018 drm_dbg_kms(&dev_priv->drm,
7019 "eDP encoder disabled. CRTC not Active\n");
7023 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7026 intel_dp_set_m_n(crtc_state, M1_N1);
7029 intel_dp_set_m_n(crtc_state, M2_N2);
7033 drm_err(&dev_priv->drm,
7034 "Unsupported refreshrate type\n");
7036 } else if (INTEL_GEN(dev_priv) > 6) {
7037 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7040 val = intel_de_read(dev_priv, reg);
7041 if (index > DRRS_HIGH_RR) {
7042 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7043 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7045 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7047 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7048 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7050 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7052 intel_de_write(dev_priv, reg, val);
7055 dev_priv->drrs.refresh_rate_type = index;
7057 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7062 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7064 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7066 dev_priv->drrs.busy_frontbuffer_bits = 0;
7067 dev_priv->drrs.dp = intel_dp;
7071 * intel_edp_drrs_enable - init drrs struct if supported
7072 * @intel_dp: DP struct
7073 * @crtc_state: A pointer to the active crtc state.
7075 * Initializes frontbuffer_bits and drrs.dp
7077 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7078 const struct intel_crtc_state *crtc_state)
7080 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7082 if (!crtc_state->has_drrs)
7085 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7087 mutex_lock(&dev_priv->drrs.mutex);
7089 if (dev_priv->drrs.dp) {
7090 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
7094 intel_edp_drrs_enable_locked(intel_dp);
7097 mutex_unlock(&dev_priv->drrs.mutex);
7101 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
7102 const struct intel_crtc_state *crtc_state)
7104 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7106 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
7109 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
7110 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
7113 dev_priv->drrs.dp = NULL;
7117 * intel_edp_drrs_disable - Disable DRRS
7118 * @intel_dp: DP struct
7119 * @old_crtc_state: Pointer to old crtc_state.
7122 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7123 const struct intel_crtc_state *old_crtc_state)
7125 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7127 if (!old_crtc_state->has_drrs)
7130 mutex_lock(&dev_priv->drrs.mutex);
7131 if (!dev_priv->drrs.dp) {
7132 mutex_unlock(&dev_priv->drrs.mutex);
7136 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
7137 mutex_unlock(&dev_priv->drrs.mutex);
7139 cancel_delayed_work_sync(&dev_priv->drrs.work);
7143 * intel_edp_drrs_update - Update DRRS state
7144 * @intel_dp: Intel DP
7145 * @crtc_state: new CRTC state
7147 * This function will update DRRS states, disabling or enabling DRRS when
7148 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
7149 * intel_edp_drrs_enable() should be called instead.
7152 intel_edp_drrs_update(struct intel_dp *intel_dp,
7153 const struct intel_crtc_state *crtc_state)
7155 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7157 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
7160 mutex_lock(&dev_priv->drrs.mutex);
7162 /* New state matches current one? */
7163 if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
7166 if (crtc_state->has_drrs)
7167 intel_edp_drrs_enable_locked(intel_dp);
7169 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
7172 mutex_unlock(&dev_priv->drrs.mutex);
7175 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7177 struct drm_i915_private *dev_priv =
7178 container_of(work, typeof(*dev_priv), drrs.work.work);
7179 struct intel_dp *intel_dp;
7181 mutex_lock(&dev_priv->drrs.mutex);
7183 intel_dp = dev_priv->drrs.dp;
7189 * The delayed work can race with an invalidate hence we need to
7193 if (dev_priv->drrs.busy_frontbuffer_bits)
7196 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7197 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7199 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7200 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
7204 mutex_unlock(&dev_priv->drrs.mutex);
7208 * intel_edp_drrs_invalidate - Disable Idleness DRRS
7209 * @dev_priv: i915 device
7210 * @frontbuffer_bits: frontbuffer plane tracking bits
7212 * This function gets called everytime rendering on the given planes start.
7213 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7215 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7217 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7218 unsigned int frontbuffer_bits)
7220 struct intel_dp *intel_dp;
7221 struct drm_crtc *crtc;
7224 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7227 cancel_delayed_work(&dev_priv->drrs.work);
7229 mutex_lock(&dev_priv->drrs.mutex);
7231 intel_dp = dev_priv->drrs.dp;
7233 mutex_unlock(&dev_priv->drrs.mutex);
7237 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7238 pipe = to_intel_crtc(crtc)->pipe;
7240 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7241 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7243 /* invalidate means busy screen hence upclock */
7244 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7245 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7246 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7248 mutex_unlock(&dev_priv->drrs.mutex);
7252 * intel_edp_drrs_flush - Restart Idleness DRRS
7253 * @dev_priv: i915 device
7254 * @frontbuffer_bits: frontbuffer plane tracking bits
7256 * This function gets called every time rendering on the given planes has
7257 * completed or flip on a crtc is completed. So DRRS should be upclocked
7258 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7259 * if no other planes are dirty.
7261 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7263 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7264 unsigned int frontbuffer_bits)
7266 struct intel_dp *intel_dp;
7267 struct drm_crtc *crtc;
7270 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7273 cancel_delayed_work(&dev_priv->drrs.work);
7275 mutex_lock(&dev_priv->drrs.mutex);
7277 intel_dp = dev_priv->drrs.dp;
7279 mutex_unlock(&dev_priv->drrs.mutex);
7283 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7284 pipe = to_intel_crtc(crtc)->pipe;
7286 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7287 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7289 /* flush means busy screen hence upclock */
7290 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7291 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7292 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7295 * flush also means no more activity hence schedule downclock, if all
7296 * other fbs are quiescent too
7298 if (!dev_priv->drrs.busy_frontbuffer_bits)
7299 schedule_delayed_work(&dev_priv->drrs.work,
7300 msecs_to_jiffies(1000));
7301 mutex_unlock(&dev_priv->drrs.mutex);
7305 * DOC: Display Refresh Rate Switching (DRRS)
7307 * Display Refresh Rate Switching (DRRS) is a power conservation feature
7308 * which enables swtching between low and high refresh rates,
7309 * dynamically, based on the usage scenario. This feature is applicable
7310 * for internal panels.
7312 * Indication that the panel supports DRRS is given by the panel EDID, which
7313 * would list multiple refresh rates for one resolution.
7315 * DRRS is of 2 types - static and seamless.
7316 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7317 * (may appear as a blink on screen) and is used in dock-undock scenario.
7318 * Seamless DRRS involves changing RR without any visual effect to the user
7319 * and can be used during normal system usage. This is done by programming
7320 * certain registers.
7322 * Support for static/seamless DRRS may be indicated in the VBT based on
7323 * inputs from the panel spec.
7325 * DRRS saves power by switching to low RR based on usage scenarios.
7327 * The implementation is based on frontbuffer tracking implementation. When
7328 * there is a disturbance on the screen triggered by user activity or a periodic
7329 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7330 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7333 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7334 * and intel_edp_drrs_flush() are called.
7336 * DRRS can be further extended to support other internal panels and also
7337 * the scenario of video playback wherein RR is set based on the rate
7338 * requested by userspace.
7342 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7343 * @connector: eDP connector
7344 * @fixed_mode: preferred mode of panel
7346 * This function is called only once at driver load to initialize basic
7350 * Downclock mode if panel supports it, else return NULL.
7351 * DRRS support is determined by the presence of downclock mode (apart
7352 * from VBT setting).
7354 static struct drm_display_mode *
7355 intel_dp_drrs_init(struct intel_connector *connector,
7356 struct drm_display_mode *fixed_mode)
7358 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7359 struct drm_display_mode *downclock_mode = NULL;
7361 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7362 mutex_init(&dev_priv->drrs.mutex);
7364 if (INTEL_GEN(dev_priv) <= 6) {
7365 drm_dbg_kms(&dev_priv->drm,
7366 "DRRS supported for Gen7 and above\n");
7370 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7371 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
7375 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7376 if (!downclock_mode) {
7377 drm_dbg_kms(&dev_priv->drm,
7378 "Downclock mode is not found. DRRS not supported\n");
7382 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7384 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7385 drm_dbg_kms(&dev_priv->drm,
7386 "seamless DRRS supported for eDP panel.\n");
7387 return downclock_mode;
7390 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7391 struct intel_connector *intel_connector)
7393 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7394 struct drm_device *dev = &dev_priv->drm;
7395 struct drm_connector *connector = &intel_connector->base;
7396 struct drm_display_mode *fixed_mode = NULL;
7397 struct drm_display_mode *downclock_mode = NULL;
7399 enum pipe pipe = INVALID_PIPE;
7400 intel_wakeref_t wakeref;
7403 if (!intel_dp_is_edp(intel_dp))
7406 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7409 * On IBX/CPT we may get here with LVDS already registered. Since the
7410 * driver uses the only internal power sequencer available for both
7411 * eDP and LVDS bail out early in this case to prevent interfering
7412 * with an already powered-on LVDS power sequencer.
7414 if (intel_get_lvds_encoder(dev_priv)) {
7416 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7417 drm_info(&dev_priv->drm,
7418 "LVDS was detected, not registering eDP\n");
7423 with_pps_lock(intel_dp, wakeref) {
7424 intel_dp_init_panel_power_timestamps(intel_dp);
7425 intel_dp_pps_init(intel_dp);
7426 intel_edp_panel_vdd_sanitize(intel_dp);
7429 /* Cache DPCD and EDID for edp. */
7430 has_dpcd = intel_edp_init_dpcd(intel_dp);
7433 /* if this fails, presume the device is a ghost */
7434 drm_info(&dev_priv->drm,
7435 "failed to retrieve link info, disabling eDP\n");
7439 mutex_lock(&dev->mode_config.mutex);
7440 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7442 if (drm_add_edid_modes(connector, edid)) {
7443 drm_connector_update_edid_property(connector, edid);
7444 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
7447 edid = ERR_PTR(-EINVAL);
7450 edid = ERR_PTR(-ENOENT);
7452 intel_connector->edid = edid;
7454 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7456 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7458 /* fallback to VBT if available for eDP */
7460 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7461 mutex_unlock(&dev->mode_config.mutex);
7463 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7464 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7465 register_reboot_notifier(&intel_dp->edp_notifier);
7468 * Figure out the current pipe for the initial backlight setup.
7469 * If the current pipe isn't valid, try the PPS pipe, and if that
7470 * fails just assume pipe A.
7472 pipe = vlv_active_pipe(intel_dp);
7474 if (pipe != PIPE_A && pipe != PIPE_B)
7475 pipe = intel_dp->pps_pipe;
7477 if (pipe != PIPE_A && pipe != PIPE_B)
7480 drm_dbg_kms(&dev_priv->drm,
7481 "using pipe %c for initial backlight setup\n",
7485 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7486 intel_connector->panel.backlight.power = intel_edp_backlight_power;
7487 intel_panel_setup_backlight(connector, pipe);
7490 drm_connector_set_panel_orientation_with_quirk(connector,
7491 dev_priv->vbt.orientation,
7492 fixed_mode->hdisplay, fixed_mode->vdisplay);
7498 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7500 * vdd might still be enabled do to the delayed vdd off.
7501 * Make sure vdd is actually turned off here.
7503 with_pps_lock(intel_dp, wakeref)
7504 edp_panel_vdd_off_sync(intel_dp);
7509 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7511 struct intel_connector *intel_connector;
7512 struct drm_connector *connector;
7514 intel_connector = container_of(work, typeof(*intel_connector),
7515 modeset_retry_work);
7516 connector = &intel_connector->base;
7517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7520 /* Grab the locks before changing connector property*/
7521 mutex_lock(&connector->dev->mode_config.mutex);
7522 /* Set connector link status to BAD and send a Uevent to notify
7523 * userspace to do a modeset.
7525 drm_connector_set_link_status_property(connector,
7526 DRM_MODE_LINK_STATUS_BAD);
7527 mutex_unlock(&connector->dev->mode_config.mutex);
7528 /* Send Hotplug uevent so userspace can reprobe */
7529 drm_kms_helper_hotplug_event(connector->dev);
7533 intel_dp_init_connector(struct intel_digital_port *dig_port,
7534 struct intel_connector *intel_connector)
7536 struct drm_connector *connector = &intel_connector->base;
7537 struct intel_dp *intel_dp = &dig_port->dp;
7538 struct intel_encoder *intel_encoder = &dig_port->base;
7539 struct drm_device *dev = intel_encoder->base.dev;
7540 struct drm_i915_private *dev_priv = to_i915(dev);
7541 enum port port = intel_encoder->port;
7542 enum phy phy = intel_port_to_phy(dev_priv, port);
7545 /* Initialize the work for modeset in case of link train failure */
7546 INIT_WORK(&intel_connector->modeset_retry_work,
7547 intel_dp_modeset_retry_work_fn);
7549 if (drm_WARN(dev, dig_port->max_lanes < 1,
7550 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7551 dig_port->max_lanes, intel_encoder->base.base.id,
7552 intel_encoder->base.name))
7555 intel_dp_set_source_rates(intel_dp);
7557 intel_dp->reset_link_params = true;
7558 intel_dp->pps_pipe = INVALID_PIPE;
7559 intel_dp->active_pipe = INVALID_PIPE;
7561 /* Preserve the current hw state. */
7562 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7563 intel_dp->attached_connector = intel_connector;
7565 if (intel_dp_is_port_edp(dev_priv, port)) {
7567 * Currently we don't support eDP on TypeC ports, although in
7568 * theory it could work on TypeC legacy ports.
7570 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
7571 type = DRM_MODE_CONNECTOR_eDP;
7573 type = DRM_MODE_CONNECTOR_DisplayPort;
7576 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7577 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7580 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7581 * for DP the encoder type can be set by the caller to
7582 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7584 if (type == DRM_MODE_CONNECTOR_eDP)
7585 intel_encoder->type = INTEL_OUTPUT_EDP;
7587 /* eDP only on port B and/or C on vlv/chv */
7588 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
7589 IS_CHERRYVIEW(dev_priv)) &&
7590 intel_dp_is_edp(intel_dp) &&
7591 port != PORT_B && port != PORT_C))
7594 drm_dbg_kms(&dev_priv->drm,
7595 "Adding %s connector on [ENCODER:%d:%s]\n",
7596 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7597 intel_encoder->base.base.id, intel_encoder->base.name);
7599 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7600 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7602 if (!HAS_GMCH(dev_priv))
7603 connector->interlace_allowed = true;
7604 connector->doublescan_allowed = 0;
7606 if (INTEL_GEN(dev_priv) >= 11)
7607 connector->ycbcr_420_allowed = true;
7609 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
7611 intel_dp_aux_init(intel_dp);
7613 intel_connector_attach_encoder(intel_connector, intel_encoder);
7615 if (HAS_DDI(dev_priv))
7616 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7618 intel_connector->get_hw_state = intel_connector_get_hw_state;
7620 /* init MST on ports that can support it */
7621 intel_dp_mst_encoder_init(dig_port,
7622 intel_connector->base.base.id);
7624 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7625 intel_dp_aux_fini(intel_dp);
7626 intel_dp_mst_encoder_cleanup(dig_port);
7630 intel_dp_add_properties(intel_dp, connector);
7632 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7633 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
7635 drm_dbg_kms(&dev_priv->drm,
7636 "HDCP init failed, skipping.\n");
7639 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7640 * 0xd. Failure to do so will result in spurious interrupts being
7641 * generated on the port when a cable is not attached.
7643 if (IS_G45(dev_priv)) {
7644 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
7645 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
7646 (temp & ~0xf) | 0xd);
7652 drm_connector_cleanup(connector);
7657 bool intel_dp_init(struct drm_i915_private *dev_priv,
7658 i915_reg_t output_reg,
7661 struct intel_digital_port *dig_port;
7662 struct intel_encoder *intel_encoder;
7663 struct drm_encoder *encoder;
7664 struct intel_connector *intel_connector;
7666 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
7670 intel_connector = intel_connector_alloc();
7671 if (!intel_connector)
7672 goto err_connector_alloc;
7674 intel_encoder = &dig_port->base;
7675 encoder = &intel_encoder->base;
7677 mutex_init(&dig_port->hdcp_mutex);
7679 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7680 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7681 "DP %c", port_name(port)))
7682 goto err_encoder_init;
7684 intel_encoder->hotplug = intel_dp_hotplug;
7685 intel_encoder->compute_config = intel_dp_compute_config;
7686 intel_encoder->get_hw_state = intel_dp_get_hw_state;
7687 intel_encoder->get_config = intel_dp_get_config;
7688 intel_encoder->update_pipe = intel_panel_update_backlight;
7689 intel_encoder->suspend = intel_dp_encoder_suspend;
7690 if (IS_CHERRYVIEW(dev_priv)) {
7691 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7692 intel_encoder->pre_enable = chv_pre_enable_dp;
7693 intel_encoder->enable = vlv_enable_dp;
7694 intel_encoder->disable = vlv_disable_dp;
7695 intel_encoder->post_disable = chv_post_disable_dp;
7696 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7697 } else if (IS_VALLEYVIEW(dev_priv)) {
7698 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7699 intel_encoder->pre_enable = vlv_pre_enable_dp;
7700 intel_encoder->enable = vlv_enable_dp;
7701 intel_encoder->disable = vlv_disable_dp;
7702 intel_encoder->post_disable = vlv_post_disable_dp;
7704 intel_encoder->pre_enable = g4x_pre_enable_dp;
7705 intel_encoder->enable = g4x_enable_dp;
7706 intel_encoder->disable = g4x_disable_dp;
7707 intel_encoder->post_disable = g4x_post_disable_dp;
7710 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
7711 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
7712 dig_port->dp.set_link_train = cpt_set_link_train;
7714 dig_port->dp.set_link_train = g4x_set_link_train;
7716 if (IS_CHERRYVIEW(dev_priv))
7717 dig_port->dp.set_signal_levels = chv_set_signal_levels;
7718 else if (IS_VALLEYVIEW(dev_priv))
7719 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
7720 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
7721 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
7722 else if (IS_GEN(dev_priv, 6) && port == PORT_A)
7723 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
7725 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
7727 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
7728 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
7729 dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
7730 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
7732 dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
7733 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
7736 dig_port->dp.output_reg = output_reg;
7737 dig_port->max_lanes = 4;
7738 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
7739 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
7741 intel_encoder->type = INTEL_OUTPUT_DP;
7742 intel_encoder->power_domain = intel_port_to_power_domain(port);
7743 if (IS_CHERRYVIEW(dev_priv)) {
7745 intel_encoder->pipe_mask = BIT(PIPE_C);
7747 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
7749 intel_encoder->pipe_mask = ~0;
7751 intel_encoder->cloneable = 0;
7752 intel_encoder->port = port;
7753 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7755 dig_port->hpd_pulse = intel_dp_hpd_pulse;
7757 if (HAS_GMCH(dev_priv)) {
7758 if (IS_GM45(dev_priv))
7759 dig_port->connected = gm45_digital_port_connected;
7761 dig_port->connected = g4x_digital_port_connected;
7764 dig_port->connected = ilk_digital_port_connected;
7766 dig_port->connected = ibx_digital_port_connected;
7770 intel_infoframe_init(dig_port);
7772 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7773 if (!intel_dp_init_connector(dig_port, intel_connector))
7774 goto err_init_connector;
7779 drm_encoder_cleanup(encoder);
7781 kfree(intel_connector);
7782 err_connector_alloc:
7787 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7789 struct intel_encoder *encoder;
7791 for_each_intel_encoder(&dev_priv->drm, encoder) {
7792 struct intel_dp *intel_dp;
7794 if (encoder->type != INTEL_OUTPUT_DDI)
7797 intel_dp = enc_to_intel_dp(encoder);
7799 if (!intel_dp->can_mst)
7802 if (intel_dp->is_mst)
7803 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7807 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7809 struct intel_encoder *encoder;
7811 for_each_intel_encoder(&dev_priv->drm, encoder) {
7812 struct intel_dp *intel_dp;
7815 if (encoder->type != INTEL_OUTPUT_DDI)
7818 intel_dp = enc_to_intel_dp(encoder);
7820 if (!intel_dp->can_mst)
7823 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
7826 intel_dp->is_mst = false;
7827 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,