drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43
  44 #include "i915_debugfs.h"
  45 #include "i915_drv.h"
  46 #include "i915_trace.h"
  47 #include "intel_atomic.h"
  48 #include "intel_audio.h"
  49 #include "intel_connector.h"
  50 #include "intel_ddi.h"
  51 #include "intel_display_types.h"
  52 #include "intel_dp.h"
  53 #include "intel_dp_link_training.h"
  54 #include "intel_dp_mst.h"
  55 #include "intel_dpio_phy.h"
  56 #include "intel_fifo_underrun.h"
  57 #include "intel_hdcp.h"
  58 #include "intel_hdmi.h"
  59 #include "intel_hotplug.h"
  60 #include "intel_lspcon.h"
  61 #include "intel_lvds.h"
  62 #include "intel_panel.h"
  63 #include "intel_psr.h"
  64 #include "intel_sideband.h"
  65 #include "intel_tc.h"
  66 #include "intel_vdsc.h"
  67
  68 #define DP_DPRX_ESI_LEN 14
  69
  70 /* DP DSC throughput values used for slice count calculations KPixels/s */
  71 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  72 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  74
  75 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  76 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  77
  78 /* Compliance test status bits  */
  79 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  80 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83
  84 struct dp_link_dpll {
  85         int clock;
  86         struct dpll dpll;
  87 };
  88
  89 static const struct dp_link_dpll g4x_dpll[] = {
  90         { 162000,
  91                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  92         { 270000,
  93                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  94 };
  95
  96 static const struct dp_link_dpll pch_dpll[] = {
  97         { 162000,
  98                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  99         { 270000,
 100                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 101 };
 102
 103 static const struct dp_link_dpll vlv_dpll[] = {
 104         { 162000,
 105                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 106         { 270000,
 107                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 108 };
 109
 110 /*
 111  * CHV supports eDP 1.4 that have  more link rates.
 112  * Below only provides the fixed rate but exclude variable rate.
 113  */
 114 static const struct dp_link_dpll chv_dpll[] = {
 115         /*
 116          * CHV requires to program fractional division for m2.
 117          * m2 is stored in fixed point format using formula below
 118          * (m2_int << 22) | m2_fraction
 119          */
 120         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 121                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 122         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 123                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 124 };
 125
 126 /* Constants for DP DSC configurations */
 127 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 128
 129 /* With Single pipe configuration, HW is capable of supporting maximum
 130  * of 4 slices per line.
 131  */
 132 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 133
 134 /**
 135  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 136  * @intel_dp: DP struct
 137  *
 138  * If a CPU or PCH DP output is attached to an eDP panel, this function
 139  * will return true, and false otherwise.
 140  */
 141 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 142 {
 143         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 144
 145         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 146 }
 147
 148 static void intel_dp_link_down(struct intel_encoder *encoder,
 149                                const struct intel_crtc_state *old_crtc_state);
 150 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 151 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 152 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 153                                            const struct intel_crtc_state *crtc_state);
 154 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 155                                       enum pipe pipe);
 156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 157
 158 /* update sink rates from dpcd */
 159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 160 {
 161         static const int dp_rates[] = {
 162                 162000, 270000, 540000, 810000
 163         };
 164         int i, max_rate;
 165
 166         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 167                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 168                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 169                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 170
 171                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 172                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 173
 174                 return;
 175         }
 176
 177         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 178
 179         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 180                 if (dp_rates[i] > max_rate)
 181                         break;
 182                 intel_dp->sink_rates[i] = dp_rates[i];
 183         }
 184
 185         intel_dp->num_sink_rates = i;
 186 }
 187
 188 /* Get length of rates array potentially limited by max_rate. */
 189 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 190 {
 191         int i;
 192
 193         /* Limit results by potentially reduced max rate */
 194         for (i = 0; i < len; i++) {
 195                 if (rates[len - i - 1] <= max_rate)
 196                         return len - i;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /* Get length of common rates array potentially limited by max_rate. */
 203 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 204                                           int max_rate)
 205 {
 206         return intel_dp_rate_limit_len(intel_dp->common_rates,
 207                                        intel_dp->num_common_rates, max_rate);
 208 }
 209
 210 /* Theoretical max between source and sink */
 211 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 212 {
 213         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 214 }
 215
 216 /* Theoretical max between source and sink */
 217 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 218 {
 219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 220         int source_max = intel_dig_port->max_lanes;
 221         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 222         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 223
 224         return min3(source_max, sink_max, fia_max);
 225 }
 226
 227 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 228 {
 229         return intel_dp->max_link_lane_count;
 230 }
 231
 232 int
 233 intel_dp_link_required(int pixel_clock, int bpp)
 234 {
 235         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 236         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 237 }
 238
 239 int
 240 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 241 {
 242         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 243          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 244          * is transmitted every LS_Clk per lane, there is no need to account for
 245          * the channel encoding that is done in the PHY layer here.
 246          */
 247
 248         return max_link_clock * max_lanes;
 249 }
 250
 251 static int
 252 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 253 {
 254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 255         struct intel_encoder *encoder = &intel_dig_port->base;
 256         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257         int max_dotclk = dev_priv->max_dotclk_freq;
 258         int ds_max_dotclk;
 259
 260         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 261
 262         if (type != DP_DS_PORT_TYPE_VGA)
 263                 return max_dotclk;
 264
 265         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 266                                                     intel_dp->downstream_ports);
 267
 268         if (ds_max_dotclk != 0)
 269                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 270
 271         return max_dotclk;
 272 }
 273
 274 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 275 {
 276         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 277         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 278         enum port port = dig_port->base.port;
 279
 280         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 281
 282         /* Low voltage SKUs are limited to max of 5.4G */
 283         if (voltage == VOLTAGE_INFO_0_85V)
 284                 return 540000;
 285
 286         /* For this SKU 8.1G is supported in all ports */
 287         if (IS_CNL_WITH_PORT_F(dev_priv))
 288                 return 810000;
 289
 290         /* For other SKUs, max rate on ports A and D is 5.4G */
 291         if (port == PORT_A || port == PORT_D)
 292                 return 540000;
 293
 294         return 810000;
 295 }
 296
 297 static int icl_max_source_rate(struct intel_dp *intel_dp)
 298 {
 299         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 300         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 301         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 302
 303         if (intel_phy_is_combo(dev_priv, phy) &&
 304             !IS_ELKHARTLAKE(dev_priv) &&
 305             !intel_dp_is_edp(intel_dp))
 306                 return 540000;
 307
 308         return 810000;
 309 }
 310
 311 static void
 312 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 313 {
 314         /* The values must be in increasing order */
 315         static const int cnl_rates[] = {
 316                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 317         };
 318         static const int bxt_rates[] = {
 319                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 320         };
 321         static const int skl_rates[] = {
 322                 162000, 216000, 270000, 324000, 432000, 540000
 323         };
 324         static const int hsw_rates[] = {
 325                 162000, 270000, 540000
 326         };
 327         static const int g4x_rates[] = {
 328                 162000, 270000
 329         };
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         struct intel_encoder *encoder = &dig_port->base;
 332         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 333         const int *source_rates;
 334         int size, max_rate = 0, vbt_max_rate;
 335
 336         /* This should only be done once */
 337         drm_WARN_ON(&dev_priv->drm,
 338                     intel_dp->source_rates || intel_dp->num_source_rates);
 339
 340         if (INTEL_GEN(dev_priv) >= 10) {
 341                 source_rates = cnl_rates;
 342                 size = ARRAY_SIZE(cnl_rates);
 343                 if (IS_GEN(dev_priv, 10))
 344                         max_rate = cnl_max_source_rate(intel_dp);
 345                 else
 346                         max_rate = icl_max_source_rate(intel_dp);
 347         } else if (IS_GEN9_LP(dev_priv)) {
 348                 source_rates = bxt_rates;
 349                 size = ARRAY_SIZE(bxt_rates);
 350         } else if (IS_GEN9_BC(dev_priv)) {
 351                 source_rates = skl_rates;
 352                 size = ARRAY_SIZE(skl_rates);
 353         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 354                    IS_BROADWELL(dev_priv)) {
 355                 source_rates = hsw_rates;
 356                 size = ARRAY_SIZE(hsw_rates);
 357         } else {
 358                 source_rates = g4x_rates;
 359                 size = ARRAY_SIZE(g4x_rates);
 360         }
 361
 362         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 363         if (max_rate && vbt_max_rate)
 364                 max_rate = min(max_rate, vbt_max_rate);
 365         else if (vbt_max_rate)
 366                 max_rate = vbt_max_rate;
 367
 368         if (max_rate)
 369                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 370
 371         intel_dp->source_rates = source_rates;
 372         intel_dp->num_source_rates = size;
 373 }
 374
 375 static int intersect_rates(const int *source_rates, int source_len,
 376                            const int *sink_rates, int sink_len,
 377                            int *common_rates)
 378 {
 379         int i = 0, j = 0, k = 0;
 380
 381         while (i < source_len && j < sink_len) {
 382                 if (source_rates[i] == sink_rates[j]) {
 383                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 384                                 return k;
 385                         common_rates[k] = source_rates[i];
 386                         ++k;
 387                         ++i;
 388                         ++j;
 389                 } else if (source_rates[i] < sink_rates[j]) {
 390                         ++i;
 391                 } else {
 392                         ++j;
 393                 }
 394         }
 395         return k;
 396 }
 397
 398 /* return index of rate in rates array, or -1 if not found */
 399 static int intel_dp_rate_index(const int *rates, int len, int rate)
 400 {
 401         int i;
 402
 403         for (i = 0; i < len; i++)
 404                 if (rate == rates[i])
 405                         return i;
 406
 407         return -1;
 408 }
 409
 410 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 411 {
 412         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 413
 414         drm_WARN_ON(&i915->drm,
 415                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 416
 417         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 418                                                      intel_dp->num_source_rates,
 419                                                      intel_dp->sink_rates,
 420                                                      intel_dp->num_sink_rates,
 421                                                      intel_dp->common_rates);
 422
 423         /* Paranoia, there should always be something in common. */
 424         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 425                 intel_dp->common_rates[0] = 162000;
 426                 intel_dp->num_common_rates = 1;
 427         }
 428 }
 429
 430 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 431                                        u8 lane_count)
 432 {
 433         /*
 434          * FIXME: we need to synchronize the current link parameters with
 435          * hardware readout. Currently fast link training doesn't work on
 436          * boot-up.
 437          */
 438         if (link_rate == 0 ||
 439             link_rate > intel_dp->max_link_rate)
 440                 return false;
 441
 442         if (lane_count == 0 ||
 443             lane_count > intel_dp_max_lane_count(intel_dp))
 444                 return false;
 445
 446         return true;
 447 }
 448
 449 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 450                                                      int link_rate,
 451                                                      u8 lane_count)
 452 {
 453         const struct drm_display_mode *fixed_mode =
 454                 intel_dp->attached_connector->panel.fixed_mode;
 455         int mode_rate, max_rate;
 456
 457         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 458         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 459         if (mode_rate > max_rate)
 460                 return false;
 461
 462         return true;
 463 }
 464
 465 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 466                                             int link_rate, u8 lane_count)
 467 {
 468         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 469         int index;
 470
 471         index = intel_dp_rate_index(intel_dp->common_rates,
 472                                     intel_dp->num_common_rates,
 473                                     link_rate);
 474         if (index > 0) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp->common_rates[index - 1],
 478                                                               lane_count)) {
 479                         drm_dbg_kms(&i915->drm,
 480                                     "Retrying Link training for eDP with same parameters\n");
 481                         return 0;
 482                 }
 483                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 484                 intel_dp->max_link_lane_count = lane_count;
 485         } else if (lane_count > 1) {
 486                 if (intel_dp_is_edp(intel_dp) &&
 487                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 488                                                               intel_dp_max_common_rate(intel_dp),
 489                                                               lane_count >> 1)) {
 490                         drm_dbg_kms(&i915->drm,
 491                                     "Retrying Link training for eDP with same parameters\n");
 492                         return 0;
 493                 }
 494                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 495                 intel_dp->max_link_lane_count = lane_count >> 1;
 496         } else {
 497                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 498                 return -1;
 499         }
 500
 501         return 0;
 502 }
 503
 504 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 505 {
 506         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 507                        DP_DSC_FEC_OVERHEAD_FACTOR);
 508 }
 509
 510 static int
 511 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 512 {
 513         if (INTEL_GEN(i915) >= 11)
 514                 return 7680 * 8;
 515         else
 516                 return 6144 * 8;
 517 }
 518
 519 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 520                                        u32 link_clock, u32 lane_count,
 521                                        u32 mode_clock, u32 mode_hdisplay)
 522 {
 523         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 524         int i;
 525
 526         /*
 527          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 528          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 529          * for SST -> TimeSlotsPerMTP is 1,
 530          * for MST -> TimeSlotsPerMTP has to be calculated
 531          */
 532         bits_per_pixel = (link_clock * lane_count * 8) /
 533                          intel_dp_mode_to_fec_clock(mode_clock);
 534         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 535
 536         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 537         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 538                 mode_hdisplay;
 539         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 540                     max_bpp_small_joiner_ram);
 541
 542         /*
 543          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 544          * check, output bpp from small joiner RAM check)
 545          */
 546         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 547
 548         /* Error out if the max bpp is less than smallest allowed valid bpp */
 549         if (bits_per_pixel < valid_dsc_bpp[0]) {
 550                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 551                             bits_per_pixel, valid_dsc_bpp[0]);
 552                 return 0;
 553         }
 554
 555         /* Find the nearest match in the array of known BPPs from VESA */
 556         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 557                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 558                         break;
 559         }
 560         bits_per_pixel = valid_dsc_bpp[i];
 561
 562         /*
 563          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 564          * fractional part is 0
 565          */
 566         return bits_per_pixel << 4;
 567 }
 568
 569 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 570                                        int mode_clock, int mode_hdisplay)
 571 {
 572         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 573         u8 min_slice_count, i;
 574         int max_slice_width;
 575
 576         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 577                 min_slice_count = DIV_ROUND_UP(mode_clock,
 578                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 579         else
 580                 min_slice_count = DIV_ROUND_UP(mode_clock,
 581                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 582
 583         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 584         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 585                 drm_dbg_kms(&i915->drm,
 586                             "Unsupported slice width %d by DP DSC Sink device\n",
 587                             max_slice_width);
 588                 return 0;
 589         }
 590         /* Also take into account max slice width */
 591         min_slice_count = min_t(u8, min_slice_count,
 592                                 DIV_ROUND_UP(mode_hdisplay,
 593                                              max_slice_width));
 594
 595         /* Find the closest match to the valid slice count values */
 596         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 597                 if (valid_dsc_slicecount[i] >
 598                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 599                                                     false))
 600                         break;
 601                 if (min_slice_count  <= valid_dsc_slicecount[i])
 602                         return valid_dsc_slicecount[i];
 603         }
 604
 605         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 606                     min_slice_count);
 607         return 0;
 608 }
 609
 610 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 611                                   int hdisplay)
 612 {
 613         /*
 614          * Older platforms don't like hdisplay==4096 with DP.
 615          *
 616          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 617          * and frame counter increment), but we don't get vblank interrupts,
 618          * and the pipe underruns immediately. The link also doesn't seem
 619          * to get trained properly.
 620          *
 621          * On CHV the vblank interrupts don't seem to disappear but
 622          * otherwise the symptoms are similar.
 623          *
 624          * TODO: confirm the behaviour on HSW+
 625          */
 626         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 627 }
 628
 629 static enum drm_mode_status
 630 intel_dp_mode_valid(struct drm_connector *connector,
 631                     struct drm_display_mode *mode)
 632 {
 633         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 634         struct intel_connector *intel_connector = to_intel_connector(connector);
 635         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 636         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 637         int target_clock = mode->clock;
 638         int max_rate, mode_rate, max_lanes, max_link_clock;
 639         int max_dotclk;
 640         u16 dsc_max_output_bpp = 0;
 641         u8 dsc_slice_count = 0;
 642
 643         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 644                 return MODE_NO_DBLESCAN;
 645
 646         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 647
 648         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 649                 if (mode->hdisplay > fixed_mode->hdisplay)
 650                         return MODE_PANEL;
 651
 652                 if (mode->vdisplay > fixed_mode->vdisplay)
 653                         return MODE_PANEL;
 654
 655                 target_clock = fixed_mode->clock;
 656         }
 657
 658         max_link_clock = intel_dp_max_link_rate(intel_dp);
 659         max_lanes = intel_dp_max_lane_count(intel_dp);
 660
 661         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 662         mode_rate = intel_dp_link_required(target_clock, 18);
 663
 664         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 665                 return MODE_H_ILLEGAL;
 666
 667         /*
 668          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 669          * integer value since we support only integer values of bpp.
 670          */
 671         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 672             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 673                 if (intel_dp_is_edp(intel_dp)) {
 674                         dsc_max_output_bpp =
 675                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 676                         dsc_slice_count =
 677                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 678                                                                 true);
 679                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 680                         dsc_max_output_bpp =
 681                                 intel_dp_dsc_get_output_bpp(dev_priv,
 682                                                             max_link_clock,
 683                                                             max_lanes,
 684                                                             target_clock,
 685                                                             mode->hdisplay) >> 4;
 686                         dsc_slice_count =
 687                                 intel_dp_dsc_get_slice_count(intel_dp,
 688                                                              target_clock,
 689                                                              mode->hdisplay);
 690                 }
 691         }
 692
 693         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 694             target_clock > max_dotclk)
 695                 return MODE_CLOCK_HIGH;
 696
 697         if (mode->clock < 10000)
 698                 return MODE_CLOCK_LOW;
 699
 700         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 701                 return MODE_H_ILLEGAL;
 702
 703         return intel_mode_valid_max_plane_size(dev_priv, mode);
 704 }
 705
 706 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 707 {
 708         int i;
 709         u32 v = 0;
 710
 711         if (src_bytes > 4)
 712                 src_bytes = 4;
 713         for (i = 0; i < src_bytes; i++)
 714                 v |= ((u32)src[i]) << ((3 - i) * 8);
 715         return v;
 716 }
 717
 718 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 719 {
 720         int i;
 721         if (dst_bytes > 4)
 722                 dst_bytes = 4;
 723         for (i = 0; i < dst_bytes; i++)
 724                 dst[i] = src >> ((3-i) * 8);
 725 }
 726
 727 static void
 728 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 729 static void
 730 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 731                                               bool force_disable_vdd);
 732 static void
 733 intel_dp_pps_init(struct intel_dp *intel_dp);
 734
 735 static intel_wakeref_t
 736 pps_lock(struct intel_dp *intel_dp)
 737 {
 738         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 739         intel_wakeref_t wakeref;
 740
 741         /*
 742          * See intel_power_sequencer_reset() why we need
 743          * a power domain reference here.
 744          */
 745         wakeref = intel_display_power_get(dev_priv,
 746                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 747
 748         mutex_lock(&dev_priv->pps_mutex);
 749
 750         return wakeref;
 751 }
 752
 753 static intel_wakeref_t
 754 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 755 {
 756         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 757
 758         mutex_unlock(&dev_priv->pps_mutex);
 759         intel_display_power_put(dev_priv,
 760                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 761                                 wakeref);
 762         return 0;
 763 }
 764
 765 #define with_pps_lock(dp, wf) \
 766         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 767
 768 static void
 769 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 770 {
 771         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 772         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 773         enum pipe pipe = intel_dp->pps_pipe;
 774         bool pll_enabled, release_cl_override = false;
 775         enum dpio_phy phy = DPIO_PHY(pipe);
 776         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 777         u32 DP;
 778
 779         if (drm_WARN(&dev_priv->drm,
 780                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 781                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 782                      pipe_name(pipe), intel_dig_port->base.base.base.id,
 783                      intel_dig_port->base.base.name))
 784                 return;
 785
 786         drm_dbg_kms(&dev_priv->drm,
 787                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 788                     pipe_name(pipe), intel_dig_port->base.base.base.id,
 789                     intel_dig_port->base.base.name);
 790
 791         /* Preserve the BIOS-computed detected bit. This is
 792          * supposed to be read-only.
 793          */
 794         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 795         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 796         DP |= DP_PORT_WIDTH(1);
 797         DP |= DP_LINK_TRAIN_PAT_1;
 798
 799         if (IS_CHERRYVIEW(dev_priv))
 800                 DP |= DP_PIPE_SEL_CHV(pipe);
 801         else
 802                 DP |= DP_PIPE_SEL(pipe);
 803
 804         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 805
 806         /*
 807          * The DPLL for the pipe must be enabled for this to work.
 808          * So enable temporarily it if it's not already enabled.
 809          */
 810         if (!pll_enabled) {
 811                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 812                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 813
 814                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 815                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 816                         drm_err(&dev_priv->drm,
 817                                 "Failed to force on pll for pipe %c!\n",
 818                                 pipe_name(pipe));
 819                         return;
 820                 }
 821         }
 822
 823         /*
 824          * Similar magic as in intel_dp_enable_port().
 825          * We _must_ do this port enable + disable trick
 826          * to make this power sequencer lock onto the port.
 827          * Otherwise even VDD force bit won't work.
 828          */
 829         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 830         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 831
 832         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 833         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 834
 835         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 836         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 837
 838         if (!pll_enabled) {
 839                 vlv_force_pll_off(dev_priv, pipe);
 840
 841                 if (release_cl_override)
 842                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 843         }
 844 }
 845
 846 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 847 {
 848         struct intel_encoder *encoder;
 849         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 850
 851         /*
 852          * We don't have power sequencer currently.
 853          * Pick one that's not used by other ports.
 854          */
 855         for_each_intel_dp(&dev_priv->drm, encoder) {
 856                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 857
 858                 if (encoder->type == INTEL_OUTPUT_EDP) {
 859                         drm_WARN_ON(&dev_priv->drm,
 860                                     intel_dp->active_pipe != INVALID_PIPE &&
 861                                     intel_dp->active_pipe !=
 862                                     intel_dp->pps_pipe);
 863
 864                         if (intel_dp->pps_pipe != INVALID_PIPE)
 865                                 pipes &= ~(1 << intel_dp->pps_pipe);
 866                 } else {
 867                         drm_WARN_ON(&dev_priv->drm,
 868                                     intel_dp->pps_pipe != INVALID_PIPE);
 869
 870                         if (intel_dp->active_pipe != INVALID_PIPE)
 871                                 pipes &= ~(1 << intel_dp->active_pipe);
 872                 }
 873         }
 874
 875         if (pipes == 0)
 876                 return INVALID_PIPE;
 877
 878         return ffs(pipes) - 1;
 879 }
 880
 881 static enum pipe
 882 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 883 {
 884         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 885         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 886         enum pipe pipe;
 887
 888         lockdep_assert_held(&dev_priv->pps_mutex);
 889
 890         /* We should never land here with regular DP ports */
 891         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 892
 893         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
 894                     intel_dp->active_pipe != intel_dp->pps_pipe);
 895
 896         if (intel_dp->pps_pipe != INVALID_PIPE)
 897                 return intel_dp->pps_pipe;
 898
 899         pipe = vlv_find_free_pps(dev_priv);
 900
 901         /*
 902          * Didn't find one. This should not happen since there
 903          * are two power sequencers and up to two eDP ports.
 904          */
 905         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 906                 pipe = PIPE_A;
 907
 908         vlv_steal_power_sequencer(dev_priv, pipe);
 909         intel_dp->pps_pipe = pipe;
 910
 911         drm_dbg_kms(&dev_priv->drm,
 912                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 913                     pipe_name(intel_dp->pps_pipe),
 914                     intel_dig_port->base.base.base.id,
 915                     intel_dig_port->base.base.name);
 916
 917         /* init power sequencer on this pipe and port */
 918         intel_dp_init_panel_power_sequencer(intel_dp);
 919         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 920
 921         /*
 922          * Even vdd force doesn't work until we've made
 923          * the power sequencer lock in on the port.
 924          */
 925         vlv_power_sequencer_kick(intel_dp);
 926
 927         return intel_dp->pps_pipe;
 928 }
 929
 930 static int
 931 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 932 {
 933         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 934         int backlight_controller = dev_priv->vbt.backlight.controller;
 935
 936         lockdep_assert_held(&dev_priv->pps_mutex);
 937
 938         /* We should never land here with regular DP ports */
 939         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 940
 941         if (!intel_dp->pps_reset)
 942                 return backlight_controller;
 943
 944         intel_dp->pps_reset = false;
 945
 946         /*
 947          * Only the HW needs to be reprogrammed, the SW state is fixed and
 948          * has been setup during connector init.
 949          */
 950         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 951
 952         return backlight_controller;
 953 }
 954
 955 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 956                                enum pipe pipe);
 957
 958 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 959                                enum pipe pipe)
 960 {
 961         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 962 }
 963
 964 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 965                                 enum pipe pipe)
 966 {
 967         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 968 }
 969
 970 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 971                          enum pipe pipe)
 972 {
 973         return true;
 974 }
 975
 976 static enum pipe
 977 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 978                      enum port port,
 979                      vlv_pipe_check pipe_check)
 980 {
 981         enum pipe pipe;
 982
 983         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 984                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 985                         PANEL_PORT_SELECT_MASK;
 986
 987                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 988                         continue;
 989
 990                 if (!pipe_check(dev_priv, pipe))
 991                         continue;
 992
 993                 return pipe;
 994         }
 995
 996         return INVALID_PIPE;
 997 }
 998
 999 static void
1000 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1001 {
1002         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1003         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1004         enum port port = intel_dig_port->base.port;
1005
1006         lockdep_assert_held(&dev_priv->pps_mutex);
1007
1008         /* try to find a pipe with this port selected */
1009         /* first pick one where the panel is on */
1010         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1011                                                   vlv_pipe_has_pp_on);
1012         /* didn't find one? pick one where vdd is on */
1013         if (intel_dp->pps_pipe == INVALID_PIPE)
1014                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1015                                                           vlv_pipe_has_vdd_on);
1016         /* didn't find one? pick one with just the correct port */
1017         if (intel_dp->pps_pipe == INVALID_PIPE)
1018                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1019                                                           vlv_pipe_any);
1020
1021         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1022         if (intel_dp->pps_pipe == INVALID_PIPE) {
1023                 drm_dbg_kms(&dev_priv->drm,
1024                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1025                             intel_dig_port->base.base.base.id,
1026                             intel_dig_port->base.base.name);
1027                 return;
1028         }
1029
1030         drm_dbg_kms(&dev_priv->drm,
1031                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1032                     intel_dig_port->base.base.base.id,
1033                     intel_dig_port->base.base.name,
1034                     pipe_name(intel_dp->pps_pipe));
1035
1036         intel_dp_init_panel_power_sequencer(intel_dp);
1037         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1038 }
1039
1040 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1041 {
1042         struct intel_encoder *encoder;
1043
1044         if (drm_WARN_ON(&dev_priv->drm,
1045                         !(IS_VALLEYVIEW(dev_priv) ||
1046                           IS_CHERRYVIEW(dev_priv) ||
1047                           IS_GEN9_LP(dev_priv))))
1048                 return;
1049
1050         /*
1051          * We can't grab pps_mutex here due to deadlock with power_domain
1052          * mutex when power_domain functions are called while holding pps_mutex.
1053          * That also means that in order to use pps_pipe the code needs to
1054          * hold both a power domain reference and pps_mutex, and the power domain
1055          * reference get/put must be done while _not_ holding pps_mutex.
1056          * pps_{lock,unlock}() do these steps in the correct order, so one
1057          * should use them always.
1058          */
1059
1060         for_each_intel_dp(&dev_priv->drm, encoder) {
1061                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1062
1063                 drm_WARN_ON(&dev_priv->drm,
1064                             intel_dp->active_pipe != INVALID_PIPE);
1065
1066                 if (encoder->type != INTEL_OUTPUT_EDP)
1067                         continue;
1068
1069                 if (IS_GEN9_LP(dev_priv))
1070                         intel_dp->pps_reset = true;
1071                 else
1072                         intel_dp->pps_pipe = INVALID_PIPE;
1073         }
1074 }
1075
1076 struct pps_registers {
1077         i915_reg_t pp_ctrl;
1078         i915_reg_t pp_stat;
1079         i915_reg_t pp_on;
1080         i915_reg_t pp_off;
1081         i915_reg_t pp_div;
1082 };
1083
1084 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1085                                     struct pps_registers *regs)
1086 {
1087         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1088         int pps_idx = 0;
1089
1090         memset(regs, 0, sizeof(*regs));
1091
1092         if (IS_GEN9_LP(dev_priv))
1093                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1094         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1095                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1096
1097         regs->pp_ctrl = PP_CONTROL(pps_idx);
1098         regs->pp_stat = PP_STATUS(pps_idx);
1099         regs->pp_on = PP_ON_DELAYS(pps_idx);
1100         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1101
1102         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1103         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1104                 regs->pp_div = INVALID_MMIO_REG;
1105         else
1106                 regs->pp_div = PP_DIVISOR(pps_idx);
1107 }
1108
1109 static i915_reg_t
1110 _pp_ctrl_reg(struct intel_dp *intel_dp)
1111 {
1112         struct pps_registers regs;
1113
1114         intel_pps_get_registers(intel_dp, &regs);
1115
1116         return regs.pp_ctrl;
1117 }
1118
1119 static i915_reg_t
1120 _pp_stat_reg(struct intel_dp *intel_dp)
1121 {
1122         struct pps_registers regs;
1123
1124         intel_pps_get_registers(intel_dp, &regs);
1125
1126         return regs.pp_stat;
1127 }
1128
1129 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1130    This function only applicable when panel PM state is not to be tracked */
1131 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1132                               void *unused)
1133 {
1134         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1135                                                  edp_notifier);
1136         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1137         intel_wakeref_t wakeref;
1138
1139         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1140                 return 0;
1141
1142         with_pps_lock(intel_dp, wakeref) {
1143                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1144                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1145                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1146                         u32 pp_div;
1147
1148                         pp_ctrl_reg = PP_CONTROL(pipe);
1149                         pp_div_reg  = PP_DIVISOR(pipe);
1150                         pp_div = intel_de_read(dev_priv, pp_div_reg);
1151                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1152
1153                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1154                         intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1155                         intel_de_write(dev_priv, pp_ctrl_reg,
1156                                        PANEL_UNLOCK_REGS);
1157                         msleep(intel_dp->panel_power_cycle_delay);
1158                 }
1159         }
1160
1161         return 0;
1162 }
1163
1164 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1165 {
1166         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1167
1168         lockdep_assert_held(&dev_priv->pps_mutex);
1169
1170         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1171             intel_dp->pps_pipe == INVALID_PIPE)
1172                 return false;
1173
1174         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1175 }
1176
1177 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1178 {
1179         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1180
1181         lockdep_assert_held(&dev_priv->pps_mutex);
1182
1183         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1184             intel_dp->pps_pipe == INVALID_PIPE)
1185                 return false;
1186
1187         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1188 }
1189
1190 static void
1191 intel_dp_check_edp(struct intel_dp *intel_dp)
1192 {
1193         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1194
1195         if (!intel_dp_is_edp(intel_dp))
1196                 return;
1197
1198         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1199                 drm_WARN(&dev_priv->drm, 1,
1200                          "eDP powered off while attempting aux channel communication.\n");
1201                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1202                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1203                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1204         }
1205 }
1206
1207 static u32
1208 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1209 {
1210         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1211         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1212         const unsigned int timeout_ms = 10;
1213         u32 status;
1214         bool done;
1215
1216 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1217         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1218                                   msecs_to_jiffies_timeout(timeout_ms));
1219
1220         /* just trace the final value */
1221         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1222
1223         if (!done)
1224                 drm_err(&i915->drm,
1225                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1226                         intel_dp->aux.name, timeout_ms, status);
1227 #undef C
1228
1229         return status;
1230 }
1231
1232 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1233 {
1234         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1235
1236         if (index)
1237                 return 0;
1238
1239         /*
1240          * The clock divider is based off the hrawclk, and would like to run at
1241          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1242          */
1243         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1244 }
1245
1246 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1247 {
1248         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1249         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1250         u32 freq;
1251
1252         if (index)
1253                 return 0;
1254
1255         /*
1256          * The clock divider is based off the cdclk or PCH rawclk, and would
1257          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1258          * divide by 2000 and use that
1259          */
1260         if (dig_port->aux_ch == AUX_CH_A)
1261                 freq = dev_priv->cdclk.hw.cdclk;
1262         else
1263                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1264         return DIV_ROUND_CLOSEST(freq, 2000);
1265 }
1266
1267 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1268 {
1269         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1271
1272         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1273                 /* Workaround for non-ULT HSW */
1274                 switch (index) {
1275                 case 0: return 63;
1276                 case 1: return 72;
1277                 default: return 0;
1278                 }
1279         }
1280
1281         return ilk_get_aux_clock_divider(intel_dp, index);
1282 }
1283
1284 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1285 {
1286         /*
1287          * SKL doesn't need us to program the AUX clock divider (Hardware will
1288          * derive the clock from CDCLK automatically). We still implement the
1289          * get_aux_clock_divider vfunc to plug-in into the existing code.
1290          */
1291         return index ? 0 : 1;
1292 }
1293
1294 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1295                                 int send_bytes,
1296                                 u32 aux_clock_divider)
1297 {
1298         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1299         struct drm_i915_private *dev_priv =
1300                         to_i915(intel_dig_port->base.base.dev);
1301         u32 precharge, timeout;
1302
1303         if (IS_GEN(dev_priv, 6))
1304                 precharge = 3;
1305         else
1306                 precharge = 5;
1307
1308         if (IS_BROADWELL(dev_priv))
1309                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1310         else
1311                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1312
1313         return DP_AUX_CH_CTL_SEND_BUSY |
1314                DP_AUX_CH_CTL_DONE |
1315                DP_AUX_CH_CTL_INTERRUPT |
1316                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1317                timeout |
1318                DP_AUX_CH_CTL_RECEIVE_ERROR |
1319                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1320                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1321                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1322 }
1323
1324 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1325                                 int send_bytes,
1326                                 u32 unused)
1327 {
1328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1329         struct drm_i915_private *i915 =
1330                         to_i915(intel_dig_port->base.base.dev);
1331         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1332         u32 ret;
1333
1334         ret = DP_AUX_CH_CTL_SEND_BUSY |
1335               DP_AUX_CH_CTL_DONE |
1336               DP_AUX_CH_CTL_INTERRUPT |
1337               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1338               DP_AUX_CH_CTL_TIME_OUT_MAX |
1339               DP_AUX_CH_CTL_RECEIVE_ERROR |
1340               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1341               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1342               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1343
1344         if (intel_phy_is_tc(i915, phy) &&
1345             intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1346                 ret |= DP_AUX_CH_CTL_TBT_IO;
1347
1348         return ret;
1349 }
1350
1351 static int
1352 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1353                   const u8 *send, int send_bytes,
1354                   u8 *recv, int recv_size,
1355                   u32 aux_send_ctl_flags)
1356 {
1357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358         struct drm_i915_private *i915 =
1359                         to_i915(intel_dig_port->base.base.dev);
1360         struct intel_uncore *uncore = &i915->uncore;
1361         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1362         bool is_tc_port = intel_phy_is_tc(i915, phy);
1363         i915_reg_t ch_ctl, ch_data[5];
1364         u32 aux_clock_divider;
1365         enum intel_display_power_domain aux_domain;
1366         intel_wakeref_t aux_wakeref;
1367         intel_wakeref_t pps_wakeref;
1368         int i, ret, recv_bytes;
1369         int try, clock = 0;
1370         u32 status;
1371         bool vdd;
1372
1373         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1374         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1375                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1376
1377         if (is_tc_port)
1378                 intel_tc_port_lock(intel_dig_port);
1379
1380         aux_domain = intel_aux_power_domain(intel_dig_port);
1381
1382         aux_wakeref = intel_display_power_get(i915, aux_domain);
1383         pps_wakeref = pps_lock(intel_dp);
1384
1385         /*
1386          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1387          * In such cases we want to leave VDD enabled and it's up to upper layers
1388          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1389          * ourselves.
1390          */
1391         vdd = edp_panel_vdd_on(intel_dp);
1392
1393         /* dp aux is extremely sensitive to irq latency, hence request the
1394          * lowest possible wakeup latency and so prevent the cpu from going into
1395          * deep sleep states.
1396          */
1397         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1398
1399         intel_dp_check_edp(intel_dp);
1400
1401         /* Try to wait for any previous AUX channel activity */
1402         for (try = 0; try < 3; try++) {
1403                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1404                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1405                         break;
1406                 msleep(1);
1407         }
1408         /* just trace the final value */
1409         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1410
1411         if (try == 3) {
1412                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1413
1414                 if (status != intel_dp->aux_busy_last_status) {
1415                         drm_WARN(&i915->drm, 1,
1416                                  "%s: not started (status 0x%08x)\n",
1417                                  intel_dp->aux.name, status);
1418                         intel_dp->aux_busy_last_status = status;
1419                 }
1420
1421                 ret = -EBUSY;
1422                 goto out;
1423         }
1424
1425         /* Only 5 data registers! */
1426         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1427                 ret = -E2BIG;
1428                 goto out;
1429         }
1430
1431         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1432                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1433                                                           send_bytes,
1434                                                           aux_clock_divider);
1435
1436                 send_ctl |= aux_send_ctl_flags;
1437
1438                 /* Must try at least 3 times according to DP spec */
1439                 for (try = 0; try < 5; try++) {
1440                         /* Load the send data into the aux channel data registers */
1441                         for (i = 0; i < send_bytes; i += 4)
1442                                 intel_uncore_write(uncore,
1443                                                    ch_data[i >> 2],
1444                                                    intel_dp_pack_aux(send + i,
1445                                                                      send_bytes - i));
1446
1447                         /* Send the command and wait for it to complete */
1448                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1449
1450                         status = intel_dp_aux_wait_done(intel_dp);
1451
1452                         /* Clear done status and any errors */
1453                         intel_uncore_write(uncore,
1454                                            ch_ctl,
1455                                            status |
1456                                            DP_AUX_CH_CTL_DONE |
1457                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1458                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1459
1460                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1461                          *   400us delay required for errors and timeouts
1462                          *   Timeout errors from the HW already meet this
1463                          *   requirement so skip to next iteration
1464                          */
1465                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1466                                 continue;
1467
1468                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1469                                 usleep_range(400, 500);
1470                                 continue;
1471                         }
1472                         if (status & DP_AUX_CH_CTL_DONE)
1473                                 goto done;
1474                 }
1475         }
1476
1477         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1478                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1479                         intel_dp->aux.name, status);
1480                 ret = -EBUSY;
1481                 goto out;
1482         }
1483
1484 done:
1485         /* Check for timeout or receive error.
1486          * Timeouts occur when the sink is not connected
1487          */
1488         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1489                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1490                         intel_dp->aux.name, status);
1491                 ret = -EIO;
1492                 goto out;
1493         }
1494
1495         /* Timeouts occur when the device isn't connected, so they're
1496          * "normal" -- don't fill the kernel log with these */
1497         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1498                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1499                             intel_dp->aux.name, status);
1500                 ret = -ETIMEDOUT;
1501                 goto out;
1502         }
1503
1504         /* Unload any bytes sent back from the other side */
1505         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1506                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1507
1508         /*
1509          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1510          * We have no idea of what happened so we return -EBUSY so
1511          * drm layer takes care for the necessary retries.
1512          */
1513         if (recv_bytes == 0 || recv_bytes > 20) {
1514                 drm_dbg_kms(&i915->drm,
1515                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1516                             intel_dp->aux.name, recv_bytes);
1517                 ret = -EBUSY;
1518                 goto out;
1519         }
1520
1521         if (recv_bytes > recv_size)
1522                 recv_bytes = recv_size;
1523
1524         for (i = 0; i < recv_bytes; i += 4)
1525                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1526                                     recv + i, recv_bytes - i);
1527
1528         ret = recv_bytes;
1529 out:
1530         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1531
1532         if (vdd)
1533                 edp_panel_vdd_off(intel_dp, false);
1534
1535         pps_unlock(intel_dp, pps_wakeref);
1536         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1537
1538         if (is_tc_port)
1539                 intel_tc_port_unlock(intel_dig_port);
1540
1541         return ret;
1542 }
1543
1544 #define BARE_ADDRESS_SIZE       3
1545 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1546
1547 static void
1548 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1549                     const struct drm_dp_aux_msg *msg)
1550 {
1551         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1552         txbuf[1] = (msg->address >> 8) & 0xff;
1553         txbuf[2] = msg->address & 0xff;
1554         txbuf[3] = msg->size - 1;
1555 }
1556
1557 static ssize_t
1558 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1559 {
1560         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1561         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1562         u8 txbuf[20], rxbuf[20];
1563         size_t txsize, rxsize;
1564         int ret;
1565
1566         intel_dp_aux_header(txbuf, msg);
1567
1568         switch (msg->request & ~DP_AUX_I2C_MOT) {
1569         case DP_AUX_NATIVE_WRITE:
1570         case DP_AUX_I2C_WRITE:
1571         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1572                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1573                 rxsize = 2; /* 0 or 1 data bytes */
1574
1575                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1576                         return -E2BIG;
1577
1578                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1579
1580                 if (msg->buffer)
1581                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1582
1583                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1584                                         rxbuf, rxsize, 0);
1585                 if (ret > 0) {
1586                         msg->reply = rxbuf[0] >> 4;
1587
1588                         if (ret > 1) {
1589                                 /* Number of bytes written in a short write. */
1590                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1591                         } else {
1592                                 /* Return payload size. */
1593                                 ret = msg->size;
1594                         }
1595                 }
1596                 break;
1597
1598         case DP_AUX_NATIVE_READ:
1599         case DP_AUX_I2C_READ:
1600                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1601                 rxsize = msg->size + 1;
1602
1603                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1604                         return -E2BIG;
1605
1606                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1607                                         rxbuf, rxsize, 0);
1608                 if (ret > 0) {
1609                         msg->reply = rxbuf[0] >> 4;
1610                         /*
1611                          * Assume happy day, and copy the data. The caller is
1612                          * expected to check msg->reply before touching it.
1613                          *
1614                          * Return payload size.
1615                          */
1616                         ret--;
1617                         memcpy(msg->buffer, rxbuf + 1, ret);
1618                 }
1619                 break;
1620
1621         default:
1622                 ret = -EINVAL;
1623                 break;
1624         }
1625
1626         return ret;
1627 }
1628
1629
1630 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1631 {
1632         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1633         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1634         enum aux_ch aux_ch = dig_port->aux_ch;
1635
1636         switch (aux_ch) {
1637         case AUX_CH_B:
1638         case AUX_CH_C:
1639         case AUX_CH_D:
1640                 return DP_AUX_CH_CTL(aux_ch);
1641         default:
1642                 MISSING_CASE(aux_ch);
1643                 return DP_AUX_CH_CTL(AUX_CH_B);
1644         }
1645 }
1646
1647 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1648 {
1649         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1650         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1651         enum aux_ch aux_ch = dig_port->aux_ch;
1652
1653         switch (aux_ch) {
1654         case AUX_CH_B:
1655         case AUX_CH_C:
1656         case AUX_CH_D:
1657                 return DP_AUX_CH_DATA(aux_ch, index);
1658         default:
1659                 MISSING_CASE(aux_ch);
1660                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1661         }
1662 }
1663
1664 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1665 {
1666         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1667         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1668         enum aux_ch aux_ch = dig_port->aux_ch;
1669
1670         switch (aux_ch) {
1671         case AUX_CH_A:
1672                 return DP_AUX_CH_CTL(aux_ch);
1673         case AUX_CH_B:
1674         case AUX_CH_C:
1675         case AUX_CH_D:
1676                 return PCH_DP_AUX_CH_CTL(aux_ch);
1677         default:
1678                 MISSING_CASE(aux_ch);
1679                 return DP_AUX_CH_CTL(AUX_CH_A);
1680         }
1681 }
1682
1683 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1684 {
1685         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1686         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687         enum aux_ch aux_ch = dig_port->aux_ch;
1688
1689         switch (aux_ch) {
1690         case AUX_CH_A:
1691                 return DP_AUX_CH_DATA(aux_ch, index);
1692         case AUX_CH_B:
1693         case AUX_CH_C:
1694         case AUX_CH_D:
1695                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1696         default:
1697                 MISSING_CASE(aux_ch);
1698                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1699         }
1700 }
1701
1702 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1703 {
1704         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1705         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1706         enum aux_ch aux_ch = dig_port->aux_ch;
1707
1708         switch (aux_ch) {
1709         case AUX_CH_A:
1710         case AUX_CH_B:
1711         case AUX_CH_C:
1712         case AUX_CH_D:
1713         case AUX_CH_E:
1714         case AUX_CH_F:
1715         case AUX_CH_G:
1716                 return DP_AUX_CH_CTL(aux_ch);
1717         default:
1718                 MISSING_CASE(aux_ch);
1719                 return DP_AUX_CH_CTL(AUX_CH_A);
1720         }
1721 }
1722
1723 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1724 {
1725         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1726         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1727         enum aux_ch aux_ch = dig_port->aux_ch;
1728
1729         switch (aux_ch) {
1730         case AUX_CH_A:
1731         case AUX_CH_B:
1732         case AUX_CH_C:
1733         case AUX_CH_D:
1734         case AUX_CH_E:
1735         case AUX_CH_F:
1736         case AUX_CH_G:
1737                 return DP_AUX_CH_DATA(aux_ch, index);
1738         default:
1739                 MISSING_CASE(aux_ch);
1740                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1741         }
1742 }
1743
1744 static void
1745 intel_dp_aux_fini(struct intel_dp *intel_dp)
1746 {
1747         kfree(intel_dp->aux.name);
1748 }
1749
1750 static void
1751 intel_dp_aux_init(struct intel_dp *intel_dp)
1752 {
1753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1754         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1755         struct intel_encoder *encoder = &dig_port->base;
1756
1757         if (INTEL_GEN(dev_priv) >= 9) {
1758                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1759                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1760         } else if (HAS_PCH_SPLIT(dev_priv)) {
1761                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1762                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1763         } else {
1764                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1765                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1766         }
1767
1768         if (INTEL_GEN(dev_priv) >= 9)
1769                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1770         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1771                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1772         else if (HAS_PCH_SPLIT(dev_priv))
1773                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1774         else
1775                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1776
1777         if (INTEL_GEN(dev_priv) >= 9)
1778                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1779         else
1780                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1781
1782         drm_dp_aux_init(&intel_dp->aux);
1783
1784         /* Failure to allocate our preferred name is not critical */
1785         intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1786                                        aux_ch_name(dig_port->aux_ch),
1787                                        port_name(encoder->port));
1788         intel_dp->aux.transfer = intel_dp_aux_transfer;
1789 }
1790
1791 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1792 {
1793         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1794
1795         return max_rate >= 540000;
1796 }
1797
1798 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1799 {
1800         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1801
1802         return max_rate >= 810000;
1803 }
1804
1805 static void
1806 intel_dp_set_clock(struct intel_encoder *encoder,
1807                    struct intel_crtc_state *pipe_config)
1808 {
1809         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1810         const struct dp_link_dpll *divisor = NULL;
1811         int i, count = 0;
1812
1813         if (IS_G4X(dev_priv)) {
1814                 divisor = g4x_dpll;
1815                 count = ARRAY_SIZE(g4x_dpll);
1816         } else if (HAS_PCH_SPLIT(dev_priv)) {
1817                 divisor = pch_dpll;
1818                 count = ARRAY_SIZE(pch_dpll);
1819         } else if (IS_CHERRYVIEW(dev_priv)) {
1820                 divisor = chv_dpll;
1821                 count = ARRAY_SIZE(chv_dpll);
1822         } else if (IS_VALLEYVIEW(dev_priv)) {
1823                 divisor = vlv_dpll;
1824                 count = ARRAY_SIZE(vlv_dpll);
1825         }
1826
1827         if (divisor && count) {
1828                 for (i = 0; i < count; i++) {
1829                         if (pipe_config->port_clock == divisor[i].clock) {
1830                                 pipe_config->dpll = divisor[i].dpll;
1831                                 pipe_config->clock_set = true;
1832                                 break;
1833                         }
1834                 }
1835         }
1836 }
1837
1838 static void snprintf_int_array(char *str, size_t len,
1839                                const int *array, int nelem)
1840 {
1841         int i;
1842
1843         str[0] = '\0';
1844
1845         for (i = 0; i < nelem; i++) {
1846                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1847                 if (r >= len)
1848                         return;
1849                 str += r;
1850                 len -= r;
1851         }
1852 }
1853
1854 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1855 {
1856         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1857         char str[128]; /* FIXME: too big for stack? */
1858
1859         if (!drm_debug_enabled(DRM_UT_KMS))
1860                 return;
1861
1862         snprintf_int_array(str, sizeof(str),
1863                            intel_dp->source_rates, intel_dp->num_source_rates);
1864         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1865
1866         snprintf_int_array(str, sizeof(str),
1867                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1868         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1869
1870         snprintf_int_array(str, sizeof(str),
1871                            intel_dp->common_rates, intel_dp->num_common_rates);
1872         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1873 }
1874
1875 int
1876 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1877 {
1878         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1879         int len;
1880
1881         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1882         if (drm_WARN_ON(&i915->drm, len <= 0))
1883                 return 162000;
1884
1885         return intel_dp->common_rates[len - 1];
1886 }
1887
1888 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1889 {
1890         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1891         int i = intel_dp_rate_index(intel_dp->sink_rates,
1892                                     intel_dp->num_sink_rates, rate);
1893
1894         if (drm_WARN_ON(&i915->drm, i < 0))
1895                 i = 0;
1896
1897         return i;
1898 }
1899
1900 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1901                            u8 *link_bw, u8 *rate_select)
1902 {
1903         /* eDP 1.4 rate select method. */
1904         if (intel_dp->use_rate_select) {
1905                 *link_bw = 0;
1906                 *rate_select =
1907                         intel_dp_rate_select(intel_dp, port_clock);
1908         } else {
1909                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1910                 *rate_select = 0;
1911         }
1912 }
1913
1914 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1915                                          const struct intel_crtc_state *pipe_config)
1916 {
1917         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1918
1919         /* On TGL, FEC is supported on all Pipes */
1920         if (INTEL_GEN(dev_priv) >= 12)
1921                 return true;
1922
1923         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1924                 return true;
1925
1926         return false;
1927 }
1928
1929 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1930                                   const struct intel_crtc_state *pipe_config)
1931 {
1932         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1933                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1934 }
1935
1936 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1937                                   const struct intel_crtc_state *crtc_state)
1938 {
1939         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1940
1941         if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1942                 return false;
1943
1944         return intel_dsc_source_support(encoder, crtc_state) &&
1945                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1946 }
1947
1948 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1949                                 struct intel_crtc_state *pipe_config)
1950 {
1951         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1952         struct intel_connector *intel_connector = intel_dp->attached_connector;
1953         int bpp, bpc;
1954
1955         bpp = pipe_config->pipe_bpp;
1956         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1957
1958         if (bpc > 0)
1959                 bpp = min(bpp, 3*bpc);
1960
1961         if (intel_dp_is_edp(intel_dp)) {
1962                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1963                 if (intel_connector->base.display_info.bpc == 0 &&
1964                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1965                         drm_dbg_kms(&dev_priv->drm,
1966                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1967                                     dev_priv->vbt.edp.bpp);
1968                         bpp = dev_priv->vbt.edp.bpp;
1969                 }
1970         }
1971
1972         return bpp;
1973 }
1974
1975 /* Adjust link config limits based on compliance test requests. */
1976 void
1977 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1978                                   struct intel_crtc_state *pipe_config,
1979                                   struct link_config_limits *limits)
1980 {
1981         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1982
1983         /* For DP Compliance we override the computed bpp for the pipe */
1984         if (intel_dp->compliance.test_data.bpc != 0) {
1985                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1986
1987                 limits->min_bpp = limits->max_bpp = bpp;
1988                 pipe_config->dither_force_disable = bpp == 6 * 3;
1989
1990                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1991         }
1992
1993         /* Use values requested by Compliance Test Request */
1994         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1995                 int index;
1996
1997                 /* Validate the compliance test data since max values
1998                  * might have changed due to link train fallback.
1999                  */
2000                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2001                                                intel_dp->compliance.test_lane_count)) {
2002                         index = intel_dp_rate_index(intel_dp->common_rates,
2003                                                     intel_dp->num_common_rates,
2004                                                     intel_dp->compliance.test_link_rate);
2005                         if (index >= 0)
2006                                 limits->min_clock = limits->max_clock = index;
2007                         limits->min_lane_count = limits->max_lane_count =
2008                                 intel_dp->compliance.test_lane_count;
2009                 }
2010         }
2011 }
2012
2013 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2014 {
2015         /*
2016          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2017          * format of the number of bytes per pixel will be half the number
2018          * of bytes of RGB pixel.
2019          */
2020         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2021                 bpp /= 2;
2022
2023         return bpp;
2024 }
2025
2026 /* Optimize link config in order: max bpp, min clock, min lanes */
2027 static int
2028 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2029                                   struct intel_crtc_state *pipe_config,
2030                                   const struct link_config_limits *limits)
2031 {
2032         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2033         int bpp, clock, lane_count;
2034         int mode_rate, link_clock, link_avail;
2035
2036         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2037                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2038
2039                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2040                                                    output_bpp);
2041
2042                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2043                         for (lane_count = limits->min_lane_count;
2044                              lane_count <= limits->max_lane_count;
2045                              lane_count <<= 1) {
2046                                 link_clock = intel_dp->common_rates[clock];
2047                                 link_avail = intel_dp_max_data_rate(link_clock,
2048                                                                     lane_count);
2049
2050                                 if (mode_rate <= link_avail) {
2051                                         pipe_config->lane_count = lane_count;
2052                                         pipe_config->pipe_bpp = bpp;
2053                                         pipe_config->port_clock = link_clock;
2054
2055                                         return 0;
2056                                 }
2057                         }
2058                 }
2059         }
2060
2061         return -EINVAL;
2062 }
2063
2064 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2065 {
2066         int i, num_bpc;
2067         u8 dsc_bpc[3] = {0};
2068
2069         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2070                                                        dsc_bpc);
2071         for (i = 0; i < num_bpc; i++) {
2072                 if (dsc_max_bpc >= dsc_bpc[i])
2073                         return dsc_bpc[i] * 3;
2074         }
2075
2076         return 0;
2077 }
2078
2079 #define DSC_SUPPORTED_VERSION_MIN               1
2080
2081 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2082                                        struct intel_crtc_state *crtc_state)
2083 {
2084         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2085         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2086         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2087         u8 line_buf_depth;
2088         int ret;
2089
2090         ret = intel_dsc_compute_params(encoder, crtc_state);
2091         if (ret)
2092                 return ret;
2093
2094         /*
2095          * Slice Height of 8 works for all currently available panels. So start
2096          * with that if pic_height is an integral multiple of 8. Eventually add
2097          * logic to try multiple slice heights.
2098          */
2099         if (vdsc_cfg->pic_height % 8 == 0)
2100                 vdsc_cfg->slice_height = 8;
2101         else if (vdsc_cfg->pic_height % 4 == 0)
2102                 vdsc_cfg->slice_height = 4;
2103         else
2104                 vdsc_cfg->slice_height = 2;
2105
2106         vdsc_cfg->dsc_version_major =
2107                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2108                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2109         vdsc_cfg->dsc_version_minor =
2110                 min(DSC_SUPPORTED_VERSION_MIN,
2111                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2112                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2113
2114         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2115                 DP_DSC_RGB;
2116
2117         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2118         if (!line_buf_depth) {
2119                 drm_dbg_kms(&i915->drm,
2120                             "DSC Sink Line Buffer Depth invalid\n");
2121                 return -EINVAL;
2122         }
2123
2124         if (vdsc_cfg->dsc_version_minor == 2)
2125                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2126                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2127         else
2128                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2129                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2130
2131         vdsc_cfg->block_pred_enable =
2132                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2133                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2134
2135         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2136 }
2137
2138 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2139                                        struct intel_crtc_state *pipe_config,
2140                                        struct drm_connector_state *conn_state,
2141                                        struct link_config_limits *limits)
2142 {
2143         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2144         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2145         const struct drm_display_mode *adjusted_mode =
2146                 &pipe_config->hw.adjusted_mode;
2147         u8 dsc_max_bpc;
2148         int pipe_bpp;
2149         int ret;
2150
2151         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2152                 intel_dp_supports_fec(intel_dp, pipe_config);
2153
2154         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2155                 return -EINVAL;
2156
2157         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2158         if (INTEL_GEN(dev_priv) >= 12)
2159                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2160         else
2161                 dsc_max_bpc = min_t(u8, 10,
2162                                     conn_state->max_requested_bpc);
2163
2164         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2165
2166         /* Min Input BPC for ICL+ is 8 */
2167         if (pipe_bpp < 8 * 3) {
2168                 drm_dbg_kms(&dev_priv->drm,
2169                             "No DSC support for less than 8bpc\n");
2170                 return -EINVAL;
2171         }
2172
2173         /*
2174          * For now enable DSC for max bpp, max link rate, max lane count.
2175          * Optimize this later for the minimum possible link rate/lane count
2176          * with DSC enabled for the requested mode.
2177          */
2178         pipe_config->pipe_bpp = pipe_bpp;
2179         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2180         pipe_config->lane_count = limits->max_lane_count;
2181
2182         if (intel_dp_is_edp(intel_dp)) {
2183                 pipe_config->dsc.compressed_bpp =
2184                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2185                               pipe_config->pipe_bpp);
2186                 pipe_config->dsc.slice_count =
2187                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2188                                                         true);
2189         } else {
2190                 u16 dsc_max_output_bpp;
2191                 u8 dsc_dp_slice_count;
2192
2193                 dsc_max_output_bpp =
2194                         intel_dp_dsc_get_output_bpp(dev_priv,
2195                                                     pipe_config->port_clock,
2196                                                     pipe_config->lane_count,
2197                                                     adjusted_mode->crtc_clock,
2198                                                     adjusted_mode->crtc_hdisplay);
2199                 dsc_dp_slice_count =
2200                         intel_dp_dsc_get_slice_count(intel_dp,
2201                                                      adjusted_mode->crtc_clock,
2202                                                      adjusted_mode->crtc_hdisplay);
2203                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2204                         drm_dbg_kms(&dev_priv->drm,
2205                                     "Compressed BPP/Slice Count not supported\n");
2206                         return -EINVAL;
2207                 }
2208                 pipe_config->dsc.compressed_bpp = min_t(u16,
2209                                                                dsc_max_output_bpp >> 4,
2210                                                                pipe_config->pipe_bpp);
2211                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2212         }
2213         /*
2214          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2215          * is greater than the maximum Cdclock and if slice count is even
2216          * then we need to use 2 VDSC instances.
2217          */
2218         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2219                 if (pipe_config->dsc.slice_count > 1) {
2220                         pipe_config->dsc.dsc_split = true;
2221                 } else {
2222                         drm_dbg_kms(&dev_priv->drm,
2223                                     "Cannot split stream to use 2 VDSC instances\n");
2224                         return -EINVAL;
2225                 }
2226         }
2227
2228         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2229         if (ret < 0) {
2230                 drm_dbg_kms(&dev_priv->drm,
2231                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2232                             "Compressed BPP = %d\n",
2233                             pipe_config->pipe_bpp,
2234                             pipe_config->dsc.compressed_bpp);
2235                 return ret;
2236         }
2237
2238         pipe_config->dsc.compression_enable = true;
2239         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2240                     "Compressed Bpp = %d Slice Count = %d\n",
2241                     pipe_config->pipe_bpp,
2242                     pipe_config->dsc.compressed_bpp,
2243                     pipe_config->dsc.slice_count);
2244
2245         return 0;
2246 }
2247
2248 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2249 {
2250         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2251                 return 6 * 3;
2252         else
2253                 return 8 * 3;
2254 }
2255
2256 static int
2257 intel_dp_compute_link_config(struct intel_encoder *encoder,
2258                              struct intel_crtc_state *pipe_config,
2259                              struct drm_connector_state *conn_state)
2260 {
2261         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2262         const struct drm_display_mode *adjusted_mode =
2263                 &pipe_config->hw.adjusted_mode;
2264         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2265         struct link_config_limits limits;
2266         int common_len;
2267         int ret;
2268
2269         common_len = intel_dp_common_len_rate_limit(intel_dp,
2270                                                     intel_dp->max_link_rate);
2271
2272         /* No common link rates between source and sink */
2273         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2274
2275         limits.min_clock = 0;
2276         limits.max_clock = common_len - 1;
2277
2278         limits.min_lane_count = 1;
2279         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2280
2281         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2282         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2283
2284         if (intel_dp_is_edp(intel_dp)) {
2285                 /*
2286                  * Use the maximum clock and number of lanes the eDP panel
2287                  * advertizes being capable of. The panels are generally
2288                  * designed to support only a single clock and lane
2289                  * configuration, and typically these values correspond to the
2290                  * native resolution of the panel.
2291                  */
2292                 limits.min_lane_count = limits.max_lane_count;
2293                 limits.min_clock = limits.max_clock;
2294         }
2295
2296         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2297
2298         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2299                     "max rate %d max bpp %d pixel clock %iKHz\n",
2300                     limits.max_lane_count,
2301                     intel_dp->common_rates[limits.max_clock],
2302                     limits.max_bpp, adjusted_mode->crtc_clock);
2303
2304         /*
2305          * Optimize for slow and wide. This is the place to add alternative
2306          * optimization policy.
2307          */
2308         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2309
2310         /* enable compression if the mode doesn't fit available BW */
2311         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2312         if (ret || intel_dp->force_dsc_en) {
2313                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2314                                                   conn_state, &limits);
2315                 if (ret < 0)
2316                         return ret;
2317         }
2318
2319         if (pipe_config->dsc.compression_enable) {
2320                 drm_dbg_kms(&i915->drm,
2321                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2322                             pipe_config->lane_count, pipe_config->port_clock,
2323                             pipe_config->pipe_bpp,
2324                             pipe_config->dsc.compressed_bpp);
2325
2326                 drm_dbg_kms(&i915->drm,
2327                             "DP link rate required %i available %i\n",
2328                             intel_dp_link_required(adjusted_mode->crtc_clock,
2329                                                    pipe_config->dsc.compressed_bpp),
2330                             intel_dp_max_data_rate(pipe_config->port_clock,
2331                                                    pipe_config->lane_count));
2332         } else {
2333                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2334                             pipe_config->lane_count, pipe_config->port_clock,
2335                             pipe_config->pipe_bpp);
2336
2337                 drm_dbg_kms(&i915->drm,
2338                             "DP link rate required %i available %i\n",
2339                             intel_dp_link_required(adjusted_mode->crtc_clock,
2340                                                    pipe_config->pipe_bpp),
2341                             intel_dp_max_data_rate(pipe_config->port_clock,
2342                                                    pipe_config->lane_count));
2343         }
2344         return 0;
2345 }
2346
2347 static int
2348 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2349                          struct intel_crtc_state *crtc_state,
2350                          const struct drm_connector_state *conn_state)
2351 {
2352         struct drm_connector *connector = conn_state->connector;
2353         const struct drm_display_info *info = &connector->display_info;
2354         const struct drm_display_mode *adjusted_mode =
2355                 &crtc_state->hw.adjusted_mode;
2356
2357         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2358             !intel_dp_get_colorimetry_status(intel_dp) ||
2359             !connector->ycbcr_420_allowed)
2360                 return 0;
2361
2362         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2363
2364         return intel_pch_panel_fitting(crtc_state, conn_state);
2365 }
2366
2367 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2368                                   const struct drm_connector_state *conn_state)
2369 {
2370         const struct intel_digital_connector_state *intel_conn_state =
2371                 to_intel_digital_connector_state(conn_state);
2372         const struct drm_display_mode *adjusted_mode =
2373                 &crtc_state->hw.adjusted_mode;
2374
2375         /*
2376          * Our YCbCr output is always limited range.
2377          * crtc_state->limited_color_range only applies to RGB,
2378          * and it must never be set for YCbCr or we risk setting
2379          * some conflicting bits in PIPECONF which will mess up
2380          * the colors on the monitor.
2381          */
2382         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2383                 return false;
2384
2385         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2386                 /*
2387                  * See:
2388                  * CEA-861-E - 5.1 Default Encoding Parameters
2389                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2390                  */
2391                 return crtc_state->pipe_bpp != 18 &&
2392                         drm_default_rgb_quant_range(adjusted_mode) ==
2393                         HDMI_QUANTIZATION_RANGE_LIMITED;
2394         } else {
2395                 return intel_conn_state->broadcast_rgb ==
2396                         INTEL_BROADCAST_RGB_LIMITED;
2397         }
2398 }
2399
2400 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2401                                     enum port port)
2402 {
2403         if (IS_G4X(dev_priv))
2404                 return false;
2405         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2406                 return false;
2407
2408         return true;
2409 }
2410
2411 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2412                                              const struct drm_connector_state *conn_state,
2413                                              struct drm_dp_vsc_sdp *vsc)
2414 {
2415         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2416         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2417
2418         /*
2419          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2420          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2421          * Colorimetry Format indication.
2422          */
2423         vsc->revision = 0x5;
2424         vsc->length = 0x13;
2425
2426         /* DP 1.4a spec, Table 2-120 */
2427         switch (crtc_state->output_format) {
2428         case INTEL_OUTPUT_FORMAT_YCBCR444:
2429                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2430                 break;
2431         case INTEL_OUTPUT_FORMAT_YCBCR420:
2432                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2433                 break;
2434         case INTEL_OUTPUT_FORMAT_RGB:
2435         default:
2436                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2437         }
2438
2439         switch (conn_state->colorspace) {
2440         case DRM_MODE_COLORIMETRY_BT709_YCC:
2441                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2442                 break;
2443         case DRM_MODE_COLORIMETRY_XVYCC_601:
2444                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2445                 break;
2446         case DRM_MODE_COLORIMETRY_XVYCC_709:
2447                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2448                 break;
2449         case DRM_MODE_COLORIMETRY_SYCC_601:
2450                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2451                 break;
2452         case DRM_MODE_COLORIMETRY_OPYCC_601:
2453                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2454                 break;
2455         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2456                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2457                 break;
2458         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2459                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2460                 break;
2461         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2462                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2463                 break;
2464         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2465         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2466                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2467                 break;
2468         default:
2469                 /*
2470                  * RGB->YCBCR color conversion uses the BT.709
2471                  * color space.
2472                  */
2473                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2474                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2475                 else
2476                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2477                 break;
2478         }
2479
2480         vsc->bpc = crtc_state->pipe_bpp / 3;
2481
2482         /* only RGB pixelformat supports 6 bpc */
2483         drm_WARN_ON(&dev_priv->drm,
2484                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2485
2486         /* all YCbCr are always limited range */
2487         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2488         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2489 }
2490
2491 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2492                                      struct intel_crtc_state *crtc_state,
2493                                      const struct drm_connector_state *conn_state)
2494 {
2495         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2496
2497         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2498         if (crtc_state->has_psr)
2499                 return;
2500
2501         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2502                 return;
2503
2504         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2505         vsc->sdp_type = DP_SDP_VSC;
2506         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2507                                          &crtc_state->infoframes.vsc);
2508 }
2509
2510 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2511                                   const struct intel_crtc_state *crtc_state,
2512                                   const struct drm_connector_state *conn_state,
2513                                   struct drm_dp_vsc_sdp *vsc)
2514 {
2515         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2516
2517         vsc->sdp_type = DP_SDP_VSC;
2518
2519         if (dev_priv->psr.psr2_enabled) {
2520                 if (dev_priv->psr.colorimetry_support &&
2521                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2522                         /* [PSR2, +Colorimetry] */
2523                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2524                                                          vsc);
2525                 } else {
2526                         /*
2527                          * [PSR2, -Colorimetry]
2528                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2529                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2530                          */
2531                         vsc->revision = 0x4;
2532                         vsc->length = 0xe;
2533                 }
2534         } else {
2535                 /*
2536                  * [PSR1]
2537                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2538                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2539                  * higher).
2540                  */
2541                 vsc->revision = 0x2;
2542                 vsc->length = 0x8;
2543         }
2544 }
2545
2546 static void
2547 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2548                                             struct intel_crtc_state *crtc_state,
2549                                             const struct drm_connector_state *conn_state)
2550 {
2551         int ret;
2552         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2553         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2554
2555         if (!conn_state->hdr_output_metadata)
2556                 return;
2557
2558         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2559
2560         if (ret) {
2561                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2562                 return;
2563         }
2564
2565         crtc_state->infoframes.enable |=
2566                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2567 }
2568
2569 int
2570 intel_dp_compute_config(struct intel_encoder *encoder,
2571                         struct intel_crtc_state *pipe_config,
2572                         struct drm_connector_state *conn_state)
2573 {
2574         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2575         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2576         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2577         struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2578         enum port port = encoder->port;
2579         struct intel_connector *intel_connector = intel_dp->attached_connector;
2580         struct intel_digital_connector_state *intel_conn_state =
2581                 to_intel_digital_connector_state(conn_state);
2582         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2583                                            DP_DPCD_QUIRK_CONSTANT_N);
2584         int ret = 0, output_bpp;
2585
2586         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2587                 pipe_config->has_pch_encoder = true;
2588
2589         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2590
2591         if (lspcon->active)
2592                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2593         else
2594                 ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
2595                                                conn_state);
2596         if (ret)
2597                 return ret;
2598
2599         pipe_config->has_drrs = false;
2600         if (!intel_dp_port_has_audio(dev_priv, port))
2601                 pipe_config->has_audio = false;
2602         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2603                 pipe_config->has_audio = intel_dp->has_audio;
2604         else
2605                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2606
2607         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2608                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2609                                        adjusted_mode);
2610
2611                 if (HAS_GMCH(dev_priv))
2612                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2613                 else
2614                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2615                 if (ret)
2616                         return ret;
2617         }
2618
2619         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2620                 return -EINVAL;
2621
2622         if (HAS_GMCH(dev_priv) &&
2623             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2624                 return -EINVAL;
2625
2626         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2627                 return -EINVAL;
2628
2629         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2630                 return -EINVAL;
2631
2632         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2633         if (ret < 0)
2634                 return ret;
2635
2636         pipe_config->limited_color_range =
2637                 intel_dp_limited_color_range(pipe_config, conn_state);
2638
2639         if (pipe_config->dsc.compression_enable)
2640                 output_bpp = pipe_config->dsc.compressed_bpp;
2641         else
2642                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2643
2644         intel_link_compute_m_n(output_bpp,
2645                                pipe_config->lane_count,
2646                                adjusted_mode->crtc_clock,
2647                                pipe_config->port_clock,
2648                                &pipe_config->dp_m_n,
2649                                constant_n, pipe_config->fec_enable);
2650
2651         if (intel_connector->panel.downclock_mode != NULL &&
2652                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2653                         pipe_config->has_drrs = true;
2654                         intel_link_compute_m_n(output_bpp,
2655                                                pipe_config->lane_count,
2656                                                intel_connector->panel.downclock_mode->clock,
2657                                                pipe_config->port_clock,
2658                                                &pipe_config->dp_m2_n2,
2659                                                constant_n, pipe_config->fec_enable);
2660         }
2661
2662         if (!HAS_DDI(dev_priv))
2663                 intel_dp_set_clock(encoder, pipe_config);
2664
2665         intel_psr_compute_config(intel_dp, pipe_config);
2666         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2667         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2668
2669         return 0;
2670 }
2671
2672 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2673                               int link_rate, u8 lane_count,
2674                               bool link_mst)
2675 {
2676         intel_dp->link_trained = false;
2677         intel_dp->link_rate = link_rate;
2678         intel_dp->lane_count = lane_count;
2679         intel_dp->link_mst = link_mst;
2680 }
2681
2682 static void intel_dp_prepare(struct intel_encoder *encoder,
2683                              const struct intel_crtc_state *pipe_config)
2684 {
2685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2686         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2687         enum port port = encoder->port;
2688         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2689         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2690
2691         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2692                                  pipe_config->lane_count,
2693                                  intel_crtc_has_type(pipe_config,
2694                                                      INTEL_OUTPUT_DP_MST));
2695
2696         /*
2697          * There are four kinds of DP registers:
2698          *
2699          *      IBX PCH
2700          *      SNB CPU
2701          *      IVB CPU
2702          *      CPT PCH
2703          *
2704          * IBX PCH and CPU are the same for almost everything,
2705          * except that the CPU DP PLL is configured in this
2706          * register
2707          *
2708          * CPT PCH is quite different, having many bits moved
2709          * to the TRANS_DP_CTL register instead. That
2710          * configuration happens (oddly) in ilk_pch_enable
2711          */
2712
2713         /* Preserve the BIOS-computed detected bit. This is
2714          * supposed to be read-only.
2715          */
2716         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2717
2718         /* Handle DP bits in common between all three register formats */
2719         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2720         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2721
2722         /* Split out the IBX/CPU vs CPT settings */
2723
2724         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2725                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2726                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2727                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2728                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2729                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2730
2731                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2732                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2733
2734                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2735         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2736                 u32 trans_dp;
2737
2738                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2739
2740                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2741                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2742                         trans_dp |= TRANS_DP_ENH_FRAMING;
2743                 else
2744                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2745                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2746         } else {
2747                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2748                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2749
2750                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2751                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2752                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2753                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2755
2756                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2757                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2758
2759                 if (IS_CHERRYVIEW(dev_priv))
2760                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2761                 else
2762                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2763         }
2764 }
2765
2766 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2767 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2768
2769 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2770 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2771
2772 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2773 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2774
2775 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2776
2777 static void wait_panel_status(struct intel_dp *intel_dp,
2778                                        u32 mask,
2779                                        u32 value)
2780 {
2781         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2782         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2783
2784         lockdep_assert_held(&dev_priv->pps_mutex);
2785
2786         intel_pps_verify_state(intel_dp);
2787
2788         pp_stat_reg = _pp_stat_reg(intel_dp);
2789         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2790
2791         drm_dbg_kms(&dev_priv->drm,
2792                     "mask %08x value %08x status %08x control %08x\n",
2793                     mask, value,
2794                     intel_de_read(dev_priv, pp_stat_reg),
2795                     intel_de_read(dev_priv, pp_ctrl_reg));
2796
2797         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2798                                        mask, value, 5000))
2799                 drm_err(&dev_priv->drm,
2800                         "Panel status timeout: status %08x control %08x\n",
2801                         intel_de_read(dev_priv, pp_stat_reg),
2802                         intel_de_read(dev_priv, pp_ctrl_reg));
2803
2804         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2805 }
2806
2807 static void wait_panel_on(struct intel_dp *intel_dp)
2808 {
2809         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2810
2811         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2812         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2813 }
2814
2815 static void wait_panel_off(struct intel_dp *intel_dp)
2816 {
2817         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2818
2819         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2820         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2821 }
2822
2823 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2824 {
2825         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2826         ktime_t panel_power_on_time;
2827         s64 panel_power_off_duration;
2828
2829         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2830
2831         /* take the difference of currrent time and panel power off time
2832          * and then make panel wait for t11_t12 if needed. */
2833         panel_power_on_time = ktime_get_boottime();
2834         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2835
2836         /* When we disable the VDD override bit last we have to do the manual
2837          * wait. */
2838         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2839                 wait_remaining_ms_from_jiffies(jiffies,
2840                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2841
2842         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2843 }
2844
2845 static void wait_backlight_on(struct intel_dp *intel_dp)
2846 {
2847         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2848                                        intel_dp->backlight_on_delay);
2849 }
2850
2851 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2852 {
2853         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2854                                        intel_dp->backlight_off_delay);
2855 }
2856
2857 /* Read the current pp_control value, unlocking the register if it
2858  * is locked
2859  */
2860
2861 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2862 {
2863         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2864         u32 control;
2865
2866         lockdep_assert_held(&dev_priv->pps_mutex);
2867
2868         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2869         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2870                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2871                 control &= ~PANEL_UNLOCK_MASK;
2872                 control |= PANEL_UNLOCK_REGS;
2873         }
2874         return control;
2875 }
2876
2877 /*
2878  * Must be paired with edp_panel_vdd_off().
2879  * Must hold pps_mutex around the whole on/off sequence.
2880  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2881  */
2882 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2883 {
2884         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2885         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2886         u32 pp;
2887         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2888         bool need_to_disable = !intel_dp->want_panel_vdd;
2889
2890         lockdep_assert_held(&dev_priv->pps_mutex);
2891
2892         if (!intel_dp_is_edp(intel_dp))
2893                 return false;
2894
2895         cancel_delayed_work(&intel_dp->panel_vdd_work);
2896         intel_dp->want_panel_vdd = true;
2897
2898         if (edp_have_panel_vdd(intel_dp))
2899                 return need_to_disable;
2900
2901         intel_display_power_get(dev_priv,
2902                                 intel_aux_power_domain(intel_dig_port));
2903
2904         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2905                     intel_dig_port->base.base.base.id,
2906                     intel_dig_port->base.base.name);
2907
2908         if (!edp_have_panel_power(intel_dp))
2909                 wait_panel_power_cycle(intel_dp);
2910
2911         pp = ilk_get_pp_control(intel_dp);
2912         pp |= EDP_FORCE_VDD;
2913
2914         pp_stat_reg = _pp_stat_reg(intel_dp);
2915         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2916
2917         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2918         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2919         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2920                     intel_de_read(dev_priv, pp_stat_reg),
2921                     intel_de_read(dev_priv, pp_ctrl_reg));
2922         /*
2923          * If the panel wasn't on, delay before accessing aux channel
2924          */
2925         if (!edp_have_panel_power(intel_dp)) {
2926                 drm_dbg_kms(&dev_priv->drm,
2927                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
2928                             intel_dig_port->base.base.base.id,
2929                             intel_dig_port->base.base.name);
2930                 msleep(intel_dp->panel_power_up_delay);
2931         }
2932
2933         return need_to_disable;
2934 }
2935
2936 /*
2937  * Must be paired with intel_edp_panel_vdd_off() or
2938  * intel_edp_panel_off().
2939  * Nested calls to these functions are not allowed since
2940  * we drop the lock. Caller must use some higher level
2941  * locking to prevent nested calls from other threads.
2942  */
2943 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2944 {
2945         intel_wakeref_t wakeref;
2946         bool vdd;
2947
2948         if (!intel_dp_is_edp(intel_dp))
2949                 return;
2950
2951         vdd = false;
2952         with_pps_lock(intel_dp, wakeref)
2953                 vdd = edp_panel_vdd_on(intel_dp);
2954         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2955                         dp_to_dig_port(intel_dp)->base.base.base.id,
2956                         dp_to_dig_port(intel_dp)->base.base.name);
2957 }
2958
2959 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2960 {
2961         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2962         struct intel_digital_port *intel_dig_port =
2963                 dp_to_dig_port(intel_dp);
2964         u32 pp;
2965         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2966
2967         lockdep_assert_held(&dev_priv->pps_mutex);
2968
2969         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2970
2971         if (!edp_have_panel_vdd(intel_dp))
2972                 return;
2973
2974         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2975                     intel_dig_port->base.base.base.id,
2976                     intel_dig_port->base.base.name);
2977
2978         pp = ilk_get_pp_control(intel_dp);
2979         pp &= ~EDP_FORCE_VDD;
2980
2981         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2982         pp_stat_reg = _pp_stat_reg(intel_dp);
2983
2984         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2985         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2986
2987         /* Make sure sequencer is idle before allowing subsequent activity */
2988         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2989                     intel_de_read(dev_priv, pp_stat_reg),
2990                     intel_de_read(dev_priv, pp_ctrl_reg));
2991
2992         if ((pp & PANEL_POWER_ON) == 0)
2993                 intel_dp->panel_power_off_time = ktime_get_boottime();
2994
2995         intel_display_power_put_unchecked(dev_priv,
2996                                           intel_aux_power_domain(intel_dig_port));
2997 }
2998
2999 static void edp_panel_vdd_work(struct work_struct *__work)
3000 {
3001         struct intel_dp *intel_dp =
3002                 container_of(to_delayed_work(__work),
3003                              struct intel_dp, panel_vdd_work);
3004         intel_wakeref_t wakeref;
3005
3006         with_pps_lock(intel_dp, wakeref) {
3007                 if (!intel_dp->want_panel_vdd)
3008                         edp_panel_vdd_off_sync(intel_dp);
3009         }
3010 }
3011
3012 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3013 {
3014         unsigned long delay;
3015
3016         /*
3017          * Queue the timer to fire a long time from now (relative to the power
3018          * down delay) to keep the panel power up across a sequence of
3019          * operations.
3020          */
3021         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3022         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3023 }
3024
3025 /*
3026  * Must be paired with edp_panel_vdd_on().
3027  * Must hold pps_mutex around the whole on/off sequence.
3028  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3029  */
3030 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3031 {
3032         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3033
3034         lockdep_assert_held(&dev_priv->pps_mutex);
3035
3036         if (!intel_dp_is_edp(intel_dp))
3037                 return;
3038
3039         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3040                         dp_to_dig_port(intel_dp)->base.base.base.id,
3041                         dp_to_dig_port(intel_dp)->base.base.name);
3042
3043         intel_dp->want_panel_vdd = false;
3044
3045         if (sync)
3046                 edp_panel_vdd_off_sync(intel_dp);
3047         else
3048                 edp_panel_vdd_schedule_off(intel_dp);
3049 }
3050
3051 static void edp_panel_on(struct intel_dp *intel_dp)
3052 {
3053         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3054         u32 pp;
3055         i915_reg_t pp_ctrl_reg;
3056
3057         lockdep_assert_held(&dev_priv->pps_mutex);
3058
3059         if (!intel_dp_is_edp(intel_dp))
3060                 return;
3061
3062         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3063                     dp_to_dig_port(intel_dp)->base.base.base.id,
3064                     dp_to_dig_port(intel_dp)->base.base.name);
3065
3066         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3067                      "[ENCODER:%d:%s] panel power already on\n",
3068                      dp_to_dig_port(intel_dp)->base.base.base.id,
3069                      dp_to_dig_port(intel_dp)->base.base.name))
3070                 return;
3071
3072         wait_panel_power_cycle(intel_dp);
3073
3074         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3075         pp = ilk_get_pp_control(intel_dp);
3076         if (IS_GEN(dev_priv, 5)) {
3077                 /* ILK workaround: disable reset around power sequence */
3078                 pp &= ~PANEL_POWER_RESET;
3079                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3080                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3081         }
3082
3083         pp |= PANEL_POWER_ON;
3084         if (!IS_GEN(dev_priv, 5))
3085                 pp |= PANEL_POWER_RESET;
3086
3087         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3088         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3089
3090         wait_panel_on(intel_dp);
3091         intel_dp->last_power_on = jiffies;
3092
3093         if (IS_GEN(dev_priv, 5)) {
3094                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3095                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3096                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3097         }
3098 }
3099
3100 void intel_edp_panel_on(struct intel_dp *intel_dp)
3101 {
3102         intel_wakeref_t wakeref;
3103
3104         if (!intel_dp_is_edp(intel_dp))
3105                 return;
3106
3107         with_pps_lock(intel_dp, wakeref)
3108                 edp_panel_on(intel_dp);
3109 }
3110
3111
3112 static void edp_panel_off(struct intel_dp *intel_dp)
3113 {
3114         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3115         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3116         u32 pp;
3117         i915_reg_t pp_ctrl_reg;
3118
3119         lockdep_assert_held(&dev_priv->pps_mutex);
3120
3121         if (!intel_dp_is_edp(intel_dp))
3122                 return;
3123
3124         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3125                     dig_port->base.base.base.id, dig_port->base.base.name);
3126
3127         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3128                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3129                  dig_port->base.base.base.id, dig_port->base.base.name);
3130
3131         pp = ilk_get_pp_control(intel_dp);
3132         /* We need to switch off panel power _and_ force vdd, for otherwise some
3133          * panels get very unhappy and cease to work. */
3134         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3135                 EDP_BLC_ENABLE);
3136
3137         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3138
3139         intel_dp->want_panel_vdd = false;
3140
3141         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3142         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3143
3144         wait_panel_off(intel_dp);
3145         intel_dp->panel_power_off_time = ktime_get_boottime();
3146
3147         /* We got a reference when we enabled the VDD. */
3148         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3149 }
3150
3151 void intel_edp_panel_off(struct intel_dp *intel_dp)
3152 {
3153         intel_wakeref_t wakeref;
3154
3155         if (!intel_dp_is_edp(intel_dp))
3156                 return;
3157
3158         with_pps_lock(intel_dp, wakeref)
3159                 edp_panel_off(intel_dp);
3160 }
3161
3162 /* Enable backlight in the panel power control. */
3163 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3164 {
3165         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3166         intel_wakeref_t wakeref;
3167
3168         /*
3169          * If we enable the backlight right away following a panel power
3170          * on, we may see slight flicker as the panel syncs with the eDP
3171          * link.  So delay a bit to make sure the image is solid before
3172          * allowing it to appear.
3173          */
3174         wait_backlight_on(intel_dp);
3175
3176         with_pps_lock(intel_dp, wakeref) {
3177                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3178                 u32 pp;
3179
3180                 pp = ilk_get_pp_control(intel_dp);
3181                 pp |= EDP_BLC_ENABLE;
3182
3183                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3184                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3185         }
3186 }
3187
3188 /* Enable backlight PWM and backlight PP control. */
3189 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3190                             const struct drm_connector_state *conn_state)
3191 {
3192         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3193         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3194
3195         if (!intel_dp_is_edp(intel_dp))
3196                 return;
3197
3198         drm_dbg_kms(&i915->drm, "\n");
3199
3200         intel_panel_enable_backlight(crtc_state, conn_state);
3201         _intel_edp_backlight_on(intel_dp);
3202 }
3203
3204 /* Disable backlight in the panel power control. */
3205 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3206 {
3207         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3208         intel_wakeref_t wakeref;
3209
3210         if (!intel_dp_is_edp(intel_dp))
3211                 return;
3212
3213         with_pps_lock(intel_dp, wakeref) {
3214                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3215                 u32 pp;
3216
3217                 pp = ilk_get_pp_control(intel_dp);
3218                 pp &= ~EDP_BLC_ENABLE;
3219
3220                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3221                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3222         }
3223
3224         intel_dp->last_backlight_off = jiffies;
3225         edp_wait_backlight_off(intel_dp);
3226 }
3227
3228 /* Disable backlight PP control and backlight PWM. */
3229 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3230 {
3231         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3232         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3233
3234         if (!intel_dp_is_edp(intel_dp))
3235                 return;
3236
3237         drm_dbg_kms(&i915->drm, "\n");
3238
3239         _intel_edp_backlight_off(intel_dp);
3240         intel_panel_disable_backlight(old_conn_state);
3241 }
3242
3243 /*
3244  * Hook for controlling the panel power control backlight through the bl_power
3245  * sysfs attribute. Take care to handle multiple calls.
3246  */
3247 static void intel_edp_backlight_power(struct intel_connector *connector,
3248                                       bool enable)
3249 {
3250         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3251         struct intel_dp *intel_dp = intel_attached_dp(connector);
3252         intel_wakeref_t wakeref;
3253         bool is_enabled;
3254
3255         is_enabled = false;
3256         with_pps_lock(intel_dp, wakeref)
3257                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3258         if (is_enabled == enable)
3259                 return;
3260
3261         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3262                     enable ? "enable" : "disable");
3263
3264         if (enable)
3265                 _intel_edp_backlight_on(intel_dp);
3266         else
3267                 _intel_edp_backlight_off(intel_dp);
3268 }
3269
3270 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3271 {
3272         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3273         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3274         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3275
3276         I915_STATE_WARN(cur_state != state,
3277                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3278                         dig_port->base.base.base.id, dig_port->base.base.name,
3279                         onoff(state), onoff(cur_state));
3280 }
3281 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3282
3283 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3284 {
3285         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3286
3287         I915_STATE_WARN(cur_state != state,
3288                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3289                         onoff(state), onoff(cur_state));
3290 }
3291 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3292 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3293
3294 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3295                            const struct intel_crtc_state *pipe_config)
3296 {
3297         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3298         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3299
3300         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3301         assert_dp_port_disabled(intel_dp);
3302         assert_edp_pll_disabled(dev_priv);
3303
3304         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3305                     pipe_config->port_clock);
3306
3307         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3308
3309         if (pipe_config->port_clock == 162000)
3310                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3311         else
3312                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3313
3314         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3315         intel_de_posting_read(dev_priv, DP_A);
3316         udelay(500);
3317
3318         /*
3319          * [DevILK] Work around required when enabling DP PLL
3320          * while a pipe is enabled going to FDI:
3321          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3322          * 2. Program DP PLL enable
3323          */
3324         if (IS_GEN(dev_priv, 5))
3325                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3326
3327         intel_dp->DP |= DP_PLL_ENABLE;
3328
3329         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3330         intel_de_posting_read(dev_priv, DP_A);
3331         udelay(200);
3332 }
3333
3334 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3335                             const struct intel_crtc_state *old_crtc_state)
3336 {
3337         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3338         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3339
3340         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3341         assert_dp_port_disabled(intel_dp);
3342         assert_edp_pll_enabled(dev_priv);
3343
3344         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3345
3346         intel_dp->DP &= ~DP_PLL_ENABLE;
3347
3348         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3349         intel_de_posting_read(dev_priv, DP_A);
3350         udelay(200);
3351 }
3352
3353 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3354 {
3355         /*
3356          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3357          * be capable of signalling downstream hpd with a long pulse.
3358          * Whether or not that means D3 is safe to use is not clear,
3359          * but let's assume so until proven otherwise.
3360          *
3361          * FIXME should really check all downstream ports...
3362          */
3363         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3364                 drm_dp_is_branch(intel_dp->dpcd) &&
3365                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3366 }
3367
3368 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3369                                            const struct intel_crtc_state *crtc_state,
3370                                            bool enable)
3371 {
3372         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3373         int ret;
3374
3375         if (!crtc_state->dsc.compression_enable)
3376                 return;
3377
3378         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3379                                  enable ? DP_DECOMPRESSION_EN : 0);
3380         if (ret < 0)
3381                 drm_dbg_kms(&i915->drm,
3382                             "Failed to %s sink decompression state\n",
3383                             enable ? "enable" : "disable");
3384 }
3385
3386 /* If the sink supports it, try to set the power state appropriately */
3387 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3388 {
3389         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3390         int ret, i;
3391
3392         /* Should have a valid DPCD by this point */
3393         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3394                 return;
3395
3396         if (mode != DRM_MODE_DPMS_ON) {
3397                 if (downstream_hpd_needs_d0(intel_dp))
3398                         return;
3399
3400                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3401                                          DP_SET_POWER_D3);
3402         } else {
3403                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3404
3405                 /*
3406                  * When turning on, we need to retry for 1ms to give the sink
3407                  * time to wake up.
3408                  */
3409                 for (i = 0; i < 3; i++) {
3410                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3411                                                  DP_SET_POWER_D0);
3412                         if (ret == 1)
3413                                 break;
3414                         msleep(1);
3415                 }
3416
3417                 if (ret == 1 && lspcon->active)
3418                         lspcon_wait_pcon_mode(lspcon);
3419         }
3420
3421         if (ret != 1)
3422                 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3423                             mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3424 }
3425
3426 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3427                                  enum port port, enum pipe *pipe)
3428 {
3429         enum pipe p;
3430
3431         for_each_pipe(dev_priv, p) {
3432                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3433
3434                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3435                         *pipe = p;
3436                         return true;
3437                 }
3438         }
3439
3440         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3441                     port_name(port));
3442
3443         /* must initialize pipe to something for the asserts */
3444         *pipe = PIPE_A;
3445
3446         return false;
3447 }
3448
3449 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3450                            i915_reg_t dp_reg, enum port port,
3451                            enum pipe *pipe)
3452 {
3453         bool ret;
3454         u32 val;
3455
3456         val = intel_de_read(dev_priv, dp_reg);
3457
3458         ret = val & DP_PORT_EN;
3459
3460         /* asserts want to know the pipe even if the port is disabled */
3461         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3462                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3463         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3464                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3465         else if (IS_CHERRYVIEW(dev_priv))
3466                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3467         else
3468                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3469
3470         return ret;
3471 }
3472
3473 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3474                                   enum pipe *pipe)
3475 {
3476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3477         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3478         intel_wakeref_t wakeref;
3479         bool ret;
3480
3481         wakeref = intel_display_power_get_if_enabled(dev_priv,
3482                                                      encoder->power_domain);
3483         if (!wakeref)
3484                 return false;
3485
3486         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3487                                     encoder->port, pipe);
3488
3489         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3490
3491         return ret;
3492 }
3493
3494 static void intel_dp_get_config(struct intel_encoder *encoder,
3495                                 struct intel_crtc_state *pipe_config)
3496 {
3497         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3498         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3499         u32 tmp, flags = 0;
3500         enum port port = encoder->port;
3501         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3502
3503         if (encoder->type == INTEL_OUTPUT_EDP)
3504                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3505         else
3506                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3507
3508         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3509
3510         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3511
3512         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3513                 u32 trans_dp = intel_de_read(dev_priv,
3514                                              TRANS_DP_CTL(crtc->pipe));
3515
3516                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3517                         flags |= DRM_MODE_FLAG_PHSYNC;
3518                 else
3519                         flags |= DRM_MODE_FLAG_NHSYNC;
3520
3521                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3522                         flags |= DRM_MODE_FLAG_PVSYNC;
3523                 else
3524                         flags |= DRM_MODE_FLAG_NVSYNC;
3525         } else {
3526                 if (tmp & DP_SYNC_HS_HIGH)
3527                         flags |= DRM_MODE_FLAG_PHSYNC;
3528                 else
3529                         flags |= DRM_MODE_FLAG_NHSYNC;
3530
3531                 if (tmp & DP_SYNC_VS_HIGH)
3532                         flags |= DRM_MODE_FLAG_PVSYNC;
3533                 else
3534                         flags |= DRM_MODE_FLAG_NVSYNC;
3535         }
3536
3537         pipe_config->hw.adjusted_mode.flags |= flags;
3538
3539         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3540                 pipe_config->limited_color_range = true;
3541
3542         pipe_config->lane_count =
3543                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3544
3545         intel_dp_get_m_n(crtc, pipe_config);
3546
3547         if (port == PORT_A) {
3548                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3549                         pipe_config->port_clock = 162000;
3550                 else
3551                         pipe_config->port_clock = 270000;
3552         }
3553
3554         pipe_config->hw.adjusted_mode.crtc_clock =
3555                 intel_dotclock_calculate(pipe_config->port_clock,
3556                                          &pipe_config->dp_m_n);
3557
3558         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3559             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3560                 /*
3561                  * This is a big fat ugly hack.
3562                  *
3563                  * Some machines in UEFI boot mode provide us a VBT that has 18
3564                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3565                  * unknown we fail to light up. Yet the same BIOS boots up with
3566                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3567                  * max, not what it tells us to use.
3568                  *
3569                  * Note: This will still be broken if the eDP panel is not lit
3570                  * up by the BIOS, and thus we can't get the mode at module
3571                  * load.
3572                  */
3573                 drm_dbg_kms(&dev_priv->drm,
3574                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3575                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3576                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3577         }
3578 }
3579
3580 static void intel_disable_dp(struct intel_atomic_state *state,
3581                              struct intel_encoder *encoder,
3582                              const struct intel_crtc_state *old_crtc_state,
3583                              const struct drm_connector_state *old_conn_state)
3584 {
3585         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3586
3587         intel_dp->link_trained = false;
3588
3589         if (old_crtc_state->has_audio)
3590                 intel_audio_codec_disable(encoder,
3591                                           old_crtc_state, old_conn_state);
3592
3593         /* Make sure the panel is off before trying to change the mode. But also
3594          * ensure that we have vdd while we switch off the panel. */
3595         intel_edp_panel_vdd_on(intel_dp);
3596         intel_edp_backlight_off(old_conn_state);
3597         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3598         intel_edp_panel_off(intel_dp);
3599 }
3600
3601 static void g4x_disable_dp(struct intel_atomic_state *state,
3602                            struct intel_encoder *encoder,
3603                            const struct intel_crtc_state *old_crtc_state,
3604                            const struct drm_connector_state *old_conn_state)
3605 {
3606         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3607 }
3608
3609 static void vlv_disable_dp(struct intel_atomic_state *state,
3610                            struct intel_encoder *encoder,
3611                            const struct intel_crtc_state *old_crtc_state,
3612                            const struct drm_connector_state *old_conn_state)
3613 {
3614         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3615 }
3616
3617 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3618                                 struct intel_encoder *encoder,
3619                                 const struct intel_crtc_state *old_crtc_state,
3620                                 const struct drm_connector_state *old_conn_state)
3621 {
3622         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3623         enum port port = encoder->port;
3624
3625         /*
3626          * Bspec does not list a specific disable sequence for g4x DP.
3627          * Follow the ilk+ sequence (disable pipe before the port) for
3628          * g4x DP as it does not suffer from underruns like the normal
3629          * g4x modeset sequence (disable pipe after the port).
3630          */
3631         intel_dp_link_down(encoder, old_crtc_state);
3632
3633         /* Only ilk+ has port A */
3634         if (port == PORT_A)
3635                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3636 }
3637
3638 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3639                                 struct intel_encoder *encoder,
3640                                 const struct intel_crtc_state *old_crtc_state,
3641                                 const struct drm_connector_state *old_conn_state)
3642 {
3643         intel_dp_link_down(encoder, old_crtc_state);
3644 }
3645
3646 static void chv_post_disable_dp(struct intel_atomic_state *state,
3647                                 struct intel_encoder *encoder,
3648                                 const struct intel_crtc_state *old_crtc_state,
3649                                 const struct drm_connector_state *old_conn_state)
3650 {
3651         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3652
3653         intel_dp_link_down(encoder, old_crtc_state);
3654
3655         vlv_dpio_get(dev_priv);
3656
3657         /* Assert data lane reset */
3658         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3659
3660         vlv_dpio_put(dev_priv);
3661 }
3662
3663 static void
3664 cpt_set_link_train(struct intel_dp *intel_dp,
3665                    u8 dp_train_pat)
3666 {
3667         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3668         u32 *DP = &intel_dp->DP;
3669
3670         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3671
3672         switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3673         case DP_TRAINING_PATTERN_DISABLE:
3674                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3675                 break;
3676         case DP_TRAINING_PATTERN_1:
3677                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3678                 break;
3679         case DP_TRAINING_PATTERN_2:
3680                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3681                 break;
3682         case DP_TRAINING_PATTERN_3:
3683                 drm_dbg_kms(&dev_priv->drm,
3684                             "TPS3 not supported, using TPS2 instead\n");
3685                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3686                 break;
3687         }
3688
3689         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3690         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3691 }
3692
3693 static void
3694 g4x_set_link_train(struct intel_dp *intel_dp,
3695                    u8 dp_train_pat)
3696 {
3697         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3698         u32 *DP = &intel_dp->DP;
3699
3700         *DP &= ~DP_LINK_TRAIN_MASK;
3701
3702         switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3703         case DP_TRAINING_PATTERN_DISABLE:
3704                 *DP |= DP_LINK_TRAIN_OFF;
3705                 break;
3706         case DP_TRAINING_PATTERN_1:
3707                 *DP |= DP_LINK_TRAIN_PAT_1;
3708                 break;
3709         case DP_TRAINING_PATTERN_2:
3710                 *DP |= DP_LINK_TRAIN_PAT_2;
3711                 break;
3712         case DP_TRAINING_PATTERN_3:
3713                 drm_dbg_kms(&dev_priv->drm,
3714                             "TPS3 not supported, using TPS2 instead\n");
3715                 *DP |= DP_LINK_TRAIN_PAT_2;
3716                 break;
3717         }
3718
3719         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3720         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3721 }
3722
3723 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3724                                  const struct intel_crtc_state *old_crtc_state)
3725 {
3726         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3727
3728         /* enable with pattern 1 (as per spec) */
3729
3730         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3731
3732         /*
3733          * Magic for VLV/CHV. We _must_ first set up the register
3734          * without actually enabling the port, and then do another
3735          * write to enable the port. Otherwise link training will
3736          * fail when the power sequencer is freshly used for this port.
3737          */
3738         intel_dp->DP |= DP_PORT_EN;
3739         if (old_crtc_state->has_audio)
3740                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3741
3742         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3743         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3744 }
3745
3746 static void intel_enable_dp(struct intel_atomic_state *state,
3747                             struct intel_encoder *encoder,
3748                             const struct intel_crtc_state *pipe_config,
3749                             const struct drm_connector_state *conn_state)
3750 {
3751         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3752         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3753         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3754         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3755         enum pipe pipe = crtc->pipe;
3756         intel_wakeref_t wakeref;
3757
3758         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3759                 return;
3760
3761         with_pps_lock(intel_dp, wakeref) {
3762                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3763                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3764
3765                 intel_dp_enable_port(intel_dp, pipe_config);
3766
3767                 edp_panel_vdd_on(intel_dp);
3768                 edp_panel_on(intel_dp);
3769                 edp_panel_vdd_off(intel_dp, true);
3770         }
3771
3772         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3773                 unsigned int lane_mask = 0x0;
3774
3775                 if (IS_CHERRYVIEW(dev_priv))
3776                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3777
3778                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3779                                     lane_mask);
3780         }
3781
3782         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3783         intel_dp_start_link_train(intel_dp);
3784         intel_dp_stop_link_train(intel_dp);
3785
3786         if (pipe_config->has_audio) {
3787                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3788                         pipe_name(pipe));
3789                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3790         }
3791 }
3792
3793 static void g4x_enable_dp(struct intel_atomic_state *state,
3794                           struct intel_encoder *encoder,
3795                           const struct intel_crtc_state *pipe_config,
3796                           const struct drm_connector_state *conn_state)
3797 {
3798         intel_enable_dp(state, encoder, pipe_config, conn_state);
3799         intel_edp_backlight_on(pipe_config, conn_state);
3800 }
3801
3802 static void vlv_enable_dp(struct intel_atomic_state *state,
3803                           struct intel_encoder *encoder,
3804                           const struct intel_crtc_state *pipe_config,
3805                           const struct drm_connector_state *conn_state)
3806 {
3807         intel_edp_backlight_on(pipe_config, conn_state);
3808 }
3809
3810 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3811                               struct intel_encoder *encoder,
3812                               const struct intel_crtc_state *pipe_config,
3813                               const struct drm_connector_state *conn_state)
3814 {
3815         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3816         enum port port = encoder->port;
3817
3818         intel_dp_prepare(encoder, pipe_config);
3819
3820         /* Only ilk+ has port A */
3821         if (port == PORT_A)
3822                 ilk_edp_pll_on(intel_dp, pipe_config);
3823 }
3824
3825 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3826 {
3827         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3828         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3829         enum pipe pipe = intel_dp->pps_pipe;
3830         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3831
3832         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3833
3834         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3835                 return;
3836
3837         edp_panel_vdd_off_sync(intel_dp);
3838
3839         /*
3840          * VLV seems to get confused when multiple power sequencers
3841          * have the same port selected (even if only one has power/vdd
3842          * enabled). The failure manifests as vlv_wait_port_ready() failing
3843          * CHV on the other hand doesn't seem to mind having the same port
3844          * selected in multiple power sequencers, but let's clear the
3845          * port select always when logically disconnecting a power sequencer
3846          * from a port.
3847          */
3848         drm_dbg_kms(&dev_priv->drm,
3849                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3850                     pipe_name(pipe), intel_dig_port->base.base.base.id,
3851                     intel_dig_port->base.base.name);
3852         intel_de_write(dev_priv, pp_on_reg, 0);
3853         intel_de_posting_read(dev_priv, pp_on_reg);
3854
3855         intel_dp->pps_pipe = INVALID_PIPE;
3856 }
3857
3858 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3859                                       enum pipe pipe)
3860 {
3861         struct intel_encoder *encoder;
3862
3863         lockdep_assert_held(&dev_priv->pps_mutex);
3864
3865         for_each_intel_dp(&dev_priv->drm, encoder) {
3866                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3867
3868                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3869                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3870                          pipe_name(pipe), encoder->base.base.id,
3871                          encoder->base.name);
3872
3873                 if (intel_dp->pps_pipe != pipe)
3874                         continue;
3875
3876                 drm_dbg_kms(&dev_priv->drm,
3877                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3878                             pipe_name(pipe), encoder->base.base.id,
3879                             encoder->base.name);
3880
3881                 /* make sure vdd is off before we steal it */
3882                 vlv_detach_power_sequencer(intel_dp);
3883         }
3884 }
3885
3886 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3887                                            const struct intel_crtc_state *crtc_state)
3888 {
3889         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3890         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3891         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3892
3893         lockdep_assert_held(&dev_priv->pps_mutex);
3894
3895         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3896
3897         if (intel_dp->pps_pipe != INVALID_PIPE &&
3898             intel_dp->pps_pipe != crtc->pipe) {
3899                 /*
3900                  * If another power sequencer was being used on this
3901                  * port previously make sure to turn off vdd there while
3902                  * we still have control of it.
3903                  */
3904                 vlv_detach_power_sequencer(intel_dp);
3905         }
3906
3907         /*
3908          * We may be stealing the power
3909          * sequencer from another port.
3910          */
3911         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3912
3913         intel_dp->active_pipe = crtc->pipe;
3914
3915         if (!intel_dp_is_edp(intel_dp))
3916                 return;
3917
3918         /* now it's all ours */
3919         intel_dp->pps_pipe = crtc->pipe;
3920
3921         drm_dbg_kms(&dev_priv->drm,
3922                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3923                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3924                     encoder->base.name);
3925
3926         /* init power sequencer on this pipe and port */
3927         intel_dp_init_panel_power_sequencer(intel_dp);
3928         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3929 }
3930
3931 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3932                               struct intel_encoder *encoder,
3933                               const struct intel_crtc_state *pipe_config,
3934                               const struct drm_connector_state *conn_state)
3935 {
3936         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3937
3938         intel_enable_dp(state, encoder, pipe_config, conn_state);
3939 }
3940
3941 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3942                                   struct intel_encoder *encoder,
3943                                   const struct intel_crtc_state *pipe_config,
3944                                   const struct drm_connector_state *conn_state)
3945 {
3946         intel_dp_prepare(encoder, pipe_config);
3947
3948         vlv_phy_pre_pll_enable(encoder, pipe_config);
3949 }
3950
3951 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3952                               struct intel_encoder *encoder,
3953                               const struct intel_crtc_state *pipe_config,
3954                               const struct drm_connector_state *conn_state)
3955 {
3956         chv_phy_pre_encoder_enable(encoder, pipe_config);
3957
3958         intel_enable_dp(state, encoder, pipe_config, conn_state);
3959
3960         /* Second common lane will stay alive on its own now */
3961         chv_phy_release_cl2_override(encoder);
3962 }
3963
3964 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3965                                   struct intel_encoder *encoder,
3966                                   const struct intel_crtc_state *pipe_config,
3967                                   const struct drm_connector_state *conn_state)
3968 {
3969         intel_dp_prepare(encoder, pipe_config);
3970
3971         chv_phy_pre_pll_enable(encoder, pipe_config);
3972 }
3973
3974 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3975                                     struct intel_encoder *encoder,
3976                                     const struct intel_crtc_state *old_crtc_state,
3977                                     const struct drm_connector_state *old_conn_state)
3978 {
3979         chv_phy_post_pll_disable(encoder, old_crtc_state);
3980 }
3981
3982 /*
3983  * Fetch AUX CH registers 0x202 - 0x207 which contain
3984  * link status information
3985  */
3986 bool
3987 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3988 {
3989         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3990                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3991 }
3992
3993 /* These are source-specific values. */
3994 u8
3995 intel_dp_voltage_max(struct intel_dp *intel_dp)
3996 {
3997         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3998         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3999         enum port port = encoder->port;
4000
4001         if (HAS_DDI(dev_priv))
4002                 return intel_ddi_dp_voltage_max(encoder);
4003         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
4004                  (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
4005                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4006         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
4007                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4008         else
4009                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4010 }
4011
4012 u8
4013 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4014 {
4015         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4016         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4017         enum port port = encoder->port;
4018
4019         if (HAS_DDI(dev_priv)) {
4020                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4021         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
4022                    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
4023                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4024                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4025                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4026                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4027                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4029                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4030                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4031                 default:
4032                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4033                 }
4034         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4035                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4037                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4038                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4039                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4040                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4041                 default:
4042                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4043                 }
4044         } else {
4045                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4046                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4047                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4048                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4049                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4051                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4052                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4053                 default:
4054                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4055                 }
4056         }
4057 }
4058
4059 static void vlv_set_signal_levels(struct intel_dp *intel_dp)
4060 {
4061         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4062         unsigned long demph_reg_value, preemph_reg_value,
4063                 uniqtranscale_reg_value;
4064         u8 train_set = intel_dp->train_set[0];
4065
4066         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4067         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4068                 preemph_reg_value = 0x0004000;
4069                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4070                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4071                         demph_reg_value = 0x2B405555;
4072                         uniqtranscale_reg_value = 0x552AB83A;
4073                         break;
4074                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4075                         demph_reg_value = 0x2B404040;
4076                         uniqtranscale_reg_value = 0x5548B83A;
4077                         break;
4078                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4079                         demph_reg_value = 0x2B245555;
4080                         uniqtranscale_reg_value = 0x5560B83A;
4081                         break;
4082                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4083                         demph_reg_value = 0x2B405555;
4084                         uniqtranscale_reg_value = 0x5598DA3A;
4085                         break;
4086                 default:
4087                         return;
4088                 }
4089                 break;
4090         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4091                 preemph_reg_value = 0x0002000;
4092                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4093                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4094                         demph_reg_value = 0x2B404040;
4095                         uniqtranscale_reg_value = 0x5552B83A;
4096                         break;
4097                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4098                         demph_reg_value = 0x2B404848;
4099                         uniqtranscale_reg_value = 0x5580B83A;
4100                         break;
4101                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4102                         demph_reg_value = 0x2B404040;
4103                         uniqtranscale_reg_value = 0x55ADDA3A;
4104                         break;
4105                 default:
4106                         return;
4107                 }
4108                 break;
4109         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4110                 preemph_reg_value = 0x0000000;
4111                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4112                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4113                         demph_reg_value = 0x2B305555;
4114                         uniqtranscale_reg_value = 0x5570B83A;
4115                         break;
4116                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4117                         demph_reg_value = 0x2B2B4040;
4118                         uniqtranscale_reg_value = 0x55ADDA3A;
4119                         break;
4120                 default:
4121                         return;
4122                 }
4123                 break;
4124         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4125                 preemph_reg_value = 0x0006000;
4126                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4127                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4128                         demph_reg_value = 0x1B405555;
4129                         uniqtranscale_reg_value = 0x55ADDA3A;
4130                         break;
4131                 default:
4132                         return;
4133                 }
4134                 break;
4135         default:
4136                 return;
4137         }
4138
4139         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4140                                  uniqtranscale_reg_value, 0);
4141 }
4142
4143 static void chv_set_signal_levels(struct intel_dp *intel_dp)
4144 {
4145         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4146         u32 deemph_reg_value, margin_reg_value;
4147         bool uniq_trans_scale = false;
4148         u8 train_set = intel_dp->train_set[0];
4149
4150         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4151         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4152                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4153                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4154                         deemph_reg_value = 128;
4155                         margin_reg_value = 52;
4156                         break;
4157                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4158                         deemph_reg_value = 128;
4159                         margin_reg_value = 77;
4160                         break;
4161                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4162                         deemph_reg_value = 128;
4163                         margin_reg_value = 102;
4164                         break;
4165                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4166                         deemph_reg_value = 128;
4167                         margin_reg_value = 154;
4168                         uniq_trans_scale = true;
4169                         break;
4170                 default:
4171                         return;
4172                 }
4173                 break;
4174         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4175                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4176                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4177                         deemph_reg_value = 85;
4178                         margin_reg_value = 78;
4179                         break;
4180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4181                         deemph_reg_value = 85;
4182                         margin_reg_value = 116;
4183                         break;
4184                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4185                         deemph_reg_value = 85;
4186                         margin_reg_value = 154;
4187                         break;
4188                 default:
4189                         return;
4190                 }
4191                 break;
4192         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4193                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4195                         deemph_reg_value = 64;
4196                         margin_reg_value = 104;
4197                         break;
4198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4199                         deemph_reg_value = 64;
4200                         margin_reg_value = 154;
4201                         break;
4202                 default:
4203                         return;
4204                 }
4205                 break;
4206         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4207                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4209                         deemph_reg_value = 43;
4210                         margin_reg_value = 154;
4211                         break;
4212                 default:
4213                         return;
4214                 }
4215                 break;
4216         default:
4217                 return;
4218         }
4219
4220         chv_set_phy_signal_level(encoder, deemph_reg_value,
4221                                  margin_reg_value, uniq_trans_scale);
4222 }
4223
4224 static u32 g4x_signal_levels(u8 train_set)
4225 {
4226         u32 signal_levels = 0;
4227
4228         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4229         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4230         default:
4231                 signal_levels |= DP_VOLTAGE_0_4;
4232                 break;
4233         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4234                 signal_levels |= DP_VOLTAGE_0_6;
4235                 break;
4236         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4237                 signal_levels |= DP_VOLTAGE_0_8;
4238                 break;
4239         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4240                 signal_levels |= DP_VOLTAGE_1_2;
4241                 break;
4242         }
4243         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4244         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4245         default:
4246                 signal_levels |= DP_PRE_EMPHASIS_0;
4247                 break;
4248         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4249                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4250                 break;
4251         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4252                 signal_levels |= DP_PRE_EMPHASIS_6;
4253                 break;
4254         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4255                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4256                 break;
4257         }
4258         return signal_levels;
4259 }
4260
4261 static void
4262 g4x_set_signal_levels(struct intel_dp *intel_dp)
4263 {
4264         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4265         u8 train_set = intel_dp->train_set[0];
4266         u32 signal_levels;
4267
4268         signal_levels = g4x_signal_levels(train_set);
4269
4270         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4271                     signal_levels);
4272
4273         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4274         intel_dp->DP |= signal_levels;
4275
4276         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4277         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4278 }
4279
4280 /* SNB CPU eDP voltage swing and pre-emphasis control */
4281 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4282 {
4283         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4284                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4285
4286         switch (signal_levels) {
4287         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4288         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4289                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4290         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4291                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4292         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4293         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4294                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4295         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4296         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4297                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4298         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4299         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4300                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4301         default:
4302                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4303                               "0x%x\n", signal_levels);
4304                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4305         }
4306 }
4307
4308 static void
4309 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4310 {
4311         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4312         u8 train_set = intel_dp->train_set[0];
4313         u32 signal_levels;
4314
4315         signal_levels = snb_cpu_edp_signal_levels(train_set);
4316
4317         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4318                     signal_levels);
4319
4320         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4321         intel_dp->DP |= signal_levels;
4322
4323         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4324         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4325 }
4326
4327 /* IVB CPU eDP voltage swing and pre-emphasis control */
4328 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4329 {
4330         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4331                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4332
4333         switch (signal_levels) {
4334         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4335                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4336         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4337                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4338         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4339                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4340
4341         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4342                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4343         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4344                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4345
4346         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4347                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4348         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4349                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4350
4351         default:
4352                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4353                               "0x%x\n", signal_levels);
4354                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4355         }
4356 }
4357
4358 static void
4359 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
4360 {
4361         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4362         u8 train_set = intel_dp->train_set[0];
4363         u32 signal_levels;
4364
4365         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4366
4367         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4368                     signal_levels);
4369
4370         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4371         intel_dp->DP |= signal_levels;
4372
4373         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4374         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4375 }
4376
4377 void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4378 {
4379         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4380         u8 train_set = intel_dp->train_set[0];
4381
4382         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4383                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4384                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4385         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4386                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4387                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4388                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4389                     " (max)" : "");
4390
4391         intel_dp->set_signal_levels(intel_dp);
4392 }
4393
4394 void
4395 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4396                                        u8 dp_train_pat)
4397 {
4398         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4399         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4400
4401         if (dp_train_pat & train_pat_mask)
4402                 drm_dbg_kms(&dev_priv->drm,
4403                             "Using DP training pattern TPS%d\n",
4404                             dp_train_pat & train_pat_mask);
4405
4406         intel_dp->set_link_train(intel_dp, dp_train_pat);
4407 }
4408
4409 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4410 {
4411         if (intel_dp->set_idle_link_train)
4412                 intel_dp->set_idle_link_train(intel_dp);
4413 }
4414
4415 static void
4416 intel_dp_link_down(struct intel_encoder *encoder,
4417                    const struct intel_crtc_state *old_crtc_state)
4418 {
4419         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4420         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4421         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4422         enum port port = encoder->port;
4423         u32 DP = intel_dp->DP;
4424
4425         if (drm_WARN_ON(&dev_priv->drm,
4426                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4427                          DP_PORT_EN) == 0))
4428                 return;
4429
4430         drm_dbg_kms(&dev_priv->drm, "\n");
4431
4432         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4433             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4434                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4435                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4436         } else {
4437                 DP &= ~DP_LINK_TRAIN_MASK;
4438                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4439         }
4440         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4441         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4442
4443         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4444         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4445         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4446
4447         /*
4448          * HW workaround for IBX, we need to move the port
4449          * to transcoder A after disabling it to allow the
4450          * matching HDMI port to be enabled on transcoder A.
4451          */
4452         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4453                 /*
4454                  * We get CPU/PCH FIFO underruns on the other pipe when
4455                  * doing the workaround. Sweep them under the rug.
4456                  */
4457                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4458                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4459
4460                 /* always enable with pattern 1 (as per spec) */
4461                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4462                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4463                         DP_LINK_TRAIN_PAT_1;
4464                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4465                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4466
4467                 DP &= ~DP_PORT_EN;
4468                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4469                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4470
4471                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4472                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4473                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4474         }
4475
4476         msleep(intel_dp->panel_power_down_delay);
4477
4478         intel_dp->DP = DP;
4479
4480         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4481                 intel_wakeref_t wakeref;
4482
4483                 with_pps_lock(intel_dp, wakeref)
4484                         intel_dp->active_pipe = INVALID_PIPE;
4485         }
4486 }
4487
4488 static void
4489 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4490 {
4491         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4492         u8 dpcd_ext[6];
4493
4494         /*
4495          * Prior to DP1.3 the bit represented by
4496          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4497          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4498          * the true capability of the panel. The only way to check is to
4499          * then compare 0000h and 2200h.
4500          */
4501         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4502               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4503                 return;
4504
4505         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4506                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4507                 drm_err(&i915->drm,
4508                         "DPCD failed read at extended capabilities\n");
4509                 return;
4510         }
4511
4512         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4513                 drm_dbg_kms(&i915->drm,
4514                             "DPCD extended DPCD rev less than base DPCD rev\n");
4515                 return;
4516         }
4517
4518         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4519                 return;
4520
4521         drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4522                     (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4523
4524         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4525 }
4526
4527 bool
4528 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4529 {
4530         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4531
4532         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4533                              sizeof(intel_dp->dpcd)) < 0)
4534                 return false; /* aux transfer failed */
4535
4536         intel_dp_extended_receiver_capabilities(intel_dp);
4537
4538         drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4539                     intel_dp->dpcd);
4540
4541         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4542 }
4543
4544 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4545 {
4546         u8 dprx = 0;
4547
4548         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4549                               &dprx) != 1)
4550                 return false;
4551         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4552 }
4553
4554 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4555 {
4556         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4557
4558         /*
4559          * Clear the cached register set to avoid using stale values
4560          * for the sinks that do not support DSC.
4561          */
4562         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4563
4564         /* Clear fec_capable to avoid using stale values */
4565         intel_dp->fec_capable = 0;
4566
4567         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4568         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4569             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4570                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4571                                      intel_dp->dsc_dpcd,
4572                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4573                         drm_err(&i915->drm,
4574                                 "Failed to read DPCD register 0x%x\n",
4575                                 DP_DSC_SUPPORT);
4576
4577                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4578                             (int)sizeof(intel_dp->dsc_dpcd),
4579                             intel_dp->dsc_dpcd);
4580
4581                 /* FEC is supported only on DP 1.4 */
4582                 if (!intel_dp_is_edp(intel_dp) &&
4583                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4584                                       &intel_dp->fec_capable) < 0)
4585                         drm_err(&i915->drm,
4586                                 "Failed to read FEC DPCD register\n");
4587
4588                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4589                             intel_dp->fec_capable);
4590         }
4591 }
4592
4593 static bool
4594 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4595 {
4596         struct drm_i915_private *dev_priv =
4597                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4598
4599         /* this function is meant to be called only once */
4600         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4601
4602         if (!intel_dp_read_dpcd(intel_dp))
4603                 return false;
4604
4605         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4606                          drm_dp_is_branch(intel_dp->dpcd));
4607
4608         /*
4609          * Read the eDP display control registers.
4610          *
4611          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4612          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4613          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4614          * method). The display control registers should read zero if they're
4615          * not supported anyway.
4616          */
4617         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4618                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4619                              sizeof(intel_dp->edp_dpcd))
4620                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4621                             (int)sizeof(intel_dp->edp_dpcd),
4622                             intel_dp->edp_dpcd);
4623
4624         /*
4625          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4626          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4627          */
4628         intel_psr_init_dpcd(intel_dp);
4629
4630         /* Read the eDP 1.4+ supported link rates. */
4631         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4632                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4633                 int i;
4634
4635                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4636                                 sink_rates, sizeof(sink_rates));
4637
4638                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4639                         int val = le16_to_cpu(sink_rates[i]);
4640
4641                         if (val == 0)
4642                                 break;
4643
4644                         /* Value read multiplied by 200kHz gives the per-lane
4645                          * link rate in kHz. The source rates are, however,
4646                          * stored in terms of LS_Clk kHz. The full conversion
4647                          * back to symbols is
4648                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4649                          */
4650                         intel_dp->sink_rates[i] = (val * 200) / 10;
4651                 }
4652                 intel_dp->num_sink_rates = i;
4653         }
4654
4655         /*
4656          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4657          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4658          */
4659         if (intel_dp->num_sink_rates)
4660                 intel_dp->use_rate_select = true;
4661         else
4662                 intel_dp_set_sink_rates(intel_dp);
4663
4664         intel_dp_set_common_rates(intel_dp);
4665
4666         /* Read the eDP DSC DPCD registers */
4667         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4668                 intel_dp_get_dsc_sink_cap(intel_dp);
4669
4670         return true;
4671 }
4672
4673
4674 static bool
4675 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4676 {
4677         if (!intel_dp_read_dpcd(intel_dp))
4678                 return false;
4679
4680         /*
4681          * Don't clobber cached eDP rates. Also skip re-reading
4682          * the OUI/ID since we know it won't change.
4683          */
4684         if (!intel_dp_is_edp(intel_dp)) {
4685                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4686                                  drm_dp_is_branch(intel_dp->dpcd));
4687
4688                 intel_dp_set_sink_rates(intel_dp);
4689                 intel_dp_set_common_rates(intel_dp);
4690         }
4691
4692         /*
4693          * Some eDP panels do not set a valid value for sink count, that is why
4694          * it don't care about read it here and in intel_edp_init_dpcd().
4695          */
4696         if (!intel_dp_is_edp(intel_dp) &&
4697             !drm_dp_has_quirk(&intel_dp->desc, 0,
4698                               DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4699                 u8 count;
4700                 ssize_t r;
4701
4702                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4703                 if (r < 1)
4704                         return false;
4705
4706                 /*
4707                  * Sink count can change between short pulse hpd hence
4708                  * a member variable in intel_dp will track any changes
4709                  * between short pulse interrupts.
4710                  */
4711                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4712
4713                 /*
4714                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4715                  * a dongle is present but no display. Unless we require to know
4716                  * if a dongle is present or not, we don't need to update
4717                  * downstream port information. So, an early return here saves
4718                  * time from performing other operations which are not required.
4719                  */
4720                 if (!intel_dp->sink_count)
4721                         return false;
4722         }
4723
4724         if (!drm_dp_is_branch(intel_dp->dpcd))
4725                 return true; /* native DP sink */
4726
4727         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4728                 return true; /* no per-port downstream info */
4729
4730         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4731                              intel_dp->downstream_ports,
4732                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4733                 return false; /* downstream port status fetch failed */
4734
4735         return true;
4736 }
4737
4738 static bool
4739 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4740 {
4741         u8 mstm_cap;
4742
4743         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4744                 return false;
4745
4746         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4747                 return false;
4748
4749         return mstm_cap & DP_MST_CAP;
4750 }
4751
4752 static bool
4753 intel_dp_can_mst(struct intel_dp *intel_dp)
4754 {
4755         return i915_modparams.enable_dp_mst &&
4756                 intel_dp->can_mst &&
4757                 intel_dp_sink_can_mst(intel_dp);
4758 }
4759
4760 static void
4761 intel_dp_configure_mst(struct intel_dp *intel_dp)
4762 {
4763         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4764         struct intel_encoder *encoder =
4765                 &dp_to_dig_port(intel_dp)->base;
4766         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4767
4768         drm_dbg_kms(&i915->drm,
4769                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4770                     encoder->base.base.id, encoder->base.name,
4771                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
4772                     yesno(i915_modparams.enable_dp_mst));
4773
4774         if (!intel_dp->can_mst)
4775                 return;
4776
4777         intel_dp->is_mst = sink_can_mst &&
4778                 i915_modparams.enable_dp_mst;
4779
4780         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4781                                         intel_dp->is_mst);
4782 }
4783
4784 static bool
4785 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4786 {
4787         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4788                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4789                 DP_DPRX_ESI_LEN;
4790 }
4791
4792 bool
4793 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4794                        const struct drm_connector_state *conn_state)
4795 {
4796         /*
4797          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4798          * of Color Encoding Format and Content Color Gamut], in order to
4799          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4800          */
4801         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4802                 return true;
4803
4804         switch (conn_state->colorspace) {
4805         case DRM_MODE_COLORIMETRY_SYCC_601:
4806         case DRM_MODE_COLORIMETRY_OPYCC_601:
4807         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4808         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4809         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4810                 return true;
4811         default:
4812                 break;
4813         }
4814
4815         return false;
4816 }
4817
4818 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4819                                      struct dp_sdp *sdp, size_t size)
4820 {
4821         size_t length = sizeof(struct dp_sdp);
4822
4823         if (size < length)
4824                 return -ENOSPC;
4825
4826         memset(sdp, 0, size);
4827
4828         /*
4829          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4830          * VSC SDP Header Bytes
4831          */
4832         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4833         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4834         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4835         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4836
4837         /*
4838          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
4839          * per DP 1.4a spec.
4840          */
4841         if (vsc->revision != 0x5)
4842                 goto out;
4843
4844         /* VSC SDP Payload for DB16 through DB18 */
4845         /* Pixel Encoding and Colorimetry Formats  */
4846         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4847         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4848
4849         switch (vsc->bpc) {
4850         case 6:
4851                 /* 6bpc: 0x0 */
4852                 break;
4853         case 8:
4854                 sdp->db[17] = 0x1; /* DB17[3:0] */
4855                 break;
4856         case 10:
4857                 sdp->db[17] = 0x2;
4858                 break;
4859         case 12:
4860                 sdp->db[17] = 0x3;
4861                 break;
4862         case 16:
4863                 sdp->db[17] = 0x4;
4864                 break;
4865         default:
4866                 MISSING_CASE(vsc->bpc);
4867                 break;
4868         }
4869         /* Dynamic Range and Component Bit Depth */
4870         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4871                 sdp->db[17] |= 0x80;  /* DB17[7] */
4872
4873         /* Content Type */
4874         sdp->db[18] = vsc->content_type & 0x7;
4875
4876 out:
4877         return length;
4878 }
4879
4880 static ssize_t
4881 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4882                                          struct dp_sdp *sdp,
4883                                          size_t size)
4884 {
4885         size_t length = sizeof(struct dp_sdp);
4886         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4887         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4888         ssize_t len;
4889
4890         if (size < length)
4891                 return -ENOSPC;
4892
4893         memset(sdp, 0, size);
4894
4895         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4896         if (len < 0) {
4897                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4898                 return -ENOSPC;
4899         }
4900
4901         if (len != infoframe_size) {
4902                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4903                 return -ENOSPC;
4904         }
4905
4906         /*
4907          * Set up the infoframe sdp packet for HDR static metadata.
4908          * Prepare VSC Header for SU as per DP 1.4a spec,
4909          * Table 2-100 and Table 2-101
4910          */
4911
4912         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4913         sdp->sdp_header.HB0 = 0;
4914         /*
4915          * Packet Type 80h + Non-audio INFOFRAME Type value
4916          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4917          * - 80h + Non-audio INFOFRAME Type value
4918          * - InfoFrame Type: 0x07
4919          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4920          */
4921         sdp->sdp_header.HB1 = drm_infoframe->type;
4922         /*
4923          * Least Significant Eight Bits of (Data Byte Count – 1)
4924          * infoframe_size - 1
4925          */
4926         sdp->sdp_header.HB2 = 0x1D;
4927         /* INFOFRAME SDP Version Number */
4928         sdp->sdp_header.HB3 = (0x13 << 2);
4929         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4930         sdp->db[0] = drm_infoframe->version;
4931         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4932         sdp->db[1] = drm_infoframe->length;
4933         /*
4934          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4935          * HDMI_INFOFRAME_HEADER_SIZE
4936          */
4937         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4938         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4939                HDMI_DRM_INFOFRAME_SIZE);
4940
4941         /*
4942          * Size of DP infoframe sdp packet for HDR static metadata consists of
4943          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4944          * - Two Data Blocks: 2 bytes
4945          *    CTA Header Byte2 (INFOFRAME Version Number)
4946          *    CTA Header Byte3 (Length of INFOFRAME)
4947          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4948          *
4949          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4950          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4951          * will pad rest of the size.
4952          */
4953         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4954 }
4955
4956 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4957                                const struct intel_crtc_state *crtc_state,
4958                                unsigned int type)
4959 {
4960         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4961         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4962         struct dp_sdp sdp = {};
4963         ssize_t len;
4964
4965         if ((crtc_state->infoframes.enable &
4966              intel_hdmi_infoframe_enable(type)) == 0)
4967                 return;
4968
4969         switch (type) {
4970         case DP_SDP_VSC:
4971                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4972                                             sizeof(sdp));
4973                 break;
4974         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4975                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4976                                                                &sdp, sizeof(sdp));
4977                 break;
4978         default:
4979                 MISSING_CASE(type);
4980                 return;
4981         }
4982
4983         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4984                 return;
4985
4986         intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4987 }
4988
4989 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4990                             const struct intel_crtc_state *crtc_state,
4991                             struct drm_dp_vsc_sdp *vsc)
4992 {
4993         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4994         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4995         struct dp_sdp sdp = {};
4996         ssize_t len;
4997
4998         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4999
5000         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5001                 return;
5002
5003         intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5004                                         &sdp, len);
5005 }
5006
5007 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5008                              bool enable,
5009                              const struct intel_crtc_state *crtc_state,
5010                              const struct drm_connector_state *conn_state)
5011 {
5012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5013         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5014         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5015         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5016                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5017                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5018         u32 val = intel_de_read(dev_priv, reg);
5019
5020         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5021         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5022         if (intel_psr_enabled(intel_dp))
5023                 val &= ~dip_enable;
5024         else
5025                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5026
5027         if (!enable) {
5028                 intel_de_write(dev_priv, reg, val);
5029                 intel_de_posting_read(dev_priv, reg);
5030                 return;
5031         }
5032
5033         intel_de_write(dev_priv, reg, val);
5034         intel_de_posting_read(dev_priv, reg);
5035
5036         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5037         if (!intel_psr_enabled(intel_dp))
5038                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5039
5040         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5041 }
5042
5043 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5044                                    const void *buffer, size_t size)
5045 {
5046         const struct dp_sdp *sdp = buffer;
5047
5048         if (size < sizeof(struct dp_sdp))
5049                 return -EINVAL;
5050
5051         memset(vsc, 0, size);
5052
5053         if (sdp->sdp_header.HB0 != 0)
5054                 return -EINVAL;
5055
5056         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5057                 return -EINVAL;
5058
5059         vsc->sdp_type = sdp->sdp_header.HB1;
5060         vsc->revision = sdp->sdp_header.HB2;
5061         vsc->length = sdp->sdp_header.HB3;
5062
5063         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5064             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5065                 /*
5066                  * - HB2 = 0x2, HB3 = 0x8
5067                  *   VSC SDP supporting 3D stereo + PSR
5068                  * - HB2 = 0x4, HB3 = 0xe
5069                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5070                  *   first scan line of the SU region (applies to eDP v1.4b
5071                  *   and higher).
5072                  */
5073                 return 0;
5074         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5075                 /*
5076                  * - HB2 = 0x5, HB3 = 0x13
5077                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5078                  *   Format.
5079                  */
5080                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5081                 vsc->colorimetry = sdp->db[16] & 0xf;
5082                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5083
5084                 switch (sdp->db[17] & 0x7) {
5085                 case 0x0:
5086                         vsc->bpc = 6;
5087                         break;
5088                 case 0x1:
5089                         vsc->bpc = 8;
5090                         break;
5091                 case 0x2:
5092                         vsc->bpc = 10;
5093                         break;
5094                 case 0x3:
5095                         vsc->bpc = 12;
5096                         break;
5097                 case 0x4:
5098                         vsc->bpc = 16;
5099                         break;
5100                 default:
5101                         MISSING_CASE(sdp->db[17] & 0x7);
5102                         return -EINVAL;
5103                 }
5104
5105                 vsc->content_type = sdp->db[18] & 0x7;
5106         } else {
5107                 return -EINVAL;
5108         }
5109
5110         return 0;
5111 }
5112
5113 static int
5114 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5115                                            const void *buffer, size_t size)
5116 {
5117         int ret;
5118
5119         const struct dp_sdp *sdp = buffer;
5120
5121         if (size < sizeof(struct dp_sdp))
5122                 return -EINVAL;
5123
5124         if (sdp->sdp_header.HB0 != 0)
5125                 return -EINVAL;
5126
5127         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5128                 return -EINVAL;
5129
5130         /*
5131          * Least Significant Eight Bits of (Data Byte Count – 1)
5132          * 1Dh (i.e., Data Byte Count = 30 bytes).
5133          */
5134         if (sdp->sdp_header.HB2 != 0x1D)
5135                 return -EINVAL;
5136
5137         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5138         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5139                 return -EINVAL;
5140
5141         /* INFOFRAME SDP Version Number */
5142         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5143                 return -EINVAL;
5144
5145         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5146         if (sdp->db[0] != 1)
5147                 return -EINVAL;
5148
5149         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5150         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5151                 return -EINVAL;
5152
5153         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5154                                              HDMI_DRM_INFOFRAME_SIZE);
5155
5156         return ret;
5157 }
5158
5159 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5160                                   struct intel_crtc_state *crtc_state,
5161                                   struct drm_dp_vsc_sdp *vsc)
5162 {
5163         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5164         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5166         unsigned int type = DP_SDP_VSC;
5167         struct dp_sdp sdp = {};
5168         int ret;
5169
5170         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5171         if (intel_psr_enabled(intel_dp))
5172                 return;
5173
5174         if ((crtc_state->infoframes.enable &
5175              intel_hdmi_infoframe_enable(type)) == 0)
5176                 return;
5177
5178         intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5179
5180         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5181
5182         if (ret)
5183                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5184 }
5185
5186 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5187                                                      struct intel_crtc_state *crtc_state,
5188                                                      struct hdmi_drm_infoframe *drm_infoframe)
5189 {
5190         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5192         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5193         struct dp_sdp sdp = {};
5194         int ret;
5195
5196         if ((crtc_state->infoframes.enable &
5197             intel_hdmi_infoframe_enable(type)) == 0)
5198                 return;
5199
5200         intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5201                                        sizeof(sdp));
5202
5203         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5204                                                          sizeof(sdp));
5205
5206         if (ret)
5207                 drm_dbg_kms(&dev_priv->drm,
5208                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5209 }
5210
5211 void intel_read_dp_sdp(struct intel_encoder *encoder,
5212                        struct intel_crtc_state *crtc_state,
5213                        unsigned int type)
5214 {
5215         if (encoder->type != INTEL_OUTPUT_DDI)
5216                 return;
5217
5218         switch (type) {
5219         case DP_SDP_VSC:
5220                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5221                                       &crtc_state->infoframes.vsc);
5222                 break;
5223         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5224                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5225                                                          &crtc_state->infoframes.drm.drm);
5226                 break;
5227         default:
5228                 MISSING_CASE(type);
5229                 break;
5230         }
5231 }
5232
5233 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5234 {
5235         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5236         int status = 0;
5237         int test_link_rate;
5238         u8 test_lane_count, test_link_bw;
5239         /* (DP CTS 1.2)
5240          * 4.3.1.11
5241          */
5242         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5243         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5244                                    &test_lane_count);
5245
5246         if (status <= 0) {
5247                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5248                 return DP_TEST_NAK;
5249         }
5250         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5251
5252         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5253                                    &test_link_bw);
5254         if (status <= 0) {
5255                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5256                 return DP_TEST_NAK;
5257         }
5258         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5259
5260         /* Validate the requested link rate and lane count */
5261         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5262                                         test_lane_count))
5263                 return DP_TEST_NAK;
5264
5265         intel_dp->compliance.test_lane_count = test_lane_count;
5266         intel_dp->compliance.test_link_rate = test_link_rate;
5267
5268         return DP_TEST_ACK;
5269 }
5270
5271 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5272 {
5273         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5274         u8 test_pattern;
5275         u8 test_misc;
5276         __be16 h_width, v_height;
5277         int status = 0;
5278
5279         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5280         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5281                                    &test_pattern);
5282         if (status <= 0) {
5283                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5284                 return DP_TEST_NAK;
5285         }
5286         if (test_pattern != DP_COLOR_RAMP)
5287                 return DP_TEST_NAK;
5288
5289         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5290                                   &h_width, 2);
5291         if (status <= 0) {
5292                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5293                 return DP_TEST_NAK;
5294         }
5295
5296         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5297                                   &v_height, 2);
5298         if (status <= 0) {
5299                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5300                 return DP_TEST_NAK;
5301         }
5302
5303         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5304                                    &test_misc);
5305         if (status <= 0) {
5306                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5307                 return DP_TEST_NAK;
5308         }
5309         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5310                 return DP_TEST_NAK;
5311         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5312                 return DP_TEST_NAK;
5313         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5314         case DP_TEST_BIT_DEPTH_6:
5315                 intel_dp->compliance.test_data.bpc = 6;
5316                 break;
5317         case DP_TEST_BIT_DEPTH_8:
5318                 intel_dp->compliance.test_data.bpc = 8;
5319                 break;
5320         default:
5321                 return DP_TEST_NAK;
5322         }
5323
5324         intel_dp->compliance.test_data.video_pattern = test_pattern;
5325         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5326         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5327         /* Set test active flag here so userspace doesn't interrupt things */
5328         intel_dp->compliance.test_active = true;
5329
5330         return DP_TEST_ACK;
5331 }
5332
5333 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5334 {
5335         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5336         u8 test_result = DP_TEST_ACK;
5337         struct intel_connector *intel_connector = intel_dp->attached_connector;
5338         struct drm_connector *connector = &intel_connector->base;
5339
5340         if (intel_connector->detect_edid == NULL ||
5341             connector->edid_corrupt ||
5342             intel_dp->aux.i2c_defer_count > 6) {
5343                 /* Check EDID read for NACKs, DEFERs and corruption
5344                  * (DP CTS 1.2 Core r1.1)
5345                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5346                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5347                  *    4.2.2.6 : EDID corruption detected
5348                  * Use failsafe mode for all cases
5349                  */
5350                 if (intel_dp->aux.i2c_nack_count > 0 ||
5351                         intel_dp->aux.i2c_defer_count > 0)
5352                         drm_dbg_kms(&i915->drm,
5353                                     "EDID read had %d NACKs, %d DEFERs\n",
5354                                     intel_dp->aux.i2c_nack_count,
5355                                     intel_dp->aux.i2c_defer_count);
5356                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5357         } else {
5358                 struct edid *block = intel_connector->detect_edid;
5359
5360                 /* We have to write the checksum
5361                  * of the last block read
5362                  */
5363                 block += intel_connector->detect_edid->extensions;
5364
5365                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5366                                        block->checksum) <= 0)
5367                         drm_dbg_kms(&i915->drm,
5368                                     "Failed to write EDID checksum\n");
5369
5370                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5371                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5372         }
5373
5374         /* Set test active flag here so userspace doesn't interrupt things */
5375         intel_dp->compliance.test_active = true;
5376
5377         return test_result;
5378 }
5379
5380 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5381 {
5382         struct drm_dp_phy_test_params *data =
5383                 &intel_dp->compliance.test_data.phytest;
5384
5385         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5386                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5387                 return DP_TEST_NAK;
5388         }
5389
5390         /*
5391          * link_mst is set to false to avoid executing mst related code
5392          * during compliance testing.
5393          */
5394         intel_dp->link_mst = false;
5395
5396         return DP_TEST_ACK;
5397 }
5398
5399 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5400 {
5401         struct drm_i915_private *dev_priv =
5402                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5403         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5404         struct drm_dp_phy_test_params *data =
5405                         &intel_dp->compliance.test_data.phytest;
5406         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5407         enum pipe pipe = crtc->pipe;
5408         u32 pattern_val;
5409
5410         switch (data->phy_pattern) {
5411         case DP_PHY_TEST_PATTERN_NONE:
5412                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5413                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5414                 break;
5415         case DP_PHY_TEST_PATTERN_D10_2:
5416                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5417                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5418                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5419                 break;
5420         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5421                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5422                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5423                                DDI_DP_COMP_CTL_ENABLE |
5424                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5425                 break;
5426         case DP_PHY_TEST_PATTERN_PRBS7:
5427                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5428                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5429                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5430                 break;
5431         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5432                 /*
5433                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5434                  * current firmware of DPR-100 could not set it, so hardcoding
5435                  * now for complaince test.
5436                  */
5437                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5438                 pattern_val = 0x3e0f83e0;
5439                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5440                 pattern_val = 0x0f83e0f8;
5441                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5442                 pattern_val = 0x0000f83e;
5443                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5444                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5445                                DDI_DP_COMP_CTL_ENABLE |
5446                                DDI_DP_COMP_CTL_CUSTOM80);
5447                 break;
5448         case DP_PHY_TEST_PATTERN_CP2520:
5449                 /*
5450                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5451                  * current firmware of DPR-100 could not set it, so hardcoding
5452                  * now for complaince test.
5453                  */
5454                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5455                 pattern_val = 0xFB;
5456                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5457                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5458                                pattern_val);
5459                 break;
5460         default:
5461                 WARN(1, "Invalid Phy Test Pattern\n");
5462         }
5463 }
5464
5465 static void
5466 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5467 {
5468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5469         struct drm_device *dev = intel_dig_port->base.base.dev;
5470         struct drm_i915_private *dev_priv = to_i915(dev);
5471         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5472         enum pipe pipe = crtc->pipe;
5473         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5474
5475         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5476                                                  TRANS_DDI_FUNC_CTL(pipe));
5477         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5478         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5479
5480         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5481                                       TGL_TRANS_DDI_PORT_MASK);
5482         trans_conf_value &= ~PIPECONF_ENABLE;
5483         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5484
5485         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5486         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5487                        trans_ddi_func_ctl_value);
5488         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5489 }
5490
5491 static void
5492 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5493 {
5494         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5495         struct drm_device *dev = intel_dig_port->base.base.dev;
5496         struct drm_i915_private *dev_priv = to_i915(dev);
5497         enum port port = intel_dig_port->base.port;
5498         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5499         enum pipe pipe = crtc->pipe;
5500         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5501
5502         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5503                                                  TRANS_DDI_FUNC_CTL(pipe));
5504         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5505         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5506
5507         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5508                                     TGL_TRANS_DDI_SELECT_PORT(port);
5509         trans_conf_value |= PIPECONF_ENABLE;
5510         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5511
5512         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5513         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5514         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5515                        trans_ddi_func_ctl_value);
5516 }
5517
5518 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5519 {
5520         struct drm_dp_phy_test_params *data =
5521                 &intel_dp->compliance.test_data.phytest;
5522         u8 link_status[DP_LINK_STATUS_SIZE];
5523
5524         if (!intel_dp_get_link_status(intel_dp, link_status)) {
5525                 DRM_DEBUG_KMS("failed to get link status\n");
5526                 return;
5527         }
5528
5529         /* retrieve vswing & pre-emphasis setting */
5530         intel_dp_get_adjust_train(intel_dp, link_status);
5531
5532         intel_dp_autotest_phy_ddi_disable(intel_dp);
5533
5534         intel_dp_set_signal_levels(intel_dp);
5535
5536         intel_dp_phy_pattern_update(intel_dp);
5537
5538         intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5539
5540         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5541                                     link_status[DP_DPCD_REV]);
5542 }
5543
5544 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5545 {
5546         u8 test_result;
5547
5548         test_result = intel_dp_prepare_phytest(intel_dp);
5549         if (test_result != DP_TEST_ACK)
5550                 DRM_ERROR("Phy test preparation failed\n");
5551
5552         intel_dp_process_phy_request(intel_dp);
5553
5554         return test_result;
5555 }
5556
5557 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5558 {
5559         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5560         u8 response = DP_TEST_NAK;
5561         u8 request = 0;
5562         int status;
5563
5564         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5565         if (status <= 0) {
5566                 drm_dbg_kms(&i915->drm,
5567                             "Could not read test request from sink\n");
5568                 goto update_status;
5569         }
5570
5571         switch (request) {
5572         case DP_TEST_LINK_TRAINING:
5573                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5574                 response = intel_dp_autotest_link_training(intel_dp);
5575                 break;
5576         case DP_TEST_LINK_VIDEO_PATTERN:
5577                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5578                 response = intel_dp_autotest_video_pattern(intel_dp);
5579                 break;
5580         case DP_TEST_LINK_EDID_READ:
5581                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5582                 response = intel_dp_autotest_edid(intel_dp);
5583                 break;
5584         case DP_TEST_LINK_PHY_TEST_PATTERN:
5585                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5586                 response = intel_dp_autotest_phy_pattern(intel_dp);
5587                 break;
5588         default:
5589                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5590                             request);
5591                 break;
5592         }
5593
5594         if (response & DP_TEST_ACK)
5595                 intel_dp->compliance.test_type = request;
5596
5597 update_status:
5598         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5599         if (status <= 0)
5600                 drm_dbg_kms(&i915->drm,
5601                             "Could not write test response to sink\n");
5602 }
5603
5604 static int
5605 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5606 {
5607         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5608         bool need_retrain = false;
5609
5610         if (!intel_dp->is_mst)
5611                 return -EINVAL;
5612
5613         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5614
5615         for (;;) {
5616                 u8 esi[DP_DPRX_ESI_LEN] = {};
5617                 bool bret, handled;
5618                 int retry;
5619
5620                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5621                 if (!bret) {
5622                         drm_dbg_kms(&i915->drm,
5623                                     "failed to get ESI - device may have failed\n");
5624                         return -EINVAL;
5625                 }
5626
5627                 /* check link status - esi[10] = 0x200c */
5628                 if (intel_dp->active_mst_links > 0 && !need_retrain &&
5629                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5630                         drm_dbg_kms(&i915->drm,
5631                                     "channel EQ not ok, retraining\n");
5632                         need_retrain = true;
5633                 }
5634
5635                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5636
5637                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5638                 if (!handled)
5639                         break;
5640
5641                 for (retry = 0; retry < 3; retry++) {
5642                         int wret;
5643
5644                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5645                                                  DP_SINK_COUNT_ESI+1,
5646                                                  &esi[1], 3);
5647                         if (wret == 3)
5648                                 break;
5649                 }
5650         }
5651
5652         return need_retrain;
5653 }
5654
5655 static bool
5656 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5657 {
5658         u8 link_status[DP_LINK_STATUS_SIZE];
5659
5660         if (!intel_dp->link_trained)
5661                 return false;
5662
5663         /*
5664          * While PSR source HW is enabled, it will control main-link sending
5665          * frames, enabling and disabling it so trying to do a retrain will fail
5666          * as the link would or not be on or it could mix training patterns
5667          * and frame data at the same time causing retrain to fail.
5668          * Also when exiting PSR, HW will retrain the link anyways fixing
5669          * any link status error.
5670          */
5671         if (intel_psr_enabled(intel_dp))
5672                 return false;
5673
5674         if (!intel_dp_get_link_status(intel_dp, link_status))
5675                 return false;
5676
5677         /*
5678          * Validate the cached values of intel_dp->link_rate and
5679          * intel_dp->lane_count before attempting to retrain.
5680          */
5681         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5682                                         intel_dp->lane_count))
5683                 return false;
5684
5685         /* Retrain if Channel EQ or CR not ok */
5686         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5687 }
5688
5689 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5690                                    const struct drm_connector_state *conn_state)
5691 {
5692         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5693         struct intel_encoder *encoder;
5694         enum pipe pipe;
5695
5696         if (!conn_state->best_encoder)
5697                 return false;
5698
5699         /* SST */
5700         encoder = &dp_to_dig_port(intel_dp)->base;
5701         if (conn_state->best_encoder == &encoder->base)
5702                 return true;
5703
5704         /* MST */
5705         for_each_pipe(i915, pipe) {
5706                 encoder = &intel_dp->mst_encoders[pipe]->base;
5707                 if (conn_state->best_encoder == &encoder->base)
5708                         return true;
5709         }
5710
5711         return false;
5712 }
5713
5714 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5715                                       struct drm_modeset_acquire_ctx *ctx,
5716                                       u32 *crtc_mask)
5717 {
5718         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5719         struct drm_connector_list_iter conn_iter;
5720         struct intel_connector *connector;
5721         int ret = 0;
5722
5723         *crtc_mask = 0;
5724
5725         if (!intel_dp_needs_link_retrain(intel_dp))
5726                 return 0;
5727
5728         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5729         for_each_intel_connector_iter(connector, &conn_iter) {
5730                 struct drm_connector_state *conn_state =
5731                         connector->base.state;
5732                 struct intel_crtc_state *crtc_state;
5733                 struct intel_crtc *crtc;
5734
5735                 if (!intel_dp_has_connector(intel_dp, conn_state))
5736                         continue;
5737
5738                 crtc = to_intel_crtc(conn_state->crtc);
5739                 if (!crtc)
5740                         continue;
5741
5742                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5743                 if (ret)
5744                         break;
5745
5746                 crtc_state = to_intel_crtc_state(crtc->base.state);
5747
5748                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5749
5750                 if (!crtc_state->hw.active)
5751                         continue;
5752
5753                 if (conn_state->commit &&
5754                     !try_wait_for_completion(&conn_state->commit->hw_done))
5755                         continue;
5756
5757                 *crtc_mask |= drm_crtc_mask(&crtc->base);
5758         }
5759         drm_connector_list_iter_end(&conn_iter);
5760
5761         if (!intel_dp_needs_link_retrain(intel_dp))
5762                 *crtc_mask = 0;
5763
5764         return ret;
5765 }
5766
5767 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5768 {
5769         struct intel_connector *connector = intel_dp->attached_connector;
5770
5771         return connector->base.status == connector_status_connected ||
5772                 intel_dp->is_mst;
5773 }
5774
5775 int intel_dp_retrain_link(struct intel_encoder *encoder,
5776                           struct drm_modeset_acquire_ctx *ctx)
5777 {
5778         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5779         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5780         struct intel_crtc *crtc;
5781         u32 crtc_mask;
5782         int ret;
5783
5784         if (!intel_dp_is_connected(intel_dp))
5785                 return 0;
5786
5787         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5788                                ctx);
5789         if (ret)
5790                 return ret;
5791
5792         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5793         if (ret)
5794                 return ret;
5795
5796         if (crtc_mask == 0)
5797                 return 0;
5798
5799         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5800                     encoder->base.base.id, encoder->base.name);
5801
5802         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5803                 const struct intel_crtc_state *crtc_state =
5804                         to_intel_crtc_state(crtc->base.state);
5805
5806                 /* Suppress underruns caused by re-training */
5807                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5808                 if (crtc_state->has_pch_encoder)
5809                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5810                                                               intel_crtc_pch_transcoder(crtc), false);
5811         }
5812
5813         intel_dp_start_link_train(intel_dp);
5814         intel_dp_stop_link_train(intel_dp);
5815
5816         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5817                 const struct intel_crtc_state *crtc_state =
5818                         to_intel_crtc_state(crtc->base.state);
5819
5820                 /* Keep underrun reporting disabled until things are stable */
5821                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5822
5823                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5824                 if (crtc_state->has_pch_encoder)
5825                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5826                                                               intel_crtc_pch_transcoder(crtc), true);
5827         }
5828
5829         return 0;
5830 }
5831
5832 /*
5833  * If display is now connected check links status,
5834  * there has been known issues of link loss triggering
5835  * long pulse.
5836  *
5837  * Some sinks (eg. ASUS PB287Q) seem to perform some
5838  * weird HPD ping pong during modesets. So we can apparently
5839  * end up with HPD going low during a modeset, and then
5840  * going back up soon after. And once that happens we must
5841  * retrain the link to get a picture. That's in case no
5842  * userspace component reacted to intermittent HPD dip.
5843  */
5844 static enum intel_hotplug_state
5845 intel_dp_hotplug(struct intel_encoder *encoder,
5846                  struct intel_connector *connector)
5847 {
5848         struct drm_modeset_acquire_ctx ctx;
5849         enum intel_hotplug_state state;
5850         int ret;
5851
5852         state = intel_encoder_hotplug(encoder, connector);
5853
5854         drm_modeset_acquire_init(&ctx, 0);
5855
5856         for (;;) {
5857                 ret = intel_dp_retrain_link(encoder, &ctx);
5858
5859                 if (ret == -EDEADLK) {
5860                         drm_modeset_backoff(&ctx);
5861                         continue;
5862                 }
5863
5864                 break;
5865         }
5866
5867         drm_modeset_drop_locks(&ctx);
5868         drm_modeset_acquire_fini(&ctx);
5869         drm_WARN(encoder->base.dev, ret,
5870                  "Acquiring modeset locks failed with %i\n", ret);
5871
5872         /*
5873          * Keeping it consistent with intel_ddi_hotplug() and
5874          * intel_hdmi_hotplug().
5875          */
5876         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5877                 state = INTEL_HOTPLUG_RETRY;
5878
5879         return state;
5880 }
5881
5882 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5883 {
5884         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5885         u8 val;
5886
5887         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5888                 return;
5889
5890         if (drm_dp_dpcd_readb(&intel_dp->aux,
5891                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5892                 return;
5893
5894         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5895
5896         if (val & DP_AUTOMATED_TEST_REQUEST)
5897                 intel_dp_handle_test_request(intel_dp);
5898
5899         if (val & DP_CP_IRQ)
5900                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5901
5902         if (val & DP_SINK_SPECIFIC_IRQ)
5903                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5904 }
5905
5906 /*
5907  * According to DP spec
5908  * 5.1.2:
5909  *  1. Read DPCD
5910  *  2. Configure link according to Receiver Capabilities
5911  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5912  *  4. Check link status on receipt of hot-plug interrupt
5913  *
5914  * intel_dp_short_pulse -  handles short pulse interrupts
5915  * when full detection is not required.
5916  * Returns %true if short pulse is handled and full detection
5917  * is NOT required and %false otherwise.
5918  */
5919 static bool
5920 intel_dp_short_pulse(struct intel_dp *intel_dp)
5921 {
5922         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5923         u8 old_sink_count = intel_dp->sink_count;
5924         bool ret;
5925
5926         /*
5927          * Clearing compliance test variables to allow capturing
5928          * of values for next automated test request.
5929          */
5930         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5931
5932         /*
5933          * Now read the DPCD to see if it's actually running
5934          * If the current value of sink count doesn't match with
5935          * the value that was stored earlier or dpcd read failed
5936          * we need to do full detection
5937          */
5938         ret = intel_dp_get_dpcd(intel_dp);
5939
5940         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5941                 /* No need to proceed if we are going to do full detect */
5942                 return false;
5943         }
5944
5945         intel_dp_check_service_irq(intel_dp);
5946
5947         /* Handle CEC interrupts, if any */
5948         drm_dp_cec_irq(&intel_dp->aux);
5949
5950         /* defer to the hotplug work for link retraining if needed */
5951         if (intel_dp_needs_link_retrain(intel_dp))
5952                 return false;
5953
5954         intel_psr_short_pulse(intel_dp);
5955
5956         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5957                 drm_dbg_kms(&dev_priv->drm,
5958                             "Link Training Compliance Test requested\n");
5959                 /* Send a Hotplug Uevent to userspace to start modeset */
5960                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5961         }
5962
5963         return true;
5964 }
5965
5966 /* XXX this is probably wrong for multiple downstream ports */
5967 static enum drm_connector_status
5968 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5969 {
5970         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5971         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5972         u8 *dpcd = intel_dp->dpcd;
5973         u8 type;
5974
5975         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5976                 return connector_status_connected;
5977
5978         if (lspcon->active)
5979                 lspcon_resume(lspcon);
5980
5981         if (!intel_dp_get_dpcd(intel_dp))
5982                 return connector_status_disconnected;
5983
5984         /* if there's no downstream port, we're done */
5985         if (!drm_dp_is_branch(dpcd))
5986                 return connector_status_connected;
5987
5988         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5989         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5990             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5991
5992                 return intel_dp->sink_count ?
5993                 connector_status_connected : connector_status_disconnected;
5994         }
5995
5996         if (intel_dp_can_mst(intel_dp))
5997                 return connector_status_connected;
5998
5999         /* If no HPD, poke DDC gently */
6000         if (drm_probe_ddc(&intel_dp->aux.ddc))
6001                 return connector_status_connected;
6002
6003         /* Well we tried, say unknown for unreliable port types */
6004         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6005                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6006                 if (type == DP_DS_PORT_TYPE_VGA ||
6007                     type == DP_DS_PORT_TYPE_NON_EDID)
6008                         return connector_status_unknown;
6009         } else {
6010                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6011                         DP_DWN_STRM_PORT_TYPE_MASK;
6012                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6013                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6014                         return connector_status_unknown;
6015         }
6016
6017         /* Anything else is out of spec, warn and ignore */
6018         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6019         return connector_status_disconnected;
6020 }
6021
6022 static enum drm_connector_status
6023 edp_detect(struct intel_dp *intel_dp)
6024 {
6025         return connector_status_connected;
6026 }
6027
6028 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6029 {
6030         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6031         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6032
6033         return intel_de_read(dev_priv, SDEISR) & bit;
6034 }
6035
6036 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6037 {
6038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6039         u32 bit;
6040
6041         switch (encoder->hpd_pin) {
6042         case HPD_PORT_B:
6043                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6044                 break;
6045         case HPD_PORT_C:
6046                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6047                 break;
6048         case HPD_PORT_D:
6049                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6050                 break;
6051         default:
6052                 MISSING_CASE(encoder->hpd_pin);
6053                 return false;
6054         }
6055
6056         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6057 }
6058
6059 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6060 {
6061         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6062         u32 bit;
6063
6064         switch (encoder->hpd_pin) {
6065         case HPD_PORT_B:
6066                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6067                 break;
6068         case HPD_PORT_C:
6069                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6070                 break;
6071         case HPD_PORT_D:
6072                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6073                 break;
6074         default:
6075                 MISSING_CASE(encoder->hpd_pin);
6076                 return false;
6077         }
6078
6079         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6080 }
6081
6082 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6083 {
6084         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6085         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6086
6087         return intel_de_read(dev_priv, DEISR) & bit;
6088 }
6089
6090 /*
6091  * intel_digital_port_connected - is the specified port connected?
6092  * @encoder: intel_encoder
6093  *
6094  * In cases where there's a connector physically connected but it can't be used
6095  * by our hardware we also return false, since the rest of the driver should
6096  * pretty much treat the port as disconnected. This is relevant for type-C
6097  * (starting on ICL) where there's ownership involved.
6098  *
6099  * Return %true if port is connected, %false otherwise.
6100  */
6101 bool intel_digital_port_connected(struct intel_encoder *encoder)
6102 {
6103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6104         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6105         bool is_connected = false;
6106         intel_wakeref_t wakeref;
6107
6108         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6109                 is_connected = dig_port->connected(encoder);
6110
6111         return is_connected;
6112 }
6113
6114 static struct edid *
6115 intel_dp_get_edid(struct intel_dp *intel_dp)
6116 {
6117         struct intel_connector *intel_connector = intel_dp->attached_connector;
6118
6119         /* use cached edid if we have one */
6120         if (intel_connector->edid) {
6121                 /* invalid edid */
6122                 if (IS_ERR(intel_connector->edid))
6123                         return NULL;
6124
6125                 return drm_edid_duplicate(intel_connector->edid);
6126         } else
6127                 return drm_get_edid(&intel_connector->base,
6128                                     &intel_dp->aux.ddc);
6129 }
6130
6131 static void
6132 intel_dp_set_edid(struct intel_dp *intel_dp)
6133 {
6134         struct intel_connector *intel_connector = intel_dp->attached_connector;
6135         struct edid *edid;
6136
6137         intel_dp_unset_edid(intel_dp);
6138         edid = intel_dp_get_edid(intel_dp);
6139         intel_connector->detect_edid = edid;
6140
6141         intel_dp->has_audio = drm_detect_monitor_audio(edid);
6142         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6143         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6144 }
6145
6146 static void
6147 intel_dp_unset_edid(struct intel_dp *intel_dp)
6148 {
6149         struct intel_connector *intel_connector = intel_dp->attached_connector;
6150
6151         drm_dp_cec_unset_edid(&intel_dp->aux);
6152         kfree(intel_connector->detect_edid);
6153         intel_connector->detect_edid = NULL;
6154
6155         intel_dp->has_audio = false;
6156         intel_dp->edid_quirks = 0;
6157 }
6158
6159 static int
6160 intel_dp_detect(struct drm_connector *connector,
6161                 struct drm_modeset_acquire_ctx *ctx,
6162                 bool force)
6163 {
6164         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6165         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6166         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6167         struct intel_encoder *encoder = &dig_port->base;
6168         enum drm_connector_status status;
6169
6170         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6171                     connector->base.id, connector->name);
6172         drm_WARN_ON(&dev_priv->drm,
6173                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6174
6175         /* Can't disconnect eDP */
6176         if (intel_dp_is_edp(intel_dp))
6177                 status = edp_detect(intel_dp);
6178         else if (intel_digital_port_connected(encoder))
6179                 status = intel_dp_detect_dpcd(intel_dp);
6180         else
6181                 status = connector_status_disconnected;
6182
6183         if (status == connector_status_disconnected) {
6184                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6185                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6186
6187                 if (intel_dp->is_mst) {
6188                         drm_dbg_kms(&dev_priv->drm,
6189                                     "MST device may have disappeared %d vs %d\n",
6190                                     intel_dp->is_mst,
6191                                     intel_dp->mst_mgr.mst_state);
6192                         intel_dp->is_mst = false;
6193                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6194                                                         intel_dp->is_mst);
6195                 }
6196
6197                 goto out;
6198         }
6199
6200         if (intel_dp->reset_link_params) {
6201                 /* Initial max link lane count */
6202                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6203
6204                 /* Initial max link rate */
6205                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6206
6207                 intel_dp->reset_link_params = false;
6208         }
6209
6210         intel_dp_print_rates(intel_dp);
6211
6212         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6213         if (INTEL_GEN(dev_priv) >= 11)
6214                 intel_dp_get_dsc_sink_cap(intel_dp);
6215
6216         intel_dp_configure_mst(intel_dp);
6217
6218         if (intel_dp->is_mst) {
6219                 /*
6220                  * If we are in MST mode then this connector
6221                  * won't appear connected or have anything
6222                  * with EDID on it
6223                  */
6224                 status = connector_status_disconnected;
6225                 goto out;
6226         }
6227
6228         /*
6229          * Some external monitors do not signal loss of link synchronization
6230          * with an IRQ_HPD, so force a link status check.
6231          */
6232         if (!intel_dp_is_edp(intel_dp)) {
6233                 int ret;
6234
6235                 ret = intel_dp_retrain_link(encoder, ctx);
6236                 if (ret)
6237                         return ret;
6238         }
6239
6240         /*
6241          * Clearing NACK and defer counts to get their exact values
6242          * while reading EDID which are required by Compliance tests
6243          * 4.2.2.4 and 4.2.2.5
6244          */
6245         intel_dp->aux.i2c_nack_count = 0;
6246         intel_dp->aux.i2c_defer_count = 0;
6247
6248         intel_dp_set_edid(intel_dp);
6249         if (intel_dp_is_edp(intel_dp) ||
6250             to_intel_connector(connector)->detect_edid)
6251                 status = connector_status_connected;
6252
6253         intel_dp_check_service_irq(intel_dp);
6254
6255 out:
6256         if (status != connector_status_connected && !intel_dp->is_mst)
6257                 intel_dp_unset_edid(intel_dp);
6258
6259         /*
6260          * Make sure the refs for power wells enabled during detect are
6261          * dropped to avoid a new detect cycle triggered by HPD polling.
6262          */
6263         intel_display_power_flush_work(dev_priv);
6264
6265         return status;
6266 }
6267
6268 static void
6269 intel_dp_force(struct drm_connector *connector)
6270 {
6271         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6272         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6273         struct intel_encoder *intel_encoder = &dig_port->base;
6274         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6275         enum intel_display_power_domain aux_domain =
6276                 intel_aux_power_domain(dig_port);
6277         intel_wakeref_t wakeref;
6278
6279         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6280                     connector->base.id, connector->name);
6281         intel_dp_unset_edid(intel_dp);
6282
6283         if (connector->status != connector_status_connected)
6284                 return;
6285
6286         wakeref = intel_display_power_get(dev_priv, aux_domain);
6287
6288         intel_dp_set_edid(intel_dp);
6289
6290         intel_display_power_put(dev_priv, aux_domain, wakeref);
6291 }
6292
6293 static int intel_dp_get_modes(struct drm_connector *connector)
6294 {
6295         struct intel_connector *intel_connector = to_intel_connector(connector);
6296         struct edid *edid;
6297
6298         edid = intel_connector->detect_edid;
6299         if (edid) {
6300                 int ret = intel_connector_update_modes(connector, edid);
6301                 if (ret)
6302                         return ret;
6303         }
6304
6305         /* if eDP has no EDID, fall back to fixed mode */
6306         if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6307             intel_connector->panel.fixed_mode) {
6308                 struct drm_display_mode *mode;
6309
6310                 mode = drm_mode_duplicate(connector->dev,
6311                                           intel_connector->panel.fixed_mode);
6312                 if (mode) {
6313                         drm_mode_probed_add(connector, mode);
6314                         return 1;
6315                 }
6316         }
6317
6318         return 0;
6319 }
6320
6321 static int
6322 intel_dp_connector_register(struct drm_connector *connector)
6323 {
6324         struct drm_i915_private *i915 = to_i915(connector->dev);
6325         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6326         int ret;
6327
6328         ret = intel_connector_register(connector);
6329         if (ret)
6330                 return ret;
6331
6332         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6333                     intel_dp->aux.name, connector->kdev->kobj.name);
6334
6335         intel_dp->aux.dev = connector->kdev;
6336         ret = drm_dp_aux_register(&intel_dp->aux);
6337         if (!ret)
6338                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6339         return ret;
6340 }
6341
6342 static void
6343 intel_dp_connector_unregister(struct drm_connector *connector)
6344 {
6345         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6346
6347         drm_dp_cec_unregister_connector(&intel_dp->aux);
6348         drm_dp_aux_unregister(&intel_dp->aux);
6349         intel_connector_unregister(connector);
6350 }
6351
6352 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6353 {
6354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6355         struct intel_dp *intel_dp = &intel_dig_port->dp;
6356
6357         intel_dp_mst_encoder_cleanup(intel_dig_port);
6358         if (intel_dp_is_edp(intel_dp)) {
6359                 intel_wakeref_t wakeref;
6360
6361                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6362                 /*
6363                  * vdd might still be enabled do to the delayed vdd off.
6364                  * Make sure vdd is actually turned off here.
6365                  */
6366                 with_pps_lock(intel_dp, wakeref)
6367                         edp_panel_vdd_off_sync(intel_dp);
6368
6369                 if (intel_dp->edp_notifier.notifier_call) {
6370                         unregister_reboot_notifier(&intel_dp->edp_notifier);
6371                         intel_dp->edp_notifier.notifier_call = NULL;
6372                 }
6373         }
6374
6375         intel_dp_aux_fini(intel_dp);
6376 }
6377
6378 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6379 {
6380         intel_dp_encoder_flush_work(encoder);
6381
6382         drm_encoder_cleanup(encoder);
6383         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6384 }
6385
6386 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6387 {
6388         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6389         intel_wakeref_t wakeref;
6390
6391         if (!intel_dp_is_edp(intel_dp))
6392                 return;
6393
6394         /*
6395          * vdd might still be enabled do to the delayed vdd off.
6396          * Make sure vdd is actually turned off here.
6397          */
6398         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6399         with_pps_lock(intel_dp, wakeref)
6400                 edp_panel_vdd_off_sync(intel_dp);
6401 }
6402
6403 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6404 {
6405         long ret;
6406
6407 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6408         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6409                                                msecs_to_jiffies(timeout));
6410
6411         if (!ret)
6412                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6413 }
6414
6415 static
6416 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6417                                 u8 *an)
6418 {
6419         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6420         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6421         static const struct drm_dp_aux_msg msg = {
6422                 .request = DP_AUX_NATIVE_WRITE,
6423                 .address = DP_AUX_HDCP_AKSV,
6424                 .size = DRM_HDCP_KSV_LEN,
6425         };
6426         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6427         ssize_t dpcd_ret;
6428         int ret;
6429
6430         /* Output An first, that's easy */
6431         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6432                                      an, DRM_HDCP_AN_LEN);
6433         if (dpcd_ret != DRM_HDCP_AN_LEN) {
6434                 drm_dbg_kms(&i915->drm,
6435                             "Failed to write An over DP/AUX (%zd)\n",
6436                             dpcd_ret);
6437                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6438         }
6439
6440         /*
6441          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6442          * order to get it on the wire, we need to create the AUX header as if
6443          * we were writing the data, and then tickle the hardware to output the
6444          * data once the header is sent out.
6445          */
6446         intel_dp_aux_header(txbuf, &msg);
6447
6448         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6449                                 rxbuf, sizeof(rxbuf),
6450                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6451         if (ret < 0) {
6452                 drm_dbg_kms(&i915->drm,
6453                             "Write Aksv over DP/AUX failed (%d)\n", ret);
6454                 return ret;
6455         } else if (ret == 0) {
6456                 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6457                 return -EIO;
6458         }
6459
6460         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6461         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6462                 drm_dbg_kms(&i915->drm,
6463                             "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6464                             reply);
6465                 return -EIO;
6466         }
6467         return 0;
6468 }
6469
6470 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6471                                    u8 *bksv)
6472 {
6473         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6474         ssize_t ret;
6475
6476         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6477                                DRM_HDCP_KSV_LEN);
6478         if (ret != DRM_HDCP_KSV_LEN) {
6479                 drm_dbg_kms(&i915->drm,
6480                             "Read Bksv from DP/AUX failed (%zd)\n", ret);
6481                 return ret >= 0 ? -EIO : ret;
6482         }
6483         return 0;
6484 }
6485
6486 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6487                                       u8 *bstatus)
6488 {
6489         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6490         ssize_t ret;
6491
6492         /*
6493          * For some reason the HDMI and DP HDCP specs call this register
6494          * definition by different names. In the HDMI spec, it's called BSTATUS,
6495          * but in DP it's called BINFO.
6496          */
6497         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6498                                bstatus, DRM_HDCP_BSTATUS_LEN);
6499         if (ret != DRM_HDCP_BSTATUS_LEN) {
6500                 drm_dbg_kms(&i915->drm,
6501                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6502                 return ret >= 0 ? -EIO : ret;
6503         }
6504         return 0;
6505 }
6506
6507 static
6508 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6509                              u8 *bcaps)
6510 {
6511         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6512         ssize_t ret;
6513
6514         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6515                                bcaps, 1);
6516         if (ret != 1) {
6517                 drm_dbg_kms(&i915->drm,
6518                             "Read bcaps from DP/AUX failed (%zd)\n", ret);
6519                 return ret >= 0 ? -EIO : ret;
6520         }
6521
6522         return 0;
6523 }
6524
6525 static
6526 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6527                                    bool *repeater_present)
6528 {
6529         ssize_t ret;
6530         u8 bcaps;
6531
6532         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6533         if (ret)
6534                 return ret;
6535
6536         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6537         return 0;
6538 }
6539
6540 static
6541 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6542                                 u8 *ri_prime)
6543 {
6544         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6545         ssize_t ret;
6546
6547         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6548                                ri_prime, DRM_HDCP_RI_LEN);
6549         if (ret != DRM_HDCP_RI_LEN) {
6550                 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6551                             ret);
6552                 return ret >= 0 ? -EIO : ret;
6553         }
6554         return 0;
6555 }
6556
6557 static
6558 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6559                                  bool *ksv_ready)
6560 {
6561         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6562         ssize_t ret;
6563         u8 bstatus;
6564
6565         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6566                                &bstatus, 1);
6567         if (ret != 1) {
6568                 drm_dbg_kms(&i915->drm,
6569                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6570                 return ret >= 0 ? -EIO : ret;
6571         }
6572         *ksv_ready = bstatus & DP_BSTATUS_READY;
6573         return 0;
6574 }
6575
6576 static
6577 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6578                                 int num_downstream, u8 *ksv_fifo)
6579 {
6580         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6581         ssize_t ret;
6582         int i;
6583
6584         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6585         for (i = 0; i < num_downstream; i += 3) {
6586                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6587                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6588                                        DP_AUX_HDCP_KSV_FIFO,
6589                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
6590                                        len);
6591                 if (ret != len) {
6592                         drm_dbg_kms(&i915->drm,
6593                                     "Read ksv[%d] from DP/AUX failed (%zd)\n",
6594                                     i, ret);
6595                         return ret >= 0 ? -EIO : ret;
6596                 }
6597         }
6598         return 0;
6599 }
6600
6601 static
6602 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6603                                     int i, u32 *part)
6604 {
6605         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6606         ssize_t ret;
6607
6608         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6609                 return -EINVAL;
6610
6611         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6612                                DP_AUX_HDCP_V_PRIME(i), part,
6613                                DRM_HDCP_V_PRIME_PART_LEN);
6614         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6615                 drm_dbg_kms(&i915->drm,
6616                             "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6617                 return ret >= 0 ? -EIO : ret;
6618         }
6619         return 0;
6620 }
6621
6622 static
6623 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6624                                     bool enable)
6625 {
6626         /* Not used for single stream DisplayPort setups */
6627         return 0;
6628 }
6629
6630 static
6631 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6632 {
6633         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6634         ssize_t ret;
6635         u8 bstatus;
6636
6637         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6638                                &bstatus, 1);
6639         if (ret != 1) {
6640                 drm_dbg_kms(&i915->drm,
6641                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6642                 return false;
6643         }
6644
6645         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6646 }
6647
6648 static
6649 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6650                           bool *hdcp_capable)
6651 {
6652         ssize_t ret;
6653         u8 bcaps;
6654
6655         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6656         if (ret)
6657                 return ret;
6658
6659         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6660         return 0;
6661 }
6662
6663 struct hdcp2_dp_errata_stream_type {
6664         u8      msg_id;
6665         u8      stream_type;
6666 } __packed;
6667
6668 struct hdcp2_dp_msg_data {
6669         u8 msg_id;
6670         u32 offset;
6671         bool msg_detectable;
6672         u32 timeout;
6673         u32 timeout2; /* Added for non_paired situation */
6674 };
6675
6676 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6677         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6678         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6679           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6680         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6681           false, 0, 0 },
6682         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6683           false, 0, 0 },
6684         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6685           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6686           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6687         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6688           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6689           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6690         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6691         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6692           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6693         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6694           0, 0 },
6695         { HDCP_2_2_REP_SEND_RECVID_LIST,
6696           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6697           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6698         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6699           0, 0 },
6700         { HDCP_2_2_REP_STREAM_MANAGE,
6701           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6702           0, 0 },
6703         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6704           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6705 /* local define to shovel this through the write_2_2 interface */
6706 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
6707         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6708           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6709           0, 0 },
6710 };
6711
6712 static int
6713 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6714                               u8 *rx_status)
6715 {
6716         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6717         ssize_t ret;
6718
6719         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6720                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6721                                HDCP_2_2_DP_RXSTATUS_LEN);
6722         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6723                 drm_dbg_kms(&i915->drm,
6724                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6725                 return ret >= 0 ? -EIO : ret;
6726         }
6727
6728         return 0;
6729 }
6730
6731 static
6732 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6733                                   u8 msg_id, bool *msg_ready)
6734 {
6735         u8 rx_status;
6736         int ret;
6737
6738         *msg_ready = false;
6739         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6740         if (ret < 0)
6741                 return ret;
6742
6743         switch (msg_id) {
6744         case HDCP_2_2_AKE_SEND_HPRIME:
6745                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6746                         *msg_ready = true;
6747                 break;
6748         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6749                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6750                         *msg_ready = true;
6751                 break;
6752         case HDCP_2_2_REP_SEND_RECVID_LIST:
6753                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6754                         *msg_ready = true;
6755                 break;
6756         default:
6757                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6758                 return -EINVAL;
6759         }
6760
6761         return 0;
6762 }
6763
6764 static ssize_t
6765 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6766                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6767 {
6768         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6769         struct intel_dp *dp = &intel_dig_port->dp;
6770         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6771         u8 msg_id = hdcp2_msg_data->msg_id;
6772         int ret, timeout;
6773         bool msg_ready = false;
6774
6775         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6776                 timeout = hdcp2_msg_data->timeout2;
6777         else
6778                 timeout = hdcp2_msg_data->timeout;
6779
6780         /*
6781          * There is no way to detect the CERT, LPRIME and STREAM_READY
6782          * availability. So Wait for timeout and read the msg.
6783          */
6784         if (!hdcp2_msg_data->msg_detectable) {
6785                 mdelay(timeout);
6786                 ret = 0;
6787         } else {
6788                 /*
6789                  * As we want to check the msg availability at timeout, Ignoring
6790                  * the timeout at wait for CP_IRQ.
6791                  */
6792                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6793                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6794                                                     msg_id, &msg_ready);
6795                 if (!msg_ready)
6796                         ret = -ETIMEDOUT;
6797         }
6798
6799         if (ret)
6800                 drm_dbg_kms(&i915->drm,
6801                             "msg_id %d, ret %d, timeout(mSec): %d\n",
6802                             hdcp2_msg_data->msg_id, ret, timeout);
6803
6804         return ret;
6805 }
6806
6807 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6808 {
6809         int i;
6810
6811         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6812                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6813                         return &hdcp2_dp_msg_data[i];
6814
6815         return NULL;
6816 }
6817
6818 static
6819 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6820                              void *buf, size_t size)
6821 {
6822         struct intel_dp *dp = &intel_dig_port->dp;
6823         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6824         unsigned int offset;
6825         u8 *byte = buf;
6826         ssize_t ret, bytes_to_write, len;
6827         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6828
6829         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6830         if (!hdcp2_msg_data)
6831                 return -EINVAL;
6832
6833         offset = hdcp2_msg_data->offset;
6834
6835         /* No msg_id in DP HDCP2.2 msgs */
6836         bytes_to_write = size - 1;
6837         byte++;
6838
6839         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6840
6841         while (bytes_to_write) {
6842                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6843                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6844
6845                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6846                                         offset, (void *)byte, len);
6847                 if (ret < 0)
6848                         return ret;
6849
6850                 bytes_to_write -= ret;
6851                 byte += ret;
6852                 offset += ret;
6853         }
6854
6855         return size;
6856 }
6857
6858 static
6859 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6860 {
6861         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6862         u32 dev_cnt;
6863         ssize_t ret;
6864
6865         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6866                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6867                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6868         if (ret != HDCP_2_2_RXINFO_LEN)
6869                 return ret >= 0 ? -EIO : ret;
6870
6871         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6872                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6873
6874         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6875                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6876
6877         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6878                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6879                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6880
6881         return ret;
6882 }
6883
6884 static
6885 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6886                             u8 msg_id, void *buf, size_t size)
6887 {
6888         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6889         unsigned int offset;
6890         u8 *byte = buf;
6891         ssize_t ret, bytes_to_recv, len;
6892         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6893
6894         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6895         if (!hdcp2_msg_data)
6896                 return -EINVAL;
6897         offset = hdcp2_msg_data->offset;
6898
6899         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6900         if (ret < 0)
6901                 return ret;
6902
6903         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6904                 ret = get_receiver_id_list_size(intel_dig_port);
6905                 if (ret < 0)
6906                         return ret;
6907
6908                 size = ret;
6909         }
6910         bytes_to_recv = size - 1;
6911
6912         /* DP adaptation msgs has no msg_id */
6913         byte++;
6914
6915         while (bytes_to_recv) {
6916                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6917                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6918
6919                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6920                                        (void *)byte, len);
6921                 if (ret < 0) {
6922                         drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
6923                                     msg_id, ret);
6924                         return ret;
6925                 }
6926
6927                 bytes_to_recv -= ret;
6928                 byte += ret;
6929                 offset += ret;
6930         }
6931         byte = buf;
6932         *byte = msg_id;
6933
6934         return size;
6935 }
6936
6937 static
6938 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6939                                       bool is_repeater, u8 content_type)
6940 {
6941         int ret;
6942         struct hdcp2_dp_errata_stream_type stream_type_msg;
6943
6944         if (is_repeater)
6945                 return 0;
6946
6947         /*
6948          * Errata for DP: As Stream type is used for encryption, Receiver
6949          * should be communicated with stream type for the decryption of the
6950          * content.
6951          * Repeater will be communicated with stream type as a part of it's
6952          * auth later in time.
6953          */
6954         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6955         stream_type_msg.stream_type = content_type;
6956
6957         ret =  intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6958                                         sizeof(stream_type_msg));
6959
6960         return ret < 0 ? ret : 0;
6961
6962 }
6963
6964 static
6965 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6966 {
6967         u8 rx_status;
6968         int ret;
6969
6970         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6971         if (ret)
6972                 return ret;
6973
6974         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6975                 ret = HDCP_REAUTH_REQUEST;
6976         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6977                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6978         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6979                 ret = HDCP_TOPOLOGY_CHANGE;
6980
6981         return ret;
6982 }
6983
6984 static
6985 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6986                            bool *capable)
6987 {
6988         u8 rx_caps[3];
6989         int ret;
6990
6991         *capable = false;
6992         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6993                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6994                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6995         if (ret != HDCP_2_2_RXCAPS_LEN)
6996                 return ret >= 0 ? -EIO : ret;
6997
6998         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6999             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
7000                 *capable = true;
7001
7002         return 0;
7003 }
7004
7005 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
7006         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
7007         .read_bksv = intel_dp_hdcp_read_bksv,
7008         .read_bstatus = intel_dp_hdcp_read_bstatus,
7009         .repeater_present = intel_dp_hdcp_repeater_present,
7010         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
7011         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
7012         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
7013         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
7014         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
7015         .check_link = intel_dp_hdcp_check_link,
7016         .hdcp_capable = intel_dp_hdcp_capable,
7017         .write_2_2_msg = intel_dp_hdcp2_write_msg,
7018         .read_2_2_msg = intel_dp_hdcp2_read_msg,
7019         .config_stream_type = intel_dp_hdcp2_config_stream_type,
7020         .check_2_2_link = intel_dp_hdcp2_check_link,
7021         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
7022         .protocol = HDCP_PROTOCOL_DP,
7023 };
7024
7025 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7026 {
7027         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7028         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7029
7030         lockdep_assert_held(&dev_priv->pps_mutex);
7031
7032         if (!edp_have_panel_vdd(intel_dp))
7033                 return;
7034
7035         /*
7036          * The VDD bit needs a power domain reference, so if the bit is
7037          * already enabled when we boot or resume, grab this reference and
7038          * schedule a vdd off, so we don't hold on to the reference
7039          * indefinitely.
7040          */
7041         drm_dbg_kms(&dev_priv->drm,
7042                     "VDD left on by BIOS, adjusting state tracking\n");
7043         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7044
7045         edp_panel_vdd_schedule_off(intel_dp);
7046 }
7047
7048 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7049 {
7050         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7051         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7052         enum pipe pipe;
7053
7054         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7055                                   encoder->port, &pipe))
7056                 return pipe;
7057
7058         return INVALID_PIPE;
7059 }
7060
7061 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7062 {
7063         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7064         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7065         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7066         intel_wakeref_t wakeref;
7067
7068         if (!HAS_DDI(dev_priv))
7069                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7070
7071         if (lspcon->active)
7072                 lspcon_resume(lspcon);
7073
7074         intel_dp->reset_link_params = true;
7075
7076         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7077             !intel_dp_is_edp(intel_dp))
7078                 return;
7079
7080         with_pps_lock(intel_dp, wakeref) {
7081                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7082                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7083
7084                 if (intel_dp_is_edp(intel_dp)) {
7085                         /*
7086                          * Reinit the power sequencer, in case BIOS did
7087                          * something nasty with it.
7088                          */
7089                         intel_dp_pps_init(intel_dp);
7090                         intel_edp_panel_vdd_sanitize(intel_dp);
7091                 }
7092         }
7093 }
7094
7095 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7096                                     int tile_group_id)
7097 {
7098         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7099         struct drm_connector_list_iter conn_iter;
7100         struct drm_connector *connector;
7101         int ret = 0;
7102
7103         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7104         drm_for_each_connector_iter(connector, &conn_iter) {
7105                 struct drm_connector_state *conn_state;
7106                 struct intel_crtc_state *crtc_state;
7107                 struct intel_crtc *crtc;
7108
7109                 if (!connector->has_tile ||
7110                     connector->tile_group->id != tile_group_id)
7111                         continue;
7112
7113                 conn_state = drm_atomic_get_connector_state(&state->base,
7114                                                             connector);
7115                 if (IS_ERR(conn_state)) {
7116                         ret = PTR_ERR(conn_state);
7117                         break;
7118                 }
7119
7120                 crtc = to_intel_crtc(conn_state->crtc);
7121
7122                 if (!crtc)
7123                         continue;
7124
7125                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7126                 crtc_state->uapi.mode_changed = true;
7127
7128                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7129                 if (ret)
7130                         break;
7131         }
7132         drm_connector_list_iter_end(&conn_iter);
7133
7134         return ret;
7135 }
7136
7137 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7138 {
7139         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7140         struct intel_crtc *crtc;
7141
7142         if (transcoders == 0)
7143                 return 0;
7144
7145         for_each_intel_crtc(&dev_priv->drm, crtc) {
7146                 struct intel_crtc_state *crtc_state;
7147                 int ret;
7148
7149                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7150                 if (IS_ERR(crtc_state))
7151                         return PTR_ERR(crtc_state);
7152
7153                 if (!crtc_state->hw.enable)
7154                         continue;
7155
7156                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7157                         continue;
7158
7159                 crtc_state->uapi.mode_changed = true;
7160
7161                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7162                 if (ret)
7163                         return ret;
7164
7165                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7166                 if (ret)
7167                         return ret;
7168
7169                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7170         }
7171
7172         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7173
7174         return 0;
7175 }
7176
7177 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7178                                       struct drm_connector *connector)
7179 {
7180         const struct drm_connector_state *old_conn_state =
7181                 drm_atomic_get_old_connector_state(&state->base, connector);
7182         const struct intel_crtc_state *old_crtc_state;
7183         struct intel_crtc *crtc;
7184         u8 transcoders;
7185
7186         crtc = to_intel_crtc(old_conn_state->crtc);
7187         if (!crtc)
7188                 return 0;
7189
7190         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7191
7192         if (!old_crtc_state->hw.active)
7193                 return 0;
7194
7195         transcoders = old_crtc_state->sync_mode_slaves_mask;
7196         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7197                 transcoders |= BIT(old_crtc_state->master_transcoder);
7198
7199         return intel_modeset_affected_transcoders(state,
7200                                                   transcoders);
7201 }
7202
7203 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7204                                            struct drm_atomic_state *_state)
7205 {
7206         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7207         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7208         int ret;
7209
7210         ret = intel_digital_connector_atomic_check(conn, &state->base);
7211         if (ret)
7212                 return ret;
7213
7214         /*
7215          * We don't enable port sync on BDW due to missing w/as and
7216          * due to not having adjusted the modeset sequence appropriately.
7217          */
7218         if (INTEL_GEN(dev_priv) < 9)
7219                 return 0;
7220
7221         if (!intel_connector_needs_modeset(state, conn))
7222                 return 0;
7223
7224         if (conn->has_tile) {
7225                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7226                 if (ret)
7227                         return ret;
7228         }
7229
7230         return intel_modeset_synced_crtcs(state, conn);
7231 }
7232
7233 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7234         .force = intel_dp_force,
7235         .fill_modes = drm_helper_probe_single_connector_modes,
7236         .atomic_get_property = intel_digital_connector_atomic_get_property,
7237         .atomic_set_property = intel_digital_connector_atomic_set_property,
7238         .late_register = intel_dp_connector_register,
7239         .early_unregister = intel_dp_connector_unregister,
7240         .destroy = intel_connector_destroy,
7241         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7242         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7243 };
7244
7245 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7246         .detect_ctx = intel_dp_detect,
7247         .get_modes = intel_dp_get_modes,
7248         .mode_valid = intel_dp_mode_valid,
7249         .atomic_check = intel_dp_connector_atomic_check,
7250 };
7251
7252 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7253         .reset = intel_dp_encoder_reset,
7254         .destroy = intel_dp_encoder_destroy,
7255 };
7256
7257 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7258 {
7259         intel_wakeref_t wakeref;
7260         bool have_power = false;
7261
7262         with_pps_lock(intel_dp, wakeref) {
7263                 have_power = edp_have_panel_power(intel_dp) &&
7264                                                   edp_have_panel_vdd(intel_dp);
7265         }
7266
7267         return have_power;
7268 }
7269
7270 enum irqreturn
7271 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7272 {
7273         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7274         struct intel_dp *intel_dp = &intel_dig_port->dp;
7275
7276         if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7277             (long_hpd || !intel_edp_have_power(intel_dp))) {
7278                 /*
7279                  * vdd off can generate a long/short pulse on eDP which
7280                  * would require vdd on to handle it, and thus we
7281                  * would end up in an endless cycle of
7282                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7283                  */
7284                 drm_dbg_kms(&i915->drm,
7285                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7286                             long_hpd ? "long" : "short",
7287                             intel_dig_port->base.base.base.id,
7288                             intel_dig_port->base.base.name);
7289                 return IRQ_HANDLED;
7290         }
7291
7292         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7293                     intel_dig_port->base.base.base.id,
7294                     intel_dig_port->base.base.name,
7295                     long_hpd ? "long" : "short");
7296
7297         if (long_hpd) {
7298                 intel_dp->reset_link_params = true;
7299                 return IRQ_NONE;
7300         }
7301
7302         if (intel_dp->is_mst) {
7303                 switch (intel_dp_check_mst_status(intel_dp)) {
7304                 case -EINVAL:
7305                         /*
7306                          * If we were in MST mode, and device is not
7307                          * there, get out of MST mode
7308                          */
7309                         drm_dbg_kms(&i915->drm,
7310                                     "MST device may have disappeared %d vs %d\n",
7311                                     intel_dp->is_mst,
7312                                     intel_dp->mst_mgr.mst_state);
7313                         intel_dp->is_mst = false;
7314                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7315                                                         intel_dp->is_mst);
7316
7317                         return IRQ_NONE;
7318                 case 1:
7319                         return IRQ_NONE;
7320                 default:
7321                         break;
7322                 }
7323         }
7324
7325         if (!intel_dp->is_mst) {
7326                 bool handled;
7327
7328                 handled = intel_dp_short_pulse(intel_dp);
7329
7330                 if (!handled)
7331                         return IRQ_NONE;
7332         }
7333
7334         return IRQ_HANDLED;
7335 }
7336
7337 /* check the VBT to see whether the eDP is on another port */
7338 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7339 {
7340         /*
7341          * eDP not supported on g4x. so bail out early just
7342          * for a bit extra safety in case the VBT is bonkers.
7343          */
7344         if (INTEL_GEN(dev_priv) < 5)
7345                 return false;
7346
7347         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7348                 return true;
7349
7350         return intel_bios_is_port_edp(dev_priv, port);
7351 }
7352
7353 static void
7354 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7355 {
7356         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7357         enum port port = dp_to_dig_port(intel_dp)->base.port;
7358
7359         if (!IS_G4X(dev_priv) && port != PORT_A)
7360                 intel_attach_force_audio_property(connector);
7361
7362         intel_attach_broadcast_rgb_property(connector);
7363         if (HAS_GMCH(dev_priv))
7364                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7365         else if (INTEL_GEN(dev_priv) >= 5)
7366                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7367
7368         intel_attach_colorspace_property(connector);
7369
7370         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7371                 drm_object_attach_property(&connector->base,
7372                                            connector->dev->mode_config.hdr_output_metadata_property,
7373                                            0);
7374
7375         if (intel_dp_is_edp(intel_dp)) {
7376                 u32 allowed_scalers;
7377
7378                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7379                 if (!HAS_GMCH(dev_priv))
7380                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7381
7382                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7383
7384                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7385
7386         }
7387 }
7388
7389 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7390 {
7391         intel_dp->panel_power_off_time = ktime_get_boottime();
7392         intel_dp->last_power_on = jiffies;
7393         intel_dp->last_backlight_off = jiffies;
7394 }
7395
7396 static void
7397 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7398 {
7399         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7400         u32 pp_on, pp_off, pp_ctl;
7401         struct pps_registers regs;
7402
7403         intel_pps_get_registers(intel_dp, &regs);
7404
7405         pp_ctl = ilk_get_pp_control(intel_dp);
7406
7407         /* Ensure PPS is unlocked */
7408         if (!HAS_DDI(dev_priv))
7409                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7410
7411         pp_on = intel_de_read(dev_priv, regs.pp_on);
7412         pp_off = intel_de_read(dev_priv, regs.pp_off);
7413
7414         /* Pull timing values out of registers */
7415         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7416         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7417         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7418         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7419
7420         if (i915_mmio_reg_valid(regs.pp_div)) {
7421                 u32 pp_div;
7422
7423                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7424
7425                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7426         } else {
7427                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7428         }
7429 }
7430
7431 static void
7432 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7433 {
7434         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7435                       state_name,
7436                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7437 }
7438
7439 static void
7440 intel_pps_verify_state(struct intel_dp *intel_dp)
7441 {
7442         struct edp_power_seq hw;
7443         struct edp_power_seq *sw = &intel_dp->pps_delays;
7444
7445         intel_pps_readout_hw_state(intel_dp, &hw);
7446
7447         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7448             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7449                 DRM_ERROR("PPS state mismatch\n");
7450                 intel_pps_dump_state("sw", sw);
7451                 intel_pps_dump_state("hw", &hw);
7452         }
7453 }
7454
7455 static void
7456 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7457 {
7458         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7459         struct edp_power_seq cur, vbt, spec,
7460                 *final = &intel_dp->pps_delays;
7461
7462         lockdep_assert_held(&dev_priv->pps_mutex);
7463
7464         /* already initialized? */
7465         if (final->t11_t12 != 0)
7466                 return;
7467
7468         intel_pps_readout_hw_state(intel_dp, &cur);
7469
7470         intel_pps_dump_state("cur", &cur);
7471
7472         vbt = dev_priv->vbt.edp.pps;
7473         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7474          * of 500ms appears to be too short. Ocassionally the panel
7475          * just fails to power back on. Increasing the delay to 800ms
7476          * seems sufficient to avoid this problem.
7477          */
7478         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7479                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7480                 drm_dbg_kms(&dev_priv->drm,
7481                             "Increasing T12 panel delay as per the quirk to %d\n",
7482                             vbt.t11_t12);
7483         }
7484         /* T11_T12 delay is special and actually in units of 100ms, but zero
7485          * based in the hw (so we need to add 100 ms). But the sw vbt
7486          * table multiplies it with 1000 to make it in units of 100usec,
7487          * too. */
7488         vbt.t11_t12 += 100 * 10;
7489
7490         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7491          * our hw here, which are all in 100usec. */
7492         spec.t1_t3 = 210 * 10;
7493         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7494         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7495         spec.t10 = 500 * 10;
7496         /* This one is special and actually in units of 100ms, but zero
7497          * based in the hw (so we need to add 100 ms). But the sw vbt
7498          * table multiplies it with 1000 to make it in units of 100usec,
7499          * too. */
7500         spec.t11_t12 = (510 + 100) * 10;
7501
7502         intel_pps_dump_state("vbt", &vbt);
7503
7504         /* Use the max of the register settings and vbt. If both are
7505          * unset, fall back to the spec limits. */
7506 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7507                                        spec.field : \
7508                                        max(cur.field, vbt.field))
7509         assign_final(t1_t3);
7510         assign_final(t8);
7511         assign_final(t9);
7512         assign_final(t10);
7513         assign_final(t11_t12);
7514 #undef assign_final
7515
7516 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7517         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7518         intel_dp->backlight_on_delay = get_delay(t8);
7519         intel_dp->backlight_off_delay = get_delay(t9);
7520         intel_dp->panel_power_down_delay = get_delay(t10);
7521         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7522 #undef get_delay
7523
7524         drm_dbg_kms(&dev_priv->drm,
7525                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7526                     intel_dp->panel_power_up_delay,
7527                     intel_dp->panel_power_down_delay,
7528                     intel_dp->panel_power_cycle_delay);
7529
7530         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7531                     intel_dp->backlight_on_delay,
7532                     intel_dp->backlight_off_delay);
7533
7534         /*
7535          * We override the HW backlight delays to 1 because we do manual waits
7536          * on them. For T8, even BSpec recommends doing it. For T9, if we
7537          * don't do this, we'll end up waiting for the backlight off delay
7538          * twice: once when we do the manual sleep, and once when we disable
7539          * the panel and wait for the PP_STATUS bit to become zero.
7540          */
7541         final->t8 = 1;
7542         final->t9 = 1;
7543
7544         /*
7545          * HW has only a 100msec granularity for t11_t12 so round it up
7546          * accordingly.
7547          */
7548         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7549 }
7550
7551 static void
7552 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7553                                               bool force_disable_vdd)
7554 {
7555         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7556         u32 pp_on, pp_off, port_sel = 0;
7557         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7558         struct pps_registers regs;
7559         enum port port = dp_to_dig_port(intel_dp)->base.port;
7560         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7561
7562         lockdep_assert_held(&dev_priv->pps_mutex);
7563
7564         intel_pps_get_registers(intel_dp, &regs);
7565
7566         /*
7567          * On some VLV machines the BIOS can leave the VDD
7568          * enabled even on power sequencers which aren't
7569          * hooked up to any port. This would mess up the
7570          * power domain tracking the first time we pick
7571          * one of these power sequencers for use since
7572          * edp_panel_vdd_on() would notice that the VDD was
7573          * already on and therefore wouldn't grab the power
7574          * domain reference. Disable VDD first to avoid this.
7575          * This also avoids spuriously turning the VDD on as
7576          * soon as the new power sequencer gets initialized.
7577          */
7578         if (force_disable_vdd) {
7579                 u32 pp = ilk_get_pp_control(intel_dp);
7580
7581                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7582                          "Panel power already on\n");
7583
7584                 if (pp & EDP_FORCE_VDD)
7585                         drm_dbg_kms(&dev_priv->drm,
7586                                     "VDD already on, disabling first\n");
7587
7588                 pp &= ~EDP_FORCE_VDD;
7589
7590                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7591         }
7592
7593         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7594                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7595         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7596                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7597
7598         /* Haswell doesn't have any port selection bits for the panel
7599          * power sequencer any more. */
7600         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7601                 port_sel = PANEL_PORT_SELECT_VLV(port);
7602         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7603                 switch (port) {
7604                 case PORT_A:
7605                         port_sel = PANEL_PORT_SELECT_DPA;
7606                         break;
7607                 case PORT_C:
7608                         port_sel = PANEL_PORT_SELECT_DPC;
7609                         break;
7610                 case PORT_D:
7611                         port_sel = PANEL_PORT_SELECT_DPD;
7612                         break;
7613                 default:
7614                         MISSING_CASE(port);
7615                         break;
7616                 }
7617         }
7618
7619         pp_on |= port_sel;
7620
7621         intel_de_write(dev_priv, regs.pp_on, pp_on);
7622         intel_de_write(dev_priv, regs.pp_off, pp_off);
7623
7624         /*
7625          * Compute the divisor for the pp clock, simply match the Bspec formula.
7626          */
7627         if (i915_mmio_reg_valid(regs.pp_div)) {
7628                 intel_de_write(dev_priv, regs.pp_div,
7629                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7630         } else {
7631                 u32 pp_ctl;
7632
7633                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7634                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7635                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7636                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7637         }
7638
7639         drm_dbg_kms(&dev_priv->drm,
7640                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7641                     intel_de_read(dev_priv, regs.pp_on),
7642                     intel_de_read(dev_priv, regs.pp_off),
7643                     i915_mmio_reg_valid(regs.pp_div) ?
7644                     intel_de_read(dev_priv, regs.pp_div) :
7645                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7646 }
7647
7648 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7649 {
7650         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7651
7652         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7653                 vlv_initial_power_sequencer_setup(intel_dp);
7654         } else {
7655                 intel_dp_init_panel_power_sequencer(intel_dp);
7656                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7657         }
7658 }
7659
7660 /**
7661  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7662  * @dev_priv: i915 device
7663  * @crtc_state: a pointer to the active intel_crtc_state
7664  * @refresh_rate: RR to be programmed
7665  *
7666  * This function gets called when refresh rate (RR) has to be changed from
7667  * one frequency to another. Switches can be between high and low RR
7668  * supported by the panel or to any other RR based on media playback (in
7669  * this case, RR value needs to be passed from user space).
7670  *
7671  * The caller of this function needs to take a lock on dev_priv->drrs.
7672  */
7673 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7674                                     const struct intel_crtc_state *crtc_state,
7675                                     int refresh_rate)
7676 {
7677         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7679         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7680
7681         if (refresh_rate <= 0) {
7682                 drm_dbg_kms(&dev_priv->drm,
7683                             "Refresh rate should be positive non-zero.\n");
7684                 return;
7685         }
7686
7687         if (intel_dp == NULL) {
7688                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7689                 return;
7690         }
7691
7692         if (!intel_crtc) {
7693                 drm_dbg_kms(&dev_priv->drm,
7694                             "DRRS: intel_crtc not initialized\n");
7695                 return;
7696         }
7697
7698         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7699                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7700                 return;
7701         }
7702
7703         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7704                         refresh_rate)
7705                 index = DRRS_LOW_RR;
7706
7707         if (index == dev_priv->drrs.refresh_rate_type) {
7708                 drm_dbg_kms(&dev_priv->drm,
7709                             "DRRS requested for previously set RR...ignoring\n");
7710                 return;
7711         }
7712
7713         if (!crtc_state->hw.active) {
7714                 drm_dbg_kms(&dev_priv->drm,
7715                             "eDP encoder disabled. CRTC not Active\n");
7716                 return;
7717         }
7718
7719         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7720                 switch (index) {
7721                 case DRRS_HIGH_RR:
7722                         intel_dp_set_m_n(crtc_state, M1_N1);
7723                         break;
7724                 case DRRS_LOW_RR:
7725                         intel_dp_set_m_n(crtc_state, M2_N2);
7726                         break;
7727                 case DRRS_MAX_RR:
7728                 default:
7729                         drm_err(&dev_priv->drm,
7730                                 "Unsupported refreshrate type\n");
7731                 }
7732         } else if (INTEL_GEN(dev_priv) > 6) {
7733                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7734                 u32 val;
7735
7736                 val = intel_de_read(dev_priv, reg);
7737                 if (index > DRRS_HIGH_RR) {
7738                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7739                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7740                         else
7741                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7742                 } else {
7743                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7744                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7745                         else
7746                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7747                 }
7748                 intel_de_write(dev_priv, reg, val);
7749         }
7750
7751         dev_priv->drrs.refresh_rate_type = index;
7752
7753         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7754                     refresh_rate);
7755 }
7756
7757 /**
7758  * intel_edp_drrs_enable - init drrs struct if supported
7759  * @intel_dp: DP struct
7760  * @crtc_state: A pointer to the active crtc state.
7761  *
7762  * Initializes frontbuffer_bits and drrs.dp
7763  */
7764 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7765                            const struct intel_crtc_state *crtc_state)
7766 {
7767         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7768
7769         if (!crtc_state->has_drrs) {
7770                 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7771                 return;
7772         }
7773
7774         if (dev_priv->psr.enabled) {
7775                 drm_dbg_kms(&dev_priv->drm,
7776                             "PSR enabled. Not enabling DRRS.\n");
7777                 return;
7778         }
7779
7780         mutex_lock(&dev_priv->drrs.mutex);
7781         if (dev_priv->drrs.dp) {
7782                 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7783                 goto unlock;
7784         }
7785
7786         dev_priv->drrs.busy_frontbuffer_bits = 0;
7787
7788         dev_priv->drrs.dp = intel_dp;
7789
7790 unlock:
7791         mutex_unlock(&dev_priv->drrs.mutex);
7792 }
7793
7794 /**
7795  * intel_edp_drrs_disable - Disable DRRS
7796  * @intel_dp: DP struct
7797  * @old_crtc_state: Pointer to old crtc_state.
7798  *
7799  */
7800 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7801                             const struct intel_crtc_state *old_crtc_state)
7802 {
7803         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7804
7805         if (!old_crtc_state->has_drrs)
7806                 return;
7807
7808         mutex_lock(&dev_priv->drrs.mutex);
7809         if (!dev_priv->drrs.dp) {
7810                 mutex_unlock(&dev_priv->drrs.mutex);
7811                 return;
7812         }
7813
7814         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7815                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7816                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7817
7818         dev_priv->drrs.dp = NULL;
7819         mutex_unlock(&dev_priv->drrs.mutex);
7820
7821         cancel_delayed_work_sync(&dev_priv->drrs.work);
7822 }
7823
7824 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7825 {
7826         struct drm_i915_private *dev_priv =
7827                 container_of(work, typeof(*dev_priv), drrs.work.work);
7828         struct intel_dp *intel_dp;
7829
7830         mutex_lock(&dev_priv->drrs.mutex);
7831
7832         intel_dp = dev_priv->drrs.dp;
7833
7834         if (!intel_dp)
7835                 goto unlock;
7836
7837         /*
7838          * The delayed work can race with an invalidate hence we need to
7839          * recheck.
7840          */
7841
7842         if (dev_priv->drrs.busy_frontbuffer_bits)
7843                 goto unlock;
7844
7845         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7846                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7847
7848                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7849                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7850         }
7851
7852 unlock:
7853         mutex_unlock(&dev_priv->drrs.mutex);
7854 }
7855
7856 /**
7857  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7858  * @dev_priv: i915 device
7859  * @frontbuffer_bits: frontbuffer plane tracking bits
7860  *
7861  * This function gets called everytime rendering on the given planes start.
7862  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7863  *
7864  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7865  */
7866 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7867                                unsigned int frontbuffer_bits)
7868 {
7869         struct drm_crtc *crtc;
7870         enum pipe pipe;
7871
7872         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7873                 return;
7874
7875         cancel_delayed_work(&dev_priv->drrs.work);
7876
7877         mutex_lock(&dev_priv->drrs.mutex);
7878         if (!dev_priv->drrs.dp) {
7879                 mutex_unlock(&dev_priv->drrs.mutex);
7880                 return;
7881         }
7882
7883         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7884         pipe = to_intel_crtc(crtc)->pipe;
7885
7886         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7887         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7888
7889         /* invalidate means busy screen hence upclock */
7890         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7891                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7892                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7893
7894         mutex_unlock(&dev_priv->drrs.mutex);
7895 }
7896
7897 /**
7898  * intel_edp_drrs_flush - Restart Idleness DRRS
7899  * @dev_priv: i915 device
7900  * @frontbuffer_bits: frontbuffer plane tracking bits
7901  *
7902  * This function gets called every time rendering on the given planes has
7903  * completed or flip on a crtc is completed. So DRRS should be upclocked
7904  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7905  * if no other planes are dirty.
7906  *
7907  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7908  */
7909 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7910                           unsigned int frontbuffer_bits)
7911 {
7912         struct drm_crtc *crtc;
7913         enum pipe pipe;
7914
7915         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7916                 return;
7917
7918         cancel_delayed_work(&dev_priv->drrs.work);
7919
7920         mutex_lock(&dev_priv->drrs.mutex);
7921         if (!dev_priv->drrs.dp) {
7922                 mutex_unlock(&dev_priv->drrs.mutex);
7923                 return;
7924         }
7925
7926         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7927         pipe = to_intel_crtc(crtc)->pipe;
7928
7929         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7930         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7931
7932         /* flush means busy screen hence upclock */
7933         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7934                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7935                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7936
7937         /*
7938          * flush also means no more activity hence schedule downclock, if all
7939          * other fbs are quiescent too
7940          */
7941         if (!dev_priv->drrs.busy_frontbuffer_bits)
7942                 schedule_delayed_work(&dev_priv->drrs.work,
7943                                 msecs_to_jiffies(1000));
7944         mutex_unlock(&dev_priv->drrs.mutex);
7945 }
7946
7947 /**
7948  * DOC: Display Refresh Rate Switching (DRRS)
7949  *
7950  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7951  * which enables swtching between low and high refresh rates,
7952  * dynamically, based on the usage scenario. This feature is applicable
7953  * for internal panels.
7954  *
7955  * Indication that the panel supports DRRS is given by the panel EDID, which
7956  * would list multiple refresh rates for one resolution.
7957  *
7958  * DRRS is of 2 types - static and seamless.
7959  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7960  * (may appear as a blink on screen) and is used in dock-undock scenario.
7961  * Seamless DRRS involves changing RR without any visual effect to the user
7962  * and can be used during normal system usage. This is done by programming
7963  * certain registers.
7964  *
7965  * Support for static/seamless DRRS may be indicated in the VBT based on
7966  * inputs from the panel spec.
7967  *
7968  * DRRS saves power by switching to low RR based on usage scenarios.
7969  *
7970  * The implementation is based on frontbuffer tracking implementation.  When
7971  * there is a disturbance on the screen triggered by user activity or a periodic
7972  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
7973  * no movement on screen, after a timeout of 1 second, a switch to low RR is
7974  * made.
7975  *
7976  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7977  * and intel_edp_drrs_flush() are called.
7978  *
7979  * DRRS can be further extended to support other internal panels and also
7980  * the scenario of video playback wherein RR is set based on the rate
7981  * requested by userspace.
7982  */
7983
7984 /**
7985  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7986  * @connector: eDP connector
7987  * @fixed_mode: preferred mode of panel
7988  *
7989  * This function is  called only once at driver load to initialize basic
7990  * DRRS stuff.
7991  *
7992  * Returns:
7993  * Downclock mode if panel supports it, else return NULL.
7994  * DRRS support is determined by the presence of downclock mode (apart
7995  * from VBT setting).
7996  */
7997 static struct drm_display_mode *
7998 intel_dp_drrs_init(struct intel_connector *connector,
7999                    struct drm_display_mode *fixed_mode)
8000 {
8001         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8002         struct drm_display_mode *downclock_mode = NULL;
8003
8004         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8005         mutex_init(&dev_priv->drrs.mutex);
8006
8007         if (INTEL_GEN(dev_priv) <= 6) {
8008                 drm_dbg_kms(&dev_priv->drm,
8009                             "DRRS supported for Gen7 and above\n");
8010                 return NULL;
8011         }
8012
8013         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8014                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8015                 return NULL;
8016         }
8017
8018         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8019         if (!downclock_mode) {
8020                 drm_dbg_kms(&dev_priv->drm,
8021                             "Downclock mode is not found. DRRS not supported\n");
8022                 return NULL;
8023         }
8024
8025         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8026
8027         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8028         drm_dbg_kms(&dev_priv->drm,
8029                     "seamless DRRS supported for eDP panel.\n");
8030         return downclock_mode;
8031 }
8032
8033 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8034                                      struct intel_connector *intel_connector)
8035 {
8036         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8037         struct drm_device *dev = &dev_priv->drm;
8038         struct drm_connector *connector = &intel_connector->base;
8039         struct drm_display_mode *fixed_mode = NULL;
8040         struct drm_display_mode *downclock_mode = NULL;
8041         bool has_dpcd;
8042         enum pipe pipe = INVALID_PIPE;
8043         intel_wakeref_t wakeref;
8044         struct edid *edid;
8045
8046         if (!intel_dp_is_edp(intel_dp))
8047                 return true;
8048
8049         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8050
8051         /*
8052          * On IBX/CPT we may get here with LVDS already registered. Since the
8053          * driver uses the only internal power sequencer available for both
8054          * eDP and LVDS bail out early in this case to prevent interfering
8055          * with an already powered-on LVDS power sequencer.
8056          */
8057         if (intel_get_lvds_encoder(dev_priv)) {
8058                 drm_WARN_ON(dev,
8059                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8060                 drm_info(&dev_priv->drm,
8061                          "LVDS was detected, not registering eDP\n");
8062
8063                 return false;
8064         }
8065
8066         with_pps_lock(intel_dp, wakeref) {
8067                 intel_dp_init_panel_power_timestamps(intel_dp);
8068                 intel_dp_pps_init(intel_dp);
8069                 intel_edp_panel_vdd_sanitize(intel_dp);
8070         }
8071
8072         /* Cache DPCD and EDID for edp. */
8073         has_dpcd = intel_edp_init_dpcd(intel_dp);
8074
8075         if (!has_dpcd) {
8076                 /* if this fails, presume the device is a ghost */
8077                 drm_info(&dev_priv->drm,
8078                          "failed to retrieve link info, disabling eDP\n");
8079                 goto out_vdd_off;
8080         }
8081
8082         mutex_lock(&dev->mode_config.mutex);
8083         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8084         if (edid) {
8085                 if (drm_add_edid_modes(connector, edid)) {
8086                         drm_connector_update_edid_property(connector, edid);
8087                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8088                 } else {
8089                         kfree(edid);
8090                         edid = ERR_PTR(-EINVAL);
8091                 }
8092         } else {
8093                 edid = ERR_PTR(-ENOENT);
8094         }
8095         intel_connector->edid = edid;
8096
8097         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8098         if (fixed_mode)
8099                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8100
8101         /* fallback to VBT if available for eDP */
8102         if (!fixed_mode)
8103                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8104         mutex_unlock(&dev->mode_config.mutex);
8105
8106         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8107                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8108                 register_reboot_notifier(&intel_dp->edp_notifier);
8109
8110                 /*
8111                  * Figure out the current pipe for the initial backlight setup.
8112                  * If the current pipe isn't valid, try the PPS pipe, and if that
8113                  * fails just assume pipe A.
8114                  */
8115                 pipe = vlv_active_pipe(intel_dp);
8116
8117                 if (pipe != PIPE_A && pipe != PIPE_B)
8118                         pipe = intel_dp->pps_pipe;
8119
8120                 if (pipe != PIPE_A && pipe != PIPE_B)
8121                         pipe = PIPE_A;
8122
8123                 drm_dbg_kms(&dev_priv->drm,
8124                             "using pipe %c for initial backlight setup\n",
8125                             pipe_name(pipe));
8126         }
8127
8128         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8129         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8130         intel_panel_setup_backlight(connector, pipe);
8131
8132         if (fixed_mode) {
8133                 drm_connector_set_panel_orientation_with_quirk(connector,
8134                                 dev_priv->vbt.orientation,
8135                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8136         }
8137
8138         return true;
8139
8140 out_vdd_off:
8141         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8142         /*
8143          * vdd might still be enabled do to the delayed vdd off.
8144          * Make sure vdd is actually turned off here.
8145          */
8146         with_pps_lock(intel_dp, wakeref)
8147                 edp_panel_vdd_off_sync(intel_dp);
8148
8149         return false;
8150 }
8151
8152 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8153 {
8154         struct intel_connector *intel_connector;
8155         struct drm_connector *connector;
8156
8157         intel_connector = container_of(work, typeof(*intel_connector),
8158                                        modeset_retry_work);
8159         connector = &intel_connector->base;
8160         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8161                       connector->name);
8162
8163         /* Grab the locks before changing connector property*/
8164         mutex_lock(&connector->dev->mode_config.mutex);
8165         /* Set connector link status to BAD and send a Uevent to notify
8166          * userspace to do a modeset.
8167          */
8168         drm_connector_set_link_status_property(connector,
8169                                                DRM_MODE_LINK_STATUS_BAD);
8170         mutex_unlock(&connector->dev->mode_config.mutex);
8171         /* Send Hotplug uevent so userspace can reprobe */
8172         drm_kms_helper_hotplug_event(connector->dev);
8173 }
8174
8175 bool
8176 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8177                         struct intel_connector *intel_connector)
8178 {
8179         struct drm_connector *connector = &intel_connector->base;
8180         struct intel_dp *intel_dp = &intel_dig_port->dp;
8181         struct intel_encoder *intel_encoder = &intel_dig_port->base;
8182         struct drm_device *dev = intel_encoder->base.dev;
8183         struct drm_i915_private *dev_priv = to_i915(dev);
8184         enum port port = intel_encoder->port;
8185         enum phy phy = intel_port_to_phy(dev_priv, port);
8186         int type;
8187
8188         /* Initialize the work for modeset in case of link train failure */
8189         INIT_WORK(&intel_connector->modeset_retry_work,
8190                   intel_dp_modeset_retry_work_fn);
8191
8192         if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8193                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8194                      intel_dig_port->max_lanes, intel_encoder->base.base.id,
8195                      intel_encoder->base.name))
8196                 return false;
8197
8198         intel_dp_set_source_rates(intel_dp);
8199
8200         intel_dp->reset_link_params = true;
8201         intel_dp->pps_pipe = INVALID_PIPE;
8202         intel_dp->active_pipe = INVALID_PIPE;
8203
8204         /* Preserve the current hw state. */
8205         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8206         intel_dp->attached_connector = intel_connector;
8207
8208         if (intel_dp_is_port_edp(dev_priv, port)) {
8209                 /*
8210                  * Currently we don't support eDP on TypeC ports, although in
8211                  * theory it could work on TypeC legacy ports.
8212                  */
8213                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8214                 type = DRM_MODE_CONNECTOR_eDP;
8215         } else {
8216                 type = DRM_MODE_CONNECTOR_DisplayPort;
8217         }
8218
8219         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8220                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8221
8222         /*
8223          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8224          * for DP the encoder type can be set by the caller to
8225          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8226          */
8227         if (type == DRM_MODE_CONNECTOR_eDP)
8228                 intel_encoder->type = INTEL_OUTPUT_EDP;
8229
8230         /* eDP only on port B and/or C on vlv/chv */
8231         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8232                               IS_CHERRYVIEW(dev_priv)) &&
8233                         intel_dp_is_edp(intel_dp) &&
8234                         port != PORT_B && port != PORT_C))
8235                 return false;
8236
8237         drm_dbg_kms(&dev_priv->drm,
8238                     "Adding %s connector on [ENCODER:%d:%s]\n",
8239                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8240                     intel_encoder->base.base.id, intel_encoder->base.name);
8241
8242         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8243         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8244
8245         if (!HAS_GMCH(dev_priv))
8246                 connector->interlace_allowed = true;
8247         connector->doublescan_allowed = 0;
8248
8249         if (INTEL_GEN(dev_priv) >= 11)
8250                 connector->ycbcr_420_allowed = true;
8251
8252         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8253         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8254
8255         intel_dp_aux_init(intel_dp);
8256
8257         intel_connector_attach_encoder(intel_connector, intel_encoder);
8258
8259         if (HAS_DDI(dev_priv))
8260                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8261         else
8262                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8263
8264         /* init MST on ports that can support it */
8265         intel_dp_mst_encoder_init(intel_dig_port,
8266                                   intel_connector->base.base.id);
8267
8268         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8269                 intel_dp_aux_fini(intel_dp);
8270                 intel_dp_mst_encoder_cleanup(intel_dig_port);
8271                 goto fail;
8272         }
8273
8274         intel_dp_add_properties(intel_dp, connector);
8275
8276         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8277                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8278                 if (ret)
8279                         drm_dbg_kms(&dev_priv->drm,
8280                                     "HDCP init failed, skipping.\n");
8281         }
8282
8283         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8284          * 0xd.  Failure to do so will result in spurious interrupts being
8285          * generated on the port when a cable is not attached.
8286          */
8287         if (IS_G45(dev_priv)) {
8288                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8289                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8290                                (temp & ~0xf) | 0xd);
8291         }
8292
8293         return true;
8294
8295 fail:
8296         drm_connector_cleanup(connector);
8297
8298         return false;
8299 }
8300
8301 bool intel_dp_init(struct drm_i915_private *dev_priv,
8302                    i915_reg_t output_reg,
8303                    enum port port)
8304 {
8305         struct intel_digital_port *intel_dig_port;
8306         struct intel_encoder *intel_encoder;
8307         struct drm_encoder *encoder;
8308         struct intel_connector *intel_connector;
8309
8310         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8311         if (!intel_dig_port)
8312                 return false;
8313
8314         intel_connector = intel_connector_alloc();
8315         if (!intel_connector)
8316                 goto err_connector_alloc;
8317
8318         intel_encoder = &intel_dig_port->base;
8319         encoder = &intel_encoder->base;
8320
8321         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8322                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8323                              "DP %c", port_name(port)))
8324                 goto err_encoder_init;
8325
8326         intel_encoder->hotplug = intel_dp_hotplug;
8327         intel_encoder->compute_config = intel_dp_compute_config;
8328         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8329         intel_encoder->get_config = intel_dp_get_config;
8330         intel_encoder->update_pipe = intel_panel_update_backlight;
8331         intel_encoder->suspend = intel_dp_encoder_suspend;
8332         if (IS_CHERRYVIEW(dev_priv)) {
8333                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8334                 intel_encoder->pre_enable = chv_pre_enable_dp;
8335                 intel_encoder->enable = vlv_enable_dp;
8336                 intel_encoder->disable = vlv_disable_dp;
8337                 intel_encoder->post_disable = chv_post_disable_dp;
8338                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8339         } else if (IS_VALLEYVIEW(dev_priv)) {
8340                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8341                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8342                 intel_encoder->enable = vlv_enable_dp;
8343                 intel_encoder->disable = vlv_disable_dp;
8344                 intel_encoder->post_disable = vlv_post_disable_dp;
8345         } else {
8346                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8347                 intel_encoder->enable = g4x_enable_dp;
8348                 intel_encoder->disable = g4x_disable_dp;
8349                 intel_encoder->post_disable = g4x_post_disable_dp;
8350         }
8351
8352         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8353             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8354                 intel_dig_port->dp.set_link_train = cpt_set_link_train;
8355         else
8356                 intel_dig_port->dp.set_link_train = g4x_set_link_train;
8357
8358         if (IS_CHERRYVIEW(dev_priv))
8359                 intel_dig_port->dp.set_signal_levels = chv_set_signal_levels;
8360         else if (IS_VALLEYVIEW(dev_priv))
8361                 intel_dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8362         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8363                 intel_dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8364         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8365                 intel_dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8366         else
8367                 intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8368
8369         intel_dig_port->dp.output_reg = output_reg;
8370         intel_dig_port->max_lanes = 4;
8371         intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
8372         intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
8373
8374         intel_encoder->type = INTEL_OUTPUT_DP;
8375         intel_encoder->power_domain = intel_port_to_power_domain(port);
8376         if (IS_CHERRYVIEW(dev_priv)) {
8377                 if (port == PORT_D)
8378                         intel_encoder->pipe_mask = BIT(PIPE_C);
8379                 else
8380                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8381         } else {
8382                 intel_encoder->pipe_mask = ~0;
8383         }
8384         intel_encoder->cloneable = 0;
8385         intel_encoder->port = port;
8386
8387         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8388
8389         if (HAS_GMCH(dev_priv)) {
8390                 if (IS_GM45(dev_priv))
8391                         intel_dig_port->connected = gm45_digital_port_connected;
8392                 else
8393                         intel_dig_port->connected = g4x_digital_port_connected;
8394         } else {
8395                 if (port == PORT_A)
8396                         intel_dig_port->connected = ilk_digital_port_connected;
8397                 else
8398                         intel_dig_port->connected = ibx_digital_port_connected;
8399         }
8400
8401         if (port != PORT_A)
8402                 intel_infoframe_init(intel_dig_port);
8403
8404         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8405         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8406                 goto err_init_connector;
8407
8408         return true;
8409
8410 err_init_connector:
8411         drm_encoder_cleanup(encoder);
8412 err_encoder_init:
8413         kfree(intel_connector);
8414 err_connector_alloc:
8415         kfree(intel_dig_port);
8416         return false;
8417 }
8418
8419 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8420 {
8421         struct intel_encoder *encoder;
8422
8423         for_each_intel_encoder(&dev_priv->drm, encoder) {
8424                 struct intel_dp *intel_dp;
8425
8426                 if (encoder->type != INTEL_OUTPUT_DDI)
8427                         continue;
8428
8429                 intel_dp = enc_to_intel_dp(encoder);
8430
8431                 if (!intel_dp->can_mst)
8432                         continue;
8433
8434                 if (intel_dp->is_mst)
8435                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8436         }
8437 }
8438
8439 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8440 {
8441         struct intel_encoder *encoder;
8442
8443         for_each_intel_encoder(&dev_priv->drm, encoder) {
8444                 struct intel_dp *intel_dp;
8445                 int ret;
8446
8447                 if (encoder->type != INTEL_OUTPUT_DDI)
8448                         continue;
8449
8450                 intel_dp = enc_to_intel_dp(encoder);
8451
8452                 if (!intel_dp->can_mst)
8453                         continue;
8454
8455                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8456                                                      true);
8457                 if (ret) {
8458                         intel_dp->is_mst = false;
8459                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8460                                                         false);
8461                 }
8462         }
8463 }