2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
35 #include <asm/byteorder.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/i915_drm.h>
45 #include "i915_debugfs.h"
47 #include "i915_trace.h"
48 #include "intel_atomic.h"
49 #include "intel_audio.h"
50 #include "intel_connector.h"
51 #include "intel_ddi.h"
52 #include "intel_display_types.h"
54 #include "intel_dp_link_training.h"
55 #include "intel_dp_mst.h"
56 #include "intel_dpio_phy.h"
57 #include "intel_fifo_underrun.h"
58 #include "intel_hdcp.h"
59 #include "intel_hdmi.h"
60 #include "intel_hotplug.h"
61 #include "intel_lspcon.h"
62 #include "intel_lvds.h"
63 #include "intel_panel.h"
64 #include "intel_psr.h"
65 #include "intel_sideband.h"
67 #include "intel_vdsc.h"
69 #define DP_DPRX_ESI_LEN 14
71 /* DP DSC throughput values used for slice count calculations KPixels/s */
72 #define DP_DSC_PEAK_PIXEL_RATE 2720000
73 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
74 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
77 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
79 /* Compliance test status bits */
80 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
81 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
82 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
83 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
90 static const struct dp_link_dpll g4x_dpll[] = {
92 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
94 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
97 static const struct dp_link_dpll pch_dpll[] = {
99 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
101 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
104 static const struct dp_link_dpll vlv_dpll[] = {
106 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
108 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
112 * CHV supports eDP 1.4 that have more link rates.
113 * Below only provides the fixed rate but exclude variable rate.
115 static const struct dp_link_dpll chv_dpll[] = {
117 * CHV requires to program fractional division for m2.
118 * m2 is stored in fixed point format using formula below
119 * (m2_int << 22) | m2_fraction
121 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
122 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
123 { 270000, /* m2_int = 27, m2_fraction = 0 */
124 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
127 /* Constants for DP DSC configurations */
128 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
130 /* With Single pipe configuration, HW is capable of supporting maximum
131 * of 4 slices per line.
133 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
136 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
137 * @intel_dp: DP struct
139 * If a CPU or PCH DP output is attached to an eDP panel, this function
140 * will return true, and false otherwise.
142 bool intel_dp_is_edp(struct intel_dp *intel_dp)
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
146 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
149 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
151 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
154 static void intel_dp_link_down(struct intel_encoder *encoder,
155 const struct intel_crtc_state *old_crtc_state);
156 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
157 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
158 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
159 const struct intel_crtc_state *crtc_state);
160 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
162 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
164 /* update sink rates from dpcd */
165 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
167 static const int dp_rates[] = {
168 162000, 270000, 540000, 810000
172 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
174 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
175 if (dp_rates[i] > max_rate)
177 intel_dp->sink_rates[i] = dp_rates[i];
180 intel_dp->num_sink_rates = i;
183 /* Get length of rates array potentially limited by max_rate. */
184 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
188 /* Limit results by potentially reduced max rate */
189 for (i = 0; i < len; i++) {
190 if (rates[len - i - 1] <= max_rate)
197 /* Get length of common rates array potentially limited by max_rate. */
198 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
201 return intel_dp_rate_limit_len(intel_dp->common_rates,
202 intel_dp->num_common_rates, max_rate);
205 /* Theoretical max between source and sink */
206 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
208 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
211 /* Theoretical max between source and sink */
212 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
214 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
215 int source_max = intel_dig_port->max_lanes;
216 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
217 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
219 return min3(source_max, sink_max, fia_max);
222 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
224 return intel_dp->max_link_lane_count;
228 intel_dp_link_required(int pixel_clock, int bpp)
230 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
231 return DIV_ROUND_UP(pixel_clock * bpp, 8);
235 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
237 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
238 * link rate that is generally expressed in Gbps. Since, 8 bits of data
239 * is transmitted every LS_Clk per lane, there is no need to account for
240 * the channel encoding that is done in the PHY layer here.
243 return max_link_clock * max_lanes;
247 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
250 struct intel_encoder *encoder = &intel_dig_port->base;
251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
252 int max_dotclk = dev_priv->max_dotclk_freq;
255 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
257 if (type != DP_DS_PORT_TYPE_VGA)
260 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
261 intel_dp->downstream_ports);
263 if (ds_max_dotclk != 0)
264 max_dotclk = min(max_dotclk, ds_max_dotclk);
269 static int cnl_max_source_rate(struct intel_dp *intel_dp)
271 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
272 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
273 enum port port = dig_port->base.port;
275 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
277 /* Low voltage SKUs are limited to max of 5.4G */
278 if (voltage == VOLTAGE_INFO_0_85V)
281 /* For this SKU 8.1G is supported in all ports */
282 if (IS_CNL_WITH_PORT_F(dev_priv))
285 /* For other SKUs, max rate on ports A and D is 5.4G */
286 if (port == PORT_A || port == PORT_D)
292 static int icl_max_source_rate(struct intel_dp *intel_dp)
294 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
295 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
296 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
298 if (intel_phy_is_combo(dev_priv, phy) &&
299 !IS_ELKHARTLAKE(dev_priv) &&
300 !intel_dp_is_edp(intel_dp))
307 intel_dp_set_source_rates(struct intel_dp *intel_dp)
309 /* The values must be in increasing order */
310 static const int cnl_rates[] = {
311 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
313 static const int bxt_rates[] = {
314 162000, 216000, 243000, 270000, 324000, 432000, 540000
316 static const int skl_rates[] = {
317 162000, 216000, 270000, 324000, 432000, 540000
319 static const int hsw_rates[] = {
320 162000, 270000, 540000
322 static const int g4x_rates[] = {
325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
326 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
327 const struct ddi_vbt_port_info *info =
328 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
329 const int *source_rates;
330 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
332 /* This should only be done once */
333 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
335 if (INTEL_GEN(dev_priv) >= 10) {
336 source_rates = cnl_rates;
337 size = ARRAY_SIZE(cnl_rates);
338 if (IS_GEN(dev_priv, 10))
339 max_rate = cnl_max_source_rate(intel_dp);
341 max_rate = icl_max_source_rate(intel_dp);
342 } else if (IS_GEN9_LP(dev_priv)) {
343 source_rates = bxt_rates;
344 size = ARRAY_SIZE(bxt_rates);
345 } else if (IS_GEN9_BC(dev_priv)) {
346 source_rates = skl_rates;
347 size = ARRAY_SIZE(skl_rates);
348 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
349 IS_BROADWELL(dev_priv)) {
350 source_rates = hsw_rates;
351 size = ARRAY_SIZE(hsw_rates);
353 source_rates = g4x_rates;
354 size = ARRAY_SIZE(g4x_rates);
357 if (max_rate && vbt_max_rate)
358 max_rate = min(max_rate, vbt_max_rate);
359 else if (vbt_max_rate)
360 max_rate = vbt_max_rate;
363 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
365 intel_dp->source_rates = source_rates;
366 intel_dp->num_source_rates = size;
369 static int intersect_rates(const int *source_rates, int source_len,
370 const int *sink_rates, int sink_len,
373 int i = 0, j = 0, k = 0;
375 while (i < source_len && j < sink_len) {
376 if (source_rates[i] == sink_rates[j]) {
377 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
379 common_rates[k] = source_rates[i];
383 } else if (source_rates[i] < sink_rates[j]) {
392 /* return index of rate in rates array, or -1 if not found */
393 static int intel_dp_rate_index(const int *rates, int len, int rate)
397 for (i = 0; i < len; i++)
398 if (rate == rates[i])
404 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
406 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
408 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
409 intel_dp->num_source_rates,
410 intel_dp->sink_rates,
411 intel_dp->num_sink_rates,
412 intel_dp->common_rates);
414 /* Paranoia, there should always be something in common. */
415 if (WARN_ON(intel_dp->num_common_rates == 0)) {
416 intel_dp->common_rates[0] = 162000;
417 intel_dp->num_common_rates = 1;
421 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
425 * FIXME: we need to synchronize the current link parameters with
426 * hardware readout. Currently fast link training doesn't work on
429 if (link_rate == 0 ||
430 link_rate > intel_dp->max_link_rate)
433 if (lane_count == 0 ||
434 lane_count > intel_dp_max_lane_count(intel_dp))
440 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
444 const struct drm_display_mode *fixed_mode =
445 intel_dp->attached_connector->panel.fixed_mode;
446 int mode_rate, max_rate;
448 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
449 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
450 if (mode_rate > max_rate)
456 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
457 int link_rate, u8 lane_count)
461 index = intel_dp_rate_index(intel_dp->common_rates,
462 intel_dp->num_common_rates,
465 if (intel_dp_is_edp(intel_dp) &&
466 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
467 intel_dp->common_rates[index - 1],
469 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
472 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
473 intel_dp->max_link_lane_count = lane_count;
474 } else if (lane_count > 1) {
475 if (intel_dp_is_edp(intel_dp) &&
476 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
477 intel_dp_max_common_rate(intel_dp),
479 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
482 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
483 intel_dp->max_link_lane_count = lane_count >> 1;
485 DRM_ERROR("Link Training Unsuccessful\n");
492 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
494 return div_u64(mul_u32_u32(mode_clock, 1000000U),
495 DP_DSC_FEC_OVERHEAD_FACTOR);
499 small_joiner_ram_size_bits(struct drm_i915_private *i915)
501 if (INTEL_GEN(i915) >= 11)
507 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
508 u32 link_clock, u32 lane_count,
509 u32 mode_clock, u32 mode_hdisplay)
511 u32 bits_per_pixel, max_bpp_small_joiner_ram;
515 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
516 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
517 * for SST -> TimeSlotsPerMTP is 1,
518 * for MST -> TimeSlotsPerMTP has to be calculated
520 bits_per_pixel = (link_clock * lane_count * 8) /
521 intel_dp_mode_to_fec_clock(mode_clock);
522 DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
524 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
525 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
527 DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
530 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
531 * check, output bpp from small joiner RAM check)
533 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
535 /* Error out if the max bpp is less than smallest allowed valid bpp */
536 if (bits_per_pixel < valid_dsc_bpp[0]) {
537 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
538 bits_per_pixel, valid_dsc_bpp[0]);
542 /* Find the nearest match in the array of known BPPs from VESA */
543 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
544 if (bits_per_pixel < valid_dsc_bpp[i + 1])
547 bits_per_pixel = valid_dsc_bpp[i];
550 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
551 * fractional part is 0
553 return bits_per_pixel << 4;
556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
557 int mode_clock, int mode_hdisplay)
559 u8 min_slice_count, i;
562 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
563 min_slice_count = DIV_ROUND_UP(mode_clock,
564 DP_DSC_MAX_ENC_THROUGHPUT_0);
566 min_slice_count = DIV_ROUND_UP(mode_clock,
567 DP_DSC_MAX_ENC_THROUGHPUT_1);
569 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
570 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
571 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
575 /* Also take into account max slice width */
576 min_slice_count = min_t(u8, min_slice_count,
577 DIV_ROUND_UP(mode_hdisplay,
580 /* Find the closest match to the valid slice count values */
581 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
582 if (valid_dsc_slicecount[i] >
583 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
586 if (min_slice_count <= valid_dsc_slicecount[i])
587 return valid_dsc_slicecount[i];
590 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
594 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
598 * Older platforms don't like hdisplay==4096 with DP.
600 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
601 * and frame counter increment), but we don't get vblank interrupts,
602 * and the pipe underruns immediately. The link also doesn't seem
603 * to get trained properly.
605 * On CHV the vblank interrupts don't seem to disappear but
606 * otherwise the symptoms are similar.
608 * TODO: confirm the behaviour on HSW+
610 return hdisplay == 4096 && !HAS_DDI(dev_priv);
613 static enum drm_mode_status
614 intel_dp_mode_valid(struct drm_connector *connector,
615 struct drm_display_mode *mode)
617 struct intel_dp *intel_dp = intel_attached_dp(connector);
618 struct intel_connector *intel_connector = to_intel_connector(connector);
619 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
620 struct drm_i915_private *dev_priv = to_i915(connector->dev);
621 int target_clock = mode->clock;
622 int max_rate, mode_rate, max_lanes, max_link_clock;
624 u16 dsc_max_output_bpp = 0;
625 u8 dsc_slice_count = 0;
627 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
628 return MODE_NO_DBLESCAN;
630 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
632 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
633 if (mode->hdisplay > fixed_mode->hdisplay)
636 if (mode->vdisplay > fixed_mode->vdisplay)
639 target_clock = fixed_mode->clock;
642 max_link_clock = intel_dp_max_link_rate(intel_dp);
643 max_lanes = intel_dp_max_lane_count(intel_dp);
645 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
646 mode_rate = intel_dp_link_required(target_clock, 18);
648 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
649 return MODE_H_ILLEGAL;
652 * Output bpp is stored in 6.4 format so right shift by 4 to get the
653 * integer value since we support only integer values of bpp.
655 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
656 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
657 if (intel_dp_is_edp(intel_dp)) {
659 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
661 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
663 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
665 intel_dp_dsc_get_output_bpp(dev_priv,
669 mode->hdisplay) >> 4;
671 intel_dp_dsc_get_slice_count(intel_dp,
677 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
678 target_clock > max_dotclk)
679 return MODE_CLOCK_HIGH;
681 if (mode->clock < 10000)
682 return MODE_CLOCK_LOW;
684 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
685 return MODE_H_ILLEGAL;
687 return intel_mode_valid_max_plane_size(dev_priv, mode);
690 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
697 for (i = 0; i < src_bytes; i++)
698 v |= ((u32)src[i]) << ((3 - i) * 8);
702 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
707 for (i = 0; i < dst_bytes; i++)
708 dst[i] = src >> ((3-i) * 8);
712 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
714 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
715 bool force_disable_vdd);
717 intel_dp_pps_init(struct intel_dp *intel_dp);
719 static intel_wakeref_t
720 pps_lock(struct intel_dp *intel_dp)
722 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
723 intel_wakeref_t wakeref;
726 * See intel_power_sequencer_reset() why we need
727 * a power domain reference here.
729 wakeref = intel_display_power_get(dev_priv,
730 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
732 mutex_lock(&dev_priv->pps_mutex);
737 static intel_wakeref_t
738 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
740 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
742 mutex_unlock(&dev_priv->pps_mutex);
743 intel_display_power_put(dev_priv,
744 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
749 #define with_pps_lock(dp, wf) \
750 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
753 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
755 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
757 enum pipe pipe = intel_dp->pps_pipe;
758 bool pll_enabled, release_cl_override = false;
759 enum dpio_phy phy = DPIO_PHY(pipe);
760 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
763 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
764 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
765 pipe_name(pipe), intel_dig_port->base.base.base.id,
766 intel_dig_port->base.base.name))
769 DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
770 pipe_name(pipe), intel_dig_port->base.base.base.id,
771 intel_dig_port->base.base.name);
773 /* Preserve the BIOS-computed detected bit. This is
774 * supposed to be read-only.
776 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
777 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
778 DP |= DP_PORT_WIDTH(1);
779 DP |= DP_LINK_TRAIN_PAT_1;
781 if (IS_CHERRYVIEW(dev_priv))
782 DP |= DP_PIPE_SEL_CHV(pipe);
784 DP |= DP_PIPE_SEL(pipe);
786 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
789 * The DPLL for the pipe must be enabled for this to work.
790 * So enable temporarily it if it's not already enabled.
793 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
794 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
796 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
797 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
798 DRM_ERROR("Failed to force on pll for pipe %c!\n",
805 * Similar magic as in intel_dp_enable_port().
806 * We _must_ do this port enable + disable trick
807 * to make this power sequencer lock onto the port.
808 * Otherwise even VDD force bit won't work.
810 I915_WRITE(intel_dp->output_reg, DP);
811 POSTING_READ(intel_dp->output_reg);
813 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
814 POSTING_READ(intel_dp->output_reg);
816 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
817 POSTING_READ(intel_dp->output_reg);
820 vlv_force_pll_off(dev_priv, pipe);
822 if (release_cl_override)
823 chv_phy_powergate_ch(dev_priv, phy, ch, false);
827 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
829 struct intel_encoder *encoder;
830 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
833 * We don't have power sequencer currently.
834 * Pick one that's not used by other ports.
836 for_each_intel_dp(&dev_priv->drm, encoder) {
837 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
839 if (encoder->type == INTEL_OUTPUT_EDP) {
840 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
841 intel_dp->active_pipe != intel_dp->pps_pipe);
843 if (intel_dp->pps_pipe != INVALID_PIPE)
844 pipes &= ~(1 << intel_dp->pps_pipe);
846 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
848 if (intel_dp->active_pipe != INVALID_PIPE)
849 pipes &= ~(1 << intel_dp->active_pipe);
856 return ffs(pipes) - 1;
860 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
862 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
863 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
866 lockdep_assert_held(&dev_priv->pps_mutex);
868 /* We should never land here with regular DP ports */
869 WARN_ON(!intel_dp_is_edp(intel_dp));
871 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
872 intel_dp->active_pipe != intel_dp->pps_pipe);
874 if (intel_dp->pps_pipe != INVALID_PIPE)
875 return intel_dp->pps_pipe;
877 pipe = vlv_find_free_pps(dev_priv);
880 * Didn't find one. This should not happen since there
881 * are two power sequencers and up to two eDP ports.
883 if (WARN_ON(pipe == INVALID_PIPE))
886 vlv_steal_power_sequencer(dev_priv, pipe);
887 intel_dp->pps_pipe = pipe;
889 DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
890 pipe_name(intel_dp->pps_pipe),
891 intel_dig_port->base.base.base.id,
892 intel_dig_port->base.base.name);
894 /* init power sequencer on this pipe and port */
895 intel_dp_init_panel_power_sequencer(intel_dp);
896 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
899 * Even vdd force doesn't work until we've made
900 * the power sequencer lock in on the port.
902 vlv_power_sequencer_kick(intel_dp);
904 return intel_dp->pps_pipe;
908 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
911 int backlight_controller = dev_priv->vbt.backlight.controller;
913 lockdep_assert_held(&dev_priv->pps_mutex);
915 /* We should never land here with regular DP ports */
916 WARN_ON(!intel_dp_is_edp(intel_dp));
918 if (!intel_dp->pps_reset)
919 return backlight_controller;
921 intel_dp->pps_reset = false;
924 * Only the HW needs to be reprogrammed, the SW state is fixed and
925 * has been setup during connector init.
927 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
929 return backlight_controller;
932 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
935 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
938 return I915_READ(PP_STATUS(pipe)) & PP_ON;
941 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
944 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
947 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
954 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
956 vlv_pipe_check pipe_check)
960 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
961 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
962 PANEL_PORT_SELECT_MASK;
964 if (port_sel != PANEL_PORT_SELECT_VLV(port))
967 if (!pipe_check(dev_priv, pipe))
977 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
979 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
980 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
981 enum port port = intel_dig_port->base.port;
983 lockdep_assert_held(&dev_priv->pps_mutex);
985 /* try to find a pipe with this port selected */
986 /* first pick one where the panel is on */
987 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
989 /* didn't find one? pick one where vdd is on */
990 if (intel_dp->pps_pipe == INVALID_PIPE)
991 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
992 vlv_pipe_has_vdd_on);
993 /* didn't find one? pick one with just the correct port */
994 if (intel_dp->pps_pipe == INVALID_PIPE)
995 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
998 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
999 if (intel_dp->pps_pipe == INVALID_PIPE) {
1000 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
1001 intel_dig_port->base.base.base.id,
1002 intel_dig_port->base.base.name);
1006 DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1007 intel_dig_port->base.base.base.id,
1008 intel_dig_port->base.base.name,
1009 pipe_name(intel_dp->pps_pipe));
1011 intel_dp_init_panel_power_sequencer(intel_dp);
1012 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1015 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1017 struct intel_encoder *encoder;
1019 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
1020 !IS_GEN9_LP(dev_priv)))
1024 * We can't grab pps_mutex here due to deadlock with power_domain
1025 * mutex when power_domain functions are called while holding pps_mutex.
1026 * That also means that in order to use pps_pipe the code needs to
1027 * hold both a power domain reference and pps_mutex, and the power domain
1028 * reference get/put must be done while _not_ holding pps_mutex.
1029 * pps_{lock,unlock}() do these steps in the correct order, so one
1030 * should use them always.
1033 for_each_intel_dp(&dev_priv->drm, encoder) {
1034 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1036 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1038 if (encoder->type != INTEL_OUTPUT_EDP)
1041 if (IS_GEN9_LP(dev_priv))
1042 intel_dp->pps_reset = true;
1044 intel_dp->pps_pipe = INVALID_PIPE;
1048 struct pps_registers {
1056 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1057 struct pps_registers *regs)
1059 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1062 memset(regs, 0, sizeof(*regs));
1064 if (IS_GEN9_LP(dev_priv))
1065 pps_idx = bxt_power_sequencer_idx(intel_dp);
1066 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1067 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1069 regs->pp_ctrl = PP_CONTROL(pps_idx);
1070 regs->pp_stat = PP_STATUS(pps_idx);
1071 regs->pp_on = PP_ON_DELAYS(pps_idx);
1072 regs->pp_off = PP_OFF_DELAYS(pps_idx);
1074 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1075 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1076 regs->pp_div = INVALID_MMIO_REG;
1078 regs->pp_div = PP_DIVISOR(pps_idx);
1082 _pp_ctrl_reg(struct intel_dp *intel_dp)
1084 struct pps_registers regs;
1086 intel_pps_get_registers(intel_dp, ®s);
1088 return regs.pp_ctrl;
1092 _pp_stat_reg(struct intel_dp *intel_dp)
1094 struct pps_registers regs;
1096 intel_pps_get_registers(intel_dp, ®s);
1098 return regs.pp_stat;
1101 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1102 This function only applicable when panel PM state is not to be tracked */
1103 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1106 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1108 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1109 intel_wakeref_t wakeref;
1111 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1114 with_pps_lock(intel_dp, wakeref) {
1115 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1116 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1117 i915_reg_t pp_ctrl_reg, pp_div_reg;
1120 pp_ctrl_reg = PP_CONTROL(pipe);
1121 pp_div_reg = PP_DIVISOR(pipe);
1122 pp_div = I915_READ(pp_div_reg);
1123 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1125 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1126 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1127 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1128 msleep(intel_dp->panel_power_cycle_delay);
1135 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1139 lockdep_assert_held(&dev_priv->pps_mutex);
1141 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1142 intel_dp->pps_pipe == INVALID_PIPE)
1145 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1148 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1150 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152 lockdep_assert_held(&dev_priv->pps_mutex);
1154 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1155 intel_dp->pps_pipe == INVALID_PIPE)
1158 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1162 intel_dp_check_edp(struct intel_dp *intel_dp)
1164 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1166 if (!intel_dp_is_edp(intel_dp))
1169 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1170 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1171 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1172 I915_READ(_pp_stat_reg(intel_dp)),
1173 I915_READ(_pp_ctrl_reg(intel_dp)));
1178 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1180 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1181 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1182 const unsigned int timeout_ms = 10;
1186 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1187 done = wait_event_timeout(i915->gmbus_wait_queue, C,
1188 msecs_to_jiffies_timeout(timeout_ms));
1190 /* just trace the final value */
1191 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1194 DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n",
1195 intel_dp->aux.name, timeout_ms, status);
1201 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1203 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1209 * The clock divider is based off the hrawclk, and would like to run at
1210 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1212 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1215 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1217 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1218 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1224 * The clock divider is based off the cdclk or PCH rawclk, and would
1225 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1226 * divide by 2000 and use that
1228 if (dig_port->aux_ch == AUX_CH_A)
1229 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1231 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1234 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1236 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1239 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1240 /* Workaround for non-ULT HSW */
1248 return ilk_get_aux_clock_divider(intel_dp, index);
1251 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1254 * SKL doesn't need us to program the AUX clock divider (Hardware will
1255 * derive the clock from CDCLK automatically). We still implement the
1256 * get_aux_clock_divider vfunc to plug-in into the existing code.
1258 return index ? 0 : 1;
1261 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1263 u32 aux_clock_divider)
1265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1266 struct drm_i915_private *dev_priv =
1267 to_i915(intel_dig_port->base.base.dev);
1268 u32 precharge, timeout;
1270 if (IS_GEN(dev_priv, 6))
1275 if (IS_BROADWELL(dev_priv))
1276 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1278 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1280 return DP_AUX_CH_CTL_SEND_BUSY |
1281 DP_AUX_CH_CTL_DONE |
1282 DP_AUX_CH_CTL_INTERRUPT |
1283 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1285 DP_AUX_CH_CTL_RECEIVE_ERROR |
1286 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1287 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1288 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1291 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296 struct drm_i915_private *i915 =
1297 to_i915(intel_dig_port->base.base.dev);
1298 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1301 ret = DP_AUX_CH_CTL_SEND_BUSY |
1302 DP_AUX_CH_CTL_DONE |
1303 DP_AUX_CH_CTL_INTERRUPT |
1304 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1305 DP_AUX_CH_CTL_TIME_OUT_MAX |
1306 DP_AUX_CH_CTL_RECEIVE_ERROR |
1307 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1308 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1309 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1311 if (intel_phy_is_tc(i915, phy) &&
1312 intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1313 ret |= DP_AUX_CH_CTL_TBT_IO;
1319 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1320 const u8 *send, int send_bytes,
1321 u8 *recv, int recv_size,
1322 u32 aux_send_ctl_flags)
1324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1325 struct drm_i915_private *i915 =
1326 to_i915(intel_dig_port->base.base.dev);
1327 struct intel_uncore *uncore = &i915->uncore;
1328 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1329 bool is_tc_port = intel_phy_is_tc(i915, phy);
1330 i915_reg_t ch_ctl, ch_data[5];
1331 u32 aux_clock_divider;
1332 enum intel_display_power_domain aux_domain =
1333 intel_aux_power_domain(intel_dig_port);
1334 intel_wakeref_t aux_wakeref;
1335 intel_wakeref_t pps_wakeref;
1336 int i, ret, recv_bytes;
1341 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1342 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1343 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1346 intel_tc_port_lock(intel_dig_port);
1348 aux_wakeref = intel_display_power_get(i915, aux_domain);
1349 pps_wakeref = pps_lock(intel_dp);
1352 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1353 * In such cases we want to leave VDD enabled and it's up to upper layers
1354 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1357 vdd = edp_panel_vdd_on(intel_dp);
1359 /* dp aux is extremely sensitive to irq latency, hence request the
1360 * lowest possible wakeup latency and so prevent the cpu from going into
1361 * deep sleep states.
1363 pm_qos_update_request(&i915->pm_qos, 0);
1365 intel_dp_check_edp(intel_dp);
1367 /* Try to wait for any previous AUX channel activity */
1368 for (try = 0; try < 3; try++) {
1369 status = intel_uncore_read_notrace(uncore, ch_ctl);
1370 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1374 /* just trace the final value */
1375 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1378 const u32 status = intel_uncore_read(uncore, ch_ctl);
1380 if (status != intel_dp->aux_busy_last_status) {
1381 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1383 intel_dp->aux_busy_last_status = status;
1390 /* Only 5 data registers! */
1391 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1396 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1397 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1401 send_ctl |= aux_send_ctl_flags;
1403 /* Must try at least 3 times according to DP spec */
1404 for (try = 0; try < 5; try++) {
1405 /* Load the send data into the aux channel data registers */
1406 for (i = 0; i < send_bytes; i += 4)
1407 intel_uncore_write(uncore,
1409 intel_dp_pack_aux(send + i,
1412 /* Send the command and wait for it to complete */
1413 intel_uncore_write(uncore, ch_ctl, send_ctl);
1415 status = intel_dp_aux_wait_done(intel_dp);
1417 /* Clear done status and any errors */
1418 intel_uncore_write(uncore,
1421 DP_AUX_CH_CTL_DONE |
1422 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1423 DP_AUX_CH_CTL_RECEIVE_ERROR);
1425 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1426 * 400us delay required for errors and timeouts
1427 * Timeout errors from the HW already meet this
1428 * requirement so skip to next iteration
1430 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1433 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1434 usleep_range(400, 500);
1437 if (status & DP_AUX_CH_CTL_DONE)
1442 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1443 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1449 /* Check for timeout or receive error.
1450 * Timeouts occur when the sink is not connected
1452 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1453 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1458 /* Timeouts occur when the device isn't connected, so they're
1459 * "normal" -- don't fill the kernel log with these */
1460 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1461 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1466 /* Unload any bytes sent back from the other side */
1467 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1468 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1471 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1472 * We have no idea of what happened so we return -EBUSY so
1473 * drm layer takes care for the necessary retries.
1475 if (recv_bytes == 0 || recv_bytes > 20) {
1476 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1482 if (recv_bytes > recv_size)
1483 recv_bytes = recv_size;
1485 for (i = 0; i < recv_bytes; i += 4)
1486 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1487 recv + i, recv_bytes - i);
1491 pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1494 edp_panel_vdd_off(intel_dp, false);
1496 pps_unlock(intel_dp, pps_wakeref);
1497 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1500 intel_tc_port_unlock(intel_dig_port);
1505 #define BARE_ADDRESS_SIZE 3
1506 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1509 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1510 const struct drm_dp_aux_msg *msg)
1512 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1513 txbuf[1] = (msg->address >> 8) & 0xff;
1514 txbuf[2] = msg->address & 0xff;
1515 txbuf[3] = msg->size - 1;
1519 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1521 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1522 u8 txbuf[20], rxbuf[20];
1523 size_t txsize, rxsize;
1526 intel_dp_aux_header(txbuf, msg);
1528 switch (msg->request & ~DP_AUX_I2C_MOT) {
1529 case DP_AUX_NATIVE_WRITE:
1530 case DP_AUX_I2C_WRITE:
1531 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1532 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1533 rxsize = 2; /* 0 or 1 data bytes */
1535 if (WARN_ON(txsize > 20))
1538 WARN_ON(!msg->buffer != !msg->size);
1541 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1543 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1546 msg->reply = rxbuf[0] >> 4;
1549 /* Number of bytes written in a short write. */
1550 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1552 /* Return payload size. */
1558 case DP_AUX_NATIVE_READ:
1559 case DP_AUX_I2C_READ:
1560 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1561 rxsize = msg->size + 1;
1563 if (WARN_ON(rxsize > 20))
1566 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1569 msg->reply = rxbuf[0] >> 4;
1571 * Assume happy day, and copy the data. The caller is
1572 * expected to check msg->reply before touching it.
1574 * Return payload size.
1577 memcpy(msg->buffer, rxbuf + 1, ret);
1590 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1592 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1593 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1594 enum aux_ch aux_ch = dig_port->aux_ch;
1600 return DP_AUX_CH_CTL(aux_ch);
1602 MISSING_CASE(aux_ch);
1603 return DP_AUX_CH_CTL(AUX_CH_B);
1607 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1609 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1610 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1611 enum aux_ch aux_ch = dig_port->aux_ch;
1617 return DP_AUX_CH_DATA(aux_ch, index);
1619 MISSING_CASE(aux_ch);
1620 return DP_AUX_CH_DATA(AUX_CH_B, index);
1624 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1626 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1627 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1628 enum aux_ch aux_ch = dig_port->aux_ch;
1632 return DP_AUX_CH_CTL(aux_ch);
1636 return PCH_DP_AUX_CH_CTL(aux_ch);
1638 MISSING_CASE(aux_ch);
1639 return DP_AUX_CH_CTL(AUX_CH_A);
1643 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1645 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1646 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1647 enum aux_ch aux_ch = dig_port->aux_ch;
1651 return DP_AUX_CH_DATA(aux_ch, index);
1655 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1657 MISSING_CASE(aux_ch);
1658 return DP_AUX_CH_DATA(AUX_CH_A, index);
1662 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1664 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1665 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1666 enum aux_ch aux_ch = dig_port->aux_ch;
1676 return DP_AUX_CH_CTL(aux_ch);
1678 MISSING_CASE(aux_ch);
1679 return DP_AUX_CH_CTL(AUX_CH_A);
1683 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1685 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687 enum aux_ch aux_ch = dig_port->aux_ch;
1697 return DP_AUX_CH_DATA(aux_ch, index);
1699 MISSING_CASE(aux_ch);
1700 return DP_AUX_CH_DATA(AUX_CH_A, index);
1705 intel_dp_aux_fini(struct intel_dp *intel_dp)
1707 kfree(intel_dp->aux.name);
1711 intel_dp_aux_init(struct intel_dp *intel_dp)
1713 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1714 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1715 struct intel_encoder *encoder = &dig_port->base;
1717 if (INTEL_GEN(dev_priv) >= 9) {
1718 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1719 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1720 } else if (HAS_PCH_SPLIT(dev_priv)) {
1721 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1722 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1724 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1725 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1728 if (INTEL_GEN(dev_priv) >= 9)
1729 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1730 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1731 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1732 else if (HAS_PCH_SPLIT(dev_priv))
1733 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1735 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1737 if (INTEL_GEN(dev_priv) >= 9)
1738 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1740 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1742 drm_dp_aux_init(&intel_dp->aux);
1744 /* Failure to allocate our preferred name is not critical */
1745 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1746 port_name(encoder->port));
1747 intel_dp->aux.transfer = intel_dp_aux_transfer;
1750 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1752 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1754 return max_rate >= 540000;
1757 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1759 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1761 return max_rate >= 810000;
1765 intel_dp_set_clock(struct intel_encoder *encoder,
1766 struct intel_crtc_state *pipe_config)
1768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1769 const struct dp_link_dpll *divisor = NULL;
1772 if (IS_G4X(dev_priv)) {
1774 count = ARRAY_SIZE(g4x_dpll);
1775 } else if (HAS_PCH_SPLIT(dev_priv)) {
1777 count = ARRAY_SIZE(pch_dpll);
1778 } else if (IS_CHERRYVIEW(dev_priv)) {
1780 count = ARRAY_SIZE(chv_dpll);
1781 } else if (IS_VALLEYVIEW(dev_priv)) {
1783 count = ARRAY_SIZE(vlv_dpll);
1786 if (divisor && count) {
1787 for (i = 0; i < count; i++) {
1788 if (pipe_config->port_clock == divisor[i].clock) {
1789 pipe_config->dpll = divisor[i].dpll;
1790 pipe_config->clock_set = true;
1797 static void snprintf_int_array(char *str, size_t len,
1798 const int *array, int nelem)
1804 for (i = 0; i < nelem; i++) {
1805 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1813 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1815 char str[128]; /* FIXME: too big for stack? */
1817 if ((drm_debug & DRM_UT_KMS) == 0)
1820 snprintf_int_array(str, sizeof(str),
1821 intel_dp->source_rates, intel_dp->num_source_rates);
1822 DRM_DEBUG_KMS("source rates: %s\n", str);
1824 snprintf_int_array(str, sizeof(str),
1825 intel_dp->sink_rates, intel_dp->num_sink_rates);
1826 DRM_DEBUG_KMS("sink rates: %s\n", str);
1828 snprintf_int_array(str, sizeof(str),
1829 intel_dp->common_rates, intel_dp->num_common_rates);
1830 DRM_DEBUG_KMS("common rates: %s\n", str);
1834 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1838 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1839 if (WARN_ON(len <= 0))
1842 return intel_dp->common_rates[len - 1];
1845 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1847 int i = intel_dp_rate_index(intel_dp->sink_rates,
1848 intel_dp->num_sink_rates, rate);
1856 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1857 u8 *link_bw, u8 *rate_select)
1859 /* eDP 1.4 rate select method. */
1860 if (intel_dp->use_rate_select) {
1863 intel_dp_rate_select(intel_dp, port_clock);
1865 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1870 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1871 const struct intel_crtc_state *pipe_config)
1873 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1875 /* On TGL, FEC is supported on all Pipes */
1876 if (INTEL_GEN(dev_priv) >= 12)
1879 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1885 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1886 const struct intel_crtc_state *pipe_config)
1888 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1889 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1892 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1893 const struct intel_crtc_state *pipe_config)
1895 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1897 if (!INTEL_INFO(dev_priv)->display.has_dsc)
1900 /* On TGL, DSC is supported on all Pipes */
1901 if (INTEL_GEN(dev_priv) >= 12)
1904 if (INTEL_GEN(dev_priv) >= 10 &&
1905 pipe_config->cpu_transcoder != TRANSCODER_A)
1911 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1912 const struct intel_crtc_state *pipe_config)
1914 if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1917 return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1918 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1921 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1922 struct intel_crtc_state *pipe_config)
1924 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1925 struct intel_connector *intel_connector = intel_dp->attached_connector;
1928 bpp = pipe_config->pipe_bpp;
1929 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1932 bpp = min(bpp, 3*bpc);
1934 if (intel_dp_is_edp(intel_dp)) {
1935 /* Get bpp from vbt only for panels that dont have bpp in edid */
1936 if (intel_connector->base.display_info.bpc == 0 &&
1937 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1938 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1939 dev_priv->vbt.edp.bpp);
1940 bpp = dev_priv->vbt.edp.bpp;
1947 /* Adjust link config limits based on compliance test requests. */
1949 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1950 struct intel_crtc_state *pipe_config,
1951 struct link_config_limits *limits)
1953 /* For DP Compliance we override the computed bpp for the pipe */
1954 if (intel_dp->compliance.test_data.bpc != 0) {
1955 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1957 limits->min_bpp = limits->max_bpp = bpp;
1958 pipe_config->dither_force_disable = bpp == 6 * 3;
1960 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1963 /* Use values requested by Compliance Test Request */
1964 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1967 /* Validate the compliance test data since max values
1968 * might have changed due to link train fallback.
1970 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1971 intel_dp->compliance.test_lane_count)) {
1972 index = intel_dp_rate_index(intel_dp->common_rates,
1973 intel_dp->num_common_rates,
1974 intel_dp->compliance.test_link_rate);
1976 limits->min_clock = limits->max_clock = index;
1977 limits->min_lane_count = limits->max_lane_count =
1978 intel_dp->compliance.test_lane_count;
1983 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1986 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1987 * format of the number of bytes per pixel will be half the number
1988 * of bytes of RGB pixel.
1990 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1996 /* Optimize link config in order: max bpp, min clock, min lanes */
1998 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1999 struct intel_crtc_state *pipe_config,
2000 const struct link_config_limits *limits)
2002 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2003 int bpp, clock, lane_count;
2004 int mode_rate, link_clock, link_avail;
2006 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2007 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2009 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2012 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2013 for (lane_count = limits->min_lane_count;
2014 lane_count <= limits->max_lane_count;
2016 link_clock = intel_dp->common_rates[clock];
2017 link_avail = intel_dp_max_data_rate(link_clock,
2020 if (mode_rate <= link_avail) {
2021 pipe_config->lane_count = lane_count;
2022 pipe_config->pipe_bpp = bpp;
2023 pipe_config->port_clock = link_clock;
2034 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2037 u8 dsc_bpc[3] = {0};
2039 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2041 for (i = 0; i < num_bpc; i++) {
2042 if (dsc_max_bpc >= dsc_bpc[i])
2043 return dsc_bpc[i] * 3;
2049 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2050 struct intel_crtc_state *pipe_config,
2051 struct drm_connector_state *conn_state,
2052 struct link_config_limits *limits)
2054 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2055 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2056 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2061 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2062 intel_dp_supports_fec(intel_dp, pipe_config);
2064 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2067 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2068 if (INTEL_GEN(dev_priv) >= 12)
2069 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2071 dsc_max_bpc = min_t(u8, 10,
2072 conn_state->max_requested_bpc);
2074 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2076 /* Min Input BPC for ICL+ is 8 */
2077 if (pipe_bpp < 8 * 3) {
2078 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2083 * For now enable DSC for max bpp, max link rate, max lane count.
2084 * Optimize this later for the minimum possible link rate/lane count
2085 * with DSC enabled for the requested mode.
2087 pipe_config->pipe_bpp = pipe_bpp;
2088 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2089 pipe_config->lane_count = limits->max_lane_count;
2091 if (intel_dp_is_edp(intel_dp)) {
2092 pipe_config->dsc.compressed_bpp =
2093 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2094 pipe_config->pipe_bpp);
2095 pipe_config->dsc.slice_count =
2096 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2099 u16 dsc_max_output_bpp;
2100 u8 dsc_dp_slice_count;
2102 dsc_max_output_bpp =
2103 intel_dp_dsc_get_output_bpp(dev_priv,
2104 pipe_config->port_clock,
2105 pipe_config->lane_count,
2106 adjusted_mode->crtc_clock,
2107 adjusted_mode->crtc_hdisplay);
2108 dsc_dp_slice_count =
2109 intel_dp_dsc_get_slice_count(intel_dp,
2110 adjusted_mode->crtc_clock,
2111 adjusted_mode->crtc_hdisplay);
2112 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2113 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2116 pipe_config->dsc.compressed_bpp = min_t(u16,
2117 dsc_max_output_bpp >> 4,
2118 pipe_config->pipe_bpp);
2119 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2122 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2123 * is greater than the maximum Cdclock and if slice count is even
2124 * then we need to use 2 VDSC instances.
2126 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2127 if (pipe_config->dsc.slice_count > 1) {
2128 pipe_config->dsc.dsc_split = true;
2130 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2135 ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
2137 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2138 "Compressed BPP = %d\n",
2139 pipe_config->pipe_bpp,
2140 pipe_config->dsc.compressed_bpp);
2144 pipe_config->dsc.compression_enable = true;
2145 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2146 "Compressed Bpp = %d Slice Count = %d\n",
2147 pipe_config->pipe_bpp,
2148 pipe_config->dsc.compressed_bpp,
2149 pipe_config->dsc.slice_count);
2154 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2156 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2163 intel_dp_compute_link_config(struct intel_encoder *encoder,
2164 struct intel_crtc_state *pipe_config,
2165 struct drm_connector_state *conn_state)
2167 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2168 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2169 struct link_config_limits limits;
2173 common_len = intel_dp_common_len_rate_limit(intel_dp,
2174 intel_dp->max_link_rate);
2176 /* No common link rates between source and sink */
2177 WARN_ON(common_len <= 0);
2179 limits.min_clock = 0;
2180 limits.max_clock = common_len - 1;
2182 limits.min_lane_count = 1;
2183 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2185 limits.min_bpp = intel_dp_min_bpp(pipe_config);
2186 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2188 if (intel_dp_is_edp(intel_dp)) {
2190 * Use the maximum clock and number of lanes the eDP panel
2191 * advertizes being capable of. The panels are generally
2192 * designed to support only a single clock and lane
2193 * configuration, and typically these values correspond to the
2194 * native resolution of the panel.
2196 limits.min_lane_count = limits.max_lane_count;
2197 limits.min_clock = limits.max_clock;
2200 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2202 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2203 "max rate %d max bpp %d pixel clock %iKHz\n",
2204 limits.max_lane_count,
2205 intel_dp->common_rates[limits.max_clock],
2206 limits.max_bpp, adjusted_mode->crtc_clock);
2209 * Optimize for slow and wide. This is the place to add alternative
2210 * optimization policy.
2212 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2214 /* enable compression if the mode doesn't fit available BW */
2215 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2216 if (ret || intel_dp->force_dsc_en) {
2217 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2218 conn_state, &limits);
2223 if (pipe_config->dsc.compression_enable) {
2224 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2225 pipe_config->lane_count, pipe_config->port_clock,
2226 pipe_config->pipe_bpp,
2227 pipe_config->dsc.compressed_bpp);
2229 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2230 intel_dp_link_required(adjusted_mode->crtc_clock,
2231 pipe_config->dsc.compressed_bpp),
2232 intel_dp_max_data_rate(pipe_config->port_clock,
2233 pipe_config->lane_count));
2235 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2236 pipe_config->lane_count, pipe_config->port_clock,
2237 pipe_config->pipe_bpp);
2239 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2240 intel_dp_link_required(adjusted_mode->crtc_clock,
2241 pipe_config->pipe_bpp),
2242 intel_dp_max_data_rate(pipe_config->port_clock,
2243 pipe_config->lane_count));
2249 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2250 struct drm_connector *connector,
2251 struct intel_crtc_state *crtc_state)
2253 const struct drm_display_info *info = &connector->display_info;
2254 const struct drm_display_mode *adjusted_mode =
2255 &crtc_state->hw.adjusted_mode;
2256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2259 if (!drm_mode_is_420_only(info, adjusted_mode) ||
2260 !intel_dp_get_colorimetry_status(intel_dp) ||
2261 !connector->ycbcr_420_allowed)
2264 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2266 /* YCBCR 420 output conversion needs a scaler */
2267 ret = skl_update_scaler_crtc(crtc_state);
2269 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2273 intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2278 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2279 const struct drm_connector_state *conn_state)
2281 const struct intel_digital_connector_state *intel_conn_state =
2282 to_intel_digital_connector_state(conn_state);
2283 const struct drm_display_mode *adjusted_mode =
2284 &crtc_state->hw.adjusted_mode;
2287 * Our YCbCr output is always limited range.
2288 * crtc_state->limited_color_range only applies to RGB,
2289 * and it must never be set for YCbCr or we risk setting
2290 * some conflicting bits in PIPECONF which will mess up
2291 * the colors on the monitor.
2293 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2296 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2299 * CEA-861-E - 5.1 Default Encoding Parameters
2300 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2302 return crtc_state->pipe_bpp != 18 &&
2303 drm_default_rgb_quant_range(adjusted_mode) ==
2304 HDMI_QUANTIZATION_RANGE_LIMITED;
2306 return intel_conn_state->broadcast_rgb ==
2307 INTEL_BROADCAST_RGB_LIMITED;
2311 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2314 if (IS_G4X(dev_priv))
2316 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2323 intel_dp_compute_config(struct intel_encoder *encoder,
2324 struct intel_crtc_state *pipe_config,
2325 struct drm_connector_state *conn_state)
2327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2328 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2329 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2330 struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2331 enum port port = encoder->port;
2332 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2333 struct intel_connector *intel_connector = intel_dp->attached_connector;
2334 struct intel_digital_connector_state *intel_conn_state =
2335 to_intel_digital_connector_state(conn_state);
2336 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2337 DP_DPCD_QUIRK_CONSTANT_N);
2338 int ret = 0, output_bpp;
2340 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2341 pipe_config->has_pch_encoder = true;
2343 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2346 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2348 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2354 pipe_config->has_drrs = false;
2355 if (!intel_dp_port_has_audio(dev_priv, port))
2356 pipe_config->has_audio = false;
2357 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2358 pipe_config->has_audio = intel_dp->has_audio;
2360 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2362 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2363 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2366 if (INTEL_GEN(dev_priv) >= 9) {
2367 ret = skl_update_scaler_crtc(pipe_config);
2372 if (HAS_GMCH(dev_priv))
2373 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2374 conn_state->scaling_mode);
2376 intel_pch_panel_fitting(intel_crtc, pipe_config,
2377 conn_state->scaling_mode);
2380 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2383 if (HAS_GMCH(dev_priv) &&
2384 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2387 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2390 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2393 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2397 pipe_config->limited_color_range =
2398 intel_dp_limited_color_range(pipe_config, conn_state);
2400 if (pipe_config->dsc.compression_enable)
2401 output_bpp = pipe_config->dsc.compressed_bpp;
2403 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2405 intel_link_compute_m_n(output_bpp,
2406 pipe_config->lane_count,
2407 adjusted_mode->crtc_clock,
2408 pipe_config->port_clock,
2409 &pipe_config->dp_m_n,
2410 constant_n, pipe_config->fec_enable);
2412 if (intel_connector->panel.downclock_mode != NULL &&
2413 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2414 pipe_config->has_drrs = true;
2415 intel_link_compute_m_n(output_bpp,
2416 pipe_config->lane_count,
2417 intel_connector->panel.downclock_mode->clock,
2418 pipe_config->port_clock,
2419 &pipe_config->dp_m2_n2,
2420 constant_n, pipe_config->fec_enable);
2423 if (!HAS_DDI(dev_priv))
2424 intel_dp_set_clock(encoder, pipe_config);
2426 intel_psr_compute_config(intel_dp, pipe_config);
2428 intel_hdcp_transcoder_config(intel_connector,
2429 pipe_config->cpu_transcoder);
2434 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2435 int link_rate, u8 lane_count,
2438 intel_dp->link_trained = false;
2439 intel_dp->link_rate = link_rate;
2440 intel_dp->lane_count = lane_count;
2441 intel_dp->link_mst = link_mst;
2444 static void intel_dp_prepare(struct intel_encoder *encoder,
2445 const struct intel_crtc_state *pipe_config)
2447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2448 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2449 enum port port = encoder->port;
2450 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2451 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2453 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2454 pipe_config->lane_count,
2455 intel_crtc_has_type(pipe_config,
2456 INTEL_OUTPUT_DP_MST));
2458 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2459 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2462 * There are four kinds of DP registers:
2469 * IBX PCH and CPU are the same for almost everything,
2470 * except that the CPU DP PLL is configured in this
2473 * CPT PCH is quite different, having many bits moved
2474 * to the TRANS_DP_CTL register instead. That
2475 * configuration happens (oddly) in ironlake_pch_enable
2478 /* Preserve the BIOS-computed detected bit. This is
2479 * supposed to be read-only.
2481 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2483 /* Handle DP bits in common between all three register formats */
2484 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2485 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2487 /* Split out the IBX/CPU vs CPT settings */
2489 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2490 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2491 intel_dp->DP |= DP_SYNC_HS_HIGH;
2492 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2493 intel_dp->DP |= DP_SYNC_VS_HIGH;
2494 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2496 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2497 intel_dp->DP |= DP_ENHANCED_FRAMING;
2499 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2500 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2503 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2505 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2506 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2507 trans_dp |= TRANS_DP_ENH_FRAMING;
2509 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2510 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2512 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2513 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2515 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2516 intel_dp->DP |= DP_SYNC_HS_HIGH;
2517 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2518 intel_dp->DP |= DP_SYNC_VS_HIGH;
2519 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2521 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2522 intel_dp->DP |= DP_ENHANCED_FRAMING;
2524 if (IS_CHERRYVIEW(dev_priv))
2525 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2527 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2531 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2532 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2534 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2535 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2537 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2538 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2540 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2542 static void wait_panel_status(struct intel_dp *intel_dp,
2546 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2547 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2549 lockdep_assert_held(&dev_priv->pps_mutex);
2551 intel_pps_verify_state(intel_dp);
2553 pp_stat_reg = _pp_stat_reg(intel_dp);
2554 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2556 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2558 I915_READ(pp_stat_reg),
2559 I915_READ(pp_ctrl_reg));
2561 if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2563 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2564 I915_READ(pp_stat_reg),
2565 I915_READ(pp_ctrl_reg));
2567 DRM_DEBUG_KMS("Wait complete\n");
2570 static void wait_panel_on(struct intel_dp *intel_dp)
2572 DRM_DEBUG_KMS("Wait for panel power on\n");
2573 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2576 static void wait_panel_off(struct intel_dp *intel_dp)
2578 DRM_DEBUG_KMS("Wait for panel power off time\n");
2579 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2582 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2584 ktime_t panel_power_on_time;
2585 s64 panel_power_off_duration;
2587 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2589 /* take the difference of currrent time and panel power off time
2590 * and then make panel wait for t11_t12 if needed. */
2591 panel_power_on_time = ktime_get_boottime();
2592 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2594 /* When we disable the VDD override bit last we have to do the manual
2596 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2597 wait_remaining_ms_from_jiffies(jiffies,
2598 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2600 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2603 static void wait_backlight_on(struct intel_dp *intel_dp)
2605 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2606 intel_dp->backlight_on_delay);
2609 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2611 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2612 intel_dp->backlight_off_delay);
2615 /* Read the current pp_control value, unlocking the register if it
2619 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2621 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2624 lockdep_assert_held(&dev_priv->pps_mutex);
2626 control = I915_READ(_pp_ctrl_reg(intel_dp));
2627 if (WARN_ON(!HAS_DDI(dev_priv) &&
2628 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2629 control &= ~PANEL_UNLOCK_MASK;
2630 control |= PANEL_UNLOCK_REGS;
2636 * Must be paired with edp_panel_vdd_off().
2637 * Must hold pps_mutex around the whole on/off sequence.
2638 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2640 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2642 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2643 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2645 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2646 bool need_to_disable = !intel_dp->want_panel_vdd;
2648 lockdep_assert_held(&dev_priv->pps_mutex);
2650 if (!intel_dp_is_edp(intel_dp))
2653 cancel_delayed_work(&intel_dp->panel_vdd_work);
2654 intel_dp->want_panel_vdd = true;
2656 if (edp_have_panel_vdd(intel_dp))
2657 return need_to_disable;
2659 intel_display_power_get(dev_priv,
2660 intel_aux_power_domain(intel_dig_port));
2662 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2663 intel_dig_port->base.base.base.id,
2664 intel_dig_port->base.base.name);
2666 if (!edp_have_panel_power(intel_dp))
2667 wait_panel_power_cycle(intel_dp);
2669 pp = ironlake_get_pp_control(intel_dp);
2670 pp |= EDP_FORCE_VDD;
2672 pp_stat_reg = _pp_stat_reg(intel_dp);
2673 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2675 I915_WRITE(pp_ctrl_reg, pp);
2676 POSTING_READ(pp_ctrl_reg);
2677 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2678 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2680 * If the panel wasn't on, delay before accessing aux channel
2682 if (!edp_have_panel_power(intel_dp)) {
2683 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2684 intel_dig_port->base.base.base.id,
2685 intel_dig_port->base.base.name);
2686 msleep(intel_dp->panel_power_up_delay);
2689 return need_to_disable;
2693 * Must be paired with intel_edp_panel_vdd_off() or
2694 * intel_edp_panel_off().
2695 * Nested calls to these functions are not allowed since
2696 * we drop the lock. Caller must use some higher level
2697 * locking to prevent nested calls from other threads.
2699 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2701 intel_wakeref_t wakeref;
2704 if (!intel_dp_is_edp(intel_dp))
2708 with_pps_lock(intel_dp, wakeref)
2709 vdd = edp_panel_vdd_on(intel_dp);
2710 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2711 dp_to_dig_port(intel_dp)->base.base.base.id,
2712 dp_to_dig_port(intel_dp)->base.base.name);
2715 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2717 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2718 struct intel_digital_port *intel_dig_port =
2719 dp_to_dig_port(intel_dp);
2721 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2723 lockdep_assert_held(&dev_priv->pps_mutex);
2725 WARN_ON(intel_dp->want_panel_vdd);
2727 if (!edp_have_panel_vdd(intel_dp))
2730 DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2731 intel_dig_port->base.base.base.id,
2732 intel_dig_port->base.base.name);
2734 pp = ironlake_get_pp_control(intel_dp);
2735 pp &= ~EDP_FORCE_VDD;
2737 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2738 pp_stat_reg = _pp_stat_reg(intel_dp);
2740 I915_WRITE(pp_ctrl_reg, pp);
2741 POSTING_READ(pp_ctrl_reg);
2743 /* Make sure sequencer is idle before allowing subsequent activity */
2744 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2745 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2747 if ((pp & PANEL_POWER_ON) == 0)
2748 intel_dp->panel_power_off_time = ktime_get_boottime();
2750 intel_display_power_put_unchecked(dev_priv,
2751 intel_aux_power_domain(intel_dig_port));
2754 static void edp_panel_vdd_work(struct work_struct *__work)
2756 struct intel_dp *intel_dp =
2757 container_of(to_delayed_work(__work),
2758 struct intel_dp, panel_vdd_work);
2759 intel_wakeref_t wakeref;
2761 with_pps_lock(intel_dp, wakeref) {
2762 if (!intel_dp->want_panel_vdd)
2763 edp_panel_vdd_off_sync(intel_dp);
2767 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2769 unsigned long delay;
2772 * Queue the timer to fire a long time from now (relative to the power
2773 * down delay) to keep the panel power up across a sequence of
2776 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2777 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2781 * Must be paired with edp_panel_vdd_on().
2782 * Must hold pps_mutex around the whole on/off sequence.
2783 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2785 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2787 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2789 lockdep_assert_held(&dev_priv->pps_mutex);
2791 if (!intel_dp_is_edp(intel_dp))
2794 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2795 dp_to_dig_port(intel_dp)->base.base.base.id,
2796 dp_to_dig_port(intel_dp)->base.base.name);
2798 intel_dp->want_panel_vdd = false;
2801 edp_panel_vdd_off_sync(intel_dp);
2803 edp_panel_vdd_schedule_off(intel_dp);
2806 static void edp_panel_on(struct intel_dp *intel_dp)
2808 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2810 i915_reg_t pp_ctrl_reg;
2812 lockdep_assert_held(&dev_priv->pps_mutex);
2814 if (!intel_dp_is_edp(intel_dp))
2817 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2818 dp_to_dig_port(intel_dp)->base.base.base.id,
2819 dp_to_dig_port(intel_dp)->base.base.name);
2821 if (WARN(edp_have_panel_power(intel_dp),
2822 "[ENCODER:%d:%s] panel power already on\n",
2823 dp_to_dig_port(intel_dp)->base.base.base.id,
2824 dp_to_dig_port(intel_dp)->base.base.name))
2827 wait_panel_power_cycle(intel_dp);
2829 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2830 pp = ironlake_get_pp_control(intel_dp);
2831 if (IS_GEN(dev_priv, 5)) {
2832 /* ILK workaround: disable reset around power sequence */
2833 pp &= ~PANEL_POWER_RESET;
2834 I915_WRITE(pp_ctrl_reg, pp);
2835 POSTING_READ(pp_ctrl_reg);
2838 pp |= PANEL_POWER_ON;
2839 if (!IS_GEN(dev_priv, 5))
2840 pp |= PANEL_POWER_RESET;
2842 I915_WRITE(pp_ctrl_reg, pp);
2843 POSTING_READ(pp_ctrl_reg);
2845 wait_panel_on(intel_dp);
2846 intel_dp->last_power_on = jiffies;
2848 if (IS_GEN(dev_priv, 5)) {
2849 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2850 I915_WRITE(pp_ctrl_reg, pp);
2851 POSTING_READ(pp_ctrl_reg);
2855 void intel_edp_panel_on(struct intel_dp *intel_dp)
2857 intel_wakeref_t wakeref;
2859 if (!intel_dp_is_edp(intel_dp))
2862 with_pps_lock(intel_dp, wakeref)
2863 edp_panel_on(intel_dp);
2867 static void edp_panel_off(struct intel_dp *intel_dp)
2869 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2870 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2872 i915_reg_t pp_ctrl_reg;
2874 lockdep_assert_held(&dev_priv->pps_mutex);
2876 if (!intel_dp_is_edp(intel_dp))
2879 DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2880 dig_port->base.base.base.id, dig_port->base.base.name);
2882 WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2883 dig_port->base.base.base.id, dig_port->base.base.name);
2885 pp = ironlake_get_pp_control(intel_dp);
2886 /* We need to switch off panel power _and_ force vdd, for otherwise some
2887 * panels get very unhappy and cease to work. */
2888 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2891 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2893 intel_dp->want_panel_vdd = false;
2895 I915_WRITE(pp_ctrl_reg, pp);
2896 POSTING_READ(pp_ctrl_reg);
2898 wait_panel_off(intel_dp);
2899 intel_dp->panel_power_off_time = ktime_get_boottime();
2901 /* We got a reference when we enabled the VDD. */
2902 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2905 void intel_edp_panel_off(struct intel_dp *intel_dp)
2907 intel_wakeref_t wakeref;
2909 if (!intel_dp_is_edp(intel_dp))
2912 with_pps_lock(intel_dp, wakeref)
2913 edp_panel_off(intel_dp);
2916 /* Enable backlight in the panel power control. */
2917 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2919 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2920 intel_wakeref_t wakeref;
2923 * If we enable the backlight right away following a panel power
2924 * on, we may see slight flicker as the panel syncs with the eDP
2925 * link. So delay a bit to make sure the image is solid before
2926 * allowing it to appear.
2928 wait_backlight_on(intel_dp);
2930 with_pps_lock(intel_dp, wakeref) {
2931 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2934 pp = ironlake_get_pp_control(intel_dp);
2935 pp |= EDP_BLC_ENABLE;
2937 I915_WRITE(pp_ctrl_reg, pp);
2938 POSTING_READ(pp_ctrl_reg);
2942 /* Enable backlight PWM and backlight PP control. */
2943 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2944 const struct drm_connector_state *conn_state)
2946 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2948 if (!intel_dp_is_edp(intel_dp))
2951 DRM_DEBUG_KMS("\n");
2953 intel_panel_enable_backlight(crtc_state, conn_state);
2954 _intel_edp_backlight_on(intel_dp);
2957 /* Disable backlight in the panel power control. */
2958 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2960 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2961 intel_wakeref_t wakeref;
2963 if (!intel_dp_is_edp(intel_dp))
2966 with_pps_lock(intel_dp, wakeref) {
2967 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2970 pp = ironlake_get_pp_control(intel_dp);
2971 pp &= ~EDP_BLC_ENABLE;
2973 I915_WRITE(pp_ctrl_reg, pp);
2974 POSTING_READ(pp_ctrl_reg);
2977 intel_dp->last_backlight_off = jiffies;
2978 edp_wait_backlight_off(intel_dp);
2981 /* Disable backlight PP control and backlight PWM. */
2982 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2984 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2986 if (!intel_dp_is_edp(intel_dp))
2989 DRM_DEBUG_KMS("\n");
2991 _intel_edp_backlight_off(intel_dp);
2992 intel_panel_disable_backlight(old_conn_state);
2996 * Hook for controlling the panel power control backlight through the bl_power
2997 * sysfs attribute. Take care to handle multiple calls.
2999 static void intel_edp_backlight_power(struct intel_connector *connector,
3002 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
3003 intel_wakeref_t wakeref;
3007 with_pps_lock(intel_dp, wakeref)
3008 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3009 if (is_enabled == enable)
3012 DRM_DEBUG_KMS("panel power control backlight %s\n",
3013 enable ? "enable" : "disable");
3016 _intel_edp_backlight_on(intel_dp);
3018 _intel_edp_backlight_off(intel_dp);
3021 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3023 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3024 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3025 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
3027 I915_STATE_WARN(cur_state != state,
3028 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3029 dig_port->base.base.base.id, dig_port->base.base.name,
3030 onoff(state), onoff(cur_state));
3032 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3034 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3036 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
3038 I915_STATE_WARN(cur_state != state,
3039 "eDP PLL state assertion failure (expected %s, current %s)\n",
3040 onoff(state), onoff(cur_state));
3042 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3043 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3045 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
3046 const struct intel_crtc_state *pipe_config)
3048 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3049 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3051 assert_pipe_disabled(dev_priv, crtc->pipe);
3052 assert_dp_port_disabled(intel_dp);
3053 assert_edp_pll_disabled(dev_priv);
3055 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
3056 pipe_config->port_clock);
3058 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3060 if (pipe_config->port_clock == 162000)
3061 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3063 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3065 I915_WRITE(DP_A, intel_dp->DP);
3070 * [DevILK] Work around required when enabling DP PLL
3071 * while a pipe is enabled going to FDI:
3072 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3073 * 2. Program DP PLL enable
3075 if (IS_GEN(dev_priv, 5))
3076 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3078 intel_dp->DP |= DP_PLL_ENABLE;
3080 I915_WRITE(DP_A, intel_dp->DP);
3085 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
3086 const struct intel_crtc_state *old_crtc_state)
3088 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3091 assert_pipe_disabled(dev_priv, crtc->pipe);
3092 assert_dp_port_disabled(intel_dp);
3093 assert_edp_pll_enabled(dev_priv);
3095 DRM_DEBUG_KMS("disabling eDP PLL\n");
3097 intel_dp->DP &= ~DP_PLL_ENABLE;
3099 I915_WRITE(DP_A, intel_dp->DP);
3104 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3107 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3108 * be capable of signalling downstream hpd with a long pulse.
3109 * Whether or not that means D3 is safe to use is not clear,
3110 * but let's assume so until proven otherwise.
3112 * FIXME should really check all downstream ports...
3114 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3115 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3116 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3119 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3120 const struct intel_crtc_state *crtc_state,
3125 if (!crtc_state->dsc.compression_enable)
3128 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3129 enable ? DP_DECOMPRESSION_EN : 0);
3131 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3132 enable ? "enable" : "disable");
3135 /* If the sink supports it, try to set the power state appropriately */
3136 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3140 /* Should have a valid DPCD by this point */
3141 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3144 if (mode != DRM_MODE_DPMS_ON) {
3145 if (downstream_hpd_needs_d0(intel_dp))
3148 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3151 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3154 * When turning on, we need to retry for 1ms to give the sink
3157 for (i = 0; i < 3; i++) {
3158 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3165 if (ret == 1 && lspcon->active)
3166 lspcon_wait_pcon_mode(lspcon);
3170 DRM_DEBUG_KMS("failed to %s sink power state\n",
3171 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3174 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3175 enum port port, enum pipe *pipe)
3179 for_each_pipe(dev_priv, p) {
3180 u32 val = I915_READ(TRANS_DP_CTL(p));
3182 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3188 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3190 /* must initialize pipe to something for the asserts */
3196 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3197 i915_reg_t dp_reg, enum port port,
3203 val = I915_READ(dp_reg);
3205 ret = val & DP_PORT_EN;
3207 /* asserts want to know the pipe even if the port is disabled */
3208 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3209 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3210 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3211 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3212 else if (IS_CHERRYVIEW(dev_priv))
3213 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3215 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3220 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3224 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3225 intel_wakeref_t wakeref;
3228 wakeref = intel_display_power_get_if_enabled(dev_priv,
3229 encoder->power_domain);
3233 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3234 encoder->port, pipe);
3236 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3241 static void intel_dp_get_config(struct intel_encoder *encoder,
3242 struct intel_crtc_state *pipe_config)
3244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3245 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3247 enum port port = encoder->port;
3248 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3250 if (encoder->type == INTEL_OUTPUT_EDP)
3251 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3253 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3255 tmp = I915_READ(intel_dp->output_reg);
3257 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3259 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3260 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3262 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3263 flags |= DRM_MODE_FLAG_PHSYNC;
3265 flags |= DRM_MODE_FLAG_NHSYNC;
3267 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3268 flags |= DRM_MODE_FLAG_PVSYNC;
3270 flags |= DRM_MODE_FLAG_NVSYNC;
3272 if (tmp & DP_SYNC_HS_HIGH)
3273 flags |= DRM_MODE_FLAG_PHSYNC;
3275 flags |= DRM_MODE_FLAG_NHSYNC;
3277 if (tmp & DP_SYNC_VS_HIGH)
3278 flags |= DRM_MODE_FLAG_PVSYNC;
3280 flags |= DRM_MODE_FLAG_NVSYNC;
3283 pipe_config->hw.adjusted_mode.flags |= flags;
3285 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3286 pipe_config->limited_color_range = true;
3288 pipe_config->lane_count =
3289 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3291 intel_dp_get_m_n(crtc, pipe_config);
3293 if (port == PORT_A) {
3294 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3295 pipe_config->port_clock = 162000;
3297 pipe_config->port_clock = 270000;
3300 pipe_config->hw.adjusted_mode.crtc_clock =
3301 intel_dotclock_calculate(pipe_config->port_clock,
3302 &pipe_config->dp_m_n);
3304 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3305 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3307 * This is a big fat ugly hack.
3309 * Some machines in UEFI boot mode provide us a VBT that has 18
3310 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3311 * unknown we fail to light up. Yet the same BIOS boots up with
3312 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3313 * max, not what it tells us to use.
3315 * Note: This will still be broken if the eDP panel is not lit
3316 * up by the BIOS, and thus we can't get the mode at module
3319 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3320 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3321 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3325 static void intel_disable_dp(struct intel_encoder *encoder,
3326 const struct intel_crtc_state *old_crtc_state,
3327 const struct drm_connector_state *old_conn_state)
3329 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3331 intel_dp->link_trained = false;
3333 if (old_crtc_state->has_audio)
3334 intel_audio_codec_disable(encoder,
3335 old_crtc_state, old_conn_state);
3337 /* Make sure the panel is off before trying to change the mode. But also
3338 * ensure that we have vdd while we switch off the panel. */
3339 intel_edp_panel_vdd_on(intel_dp);
3340 intel_edp_backlight_off(old_conn_state);
3341 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3342 intel_edp_panel_off(intel_dp);
3345 static void g4x_disable_dp(struct intel_encoder *encoder,
3346 const struct intel_crtc_state *old_crtc_state,
3347 const struct drm_connector_state *old_conn_state)
3349 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3352 static void vlv_disable_dp(struct intel_encoder *encoder,
3353 const struct intel_crtc_state *old_crtc_state,
3354 const struct drm_connector_state *old_conn_state)
3356 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3359 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3360 const struct intel_crtc_state *old_crtc_state,
3361 const struct drm_connector_state *old_conn_state)
3363 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3364 enum port port = encoder->port;
3367 * Bspec does not list a specific disable sequence for g4x DP.
3368 * Follow the ilk+ sequence (disable pipe before the port) for
3369 * g4x DP as it does not suffer from underruns like the normal
3370 * g4x modeset sequence (disable pipe after the port).
3372 intel_dp_link_down(encoder, old_crtc_state);
3374 /* Only ilk+ has port A */
3376 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3379 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3380 const struct intel_crtc_state *old_crtc_state,
3381 const struct drm_connector_state *old_conn_state)
3383 intel_dp_link_down(encoder, old_crtc_state);
3386 static void chv_post_disable_dp(struct intel_encoder *encoder,
3387 const struct intel_crtc_state *old_crtc_state,
3388 const struct drm_connector_state *old_conn_state)
3390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3392 intel_dp_link_down(encoder, old_crtc_state);
3394 vlv_dpio_get(dev_priv);
3396 /* Assert data lane reset */
3397 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3399 vlv_dpio_put(dev_priv);
3403 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3407 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3408 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3409 enum port port = intel_dig_port->base.port;
3410 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3412 if (dp_train_pat & train_pat_mask)
3413 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3414 dp_train_pat & train_pat_mask);
3416 if (HAS_DDI(dev_priv)) {
3417 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3419 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3420 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3422 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3424 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3425 switch (dp_train_pat & train_pat_mask) {
3426 case DP_TRAINING_PATTERN_DISABLE:
3427 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3430 case DP_TRAINING_PATTERN_1:
3431 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3433 case DP_TRAINING_PATTERN_2:
3434 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3436 case DP_TRAINING_PATTERN_3:
3437 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3439 case DP_TRAINING_PATTERN_4:
3440 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3443 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3445 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3446 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3447 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3449 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3450 case DP_TRAINING_PATTERN_DISABLE:
3451 *DP |= DP_LINK_TRAIN_OFF_CPT;
3453 case DP_TRAINING_PATTERN_1:
3454 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3456 case DP_TRAINING_PATTERN_2:
3457 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3459 case DP_TRAINING_PATTERN_3:
3460 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3461 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3466 *DP &= ~DP_LINK_TRAIN_MASK;
3468 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3469 case DP_TRAINING_PATTERN_DISABLE:
3470 *DP |= DP_LINK_TRAIN_OFF;
3472 case DP_TRAINING_PATTERN_1:
3473 *DP |= DP_LINK_TRAIN_PAT_1;
3475 case DP_TRAINING_PATTERN_2:
3476 *DP |= DP_LINK_TRAIN_PAT_2;
3478 case DP_TRAINING_PATTERN_3:
3479 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3480 *DP |= DP_LINK_TRAIN_PAT_2;
3486 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3487 const struct intel_crtc_state *old_crtc_state)
3489 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3491 /* enable with pattern 1 (as per spec) */
3493 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3496 * Magic for VLV/CHV. We _must_ first set up the register
3497 * without actually enabling the port, and then do another
3498 * write to enable the port. Otherwise link training will
3499 * fail when the power sequencer is freshly used for this port.
3501 intel_dp->DP |= DP_PORT_EN;
3502 if (old_crtc_state->has_audio)
3503 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3505 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3506 POSTING_READ(intel_dp->output_reg);
3509 static void intel_enable_dp(struct intel_encoder *encoder,
3510 const struct intel_crtc_state *pipe_config,
3511 const struct drm_connector_state *conn_state)
3513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3514 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3515 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3516 u32 dp_reg = I915_READ(intel_dp->output_reg);
3517 enum pipe pipe = crtc->pipe;
3518 intel_wakeref_t wakeref;
3520 if (WARN_ON(dp_reg & DP_PORT_EN))
3523 with_pps_lock(intel_dp, wakeref) {
3524 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3525 vlv_init_panel_power_sequencer(encoder, pipe_config);
3527 intel_dp_enable_port(intel_dp, pipe_config);
3529 edp_panel_vdd_on(intel_dp);
3530 edp_panel_on(intel_dp);
3531 edp_panel_vdd_off(intel_dp, true);
3534 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3535 unsigned int lane_mask = 0x0;
3537 if (IS_CHERRYVIEW(dev_priv))
3538 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3540 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3544 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3545 intel_dp_start_link_train(intel_dp);
3546 intel_dp_stop_link_train(intel_dp);
3548 if (pipe_config->has_audio) {
3549 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3551 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3555 static void g4x_enable_dp(struct intel_encoder *encoder,
3556 const struct intel_crtc_state *pipe_config,
3557 const struct drm_connector_state *conn_state)
3559 intel_enable_dp(encoder, pipe_config, conn_state);
3560 intel_edp_backlight_on(pipe_config, conn_state);
3563 static void vlv_enable_dp(struct intel_encoder *encoder,
3564 const struct intel_crtc_state *pipe_config,
3565 const struct drm_connector_state *conn_state)
3567 intel_edp_backlight_on(pipe_config, conn_state);
3570 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3571 const struct intel_crtc_state *pipe_config,
3572 const struct drm_connector_state *conn_state)
3574 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3575 enum port port = encoder->port;
3577 intel_dp_prepare(encoder, pipe_config);
3579 /* Only ilk+ has port A */
3581 ironlake_edp_pll_on(intel_dp, pipe_config);
3584 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3587 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3588 enum pipe pipe = intel_dp->pps_pipe;
3589 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3591 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3593 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3596 edp_panel_vdd_off_sync(intel_dp);
3599 * VLV seems to get confused when multiple power sequencers
3600 * have the same port selected (even if only one has power/vdd
3601 * enabled). The failure manifests as vlv_wait_port_ready() failing
3602 * CHV on the other hand doesn't seem to mind having the same port
3603 * selected in multiple power sequencers, but let's clear the
3604 * port select always when logically disconnecting a power sequencer
3607 DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3608 pipe_name(pipe), intel_dig_port->base.base.base.id,
3609 intel_dig_port->base.base.name);
3610 I915_WRITE(pp_on_reg, 0);
3611 POSTING_READ(pp_on_reg);
3613 intel_dp->pps_pipe = INVALID_PIPE;
3616 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3619 struct intel_encoder *encoder;
3621 lockdep_assert_held(&dev_priv->pps_mutex);
3623 for_each_intel_dp(&dev_priv->drm, encoder) {
3624 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3626 WARN(intel_dp->active_pipe == pipe,
3627 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3628 pipe_name(pipe), encoder->base.base.id,
3629 encoder->base.name);
3631 if (intel_dp->pps_pipe != pipe)
3634 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3635 pipe_name(pipe), encoder->base.base.id,
3636 encoder->base.name);
3638 /* make sure vdd is off before we steal it */
3639 vlv_detach_power_sequencer(intel_dp);
3643 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3644 const struct intel_crtc_state *crtc_state)
3646 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3647 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3648 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3650 lockdep_assert_held(&dev_priv->pps_mutex);
3652 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3654 if (intel_dp->pps_pipe != INVALID_PIPE &&
3655 intel_dp->pps_pipe != crtc->pipe) {
3657 * If another power sequencer was being used on this
3658 * port previously make sure to turn off vdd there while
3659 * we still have control of it.
3661 vlv_detach_power_sequencer(intel_dp);
3665 * We may be stealing the power
3666 * sequencer from another port.
3668 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3670 intel_dp->active_pipe = crtc->pipe;
3672 if (!intel_dp_is_edp(intel_dp))
3675 /* now it's all ours */
3676 intel_dp->pps_pipe = crtc->pipe;
3678 DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3679 pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3680 encoder->base.name);
3682 /* init power sequencer on this pipe and port */
3683 intel_dp_init_panel_power_sequencer(intel_dp);
3684 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3687 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3688 const struct intel_crtc_state *pipe_config,
3689 const struct drm_connector_state *conn_state)
3691 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3693 intel_enable_dp(encoder, pipe_config, conn_state);
3696 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3697 const struct intel_crtc_state *pipe_config,
3698 const struct drm_connector_state *conn_state)
3700 intel_dp_prepare(encoder, pipe_config);
3702 vlv_phy_pre_pll_enable(encoder, pipe_config);
3705 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3706 const struct intel_crtc_state *pipe_config,
3707 const struct drm_connector_state *conn_state)
3709 chv_phy_pre_encoder_enable(encoder, pipe_config);
3711 intel_enable_dp(encoder, pipe_config, conn_state);
3713 /* Second common lane will stay alive on its own now */
3714 chv_phy_release_cl2_override(encoder);
3717 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3718 const struct intel_crtc_state *pipe_config,
3719 const struct drm_connector_state *conn_state)
3721 intel_dp_prepare(encoder, pipe_config);
3723 chv_phy_pre_pll_enable(encoder, pipe_config);
3726 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3727 const struct intel_crtc_state *old_crtc_state,
3728 const struct drm_connector_state *old_conn_state)
3730 chv_phy_post_pll_disable(encoder, old_crtc_state);
3734 * Fetch AUX CH registers 0x202 - 0x207 which contain
3735 * link status information
3738 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3740 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3741 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3744 /* These are source-specific values. */
3746 intel_dp_voltage_max(struct intel_dp *intel_dp)
3748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3749 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3750 enum port port = encoder->port;
3752 if (HAS_DDI(dev_priv))
3753 return intel_ddi_dp_voltage_max(encoder);
3754 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3755 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3756 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3757 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3758 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3759 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3761 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3765 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3767 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3768 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3769 enum port port = encoder->port;
3771 if (HAS_DDI(dev_priv)) {
3772 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3773 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3774 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3775 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3776 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3777 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3778 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3779 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3780 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3781 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3783 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3785 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3786 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3787 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3788 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3789 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3790 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3791 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3793 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3796 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3797 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3798 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3799 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3800 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3801 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3802 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3803 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3805 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3810 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3812 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3813 unsigned long demph_reg_value, preemph_reg_value,
3814 uniqtranscale_reg_value;
3815 u8 train_set = intel_dp->train_set[0];
3817 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3818 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3819 preemph_reg_value = 0x0004000;
3820 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3821 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3822 demph_reg_value = 0x2B405555;
3823 uniqtranscale_reg_value = 0x552AB83A;
3825 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3826 demph_reg_value = 0x2B404040;
3827 uniqtranscale_reg_value = 0x5548B83A;
3829 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3830 demph_reg_value = 0x2B245555;
3831 uniqtranscale_reg_value = 0x5560B83A;
3833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3834 demph_reg_value = 0x2B405555;
3835 uniqtranscale_reg_value = 0x5598DA3A;
3841 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3842 preemph_reg_value = 0x0002000;
3843 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3844 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3845 demph_reg_value = 0x2B404040;
3846 uniqtranscale_reg_value = 0x5552B83A;
3848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3849 demph_reg_value = 0x2B404848;
3850 uniqtranscale_reg_value = 0x5580B83A;
3852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3853 demph_reg_value = 0x2B404040;
3854 uniqtranscale_reg_value = 0x55ADDA3A;
3860 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3861 preemph_reg_value = 0x0000000;
3862 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3864 demph_reg_value = 0x2B305555;
3865 uniqtranscale_reg_value = 0x5570B83A;
3867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3868 demph_reg_value = 0x2B2B4040;
3869 uniqtranscale_reg_value = 0x55ADDA3A;
3875 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3876 preemph_reg_value = 0x0006000;
3877 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3879 demph_reg_value = 0x1B405555;
3880 uniqtranscale_reg_value = 0x55ADDA3A;
3890 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3891 uniqtranscale_reg_value, 0);
3896 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3898 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3899 u32 deemph_reg_value, margin_reg_value;
3900 bool uniq_trans_scale = false;
3901 u8 train_set = intel_dp->train_set[0];
3903 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3904 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3905 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3907 deemph_reg_value = 128;
3908 margin_reg_value = 52;
3910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3911 deemph_reg_value = 128;
3912 margin_reg_value = 77;
3914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3915 deemph_reg_value = 128;
3916 margin_reg_value = 102;
3918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3919 deemph_reg_value = 128;
3920 margin_reg_value = 154;
3921 uniq_trans_scale = true;
3927 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3928 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3930 deemph_reg_value = 85;
3931 margin_reg_value = 78;
3933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3934 deemph_reg_value = 85;
3935 margin_reg_value = 116;
3937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3938 deemph_reg_value = 85;
3939 margin_reg_value = 154;
3945 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3946 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3948 deemph_reg_value = 64;
3949 margin_reg_value = 104;
3951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3952 deemph_reg_value = 64;
3953 margin_reg_value = 154;
3959 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3960 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3962 deemph_reg_value = 43;
3963 margin_reg_value = 154;
3973 chv_set_phy_signal_level(encoder, deemph_reg_value,
3974 margin_reg_value, uniq_trans_scale);
3980 g4x_signal_levels(u8 train_set)
3982 u32 signal_levels = 0;
3984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3987 signal_levels |= DP_VOLTAGE_0_4;
3989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3990 signal_levels |= DP_VOLTAGE_0_6;
3992 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3993 signal_levels |= DP_VOLTAGE_0_8;
3995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3996 signal_levels |= DP_VOLTAGE_1_2;
3999 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4000 case DP_TRAIN_PRE_EMPH_LEVEL_0:
4002 signal_levels |= DP_PRE_EMPHASIS_0;
4004 case DP_TRAIN_PRE_EMPH_LEVEL_1:
4005 signal_levels |= DP_PRE_EMPHASIS_3_5;
4007 case DP_TRAIN_PRE_EMPH_LEVEL_2:
4008 signal_levels |= DP_PRE_EMPHASIS_6;
4010 case DP_TRAIN_PRE_EMPH_LEVEL_3:
4011 signal_levels |= DP_PRE_EMPHASIS_9_5;
4014 return signal_levels;
4017 /* SNB CPU eDP voltage swing and pre-emphasis control */
4019 snb_cpu_edp_signal_levels(u8 train_set)
4021 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4022 DP_TRAIN_PRE_EMPHASIS_MASK);
4023 switch (signal_levels) {
4024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4026 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4028 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4031 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4034 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4037 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4039 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4040 "0x%x\n", signal_levels);
4041 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4045 /* IVB CPU eDP voltage swing and pre-emphasis control */
4047 ivb_cpu_edp_signal_levels(u8 train_set)
4049 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4050 DP_TRAIN_PRE_EMPHASIS_MASK);
4051 switch (signal_levels) {
4052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4053 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4055 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4057 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4060 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4062 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4065 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4067 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4070 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4071 "0x%x\n", signal_levels);
4072 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4077 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4079 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4080 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4081 enum port port = intel_dig_port->base.port;
4082 u32 signal_levels, mask = 0;
4083 u8 train_set = intel_dp->train_set[0];
4085 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4086 signal_levels = bxt_signal_levels(intel_dp);
4087 } else if (HAS_DDI(dev_priv)) {
4088 signal_levels = ddi_signal_levels(intel_dp);
4089 mask = DDI_BUF_EMP_MASK;
4090 } else if (IS_CHERRYVIEW(dev_priv)) {
4091 signal_levels = chv_signal_levels(intel_dp);
4092 } else if (IS_VALLEYVIEW(dev_priv)) {
4093 signal_levels = vlv_signal_levels(intel_dp);
4094 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4095 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4096 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4097 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4098 signal_levels = snb_cpu_edp_signal_levels(train_set);
4099 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4101 signal_levels = g4x_signal_levels(train_set);
4102 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4106 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4108 DRM_DEBUG_KMS("Using vswing level %d\n",
4109 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4110 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4111 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4112 DP_TRAIN_PRE_EMPHASIS_SHIFT);
4114 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4116 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4117 POSTING_READ(intel_dp->output_reg);
4121 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4124 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4125 struct drm_i915_private *dev_priv =
4126 to_i915(intel_dig_port->base.base.dev);
4128 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4130 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4131 POSTING_READ(intel_dp->output_reg);
4134 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4136 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4137 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4138 enum port port = intel_dig_port->base.port;
4141 if (!HAS_DDI(dev_priv))
4144 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4145 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4146 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4147 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4150 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4151 * reason we need to set idle transmission mode is to work around a HW
4152 * issue where we enable the pipe while not in idle link-training mode.
4153 * In this case there is requirement to wait for a minimum number of
4154 * idle patterns to be sent.
4156 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4159 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4160 DP_TP_STATUS_IDLE_DONE, 1))
4161 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4165 intel_dp_link_down(struct intel_encoder *encoder,
4166 const struct intel_crtc_state *old_crtc_state)
4168 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4169 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4170 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4171 enum port port = encoder->port;
4172 u32 DP = intel_dp->DP;
4174 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4177 DRM_DEBUG_KMS("\n");
4179 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4180 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4181 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4182 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4184 DP &= ~DP_LINK_TRAIN_MASK;
4185 DP |= DP_LINK_TRAIN_PAT_IDLE;
4187 I915_WRITE(intel_dp->output_reg, DP);
4188 POSTING_READ(intel_dp->output_reg);
4190 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4191 I915_WRITE(intel_dp->output_reg, DP);
4192 POSTING_READ(intel_dp->output_reg);
4195 * HW workaround for IBX, we need to move the port
4196 * to transcoder A after disabling it to allow the
4197 * matching HDMI port to be enabled on transcoder A.
4199 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4201 * We get CPU/PCH FIFO underruns on the other pipe when
4202 * doing the workaround. Sweep them under the rug.
4204 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4205 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4207 /* always enable with pattern 1 (as per spec) */
4208 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4209 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4210 DP_LINK_TRAIN_PAT_1;
4211 I915_WRITE(intel_dp->output_reg, DP);
4212 POSTING_READ(intel_dp->output_reg);
4215 I915_WRITE(intel_dp->output_reg, DP);
4216 POSTING_READ(intel_dp->output_reg);
4218 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4219 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4220 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4223 msleep(intel_dp->panel_power_down_delay);
4227 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4228 intel_wakeref_t wakeref;
4230 with_pps_lock(intel_dp, wakeref)
4231 intel_dp->active_pipe = INVALID_PIPE;
4236 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4241 * Prior to DP1.3 the bit represented by
4242 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4243 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4244 * the true capability of the panel. The only way to check is to
4245 * then compare 0000h and 2200h.
4247 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4248 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4251 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4252 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4253 DRM_ERROR("DPCD failed read at extended capabilities\n");
4257 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4258 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4262 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4265 DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4266 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4268 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4272 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4274 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4275 sizeof(intel_dp->dpcd)) < 0)
4276 return false; /* aux transfer failed */
4278 intel_dp_extended_receiver_capabilities(intel_dp);
4280 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4282 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4285 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4289 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4292 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4295 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4298 * Clear the cached register set to avoid using stale values
4299 * for the sinks that do not support DSC.
4301 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4303 /* Clear fec_capable to avoid using stale values */
4304 intel_dp->fec_capable = 0;
4306 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4307 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4308 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4309 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4311 sizeof(intel_dp->dsc_dpcd)) < 0)
4312 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4315 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4316 (int)sizeof(intel_dp->dsc_dpcd),
4317 intel_dp->dsc_dpcd);
4319 /* FEC is supported only on DP 1.4 */
4320 if (!intel_dp_is_edp(intel_dp) &&
4321 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4322 &intel_dp->fec_capable) < 0)
4323 DRM_ERROR("Failed to read FEC DPCD register\n");
4325 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4330 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4332 struct drm_i915_private *dev_priv =
4333 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4335 /* this function is meant to be called only once */
4336 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4338 if (!intel_dp_read_dpcd(intel_dp))
4341 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4342 drm_dp_is_branch(intel_dp->dpcd));
4345 * Read the eDP display control registers.
4347 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4348 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4349 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4350 * method). The display control registers should read zero if they're
4351 * not supported anyway.
4353 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4354 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4355 sizeof(intel_dp->edp_dpcd))
4356 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4357 intel_dp->edp_dpcd);
4360 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4361 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4363 intel_psr_init_dpcd(intel_dp);
4365 /* Read the eDP 1.4+ supported link rates. */
4366 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4367 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4370 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4371 sink_rates, sizeof(sink_rates));
4373 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4374 int val = le16_to_cpu(sink_rates[i]);
4379 /* Value read multiplied by 200kHz gives the per-lane
4380 * link rate in kHz. The source rates are, however,
4381 * stored in terms of LS_Clk kHz. The full conversion
4382 * back to symbols is
4383 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4385 intel_dp->sink_rates[i] = (val * 200) / 10;
4387 intel_dp->num_sink_rates = i;
4391 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4392 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4394 if (intel_dp->num_sink_rates)
4395 intel_dp->use_rate_select = true;
4397 intel_dp_set_sink_rates(intel_dp);
4399 intel_dp_set_common_rates(intel_dp);
4401 /* Read the eDP DSC DPCD registers */
4402 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4403 intel_dp_get_dsc_sink_cap(intel_dp);
4410 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4412 if (!intel_dp_read_dpcd(intel_dp))
4416 * Don't clobber cached eDP rates. Also skip re-reading
4417 * the OUI/ID since we know it won't change.
4419 if (!intel_dp_is_edp(intel_dp)) {
4420 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4421 drm_dp_is_branch(intel_dp->dpcd));
4423 intel_dp_set_sink_rates(intel_dp);
4424 intel_dp_set_common_rates(intel_dp);
4428 * Some eDP panels do not set a valid value for sink count, that is why
4429 * it don't care about read it here and in intel_edp_init_dpcd().
4431 if (!intel_dp_is_edp(intel_dp) &&
4432 !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4436 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4441 * Sink count can change between short pulse hpd hence
4442 * a member variable in intel_dp will track any changes
4443 * between short pulse interrupts.
4445 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4448 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4449 * a dongle is present but no display. Unless we require to know
4450 * if a dongle is present or not, we don't need to update
4451 * downstream port information. So, an early return here saves
4452 * time from performing other operations which are not required.
4454 if (!intel_dp->sink_count)
4458 if (!drm_dp_is_branch(intel_dp->dpcd))
4459 return true; /* native DP sink */
4461 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4462 return true; /* no per-port downstream info */
4464 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4465 intel_dp->downstream_ports,
4466 DP_MAX_DOWNSTREAM_PORTS) < 0)
4467 return false; /* downstream port status fetch failed */
4473 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4477 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4480 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4483 return mstm_cap & DP_MST_CAP;
4487 intel_dp_can_mst(struct intel_dp *intel_dp)
4489 return i915_modparams.enable_dp_mst &&
4490 intel_dp->can_mst &&
4491 intel_dp_sink_can_mst(intel_dp);
4495 intel_dp_configure_mst(struct intel_dp *intel_dp)
4497 struct intel_encoder *encoder =
4498 &dp_to_dig_port(intel_dp)->base;
4499 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4501 DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4502 encoder->base.base.id, encoder->base.name,
4503 yesno(intel_dp->can_mst), yesno(sink_can_mst),
4504 yesno(i915_modparams.enable_dp_mst));
4506 if (!intel_dp->can_mst)
4509 intel_dp->is_mst = sink_can_mst &&
4510 i915_modparams.enable_dp_mst;
4512 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4517 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4519 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4520 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4525 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4526 const struct drm_connector_state *conn_state)
4529 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4530 * of Color Encoding Format and Content Color Gamut], in order to
4531 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4533 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4536 switch (conn_state->colorspace) {
4537 case DRM_MODE_COLORIMETRY_SYCC_601:
4538 case DRM_MODE_COLORIMETRY_OPYCC_601:
4539 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4540 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4541 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4551 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
4552 const struct intel_crtc_state *crtc_state,
4553 const struct drm_connector_state *conn_state)
4555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4556 struct dp_sdp vsc_sdp = {};
4558 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4559 vsc_sdp.sdp_header.HB0 = 0;
4560 vsc_sdp.sdp_header.HB1 = 0x7;
4563 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4564 * Colorimetry Format indication.
4566 vsc_sdp.sdp_header.HB2 = 0x5;
4569 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4570 * Colorimetry Format indication (HB2 = 05h).
4572 vsc_sdp.sdp_header.HB3 = 0x13;
4574 /* DP 1.4a spec, Table 2-120 */
4575 switch (crtc_state->output_format) {
4576 case INTEL_OUTPUT_FORMAT_YCBCR444:
4577 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
4579 case INTEL_OUTPUT_FORMAT_YCBCR420:
4580 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
4582 case INTEL_OUTPUT_FORMAT_RGB:
4584 /* RGB: DB16[7:4] = 0h */
4588 switch (conn_state->colorspace) {
4589 case DRM_MODE_COLORIMETRY_BT709_YCC:
4590 vsc_sdp.db[16] |= 0x1;
4592 case DRM_MODE_COLORIMETRY_XVYCC_601:
4593 vsc_sdp.db[16] |= 0x2;
4595 case DRM_MODE_COLORIMETRY_XVYCC_709:
4596 vsc_sdp.db[16] |= 0x3;
4598 case DRM_MODE_COLORIMETRY_SYCC_601:
4599 vsc_sdp.db[16] |= 0x4;
4601 case DRM_MODE_COLORIMETRY_OPYCC_601:
4602 vsc_sdp.db[16] |= 0x5;
4604 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4605 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4606 vsc_sdp.db[16] |= 0x6;
4608 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4609 vsc_sdp.db[16] |= 0x7;
4611 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
4612 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
4613 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
4616 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
4618 /* RGB->YCBCR color conversion uses the BT.709 color space. */
4619 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4620 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4625 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4626 * the following Component Bit Depth values are defined:
4632 switch (crtc_state->pipe_bpp) {
4634 vsc_sdp.db[17] = 0x1;
4636 case 30: /* 10bpc */
4637 vsc_sdp.db[17] = 0x2;
4639 case 36: /* 12bpc */
4640 vsc_sdp.db[17] = 0x3;
4642 case 48: /* 16bpc */
4643 vsc_sdp.db[17] = 0x4;
4646 MISSING_CASE(crtc_state->pipe_bpp);
4651 * Dynamic Range (Bit 7)
4652 * 0 = VESA range, 1 = CTA range.
4653 * all YCbCr are always limited range
4655 vsc_sdp.db[17] |= 0x80;
4658 * Content Type (Bits 2:0)
4659 * 000b = Not defined.
4664 * All other values are RESERVED.
4665 * Note: See CTA-861-G for the definition and expected
4666 * processing by a stream sink for the above contect types.
4670 intel_dig_port->write_infoframe(&intel_dig_port->base,
4671 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4675 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
4676 const struct intel_crtc_state *crtc_state,
4677 const struct drm_connector_state *conn_state)
4679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4680 struct dp_sdp infoframe_sdp = {};
4681 struct hdmi_drm_infoframe drm_infoframe = {};
4682 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4683 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4687 ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
4689 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
4693 len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
4695 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4699 if (len != infoframe_size) {
4700 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4705 * Set up the infoframe sdp packet for HDR static metadata.
4706 * Prepare VSC Header for SU as per DP 1.4a spec,
4707 * Table 2-100 and Table 2-101
4710 /* Packet ID, 00h for non-Audio INFOFRAME */
4711 infoframe_sdp.sdp_header.HB0 = 0;
4713 * Packet Type 80h + Non-audio INFOFRAME Type value
4714 * HDMI_INFOFRAME_TYPE_DRM: 0x87,
4716 infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
4718 * Least Significant Eight Bits of (Data Byte Count – 1)
4719 * infoframe_size - 1,
4721 infoframe_sdp.sdp_header.HB2 = 0x1D;
4722 /* INFOFRAME SDP Version Number */
4723 infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
4724 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4725 infoframe_sdp.db[0] = drm_infoframe.version;
4726 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4727 infoframe_sdp.db[1] = drm_infoframe.length;
4729 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4730 * HDMI_INFOFRAME_HEADER_SIZE
4732 BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4733 memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4734 HDMI_DRM_INFOFRAME_SIZE);
4737 * Size of DP infoframe sdp packet for HDR static metadata is consist of
4738 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4739 * - Two Data Blocks: 2 bytes
4740 * CTA Header Byte2 (INFOFRAME Version Number)
4741 * CTA Header Byte3 (Length of INFOFRAME)
4742 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4744 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4745 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4746 * will pad rest of the size.
4748 intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
4749 HDMI_PACKET_TYPE_GAMUT_METADATA,
4751 sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
4754 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
4755 const struct intel_crtc_state *crtc_state,
4756 const struct drm_connector_state *conn_state)
4758 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
4761 intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
4764 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
4765 const struct intel_crtc_state *crtc_state,
4766 const struct drm_connector_state *conn_state)
4768 if (!conn_state->hdr_output_metadata)
4771 intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
4776 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4780 u8 test_lane_count, test_link_bw;
4784 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4785 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4789 DRM_DEBUG_KMS("Lane count read failed\n");
4792 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4794 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4797 DRM_DEBUG_KMS("Link Rate read failed\n");
4800 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4802 /* Validate the requested link rate and lane count */
4803 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4807 intel_dp->compliance.test_lane_count = test_lane_count;
4808 intel_dp->compliance.test_link_rate = test_link_rate;
4813 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4817 __be16 h_width, v_height;
4820 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4821 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4824 DRM_DEBUG_KMS("Test pattern read failed\n");
4827 if (test_pattern != DP_COLOR_RAMP)
4830 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4833 DRM_DEBUG_KMS("H Width read failed\n");
4837 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4840 DRM_DEBUG_KMS("V Height read failed\n");
4844 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4847 DRM_DEBUG_KMS("TEST MISC read failed\n");
4850 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4852 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4854 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4855 case DP_TEST_BIT_DEPTH_6:
4856 intel_dp->compliance.test_data.bpc = 6;
4858 case DP_TEST_BIT_DEPTH_8:
4859 intel_dp->compliance.test_data.bpc = 8;
4865 intel_dp->compliance.test_data.video_pattern = test_pattern;
4866 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4867 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4868 /* Set test active flag here so userspace doesn't interrupt things */
4869 intel_dp->compliance.test_active = 1;
4874 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4876 u8 test_result = DP_TEST_ACK;
4877 struct intel_connector *intel_connector = intel_dp->attached_connector;
4878 struct drm_connector *connector = &intel_connector->base;
4880 if (intel_connector->detect_edid == NULL ||
4881 connector->edid_corrupt ||
4882 intel_dp->aux.i2c_defer_count > 6) {
4883 /* Check EDID read for NACKs, DEFERs and corruption
4884 * (DP CTS 1.2 Core r1.1)
4885 * 4.2.2.4 : Failed EDID read, I2C_NAK
4886 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4887 * 4.2.2.6 : EDID corruption detected
4888 * Use failsafe mode for all cases
4890 if (intel_dp->aux.i2c_nack_count > 0 ||
4891 intel_dp->aux.i2c_defer_count > 0)
4892 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4893 intel_dp->aux.i2c_nack_count,
4894 intel_dp->aux.i2c_defer_count);
4895 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4897 struct edid *block = intel_connector->detect_edid;
4899 /* We have to write the checksum
4900 * of the last block read
4902 block += intel_connector->detect_edid->extensions;
4904 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4905 block->checksum) <= 0)
4906 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4908 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4909 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4912 /* Set test active flag here so userspace doesn't interrupt things */
4913 intel_dp->compliance.test_active = 1;
4918 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4920 u8 test_result = DP_TEST_NAK;
4924 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4926 u8 response = DP_TEST_NAK;
4930 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4932 DRM_DEBUG_KMS("Could not read test request from sink\n");
4937 case DP_TEST_LINK_TRAINING:
4938 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4939 response = intel_dp_autotest_link_training(intel_dp);
4941 case DP_TEST_LINK_VIDEO_PATTERN:
4942 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4943 response = intel_dp_autotest_video_pattern(intel_dp);
4945 case DP_TEST_LINK_EDID_READ:
4946 DRM_DEBUG_KMS("EDID test requested\n");
4947 response = intel_dp_autotest_edid(intel_dp);
4949 case DP_TEST_LINK_PHY_TEST_PATTERN:
4950 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4951 response = intel_dp_autotest_phy_pattern(intel_dp);
4954 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4958 if (response & DP_TEST_ACK)
4959 intel_dp->compliance.test_type = request;
4962 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4964 DRM_DEBUG_KMS("Could not write test response to sink\n");
4968 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4972 if (intel_dp->is_mst) {
4973 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4978 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4979 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4983 /* check link status - esi[10] = 0x200c */
4984 if (intel_dp->active_mst_links > 0 &&
4985 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4986 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4987 intel_dp_start_link_train(intel_dp);
4988 intel_dp_stop_link_train(intel_dp);
4991 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4992 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4995 for (retry = 0; retry < 3; retry++) {
4997 wret = drm_dp_dpcd_write(&intel_dp->aux,
4998 DP_SINK_COUNT_ESI+1,
5005 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5007 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
5015 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
5016 intel_dp->is_mst = false;
5017 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5025 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5027 u8 link_status[DP_LINK_STATUS_SIZE];
5029 if (!intel_dp->link_trained)
5033 * While PSR source HW is enabled, it will control main-link sending
5034 * frames, enabling and disabling it so trying to do a retrain will fail
5035 * as the link would or not be on or it could mix training patterns
5036 * and frame data at the same time causing retrain to fail.
5037 * Also when exiting PSR, HW will retrain the link anyways fixing
5038 * any link status error.
5040 if (intel_psr_enabled(intel_dp))
5043 if (!intel_dp_get_link_status(intel_dp, link_status))
5047 * Validate the cached values of intel_dp->link_rate and
5048 * intel_dp->lane_count before attempting to retrain.
5050 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5051 intel_dp->lane_count))
5054 /* Retrain if Channel EQ or CR not ok */
5055 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5058 int intel_dp_retrain_link(struct intel_encoder *encoder,
5059 struct drm_modeset_acquire_ctx *ctx)
5061 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5062 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
5063 struct intel_connector *connector = intel_dp->attached_connector;
5064 struct drm_connector_state *conn_state;
5065 struct intel_crtc_state *crtc_state;
5066 struct intel_crtc *crtc;
5069 /* FIXME handle the MST connectors as well */
5071 if (!connector || connector->base.status != connector_status_connected)
5074 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5079 conn_state = connector->base.state;
5081 crtc = to_intel_crtc(conn_state->crtc);
5085 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5089 crtc_state = to_intel_crtc_state(crtc->base.state);
5091 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
5093 if (!crtc_state->hw.active)
5096 if (conn_state->commit &&
5097 !try_wait_for_completion(&conn_state->commit->hw_done))
5100 if (!intel_dp_needs_link_retrain(intel_dp))
5103 /* Suppress underruns caused by re-training */
5104 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5105 if (crtc_state->has_pch_encoder)
5106 intel_set_pch_fifo_underrun_reporting(dev_priv,
5107 intel_crtc_pch_transcoder(crtc), false);
5109 intel_dp_start_link_train(intel_dp);
5110 intel_dp_stop_link_train(intel_dp);
5112 /* Keep underrun reporting disabled until things are stable */
5113 intel_wait_for_vblank(dev_priv, crtc->pipe);
5115 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5116 if (crtc_state->has_pch_encoder)
5117 intel_set_pch_fifo_underrun_reporting(dev_priv,
5118 intel_crtc_pch_transcoder(crtc), true);
5124 * If display is now connected check links status,
5125 * there has been known issues of link loss triggering
5128 * Some sinks (eg. ASUS PB287Q) seem to perform some
5129 * weird HPD ping pong during modesets. So we can apparently
5130 * end up with HPD going low during a modeset, and then
5131 * going back up soon after. And once that happens we must
5132 * retrain the link to get a picture. That's in case no
5133 * userspace component reacted to intermittent HPD dip.
5135 static enum intel_hotplug_state
5136 intel_dp_hotplug(struct intel_encoder *encoder,
5137 struct intel_connector *connector,
5140 struct drm_modeset_acquire_ctx ctx;
5141 enum intel_hotplug_state state;
5144 state = intel_encoder_hotplug(encoder, connector, irq_received);
5146 drm_modeset_acquire_init(&ctx, 0);
5149 ret = intel_dp_retrain_link(encoder, &ctx);
5151 if (ret == -EDEADLK) {
5152 drm_modeset_backoff(&ctx);
5159 drm_modeset_drop_locks(&ctx);
5160 drm_modeset_acquire_fini(&ctx);
5161 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
5164 * Keeping it consistent with intel_ddi_hotplug() and
5165 * intel_hdmi_hotplug().
5167 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
5168 state = INTEL_HOTPLUG_RETRY;
5173 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5177 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5180 if (drm_dp_dpcd_readb(&intel_dp->aux,
5181 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5184 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5186 if (val & DP_AUTOMATED_TEST_REQUEST)
5187 intel_dp_handle_test_request(intel_dp);
5189 if (val & DP_CP_IRQ)
5190 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5192 if (val & DP_SINK_SPECIFIC_IRQ)
5193 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
5197 * According to DP spec
5200 * 2. Configure link according to Receiver Capabilities
5201 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5202 * 4. Check link status on receipt of hot-plug interrupt
5204 * intel_dp_short_pulse - handles short pulse interrupts
5205 * when full detection is not required.
5206 * Returns %true if short pulse is handled and full detection
5207 * is NOT required and %false otherwise.
5210 intel_dp_short_pulse(struct intel_dp *intel_dp)
5212 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5213 u8 old_sink_count = intel_dp->sink_count;
5217 * Clearing compliance test variables to allow capturing
5218 * of values for next automated test request.
5220 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5223 * Now read the DPCD to see if it's actually running
5224 * If the current value of sink count doesn't match with
5225 * the value that was stored earlier or dpcd read failed
5226 * we need to do full detection
5228 ret = intel_dp_get_dpcd(intel_dp);
5230 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5231 /* No need to proceed if we are going to do full detect */
5235 intel_dp_check_service_irq(intel_dp);
5237 /* Handle CEC interrupts, if any */
5238 drm_dp_cec_irq(&intel_dp->aux);
5240 /* defer to the hotplug work for link retraining if needed */
5241 if (intel_dp_needs_link_retrain(intel_dp))
5244 intel_psr_short_pulse(intel_dp);
5246 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5247 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5248 /* Send a Hotplug Uevent to userspace to start modeset */
5249 drm_kms_helper_hotplug_event(&dev_priv->drm);
5255 /* XXX this is probably wrong for multiple downstream ports */
5256 static enum drm_connector_status
5257 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5259 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5260 u8 *dpcd = intel_dp->dpcd;
5263 if (WARN_ON(intel_dp_is_edp(intel_dp)))
5264 return connector_status_connected;
5267 lspcon_resume(lspcon);
5269 if (!intel_dp_get_dpcd(intel_dp))
5270 return connector_status_disconnected;
5272 /* if there's no downstream port, we're done */
5273 if (!drm_dp_is_branch(dpcd))
5274 return connector_status_connected;
5276 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5277 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5278 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5280 return intel_dp->sink_count ?
5281 connector_status_connected : connector_status_disconnected;
5284 if (intel_dp_can_mst(intel_dp))
5285 return connector_status_connected;
5287 /* If no HPD, poke DDC gently */
5288 if (drm_probe_ddc(&intel_dp->aux.ddc))
5289 return connector_status_connected;
5291 /* Well we tried, say unknown for unreliable port types */
5292 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5293 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5294 if (type == DP_DS_PORT_TYPE_VGA ||
5295 type == DP_DS_PORT_TYPE_NON_EDID)
5296 return connector_status_unknown;
5298 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5299 DP_DWN_STRM_PORT_TYPE_MASK;
5300 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5301 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5302 return connector_status_unknown;
5305 /* Anything else is out of spec, warn and ignore */
5306 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5307 return connector_status_disconnected;
5310 static enum drm_connector_status
5311 edp_detect(struct intel_dp *intel_dp)
5313 return connector_status_connected;
5316 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5321 switch (encoder->hpd_pin) {
5323 bit = SDE_PORTB_HOTPLUG;
5326 bit = SDE_PORTC_HOTPLUG;
5329 bit = SDE_PORTD_HOTPLUG;
5332 MISSING_CASE(encoder->hpd_pin);
5336 return I915_READ(SDEISR) & bit;
5339 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5344 switch (encoder->hpd_pin) {
5346 bit = SDE_PORTB_HOTPLUG_CPT;
5349 bit = SDE_PORTC_HOTPLUG_CPT;
5352 bit = SDE_PORTD_HOTPLUG_CPT;
5355 MISSING_CASE(encoder->hpd_pin);
5359 return I915_READ(SDEISR) & bit;
5362 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5364 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5367 switch (encoder->hpd_pin) {
5369 bit = SDE_PORTA_HOTPLUG_SPT;
5372 bit = SDE_PORTE_HOTPLUG_SPT;
5375 return cpt_digital_port_connected(encoder);
5378 return I915_READ(SDEISR) & bit;
5381 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5383 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5386 switch (encoder->hpd_pin) {
5388 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5391 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5394 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5397 MISSING_CASE(encoder->hpd_pin);
5401 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5404 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5406 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5409 switch (encoder->hpd_pin) {
5411 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5414 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5417 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5420 MISSING_CASE(encoder->hpd_pin);
5424 return I915_READ(PORT_HOTPLUG_STAT) & bit;
5427 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5431 if (encoder->hpd_pin == HPD_PORT_A)
5432 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5434 return ibx_digital_port_connected(encoder);
5437 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5441 if (encoder->hpd_pin == HPD_PORT_A)
5442 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5444 return cpt_digital_port_connected(encoder);
5447 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5451 if (encoder->hpd_pin == HPD_PORT_A)
5452 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5454 return cpt_digital_port_connected(encoder);
5457 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5461 if (encoder->hpd_pin == HPD_PORT_A)
5462 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5464 return cpt_digital_port_connected(encoder);
5467 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5469 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5472 switch (encoder->hpd_pin) {
5474 bit = BXT_DE_PORT_HP_DDIA;
5477 bit = BXT_DE_PORT_HP_DDIB;
5480 bit = BXT_DE_PORT_HP_DDIC;
5483 MISSING_CASE(encoder->hpd_pin);
5487 return I915_READ(GEN8_DE_PORT_ISR) & bit;
5490 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
5493 if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
5494 return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
5496 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
5499 static bool icp_digital_port_connected(struct intel_encoder *encoder)
5501 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5502 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5503 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5505 if (intel_phy_is_combo(dev_priv, phy))
5506 return intel_combo_phy_connected(dev_priv, phy);
5507 else if (intel_phy_is_tc(dev_priv, phy))
5508 return intel_tc_port_connected(dig_port);
5510 MISSING_CASE(encoder->hpd_pin);
5516 * intel_digital_port_connected - is the specified port connected?
5517 * @encoder: intel_encoder
5519 * In cases where there's a connector physically connected but it can't be used
5520 * by our hardware we also return false, since the rest of the driver should
5521 * pretty much treat the port as disconnected. This is relevant for type-C
5522 * (starting on ICL) where there's ownership involved.
5524 * Return %true if port is connected, %false otherwise.
5526 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5528 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5530 if (HAS_GMCH(dev_priv)) {
5531 if (IS_GM45(dev_priv))
5532 return gm45_digital_port_connected(encoder);
5534 return g4x_digital_port_connected(encoder);
5537 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
5538 return icp_digital_port_connected(encoder);
5539 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
5540 return spt_digital_port_connected(encoder);
5541 else if (IS_GEN9_LP(dev_priv))
5542 return bxt_digital_port_connected(encoder);
5543 else if (IS_GEN(dev_priv, 8))
5544 return bdw_digital_port_connected(encoder);
5545 else if (IS_GEN(dev_priv, 7))
5546 return ivb_digital_port_connected(encoder);
5547 else if (IS_GEN(dev_priv, 6))
5548 return snb_digital_port_connected(encoder);
5549 else if (IS_GEN(dev_priv, 5))
5550 return ilk_digital_port_connected(encoder);
5552 MISSING_CASE(INTEL_GEN(dev_priv));
5556 bool intel_digital_port_connected(struct intel_encoder *encoder)
5558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5559 bool is_connected = false;
5560 intel_wakeref_t wakeref;
5562 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5563 is_connected = __intel_digital_port_connected(encoder);
5565 return is_connected;
5568 static struct edid *
5569 intel_dp_get_edid(struct intel_dp *intel_dp)
5571 struct intel_connector *intel_connector = intel_dp->attached_connector;
5573 /* use cached edid if we have one */
5574 if (intel_connector->edid) {
5576 if (IS_ERR(intel_connector->edid))
5579 return drm_edid_duplicate(intel_connector->edid);
5581 return drm_get_edid(&intel_connector->base,
5582 &intel_dp->aux.ddc);
5586 intel_dp_set_edid(struct intel_dp *intel_dp)
5588 struct intel_connector *intel_connector = intel_dp->attached_connector;
5591 intel_dp_unset_edid(intel_dp);
5592 edid = intel_dp_get_edid(intel_dp);
5593 intel_connector->detect_edid = edid;
5595 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5596 drm_dp_cec_set_edid(&intel_dp->aux, edid);
5600 intel_dp_unset_edid(struct intel_dp *intel_dp)
5602 struct intel_connector *intel_connector = intel_dp->attached_connector;
5604 drm_dp_cec_unset_edid(&intel_dp->aux);
5605 kfree(intel_connector->detect_edid);
5606 intel_connector->detect_edid = NULL;
5608 intel_dp->has_audio = false;
5612 intel_dp_detect(struct drm_connector *connector,
5613 struct drm_modeset_acquire_ctx *ctx,
5616 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5617 struct intel_dp *intel_dp = intel_attached_dp(connector);
5618 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5619 struct intel_encoder *encoder = &dig_port->base;
5620 enum drm_connector_status status;
5622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5623 connector->base.id, connector->name);
5624 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5626 /* Can't disconnect eDP */
5627 if (intel_dp_is_edp(intel_dp))
5628 status = edp_detect(intel_dp);
5629 else if (intel_digital_port_connected(encoder))
5630 status = intel_dp_detect_dpcd(intel_dp);
5632 status = connector_status_disconnected;
5634 if (status == connector_status_disconnected) {
5635 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5636 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5638 if (intel_dp->is_mst) {
5639 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5641 intel_dp->mst_mgr.mst_state);
5642 intel_dp->is_mst = false;
5643 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5650 if (intel_dp->reset_link_params) {
5651 /* Initial max link lane count */
5652 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5654 /* Initial max link rate */
5655 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5657 intel_dp->reset_link_params = false;
5660 intel_dp_print_rates(intel_dp);
5662 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5663 if (INTEL_GEN(dev_priv) >= 11)
5664 intel_dp_get_dsc_sink_cap(intel_dp);
5666 intel_dp_configure_mst(intel_dp);
5668 if (intel_dp->is_mst) {
5670 * If we are in MST mode then this connector
5671 * won't appear connected or have anything
5674 status = connector_status_disconnected;
5679 * Some external monitors do not signal loss of link synchronization
5680 * with an IRQ_HPD, so force a link status check.
5682 if (!intel_dp_is_edp(intel_dp)) {
5685 ret = intel_dp_retrain_link(encoder, ctx);
5691 * Clearing NACK and defer counts to get their exact values
5692 * while reading EDID which are required by Compliance tests
5693 * 4.2.2.4 and 4.2.2.5
5695 intel_dp->aux.i2c_nack_count = 0;
5696 intel_dp->aux.i2c_defer_count = 0;
5698 intel_dp_set_edid(intel_dp);
5699 if (intel_dp_is_edp(intel_dp) ||
5700 to_intel_connector(connector)->detect_edid)
5701 status = connector_status_connected;
5703 intel_dp_check_service_irq(intel_dp);
5706 if (status != connector_status_connected && !intel_dp->is_mst)
5707 intel_dp_unset_edid(intel_dp);
5710 * Make sure the refs for power wells enabled during detect are
5711 * dropped to avoid a new detect cycle triggered by HPD polling.
5713 intel_display_power_flush_work(dev_priv);
5719 intel_dp_force(struct drm_connector *connector)
5721 struct intel_dp *intel_dp = intel_attached_dp(connector);
5722 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5723 struct intel_encoder *intel_encoder = &dig_port->base;
5724 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5725 enum intel_display_power_domain aux_domain =
5726 intel_aux_power_domain(dig_port);
5727 intel_wakeref_t wakeref;
5729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5730 connector->base.id, connector->name);
5731 intel_dp_unset_edid(intel_dp);
5733 if (connector->status != connector_status_connected)
5736 wakeref = intel_display_power_get(dev_priv, aux_domain);
5738 intel_dp_set_edid(intel_dp);
5740 intel_display_power_put(dev_priv, aux_domain, wakeref);
5743 static int intel_dp_get_modes(struct drm_connector *connector)
5745 struct intel_connector *intel_connector = to_intel_connector(connector);
5748 edid = intel_connector->detect_edid;
5750 int ret = intel_connector_update_modes(connector, edid);
5755 /* if eDP has no EDID, fall back to fixed mode */
5756 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5757 intel_connector->panel.fixed_mode) {
5758 struct drm_display_mode *mode;
5760 mode = drm_mode_duplicate(connector->dev,
5761 intel_connector->panel.fixed_mode);
5763 drm_mode_probed_add(connector, mode);
5772 intel_dp_connector_register(struct drm_connector *connector)
5774 struct intel_dp *intel_dp = intel_attached_dp(connector);
5777 ret = intel_connector_register(connector);
5781 i915_debugfs_connector_add(connector);
5783 DRM_DEBUG_KMS("registering %s bus for %s\n",
5784 intel_dp->aux.name, connector->kdev->kobj.name);
5786 intel_dp->aux.dev = connector->kdev;
5787 ret = drm_dp_aux_register(&intel_dp->aux);
5789 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5794 intel_dp_connector_unregister(struct drm_connector *connector)
5796 struct intel_dp *intel_dp = intel_attached_dp(connector);
5798 drm_dp_cec_unregister_connector(&intel_dp->aux);
5799 drm_dp_aux_unregister(&intel_dp->aux);
5800 intel_connector_unregister(connector);
5803 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5805 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5806 struct intel_dp *intel_dp = &intel_dig_port->dp;
5808 intel_dp_mst_encoder_cleanup(intel_dig_port);
5809 if (intel_dp_is_edp(intel_dp)) {
5810 intel_wakeref_t wakeref;
5812 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5814 * vdd might still be enabled do to the delayed vdd off.
5815 * Make sure vdd is actually turned off here.
5817 with_pps_lock(intel_dp, wakeref)
5818 edp_panel_vdd_off_sync(intel_dp);
5820 if (intel_dp->edp_notifier.notifier_call) {
5821 unregister_reboot_notifier(&intel_dp->edp_notifier);
5822 intel_dp->edp_notifier.notifier_call = NULL;
5826 intel_dp_aux_fini(intel_dp);
5829 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5831 intel_dp_encoder_flush_work(encoder);
5833 drm_encoder_cleanup(encoder);
5834 kfree(enc_to_dig_port(encoder));
5837 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5839 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5840 intel_wakeref_t wakeref;
5842 if (!intel_dp_is_edp(intel_dp))
5846 * vdd might still be enabled do to the delayed vdd off.
5847 * Make sure vdd is actually turned off here.
5849 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5850 with_pps_lock(intel_dp, wakeref)
5851 edp_panel_vdd_off_sync(intel_dp);
5854 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5858 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5859 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5860 msecs_to_jiffies(timeout));
5863 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5867 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5870 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5871 static const struct drm_dp_aux_msg msg = {
5872 .request = DP_AUX_NATIVE_WRITE,
5873 .address = DP_AUX_HDCP_AKSV,
5874 .size = DRM_HDCP_KSV_LEN,
5876 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5880 /* Output An first, that's easy */
5881 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5882 an, DRM_HDCP_AN_LEN);
5883 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5884 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5886 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5890 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5891 * order to get it on the wire, we need to create the AUX header as if
5892 * we were writing the data, and then tickle the hardware to output the
5893 * data once the header is sent out.
5895 intel_dp_aux_header(txbuf, &msg);
5897 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5898 rxbuf, sizeof(rxbuf),
5899 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5901 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5903 } else if (ret == 0) {
5904 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5908 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5909 if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5910 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5917 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5921 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5923 if (ret != DRM_HDCP_KSV_LEN) {
5924 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5925 return ret >= 0 ? -EIO : ret;
5930 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5935 * For some reason the HDMI and DP HDCP specs call this register
5936 * definition by different names. In the HDMI spec, it's called BSTATUS,
5937 * but in DP it's called BINFO.
5939 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5940 bstatus, DRM_HDCP_BSTATUS_LEN);
5941 if (ret != DRM_HDCP_BSTATUS_LEN) {
5942 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5943 return ret >= 0 ? -EIO : ret;
5949 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5954 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5957 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5958 return ret >= 0 ? -EIO : ret;
5965 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5966 bool *repeater_present)
5971 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5975 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5980 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5984 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5985 ri_prime, DRM_HDCP_RI_LEN);
5986 if (ret != DRM_HDCP_RI_LEN) {
5987 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5988 return ret >= 0 ? -EIO : ret;
5994 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5999 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6002 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6003 return ret >= 0 ? -EIO : ret;
6005 *ksv_ready = bstatus & DP_BSTATUS_READY;
6010 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6011 int num_downstream, u8 *ksv_fifo)
6016 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6017 for (i = 0; i < num_downstream; i += 3) {
6018 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6019 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6020 DP_AUX_HDCP_KSV_FIFO,
6021 ksv_fifo + i * DRM_HDCP_KSV_LEN,
6024 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
6026 return ret >= 0 ? -EIO : ret;
6033 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6038 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6041 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6042 DP_AUX_HDCP_V_PRIME(i), part,
6043 DRM_HDCP_V_PRIME_PART_LEN);
6044 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6045 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6046 return ret >= 0 ? -EIO : ret;
6052 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6055 /* Not used for single stream DisplayPort setups */
6060 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6065 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6068 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6072 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6076 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6082 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6086 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6090 struct hdcp2_dp_errata_stream_type {
6095 struct hdcp2_dp_msg_data {
6098 bool msg_detectable;
6100 u32 timeout2; /* Added for non_paired situation */
6103 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6104 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6105 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6106 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6107 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6109 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6111 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6112 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6113 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6114 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6115 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6116 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6117 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6118 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6119 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6120 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6122 { HDCP_2_2_REP_SEND_RECVID_LIST,
6123 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6124 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6125 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6127 { HDCP_2_2_REP_STREAM_MANAGE,
6128 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6130 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6131 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6132 /* local define to shovel this through the write_2_2 interface */
6133 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
6134 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6135 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6140 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6145 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6146 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6147 HDCP_2_2_DP_RXSTATUS_LEN);
6148 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6149 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6150 return ret >= 0 ? -EIO : ret;
6157 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6158 u8 msg_id, bool *msg_ready)
6164 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6169 case HDCP_2_2_AKE_SEND_HPRIME:
6170 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6173 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6174 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6177 case HDCP_2_2_REP_SEND_RECVID_LIST:
6178 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6182 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6190 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6191 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6193 struct intel_dp *dp = &intel_dig_port->dp;
6194 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6195 u8 msg_id = hdcp2_msg_data->msg_id;
6197 bool msg_ready = false;
6199 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6200 timeout = hdcp2_msg_data->timeout2;
6202 timeout = hdcp2_msg_data->timeout;
6205 * There is no way to detect the CERT, LPRIME and STREAM_READY
6206 * availability. So Wait for timeout and read the msg.
6208 if (!hdcp2_msg_data->msg_detectable) {
6213 * As we want to check the msg availability at timeout, Ignoring
6214 * the timeout at wait for CP_IRQ.
6216 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6217 ret = hdcp2_detect_msg_availability(intel_dig_port,
6218 msg_id, &msg_ready);
6224 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6225 hdcp2_msg_data->msg_id, ret, timeout);
6230 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6234 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6235 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6236 return &hdcp2_dp_msg_data[i];
6242 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6243 void *buf, size_t size)
6245 struct intel_dp *dp = &intel_dig_port->dp;
6246 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6247 unsigned int offset;
6249 ssize_t ret, bytes_to_write, len;
6250 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6252 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6253 if (!hdcp2_msg_data)
6256 offset = hdcp2_msg_data->offset;
6258 /* No msg_id in DP HDCP2.2 msgs */
6259 bytes_to_write = size - 1;
6262 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6264 while (bytes_to_write) {
6265 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6266 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6268 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6269 offset, (void *)byte, len);
6273 bytes_to_write -= ret;
6282 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6284 u8 rx_info[HDCP_2_2_RXINFO_LEN];
6288 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6289 DP_HDCP_2_2_REG_RXINFO_OFFSET,
6290 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6291 if (ret != HDCP_2_2_RXINFO_LEN)
6292 return ret >= 0 ? -EIO : ret;
6294 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6295 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6297 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6298 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6300 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6301 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6302 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6308 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6309 u8 msg_id, void *buf, size_t size)
6311 unsigned int offset;
6313 ssize_t ret, bytes_to_recv, len;
6314 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6316 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6317 if (!hdcp2_msg_data)
6319 offset = hdcp2_msg_data->offset;
6321 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6325 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6326 ret = get_receiver_id_list_size(intel_dig_port);
6332 bytes_to_recv = size - 1;
6334 /* DP adaptation msgs has no msg_id */
6337 while (bytes_to_recv) {
6338 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6339 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6341 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6344 DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6348 bytes_to_recv -= ret;
6359 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6360 bool is_repeater, u8 content_type)
6362 struct hdcp2_dp_errata_stream_type stream_type_msg;
6368 * Errata for DP: As Stream type is used for encryption, Receiver
6369 * should be communicated with stream type for the decryption of the
6371 * Repeater will be communicated with stream type as a part of it's
6372 * auth later in time.
6374 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6375 stream_type_msg.stream_type = content_type;
6377 return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6378 sizeof(stream_type_msg));
6382 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6387 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6391 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6392 ret = HDCP_REAUTH_REQUEST;
6393 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6394 ret = HDCP_LINK_INTEGRITY_FAILURE;
6395 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6396 ret = HDCP_TOPOLOGY_CHANGE;
6402 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6409 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6410 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6411 rx_caps, HDCP_2_2_RXCAPS_LEN);
6412 if (ret != HDCP_2_2_RXCAPS_LEN)
6413 return ret >= 0 ? -EIO : ret;
6415 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6416 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6422 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6423 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6424 .read_bksv = intel_dp_hdcp_read_bksv,
6425 .read_bstatus = intel_dp_hdcp_read_bstatus,
6426 .repeater_present = intel_dp_hdcp_repeater_present,
6427 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6428 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6429 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6430 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6431 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6432 .check_link = intel_dp_hdcp_check_link,
6433 .hdcp_capable = intel_dp_hdcp_capable,
6434 .write_2_2_msg = intel_dp_hdcp2_write_msg,
6435 .read_2_2_msg = intel_dp_hdcp2_read_msg,
6436 .config_stream_type = intel_dp_hdcp2_config_stream_type,
6437 .check_2_2_link = intel_dp_hdcp2_check_link,
6438 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6439 .protocol = HDCP_PROTOCOL_DP,
6442 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6444 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6445 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6447 lockdep_assert_held(&dev_priv->pps_mutex);
6449 if (!edp_have_panel_vdd(intel_dp))
6453 * The VDD bit needs a power domain reference, so if the bit is
6454 * already enabled when we boot or resume, grab this reference and
6455 * schedule a vdd off, so we don't hold on to the reference
6458 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6459 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6461 edp_panel_vdd_schedule_off(intel_dp);
6464 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6466 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6467 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6470 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6471 encoder->port, &pipe))
6474 return INVALID_PIPE;
6477 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6479 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6480 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6481 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6482 intel_wakeref_t wakeref;
6484 if (!HAS_DDI(dev_priv))
6485 intel_dp->DP = I915_READ(intel_dp->output_reg);
6488 lspcon_resume(lspcon);
6490 intel_dp->reset_link_params = true;
6492 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6493 !intel_dp_is_edp(intel_dp))
6496 with_pps_lock(intel_dp, wakeref) {
6497 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6498 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6500 if (intel_dp_is_edp(intel_dp)) {
6502 * Reinit the power sequencer, in case BIOS did
6503 * something nasty with it.
6505 intel_dp_pps_init(intel_dp);
6506 intel_edp_panel_vdd_sanitize(intel_dp);
6511 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6512 .force = intel_dp_force,
6513 .fill_modes = drm_helper_probe_single_connector_modes,
6514 .atomic_get_property = intel_digital_connector_atomic_get_property,
6515 .atomic_set_property = intel_digital_connector_atomic_set_property,
6516 .late_register = intel_dp_connector_register,
6517 .early_unregister = intel_dp_connector_unregister,
6518 .destroy = intel_connector_destroy,
6519 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6520 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6523 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6524 .detect_ctx = intel_dp_detect,
6525 .get_modes = intel_dp_get_modes,
6526 .mode_valid = intel_dp_mode_valid,
6527 .atomic_check = intel_digital_connector_atomic_check,
6530 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6531 .reset = intel_dp_encoder_reset,
6532 .destroy = intel_dp_encoder_destroy,
6536 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6538 struct intel_dp *intel_dp = &intel_dig_port->dp;
6540 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6542 * vdd off can generate a long pulse on eDP which
6543 * would require vdd on to handle it, and thus we
6544 * would end up in an endless cycle of
6545 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6547 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6548 intel_dig_port->base.base.base.id,
6549 intel_dig_port->base.base.name);
6553 DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6554 intel_dig_port->base.base.base.id,
6555 intel_dig_port->base.base.name,
6556 long_hpd ? "long" : "short");
6559 intel_dp->reset_link_params = true;
6563 if (intel_dp->is_mst) {
6564 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6566 * If we were in MST mode, and device is not
6567 * there, get out of MST mode
6569 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6570 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6571 intel_dp->is_mst = false;
6572 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6579 if (!intel_dp->is_mst) {
6582 handled = intel_dp_short_pulse(intel_dp);
6591 /* check the VBT to see whether the eDP is on another port */
6592 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6595 * eDP not supported on g4x. so bail out early just
6596 * for a bit extra safety in case the VBT is bonkers.
6598 if (INTEL_GEN(dev_priv) < 5)
6601 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6604 return intel_bios_is_port_edp(dev_priv, port);
6608 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6610 struct drm_i915_private *dev_priv = to_i915(connector->dev);
6611 enum port port = dp_to_dig_port(intel_dp)->base.port;
6613 if (!IS_G4X(dev_priv) && port != PORT_A)
6614 intel_attach_force_audio_property(connector);
6616 intel_attach_broadcast_rgb_property(connector);
6617 if (HAS_GMCH(dev_priv))
6618 drm_connector_attach_max_bpc_property(connector, 6, 10);
6619 else if (INTEL_GEN(dev_priv) >= 5)
6620 drm_connector_attach_max_bpc_property(connector, 6, 12);
6622 intel_attach_colorspace_property(connector);
6624 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6625 drm_object_attach_property(&connector->base,
6626 connector->dev->mode_config.hdr_output_metadata_property,
6629 if (intel_dp_is_edp(intel_dp)) {
6630 u32 allowed_scalers;
6632 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6633 if (!HAS_GMCH(dev_priv))
6634 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6636 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6638 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6643 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6645 intel_dp->panel_power_off_time = ktime_get_boottime();
6646 intel_dp->last_power_on = jiffies;
6647 intel_dp->last_backlight_off = jiffies;
6651 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6653 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6654 u32 pp_on, pp_off, pp_ctl;
6655 struct pps_registers regs;
6657 intel_pps_get_registers(intel_dp, ®s);
6659 pp_ctl = ironlake_get_pp_control(intel_dp);
6661 /* Ensure PPS is unlocked */
6662 if (!HAS_DDI(dev_priv))
6663 I915_WRITE(regs.pp_ctrl, pp_ctl);
6665 pp_on = I915_READ(regs.pp_on);
6666 pp_off = I915_READ(regs.pp_off);
6668 /* Pull timing values out of registers */
6669 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6670 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6671 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6672 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6674 if (i915_mmio_reg_valid(regs.pp_div)) {
6677 pp_div = I915_READ(regs.pp_div);
6679 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6681 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6686 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6688 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6690 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6694 intel_pps_verify_state(struct intel_dp *intel_dp)
6696 struct edp_power_seq hw;
6697 struct edp_power_seq *sw = &intel_dp->pps_delays;
6699 intel_pps_readout_hw_state(intel_dp, &hw);
6701 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6702 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6703 DRM_ERROR("PPS state mismatch\n");
6704 intel_pps_dump_state("sw", sw);
6705 intel_pps_dump_state("hw", &hw);
6710 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6712 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6713 struct edp_power_seq cur, vbt, spec,
6714 *final = &intel_dp->pps_delays;
6716 lockdep_assert_held(&dev_priv->pps_mutex);
6718 /* already initialized? */
6719 if (final->t11_t12 != 0)
6722 intel_pps_readout_hw_state(intel_dp, &cur);
6724 intel_pps_dump_state("cur", &cur);
6726 vbt = dev_priv->vbt.edp.pps;
6727 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6728 * of 500ms appears to be too short. Ocassionally the panel
6729 * just fails to power back on. Increasing the delay to 800ms
6730 * seems sufficient to avoid this problem.
6732 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6733 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6734 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6737 /* T11_T12 delay is special and actually in units of 100ms, but zero
6738 * based in the hw (so we need to add 100 ms). But the sw vbt
6739 * table multiplies it with 1000 to make it in units of 100usec,
6741 vbt.t11_t12 += 100 * 10;
6743 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6744 * our hw here, which are all in 100usec. */
6745 spec.t1_t3 = 210 * 10;
6746 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6747 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6748 spec.t10 = 500 * 10;
6749 /* This one is special and actually in units of 100ms, but zero
6750 * based in the hw (so we need to add 100 ms). But the sw vbt
6751 * table multiplies it with 1000 to make it in units of 100usec,
6753 spec.t11_t12 = (510 + 100) * 10;
6755 intel_pps_dump_state("vbt", &vbt);
6757 /* Use the max of the register settings and vbt. If both are
6758 * unset, fall back to the spec limits. */
6759 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6761 max(cur.field, vbt.field))
6762 assign_final(t1_t3);
6766 assign_final(t11_t12);
6769 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6770 intel_dp->panel_power_up_delay = get_delay(t1_t3);
6771 intel_dp->backlight_on_delay = get_delay(t8);
6772 intel_dp->backlight_off_delay = get_delay(t9);
6773 intel_dp->panel_power_down_delay = get_delay(t10);
6774 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6777 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6778 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6779 intel_dp->panel_power_cycle_delay);
6781 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6782 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6785 * We override the HW backlight delays to 1 because we do manual waits
6786 * on them. For T8, even BSpec recommends doing it. For T9, if we
6787 * don't do this, we'll end up waiting for the backlight off delay
6788 * twice: once when we do the manual sleep, and once when we disable
6789 * the panel and wait for the PP_STATUS bit to become zero.
6795 * HW has only a 100msec granularity for t11_t12 so round it up
6798 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6802 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6803 bool force_disable_vdd)
6805 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6806 u32 pp_on, pp_off, port_sel = 0;
6807 int div = dev_priv->rawclk_freq / 1000;
6808 struct pps_registers regs;
6809 enum port port = dp_to_dig_port(intel_dp)->base.port;
6810 const struct edp_power_seq *seq = &intel_dp->pps_delays;
6812 lockdep_assert_held(&dev_priv->pps_mutex);
6814 intel_pps_get_registers(intel_dp, ®s);
6817 * On some VLV machines the BIOS can leave the VDD
6818 * enabled even on power sequencers which aren't
6819 * hooked up to any port. This would mess up the
6820 * power domain tracking the first time we pick
6821 * one of these power sequencers for use since
6822 * edp_panel_vdd_on() would notice that the VDD was
6823 * already on and therefore wouldn't grab the power
6824 * domain reference. Disable VDD first to avoid this.
6825 * This also avoids spuriously turning the VDD on as
6826 * soon as the new power sequencer gets initialized.
6828 if (force_disable_vdd) {
6829 u32 pp = ironlake_get_pp_control(intel_dp);
6831 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6833 if (pp & EDP_FORCE_VDD)
6834 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6836 pp &= ~EDP_FORCE_VDD;
6838 I915_WRITE(regs.pp_ctrl, pp);
6841 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6842 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6843 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6844 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6846 /* Haswell doesn't have any port selection bits for the panel
6847 * power sequencer any more. */
6848 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6849 port_sel = PANEL_PORT_SELECT_VLV(port);
6850 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6853 port_sel = PANEL_PORT_SELECT_DPA;
6856 port_sel = PANEL_PORT_SELECT_DPC;
6859 port_sel = PANEL_PORT_SELECT_DPD;
6869 I915_WRITE(regs.pp_on, pp_on);
6870 I915_WRITE(regs.pp_off, pp_off);
6873 * Compute the divisor for the pp clock, simply match the Bspec formula.
6875 if (i915_mmio_reg_valid(regs.pp_div)) {
6876 I915_WRITE(regs.pp_div,
6877 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6878 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6882 pp_ctl = I915_READ(regs.pp_ctrl);
6883 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6884 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6885 I915_WRITE(regs.pp_ctrl, pp_ctl);
6888 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6889 I915_READ(regs.pp_on),
6890 I915_READ(regs.pp_off),
6891 i915_mmio_reg_valid(regs.pp_div) ?
6892 I915_READ(regs.pp_div) :
6893 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6896 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6898 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6900 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6901 vlv_initial_power_sequencer_setup(intel_dp);
6903 intel_dp_init_panel_power_sequencer(intel_dp);
6904 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6909 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6910 * @dev_priv: i915 device
6911 * @crtc_state: a pointer to the active intel_crtc_state
6912 * @refresh_rate: RR to be programmed
6914 * This function gets called when refresh rate (RR) has to be changed from
6915 * one frequency to another. Switches can be between high and low RR
6916 * supported by the panel or to any other RR based on media playback (in
6917 * this case, RR value needs to be passed from user space).
6919 * The caller of this function needs to take a lock on dev_priv->drrs.
6921 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6922 const struct intel_crtc_state *crtc_state,
6925 struct intel_dp *intel_dp = dev_priv->drrs.dp;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
6927 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6929 if (refresh_rate <= 0) {
6930 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6934 if (intel_dp == NULL) {
6935 DRM_DEBUG_KMS("DRRS not supported.\n");
6940 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6944 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6945 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6949 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6951 index = DRRS_LOW_RR;
6953 if (index == dev_priv->drrs.refresh_rate_type) {
6955 "DRRS requested for previously set RR...ignoring\n");
6959 if (!crtc_state->hw.active) {
6960 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6964 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6967 intel_dp_set_m_n(crtc_state, M1_N1);
6970 intel_dp_set_m_n(crtc_state, M2_N2);
6974 DRM_ERROR("Unsupported refreshrate type\n");
6976 } else if (INTEL_GEN(dev_priv) > 6) {
6977 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6980 val = I915_READ(reg);
6981 if (index > DRRS_HIGH_RR) {
6982 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6983 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6985 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6987 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6988 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6990 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6992 I915_WRITE(reg, val);
6995 dev_priv->drrs.refresh_rate_type = index;
6997 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
7001 * intel_edp_drrs_enable - init drrs struct if supported
7002 * @intel_dp: DP struct
7003 * @crtc_state: A pointer to the active crtc state.
7005 * Initializes frontbuffer_bits and drrs.dp
7007 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7008 const struct intel_crtc_state *crtc_state)
7010 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7012 if (!crtc_state->has_drrs) {
7013 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
7017 if (dev_priv->psr.enabled) {
7018 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
7022 mutex_lock(&dev_priv->drrs.mutex);
7023 if (dev_priv->drrs.dp) {
7024 DRM_DEBUG_KMS("DRRS already enabled\n");
7028 dev_priv->drrs.busy_frontbuffer_bits = 0;
7030 dev_priv->drrs.dp = intel_dp;
7033 mutex_unlock(&dev_priv->drrs.mutex);
7037 * intel_edp_drrs_disable - Disable DRRS
7038 * @intel_dp: DP struct
7039 * @old_crtc_state: Pointer to old crtc_state.
7042 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7043 const struct intel_crtc_state *old_crtc_state)
7045 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7047 if (!old_crtc_state->has_drrs)
7050 mutex_lock(&dev_priv->drrs.mutex);
7051 if (!dev_priv->drrs.dp) {
7052 mutex_unlock(&dev_priv->drrs.mutex);
7056 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7057 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7058 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7060 dev_priv->drrs.dp = NULL;
7061 mutex_unlock(&dev_priv->drrs.mutex);
7063 cancel_delayed_work_sync(&dev_priv->drrs.work);
7066 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7068 struct drm_i915_private *dev_priv =
7069 container_of(work, typeof(*dev_priv), drrs.work.work);
7070 struct intel_dp *intel_dp;
7072 mutex_lock(&dev_priv->drrs.mutex);
7074 intel_dp = dev_priv->drrs.dp;
7080 * The delayed work can race with an invalidate hence we need to
7084 if (dev_priv->drrs.busy_frontbuffer_bits)
7087 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7088 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7090 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7091 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7095 mutex_unlock(&dev_priv->drrs.mutex);
7099 * intel_edp_drrs_invalidate - Disable Idleness DRRS
7100 * @dev_priv: i915 device
7101 * @frontbuffer_bits: frontbuffer plane tracking bits
7103 * This function gets called everytime rendering on the given planes start.
7104 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7106 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7108 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7109 unsigned int frontbuffer_bits)
7111 struct drm_crtc *crtc;
7114 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7117 cancel_delayed_work(&dev_priv->drrs.work);
7119 mutex_lock(&dev_priv->drrs.mutex);
7120 if (!dev_priv->drrs.dp) {
7121 mutex_unlock(&dev_priv->drrs.mutex);
7125 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7126 pipe = to_intel_crtc(crtc)->pipe;
7128 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7129 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7131 /* invalidate means busy screen hence upclock */
7132 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7133 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7134 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7136 mutex_unlock(&dev_priv->drrs.mutex);
7140 * intel_edp_drrs_flush - Restart Idleness DRRS
7141 * @dev_priv: i915 device
7142 * @frontbuffer_bits: frontbuffer plane tracking bits
7144 * This function gets called every time rendering on the given planes has
7145 * completed or flip on a crtc is completed. So DRRS should be upclocked
7146 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7147 * if no other planes are dirty.
7149 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7151 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7152 unsigned int frontbuffer_bits)
7154 struct drm_crtc *crtc;
7157 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7160 cancel_delayed_work(&dev_priv->drrs.work);
7162 mutex_lock(&dev_priv->drrs.mutex);
7163 if (!dev_priv->drrs.dp) {
7164 mutex_unlock(&dev_priv->drrs.mutex);
7168 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7169 pipe = to_intel_crtc(crtc)->pipe;
7171 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7172 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7174 /* flush means busy screen hence upclock */
7175 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7176 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7177 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7180 * flush also means no more activity hence schedule downclock, if all
7181 * other fbs are quiescent too
7183 if (!dev_priv->drrs.busy_frontbuffer_bits)
7184 schedule_delayed_work(&dev_priv->drrs.work,
7185 msecs_to_jiffies(1000));
7186 mutex_unlock(&dev_priv->drrs.mutex);
7190 * DOC: Display Refresh Rate Switching (DRRS)
7192 * Display Refresh Rate Switching (DRRS) is a power conservation feature
7193 * which enables swtching between low and high refresh rates,
7194 * dynamically, based on the usage scenario. This feature is applicable
7195 * for internal panels.
7197 * Indication that the panel supports DRRS is given by the panel EDID, which
7198 * would list multiple refresh rates for one resolution.
7200 * DRRS is of 2 types - static and seamless.
7201 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7202 * (may appear as a blink on screen) and is used in dock-undock scenario.
7203 * Seamless DRRS involves changing RR without any visual effect to the user
7204 * and can be used during normal system usage. This is done by programming
7205 * certain registers.
7207 * Support for static/seamless DRRS may be indicated in the VBT based on
7208 * inputs from the panel spec.
7210 * DRRS saves power by switching to low RR based on usage scenarios.
7212 * The implementation is based on frontbuffer tracking implementation. When
7213 * there is a disturbance on the screen triggered by user activity or a periodic
7214 * system activity, DRRS is disabled (RR is changed to high RR). When there is
7215 * no movement on screen, after a timeout of 1 second, a switch to low RR is
7218 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7219 * and intel_edp_drrs_flush() are called.
7221 * DRRS can be further extended to support other internal panels and also
7222 * the scenario of video playback wherein RR is set based on the rate
7223 * requested by userspace.
7227 * intel_dp_drrs_init - Init basic DRRS work and mutex.
7228 * @connector: eDP connector
7229 * @fixed_mode: preferred mode of panel
7231 * This function is called only once at driver load to initialize basic
7235 * Downclock mode if panel supports it, else return NULL.
7236 * DRRS support is determined by the presence of downclock mode (apart
7237 * from VBT setting).
7239 static struct drm_display_mode *
7240 intel_dp_drrs_init(struct intel_connector *connector,
7241 struct drm_display_mode *fixed_mode)
7243 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7244 struct drm_display_mode *downclock_mode = NULL;
7246 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7247 mutex_init(&dev_priv->drrs.mutex);
7249 if (INTEL_GEN(dev_priv) <= 6) {
7250 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7254 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7255 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7259 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7260 if (!downclock_mode) {
7261 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7265 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7267 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7268 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7269 return downclock_mode;
7272 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7273 struct intel_connector *intel_connector)
7275 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7276 struct drm_device *dev = &dev_priv->drm;
7277 struct drm_connector *connector = &intel_connector->base;
7278 struct drm_display_mode *fixed_mode = NULL;
7279 struct drm_display_mode *downclock_mode = NULL;
7281 enum pipe pipe = INVALID_PIPE;
7282 intel_wakeref_t wakeref;
7285 if (!intel_dp_is_edp(intel_dp))
7288 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7291 * On IBX/CPT we may get here with LVDS already registered. Since the
7292 * driver uses the only internal power sequencer available for both
7293 * eDP and LVDS bail out early in this case to prevent interfering
7294 * with an already powered-on LVDS power sequencer.
7296 if (intel_get_lvds_encoder(dev_priv)) {
7297 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7298 DRM_INFO("LVDS was detected, not registering eDP\n");
7303 with_pps_lock(intel_dp, wakeref) {
7304 intel_dp_init_panel_power_timestamps(intel_dp);
7305 intel_dp_pps_init(intel_dp);
7306 intel_edp_panel_vdd_sanitize(intel_dp);
7309 /* Cache DPCD and EDID for edp. */
7310 has_dpcd = intel_edp_init_dpcd(intel_dp);
7313 /* if this fails, presume the device is a ghost */
7314 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7318 mutex_lock(&dev->mode_config.mutex);
7319 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7321 if (drm_add_edid_modes(connector, edid)) {
7322 drm_connector_update_edid_property(connector,
7326 edid = ERR_PTR(-EINVAL);
7329 edid = ERR_PTR(-ENOENT);
7331 intel_connector->edid = edid;
7333 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7335 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7337 /* fallback to VBT if available for eDP */
7339 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7340 mutex_unlock(&dev->mode_config.mutex);
7342 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7343 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7344 register_reboot_notifier(&intel_dp->edp_notifier);
7347 * Figure out the current pipe for the initial backlight setup.
7348 * If the current pipe isn't valid, try the PPS pipe, and if that
7349 * fails just assume pipe A.
7351 pipe = vlv_active_pipe(intel_dp);
7353 if (pipe != PIPE_A && pipe != PIPE_B)
7354 pipe = intel_dp->pps_pipe;
7356 if (pipe != PIPE_A && pipe != PIPE_B)
7359 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7363 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7364 intel_connector->panel.backlight.power = intel_edp_backlight_power;
7365 intel_panel_setup_backlight(connector, pipe);
7368 drm_connector_init_panel_orientation_property(
7369 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7374 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7376 * vdd might still be enabled do to the delayed vdd off.
7377 * Make sure vdd is actually turned off here.
7379 with_pps_lock(intel_dp, wakeref)
7380 edp_panel_vdd_off_sync(intel_dp);
7385 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7387 struct intel_connector *intel_connector;
7388 struct drm_connector *connector;
7390 intel_connector = container_of(work, typeof(*intel_connector),
7391 modeset_retry_work);
7392 connector = &intel_connector->base;
7393 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7396 /* Grab the locks before changing connector property*/
7397 mutex_lock(&connector->dev->mode_config.mutex);
7398 /* Set connector link status to BAD and send a Uevent to notify
7399 * userspace to do a modeset.
7401 drm_connector_set_link_status_property(connector,
7402 DRM_MODE_LINK_STATUS_BAD);
7403 mutex_unlock(&connector->dev->mode_config.mutex);
7404 /* Send Hotplug uevent so userspace can reprobe */
7405 drm_kms_helper_hotplug_event(connector->dev);
7409 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7410 struct intel_connector *intel_connector)
7412 struct drm_connector *connector = &intel_connector->base;
7413 struct intel_dp *intel_dp = &intel_dig_port->dp;
7414 struct intel_encoder *intel_encoder = &intel_dig_port->base;
7415 struct drm_device *dev = intel_encoder->base.dev;
7416 struct drm_i915_private *dev_priv = to_i915(dev);
7417 enum port port = intel_encoder->port;
7418 enum phy phy = intel_port_to_phy(dev_priv, port);
7421 /* Initialize the work for modeset in case of link train failure */
7422 INIT_WORK(&intel_connector->modeset_retry_work,
7423 intel_dp_modeset_retry_work_fn);
7425 if (WARN(intel_dig_port->max_lanes < 1,
7426 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7427 intel_dig_port->max_lanes, intel_encoder->base.base.id,
7428 intel_encoder->base.name))
7431 intel_dp_set_source_rates(intel_dp);
7433 intel_dp->reset_link_params = true;
7434 intel_dp->pps_pipe = INVALID_PIPE;
7435 intel_dp->active_pipe = INVALID_PIPE;
7437 /* Preserve the current hw state. */
7438 intel_dp->DP = I915_READ(intel_dp->output_reg);
7439 intel_dp->attached_connector = intel_connector;
7441 if (intel_dp_is_port_edp(dev_priv, port)) {
7443 * Currently we don't support eDP on TypeC ports, although in
7444 * theory it could work on TypeC legacy ports.
7446 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7447 type = DRM_MODE_CONNECTOR_eDP;
7449 type = DRM_MODE_CONNECTOR_DisplayPort;
7452 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7453 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7456 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7457 * for DP the encoder type can be set by the caller to
7458 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7460 if (type == DRM_MODE_CONNECTOR_eDP)
7461 intel_encoder->type = INTEL_OUTPUT_EDP;
7463 /* eDP only on port B and/or C on vlv/chv */
7464 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7465 intel_dp_is_edp(intel_dp) &&
7466 port != PORT_B && port != PORT_C))
7469 DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7470 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7471 intel_encoder->base.base.id, intel_encoder->base.name);
7473 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7474 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7476 if (!HAS_GMCH(dev_priv))
7477 connector->interlace_allowed = true;
7478 connector->doublescan_allowed = 0;
7480 if (INTEL_GEN(dev_priv) >= 11)
7481 connector->ycbcr_420_allowed = true;
7483 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7485 intel_dp_aux_init(intel_dp);
7487 intel_connector_attach_encoder(intel_connector, intel_encoder);
7489 if (HAS_DDI(dev_priv))
7490 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7492 intel_connector->get_hw_state = intel_connector_get_hw_state;
7494 /* init MST on ports that can support it */
7495 intel_dp_mst_encoder_init(intel_dig_port,
7496 intel_connector->base.base.id);
7498 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7499 intel_dp_aux_fini(intel_dp);
7500 intel_dp_mst_encoder_cleanup(intel_dig_port);
7504 intel_dp_add_properties(intel_dp, connector);
7506 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7507 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7509 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7512 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7513 * 0xd. Failure to do so will result in spurious interrupts being
7514 * generated on the port when a cable is not attached.
7516 if (IS_G45(dev_priv)) {
7517 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7518 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7524 drm_connector_cleanup(connector);
7529 bool intel_dp_init(struct drm_i915_private *dev_priv,
7530 i915_reg_t output_reg,
7533 struct intel_digital_port *intel_dig_port;
7534 struct intel_encoder *intel_encoder;
7535 struct drm_encoder *encoder;
7536 struct intel_connector *intel_connector;
7538 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7539 if (!intel_dig_port)
7542 intel_connector = intel_connector_alloc();
7543 if (!intel_connector)
7544 goto err_connector_alloc;
7546 intel_encoder = &intel_dig_port->base;
7547 encoder = &intel_encoder->base;
7549 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7550 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7551 "DP %c", port_name(port)))
7552 goto err_encoder_init;
7554 intel_encoder->hotplug = intel_dp_hotplug;
7555 intel_encoder->compute_config = intel_dp_compute_config;
7556 intel_encoder->get_hw_state = intel_dp_get_hw_state;
7557 intel_encoder->get_config = intel_dp_get_config;
7558 intel_encoder->update_pipe = intel_panel_update_backlight;
7559 intel_encoder->suspend = intel_dp_encoder_suspend;
7560 if (IS_CHERRYVIEW(dev_priv)) {
7561 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7562 intel_encoder->pre_enable = chv_pre_enable_dp;
7563 intel_encoder->enable = vlv_enable_dp;
7564 intel_encoder->disable = vlv_disable_dp;
7565 intel_encoder->post_disable = chv_post_disable_dp;
7566 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7567 } else if (IS_VALLEYVIEW(dev_priv)) {
7568 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7569 intel_encoder->pre_enable = vlv_pre_enable_dp;
7570 intel_encoder->enable = vlv_enable_dp;
7571 intel_encoder->disable = vlv_disable_dp;
7572 intel_encoder->post_disable = vlv_post_disable_dp;
7574 intel_encoder->pre_enable = g4x_pre_enable_dp;
7575 intel_encoder->enable = g4x_enable_dp;
7576 intel_encoder->disable = g4x_disable_dp;
7577 intel_encoder->post_disable = g4x_post_disable_dp;
7580 intel_dig_port->dp.output_reg = output_reg;
7581 intel_dig_port->max_lanes = 4;
7583 intel_encoder->type = INTEL_OUTPUT_DP;
7584 intel_encoder->power_domain = intel_port_to_power_domain(port);
7585 if (IS_CHERRYVIEW(dev_priv)) {
7587 intel_encoder->pipe_mask = BIT(PIPE_C);
7589 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
7591 intel_encoder->pipe_mask = ~0;
7593 intel_encoder->cloneable = 0;
7594 intel_encoder->port = port;
7596 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7599 intel_infoframe_init(intel_dig_port);
7601 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7602 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7603 goto err_init_connector;
7608 drm_encoder_cleanup(encoder);
7610 kfree(intel_connector);
7611 err_connector_alloc:
7612 kfree(intel_dig_port);
7616 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7618 struct intel_encoder *encoder;
7620 for_each_intel_encoder(&dev_priv->drm, encoder) {
7621 struct intel_dp *intel_dp;
7623 if (encoder->type != INTEL_OUTPUT_DDI)
7626 intel_dp = enc_to_intel_dp(&encoder->base);
7628 if (!intel_dp->can_mst)
7631 if (intel_dp->is_mst)
7632 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7636 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7638 struct intel_encoder *encoder;
7640 for_each_intel_encoder(&dev_priv->drm, encoder) {
7641 struct intel_dp *intel_dp;
7644 if (encoder->type != INTEL_OUTPUT_DDI)
7647 intel_dp = enc_to_intel_dp(&encoder->base);
7649 if (!intel_dp->can_mst)
7652 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
7655 intel_dp->is_mst = false;
7656 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,