2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
42 #include "i915_debugfs.h"
44 #include "intel_atomic.h"
45 #include "intel_audio.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
48 #include "intel_display_types.h"
50 #include "intel_dp_aux.h"
51 #include "intel_dp_link_training.h"
52 #include "intel_dp_mst.h"
53 #include "intel_dpll.h"
54 #include "intel_dpio_phy.h"
55 #include "intel_fifo_underrun.h"
56 #include "intel_hdcp.h"
57 #include "intel_hdmi.h"
58 #include "intel_hotplug.h"
59 #include "intel_lspcon.h"
60 #include "intel_lvds.h"
61 #include "intel_panel.h"
62 #include "intel_pps.h"
63 #include "intel_psr.h"
64 #include "intel_sideband.h"
66 #include "intel_vdsc.h"
67 #include "intel_vrr.h"
69 #define DP_DPRX_ESI_LEN 14
71 /* DP DSC throughput values used for slice count calculations KPixels/s */
72 #define DP_DSC_PEAK_PIXEL_RATE 2720000
73 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
74 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
77 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
79 /* Compliance test status bits */
80 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
81 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
82 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
83 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
90 static const struct dp_link_dpll g4x_dpll[] = {
92 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
94 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
97 static const struct dp_link_dpll pch_dpll[] = {
99 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
101 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
104 static const struct dp_link_dpll vlv_dpll[] = {
106 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
108 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
112 * CHV supports eDP 1.4 that have more link rates.
113 * Below only provides the fixed rate but exclude variable rate.
115 static const struct dp_link_dpll chv_dpll[] = {
117 * CHV requires to program fractional division for m2.
118 * m2 is stored in fixed point format using formula below
119 * (m2_int << 22) | m2_fraction
121 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
122 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
123 { 270000, /* m2_int = 27, m2_fraction = 0 */
124 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
127 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
129 return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
132 /* Constants for DP DSC configurations */
133 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
135 /* With Single pipe configuration, HW is capable of supporting maximum
136 * of 4 slices per line.
138 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
141 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
142 * @intel_dp: DP struct
144 * If a CPU or PCH DP output is attached to an eDP panel, this function
145 * will return true, and false otherwise.
147 bool intel_dp_is_edp(struct intel_dp *intel_dp)
149 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
151 return dig_port->base.type == INTEL_OUTPUT_EDP;
154 static void intel_dp_link_down(struct intel_encoder *encoder,
155 const struct intel_crtc_state *old_crtc_state);
156 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
158 /* update sink rates from dpcd */
159 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
161 static const int dp_rates[] = {
162 162000, 270000, 540000, 810000
167 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
168 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
169 static const int quirk_rates[] = { 162000, 270000, 324000 };
171 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
172 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
178 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
180 max_rate = min(max_rate, max_lttpr_rate);
182 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
183 if (dp_rates[i] > max_rate)
185 intel_dp->sink_rates[i] = dp_rates[i];
188 intel_dp->num_sink_rates = i;
191 /* Get length of rates array potentially limited by max_rate. */
192 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
196 /* Limit results by potentially reduced max rate */
197 for (i = 0; i < len; i++) {
198 if (rates[len - i - 1] <= max_rate)
205 /* Get length of common rates array potentially limited by max_rate. */
206 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
209 return intel_dp_rate_limit_len(intel_dp->common_rates,
210 intel_dp->num_common_rates, max_rate);
213 /* Theoretical max between source and sink */
214 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
216 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
219 /* Theoretical max between source and sink */
220 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
222 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
223 int source_max = dig_port->max_lanes;
224 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
225 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
226 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
229 sink_max = min(sink_max, lttpr_max);
231 return min3(source_max, sink_max, fia_max);
234 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
236 return intel_dp->max_link_lane_count;
240 intel_dp_link_required(int pixel_clock, int bpp)
242 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
243 return DIV_ROUND_UP(pixel_clock * bpp, 8);
247 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
249 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
250 * link rate that is generally expressed in Gbps. Since, 8 bits of data
251 * is transmitted every LS_Clk per lane, there is no need to account for
252 * the channel encoding that is done in the PHY layer here.
255 return max_link_clock * max_lanes;
258 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261 struct intel_encoder *encoder = &intel_dig_port->base;
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
264 return INTEL_GEN(dev_priv) >= 12 ||
265 (INTEL_GEN(dev_priv) == 11 &&
266 encoder->port != PORT_A);
269 static int cnl_max_source_rate(struct intel_dp *intel_dp)
271 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
272 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
273 enum port port = dig_port->base.port;
275 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
277 /* Low voltage SKUs are limited to max of 5.4G */
278 if (voltage == VOLTAGE_INFO_0_85V)
281 /* For this SKU 8.1G is supported in all ports */
282 if (IS_CNL_WITH_PORT_F(dev_priv))
285 /* For other SKUs, max rate on ports A and D is 5.4G */
286 if (port == PORT_A || port == PORT_D)
292 static int icl_max_source_rate(struct intel_dp *intel_dp)
294 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
295 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
296 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
298 if (intel_phy_is_combo(dev_priv, phy) &&
299 !intel_dp_is_edp(intel_dp))
305 static int ehl_max_source_rate(struct intel_dp *intel_dp)
307 if (intel_dp_is_edp(intel_dp))
314 intel_dp_set_source_rates(struct intel_dp *intel_dp)
316 /* The values must be in increasing order */
317 static const int cnl_rates[] = {
318 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
320 static const int bxt_rates[] = {
321 162000, 216000, 243000, 270000, 324000, 432000, 540000
323 static const int skl_rates[] = {
324 162000, 216000, 270000, 324000, 432000, 540000
326 static const int hsw_rates[] = {
327 162000, 270000, 540000
329 static const int g4x_rates[] = {
332 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
333 struct intel_encoder *encoder = &dig_port->base;
334 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
335 const int *source_rates;
336 int size, max_rate = 0, vbt_max_rate;
338 /* This should only be done once */
339 drm_WARN_ON(&dev_priv->drm,
340 intel_dp->source_rates || intel_dp->num_source_rates);
342 if (INTEL_GEN(dev_priv) >= 10) {
343 source_rates = cnl_rates;
344 size = ARRAY_SIZE(cnl_rates);
345 if (IS_GEN(dev_priv, 10))
346 max_rate = cnl_max_source_rate(intel_dp);
347 else if (IS_JSL_EHL(dev_priv))
348 max_rate = ehl_max_source_rate(intel_dp);
350 max_rate = icl_max_source_rate(intel_dp);
351 } else if (IS_GEN9_LP(dev_priv)) {
352 source_rates = bxt_rates;
353 size = ARRAY_SIZE(bxt_rates);
354 } else if (IS_GEN9_BC(dev_priv)) {
355 source_rates = skl_rates;
356 size = ARRAY_SIZE(skl_rates);
357 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
358 IS_BROADWELL(dev_priv)) {
359 source_rates = hsw_rates;
360 size = ARRAY_SIZE(hsw_rates);
362 source_rates = g4x_rates;
363 size = ARRAY_SIZE(g4x_rates);
366 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
367 if (max_rate && vbt_max_rate)
368 max_rate = min(max_rate, vbt_max_rate);
369 else if (vbt_max_rate)
370 max_rate = vbt_max_rate;
373 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
375 intel_dp->source_rates = source_rates;
376 intel_dp->num_source_rates = size;
379 static int intersect_rates(const int *source_rates, int source_len,
380 const int *sink_rates, int sink_len,
383 int i = 0, j = 0, k = 0;
385 while (i < source_len && j < sink_len) {
386 if (source_rates[i] == sink_rates[j]) {
387 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
389 common_rates[k] = source_rates[i];
393 } else if (source_rates[i] < sink_rates[j]) {
402 /* return index of rate in rates array, or -1 if not found */
403 static int intel_dp_rate_index(const int *rates, int len, int rate)
407 for (i = 0; i < len; i++)
408 if (rate == rates[i])
414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
416 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
418 drm_WARN_ON(&i915->drm,
419 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
421 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
422 intel_dp->num_source_rates,
423 intel_dp->sink_rates,
424 intel_dp->num_sink_rates,
425 intel_dp->common_rates);
427 /* Paranoia, there should always be something in common. */
428 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
429 intel_dp->common_rates[0] = 162000;
430 intel_dp->num_common_rates = 1;
434 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
438 * FIXME: we need to synchronize the current link parameters with
439 * hardware readout. Currently fast link training doesn't work on
442 if (link_rate == 0 ||
443 link_rate > intel_dp->max_link_rate)
446 if (lane_count == 0 ||
447 lane_count > intel_dp_max_lane_count(intel_dp))
453 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
457 const struct drm_display_mode *fixed_mode =
458 intel_dp->attached_connector->panel.fixed_mode;
459 int mode_rate, max_rate;
461 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
462 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
463 if (mode_rate > max_rate)
469 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
470 int link_rate, u8 lane_count)
472 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
476 * TODO: Enable fallback on MST links once MST link compute can handle
477 * the fallback params.
479 if (intel_dp->is_mst) {
480 drm_err(&i915->drm, "Link Training Unsuccessful\n");
484 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
485 drm_dbg_kms(&i915->drm,
486 "Retrying Link training for eDP with max parameters\n");
487 intel_dp->use_max_params = true;
491 index = intel_dp_rate_index(intel_dp->common_rates,
492 intel_dp->num_common_rates,
495 if (intel_dp_is_edp(intel_dp) &&
496 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
497 intel_dp->common_rates[index - 1],
499 drm_dbg_kms(&i915->drm,
500 "Retrying Link training for eDP with same parameters\n");
503 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
504 intel_dp->max_link_lane_count = lane_count;
505 } else if (lane_count > 1) {
506 if (intel_dp_is_edp(intel_dp) &&
507 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
508 intel_dp_max_common_rate(intel_dp),
510 drm_dbg_kms(&i915->drm,
511 "Retrying Link training for eDP with same parameters\n");
514 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
515 intel_dp->max_link_lane_count = lane_count >> 1;
517 drm_err(&i915->drm, "Link Training Unsuccessful\n");
524 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
526 return div_u64(mul_u32_u32(mode_clock, 1000000U),
527 DP_DSC_FEC_OVERHEAD_FACTOR);
531 small_joiner_ram_size_bits(struct drm_i915_private *i915)
533 if (INTEL_GEN(i915) >= 11)
539 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
540 u32 link_clock, u32 lane_count,
541 u32 mode_clock, u32 mode_hdisplay,
544 u32 bits_per_pixel, max_bpp_small_joiner_ram;
548 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
549 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
550 * for SST -> TimeSlotsPerMTP is 1,
551 * for MST -> TimeSlotsPerMTP has to be calculated
553 bits_per_pixel = (link_clock * lane_count * 8) /
554 intel_dp_mode_to_fec_clock(mode_clock);
555 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
557 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
558 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
562 max_bpp_small_joiner_ram *= 2;
564 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
565 max_bpp_small_joiner_ram);
568 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
569 * check, output bpp from small joiner RAM check)
571 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
574 u32 max_bpp_bigjoiner =
575 i915->max_cdclk_freq * 48 /
576 intel_dp_mode_to_fec_clock(mode_clock);
578 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
579 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
582 /* Error out if the max bpp is less than smallest allowed valid bpp */
583 if (bits_per_pixel < valid_dsc_bpp[0]) {
584 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
585 bits_per_pixel, valid_dsc_bpp[0]);
589 /* Find the nearest match in the array of known BPPs from VESA */
590 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
591 if (bits_per_pixel < valid_dsc_bpp[i + 1])
594 bits_per_pixel = valid_dsc_bpp[i];
597 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
598 * fractional part is 0
600 return bits_per_pixel << 4;
603 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
604 int mode_clock, int mode_hdisplay,
607 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
608 u8 min_slice_count, i;
611 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
612 min_slice_count = DIV_ROUND_UP(mode_clock,
613 DP_DSC_MAX_ENC_THROUGHPUT_0);
615 min_slice_count = DIV_ROUND_UP(mode_clock,
616 DP_DSC_MAX_ENC_THROUGHPUT_1);
618 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
619 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
620 drm_dbg_kms(&i915->drm,
621 "Unsupported slice width %d by DP DSC Sink device\n",
625 /* Also take into account max slice width */
626 min_slice_count = max_t(u8, min_slice_count,
627 DIV_ROUND_UP(mode_hdisplay,
630 /* Find the closest match to the valid slice count values */
631 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
632 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
634 if (test_slice_count >
635 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
638 /* big joiner needs small joiner to be enabled */
639 if (bigjoiner && test_slice_count < 4)
642 if (min_slice_count <= test_slice_count)
643 return test_slice_count;
646 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
651 static enum intel_output_format
652 intel_dp_output_format(struct drm_connector *connector,
653 const struct drm_display_mode *mode)
655 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
656 const struct drm_display_info *info = &connector->display_info;
658 if (!connector->ycbcr_420_allowed ||
659 !drm_mode_is_420_only(info, mode))
660 return INTEL_OUTPUT_FORMAT_RGB;
662 if (intel_dp->dfp.rgb_to_ycbcr &&
663 intel_dp->dfp.ycbcr_444_to_420)
664 return INTEL_OUTPUT_FORMAT_RGB;
666 if (intel_dp->dfp.ycbcr_444_to_420)
667 return INTEL_OUTPUT_FORMAT_YCBCR444;
669 return INTEL_OUTPUT_FORMAT_YCBCR420;
672 int intel_dp_min_bpp(enum intel_output_format output_format)
674 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
680 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
683 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
684 * format of the number of bytes per pixel will be half the number
685 * of bytes of RGB pixel.
687 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
694 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
695 const struct drm_display_mode *mode)
697 enum intel_output_format output_format =
698 intel_dp_output_format(connector, mode);
700 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
703 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
707 * Older platforms don't like hdisplay==4096 with DP.
709 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
710 * and frame counter increment), but we don't get vblank interrupts,
711 * and the pipe underruns immediately. The link also doesn't seem
712 * to get trained properly.
714 * On CHV the vblank interrupts don't seem to disappear but
715 * otherwise the symptoms are similar.
717 * TODO: confirm the behaviour on HSW+
719 return hdisplay == 4096 && !HAS_DDI(dev_priv);
722 static enum drm_mode_status
723 intel_dp_mode_valid_downstream(struct intel_connector *connector,
724 const struct drm_display_mode *mode,
727 struct intel_dp *intel_dp = intel_attached_dp(connector);
728 const struct drm_display_info *info = &connector->base.display_info;
731 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
732 if (intel_dp->dfp.pcon_max_frl_bw) {
735 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
737 target_bw = bpp * target_clock;
739 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
741 /* converting bw from Gbps to Kbps*/
742 max_frl_bw = max_frl_bw * 1000000;
744 if (target_bw > max_frl_bw)
745 return MODE_CLOCK_HIGH;
750 if (intel_dp->dfp.max_dotclock &&
751 target_clock > intel_dp->dfp.max_dotclock)
752 return MODE_CLOCK_HIGH;
754 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
755 tmds_clock = target_clock;
756 if (drm_mode_is_420_only(info, mode))
759 if (intel_dp->dfp.min_tmds_clock &&
760 tmds_clock < intel_dp->dfp.min_tmds_clock)
761 return MODE_CLOCK_LOW;
762 if (intel_dp->dfp.max_tmds_clock &&
763 tmds_clock > intel_dp->dfp.max_tmds_clock)
764 return MODE_CLOCK_HIGH;
769 static enum drm_mode_status
770 intel_dp_mode_valid(struct drm_connector *connector,
771 struct drm_display_mode *mode)
773 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
774 struct intel_connector *intel_connector = to_intel_connector(connector);
775 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
776 struct drm_i915_private *dev_priv = to_i915(connector->dev);
777 int target_clock = mode->clock;
778 int max_rate, mode_rate, max_lanes, max_link_clock;
779 int max_dotclk = dev_priv->max_dotclk_freq;
780 u16 dsc_max_output_bpp = 0;
781 u8 dsc_slice_count = 0;
782 enum drm_mode_status status;
783 bool dsc = false, bigjoiner = false;
785 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
786 return MODE_NO_DBLESCAN;
788 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
789 return MODE_H_ILLEGAL;
791 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
792 if (mode->hdisplay > fixed_mode->hdisplay)
795 if (mode->vdisplay > fixed_mode->vdisplay)
798 target_clock = fixed_mode->clock;
801 if (mode->clock < 10000)
802 return MODE_CLOCK_LOW;
804 if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
805 intel_dp_can_bigjoiner(intel_dp)) {
809 if (target_clock > max_dotclk)
810 return MODE_CLOCK_HIGH;
812 max_link_clock = intel_dp_max_link_rate(intel_dp);
813 max_lanes = intel_dp_max_lane_count(intel_dp);
815 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
816 mode_rate = intel_dp_link_required(target_clock,
817 intel_dp_mode_min_output_bpp(connector, mode));
819 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
820 return MODE_H_ILLEGAL;
823 * Output bpp is stored in 6.4 format so right shift by 4 to get the
824 * integer value since we support only integer values of bpp.
826 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
827 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
828 if (intel_dp_is_edp(intel_dp)) {
830 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
832 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
834 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
836 intel_dp_dsc_get_output_bpp(dev_priv,
843 intel_dp_dsc_get_slice_count(intel_dp,
849 dsc = dsc_max_output_bpp && dsc_slice_count;
852 /* big joiner configuration needs DSC */
853 if (bigjoiner && !dsc)
854 return MODE_CLOCK_HIGH;
856 if (mode_rate > max_rate && !dsc)
857 return MODE_CLOCK_HIGH;
859 status = intel_dp_mode_valid_downstream(intel_connector,
861 if (status != MODE_OK)
864 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
867 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
869 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
871 return max_rate >= 540000;
874 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
876 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
878 return max_rate >= 810000;
882 intel_dp_set_clock(struct intel_encoder *encoder,
883 struct intel_crtc_state *pipe_config)
885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886 const struct dp_link_dpll *divisor = NULL;
889 if (IS_G4X(dev_priv)) {
891 count = ARRAY_SIZE(g4x_dpll);
892 } else if (HAS_PCH_SPLIT(dev_priv)) {
894 count = ARRAY_SIZE(pch_dpll);
895 } else if (IS_CHERRYVIEW(dev_priv)) {
897 count = ARRAY_SIZE(chv_dpll);
898 } else if (IS_VALLEYVIEW(dev_priv)) {
900 count = ARRAY_SIZE(vlv_dpll);
903 if (divisor && count) {
904 for (i = 0; i < count; i++) {
905 if (pipe_config->port_clock == divisor[i].clock) {
906 pipe_config->dpll = divisor[i].dpll;
907 pipe_config->clock_set = true;
914 static void snprintf_int_array(char *str, size_t len,
915 const int *array, int nelem)
921 for (i = 0; i < nelem; i++) {
922 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
930 static void intel_dp_print_rates(struct intel_dp *intel_dp)
932 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
933 char str[128]; /* FIXME: too big for stack? */
935 if (!drm_debug_enabled(DRM_UT_KMS))
938 snprintf_int_array(str, sizeof(str),
939 intel_dp->source_rates, intel_dp->num_source_rates);
940 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
942 snprintf_int_array(str, sizeof(str),
943 intel_dp->sink_rates, intel_dp->num_sink_rates);
944 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
946 snprintf_int_array(str, sizeof(str),
947 intel_dp->common_rates, intel_dp->num_common_rates);
948 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
952 intel_dp_max_link_rate(struct intel_dp *intel_dp)
954 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
957 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
958 if (drm_WARN_ON(&i915->drm, len <= 0))
961 return intel_dp->common_rates[len - 1];
964 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
966 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
967 int i = intel_dp_rate_index(intel_dp->sink_rates,
968 intel_dp->num_sink_rates, rate);
970 if (drm_WARN_ON(&i915->drm, i < 0))
976 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
977 u8 *link_bw, u8 *rate_select)
979 /* eDP 1.4 rate select method. */
980 if (intel_dp->use_rate_select) {
983 intel_dp_rate_select(intel_dp, port_clock);
985 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
990 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
991 const struct intel_crtc_state *pipe_config)
993 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
995 /* On TGL, FEC is supported on all Pipes */
996 if (INTEL_GEN(dev_priv) >= 12)
999 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1005 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1006 const struct intel_crtc_state *pipe_config)
1008 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1009 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1012 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1013 const struct intel_crtc_state *crtc_state)
1015 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1018 return intel_dsc_source_support(crtc_state) &&
1019 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1022 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
1023 const struct intel_crtc_state *crtc_state)
1025 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1026 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1027 intel_dp->dfp.ycbcr_444_to_420);
1030 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
1031 const struct intel_crtc_state *crtc_state, int bpc)
1033 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
1035 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
1041 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
1042 const struct intel_crtc_state *crtc_state, int bpc)
1044 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
1046 if (intel_dp->dfp.min_tmds_clock &&
1047 tmds_clock < intel_dp->dfp.min_tmds_clock)
1050 if (intel_dp->dfp.max_tmds_clock &&
1051 tmds_clock > intel_dp->dfp.max_tmds_clock)
1057 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
1058 const struct intel_crtc_state *crtc_state,
1062 return intel_hdmi_deep_color_possible(crtc_state, bpc,
1063 intel_dp->has_hdmi_sink,
1064 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1065 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
1068 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1069 const struct intel_crtc_state *crtc_state)
1071 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1072 struct intel_connector *intel_connector = intel_dp->attached_connector;
1075 bpc = crtc_state->pipe_bpp / 3;
1077 if (intel_dp->dfp.max_bpc)
1078 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1080 if (intel_dp->dfp.min_tmds_clock) {
1081 for (; bpc >= 10; bpc -= 2) {
1082 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1088 if (intel_dp_is_edp(intel_dp)) {
1089 /* Get bpp from vbt only for panels that dont have bpp in edid */
1090 if (intel_connector->base.display_info.bpc == 0 &&
1091 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1092 drm_dbg_kms(&dev_priv->drm,
1093 "clamping bpp for eDP panel to BIOS-provided %i\n",
1094 dev_priv->vbt.edp.bpp);
1095 bpp = dev_priv->vbt.edp.bpp;
1102 /* Adjust link config limits based on compliance test requests. */
1104 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1105 struct intel_crtc_state *pipe_config,
1106 struct link_config_limits *limits)
1108 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1110 /* For DP Compliance we override the computed bpp for the pipe */
1111 if (intel_dp->compliance.test_data.bpc != 0) {
1112 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1114 limits->min_bpp = limits->max_bpp = bpp;
1115 pipe_config->dither_force_disable = bpp == 6 * 3;
1117 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1120 /* Use values requested by Compliance Test Request */
1121 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1124 /* Validate the compliance test data since max values
1125 * might have changed due to link train fallback.
1127 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1128 intel_dp->compliance.test_lane_count)) {
1129 index = intel_dp_rate_index(intel_dp->common_rates,
1130 intel_dp->num_common_rates,
1131 intel_dp->compliance.test_link_rate);
1133 limits->min_clock = limits->max_clock = index;
1134 limits->min_lane_count = limits->max_lane_count =
1135 intel_dp->compliance.test_lane_count;
1140 /* Optimize link config in order: max bpp, min clock, min lanes */
1142 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1143 struct intel_crtc_state *pipe_config,
1144 const struct link_config_limits *limits)
1146 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1147 int bpp, clock, lane_count;
1148 int mode_rate, link_clock, link_avail;
1150 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1151 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1153 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1156 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1157 for (lane_count = limits->min_lane_count;
1158 lane_count <= limits->max_lane_count;
1160 link_clock = intel_dp->common_rates[clock];
1161 link_avail = intel_dp_max_data_rate(link_clock,
1164 if (mode_rate <= link_avail) {
1165 pipe_config->lane_count = lane_count;
1166 pipe_config->pipe_bpp = bpp;
1167 pipe_config->port_clock = link_clock;
1178 /* Optimize link config in order: max bpp, min lanes, min clock */
1180 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1181 struct intel_crtc_state *pipe_config,
1182 const struct link_config_limits *limits)
1184 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1185 int bpp, clock, lane_count;
1186 int mode_rate, link_clock, link_avail;
1188 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1189 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1191 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1194 for (lane_count = limits->min_lane_count;
1195 lane_count <= limits->max_lane_count;
1197 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1198 link_clock = intel_dp->common_rates[clock];
1199 link_avail = intel_dp_max_data_rate(link_clock,
1202 if (mode_rate <= link_avail) {
1203 pipe_config->lane_count = lane_count;
1204 pipe_config->pipe_bpp = bpp;
1205 pipe_config->port_clock = link_clock;
1216 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1219 u8 dsc_bpc[3] = {0};
1221 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1223 for (i = 0; i < num_bpc; i++) {
1224 if (dsc_max_bpc >= dsc_bpc[i])
1225 return dsc_bpc[i] * 3;
1231 #define DSC_SUPPORTED_VERSION_MIN 1
1233 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1234 struct intel_crtc_state *crtc_state)
1236 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1238 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1243 * RC_MODEL_SIZE is currently a constant across all configurations.
1245 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1246 * DP_DSC_RC_BUF_SIZE for this.
1248 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1250 ret = intel_dsc_compute_params(encoder, crtc_state);
1255 * Slice Height of 8 works for all currently available panels. So start
1256 * with that if pic_height is an integral multiple of 8. Eventually add
1257 * logic to try multiple slice heights.
1259 if (vdsc_cfg->pic_height % 8 == 0)
1260 vdsc_cfg->slice_height = 8;
1261 else if (vdsc_cfg->pic_height % 4 == 0)
1262 vdsc_cfg->slice_height = 4;
1264 vdsc_cfg->slice_height = 2;
1266 vdsc_cfg->dsc_version_major =
1267 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1268 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1269 vdsc_cfg->dsc_version_minor =
1270 min(DSC_SUPPORTED_VERSION_MIN,
1271 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1272 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1274 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1277 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1278 if (!line_buf_depth) {
1279 drm_dbg_kms(&i915->drm,
1280 "DSC Sink Line Buffer Depth invalid\n");
1284 if (vdsc_cfg->dsc_version_minor == 2)
1285 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1286 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1288 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1289 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1291 vdsc_cfg->block_pred_enable =
1292 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1293 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1295 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1298 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1299 struct intel_crtc_state *pipe_config,
1300 struct drm_connector_state *conn_state,
1301 struct link_config_limits *limits)
1303 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1304 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1305 const struct drm_display_mode *adjusted_mode =
1306 &pipe_config->hw.adjusted_mode;
1311 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1312 intel_dp_supports_fec(intel_dp, pipe_config);
1314 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1317 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1318 if (INTEL_GEN(dev_priv) >= 12)
1319 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1321 dsc_max_bpc = min_t(u8, 10,
1322 conn_state->max_requested_bpc);
1324 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1326 /* Min Input BPC for ICL+ is 8 */
1327 if (pipe_bpp < 8 * 3) {
1328 drm_dbg_kms(&dev_priv->drm,
1329 "No DSC support for less than 8bpc\n");
1334 * For now enable DSC for max bpp, max link rate, max lane count.
1335 * Optimize this later for the minimum possible link rate/lane count
1336 * with DSC enabled for the requested mode.
1338 pipe_config->pipe_bpp = pipe_bpp;
1339 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1340 pipe_config->lane_count = limits->max_lane_count;
1342 if (intel_dp_is_edp(intel_dp)) {
1343 pipe_config->dsc.compressed_bpp =
1344 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1345 pipe_config->pipe_bpp);
1346 pipe_config->dsc.slice_count =
1347 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1350 u16 dsc_max_output_bpp;
1351 u8 dsc_dp_slice_count;
1353 dsc_max_output_bpp =
1354 intel_dp_dsc_get_output_bpp(dev_priv,
1355 pipe_config->port_clock,
1356 pipe_config->lane_count,
1357 adjusted_mode->crtc_clock,
1358 adjusted_mode->crtc_hdisplay,
1359 pipe_config->bigjoiner);
1360 dsc_dp_slice_count =
1361 intel_dp_dsc_get_slice_count(intel_dp,
1362 adjusted_mode->crtc_clock,
1363 adjusted_mode->crtc_hdisplay,
1364 pipe_config->bigjoiner);
1365 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1366 drm_dbg_kms(&dev_priv->drm,
1367 "Compressed BPP/Slice Count not supported\n");
1370 pipe_config->dsc.compressed_bpp = min_t(u16,
1371 dsc_max_output_bpp >> 4,
1372 pipe_config->pipe_bpp);
1373 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1376 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1377 * is greater than the maximum Cdclock and if slice count is even
1378 * then we need to use 2 VDSC instances.
1380 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1381 pipe_config->bigjoiner) {
1382 if (pipe_config->dsc.slice_count < 2) {
1383 drm_dbg_kms(&dev_priv->drm,
1384 "Cannot split stream to use 2 VDSC instances\n");
1388 pipe_config->dsc.dsc_split = true;
1391 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1393 drm_dbg_kms(&dev_priv->drm,
1394 "Cannot compute valid DSC parameters for Input Bpp = %d "
1395 "Compressed BPP = %d\n",
1396 pipe_config->pipe_bpp,
1397 pipe_config->dsc.compressed_bpp);
1401 pipe_config->dsc.compression_enable = true;
1402 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1403 "Compressed Bpp = %d Slice Count = %d\n",
1404 pipe_config->pipe_bpp,
1405 pipe_config->dsc.compressed_bpp,
1406 pipe_config->dsc.slice_count);
1412 intel_dp_compute_link_config(struct intel_encoder *encoder,
1413 struct intel_crtc_state *pipe_config,
1414 struct drm_connector_state *conn_state)
1416 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1417 const struct drm_display_mode *adjusted_mode =
1418 &pipe_config->hw.adjusted_mode;
1419 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1420 struct link_config_limits limits;
1424 common_len = intel_dp_common_len_rate_limit(intel_dp,
1425 intel_dp->max_link_rate);
1427 /* No common link rates between source and sink */
1428 drm_WARN_ON(encoder->base.dev, common_len <= 0);
1430 limits.min_clock = 0;
1431 limits.max_clock = common_len - 1;
1433 limits.min_lane_count = 1;
1434 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1436 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1437 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1439 if (intel_dp->use_max_params) {
1441 * Use the maximum clock and number of lanes the eDP panel
1442 * advertizes being capable of in case the initial fast
1443 * optimal params failed us. The panels are generally
1444 * designed to support only a single clock and lane
1445 * configuration, and typically on older panels these
1446 * values correspond to the native resolution of the panel.
1448 limits.min_lane_count = limits.max_lane_count;
1449 limits.min_clock = limits.max_clock;
1452 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1454 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1455 "max rate %d max bpp %d pixel clock %iKHz\n",
1456 limits.max_lane_count,
1457 intel_dp->common_rates[limits.max_clock],
1458 limits.max_bpp, adjusted_mode->crtc_clock);
1460 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1461 adjusted_mode->crtc_hdisplay > 5120) &&
1462 intel_dp_can_bigjoiner(intel_dp))
1463 pipe_config->bigjoiner = true;
1465 if (intel_dp_is_edp(intel_dp))
1467 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
1468 * section A.1: "It is recommended that the minimum number of
1469 * lanes be used, using the minimum link rate allowed for that
1470 * lane configuration."
1472 * Note that we fall back to the max clock and lane count for eDP
1473 * panels that fail with the fast optimal settings (see
1474 * intel_dp->use_max_params), in which case the fast vs. wide
1475 * choice doesn't matter.
1477 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
1479 /* Optimize for slow and wide. */
1480 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1482 /* enable compression if the mode doesn't fit available BW */
1483 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1484 if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
1485 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1486 conn_state, &limits);
1491 if (pipe_config->dsc.compression_enable) {
1492 drm_dbg_kms(&i915->drm,
1493 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1494 pipe_config->lane_count, pipe_config->port_clock,
1495 pipe_config->pipe_bpp,
1496 pipe_config->dsc.compressed_bpp);
1498 drm_dbg_kms(&i915->drm,
1499 "DP link rate required %i available %i\n",
1500 intel_dp_link_required(adjusted_mode->crtc_clock,
1501 pipe_config->dsc.compressed_bpp),
1502 intel_dp_max_data_rate(pipe_config->port_clock,
1503 pipe_config->lane_count));
1505 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1506 pipe_config->lane_count, pipe_config->port_clock,
1507 pipe_config->pipe_bpp);
1509 drm_dbg_kms(&i915->drm,
1510 "DP link rate required %i available %i\n",
1511 intel_dp_link_required(adjusted_mode->crtc_clock,
1512 pipe_config->pipe_bpp),
1513 intel_dp_max_data_rate(pipe_config->port_clock,
1514 pipe_config->lane_count));
1519 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1520 const struct drm_connector_state *conn_state)
1522 const struct intel_digital_connector_state *intel_conn_state =
1523 to_intel_digital_connector_state(conn_state);
1524 const struct drm_display_mode *adjusted_mode =
1525 &crtc_state->hw.adjusted_mode;
1528 * Our YCbCr output is always limited range.
1529 * crtc_state->limited_color_range only applies to RGB,
1530 * and it must never be set for YCbCr or we risk setting
1531 * some conflicting bits in PIPECONF which will mess up
1532 * the colors on the monitor.
1534 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1537 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1540 * CEA-861-E - 5.1 Default Encoding Parameters
1541 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1543 return crtc_state->pipe_bpp != 18 &&
1544 drm_default_rgb_quant_range(adjusted_mode) ==
1545 HDMI_QUANTIZATION_RANGE_LIMITED;
1547 return intel_conn_state->broadcast_rgb ==
1548 INTEL_BROADCAST_RGB_LIMITED;
1552 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1555 if (IS_G4X(dev_priv))
1557 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
1563 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1564 const struct drm_connector_state *conn_state,
1565 struct drm_dp_vsc_sdp *vsc)
1567 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1571 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1572 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1573 * Colorimetry Format indication.
1575 vsc->revision = 0x5;
1578 /* DP 1.4a spec, Table 2-120 */
1579 switch (crtc_state->output_format) {
1580 case INTEL_OUTPUT_FORMAT_YCBCR444:
1581 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1583 case INTEL_OUTPUT_FORMAT_YCBCR420:
1584 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1586 case INTEL_OUTPUT_FORMAT_RGB:
1588 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1591 switch (conn_state->colorspace) {
1592 case DRM_MODE_COLORIMETRY_BT709_YCC:
1593 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1595 case DRM_MODE_COLORIMETRY_XVYCC_601:
1596 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1598 case DRM_MODE_COLORIMETRY_XVYCC_709:
1599 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1601 case DRM_MODE_COLORIMETRY_SYCC_601:
1602 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1604 case DRM_MODE_COLORIMETRY_OPYCC_601:
1605 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1607 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1608 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1610 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1611 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1613 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1614 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1616 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1617 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1618 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1622 * RGB->YCBCR color conversion uses the BT.709
1625 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1626 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1628 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1632 vsc->bpc = crtc_state->pipe_bpp / 3;
1634 /* only RGB pixelformat supports 6 bpc */
1635 drm_WARN_ON(&dev_priv->drm,
1636 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1638 /* all YCbCr are always limited range */
1639 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1640 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1643 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1644 struct intel_crtc_state *crtc_state,
1645 const struct drm_connector_state *conn_state)
1647 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1649 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1650 if (crtc_state->has_psr)
1653 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1656 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1657 vsc->sdp_type = DP_SDP_VSC;
1658 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1659 &crtc_state->infoframes.vsc);
1662 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1663 const struct intel_crtc_state *crtc_state,
1664 const struct drm_connector_state *conn_state,
1665 struct drm_dp_vsc_sdp *vsc)
1667 vsc->sdp_type = DP_SDP_VSC;
1669 if (intel_dp->psr.psr2_enabled) {
1670 if (intel_dp->psr.colorimetry_support &&
1671 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1672 /* [PSR2, +Colorimetry] */
1673 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1677 * [PSR2, -Colorimetry]
1678 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1679 * 3D stereo + PSR/PSR2 + Y-coordinate.
1681 vsc->revision = 0x4;
1687 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1688 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1691 vsc->revision = 0x2;
1697 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1698 struct intel_crtc_state *crtc_state,
1699 const struct drm_connector_state *conn_state)
1702 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1703 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1705 if (!conn_state->hdr_output_metadata)
1708 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1711 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1715 crtc_state->infoframes.enable |=
1716 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1720 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1721 struct intel_crtc_state *pipe_config,
1722 int output_bpp, bool constant_n)
1724 struct intel_connector *intel_connector = intel_dp->attached_connector;
1725 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1727 if (pipe_config->vrr.enable)
1731 * DRRS and PSR can't be enable together, so giving preference to PSR
1732 * as it allows more power-savings by complete shutting down display,
1733 * so to guarantee this, intel_dp_drrs_compute_config() must be called
1734 * after intel_psr_compute_config().
1736 if (pipe_config->has_psr)
1739 if (!intel_connector->panel.downclock_mode ||
1740 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1743 pipe_config->has_drrs = true;
1744 intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
1745 intel_connector->panel.downclock_mode->clock,
1746 pipe_config->port_clock, &pipe_config->dp_m2_n2,
1747 constant_n, pipe_config->fec_enable);
1751 intel_dp_compute_config(struct intel_encoder *encoder,
1752 struct intel_crtc_state *pipe_config,
1753 struct drm_connector_state *conn_state)
1755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1756 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1757 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1758 enum port port = encoder->port;
1759 struct intel_connector *intel_connector = intel_dp->attached_connector;
1760 struct intel_digital_connector_state *intel_conn_state =
1761 to_intel_digital_connector_state(conn_state);
1762 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1763 int ret = 0, output_bpp;
1765 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1766 pipe_config->has_pch_encoder = true;
1768 pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1771 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1772 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1777 if (!intel_dp_port_has_audio(dev_priv, port))
1778 pipe_config->has_audio = false;
1779 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1780 pipe_config->has_audio = intel_dp->has_audio;
1782 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1784 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1785 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1788 if (HAS_GMCH(dev_priv))
1789 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1791 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1796 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1799 if (HAS_GMCH(dev_priv) &&
1800 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1803 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1806 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1809 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1813 pipe_config->limited_color_range =
1814 intel_dp_limited_color_range(pipe_config, conn_state);
1816 if (pipe_config->dsc.compression_enable)
1817 output_bpp = pipe_config->dsc.compressed_bpp;
1819 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1820 pipe_config->pipe_bpp);
1822 intel_link_compute_m_n(output_bpp,
1823 pipe_config->lane_count,
1824 adjusted_mode->crtc_clock,
1825 pipe_config->port_clock,
1826 &pipe_config->dp_m_n,
1827 constant_n, pipe_config->fec_enable);
1829 if (!HAS_DDI(dev_priv))
1830 intel_dp_set_clock(encoder, pipe_config);
1832 intel_vrr_compute_config(pipe_config, conn_state);
1833 intel_psr_compute_config(intel_dp, pipe_config);
1834 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1836 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1837 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1842 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1843 int link_rate, int lane_count)
1845 intel_dp->link_trained = false;
1846 intel_dp->link_rate = link_rate;
1847 intel_dp->lane_count = lane_count;
1850 static void intel_dp_prepare(struct intel_encoder *encoder,
1851 const struct intel_crtc_state *pipe_config)
1853 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1854 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1855 enum port port = encoder->port;
1856 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1857 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1859 intel_dp_set_link_params(intel_dp,
1860 pipe_config->port_clock,
1861 pipe_config->lane_count);
1864 * There are four kinds of DP registers:
1871 * IBX PCH and CPU are the same for almost everything,
1872 * except that the CPU DP PLL is configured in this
1875 * CPT PCH is quite different, having many bits moved
1876 * to the TRANS_DP_CTL register instead. That
1877 * configuration happens (oddly) in ilk_pch_enable
1880 /* Preserve the BIOS-computed detected bit. This is
1881 * supposed to be read-only.
1883 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
1885 /* Handle DP bits in common between all three register formats */
1886 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1887 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1889 /* Split out the IBX/CPU vs CPT settings */
1891 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1892 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1893 intel_dp->DP |= DP_SYNC_HS_HIGH;
1894 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1895 intel_dp->DP |= DP_SYNC_VS_HIGH;
1896 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1898 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1899 intel_dp->DP |= DP_ENHANCED_FRAMING;
1901 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
1902 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1905 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1907 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
1908 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1909 trans_dp |= TRANS_DP_ENH_FRAMING;
1911 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1912 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
1914 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1915 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1917 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1918 intel_dp->DP |= DP_SYNC_HS_HIGH;
1919 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1920 intel_dp->DP |= DP_SYNC_VS_HIGH;
1921 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1923 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1924 intel_dp->DP |= DP_ENHANCED_FRAMING;
1926 if (IS_CHERRYVIEW(dev_priv))
1927 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
1929 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
1934 /* Enable backlight PWM and backlight PP control. */
1935 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1936 const struct drm_connector_state *conn_state)
1938 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1939 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1941 if (!intel_dp_is_edp(intel_dp))
1944 drm_dbg_kms(&i915->drm, "\n");
1946 intel_panel_enable_backlight(crtc_state, conn_state);
1947 intel_pps_backlight_on(intel_dp);
1950 /* Disable backlight PP control and backlight PWM. */
1951 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1953 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1954 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956 if (!intel_dp_is_edp(intel_dp))
1959 drm_dbg_kms(&i915->drm, "\n");
1961 intel_pps_backlight_off(intel_dp);
1962 intel_panel_disable_backlight(old_conn_state);
1965 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
1967 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1968 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1969 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
1971 I915_STATE_WARN(cur_state != state,
1972 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
1973 dig_port->base.base.base.id, dig_port->base.base.name,
1974 onoff(state), onoff(cur_state));
1976 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
1978 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
1980 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
1982 I915_STATE_WARN(cur_state != state,
1983 "eDP PLL state assertion failure (expected %s, current %s)\n",
1984 onoff(state), onoff(cur_state));
1986 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
1987 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
1989 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
1990 const struct intel_crtc_state *pipe_config)
1992 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1995 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1996 assert_dp_port_disabled(intel_dp);
1997 assert_edp_pll_disabled(dev_priv);
1999 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
2000 pipe_config->port_clock);
2002 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2004 if (pipe_config->port_clock == 162000)
2005 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2007 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2009 intel_de_write(dev_priv, DP_A, intel_dp->DP);
2010 intel_de_posting_read(dev_priv, DP_A);
2014 * [DevILK] Work around required when enabling DP PLL
2015 * while a pipe is enabled going to FDI:
2016 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2017 * 2. Program DP PLL enable
2019 if (IS_GEN(dev_priv, 5))
2020 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2022 intel_dp->DP |= DP_PLL_ENABLE;
2024 intel_de_write(dev_priv, DP_A, intel_dp->DP);
2025 intel_de_posting_read(dev_priv, DP_A);
2029 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
2030 const struct intel_crtc_state *old_crtc_state)
2032 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2035 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2036 assert_dp_port_disabled(intel_dp);
2037 assert_edp_pll_enabled(dev_priv);
2039 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
2041 intel_dp->DP &= ~DP_PLL_ENABLE;
2043 intel_de_write(dev_priv, DP_A, intel_dp->DP);
2044 intel_de_posting_read(dev_priv, DP_A);
2048 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2051 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2052 * be capable of signalling downstream hpd with a long pulse.
2053 * Whether or not that means D3 is safe to use is not clear,
2054 * but let's assume so until proven otherwise.
2056 * FIXME should really check all downstream ports...
2058 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2059 drm_dp_is_branch(intel_dp->dpcd) &&
2060 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2063 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2064 const struct intel_crtc_state *crtc_state,
2067 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2070 if (!crtc_state->dsc.compression_enable)
2073 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2074 enable ? DP_DECOMPRESSION_EN : 0);
2076 drm_dbg_kms(&i915->drm,
2077 "Failed to %s sink decompression state\n",
2078 enable ? "enable" : "disable");
2082 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2084 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2085 u8 oui[] = { 0x00, 0xaa, 0x01 };
2089 * During driver init, we want to be careful and avoid changing the source OUI if it's
2090 * already set to what we want, so as to avoid clearing any state by accident
2093 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2094 drm_err(&i915->drm, "Failed to read source OUI\n");
2096 if (memcmp(oui, buf, sizeof(oui)) == 0)
2100 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2101 drm_err(&i915->drm, "Failed to write source OUI\n");
2104 /* If the device supports it, try to set the power state appropriately */
2105 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2107 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2108 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2111 /* Should have a valid DPCD by this point */
2112 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2115 if (mode != DP_SET_POWER_D0) {
2116 if (downstream_hpd_needs_d0(intel_dp))
2119 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2121 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2123 lspcon_resume(dp_to_dig_port(intel_dp));
2125 /* Write the source OUI as early as possible */
2126 if (intel_dp_is_edp(intel_dp))
2127 intel_edp_init_source_oui(intel_dp, false);
2130 * When turning on, we need to retry for 1ms to give the sink
2133 for (i = 0; i < 3; i++) {
2134 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2140 if (ret == 1 && lspcon->active)
2141 lspcon_wait_pcon_mode(lspcon);
2145 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2146 encoder->base.base.id, encoder->base.name,
2147 mode == DP_SET_POWER_D0 ? "D0" : "D3");
2150 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2151 enum port port, enum pipe *pipe)
2155 for_each_pipe(dev_priv, p) {
2156 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
2158 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2164 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
2167 /* must initialize pipe to something for the asserts */
2173 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2174 i915_reg_t dp_reg, enum port port,
2180 val = intel_de_read(dev_priv, dp_reg);
2182 ret = val & DP_PORT_EN;
2184 /* asserts want to know the pipe even if the port is disabled */
2185 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2186 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2187 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2188 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2189 else if (IS_CHERRYVIEW(dev_priv))
2190 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2192 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2197 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2201 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2202 intel_wakeref_t wakeref;
2205 wakeref = intel_display_power_get_if_enabled(dev_priv,
2206 encoder->power_domain);
2210 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2211 encoder->port, pipe);
2213 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2218 static void intel_dp_get_config(struct intel_encoder *encoder,
2219 struct intel_crtc_state *pipe_config)
2221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2222 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2224 enum port port = encoder->port;
2225 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2227 if (encoder->type == INTEL_OUTPUT_EDP)
2228 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2230 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2232 tmp = intel_de_read(dev_priv, intel_dp->output_reg);
2234 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2236 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2237 u32 trans_dp = intel_de_read(dev_priv,
2238 TRANS_DP_CTL(crtc->pipe));
2240 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2241 flags |= DRM_MODE_FLAG_PHSYNC;
2243 flags |= DRM_MODE_FLAG_NHSYNC;
2245 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2246 flags |= DRM_MODE_FLAG_PVSYNC;
2248 flags |= DRM_MODE_FLAG_NVSYNC;
2250 if (tmp & DP_SYNC_HS_HIGH)
2251 flags |= DRM_MODE_FLAG_PHSYNC;
2253 flags |= DRM_MODE_FLAG_NHSYNC;
2255 if (tmp & DP_SYNC_VS_HIGH)
2256 flags |= DRM_MODE_FLAG_PVSYNC;
2258 flags |= DRM_MODE_FLAG_NVSYNC;
2261 pipe_config->hw.adjusted_mode.flags |= flags;
2263 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2264 pipe_config->limited_color_range = true;
2266 pipe_config->lane_count =
2267 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2269 intel_dp_get_m_n(crtc, pipe_config);
2271 if (port == PORT_A) {
2272 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2273 pipe_config->port_clock = 162000;
2275 pipe_config->port_clock = 270000;
2278 pipe_config->hw.adjusted_mode.crtc_clock =
2279 intel_dotclock_calculate(pipe_config->port_clock,
2280 &pipe_config->dp_m_n);
2282 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2283 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2285 * This is a big fat ugly hack.
2287 * Some machines in UEFI boot mode provide us a VBT that has 18
2288 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2289 * unknown we fail to light up. Yet the same BIOS boots up with
2290 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2291 * max, not what it tells us to use.
2293 * Note: This will still be broken if the eDP panel is not lit
2294 * up by the BIOS, and thus we can't get the mode at module
2297 drm_dbg_kms(&dev_priv->drm,
2298 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2299 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2300 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2305 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2308 * intel_dp_sync_state - sync the encoder state during init/resume
2309 * @encoder: intel encoder to sync
2310 * @crtc_state: state for the CRTC connected to the encoder
2312 * Sync any state stored in the encoder wrt. HW state during driver init
2313 * and system resume.
2315 void intel_dp_sync_state(struct intel_encoder *encoder,
2316 const struct intel_crtc_state *crtc_state)
2318 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2321 * Don't clobber DPCD if it's been already read out during output
2322 * setup (eDP) or detect.
2324 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2325 intel_dp_get_dpcd(intel_dp);
2327 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2328 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2331 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2332 struct intel_crtc_state *crtc_state)
2334 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2338 * If BIOS has set an unsupported or non-standard link rate for some
2339 * reason force an encoder recompute and full modeset.
2341 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2342 crtc_state->port_clock) < 0) {
2343 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2344 crtc_state->uapi.connectors_changed = true;
2349 * FIXME hack to force full modeset when DSC is being used.
2351 * As long as we do not have full state readout and config comparison
2352 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2353 * Remove once we have readout for DSC.
2355 if (crtc_state->dsc.compression_enable) {
2356 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2357 crtc_state->uapi.mode_changed = true;
2361 if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) {
2362 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2363 crtc_state->uapi.mode_changed = true;
2370 static void intel_disable_dp(struct intel_atomic_state *state,
2371 struct intel_encoder *encoder,
2372 const struct intel_crtc_state *old_crtc_state,
2373 const struct drm_connector_state *old_conn_state)
2375 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2377 intel_dp->link_trained = false;
2379 if (old_crtc_state->has_audio)
2380 intel_audio_codec_disable(encoder,
2381 old_crtc_state, old_conn_state);
2383 /* Make sure the panel is off before trying to change the mode. But also
2384 * ensure that we have vdd while we switch off the panel. */
2385 intel_pps_vdd_on(intel_dp);
2386 intel_edp_backlight_off(old_conn_state);
2387 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2388 intel_pps_off(intel_dp);
2389 intel_dp->frl.is_trained = false;
2390 intel_dp->frl.trained_rate_gbps = 0;
2393 static void g4x_disable_dp(struct intel_atomic_state *state,
2394 struct intel_encoder *encoder,
2395 const struct intel_crtc_state *old_crtc_state,
2396 const struct drm_connector_state *old_conn_state)
2398 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
2401 static void vlv_disable_dp(struct intel_atomic_state *state,
2402 struct intel_encoder *encoder,
2403 const struct intel_crtc_state *old_crtc_state,
2404 const struct drm_connector_state *old_conn_state)
2406 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
2409 static void g4x_post_disable_dp(struct intel_atomic_state *state,
2410 struct intel_encoder *encoder,
2411 const struct intel_crtc_state *old_crtc_state,
2412 const struct drm_connector_state *old_conn_state)
2414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2415 enum port port = encoder->port;
2418 * Bspec does not list a specific disable sequence for g4x DP.
2419 * Follow the ilk+ sequence (disable pipe before the port) for
2420 * g4x DP as it does not suffer from underruns like the normal
2421 * g4x modeset sequence (disable pipe after the port).
2423 intel_dp_link_down(encoder, old_crtc_state);
2425 /* Only ilk+ has port A */
2427 ilk_edp_pll_off(intel_dp, old_crtc_state);
2430 static void vlv_post_disable_dp(struct intel_atomic_state *state,
2431 struct intel_encoder *encoder,
2432 const struct intel_crtc_state *old_crtc_state,
2433 const struct drm_connector_state *old_conn_state)
2435 intel_dp_link_down(encoder, old_crtc_state);
2438 static void chv_post_disable_dp(struct intel_atomic_state *state,
2439 struct intel_encoder *encoder,
2440 const struct intel_crtc_state *old_crtc_state,
2441 const struct drm_connector_state *old_conn_state)
2443 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2445 intel_dp_link_down(encoder, old_crtc_state);
2447 vlv_dpio_get(dev_priv);
2449 /* Assert data lane reset */
2450 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2452 vlv_dpio_put(dev_priv);
2456 cpt_set_link_train(struct intel_dp *intel_dp,
2457 const struct intel_crtc_state *crtc_state,
2460 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2461 u32 *DP = &intel_dp->DP;
2463 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2465 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
2466 case DP_TRAINING_PATTERN_DISABLE:
2467 *DP |= DP_LINK_TRAIN_OFF_CPT;
2469 case DP_TRAINING_PATTERN_1:
2470 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2472 case DP_TRAINING_PATTERN_2:
2473 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2475 case DP_TRAINING_PATTERN_3:
2476 drm_dbg_kms(&dev_priv->drm,
2477 "TPS3 not supported, using TPS2 instead\n");
2478 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2482 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2483 intel_de_posting_read(dev_priv, intel_dp->output_reg);
2486 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2488 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2490 /* Clear the cached register set to avoid using stale values */
2492 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2494 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2495 intel_dp->pcon_dsc_dpcd,
2496 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2497 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2498 DP_PCON_DSC_ENCODER);
2500 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2501 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2504 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2506 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2509 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2510 if (frl_bw_mask & (1 << i))
2516 static int intel_dp_pcon_set_frl_mask(int max_frl)
2520 return DP_PCON_FRL_BW_MASK_48GBPS;
2522 return DP_PCON_FRL_BW_MASK_40GBPS;
2524 return DP_PCON_FRL_BW_MASK_32GBPS;
2526 return DP_PCON_FRL_BW_MASK_24GBPS;
2528 return DP_PCON_FRL_BW_MASK_18GBPS;
2530 return DP_PCON_FRL_BW_MASK_9GBPS;
2536 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2538 struct intel_connector *intel_connector = intel_dp->attached_connector;
2539 struct drm_connector *connector = &intel_connector->base;
2541 int max_lanes, rate_per_lane;
2542 int max_dsc_lanes, dsc_rate_per_lane;
2544 max_lanes = connector->display_info.hdmi.max_lanes;
2545 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2546 max_frl_rate = max_lanes * rate_per_lane;
2548 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2549 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2550 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2551 if (max_dsc_lanes && dsc_rate_per_lane)
2552 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2555 return max_frl_rate;
2558 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2560 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
2561 #define PCON_CONCURRENT_MODE (1 > 0)
2562 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
2563 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
2564 #define TIMEOUT_FRL_READY_MS 500
2565 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2567 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2568 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2569 u8 max_frl_bw_mask = 0, frl_trained_mask;
2572 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2576 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2577 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2579 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2580 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2582 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2584 if (max_frl_bw <= 0)
2587 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2590 /* Wait for PCON to be FRL Ready */
2591 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2596 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2597 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
2600 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
2603 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2607 * Wait for FRL to be completed
2608 * Check if the HDMI Link is up and active.
2610 wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2615 /* Verify HDMI Link configuration shows FRL Mode */
2616 if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2617 DP_PCON_HDMI_MODE_FRL) {
2618 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2621 drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2623 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2624 intel_dp->frl.is_trained = true;
2625 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2630 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2632 if (drm_dp_is_branch(intel_dp->dpcd) &&
2633 intel_dp->has_hdmi_sink &&
2634 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2640 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2642 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2644 /* Always go for FRL training if supported */
2645 if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2646 intel_dp->frl.is_trained)
2649 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2652 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2653 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2654 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2656 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2657 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2659 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2664 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2666 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2668 return intel_hdmi_dsc_get_slice_height(vactive);
2672 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2673 const struct intel_crtc_state *crtc_state)
2675 struct intel_connector *intel_connector = intel_dp->attached_connector;
2676 struct drm_connector *connector = &intel_connector->base;
2677 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2678 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2679 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2680 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2682 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2683 pcon_max_slice_width,
2684 hdmi_max_slices, hdmi_throughput);
2688 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2689 const struct intel_crtc_state *crtc_state,
2690 int num_slices, int slice_width)
2692 struct intel_connector *intel_connector = intel_dp->attached_connector;
2693 struct drm_connector *connector = &intel_connector->base;
2694 int output_format = crtc_state->output_format;
2695 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2696 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2697 int hdmi_max_chunk_bytes =
2698 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2700 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2701 num_slices, output_format, hdmi_all_bpp,
2702 hdmi_max_chunk_bytes);
2706 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2707 const struct intel_crtc_state *crtc_state)
2715 struct intel_connector *intel_connector = intel_dp->attached_connector;
2716 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2717 struct drm_connector *connector;
2718 bool hdmi_is_dsc_1_2;
2720 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2723 if (!intel_connector)
2725 connector = &intel_connector->base;
2726 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2728 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2732 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2736 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2740 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2743 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2744 num_slices, slice_width);
2745 if (!bits_per_pixel)
2748 pps_param[0] = slice_height & 0xFF;
2749 pps_param[1] = slice_height >> 8;
2750 pps_param[2] = slice_width & 0xFF;
2751 pps_param[3] = slice_width >> 8;
2752 pps_param[4] = bits_per_pixel & 0xFF;
2753 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2755 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2757 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2761 g4x_set_link_train(struct intel_dp *intel_dp,
2762 const struct intel_crtc_state *crtc_state,
2765 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2766 u32 *DP = &intel_dp->DP;
2768 *DP &= ~DP_LINK_TRAIN_MASK;
2770 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
2771 case DP_TRAINING_PATTERN_DISABLE:
2772 *DP |= DP_LINK_TRAIN_OFF;
2774 case DP_TRAINING_PATTERN_1:
2775 *DP |= DP_LINK_TRAIN_PAT_1;
2777 case DP_TRAINING_PATTERN_2:
2778 *DP |= DP_LINK_TRAIN_PAT_2;
2780 case DP_TRAINING_PATTERN_3:
2781 drm_dbg_kms(&dev_priv->drm,
2782 "TPS3 not supported, using TPS2 instead\n");
2783 *DP |= DP_LINK_TRAIN_PAT_2;
2787 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2788 intel_de_posting_read(dev_priv, intel_dp->output_reg);
2791 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2792 const struct intel_crtc_state *crtc_state)
2794 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2796 /* enable with pattern 1 (as per spec) */
2798 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
2799 DP_TRAINING_PATTERN_1);
2802 * Magic for VLV/CHV. We _must_ first set up the register
2803 * without actually enabling the port, and then do another
2804 * write to enable the port. Otherwise link training will
2805 * fail when the power sequencer is freshly used for this port.
2807 intel_dp->DP |= DP_PORT_EN;
2808 if (crtc_state->has_audio)
2809 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2811 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
2812 intel_de_posting_read(dev_priv, intel_dp->output_reg);
2815 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2816 const struct intel_crtc_state *crtc_state)
2818 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2821 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2824 if (!drm_dp_is_branch(intel_dp->dpcd))
2827 tmp = intel_dp->has_hdmi_sink ?
2828 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2830 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2831 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2832 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
2833 enableddisabled(intel_dp->has_hdmi_sink));
2835 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2836 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2838 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2839 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2840 drm_dbg_kms(&i915->drm,
2841 "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
2842 enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
2845 if (intel_dp->dfp.rgb_to_ycbcr) {
2849 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2850 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2853 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2855 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2856 intel_dp->downstream_ports,
2857 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2858 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2859 intel_dp->downstream_ports,
2860 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2861 switch (crtc_state->infoframes.vsc.colorimetry) {
2862 case DP_COLORIMETRY_BT2020_RGB:
2863 case DP_COLORIMETRY_BT2020_YCC:
2865 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2867 case DP_COLORIMETRY_BT709_YCC:
2868 case DP_COLORIMETRY_XVYCC_709:
2870 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2877 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2878 drm_dbg_kms(&i915->drm,
2879 "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
2880 enableddisabled(tmp ? true : false));
2883 static void intel_enable_dp(struct intel_atomic_state *state,
2884 struct intel_encoder *encoder,
2885 const struct intel_crtc_state *pipe_config,
2886 const struct drm_connector_state *conn_state)
2888 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2889 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2890 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2891 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
2892 enum pipe pipe = crtc->pipe;
2893 intel_wakeref_t wakeref;
2895 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
2898 with_intel_pps_lock(intel_dp, wakeref) {
2899 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2900 vlv_pps_init(encoder, pipe_config);
2902 intel_dp_enable_port(intel_dp, pipe_config);
2904 intel_pps_vdd_on_unlocked(intel_dp);
2905 intel_pps_on_unlocked(intel_dp);
2906 intel_pps_vdd_off_unlocked(intel_dp, true);
2909 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2910 unsigned int lane_mask = 0x0;
2912 if (IS_CHERRYVIEW(dev_priv))
2913 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2915 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2919 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2920 intel_dp_configure_protocol_converter(intel_dp, pipe_config);
2921 intel_dp_check_frl_training(intel_dp);
2922 intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
2923 intel_dp_start_link_train(intel_dp, pipe_config);
2924 intel_dp_stop_link_train(intel_dp, pipe_config);
2926 if (pipe_config->has_audio) {
2927 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
2929 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2933 static void g4x_enable_dp(struct intel_atomic_state *state,
2934 struct intel_encoder *encoder,
2935 const struct intel_crtc_state *pipe_config,
2936 const struct drm_connector_state *conn_state)
2938 intel_enable_dp(state, encoder, pipe_config, conn_state);
2939 intel_edp_backlight_on(pipe_config, conn_state);
2942 static void vlv_enable_dp(struct intel_atomic_state *state,
2943 struct intel_encoder *encoder,
2944 const struct intel_crtc_state *pipe_config,
2945 const struct drm_connector_state *conn_state)
2947 intel_edp_backlight_on(pipe_config, conn_state);
2950 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
2951 struct intel_encoder *encoder,
2952 const struct intel_crtc_state *pipe_config,
2953 const struct drm_connector_state *conn_state)
2955 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2956 enum port port = encoder->port;
2958 intel_dp_prepare(encoder, pipe_config);
2960 /* Only ilk+ has port A */
2962 ilk_edp_pll_on(intel_dp, pipe_config);
2965 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
2966 struct intel_encoder *encoder,
2967 const struct intel_crtc_state *pipe_config,
2968 const struct drm_connector_state *conn_state)
2970 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2972 intel_enable_dp(state, encoder, pipe_config, conn_state);
2975 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
2976 struct intel_encoder *encoder,
2977 const struct intel_crtc_state *pipe_config,
2978 const struct drm_connector_state *conn_state)
2980 intel_dp_prepare(encoder, pipe_config);
2982 vlv_phy_pre_pll_enable(encoder, pipe_config);
2985 static void chv_pre_enable_dp(struct intel_atomic_state *state,
2986 struct intel_encoder *encoder,
2987 const struct intel_crtc_state *pipe_config,
2988 const struct drm_connector_state *conn_state)
2990 chv_phy_pre_encoder_enable(encoder, pipe_config);
2992 intel_enable_dp(state, encoder, pipe_config, conn_state);
2994 /* Second common lane will stay alive on its own now */
2995 chv_phy_release_cl2_override(encoder);
2998 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
2999 struct intel_encoder *encoder,
3000 const struct intel_crtc_state *pipe_config,
3001 const struct drm_connector_state *conn_state)
3003 intel_dp_prepare(encoder, pipe_config);
3005 chv_phy_pre_pll_enable(encoder, pipe_config);
3008 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3009 struct intel_encoder *encoder,
3010 const struct intel_crtc_state *old_crtc_state,
3011 const struct drm_connector_state *old_conn_state)
3013 chv_phy_post_pll_disable(encoder, old_crtc_state);
3016 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
3017 const struct intel_crtc_state *crtc_state)
3019 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3022 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
3023 const struct intel_crtc_state *crtc_state)
3025 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3028 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
3030 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3033 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
3035 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3038 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
3039 const struct intel_crtc_state *crtc_state)
3041 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3042 unsigned long demph_reg_value, preemph_reg_value,
3043 uniqtranscale_reg_value;
3044 u8 train_set = intel_dp->train_set[0];
3046 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3047 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3048 preemph_reg_value = 0x0004000;
3049 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3051 demph_reg_value = 0x2B405555;
3052 uniqtranscale_reg_value = 0x552AB83A;
3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3055 demph_reg_value = 0x2B404040;
3056 uniqtranscale_reg_value = 0x5548B83A;
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3059 demph_reg_value = 0x2B245555;
3060 uniqtranscale_reg_value = 0x5560B83A;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3063 demph_reg_value = 0x2B405555;
3064 uniqtranscale_reg_value = 0x5598DA3A;
3070 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3071 preemph_reg_value = 0x0002000;
3072 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3074 demph_reg_value = 0x2B404040;
3075 uniqtranscale_reg_value = 0x5552B83A;
3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3078 demph_reg_value = 0x2B404848;
3079 uniqtranscale_reg_value = 0x5580B83A;
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3082 demph_reg_value = 0x2B404040;
3083 uniqtranscale_reg_value = 0x55ADDA3A;
3089 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3090 preemph_reg_value = 0x0000000;
3091 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3093 demph_reg_value = 0x2B305555;
3094 uniqtranscale_reg_value = 0x5570B83A;
3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3097 demph_reg_value = 0x2B2B4040;
3098 uniqtranscale_reg_value = 0x55ADDA3A;
3104 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3105 preemph_reg_value = 0x0006000;
3106 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3108 demph_reg_value = 0x1B405555;
3109 uniqtranscale_reg_value = 0x55ADDA3A;
3119 vlv_set_phy_signal_level(encoder, crtc_state,
3120 demph_reg_value, preemph_reg_value,
3121 uniqtranscale_reg_value, 0);
3124 static void chv_set_signal_levels(struct intel_dp *intel_dp,
3125 const struct intel_crtc_state *crtc_state)
3127 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3128 u32 deemph_reg_value, margin_reg_value;
3129 bool uniq_trans_scale = false;
3130 u8 train_set = intel_dp->train_set[0];
3132 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3133 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3136 deemph_reg_value = 128;
3137 margin_reg_value = 52;
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3140 deemph_reg_value = 128;
3141 margin_reg_value = 77;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3144 deemph_reg_value = 128;
3145 margin_reg_value = 102;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3148 deemph_reg_value = 128;
3149 margin_reg_value = 154;
3150 uniq_trans_scale = true;
3156 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3157 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3159 deemph_reg_value = 85;
3160 margin_reg_value = 78;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3163 deemph_reg_value = 85;
3164 margin_reg_value = 116;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3167 deemph_reg_value = 85;
3168 margin_reg_value = 154;
3174 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3175 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3177 deemph_reg_value = 64;
3178 margin_reg_value = 104;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3181 deemph_reg_value = 64;
3182 margin_reg_value = 154;
3188 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3189 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191 deemph_reg_value = 43;
3192 margin_reg_value = 154;
3202 chv_set_phy_signal_level(encoder, crtc_state,
3203 deemph_reg_value, margin_reg_value,
3207 static u32 g4x_signal_levels(u8 train_set)
3209 u32 signal_levels = 0;
3211 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3214 signal_levels |= DP_VOLTAGE_0_4;
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3217 signal_levels |= DP_VOLTAGE_0_6;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3220 signal_levels |= DP_VOLTAGE_0_8;
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3223 signal_levels |= DP_VOLTAGE_1_2;
3226 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3227 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3229 signal_levels |= DP_PRE_EMPHASIS_0;
3231 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3232 signal_levels |= DP_PRE_EMPHASIS_3_5;
3234 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3235 signal_levels |= DP_PRE_EMPHASIS_6;
3237 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3238 signal_levels |= DP_PRE_EMPHASIS_9_5;
3241 return signal_levels;
3245 g4x_set_signal_levels(struct intel_dp *intel_dp,
3246 const struct intel_crtc_state *crtc_state)
3248 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3249 u8 train_set = intel_dp->train_set[0];
3252 signal_levels = g4x_signal_levels(train_set);
3254 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3257 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
3258 intel_dp->DP |= signal_levels;
3260 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3261 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3264 /* SNB CPU eDP voltage swing and pre-emphasis control */
3265 static u32 snb_cpu_edp_signal_levels(u8 train_set)
3267 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3268 DP_TRAIN_PRE_EMPHASIS_MASK);
3270 switch (signal_levels) {
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3273 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3275 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3278 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3281 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3284 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3286 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3287 "0x%x\n", signal_levels);
3288 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3293 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
3294 const struct intel_crtc_state *crtc_state)
3296 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3297 u8 train_set = intel_dp->train_set[0];
3300 signal_levels = snb_cpu_edp_signal_levels(train_set);
3302 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3305 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3306 intel_dp->DP |= signal_levels;
3308 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3309 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3312 /* IVB CPU eDP voltage swing and pre-emphasis control */
3313 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
3315 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3316 DP_TRAIN_PRE_EMPHASIS_MASK);
3318 switch (signal_levels) {
3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3320 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3322 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3325 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3328 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3330 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3333 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3335 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3338 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3339 "0x%x\n", signal_levels);
3340 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3345 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
3346 const struct intel_crtc_state *crtc_state)
3348 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3349 u8 train_set = intel_dp->train_set[0];
3352 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3354 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3357 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3358 intel_dp->DP |= signal_levels;
3360 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3361 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3364 static char dp_training_pattern_name(u8 train_pat)
3366 switch (train_pat) {
3367 case DP_TRAINING_PATTERN_1:
3368 case DP_TRAINING_PATTERN_2:
3369 case DP_TRAINING_PATTERN_3:
3370 return '0' + train_pat;
3371 case DP_TRAINING_PATTERN_4:
3374 MISSING_CASE(train_pat);
3380 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3381 const struct intel_crtc_state *crtc_state,
3384 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3385 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3386 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
3388 if (train_pat != DP_TRAINING_PATTERN_DISABLE)
3389 drm_dbg_kms(&dev_priv->drm,
3390 "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
3391 encoder->base.base.id, encoder->base.name,
3392 dp_training_pattern_name(train_pat));
3394 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
3398 intel_dp_link_down(struct intel_encoder *encoder,
3399 const struct intel_crtc_state *old_crtc_state)
3401 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3402 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3403 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3404 enum port port = encoder->port;
3405 u32 DP = intel_dp->DP;
3407 if (drm_WARN_ON(&dev_priv->drm,
3408 (intel_de_read(dev_priv, intel_dp->output_reg) &
3412 drm_dbg_kms(&dev_priv->drm, "\n");
3414 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3415 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3416 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3417 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3419 DP &= ~DP_LINK_TRAIN_MASK;
3420 DP |= DP_LINK_TRAIN_PAT_IDLE;
3422 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3423 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3425 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3426 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3427 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3430 * HW workaround for IBX, we need to move the port
3431 * to transcoder A after disabling it to allow the
3432 * matching HDMI port to be enabled on transcoder A.
3434 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3436 * We get CPU/PCH FIFO underruns on the other pipe when
3437 * doing the workaround. Sweep them under the rug.
3439 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3440 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3442 /* always enable with pattern 1 (as per spec) */
3443 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3444 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3445 DP_LINK_TRAIN_PAT_1;
3446 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3447 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3450 intel_de_write(dev_priv, intel_dp->output_reg, DP);
3451 intel_de_posting_read(dev_priv, intel_dp->output_reg);
3453 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3454 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3455 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3458 msleep(intel_dp->pps.panel_power_down_delay);
3462 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3463 intel_wakeref_t wakeref;
3465 with_intel_pps_lock(intel_dp, wakeref)
3466 intel_dp->pps.active_pipe = INVALID_PIPE;
3470 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3474 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3477 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3480 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
3482 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3485 * Clear the cached register set to avoid using stale values
3486 * for the sinks that do not support DSC.
3488 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
3490 /* Clear fec_capable to avoid using stale values */
3491 intel_dp->fec_capable = 0;
3493 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
3494 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
3495 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3496 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
3498 sizeof(intel_dp->dsc_dpcd)) < 0)
3500 "Failed to read DPCD register 0x%x\n",
3503 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
3504 (int)sizeof(intel_dp->dsc_dpcd),
3505 intel_dp->dsc_dpcd);
3507 /* FEC is supported only on DP 1.4 */
3508 if (!intel_dp_is_edp(intel_dp) &&
3509 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3510 &intel_dp->fec_capable) < 0)
3512 "Failed to read FEC DPCD register\n");
3514 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3515 intel_dp->fec_capable);
3520 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3522 struct drm_i915_private *dev_priv =
3523 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3525 /* this function is meant to be called only once */
3526 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3528 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3531 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3532 drm_dp_is_branch(intel_dp->dpcd));
3535 * Read the eDP display control registers.
3537 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3538 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3539 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3540 * method). The display control registers should read zero if they're
3541 * not supported anyway.
3543 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3544 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3545 sizeof(intel_dp->edp_dpcd))
3546 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3547 (int)sizeof(intel_dp->edp_dpcd),
3548 intel_dp->edp_dpcd);
3551 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3552 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3554 intel_psr_init_dpcd(intel_dp);
3556 /* Read the eDP 1.4+ supported link rates. */
3557 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3558 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3561 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3562 sink_rates, sizeof(sink_rates));
3564 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3565 int val = le16_to_cpu(sink_rates[i]);
3570 /* Value read multiplied by 200kHz gives the per-lane
3571 * link rate in kHz. The source rates are, however,
3572 * stored in terms of LS_Clk kHz. The full conversion
3573 * back to symbols is
3574 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3576 intel_dp->sink_rates[i] = (val * 200) / 10;
3578 intel_dp->num_sink_rates = i;
3582 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3583 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3585 if (intel_dp->num_sink_rates)
3586 intel_dp->use_rate_select = true;
3588 intel_dp_set_sink_rates(intel_dp);
3590 intel_dp_set_common_rates(intel_dp);
3592 /* Read the eDP DSC DPCD registers */
3593 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3594 intel_dp_get_dsc_sink_cap(intel_dp);
3597 * If needed, program our source OUI so we can make various Intel-specific AUX services
3598 * available (such as HDR backlight controls)
3600 intel_edp_init_source_oui(intel_dp, true);
3606 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3608 if (!intel_dp->attached_connector)
3611 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3617 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3621 intel_dp_lttpr_init(intel_dp);
3623 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
3627 * Don't clobber cached eDP rates. Also skip re-reading
3628 * the OUI/ID since we know it won't change.
3630 if (!intel_dp_is_edp(intel_dp)) {
3631 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3632 drm_dp_is_branch(intel_dp->dpcd));
3634 intel_dp_set_sink_rates(intel_dp);
3635 intel_dp_set_common_rates(intel_dp);
3638 if (intel_dp_has_sink_count(intel_dp)) {
3639 ret = drm_dp_read_sink_count(&intel_dp->aux);
3644 * Sink count can change between short pulse hpd hence
3645 * a member variable in intel_dp will track any changes
3646 * between short pulse interrupts.
3648 intel_dp->sink_count = ret;
3651 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3652 * a dongle is present but no display. Unless we require to know
3653 * if a dongle is present or not, we don't need to update
3654 * downstream port information. So, an early return here saves
3655 * time from performing other operations which are not required.
3657 if (!intel_dp->sink_count)
3661 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3662 intel_dp->downstream_ports) == 0;
3666 intel_dp_can_mst(struct intel_dp *intel_dp)
3668 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3670 return i915->params.enable_dp_mst &&
3671 intel_dp->can_mst &&
3672 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3676 intel_dp_configure_mst(struct intel_dp *intel_dp)
3678 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3679 struct intel_encoder *encoder =
3680 &dp_to_dig_port(intel_dp)->base;
3681 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3683 drm_dbg_kms(&i915->drm,
3684 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3685 encoder->base.base.id, encoder->base.name,
3686 yesno(intel_dp->can_mst), yesno(sink_can_mst),
3687 yesno(i915->params.enable_dp_mst));
3689 if (!intel_dp->can_mst)
3692 intel_dp->is_mst = sink_can_mst &&
3693 i915->params.enable_dp_mst;
3695 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3700 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3702 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3703 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3708 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3709 const struct drm_connector_state *conn_state)
3712 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3713 * of Color Encoding Format and Content Color Gamut], in order to
3714 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3716 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3719 switch (conn_state->colorspace) {
3720 case DRM_MODE_COLORIMETRY_SYCC_601:
3721 case DRM_MODE_COLORIMETRY_OPYCC_601:
3722 case DRM_MODE_COLORIMETRY_BT2020_YCC:
3723 case DRM_MODE_COLORIMETRY_BT2020_RGB:
3724 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3733 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3734 struct dp_sdp *sdp, size_t size)
3736 size_t length = sizeof(struct dp_sdp);
3741 memset(sdp, 0, size);
3744 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3745 * VSC SDP Header Bytes
3747 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3748 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3749 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3750 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3753 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3756 if (vsc->revision != 0x5)
3759 /* VSC SDP Payload for DB16 through DB18 */
3760 /* Pixel Encoding and Colorimetry Formats */
3761 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3762 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3769 sdp->db[17] = 0x1; /* DB17[3:0] */
3781 MISSING_CASE(vsc->bpc);
3784 /* Dynamic Range and Component Bit Depth */
3785 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3786 sdp->db[17] |= 0x80; /* DB17[7] */
3789 sdp->db[18] = vsc->content_type & 0x7;
3796 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
3800 size_t length = sizeof(struct dp_sdp);
3801 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3802 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3808 memset(sdp, 0, size);
3810 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3812 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
3816 if (len != infoframe_size) {
3817 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
3822 * Set up the infoframe sdp packet for HDR static metadata.
3823 * Prepare VSC Header for SU as per DP 1.4a spec,
3824 * Table 2-100 and Table 2-101
3827 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3828 sdp->sdp_header.HB0 = 0;
3830 * Packet Type 80h + Non-audio INFOFRAME Type value
3831 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3832 * - 80h + Non-audio INFOFRAME Type value
3833 * - InfoFrame Type: 0x07
3834 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3836 sdp->sdp_header.HB1 = drm_infoframe->type;
3838 * Least Significant Eight Bits of (Data Byte Count – 1)
3839 * infoframe_size - 1
3841 sdp->sdp_header.HB2 = 0x1D;
3842 /* INFOFRAME SDP Version Number */
3843 sdp->sdp_header.HB3 = (0x13 << 2);
3844 /* CTA Header Byte 2 (INFOFRAME Version Number) */
3845 sdp->db[0] = drm_infoframe->version;
3846 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3847 sdp->db[1] = drm_infoframe->length;
3849 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3850 * HDMI_INFOFRAME_HEADER_SIZE
3852 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3853 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3854 HDMI_DRM_INFOFRAME_SIZE);
3857 * Size of DP infoframe sdp packet for HDR static metadata consists of
3858 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3859 * - Two Data Blocks: 2 bytes
3860 * CTA Header Byte2 (INFOFRAME Version Number)
3861 * CTA Header Byte3 (Length of INFOFRAME)
3862 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3864 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3865 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3866 * will pad rest of the size.
3868 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3871 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3872 const struct intel_crtc_state *crtc_state,
3875 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3877 struct dp_sdp sdp = {};
3880 if ((crtc_state->infoframes.enable &
3881 intel_hdmi_infoframe_enable(type)) == 0)
3886 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3889 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3890 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
3898 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3901 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3904 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3905 const struct intel_crtc_state *crtc_state,
3906 struct drm_dp_vsc_sdp *vsc)
3908 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3910 struct dp_sdp sdp = {};
3913 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3915 if (drm_WARN_ON(&dev_priv->drm, len < 0))
3918 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3922 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3924 const struct intel_crtc_state *crtc_state,
3925 const struct drm_connector_state *conn_state)
3927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3928 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3929 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3930 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3931 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3932 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3933 u32 val = intel_de_read(dev_priv, reg);
3935 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3936 /* When PSR is enabled, this routine doesn't disable VSC DIP */
3937 if (intel_psr_enabled(intel_dp))
3940 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
3943 intel_de_write(dev_priv, reg, val);
3944 intel_de_posting_read(dev_priv, reg);
3948 intel_de_write(dev_priv, reg, val);
3949 intel_de_posting_read(dev_priv, reg);
3951 /* When PSR is enabled, VSC SDP is handled by PSR routine */
3952 if (!intel_psr_enabled(intel_dp))
3953 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3955 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3958 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3959 const void *buffer, size_t size)
3961 const struct dp_sdp *sdp = buffer;
3963 if (size < sizeof(struct dp_sdp))
3966 memset(vsc, 0, size);
3968 if (sdp->sdp_header.HB0 != 0)
3971 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3974 vsc->sdp_type = sdp->sdp_header.HB1;
3975 vsc->revision = sdp->sdp_header.HB2;
3976 vsc->length = sdp->sdp_header.HB3;
3978 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3979 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3981 * - HB2 = 0x2, HB3 = 0x8
3982 * VSC SDP supporting 3D stereo + PSR
3983 * - HB2 = 0x4, HB3 = 0xe
3984 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3985 * first scan line of the SU region (applies to eDP v1.4b
3989 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3991 * - HB2 = 0x5, HB3 = 0x13
3992 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3995 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3996 vsc->colorimetry = sdp->db[16] & 0xf;
3997 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3999 switch (sdp->db[17] & 0x7) {
4016 MISSING_CASE(sdp->db[17] & 0x7);
4020 vsc->content_type = sdp->db[18] & 0x7;
4029 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4030 const void *buffer, size_t size)
4034 const struct dp_sdp *sdp = buffer;
4036 if (size < sizeof(struct dp_sdp))
4039 if (sdp->sdp_header.HB0 != 0)
4042 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4046 * Least Significant Eight Bits of (Data Byte Count – 1)
4047 * 1Dh (i.e., Data Byte Count = 30 bytes).
4049 if (sdp->sdp_header.HB2 != 0x1D)
4052 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4053 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4056 /* INFOFRAME SDP Version Number */
4057 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4060 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4061 if (sdp->db[0] != 1)
4064 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4065 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4068 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4069 HDMI_DRM_INFOFRAME_SIZE);
4074 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4075 struct intel_crtc_state *crtc_state,
4076 struct drm_dp_vsc_sdp *vsc)
4078 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4079 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4081 unsigned int type = DP_SDP_VSC;
4082 struct dp_sdp sdp = {};
4085 /* When PSR is enabled, VSC SDP is handled by PSR routine */
4086 if (intel_psr_enabled(intel_dp))
4089 if ((crtc_state->infoframes.enable &
4090 intel_hdmi_infoframe_enable(type)) == 0)
4093 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4095 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4098 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4101 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4102 struct intel_crtc_state *crtc_state,
4103 struct hdmi_drm_infoframe *drm_infoframe)
4105 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4107 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4108 struct dp_sdp sdp = {};
4111 if ((crtc_state->infoframes.enable &
4112 intel_hdmi_infoframe_enable(type)) == 0)
4115 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4118 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4122 drm_dbg_kms(&dev_priv->drm,
4123 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4126 void intel_read_dp_sdp(struct intel_encoder *encoder,
4127 struct intel_crtc_state *crtc_state,
4130 if (encoder->type != INTEL_OUTPUT_DDI)
4135 intel_read_dp_vsc_sdp(encoder, crtc_state,
4136 &crtc_state->infoframes.vsc);
4138 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4139 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4140 &crtc_state->infoframes.drm.drm);
4148 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4150 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4153 u8 test_lane_count, test_link_bw;
4157 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4158 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4162 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4165 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4167 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4170 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4173 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4175 /* Validate the requested link rate and lane count */
4176 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4180 intel_dp->compliance.test_lane_count = test_lane_count;
4181 intel_dp->compliance.test_link_rate = test_link_rate;
4186 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4188 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4191 __be16 h_width, v_height;
4194 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4195 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4198 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4201 if (test_pattern != DP_COLOR_RAMP)
4204 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4207 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4211 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4214 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4218 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4221 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4224 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4226 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4228 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4229 case DP_TEST_BIT_DEPTH_6:
4230 intel_dp->compliance.test_data.bpc = 6;
4232 case DP_TEST_BIT_DEPTH_8:
4233 intel_dp->compliance.test_data.bpc = 8;
4239 intel_dp->compliance.test_data.video_pattern = test_pattern;
4240 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4241 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4242 /* Set test active flag here so userspace doesn't interrupt things */
4243 intel_dp->compliance.test_active = true;
4248 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4250 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4251 u8 test_result = DP_TEST_ACK;
4252 struct intel_connector *intel_connector = intel_dp->attached_connector;
4253 struct drm_connector *connector = &intel_connector->base;
4255 if (intel_connector->detect_edid == NULL ||
4256 connector->edid_corrupt ||
4257 intel_dp->aux.i2c_defer_count > 6) {
4258 /* Check EDID read for NACKs, DEFERs and corruption
4259 * (DP CTS 1.2 Core r1.1)
4260 * 4.2.2.4 : Failed EDID read, I2C_NAK
4261 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4262 * 4.2.2.6 : EDID corruption detected
4263 * Use failsafe mode for all cases
4265 if (intel_dp->aux.i2c_nack_count > 0 ||
4266 intel_dp->aux.i2c_defer_count > 0)
4267 drm_dbg_kms(&i915->drm,
4268 "EDID read had %d NACKs, %d DEFERs\n",
4269 intel_dp->aux.i2c_nack_count,
4270 intel_dp->aux.i2c_defer_count);
4271 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4273 struct edid *block = intel_connector->detect_edid;
4275 /* We have to write the checksum
4276 * of the last block read
4278 block += intel_connector->detect_edid->extensions;
4280 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4281 block->checksum) <= 0)
4282 drm_dbg_kms(&i915->drm,
4283 "Failed to write EDID checksum\n");
4285 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4286 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4289 /* Set test active flag here so userspace doesn't interrupt things */
4290 intel_dp->compliance.test_active = true;
4295 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4296 const struct intel_crtc_state *crtc_state)
4298 struct drm_i915_private *dev_priv =
4299 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4300 struct drm_dp_phy_test_params *data =
4301 &intel_dp->compliance.test_data.phytest;
4302 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4303 enum pipe pipe = crtc->pipe;
4306 switch (data->phy_pattern) {
4307 case DP_PHY_TEST_PATTERN_NONE:
4308 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
4309 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4311 case DP_PHY_TEST_PATTERN_D10_2:
4312 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
4313 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4314 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4316 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
4317 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
4318 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4319 DDI_DP_COMP_CTL_ENABLE |
4320 DDI_DP_COMP_CTL_SCRAMBLED_0);
4322 case DP_PHY_TEST_PATTERN_PRBS7:
4323 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
4324 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4325 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4327 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
4329 * FIXME: Ideally pattern should come from DPCD 0x250. As
4330 * current firmware of DPR-100 could not set it, so hardcoding
4331 * now for complaince test.
4333 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4334 pattern_val = 0x3e0f83e0;
4335 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4336 pattern_val = 0x0f83e0f8;
4337 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4338 pattern_val = 0x0000f83e;
4339 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4340 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4341 DDI_DP_COMP_CTL_ENABLE |
4342 DDI_DP_COMP_CTL_CUSTOM80);
4344 case DP_PHY_TEST_PATTERN_CP2520:
4346 * FIXME: Ideally pattern should come from DPCD 0x24A. As
4347 * current firmware of DPR-100 could not set it, so hardcoding
4348 * now for complaince test.
4350 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
4352 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4353 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4357 WARN(1, "Invalid Phy Test Pattern\n");
4362 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
4363 const struct intel_crtc_state *crtc_state)
4365 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4366 struct drm_device *dev = dig_port->base.base.dev;
4367 struct drm_i915_private *dev_priv = to_i915(dev);
4368 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
4369 enum pipe pipe = crtc->pipe;
4370 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
4372 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
4373 TRANS_DDI_FUNC_CTL(pipe));
4374 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
4375 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
4377 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
4378 TGL_TRANS_DDI_PORT_MASK);
4379 trans_conf_value &= ~PIPECONF_ENABLE;
4380 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
4382 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
4383 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
4384 trans_ddi_func_ctl_value);
4385 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
4389 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
4390 const struct intel_crtc_state *crtc_state)
4392 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4393 struct drm_device *dev = dig_port->base.base.dev;
4394 struct drm_i915_private *dev_priv = to_i915(dev);
4395 enum port port = dig_port->base.port;
4396 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
4397 enum pipe pipe = crtc->pipe;
4398 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
4400 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
4401 TRANS_DDI_FUNC_CTL(pipe));
4402 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
4403 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
4405 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
4406 TGL_TRANS_DDI_SELECT_PORT(port);
4407 trans_conf_value |= PIPECONF_ENABLE;
4408 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
4410 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
4411 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
4412 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
4413 trans_ddi_func_ctl_value);
4416 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4417 const struct intel_crtc_state *crtc_state)
4419 struct drm_dp_phy_test_params *data =
4420 &intel_dp->compliance.test_data.phytest;
4421 u8 link_status[DP_LINK_STATUS_SIZE];
4423 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4425 DRM_DEBUG_KMS("failed to get link status\n");
4429 /* retrieve vswing & pre-emphasis setting */
4430 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4433 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
4435 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4437 intel_dp_phy_pattern_update(intel_dp, crtc_state);
4439 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
4441 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4442 link_status[DP_DPCD_REV]);
4445 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4447 struct drm_dp_phy_test_params *data =
4448 &intel_dp->compliance.test_data.phytest;
4450 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4451 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
4455 /* Set test active flag here so userspace doesn't interrupt things */
4456 intel_dp->compliance.test_active = true;
4461 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4463 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4464 u8 response = DP_TEST_NAK;
4468 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4470 drm_dbg_kms(&i915->drm,
4471 "Could not read test request from sink\n");
4476 case DP_TEST_LINK_TRAINING:
4477 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4478 response = intel_dp_autotest_link_training(intel_dp);
4480 case DP_TEST_LINK_VIDEO_PATTERN:
4481 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4482 response = intel_dp_autotest_video_pattern(intel_dp);
4484 case DP_TEST_LINK_EDID_READ:
4485 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4486 response = intel_dp_autotest_edid(intel_dp);
4488 case DP_TEST_LINK_PHY_TEST_PATTERN:
4489 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4490 response = intel_dp_autotest_phy_pattern(intel_dp);
4493 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4498 if (response & DP_TEST_ACK)
4499 intel_dp->compliance.test_type = request;
4502 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4504 drm_dbg_kms(&i915->drm,
4505 "Could not write test response to sink\n");
4509 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
4511 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
4513 if (esi[1] & DP_CP_IRQ) {
4514 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4520 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4521 * @intel_dp: Intel DP struct
4523 * Read any pending MST interrupts, call MST core to handle these and ack the
4524 * interrupts. Check if the main and AUX link state is ok.
4527 * - %true if pending interrupts were serviced (or no interrupts were
4528 * pending) w/o detecting an error condition.
4529 * - %false if an error condition - like AUX failure or a loss of link - is
4530 * detected, which needs servicing from the hotplug work.
4533 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4535 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4536 bool link_ok = true;
4538 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4541 u8 esi[DP_DPRX_ESI_LEN] = {};
4545 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4546 drm_dbg_kms(&i915->drm,
4547 "failed to get ESI - device may have failed\n");
4553 /* check link status - esi[10] = 0x200c */
4554 if (intel_dp->active_mst_links > 0 && link_ok &&
4555 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4556 drm_dbg_kms(&i915->drm,
4557 "channel EQ not ok, retraining\n");
4561 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
4563 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
4568 for (retry = 0; retry < 3; retry++) {
4571 wret = drm_dp_dpcd_write(&intel_dp->aux,
4572 DP_SINK_COUNT_ESI+1,
4583 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4588 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4589 if (intel_dp->frl.is_trained && !is_active) {
4590 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4593 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
4594 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4597 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4599 /* Restart FRL training or fall back to TMDS mode */
4600 intel_dp_check_frl_training(intel_dp);
4605 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4607 u8 link_status[DP_LINK_STATUS_SIZE];
4609 if (!intel_dp->link_trained)
4613 * While PSR source HW is enabled, it will control main-link sending
4614 * frames, enabling and disabling it so trying to do a retrain will fail
4615 * as the link would or not be on or it could mix training patterns
4616 * and frame data at the same time causing retrain to fail.
4617 * Also when exiting PSR, HW will retrain the link anyways fixing
4618 * any link status error.
4620 if (intel_psr_enabled(intel_dp))
4623 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4628 * Validate the cached values of intel_dp->link_rate and
4629 * intel_dp->lane_count before attempting to retrain.
4631 * FIXME would be nice to user the crtc state here, but since
4632 * we need to call this from the short HPD handler that seems
4635 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4636 intel_dp->lane_count))
4639 /* Retrain if Channel EQ or CR not ok */
4640 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4643 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4644 const struct drm_connector_state *conn_state)
4646 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4647 struct intel_encoder *encoder;
4650 if (!conn_state->best_encoder)
4654 encoder = &dp_to_dig_port(intel_dp)->base;
4655 if (conn_state->best_encoder == &encoder->base)
4659 for_each_pipe(i915, pipe) {
4660 encoder = &intel_dp->mst_encoders[pipe]->base;
4661 if (conn_state->best_encoder == &encoder->base)
4668 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4669 struct drm_modeset_acquire_ctx *ctx,
4672 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4673 struct drm_connector_list_iter conn_iter;
4674 struct intel_connector *connector;
4679 if (!intel_dp_needs_link_retrain(intel_dp))
4682 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4683 for_each_intel_connector_iter(connector, &conn_iter) {
4684 struct drm_connector_state *conn_state =
4685 connector->base.state;
4686 struct intel_crtc_state *crtc_state;
4687 struct intel_crtc *crtc;
4689 if (!intel_dp_has_connector(intel_dp, conn_state))
4692 crtc = to_intel_crtc(conn_state->crtc);
4696 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4700 crtc_state = to_intel_crtc_state(crtc->base.state);
4702 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4704 if (!crtc_state->hw.active)
4707 if (conn_state->commit &&
4708 !try_wait_for_completion(&conn_state->commit->hw_done))
4711 *crtc_mask |= drm_crtc_mask(&crtc->base);
4713 drm_connector_list_iter_end(&conn_iter);
4715 if (!intel_dp_needs_link_retrain(intel_dp))
4721 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4723 struct intel_connector *connector = intel_dp->attached_connector;
4725 return connector->base.status == connector_status_connected ||
4729 int intel_dp_retrain_link(struct intel_encoder *encoder,
4730 struct drm_modeset_acquire_ctx *ctx)
4732 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4733 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4734 struct intel_crtc *crtc;
4738 if (!intel_dp_is_connected(intel_dp))
4741 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4746 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
4753 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4754 encoder->base.base.id, encoder->base.name);
4756 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4757 const struct intel_crtc_state *crtc_state =
4758 to_intel_crtc_state(crtc->base.state);
4760 /* Suppress underruns caused by re-training */
4761 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4762 if (crtc_state->has_pch_encoder)
4763 intel_set_pch_fifo_underrun_reporting(dev_priv,
4764 intel_crtc_pch_transcoder(crtc), false);
4767 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4768 const struct intel_crtc_state *crtc_state =
4769 to_intel_crtc_state(crtc->base.state);
4771 /* retrain on the MST master transcoder */
4772 if (INTEL_GEN(dev_priv) >= 12 &&
4773 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4774 !intel_dp_mst_is_master_trans(crtc_state))
4777 intel_dp_check_frl_training(intel_dp);
4778 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4779 intel_dp_start_link_train(intel_dp, crtc_state);
4780 intel_dp_stop_link_train(intel_dp, crtc_state);
4784 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4785 const struct intel_crtc_state *crtc_state =
4786 to_intel_crtc_state(crtc->base.state);
4788 /* Keep underrun reporting disabled until things are stable */
4789 intel_wait_for_vblank(dev_priv, crtc->pipe);
4791 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4792 if (crtc_state->has_pch_encoder)
4793 intel_set_pch_fifo_underrun_reporting(dev_priv,
4794 intel_crtc_pch_transcoder(crtc), true);
4800 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4801 struct drm_modeset_acquire_ctx *ctx,
4804 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4805 struct drm_connector_list_iter conn_iter;
4806 struct intel_connector *connector;
4811 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4812 for_each_intel_connector_iter(connector, &conn_iter) {
4813 struct drm_connector_state *conn_state =
4814 connector->base.state;
4815 struct intel_crtc_state *crtc_state;
4816 struct intel_crtc *crtc;
4818 if (!intel_dp_has_connector(intel_dp, conn_state))
4821 crtc = to_intel_crtc(conn_state->crtc);
4825 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4829 crtc_state = to_intel_crtc_state(crtc->base.state);
4831 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4833 if (!crtc_state->hw.active)
4836 if (conn_state->commit &&
4837 !try_wait_for_completion(&conn_state->commit->hw_done))
4840 *crtc_mask |= drm_crtc_mask(&crtc->base);
4842 drm_connector_list_iter_end(&conn_iter);
4847 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4848 struct drm_modeset_acquire_ctx *ctx)
4850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4851 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4852 struct intel_crtc *crtc;
4856 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4861 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
4868 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4869 encoder->base.base.id, encoder->base.name);
4871 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
4872 const struct intel_crtc_state *crtc_state =
4873 to_intel_crtc_state(crtc->base.state);
4875 /* test on the MST master transcoder */
4876 if (INTEL_GEN(dev_priv) >= 12 &&
4877 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4878 !intel_dp_mst_is_master_trans(crtc_state))
4881 intel_dp_process_phy_request(intel_dp, crtc_state);
4888 void intel_dp_phy_test(struct intel_encoder *encoder)
4890 struct drm_modeset_acquire_ctx ctx;
4893 drm_modeset_acquire_init(&ctx, 0);
4896 ret = intel_dp_do_phy_test(encoder, &ctx);
4898 if (ret == -EDEADLK) {
4899 drm_modeset_backoff(&ctx);
4906 drm_modeset_drop_locks(&ctx);
4907 drm_modeset_acquire_fini(&ctx);
4908 drm_WARN(encoder->base.dev, ret,
4909 "Acquiring modeset locks failed with %i\n", ret);
4913 * If display is now connected check links status,
4914 * there has been known issues of link loss triggering
4917 * Some sinks (eg. ASUS PB287Q) seem to perform some
4918 * weird HPD ping pong during modesets. So we can apparently
4919 * end up with HPD going low during a modeset, and then
4920 * going back up soon after. And once that happens we must
4921 * retrain the link to get a picture. That's in case no
4922 * userspace component reacted to intermittent HPD dip.
4924 static enum intel_hotplug_state
4925 intel_dp_hotplug(struct intel_encoder *encoder,
4926 struct intel_connector *connector)
4928 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4929 struct drm_modeset_acquire_ctx ctx;
4930 enum intel_hotplug_state state;
4933 if (intel_dp->compliance.test_active &&
4934 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4935 intel_dp_phy_test(encoder);
4936 /* just do the PHY test and nothing else */
4937 return INTEL_HOTPLUG_UNCHANGED;
4940 state = intel_encoder_hotplug(encoder, connector);
4942 drm_modeset_acquire_init(&ctx, 0);
4945 ret = intel_dp_retrain_link(encoder, &ctx);
4947 if (ret == -EDEADLK) {
4948 drm_modeset_backoff(&ctx);
4955 drm_modeset_drop_locks(&ctx);
4956 drm_modeset_acquire_fini(&ctx);
4957 drm_WARN(encoder->base.dev, ret,
4958 "Acquiring modeset locks failed with %i\n", ret);
4961 * Keeping it consistent with intel_ddi_hotplug() and
4962 * intel_hdmi_hotplug().
4964 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
4965 state = INTEL_HOTPLUG_RETRY;
4970 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4972 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4975 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4978 if (drm_dp_dpcd_readb(&intel_dp->aux,
4979 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4982 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4984 if (val & DP_AUTOMATED_TEST_REQUEST)
4985 intel_dp_handle_test_request(intel_dp);
4987 if (val & DP_CP_IRQ)
4988 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4990 if (val & DP_SINK_SPECIFIC_IRQ)
4991 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4994 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4996 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4999 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5002 if (drm_dp_dpcd_readb(&intel_dp->aux,
5003 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
5004 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
5008 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5009 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
5010 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
5014 if (val & HDMI_LINK_STATUS_CHANGED)
5015 intel_dp_handle_hdmi_link_status_change(intel_dp);
5019 * According to DP spec
5022 * 2. Configure link according to Receiver Capabilities
5023 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5024 * 4. Check link status on receipt of hot-plug interrupt
5026 * intel_dp_short_pulse - handles short pulse interrupts
5027 * when full detection is not required.
5028 * Returns %true if short pulse is handled and full detection
5029 * is NOT required and %false otherwise.
5032 intel_dp_short_pulse(struct intel_dp *intel_dp)
5034 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5035 u8 old_sink_count = intel_dp->sink_count;
5039 * Clearing compliance test variables to allow capturing
5040 * of values for next automated test request.
5042 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5045 * Now read the DPCD to see if it's actually running
5046 * If the current value of sink count doesn't match with
5047 * the value that was stored earlier or dpcd read failed
5048 * we need to do full detection
5050 ret = intel_dp_get_dpcd(intel_dp);
5052 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5053 /* No need to proceed if we are going to do full detect */
5057 intel_dp_check_device_service_irq(intel_dp);
5058 intel_dp_check_link_service_irq(intel_dp);
5060 /* Handle CEC interrupts, if any */
5061 drm_dp_cec_irq(&intel_dp->aux);
5063 /* defer to the hotplug work for link retraining if needed */
5064 if (intel_dp_needs_link_retrain(intel_dp))
5067 intel_psr_short_pulse(intel_dp);
5069 switch (intel_dp->compliance.test_type) {
5070 case DP_TEST_LINK_TRAINING:
5071 drm_dbg_kms(&dev_priv->drm,
5072 "Link Training Compliance Test requested\n");
5073 /* Send a Hotplug Uevent to userspace to start modeset */
5074 drm_kms_helper_hotplug_event(&dev_priv->drm);
5076 case DP_TEST_LINK_PHY_TEST_PATTERN:
5077 drm_dbg_kms(&dev_priv->drm,
5078 "PHY test pattern Compliance Test requested\n");
5080 * Schedule long hpd to do the test
5082 * FIXME get rid of the ad-hoc phy test modeset code
5083 * and properly incorporate it into the normal modeset.
5091 /* XXX this is probably wrong for multiple downstream ports */
5092 static enum drm_connector_status
5093 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5095 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5096 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5097 u8 *dpcd = intel_dp->dpcd;
5100 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5101 return connector_status_connected;
5103 lspcon_resume(dig_port);
5105 if (!intel_dp_get_dpcd(intel_dp))
5106 return connector_status_disconnected;
5108 /* if there's no downstream port, we're done */
5109 if (!drm_dp_is_branch(dpcd))
5110 return connector_status_connected;
5112 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5113 if (intel_dp_has_sink_count(intel_dp) &&
5114 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5115 return intel_dp->sink_count ?
5116 connector_status_connected : connector_status_disconnected;
5119 if (intel_dp_can_mst(intel_dp))
5120 return connector_status_connected;
5122 /* If no HPD, poke DDC gently */
5123 if (drm_probe_ddc(&intel_dp->aux.ddc))
5124 return connector_status_connected;
5126 /* Well we tried, say unknown for unreliable port types */
5127 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5128 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5129 if (type == DP_DS_PORT_TYPE_VGA ||
5130 type == DP_DS_PORT_TYPE_NON_EDID)
5131 return connector_status_unknown;
5133 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5134 DP_DWN_STRM_PORT_TYPE_MASK;
5135 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5136 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5137 return connector_status_unknown;
5140 /* Anything else is out of spec, warn and ignore */
5141 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5142 return connector_status_disconnected;
5145 static enum drm_connector_status
5146 edp_detect(struct intel_dp *intel_dp)
5148 return connector_status_connected;
5151 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5154 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
5156 return intel_de_read(dev_priv, SDEISR) & bit;
5159 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5161 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5164 switch (encoder->hpd_pin) {
5166 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5169 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5172 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5175 MISSING_CASE(encoder->hpd_pin);
5179 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5182 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5187 switch (encoder->hpd_pin) {
5189 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5192 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5195 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5198 MISSING_CASE(encoder->hpd_pin);
5202 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5205 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5208 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5210 return intel_de_read(dev_priv, DEISR) & bit;
5214 * intel_digital_port_connected - is the specified port connected?
5215 * @encoder: intel_encoder
5217 * In cases where there's a connector physically connected but it can't be used
5218 * by our hardware we also return false, since the rest of the driver should
5219 * pretty much treat the port as disconnected. This is relevant for type-C
5220 * (starting on ICL) where there's ownership involved.
5222 * Return %true if port is connected, %false otherwise.
5224 bool intel_digital_port_connected(struct intel_encoder *encoder)
5226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5227 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5228 bool is_connected = false;
5229 intel_wakeref_t wakeref;
5231 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5232 is_connected = dig_port->connected(encoder);
5234 return is_connected;
5237 static struct edid *
5238 intel_dp_get_edid(struct intel_dp *intel_dp)
5240 struct intel_connector *intel_connector = intel_dp->attached_connector;
5242 /* use cached edid if we have one */
5243 if (intel_connector->edid) {
5245 if (IS_ERR(intel_connector->edid))
5248 return drm_edid_duplicate(intel_connector->edid);
5250 return drm_get_edid(&intel_connector->base,
5251 &intel_dp->aux.ddc);
5255 intel_dp_update_dfp(struct intel_dp *intel_dp,
5256 const struct edid *edid)
5258 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5259 struct intel_connector *connector = intel_dp->attached_connector;
5261 intel_dp->dfp.max_bpc =
5262 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5263 intel_dp->downstream_ports, edid);
5265 intel_dp->dfp.max_dotclock =
5266 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5267 intel_dp->downstream_ports);
5269 intel_dp->dfp.min_tmds_clock =
5270 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5271 intel_dp->downstream_ports,
5273 intel_dp->dfp.max_tmds_clock =
5274 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5275 intel_dp->downstream_ports,
5278 intel_dp->dfp.pcon_max_frl_bw =
5279 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5280 intel_dp->downstream_ports);
5282 drm_dbg_kms(&i915->drm,
5283 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5284 connector->base.base.id, connector->base.name,
5285 intel_dp->dfp.max_bpc,
5286 intel_dp->dfp.max_dotclock,
5287 intel_dp->dfp.min_tmds_clock,
5288 intel_dp->dfp.max_tmds_clock,
5289 intel_dp->dfp.pcon_max_frl_bw);
5291 intel_dp_get_pcon_dsc_cap(intel_dp);
5295 intel_dp_update_420(struct intel_dp *intel_dp)
5297 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5298 struct intel_connector *connector = intel_dp->attached_connector;
5299 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
5301 /* No YCbCr output support on gmch platforms */
5306 * ILK doesn't seem capable of DP YCbCr output. The
5307 * displayed image is severly corrupted. SNB+ is fine.
5309 if (IS_GEN(i915, 5))
5312 is_branch = drm_dp_is_branch(intel_dp->dpcd);
5313 ycbcr_420_passthrough =
5314 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5315 intel_dp->downstream_ports);
5316 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5318 dp_to_dig_port(intel_dp)->lspcon.active ||
5319 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5320 intel_dp->downstream_ports);
5321 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5322 intel_dp->downstream_ports,
5323 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
5324 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
5325 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
5327 if (INTEL_GEN(i915) >= 11) {
5328 /* Let PCON convert from RGB->YCbCr if possible */
5329 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
5330 intel_dp->dfp.rgb_to_ycbcr = true;
5331 intel_dp->dfp.ycbcr_444_to_420 = true;
5332 connector->base.ycbcr_420_allowed = true;
5334 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
5335 intel_dp->dfp.ycbcr_444_to_420 =
5336 ycbcr_444_to_420 && !ycbcr_420_passthrough;
5338 connector->base.ycbcr_420_allowed =
5339 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
5342 /* 4:4:4->4:2:0 conversion is the only way */
5343 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
5345 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
5348 drm_dbg_kms(&i915->drm,
5349 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5350 connector->base.base.id, connector->base.name,
5351 yesno(intel_dp->dfp.rgb_to_ycbcr),
5352 yesno(connector->base.ycbcr_420_allowed),
5353 yesno(intel_dp->dfp.ycbcr_444_to_420));
5357 intel_dp_set_edid(struct intel_dp *intel_dp)
5359 struct intel_connector *connector = intel_dp->attached_connector;
5362 intel_dp_unset_edid(intel_dp);
5363 edid = intel_dp_get_edid(intel_dp);
5364 connector->detect_edid = edid;
5366 intel_dp_update_dfp(intel_dp, edid);
5367 intel_dp_update_420(intel_dp);
5369 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
5370 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
5371 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5374 drm_dp_cec_set_edid(&intel_dp->aux, edid);
5378 intel_dp_unset_edid(struct intel_dp *intel_dp)
5380 struct intel_connector *connector = intel_dp->attached_connector;
5382 drm_dp_cec_unset_edid(&intel_dp->aux);
5383 kfree(connector->detect_edid);
5384 connector->detect_edid = NULL;
5386 intel_dp->has_hdmi_sink = false;
5387 intel_dp->has_audio = false;
5389 intel_dp->dfp.max_bpc = 0;
5390 intel_dp->dfp.max_dotclock = 0;
5391 intel_dp->dfp.min_tmds_clock = 0;
5392 intel_dp->dfp.max_tmds_clock = 0;
5394 intel_dp->dfp.pcon_max_frl_bw = 0;
5396 intel_dp->dfp.ycbcr_444_to_420 = false;
5397 connector->base.ycbcr_420_allowed = false;
5401 intel_dp_detect(struct drm_connector *connector,
5402 struct drm_modeset_acquire_ctx *ctx,
5405 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5406 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5407 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5408 struct intel_encoder *encoder = &dig_port->base;
5409 enum drm_connector_status status;
5411 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5412 connector->base.id, connector->name);
5413 drm_WARN_ON(&dev_priv->drm,
5414 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5416 if (!INTEL_DISPLAY_ENABLED(dev_priv))
5417 return connector_status_disconnected;
5419 /* Can't disconnect eDP */
5420 if (intel_dp_is_edp(intel_dp))
5421 status = edp_detect(intel_dp);
5422 else if (intel_digital_port_connected(encoder))
5423 status = intel_dp_detect_dpcd(intel_dp);
5425 status = connector_status_disconnected;
5427 if (status == connector_status_disconnected) {
5428 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5429 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5431 if (intel_dp->is_mst) {
5432 drm_dbg_kms(&dev_priv->drm,
5433 "MST device may have disappeared %d vs %d\n",
5435 intel_dp->mst_mgr.mst_state);
5436 intel_dp->is_mst = false;
5437 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5444 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5445 if (INTEL_GEN(dev_priv) >= 11)
5446 intel_dp_get_dsc_sink_cap(intel_dp);
5448 intel_dp_configure_mst(intel_dp);
5451 * TODO: Reset link params when switching to MST mode, until MST
5452 * supports link training fallback params.
5454 if (intel_dp->reset_link_params || intel_dp->is_mst) {
5455 /* Initial max link lane count */
5456 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5458 /* Initial max link rate */
5459 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5461 intel_dp->reset_link_params = false;
5464 intel_dp_print_rates(intel_dp);
5466 if (intel_dp->is_mst) {
5468 * If we are in MST mode then this connector
5469 * won't appear connected or have anything
5472 status = connector_status_disconnected;
5477 * Some external monitors do not signal loss of link synchronization
5478 * with an IRQ_HPD, so force a link status check.
5480 if (!intel_dp_is_edp(intel_dp)) {
5483 ret = intel_dp_retrain_link(encoder, ctx);
5489 * Clearing NACK and defer counts to get their exact values
5490 * while reading EDID which are required by Compliance tests
5491 * 4.2.2.4 and 4.2.2.5
5493 intel_dp->aux.i2c_nack_count = 0;
5494 intel_dp->aux.i2c_defer_count = 0;
5496 intel_dp_set_edid(intel_dp);
5497 if (intel_dp_is_edp(intel_dp) ||
5498 to_intel_connector(connector)->detect_edid)
5499 status = connector_status_connected;
5501 intel_dp_check_device_service_irq(intel_dp);
5504 if (status != connector_status_connected && !intel_dp->is_mst)
5505 intel_dp_unset_edid(intel_dp);
5508 * Make sure the refs for power wells enabled during detect are
5509 * dropped to avoid a new detect cycle triggered by HPD polling.
5511 intel_display_power_flush_work(dev_priv);
5513 if (!intel_dp_is_edp(intel_dp))
5514 drm_dp_set_subconnector_property(connector,
5517 intel_dp->downstream_ports);
5522 intel_dp_force(struct drm_connector *connector)
5524 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5525 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5526 struct intel_encoder *intel_encoder = &dig_port->base;
5527 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5528 enum intel_display_power_domain aux_domain =
5529 intel_aux_power_domain(dig_port);
5530 intel_wakeref_t wakeref;
5532 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5533 connector->base.id, connector->name);
5534 intel_dp_unset_edid(intel_dp);
5536 if (connector->status != connector_status_connected)
5539 wakeref = intel_display_power_get(dev_priv, aux_domain);
5541 intel_dp_set_edid(intel_dp);
5543 intel_display_power_put(dev_priv, aux_domain, wakeref);
5546 static int intel_dp_get_modes(struct drm_connector *connector)
5548 struct intel_connector *intel_connector = to_intel_connector(connector);
5551 edid = intel_connector->detect_edid;
5553 int ret = intel_connector_update_modes(connector, edid);
5555 if (intel_vrr_is_capable(connector))
5556 drm_connector_set_vrr_capable_property(connector,
5562 /* if eDP has no EDID, fall back to fixed mode */
5563 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
5564 intel_connector->panel.fixed_mode) {
5565 struct drm_display_mode *mode;
5567 mode = drm_mode_duplicate(connector->dev,
5568 intel_connector->panel.fixed_mode);
5570 drm_mode_probed_add(connector, mode);
5576 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5577 struct drm_display_mode *mode;
5579 mode = drm_dp_downstream_mode(connector->dev,
5581 intel_dp->downstream_ports);
5583 drm_mode_probed_add(connector, mode);
5592 intel_dp_connector_register(struct drm_connector *connector)
5594 struct drm_i915_private *i915 = to_i915(connector->dev);
5595 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5596 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5597 struct intel_lspcon *lspcon = &dig_port->lspcon;
5600 ret = intel_connector_register(connector);
5604 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5605 intel_dp->aux.name, connector->kdev->kobj.name);
5607 intel_dp->aux.dev = connector->kdev;
5608 ret = drm_dp_aux_register(&intel_dp->aux);
5610 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5612 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
5616 * ToDo: Clean this up to handle lspcon init and resume more
5617 * efficiently and streamlined.
5619 if (lspcon_init(dig_port)) {
5620 lspcon_detect_hdr_capability(lspcon);
5621 if (lspcon->hdr_supported)
5622 drm_object_attach_property(&connector->base,
5623 connector->dev->mode_config.hdr_output_metadata_property,
5631 intel_dp_connector_unregister(struct drm_connector *connector)
5633 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5635 drm_dp_cec_unregister_connector(&intel_dp->aux);
5636 drm_dp_aux_unregister(&intel_dp->aux);
5637 intel_connector_unregister(connector);
5640 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5642 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5643 struct intel_dp *intel_dp = &dig_port->dp;
5645 intel_dp_mst_encoder_cleanup(dig_port);
5647 intel_pps_vdd_off_sync(intel_dp);
5649 intel_dp_aux_fini(intel_dp);
5652 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5654 intel_dp_encoder_flush_work(encoder);
5656 drm_encoder_cleanup(encoder);
5657 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
5660 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5662 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5664 intel_pps_vdd_off_sync(intel_dp);
5667 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5669 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5671 intel_pps_wait_power_cycle(intel_dp);
5674 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5676 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5677 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5680 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5681 encoder->port, &pipe))
5684 return INVALID_PIPE;
5687 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5689 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5690 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
5692 if (!HAS_DDI(dev_priv))
5693 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5695 intel_dp->reset_link_params = true;
5697 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5698 intel_wakeref_t wakeref;
5700 with_intel_pps_lock(intel_dp, wakeref)
5701 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5704 intel_pps_encoder_reset(intel_dp);
5707 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5710 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5711 struct drm_connector_list_iter conn_iter;
5712 struct drm_connector *connector;
5715 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5716 drm_for_each_connector_iter(connector, &conn_iter) {
5717 struct drm_connector_state *conn_state;
5718 struct intel_crtc_state *crtc_state;
5719 struct intel_crtc *crtc;
5721 if (!connector->has_tile ||
5722 connector->tile_group->id != tile_group_id)
5725 conn_state = drm_atomic_get_connector_state(&state->base,
5727 if (IS_ERR(conn_state)) {
5728 ret = PTR_ERR(conn_state);
5732 crtc = to_intel_crtc(conn_state->crtc);
5737 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5738 crtc_state->uapi.mode_changed = true;
5740 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5744 drm_connector_list_iter_end(&conn_iter);
5749 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5751 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5752 struct intel_crtc *crtc;
5754 if (transcoders == 0)
5757 for_each_intel_crtc(&dev_priv->drm, crtc) {
5758 struct intel_crtc_state *crtc_state;
5761 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5762 if (IS_ERR(crtc_state))
5763 return PTR_ERR(crtc_state);
5765 if (!crtc_state->hw.enable)
5768 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5771 crtc_state->uapi.mode_changed = true;
5773 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5777 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5781 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5784 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5789 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5790 struct drm_connector *connector)
5792 const struct drm_connector_state *old_conn_state =
5793 drm_atomic_get_old_connector_state(&state->base, connector);
5794 const struct intel_crtc_state *old_crtc_state;
5795 struct intel_crtc *crtc;
5798 crtc = to_intel_crtc(old_conn_state->crtc);
5802 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5804 if (!old_crtc_state->hw.active)
5807 transcoders = old_crtc_state->sync_mode_slaves_mask;
5808 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5809 transcoders |= BIT(old_crtc_state->master_transcoder);
5811 return intel_modeset_affected_transcoders(state,
5815 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5816 struct drm_atomic_state *_state)
5818 struct drm_i915_private *dev_priv = to_i915(conn->dev);
5819 struct intel_atomic_state *state = to_intel_atomic_state(_state);
5822 ret = intel_digital_connector_atomic_check(conn, &state->base);
5827 * We don't enable port sync on BDW due to missing w/as and
5828 * due to not having adjusted the modeset sequence appropriately.
5830 if (INTEL_GEN(dev_priv) < 9)
5833 if (!intel_connector_needs_modeset(state, conn))
5836 if (conn->has_tile) {
5837 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5842 return intel_modeset_synced_crtcs(state, conn);
5845 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5846 .force = intel_dp_force,
5847 .fill_modes = drm_helper_probe_single_connector_modes,
5848 .atomic_get_property = intel_digital_connector_atomic_get_property,
5849 .atomic_set_property = intel_digital_connector_atomic_set_property,
5850 .late_register = intel_dp_connector_register,
5851 .early_unregister = intel_dp_connector_unregister,
5852 .destroy = intel_connector_destroy,
5853 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5854 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5857 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5858 .detect_ctx = intel_dp_detect,
5859 .get_modes = intel_dp_get_modes,
5860 .mode_valid = intel_dp_mode_valid,
5861 .atomic_check = intel_dp_connector_atomic_check,
5864 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5865 .reset = intel_dp_encoder_reset,
5866 .destroy = intel_dp_encoder_destroy,
5870 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5872 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5873 struct intel_dp *intel_dp = &dig_port->dp;
5875 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5876 (long_hpd || !intel_pps_have_power(intel_dp))) {
5878 * vdd off can generate a long/short pulse on eDP which
5879 * would require vdd on to handle it, and thus we
5880 * would end up in an endless cycle of
5881 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5883 drm_dbg_kms(&i915->drm,
5884 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5885 long_hpd ? "long" : "short",
5886 dig_port->base.base.base.id,
5887 dig_port->base.base.name);
5891 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5892 dig_port->base.base.base.id,
5893 dig_port->base.base.name,
5894 long_hpd ? "long" : "short");
5897 intel_dp->reset_link_params = true;
5901 if (intel_dp->is_mst) {
5902 if (!intel_dp_check_mst_status(intel_dp))
5904 } else if (!intel_dp_short_pulse(intel_dp)) {
5911 /* check the VBT to see whether the eDP is on another port */
5912 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5915 * eDP not supported on g4x. so bail out early just
5916 * for a bit extra safety in case the VBT is bonkers.
5918 if (INTEL_GEN(dev_priv) < 5)
5921 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5924 return intel_bios_is_port_edp(dev_priv, port);
5928 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5930 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5931 enum port port = dp_to_dig_port(intel_dp)->base.port;
5933 if (!intel_dp_is_edp(intel_dp))
5934 drm_connector_attach_dp_subconnector_property(connector);
5936 if (!IS_G4X(dev_priv) && port != PORT_A)
5937 intel_attach_force_audio_property(connector);
5939 intel_attach_broadcast_rgb_property(connector);
5940 if (HAS_GMCH(dev_priv))
5941 drm_connector_attach_max_bpc_property(connector, 6, 10);
5942 else if (INTEL_GEN(dev_priv) >= 5)
5943 drm_connector_attach_max_bpc_property(connector, 6, 12);
5945 /* Register HDMI colorspace for case of lspcon */
5946 if (intel_bios_is_lspcon_present(dev_priv, port)) {
5947 drm_connector_attach_content_type_property(connector);
5948 intel_attach_hdmi_colorspace_property(connector);
5950 intel_attach_dp_colorspace_property(connector);
5953 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
5954 drm_object_attach_property(&connector->base,
5955 connector->dev->mode_config.hdr_output_metadata_property,
5958 if (intel_dp_is_edp(intel_dp)) {
5959 u32 allowed_scalers;
5961 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5962 if (!HAS_GMCH(dev_priv))
5963 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5965 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5967 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5971 if (HAS_VRR(dev_priv))
5972 drm_connector_attach_vrr_capable_property(connector);
5976 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5977 * @dev_priv: i915 device
5978 * @crtc_state: a pointer to the active intel_crtc_state
5979 * @refresh_rate: RR to be programmed
5981 * This function gets called when refresh rate (RR) has to be changed from
5982 * one frequency to another. Switches can be between high and low RR
5983 * supported by the panel or to any other RR based on media playback (in
5984 * this case, RR value needs to be passed from user space).
5986 * The caller of this function needs to take a lock on dev_priv->drrs.
5988 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5989 const struct intel_crtc_state *crtc_state,
5992 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5994 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5996 if (refresh_rate <= 0) {
5997 drm_dbg_kms(&dev_priv->drm,
5998 "Refresh rate should be positive non-zero.\n");
6002 if (intel_dp == NULL) {
6003 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
6008 drm_dbg_kms(&dev_priv->drm,
6009 "DRRS: intel_crtc not initialized\n");
6013 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6014 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
6018 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
6020 index = DRRS_LOW_RR;
6022 if (index == dev_priv->drrs.refresh_rate_type) {
6023 drm_dbg_kms(&dev_priv->drm,
6024 "DRRS requested for previously set RR...ignoring\n");
6028 if (!crtc_state->hw.active) {
6029 drm_dbg_kms(&dev_priv->drm,
6030 "eDP encoder disabled. CRTC not Active\n");
6034 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6037 intel_dp_set_m_n(crtc_state, M1_N1);
6040 intel_dp_set_m_n(crtc_state, M2_N2);
6044 drm_err(&dev_priv->drm,
6045 "Unsupported refreshrate type\n");
6047 } else if (INTEL_GEN(dev_priv) > 6) {
6048 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6051 val = intel_de_read(dev_priv, reg);
6052 if (index > DRRS_HIGH_RR) {
6053 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6054 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6056 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6058 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6059 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6061 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6063 intel_de_write(dev_priv, reg, val);
6066 dev_priv->drrs.refresh_rate_type = index;
6068 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
6073 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
6075 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6077 dev_priv->drrs.busy_frontbuffer_bits = 0;
6078 dev_priv->drrs.dp = intel_dp;
6082 * intel_edp_drrs_enable - init drrs struct if supported
6083 * @intel_dp: DP struct
6084 * @crtc_state: A pointer to the active crtc state.
6086 * Initializes frontbuffer_bits and drrs.dp
6088 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6089 const struct intel_crtc_state *crtc_state)
6091 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6093 if (!crtc_state->has_drrs)
6096 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
6098 mutex_lock(&dev_priv->drrs.mutex);
6100 if (dev_priv->drrs.dp) {
6101 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
6105 intel_edp_drrs_enable_locked(intel_dp);
6108 mutex_unlock(&dev_priv->drrs.mutex);
6112 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
6113 const struct intel_crtc_state *crtc_state)
6115 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6117 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
6120 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
6121 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
6124 dev_priv->drrs.dp = NULL;
6128 * intel_edp_drrs_disable - Disable DRRS
6129 * @intel_dp: DP struct
6130 * @old_crtc_state: Pointer to old crtc_state.
6133 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6134 const struct intel_crtc_state *old_crtc_state)
6136 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6138 if (!old_crtc_state->has_drrs)
6141 mutex_lock(&dev_priv->drrs.mutex);
6142 if (!dev_priv->drrs.dp) {
6143 mutex_unlock(&dev_priv->drrs.mutex);
6147 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
6148 mutex_unlock(&dev_priv->drrs.mutex);
6150 cancel_delayed_work_sync(&dev_priv->drrs.work);
6154 * intel_edp_drrs_update - Update DRRS state
6155 * @intel_dp: Intel DP
6156 * @crtc_state: new CRTC state
6158 * This function will update DRRS states, disabling or enabling DRRS when
6159 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
6160 * intel_edp_drrs_enable() should be called instead.
6163 intel_edp_drrs_update(struct intel_dp *intel_dp,
6164 const struct intel_crtc_state *crtc_state)
6166 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6168 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
6171 mutex_lock(&dev_priv->drrs.mutex);
6173 /* New state matches current one? */
6174 if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
6177 if (crtc_state->has_drrs)
6178 intel_edp_drrs_enable_locked(intel_dp);
6180 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
6183 mutex_unlock(&dev_priv->drrs.mutex);
6186 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6188 struct drm_i915_private *dev_priv =
6189 container_of(work, typeof(*dev_priv), drrs.work.work);
6190 struct intel_dp *intel_dp;
6192 mutex_lock(&dev_priv->drrs.mutex);
6194 intel_dp = dev_priv->drrs.dp;
6200 * The delayed work can race with an invalidate hence we need to
6204 if (dev_priv->drrs.busy_frontbuffer_bits)
6207 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6208 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6210 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6211 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
6215 mutex_unlock(&dev_priv->drrs.mutex);
6219 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6220 * @dev_priv: i915 device
6221 * @frontbuffer_bits: frontbuffer plane tracking bits
6223 * This function gets called everytime rendering on the given planes start.
6224 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6226 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6228 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6229 unsigned int frontbuffer_bits)
6231 struct intel_dp *intel_dp;
6232 struct drm_crtc *crtc;
6235 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6238 cancel_delayed_work(&dev_priv->drrs.work);
6240 mutex_lock(&dev_priv->drrs.mutex);
6242 intel_dp = dev_priv->drrs.dp;
6244 mutex_unlock(&dev_priv->drrs.mutex);
6248 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6249 pipe = to_intel_crtc(crtc)->pipe;
6251 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6252 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6254 /* invalidate means busy screen hence upclock */
6255 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6256 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6257 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
6259 mutex_unlock(&dev_priv->drrs.mutex);
6263 * intel_edp_drrs_flush - Restart Idleness DRRS
6264 * @dev_priv: i915 device
6265 * @frontbuffer_bits: frontbuffer plane tracking bits
6267 * This function gets called every time rendering on the given planes has
6268 * completed or flip on a crtc is completed. So DRRS should be upclocked
6269 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6270 * if no other planes are dirty.
6272 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6274 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6275 unsigned int frontbuffer_bits)
6277 struct intel_dp *intel_dp;
6278 struct drm_crtc *crtc;
6281 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6284 cancel_delayed_work(&dev_priv->drrs.work);
6286 mutex_lock(&dev_priv->drrs.mutex);
6288 intel_dp = dev_priv->drrs.dp;
6290 mutex_unlock(&dev_priv->drrs.mutex);
6294 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6295 pipe = to_intel_crtc(crtc)->pipe;
6297 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6298 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6300 /* flush means busy screen hence upclock */
6301 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6302 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6303 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
6306 * flush also means no more activity hence schedule downclock, if all
6307 * other fbs are quiescent too
6309 if (!dev_priv->drrs.busy_frontbuffer_bits)
6310 schedule_delayed_work(&dev_priv->drrs.work,
6311 msecs_to_jiffies(1000));
6312 mutex_unlock(&dev_priv->drrs.mutex);
6316 * DOC: Display Refresh Rate Switching (DRRS)
6318 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6319 * which enables swtching between low and high refresh rates,
6320 * dynamically, based on the usage scenario. This feature is applicable
6321 * for internal panels.
6323 * Indication that the panel supports DRRS is given by the panel EDID, which
6324 * would list multiple refresh rates for one resolution.
6326 * DRRS is of 2 types - static and seamless.
6327 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6328 * (may appear as a blink on screen) and is used in dock-undock scenario.
6329 * Seamless DRRS involves changing RR without any visual effect to the user
6330 * and can be used during normal system usage. This is done by programming
6331 * certain registers.
6333 * Support for static/seamless DRRS may be indicated in the VBT based on
6334 * inputs from the panel spec.
6336 * DRRS saves power by switching to low RR based on usage scenarios.
6338 * The implementation is based on frontbuffer tracking implementation. When
6339 * there is a disturbance on the screen triggered by user activity or a periodic
6340 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6341 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6344 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6345 * and intel_edp_drrs_flush() are called.
6347 * DRRS can be further extended to support other internal panels and also
6348 * the scenario of video playback wherein RR is set based on the rate
6349 * requested by userspace.
6353 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6354 * @connector: eDP connector
6355 * @fixed_mode: preferred mode of panel
6357 * This function is called only once at driver load to initialize basic
6361 * Downclock mode if panel supports it, else return NULL.
6362 * DRRS support is determined by the presence of downclock mode (apart
6363 * from VBT setting).
6365 static struct drm_display_mode *
6366 intel_dp_drrs_init(struct intel_connector *connector,
6367 struct drm_display_mode *fixed_mode)
6369 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6370 struct drm_display_mode *downclock_mode = NULL;
6372 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6373 mutex_init(&dev_priv->drrs.mutex);
6375 if (INTEL_GEN(dev_priv) <= 6) {
6376 drm_dbg_kms(&dev_priv->drm,
6377 "DRRS supported for Gen7 and above\n");
6381 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6382 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
6386 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
6387 if (!downclock_mode) {
6388 drm_dbg_kms(&dev_priv->drm,
6389 "Downclock mode is not found. DRRS not supported\n");
6393 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6395 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6396 drm_dbg_kms(&dev_priv->drm,
6397 "seamless DRRS supported for eDP panel.\n");
6398 return downclock_mode;
6401 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6402 struct intel_connector *intel_connector)
6404 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6405 struct drm_device *dev = &dev_priv->drm;
6406 struct drm_connector *connector = &intel_connector->base;
6407 struct drm_display_mode *fixed_mode = NULL;
6408 struct drm_display_mode *downclock_mode = NULL;
6410 enum pipe pipe = INVALID_PIPE;
6413 if (!intel_dp_is_edp(intel_dp))
6417 * On IBX/CPT we may get here with LVDS already registered. Since the
6418 * driver uses the only internal power sequencer available for both
6419 * eDP and LVDS bail out early in this case to prevent interfering
6420 * with an already powered-on LVDS power sequencer.
6422 if (intel_get_lvds_encoder(dev_priv)) {
6424 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6425 drm_info(&dev_priv->drm,
6426 "LVDS was detected, not registering eDP\n");
6431 intel_pps_init(intel_dp);
6433 /* Cache DPCD and EDID for edp. */
6434 has_dpcd = intel_edp_init_dpcd(intel_dp);
6437 /* if this fails, presume the device is a ghost */
6438 drm_info(&dev_priv->drm,
6439 "failed to retrieve link info, disabling eDP\n");
6443 mutex_lock(&dev->mode_config.mutex);
6444 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6446 if (drm_add_edid_modes(connector, edid)) {
6447 drm_connector_update_edid_property(connector, edid);
6450 edid = ERR_PTR(-EINVAL);
6453 edid = ERR_PTR(-ENOENT);
6455 intel_connector->edid = edid;
6457 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
6459 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
6461 /* fallback to VBT if available for eDP */
6463 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
6464 mutex_unlock(&dev->mode_config.mutex);
6466 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6468 * Figure out the current pipe for the initial backlight setup.
6469 * If the current pipe isn't valid, try the PPS pipe, and if that
6470 * fails just assume pipe A.
6472 pipe = vlv_active_pipe(intel_dp);
6474 if (pipe != PIPE_A && pipe != PIPE_B)
6475 pipe = intel_dp->pps.pps_pipe;
6477 if (pipe != PIPE_A && pipe != PIPE_B)
6480 drm_dbg_kms(&dev_priv->drm,
6481 "using pipe %c for initial backlight setup\n",
6485 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6486 intel_connector->panel.backlight.power = intel_pps_backlight_power;
6487 intel_panel_setup_backlight(connector, pipe);
6490 drm_connector_set_panel_orientation_with_quirk(connector,
6491 dev_priv->vbt.orientation,
6492 fixed_mode->hdisplay, fixed_mode->vdisplay);
6498 intel_pps_vdd_off_sync(intel_dp);
6503 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6505 struct intel_connector *intel_connector;
6506 struct drm_connector *connector;
6508 intel_connector = container_of(work, typeof(*intel_connector),
6509 modeset_retry_work);
6510 connector = &intel_connector->base;
6511 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6514 /* Grab the locks before changing connector property*/
6515 mutex_lock(&connector->dev->mode_config.mutex);
6516 /* Set connector link status to BAD and send a Uevent to notify
6517 * userspace to do a modeset.
6519 drm_connector_set_link_status_property(connector,
6520 DRM_MODE_LINK_STATUS_BAD);
6521 mutex_unlock(&connector->dev->mode_config.mutex);
6522 /* Send Hotplug uevent so userspace can reprobe */
6523 drm_kms_helper_hotplug_event(connector->dev);
6527 intel_dp_init_connector(struct intel_digital_port *dig_port,
6528 struct intel_connector *intel_connector)
6530 struct drm_connector *connector = &intel_connector->base;
6531 struct intel_dp *intel_dp = &dig_port->dp;
6532 struct intel_encoder *intel_encoder = &dig_port->base;
6533 struct drm_device *dev = intel_encoder->base.dev;
6534 struct drm_i915_private *dev_priv = to_i915(dev);
6535 enum port port = intel_encoder->port;
6536 enum phy phy = intel_port_to_phy(dev_priv, port);
6539 /* Initialize the work for modeset in case of link train failure */
6540 INIT_WORK(&intel_connector->modeset_retry_work,
6541 intel_dp_modeset_retry_work_fn);
6543 if (drm_WARN(dev, dig_port->max_lanes < 1,
6544 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6545 dig_port->max_lanes, intel_encoder->base.base.id,
6546 intel_encoder->base.name))
6549 intel_dp_set_source_rates(intel_dp);
6551 intel_dp->reset_link_params = true;
6552 intel_dp->pps.pps_pipe = INVALID_PIPE;
6553 intel_dp->pps.active_pipe = INVALID_PIPE;
6555 /* Preserve the current hw state. */
6556 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6557 intel_dp->attached_connector = intel_connector;
6559 if (intel_dp_is_port_edp(dev_priv, port)) {
6561 * Currently we don't support eDP on TypeC ports, although in
6562 * theory it could work on TypeC legacy ports.
6564 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6565 type = DRM_MODE_CONNECTOR_eDP;
6567 type = DRM_MODE_CONNECTOR_DisplayPort;
6570 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6571 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6574 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6575 * for DP the encoder type can be set by the caller to
6576 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6578 if (type == DRM_MODE_CONNECTOR_eDP)
6579 intel_encoder->type = INTEL_OUTPUT_EDP;
6581 /* eDP only on port B and/or C on vlv/chv */
6582 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6583 IS_CHERRYVIEW(dev_priv)) &&
6584 intel_dp_is_edp(intel_dp) &&
6585 port != PORT_B && port != PORT_C))
6588 drm_dbg_kms(&dev_priv->drm,
6589 "Adding %s connector on [ENCODER:%d:%s]\n",
6590 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6591 intel_encoder->base.base.id, intel_encoder->base.name);
6593 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6594 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6596 if (!HAS_GMCH(dev_priv))
6597 connector->interlace_allowed = true;
6598 connector->doublescan_allowed = 0;
6600 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6602 intel_dp_aux_init(intel_dp);
6604 intel_connector_attach_encoder(intel_connector, intel_encoder);
6606 if (HAS_DDI(dev_priv))
6607 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6609 intel_connector->get_hw_state = intel_connector_get_hw_state;
6611 /* init MST on ports that can support it */
6612 intel_dp_mst_encoder_init(dig_port,
6613 intel_connector->base.base.id);
6615 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6616 intel_dp_aux_fini(intel_dp);
6617 intel_dp_mst_encoder_cleanup(dig_port);
6621 intel_dp_add_properties(intel_dp, connector);
6623 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6624 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
6626 drm_dbg_kms(&dev_priv->drm,
6627 "HDCP init failed, skipping.\n");
6630 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6631 * 0xd. Failure to do so will result in spurious interrupts being
6632 * generated on the port when a cable is not attached.
6634 if (IS_G45(dev_priv)) {
6635 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
6636 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
6637 (temp & ~0xf) | 0xd);
6640 intel_dp->frl.is_trained = false;
6641 intel_dp->frl.trained_rate_gbps = 0;
6643 intel_psr_init(intel_dp);
6648 drm_connector_cleanup(connector);
6653 bool intel_dp_init(struct drm_i915_private *dev_priv,
6654 i915_reg_t output_reg,
6657 struct intel_digital_port *dig_port;
6658 struct intel_encoder *intel_encoder;
6659 struct drm_encoder *encoder;
6660 struct intel_connector *intel_connector;
6662 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
6666 intel_connector = intel_connector_alloc();
6667 if (!intel_connector)
6668 goto err_connector_alloc;
6670 intel_encoder = &dig_port->base;
6671 encoder = &intel_encoder->base;
6673 mutex_init(&dig_port->hdcp_mutex);
6675 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6676 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6677 "DP %c", port_name(port)))
6678 goto err_encoder_init;
6680 intel_encoder->hotplug = intel_dp_hotplug;
6681 intel_encoder->compute_config = intel_dp_compute_config;
6682 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6683 intel_encoder->get_config = intel_dp_get_config;
6684 intel_encoder->sync_state = intel_dp_sync_state;
6685 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
6686 intel_encoder->update_pipe = intel_panel_update_backlight;
6687 intel_encoder->suspend = intel_dp_encoder_suspend;
6688 intel_encoder->shutdown = intel_dp_encoder_shutdown;
6689 if (IS_CHERRYVIEW(dev_priv)) {
6690 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6691 intel_encoder->pre_enable = chv_pre_enable_dp;
6692 intel_encoder->enable = vlv_enable_dp;
6693 intel_encoder->disable = vlv_disable_dp;
6694 intel_encoder->post_disable = chv_post_disable_dp;
6695 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6696 } else if (IS_VALLEYVIEW(dev_priv)) {
6697 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6698 intel_encoder->pre_enable = vlv_pre_enable_dp;
6699 intel_encoder->enable = vlv_enable_dp;
6700 intel_encoder->disable = vlv_disable_dp;
6701 intel_encoder->post_disable = vlv_post_disable_dp;
6703 intel_encoder->pre_enable = g4x_pre_enable_dp;
6704 intel_encoder->enable = g4x_enable_dp;
6705 intel_encoder->disable = g4x_disable_dp;
6706 intel_encoder->post_disable = g4x_post_disable_dp;
6709 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
6710 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
6711 dig_port->dp.set_link_train = cpt_set_link_train;
6713 dig_port->dp.set_link_train = g4x_set_link_train;
6715 if (IS_CHERRYVIEW(dev_priv))
6716 dig_port->dp.set_signal_levels = chv_set_signal_levels;
6717 else if (IS_VALLEYVIEW(dev_priv))
6718 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
6719 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
6720 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
6721 else if (IS_GEN(dev_priv, 6) && port == PORT_A)
6722 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
6724 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
6726 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
6727 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
6728 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
6729 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
6731 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
6732 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
6735 dig_port->dp.output_reg = output_reg;
6736 dig_port->max_lanes = 4;
6738 intel_encoder->type = INTEL_OUTPUT_DP;
6739 intel_encoder->power_domain = intel_port_to_power_domain(port);
6740 if (IS_CHERRYVIEW(dev_priv)) {
6742 intel_encoder->pipe_mask = BIT(PIPE_C);
6744 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
6746 intel_encoder->pipe_mask = ~0;
6748 intel_encoder->cloneable = 0;
6749 intel_encoder->port = port;
6750 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6752 dig_port->hpd_pulse = intel_dp_hpd_pulse;
6754 if (HAS_GMCH(dev_priv)) {
6755 if (IS_GM45(dev_priv))
6756 dig_port->connected = gm45_digital_port_connected;
6758 dig_port->connected = g4x_digital_port_connected;
6761 dig_port->connected = ilk_digital_port_connected;
6763 dig_port->connected = ibx_digital_port_connected;
6767 intel_infoframe_init(dig_port);
6769 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
6770 if (!intel_dp_init_connector(dig_port, intel_connector))
6771 goto err_init_connector;
6776 drm_encoder_cleanup(encoder);
6778 kfree(intel_connector);
6779 err_connector_alloc:
6784 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6786 struct intel_encoder *encoder;
6788 for_each_intel_encoder(&dev_priv->drm, encoder) {
6789 struct intel_dp *intel_dp;
6791 if (encoder->type != INTEL_OUTPUT_DDI)
6794 intel_dp = enc_to_intel_dp(encoder);
6796 if (!intel_dp->can_mst)
6799 if (intel_dp->is_mst)
6800 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6804 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6806 struct intel_encoder *encoder;
6808 for_each_intel_encoder(&dev_priv->drm, encoder) {
6809 struct intel_dp *intel_dp;
6812 if (encoder->type != INTEL_OUTPUT_DDI)
6815 intel_dp = enc_to_intel_dp(encoder);
6817 if (!intel_dp->can_mst)
6820 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6823 intel_dp->is_mst = false;
6824 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,