drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_fifo_underrun.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdmi.h"
  57 #include "intel_hotplug.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_lvds.h"
  60 #include "intel_panel.h"
  61 #include "intel_psr.h"
  62 #include "intel_sideband.h"
  63 #include "intel_tc.h"
  64 #include "intel_vdsc.h"
  65
  66 #define DP_DPRX_ESI_LEN 14
  67
  68 /* DP DSC throughput values used for slice count calculations KPixels/s */
  69 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  70 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  71 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  72
  73 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  74 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  75
  76 /* Compliance test status bits  */
  77 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  78 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  79 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  80 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81
  82 struct dp_link_dpll {
  83         int clock;
  84         struct dpll dpll;
  85 };
  86
  87 static const struct dp_link_dpll g4x_dpll[] = {
  88         { 162000,
  89                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  90         { 270000,
  91                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  92 };
  93
  94 static const struct dp_link_dpll pch_dpll[] = {
  95         { 162000,
  96                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  97         { 270000,
  98                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  99 };
 100
 101 static const struct dp_link_dpll vlv_dpll[] = {
 102         { 162000,
 103                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 104         { 270000,
 105                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 106 };
 107
 108 /*
 109  * CHV supports eDP 1.4 that have  more link rates.
 110  * Below only provides the fixed rate but exclude variable rate.
 111  */
 112 static const struct dp_link_dpll chv_dpll[] = {
 113         /*
 114          * CHV requires to program fractional division for m2.
 115          * m2 is stored in fixed point format using formula below
 116          * (m2_int << 22) | m2_fraction
 117          */
 118         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 119                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 120         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 121                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 122 };
 123
 124 /* Constants for DP DSC configurations */
 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 126
 127 /* With Single pipe configuration, HW is capable of supporting maximum
 128  * of 4 slices per line.
 129  */
 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 131
 132 /**
 133  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 134  * @intel_dp: DP struct
 135  *
 136  * If a CPU or PCH DP output is attached to an eDP panel, this function
 137  * will return true, and false otherwise.
 138  */
 139 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 140 {
 141         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 142
 143         return dig_port->base.type == INTEL_OUTPUT_EDP;
 144 }
 145
 146 static void intel_dp_link_down(struct intel_encoder *encoder,
 147                                const struct intel_crtc_state *old_crtc_state);
 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 151                                            const struct intel_crtc_state *crtc_state);
 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 153                                       enum pipe pipe);
 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 155
 156 /* update sink rates from dpcd */
 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 158 {
 159         static const int dp_rates[] = {
 160                 162000, 270000, 540000, 810000
 161         };
 162         int i, max_rate;
 163         int max_lttpr_rate;
 164
 165         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 166                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 167                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 168                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 169
 170                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 171                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 172
 173                 return;
 174         }
 175
 176         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 177         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 178         if (max_lttpr_rate)
 179                 max_rate = min(max_rate, max_lttpr_rate);
 180
 181         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 182                 if (dp_rates[i] > max_rate)
 183                         break;
 184                 intel_dp->sink_rates[i] = dp_rates[i];
 185         }
 186
 187         intel_dp->num_sink_rates = i;
 188 }
 189
 190 /* Get length of rates array potentially limited by max_rate. */
 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 192 {
 193         int i;
 194
 195         /* Limit results by potentially reduced max rate */
 196         for (i = 0; i < len; i++) {
 197                 if (rates[len - i - 1] <= max_rate)
 198                         return len - i;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /* Get length of common rates array potentially limited by max_rate. */
 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 206                                           int max_rate)
 207 {
 208         return intel_dp_rate_limit_len(intel_dp->common_rates,
 209                                        intel_dp->num_common_rates, max_rate);
 210 }
 211
 212 /* Theoretical max between source and sink */
 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 216 }
 217
 218 /* Theoretical max between source and sink */
 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         int source_max = dig_port->max_lanes;
 223         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 224         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 225         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 226
 227         if (lttpr_max)
 228                 sink_max = min(sink_max, lttpr_max);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262
 263         return INTEL_GEN(dev_priv) >= 12 ||
 264                 (INTEL_GEN(dev_priv) == 11 &&
 265                  encoder->port != PORT_A);
 266 }
 267
 268 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 272         enum port port = dig_port->base.port;
 273
 274         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 275
 276         /* Low voltage SKUs are limited to max of 5.4G */
 277         if (voltage == VOLTAGE_INFO_0_85V)
 278                 return 540000;
 279
 280         /* For this SKU 8.1G is supported in all ports */
 281         if (IS_CNL_WITH_PORT_F(dev_priv))
 282                 return 810000;
 283
 284         /* For other SKUs, max rate on ports A and D is 5.4G */
 285         if (port == PORT_A || port == PORT_D)
 286                 return 540000;
 287
 288         return 810000;
 289 }
 290
 291 static int icl_max_source_rate(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 295         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 296
 297         if (intel_phy_is_combo(dev_priv, phy) &&
 298             !intel_dp_is_edp(intel_dp))
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         if (intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else if (IS_JSL_EHL(dev_priv))
 347                         max_rate = ehl_max_source_rate(intel_dp);
 348                 else
 349                         max_rate = icl_max_source_rate(intel_dp);
 350         } else if (IS_GEN9_LP(dev_priv)) {
 351                 source_rates = bxt_rates;
 352                 size = ARRAY_SIZE(bxt_rates);
 353         } else if (IS_GEN9_BC(dev_priv)) {
 354                 source_rates = skl_rates;
 355                 size = ARRAY_SIZE(skl_rates);
 356         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 357                    IS_BROADWELL(dev_priv)) {
 358                 source_rates = hsw_rates;
 359                 size = ARRAY_SIZE(hsw_rates);
 360         } else {
 361                 source_rates = g4x_rates;
 362                 size = ARRAY_SIZE(g4x_rates);
 363         }
 364
 365         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 366         if (max_rate && vbt_max_rate)
 367                 max_rate = min(max_rate, vbt_max_rate);
 368         else if (vbt_max_rate)
 369                 max_rate = vbt_max_rate;
 370
 371         if (max_rate)
 372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 373
 374         intel_dp->source_rates = source_rates;
 375         intel_dp->num_source_rates = size;
 376 }
 377
 378 static int intersect_rates(const int *source_rates, int source_len,
 379                            const int *sink_rates, int sink_len,
 380                            int *common_rates)
 381 {
 382         int i = 0, j = 0, k = 0;
 383
 384         while (i < source_len && j < sink_len) {
 385                 if (source_rates[i] == sink_rates[j]) {
 386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 387                                 return k;
 388                         common_rates[k] = source_rates[i];
 389                         ++k;
 390                         ++i;
 391                         ++j;
 392                 } else if (source_rates[i] < sink_rates[j]) {
 393                         ++i;
 394                 } else {
 395                         ++j;
 396                 }
 397         }
 398         return k;
 399 }
 400
 401 /* return index of rate in rates array, or -1 if not found */
 402 static int intel_dp_rate_index(const int *rates, int len, int rate)
 403 {
 404         int i;
 405
 406         for (i = 0; i < len; i++)
 407                 if (rate == rates[i])
 408                         return i;
 409
 410         return -1;
 411 }
 412
 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 414 {
 415         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 416
 417         drm_WARN_ON(&i915->drm,
 418                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 419
 420         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 421                                                      intel_dp->num_source_rates,
 422                                                      intel_dp->sink_rates,
 423                                                      intel_dp->num_sink_rates,
 424                                                      intel_dp->common_rates);
 425
 426         /* Paranoia, there should always be something in common. */
 427         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 428                 intel_dp->common_rates[0] = 162000;
 429                 intel_dp->num_common_rates = 1;
 430         }
 431 }
 432
 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 434                                        u8 lane_count)
 435 {
 436         /*
 437          * FIXME: we need to synchronize the current link parameters with
 438          * hardware readout. Currently fast link training doesn't work on
 439          * boot-up.
 440          */
 441         if (link_rate == 0 ||
 442             link_rate > intel_dp->max_link_rate)
 443                 return false;
 444
 445         if (lane_count == 0 ||
 446             lane_count > intel_dp_max_lane_count(intel_dp))
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 453                                                      int link_rate,
 454                                                      u8 lane_count)
 455 {
 456         const struct drm_display_mode *fixed_mode =
 457                 intel_dp->attached_connector->panel.fixed_mode;
 458         int mode_rate, max_rate;
 459
 460         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 461         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 462         if (mode_rate > max_rate)
 463                 return false;
 464
 465         return true;
 466 }
 467
 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 469                                             int link_rate, u8 lane_count)
 470 {
 471         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 472         int index;
 473
 474         /*
 475          * TODO: Enable fallback on MST links once MST link compute can handle
 476          * the fallback params.
 477          */
 478         if (intel_dp->is_mst) {
 479                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 480                 return -1;
 481         }
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         drm_dbg_kms(&i915->drm,
 492                                     "Retrying Link training for eDP with same parameters\n");
 493                         return 0;
 494                 }
 495                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 496                 intel_dp->max_link_lane_count = lane_count;
 497         } else if (lane_count > 1) {
 498                 if (intel_dp_is_edp(intel_dp) &&
 499                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 500                                                               intel_dp_max_common_rate(intel_dp),
 501                                                               lane_count >> 1)) {
 502                         drm_dbg_kms(&i915->drm,
 503                                     "Retrying Link training for eDP with same parameters\n");
 504                         return 0;
 505                 }
 506                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 507                 intel_dp->max_link_lane_count = lane_count >> 1;
 508         } else {
 509                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 510                 return -1;
 511         }
 512
 513         return 0;
 514 }
 515
 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 517 {
 518         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 519                        DP_DSC_FEC_OVERHEAD_FACTOR);
 520 }
 521
 522 static int
 523 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 524 {
 525         if (INTEL_GEN(i915) >= 11)
 526                 return 7680 * 8;
 527         else
 528                 return 6144 * 8;
 529 }
 530
 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 532                                        u32 link_clock, u32 lane_count,
 533                                        u32 mode_clock, u32 mode_hdisplay,
 534                                        bool bigjoiner)
 535 {
 536         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 537         int i;
 538
 539         /*
 540          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 541          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 542          * for SST -> TimeSlotsPerMTP is 1,
 543          * for MST -> TimeSlotsPerMTP has to be calculated
 544          */
 545         bits_per_pixel = (link_clock * lane_count * 8) /
 546                          intel_dp_mode_to_fec_clock(mode_clock);
 547         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 548
 549         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 550         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 551                 mode_hdisplay;
 552
 553         if (bigjoiner)
 554                 max_bpp_small_joiner_ram *= 2;
 555
 556         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 557                     max_bpp_small_joiner_ram);
 558
 559         /*
 560          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 561          * check, output bpp from small joiner RAM check)
 562          */
 563         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 564
 565         if (bigjoiner) {
 566                 u32 max_bpp_bigjoiner =
 567                         i915->max_cdclk_freq * 48 /
 568                         intel_dp_mode_to_fec_clock(mode_clock);
 569
 570                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 571                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 572         }
 573
 574         /* Error out if the max bpp is less than smallest allowed valid bpp */
 575         if (bits_per_pixel < valid_dsc_bpp[0]) {
 576                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 577                             bits_per_pixel, valid_dsc_bpp[0]);
 578                 return 0;
 579         }
 580
 581         /* Find the nearest match in the array of known BPPs from VESA */
 582         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 583                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 584                         break;
 585         }
 586         bits_per_pixel = valid_dsc_bpp[i];
 587
 588         /*
 589          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 590          * fractional part is 0
 591          */
 592         return bits_per_pixel << 4;
 593 }
 594
 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 596                                        int mode_clock, int mode_hdisplay,
 597                                        bool bigjoiner)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         u8 min_slice_count, i;
 601         int max_slice_width;
 602
 603         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 604                 min_slice_count = DIV_ROUND_UP(mode_clock,
 605                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 606         else
 607                 min_slice_count = DIV_ROUND_UP(mode_clock,
 608                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 609
 610         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 611         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 612                 drm_dbg_kms(&i915->drm,
 613                             "Unsupported slice width %d by DP DSC Sink device\n",
 614                             max_slice_width);
 615                 return 0;
 616         }
 617         /* Also take into account max slice width */
 618         min_slice_count = max_t(u8, min_slice_count,
 619                                 DIV_ROUND_UP(mode_hdisplay,
 620                                              max_slice_width));
 621
 622         /* Find the closest match to the valid slice count values */
 623         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 624                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 625
 626                 if (test_slice_count >
 627                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 628                         break;
 629
 630                 /* big joiner needs small joiner to be enabled */
 631                 if (bigjoiner && test_slice_count < 4)
 632                         continue;
 633
 634                 if (min_slice_count <= test_slice_count)
 635                         return test_slice_count;
 636         }
 637
 638         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 639                     min_slice_count);
 640         return 0;
 641 }
 642
 643 static enum intel_output_format
 644 intel_dp_output_format(struct drm_connector *connector,
 645                        const struct drm_display_mode *mode)
 646 {
 647         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 648         const struct drm_display_info *info = &connector->display_info;
 649
 650         if (!connector->ycbcr_420_allowed ||
 651             !drm_mode_is_420_only(info, mode))
 652                 return INTEL_OUTPUT_FORMAT_RGB;
 653
 654         if (intel_dp->dfp.ycbcr_444_to_420)
 655                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 656         else
 657                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 658 }
 659
 660 int intel_dp_min_bpp(enum intel_output_format output_format)
 661 {
 662         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 663                 return 6 * 3;
 664         else
 665                 return 8 * 3;
 666 }
 667
 668 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 669 {
 670         /*
 671          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 672          * format of the number of bytes per pixel will be half the number
 673          * of bytes of RGB pixel.
 674          */
 675         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 676                 bpp /= 2;
 677
 678         return bpp;
 679 }
 680
 681 static int
 682 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 683                              const struct drm_display_mode *mode)
 684 {
 685         enum intel_output_format output_format =
 686                 intel_dp_output_format(connector, mode);
 687
 688         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 689 }
 690
 691 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 692                                   int hdisplay)
 693 {
 694         /*
 695          * Older platforms don't like hdisplay==4096 with DP.
 696          *
 697          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 698          * and frame counter increment), but we don't get vblank interrupts,
 699          * and the pipe underruns immediately. The link also doesn't seem
 700          * to get trained properly.
 701          *
 702          * On CHV the vblank interrupts don't seem to disappear but
 703          * otherwise the symptoms are similar.
 704          *
 705          * TODO: confirm the behaviour on HSW+
 706          */
 707         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 708 }
 709
 710 static enum drm_mode_status
 711 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 712                                const struct drm_display_mode *mode,
 713                                int target_clock)
 714 {
 715         struct intel_dp *intel_dp = intel_attached_dp(connector);
 716         const struct drm_display_info *info = &connector->base.display_info;
 717         int tmds_clock;
 718
 719         if (intel_dp->dfp.max_dotclock &&
 720             target_clock > intel_dp->dfp.max_dotclock)
 721                 return MODE_CLOCK_HIGH;
 722
 723         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 724         tmds_clock = target_clock;
 725         if (drm_mode_is_420_only(info, mode))
 726                 tmds_clock /= 2;
 727
 728         if (intel_dp->dfp.min_tmds_clock &&
 729             tmds_clock < intel_dp->dfp.min_tmds_clock)
 730                 return MODE_CLOCK_LOW;
 731         if (intel_dp->dfp.max_tmds_clock &&
 732             tmds_clock > intel_dp->dfp.max_tmds_clock)
 733                 return MODE_CLOCK_HIGH;
 734
 735         return MODE_OK;
 736 }
 737
 738 static enum drm_mode_status
 739 intel_dp_mode_valid(struct drm_connector *connector,
 740                     struct drm_display_mode *mode)
 741 {
 742         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 743         struct intel_connector *intel_connector = to_intel_connector(connector);
 744         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 745         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 746         int target_clock = mode->clock;
 747         int max_rate, mode_rate, max_lanes, max_link_clock;
 748         int max_dotclk = dev_priv->max_dotclk_freq;
 749         u16 dsc_max_output_bpp = 0;
 750         u8 dsc_slice_count = 0;
 751         enum drm_mode_status status;
 752         bool dsc = false, bigjoiner = false;
 753
 754         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 755                 return MODE_NO_DBLESCAN;
 756
 757         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 758                 return MODE_H_ILLEGAL;
 759
 760         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 761                 if (mode->hdisplay > fixed_mode->hdisplay)
 762                         return MODE_PANEL;
 763
 764                 if (mode->vdisplay > fixed_mode->vdisplay)
 765                         return MODE_PANEL;
 766
 767                 target_clock = fixed_mode->clock;
 768         }
 769
 770         if (mode->clock < 10000)
 771                 return MODE_CLOCK_LOW;
 772
 773         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 774             intel_dp_can_bigjoiner(intel_dp)) {
 775                 bigjoiner = true;
 776                 max_dotclk *= 2;
 777         }
 778         if (target_clock > max_dotclk)
 779                 return MODE_CLOCK_HIGH;
 780
 781         max_link_clock = intel_dp_max_link_rate(intel_dp);
 782         max_lanes = intel_dp_max_lane_count(intel_dp);
 783
 784         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 785         mode_rate = intel_dp_link_required(target_clock,
 786                                            intel_dp_mode_min_output_bpp(connector, mode));
 787
 788         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 789                 return MODE_H_ILLEGAL;
 790
 791         /*
 792          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 793          * integer value since we support only integer values of bpp.
 794          */
 795         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 796             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 797                 if (intel_dp_is_edp(intel_dp)) {
 798                         dsc_max_output_bpp =
 799                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 800                         dsc_slice_count =
 801                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 802                                                                 true);
 803                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 804                         dsc_max_output_bpp =
 805                                 intel_dp_dsc_get_output_bpp(dev_priv,
 806                                                             max_link_clock,
 807                                                             max_lanes,
 808                                                             target_clock,
 809                                                             mode->hdisplay,
 810                                                             bigjoiner) >> 4;
 811                         dsc_slice_count =
 812                                 intel_dp_dsc_get_slice_count(intel_dp,
 813                                                              target_clock,
 814                                                              mode->hdisplay,
 815                                                              bigjoiner);
 816                 }
 817
 818                 dsc = dsc_max_output_bpp && dsc_slice_count;
 819         }
 820
 821         /* big joiner configuration needs DSC */
 822         if (bigjoiner && !dsc)
 823                 return MODE_CLOCK_HIGH;
 824
 825         if (mode_rate > max_rate && !dsc)
 826                 return MODE_CLOCK_HIGH;
 827
 828         status = intel_dp_mode_valid_downstream(intel_connector,
 829                                                 mode, target_clock);
 830         if (status != MODE_OK)
 831                 return status;
 832
 833         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 834 }
 835
 836 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 837 {
 838         int i;
 839         u32 v = 0;
 840
 841         if (src_bytes > 4)
 842                 src_bytes = 4;
 843         for (i = 0; i < src_bytes; i++)
 844                 v |= ((u32)src[i]) << ((3 - i) * 8);
 845         return v;
 846 }
 847
 848 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 849 {
 850         int i;
 851         if (dst_bytes > 4)
 852                 dst_bytes = 4;
 853         for (i = 0; i < dst_bytes; i++)
 854                 dst[i] = src >> ((3-i) * 8);
 855 }
 856
 857 static void
 858 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 859 static void
 860 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 861                                               bool force_disable_vdd);
 862 static void
 863 intel_dp_pps_init(struct intel_dp *intel_dp);
 864
 865 static intel_wakeref_t
 866 pps_lock(struct intel_dp *intel_dp)
 867 {
 868         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 869         intel_wakeref_t wakeref;
 870
 871         /*
 872          * See intel_power_sequencer_reset() why we need
 873          * a power domain reference here.
 874          */
 875         wakeref = intel_display_power_get(dev_priv,
 876                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 877
 878         mutex_lock(&dev_priv->pps_mutex);
 879
 880         return wakeref;
 881 }
 882
 883 static intel_wakeref_t
 884 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 885 {
 886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 887
 888         mutex_unlock(&dev_priv->pps_mutex);
 889         intel_display_power_put(dev_priv,
 890                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 891                                 wakeref);
 892         return 0;
 893 }
 894
 895 #define with_pps_lock(dp, wf) \
 896         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 897
 898 static void
 899 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 902         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 903         enum pipe pipe = intel_dp->pps_pipe;
 904         bool pll_enabled, release_cl_override = false;
 905         enum dpio_phy phy = DPIO_PHY(pipe);
 906         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 907         u32 DP;
 908
 909         if (drm_WARN(&dev_priv->drm,
 910                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 911                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 912                      pipe_name(pipe), dig_port->base.base.base.id,
 913                      dig_port->base.base.name))
 914                 return;
 915
 916         drm_dbg_kms(&dev_priv->drm,
 917                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 918                     pipe_name(pipe), dig_port->base.base.base.id,
 919                     dig_port->base.base.name);
 920
 921         /* Preserve the BIOS-computed detected bit. This is
 922          * supposed to be read-only.
 923          */
 924         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 925         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 926         DP |= DP_PORT_WIDTH(1);
 927         DP |= DP_LINK_TRAIN_PAT_1;
 928
 929         if (IS_CHERRYVIEW(dev_priv))
 930                 DP |= DP_PIPE_SEL_CHV(pipe);
 931         else
 932                 DP |= DP_PIPE_SEL(pipe);
 933
 934         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 935
 936         /*
 937          * The DPLL for the pipe must be enabled for this to work.
 938          * So enable temporarily it if it's not already enabled.
 939          */
 940         if (!pll_enabled) {
 941                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 942                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 943
 944                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 945                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 946                         drm_err(&dev_priv->drm,
 947                                 "Failed to force on pll for pipe %c!\n",
 948                                 pipe_name(pipe));
 949                         return;
 950                 }
 951         }
 952
 953         /*
 954          * Similar magic as in intel_dp_enable_port().
 955          * We _must_ do this port enable + disable trick
 956          * to make this power sequencer lock onto the port.
 957          * Otherwise even VDD force bit won't work.
 958          */
 959         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 960         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 961
 962         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 963         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 964
 965         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 966         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 967
 968         if (!pll_enabled) {
 969                 vlv_force_pll_off(dev_priv, pipe);
 970
 971                 if (release_cl_override)
 972                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 973         }
 974 }
 975
 976 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 977 {
 978         struct intel_encoder *encoder;
 979         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 980
 981         /*
 982          * We don't have power sequencer currently.
 983          * Pick one that's not used by other ports.
 984          */
 985         for_each_intel_dp(&dev_priv->drm, encoder) {
 986                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 987
 988                 if (encoder->type == INTEL_OUTPUT_EDP) {
 989                         drm_WARN_ON(&dev_priv->drm,
 990                                     intel_dp->active_pipe != INVALID_PIPE &&
 991                                     intel_dp->active_pipe !=
 992                                     intel_dp->pps_pipe);
 993
 994                         if (intel_dp->pps_pipe != INVALID_PIPE)
 995                                 pipes &= ~(1 << intel_dp->pps_pipe);
 996                 } else {
 997                         drm_WARN_ON(&dev_priv->drm,
 998                                     intel_dp->pps_pipe != INVALID_PIPE);
 999
1000                         if (intel_dp->active_pipe != INVALID_PIPE)
1001                                 pipes &= ~(1 << intel_dp->active_pipe);
1002                 }
1003         }
1004
1005         if (pipes == 0)
1006                 return INVALID_PIPE;
1007
1008         return ffs(pipes) - 1;
1009 }
1010
1011 static enum pipe
1012 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
1013 {
1014         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1015         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1016         enum pipe pipe;
1017
1018         lockdep_assert_held(&dev_priv->pps_mutex);
1019
1020         /* We should never land here with regular DP ports */
1021         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1022
1023         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
1024                     intel_dp->active_pipe != intel_dp->pps_pipe);
1025
1026         if (intel_dp->pps_pipe != INVALID_PIPE)
1027                 return intel_dp->pps_pipe;
1028
1029         pipe = vlv_find_free_pps(dev_priv);
1030
1031         /*
1032          * Didn't find one. This should not happen since there
1033          * are two power sequencers and up to two eDP ports.
1034          */
1035         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
1036                 pipe = PIPE_A;
1037
1038         vlv_steal_power_sequencer(dev_priv, pipe);
1039         intel_dp->pps_pipe = pipe;
1040
1041         drm_dbg_kms(&dev_priv->drm,
1042                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1043                     pipe_name(intel_dp->pps_pipe),
1044                     dig_port->base.base.base.id,
1045                     dig_port->base.base.name);
1046
1047         /* init power sequencer on this pipe and port */
1048         intel_dp_init_panel_power_sequencer(intel_dp);
1049         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1050
1051         /*
1052          * Even vdd force doesn't work until we've made
1053          * the power sequencer lock in on the port.
1054          */
1055         vlv_power_sequencer_kick(intel_dp);
1056
1057         return intel_dp->pps_pipe;
1058 }
1059
1060 static int
1061 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
1062 {
1063         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1064         int backlight_controller = dev_priv->vbt.backlight.controller;
1065
1066         lockdep_assert_held(&dev_priv->pps_mutex);
1067
1068         /* We should never land here with regular DP ports */
1069         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1070
1071         if (!intel_dp->pps_reset)
1072                 return backlight_controller;
1073
1074         intel_dp->pps_reset = false;
1075
1076         /*
1077          * Only the HW needs to be reprogrammed, the SW state is fixed and
1078          * has been setup during connector init.
1079          */
1080         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1081
1082         return backlight_controller;
1083 }
1084
1085 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
1086                                enum pipe pipe);
1087
1088 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
1089                                enum pipe pipe)
1090 {
1091         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
1092 }
1093
1094 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
1095                                 enum pipe pipe)
1096 {
1097         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1098 }
1099
1100 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
1101                          enum pipe pipe)
1102 {
1103         return true;
1104 }
1105
1106 static enum pipe
1107 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
1108                      enum port port,
1109                      vlv_pipe_check pipe_check)
1110 {
1111         enum pipe pipe;
1112
1113         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
1114                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
1115                         PANEL_PORT_SELECT_MASK;
1116
1117                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
1118                         continue;
1119
1120                 if (!pipe_check(dev_priv, pipe))
1121                         continue;
1122
1123                 return pipe;
1124         }
1125
1126         return INVALID_PIPE;
1127 }
1128
1129 static void
1130 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1131 {
1132         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1133         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1134         enum port port = dig_port->base.port;
1135
1136         lockdep_assert_held(&dev_priv->pps_mutex);
1137
1138         /* try to find a pipe with this port selected */
1139         /* first pick one where the panel is on */
1140         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1141                                                   vlv_pipe_has_pp_on);
1142         /* didn't find one? pick one where vdd is on */
1143         if (intel_dp->pps_pipe == INVALID_PIPE)
1144                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1145                                                           vlv_pipe_has_vdd_on);
1146         /* didn't find one? pick one with just the correct port */
1147         if (intel_dp->pps_pipe == INVALID_PIPE)
1148                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1149                                                           vlv_pipe_any);
1150
1151         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1152         if (intel_dp->pps_pipe == INVALID_PIPE) {
1153                 drm_dbg_kms(&dev_priv->drm,
1154                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1155                             dig_port->base.base.base.id,
1156                             dig_port->base.base.name);
1157                 return;
1158         }
1159
1160         drm_dbg_kms(&dev_priv->drm,
1161                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1162                     dig_port->base.base.base.id,
1163                     dig_port->base.base.name,
1164                     pipe_name(intel_dp->pps_pipe));
1165
1166         intel_dp_init_panel_power_sequencer(intel_dp);
1167         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1168 }
1169
1170 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1171 {
1172         struct intel_encoder *encoder;
1173
1174         if (drm_WARN_ON(&dev_priv->drm,
1175                         !(IS_VALLEYVIEW(dev_priv) ||
1176                           IS_CHERRYVIEW(dev_priv) ||
1177                           IS_GEN9_LP(dev_priv))))
1178                 return;
1179
1180         /*
1181          * We can't grab pps_mutex here due to deadlock with power_domain
1182          * mutex when power_domain functions are called while holding pps_mutex.
1183          * That also means that in order to use pps_pipe the code needs to
1184          * hold both a power domain reference and pps_mutex, and the power domain
1185          * reference get/put must be done while _not_ holding pps_mutex.
1186          * pps_{lock,unlock}() do these steps in the correct order, so one
1187          * should use them always.
1188          */
1189
1190         for_each_intel_dp(&dev_priv->drm, encoder) {
1191                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1192
1193                 drm_WARN_ON(&dev_priv->drm,
1194                             intel_dp->active_pipe != INVALID_PIPE);
1195
1196                 if (encoder->type != INTEL_OUTPUT_EDP)
1197                         continue;
1198
1199                 if (IS_GEN9_LP(dev_priv))
1200                         intel_dp->pps_reset = true;
1201                 else
1202                         intel_dp->pps_pipe = INVALID_PIPE;
1203         }
1204 }
1205
1206 struct pps_registers {
1207         i915_reg_t pp_ctrl;
1208         i915_reg_t pp_stat;
1209         i915_reg_t pp_on;
1210         i915_reg_t pp_off;
1211         i915_reg_t pp_div;
1212 };
1213
1214 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1215                                     struct pps_registers *regs)
1216 {
1217         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1218         int pps_idx = 0;
1219
1220         memset(regs, 0, sizeof(*regs));
1221
1222         if (IS_GEN9_LP(dev_priv))
1223                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1224         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1225                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1226
1227         regs->pp_ctrl = PP_CONTROL(pps_idx);
1228         regs->pp_stat = PP_STATUS(pps_idx);
1229         regs->pp_on = PP_ON_DELAYS(pps_idx);
1230         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1231
1232         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1233         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1234                 regs->pp_div = INVALID_MMIO_REG;
1235         else
1236                 regs->pp_div = PP_DIVISOR(pps_idx);
1237 }
1238
1239 static i915_reg_t
1240 _pp_ctrl_reg(struct intel_dp *intel_dp)
1241 {
1242         struct pps_registers regs;
1243
1244         intel_pps_get_registers(intel_dp, &regs);
1245
1246         return regs.pp_ctrl;
1247 }
1248
1249 static i915_reg_t
1250 _pp_stat_reg(struct intel_dp *intel_dp)
1251 {
1252         struct pps_registers regs;
1253
1254         intel_pps_get_registers(intel_dp, &regs);
1255
1256         return regs.pp_stat;
1257 }
1258
1259 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1260 {
1261         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1262
1263         lockdep_assert_held(&dev_priv->pps_mutex);
1264
1265         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1266             intel_dp->pps_pipe == INVALID_PIPE)
1267                 return false;
1268
1269         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1270 }
1271
1272 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1273 {
1274         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1275
1276         lockdep_assert_held(&dev_priv->pps_mutex);
1277
1278         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1279             intel_dp->pps_pipe == INVALID_PIPE)
1280                 return false;
1281
1282         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1283 }
1284
1285 static void
1286 intel_dp_check_edp(struct intel_dp *intel_dp)
1287 {
1288         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1289
1290         if (!intel_dp_is_edp(intel_dp))
1291                 return;
1292
1293         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1294                 drm_WARN(&dev_priv->drm, 1,
1295                          "eDP powered off while attempting aux channel communication.\n");
1296                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1297                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1298                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1299         }
1300 }
1301
1302 static u32
1303 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1304 {
1305         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1306         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1307         const unsigned int timeout_ms = 10;
1308         u32 status;
1309         bool done;
1310
1311 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1312         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1313                                   msecs_to_jiffies_timeout(timeout_ms));
1314
1315         /* just trace the final value */
1316         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1317
1318         if (!done)
1319                 drm_err(&i915->drm,
1320                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1321                         intel_dp->aux.name, timeout_ms, status);
1322 #undef C
1323
1324         return status;
1325 }
1326
1327 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1328 {
1329         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1330
1331         if (index)
1332                 return 0;
1333
1334         /*
1335          * The clock divider is based off the hrawclk, and would like to run at
1336          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1337          */
1338         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1339 }
1340
1341 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1342 {
1343         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1344         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1345         u32 freq;
1346
1347         if (index)
1348                 return 0;
1349
1350         /*
1351          * The clock divider is based off the cdclk or PCH rawclk, and would
1352          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1353          * divide by 2000 and use that
1354          */
1355         if (dig_port->aux_ch == AUX_CH_A)
1356                 freq = dev_priv->cdclk.hw.cdclk;
1357         else
1358                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1359         return DIV_ROUND_CLOSEST(freq, 2000);
1360 }
1361
1362 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1363 {
1364         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1365         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1366
1367         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1368                 /* Workaround for non-ULT HSW */
1369                 switch (index) {
1370                 case 0: return 63;
1371                 case 1: return 72;
1372                 default: return 0;
1373                 }
1374         }
1375
1376         return ilk_get_aux_clock_divider(intel_dp, index);
1377 }
1378
1379 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1380 {
1381         /*
1382          * SKL doesn't need us to program the AUX clock divider (Hardware will
1383          * derive the clock from CDCLK automatically). We still implement the
1384          * get_aux_clock_divider vfunc to plug-in into the existing code.
1385          */
1386         return index ? 0 : 1;
1387 }
1388
1389 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1390                                 int send_bytes,
1391                                 u32 aux_clock_divider)
1392 {
1393         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1394         struct drm_i915_private *dev_priv =
1395                         to_i915(dig_port->base.base.dev);
1396         u32 precharge, timeout;
1397
1398         if (IS_GEN(dev_priv, 6))
1399                 precharge = 3;
1400         else
1401                 precharge = 5;
1402
1403         if (IS_BROADWELL(dev_priv))
1404                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1405         else
1406                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1407
1408         return DP_AUX_CH_CTL_SEND_BUSY |
1409                DP_AUX_CH_CTL_DONE |
1410                DP_AUX_CH_CTL_INTERRUPT |
1411                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1412                timeout |
1413                DP_AUX_CH_CTL_RECEIVE_ERROR |
1414                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1415                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1416                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1417 }
1418
1419 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1420                                 int send_bytes,
1421                                 u32 unused)
1422 {
1423         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1424         struct drm_i915_private *i915 =
1425                         to_i915(dig_port->base.base.dev);
1426         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1427         u32 ret;
1428
1429         ret = DP_AUX_CH_CTL_SEND_BUSY |
1430               DP_AUX_CH_CTL_DONE |
1431               DP_AUX_CH_CTL_INTERRUPT |
1432               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1433               DP_AUX_CH_CTL_TIME_OUT_MAX |
1434               DP_AUX_CH_CTL_RECEIVE_ERROR |
1435               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1436               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1437               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1438
1439         if (intel_phy_is_tc(i915, phy) &&
1440             dig_port->tc_mode == TC_PORT_TBT_ALT)
1441                 ret |= DP_AUX_CH_CTL_TBT_IO;
1442
1443         return ret;
1444 }
1445
1446 static int
1447 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1448                   const u8 *send, int send_bytes,
1449                   u8 *recv, int recv_size,
1450                   u32 aux_send_ctl_flags)
1451 {
1452         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1453         struct drm_i915_private *i915 =
1454                         to_i915(dig_port->base.base.dev);
1455         struct intel_uncore *uncore = &i915->uncore;
1456         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1457         bool is_tc_port = intel_phy_is_tc(i915, phy);
1458         i915_reg_t ch_ctl, ch_data[5];
1459         u32 aux_clock_divider;
1460         enum intel_display_power_domain aux_domain;
1461         intel_wakeref_t aux_wakeref;
1462         intel_wakeref_t pps_wakeref;
1463         int i, ret, recv_bytes;
1464         int try, clock = 0;
1465         u32 status;
1466         bool vdd;
1467
1468         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1469         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1470                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1471
1472         if (is_tc_port)
1473                 intel_tc_port_lock(dig_port);
1474
1475         aux_domain = intel_aux_power_domain(dig_port);
1476
1477         aux_wakeref = intel_display_power_get(i915, aux_domain);
1478         pps_wakeref = pps_lock(intel_dp);
1479
1480         /*
1481          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1482          * In such cases we want to leave VDD enabled and it's up to upper layers
1483          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1484          * ourselves.
1485          */
1486         vdd = edp_panel_vdd_on(intel_dp);
1487
1488         /* dp aux is extremely sensitive to irq latency, hence request the
1489          * lowest possible wakeup latency and so prevent the cpu from going into
1490          * deep sleep states.
1491          */
1492         cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
1493
1494         intel_dp_check_edp(intel_dp);
1495
1496         /* Try to wait for any previous AUX channel activity */
1497         for (try = 0; try < 3; try++) {
1498                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1499                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1500                         break;
1501                 msleep(1);
1502         }
1503         /* just trace the final value */
1504         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1505
1506         if (try == 3) {
1507                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1508
1509                 if (status != intel_dp->aux_busy_last_status) {
1510                         drm_WARN(&i915->drm, 1,
1511                                  "%s: not started (status 0x%08x)\n",
1512                                  intel_dp->aux.name, status);
1513                         intel_dp->aux_busy_last_status = status;
1514                 }
1515
1516                 ret = -EBUSY;
1517                 goto out;
1518         }
1519
1520         /* Only 5 data registers! */
1521         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1522                 ret = -E2BIG;
1523                 goto out;
1524         }
1525
1526         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1527                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1528                                                           send_bytes,
1529                                                           aux_clock_divider);
1530
1531                 send_ctl |= aux_send_ctl_flags;
1532
1533                 /* Must try at least 3 times according to DP spec */
1534                 for (try = 0; try < 5; try++) {
1535                         /* Load the send data into the aux channel data registers */
1536                         for (i = 0; i < send_bytes; i += 4)
1537                                 intel_uncore_write(uncore,
1538                                                    ch_data[i >> 2],
1539                                                    intel_dp_pack_aux(send + i,
1540                                                                      send_bytes - i));
1541
1542                         /* Send the command and wait for it to complete */
1543                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1544
1545                         status = intel_dp_aux_wait_done(intel_dp);
1546
1547                         /* Clear done status and any errors */
1548                         intel_uncore_write(uncore,
1549                                            ch_ctl,
1550                                            status |
1551                                            DP_AUX_CH_CTL_DONE |
1552                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1553                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1554
1555                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1556                          *   400us delay required for errors and timeouts
1557                          *   Timeout errors from the HW already meet this
1558                          *   requirement so skip to next iteration
1559                          */
1560                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1561                                 continue;
1562
1563                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1564                                 usleep_range(400, 500);
1565                                 continue;
1566                         }
1567                         if (status & DP_AUX_CH_CTL_DONE)
1568                                 goto done;
1569                 }
1570         }
1571
1572         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1573                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1574                         intel_dp->aux.name, status);
1575                 ret = -EBUSY;
1576                 goto out;
1577         }
1578
1579 done:
1580         /* Check for timeout or receive error.
1581          * Timeouts occur when the sink is not connected
1582          */
1583         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1584                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1585                         intel_dp->aux.name, status);
1586                 ret = -EIO;
1587                 goto out;
1588         }
1589
1590         /* Timeouts occur when the device isn't connected, so they're
1591          * "normal" -- don't fill the kernel log with these */
1592         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1593                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1594                             intel_dp->aux.name, status);
1595                 ret = -ETIMEDOUT;
1596                 goto out;
1597         }
1598
1599         /* Unload any bytes sent back from the other side */
1600         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1601                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1602
1603         /*
1604          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1605          * We have no idea of what happened so we return -EBUSY so
1606          * drm layer takes care for the necessary retries.
1607          */
1608         if (recv_bytes == 0 || recv_bytes > 20) {
1609                 drm_dbg_kms(&i915->drm,
1610                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1611                             intel_dp->aux.name, recv_bytes);
1612                 ret = -EBUSY;
1613                 goto out;
1614         }
1615
1616         if (recv_bytes > recv_size)
1617                 recv_bytes = recv_size;
1618
1619         for (i = 0; i < recv_bytes; i += 4)
1620                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1621                                     recv + i, recv_bytes - i);
1622
1623         ret = recv_bytes;
1624 out:
1625         cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
1626
1627         if (vdd)
1628                 edp_panel_vdd_off(intel_dp, false);
1629
1630         pps_unlock(intel_dp, pps_wakeref);
1631         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1632
1633         if (is_tc_port)
1634                 intel_tc_port_unlock(dig_port);
1635
1636         return ret;
1637 }
1638
1639 #define BARE_ADDRESS_SIZE       3
1640 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1641
1642 static void
1643 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1644                     const struct drm_dp_aux_msg *msg)
1645 {
1646         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1647         txbuf[1] = (msg->address >> 8) & 0xff;
1648         txbuf[2] = msg->address & 0xff;
1649         txbuf[3] = msg->size - 1;
1650 }
1651
1652 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1653 {
1654         /*
1655          * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1656          * select bit to inform the hardware to send the Aksv after our header
1657          * since we can't access that data from software.
1658          */
1659         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1660             msg->address == DP_AUX_HDCP_AKSV)
1661                 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1662
1663         return 0;
1664 }
1665
1666 static ssize_t
1667 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1668 {
1669         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1670         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1671         u8 txbuf[20], rxbuf[20];
1672         size_t txsize, rxsize;
1673         u32 flags = intel_dp_aux_xfer_flags(msg);
1674         int ret;
1675
1676         intel_dp_aux_header(txbuf, msg);
1677
1678         switch (msg->request & ~DP_AUX_I2C_MOT) {
1679         case DP_AUX_NATIVE_WRITE:
1680         case DP_AUX_I2C_WRITE:
1681         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1682                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1683                 rxsize = 2; /* 0 or 1 data bytes */
1684
1685                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1686                         return -E2BIG;
1687
1688                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1689
1690                 if (msg->buffer)
1691                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1692
1693                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1694                                         rxbuf, rxsize, flags);
1695                 if (ret > 0) {
1696                         msg->reply = rxbuf[0] >> 4;
1697
1698                         if (ret > 1) {
1699                                 /* Number of bytes written in a short write. */
1700                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1701                         } else {
1702                                 /* Return payload size. */
1703                                 ret = msg->size;
1704                         }
1705                 }
1706                 break;
1707
1708         case DP_AUX_NATIVE_READ:
1709         case DP_AUX_I2C_READ:
1710                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1711                 rxsize = msg->size + 1;
1712
1713                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1714                         return -E2BIG;
1715
1716                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1717                                         rxbuf, rxsize, flags);
1718                 if (ret > 0) {
1719                         msg->reply = rxbuf[0] >> 4;
1720                         /*
1721                          * Assume happy day, and copy the data. The caller is
1722                          * expected to check msg->reply before touching it.
1723                          *
1724                          * Return payload size.
1725                          */
1726                         ret--;
1727                         memcpy(msg->buffer, rxbuf + 1, ret);
1728                 }
1729                 break;
1730
1731         default:
1732                 ret = -EINVAL;
1733                 break;
1734         }
1735
1736         return ret;
1737 }
1738
1739
1740 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1741 {
1742         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1743         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1744         enum aux_ch aux_ch = dig_port->aux_ch;
1745
1746         switch (aux_ch) {
1747         case AUX_CH_B:
1748         case AUX_CH_C:
1749         case AUX_CH_D:
1750                 return DP_AUX_CH_CTL(aux_ch);
1751         default:
1752                 MISSING_CASE(aux_ch);
1753                 return DP_AUX_CH_CTL(AUX_CH_B);
1754         }
1755 }
1756
1757 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1758 {
1759         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1760         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1761         enum aux_ch aux_ch = dig_port->aux_ch;
1762
1763         switch (aux_ch) {
1764         case AUX_CH_B:
1765         case AUX_CH_C:
1766         case AUX_CH_D:
1767                 return DP_AUX_CH_DATA(aux_ch, index);
1768         default:
1769                 MISSING_CASE(aux_ch);
1770                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1771         }
1772 }
1773
1774 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1775 {
1776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1777         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1778         enum aux_ch aux_ch = dig_port->aux_ch;
1779
1780         switch (aux_ch) {
1781         case AUX_CH_A:
1782                 return DP_AUX_CH_CTL(aux_ch);
1783         case AUX_CH_B:
1784         case AUX_CH_C:
1785         case AUX_CH_D:
1786                 return PCH_DP_AUX_CH_CTL(aux_ch);
1787         default:
1788                 MISSING_CASE(aux_ch);
1789                 return DP_AUX_CH_CTL(AUX_CH_A);
1790         }
1791 }
1792
1793 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1794 {
1795         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1796         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1797         enum aux_ch aux_ch = dig_port->aux_ch;
1798
1799         switch (aux_ch) {
1800         case AUX_CH_A:
1801                 return DP_AUX_CH_DATA(aux_ch, index);
1802         case AUX_CH_B:
1803         case AUX_CH_C:
1804         case AUX_CH_D:
1805                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1806         default:
1807                 MISSING_CASE(aux_ch);
1808                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1809         }
1810 }
1811
1812 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1813 {
1814         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1815         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1816         enum aux_ch aux_ch = dig_port->aux_ch;
1817
1818         switch (aux_ch) {
1819         case AUX_CH_A:
1820         case AUX_CH_B:
1821         case AUX_CH_C:
1822         case AUX_CH_D:
1823         case AUX_CH_E:
1824         case AUX_CH_F:
1825                 return DP_AUX_CH_CTL(aux_ch);
1826         default:
1827                 MISSING_CASE(aux_ch);
1828                 return DP_AUX_CH_CTL(AUX_CH_A);
1829         }
1830 }
1831
1832 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1833 {
1834         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1835         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1836         enum aux_ch aux_ch = dig_port->aux_ch;
1837
1838         switch (aux_ch) {
1839         case AUX_CH_A:
1840         case AUX_CH_B:
1841         case AUX_CH_C:
1842         case AUX_CH_D:
1843         case AUX_CH_E:
1844         case AUX_CH_F:
1845                 return DP_AUX_CH_DATA(aux_ch, index);
1846         default:
1847                 MISSING_CASE(aux_ch);
1848                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1849         }
1850 }
1851
1852 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
1853 {
1854         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1855         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1856         enum aux_ch aux_ch = dig_port->aux_ch;
1857
1858         switch (aux_ch) {
1859         case AUX_CH_A:
1860         case AUX_CH_B:
1861         case AUX_CH_C:
1862         case AUX_CH_USBC1:
1863         case AUX_CH_USBC2:
1864         case AUX_CH_USBC3:
1865         case AUX_CH_USBC4:
1866         case AUX_CH_USBC5:
1867         case AUX_CH_USBC6:
1868                 return DP_AUX_CH_CTL(aux_ch);
1869         default:
1870                 MISSING_CASE(aux_ch);
1871                 return DP_AUX_CH_CTL(AUX_CH_A);
1872         }
1873 }
1874
1875 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
1876 {
1877         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1878         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1879         enum aux_ch aux_ch = dig_port->aux_ch;
1880
1881         switch (aux_ch) {
1882         case AUX_CH_A:
1883         case AUX_CH_B:
1884         case AUX_CH_C:
1885         case AUX_CH_USBC1:
1886         case AUX_CH_USBC2:
1887         case AUX_CH_USBC3:
1888         case AUX_CH_USBC4:
1889         case AUX_CH_USBC5:
1890         case AUX_CH_USBC6:
1891                 return DP_AUX_CH_DATA(aux_ch, index);
1892         default:
1893                 MISSING_CASE(aux_ch);
1894                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1895         }
1896 }
1897
1898 static void
1899 intel_dp_aux_fini(struct intel_dp *intel_dp)
1900 {
1901         if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
1902                 cpu_latency_qos_remove_request(&intel_dp->pm_qos);
1903
1904         kfree(intel_dp->aux.name);
1905 }
1906
1907 static void
1908 intel_dp_aux_init(struct intel_dp *intel_dp)
1909 {
1910         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1911         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1912         struct intel_encoder *encoder = &dig_port->base;
1913         enum aux_ch aux_ch = dig_port->aux_ch;
1914
1915         if (INTEL_GEN(dev_priv) >= 12) {
1916                 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
1917                 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
1918         } else if (INTEL_GEN(dev_priv) >= 9) {
1919                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1920                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1921         } else if (HAS_PCH_SPLIT(dev_priv)) {
1922                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1923                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1924         } else {
1925                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1926                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1927         }
1928
1929         if (INTEL_GEN(dev_priv) >= 9)
1930                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1931         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1932                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1933         else if (HAS_PCH_SPLIT(dev_priv))
1934                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1935         else
1936                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1937
1938         if (INTEL_GEN(dev_priv) >= 9)
1939                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1940         else
1941                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1942
1943         drm_dp_aux_init(&intel_dp->aux);
1944
1945         /* Failure to allocate our preferred name is not critical */
1946         if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
1947                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
1948                                                aux_ch - AUX_CH_USBC1 + '1',
1949                                                encoder->base.name);
1950         else
1951                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
1952                                                aux_ch_name(aux_ch),
1953                                                encoder->base.name);
1954
1955         intel_dp->aux.transfer = intel_dp_aux_transfer;
1956         cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
1957 }
1958
1959 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1960 {
1961         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1962
1963         return max_rate >= 540000;
1964 }
1965
1966 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1967 {
1968         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1969
1970         return max_rate >= 810000;
1971 }
1972
1973 static void
1974 intel_dp_set_clock(struct intel_encoder *encoder,
1975                    struct intel_crtc_state *pipe_config)
1976 {
1977         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1978         const struct dp_link_dpll *divisor = NULL;
1979         int i, count = 0;
1980
1981         if (IS_G4X(dev_priv)) {
1982                 divisor = g4x_dpll;
1983                 count = ARRAY_SIZE(g4x_dpll);
1984         } else if (HAS_PCH_SPLIT(dev_priv)) {
1985                 divisor = pch_dpll;
1986                 count = ARRAY_SIZE(pch_dpll);
1987         } else if (IS_CHERRYVIEW(dev_priv)) {
1988                 divisor = chv_dpll;
1989                 count = ARRAY_SIZE(chv_dpll);
1990         } else if (IS_VALLEYVIEW(dev_priv)) {
1991                 divisor = vlv_dpll;
1992                 count = ARRAY_SIZE(vlv_dpll);
1993         }
1994
1995         if (divisor && count) {
1996                 for (i = 0; i < count; i++) {
1997                         if (pipe_config->port_clock == divisor[i].clock) {
1998                                 pipe_config->dpll = divisor[i].dpll;
1999                                 pipe_config->clock_set = true;
2000                                 break;
2001                         }
2002                 }
2003         }
2004 }
2005
2006 static void snprintf_int_array(char *str, size_t len,
2007                                const int *array, int nelem)
2008 {
2009         int i;
2010
2011         str[0] = '\0';
2012
2013         for (i = 0; i < nelem; i++) {
2014                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
2015                 if (r >= len)
2016                         return;
2017                 str += r;
2018                 len -= r;
2019         }
2020 }
2021
2022 static void intel_dp_print_rates(struct intel_dp *intel_dp)
2023 {
2024         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2025         char str[128]; /* FIXME: too big for stack? */
2026
2027         if (!drm_debug_enabled(DRM_UT_KMS))
2028                 return;
2029
2030         snprintf_int_array(str, sizeof(str),
2031                            intel_dp->source_rates, intel_dp->num_source_rates);
2032         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
2033
2034         snprintf_int_array(str, sizeof(str),
2035                            intel_dp->sink_rates, intel_dp->num_sink_rates);
2036         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
2037
2038         snprintf_int_array(str, sizeof(str),
2039                            intel_dp->common_rates, intel_dp->num_common_rates);
2040         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
2041 }
2042
2043 int
2044 intel_dp_max_link_rate(struct intel_dp *intel_dp)
2045 {
2046         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2047         int len;
2048
2049         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
2050         if (drm_WARN_ON(&i915->drm, len <= 0))
2051                 return 162000;
2052
2053         return intel_dp->common_rates[len - 1];
2054 }
2055
2056 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
2057 {
2058         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2059         int i = intel_dp_rate_index(intel_dp->sink_rates,
2060                                     intel_dp->num_sink_rates, rate);
2061
2062         if (drm_WARN_ON(&i915->drm, i < 0))
2063                 i = 0;
2064
2065         return i;
2066 }
2067
2068 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2069                            u8 *link_bw, u8 *rate_select)
2070 {
2071         /* eDP 1.4 rate select method. */
2072         if (intel_dp->use_rate_select) {
2073                 *link_bw = 0;
2074                 *rate_select =
2075                         intel_dp_rate_select(intel_dp, port_clock);
2076         } else {
2077                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
2078                 *rate_select = 0;
2079         }
2080 }
2081
2082 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
2083                                          const struct intel_crtc_state *pipe_config)
2084 {
2085         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2086
2087         /* On TGL, FEC is supported on all Pipes */
2088         if (INTEL_GEN(dev_priv) >= 12)
2089                 return true;
2090
2091         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
2092                 return true;
2093
2094         return false;
2095 }
2096
2097 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
2098                                   const struct intel_crtc_state *pipe_config)
2099 {
2100         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
2101                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
2102 }
2103
2104 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
2105                                   const struct intel_crtc_state *crtc_state)
2106 {
2107         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
2108                 return false;
2109
2110         return intel_dsc_source_support(crtc_state) &&
2111                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
2112 }
2113
2114 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
2115                                    const struct intel_crtc_state *crtc_state)
2116 {
2117         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2118                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2119                  intel_dp->dfp.ycbcr_444_to_420);
2120 }
2121
2122 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
2123                                     const struct intel_crtc_state *crtc_state, int bpc)
2124 {
2125         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
2126
2127         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
2128                 clock /= 2;
2129
2130         return clock;
2131 }
2132
2133 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
2134                                            const struct intel_crtc_state *crtc_state, int bpc)
2135 {
2136         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
2137
2138         if (intel_dp->dfp.min_tmds_clock &&
2139             tmds_clock < intel_dp->dfp.min_tmds_clock)
2140                 return false;
2141
2142         if (intel_dp->dfp.max_tmds_clock &&
2143             tmds_clock > intel_dp->dfp.max_tmds_clock)
2144                 return false;
2145
2146         return true;
2147 }
2148
2149 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
2150                                               const struct intel_crtc_state *crtc_state,
2151                                               int bpc)
2152 {
2153
2154         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2155                                               intel_dp->has_hdmi_sink,
2156                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
2157                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
2158 }
2159
2160 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
2161                             const struct intel_crtc_state *crtc_state)
2162 {
2163         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2164         struct intel_connector *intel_connector = intel_dp->attached_connector;
2165         int bpp, bpc;
2166
2167         bpc = crtc_state->pipe_bpp / 3;
2168
2169         if (intel_dp->dfp.max_bpc)
2170                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
2171
2172         if (intel_dp->dfp.min_tmds_clock) {
2173                 for (; bpc >= 10; bpc -= 2) {
2174                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
2175                                 break;
2176                 }
2177         }
2178
2179         bpp = bpc * 3;
2180         if (intel_dp_is_edp(intel_dp)) {
2181                 /* Get bpp from vbt only for panels that dont have bpp in edid */
2182                 if (intel_connector->base.display_info.bpc == 0 &&
2183                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
2184                         drm_dbg_kms(&dev_priv->drm,
2185                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
2186                                     dev_priv->vbt.edp.bpp);
2187                         bpp = dev_priv->vbt.edp.bpp;
2188                 }
2189         }
2190
2191         return bpp;
2192 }
2193
2194 /* Adjust link config limits based on compliance test requests. */
2195 void
2196 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2197                                   struct intel_crtc_state *pipe_config,
2198                                   struct link_config_limits *limits)
2199 {
2200         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2201
2202         /* For DP Compliance we override the computed bpp for the pipe */
2203         if (intel_dp->compliance.test_data.bpc != 0) {
2204                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2205
2206                 limits->min_bpp = limits->max_bpp = bpp;
2207                 pipe_config->dither_force_disable = bpp == 6 * 3;
2208
2209                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2210         }
2211
2212         /* Use values requested by Compliance Test Request */
2213         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2214                 int index;
2215
2216                 /* Validate the compliance test data since max values
2217                  * might have changed due to link train fallback.
2218                  */
2219                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2220                                                intel_dp->compliance.test_lane_count)) {
2221                         index = intel_dp_rate_index(intel_dp->common_rates,
2222                                                     intel_dp->num_common_rates,
2223                                                     intel_dp->compliance.test_link_rate);
2224                         if (index >= 0)
2225                                 limits->min_clock = limits->max_clock = index;
2226                         limits->min_lane_count = limits->max_lane_count =
2227                                 intel_dp->compliance.test_lane_count;
2228                 }
2229         }
2230 }
2231
2232 /* Optimize link config in order: max bpp, min clock, min lanes */
2233 static int
2234 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2235                                   struct intel_crtc_state *pipe_config,
2236                                   const struct link_config_limits *limits)
2237 {
2238         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2239         int bpp, clock, lane_count;
2240         int mode_rate, link_clock, link_avail;
2241
2242         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2243                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
2244
2245                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2246                                                    output_bpp);
2247
2248                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2249                         for (lane_count = limits->min_lane_count;
2250                              lane_count <= limits->max_lane_count;
2251                              lane_count <<= 1) {
2252                                 link_clock = intel_dp->common_rates[clock];
2253                                 link_avail = intel_dp_max_data_rate(link_clock,
2254                                                                     lane_count);
2255
2256                                 if (mode_rate <= link_avail) {
2257                                         pipe_config->lane_count = lane_count;
2258                                         pipe_config->pipe_bpp = bpp;
2259                                         pipe_config->port_clock = link_clock;
2260
2261                                         return 0;
2262                                 }
2263                         }
2264                 }
2265         }
2266
2267         return -EINVAL;
2268 }
2269
2270 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2271 {
2272         int i, num_bpc;
2273         u8 dsc_bpc[3] = {0};
2274
2275         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2276                                                        dsc_bpc);
2277         for (i = 0; i < num_bpc; i++) {
2278                 if (dsc_max_bpc >= dsc_bpc[i])
2279                         return dsc_bpc[i] * 3;
2280         }
2281
2282         return 0;
2283 }
2284
2285 #define DSC_SUPPORTED_VERSION_MIN               1
2286
2287 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2288                                        struct intel_crtc_state *crtc_state)
2289 {
2290         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2291         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2292         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2293         u8 line_buf_depth;
2294         int ret;
2295
2296         ret = intel_dsc_compute_params(encoder, crtc_state);
2297         if (ret)
2298                 return ret;
2299
2300         /*
2301          * Slice Height of 8 works for all currently available panels. So start
2302          * with that if pic_height is an integral multiple of 8. Eventually add
2303          * logic to try multiple slice heights.
2304          */
2305         if (vdsc_cfg->pic_height % 8 == 0)
2306                 vdsc_cfg->slice_height = 8;
2307         else if (vdsc_cfg->pic_height % 4 == 0)
2308                 vdsc_cfg->slice_height = 4;
2309         else
2310                 vdsc_cfg->slice_height = 2;
2311
2312         vdsc_cfg->dsc_version_major =
2313                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2314                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2315         vdsc_cfg->dsc_version_minor =
2316                 min(DSC_SUPPORTED_VERSION_MIN,
2317                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2318                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2319
2320         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2321                 DP_DSC_RGB;
2322
2323         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2324         if (!line_buf_depth) {
2325                 drm_dbg_kms(&i915->drm,
2326                             "DSC Sink Line Buffer Depth invalid\n");
2327                 return -EINVAL;
2328         }
2329
2330         if (vdsc_cfg->dsc_version_minor == 2)
2331                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2332                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2333         else
2334                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2335                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2336
2337         vdsc_cfg->block_pred_enable =
2338                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2339                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2340
2341         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2342 }
2343
2344 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2345                                        struct intel_crtc_state *pipe_config,
2346                                        struct drm_connector_state *conn_state,
2347                                        struct link_config_limits *limits)
2348 {
2349         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2350         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2351         const struct drm_display_mode *adjusted_mode =
2352                 &pipe_config->hw.adjusted_mode;
2353         u8 dsc_max_bpc;
2354         int pipe_bpp;
2355         int ret;
2356
2357         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2358                 intel_dp_supports_fec(intel_dp, pipe_config);
2359
2360         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2361                 return -EINVAL;
2362
2363         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2364         if (INTEL_GEN(dev_priv) >= 12)
2365                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2366         else
2367                 dsc_max_bpc = min_t(u8, 10,
2368                                     conn_state->max_requested_bpc);
2369
2370         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2371
2372         /* Min Input BPC for ICL+ is 8 */
2373         if (pipe_bpp < 8 * 3) {
2374                 drm_dbg_kms(&dev_priv->drm,
2375                             "No DSC support for less than 8bpc\n");
2376                 return -EINVAL;
2377         }
2378
2379         /*
2380          * For now enable DSC for max bpp, max link rate, max lane count.
2381          * Optimize this later for the minimum possible link rate/lane count
2382          * with DSC enabled for the requested mode.
2383          */
2384         pipe_config->pipe_bpp = pipe_bpp;
2385         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2386         pipe_config->lane_count = limits->max_lane_count;
2387
2388         if (intel_dp_is_edp(intel_dp)) {
2389                 pipe_config->dsc.compressed_bpp =
2390                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2391                               pipe_config->pipe_bpp);
2392                 pipe_config->dsc.slice_count =
2393                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2394                                                         true);
2395         } else {
2396                 u16 dsc_max_output_bpp;
2397                 u8 dsc_dp_slice_count;
2398
2399                 dsc_max_output_bpp =
2400                         intel_dp_dsc_get_output_bpp(dev_priv,
2401                                                     pipe_config->port_clock,
2402                                                     pipe_config->lane_count,
2403                                                     adjusted_mode->crtc_clock,
2404                                                     adjusted_mode->crtc_hdisplay,
2405                                                     pipe_config->bigjoiner);
2406                 dsc_dp_slice_count =
2407                         intel_dp_dsc_get_slice_count(intel_dp,
2408                                                      adjusted_mode->crtc_clock,
2409                                                      adjusted_mode->crtc_hdisplay,
2410                                                      pipe_config->bigjoiner);
2411                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2412                         drm_dbg_kms(&dev_priv->drm,
2413                                     "Compressed BPP/Slice Count not supported\n");
2414                         return -EINVAL;
2415                 }
2416                 pipe_config->dsc.compressed_bpp = min_t(u16,
2417                                                                dsc_max_output_bpp >> 4,
2418                                                                pipe_config->pipe_bpp);
2419                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2420         }
2421         /*
2422          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2423          * is greater than the maximum Cdclock and if slice count is even
2424          * then we need to use 2 VDSC instances.
2425          */
2426         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
2427             pipe_config->bigjoiner) {
2428                 if (pipe_config->dsc.slice_count < 2) {
2429                         drm_dbg_kms(&dev_priv->drm,
2430                                     "Cannot split stream to use 2 VDSC instances\n");
2431                         return -EINVAL;
2432                 }
2433
2434                 pipe_config->dsc.dsc_split = true;
2435         }
2436
2437         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2438         if (ret < 0) {
2439                 drm_dbg_kms(&dev_priv->drm,
2440                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2441                             "Compressed BPP = %d\n",
2442                             pipe_config->pipe_bpp,
2443                             pipe_config->dsc.compressed_bpp);
2444                 return ret;
2445         }
2446
2447         pipe_config->dsc.compression_enable = true;
2448         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2449                     "Compressed Bpp = %d Slice Count = %d\n",
2450                     pipe_config->pipe_bpp,
2451                     pipe_config->dsc.compressed_bpp,
2452                     pipe_config->dsc.slice_count);
2453
2454         return 0;
2455 }
2456
2457 static int
2458 intel_dp_compute_link_config(struct intel_encoder *encoder,
2459                              struct intel_crtc_state *pipe_config,
2460                              struct drm_connector_state *conn_state)
2461 {
2462         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2463         const struct drm_display_mode *adjusted_mode =
2464                 &pipe_config->hw.adjusted_mode;
2465         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2466         struct link_config_limits limits;
2467         int common_len;
2468         int ret;
2469
2470         common_len = intel_dp_common_len_rate_limit(intel_dp,
2471                                                     intel_dp->max_link_rate);
2472
2473         /* No common link rates between source and sink */
2474         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2475
2476         limits.min_clock = 0;
2477         limits.max_clock = common_len - 1;
2478
2479         limits.min_lane_count = 1;
2480         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2481
2482         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
2483         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
2484
2485         if (intel_dp_is_edp(intel_dp)) {
2486                 /*
2487                  * Use the maximum clock and number of lanes the eDP panel
2488                  * advertizes being capable of. The panels are generally
2489                  * designed to support only a single clock and lane
2490                  * configuration, and typically these values correspond to the
2491                  * native resolution of the panel.
2492                  */
2493                 limits.min_lane_count = limits.max_lane_count;
2494                 limits.min_clock = limits.max_clock;
2495         }
2496
2497         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2498
2499         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2500                     "max rate %d max bpp %d pixel clock %iKHz\n",
2501                     limits.max_lane_count,
2502                     intel_dp->common_rates[limits.max_clock],
2503                     limits.max_bpp, adjusted_mode->crtc_clock);
2504
2505         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
2506              adjusted_mode->crtc_hdisplay > 5120) &&
2507             intel_dp_can_bigjoiner(intel_dp))
2508                 pipe_config->bigjoiner = true;
2509
2510         /*
2511          * Optimize for slow and wide. This is the place to add alternative
2512          * optimization policy.
2513          */
2514         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2515
2516         /* enable compression if the mode doesn't fit available BW */
2517         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2518         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
2519                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2520                                                   conn_state, &limits);
2521                 if (ret < 0)
2522                         return ret;
2523         }
2524
2525         if (pipe_config->dsc.compression_enable) {
2526                 drm_dbg_kms(&i915->drm,
2527                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2528                             pipe_config->lane_count, pipe_config->port_clock,
2529                             pipe_config->pipe_bpp,
2530                             pipe_config->dsc.compressed_bpp);
2531
2532                 drm_dbg_kms(&i915->drm,
2533                             "DP link rate required %i available %i\n",
2534                             intel_dp_link_required(adjusted_mode->crtc_clock,
2535                                                    pipe_config->dsc.compressed_bpp),
2536                             intel_dp_max_data_rate(pipe_config->port_clock,
2537                                                    pipe_config->lane_count));
2538         } else {
2539                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2540                             pipe_config->lane_count, pipe_config->port_clock,
2541                             pipe_config->pipe_bpp);
2542
2543                 drm_dbg_kms(&i915->drm,
2544                             "DP link rate required %i available %i\n",
2545                             intel_dp_link_required(adjusted_mode->crtc_clock,
2546                                                    pipe_config->pipe_bpp),
2547                             intel_dp_max_data_rate(pipe_config->port_clock,
2548                                                    pipe_config->lane_count));
2549         }
2550         return 0;
2551 }
2552
2553 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2554                                   const struct drm_connector_state *conn_state)
2555 {
2556         const struct intel_digital_connector_state *intel_conn_state =
2557                 to_intel_digital_connector_state(conn_state);
2558         const struct drm_display_mode *adjusted_mode =
2559                 &crtc_state->hw.adjusted_mode;
2560
2561         /*
2562          * Our YCbCr output is always limited range.
2563          * crtc_state->limited_color_range only applies to RGB,
2564          * and it must never be set for YCbCr or we risk setting
2565          * some conflicting bits in PIPECONF which will mess up
2566          * the colors on the monitor.
2567          */
2568         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2569                 return false;
2570
2571         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2572                 /*
2573                  * See:
2574                  * CEA-861-E - 5.1 Default Encoding Parameters
2575                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2576                  */
2577                 return crtc_state->pipe_bpp != 18 &&
2578                         drm_default_rgb_quant_range(adjusted_mode) ==
2579                         HDMI_QUANTIZATION_RANGE_LIMITED;
2580         } else {
2581                 return intel_conn_state->broadcast_rgb ==
2582                         INTEL_BROADCAST_RGB_LIMITED;
2583         }
2584 }
2585
2586 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2587                                     enum port port)
2588 {
2589         if (IS_G4X(dev_priv))
2590                 return false;
2591         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2592                 return false;
2593
2594         return true;
2595 }
2596
2597 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2598                                              const struct drm_connector_state *conn_state,
2599                                              struct drm_dp_vsc_sdp *vsc)
2600 {
2601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2602         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2603
2604         /*
2605          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2606          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2607          * Colorimetry Format indication.
2608          */
2609         vsc->revision = 0x5;
2610         vsc->length = 0x13;
2611
2612         /* DP 1.4a spec, Table 2-120 */
2613         switch (crtc_state->output_format) {
2614         case INTEL_OUTPUT_FORMAT_YCBCR444:
2615                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2616                 break;
2617         case INTEL_OUTPUT_FORMAT_YCBCR420:
2618                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2619                 break;
2620         case INTEL_OUTPUT_FORMAT_RGB:
2621         default:
2622                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2623         }
2624
2625         switch (conn_state->colorspace) {
2626         case DRM_MODE_COLORIMETRY_BT709_YCC:
2627                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2628                 break;
2629         case DRM_MODE_COLORIMETRY_XVYCC_601:
2630                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2631                 break;
2632         case DRM_MODE_COLORIMETRY_XVYCC_709:
2633                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2634                 break;
2635         case DRM_MODE_COLORIMETRY_SYCC_601:
2636                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2637                 break;
2638         case DRM_MODE_COLORIMETRY_OPYCC_601:
2639                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2640                 break;
2641         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2642                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2643                 break;
2644         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2645                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2646                 break;
2647         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2648                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2649                 break;
2650         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2651         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2652                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2653                 break;
2654         default:
2655                 /*
2656                  * RGB->YCBCR color conversion uses the BT.709
2657                  * color space.
2658                  */
2659                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2660                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2661                 else
2662                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2663                 break;
2664         }
2665
2666         vsc->bpc = crtc_state->pipe_bpp / 3;
2667
2668         /* only RGB pixelformat supports 6 bpc */
2669         drm_WARN_ON(&dev_priv->drm,
2670                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2671
2672         /* all YCbCr are always limited range */
2673         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2674         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2675 }
2676
2677 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2678                                      struct intel_crtc_state *crtc_state,
2679                                      const struct drm_connector_state *conn_state)
2680 {
2681         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2682
2683         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2684         if (crtc_state->has_psr)
2685                 return;
2686
2687         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2688                 return;
2689
2690         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2691         vsc->sdp_type = DP_SDP_VSC;
2692         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2693                                          &crtc_state->infoframes.vsc);
2694 }
2695
2696 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2697                                   const struct intel_crtc_state *crtc_state,
2698                                   const struct drm_connector_state *conn_state,
2699                                   struct drm_dp_vsc_sdp *vsc)
2700 {
2701         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2702
2703         vsc->sdp_type = DP_SDP_VSC;
2704
2705         if (dev_priv->psr.psr2_enabled) {
2706                 if (dev_priv->psr.colorimetry_support &&
2707                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2708                         /* [PSR2, +Colorimetry] */
2709                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2710                                                          vsc);
2711                 } else {
2712                         /*
2713                          * [PSR2, -Colorimetry]
2714                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2715                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2716                          */
2717                         vsc->revision = 0x4;
2718                         vsc->length = 0xe;
2719                 }
2720         } else {
2721                 /*
2722                  * [PSR1]
2723                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2724                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2725                  * higher).
2726                  */
2727                 vsc->revision = 0x2;
2728                 vsc->length = 0x8;
2729         }
2730 }
2731
2732 static void
2733 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2734                                             struct intel_crtc_state *crtc_state,
2735                                             const struct drm_connector_state *conn_state)
2736 {
2737         int ret;
2738         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2739         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2740
2741         if (!conn_state->hdr_output_metadata)
2742                 return;
2743
2744         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2745
2746         if (ret) {
2747                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2748                 return;
2749         }
2750
2751         crtc_state->infoframes.enable |=
2752                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2753 }
2754
2755 static void
2756 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2757                              struct intel_crtc_state *pipe_config,
2758                              int output_bpp, bool constant_n)
2759 {
2760         struct intel_connector *intel_connector = intel_dp->attached_connector;
2761         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2762
2763         /*
2764          * DRRS and PSR can't be enable together, so giving preference to PSR
2765          * as it allows more power-savings by complete shutting down display,
2766          * so to guarantee this, intel_dp_drrs_compute_config() must be called
2767          * after intel_psr_compute_config().
2768          */
2769         if (pipe_config->has_psr)
2770                 return;
2771
2772         if (!intel_connector->panel.downclock_mode ||
2773             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2774                 return;
2775
2776         pipe_config->has_drrs = true;
2777         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2778                                intel_connector->panel.downclock_mode->clock,
2779                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2780                                constant_n, pipe_config->fec_enable);
2781 }
2782
2783 int
2784 intel_dp_compute_config(struct intel_encoder *encoder,
2785                         struct intel_crtc_state *pipe_config,
2786                         struct drm_connector_state *conn_state)
2787 {
2788         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2789         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2790         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2791         enum port port = encoder->port;
2792         struct intel_connector *intel_connector = intel_dp->attached_connector;
2793         struct intel_digital_connector_state *intel_conn_state =
2794                 to_intel_digital_connector_state(conn_state);
2795         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2796                                            DP_DPCD_QUIRK_CONSTANT_N);
2797         int ret = 0, output_bpp;
2798
2799         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2800                 pipe_config->has_pch_encoder = true;
2801
2802         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
2803                                                             adjusted_mode);
2804
2805         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2806                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2807                 if (ret)
2808                         return ret;
2809         }
2810
2811         if (!intel_dp_port_has_audio(dev_priv, port))
2812                 pipe_config->has_audio = false;
2813         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2814                 pipe_config->has_audio = intel_dp->has_audio;
2815         else
2816                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2817
2818         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2819                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2820                                        adjusted_mode);
2821
2822                 if (HAS_GMCH(dev_priv))
2823                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2824                 else
2825                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2826                 if (ret)
2827                         return ret;
2828         }
2829
2830         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2831                 return -EINVAL;
2832
2833         if (HAS_GMCH(dev_priv) &&
2834             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2835                 return -EINVAL;
2836
2837         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2838                 return -EINVAL;
2839
2840         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2841                 return -EINVAL;
2842
2843         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2844         if (ret < 0)
2845                 return ret;
2846
2847         pipe_config->limited_color_range =
2848                 intel_dp_limited_color_range(pipe_config, conn_state);
2849
2850         if (pipe_config->dsc.compression_enable)
2851                 output_bpp = pipe_config->dsc.compressed_bpp;
2852         else
2853                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2854                                                  pipe_config->pipe_bpp);
2855
2856         intel_link_compute_m_n(output_bpp,
2857                                pipe_config->lane_count,
2858                                adjusted_mode->crtc_clock,
2859                                pipe_config->port_clock,
2860                                &pipe_config->dp_m_n,
2861                                constant_n, pipe_config->fec_enable);
2862
2863         if (!HAS_DDI(dev_priv))
2864                 intel_dp_set_clock(encoder, pipe_config);
2865
2866         intel_psr_compute_config(intel_dp, pipe_config);
2867         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2868                                      constant_n);
2869         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2870         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2871
2872         return 0;
2873 }
2874
2875 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2876                               int link_rate, int lane_count)
2877 {
2878         intel_dp->link_trained = false;
2879         intel_dp->link_rate = link_rate;
2880         intel_dp->lane_count = lane_count;
2881 }
2882
2883 static void intel_dp_prepare(struct intel_encoder *encoder,
2884                              const struct intel_crtc_state *pipe_config)
2885 {
2886         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2887         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2888         enum port port = encoder->port;
2889         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2890         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2891
2892         intel_dp_set_link_params(intel_dp,
2893                                  pipe_config->port_clock,
2894                                  pipe_config->lane_count);
2895
2896         /*
2897          * There are four kinds of DP registers:
2898          *
2899          *      IBX PCH
2900          *      SNB CPU
2901          *      IVB CPU
2902          *      CPT PCH
2903          *
2904          * IBX PCH and CPU are the same for almost everything,
2905          * except that the CPU DP PLL is configured in this
2906          * register
2907          *
2908          * CPT PCH is quite different, having many bits moved
2909          * to the TRANS_DP_CTL register instead. That
2910          * configuration happens (oddly) in ilk_pch_enable
2911          */
2912
2913         /* Preserve the BIOS-computed detected bit. This is
2914          * supposed to be read-only.
2915          */
2916         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2917
2918         /* Handle DP bits in common between all three register formats */
2919         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2920         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2921
2922         /* Split out the IBX/CPU vs CPT settings */
2923
2924         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2925                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2926                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2927                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2928                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2929                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2930
2931                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2932                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2933
2934                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2935         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2936                 u32 trans_dp;
2937
2938                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2939
2940                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2941                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2942                         trans_dp |= TRANS_DP_ENH_FRAMING;
2943                 else
2944                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2945                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2946         } else {
2947                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2948                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2949
2950                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2951                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2952                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2953                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2954                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2955
2956                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2957                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2958
2959                 if (IS_CHERRYVIEW(dev_priv))
2960                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2961                 else
2962                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2963         }
2964 }
2965
2966 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2967 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2968
2969 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2970 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2971
2972 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2973 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2974
2975 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2976
2977 static void wait_panel_status(struct intel_dp *intel_dp,
2978                                        u32 mask,
2979                                        u32 value)
2980 {
2981         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2982         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2983
2984         lockdep_assert_held(&dev_priv->pps_mutex);
2985
2986         intel_pps_verify_state(intel_dp);
2987
2988         pp_stat_reg = _pp_stat_reg(intel_dp);
2989         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2990
2991         drm_dbg_kms(&dev_priv->drm,
2992                     "mask %08x value %08x status %08x control %08x\n",
2993                     mask, value,
2994                     intel_de_read(dev_priv, pp_stat_reg),
2995                     intel_de_read(dev_priv, pp_ctrl_reg));
2996
2997         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2998                                        mask, value, 5000))
2999                 drm_err(&dev_priv->drm,
3000                         "Panel status timeout: status %08x control %08x\n",
3001                         intel_de_read(dev_priv, pp_stat_reg),
3002                         intel_de_read(dev_priv, pp_ctrl_reg));
3003
3004         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
3005 }
3006
3007 static void wait_panel_on(struct intel_dp *intel_dp)
3008 {
3009         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3010
3011         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
3012         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
3013 }
3014
3015 static void wait_panel_off(struct intel_dp *intel_dp)
3016 {
3017         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3018
3019         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
3020         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
3021 }
3022
3023 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
3024 {
3025         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3026         ktime_t panel_power_on_time;
3027         s64 panel_power_off_duration;
3028
3029         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
3030
3031         /* take the difference of currrent time and panel power off time
3032          * and then make panel wait for t11_t12 if needed. */
3033         panel_power_on_time = ktime_get_boottime();
3034         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
3035
3036         /* When we disable the VDD override bit last we have to do the manual
3037          * wait. */
3038         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
3039                 wait_remaining_ms_from_jiffies(jiffies,
3040                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
3041
3042         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
3043 }
3044
3045 static void wait_backlight_on(struct intel_dp *intel_dp)
3046 {
3047         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
3048                                        intel_dp->backlight_on_delay);
3049 }
3050
3051 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
3052 {
3053         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
3054                                        intel_dp->backlight_off_delay);
3055 }
3056
3057 /* Read the current pp_control value, unlocking the register if it
3058  * is locked
3059  */
3060
3061 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
3062 {
3063         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3064         u32 control;
3065
3066         lockdep_assert_held(&dev_priv->pps_mutex);
3067
3068         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
3069         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
3070                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
3071                 control &= ~PANEL_UNLOCK_MASK;
3072                 control |= PANEL_UNLOCK_REGS;
3073         }
3074         return control;
3075 }
3076
3077 /*
3078  * Must be paired with edp_panel_vdd_off().
3079  * Must hold pps_mutex around the whole on/off sequence.
3080  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3081  */
3082 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
3083 {
3084         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3085         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3086         u32 pp;
3087         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3088         bool need_to_disable = !intel_dp->want_panel_vdd;
3089
3090         lockdep_assert_held(&dev_priv->pps_mutex);
3091
3092         if (!intel_dp_is_edp(intel_dp))
3093                 return false;
3094
3095         cancel_delayed_work(&intel_dp->panel_vdd_work);
3096         intel_dp->want_panel_vdd = true;
3097
3098         if (edp_have_panel_vdd(intel_dp))
3099                 return need_to_disable;
3100
3101         intel_display_power_get(dev_priv,
3102                                 intel_aux_power_domain(dig_port));
3103
3104         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
3105                     dig_port->base.base.base.id,
3106                     dig_port->base.base.name);
3107
3108         if (!edp_have_panel_power(intel_dp))
3109                 wait_panel_power_cycle(intel_dp);
3110
3111         pp = ilk_get_pp_control(intel_dp);
3112         pp |= EDP_FORCE_VDD;
3113
3114         pp_stat_reg = _pp_stat_reg(intel_dp);
3115         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3116
3117         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3118         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3119         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3120                     intel_de_read(dev_priv, pp_stat_reg),
3121                     intel_de_read(dev_priv, pp_ctrl_reg));
3122         /*
3123          * If the panel wasn't on, delay before accessing aux channel
3124          */
3125         if (!edp_have_panel_power(intel_dp)) {
3126                 drm_dbg_kms(&dev_priv->drm,
3127                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
3128                             dig_port->base.base.base.id,
3129                             dig_port->base.base.name);
3130                 msleep(intel_dp->panel_power_up_delay);
3131         }
3132
3133         return need_to_disable;
3134 }
3135
3136 /*
3137  * Must be paired with intel_edp_panel_vdd_off() or
3138  * intel_edp_panel_off().
3139  * Nested calls to these functions are not allowed since
3140  * we drop the lock. Caller must use some higher level
3141  * locking to prevent nested calls from other threads.
3142  */
3143 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
3144 {
3145         intel_wakeref_t wakeref;
3146         bool vdd;
3147
3148         if (!intel_dp_is_edp(intel_dp))
3149                 return;
3150
3151         vdd = false;
3152         with_pps_lock(intel_dp, wakeref)
3153                 vdd = edp_panel_vdd_on(intel_dp);
3154         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
3155                         dp_to_dig_port(intel_dp)->base.base.base.id,
3156                         dp_to_dig_port(intel_dp)->base.base.name);
3157 }
3158
3159 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3160 {
3161         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3162         struct intel_digital_port *dig_port =
3163                 dp_to_dig_port(intel_dp);
3164         u32 pp;
3165         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3166
3167         lockdep_assert_held(&dev_priv->pps_mutex);
3168
3169         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3170
3171         if (!edp_have_panel_vdd(intel_dp))
3172                 return;
3173
3174         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3175                     dig_port->base.base.base.id,
3176                     dig_port->base.base.name);
3177
3178         pp = ilk_get_pp_control(intel_dp);
3179         pp &= ~EDP_FORCE_VDD;
3180
3181         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3182         pp_stat_reg = _pp_stat_reg(intel_dp);
3183
3184         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3185         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3186
3187         /* Make sure sequencer is idle before allowing subsequent activity */
3188         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3189                     intel_de_read(dev_priv, pp_stat_reg),
3190                     intel_de_read(dev_priv, pp_ctrl_reg));
3191
3192         if ((pp & PANEL_POWER_ON) == 0)
3193                 intel_dp->panel_power_off_time = ktime_get_boottime();
3194
3195         intel_display_power_put_unchecked(dev_priv,
3196                                           intel_aux_power_domain(dig_port));
3197 }
3198
3199 static void edp_panel_vdd_work(struct work_struct *__work)
3200 {
3201         struct intel_dp *intel_dp =
3202                 container_of(to_delayed_work(__work),
3203                              struct intel_dp, panel_vdd_work);
3204         intel_wakeref_t wakeref;
3205
3206         with_pps_lock(intel_dp, wakeref) {
3207                 if (!intel_dp->want_panel_vdd)
3208                         edp_panel_vdd_off_sync(intel_dp);
3209         }
3210 }
3211
3212 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3213 {
3214         unsigned long delay;
3215
3216         /*
3217          * Queue the timer to fire a long time from now (relative to the power
3218          * down delay) to keep the panel power up across a sequence of
3219          * operations.
3220          */
3221         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3222         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3223 }
3224
3225 /*
3226  * Must be paired with edp_panel_vdd_on().
3227  * Must hold pps_mutex around the whole on/off sequence.
3228  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3229  */
3230 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3231 {
3232         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3233
3234         lockdep_assert_held(&dev_priv->pps_mutex);
3235
3236         if (!intel_dp_is_edp(intel_dp))
3237                 return;
3238
3239         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3240                         dp_to_dig_port(intel_dp)->base.base.base.id,
3241                         dp_to_dig_port(intel_dp)->base.base.name);
3242
3243         intel_dp->want_panel_vdd = false;
3244
3245         if (sync)
3246                 edp_panel_vdd_off_sync(intel_dp);
3247         else
3248                 edp_panel_vdd_schedule_off(intel_dp);
3249 }
3250
3251 static void edp_panel_on(struct intel_dp *intel_dp)
3252 {
3253         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3254         u32 pp;
3255         i915_reg_t pp_ctrl_reg;
3256
3257         lockdep_assert_held(&dev_priv->pps_mutex);
3258
3259         if (!intel_dp_is_edp(intel_dp))
3260                 return;
3261
3262         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3263                     dp_to_dig_port(intel_dp)->base.base.base.id,
3264                     dp_to_dig_port(intel_dp)->base.base.name);
3265
3266         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3267                      "[ENCODER:%d:%s] panel power already on\n",
3268                      dp_to_dig_port(intel_dp)->base.base.base.id,
3269                      dp_to_dig_port(intel_dp)->base.base.name))
3270                 return;
3271
3272         wait_panel_power_cycle(intel_dp);
3273
3274         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3275         pp = ilk_get_pp_control(intel_dp);
3276         if (IS_GEN(dev_priv, 5)) {
3277                 /* ILK workaround: disable reset around power sequence */
3278                 pp &= ~PANEL_POWER_RESET;
3279                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3280                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3281         }
3282
3283         pp |= PANEL_POWER_ON;
3284         if (!IS_GEN(dev_priv, 5))
3285                 pp |= PANEL_POWER_RESET;
3286
3287         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3288         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3289
3290         wait_panel_on(intel_dp);
3291         intel_dp->last_power_on = jiffies;
3292
3293         if (IS_GEN(dev_priv, 5)) {
3294                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3295                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3296                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3297         }
3298 }
3299
3300 void intel_edp_panel_on(struct intel_dp *intel_dp)
3301 {
3302         intel_wakeref_t wakeref;
3303
3304         if (!intel_dp_is_edp(intel_dp))
3305                 return;
3306
3307         with_pps_lock(intel_dp, wakeref)
3308                 edp_panel_on(intel_dp);
3309 }
3310
3311
3312 static void edp_panel_off(struct intel_dp *intel_dp)
3313 {
3314         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3315         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3316         u32 pp;
3317         i915_reg_t pp_ctrl_reg;
3318
3319         lockdep_assert_held(&dev_priv->pps_mutex);
3320
3321         if (!intel_dp_is_edp(intel_dp))
3322                 return;
3323
3324         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3325                     dig_port->base.base.base.id, dig_port->base.base.name);
3326
3327         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3328                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3329                  dig_port->base.base.base.id, dig_port->base.base.name);
3330
3331         pp = ilk_get_pp_control(intel_dp);
3332         /* We need to switch off panel power _and_ force vdd, for otherwise some
3333          * panels get very unhappy and cease to work. */
3334         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3335                 EDP_BLC_ENABLE);
3336
3337         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3338
3339         intel_dp->want_panel_vdd = false;
3340
3341         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3342         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3343
3344         wait_panel_off(intel_dp);
3345         intel_dp->panel_power_off_time = ktime_get_boottime();
3346
3347         /* We got a reference when we enabled the VDD. */
3348         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3349 }
3350
3351 void intel_edp_panel_off(struct intel_dp *intel_dp)
3352 {
3353         intel_wakeref_t wakeref;
3354
3355         if (!intel_dp_is_edp(intel_dp))
3356                 return;
3357
3358         with_pps_lock(intel_dp, wakeref)
3359                 edp_panel_off(intel_dp);
3360 }
3361
3362 /* Enable backlight in the panel power control. */
3363 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3364 {
3365         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3366         intel_wakeref_t wakeref;
3367
3368         /*
3369          * If we enable the backlight right away following a panel power
3370          * on, we may see slight flicker as the panel syncs with the eDP
3371          * link.  So delay a bit to make sure the image is solid before
3372          * allowing it to appear.
3373          */
3374         wait_backlight_on(intel_dp);
3375
3376         with_pps_lock(intel_dp, wakeref) {
3377                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3378                 u32 pp;
3379
3380                 pp = ilk_get_pp_control(intel_dp);
3381                 pp |= EDP_BLC_ENABLE;
3382
3383                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3384                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3385         }
3386 }
3387
3388 /* Enable backlight PWM and backlight PP control. */
3389 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3390                             const struct drm_connector_state *conn_state)
3391 {
3392         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3393         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3394
3395         if (!intel_dp_is_edp(intel_dp))
3396                 return;
3397
3398         drm_dbg_kms(&i915->drm, "\n");
3399
3400         intel_panel_enable_backlight(crtc_state, conn_state);
3401         _intel_edp_backlight_on(intel_dp);
3402 }
3403
3404 /* Disable backlight in the panel power control. */
3405 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3406 {
3407         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3408         intel_wakeref_t wakeref;
3409
3410         if (!intel_dp_is_edp(intel_dp))
3411                 return;
3412
3413         with_pps_lock(intel_dp, wakeref) {
3414                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3415                 u32 pp;
3416
3417                 pp = ilk_get_pp_control(intel_dp);
3418                 pp &= ~EDP_BLC_ENABLE;
3419
3420                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3421                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3422         }
3423
3424         intel_dp->last_backlight_off = jiffies;
3425         edp_wait_backlight_off(intel_dp);
3426 }
3427
3428 /* Disable backlight PP control and backlight PWM. */
3429 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3430 {
3431         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3432         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3433
3434         if (!intel_dp_is_edp(intel_dp))
3435                 return;
3436
3437         drm_dbg_kms(&i915->drm, "\n");
3438
3439         _intel_edp_backlight_off(intel_dp);
3440         intel_panel_disable_backlight(old_conn_state);
3441 }
3442
3443 /*
3444  * Hook for controlling the panel power control backlight through the bl_power
3445  * sysfs attribute. Take care to handle multiple calls.
3446  */
3447 static void intel_edp_backlight_power(struct intel_connector *connector,
3448                                       bool enable)
3449 {
3450         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3451         struct intel_dp *intel_dp = intel_attached_dp(connector);
3452         intel_wakeref_t wakeref;
3453         bool is_enabled;
3454
3455         is_enabled = false;
3456         with_pps_lock(intel_dp, wakeref)
3457                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3458         if (is_enabled == enable)
3459                 return;
3460
3461         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3462                     enable ? "enable" : "disable");
3463
3464         if (enable)
3465                 _intel_edp_backlight_on(intel_dp);
3466         else
3467                 _intel_edp_backlight_off(intel_dp);
3468 }
3469
3470 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3471 {
3472         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3473         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3474         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3475
3476         I915_STATE_WARN(cur_state != state,
3477                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3478                         dig_port->base.base.base.id, dig_port->base.base.name,
3479                         onoff(state), onoff(cur_state));
3480 }
3481 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3482
3483 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3484 {
3485         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3486
3487         I915_STATE_WARN(cur_state != state,
3488                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3489                         onoff(state), onoff(cur_state));
3490 }
3491 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3492 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3493
3494 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3495                            const struct intel_crtc_state *pipe_config)
3496 {
3497         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3498         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3499
3500         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3501         assert_dp_port_disabled(intel_dp);
3502         assert_edp_pll_disabled(dev_priv);
3503
3504         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3505                     pipe_config->port_clock);
3506
3507         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3508
3509         if (pipe_config->port_clock == 162000)
3510                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3511         else
3512                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3513
3514         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3515         intel_de_posting_read(dev_priv, DP_A);
3516         udelay(500);
3517
3518         /*
3519          * [DevILK] Work around required when enabling DP PLL
3520          * while a pipe is enabled going to FDI:
3521          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3522          * 2. Program DP PLL enable
3523          */
3524         if (IS_GEN(dev_priv, 5))
3525                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3526
3527         intel_dp->DP |= DP_PLL_ENABLE;
3528
3529         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3530         intel_de_posting_read(dev_priv, DP_A);
3531         udelay(200);
3532 }
3533
3534 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3535                             const struct intel_crtc_state *old_crtc_state)
3536 {
3537         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3538         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3539
3540         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3541         assert_dp_port_disabled(intel_dp);
3542         assert_edp_pll_enabled(dev_priv);
3543
3544         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3545
3546         intel_dp->DP &= ~DP_PLL_ENABLE;
3547
3548         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3549         intel_de_posting_read(dev_priv, DP_A);
3550         udelay(200);
3551 }
3552
3553 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3554 {
3555         /*
3556          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3557          * be capable of signalling downstream hpd with a long pulse.
3558          * Whether or not that means D3 is safe to use is not clear,
3559          * but let's assume so until proven otherwise.
3560          *
3561          * FIXME should really check all downstream ports...
3562          */
3563         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3564                 drm_dp_is_branch(intel_dp->dpcd) &&
3565                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3566 }
3567
3568 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3569                                            const struct intel_crtc_state *crtc_state,
3570                                            bool enable)
3571 {
3572         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3573         int ret;
3574
3575         if (!crtc_state->dsc.compression_enable)
3576                 return;
3577
3578         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3579                                  enable ? DP_DECOMPRESSION_EN : 0);
3580         if (ret < 0)
3581                 drm_dbg_kms(&i915->drm,
3582                             "Failed to %s sink decompression state\n",
3583                             enable ? "enable" : "disable");
3584 }
3585
3586 /* If the device supports it, try to set the power state appropriately */
3587 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3588 {
3589         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3590         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3591         int ret, i;
3592
3593         /* Should have a valid DPCD by this point */
3594         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3595                 return;
3596
3597         if (mode != DP_SET_POWER_D0) {
3598                 if (downstream_hpd_needs_d0(intel_dp))
3599                         return;
3600
3601                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3602         } else {
3603                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3604
3605                 lspcon_resume(dp_to_dig_port(intel_dp));
3606
3607                 /*
3608                  * When turning on, we need to retry for 1ms to give the sink
3609                  * time to wake up.
3610                  */
3611                 for (i = 0; i < 3; i++) {
3612                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3613                         if (ret == 1)
3614                                 break;
3615                         msleep(1);
3616                 }
3617
3618                 if (ret == 1 && lspcon->active)
3619                         lspcon_wait_pcon_mode(lspcon);
3620         }
3621
3622         if (ret != 1)
3623                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3624                             encoder->base.base.id, encoder->base.name,
3625                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3626 }
3627
3628 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3629                                  enum port port, enum pipe *pipe)
3630 {
3631         enum pipe p;
3632
3633         for_each_pipe(dev_priv, p) {
3634                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3635
3636                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3637                         *pipe = p;
3638                         return true;
3639                 }
3640         }
3641
3642         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3643                     port_name(port));
3644
3645         /* must initialize pipe to something for the asserts */
3646         *pipe = PIPE_A;
3647
3648         return false;
3649 }
3650
3651 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3652                            i915_reg_t dp_reg, enum port port,
3653                            enum pipe *pipe)
3654 {
3655         bool ret;
3656         u32 val;
3657
3658         val = intel_de_read(dev_priv, dp_reg);
3659
3660         ret = val & DP_PORT_EN;
3661
3662         /* asserts want to know the pipe even if the port is disabled */
3663         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3664                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3665         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3666                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3667         else if (IS_CHERRYVIEW(dev_priv))
3668                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3669         else
3670                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3671
3672         return ret;
3673 }
3674
3675 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3676                                   enum pipe *pipe)
3677 {
3678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3679         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3680         intel_wakeref_t wakeref;
3681         bool ret;
3682
3683         wakeref = intel_display_power_get_if_enabled(dev_priv,
3684                                                      encoder->power_domain);
3685         if (!wakeref)
3686                 return false;
3687
3688         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3689                                     encoder->port, pipe);
3690
3691         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3692
3693         return ret;
3694 }
3695
3696 static void intel_dp_get_config(struct intel_encoder *encoder,
3697                                 struct intel_crtc_state *pipe_config)
3698 {
3699         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3700         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3701         u32 tmp, flags = 0;
3702         enum port port = encoder->port;
3703         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3704
3705         if (encoder->type == INTEL_OUTPUT_EDP)
3706                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3707         else
3708                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3709
3710         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3711
3712         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3713
3714         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3715                 u32 trans_dp = intel_de_read(dev_priv,
3716                                              TRANS_DP_CTL(crtc->pipe));
3717
3718                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3719                         flags |= DRM_MODE_FLAG_PHSYNC;
3720                 else
3721                         flags |= DRM_MODE_FLAG_NHSYNC;
3722
3723                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3724                         flags |= DRM_MODE_FLAG_PVSYNC;
3725                 else
3726                         flags |= DRM_MODE_FLAG_NVSYNC;
3727         } else {
3728                 if (tmp & DP_SYNC_HS_HIGH)
3729                         flags |= DRM_MODE_FLAG_PHSYNC;
3730                 else
3731                         flags |= DRM_MODE_FLAG_NHSYNC;
3732
3733                 if (tmp & DP_SYNC_VS_HIGH)
3734                         flags |= DRM_MODE_FLAG_PVSYNC;
3735                 else
3736                         flags |= DRM_MODE_FLAG_NVSYNC;
3737         }
3738
3739         pipe_config->hw.adjusted_mode.flags |= flags;
3740
3741         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3742                 pipe_config->limited_color_range = true;
3743
3744         pipe_config->lane_count =
3745                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3746
3747         intel_dp_get_m_n(crtc, pipe_config);
3748
3749         if (port == PORT_A) {
3750                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3751                         pipe_config->port_clock = 162000;
3752                 else
3753                         pipe_config->port_clock = 270000;
3754         }
3755
3756         pipe_config->hw.adjusted_mode.crtc_clock =
3757                 intel_dotclock_calculate(pipe_config->port_clock,
3758                                          &pipe_config->dp_m_n);
3759
3760         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3761             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3762                 /*
3763                  * This is a big fat ugly hack.
3764                  *
3765                  * Some machines in UEFI boot mode provide us a VBT that has 18
3766                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3767                  * unknown we fail to light up. Yet the same BIOS boots up with
3768                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3769                  * max, not what it tells us to use.
3770                  *
3771                  * Note: This will still be broken if the eDP panel is not lit
3772                  * up by the BIOS, and thus we can't get the mode at module
3773                  * load.
3774                  */
3775                 drm_dbg_kms(&dev_priv->drm,
3776                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3777                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3778                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3779         }
3780 }
3781
3782 static bool
3783 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3784
3785 /**
3786  * intel_dp_sync_state - sync the encoder state during init/resume
3787  * @encoder: intel encoder to sync
3788  * @crtc_state: state for the CRTC connected to the encoder
3789  *
3790  * Sync any state stored in the encoder wrt. HW state during driver init
3791  * and system resume.
3792  */
3793 void intel_dp_sync_state(struct intel_encoder *encoder,
3794                          const struct intel_crtc_state *crtc_state)
3795 {
3796         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3797
3798         /*
3799          * Don't clobber DPCD if it's been already read out during output
3800          * setup (eDP) or detect.
3801          */
3802         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3803                 intel_dp_get_dpcd(intel_dp);
3804
3805         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3806         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3807 }
3808
3809 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3810                                     struct intel_crtc_state *crtc_state)
3811 {
3812         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3813         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3814
3815         /*
3816          * If BIOS has set an unsupported or non-standard link rate for some
3817          * reason force an encoder recompute and full modeset.
3818          */
3819         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3820                                 crtc_state->port_clock) < 0) {
3821                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
3822                 crtc_state->uapi.connectors_changed = true;
3823                 return false;
3824         }
3825
3826         /*
3827          * FIXME hack to force full modeset when DSC is being used.
3828          *
3829          * As long as we do not have full state readout and config comparison
3830          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3831          * Remove once we have readout for DSC.
3832          */
3833         if (crtc_state->dsc.compression_enable) {
3834                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
3835                 crtc_state->uapi.mode_changed = true;
3836                 return false;
3837         }
3838
3839         if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
3840                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
3841                 crtc_state->uapi.mode_changed = true;
3842                 return false;
3843         }
3844
3845         return true;
3846 }
3847
3848 static void intel_disable_dp(struct intel_atomic_state *state,
3849                              struct intel_encoder *encoder,
3850                              const struct intel_crtc_state *old_crtc_state,
3851                              const struct drm_connector_state *old_conn_state)
3852 {
3853         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3854
3855         intel_dp->link_trained = false;
3856
3857         if (old_crtc_state->has_audio)
3858                 intel_audio_codec_disable(encoder,
3859                                           old_crtc_state, old_conn_state);
3860
3861         /* Make sure the panel is off before trying to change the mode. But also
3862          * ensure that we have vdd while we switch off the panel. */
3863         intel_edp_panel_vdd_on(intel_dp);
3864         intel_edp_backlight_off(old_conn_state);
3865         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3866         intel_edp_panel_off(intel_dp);
3867 }
3868
3869 static void g4x_disable_dp(struct intel_atomic_state *state,
3870                            struct intel_encoder *encoder,
3871                            const struct intel_crtc_state *old_crtc_state,
3872                            const struct drm_connector_state *old_conn_state)
3873 {
3874         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3875 }
3876
3877 static void vlv_disable_dp(struct intel_atomic_state *state,
3878                            struct intel_encoder *encoder,
3879                            const struct intel_crtc_state *old_crtc_state,
3880                            const struct drm_connector_state *old_conn_state)
3881 {
3882         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3883 }
3884
3885 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3886                                 struct intel_encoder *encoder,
3887                                 const struct intel_crtc_state *old_crtc_state,
3888                                 const struct drm_connector_state *old_conn_state)
3889 {
3890         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3891         enum port port = encoder->port;
3892
3893         /*
3894          * Bspec does not list a specific disable sequence for g4x DP.
3895          * Follow the ilk+ sequence (disable pipe before the port) for
3896          * g4x DP as it does not suffer from underruns like the normal
3897          * g4x modeset sequence (disable pipe after the port).
3898          */
3899         intel_dp_link_down(encoder, old_crtc_state);
3900
3901         /* Only ilk+ has port A */
3902         if (port == PORT_A)
3903                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3904 }
3905
3906 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3907                                 struct intel_encoder *encoder,
3908                                 const struct intel_crtc_state *old_crtc_state,
3909                                 const struct drm_connector_state *old_conn_state)
3910 {
3911         intel_dp_link_down(encoder, old_crtc_state);
3912 }
3913
3914 static void chv_post_disable_dp(struct intel_atomic_state *state,
3915                                 struct intel_encoder *encoder,
3916                                 const struct intel_crtc_state *old_crtc_state,
3917                                 const struct drm_connector_state *old_conn_state)
3918 {
3919         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3920
3921         intel_dp_link_down(encoder, old_crtc_state);
3922
3923         vlv_dpio_get(dev_priv);
3924
3925         /* Assert data lane reset */
3926         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3927
3928         vlv_dpio_put(dev_priv);
3929 }
3930
3931 static void
3932 cpt_set_link_train(struct intel_dp *intel_dp,
3933                    const struct intel_crtc_state *crtc_state,
3934                    u8 dp_train_pat)
3935 {
3936         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3937         u32 *DP = &intel_dp->DP;
3938
3939         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3940
3941         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3942         case DP_TRAINING_PATTERN_DISABLE:
3943                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3944                 break;
3945         case DP_TRAINING_PATTERN_1:
3946                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3947                 break;
3948         case DP_TRAINING_PATTERN_2:
3949                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3950                 break;
3951         case DP_TRAINING_PATTERN_3:
3952                 drm_dbg_kms(&dev_priv->drm,
3953                             "TPS3 not supported, using TPS2 instead\n");
3954                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3955                 break;
3956         }
3957
3958         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3959         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3960 }
3961
3962 static void
3963 g4x_set_link_train(struct intel_dp *intel_dp,
3964                    const struct intel_crtc_state *crtc_state,
3965                    u8 dp_train_pat)
3966 {
3967         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3968         u32 *DP = &intel_dp->DP;
3969
3970         *DP &= ~DP_LINK_TRAIN_MASK;
3971
3972         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3973         case DP_TRAINING_PATTERN_DISABLE:
3974                 *DP |= DP_LINK_TRAIN_OFF;
3975                 break;
3976         case DP_TRAINING_PATTERN_1:
3977                 *DP |= DP_LINK_TRAIN_PAT_1;
3978                 break;
3979         case DP_TRAINING_PATTERN_2:
3980                 *DP |= DP_LINK_TRAIN_PAT_2;
3981                 break;
3982         case DP_TRAINING_PATTERN_3:
3983                 drm_dbg_kms(&dev_priv->drm,
3984                             "TPS3 not supported, using TPS2 instead\n");
3985                 *DP |= DP_LINK_TRAIN_PAT_2;
3986                 break;
3987         }
3988
3989         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3990         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3991 }
3992
3993 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3994                                  const struct intel_crtc_state *crtc_state)
3995 {
3996         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3997
3998         /* enable with pattern 1 (as per spec) */
3999
4000         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
4001                                                DP_TRAINING_PATTERN_1);
4002
4003         /*
4004          * Magic for VLV/CHV. We _must_ first set up the register
4005          * without actually enabling the port, and then do another
4006          * write to enable the port. Otherwise link training will
4007          * fail when the power sequencer is freshly used for this port.
4008          */
4009         intel_dp->DP |= DP_PORT_EN;
4010         if (crtc_state->has_audio)
4011                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
4012
4013         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4014         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4015 }
4016
4017 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
4018 {
4019         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4020         u8 tmp;
4021
4022         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4023                 return;
4024
4025         if (!drm_dp_is_branch(intel_dp->dpcd))
4026                 return;
4027
4028         tmp = intel_dp->has_hdmi_sink ?
4029                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4030
4031         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4032                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
4033                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
4034                             enableddisabled(intel_dp->has_hdmi_sink));
4035
4036         tmp = intel_dp->dfp.ycbcr_444_to_420 ?
4037                 DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4038
4039         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4040                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4041                 drm_dbg_kms(&i915->drm,
4042                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
4043                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
4044
4045         tmp = 0;
4046
4047         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4048                                DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
4049                 drm_dbg_kms(&i915->drm,
4050                             "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n",
4051                             enableddisabled(false));
4052 }
4053
4054 static void intel_enable_dp(struct intel_atomic_state *state,
4055                             struct intel_encoder *encoder,
4056                             const struct intel_crtc_state *pipe_config,
4057                             const struct drm_connector_state *conn_state)
4058 {
4059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4060         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4061         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4062         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
4063         enum pipe pipe = crtc->pipe;
4064         intel_wakeref_t wakeref;
4065
4066         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
4067                 return;
4068
4069         with_pps_lock(intel_dp, wakeref) {
4070                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4071                         vlv_init_panel_power_sequencer(encoder, pipe_config);
4072
4073                 intel_dp_enable_port(intel_dp, pipe_config);
4074
4075                 edp_panel_vdd_on(intel_dp);
4076                 edp_panel_on(intel_dp);
4077                 edp_panel_vdd_off(intel_dp, true);
4078         }
4079
4080         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4081                 unsigned int lane_mask = 0x0;
4082
4083                 if (IS_CHERRYVIEW(dev_priv))
4084                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
4085
4086                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
4087                                     lane_mask);
4088         }
4089
4090         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
4091         intel_dp_configure_protocol_converter(intel_dp);
4092         intel_dp_start_link_train(intel_dp, pipe_config);
4093         intel_dp_stop_link_train(intel_dp, pipe_config);
4094
4095         if (pipe_config->has_audio) {
4096                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
4097                         pipe_name(pipe));
4098                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
4099         }
4100 }
4101
4102 static void g4x_enable_dp(struct intel_atomic_state *state,
4103                           struct intel_encoder *encoder,
4104                           const struct intel_crtc_state *pipe_config,
4105                           const struct drm_connector_state *conn_state)
4106 {
4107         intel_enable_dp(state, encoder, pipe_config, conn_state);
4108         intel_edp_backlight_on(pipe_config, conn_state);
4109 }
4110
4111 static void vlv_enable_dp(struct intel_atomic_state *state,
4112                           struct intel_encoder *encoder,
4113                           const struct intel_crtc_state *pipe_config,
4114                           const struct drm_connector_state *conn_state)
4115 {
4116         intel_edp_backlight_on(pipe_config, conn_state);
4117 }
4118
4119 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
4120                               struct intel_encoder *encoder,
4121                               const struct intel_crtc_state *pipe_config,
4122                               const struct drm_connector_state *conn_state)
4123 {
4124         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4125         enum port port = encoder->port;
4126
4127         intel_dp_prepare(encoder, pipe_config);
4128
4129         /* Only ilk+ has port A */
4130         if (port == PORT_A)
4131                 ilk_edp_pll_on(intel_dp, pipe_config);
4132 }
4133
4134 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
4135 {
4136         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4137         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4138         enum pipe pipe = intel_dp->pps_pipe;
4139         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
4140
4141         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4142
4143         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
4144                 return;
4145
4146         edp_panel_vdd_off_sync(intel_dp);
4147
4148         /*
4149          * VLV seems to get confused when multiple power sequencers
4150          * have the same port selected (even if only one has power/vdd
4151          * enabled). The failure manifests as vlv_wait_port_ready() failing
4152          * CHV on the other hand doesn't seem to mind having the same port
4153          * selected in multiple power sequencers, but let's clear the
4154          * port select always when logically disconnecting a power sequencer
4155          * from a port.
4156          */
4157         drm_dbg_kms(&dev_priv->drm,
4158                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
4159                     pipe_name(pipe), dig_port->base.base.base.id,
4160                     dig_port->base.base.name);
4161         intel_de_write(dev_priv, pp_on_reg, 0);
4162         intel_de_posting_read(dev_priv, pp_on_reg);
4163
4164         intel_dp->pps_pipe = INVALID_PIPE;
4165 }
4166
4167 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
4168                                       enum pipe pipe)
4169 {
4170         struct intel_encoder *encoder;
4171
4172         lockdep_assert_held(&dev_priv->pps_mutex);
4173
4174         for_each_intel_dp(&dev_priv->drm, encoder) {
4175                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4176
4177                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
4178                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
4179                          pipe_name(pipe), encoder->base.base.id,
4180                          encoder->base.name);
4181
4182                 if (intel_dp->pps_pipe != pipe)
4183                         continue;
4184
4185                 drm_dbg_kms(&dev_priv->drm,
4186                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
4187                             pipe_name(pipe), encoder->base.base.id,
4188                             encoder->base.name);
4189
4190                 /* make sure vdd is off before we steal it */
4191                 vlv_detach_power_sequencer(intel_dp);
4192         }
4193 }
4194
4195 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
4196                                            const struct intel_crtc_state *crtc_state)
4197 {
4198         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4199         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4200         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4201
4202         lockdep_assert_held(&dev_priv->pps_mutex);
4203
4204         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4205
4206         if (intel_dp->pps_pipe != INVALID_PIPE &&
4207             intel_dp->pps_pipe != crtc->pipe) {
4208                 /*
4209                  * If another power sequencer was being used on this
4210                  * port previously make sure to turn off vdd there while
4211                  * we still have control of it.
4212                  */
4213                 vlv_detach_power_sequencer(intel_dp);
4214         }
4215
4216         /*
4217          * We may be stealing the power
4218          * sequencer from another port.
4219          */
4220         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
4221
4222         intel_dp->active_pipe = crtc->pipe;
4223
4224         if (!intel_dp_is_edp(intel_dp))
4225                 return;
4226
4227         /* now it's all ours */
4228         intel_dp->pps_pipe = crtc->pipe;
4229
4230         drm_dbg_kms(&dev_priv->drm,
4231                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
4232                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
4233                     encoder->base.name);
4234
4235         /* init power sequencer on this pipe and port */
4236         intel_dp_init_panel_power_sequencer(intel_dp);
4237         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
4238 }
4239
4240 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
4241                               struct intel_encoder *encoder,
4242                               const struct intel_crtc_state *pipe_config,
4243                               const struct drm_connector_state *conn_state)
4244 {
4245         vlv_phy_pre_encoder_enable(encoder, pipe_config);
4246
4247         intel_enable_dp(state, encoder, pipe_config, conn_state);
4248 }
4249
4250 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
4251                                   struct intel_encoder *encoder,
4252                                   const struct intel_crtc_state *pipe_config,
4253                                   const struct drm_connector_state *conn_state)
4254 {
4255         intel_dp_prepare(encoder, pipe_config);
4256
4257         vlv_phy_pre_pll_enable(encoder, pipe_config);
4258 }
4259
4260 static void chv_pre_enable_dp(struct intel_atomic_state *state,
4261                               struct intel_encoder *encoder,
4262                               const struct intel_crtc_state *pipe_config,
4263                               const struct drm_connector_state *conn_state)
4264 {
4265         chv_phy_pre_encoder_enable(encoder, pipe_config);
4266
4267         intel_enable_dp(state, encoder, pipe_config, conn_state);
4268
4269         /* Second common lane will stay alive on its own now */
4270         chv_phy_release_cl2_override(encoder);
4271 }
4272
4273 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4274                                   struct intel_encoder *encoder,
4275                                   const struct intel_crtc_state *pipe_config,
4276                                   const struct drm_connector_state *conn_state)
4277 {
4278         intel_dp_prepare(encoder, pipe_config);
4279
4280         chv_phy_pre_pll_enable(encoder, pipe_config);
4281 }
4282
4283 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4284                                     struct intel_encoder *encoder,
4285                                     const struct intel_crtc_state *old_crtc_state,
4286                                     const struct drm_connector_state *old_conn_state)
4287 {
4288         chv_phy_post_pll_disable(encoder, old_crtc_state);
4289 }
4290
4291 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
4292                                  const struct intel_crtc_state *crtc_state)
4293 {
4294         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4295 }
4296
4297 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
4298                                  const struct intel_crtc_state *crtc_state)
4299 {
4300         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4301 }
4302
4303 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
4304 {
4305         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4306 }
4307
4308 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
4309 {
4310         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4311 }
4312
4313 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
4314                                   const struct intel_crtc_state *crtc_state)
4315 {
4316         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4317         unsigned long demph_reg_value, preemph_reg_value,
4318                 uniqtranscale_reg_value;
4319         u8 train_set = intel_dp->train_set[0];
4320
4321         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4322         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4323                 preemph_reg_value = 0x0004000;
4324                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4325                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4326                         demph_reg_value = 0x2B405555;
4327                         uniqtranscale_reg_value = 0x552AB83A;
4328                         break;
4329                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4330                         demph_reg_value = 0x2B404040;
4331                         uniqtranscale_reg_value = 0x5548B83A;
4332                         break;
4333                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4334                         demph_reg_value = 0x2B245555;
4335                         uniqtranscale_reg_value = 0x5560B83A;
4336                         break;
4337                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4338                         demph_reg_value = 0x2B405555;
4339                         uniqtranscale_reg_value = 0x5598DA3A;
4340                         break;
4341                 default:
4342                         return;
4343                 }
4344                 break;
4345         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4346                 preemph_reg_value = 0x0002000;
4347                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4348                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4349                         demph_reg_value = 0x2B404040;
4350                         uniqtranscale_reg_value = 0x5552B83A;
4351                         break;
4352                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4353                         demph_reg_value = 0x2B404848;
4354                         uniqtranscale_reg_value = 0x5580B83A;
4355                         break;
4356                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4357                         demph_reg_value = 0x2B404040;
4358                         uniqtranscale_reg_value = 0x55ADDA3A;
4359                         break;
4360                 default:
4361                         return;
4362                 }
4363                 break;
4364         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4365                 preemph_reg_value = 0x0000000;
4366                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4367                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4368                         demph_reg_value = 0x2B305555;
4369                         uniqtranscale_reg_value = 0x5570B83A;
4370                         break;
4371                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4372                         demph_reg_value = 0x2B2B4040;
4373                         uniqtranscale_reg_value = 0x55ADDA3A;
4374                         break;
4375                 default:
4376                         return;
4377                 }
4378                 break;
4379         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4380                 preemph_reg_value = 0x0006000;
4381                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4382                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4383                         demph_reg_value = 0x1B405555;
4384                         uniqtranscale_reg_value = 0x55ADDA3A;
4385                         break;
4386                 default:
4387                         return;
4388                 }
4389                 break;
4390         default:
4391                 return;
4392         }
4393
4394         vlv_set_phy_signal_level(encoder, crtc_state,
4395                                  demph_reg_value, preemph_reg_value,
4396                                  uniqtranscale_reg_value, 0);
4397 }
4398
4399 static void chv_set_signal_levels(struct intel_dp *intel_dp,
4400                                   const struct intel_crtc_state *crtc_state)
4401 {
4402         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4403         u32 deemph_reg_value, margin_reg_value;
4404         bool uniq_trans_scale = false;
4405         u8 train_set = intel_dp->train_set[0];
4406
4407         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4408         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4409                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4410                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4411                         deemph_reg_value = 128;
4412                         margin_reg_value = 52;
4413                         break;
4414                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4415                         deemph_reg_value = 128;
4416                         margin_reg_value = 77;
4417                         break;
4418                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4419                         deemph_reg_value = 128;
4420                         margin_reg_value = 102;
4421                         break;
4422                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4423                         deemph_reg_value = 128;
4424                         margin_reg_value = 154;
4425                         uniq_trans_scale = true;
4426                         break;
4427                 default:
4428                         return;
4429                 }
4430                 break;
4431         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4432                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4433                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4434                         deemph_reg_value = 85;
4435                         margin_reg_value = 78;
4436                         break;
4437                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4438                         deemph_reg_value = 85;
4439                         margin_reg_value = 116;
4440                         break;
4441                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4442                         deemph_reg_value = 85;
4443                         margin_reg_value = 154;
4444                         break;
4445                 default:
4446                         return;
4447                 }
4448                 break;
4449         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4450                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4451                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4452                         deemph_reg_value = 64;
4453                         margin_reg_value = 104;
4454                         break;
4455                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4456                         deemph_reg_value = 64;
4457                         margin_reg_value = 154;
4458                         break;
4459                 default:
4460                         return;
4461                 }
4462                 break;
4463         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4464                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4465                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4466                         deemph_reg_value = 43;
4467                         margin_reg_value = 154;
4468                         break;
4469                 default:
4470                         return;
4471                 }
4472                 break;
4473         default:
4474                 return;
4475         }
4476
4477         chv_set_phy_signal_level(encoder, crtc_state,
4478                                  deemph_reg_value, margin_reg_value,
4479                                  uniq_trans_scale);
4480 }
4481
4482 static u32 g4x_signal_levels(u8 train_set)
4483 {
4484         u32 signal_levels = 0;
4485
4486         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4488         default:
4489                 signal_levels |= DP_VOLTAGE_0_4;
4490                 break;
4491         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4492                 signal_levels |= DP_VOLTAGE_0_6;
4493                 break;
4494         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4495                 signal_levels |= DP_VOLTAGE_0_8;
4496                 break;
4497         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4498                 signal_levels |= DP_VOLTAGE_1_2;
4499                 break;
4500         }
4501         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4502         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4503         default:
4504                 signal_levels |= DP_PRE_EMPHASIS_0;
4505                 break;
4506         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4507                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4508                 break;
4509         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4510                 signal_levels |= DP_PRE_EMPHASIS_6;
4511                 break;
4512         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4513                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4514                 break;
4515         }
4516         return signal_levels;
4517 }
4518
4519 static void
4520 g4x_set_signal_levels(struct intel_dp *intel_dp,
4521                       const struct intel_crtc_state *crtc_state)
4522 {
4523         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4524         u8 train_set = intel_dp->train_set[0];
4525         u32 signal_levels;
4526
4527         signal_levels = g4x_signal_levels(train_set);
4528
4529         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4530                     signal_levels);
4531
4532         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4533         intel_dp->DP |= signal_levels;
4534
4535         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4536         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4537 }
4538
4539 /* SNB CPU eDP voltage swing and pre-emphasis control */
4540 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4541 {
4542         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4543                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4544
4545         switch (signal_levels) {
4546         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4547         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4548                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4549         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4550                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4551         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4552         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4553                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4554         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4555         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4556                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4557         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4558         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4559                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4560         default:
4561                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4562                               "0x%x\n", signal_levels);
4563                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4564         }
4565 }
4566
4567 static void
4568 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4569                               const struct intel_crtc_state *crtc_state)
4570 {
4571         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4572         u8 train_set = intel_dp->train_set[0];
4573         u32 signal_levels;
4574
4575         signal_levels = snb_cpu_edp_signal_levels(train_set);
4576
4577         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4578                     signal_levels);
4579
4580         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4581         intel_dp->DP |= signal_levels;
4582
4583         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4584         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4585 }
4586
4587 /* IVB CPU eDP voltage swing and pre-emphasis control */
4588 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4589 {
4590         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4591                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4592
4593         switch (signal_levels) {
4594         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4595                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4596         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4597                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4598         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4599         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4600                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4601
4602         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4603                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4604         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4605                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4606
4607         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4608                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4609         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4610                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4611
4612         default:
4613                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4614                               "0x%x\n", signal_levels);
4615                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4616         }
4617 }
4618
4619 static void
4620 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4621                               const struct intel_crtc_state *crtc_state)
4622 {
4623         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4624         u8 train_set = intel_dp->train_set[0];
4625         u32 signal_levels;
4626
4627         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4628
4629         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4630                     signal_levels);
4631
4632         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4633         intel_dp->DP |= signal_levels;
4634
4635         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4636         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4637 }
4638
4639 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
4640                                 const struct intel_crtc_state *crtc_state)
4641 {
4642         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4643         u8 train_set = intel_dp->train_set[0];
4644
4645         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4646                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4647                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4648         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4649                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4650                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4651                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4652                     " (max)" : "");
4653
4654         intel_dp->set_signal_levels(intel_dp, crtc_state);
4655 }
4656
4657 void
4658 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4659                                        const struct intel_crtc_state *crtc_state,
4660                                        u8 dp_train_pat)
4661 {
4662         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4663
4664         if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
4665             DP_TRAINING_PATTERN_DISABLE)
4666                 drm_dbg_kms(&dev_priv->drm,
4667                             "Using DP training pattern TPS%d\n",
4668                             intel_dp_training_pattern_symbol(dp_train_pat));
4669
4670         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
4671 }
4672
4673 static void
4674 intel_dp_link_down(struct intel_encoder *encoder,
4675                    const struct intel_crtc_state *old_crtc_state)
4676 {
4677         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4678         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4679         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4680         enum port port = encoder->port;
4681         u32 DP = intel_dp->DP;
4682
4683         if (drm_WARN_ON(&dev_priv->drm,
4684                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4685                          DP_PORT_EN) == 0))
4686                 return;
4687
4688         drm_dbg_kms(&dev_priv->drm, "\n");
4689
4690         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4691             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4692                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4693                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4694         } else {
4695                 DP &= ~DP_LINK_TRAIN_MASK;
4696                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4697         }
4698         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4699         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4700
4701         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4702         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4703         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4704
4705         /*
4706          * HW workaround for IBX, we need to move the port
4707          * to transcoder A after disabling it to allow the
4708          * matching HDMI port to be enabled on transcoder A.
4709          */
4710         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4711                 /*
4712                  * We get CPU/PCH FIFO underruns on the other pipe when
4713                  * doing the workaround. Sweep them under the rug.
4714                  */
4715                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4716                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4717
4718                 /* always enable with pattern 1 (as per spec) */
4719                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4720                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4721                         DP_LINK_TRAIN_PAT_1;
4722                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4723                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4724
4725                 DP &= ~DP_PORT_EN;
4726                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4727                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4728
4729                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4730                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4731                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4732         }
4733
4734         msleep(intel_dp->panel_power_down_delay);
4735
4736         intel_dp->DP = DP;
4737
4738         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4739                 intel_wakeref_t wakeref;
4740
4741                 with_pps_lock(intel_dp, wakeref)
4742                         intel_dp->active_pipe = INVALID_PIPE;
4743         }
4744 }
4745
4746 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4747 {
4748         u8 dprx = 0;
4749
4750         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4751                               &dprx) != 1)
4752                 return false;
4753         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4754 }
4755
4756 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4757 {
4758         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4759
4760         /*
4761          * Clear the cached register set to avoid using stale values
4762          * for the sinks that do not support DSC.
4763          */
4764         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4765
4766         /* Clear fec_capable to avoid using stale values */
4767         intel_dp->fec_capable = 0;
4768
4769         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4770         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4771             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4772                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4773                                      intel_dp->dsc_dpcd,
4774                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4775                         drm_err(&i915->drm,
4776                                 "Failed to read DPCD register 0x%x\n",
4777                                 DP_DSC_SUPPORT);
4778
4779                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4780                             (int)sizeof(intel_dp->dsc_dpcd),
4781                             intel_dp->dsc_dpcd);
4782
4783                 /* FEC is supported only on DP 1.4 */
4784                 if (!intel_dp_is_edp(intel_dp) &&
4785                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4786                                       &intel_dp->fec_capable) < 0)
4787                         drm_err(&i915->drm,
4788                                 "Failed to read FEC DPCD register\n");
4789
4790                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4791                             intel_dp->fec_capable);
4792         }
4793 }
4794
4795 static bool
4796 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4797 {
4798         struct drm_i915_private *dev_priv =
4799                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4800
4801         /* this function is meant to be called only once */
4802         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4803
4804         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4805                 return false;
4806
4807         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4808                          drm_dp_is_branch(intel_dp->dpcd));
4809
4810         /*
4811          * Read the eDP display control registers.
4812          *
4813          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4814          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4815          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4816          * method). The display control registers should read zero if they're
4817          * not supported anyway.
4818          */
4819         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4820                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4821                              sizeof(intel_dp->edp_dpcd))
4822                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4823                             (int)sizeof(intel_dp->edp_dpcd),
4824                             intel_dp->edp_dpcd);
4825
4826         /*
4827          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4828          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4829          */
4830         intel_psr_init_dpcd(intel_dp);
4831
4832         /* Read the eDP 1.4+ supported link rates. */
4833         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4834                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4835                 int i;
4836
4837                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4838                                 sink_rates, sizeof(sink_rates));
4839
4840                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4841                         int val = le16_to_cpu(sink_rates[i]);
4842
4843                         if (val == 0)
4844                                 break;
4845
4846                         /* Value read multiplied by 200kHz gives the per-lane
4847                          * link rate in kHz. The source rates are, however,
4848                          * stored in terms of LS_Clk kHz. The full conversion
4849                          * back to symbols is
4850                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4851                          */
4852                         intel_dp->sink_rates[i] = (val * 200) / 10;
4853                 }
4854                 intel_dp->num_sink_rates = i;
4855         }
4856
4857         /*
4858          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4859          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4860          */
4861         if (intel_dp->num_sink_rates)
4862                 intel_dp->use_rate_select = true;
4863         else
4864                 intel_dp_set_sink_rates(intel_dp);
4865
4866         intel_dp_set_common_rates(intel_dp);
4867
4868         /* Read the eDP DSC DPCD registers */
4869         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4870                 intel_dp_get_dsc_sink_cap(intel_dp);
4871
4872         return true;
4873 }
4874
4875 static bool
4876 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4877 {
4878         if (!intel_dp->attached_connector)
4879                 return false;
4880
4881         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4882                                           intel_dp->dpcd,
4883                                           &intel_dp->desc);
4884 }
4885
4886 static bool
4887 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4888 {
4889         int ret;
4890
4891         intel_dp_lttpr_init(intel_dp);
4892
4893         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
4894                 return false;
4895
4896         /*
4897          * Don't clobber cached eDP rates. Also skip re-reading
4898          * the OUI/ID since we know it won't change.
4899          */
4900         if (!intel_dp_is_edp(intel_dp)) {
4901                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4902                                  drm_dp_is_branch(intel_dp->dpcd));
4903
4904                 intel_dp_set_sink_rates(intel_dp);
4905                 intel_dp_set_common_rates(intel_dp);
4906         }
4907
4908         if (intel_dp_has_sink_count(intel_dp)) {
4909                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4910                 if (ret < 0)
4911                         return false;
4912
4913                 /*
4914                  * Sink count can change between short pulse hpd hence
4915                  * a member variable in intel_dp will track any changes
4916                  * between short pulse interrupts.
4917                  */
4918                 intel_dp->sink_count = ret;
4919
4920                 /*
4921                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4922                  * a dongle is present but no display. Unless we require to know
4923                  * if a dongle is present or not, we don't need to update
4924                  * downstream port information. So, an early return here saves
4925                  * time from performing other operations which are not required.
4926                  */
4927                 if (!intel_dp->sink_count)
4928                         return false;
4929         }
4930
4931         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4932                                            intel_dp->downstream_ports) == 0;
4933 }
4934
4935 static bool
4936 intel_dp_can_mst(struct intel_dp *intel_dp)
4937 {
4938         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4939
4940         return i915->params.enable_dp_mst &&
4941                 intel_dp->can_mst &&
4942                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4943 }
4944
4945 static void
4946 intel_dp_configure_mst(struct intel_dp *intel_dp)
4947 {
4948         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4949         struct intel_encoder *encoder =
4950                 &dp_to_dig_port(intel_dp)->base;
4951         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4952
4953         drm_dbg_kms(&i915->drm,
4954                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4955                     encoder->base.base.id, encoder->base.name,
4956                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
4957                     yesno(i915->params.enable_dp_mst));
4958
4959         if (!intel_dp->can_mst)
4960                 return;
4961
4962         intel_dp->is_mst = sink_can_mst &&
4963                 i915->params.enable_dp_mst;
4964
4965         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4966                                         intel_dp->is_mst);
4967 }
4968
4969 static bool
4970 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4971 {
4972         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4973                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4974                 DP_DPRX_ESI_LEN;
4975 }
4976
4977 bool
4978 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4979                        const struct drm_connector_state *conn_state)
4980 {
4981         /*
4982          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4983          * of Color Encoding Format and Content Color Gamut], in order to
4984          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4985          */
4986         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4987                 return true;
4988
4989         switch (conn_state->colorspace) {
4990         case DRM_MODE_COLORIMETRY_SYCC_601:
4991         case DRM_MODE_COLORIMETRY_OPYCC_601:
4992         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4993         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4994         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4995                 return true;
4996         default:
4997                 break;
4998         }
4999
5000         return false;
5001 }
5002
5003 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
5004                                      struct dp_sdp *sdp, size_t size)
5005 {
5006         size_t length = sizeof(struct dp_sdp);
5007
5008         if (size < length)
5009                 return -ENOSPC;
5010
5011         memset(sdp, 0, size);
5012
5013         /*
5014          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
5015          * VSC SDP Header Bytes
5016          */
5017         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
5018         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
5019         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
5020         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
5021
5022         /*
5023          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
5024          * per DP 1.4a spec.
5025          */
5026         if (vsc->revision != 0x5)
5027                 goto out;
5028
5029         /* VSC SDP Payload for DB16 through DB18 */
5030         /* Pixel Encoding and Colorimetry Formats  */
5031         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
5032         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
5033
5034         switch (vsc->bpc) {
5035         case 6:
5036                 /* 6bpc: 0x0 */
5037                 break;
5038         case 8:
5039                 sdp->db[17] = 0x1; /* DB17[3:0] */
5040                 break;
5041         case 10:
5042                 sdp->db[17] = 0x2;
5043                 break;
5044         case 12:
5045                 sdp->db[17] = 0x3;
5046                 break;
5047         case 16:
5048                 sdp->db[17] = 0x4;
5049                 break;
5050         default:
5051                 MISSING_CASE(vsc->bpc);
5052                 break;
5053         }
5054         /* Dynamic Range and Component Bit Depth */
5055         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
5056                 sdp->db[17] |= 0x80;  /* DB17[7] */
5057
5058         /* Content Type */
5059         sdp->db[18] = vsc->content_type & 0x7;
5060
5061 out:
5062         return length;
5063 }
5064
5065 static ssize_t
5066 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
5067                                          struct dp_sdp *sdp,
5068                                          size_t size)
5069 {
5070         size_t length = sizeof(struct dp_sdp);
5071         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5072         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5073         ssize_t len;
5074
5075         if (size < length)
5076                 return -ENOSPC;
5077
5078         memset(sdp, 0, size);
5079
5080         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
5081         if (len < 0) {
5082                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
5083                 return -ENOSPC;
5084         }
5085
5086         if (len != infoframe_size) {
5087                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
5088                 return -ENOSPC;
5089         }
5090
5091         /*
5092          * Set up the infoframe sdp packet for HDR static metadata.
5093          * Prepare VSC Header for SU as per DP 1.4a spec,
5094          * Table 2-100 and Table 2-101
5095          */
5096
5097         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
5098         sdp->sdp_header.HB0 = 0;
5099         /*
5100          * Packet Type 80h + Non-audio INFOFRAME Type value
5101          * HDMI_INFOFRAME_TYPE_DRM: 0x87
5102          * - 80h + Non-audio INFOFRAME Type value
5103          * - InfoFrame Type: 0x07
5104          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
5105          */
5106         sdp->sdp_header.HB1 = drm_infoframe->type;
5107         /*
5108          * Least Significant Eight Bits of (Data Byte Count – 1)
5109          * infoframe_size - 1
5110          */
5111         sdp->sdp_header.HB2 = 0x1D;
5112         /* INFOFRAME SDP Version Number */
5113         sdp->sdp_header.HB3 = (0x13 << 2);
5114         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5115         sdp->db[0] = drm_infoframe->version;
5116         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5117         sdp->db[1] = drm_infoframe->length;
5118         /*
5119          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5120          * HDMI_INFOFRAME_HEADER_SIZE
5121          */
5122         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5123         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5124                HDMI_DRM_INFOFRAME_SIZE);
5125
5126         /*
5127          * Size of DP infoframe sdp packet for HDR static metadata consists of
5128          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5129          * - Two Data Blocks: 2 bytes
5130          *    CTA Header Byte2 (INFOFRAME Version Number)
5131          *    CTA Header Byte3 (Length of INFOFRAME)
5132          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5133          *
5134          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5135          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5136          * will pad rest of the size.
5137          */
5138         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
5139 }
5140
5141 static void intel_write_dp_sdp(struct intel_encoder *encoder,
5142                                const struct intel_crtc_state *crtc_state,
5143                                unsigned int type)
5144 {
5145         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5147         struct dp_sdp sdp = {};
5148         ssize_t len;
5149
5150         if ((crtc_state->infoframes.enable &
5151              intel_hdmi_infoframe_enable(type)) == 0)
5152                 return;
5153
5154         switch (type) {
5155         case DP_SDP_VSC:
5156                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
5157                                             sizeof(sdp));
5158                 break;
5159         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5160                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
5161                                                                &sdp, sizeof(sdp));
5162                 break;
5163         default:
5164                 MISSING_CASE(type);
5165                 return;
5166         }
5167
5168         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5169                 return;
5170
5171         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
5172 }
5173
5174 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
5175                             const struct intel_crtc_state *crtc_state,
5176                             struct drm_dp_vsc_sdp *vsc)
5177 {
5178         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5180         struct dp_sdp sdp = {};
5181         ssize_t len;
5182
5183         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
5184
5185         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5186                 return;
5187
5188         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5189                                         &sdp, len);
5190 }
5191
5192 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5193                              bool enable,
5194                              const struct intel_crtc_state *crtc_state,
5195                              const struct drm_connector_state *conn_state)
5196 {
5197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5198         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5199         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5200         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5201                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5202                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5203         u32 val = intel_de_read(dev_priv, reg);
5204
5205         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5206         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5207         if (intel_psr_enabled(intel_dp))
5208                 val &= ~dip_enable;
5209         else
5210                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5211
5212         if (!enable) {
5213                 intel_de_write(dev_priv, reg, val);
5214                 intel_de_posting_read(dev_priv, reg);
5215                 return;
5216         }
5217
5218         intel_de_write(dev_priv, reg, val);
5219         intel_de_posting_read(dev_priv, reg);
5220
5221         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5222         if (!intel_psr_enabled(intel_dp))
5223                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5224
5225         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5226 }
5227
5228 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5229                                    const void *buffer, size_t size)
5230 {
5231         const struct dp_sdp *sdp = buffer;
5232
5233         if (size < sizeof(struct dp_sdp))
5234                 return -EINVAL;
5235
5236         memset(vsc, 0, size);
5237
5238         if (sdp->sdp_header.HB0 != 0)
5239                 return -EINVAL;
5240
5241         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5242                 return -EINVAL;
5243
5244         vsc->sdp_type = sdp->sdp_header.HB1;
5245         vsc->revision = sdp->sdp_header.HB2;
5246         vsc->length = sdp->sdp_header.HB3;
5247
5248         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5249             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5250                 /*
5251                  * - HB2 = 0x2, HB3 = 0x8
5252                  *   VSC SDP supporting 3D stereo + PSR
5253                  * - HB2 = 0x4, HB3 = 0xe
5254                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5255                  *   first scan line of the SU region (applies to eDP v1.4b
5256                  *   and higher).
5257                  */
5258                 return 0;
5259         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5260                 /*
5261                  * - HB2 = 0x5, HB3 = 0x13
5262                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5263                  *   Format.
5264                  */
5265                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5266                 vsc->colorimetry = sdp->db[16] & 0xf;
5267                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5268
5269                 switch (sdp->db[17] & 0x7) {
5270                 case 0x0:
5271                         vsc->bpc = 6;
5272                         break;
5273                 case 0x1:
5274                         vsc->bpc = 8;
5275                         break;
5276                 case 0x2:
5277                         vsc->bpc = 10;
5278                         break;
5279                 case 0x3:
5280                         vsc->bpc = 12;
5281                         break;
5282                 case 0x4:
5283                         vsc->bpc = 16;
5284                         break;
5285                 default:
5286                         MISSING_CASE(sdp->db[17] & 0x7);
5287                         return -EINVAL;
5288                 }
5289
5290                 vsc->content_type = sdp->db[18] & 0x7;
5291         } else {
5292                 return -EINVAL;
5293         }
5294
5295         return 0;
5296 }
5297
5298 static int
5299 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5300                                            const void *buffer, size_t size)
5301 {
5302         int ret;
5303
5304         const struct dp_sdp *sdp = buffer;
5305
5306         if (size < sizeof(struct dp_sdp))
5307                 return -EINVAL;
5308
5309         if (sdp->sdp_header.HB0 != 0)
5310                 return -EINVAL;
5311
5312         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5313                 return -EINVAL;
5314
5315         /*
5316          * Least Significant Eight Bits of (Data Byte Count – 1)
5317          * 1Dh (i.e., Data Byte Count = 30 bytes).
5318          */
5319         if (sdp->sdp_header.HB2 != 0x1D)
5320                 return -EINVAL;
5321
5322         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5323         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5324                 return -EINVAL;
5325
5326         /* INFOFRAME SDP Version Number */
5327         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5328                 return -EINVAL;
5329
5330         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5331         if (sdp->db[0] != 1)
5332                 return -EINVAL;
5333
5334         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5335         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5336                 return -EINVAL;
5337
5338         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5339                                              HDMI_DRM_INFOFRAME_SIZE);
5340
5341         return ret;
5342 }
5343
5344 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5345                                   struct intel_crtc_state *crtc_state,
5346                                   struct drm_dp_vsc_sdp *vsc)
5347 {
5348         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5349         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5351         unsigned int type = DP_SDP_VSC;
5352         struct dp_sdp sdp = {};
5353         int ret;
5354
5355         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5356         if (intel_psr_enabled(intel_dp))
5357                 return;
5358
5359         if ((crtc_state->infoframes.enable &
5360              intel_hdmi_infoframe_enable(type)) == 0)
5361                 return;
5362
5363         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5364
5365         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5366
5367         if (ret)
5368                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5369 }
5370
5371 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5372                                                      struct intel_crtc_state *crtc_state,
5373                                                      struct hdmi_drm_infoframe *drm_infoframe)
5374 {
5375         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5377         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5378         struct dp_sdp sdp = {};
5379         int ret;
5380
5381         if ((crtc_state->infoframes.enable &
5382             intel_hdmi_infoframe_enable(type)) == 0)
5383                 return;
5384
5385         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5386                                  sizeof(sdp));
5387
5388         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5389                                                          sizeof(sdp));
5390
5391         if (ret)
5392                 drm_dbg_kms(&dev_priv->drm,
5393                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5394 }
5395
5396 void intel_read_dp_sdp(struct intel_encoder *encoder,
5397                        struct intel_crtc_state *crtc_state,
5398                        unsigned int type)
5399 {
5400         if (encoder->type != INTEL_OUTPUT_DDI)
5401                 return;
5402
5403         switch (type) {
5404         case DP_SDP_VSC:
5405                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5406                                       &crtc_state->infoframes.vsc);
5407                 break;
5408         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5409                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5410                                                          &crtc_state->infoframes.drm.drm);
5411                 break;
5412         default:
5413                 MISSING_CASE(type);
5414                 break;
5415         }
5416 }
5417
5418 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5419 {
5420         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5421         int status = 0;
5422         int test_link_rate;
5423         u8 test_lane_count, test_link_bw;
5424         /* (DP CTS 1.2)
5425          * 4.3.1.11
5426          */
5427         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5428         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5429                                    &test_lane_count);
5430
5431         if (status <= 0) {
5432                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5433                 return DP_TEST_NAK;
5434         }
5435         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5436
5437         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5438                                    &test_link_bw);
5439         if (status <= 0) {
5440                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5441                 return DP_TEST_NAK;
5442         }
5443         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5444
5445         /* Validate the requested link rate and lane count */
5446         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5447                                         test_lane_count))
5448                 return DP_TEST_NAK;
5449
5450         intel_dp->compliance.test_lane_count = test_lane_count;
5451         intel_dp->compliance.test_link_rate = test_link_rate;
5452
5453         return DP_TEST_ACK;
5454 }
5455
5456 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5457 {
5458         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5459         u8 test_pattern;
5460         u8 test_misc;
5461         __be16 h_width, v_height;
5462         int status = 0;
5463
5464         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5465         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5466                                    &test_pattern);
5467         if (status <= 0) {
5468                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5469                 return DP_TEST_NAK;
5470         }
5471         if (test_pattern != DP_COLOR_RAMP)
5472                 return DP_TEST_NAK;
5473
5474         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5475                                   &h_width, 2);
5476         if (status <= 0) {
5477                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5478                 return DP_TEST_NAK;
5479         }
5480
5481         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5482                                   &v_height, 2);
5483         if (status <= 0) {
5484                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5485                 return DP_TEST_NAK;
5486         }
5487
5488         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5489                                    &test_misc);
5490         if (status <= 0) {
5491                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5492                 return DP_TEST_NAK;
5493         }
5494         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5495                 return DP_TEST_NAK;
5496         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5497                 return DP_TEST_NAK;
5498         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5499         case DP_TEST_BIT_DEPTH_6:
5500                 intel_dp->compliance.test_data.bpc = 6;
5501                 break;
5502         case DP_TEST_BIT_DEPTH_8:
5503                 intel_dp->compliance.test_data.bpc = 8;
5504                 break;
5505         default:
5506                 return DP_TEST_NAK;
5507         }
5508
5509         intel_dp->compliance.test_data.video_pattern = test_pattern;
5510         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5511         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5512         /* Set test active flag here so userspace doesn't interrupt things */
5513         intel_dp->compliance.test_active = true;
5514
5515         return DP_TEST_ACK;
5516 }
5517
5518 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5519 {
5520         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5521         u8 test_result = DP_TEST_ACK;
5522         struct intel_connector *intel_connector = intel_dp->attached_connector;
5523         struct drm_connector *connector = &intel_connector->base;
5524
5525         if (intel_connector->detect_edid == NULL ||
5526             connector->edid_corrupt ||
5527             intel_dp->aux.i2c_defer_count > 6) {
5528                 /* Check EDID read for NACKs, DEFERs and corruption
5529                  * (DP CTS 1.2 Core r1.1)
5530                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5531                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5532                  *    4.2.2.6 : EDID corruption detected
5533                  * Use failsafe mode for all cases
5534                  */
5535                 if (intel_dp->aux.i2c_nack_count > 0 ||
5536                         intel_dp->aux.i2c_defer_count > 0)
5537                         drm_dbg_kms(&i915->drm,
5538                                     "EDID read had %d NACKs, %d DEFERs\n",
5539                                     intel_dp->aux.i2c_nack_count,
5540                                     intel_dp->aux.i2c_defer_count);
5541                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5542         } else {
5543                 struct edid *block = intel_connector->detect_edid;
5544
5545                 /* We have to write the checksum
5546                  * of the last block read
5547                  */
5548                 block += intel_connector->detect_edid->extensions;
5549
5550                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5551                                        block->checksum) <= 0)
5552                         drm_dbg_kms(&i915->drm,
5553                                     "Failed to write EDID checksum\n");
5554
5555                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5556                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5557         }
5558
5559         /* Set test active flag here so userspace doesn't interrupt things */
5560         intel_dp->compliance.test_active = true;
5561
5562         return test_result;
5563 }
5564
5565 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
5566                                         const struct intel_crtc_state *crtc_state)
5567 {
5568         struct drm_i915_private *dev_priv =
5569                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5570         struct drm_dp_phy_test_params *data =
5571                         &intel_dp->compliance.test_data.phytest;
5572         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5573         enum pipe pipe = crtc->pipe;
5574         u32 pattern_val;
5575
5576         switch (data->phy_pattern) {
5577         case DP_PHY_TEST_PATTERN_NONE:
5578                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5579                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5580                 break;
5581         case DP_PHY_TEST_PATTERN_D10_2:
5582                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5583                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5584                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5585                 break;
5586         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5587                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5588                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5589                                DDI_DP_COMP_CTL_ENABLE |
5590                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5591                 break;
5592         case DP_PHY_TEST_PATTERN_PRBS7:
5593                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5594                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5595                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5596                 break;
5597         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5598                 /*
5599                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5600                  * current firmware of DPR-100 could not set it, so hardcoding
5601                  * now for complaince test.
5602                  */
5603                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5604                 pattern_val = 0x3e0f83e0;
5605                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5606                 pattern_val = 0x0f83e0f8;
5607                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5608                 pattern_val = 0x0000f83e;
5609                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5610                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5611                                DDI_DP_COMP_CTL_ENABLE |
5612                                DDI_DP_COMP_CTL_CUSTOM80);
5613                 break;
5614         case DP_PHY_TEST_PATTERN_CP2520:
5615                 /*
5616                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5617                  * current firmware of DPR-100 could not set it, so hardcoding
5618                  * now for complaince test.
5619                  */
5620                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5621                 pattern_val = 0xFB;
5622                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5623                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5624                                pattern_val);
5625                 break;
5626         default:
5627                 WARN(1, "Invalid Phy Test Pattern\n");
5628         }
5629 }
5630
5631 static void
5632 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
5633                                   const struct intel_crtc_state *crtc_state)
5634 {
5635         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5636         struct drm_device *dev = dig_port->base.base.dev;
5637         struct drm_i915_private *dev_priv = to_i915(dev);
5638         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5639         enum pipe pipe = crtc->pipe;
5640         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5641
5642         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5643                                                  TRANS_DDI_FUNC_CTL(pipe));
5644         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5645         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5646
5647         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5648                                       TGL_TRANS_DDI_PORT_MASK);
5649         trans_conf_value &= ~PIPECONF_ENABLE;
5650         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5651
5652         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5653         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5654                        trans_ddi_func_ctl_value);
5655         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5656 }
5657
5658 static void
5659 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
5660                                  const struct intel_crtc_state *crtc_state)
5661 {
5662         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5663         struct drm_device *dev = dig_port->base.base.dev;
5664         struct drm_i915_private *dev_priv = to_i915(dev);
5665         enum port port = dig_port->base.port;
5666         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5667         enum pipe pipe = crtc->pipe;
5668         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5669
5670         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5671                                                  TRANS_DDI_FUNC_CTL(pipe));
5672         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5673         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5674
5675         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5676                                     TGL_TRANS_DDI_SELECT_PORT(port);
5677         trans_conf_value |= PIPECONF_ENABLE;
5678         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5679
5680         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5681         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5682         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5683                        trans_ddi_func_ctl_value);
5684 }
5685
5686 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
5687                                          const struct intel_crtc_state *crtc_state)
5688 {
5689         struct drm_dp_phy_test_params *data =
5690                 &intel_dp->compliance.test_data.phytest;
5691         u8 link_status[DP_LINK_STATUS_SIZE];
5692
5693         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5694                                              link_status) < 0) {
5695                 DRM_DEBUG_KMS("failed to get link status\n");
5696                 return;
5697         }
5698
5699         /* retrieve vswing & pre-emphasis setting */
5700         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
5701                                   link_status);
5702
5703         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
5704
5705         intel_dp_set_signal_levels(intel_dp, crtc_state);
5706
5707         intel_dp_phy_pattern_update(intel_dp, crtc_state);
5708
5709         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
5710
5711         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5712                                     link_status[DP_DPCD_REV]);
5713 }
5714
5715 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5716 {
5717         struct drm_dp_phy_test_params *data =
5718                 &intel_dp->compliance.test_data.phytest;
5719
5720         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5721                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5722                 return DP_TEST_NAK;
5723         }
5724
5725         /* Set test active flag here so userspace doesn't interrupt things */
5726         intel_dp->compliance.test_active = true;
5727
5728         return DP_TEST_ACK;
5729 }
5730
5731 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5732 {
5733         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5734         u8 response = DP_TEST_NAK;
5735         u8 request = 0;
5736         int status;
5737
5738         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5739         if (status <= 0) {
5740                 drm_dbg_kms(&i915->drm,
5741                             "Could not read test request from sink\n");
5742                 goto update_status;
5743         }
5744
5745         switch (request) {
5746         case DP_TEST_LINK_TRAINING:
5747                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5748                 response = intel_dp_autotest_link_training(intel_dp);
5749                 break;
5750         case DP_TEST_LINK_VIDEO_PATTERN:
5751                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5752                 response = intel_dp_autotest_video_pattern(intel_dp);
5753                 break;
5754         case DP_TEST_LINK_EDID_READ:
5755                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5756                 response = intel_dp_autotest_edid(intel_dp);
5757                 break;
5758         case DP_TEST_LINK_PHY_TEST_PATTERN:
5759                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5760                 response = intel_dp_autotest_phy_pattern(intel_dp);
5761                 break;
5762         default:
5763                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5764                             request);
5765                 break;
5766         }
5767
5768         if (response & DP_TEST_ACK)
5769                 intel_dp->compliance.test_type = request;
5770
5771 update_status:
5772         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5773         if (status <= 0)
5774                 drm_dbg_kms(&i915->drm,
5775                             "Could not write test response to sink\n");
5776 }
5777
5778 /**
5779  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5780  * @intel_dp: Intel DP struct
5781  *
5782  * Read any pending MST interrupts, call MST core to handle these and ack the
5783  * interrupts. Check if the main and AUX link state is ok.
5784  *
5785  * Returns:
5786  * - %true if pending interrupts were serviced (or no interrupts were
5787  *   pending) w/o detecting an error condition.
5788  * - %false if an error condition - like AUX failure or a loss of link - is
5789  *   detected, which needs servicing from the hotplug work.
5790  */
5791 static bool
5792 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5793 {
5794         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5795         bool link_ok = true;
5796
5797         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5798
5799         for (;;) {
5800                 u8 esi[DP_DPRX_ESI_LEN] = {};
5801                 bool handled;
5802                 int retry;
5803
5804                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5805                         drm_dbg_kms(&i915->drm,
5806                                     "failed to get ESI - device may have failed\n");
5807                         link_ok = false;
5808
5809                         break;
5810                 }
5811
5812                 /* check link status - esi[10] = 0x200c */
5813                 if (intel_dp->active_mst_links > 0 && link_ok &&
5814                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5815                         drm_dbg_kms(&i915->drm,
5816                                     "channel EQ not ok, retraining\n");
5817                         link_ok = false;
5818                 }
5819
5820                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5821
5822                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5823                 if (!handled)
5824                         break;
5825
5826                 for (retry = 0; retry < 3; retry++) {
5827                         int wret;
5828
5829                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5830                                                  DP_SINK_COUNT_ESI+1,
5831                                                  &esi[1], 3);
5832                         if (wret == 3)
5833                                 break;
5834                 }
5835         }
5836
5837         return link_ok;
5838 }
5839
5840 static bool
5841 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5842 {
5843         u8 link_status[DP_LINK_STATUS_SIZE];
5844
5845         if (!intel_dp->link_trained)
5846                 return false;
5847
5848         /*
5849          * While PSR source HW is enabled, it will control main-link sending
5850          * frames, enabling and disabling it so trying to do a retrain will fail
5851          * as the link would or not be on or it could mix training patterns
5852          * and frame data at the same time causing retrain to fail.
5853          * Also when exiting PSR, HW will retrain the link anyways fixing
5854          * any link status error.
5855          */
5856         if (intel_psr_enabled(intel_dp))
5857                 return false;
5858
5859         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5860                                              link_status) < 0)
5861                 return false;
5862
5863         /*
5864          * Validate the cached values of intel_dp->link_rate and
5865          * intel_dp->lane_count before attempting to retrain.
5866          *
5867          * FIXME would be nice to user the crtc state here, but since
5868          * we need to call this from the short HPD handler that seems
5869          * a bit hard.
5870          */
5871         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5872                                         intel_dp->lane_count))
5873                 return false;
5874
5875         /* Retrain if Channel EQ or CR not ok */
5876         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5877 }
5878
5879 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5880                                    const struct drm_connector_state *conn_state)
5881 {
5882         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5883         struct intel_encoder *encoder;
5884         enum pipe pipe;
5885
5886         if (!conn_state->best_encoder)
5887                 return false;
5888
5889         /* SST */
5890         encoder = &dp_to_dig_port(intel_dp)->base;
5891         if (conn_state->best_encoder == &encoder->base)
5892                 return true;
5893
5894         /* MST */
5895         for_each_pipe(i915, pipe) {
5896                 encoder = &intel_dp->mst_encoders[pipe]->base;
5897                 if (conn_state->best_encoder == &encoder->base)
5898                         return true;
5899         }
5900
5901         return false;
5902 }
5903
5904 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5905                                       struct drm_modeset_acquire_ctx *ctx,
5906                                       u32 *crtc_mask)
5907 {
5908         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5909         struct drm_connector_list_iter conn_iter;
5910         struct intel_connector *connector;
5911         int ret = 0;
5912
5913         *crtc_mask = 0;
5914
5915         if (!intel_dp_needs_link_retrain(intel_dp))
5916                 return 0;
5917
5918         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5919         for_each_intel_connector_iter(connector, &conn_iter) {
5920                 struct drm_connector_state *conn_state =
5921                         connector->base.state;
5922                 struct intel_crtc_state *crtc_state;
5923                 struct intel_crtc *crtc;
5924
5925                 if (!intel_dp_has_connector(intel_dp, conn_state))
5926                         continue;
5927
5928                 crtc = to_intel_crtc(conn_state->crtc);
5929                 if (!crtc)
5930                         continue;
5931
5932                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5933                 if (ret)
5934                         break;
5935
5936                 crtc_state = to_intel_crtc_state(crtc->base.state);
5937
5938                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5939
5940                 if (!crtc_state->hw.active)
5941                         continue;
5942
5943                 if (conn_state->commit &&
5944                     !try_wait_for_completion(&conn_state->commit->hw_done))
5945                         continue;
5946
5947                 *crtc_mask |= drm_crtc_mask(&crtc->base);
5948         }
5949         drm_connector_list_iter_end(&conn_iter);
5950
5951         if (!intel_dp_needs_link_retrain(intel_dp))
5952                 *crtc_mask = 0;
5953
5954         return ret;
5955 }
5956
5957 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5958 {
5959         struct intel_connector *connector = intel_dp->attached_connector;
5960
5961         return connector->base.status == connector_status_connected ||
5962                 intel_dp->is_mst;
5963 }
5964
5965 int intel_dp_retrain_link(struct intel_encoder *encoder,
5966                           struct drm_modeset_acquire_ctx *ctx)
5967 {
5968         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5969         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5970         struct intel_crtc *crtc;
5971         u32 crtc_mask;
5972         int ret;
5973
5974         if (!intel_dp_is_connected(intel_dp))
5975                 return 0;
5976
5977         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5978                                ctx);
5979         if (ret)
5980                 return ret;
5981
5982         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5983         if (ret)
5984                 return ret;
5985
5986         if (crtc_mask == 0)
5987                 return 0;
5988
5989         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5990                     encoder->base.base.id, encoder->base.name);
5991
5992         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5993                 const struct intel_crtc_state *crtc_state =
5994                         to_intel_crtc_state(crtc->base.state);
5995
5996                 /* Suppress underruns caused by re-training */
5997                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5998                 if (crtc_state->has_pch_encoder)
5999                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6000                                                               intel_crtc_pch_transcoder(crtc), false);
6001         }
6002
6003         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6004                 const struct intel_crtc_state *crtc_state =
6005                         to_intel_crtc_state(crtc->base.state);
6006
6007                 /* retrain on the MST master transcoder */
6008                 if (INTEL_GEN(dev_priv) >= 12 &&
6009                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6010                     !intel_dp_mst_is_master_trans(crtc_state))
6011                         continue;
6012
6013                 intel_dp_start_link_train(intel_dp, crtc_state);
6014                 intel_dp_stop_link_train(intel_dp, crtc_state);
6015                 break;
6016         }
6017
6018         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6019                 const struct intel_crtc_state *crtc_state =
6020                         to_intel_crtc_state(crtc->base.state);
6021
6022                 /* Keep underrun reporting disabled until things are stable */
6023                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6024
6025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6026                 if (crtc_state->has_pch_encoder)
6027                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6028                                                               intel_crtc_pch_transcoder(crtc), true);
6029         }
6030
6031         return 0;
6032 }
6033
6034 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
6035                                   struct drm_modeset_acquire_ctx *ctx,
6036                                   u32 *crtc_mask)
6037 {
6038         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6039         struct drm_connector_list_iter conn_iter;
6040         struct intel_connector *connector;
6041         int ret = 0;
6042
6043         *crtc_mask = 0;
6044
6045         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6046         for_each_intel_connector_iter(connector, &conn_iter) {
6047                 struct drm_connector_state *conn_state =
6048                         connector->base.state;
6049                 struct intel_crtc_state *crtc_state;
6050                 struct intel_crtc *crtc;
6051
6052                 if (!intel_dp_has_connector(intel_dp, conn_state))
6053                         continue;
6054
6055                 crtc = to_intel_crtc(conn_state->crtc);
6056                 if (!crtc)
6057                         continue;
6058
6059                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6060                 if (ret)
6061                         break;
6062
6063                 crtc_state = to_intel_crtc_state(crtc->base.state);
6064
6065                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6066
6067                 if (!crtc_state->hw.active)
6068                         continue;
6069
6070                 if (conn_state->commit &&
6071                     !try_wait_for_completion(&conn_state->commit->hw_done))
6072                         continue;
6073
6074                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6075         }
6076         drm_connector_list_iter_end(&conn_iter);
6077
6078         return ret;
6079 }
6080
6081 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
6082                                 struct drm_modeset_acquire_ctx *ctx)
6083 {
6084         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6085         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6086         struct intel_crtc *crtc;
6087         u32 crtc_mask;
6088         int ret;
6089
6090         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6091                                ctx);
6092         if (ret)
6093                 return ret;
6094
6095         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
6096         if (ret)
6097                 return ret;
6098
6099         if (crtc_mask == 0)
6100                 return 0;
6101
6102         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
6103                     encoder->base.base.id, encoder->base.name);
6104
6105         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6106                 const struct intel_crtc_state *crtc_state =
6107                         to_intel_crtc_state(crtc->base.state);
6108
6109                 /* test on the MST master transcoder */
6110                 if (INTEL_GEN(dev_priv) >= 12 &&
6111                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6112                     !intel_dp_mst_is_master_trans(crtc_state))
6113                         continue;
6114
6115                 intel_dp_process_phy_request(intel_dp, crtc_state);
6116                 break;
6117         }
6118
6119         return 0;
6120 }
6121
6122 static void intel_dp_phy_test(struct intel_encoder *encoder)
6123 {
6124         struct drm_modeset_acquire_ctx ctx;
6125         int ret;
6126
6127         drm_modeset_acquire_init(&ctx, 0);
6128
6129         for (;;) {
6130                 ret = intel_dp_do_phy_test(encoder, &ctx);
6131
6132                 if (ret == -EDEADLK) {
6133                         drm_modeset_backoff(&ctx);
6134                         continue;
6135                 }
6136
6137                 break;
6138         }
6139
6140         drm_modeset_drop_locks(&ctx);
6141         drm_modeset_acquire_fini(&ctx);
6142         drm_WARN(encoder->base.dev, ret,
6143                  "Acquiring modeset locks failed with %i\n", ret);
6144 }
6145
6146 /*
6147  * If display is now connected check links status,
6148  * there has been known issues of link loss triggering
6149  * long pulse.
6150  *
6151  * Some sinks (eg. ASUS PB287Q) seem to perform some
6152  * weird HPD ping pong during modesets. So we can apparently
6153  * end up with HPD going low during a modeset, and then
6154  * going back up soon after. And once that happens we must
6155  * retrain the link to get a picture. That's in case no
6156  * userspace component reacted to intermittent HPD dip.
6157  */
6158 static enum intel_hotplug_state
6159 intel_dp_hotplug(struct intel_encoder *encoder,
6160                  struct intel_connector *connector)
6161 {
6162         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6163         struct drm_modeset_acquire_ctx ctx;
6164         enum intel_hotplug_state state;
6165         int ret;
6166
6167         if (intel_dp->compliance.test_active &&
6168             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
6169                 intel_dp_phy_test(encoder);
6170                 /* just do the PHY test and nothing else */
6171                 return INTEL_HOTPLUG_UNCHANGED;
6172         }
6173
6174         state = intel_encoder_hotplug(encoder, connector);
6175
6176         drm_modeset_acquire_init(&ctx, 0);
6177
6178         for (;;) {
6179                 ret = intel_dp_retrain_link(encoder, &ctx);
6180
6181                 if (ret == -EDEADLK) {
6182                         drm_modeset_backoff(&ctx);
6183                         continue;
6184                 }
6185
6186                 break;
6187         }
6188
6189         drm_modeset_drop_locks(&ctx);
6190         drm_modeset_acquire_fini(&ctx);
6191         drm_WARN(encoder->base.dev, ret,
6192                  "Acquiring modeset locks failed with %i\n", ret);
6193
6194         /*
6195          * Keeping it consistent with intel_ddi_hotplug() and
6196          * intel_hdmi_hotplug().
6197          */
6198         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
6199                 state = INTEL_HOTPLUG_RETRY;
6200
6201         return state;
6202 }
6203
6204 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
6205 {
6206         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6207         u8 val;
6208
6209         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6210                 return;
6211
6212         if (drm_dp_dpcd_readb(&intel_dp->aux,
6213                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
6214                 return;
6215
6216         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
6217
6218         if (val & DP_AUTOMATED_TEST_REQUEST)
6219                 intel_dp_handle_test_request(intel_dp);
6220
6221         if (val & DP_CP_IRQ)
6222                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
6223
6224         if (val & DP_SINK_SPECIFIC_IRQ)
6225                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
6226 }
6227
6228 /*
6229  * According to DP spec
6230  * 5.1.2:
6231  *  1. Read DPCD
6232  *  2. Configure link according to Receiver Capabilities
6233  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
6234  *  4. Check link status on receipt of hot-plug interrupt
6235  *
6236  * intel_dp_short_pulse -  handles short pulse interrupts
6237  * when full detection is not required.
6238  * Returns %true if short pulse is handled and full detection
6239  * is NOT required and %false otherwise.
6240  */
6241 static bool
6242 intel_dp_short_pulse(struct intel_dp *intel_dp)
6243 {
6244         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6245         u8 old_sink_count = intel_dp->sink_count;
6246         bool ret;
6247
6248         /*
6249          * Clearing compliance test variables to allow capturing
6250          * of values for next automated test request.
6251          */
6252         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6253
6254         /*
6255          * Now read the DPCD to see if it's actually running
6256          * If the current value of sink count doesn't match with
6257          * the value that was stored earlier or dpcd read failed
6258          * we need to do full detection
6259          */
6260         ret = intel_dp_get_dpcd(intel_dp);
6261
6262         if ((old_sink_count != intel_dp->sink_count) || !ret) {
6263                 /* No need to proceed if we are going to do full detect */
6264                 return false;
6265         }
6266
6267         intel_dp_check_service_irq(intel_dp);
6268
6269         /* Handle CEC interrupts, if any */
6270         drm_dp_cec_irq(&intel_dp->aux);
6271
6272         /* defer to the hotplug work for link retraining if needed */
6273         if (intel_dp_needs_link_retrain(intel_dp))
6274                 return false;
6275
6276         intel_psr_short_pulse(intel_dp);
6277
6278         switch (intel_dp->compliance.test_type) {
6279         case DP_TEST_LINK_TRAINING:
6280                 drm_dbg_kms(&dev_priv->drm,
6281                             "Link Training Compliance Test requested\n");
6282                 /* Send a Hotplug Uevent to userspace to start modeset */
6283                 drm_kms_helper_hotplug_event(&dev_priv->drm);
6284                 break;
6285         case DP_TEST_LINK_PHY_TEST_PATTERN:
6286                 drm_dbg_kms(&dev_priv->drm,
6287                             "PHY test pattern Compliance Test requested\n");
6288                 /*
6289                  * Schedule long hpd to do the test
6290                  *
6291                  * FIXME get rid of the ad-hoc phy test modeset code
6292                  * and properly incorporate it into the normal modeset.
6293                  */
6294                 return false;
6295         }
6296
6297         return true;
6298 }
6299
6300 /* XXX this is probably wrong for multiple downstream ports */
6301 static enum drm_connector_status
6302 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
6303 {
6304         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6306         u8 *dpcd = intel_dp->dpcd;
6307         u8 type;
6308
6309         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
6310                 return connector_status_connected;
6311
6312         lspcon_resume(dig_port);
6313
6314         if (!intel_dp_get_dpcd(intel_dp))
6315                 return connector_status_disconnected;
6316
6317         /* if there's no downstream port, we're done */
6318         if (!drm_dp_is_branch(dpcd))
6319                 return connector_status_connected;
6320
6321         /* If we're HPD-aware, SINK_COUNT changes dynamically */
6322         if (intel_dp_has_sink_count(intel_dp) &&
6323             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
6324                 return intel_dp->sink_count ?
6325                 connector_status_connected : connector_status_disconnected;
6326         }
6327
6328         if (intel_dp_can_mst(intel_dp))
6329                 return connector_status_connected;
6330
6331         /* If no HPD, poke DDC gently */
6332         if (drm_probe_ddc(&intel_dp->aux.ddc))
6333                 return connector_status_connected;
6334
6335         /* Well we tried, say unknown for unreliable port types */
6336         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6337                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6338                 if (type == DP_DS_PORT_TYPE_VGA ||
6339                     type == DP_DS_PORT_TYPE_NON_EDID)
6340                         return connector_status_unknown;
6341         } else {
6342                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6343                         DP_DWN_STRM_PORT_TYPE_MASK;
6344                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6345                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6346                         return connector_status_unknown;
6347         }
6348
6349         /* Anything else is out of spec, warn and ignore */
6350         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6351         return connector_status_disconnected;
6352 }
6353
6354 static enum drm_connector_status
6355 edp_detect(struct intel_dp *intel_dp)
6356 {
6357         return connector_status_connected;
6358 }
6359
6360 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6361 {
6362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6363         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6364
6365         return intel_de_read(dev_priv, SDEISR) & bit;
6366 }
6367
6368 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6369 {
6370         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6371         u32 bit;
6372
6373         switch (encoder->hpd_pin) {
6374         case HPD_PORT_B:
6375                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6376                 break;
6377         case HPD_PORT_C:
6378                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6379                 break;
6380         case HPD_PORT_D:
6381                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6382                 break;
6383         default:
6384                 MISSING_CASE(encoder->hpd_pin);
6385                 return false;
6386         }
6387
6388         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6389 }
6390
6391 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6392 {
6393         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6394         u32 bit;
6395
6396         switch (encoder->hpd_pin) {
6397         case HPD_PORT_B:
6398                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6399                 break;
6400         case HPD_PORT_C:
6401                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6402                 break;
6403         case HPD_PORT_D:
6404                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6405                 break;
6406         default:
6407                 MISSING_CASE(encoder->hpd_pin);
6408                 return false;
6409         }
6410
6411         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6412 }
6413
6414 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6415 {
6416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6417         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6418
6419         return intel_de_read(dev_priv, DEISR) & bit;
6420 }
6421
6422 /*
6423  * intel_digital_port_connected - is the specified port connected?
6424  * @encoder: intel_encoder
6425  *
6426  * In cases where there's a connector physically connected but it can't be used
6427  * by our hardware we also return false, since the rest of the driver should
6428  * pretty much treat the port as disconnected. This is relevant for type-C
6429  * (starting on ICL) where there's ownership involved.
6430  *
6431  * Return %true if port is connected, %false otherwise.
6432  */
6433 bool intel_digital_port_connected(struct intel_encoder *encoder)
6434 {
6435         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6436         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6437         bool is_connected = false;
6438         intel_wakeref_t wakeref;
6439
6440         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6441                 is_connected = dig_port->connected(encoder);
6442
6443         return is_connected;
6444 }
6445
6446 static struct edid *
6447 intel_dp_get_edid(struct intel_dp *intel_dp)
6448 {
6449         struct intel_connector *intel_connector = intel_dp->attached_connector;
6450
6451         /* use cached edid if we have one */
6452         if (intel_connector->edid) {
6453                 /* invalid edid */
6454                 if (IS_ERR(intel_connector->edid))
6455                         return NULL;
6456
6457                 return drm_edid_duplicate(intel_connector->edid);
6458         } else
6459                 return drm_get_edid(&intel_connector->base,
6460                                     &intel_dp->aux.ddc);
6461 }
6462
6463 static void
6464 intel_dp_update_dfp(struct intel_dp *intel_dp,
6465                     const struct edid *edid)
6466 {
6467         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6468         struct intel_connector *connector = intel_dp->attached_connector;
6469
6470         intel_dp->dfp.max_bpc =
6471                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
6472                                           intel_dp->downstream_ports, edid);
6473
6474         intel_dp->dfp.max_dotclock =
6475                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
6476                                                intel_dp->downstream_ports);
6477
6478         intel_dp->dfp.min_tmds_clock =
6479                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
6480                                                  intel_dp->downstream_ports,
6481                                                  edid);
6482         intel_dp->dfp.max_tmds_clock =
6483                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
6484                                                  intel_dp->downstream_ports,
6485                                                  edid);
6486
6487         drm_dbg_kms(&i915->drm,
6488                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n",
6489                     connector->base.base.id, connector->base.name,
6490                     intel_dp->dfp.max_bpc,
6491                     intel_dp->dfp.max_dotclock,
6492                     intel_dp->dfp.min_tmds_clock,
6493                     intel_dp->dfp.max_tmds_clock);
6494 }
6495
6496 static void
6497 intel_dp_update_420(struct intel_dp *intel_dp)
6498 {
6499         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6500         struct intel_connector *connector = intel_dp->attached_connector;
6501         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420;
6502
6503         /* No YCbCr output support on gmch platforms */
6504         if (HAS_GMCH(i915))
6505                 return;
6506
6507         /*
6508          * ILK doesn't seem capable of DP YCbCr output. The
6509          * displayed image is severly corrupted. SNB+ is fine.
6510          */
6511         if (IS_GEN(i915, 5))
6512                 return;
6513
6514         is_branch = drm_dp_is_branch(intel_dp->dpcd);
6515         ycbcr_420_passthrough =
6516                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
6517                                                   intel_dp->downstream_ports);
6518         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
6519         ycbcr_444_to_420 =
6520                 dp_to_dig_port(intel_dp)->lspcon.active ||
6521                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
6522                                                         intel_dp->downstream_ports);
6523
6524         if (INTEL_GEN(i915) >= 11) {
6525                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
6526                 intel_dp->dfp.ycbcr_444_to_420 =
6527                         ycbcr_444_to_420 && !ycbcr_420_passthrough;
6528
6529                 connector->base.ycbcr_420_allowed =
6530                         !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
6531         } else {
6532                 /* 4:4:4->4:2:0 conversion is the only way */
6533                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
6534
6535                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
6536         }
6537
6538         drm_dbg_kms(&i915->drm,
6539                     "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
6540                     connector->base.base.id, connector->base.name,
6541                     yesno(connector->base.ycbcr_420_allowed),
6542                     yesno(intel_dp->dfp.ycbcr_444_to_420));
6543 }
6544
6545 static void
6546 intel_dp_set_edid(struct intel_dp *intel_dp)
6547 {
6548         struct intel_connector *connector = intel_dp->attached_connector;
6549         struct edid *edid;
6550
6551         intel_dp_unset_edid(intel_dp);
6552         edid = intel_dp_get_edid(intel_dp);
6553         connector->detect_edid = edid;
6554
6555         intel_dp_update_dfp(intel_dp, edid);
6556         intel_dp_update_420(intel_dp);
6557
6558         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6559                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6560                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6561         }
6562
6563         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6564         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6565 }
6566
6567 static void
6568 intel_dp_unset_edid(struct intel_dp *intel_dp)
6569 {
6570         struct intel_connector *connector = intel_dp->attached_connector;
6571
6572         drm_dp_cec_unset_edid(&intel_dp->aux);
6573         kfree(connector->detect_edid);
6574         connector->detect_edid = NULL;
6575
6576         intel_dp->has_hdmi_sink = false;
6577         intel_dp->has_audio = false;
6578         intel_dp->edid_quirks = 0;
6579
6580         intel_dp->dfp.max_bpc = 0;
6581         intel_dp->dfp.max_dotclock = 0;
6582         intel_dp->dfp.min_tmds_clock = 0;
6583         intel_dp->dfp.max_tmds_clock = 0;
6584
6585         intel_dp->dfp.ycbcr_444_to_420 = false;
6586         connector->base.ycbcr_420_allowed = false;
6587 }
6588
6589 static int
6590 intel_dp_detect(struct drm_connector *connector,
6591                 struct drm_modeset_acquire_ctx *ctx,
6592                 bool force)
6593 {
6594         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6595         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6596         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6597         struct intel_encoder *encoder = &dig_port->base;
6598         enum drm_connector_status status;
6599
6600         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6601                     connector->base.id, connector->name);
6602         drm_WARN_ON(&dev_priv->drm,
6603                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6604
6605         if (!INTEL_DISPLAY_ENABLED(dev_priv))
6606                 return connector_status_disconnected;
6607
6608         /* Can't disconnect eDP */
6609         if (intel_dp_is_edp(intel_dp))
6610                 status = edp_detect(intel_dp);
6611         else if (intel_digital_port_connected(encoder))
6612                 status = intel_dp_detect_dpcd(intel_dp);
6613         else
6614                 status = connector_status_disconnected;
6615
6616         if (status == connector_status_disconnected) {
6617                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6618                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6619
6620                 if (intel_dp->is_mst) {
6621                         drm_dbg_kms(&dev_priv->drm,
6622                                     "MST device may have disappeared %d vs %d\n",
6623                                     intel_dp->is_mst,
6624                                     intel_dp->mst_mgr.mst_state);
6625                         intel_dp->is_mst = false;
6626                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6627                                                         intel_dp->is_mst);
6628                 }
6629
6630                 goto out;
6631         }
6632
6633         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6634         if (INTEL_GEN(dev_priv) >= 11)
6635                 intel_dp_get_dsc_sink_cap(intel_dp);
6636
6637         intel_dp_configure_mst(intel_dp);
6638
6639         /*
6640          * TODO: Reset link params when switching to MST mode, until MST
6641          * supports link training fallback params.
6642          */
6643         if (intel_dp->reset_link_params || intel_dp->is_mst) {
6644                 /* Initial max link lane count */
6645                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6646
6647                 /* Initial max link rate */
6648                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6649
6650                 intel_dp->reset_link_params = false;
6651         }
6652
6653         intel_dp_print_rates(intel_dp);
6654
6655         if (intel_dp->is_mst) {
6656                 /*
6657                  * If we are in MST mode then this connector
6658                  * won't appear connected or have anything
6659                  * with EDID on it
6660                  */
6661                 status = connector_status_disconnected;
6662                 goto out;
6663         }
6664
6665         /*
6666          * Some external monitors do not signal loss of link synchronization
6667          * with an IRQ_HPD, so force a link status check.
6668          */
6669         if (!intel_dp_is_edp(intel_dp)) {
6670                 int ret;
6671
6672                 ret = intel_dp_retrain_link(encoder, ctx);
6673                 if (ret)
6674                         return ret;
6675         }
6676
6677         /*
6678          * Clearing NACK and defer counts to get their exact values
6679          * while reading EDID which are required by Compliance tests
6680          * 4.2.2.4 and 4.2.2.5
6681          */
6682         intel_dp->aux.i2c_nack_count = 0;
6683         intel_dp->aux.i2c_defer_count = 0;
6684
6685         intel_dp_set_edid(intel_dp);
6686         if (intel_dp_is_edp(intel_dp) ||
6687             to_intel_connector(connector)->detect_edid)
6688                 status = connector_status_connected;
6689
6690         intel_dp_check_service_irq(intel_dp);
6691
6692 out:
6693         if (status != connector_status_connected && !intel_dp->is_mst)
6694                 intel_dp_unset_edid(intel_dp);
6695
6696         /*
6697          * Make sure the refs for power wells enabled during detect are
6698          * dropped to avoid a new detect cycle triggered by HPD polling.
6699          */
6700         intel_display_power_flush_work(dev_priv);
6701
6702         if (!intel_dp_is_edp(intel_dp))
6703                 drm_dp_set_subconnector_property(connector,
6704                                                  status,
6705                                                  intel_dp->dpcd,
6706                                                  intel_dp->downstream_ports);
6707         return status;
6708 }
6709
6710 static void
6711 intel_dp_force(struct drm_connector *connector)
6712 {
6713         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6714         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6715         struct intel_encoder *intel_encoder = &dig_port->base;
6716         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6717         enum intel_display_power_domain aux_domain =
6718                 intel_aux_power_domain(dig_port);
6719         intel_wakeref_t wakeref;
6720
6721         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6722                     connector->base.id, connector->name);
6723         intel_dp_unset_edid(intel_dp);
6724
6725         if (connector->status != connector_status_connected)
6726                 return;
6727
6728         wakeref = intel_display_power_get(dev_priv, aux_domain);
6729
6730         intel_dp_set_edid(intel_dp);
6731
6732         intel_display_power_put(dev_priv, aux_domain, wakeref);
6733 }
6734
6735 static int intel_dp_get_modes(struct drm_connector *connector)
6736 {
6737         struct intel_connector *intel_connector = to_intel_connector(connector);
6738         struct edid *edid;
6739
6740         edid = intel_connector->detect_edid;
6741         if (edid) {
6742                 int ret = intel_connector_update_modes(connector, edid);
6743                 if (ret)
6744                         return ret;
6745         }
6746
6747         /* if eDP has no EDID, fall back to fixed mode */
6748         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
6749             intel_connector->panel.fixed_mode) {
6750                 struct drm_display_mode *mode;
6751
6752                 mode = drm_mode_duplicate(connector->dev,
6753                                           intel_connector->panel.fixed_mode);
6754                 if (mode) {
6755                         drm_mode_probed_add(connector, mode);
6756                         return 1;
6757                 }
6758         }
6759
6760         if (!edid) {
6761                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
6762                 struct drm_display_mode *mode;
6763
6764                 mode = drm_dp_downstream_mode(connector->dev,
6765                                               intel_dp->dpcd,
6766                                               intel_dp->downstream_ports);
6767                 if (mode) {
6768                         drm_mode_probed_add(connector, mode);
6769                         return 1;
6770                 }
6771         }
6772
6773         return 0;
6774 }
6775
6776 static int
6777 intel_dp_connector_register(struct drm_connector *connector)
6778 {
6779         struct drm_i915_private *i915 = to_i915(connector->dev);
6780         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6781         int ret;
6782
6783         ret = intel_connector_register(connector);
6784         if (ret)
6785                 return ret;
6786
6787         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6788                     intel_dp->aux.name, connector->kdev->kobj.name);
6789
6790         intel_dp->aux.dev = connector->kdev;
6791         ret = drm_dp_aux_register(&intel_dp->aux);
6792         if (!ret)
6793                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6794         return ret;
6795 }
6796
6797 static void
6798 intel_dp_connector_unregister(struct drm_connector *connector)
6799 {
6800         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6801
6802         drm_dp_cec_unregister_connector(&intel_dp->aux);
6803         drm_dp_aux_unregister(&intel_dp->aux);
6804         intel_connector_unregister(connector);
6805 }
6806
6807 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6808 {
6809         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6810         struct intel_dp *intel_dp = &dig_port->dp;
6811
6812         intel_dp_mst_encoder_cleanup(dig_port);
6813         if (intel_dp_is_edp(intel_dp)) {
6814                 intel_wakeref_t wakeref;
6815
6816                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6817                 /*
6818                  * vdd might still be enabled do to the delayed vdd off.
6819                  * Make sure vdd is actually turned off here.
6820                  */
6821                 with_pps_lock(intel_dp, wakeref)
6822                         edp_panel_vdd_off_sync(intel_dp);
6823         }
6824
6825         intel_dp_aux_fini(intel_dp);
6826 }
6827
6828 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6829 {
6830         intel_dp_encoder_flush_work(encoder);
6831
6832         drm_encoder_cleanup(encoder);
6833         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6834 }
6835
6836 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6837 {
6838         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6839         intel_wakeref_t wakeref;
6840
6841         if (!intel_dp_is_edp(intel_dp))
6842                 return;
6843
6844         /*
6845          * vdd might still be enabled do to the delayed vdd off.
6846          * Make sure vdd is actually turned off here.
6847          */
6848         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6849         with_pps_lock(intel_dp, wakeref)
6850                 edp_panel_vdd_off_sync(intel_dp);
6851 }
6852
6853 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
6854 {
6855         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6856         intel_wakeref_t wakeref;
6857
6858         if (!intel_dp_is_edp(intel_dp))
6859                 return;
6860
6861         with_pps_lock(intel_dp, wakeref)
6862                 wait_panel_power_cycle(intel_dp);
6863 }
6864
6865 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6866 {
6867         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6868         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6869
6870         lockdep_assert_held(&dev_priv->pps_mutex);
6871
6872         if (!edp_have_panel_vdd(intel_dp))
6873                 return;
6874
6875         /*
6876          * The VDD bit needs a power domain reference, so if the bit is
6877          * already enabled when we boot or resume, grab this reference and
6878          * schedule a vdd off, so we don't hold on to the reference
6879          * indefinitely.
6880          */
6881         drm_dbg_kms(&dev_priv->drm,
6882                     "VDD left on by BIOS, adjusting state tracking\n");
6883         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6884
6885         edp_panel_vdd_schedule_off(intel_dp);
6886 }
6887
6888 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6889 {
6890         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6891         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6892         enum pipe pipe;
6893
6894         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6895                                   encoder->port, &pipe))
6896                 return pipe;
6897
6898         return INVALID_PIPE;
6899 }
6900
6901 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6902 {
6903         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6904         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
6905         intel_wakeref_t wakeref;
6906
6907         if (!HAS_DDI(dev_priv))
6908                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6909
6910         intel_dp->reset_link_params = true;
6911
6912         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6913             !intel_dp_is_edp(intel_dp))
6914                 return;
6915
6916         with_pps_lock(intel_dp, wakeref) {
6917                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6918                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6919
6920                 if (intel_dp_is_edp(intel_dp)) {
6921                         /*
6922                          * Reinit the power sequencer, in case BIOS did
6923                          * something nasty with it.
6924                          */
6925                         intel_dp_pps_init(intel_dp);
6926                         intel_edp_panel_vdd_sanitize(intel_dp);
6927                 }
6928         }
6929 }
6930
6931 static int intel_modeset_tile_group(struct intel_atomic_state *state,
6932                                     int tile_group_id)
6933 {
6934         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6935         struct drm_connector_list_iter conn_iter;
6936         struct drm_connector *connector;
6937         int ret = 0;
6938
6939         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6940         drm_for_each_connector_iter(connector, &conn_iter) {
6941                 struct drm_connector_state *conn_state;
6942                 struct intel_crtc_state *crtc_state;
6943                 struct intel_crtc *crtc;
6944
6945                 if (!connector->has_tile ||
6946                     connector->tile_group->id != tile_group_id)
6947                         continue;
6948
6949                 conn_state = drm_atomic_get_connector_state(&state->base,
6950                                                             connector);
6951                 if (IS_ERR(conn_state)) {
6952                         ret = PTR_ERR(conn_state);
6953                         break;
6954                 }
6955
6956                 crtc = to_intel_crtc(conn_state->crtc);
6957
6958                 if (!crtc)
6959                         continue;
6960
6961                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6962                 crtc_state->uapi.mode_changed = true;
6963
6964                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6965                 if (ret)
6966                         break;
6967         }
6968         drm_connector_list_iter_end(&conn_iter);
6969
6970         return ret;
6971 }
6972
6973 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6974 {
6975         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6976         struct intel_crtc *crtc;
6977
6978         if (transcoders == 0)
6979                 return 0;
6980
6981         for_each_intel_crtc(&dev_priv->drm, crtc) {
6982                 struct intel_crtc_state *crtc_state;
6983                 int ret;
6984
6985                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6986                 if (IS_ERR(crtc_state))
6987                         return PTR_ERR(crtc_state);
6988
6989                 if (!crtc_state->hw.enable)
6990                         continue;
6991
6992                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6993                         continue;
6994
6995                 crtc_state->uapi.mode_changed = true;
6996
6997                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6998                 if (ret)
6999                         return ret;
7000
7001                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7002                 if (ret)
7003                         return ret;
7004
7005                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7006         }
7007
7008         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7009
7010         return 0;
7011 }
7012
7013 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7014                                       struct drm_connector *connector)
7015 {
7016         const struct drm_connector_state *old_conn_state =
7017                 drm_atomic_get_old_connector_state(&state->base, connector);
7018         const struct intel_crtc_state *old_crtc_state;
7019         struct intel_crtc *crtc;
7020         u8 transcoders;
7021
7022         crtc = to_intel_crtc(old_conn_state->crtc);
7023         if (!crtc)
7024                 return 0;
7025
7026         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7027
7028         if (!old_crtc_state->hw.active)
7029                 return 0;
7030
7031         transcoders = old_crtc_state->sync_mode_slaves_mask;
7032         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7033                 transcoders |= BIT(old_crtc_state->master_transcoder);
7034
7035         return intel_modeset_affected_transcoders(state,
7036                                                   transcoders);
7037 }
7038
7039 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7040                                            struct drm_atomic_state *_state)
7041 {
7042         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7043         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7044         int ret;
7045
7046         ret = intel_digital_connector_atomic_check(conn, &state->base);
7047         if (ret)
7048                 return ret;
7049
7050         /*
7051          * We don't enable port sync on BDW due to missing w/as and
7052          * due to not having adjusted the modeset sequence appropriately.
7053          */
7054         if (INTEL_GEN(dev_priv) < 9)
7055                 return 0;
7056
7057         if (!intel_connector_needs_modeset(state, conn))
7058                 return 0;
7059
7060         if (conn->has_tile) {
7061                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7062                 if (ret)
7063                         return ret;
7064         }
7065
7066         return intel_modeset_synced_crtcs(state, conn);
7067 }
7068
7069 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7070         .force = intel_dp_force,
7071         .fill_modes = drm_helper_probe_single_connector_modes,
7072         .atomic_get_property = intel_digital_connector_atomic_get_property,
7073         .atomic_set_property = intel_digital_connector_atomic_set_property,
7074         .late_register = intel_dp_connector_register,
7075         .early_unregister = intel_dp_connector_unregister,
7076         .destroy = intel_connector_destroy,
7077         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7078         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7079 };
7080
7081 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7082         .detect_ctx = intel_dp_detect,
7083         .get_modes = intel_dp_get_modes,
7084         .mode_valid = intel_dp_mode_valid,
7085         .atomic_check = intel_dp_connector_atomic_check,
7086 };
7087
7088 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7089         .reset = intel_dp_encoder_reset,
7090         .destroy = intel_dp_encoder_destroy,
7091 };
7092
7093 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7094 {
7095         intel_wakeref_t wakeref;
7096         bool have_power = false;
7097
7098         with_pps_lock(intel_dp, wakeref) {
7099                 have_power = edp_have_panel_power(intel_dp) &&
7100                                                   edp_have_panel_vdd(intel_dp);
7101         }
7102
7103         return have_power;
7104 }
7105
7106 enum irqreturn
7107 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
7108 {
7109         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
7110         struct intel_dp *intel_dp = &dig_port->dp;
7111
7112         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
7113             (long_hpd || !intel_edp_have_power(intel_dp))) {
7114                 /*
7115                  * vdd off can generate a long/short pulse on eDP which
7116                  * would require vdd on to handle it, and thus we
7117                  * would end up in an endless cycle of
7118                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7119                  */
7120                 drm_dbg_kms(&i915->drm,
7121                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7122                             long_hpd ? "long" : "short",
7123                             dig_port->base.base.base.id,
7124                             dig_port->base.base.name);
7125                 return IRQ_HANDLED;
7126         }
7127
7128         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7129                     dig_port->base.base.base.id,
7130                     dig_port->base.base.name,
7131                     long_hpd ? "long" : "short");
7132
7133         if (long_hpd) {
7134                 intel_dp->reset_link_params = true;
7135                 return IRQ_NONE;
7136         }
7137
7138         if (intel_dp->is_mst) {
7139                 if (!intel_dp_check_mst_status(intel_dp))
7140                         return IRQ_NONE;
7141         } else if (!intel_dp_short_pulse(intel_dp)) {
7142                 return IRQ_NONE;
7143         }
7144
7145         return IRQ_HANDLED;
7146 }
7147
7148 /* check the VBT to see whether the eDP is on another port */
7149 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7150 {
7151         /*
7152          * eDP not supported on g4x. so bail out early just
7153          * for a bit extra safety in case the VBT is bonkers.
7154          */
7155         if (INTEL_GEN(dev_priv) < 5)
7156                 return false;
7157
7158         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7159                 return true;
7160
7161         return intel_bios_is_port_edp(dev_priv, port);
7162 }
7163
7164 static void
7165 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7166 {
7167         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7168         enum port port = dp_to_dig_port(intel_dp)->base.port;
7169
7170         if (!intel_dp_is_edp(intel_dp))
7171                 drm_connector_attach_dp_subconnector_property(connector);
7172
7173         if (!IS_G4X(dev_priv) && port != PORT_A)
7174                 intel_attach_force_audio_property(connector);
7175
7176         intel_attach_broadcast_rgb_property(connector);
7177         if (HAS_GMCH(dev_priv))
7178                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7179         else if (INTEL_GEN(dev_priv) >= 5)
7180                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7181
7182         intel_attach_colorspace_property(connector);
7183
7184         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7185                 drm_object_attach_property(&connector->base,
7186                                            connector->dev->mode_config.hdr_output_metadata_property,
7187                                            0);
7188
7189         if (intel_dp_is_edp(intel_dp)) {
7190                 u32 allowed_scalers;
7191
7192                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7193                 if (!HAS_GMCH(dev_priv))
7194                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7195
7196                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7197
7198                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7199
7200         }
7201 }
7202
7203 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7204 {
7205         intel_dp->panel_power_off_time = ktime_get_boottime();
7206         intel_dp->last_power_on = jiffies;
7207         intel_dp->last_backlight_off = jiffies;
7208 }
7209
7210 static void
7211 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7212 {
7213         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7214         u32 pp_on, pp_off, pp_ctl;
7215         struct pps_registers regs;
7216
7217         intel_pps_get_registers(intel_dp, &regs);
7218
7219         pp_ctl = ilk_get_pp_control(intel_dp);
7220
7221         /* Ensure PPS is unlocked */
7222         if (!HAS_DDI(dev_priv))
7223                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7224
7225         pp_on = intel_de_read(dev_priv, regs.pp_on);
7226         pp_off = intel_de_read(dev_priv, regs.pp_off);
7227
7228         /* Pull timing values out of registers */
7229         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7230         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7231         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7232         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7233
7234         if (i915_mmio_reg_valid(regs.pp_div)) {
7235                 u32 pp_div;
7236
7237                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7238
7239                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7240         } else {
7241                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7242         }
7243 }
7244
7245 static void
7246 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7247 {
7248         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7249                       state_name,
7250                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7251 }
7252
7253 static void
7254 intel_pps_verify_state(struct intel_dp *intel_dp)
7255 {
7256         struct edp_power_seq hw;
7257         struct edp_power_seq *sw = &intel_dp->pps_delays;
7258
7259         intel_pps_readout_hw_state(intel_dp, &hw);
7260
7261         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7262             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7263                 DRM_ERROR("PPS state mismatch\n");
7264                 intel_pps_dump_state("sw", sw);
7265                 intel_pps_dump_state("hw", &hw);
7266         }
7267 }
7268
7269 static void
7270 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7271 {
7272         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7273         struct edp_power_seq cur, vbt, spec,
7274                 *final = &intel_dp->pps_delays;
7275
7276         lockdep_assert_held(&dev_priv->pps_mutex);
7277
7278         /* already initialized? */
7279         if (final->t11_t12 != 0)
7280                 return;
7281
7282         intel_pps_readout_hw_state(intel_dp, &cur);
7283
7284         intel_pps_dump_state("cur", &cur);
7285
7286         vbt = dev_priv->vbt.edp.pps;
7287         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7288          * of 500ms appears to be too short. Ocassionally the panel
7289          * just fails to power back on. Increasing the delay to 800ms
7290          * seems sufficient to avoid this problem.
7291          */
7292         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7293                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7294                 drm_dbg_kms(&dev_priv->drm,
7295                             "Increasing T12 panel delay as per the quirk to %d\n",
7296                             vbt.t11_t12);
7297         }
7298         /* T11_T12 delay is special and actually in units of 100ms, but zero
7299          * based in the hw (so we need to add 100 ms). But the sw vbt
7300          * table multiplies it with 1000 to make it in units of 100usec,
7301          * too. */
7302         vbt.t11_t12 += 100 * 10;
7303
7304         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7305          * our hw here, which are all in 100usec. */
7306         spec.t1_t3 = 210 * 10;
7307         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7308         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7309         spec.t10 = 500 * 10;
7310         /* This one is special and actually in units of 100ms, but zero
7311          * based in the hw (so we need to add 100 ms). But the sw vbt
7312          * table multiplies it with 1000 to make it in units of 100usec,
7313          * too. */
7314         spec.t11_t12 = (510 + 100) * 10;
7315
7316         intel_pps_dump_state("vbt", &vbt);
7317
7318         /* Use the max of the register settings and vbt. If both are
7319          * unset, fall back to the spec limits. */
7320 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7321                                        spec.field : \
7322                                        max(cur.field, vbt.field))
7323         assign_final(t1_t3);
7324         assign_final(t8);
7325         assign_final(t9);
7326         assign_final(t10);
7327         assign_final(t11_t12);
7328 #undef assign_final
7329
7330 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7331         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7332         intel_dp->backlight_on_delay = get_delay(t8);
7333         intel_dp->backlight_off_delay = get_delay(t9);
7334         intel_dp->panel_power_down_delay = get_delay(t10);
7335         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7336 #undef get_delay
7337
7338         drm_dbg_kms(&dev_priv->drm,
7339                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7340                     intel_dp->panel_power_up_delay,
7341                     intel_dp->panel_power_down_delay,
7342                     intel_dp->panel_power_cycle_delay);
7343
7344         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7345                     intel_dp->backlight_on_delay,
7346                     intel_dp->backlight_off_delay);
7347
7348         /*
7349          * We override the HW backlight delays to 1 because we do manual waits
7350          * on them. For T8, even BSpec recommends doing it. For T9, if we
7351          * don't do this, we'll end up waiting for the backlight off delay
7352          * twice: once when we do the manual sleep, and once when we disable
7353          * the panel and wait for the PP_STATUS bit to become zero.
7354          */
7355         final->t8 = 1;
7356         final->t9 = 1;
7357
7358         /*
7359          * HW has only a 100msec granularity for t11_t12 so round it up
7360          * accordingly.
7361          */
7362         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7363 }
7364
7365 static void
7366 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7367                                               bool force_disable_vdd)
7368 {
7369         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7370         u32 pp_on, pp_off, port_sel = 0;
7371         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7372         struct pps_registers regs;
7373         enum port port = dp_to_dig_port(intel_dp)->base.port;
7374         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7375
7376         lockdep_assert_held(&dev_priv->pps_mutex);
7377
7378         intel_pps_get_registers(intel_dp, &regs);
7379
7380         /*
7381          * On some VLV machines the BIOS can leave the VDD
7382          * enabled even on power sequencers which aren't
7383          * hooked up to any port. This would mess up the
7384          * power domain tracking the first time we pick
7385          * one of these power sequencers for use since
7386          * edp_panel_vdd_on() would notice that the VDD was
7387          * already on and therefore wouldn't grab the power
7388          * domain reference. Disable VDD first to avoid this.
7389          * This also avoids spuriously turning the VDD on as
7390          * soon as the new power sequencer gets initialized.
7391          */
7392         if (force_disable_vdd) {
7393                 u32 pp = ilk_get_pp_control(intel_dp);
7394
7395                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7396                          "Panel power already on\n");
7397
7398                 if (pp & EDP_FORCE_VDD)
7399                         drm_dbg_kms(&dev_priv->drm,
7400                                     "VDD already on, disabling first\n");
7401
7402                 pp &= ~EDP_FORCE_VDD;
7403
7404                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7405         }
7406
7407         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7408                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7409         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7410                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7411
7412         /* Haswell doesn't have any port selection bits for the panel
7413          * power sequencer any more. */
7414         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7415                 port_sel = PANEL_PORT_SELECT_VLV(port);
7416         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7417                 switch (port) {
7418                 case PORT_A:
7419                         port_sel = PANEL_PORT_SELECT_DPA;
7420                         break;
7421                 case PORT_C:
7422                         port_sel = PANEL_PORT_SELECT_DPC;
7423                         break;
7424                 case PORT_D:
7425                         port_sel = PANEL_PORT_SELECT_DPD;
7426                         break;
7427                 default:
7428                         MISSING_CASE(port);
7429                         break;
7430                 }
7431         }
7432
7433         pp_on |= port_sel;
7434
7435         intel_de_write(dev_priv, regs.pp_on, pp_on);
7436         intel_de_write(dev_priv, regs.pp_off, pp_off);
7437
7438         /*
7439          * Compute the divisor for the pp clock, simply match the Bspec formula.
7440          */
7441         if (i915_mmio_reg_valid(regs.pp_div)) {
7442                 intel_de_write(dev_priv, regs.pp_div,
7443                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7444         } else {
7445                 u32 pp_ctl;
7446
7447                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7448                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7449                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7450                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7451         }
7452
7453         drm_dbg_kms(&dev_priv->drm,
7454                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7455                     intel_de_read(dev_priv, regs.pp_on),
7456                     intel_de_read(dev_priv, regs.pp_off),
7457                     i915_mmio_reg_valid(regs.pp_div) ?
7458                     intel_de_read(dev_priv, regs.pp_div) :
7459                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7460 }
7461
7462 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7463 {
7464         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7465
7466         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7467                 vlv_initial_power_sequencer_setup(intel_dp);
7468         } else {
7469                 intel_dp_init_panel_power_sequencer(intel_dp);
7470                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7471         }
7472 }
7473
7474 /**
7475  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7476  * @dev_priv: i915 device
7477  * @crtc_state: a pointer to the active intel_crtc_state
7478  * @refresh_rate: RR to be programmed
7479  *
7480  * This function gets called when refresh rate (RR) has to be changed from
7481  * one frequency to another. Switches can be between high and low RR
7482  * supported by the panel or to any other RR based on media playback (in
7483  * this case, RR value needs to be passed from user space).
7484  *
7485  * The caller of this function needs to take a lock on dev_priv->drrs.
7486  */
7487 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7488                                     const struct intel_crtc_state *crtc_state,
7489                                     int refresh_rate)
7490 {
7491         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7493         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7494
7495         if (refresh_rate <= 0) {
7496                 drm_dbg_kms(&dev_priv->drm,
7497                             "Refresh rate should be positive non-zero.\n");
7498                 return;
7499         }
7500
7501         if (intel_dp == NULL) {
7502                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7503                 return;
7504         }
7505
7506         if (!intel_crtc) {
7507                 drm_dbg_kms(&dev_priv->drm,
7508                             "DRRS: intel_crtc not initialized\n");
7509                 return;
7510         }
7511
7512         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7513                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7514                 return;
7515         }
7516
7517         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7518                         refresh_rate)
7519                 index = DRRS_LOW_RR;
7520
7521         if (index == dev_priv->drrs.refresh_rate_type) {
7522                 drm_dbg_kms(&dev_priv->drm,
7523                             "DRRS requested for previously set RR...ignoring\n");
7524                 return;
7525         }
7526
7527         if (!crtc_state->hw.active) {
7528                 drm_dbg_kms(&dev_priv->drm,
7529                             "eDP encoder disabled. CRTC not Active\n");
7530                 return;
7531         }
7532
7533         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7534                 switch (index) {
7535                 case DRRS_HIGH_RR:
7536                         intel_dp_set_m_n(crtc_state, M1_N1);
7537                         break;
7538                 case DRRS_LOW_RR:
7539                         intel_dp_set_m_n(crtc_state, M2_N2);
7540                         break;
7541                 case DRRS_MAX_RR:
7542                 default:
7543                         drm_err(&dev_priv->drm,
7544                                 "Unsupported refreshrate type\n");
7545                 }
7546         } else if (INTEL_GEN(dev_priv) > 6) {
7547                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7548                 u32 val;
7549
7550                 val = intel_de_read(dev_priv, reg);
7551                 if (index > DRRS_HIGH_RR) {
7552                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7553                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7554                         else
7555                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7556                 } else {
7557                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7558                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7559                         else
7560                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7561                 }
7562                 intel_de_write(dev_priv, reg, val);
7563         }
7564
7565         dev_priv->drrs.refresh_rate_type = index;
7566
7567         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7568                     refresh_rate);
7569 }
7570
7571 static void
7572 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7573 {
7574         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7575
7576         dev_priv->drrs.busy_frontbuffer_bits = 0;
7577         dev_priv->drrs.dp = intel_dp;
7578 }
7579
7580 /**
7581  * intel_edp_drrs_enable - init drrs struct if supported
7582  * @intel_dp: DP struct
7583  * @crtc_state: A pointer to the active crtc state.
7584  *
7585  * Initializes frontbuffer_bits and drrs.dp
7586  */
7587 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7588                            const struct intel_crtc_state *crtc_state)
7589 {
7590         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7591
7592         if (!crtc_state->has_drrs)
7593                 return;
7594
7595         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7596
7597         mutex_lock(&dev_priv->drrs.mutex);
7598
7599         if (dev_priv->drrs.dp) {
7600                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
7601                 goto unlock;
7602         }
7603
7604         intel_edp_drrs_enable_locked(intel_dp);
7605
7606 unlock:
7607         mutex_unlock(&dev_priv->drrs.mutex);
7608 }
7609
7610 static void
7611 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
7612                               const struct intel_crtc_state *crtc_state)
7613 {
7614         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7615
7616         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
7617                 int refresh;
7618
7619                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
7620                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
7621         }
7622
7623         dev_priv->drrs.dp = NULL;
7624 }
7625
7626 /**
7627  * intel_edp_drrs_disable - Disable DRRS
7628  * @intel_dp: DP struct
7629  * @old_crtc_state: Pointer to old crtc_state.
7630  *
7631  */
7632 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7633                             const struct intel_crtc_state *old_crtc_state)
7634 {
7635         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7636
7637         if (!old_crtc_state->has_drrs)
7638                 return;
7639
7640         mutex_lock(&dev_priv->drrs.mutex);
7641         if (!dev_priv->drrs.dp) {
7642                 mutex_unlock(&dev_priv->drrs.mutex);
7643                 return;
7644         }
7645
7646         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
7647         mutex_unlock(&dev_priv->drrs.mutex);
7648
7649         cancel_delayed_work_sync(&dev_priv->drrs.work);
7650 }
7651
7652 /**
7653  * intel_edp_drrs_update - Update DRRS state
7654  * @intel_dp: Intel DP
7655  * @crtc_state: new CRTC state
7656  *
7657  * This function will update DRRS states, disabling or enabling DRRS when
7658  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
7659  * intel_edp_drrs_enable() should be called instead.
7660  */
7661 void
7662 intel_edp_drrs_update(struct intel_dp *intel_dp,
7663                       const struct intel_crtc_state *crtc_state)
7664 {
7665         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7666
7667         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
7668                 return;
7669
7670         mutex_lock(&dev_priv->drrs.mutex);
7671
7672         /* New state matches current one? */
7673         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
7674                 goto unlock;
7675
7676         if (crtc_state->has_drrs)
7677                 intel_edp_drrs_enable_locked(intel_dp);
7678         else
7679                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
7680
7681 unlock:
7682         mutex_unlock(&dev_priv->drrs.mutex);
7683 }
7684
7685 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7686 {
7687         struct drm_i915_private *dev_priv =
7688                 container_of(work, typeof(*dev_priv), drrs.work.work);
7689         struct intel_dp *intel_dp;
7690
7691         mutex_lock(&dev_priv->drrs.mutex);
7692
7693         intel_dp = dev_priv->drrs.dp;
7694
7695         if (!intel_dp)
7696                 goto unlock;
7697
7698         /*
7699          * The delayed work can race with an invalidate hence we need to
7700          * recheck.
7701          */
7702
7703         if (dev_priv->drrs.busy_frontbuffer_bits)
7704                 goto unlock;
7705
7706         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7707                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7708
7709                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7710                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
7711         }
7712
7713 unlock:
7714         mutex_unlock(&dev_priv->drrs.mutex);
7715 }
7716
7717 /**
7718  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7719  * @dev_priv: i915 device
7720  * @frontbuffer_bits: frontbuffer plane tracking bits
7721  *
7722  * This function gets called everytime rendering on the given planes start.
7723  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7724  *
7725  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7726  */
7727 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7728                                unsigned int frontbuffer_bits)
7729 {
7730         struct intel_dp *intel_dp;
7731         struct drm_crtc *crtc;
7732         enum pipe pipe;
7733
7734         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7735                 return;
7736
7737         cancel_delayed_work(&dev_priv->drrs.work);
7738
7739         mutex_lock(&dev_priv->drrs.mutex);
7740
7741         intel_dp = dev_priv->drrs.dp;
7742         if (!intel_dp) {
7743                 mutex_unlock(&dev_priv->drrs.mutex);
7744                 return;
7745         }
7746
7747         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7748         pipe = to_intel_crtc(crtc)->pipe;
7749
7750         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7751         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7752
7753         /* invalidate means busy screen hence upclock */
7754         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7755                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7756                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7757
7758         mutex_unlock(&dev_priv->drrs.mutex);
7759 }
7760
7761 /**
7762  * intel_edp_drrs_flush - Restart Idleness DRRS
7763  * @dev_priv: i915 device
7764  * @frontbuffer_bits: frontbuffer plane tracking bits
7765  *
7766  * This function gets called every time rendering on the given planes has
7767  * completed or flip on a crtc is completed. So DRRS should be upclocked
7768  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7769  * if no other planes are dirty.
7770  *
7771  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7772  */
7773 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7774                           unsigned int frontbuffer_bits)
7775 {
7776         struct intel_dp *intel_dp;
7777         struct drm_crtc *crtc;
7778         enum pipe pipe;
7779
7780         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7781                 return;
7782
7783         cancel_delayed_work(&dev_priv->drrs.work);
7784
7785         mutex_lock(&dev_priv->drrs.mutex);
7786
7787         intel_dp = dev_priv->drrs.dp;
7788         if (!intel_dp) {
7789                 mutex_unlock(&dev_priv->drrs.mutex);
7790                 return;
7791         }
7792
7793         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7794         pipe = to_intel_crtc(crtc)->pipe;
7795
7796         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7797         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7798
7799         /* flush means busy screen hence upclock */
7800         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7801                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7802                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7803
7804         /*
7805          * flush also means no more activity hence schedule downclock, if all
7806          * other fbs are quiescent too
7807          */
7808         if (!dev_priv->drrs.busy_frontbuffer_bits)
7809                 schedule_delayed_work(&dev_priv->drrs.work,
7810                                 msecs_to_jiffies(1000));
7811         mutex_unlock(&dev_priv->drrs.mutex);
7812 }
7813
7814 /**
7815  * DOC: Display Refresh Rate Switching (DRRS)
7816  *
7817  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7818  * which enables swtching between low and high refresh rates,
7819  * dynamically, based on the usage scenario. This feature is applicable
7820  * for internal panels.
7821  *
7822  * Indication that the panel supports DRRS is given by the panel EDID, which
7823  * would list multiple refresh rates for one resolution.
7824  *
7825  * DRRS is of 2 types - static and seamless.
7826  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7827  * (may appear as a blink on screen) and is used in dock-undock scenario.
7828  * Seamless DRRS involves changing RR without any visual effect to the user
7829  * and can be used during normal system usage. This is done by programming
7830  * certain registers.
7831  *
7832  * Support for static/seamless DRRS may be indicated in the VBT based on
7833  * inputs from the panel spec.
7834  *
7835  * DRRS saves power by switching to low RR based on usage scenarios.
7836  *
7837  * The implementation is based on frontbuffer tracking implementation.  When
7838  * there is a disturbance on the screen triggered by user activity or a periodic
7839  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
7840  * no movement on screen, after a timeout of 1 second, a switch to low RR is
7841  * made.
7842  *
7843  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7844  * and intel_edp_drrs_flush() are called.
7845  *
7846  * DRRS can be further extended to support other internal panels and also
7847  * the scenario of video playback wherein RR is set based on the rate
7848  * requested by userspace.
7849  */
7850
7851 /**
7852  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7853  * @connector: eDP connector
7854  * @fixed_mode: preferred mode of panel
7855  *
7856  * This function is  called only once at driver load to initialize basic
7857  * DRRS stuff.
7858  *
7859  * Returns:
7860  * Downclock mode if panel supports it, else return NULL.
7861  * DRRS support is determined by the presence of downclock mode (apart
7862  * from VBT setting).
7863  */
7864 static struct drm_display_mode *
7865 intel_dp_drrs_init(struct intel_connector *connector,
7866                    struct drm_display_mode *fixed_mode)
7867 {
7868         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7869         struct drm_display_mode *downclock_mode = NULL;
7870
7871         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7872         mutex_init(&dev_priv->drrs.mutex);
7873
7874         if (INTEL_GEN(dev_priv) <= 6) {
7875                 drm_dbg_kms(&dev_priv->drm,
7876                             "DRRS supported for Gen7 and above\n");
7877                 return NULL;
7878         }
7879
7880         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7881                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
7882                 return NULL;
7883         }
7884
7885         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7886         if (!downclock_mode) {
7887                 drm_dbg_kms(&dev_priv->drm,
7888                             "Downclock mode is not found. DRRS not supported\n");
7889                 return NULL;
7890         }
7891
7892         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7893
7894         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7895         drm_dbg_kms(&dev_priv->drm,
7896                     "seamless DRRS supported for eDP panel.\n");
7897         return downclock_mode;
7898 }
7899
7900 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7901                                      struct intel_connector *intel_connector)
7902 {
7903         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7904         struct drm_device *dev = &dev_priv->drm;
7905         struct drm_connector *connector = &intel_connector->base;
7906         struct drm_display_mode *fixed_mode = NULL;
7907         struct drm_display_mode *downclock_mode = NULL;
7908         bool has_dpcd;
7909         enum pipe pipe = INVALID_PIPE;
7910         intel_wakeref_t wakeref;
7911         struct edid *edid;
7912
7913         if (!intel_dp_is_edp(intel_dp))
7914                 return true;
7915
7916         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7917
7918         /*
7919          * On IBX/CPT we may get here with LVDS already registered. Since the
7920          * driver uses the only internal power sequencer available for both
7921          * eDP and LVDS bail out early in this case to prevent interfering
7922          * with an already powered-on LVDS power sequencer.
7923          */
7924         if (intel_get_lvds_encoder(dev_priv)) {
7925                 drm_WARN_ON(dev,
7926                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7927                 drm_info(&dev_priv->drm,
7928                          "LVDS was detected, not registering eDP\n");
7929
7930                 return false;
7931         }
7932
7933         with_pps_lock(intel_dp, wakeref) {
7934                 intel_dp_init_panel_power_timestamps(intel_dp);
7935                 intel_dp_pps_init(intel_dp);
7936                 intel_edp_panel_vdd_sanitize(intel_dp);
7937         }
7938
7939         /* Cache DPCD and EDID for edp. */
7940         has_dpcd = intel_edp_init_dpcd(intel_dp);
7941
7942         if (!has_dpcd) {
7943                 /* if this fails, presume the device is a ghost */
7944                 drm_info(&dev_priv->drm,
7945                          "failed to retrieve link info, disabling eDP\n");
7946                 goto out_vdd_off;
7947         }
7948
7949         mutex_lock(&dev->mode_config.mutex);
7950         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7951         if (edid) {
7952                 if (drm_add_edid_modes(connector, edid)) {
7953                         drm_connector_update_edid_property(connector, edid);
7954                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
7955                 } else {
7956                         kfree(edid);
7957                         edid = ERR_PTR(-EINVAL);
7958                 }
7959         } else {
7960                 edid = ERR_PTR(-ENOENT);
7961         }
7962         intel_connector->edid = edid;
7963
7964         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7965         if (fixed_mode)
7966                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7967
7968         /* fallback to VBT if available for eDP */
7969         if (!fixed_mode)
7970                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7971         mutex_unlock(&dev->mode_config.mutex);
7972
7973         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7974                 /*
7975                  * Figure out the current pipe for the initial backlight setup.
7976                  * If the current pipe isn't valid, try the PPS pipe, and if that
7977                  * fails just assume pipe A.
7978                  */
7979                 pipe = vlv_active_pipe(intel_dp);
7980
7981                 if (pipe != PIPE_A && pipe != PIPE_B)
7982                         pipe = intel_dp->pps_pipe;
7983
7984                 if (pipe != PIPE_A && pipe != PIPE_B)
7985                         pipe = PIPE_A;
7986
7987                 drm_dbg_kms(&dev_priv->drm,
7988                             "using pipe %c for initial backlight setup\n",
7989                             pipe_name(pipe));
7990         }
7991
7992         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7993         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7994         intel_panel_setup_backlight(connector, pipe);
7995
7996         if (fixed_mode) {
7997                 drm_connector_set_panel_orientation_with_quirk(connector,
7998                                 dev_priv->vbt.orientation,
7999                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8000         }
8001
8002         return true;
8003
8004 out_vdd_off:
8005         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8006         /*
8007          * vdd might still be enabled do to the delayed vdd off.
8008          * Make sure vdd is actually turned off here.
8009          */
8010         with_pps_lock(intel_dp, wakeref)
8011                 edp_panel_vdd_off_sync(intel_dp);
8012
8013         return false;
8014 }
8015
8016 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8017 {
8018         struct intel_connector *intel_connector;
8019         struct drm_connector *connector;
8020
8021         intel_connector = container_of(work, typeof(*intel_connector),
8022                                        modeset_retry_work);
8023         connector = &intel_connector->base;
8024         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8025                       connector->name);
8026
8027         /* Grab the locks before changing connector property*/
8028         mutex_lock(&connector->dev->mode_config.mutex);
8029         /* Set connector link status to BAD and send a Uevent to notify
8030          * userspace to do a modeset.
8031          */
8032         drm_connector_set_link_status_property(connector,
8033                                                DRM_MODE_LINK_STATUS_BAD);
8034         mutex_unlock(&connector->dev->mode_config.mutex);
8035         /* Send Hotplug uevent so userspace can reprobe */
8036         drm_kms_helper_hotplug_event(connector->dev);
8037 }
8038
8039 bool
8040 intel_dp_init_connector(struct intel_digital_port *dig_port,
8041                         struct intel_connector *intel_connector)
8042 {
8043         struct drm_connector *connector = &intel_connector->base;
8044         struct intel_dp *intel_dp = &dig_port->dp;
8045         struct intel_encoder *intel_encoder = &dig_port->base;
8046         struct drm_device *dev = intel_encoder->base.dev;
8047         struct drm_i915_private *dev_priv = to_i915(dev);
8048         enum port port = intel_encoder->port;
8049         enum phy phy = intel_port_to_phy(dev_priv, port);
8050         int type;
8051
8052         /* Initialize the work for modeset in case of link train failure */
8053         INIT_WORK(&intel_connector->modeset_retry_work,
8054                   intel_dp_modeset_retry_work_fn);
8055
8056         if (drm_WARN(dev, dig_port->max_lanes < 1,
8057                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8058                      dig_port->max_lanes, intel_encoder->base.base.id,
8059                      intel_encoder->base.name))
8060                 return false;
8061
8062         intel_dp_set_source_rates(intel_dp);
8063
8064         intel_dp->reset_link_params = true;
8065         intel_dp->pps_pipe = INVALID_PIPE;
8066         intel_dp->active_pipe = INVALID_PIPE;
8067
8068         /* Preserve the current hw state. */
8069         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8070         intel_dp->attached_connector = intel_connector;
8071
8072         if (intel_dp_is_port_edp(dev_priv, port)) {
8073                 /*
8074                  * Currently we don't support eDP on TypeC ports, although in
8075                  * theory it could work on TypeC legacy ports.
8076                  */
8077                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8078                 type = DRM_MODE_CONNECTOR_eDP;
8079         } else {
8080                 type = DRM_MODE_CONNECTOR_DisplayPort;
8081         }
8082
8083         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8084                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8085
8086         /*
8087          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8088          * for DP the encoder type can be set by the caller to
8089          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8090          */
8091         if (type == DRM_MODE_CONNECTOR_eDP)
8092                 intel_encoder->type = INTEL_OUTPUT_EDP;
8093
8094         /* eDP only on port B and/or C on vlv/chv */
8095         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8096                               IS_CHERRYVIEW(dev_priv)) &&
8097                         intel_dp_is_edp(intel_dp) &&
8098                         port != PORT_B && port != PORT_C))
8099                 return false;
8100
8101         drm_dbg_kms(&dev_priv->drm,
8102                     "Adding %s connector on [ENCODER:%d:%s]\n",
8103                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8104                     intel_encoder->base.base.id, intel_encoder->base.name);
8105
8106         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8107         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8108
8109         if (!HAS_GMCH(dev_priv))
8110                 connector->interlace_allowed = true;
8111         connector->doublescan_allowed = 0;
8112
8113         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8114
8115         intel_dp_aux_init(intel_dp);
8116
8117         intel_connector_attach_encoder(intel_connector, intel_encoder);
8118
8119         if (HAS_DDI(dev_priv))
8120                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8121         else
8122                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8123
8124         /* init MST on ports that can support it */
8125         intel_dp_mst_encoder_init(dig_port,
8126                                   intel_connector->base.base.id);
8127
8128         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8129                 intel_dp_aux_fini(intel_dp);
8130                 intel_dp_mst_encoder_cleanup(dig_port);
8131                 goto fail;
8132         }
8133
8134         intel_dp_add_properties(intel_dp, connector);
8135
8136         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8137                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
8138                 if (ret)
8139                         drm_dbg_kms(&dev_priv->drm,
8140                                     "HDCP init failed, skipping.\n");
8141         }
8142
8143         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8144          * 0xd.  Failure to do so will result in spurious interrupts being
8145          * generated on the port when a cable is not attached.
8146          */
8147         if (IS_G45(dev_priv)) {
8148                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8149                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8150                                (temp & ~0xf) | 0xd);
8151         }
8152
8153         return true;
8154
8155 fail:
8156         drm_connector_cleanup(connector);
8157
8158         return false;
8159 }
8160
8161 bool intel_dp_init(struct drm_i915_private *dev_priv,
8162                    i915_reg_t output_reg,
8163                    enum port port)
8164 {
8165         struct intel_digital_port *dig_port;
8166         struct intel_encoder *intel_encoder;
8167         struct drm_encoder *encoder;
8168         struct intel_connector *intel_connector;
8169
8170         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
8171         if (!dig_port)
8172                 return false;
8173
8174         intel_connector = intel_connector_alloc();
8175         if (!intel_connector)
8176                 goto err_connector_alloc;
8177
8178         intel_encoder = &dig_port->base;
8179         encoder = &intel_encoder->base;
8180
8181         mutex_init(&dig_port->hdcp_mutex);
8182
8183         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8184                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8185                              "DP %c", port_name(port)))
8186                 goto err_encoder_init;
8187
8188         intel_encoder->hotplug = intel_dp_hotplug;
8189         intel_encoder->compute_config = intel_dp_compute_config;
8190         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8191         intel_encoder->get_config = intel_dp_get_config;
8192         intel_encoder->sync_state = intel_dp_sync_state;
8193         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
8194         intel_encoder->update_pipe = intel_panel_update_backlight;
8195         intel_encoder->suspend = intel_dp_encoder_suspend;
8196         intel_encoder->shutdown = intel_dp_encoder_shutdown;
8197         if (IS_CHERRYVIEW(dev_priv)) {
8198                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8199                 intel_encoder->pre_enable = chv_pre_enable_dp;
8200                 intel_encoder->enable = vlv_enable_dp;
8201                 intel_encoder->disable = vlv_disable_dp;
8202                 intel_encoder->post_disable = chv_post_disable_dp;
8203                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8204         } else if (IS_VALLEYVIEW(dev_priv)) {
8205                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8206                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8207                 intel_encoder->enable = vlv_enable_dp;
8208                 intel_encoder->disable = vlv_disable_dp;
8209                 intel_encoder->post_disable = vlv_post_disable_dp;
8210         } else {
8211                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8212                 intel_encoder->enable = g4x_enable_dp;
8213                 intel_encoder->disable = g4x_disable_dp;
8214                 intel_encoder->post_disable = g4x_post_disable_dp;
8215         }
8216
8217         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8218             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8219                 dig_port->dp.set_link_train = cpt_set_link_train;
8220         else
8221                 dig_port->dp.set_link_train = g4x_set_link_train;
8222
8223         if (IS_CHERRYVIEW(dev_priv))
8224                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
8225         else if (IS_VALLEYVIEW(dev_priv))
8226                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8227         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8228                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8229         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8230                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8231         else
8232                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8233
8234         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
8235             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
8236                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
8237                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
8238         } else {
8239                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
8240                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
8241         }
8242
8243         dig_port->dp.output_reg = output_reg;
8244         dig_port->max_lanes = 4;
8245
8246         intel_encoder->type = INTEL_OUTPUT_DP;
8247         intel_encoder->power_domain = intel_port_to_power_domain(port);
8248         if (IS_CHERRYVIEW(dev_priv)) {
8249                 if (port == PORT_D)
8250                         intel_encoder->pipe_mask = BIT(PIPE_C);
8251                 else
8252                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8253         } else {
8254                 intel_encoder->pipe_mask = ~0;
8255         }
8256         intel_encoder->cloneable = 0;
8257         intel_encoder->port = port;
8258         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8259
8260         dig_port->hpd_pulse = intel_dp_hpd_pulse;
8261
8262         if (HAS_GMCH(dev_priv)) {
8263                 if (IS_GM45(dev_priv))
8264                         dig_port->connected = gm45_digital_port_connected;
8265                 else
8266                         dig_port->connected = g4x_digital_port_connected;
8267         } else {
8268                 if (port == PORT_A)
8269                         dig_port->connected = ilk_digital_port_connected;
8270                 else
8271                         dig_port->connected = ibx_digital_port_connected;
8272         }
8273
8274         if (port != PORT_A)
8275                 intel_infoframe_init(dig_port);
8276
8277         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8278         if (!intel_dp_init_connector(dig_port, intel_connector))
8279                 goto err_init_connector;
8280
8281         return true;
8282
8283 err_init_connector:
8284         drm_encoder_cleanup(encoder);
8285 err_encoder_init:
8286         kfree(intel_connector);
8287 err_connector_alloc:
8288         kfree(dig_port);
8289         return false;
8290 }
8291
8292 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8293 {
8294         struct intel_encoder *encoder;
8295
8296         for_each_intel_encoder(&dev_priv->drm, encoder) {
8297                 struct intel_dp *intel_dp;
8298
8299                 if (encoder->type != INTEL_OUTPUT_DDI)
8300                         continue;
8301
8302                 intel_dp = enc_to_intel_dp(encoder);
8303
8304                 if (!intel_dp->can_mst)
8305                         continue;
8306
8307                 if (intel_dp->is_mst)
8308                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8309         }
8310 }
8311
8312 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8313 {
8314         struct intel_encoder *encoder;
8315
8316         for_each_intel_encoder(&dev_priv->drm, encoder) {
8317                 struct intel_dp *intel_dp;
8318                 int ret;
8319
8320                 if (encoder->type != INTEL_OUTPUT_DDI)
8321                         continue;
8322
8323                 intel_dp = enc_to_intel_dp(encoder);
8324
8325                 if (!intel_dp->can_mst)
8326                         continue;
8327
8328                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8329                                                      true);
8330                 if (ret) {
8331                         intel_dp->is_mst = false;
8332                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8333                                                         false);
8334                 }
8335         }
8336 }