drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_types.h"
  60 #include "intel_dp.h"
  61 #include "intel_dp_aux.h"
  62 #include "intel_dp_hdcp.h"
  63 #include "intel_dp_link_training.h"
  64 #include "intel_dp_mst.h"
  65 #include "intel_dpio_phy.h"
  66 #include "intel_dpll.h"
  67 #include "intel_fifo_underrun.h"
  68 #include "intel_hdcp.h"
  69 #include "intel_hdmi.h"
  70 #include "intel_hotplug.h"
  71 #include "intel_hotplug_irq.h"
  72 #include "intel_lspcon.h"
  73 #include "intel_lvds.h"
  74 #include "intel_panel.h"
  75 #include "intel_pch_display.h"
  76 #include "intel_pps.h"
  77 #include "intel_psr.h"
  78 #include "intel_tc.h"
  79 #include "intel_vdsc.h"
  80 #include "intel_vrr.h"
  81 #include "intel_crtc_state_dump.h"
  82
  83 /* DP DSC throughput values used for slice count calculations KPixels/s */
  84 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  85 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  87
  88 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
  89 #define DP_DSC_FEC_OVERHEAD_FACTOR              1028530
  90
  91 /* Compliance test status bits  */
  92 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  93 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  94 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96
  97
  98 /* Constants for DP DSC configurations */
  99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 100
 101 /* With Single pipe configuration, HW is capable of supporting maximum
 102  * of 4 slices per line.
 103  */
 104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  *
 113  * This function is not safe to use prior to encoder type being set.
 114  */
 115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 118
 119         return dig_port->base.type == INTEL_OUTPUT_EDP;
 120 }
 121
 122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 123
 124 /* Is link rate UHBR and thus 128b/132b? */
 125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 126 {
 127         return drm_dp_is_uhbr_rate(crtc_state->port_clock);
 128 }
 129
 130 /**
 131  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
 132  * @rate: link rate in 10kbit/s units
 133  *
 134  * Returns the link symbol size in bits/symbol units depending on the link
 135  * rate -> channel coding.
 136  */
 137 int intel_dp_link_symbol_size(int rate)
 138 {
 139         return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
 140 }
 141
 142 /**
 143  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
 144  * @rate: link rate in 10kbit/s units
 145  *
 146  * Returns the link symbol clock frequency in kHz units depending on the
 147  * link rate and channel coding.
 148  */
 149 int intel_dp_link_symbol_clock(int rate)
 150 {
 151         return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 152 }
 153
 154 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 155 {
 156         intel_dp->sink_rates[0] = 162000;
 157         intel_dp->num_sink_rates = 1;
 158 }
 159
 160 /* update sink rates from dpcd */
 161 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 162 {
 163         static const int dp_rates[] = {
 164                 162000, 270000, 540000, 810000
 165         };
 166         int i, max_rate;
 167         int max_lttpr_rate;
 168
 169         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 170                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 171                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 172
 173                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 174                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 175
 176                 return;
 177         }
 178
 179         /*
 180          * Sink rates for 8b/10b.
 181          */
 182         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 183         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 184         if (max_lttpr_rate)
 185                 max_rate = min(max_rate, max_lttpr_rate);
 186
 187         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 188                 if (dp_rates[i] > max_rate)
 189                         break;
 190                 intel_dp->sink_rates[i] = dp_rates[i];
 191         }
 192
 193         /*
 194          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 195          * rates and 10 Gbps.
 196          */
 197         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 198                 u8 uhbr_rates = 0;
 199
 200                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 201
 202                 drm_dp_dpcd_readb(&intel_dp->aux,
 203                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 204
 205                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 206                         /* We have a repeater */
 207                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 208                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 209                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 210                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 211                                 /* Repeater supports 128b/132b, valid UHBR rates */
 212                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 213                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 214                         } else {
 215                                 /* Does not support 128b/132b */
 216                                 uhbr_rates = 0;
 217                         }
 218                 }
 219
 220                 if (uhbr_rates & DP_UHBR10)
 221                         intel_dp->sink_rates[i++] = 1000000;
 222                 if (uhbr_rates & DP_UHBR13_5)
 223                         intel_dp->sink_rates[i++] = 1350000;
 224                 if (uhbr_rates & DP_UHBR20)
 225                         intel_dp->sink_rates[i++] = 2000000;
 226         }
 227
 228         intel_dp->num_sink_rates = i;
 229 }
 230
 231 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 232 {
 233         struct intel_connector *connector = intel_dp->attached_connector;
 234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 235         struct intel_encoder *encoder = &intel_dig_port->base;
 236
 237         intel_dp_set_dpcd_sink_rates(intel_dp);
 238
 239         if (intel_dp->num_sink_rates)
 240                 return;
 241
 242         drm_err(&dp_to_i915(intel_dp)->drm,
 243                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 244                 connector->base.base.id, connector->base.name,
 245                 encoder->base.base.id, encoder->base.name);
 246
 247         intel_dp_set_default_sink_rates(intel_dp);
 248 }
 249
 250 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 251 {
 252         intel_dp->max_sink_lane_count = 1;
 253 }
 254
 255 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 256 {
 257         struct intel_connector *connector = intel_dp->attached_connector;
 258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 259         struct intel_encoder *encoder = &intel_dig_port->base;
 260
 261         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 262
 263         switch (intel_dp->max_sink_lane_count) {
 264         case 1:
 265         case 2:
 266         case 4:
 267                 return;
 268         }
 269
 270         drm_err(&dp_to_i915(intel_dp)->drm,
 271                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 272                 connector->base.base.id, connector->base.name,
 273                 encoder->base.base.id, encoder->base.name,
 274                 intel_dp->max_sink_lane_count);
 275
 276         intel_dp_set_default_max_sink_lane_count(intel_dp);
 277 }
 278
 279 /* Get length of rates array potentially limited by max_rate. */
 280 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 281 {
 282         int i;
 283
 284         /* Limit results by potentially reduced max rate */
 285         for (i = 0; i < len; i++) {
 286                 if (rates[len - i - 1] <= max_rate)
 287                         return len - i;
 288         }
 289
 290         return 0;
 291 }
 292
 293 /* Get length of common rates array potentially limited by max_rate. */
 294 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 295                                           int max_rate)
 296 {
 297         return intel_dp_rate_limit_len(intel_dp->common_rates,
 298                                        intel_dp->num_common_rates, max_rate);
 299 }
 300
 301 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 302 {
 303         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 304                         index < 0 || index >= intel_dp->num_common_rates))
 305                 return 162000;
 306
 307         return intel_dp->common_rates[index];
 308 }
 309
 310 /* Theoretical max between source and sink */
 311 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 312 {
 313         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 314 }
 315
 316 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 317 {
 318         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 319         int max_lanes = dig_port->max_lanes;
 320
 321         if (vbt_max_lanes)
 322                 max_lanes = min(max_lanes, vbt_max_lanes);
 323
 324         return max_lanes;
 325 }
 326
 327 /* Theoretical max between source and sink */
 328 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 329 {
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         int source_max = intel_dp_max_source_lane_count(dig_port);
 332         int sink_max = intel_dp->max_sink_lane_count;
 333         int lane_max = intel_tc_port_max_lane_count(dig_port);
 334         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 335
 336         if (lttpr_max)
 337                 sink_max = min(sink_max, lttpr_max);
 338
 339         return min3(source_max, sink_max, lane_max);
 340 }
 341
 342 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 343 {
 344         switch (intel_dp->max_link_lane_count) {
 345         case 1:
 346         case 2:
 347         case 4:
 348                 return intel_dp->max_link_lane_count;
 349         default:
 350                 MISSING_CASE(intel_dp->max_link_lane_count);
 351                 return 1;
 352         }
 353 }
 354
 355 /*
 356  * The required data bandwidth for a mode with given pixel clock and bpp. This
 357  * is the required net bandwidth independent of the data bandwidth efficiency.
 358  *
 359  * TODO: check if callers of this functions should use
 360  * intel_dp_effective_data_rate() instead.
 361  */
 362 int
 363 intel_dp_link_required(int pixel_clock, int bpp)
 364 {
 365         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 366         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 367 }
 368
 369 /**
 370  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
 371  * @pixel_clock: pixel clock in kHz
 372  * @bpp_x16: bits per pixel .4 fixed point format
 373  * @bw_overhead: BW allocation overhead in 1ppm units
 374  *
 375  * Return the effective pixel data rate in kB/sec units taking into account
 376  * the provided SSC, FEC, DSC BW allocation overhead.
 377  */
 378 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 379                                  int bw_overhead)
 380 {
 381         return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
 382                                 1000000 * 16 * 8);
 383 }
 384
 385 /*
 386  * Given a link rate and lanes, get the data bandwidth.
 387  *
 388  * Data bandwidth is the actual payload rate, which depends on the data
 389  * bandwidth efficiency and the link rate.
 390  *
 391  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 392  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 393  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 394  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 395  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 396  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 397  *
 398  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 399  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 400  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 401  * does not match the symbol clock, the port clock (not even if you think in
 402  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 403  * rate in units of 10000 bps.
 404  */
 405 int
 406 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 407 {
 408         int ch_coding_efficiency =
 409                 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
 410         int max_link_rate_kbps = max_link_rate * 10;
 411
 412         /*
 413          * UHBR rates always use 128b/132b channel encoding, and have
 414          * 97.71% data bandwidth efficiency. Consider max_link_rate the
 415          * link bit rate in units of 10000 bps.
 416          */
 417         /*
 418          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 419          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 420          * out to be a nop by coincidence:
 421          *
 422          *      int max_link_rate_kbps = max_link_rate * 10;
 423          *      max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10);
 424          *      max_link_rate = max_link_rate_kbps / 8;
 425          */
 426         return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
 427                                               ch_coding_efficiency),
 428                                   1000000 * 8);
 429 }
 430
 431 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 432 {
 433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 434         struct intel_encoder *encoder = &intel_dig_port->base;
 435         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 436
 437         return DISPLAY_VER(dev_priv) >= 12 ||
 438                 (DISPLAY_VER(dev_priv) == 11 &&
 439                  encoder->port != PORT_A);
 440 }
 441
 442 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 443 {
 444         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 445 }
 446
 447 static int icl_max_source_rate(struct intel_dp *intel_dp)
 448 {
 449         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 450         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 451         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 452
 453         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 454                 return 540000;
 455
 456         return 810000;
 457 }
 458
 459 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 460 {
 461         if (intel_dp_is_edp(intel_dp))
 462                 return 540000;
 463
 464         return 810000;
 465 }
 466
 467 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 468 {
 469         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 470         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 471         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 472
 473         if (intel_is_c10phy(i915, phy))
 474                 return 810000;
 475
 476         return 2000000;
 477 }
 478
 479 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 480 {
 481         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 482         int max_rate;
 483
 484         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 485
 486         if (intel_dp_is_edp(intel_dp)) {
 487                 struct intel_connector *connector = intel_dp->attached_connector;
 488                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 489
 490                 if (max_rate && edp_max_rate)
 491                         max_rate = min(max_rate, edp_max_rate);
 492                 else if (edp_max_rate)
 493                         max_rate = edp_max_rate;
 494         }
 495
 496         return max_rate;
 497 }
 498
 499 static void
 500 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 501 {
 502         /* The values must be in increasing order */
 503         static const int mtl_rates[] = {
 504                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 505                 810000, 1000000, 1350000, 2000000,
 506         };
 507         static const int icl_rates[] = {
 508                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 509                 1000000, 1350000,
 510         };
 511         static const int bxt_rates[] = {
 512                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 513         };
 514         static const int skl_rates[] = {
 515                 162000, 216000, 270000, 324000, 432000, 540000
 516         };
 517         static const int hsw_rates[] = {
 518                 162000, 270000, 540000
 519         };
 520         static const int g4x_rates[] = {
 521                 162000, 270000
 522         };
 523         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 524         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 525         const int *source_rates;
 526         int size, max_rate = 0, vbt_max_rate;
 527
 528         /* This should only be done once */
 529         drm_WARN_ON(&dev_priv->drm,
 530                     intel_dp->source_rates || intel_dp->num_source_rates);
 531
 532         if (DISPLAY_VER(dev_priv) >= 14) {
 533                 source_rates = mtl_rates;
 534                 size = ARRAY_SIZE(mtl_rates);
 535                 max_rate = mtl_max_source_rate(intel_dp);
 536         } else if (DISPLAY_VER(dev_priv) >= 11) {
 537                 source_rates = icl_rates;
 538                 size = ARRAY_SIZE(icl_rates);
 539                 if (IS_DG2(dev_priv))
 540                         max_rate = dg2_max_source_rate(intel_dp);
 541                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 542                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 543                         max_rate = 810000;
 544                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 545                         max_rate = ehl_max_source_rate(intel_dp);
 546                 else
 547                         max_rate = icl_max_source_rate(intel_dp);
 548         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 549                 source_rates = bxt_rates;
 550                 size = ARRAY_SIZE(bxt_rates);
 551         } else if (DISPLAY_VER(dev_priv) == 9) {
 552                 source_rates = skl_rates;
 553                 size = ARRAY_SIZE(skl_rates);
 554         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 555                    IS_BROADWELL(dev_priv)) {
 556                 source_rates = hsw_rates;
 557                 size = ARRAY_SIZE(hsw_rates);
 558         } else {
 559                 source_rates = g4x_rates;
 560                 size = ARRAY_SIZE(g4x_rates);
 561         }
 562
 563         vbt_max_rate = vbt_max_link_rate(intel_dp);
 564         if (max_rate && vbt_max_rate)
 565                 max_rate = min(max_rate, vbt_max_rate);
 566         else if (vbt_max_rate)
 567                 max_rate = vbt_max_rate;
 568
 569         if (max_rate)
 570                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 571
 572         intel_dp->source_rates = source_rates;
 573         intel_dp->num_source_rates = size;
 574 }
 575
 576 static int intersect_rates(const int *source_rates, int source_len,
 577                            const int *sink_rates, int sink_len,
 578                            int *common_rates)
 579 {
 580         int i = 0, j = 0, k = 0;
 581
 582         while (i < source_len && j < sink_len) {
 583                 if (source_rates[i] == sink_rates[j]) {
 584                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 585                                 return k;
 586                         common_rates[k] = source_rates[i];
 587                         ++k;
 588                         ++i;
 589                         ++j;
 590                 } else if (source_rates[i] < sink_rates[j]) {
 591                         ++i;
 592                 } else {
 593                         ++j;
 594                 }
 595         }
 596         return k;
 597 }
 598
 599 /* return index of rate in rates array, or -1 if not found */
 600 static int intel_dp_rate_index(const int *rates, int len, int rate)
 601 {
 602         int i;
 603
 604         for (i = 0; i < len; i++)
 605                 if (rate == rates[i])
 606                         return i;
 607
 608         return -1;
 609 }
 610
 611 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 612 {
 613         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 614
 615         drm_WARN_ON(&i915->drm,
 616                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 617
 618         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 619                                                      intel_dp->num_source_rates,
 620                                                      intel_dp->sink_rates,
 621                                                      intel_dp->num_sink_rates,
 622                                                      intel_dp->common_rates);
 623
 624         /* Paranoia, there should always be something in common. */
 625         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 626                 intel_dp->common_rates[0] = 162000;
 627                 intel_dp->num_common_rates = 1;
 628         }
 629 }
 630
 631 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 632                                        u8 lane_count)
 633 {
 634         /*
 635          * FIXME: we need to synchronize the current link parameters with
 636          * hardware readout. Currently fast link training doesn't work on
 637          * boot-up.
 638          */
 639         if (link_rate == 0 ||
 640             link_rate > intel_dp->max_link_rate)
 641                 return false;
 642
 643         if (lane_count == 0 ||
 644             lane_count > intel_dp_max_lane_count(intel_dp))
 645                 return false;
 646
 647         return true;
 648 }
 649
 650 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 651                                                      int link_rate,
 652                                                      u8 lane_count)
 653 {
 654         /* FIXME figure out what we actually want here */
 655         const struct drm_display_mode *fixed_mode =
 656                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 657         int mode_rate, max_rate;
 658
 659         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 660         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 661         if (mode_rate > max_rate)
 662                 return false;
 663
 664         return true;
 665 }
 666
 667 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 668                                             int link_rate, u8 lane_count)
 669 {
 670         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 671         int index;
 672
 673         /*
 674          * TODO: Enable fallback on MST links once MST link compute can handle
 675          * the fallback params.
 676          */
 677         if (intel_dp->is_mst) {
 678                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 679                 return -1;
 680         }
 681
 682         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 683                 drm_dbg_kms(&i915->drm,
 684                             "Retrying Link training for eDP with max parameters\n");
 685                 intel_dp->use_max_params = true;
 686                 return 0;
 687         }
 688
 689         index = intel_dp_rate_index(intel_dp->common_rates,
 690                                     intel_dp->num_common_rates,
 691                                     link_rate);
 692         if (index > 0) {
 693                 if (intel_dp_is_edp(intel_dp) &&
 694                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 695                                                               intel_dp_common_rate(intel_dp, index - 1),
 696                                                               lane_count)) {
 697                         drm_dbg_kms(&i915->drm,
 698                                     "Retrying Link training for eDP with same parameters\n");
 699                         return 0;
 700                 }
 701                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 702                 intel_dp->max_link_lane_count = lane_count;
 703         } else if (lane_count > 1) {
 704                 if (intel_dp_is_edp(intel_dp) &&
 705                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 706                                                               intel_dp_max_common_rate(intel_dp),
 707                                                               lane_count >> 1)) {
 708                         drm_dbg_kms(&i915->drm,
 709                                     "Retrying Link training for eDP with same parameters\n");
 710                         return 0;
 711                 }
 712                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 713                 intel_dp->max_link_lane_count = lane_count >> 1;
 714         } else {
 715                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 716                 return -1;
 717         }
 718
 719         return 0;
 720 }
 721
 722 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 723 {
 724         return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
 725                        1000000U);
 726 }
 727
 728 int intel_dp_bw_fec_overhead(bool fec_enabled)
 729 {
 730         /*
 731          * TODO: Calculate the actual overhead for a given mode.
 732          * The hard-coded 1/0.972261=2.853% overhead factor
 733          * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
 734          * 0.453% DSC overhead. This is enough for a 3840 width mode,
 735          * which has a DSC overhead of up to ~0.2%, but may not be
 736          * enough for a 1024 width mode where this is ~0.8% (on a 4
 737          * lane DP link, with 2 DSC slices and 8 bpp color depth).
 738          */
 739         return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
 740 }
 741
 742 static int
 743 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 744 {
 745         if (DISPLAY_VER(i915) >= 13)
 746                 return 17280 * 8;
 747         else if (DISPLAY_VER(i915) >= 11)
 748                 return 7680 * 8;
 749         else
 750                 return 6144 * 8;
 751 }
 752
 753 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 754 {
 755         u32 bits_per_pixel = bpp;
 756         int i;
 757
 758         /* Error out if the max bpp is less than smallest allowed valid bpp */
 759         if (bits_per_pixel < valid_dsc_bpp[0]) {
 760                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 761                             bits_per_pixel, valid_dsc_bpp[0]);
 762                 return 0;
 763         }
 764
 765         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 766         if (DISPLAY_VER(i915) >= 13) {
 767                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 768
 769                 /*
 770                  * According to BSpec, 27 is the max DSC output bpp,
 771                  * 8 is the min DSC output bpp.
 772                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 773                  * if it is required to oompress up to bpp < 8, means we can't do
 774                  * that and probably means we can't fit the required mode, even with
 775                  * DSC enabled.
 776                  */
 777                 if (bits_per_pixel < 8) {
 778                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 779                                     bits_per_pixel);
 780                         return 0;
 781                 }
 782                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 783         } else {
 784                 /* Find the nearest match in the array of known BPPs from VESA */
 785                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 786                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 787                                 break;
 788                 }
 789                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 790                             bits_per_pixel, valid_dsc_bpp[i]);
 791
 792                 bits_per_pixel = valid_dsc_bpp[i];
 793         }
 794
 795         return bits_per_pixel;
 796 }
 797
 798 static
 799 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 800                                        u32 mode_clock, u32 mode_hdisplay,
 801                                        bool bigjoiner)
 802 {
 803         u32 max_bpp_small_joiner_ram;
 804
 805         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 806         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 807
 808         if (bigjoiner) {
 809                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 810                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 811                 int ppc = 2;
 812                 u32 max_bpp_bigjoiner =
 813                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 814                         intel_dp_mode_to_fec_clock(mode_clock);
 815
 816                 max_bpp_small_joiner_ram *= 2;
 817
 818                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 819         }
 820
 821         return max_bpp_small_joiner_ram;
 822 }
 823
 824 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 825                                         u32 link_clock, u32 lane_count,
 826                                         u32 mode_clock, u32 mode_hdisplay,
 827                                         bool bigjoiner,
 828                                         enum intel_output_format output_format,
 829                                         u32 pipe_bpp,
 830                                         u32 timeslots)
 831 {
 832         u32 bits_per_pixel, joiner_max_bpp;
 833
 834         /*
 835          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 836          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 837          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 838          * for MST -> TimeSlots has to be calculated, based on mode requirements
 839          *
 840          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 841          * To support the given mode:
 842          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 843          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 844          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 845          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 846          *                     (ModeClock / FEC Overhead)
 847          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 848          *                     (ModeClock / FEC Overhead * 8)
 849          */
 850         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 851                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 852
 853         /* Bandwidth required for 420 is half, that of 444 format */
 854         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 855                 bits_per_pixel *= 2;
 856
 857         /*
 858          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 859          * supported PPS value can be 63.9375 and with the further
 860          * mention that for 420, 422 formats, bpp should be programmed double
 861          * the target bpp restricting our target bpp to be 31.9375 at max.
 862          */
 863         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 864                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 865
 866         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 867                                 "total bw %u pixel clock %u\n",
 868                                 bits_per_pixel, timeslots,
 869                                 (link_clock * lane_count * 8),
 870                                 intel_dp_mode_to_fec_clock(mode_clock));
 871
 872         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 873                                                             mode_hdisplay, bigjoiner);
 874         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 875
 876         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 877
 878         return bits_per_pixel;
 879 }
 880
 881 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 882                                 int mode_clock, int mode_hdisplay,
 883                                 bool bigjoiner)
 884 {
 885         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 886         u8 min_slice_count, i;
 887         int max_slice_width;
 888
 889         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 890                 min_slice_count = DIV_ROUND_UP(mode_clock,
 891                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 892         else
 893                 min_slice_count = DIV_ROUND_UP(mode_clock,
 894                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 895
 896         /*
 897          * Due to some DSC engine BW limitations, we need to enable second
 898          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 899          */
 900         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 901                 min_slice_count = max_t(u8, min_slice_count, 2);
 902
 903         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 904         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 905                 drm_dbg_kms(&i915->drm,
 906                             "Unsupported slice width %d by DP DSC Sink device\n",
 907                             max_slice_width);
 908                 return 0;
 909         }
 910         /* Also take into account max slice width */
 911         min_slice_count = max_t(u8, min_slice_count,
 912                                 DIV_ROUND_UP(mode_hdisplay,
 913                                              max_slice_width));
 914
 915         /* Find the closest match to the valid slice count values */
 916         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 917                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 918
 919                 if (test_slice_count >
 920                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 921                         break;
 922
 923                 /* big joiner needs small joiner to be enabled */
 924                 if (bigjoiner && test_slice_count < 4)
 925                         continue;
 926
 927                 if (min_slice_count <= test_slice_count)
 928                         return test_slice_count;
 929         }
 930
 931         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 932                     min_slice_count);
 933         return 0;
 934 }
 935
 936 static bool source_can_output(struct intel_dp *intel_dp,
 937                               enum intel_output_format format)
 938 {
 939         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 940
 941         switch (format) {
 942         case INTEL_OUTPUT_FORMAT_RGB:
 943                 return true;
 944
 945         case INTEL_OUTPUT_FORMAT_YCBCR444:
 946                 /*
 947                  * No YCbCr output support on gmch platforms.
 948                  * Also, ILK doesn't seem capable of DP YCbCr output.
 949                  * The displayed image is severly corrupted. SNB+ is fine.
 950                  */
 951                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 952
 953         case INTEL_OUTPUT_FORMAT_YCBCR420:
 954                 /* Platform < Gen 11 cannot output YCbCr420 format */
 955                 return DISPLAY_VER(i915) >= 11;
 956
 957         default:
 958                 MISSING_CASE(format);
 959                 return false;
 960         }
 961 }
 962
 963 static bool
 964 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 965                          enum intel_output_format sink_format)
 966 {
 967         if (!drm_dp_is_branch(intel_dp->dpcd))
 968                 return false;
 969
 970         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 971                 return intel_dp->dfp.rgb_to_ycbcr;
 972
 973         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 974                 return intel_dp->dfp.rgb_to_ycbcr &&
 975                         intel_dp->dfp.ycbcr_444_to_420;
 976
 977         return false;
 978 }
 979
 980 static bool
 981 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 982                               enum intel_output_format sink_format)
 983 {
 984         if (!drm_dp_is_branch(intel_dp->dpcd))
 985                 return false;
 986
 987         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 988                 return intel_dp->dfp.ycbcr_444_to_420;
 989
 990         return false;
 991 }
 992
 993 static bool
 994 dfp_can_convert(struct intel_dp *intel_dp,
 995                 enum intel_output_format output_format,
 996                 enum intel_output_format sink_format)
 997 {
 998         switch (output_format) {
 999         case INTEL_OUTPUT_FORMAT_RGB:
1000                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1001         case INTEL_OUTPUT_FORMAT_YCBCR444:
1002                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1003         default:
1004                 MISSING_CASE(output_format);
1005                 return false;
1006         }
1007
1008         return false;
1009 }
1010
1011 static enum intel_output_format
1012 intel_dp_output_format(struct intel_connector *connector,
1013                        enum intel_output_format sink_format)
1014 {
1015         struct intel_dp *intel_dp = intel_attached_dp(connector);
1016         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1017         enum intel_output_format force_dsc_output_format =
1018                 intel_dp->force_dsc_output_format;
1019         enum intel_output_format output_format;
1020         if (force_dsc_output_format) {
1021                 if (source_can_output(intel_dp, force_dsc_output_format) &&
1022                     (!drm_dp_is_branch(intel_dp->dpcd) ||
1023                      sink_format != force_dsc_output_format ||
1024                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1025                         return force_dsc_output_format;
1026
1027                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1028         }
1029
1030         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1031             dfp_can_convert_from_rgb(intel_dp, sink_format))
1032                 output_format = INTEL_OUTPUT_FORMAT_RGB;
1033
1034         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1035                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1036                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1037
1038         else
1039                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1040
1041         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1042
1043         return output_format;
1044 }
1045
1046 int intel_dp_min_bpp(enum intel_output_format output_format)
1047 {
1048         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1049                 return 6 * 3;
1050         else
1051                 return 8 * 3;
1052 }
1053
1054 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1055 {
1056         /*
1057          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1058          * format of the number of bytes per pixel will be half the number
1059          * of bytes of RGB pixel.
1060          */
1061         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1062                 bpp /= 2;
1063
1064         return bpp;
1065 }
1066
1067 static enum intel_output_format
1068 intel_dp_sink_format(struct intel_connector *connector,
1069                      const struct drm_display_mode *mode)
1070 {
1071         const struct drm_display_info *info = &connector->base.display_info;
1072
1073         if (drm_mode_is_420_only(info, mode))
1074                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1075
1076         return INTEL_OUTPUT_FORMAT_RGB;
1077 }
1078
1079 static int
1080 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1081                              const struct drm_display_mode *mode)
1082 {
1083         enum intel_output_format output_format, sink_format;
1084
1085         sink_format = intel_dp_sink_format(connector, mode);
1086
1087         output_format = intel_dp_output_format(connector, sink_format);
1088
1089         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1090 }
1091
1092 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1093                                   int hdisplay)
1094 {
1095         /*
1096          * Older platforms don't like hdisplay==4096 with DP.
1097          *
1098          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1099          * and frame counter increment), but we don't get vblank interrupts,
1100          * and the pipe underruns immediately. The link also doesn't seem
1101          * to get trained properly.
1102          *
1103          * On CHV the vblank interrupts don't seem to disappear but
1104          * otherwise the symptoms are similar.
1105          *
1106          * TODO: confirm the behaviour on HSW+
1107          */
1108         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1109 }
1110
1111 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1112 {
1113         struct intel_connector *connector = intel_dp->attached_connector;
1114         const struct drm_display_info *info = &connector->base.display_info;
1115         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1116
1117         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1118         if (max_tmds_clock && info->max_tmds_clock)
1119                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1120
1121         return max_tmds_clock;
1122 }
1123
1124 static enum drm_mode_status
1125 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1126                           int clock, int bpc,
1127                           enum intel_output_format sink_format,
1128                           bool respect_downstream_limits)
1129 {
1130         int tmds_clock, min_tmds_clock, max_tmds_clock;
1131
1132         if (!respect_downstream_limits)
1133                 return MODE_OK;
1134
1135         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1136
1137         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1138         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1139
1140         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1141                 return MODE_CLOCK_LOW;
1142
1143         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1144                 return MODE_CLOCK_HIGH;
1145
1146         return MODE_OK;
1147 }
1148
1149 static enum drm_mode_status
1150 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1151                                const struct drm_display_mode *mode,
1152                                int target_clock)
1153 {
1154         struct intel_dp *intel_dp = intel_attached_dp(connector);
1155         const struct drm_display_info *info = &connector->base.display_info;
1156         enum drm_mode_status status;
1157         enum intel_output_format sink_format;
1158
1159         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1160         if (intel_dp->dfp.pcon_max_frl_bw) {
1161                 int target_bw;
1162                 int max_frl_bw;
1163                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1164
1165                 target_bw = bpp * target_clock;
1166
1167                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1168
1169                 /* converting bw from Gbps to Kbps*/
1170                 max_frl_bw = max_frl_bw * 1000000;
1171
1172                 if (target_bw > max_frl_bw)
1173                         return MODE_CLOCK_HIGH;
1174
1175                 return MODE_OK;
1176         }
1177
1178         if (intel_dp->dfp.max_dotclock &&
1179             target_clock > intel_dp->dfp.max_dotclock)
1180                 return MODE_CLOCK_HIGH;
1181
1182         sink_format = intel_dp_sink_format(connector, mode);
1183
1184         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1185         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1186                                            8, sink_format, true);
1187
1188         if (status != MODE_OK) {
1189                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1190                     !connector->base.ycbcr_420_allowed ||
1191                     !drm_mode_is_420_also(info, mode))
1192                         return status;
1193                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1194                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1195                                                    8, sink_format, true);
1196                 if (status != MODE_OK)
1197                         return status;
1198         }
1199
1200         return MODE_OK;
1201 }
1202
1203 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1204                              int hdisplay, int clock)
1205 {
1206         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1207
1208         if (!intel_dp_can_bigjoiner(intel_dp))
1209                 return false;
1210
1211         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1212 }
1213
1214 static enum drm_mode_status
1215 intel_dp_mode_valid(struct drm_connector *_connector,
1216                     struct drm_display_mode *mode)
1217 {
1218         struct intel_connector *connector = to_intel_connector(_connector);
1219         struct intel_dp *intel_dp = intel_attached_dp(connector);
1220         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1221         const struct drm_display_mode *fixed_mode;
1222         int target_clock = mode->clock;
1223         int max_rate, mode_rate, max_lanes, max_link_clock;
1224         int max_dotclk = dev_priv->max_dotclk_freq;
1225         u16 dsc_max_compressed_bpp = 0;
1226         u8 dsc_slice_count = 0;
1227         enum drm_mode_status status;
1228         bool dsc = false, bigjoiner = false;
1229
1230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1231                 return MODE_H_ILLEGAL;
1232
1233         fixed_mode = intel_panel_fixed_mode(connector, mode);
1234         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1235                 status = intel_panel_mode_valid(connector, mode);
1236                 if (status != MODE_OK)
1237                         return status;
1238
1239                 target_clock = fixed_mode->clock;
1240         }
1241
1242         if (mode->clock < 10000)
1243                 return MODE_CLOCK_LOW;
1244
1245         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1246                 bigjoiner = true;
1247                 max_dotclk *= 2;
1248         }
1249         if (target_clock > max_dotclk)
1250                 return MODE_CLOCK_HIGH;
1251
1252         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1253                 return MODE_H_ILLEGAL;
1254
1255         max_link_clock = intel_dp_max_link_rate(intel_dp);
1256         max_lanes = intel_dp_max_lane_count(intel_dp);
1257
1258         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1259         mode_rate = intel_dp_link_required(target_clock,
1260                                            intel_dp_mode_min_output_bpp(connector, mode));
1261
1262         if (HAS_DSC(dev_priv) &&
1263             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1264                 enum intel_output_format sink_format, output_format;
1265                 int pipe_bpp;
1266
1267                 sink_format = intel_dp_sink_format(connector, mode);
1268                 output_format = intel_dp_output_format(connector, sink_format);
1269                 /*
1270                  * TBD pass the connector BPC,
1271                  * for now U8_MAX so that max BPC on that platform would be picked
1272                  */
1273                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1274
1275                 /*
1276                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1277                  * integer value since we support only integer values of bpp.
1278                  */
1279                 if (intel_dp_is_edp(intel_dp)) {
1280                         dsc_max_compressed_bpp =
1281                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1282                         dsc_slice_count =
1283                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1284                                                                 true);
1285                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1286                         dsc_max_compressed_bpp =
1287                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1288                                                                     max_link_clock,
1289                                                                     max_lanes,
1290                                                                     target_clock,
1291                                                                     mode->hdisplay,
1292                                                                     bigjoiner,
1293                                                                     output_format,
1294                                                                     pipe_bpp, 64);
1295                         dsc_slice_count =
1296                                 intel_dp_dsc_get_slice_count(connector,
1297                                                              target_clock,
1298                                                              mode->hdisplay,
1299                                                              bigjoiner);
1300                 }
1301
1302                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1303         }
1304
1305         /*
1306          * Big joiner configuration needs DSC for TGL which is not true for
1307          * XE_LPD where uncompressed joiner is supported.
1308          */
1309         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1310                 return MODE_CLOCK_HIGH;
1311
1312         if (mode_rate > max_rate && !dsc)
1313                 return MODE_CLOCK_HIGH;
1314
1315         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1316         if (status != MODE_OK)
1317                 return status;
1318
1319         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1320 }
1321
1322 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1323 {
1324         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1325 }
1326
1327 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1328 {
1329         return DISPLAY_VER(i915) >= 10;
1330 }
1331
1332 static void snprintf_int_array(char *str, size_t len,
1333                                const int *array, int nelem)
1334 {
1335         int i;
1336
1337         str[0] = '\0';
1338
1339         for (i = 0; i < nelem; i++) {
1340                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1341                 if (r >= len)
1342                         return;
1343                 str += r;
1344                 len -= r;
1345         }
1346 }
1347
1348 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1349 {
1350         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1351         char str[128]; /* FIXME: too big for stack? */
1352
1353         if (!drm_debug_enabled(DRM_UT_KMS))
1354                 return;
1355
1356         snprintf_int_array(str, sizeof(str),
1357                            intel_dp->source_rates, intel_dp->num_source_rates);
1358         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1359
1360         snprintf_int_array(str, sizeof(str),
1361                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1362         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1363
1364         snprintf_int_array(str, sizeof(str),
1365                            intel_dp->common_rates, intel_dp->num_common_rates);
1366         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1367 }
1368
1369 int
1370 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1371 {
1372         int len;
1373
1374         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1375
1376         return intel_dp_common_rate(intel_dp, len - 1);
1377 }
1378
1379 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1380 {
1381         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1382         int i = intel_dp_rate_index(intel_dp->sink_rates,
1383                                     intel_dp->num_sink_rates, rate);
1384
1385         if (drm_WARN_ON(&i915->drm, i < 0))
1386                 i = 0;
1387
1388         return i;
1389 }
1390
1391 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1392                            u8 *link_bw, u8 *rate_select)
1393 {
1394         /* eDP 1.4 rate select method. */
1395         if (intel_dp->use_rate_select) {
1396                 *link_bw = 0;
1397                 *rate_select =
1398                         intel_dp_rate_select(intel_dp, port_clock);
1399         } else {
1400                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1401                 *rate_select = 0;
1402         }
1403 }
1404
1405 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1406 {
1407         struct intel_connector *connector = intel_dp->attached_connector;
1408
1409         return connector->base.display_info.is_hdmi;
1410 }
1411
1412 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1413                                          const struct intel_crtc_state *pipe_config)
1414 {
1415         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1416         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1417
1418         if (DISPLAY_VER(dev_priv) >= 12)
1419                 return true;
1420
1421         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1422                 return true;
1423
1424         return false;
1425 }
1426
1427 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1428                            const struct intel_connector *connector,
1429                            const struct intel_crtc_state *pipe_config)
1430 {
1431         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1432                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1433 }
1434
1435 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1436                                   const struct intel_crtc_state *crtc_state)
1437 {
1438         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1439                 return false;
1440
1441         return intel_dsc_source_support(crtc_state) &&
1442                 connector->dp.dsc_decompression_aux &&
1443                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1444 }
1445
1446 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1447                                      const struct intel_crtc_state *crtc_state,
1448                                      int bpc, bool respect_downstream_limits)
1449 {
1450         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1451
1452         /*
1453          * Current bpc could already be below 8bpc due to
1454          * FDI bandwidth constraints or other limits.
1455          * HDMI minimum is 8bpc however.
1456          */
1457         bpc = max(bpc, 8);
1458
1459         /*
1460          * We will never exceed downstream TMDS clock limits while
1461          * attempting deep color. If the user insists on forcing an
1462          * out of spec mode they will have to be satisfied with 8bpc.
1463          */
1464         if (!respect_downstream_limits)
1465                 bpc = 8;
1466
1467         for (; bpc >= 8; bpc -= 2) {
1468                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1469                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1470                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1471                                               respect_downstream_limits) == MODE_OK)
1472                         return bpc;
1473         }
1474
1475         return -EINVAL;
1476 }
1477
1478 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1479                             const struct intel_crtc_state *crtc_state,
1480                             bool respect_downstream_limits)
1481 {
1482         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1483         struct intel_connector *intel_connector = intel_dp->attached_connector;
1484         int bpp, bpc;
1485
1486         bpc = crtc_state->pipe_bpp / 3;
1487
1488         if (intel_dp->dfp.max_bpc)
1489                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1490
1491         if (intel_dp->dfp.min_tmds_clock) {
1492                 int max_hdmi_bpc;
1493
1494                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1495                                                          respect_downstream_limits);
1496                 if (max_hdmi_bpc < 0)
1497                         return 0;
1498
1499                 bpc = min(bpc, max_hdmi_bpc);
1500         }
1501
1502         bpp = bpc * 3;
1503         if (intel_dp_is_edp(intel_dp)) {
1504                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1505                 if (intel_connector->base.display_info.bpc == 0 &&
1506                     intel_connector->panel.vbt.edp.bpp &&
1507                     intel_connector->panel.vbt.edp.bpp < bpp) {
1508                         drm_dbg_kms(&dev_priv->drm,
1509                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1510                                     intel_connector->panel.vbt.edp.bpp);
1511                         bpp = intel_connector->panel.vbt.edp.bpp;
1512                 }
1513         }
1514
1515         return bpp;
1516 }
1517
1518 /* Adjust link config limits based on compliance test requests. */
1519 void
1520 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1521                                   struct intel_crtc_state *pipe_config,
1522                                   struct link_config_limits *limits)
1523 {
1524         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1525
1526         /* For DP Compliance we override the computed bpp for the pipe */
1527         if (intel_dp->compliance.test_data.bpc != 0) {
1528                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1529
1530                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1531                 pipe_config->dither_force_disable = bpp == 6 * 3;
1532
1533                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1534         }
1535
1536         /* Use values requested by Compliance Test Request */
1537         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1538                 int index;
1539
1540                 /* Validate the compliance test data since max values
1541                  * might have changed due to link train fallback.
1542                  */
1543                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1544                                                intel_dp->compliance.test_lane_count)) {
1545                         index = intel_dp_rate_index(intel_dp->common_rates,
1546                                                     intel_dp->num_common_rates,
1547                                                     intel_dp->compliance.test_link_rate);
1548                         if (index >= 0)
1549                                 limits->min_rate = limits->max_rate =
1550                                         intel_dp->compliance.test_link_rate;
1551                         limits->min_lane_count = limits->max_lane_count =
1552                                 intel_dp->compliance.test_lane_count;
1553                 }
1554         }
1555 }
1556
1557 static bool has_seamless_m_n(struct intel_connector *connector)
1558 {
1559         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1560
1561         /*
1562          * Seamless M/N reprogramming only implemented
1563          * for BDW+ double buffered M/N registers so far.
1564          */
1565         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1566                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1567 }
1568
1569 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1570                                const struct drm_connector_state *conn_state)
1571 {
1572         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1573         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1574
1575         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1576         if (has_seamless_m_n(connector))
1577                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1578         else
1579                 return adjusted_mode->crtc_clock;
1580 }
1581
1582 /* Optimize link config in order: max bpp, min clock, min lanes */
1583 static int
1584 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1585                                   struct intel_crtc_state *pipe_config,
1586                                   const struct drm_connector_state *conn_state,
1587                                   const struct link_config_limits *limits)
1588 {
1589         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1590         int mode_rate, link_rate, link_avail;
1591
1592         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1593              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1594              bpp -= 2 * 3) {
1595                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1596
1597                 mode_rate = intel_dp_link_required(clock, link_bpp);
1598
1599                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1600                         link_rate = intel_dp_common_rate(intel_dp, i);
1601                         if (link_rate < limits->min_rate ||
1602                             link_rate > limits->max_rate)
1603                                 continue;
1604
1605                         for (lane_count = limits->min_lane_count;
1606                              lane_count <= limits->max_lane_count;
1607                              lane_count <<= 1) {
1608                                 link_avail = intel_dp_max_data_rate(link_rate,
1609                                                                     lane_count);
1610
1611                                 if (mode_rate <= link_avail) {
1612                                         pipe_config->lane_count = lane_count;
1613                                         pipe_config->pipe_bpp = bpp;
1614                                         pipe_config->port_clock = link_rate;
1615
1616                                         return 0;
1617                                 }
1618                         }
1619                 }
1620         }
1621
1622         return -EINVAL;
1623 }
1624
1625 static
1626 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1627 {
1628         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1629         if (DISPLAY_VER(i915) >= 12)
1630                 return 12;
1631         if (DISPLAY_VER(i915) == 11)
1632                 return 10;
1633
1634         return 0;
1635 }
1636
1637 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1638                                  u8 max_req_bpc)
1639 {
1640         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1641         int i, num_bpc;
1642         u8 dsc_bpc[3] = {};
1643         u8 dsc_max_bpc;
1644
1645         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1646
1647         if (!dsc_max_bpc)
1648                 return dsc_max_bpc;
1649
1650         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1651
1652         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1653                                                        dsc_bpc);
1654         for (i = 0; i < num_bpc; i++) {
1655                 if (dsc_max_bpc >= dsc_bpc[i])
1656                         return dsc_bpc[i] * 3;
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1663 {
1664         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1665 }
1666
1667 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1668 {
1669         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1670                 DP_DSC_MINOR_SHIFT;
1671 }
1672
1673 static int intel_dp_get_slice_height(int vactive)
1674 {
1675         int slice_height;
1676
1677         /*
1678          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1679          * lines is an optimal slice height, but any size can be used as long as
1680          * vertical active integer multiple and maximum vertical slice count
1681          * requirements are met.
1682          */
1683         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1684                 if (vactive % slice_height == 0)
1685                         return slice_height;
1686
1687         /*
1688          * Highly unlikely we reach here as most of the resolutions will end up
1689          * finding appropriate slice_height in above loop but returning
1690          * slice_height as 2 here as it should work with all resolutions.
1691          */
1692         return 2;
1693 }
1694
1695 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1696                                        struct intel_crtc_state *crtc_state)
1697 {
1698         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1699         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1700         u8 line_buf_depth;
1701         int ret;
1702
1703         /*
1704          * RC_MODEL_SIZE is currently a constant across all configurations.
1705          *
1706          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1707          * DP_DSC_RC_BUF_SIZE for this.
1708          */
1709         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1710         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1711
1712         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1713
1714         ret = intel_dsc_compute_params(crtc_state);
1715         if (ret)
1716                 return ret;
1717
1718         vdsc_cfg->dsc_version_major =
1719                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1720                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1721         vdsc_cfg->dsc_version_minor =
1722                 min(intel_dp_source_dsc_version_minor(i915),
1723                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1724         if (vdsc_cfg->convert_rgb)
1725                 vdsc_cfg->convert_rgb =
1726                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1727                         DP_DSC_RGB;
1728
1729         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1730         if (!line_buf_depth) {
1731                 drm_dbg_kms(&i915->drm,
1732                             "DSC Sink Line Buffer Depth invalid\n");
1733                 return -EINVAL;
1734         }
1735
1736         if (vdsc_cfg->dsc_version_minor == 2)
1737                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1738                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1739         else
1740                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1741                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1742
1743         vdsc_cfg->block_pred_enable =
1744                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1745                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1746
1747         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1748 }
1749
1750 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1751                                          enum intel_output_format output_format)
1752 {
1753         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1754         u8 sink_dsc_format;
1755
1756         switch (output_format) {
1757         case INTEL_OUTPUT_FORMAT_RGB:
1758                 sink_dsc_format = DP_DSC_RGB;
1759                 break;
1760         case INTEL_OUTPUT_FORMAT_YCBCR444:
1761                 sink_dsc_format = DP_DSC_YCbCr444;
1762                 break;
1763         case INTEL_OUTPUT_FORMAT_YCBCR420:
1764                 if (min(intel_dp_source_dsc_version_minor(i915),
1765                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1766                         return false;
1767                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1768                 break;
1769         default:
1770                 return false;
1771         }
1772
1773         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1774 }
1775
1776 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1777                                             u32 lane_count, u32 mode_clock,
1778                                             enum intel_output_format output_format,
1779                                             int timeslots)
1780 {
1781         u32 available_bw, required_bw;
1782
1783         available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
1784         required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1785
1786         return available_bw > required_bw;
1787 }
1788
1789 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1790                                    struct intel_crtc_state *pipe_config,
1791                                    struct link_config_limits *limits,
1792                                    u16 compressed_bppx16,
1793                                    int timeslots)
1794 {
1795         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1796         int link_rate, lane_count;
1797         int i;
1798
1799         for (i = 0; i < intel_dp->num_common_rates; i++) {
1800                 link_rate = intel_dp_common_rate(intel_dp, i);
1801                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1802                         continue;
1803
1804                 for (lane_count = limits->min_lane_count;
1805                      lane_count <= limits->max_lane_count;
1806                      lane_count <<= 1) {
1807                         if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1808                                                              lane_count, adjusted_mode->clock,
1809                                                              pipe_config->output_format,
1810                                                              timeslots))
1811                                 continue;
1812
1813                         pipe_config->lane_count = lane_count;
1814                         pipe_config->port_clock = link_rate;
1815
1816                         return 0;
1817                 }
1818         }
1819
1820         return -EINVAL;
1821 }
1822
1823 static
1824 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1825                                             struct intel_crtc_state *pipe_config,
1826                                             int bpc)
1827 {
1828         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1829
1830         if (max_bppx16)
1831                 return max_bppx16;
1832         /*
1833          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1834          * values as given in spec Table 2-157 DP v2.0
1835          */
1836         switch (pipe_config->output_format) {
1837         case INTEL_OUTPUT_FORMAT_RGB:
1838         case INTEL_OUTPUT_FORMAT_YCBCR444:
1839                 return (3 * bpc) << 4;
1840         case INTEL_OUTPUT_FORMAT_YCBCR420:
1841                 return (3 * (bpc / 2)) << 4;
1842         default:
1843                 MISSING_CASE(pipe_config->output_format);
1844                 break;
1845         }
1846
1847         return 0;
1848 }
1849
1850 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1851 {
1852         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1853         switch (pipe_config->output_format) {
1854         case INTEL_OUTPUT_FORMAT_RGB:
1855         case INTEL_OUTPUT_FORMAT_YCBCR444:
1856                 return 8;
1857         case INTEL_OUTPUT_FORMAT_YCBCR420:
1858                 return 6;
1859         default:
1860                 MISSING_CASE(pipe_config->output_format);
1861                 break;
1862         }
1863
1864         return 0;
1865 }
1866
1867 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1868                                          struct intel_crtc_state *pipe_config,
1869                                          int bpc)
1870 {
1871         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1872                                                        pipe_config, bpc) >> 4;
1873 }
1874
1875 static int dsc_src_min_compressed_bpp(void)
1876 {
1877         /* Min Compressed bpp supported by source is 8 */
1878         return 8;
1879 }
1880
1881 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1882 {
1883         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1884
1885         /*
1886          * Max Compressed bpp for Gen 13+ is 27bpp.
1887          * For earlier platform is 23bpp. (Bspec:49259).
1888          */
1889         if (DISPLAY_VER(i915) <= 12)
1890                 return 23;
1891         else
1892                 return 27;
1893 }
1894
1895 /*
1896  * From a list of valid compressed bpps try different compressed bpp and find a
1897  * suitable link configuration that can support it.
1898  */
1899 static int
1900 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1901                             struct intel_crtc_state *pipe_config,
1902                             struct link_config_limits *limits,
1903                             int dsc_max_bpp,
1904                             int dsc_min_bpp,
1905                             int pipe_bpp,
1906                             int timeslots)
1907 {
1908         int i, ret;
1909
1910         /* Compressed BPP should be less than the Input DSC bpp */
1911         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1912
1913         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1914                 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1915                     valid_dsc_bpp[i] > dsc_max_bpp)
1916                         break;
1917
1918                 ret = dsc_compute_link_config(intel_dp,
1919                                               pipe_config,
1920                                               limits,
1921                                               valid_dsc_bpp[i] << 4,
1922                                               timeslots);
1923                 if (ret == 0) {
1924                         pipe_config->dsc.compressed_bpp_x16 =
1925                                 to_bpp_x16(valid_dsc_bpp[i]);
1926                         return 0;
1927                 }
1928         }
1929
1930         return -EINVAL;
1931 }
1932
1933 /*
1934  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1935  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1936  * link configuration is able to support that compressed bpp, if not we
1937  * step down and check for lower compressed bpp.
1938  */
1939 static int
1940 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1941                               const struct intel_connector *connector,
1942                               struct intel_crtc_state *pipe_config,
1943                               struct link_config_limits *limits,
1944                               int dsc_max_bpp,
1945                               int dsc_min_bpp,
1946                               int pipe_bpp,
1947                               int timeslots)
1948 {
1949         u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
1950         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1951         u16 compressed_bppx16;
1952         u8 bppx16_step;
1953         int ret;
1954
1955         if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
1956                 bppx16_step = 16;
1957         else
1958                 bppx16_step = 16 / bppx16_incr;
1959
1960         /* Compressed BPP should be less than the Input DSC bpp */
1961         dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
1962         dsc_min_bpp = dsc_min_bpp << 4;
1963
1964         for (compressed_bppx16 = dsc_max_bpp;
1965              compressed_bppx16 >= dsc_min_bpp;
1966              compressed_bppx16 -= bppx16_step) {
1967                 if (intel_dp->force_dsc_fractional_bpp_en &&
1968                     !to_bpp_frac(compressed_bppx16))
1969                         continue;
1970                 ret = dsc_compute_link_config(intel_dp,
1971                                               pipe_config,
1972                                               limits,
1973                                               compressed_bppx16,
1974                                               timeslots);
1975                 if (ret == 0) {
1976                         pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
1977                         if (intel_dp->force_dsc_fractional_bpp_en &&
1978                             to_bpp_frac(compressed_bppx16))
1979                                 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
1980
1981                         return 0;
1982                 }
1983         }
1984         return -EINVAL;
1985 }
1986
1987 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1988                                       const struct intel_connector *connector,
1989                                       struct intel_crtc_state *pipe_config,
1990                                       struct link_config_limits *limits,
1991                                       int pipe_bpp,
1992                                       int timeslots)
1993 {
1994         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1995         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1996         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
1997         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
1998         int dsc_joiner_max_bpp;
1999
2000         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2001         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2002         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2003         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2004
2005         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2006         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2007                                                                 pipe_config,
2008                                                                 pipe_bpp / 3);
2009         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2010
2011         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2012                                                                 adjusted_mode->hdisplay,
2013                                                                 pipe_config->bigjoiner_pipes);
2014         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2015         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2016
2017         if (DISPLAY_VER(i915) >= 13)
2018                 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2019                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2020         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2021                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2022 }
2023
2024 static
2025 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2026 {
2027         /* Min DSC Input BPC for ICL+ is 8 */
2028         return HAS_DSC(i915) ? 8 : 0;
2029 }
2030
2031 static
2032 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2033                                 struct drm_connector_state *conn_state,
2034                                 struct link_config_limits *limits,
2035                                 int pipe_bpp)
2036 {
2037         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2038
2039         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2040         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2041
2042         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2043         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2044
2045         return pipe_bpp >= dsc_min_pipe_bpp &&
2046                pipe_bpp <= dsc_max_pipe_bpp;
2047 }
2048
2049 static
2050 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2051                                 struct drm_connector_state *conn_state,
2052                                 struct link_config_limits *limits)
2053 {
2054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2055         int forced_bpp;
2056
2057         if (!intel_dp->force_dsc_bpc)
2058                 return 0;
2059
2060         forced_bpp = intel_dp->force_dsc_bpc * 3;
2061
2062         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2063                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2064                 return forced_bpp;
2065         }
2066
2067         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2068                     intel_dp->force_dsc_bpc);
2069
2070         return 0;
2071 }
2072
2073 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2074                                          struct intel_crtc_state *pipe_config,
2075                                          struct drm_connector_state *conn_state,
2076                                          struct link_config_limits *limits,
2077                                          int timeslots)
2078 {
2079         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2080         const struct intel_connector *connector =
2081                 to_intel_connector(conn_state->connector);
2082         u8 max_req_bpc = conn_state->max_requested_bpc;
2083         u8 dsc_max_bpc, dsc_max_bpp;
2084         u8 dsc_min_bpc, dsc_min_bpp;
2085         u8 dsc_bpc[3] = {};
2086         int forced_bpp, pipe_bpp;
2087         int num_bpc, i, ret;
2088
2089         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2090
2091         if (forced_bpp) {
2092                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2093                                                  limits, forced_bpp, timeslots);
2094                 if (ret == 0) {
2095                         pipe_config->pipe_bpp = forced_bpp;
2096                         return 0;
2097                 }
2098         }
2099
2100         dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2101         if (!dsc_max_bpc)
2102                 return -EINVAL;
2103
2104         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2105         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2106
2107         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2108         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2109
2110         /*
2111          * Get the maximum DSC bpc that will be supported by any valid
2112          * link configuration and compressed bpp.
2113          */
2114         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2115         for (i = 0; i < num_bpc; i++) {
2116                 pipe_bpp = dsc_bpc[i] * 3;
2117                 if (pipe_bpp < dsc_min_bpp)
2118                         break;
2119                 if (pipe_bpp > dsc_max_bpp)
2120                         continue;
2121                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2122                                                  limits, pipe_bpp, timeslots);
2123                 if (ret == 0) {
2124                         pipe_config->pipe_bpp = pipe_bpp;
2125                         return 0;
2126                 }
2127         }
2128
2129         return -EINVAL;
2130 }
2131
2132 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2133                                           struct intel_crtc_state *pipe_config,
2134                                           struct drm_connector_state *conn_state,
2135                                           struct link_config_limits *limits)
2136 {
2137         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2138         struct intel_connector *connector =
2139                 to_intel_connector(conn_state->connector);
2140         int pipe_bpp, forced_bpp;
2141         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2142         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2143
2144         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2145
2146         if (forced_bpp) {
2147                 pipe_bpp = forced_bpp;
2148         } else {
2149                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2150
2151                 /* For eDP use max bpp that can be supported with DSC. */
2152                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2153                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2154                         drm_dbg_kms(&i915->drm,
2155                                     "Computed BPC is not in DSC BPC limits\n");
2156                         return -EINVAL;
2157                 }
2158         }
2159         pipe_config->port_clock = limits->max_rate;
2160         pipe_config->lane_count = limits->max_lane_count;
2161
2162         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2163         dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
2164         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2165         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2166
2167         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2168         dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2169                                                                 pipe_config,
2170                                                                 pipe_bpp / 3);
2171         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2172         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2173
2174         /* Compressed BPP should be less than the Input DSC bpp */
2175         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2176
2177         pipe_config->dsc.compressed_bpp_x16 =
2178                 to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
2179
2180         pipe_config->pipe_bpp = pipe_bpp;
2181
2182         return 0;
2183 }
2184
2185 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2186                                 struct intel_crtc_state *pipe_config,
2187                                 struct drm_connector_state *conn_state,
2188                                 struct link_config_limits *limits,
2189                                 int timeslots,
2190                                 bool compute_pipe_bpp)
2191 {
2192         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2193         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2194         const struct intel_connector *connector =
2195                 to_intel_connector(conn_state->connector);
2196         const struct drm_display_mode *adjusted_mode =
2197                 &pipe_config->hw.adjusted_mode;
2198         int ret;
2199
2200         pipe_config->fec_enable = pipe_config->fec_enable ||
2201                 (!intel_dp_is_edp(intel_dp) &&
2202                  intel_dp_supports_fec(intel_dp, connector, pipe_config));
2203
2204         if (!intel_dp_supports_dsc(connector, pipe_config))
2205                 return -EINVAL;
2206
2207         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2208                 return -EINVAL;
2209
2210         /*
2211          * compute pipe bpp is set to false for DP MST DSC case
2212          * and compressed_bpp is calculated same time once
2213          * vpci timeslots are allocated, because overall bpp
2214          * calculation procedure is bit different for MST case.
2215          */
2216         if (compute_pipe_bpp) {
2217                 if (intel_dp_is_edp(intel_dp))
2218                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2219                                                              conn_state, limits);
2220                 else
2221                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2222                                                             conn_state, limits, timeslots);
2223                 if (ret) {
2224                         drm_dbg_kms(&dev_priv->drm,
2225                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2226                         return ret;
2227                 }
2228         }
2229
2230         /* Calculate Slice count */
2231         if (intel_dp_is_edp(intel_dp)) {
2232                 pipe_config->dsc.slice_count =
2233                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2234                                                         true);
2235                 if (!pipe_config->dsc.slice_count) {
2236                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2237                                     pipe_config->dsc.slice_count);
2238                         return -EINVAL;
2239                 }
2240         } else {
2241                 u8 dsc_dp_slice_count;
2242
2243                 dsc_dp_slice_count =
2244                         intel_dp_dsc_get_slice_count(connector,
2245                                                      adjusted_mode->crtc_clock,
2246                                                      adjusted_mode->crtc_hdisplay,
2247                                                      pipe_config->bigjoiner_pipes);
2248                 if (!dsc_dp_slice_count) {
2249                         drm_dbg_kms(&dev_priv->drm,
2250                                     "Compressed Slice Count not supported\n");
2251                         return -EINVAL;
2252                 }
2253
2254                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2255         }
2256         /*
2257          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2258          * is greater than the maximum Cdclock and if slice count is even
2259          * then we need to use 2 VDSC instances.
2260          */
2261         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2262                 pipe_config->dsc.dsc_split = true;
2263
2264         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2265         if (ret < 0) {
2266                 drm_dbg_kms(&dev_priv->drm,
2267                             "Cannot compute valid DSC parameters for Input Bpp = %d"
2268                             "Compressed BPP = " BPP_X16_FMT "\n",
2269                             pipe_config->pipe_bpp,
2270                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2271                 return ret;
2272         }
2273
2274         pipe_config->dsc.compression_enable = true;
2275         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2276                     "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
2277                     pipe_config->pipe_bpp,
2278                     BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
2279                     pipe_config->dsc.slice_count);
2280
2281         return 0;
2282 }
2283
2284 /**
2285  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2286  * @intel_dp: intel DP
2287  * @crtc_state: crtc state
2288  * @dsc: DSC compression mode
2289  * @limits: link configuration limits
2290  *
2291  * Calculates the output link min, max bpp values in @limits based on the
2292  * pipe bpp range, @crtc_state and @dsc mode.
2293  *
2294  * Returns %true in case of success.
2295  */
2296 bool
2297 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2298                                         const struct intel_crtc_state *crtc_state,
2299                                         bool dsc,
2300                                         struct link_config_limits *limits)
2301 {
2302         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2303         const struct drm_display_mode *adjusted_mode =
2304                 &crtc_state->hw.adjusted_mode;
2305         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2306         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2307         int max_link_bpp_x16;
2308
2309         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2310                                to_bpp_x16(limits->pipe.max_bpp));
2311
2312         if (!dsc) {
2313                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2314
2315                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2316                         return false;
2317
2318                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2319         } else {
2320                 /*
2321                  * TODO: set the DSC link limits already here, atm these are
2322                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2323                  * intel_dp_dsc_compute_pipe_bpp()
2324                  */
2325                 limits->link.min_bpp_x16 = 0;
2326         }
2327
2328         limits->link.max_bpp_x16 = max_link_bpp_x16;
2329
2330         drm_dbg_kms(&i915->drm,
2331                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2332                     encoder->base.base.id, encoder->base.name,
2333                     crtc->base.base.id, crtc->base.name,
2334                     adjusted_mode->crtc_clock,
2335                     dsc ? "on" : "off",
2336                     limits->max_lane_count,
2337                     limits->max_rate,
2338                     limits->pipe.max_bpp,
2339                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2340
2341         return true;
2342 }
2343
2344 static bool
2345 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2346                                struct intel_crtc_state *crtc_state,
2347                                bool respect_downstream_limits,
2348                                bool dsc,
2349                                struct link_config_limits *limits)
2350 {
2351         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2352         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2353
2354         limits->min_lane_count = 1;
2355         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2356
2357         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2358         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2359                                                      respect_downstream_limits);
2360
2361         if (intel_dp->use_max_params) {
2362                 /*
2363                  * Use the maximum clock and number of lanes the eDP panel
2364                  * advertizes being capable of in case the initial fast
2365                  * optimal params failed us. The panels are generally
2366                  * designed to support only a single clock and lane
2367                  * configuration, and typically on older panels these
2368                  * values correspond to the native resolution of the panel.
2369                  */
2370                 limits->min_lane_count = limits->max_lane_count;
2371                 limits->min_rate = limits->max_rate;
2372         }
2373
2374         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2375
2376         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2377                                                        crtc_state,
2378                                                        dsc,
2379                                                        limits);
2380 }
2381
2382 static int
2383 intel_dp_compute_link_config(struct intel_encoder *encoder,
2384                              struct intel_crtc_state *pipe_config,
2385                              struct drm_connector_state *conn_state,
2386                              bool respect_downstream_limits)
2387 {
2388         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2389         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2390         const struct intel_connector *connector =
2391                 to_intel_connector(conn_state->connector);
2392         const struct drm_display_mode *adjusted_mode =
2393                 &pipe_config->hw.adjusted_mode;
2394         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2395         struct link_config_limits limits;
2396         bool joiner_needs_dsc = false;
2397         bool dsc_needed;
2398         int ret = 0;
2399
2400         if (pipe_config->fec_enable &&
2401             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2402                 return -EINVAL;
2403
2404         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2405                                     adjusted_mode->crtc_clock))
2406                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2407
2408         /*
2409          * Pipe joiner needs compression up to display 12 due to bandwidth
2410          * limitation. DG2 onwards pipe joiner can be enabled without
2411          * compression.
2412          */
2413         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2414
2415         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2416                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2417                                                      respect_downstream_limits,
2418                                                      false,
2419                                                      &limits);
2420
2421         if (!dsc_needed) {
2422                 /*
2423                  * Optimize for slow and wide for everything, because there are some
2424                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2425                  */
2426                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2427                                                         conn_state, &limits);
2428                 if (ret)
2429                         dsc_needed = true;
2430         }
2431
2432         if (dsc_needed) {
2433                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2434                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2435                             str_yes_no(intel_dp->force_dsc_en));
2436
2437                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2438                                                     respect_downstream_limits,
2439                                                     true,
2440                                                     &limits))
2441                         return -EINVAL;
2442
2443                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2444                                                   conn_state, &limits, 64, true);
2445                 if (ret < 0)
2446                         return ret;
2447         }
2448
2449         if (pipe_config->dsc.compression_enable) {
2450                 drm_dbg_kms(&i915->drm,
2451                             "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
2452                             pipe_config->lane_count, pipe_config->port_clock,
2453                             pipe_config->pipe_bpp,
2454                             BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
2455
2456                 drm_dbg_kms(&i915->drm,
2457                             "DP link rate required %i available %i\n",
2458                             intel_dp_link_required(adjusted_mode->crtc_clock,
2459                                                    to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
2460                             intel_dp_max_data_rate(pipe_config->port_clock,
2461                                                    pipe_config->lane_count));
2462         } else {
2463                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2464                             pipe_config->lane_count, pipe_config->port_clock,
2465                             pipe_config->pipe_bpp);
2466
2467                 drm_dbg_kms(&i915->drm,
2468                             "DP link rate required %i available %i\n",
2469                             intel_dp_link_required(adjusted_mode->crtc_clock,
2470                                                    pipe_config->pipe_bpp),
2471                             intel_dp_max_data_rate(pipe_config->port_clock,
2472                                                    pipe_config->lane_count));
2473         }
2474         return 0;
2475 }
2476
2477 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2478                                   const struct drm_connector_state *conn_state)
2479 {
2480         const struct intel_digital_connector_state *intel_conn_state =
2481                 to_intel_digital_connector_state(conn_state);
2482         const struct drm_display_mode *adjusted_mode =
2483                 &crtc_state->hw.adjusted_mode;
2484
2485         /*
2486          * Our YCbCr output is always limited range.
2487          * crtc_state->limited_color_range only applies to RGB,
2488          * and it must never be set for YCbCr or we risk setting
2489          * some conflicting bits in TRANSCONF which will mess up
2490          * the colors on the monitor.
2491          */
2492         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2493                 return false;
2494
2495         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2496                 /*
2497                  * See:
2498                  * CEA-861-E - 5.1 Default Encoding Parameters
2499                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2500                  */
2501                 return crtc_state->pipe_bpp != 18 &&
2502                         drm_default_rgb_quant_range(adjusted_mode) ==
2503                         HDMI_QUANTIZATION_RANGE_LIMITED;
2504         } else {
2505                 return intel_conn_state->broadcast_rgb ==
2506                         INTEL_BROADCAST_RGB_LIMITED;
2507         }
2508 }
2509
2510 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2511                                     enum port port)
2512 {
2513         if (IS_G4X(dev_priv))
2514                 return false;
2515         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2516                 return false;
2517
2518         return true;
2519 }
2520
2521 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2522                                              const struct drm_connector_state *conn_state,
2523                                              struct drm_dp_vsc_sdp *vsc)
2524 {
2525         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2526         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2527
2528         if (crtc_state->has_panel_replay) {
2529                 /*
2530                  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2531                  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2532                  * Encoding/Colorimetry Format indication.
2533                  */
2534                 vsc->revision = 0x7;
2535         } else {
2536                 /*
2537                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2538                  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2539                  * Colorimetry Format indication.
2540                  */
2541                 vsc->revision = 0x5;
2542         }
2543
2544         vsc->length = 0x13;
2545
2546         /* DP 1.4a spec, Table 2-120 */
2547         switch (crtc_state->output_format) {
2548         case INTEL_OUTPUT_FORMAT_YCBCR444:
2549                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2550                 break;
2551         case INTEL_OUTPUT_FORMAT_YCBCR420:
2552                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2553                 break;
2554         case INTEL_OUTPUT_FORMAT_RGB:
2555         default:
2556                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2557         }
2558
2559         switch (conn_state->colorspace) {
2560         case DRM_MODE_COLORIMETRY_BT709_YCC:
2561                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2562                 break;
2563         case DRM_MODE_COLORIMETRY_XVYCC_601:
2564                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2565                 break;
2566         case DRM_MODE_COLORIMETRY_XVYCC_709:
2567                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2568                 break;
2569         case DRM_MODE_COLORIMETRY_SYCC_601:
2570                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2571                 break;
2572         case DRM_MODE_COLORIMETRY_OPYCC_601:
2573                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2574                 break;
2575         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2576                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2577                 break;
2578         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2579                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2580                 break;
2581         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2582                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2583                 break;
2584         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2585         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2586                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2587                 break;
2588         default:
2589                 /*
2590                  * RGB->YCBCR color conversion uses the BT.709
2591                  * color space.
2592                  */
2593                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2594                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2595                 else
2596                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2597                 break;
2598         }
2599
2600         vsc->bpc = crtc_state->pipe_bpp / 3;
2601
2602         /* only RGB pixelformat supports 6 bpc */
2603         drm_WARN_ON(&dev_priv->drm,
2604                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2605
2606         /* all YCbCr are always limited range */
2607         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2608         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2609 }
2610
2611 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2612                                      struct intel_crtc_state *crtc_state,
2613                                      const struct drm_connector_state *conn_state)
2614 {
2615         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2616
2617         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2618         if (crtc_state->has_psr)
2619                 return;
2620
2621         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2622                 return;
2623
2624         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2625         vsc->sdp_type = DP_SDP_VSC;
2626         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2627                                          &crtc_state->infoframes.vsc);
2628 }
2629
2630 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2631                                   const struct intel_crtc_state *crtc_state,
2632                                   const struct drm_connector_state *conn_state,
2633                                   struct drm_dp_vsc_sdp *vsc)
2634 {
2635         vsc->sdp_type = DP_SDP_VSC;
2636
2637         if (crtc_state->has_psr2) {
2638                 if (intel_dp->psr.colorimetry_support &&
2639                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2640                         /* [PSR2, +Colorimetry] */
2641                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2642                                                          vsc);
2643                 } else {
2644                         /*
2645                          * [PSR2, -Colorimetry]
2646                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2647                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2648                          */
2649                         vsc->revision = 0x4;
2650                         vsc->length = 0xe;
2651                 }
2652         } else if (crtc_state->has_panel_replay) {
2653                 if (intel_dp->psr.colorimetry_support &&
2654                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2655                         /* [Panel Replay with colorimetry info] */
2656                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2657                                                          vsc);
2658                 } else {
2659                         /*
2660                          * [Panel Replay without colorimetry info]
2661                          * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2662                          * VSC SDP supporting 3D stereo + Panel Replay.
2663                          */
2664                         vsc->revision = 0x6;
2665                         vsc->length = 0x10;
2666                 }
2667         } else {
2668                 /*
2669                  * [PSR1]
2670                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2671                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2672                  * higher).
2673                  */
2674                 vsc->revision = 0x2;
2675                 vsc->length = 0x8;
2676         }
2677 }
2678
2679 static void
2680 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2681                                             struct intel_crtc_state *crtc_state,
2682                                             const struct drm_connector_state *conn_state)
2683 {
2684         int ret;
2685         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2686         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2687
2688         if (!conn_state->hdr_output_metadata)
2689                 return;
2690
2691         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2692
2693         if (ret) {
2694                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2695                 return;
2696         }
2697
2698         crtc_state->infoframes.enable |=
2699                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2700 }
2701
2702 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2703                                     enum transcoder cpu_transcoder)
2704 {
2705         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2706                 return true;
2707
2708         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2709 }
2710
2711 static bool can_enable_drrs(struct intel_connector *connector,
2712                             const struct intel_crtc_state *pipe_config,
2713                             const struct drm_display_mode *downclock_mode)
2714 {
2715         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2716
2717         if (pipe_config->vrr.enable)
2718                 return false;
2719
2720         /*
2721          * DRRS and PSR can't be enable together, so giving preference to PSR
2722          * as it allows more power-savings by complete shutting down display,
2723          * so to guarantee this, intel_drrs_compute_config() must be called
2724          * after intel_psr_compute_config().
2725          */
2726         if (pipe_config->has_psr)
2727                 return false;
2728
2729         /* FIXME missing FDI M2/N2 etc. */
2730         if (pipe_config->has_pch_encoder)
2731                 return false;
2732
2733         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2734                 return false;
2735
2736         return downclock_mode &&
2737                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2738 }
2739
2740 static void
2741 intel_dp_drrs_compute_config(struct intel_connector *connector,
2742                              struct intel_crtc_state *pipe_config,
2743                              int link_bpp_x16)
2744 {
2745         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2746         const struct drm_display_mode *downclock_mode =
2747                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2748         int pixel_clock;
2749
2750         if (has_seamless_m_n(connector))
2751                 pipe_config->update_m_n = true;
2752
2753         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2754                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2755                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2756                 return;
2757         }
2758
2759         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2760                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2761
2762         pipe_config->has_drrs = true;
2763
2764         pixel_clock = downclock_mode->clock;
2765         if (pipe_config->splitter.enable)
2766                 pixel_clock /= pipe_config->splitter.link_count;
2767
2768         intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2769                                pipe_config->port_clock,
2770                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2771                                &pipe_config->dp_m2_n2);
2772
2773         /* FIXME: abstract this better */
2774         if (pipe_config->splitter.enable)
2775                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2776 }
2777
2778 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2779                                struct intel_crtc_state *crtc_state,
2780                                const struct drm_connector_state *conn_state)
2781 {
2782         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2783         const struct intel_digital_connector_state *intel_conn_state =
2784                 to_intel_digital_connector_state(conn_state);
2785         struct intel_connector *connector =
2786                 to_intel_connector(conn_state->connector);
2787
2788         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2789             !intel_dp_port_has_audio(i915, encoder->port))
2790                 return false;
2791
2792         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2793                 return connector->base.display_info.has_audio;
2794         else
2795                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2796 }
2797
2798 static int
2799 intel_dp_compute_output_format(struct intel_encoder *encoder,
2800                                struct intel_crtc_state *crtc_state,
2801                                struct drm_connector_state *conn_state,
2802                                bool respect_downstream_limits)
2803 {
2804         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2805         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2806         struct intel_connector *connector = intel_dp->attached_connector;
2807         const struct drm_display_info *info = &connector->base.display_info;
2808         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2809         bool ycbcr_420_only;
2810         int ret;
2811
2812         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2813
2814         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2815                 drm_dbg_kms(&i915->drm,
2816                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2817                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2818         } else {
2819                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2820         }
2821
2822         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2823
2824         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2825                                            respect_downstream_limits);
2826         if (ret) {
2827                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2828                     !connector->base.ycbcr_420_allowed ||
2829                     !drm_mode_is_420_also(info, adjusted_mode))
2830                         return ret;
2831
2832                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2833                 crtc_state->output_format = intel_dp_output_format(connector,
2834                                                                    crtc_state->sink_format);
2835                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2836                                                    respect_downstream_limits);
2837         }
2838
2839         return ret;
2840 }
2841
2842 void
2843 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2844                               struct intel_crtc_state *pipe_config,
2845                               struct drm_connector_state *conn_state)
2846 {
2847         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2848         struct drm_connector *connector = conn_state->connector;
2849
2850         pipe_config->has_audio =
2851                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2852                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2853
2854         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2855                                         intel_dp_is_uhbr(pipe_config);
2856
2857         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2858                     connector->base.id, connector->name,
2859                     str_yes_no(pipe_config->sdp_split_enable));
2860 }
2861
2862 int
2863 intel_dp_compute_config(struct intel_encoder *encoder,
2864                         struct intel_crtc_state *pipe_config,
2865                         struct drm_connector_state *conn_state)
2866 {
2867         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2868         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2869         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2870         const struct drm_display_mode *fixed_mode;
2871         struct intel_connector *connector = intel_dp->attached_connector;
2872         int ret = 0, link_bpp_x16;
2873
2874         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2875                 pipe_config->has_pch_encoder = true;
2876
2877         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2878         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2879                 ret = intel_panel_compute_config(connector, adjusted_mode);
2880                 if (ret)
2881                         return ret;
2882         }
2883
2884         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2885                 return -EINVAL;
2886
2887         if (!connector->base.interlace_allowed &&
2888             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2889                 return -EINVAL;
2890
2891         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2892                 return -EINVAL;
2893
2894         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2895                 return -EINVAL;
2896
2897         /*
2898          * Try to respect downstream TMDS clock limits first, if
2899          * that fails assume the user might know something we don't.
2900          */
2901         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2902         if (ret)
2903                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2904         if (ret)
2905                 return ret;
2906
2907         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2908             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2909                 ret = intel_panel_fitting(pipe_config, conn_state);
2910                 if (ret)
2911                         return ret;
2912         }
2913
2914         pipe_config->limited_color_range =
2915                 intel_dp_limited_color_range(pipe_config, conn_state);
2916
2917         pipe_config->enhanced_framing =
2918                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2919
2920         if (pipe_config->dsc.compression_enable)
2921                 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
2922         else
2923                 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
2924                                                               pipe_config->pipe_bpp));
2925
2926         if (intel_dp->mso_link_count) {
2927                 int n = intel_dp->mso_link_count;
2928                 int overlap = intel_dp->mso_pixel_overlap;
2929
2930                 pipe_config->splitter.enable = true;
2931                 pipe_config->splitter.link_count = n;
2932                 pipe_config->splitter.pixel_overlap = overlap;
2933
2934                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2935                             n, overlap);
2936
2937                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2938                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2939                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2940                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2941                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2942                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2943                 adjusted_mode->crtc_clock /= n;
2944         }
2945
2946         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2947
2948         intel_link_compute_m_n(link_bpp_x16,
2949                                pipe_config->lane_count,
2950                                adjusted_mode->crtc_clock,
2951                                pipe_config->port_clock,
2952                                intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2953                                &pipe_config->dp_m_n);
2954
2955         /* FIXME: abstract this better */
2956         if (pipe_config->splitter.enable)
2957                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2958
2959         if (!HAS_DDI(dev_priv))
2960                 g4x_dp_set_clock(encoder, pipe_config);
2961
2962         intel_vrr_compute_config(pipe_config, conn_state);
2963         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2964         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
2965         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2966         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2967
2968         return 0;
2969 }
2970
2971 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2972                               int link_rate, int lane_count)
2973 {
2974         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2975         intel_dp->link_trained = false;
2976         intel_dp->link_rate = link_rate;
2977         intel_dp->lane_count = lane_count;
2978 }
2979
2980 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2981 {
2982         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2983         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2984 }
2985
2986 /* Enable backlight PWM and backlight PP control. */
2987 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2988                             const struct drm_connector_state *conn_state)
2989 {
2990         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2991         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2992
2993         if (!intel_dp_is_edp(intel_dp))
2994                 return;
2995
2996         drm_dbg_kms(&i915->drm, "\n");
2997
2998         intel_backlight_enable(crtc_state, conn_state);
2999         intel_pps_backlight_on(intel_dp);
3000 }
3001
3002 /* Disable backlight PP control and backlight PWM. */
3003 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3004 {
3005         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3006         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3007
3008         if (!intel_dp_is_edp(intel_dp))
3009                 return;
3010
3011         drm_dbg_kms(&i915->drm, "\n");
3012
3013         intel_pps_backlight_off(intel_dp);
3014         intel_backlight_disable(old_conn_state);
3015 }
3016
3017 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3018 {
3019         /*
3020          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3021          * be capable of signalling downstream hpd with a long pulse.
3022          * Whether or not that means D3 is safe to use is not clear,
3023          * but let's assume so until proven otherwise.
3024          *
3025          * FIXME should really check all downstream ports...
3026          */
3027         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3028                 drm_dp_is_branch(intel_dp->dpcd) &&
3029                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3030 }
3031
3032 static int
3033 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3034 {
3035         int err;
3036         u8 val;
3037
3038         err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3039         if (err < 0)
3040                 return err;
3041
3042         if (set)
3043                 val |= flag;
3044         else
3045                 val &= ~flag;
3046
3047         return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3048 }
3049
3050 static void
3051 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3052                                     bool enable)
3053 {
3054         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3055
3056         if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3057                                          DP_DECOMPRESSION_EN, enable) < 0)
3058                 drm_dbg_kms(&i915->drm,
3059                             "Failed to %s sink decompression state\n",
3060                             str_enable_disable(enable));
3061 }
3062
3063 static void
3064 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3065                                   bool enable)
3066 {
3067         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3068         struct drm_dp_aux *aux = connector->port ?
3069                                  connector->port->passthrough_aux : NULL;
3070
3071         if (!aux)
3072                 return;
3073
3074         if (write_dsc_decompression_flag(aux,
3075                                          DP_DSC_PASSTHROUGH_EN, enable) < 0)
3076                 drm_dbg_kms(&i915->drm,
3077                             "Failed to %s sink compression passthrough state\n",
3078                             str_enable_disable(enable));
3079 }
3080
3081 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3082                                       const struct intel_connector *connector,
3083                                       bool for_get_ref)
3084 {
3085         struct drm_i915_private *i915 = to_i915(state->base.dev);
3086         struct drm_connector *_connector_iter;
3087         struct drm_connector_state *old_conn_state;
3088         struct drm_connector_state *new_conn_state;
3089         int ref_count = 0;
3090         int i;
3091
3092         /*
3093          * On SST the decompression AUX device won't be shared, each connector
3094          * uses for this its own AUX targeting the sink device.
3095          */
3096         if (!connector->mst_port)
3097                 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3098
3099         for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3100                                            old_conn_state, new_conn_state, i) {
3101                 const struct intel_connector *
3102                         connector_iter = to_intel_connector(_connector_iter);
3103
3104                 if (connector_iter->mst_port != connector->mst_port)
3105                         continue;
3106
3107                 if (!connector_iter->dp.dsc_decompression_enabled)
3108                         continue;
3109
3110                 drm_WARN_ON(&i915->drm,
3111                             (for_get_ref && !new_conn_state->crtc) ||
3112                             (!for_get_ref && !old_conn_state->crtc));
3113
3114                 if (connector_iter->dp.dsc_decompression_aux ==
3115                     connector->dp.dsc_decompression_aux)
3116                         ref_count++;
3117         }
3118
3119         return ref_count;
3120 }
3121
3122 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3123                                      struct intel_connector *connector)
3124 {
3125         bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3126
3127         connector->dp.dsc_decompression_enabled = true;
3128
3129         return ret;
3130 }
3131
3132 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3133                                      struct intel_connector *connector)
3134 {
3135         connector->dp.dsc_decompression_enabled = false;
3136
3137         return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3138 }
3139
3140 /**
3141  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3142  * @state: atomic state
3143  * @connector: connector to enable the decompression for
3144  * @new_crtc_state: new state for the CRTC driving @connector
3145  *
3146  * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3147  * register of the appropriate sink/branch device. On SST this is always the
3148  * sink device, whereas on MST based on each device's DSC capabilities it's
3149  * either the last branch device (enabling decompression in it) or both the
3150  * last branch device (enabling passthrough in it) and the sink device
3151  * (enabling decompression in it).
3152  */
3153 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3154                                         struct intel_connector *connector,
3155                                         const struct intel_crtc_state *new_crtc_state)
3156 {
3157         struct drm_i915_private *i915 = to_i915(state->base.dev);
3158
3159         if (!new_crtc_state->dsc.compression_enable)
3160                 return;
3161
3162         if (drm_WARN_ON(&i915->drm,
3163                         !connector->dp.dsc_decompression_aux ||
3164                         connector->dp.dsc_decompression_enabled))
3165                 return;
3166
3167         if (!intel_dp_dsc_aux_get_ref(state, connector))
3168                 return;
3169
3170         intel_dp_sink_set_dsc_passthrough(connector, true);
3171         intel_dp_sink_set_dsc_decompression(connector, true);
3172 }
3173
3174 /**
3175  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3176  * @state: atomic state
3177  * @connector: connector to disable the decompression for
3178  * @old_crtc_state: old state for the CRTC driving @connector
3179  *
3180  * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3181  * register of the appropriate sink/branch device, corresponding to the
3182  * sequence in intel_dp_sink_enable_decompression().
3183  */
3184 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3185                                          struct intel_connector *connector,
3186                                          const struct intel_crtc_state *old_crtc_state)
3187 {
3188         struct drm_i915_private *i915 = to_i915(state->base.dev);
3189
3190         if (!old_crtc_state->dsc.compression_enable)
3191                 return;
3192
3193         if (drm_WARN_ON(&i915->drm,
3194                         !connector->dp.dsc_decompression_aux ||
3195                         !connector->dp.dsc_decompression_enabled))
3196                 return;
3197
3198         if (!intel_dp_dsc_aux_put_ref(state, connector))
3199                 return;
3200
3201         intel_dp_sink_set_dsc_decompression(connector, false);
3202         intel_dp_sink_set_dsc_passthrough(connector, false);
3203 }
3204
3205 static void
3206 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3207 {
3208         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3209         u8 oui[] = { 0x00, 0xaa, 0x01 };
3210         u8 buf[3] = {};
3211
3212         /*
3213          * During driver init, we want to be careful and avoid changing the source OUI if it's
3214          * already set to what we want, so as to avoid clearing any state by accident
3215          */
3216         if (careful) {
3217                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3218                         drm_err(&i915->drm, "Failed to read source OUI\n");
3219
3220                 if (memcmp(oui, buf, sizeof(oui)) == 0)
3221                         return;
3222         }
3223
3224         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3225                 drm_err(&i915->drm, "Failed to write source OUI\n");
3226
3227         intel_dp->last_oui_write = jiffies;
3228 }
3229
3230 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3231 {
3232         struct intel_connector *connector = intel_dp->attached_connector;
3233         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3234
3235         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3236                     connector->base.base.id, connector->base.name,
3237                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3238
3239         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3240                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3241 }
3242
3243 /* If the device supports it, try to set the power state appropriately */
3244 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3245 {
3246         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3247         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3248         int ret, i;
3249
3250         /* Should have a valid DPCD by this point */
3251         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3252                 return;
3253
3254         if (mode != DP_SET_POWER_D0) {
3255                 if (downstream_hpd_needs_d0(intel_dp))
3256                         return;
3257
3258                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3259         } else {
3260                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3261
3262                 lspcon_resume(dp_to_dig_port(intel_dp));
3263
3264                 /* Write the source OUI as early as possible */
3265                 if (intel_dp_is_edp(intel_dp))
3266                         intel_edp_init_source_oui(intel_dp, false);
3267
3268                 /*
3269                  * When turning on, we need to retry for 1ms to give the sink
3270                  * time to wake up.
3271                  */
3272                 for (i = 0; i < 3; i++) {
3273                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3274                         if (ret == 1)
3275                                 break;
3276                         msleep(1);
3277                 }
3278
3279                 if (ret == 1 && lspcon->active)
3280                         lspcon_wait_pcon_mode(lspcon);
3281         }
3282
3283         if (ret != 1)
3284                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3285                             encoder->base.base.id, encoder->base.name,
3286                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3287 }
3288
3289 static bool
3290 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3291
3292 /**
3293  * intel_dp_sync_state - sync the encoder state during init/resume
3294  * @encoder: intel encoder to sync
3295  * @crtc_state: state for the CRTC connected to the encoder
3296  *
3297  * Sync any state stored in the encoder wrt. HW state during driver init
3298  * and system resume.
3299  */
3300 void intel_dp_sync_state(struct intel_encoder *encoder,
3301                          const struct intel_crtc_state *crtc_state)
3302 {
3303         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3304
3305         if (!crtc_state)
3306                 return;
3307
3308         /*
3309          * Don't clobber DPCD if it's been already read out during output
3310          * setup (eDP) or detect.
3311          */
3312         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3313                 intel_dp_get_dpcd(intel_dp);
3314
3315         intel_dp_reset_max_link_params(intel_dp);
3316 }
3317
3318 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3319                                     struct intel_crtc_state *crtc_state)
3320 {
3321         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3322         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3323         bool fastset = true;
3324
3325         /*
3326          * If BIOS has set an unsupported or non-standard link rate for some
3327          * reason force an encoder recompute and full modeset.
3328          */
3329         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3330                                 crtc_state->port_clock) < 0) {
3331                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3332                             encoder->base.base.id, encoder->base.name);
3333                 crtc_state->uapi.connectors_changed = true;
3334                 fastset = false;
3335         }
3336
3337         /*
3338          * FIXME hack to force full modeset when DSC is being used.
3339          *
3340          * As long as we do not have full state readout and config comparison
3341          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3342          * Remove once we have readout for DSC.
3343          */
3344         if (crtc_state->dsc.compression_enable) {
3345                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3346                             encoder->base.base.id, encoder->base.name);
3347                 crtc_state->uapi.mode_changed = true;
3348                 fastset = false;
3349         }
3350
3351         if (CAN_PSR(intel_dp)) {
3352                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
3353                             encoder->base.base.id, encoder->base.name);
3354                 crtc_state->uapi.mode_changed = true;
3355                 fastset = false;
3356         }
3357
3358         return fastset;
3359 }
3360
3361 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3362 {
3363         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3364
3365         /* Clear the cached register set to avoid using stale values */
3366
3367         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3368
3369         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3370                              intel_dp->pcon_dsc_dpcd,
3371                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3372                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3373                         DP_PCON_DSC_ENCODER);
3374
3375         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3376                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3377 }
3378
3379 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3380 {
3381         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3382         int i;
3383
3384         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3385                 if (frl_bw_mask & (1 << i))
3386                         return bw_gbps[i];
3387         }
3388         return 0;
3389 }
3390
3391 static int intel_dp_pcon_set_frl_mask(int max_frl)
3392 {
3393         switch (max_frl) {
3394         case 48:
3395                 return DP_PCON_FRL_BW_MASK_48GBPS;
3396         case 40:
3397                 return DP_PCON_FRL_BW_MASK_40GBPS;
3398         case 32:
3399                 return DP_PCON_FRL_BW_MASK_32GBPS;
3400         case 24:
3401                 return DP_PCON_FRL_BW_MASK_24GBPS;
3402         case 18:
3403                 return DP_PCON_FRL_BW_MASK_18GBPS;
3404         case 9:
3405                 return DP_PCON_FRL_BW_MASK_9GBPS;
3406         }
3407
3408         return 0;
3409 }
3410
3411 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3412 {
3413         struct intel_connector *intel_connector = intel_dp->attached_connector;
3414         struct drm_connector *connector = &intel_connector->base;
3415         int max_frl_rate;
3416         int max_lanes, rate_per_lane;
3417         int max_dsc_lanes, dsc_rate_per_lane;
3418
3419         max_lanes = connector->display_info.hdmi.max_lanes;
3420         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3421         max_frl_rate = max_lanes * rate_per_lane;
3422
3423         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3424                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3425                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3426                 if (max_dsc_lanes && dsc_rate_per_lane)
3427                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3428         }
3429
3430         return max_frl_rate;
3431 }
3432
3433 static bool
3434 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3435                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3436 {
3437         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3438             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3439             *frl_trained_mask >= max_frl_bw_mask)
3440                 return true;
3441
3442         return false;
3443 }
3444
3445 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3446 {
3447 #define TIMEOUT_FRL_READY_MS 500
3448 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3449
3450         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3451         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3452         u8 max_frl_bw_mask = 0, frl_trained_mask;
3453         bool is_active;
3454
3455         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3456         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3457
3458         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3459         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3460
3461         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3462
3463         if (max_frl_bw <= 0)
3464                 return -EINVAL;
3465
3466         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3467         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3468
3469         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3470                 goto frl_trained;
3471
3472         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3473         if (ret < 0)
3474                 return ret;
3475         /* Wait for PCON to be FRL Ready */
3476         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3477
3478         if (!is_active)
3479                 return -ETIMEDOUT;
3480
3481         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3482                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3483         if (ret < 0)
3484                 return ret;
3485         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3486                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3487         if (ret < 0)
3488                 return ret;
3489         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3490         if (ret < 0)
3491                 return ret;
3492         /*
3493          * Wait for FRL to be completed
3494          * Check if the HDMI Link is up and active.
3495          */
3496         wait_for(is_active =
3497                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3498                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3499
3500         if (!is_active)
3501                 return -ETIMEDOUT;
3502
3503 frl_trained:
3504         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3505         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3506         intel_dp->frl.is_trained = true;
3507         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3508
3509         return 0;
3510 }
3511
3512 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3513 {
3514         if (drm_dp_is_branch(intel_dp->dpcd) &&
3515             intel_dp_has_hdmi_sink(intel_dp) &&
3516             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3517                 return true;
3518
3519         return false;
3520 }
3521
3522 static
3523 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3524 {
3525         int ret;
3526         u8 buf = 0;
3527
3528         /* Set PCON source control mode */
3529         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3530
3531         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3532         if (ret < 0)
3533                 return ret;
3534
3535         /* Set HDMI LINK ENABLE */
3536         buf |= DP_PCON_ENABLE_HDMI_LINK;
3537         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3538         if (ret < 0)
3539                 return ret;
3540
3541         return 0;
3542 }
3543
3544 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3545 {
3546         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3547
3548         /*
3549          * Always go for FRL training if:
3550          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3551          * -sink is HDMI2.1
3552          */
3553         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3554             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3555             intel_dp->frl.is_trained)
3556                 return;
3557
3558         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3559                 int ret, mode;
3560
3561                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3562                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3563                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3564
3565                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3566                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3567         } else {
3568                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3569         }
3570 }
3571
3572 static int
3573 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3574 {
3575         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3576
3577         return intel_hdmi_dsc_get_slice_height(vactive);
3578 }
3579
3580 static int
3581 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3582                              const struct intel_crtc_state *crtc_state)
3583 {
3584         struct intel_connector *intel_connector = intel_dp->attached_connector;
3585         struct drm_connector *connector = &intel_connector->base;
3586         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3587         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3588         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3589         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3590
3591         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3592                                              pcon_max_slice_width,
3593                                              hdmi_max_slices, hdmi_throughput);
3594 }
3595
3596 static int
3597 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3598                           const struct intel_crtc_state *crtc_state,
3599                           int num_slices, int slice_width)
3600 {
3601         struct intel_connector *intel_connector = intel_dp->attached_connector;
3602         struct drm_connector *connector = &intel_connector->base;
3603         int output_format = crtc_state->output_format;
3604         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3605         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3606         int hdmi_max_chunk_bytes =
3607                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3608
3609         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3610                                       num_slices, output_format, hdmi_all_bpp,
3611                                       hdmi_max_chunk_bytes);
3612 }
3613
3614 void
3615 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3616                             const struct intel_crtc_state *crtc_state)
3617 {
3618         u8 pps_param[6];
3619         int slice_height;
3620         int slice_width;
3621         int num_slices;
3622         int bits_per_pixel;
3623         int ret;
3624         struct intel_connector *intel_connector = intel_dp->attached_connector;
3625         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3626         struct drm_connector *connector;
3627         bool hdmi_is_dsc_1_2;
3628
3629         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3630                 return;
3631
3632         if (!intel_connector)
3633                 return;
3634         connector = &intel_connector->base;
3635         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3636
3637         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3638             !hdmi_is_dsc_1_2)
3639                 return;
3640
3641         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3642         if (!slice_height)
3643                 return;
3644
3645         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3646         if (!num_slices)
3647                 return;
3648
3649         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3650                                    num_slices);
3651
3652         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3653                                                    num_slices, slice_width);
3654         if (!bits_per_pixel)
3655                 return;
3656
3657         pps_param[0] = slice_height & 0xFF;
3658         pps_param[1] = slice_height >> 8;
3659         pps_param[2] = slice_width & 0xFF;
3660         pps_param[3] = slice_width >> 8;
3661         pps_param[4] = bits_per_pixel & 0xFF;
3662         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3663
3664         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3665         if (ret < 0)
3666                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3667 }
3668
3669 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3670                                            const struct intel_crtc_state *crtc_state)
3671 {
3672         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3673         bool ycbcr444_to_420 = false;
3674         bool rgb_to_ycbcr = false;
3675         u8 tmp;
3676
3677         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3678                 return;
3679
3680         if (!drm_dp_is_branch(intel_dp->dpcd))
3681                 return;
3682
3683         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3684
3685         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3686                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3687                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3688                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3689
3690         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3691                 switch (crtc_state->output_format) {
3692                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3693                         break;
3694                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3695                         ycbcr444_to_420 = true;
3696                         break;
3697                 case INTEL_OUTPUT_FORMAT_RGB:
3698                         rgb_to_ycbcr = true;
3699                         ycbcr444_to_420 = true;
3700                         break;
3701                 default:
3702                         MISSING_CASE(crtc_state->output_format);
3703                         break;
3704                 }
3705         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3706                 switch (crtc_state->output_format) {
3707                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3708                         break;
3709                 case INTEL_OUTPUT_FORMAT_RGB:
3710                         rgb_to_ycbcr = true;
3711                         break;
3712                 default:
3713                         MISSING_CASE(crtc_state->output_format);
3714                         break;
3715                 }
3716         }
3717
3718         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3719
3720         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3721                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3722                 drm_dbg_kms(&i915->drm,
3723                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3724                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3725
3726         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3727
3728         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3729                 drm_dbg_kms(&i915->drm,
3730                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3731                             str_enable_disable(tmp));
3732 }
3733
3734 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3735 {
3736         u8 dprx = 0;
3737
3738         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3739                               &dprx) != 1)
3740                 return false;
3741         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3742 }
3743
3744 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3745                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3746 {
3747         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3748                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3749                 drm_err(aux->drm_dev,
3750                         "Failed to read DPCD register 0x%x\n",
3751                         DP_DSC_SUPPORT);
3752                 return;
3753         }
3754
3755         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3756                     DP_DSC_RECEIVER_CAP_SIZE,
3757                     dsc_dpcd);
3758 }
3759
3760 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3761 {
3762         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3763
3764         /*
3765          * Clear the cached register set to avoid using stale values
3766          * for the sinks that do not support DSC.
3767          */
3768         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3769
3770         /* Clear fec_capable to avoid using stale values */
3771         connector->dp.fec_capability = 0;
3772
3773         if (dpcd_rev < DP_DPCD_REV_14)
3774                 return;
3775
3776         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3777                                connector->dp.dsc_dpcd);
3778
3779         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3780                               &connector->dp.fec_capability) < 0) {
3781                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3782                 return;
3783         }
3784
3785         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3786                     connector->dp.fec_capability);
3787 }
3788
3789 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3790 {
3791         if (edp_dpcd_rev < DP_EDP_14)
3792                 return;
3793
3794         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3795 }
3796
3797 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3798                                      struct drm_display_mode *mode)
3799 {
3800         struct intel_dp *intel_dp = intel_attached_dp(connector);
3801         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3802         int n = intel_dp->mso_link_count;
3803         int overlap = intel_dp->mso_pixel_overlap;
3804
3805         if (!mode || !n)
3806                 return;
3807
3808         mode->hdisplay = (mode->hdisplay - overlap) * n;
3809         mode->hsync_start = (mode->hsync_start - overlap) * n;
3810         mode->hsync_end = (mode->hsync_end - overlap) * n;
3811         mode->htotal = (mode->htotal - overlap) * n;
3812         mode->clock *= n;
3813
3814         drm_mode_set_name(mode);
3815
3816         drm_dbg_kms(&i915->drm,
3817                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3818                     connector->base.base.id, connector->base.name,
3819                     DRM_MODE_ARG(mode));
3820 }
3821
3822 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3823 {
3824         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3825         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3826         struct intel_connector *connector = intel_dp->attached_connector;
3827
3828         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3829                 /*
3830                  * This is a big fat ugly hack.
3831                  *
3832                  * Some machines in UEFI boot mode provide us a VBT that has 18
3833                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3834                  * unknown we fail to light up. Yet the same BIOS boots up with
3835                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3836                  * max, not what it tells us to use.
3837                  *
3838                  * Note: This will still be broken if the eDP panel is not lit
3839                  * up by the BIOS, and thus we can't get the mode at module
3840                  * load.
3841                  */
3842                 drm_dbg_kms(&dev_priv->drm,
3843                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3844                             pipe_bpp, connector->panel.vbt.edp.bpp);
3845                 connector->panel.vbt.edp.bpp = pipe_bpp;
3846         }
3847 }
3848
3849 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3850 {
3851         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3852         struct intel_connector *connector = intel_dp->attached_connector;
3853         struct drm_display_info *info = &connector->base.display_info;
3854         u8 mso;
3855
3856         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3857                 return;
3858
3859         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3860                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3861                 return;
3862         }
3863
3864         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3865         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3866         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3867                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3868                 mso = 0;
3869         }
3870
3871         if (mso) {
3872                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3873                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3874                             info->mso_pixel_overlap);
3875                 if (!HAS_MSO(i915)) {
3876                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3877                         mso = 0;
3878                 }
3879         }
3880
3881         intel_dp->mso_link_count = mso;
3882         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3883 }
3884
3885 static bool
3886 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3887 {
3888         struct drm_i915_private *dev_priv =
3889                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3890
3891         /* this function is meant to be called only once */
3892         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3893
3894         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3895                 return false;
3896
3897         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3898                          drm_dp_is_branch(intel_dp->dpcd));
3899
3900         /*
3901          * Read the eDP display control registers.
3902          *
3903          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3904          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3905          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3906          * method). The display control registers should read zero if they're
3907          * not supported anyway.
3908          */
3909         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3910                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3911                              sizeof(intel_dp->edp_dpcd)) {
3912                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3913                             (int)sizeof(intel_dp->edp_dpcd),
3914                             intel_dp->edp_dpcd);
3915
3916                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3917         }
3918
3919         /*
3920          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3921          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3922          */
3923         intel_psr_init_dpcd(intel_dp);
3924
3925         /* Clear the default sink rates */
3926         intel_dp->num_sink_rates = 0;
3927
3928         /* Read the eDP 1.4+ supported link rates. */
3929         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3930                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3931                 int i;
3932
3933                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3934                                 sink_rates, sizeof(sink_rates));
3935
3936                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3937                         int val = le16_to_cpu(sink_rates[i]);
3938
3939                         if (val == 0)
3940                                 break;
3941
3942                         /* Value read multiplied by 200kHz gives the per-lane
3943                          * link rate in kHz. The source rates are, however,
3944                          * stored in terms of LS_Clk kHz. The full conversion
3945                          * back to symbols is
3946                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3947                          */
3948                         intel_dp->sink_rates[i] = (val * 200) / 10;
3949                 }
3950                 intel_dp->num_sink_rates = i;
3951         }
3952
3953         /*
3954          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3955          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3956          */
3957         if (intel_dp->num_sink_rates)
3958                 intel_dp->use_rate_select = true;
3959         else
3960                 intel_dp_set_sink_rates(intel_dp);
3961         intel_dp_set_max_sink_lane_count(intel_dp);
3962
3963         /* Read the eDP DSC DPCD registers */
3964         if (HAS_DSC(dev_priv))
3965                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3966                                            connector);
3967
3968         /*
3969          * If needed, program our source OUI so we can make various Intel-specific AUX services
3970          * available (such as HDR backlight controls)
3971          */
3972         intel_edp_init_source_oui(intel_dp, true);
3973
3974         return true;
3975 }
3976
3977 static bool
3978 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3979 {
3980         if (!intel_dp->attached_connector)
3981                 return false;
3982
3983         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3984                                           intel_dp->dpcd,
3985                                           &intel_dp->desc);
3986 }
3987
3988 static bool
3989 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3990 {
3991         int ret;
3992
3993         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3994                 return false;
3995
3996         /*
3997          * Don't clobber cached eDP rates. Also skip re-reading
3998          * the OUI/ID since we know it won't change.
3999          */
4000         if (!intel_dp_is_edp(intel_dp)) {
4001                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4002                                  drm_dp_is_branch(intel_dp->dpcd));
4003
4004                 intel_dp_set_sink_rates(intel_dp);
4005                 intel_dp_set_max_sink_lane_count(intel_dp);
4006                 intel_dp_set_common_rates(intel_dp);
4007         }
4008
4009         if (intel_dp_has_sink_count(intel_dp)) {
4010                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4011                 if (ret < 0)
4012                         return false;
4013
4014                 /*
4015                  * Sink count can change between short pulse hpd hence
4016                  * a member variable in intel_dp will track any changes
4017                  * between short pulse interrupts.
4018                  */
4019                 intel_dp->sink_count = ret;
4020
4021                 /*
4022                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4023                  * a dongle is present but no display. Unless we require to know
4024                  * if a dongle is present or not, we don't need to update
4025                  * downstream port information. So, an early return here saves
4026                  * time from performing other operations which are not required.
4027                  */
4028                 if (!intel_dp->sink_count)
4029                         return false;
4030         }
4031
4032         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4033                                            intel_dp->downstream_ports) == 0;
4034 }
4035
4036 static bool
4037 intel_dp_can_mst(struct intel_dp *intel_dp)
4038 {
4039         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4040
4041         return i915->display.params.enable_dp_mst &&
4042                 intel_dp_mst_source_support(intel_dp) &&
4043                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4044 }
4045
4046 static void
4047 intel_dp_configure_mst(struct intel_dp *intel_dp)
4048 {
4049         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4050         struct intel_encoder *encoder =
4051                 &dp_to_dig_port(intel_dp)->base;
4052         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4053
4054         drm_dbg_kms(&i915->drm,
4055                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4056                     encoder->base.base.id, encoder->base.name,
4057                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
4058                     str_yes_no(sink_can_mst),
4059                     str_yes_no(i915->display.params.enable_dp_mst));
4060
4061         if (!intel_dp_mst_source_support(intel_dp))
4062                 return;
4063
4064         intel_dp->is_mst = sink_can_mst &&
4065                 i915->display.params.enable_dp_mst;
4066
4067         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4068                                         intel_dp->is_mst);
4069 }
4070
4071 static bool
4072 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4073 {
4074         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4075 }
4076
4077 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4078 {
4079         int retry;
4080
4081         for (retry = 0; retry < 3; retry++) {
4082                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4083                                       &esi[1], 3) == 3)
4084                         return true;
4085         }
4086
4087         return false;
4088 }
4089
4090 bool
4091 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4092                        const struct drm_connector_state *conn_state)
4093 {
4094         /*
4095          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4096          * of Color Encoding Format and Content Color Gamut], in order to
4097          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4098          */
4099         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4100                 return true;
4101
4102         switch (conn_state->colorspace) {
4103         case DRM_MODE_COLORIMETRY_SYCC_601:
4104         case DRM_MODE_COLORIMETRY_OPYCC_601:
4105         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4106         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4107         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4108                 return true;
4109         default:
4110                 break;
4111         }
4112
4113         return false;
4114 }
4115
4116 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4117                                      struct dp_sdp *sdp, size_t size)
4118 {
4119         size_t length = sizeof(struct dp_sdp);
4120
4121         if (size < length)
4122                 return -ENOSPC;
4123
4124         memset(sdp, 0, size);
4125
4126         /*
4127          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4128          * VSC SDP Header Bytes
4129          */
4130         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4131         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4132         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4133         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4134
4135         if (vsc->revision == 0x6) {
4136                 sdp->db[0] = 1;
4137                 sdp->db[3] = 1;
4138         }
4139
4140         /*
4141          * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
4142          * Format as per DP 1.4a spec and DP 2.0 respectively.
4143          */
4144         if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
4145                 goto out;
4146
4147         /* VSC SDP Payload for DB16 through DB18 */
4148         /* Pixel Encoding and Colorimetry Formats  */
4149         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4150         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4151
4152         switch (vsc->bpc) {
4153         case 6:
4154                 /* 6bpc: 0x0 */
4155                 break;
4156         case 8:
4157                 sdp->db[17] = 0x1; /* DB17[3:0] */
4158                 break;
4159         case 10:
4160                 sdp->db[17] = 0x2;
4161                 break;
4162         case 12:
4163                 sdp->db[17] = 0x3;
4164                 break;
4165         case 16:
4166                 sdp->db[17] = 0x4;
4167                 break;
4168         default:
4169                 MISSING_CASE(vsc->bpc);
4170                 break;
4171         }
4172         /* Dynamic Range and Component Bit Depth */
4173         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4174                 sdp->db[17] |= 0x80;  /* DB17[7] */
4175
4176         /* Content Type */
4177         sdp->db[18] = vsc->content_type & 0x7;
4178
4179 out:
4180         return length;
4181 }
4182
4183 static ssize_t
4184 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4185                                          const struct hdmi_drm_infoframe *drm_infoframe,
4186                                          struct dp_sdp *sdp,
4187                                          size_t size)
4188 {
4189         size_t length = sizeof(struct dp_sdp);
4190         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4191         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4192         ssize_t len;
4193
4194         if (size < length)
4195                 return -ENOSPC;
4196
4197         memset(sdp, 0, size);
4198
4199         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4200         if (len < 0) {
4201                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4202                 return -ENOSPC;
4203         }
4204
4205         if (len != infoframe_size) {
4206                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4207                 return -ENOSPC;
4208         }
4209
4210         /*
4211          * Set up the infoframe sdp packet for HDR static metadata.
4212          * Prepare VSC Header for SU as per DP 1.4a spec,
4213          * Table 2-100 and Table 2-101
4214          */
4215
4216         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4217         sdp->sdp_header.HB0 = 0;
4218         /*
4219          * Packet Type 80h + Non-audio INFOFRAME Type value
4220          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4221          * - 80h + Non-audio INFOFRAME Type value
4222          * - InfoFrame Type: 0x07
4223          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4224          */
4225         sdp->sdp_header.HB1 = drm_infoframe->type;
4226         /*
4227          * Least Significant Eight Bits of (Data Byte Count – 1)
4228          * infoframe_size - 1
4229          */
4230         sdp->sdp_header.HB2 = 0x1D;
4231         /* INFOFRAME SDP Version Number */
4232         sdp->sdp_header.HB3 = (0x13 << 2);
4233         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4234         sdp->db[0] = drm_infoframe->version;
4235         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4236         sdp->db[1] = drm_infoframe->length;
4237         /*
4238          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4239          * HDMI_INFOFRAME_HEADER_SIZE
4240          */
4241         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4242         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4243                HDMI_DRM_INFOFRAME_SIZE);
4244
4245         /*
4246          * Size of DP infoframe sdp packet for HDR static metadata consists of
4247          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4248          * - Two Data Blocks: 2 bytes
4249          *    CTA Header Byte2 (INFOFRAME Version Number)
4250          *    CTA Header Byte3 (Length of INFOFRAME)
4251          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4252          *
4253          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4254          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4255          * will pad rest of the size.
4256          */
4257         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4258 }
4259
4260 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4261                                const struct intel_crtc_state *crtc_state,
4262                                unsigned int type)
4263 {
4264         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4265         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4266         struct dp_sdp sdp = {};
4267         ssize_t len;
4268
4269         if ((crtc_state->infoframes.enable &
4270              intel_hdmi_infoframe_enable(type)) == 0)
4271                 return;
4272
4273         switch (type) {
4274         case DP_SDP_VSC:
4275                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4276                                             sizeof(sdp));
4277                 break;
4278         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4279                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4280                                                                &crtc_state->infoframes.drm.drm,
4281                                                                &sdp, sizeof(sdp));
4282                 break;
4283         default:
4284                 MISSING_CASE(type);
4285                 return;
4286         }
4287
4288         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4289                 return;
4290
4291         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4292 }
4293
4294 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4295                             const struct intel_crtc_state *crtc_state,
4296                             const struct drm_dp_vsc_sdp *vsc)
4297 {
4298         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4299         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4300         struct dp_sdp sdp = {};
4301         ssize_t len;
4302
4303         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4304
4305         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4306                 return;
4307
4308         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
4309                                         &sdp, len);
4310 }
4311
4312 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4313                              bool enable,
4314                              const struct intel_crtc_state *crtc_state,
4315                              const struct drm_connector_state *conn_state)
4316 {
4317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4318         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4319         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4320                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4321                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4322         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4323
4324         /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4325         if (!enable && HAS_DSC(dev_priv))
4326                 val &= ~VDIP_ENABLE_PPS;
4327
4328         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4329         if (!crtc_state->has_psr)
4330                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4331
4332         intel_de_write(dev_priv, reg, val);
4333         intel_de_posting_read(dev_priv, reg);
4334
4335         if (!enable)
4336                 return;
4337
4338         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4339         if (!crtc_state->has_psr)
4340                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4341
4342         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4343 }
4344
4345 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4346                                    const void *buffer, size_t size)
4347 {
4348         const struct dp_sdp *sdp = buffer;
4349
4350         if (size < sizeof(struct dp_sdp))
4351                 return -EINVAL;
4352
4353         memset(vsc, 0, sizeof(*vsc));
4354
4355         if (sdp->sdp_header.HB0 != 0)
4356                 return -EINVAL;
4357
4358         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4359                 return -EINVAL;
4360
4361         vsc->sdp_type = sdp->sdp_header.HB1;
4362         vsc->revision = sdp->sdp_header.HB2;
4363         vsc->length = sdp->sdp_header.HB3;
4364
4365         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4366             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4367                 /*
4368                  * - HB2 = 0x2, HB3 = 0x8
4369                  *   VSC SDP supporting 3D stereo + PSR
4370                  * - HB2 = 0x4, HB3 = 0xe
4371                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4372                  *   first scan line of the SU region (applies to eDP v1.4b
4373                  *   and higher).
4374                  */
4375                 return 0;
4376         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4377                 /*
4378                  * - HB2 = 0x5, HB3 = 0x13
4379                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4380                  *   Format.
4381                  */
4382                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4383                 vsc->colorimetry = sdp->db[16] & 0xf;
4384                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4385
4386                 switch (sdp->db[17] & 0x7) {
4387                 case 0x0:
4388                         vsc->bpc = 6;
4389                         break;
4390                 case 0x1:
4391                         vsc->bpc = 8;
4392                         break;
4393                 case 0x2:
4394                         vsc->bpc = 10;
4395                         break;
4396                 case 0x3:
4397                         vsc->bpc = 12;
4398                         break;
4399                 case 0x4:
4400                         vsc->bpc = 16;
4401                         break;
4402                 default:
4403                         MISSING_CASE(sdp->db[17] & 0x7);
4404                         return -EINVAL;
4405                 }
4406
4407                 vsc->content_type = sdp->db[18] & 0x7;
4408         } else {
4409                 return -EINVAL;
4410         }
4411
4412         return 0;
4413 }
4414
4415 static int
4416 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4417                                            const void *buffer, size_t size)
4418 {
4419         int ret;
4420
4421         const struct dp_sdp *sdp = buffer;
4422
4423         if (size < sizeof(struct dp_sdp))
4424                 return -EINVAL;
4425
4426         if (sdp->sdp_header.HB0 != 0)
4427                 return -EINVAL;
4428
4429         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4430                 return -EINVAL;
4431
4432         /*
4433          * Least Significant Eight Bits of (Data Byte Count – 1)
4434          * 1Dh (i.e., Data Byte Count = 30 bytes).
4435          */
4436         if (sdp->sdp_header.HB2 != 0x1D)
4437                 return -EINVAL;
4438
4439         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4440         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4441                 return -EINVAL;
4442
4443         /* INFOFRAME SDP Version Number */
4444         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4445                 return -EINVAL;
4446
4447         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4448         if (sdp->db[0] != 1)
4449                 return -EINVAL;
4450
4451         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4452         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4453                 return -EINVAL;
4454
4455         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4456                                              HDMI_DRM_INFOFRAME_SIZE);
4457
4458         return ret;
4459 }
4460
4461 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4462                                   struct intel_crtc_state *crtc_state,
4463                                   struct drm_dp_vsc_sdp *vsc)
4464 {
4465         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4467         unsigned int type = DP_SDP_VSC;
4468         struct dp_sdp sdp = {};
4469         int ret;
4470
4471         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4472         if (crtc_state->has_psr)
4473                 return;
4474
4475         if ((crtc_state->infoframes.enable &
4476              intel_hdmi_infoframe_enable(type)) == 0)
4477                 return;
4478
4479         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4480
4481         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4482
4483         if (ret)
4484                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4485 }
4486
4487 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4488                                                      struct intel_crtc_state *crtc_state,
4489                                                      struct hdmi_drm_infoframe *drm_infoframe)
4490 {
4491         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4492         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4493         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4494         struct dp_sdp sdp = {};
4495         int ret;
4496
4497         if ((crtc_state->infoframes.enable &
4498             intel_hdmi_infoframe_enable(type)) == 0)
4499                 return;
4500
4501         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4502                                  sizeof(sdp));
4503
4504         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4505                                                          sizeof(sdp));
4506
4507         if (ret)
4508                 drm_dbg_kms(&dev_priv->drm,
4509                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4510 }
4511
4512 void intel_read_dp_sdp(struct intel_encoder *encoder,
4513                        struct intel_crtc_state *crtc_state,
4514                        unsigned int type)
4515 {
4516         switch (type) {
4517         case DP_SDP_VSC:
4518                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4519                                       &crtc_state->infoframes.vsc);
4520                 break;
4521         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4522                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4523                                                          &crtc_state->infoframes.drm.drm);
4524                 break;
4525         default:
4526                 MISSING_CASE(type);
4527                 break;
4528         }
4529 }
4530
4531 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4532 {
4533         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4534         int status = 0;
4535         int test_link_rate;
4536         u8 test_lane_count, test_link_bw;
4537         /* (DP CTS 1.2)
4538          * 4.3.1.11
4539          */
4540         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4541         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4542                                    &test_lane_count);
4543
4544         if (status <= 0) {
4545                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4546                 return DP_TEST_NAK;
4547         }
4548         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4549
4550         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4551                                    &test_link_bw);
4552         if (status <= 0) {
4553                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4554                 return DP_TEST_NAK;
4555         }
4556         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4557
4558         /* Validate the requested link rate and lane count */
4559         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4560                                         test_lane_count))
4561                 return DP_TEST_NAK;
4562
4563         intel_dp->compliance.test_lane_count = test_lane_count;
4564         intel_dp->compliance.test_link_rate = test_link_rate;
4565
4566         return DP_TEST_ACK;
4567 }
4568
4569 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4570 {
4571         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4572         u8 test_pattern;
4573         u8 test_misc;
4574         __be16 h_width, v_height;
4575         int status = 0;
4576
4577         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4578         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4579                                    &test_pattern);
4580         if (status <= 0) {
4581                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4582                 return DP_TEST_NAK;
4583         }
4584         if (test_pattern != DP_COLOR_RAMP)
4585                 return DP_TEST_NAK;
4586
4587         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4588                                   &h_width, 2);
4589         if (status <= 0) {
4590                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4591                 return DP_TEST_NAK;
4592         }
4593
4594         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4595                                   &v_height, 2);
4596         if (status <= 0) {
4597                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4598                 return DP_TEST_NAK;
4599         }
4600
4601         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4602                                    &test_misc);
4603         if (status <= 0) {
4604                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4605                 return DP_TEST_NAK;
4606         }
4607         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4608                 return DP_TEST_NAK;
4609         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4610                 return DP_TEST_NAK;
4611         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4612         case DP_TEST_BIT_DEPTH_6:
4613                 intel_dp->compliance.test_data.bpc = 6;
4614                 break;
4615         case DP_TEST_BIT_DEPTH_8:
4616                 intel_dp->compliance.test_data.bpc = 8;
4617                 break;
4618         default:
4619                 return DP_TEST_NAK;
4620         }
4621
4622         intel_dp->compliance.test_data.video_pattern = test_pattern;
4623         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4624         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4625         /* Set test active flag here so userspace doesn't interrupt things */
4626         intel_dp->compliance.test_active = true;
4627
4628         return DP_TEST_ACK;
4629 }
4630
4631 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4632 {
4633         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4634         u8 test_result = DP_TEST_ACK;
4635         struct intel_connector *intel_connector = intel_dp->attached_connector;
4636         struct drm_connector *connector = &intel_connector->base;
4637
4638         if (intel_connector->detect_edid == NULL ||
4639             connector->edid_corrupt ||
4640             intel_dp->aux.i2c_defer_count > 6) {
4641                 /* Check EDID read for NACKs, DEFERs and corruption
4642                  * (DP CTS 1.2 Core r1.1)
4643                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4644                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4645                  *    4.2.2.6 : EDID corruption detected
4646                  * Use failsafe mode for all cases
4647                  */
4648                 if (intel_dp->aux.i2c_nack_count > 0 ||
4649                         intel_dp->aux.i2c_defer_count > 0)
4650                         drm_dbg_kms(&i915->drm,
4651                                     "EDID read had %d NACKs, %d DEFERs\n",
4652                                     intel_dp->aux.i2c_nack_count,
4653                                     intel_dp->aux.i2c_defer_count);
4654                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4655         } else {
4656                 /* FIXME: Get rid of drm_edid_raw() */
4657                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4658
4659                 /* We have to write the checksum of the last block read */
4660                 block += block->extensions;
4661
4662                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4663                                        block->checksum) <= 0)
4664                         drm_dbg_kms(&i915->drm,
4665                                     "Failed to write EDID checksum\n");
4666
4667                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4668                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4669         }
4670
4671         /* Set test active flag here so userspace doesn't interrupt things */
4672         intel_dp->compliance.test_active = true;
4673
4674         return test_result;
4675 }
4676
4677 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4678                                         const struct intel_crtc_state *crtc_state)
4679 {
4680         struct drm_i915_private *dev_priv =
4681                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4682         struct drm_dp_phy_test_params *data =
4683                         &intel_dp->compliance.test_data.phytest;
4684         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4685         enum pipe pipe = crtc->pipe;
4686         u32 pattern_val;
4687
4688         switch (data->phy_pattern) {
4689         case DP_PHY_TEST_PATTERN_NONE:
4690                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4691                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4692                 break;
4693         case DP_PHY_TEST_PATTERN_D10_2:
4694                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4695                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4696                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4697                 break;
4698         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
4699                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4700                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4701                                DDI_DP_COMP_CTL_ENABLE |
4702                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4703                 break;
4704         case DP_PHY_TEST_PATTERN_PRBS7:
4705                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4706                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4707                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4708                 break;
4709         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
4710                 /*
4711                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4712                  * current firmware of DPR-100 could not set it, so hardcoding
4713                  * now for complaince test.
4714                  */
4715                 drm_dbg_kms(&dev_priv->drm,
4716                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4717                 pattern_val = 0x3e0f83e0;
4718                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4719                 pattern_val = 0x0f83e0f8;
4720                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4721                 pattern_val = 0x0000f83e;
4722                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4723                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4724                                DDI_DP_COMP_CTL_ENABLE |
4725                                DDI_DP_COMP_CTL_CUSTOM80);
4726                 break;
4727         case DP_PHY_TEST_PATTERN_CP2520:
4728                 /*
4729                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4730                  * current firmware of DPR-100 could not set it, so hardcoding
4731                  * now for complaince test.
4732                  */
4733                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4734                 pattern_val = 0xFB;
4735                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4736                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4737                                pattern_val);
4738                 break;
4739         default:
4740                 WARN(1, "Invalid Phy Test Pattern\n");
4741         }
4742 }
4743
4744 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4745                                          const struct intel_crtc_state *crtc_state)
4746 {
4747         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4748         struct drm_dp_phy_test_params *data =
4749                 &intel_dp->compliance.test_data.phytest;
4750         u8 link_status[DP_LINK_STATUS_SIZE];
4751
4752         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4753                                              link_status) < 0) {
4754                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4755                 return;
4756         }
4757
4758         /* retrieve vswing & pre-emphasis setting */
4759         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4760                                   link_status);
4761
4762         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4763
4764         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4765
4766         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4767                           intel_dp->train_set, crtc_state->lane_count);
4768
4769         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4770                                     link_status[DP_DPCD_REV]);
4771 }
4772
4773 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4774 {
4775         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4776         struct drm_dp_phy_test_params *data =
4777                 &intel_dp->compliance.test_data.phytest;
4778
4779         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4780                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4781                 return DP_TEST_NAK;
4782         }
4783
4784         /* Set test active flag here so userspace doesn't interrupt things */
4785         intel_dp->compliance.test_active = true;
4786
4787         return DP_TEST_ACK;
4788 }
4789
4790 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4791 {
4792         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4793         u8 response = DP_TEST_NAK;
4794         u8 request = 0;
4795         int status;
4796
4797         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4798         if (status <= 0) {
4799                 drm_dbg_kms(&i915->drm,
4800                             "Could not read test request from sink\n");
4801                 goto update_status;
4802         }
4803
4804         switch (request) {
4805         case DP_TEST_LINK_TRAINING:
4806                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4807                 response = intel_dp_autotest_link_training(intel_dp);
4808                 break;
4809         case DP_TEST_LINK_VIDEO_PATTERN:
4810                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4811                 response = intel_dp_autotest_video_pattern(intel_dp);
4812                 break;
4813         case DP_TEST_LINK_EDID_READ:
4814                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4815                 response = intel_dp_autotest_edid(intel_dp);
4816                 break;
4817         case DP_TEST_LINK_PHY_TEST_PATTERN:
4818                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4819                 response = intel_dp_autotest_phy_pattern(intel_dp);
4820                 break;
4821         default:
4822                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4823                             request);
4824                 break;
4825         }
4826
4827         if (response & DP_TEST_ACK)
4828                 intel_dp->compliance.test_type = request;
4829
4830 update_status:
4831         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4832         if (status <= 0)
4833                 drm_dbg_kms(&i915->drm,
4834                             "Could not write test response to sink\n");
4835 }
4836
4837 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4838                              u8 link_status[DP_LINK_STATUS_SIZE])
4839 {
4840         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4841         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4842         bool uhbr = intel_dp->link_rate >= 1000000;
4843         bool ok;
4844
4845         if (uhbr)
4846                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4847                                                           intel_dp->lane_count);
4848         else
4849                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4850
4851         if (ok)
4852                 return true;
4853
4854         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4855         drm_dbg_kms(&i915->drm,
4856                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4857                     encoder->base.base.id, encoder->base.name,
4858                     uhbr ? "128b/132b" : "8b/10b");
4859
4860         return false;
4861 }
4862
4863 static void
4864 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4865 {
4866         bool handled = false;
4867
4868         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4869
4870         if (esi[1] & DP_CP_IRQ) {
4871                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4872                 ack[1] |= DP_CP_IRQ;
4873         }
4874 }
4875
4876 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4877 {
4878         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4879         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4880         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4881         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4882
4883         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4884                              esi_link_status_size) != esi_link_status_size) {
4885                 drm_err(&i915->drm,
4886                         "[ENCODER:%d:%s] Failed to read link status\n",
4887                         encoder->base.base.id, encoder->base.name);
4888                 return false;
4889         }
4890
4891         return intel_dp_link_ok(intel_dp, link_status);
4892 }
4893
4894 /**
4895  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4896  * @intel_dp: Intel DP struct
4897  *
4898  * Read any pending MST interrupts, call MST core to handle these and ack the
4899  * interrupts. Check if the main and AUX link state is ok.
4900  *
4901  * Returns:
4902  * - %true if pending interrupts were serviced (or no interrupts were
4903  *   pending) w/o detecting an error condition.
4904  * - %false if an error condition - like AUX failure or a loss of link - is
4905  *   detected, which needs servicing from the hotplug work.
4906  */
4907 static bool
4908 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4909 {
4910         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4911         bool link_ok = true;
4912
4913         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4914
4915         for (;;) {
4916                 u8 esi[4] = {};
4917                 u8 ack[4] = {};
4918
4919                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4920                         drm_dbg_kms(&i915->drm,
4921                                     "failed to get ESI - device may have failed\n");
4922                         link_ok = false;
4923
4924                         break;
4925                 }
4926
4927                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4928
4929                 if (intel_dp->active_mst_links > 0 && link_ok &&
4930                     esi[3] & LINK_STATUS_CHANGED) {
4931                         if (!intel_dp_mst_link_status(intel_dp))
4932                                 link_ok = false;
4933                         ack[3] |= LINK_STATUS_CHANGED;
4934                 }
4935
4936                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4937
4938                 if (!memchr_inv(ack, 0, sizeof(ack)))
4939                         break;
4940
4941                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4942                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4943
4944                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4945                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4946         }
4947
4948         return link_ok;
4949 }
4950
4951 static void
4952 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4953 {
4954         bool is_active;
4955         u8 buf = 0;
4956
4957         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4958         if (intel_dp->frl.is_trained && !is_active) {
4959                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4960                         return;
4961
4962                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4963                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4964                         return;
4965
4966                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4967
4968                 intel_dp->frl.is_trained = false;
4969
4970                 /* Restart FRL training or fall back to TMDS mode */
4971                 intel_dp_check_frl_training(intel_dp);
4972         }
4973 }
4974
4975 static bool
4976 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4977 {
4978         u8 link_status[DP_LINK_STATUS_SIZE];
4979
4980         if (!intel_dp->link_trained)
4981                 return false;
4982
4983         /*
4984          * While PSR source HW is enabled, it will control main-link sending
4985          * frames, enabling and disabling it so trying to do a retrain will fail
4986          * as the link would or not be on or it could mix training patterns
4987          * and frame data at the same time causing retrain to fail.
4988          * Also when exiting PSR, HW will retrain the link anyways fixing
4989          * any link status error.
4990          */
4991         if (intel_psr_enabled(intel_dp))
4992                 return false;
4993
4994         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4995                                              link_status) < 0)
4996                 return false;
4997
4998         /*
4999          * Validate the cached values of intel_dp->link_rate and
5000          * intel_dp->lane_count before attempting to retrain.
5001          *
5002          * FIXME would be nice to user the crtc state here, but since
5003          * we need to call this from the short HPD handler that seems
5004          * a bit hard.
5005          */
5006         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5007                                         intel_dp->lane_count))
5008                 return false;
5009
5010         /* Retrain if link not ok */
5011         return !intel_dp_link_ok(intel_dp, link_status);
5012 }
5013
5014 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5015                                    const struct drm_connector_state *conn_state)
5016 {
5017         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5018         struct intel_encoder *encoder;
5019         enum pipe pipe;
5020
5021         if (!conn_state->best_encoder)
5022                 return false;
5023
5024         /* SST */
5025         encoder = &dp_to_dig_port(intel_dp)->base;
5026         if (conn_state->best_encoder == &encoder->base)
5027                 return true;
5028
5029         /* MST */
5030         for_each_pipe(i915, pipe) {
5031                 encoder = &intel_dp->mst_encoders[pipe]->base;
5032                 if (conn_state->best_encoder == &encoder->base)
5033                         return true;
5034         }
5035
5036         return false;
5037 }
5038
5039 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5040                               struct drm_modeset_acquire_ctx *ctx,
5041                               u8 *pipe_mask)
5042 {
5043         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5044         struct drm_connector_list_iter conn_iter;
5045         struct intel_connector *connector;
5046         int ret = 0;
5047
5048         *pipe_mask = 0;
5049
5050         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5051         for_each_intel_connector_iter(connector, &conn_iter) {
5052                 struct drm_connector_state *conn_state =
5053                         connector->base.state;
5054                 struct intel_crtc_state *crtc_state;
5055                 struct intel_crtc *crtc;
5056
5057                 if (!intel_dp_has_connector(intel_dp, conn_state))
5058                         continue;
5059
5060                 crtc = to_intel_crtc(conn_state->crtc);
5061                 if (!crtc)
5062                         continue;
5063
5064                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5065                 if (ret)
5066                         break;
5067
5068                 crtc_state = to_intel_crtc_state(crtc->base.state);
5069
5070                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5071
5072                 if (!crtc_state->hw.active)
5073                         continue;
5074
5075                 if (conn_state->commit &&
5076                     !try_wait_for_completion(&conn_state->commit->hw_done))
5077                         continue;
5078
5079                 *pipe_mask |= BIT(crtc->pipe);
5080         }
5081         drm_connector_list_iter_end(&conn_iter);
5082
5083         return ret;
5084 }
5085
5086 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5087 {
5088         struct intel_connector *connector = intel_dp->attached_connector;
5089
5090         return connector->base.status == connector_status_connected ||
5091                 intel_dp->is_mst;
5092 }
5093
5094 int intel_dp_retrain_link(struct intel_encoder *encoder,
5095                           struct drm_modeset_acquire_ctx *ctx)
5096 {
5097         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5098         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5099         struct intel_crtc *crtc;
5100         u8 pipe_mask;
5101         int ret;
5102
5103         if (!intel_dp_is_connected(intel_dp))
5104                 return 0;
5105
5106         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5107                                ctx);
5108         if (ret)
5109                 return ret;
5110
5111         if (!intel_dp_needs_link_retrain(intel_dp))
5112                 return 0;
5113
5114         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5115         if (ret)
5116                 return ret;
5117
5118         if (pipe_mask == 0)
5119                 return 0;
5120
5121         if (!intel_dp_needs_link_retrain(intel_dp))
5122                 return 0;
5123
5124         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5125                     encoder->base.base.id, encoder->base.name);
5126
5127         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5128                 const struct intel_crtc_state *crtc_state =
5129                         to_intel_crtc_state(crtc->base.state);
5130
5131                 /* Suppress underruns caused by re-training */
5132                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5133                 if (crtc_state->has_pch_encoder)
5134                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5135                                                               intel_crtc_pch_transcoder(crtc), false);
5136         }
5137
5138         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5139                 const struct intel_crtc_state *crtc_state =
5140                         to_intel_crtc_state(crtc->base.state);
5141
5142                 /* retrain on the MST master transcoder */
5143                 if (DISPLAY_VER(dev_priv) >= 12 &&
5144                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5145                     !intel_dp_mst_is_master_trans(crtc_state))
5146                         continue;
5147
5148                 intel_dp_check_frl_training(intel_dp);
5149                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
5150                 intel_dp_start_link_train(intel_dp, crtc_state);
5151                 intel_dp_stop_link_train(intel_dp, crtc_state);
5152                 break;
5153         }
5154
5155         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5156                 const struct intel_crtc_state *crtc_state =
5157                         to_intel_crtc_state(crtc->base.state);
5158
5159                 /* Keep underrun reporting disabled until things are stable */
5160                 intel_crtc_wait_for_next_vblank(crtc);
5161
5162                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5163                 if (crtc_state->has_pch_encoder)
5164                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5165                                                               intel_crtc_pch_transcoder(crtc), true);
5166         }
5167
5168         return 0;
5169 }
5170
5171 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
5172                                   struct drm_modeset_acquire_ctx *ctx,
5173                                   u8 *pipe_mask)
5174 {
5175         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5176         struct drm_connector_list_iter conn_iter;
5177         struct intel_connector *connector;
5178         int ret = 0;
5179
5180         *pipe_mask = 0;
5181
5182         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5183         for_each_intel_connector_iter(connector, &conn_iter) {
5184                 struct drm_connector_state *conn_state =
5185                         connector->base.state;
5186                 struct intel_crtc_state *crtc_state;
5187                 struct intel_crtc *crtc;
5188
5189                 if (!intel_dp_has_connector(intel_dp, conn_state))
5190                         continue;
5191
5192                 crtc = to_intel_crtc(conn_state->crtc);
5193                 if (!crtc)
5194                         continue;
5195
5196                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5197                 if (ret)
5198                         break;
5199
5200                 crtc_state = to_intel_crtc_state(crtc->base.state);
5201
5202                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5203
5204                 if (!crtc_state->hw.active)
5205                         continue;
5206
5207                 if (conn_state->commit &&
5208                     !try_wait_for_completion(&conn_state->commit->hw_done))
5209                         continue;
5210
5211                 *pipe_mask |= BIT(crtc->pipe);
5212         }
5213         drm_connector_list_iter_end(&conn_iter);
5214
5215         return ret;
5216 }
5217
5218 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
5219                                 struct drm_modeset_acquire_ctx *ctx)
5220 {
5221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5222         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5223         struct intel_crtc *crtc;
5224         u8 pipe_mask;
5225         int ret;
5226
5227         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5228                                ctx);
5229         if (ret)
5230                 return ret;
5231
5232         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
5233         if (ret)
5234                 return ret;
5235
5236         if (pipe_mask == 0)
5237                 return 0;
5238
5239         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
5240                     encoder->base.base.id, encoder->base.name);
5241
5242         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
5243                 const struct intel_crtc_state *crtc_state =
5244                         to_intel_crtc_state(crtc->base.state);
5245
5246                 /* test on the MST master transcoder */
5247                 if (DISPLAY_VER(dev_priv) >= 12 &&
5248                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
5249                     !intel_dp_mst_is_master_trans(crtc_state))
5250                         continue;
5251
5252                 intel_dp_process_phy_request(intel_dp, crtc_state);
5253                 break;
5254         }
5255
5256         return 0;
5257 }
5258
5259 void intel_dp_phy_test(struct intel_encoder *encoder)
5260 {
5261         struct drm_modeset_acquire_ctx ctx;
5262         int ret;
5263
5264         drm_modeset_acquire_init(&ctx, 0);
5265
5266         for (;;) {
5267                 ret = intel_dp_do_phy_test(encoder, &ctx);
5268
5269                 if (ret == -EDEADLK) {
5270                         drm_modeset_backoff(&ctx);
5271                         continue;
5272                 }
5273
5274                 break;
5275         }
5276
5277         drm_modeset_drop_locks(&ctx);
5278         drm_modeset_acquire_fini(&ctx);
5279         drm_WARN(encoder->base.dev, ret,
5280                  "Acquiring modeset locks failed with %i\n", ret);
5281 }
5282
5283 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5284 {
5285         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5286         u8 val;
5287
5288         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5289                 return;
5290
5291         if (drm_dp_dpcd_readb(&intel_dp->aux,
5292                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5293                 return;
5294
5295         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5296
5297         if (val & DP_AUTOMATED_TEST_REQUEST)
5298                 intel_dp_handle_test_request(intel_dp);
5299
5300         if (val & DP_CP_IRQ)
5301                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5302
5303         if (val & DP_SINK_SPECIFIC_IRQ)
5304                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5305 }
5306
5307 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5308 {
5309         u8 val;
5310
5311         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5312                 return;
5313
5314         if (drm_dp_dpcd_readb(&intel_dp->aux,
5315                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5316                 return;
5317
5318         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5319                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5320                 return;
5321
5322         if (val & HDMI_LINK_STATUS_CHANGED)
5323                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5324 }
5325
5326 /*
5327  * According to DP spec
5328  * 5.1.2:
5329  *  1. Read DPCD
5330  *  2. Configure link according to Receiver Capabilities
5331  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5332  *  4. Check link status on receipt of hot-plug interrupt
5333  *
5334  * intel_dp_short_pulse -  handles short pulse interrupts
5335  * when full detection is not required.
5336  * Returns %true if short pulse is handled and full detection
5337  * is NOT required and %false otherwise.
5338  */
5339 static bool
5340 intel_dp_short_pulse(struct intel_dp *intel_dp)
5341 {
5342         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5343         u8 old_sink_count = intel_dp->sink_count;
5344         bool ret;
5345
5346         /*
5347          * Clearing compliance test variables to allow capturing
5348          * of values for next automated test request.
5349          */
5350         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5351
5352         /*
5353          * Now read the DPCD to see if it's actually running
5354          * If the current value of sink count doesn't match with
5355          * the value that was stored earlier or dpcd read failed
5356          * we need to do full detection
5357          */
5358         ret = intel_dp_get_dpcd(intel_dp);
5359
5360         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5361                 /* No need to proceed if we are going to do full detect */
5362                 return false;
5363         }
5364
5365         intel_dp_check_device_service_irq(intel_dp);
5366         intel_dp_check_link_service_irq(intel_dp);
5367
5368         /* Handle CEC interrupts, if any */
5369         drm_dp_cec_irq(&intel_dp->aux);
5370
5371         /* defer to the hotplug work for link retraining if needed */
5372         if (intel_dp_needs_link_retrain(intel_dp))
5373                 return false;
5374
5375         intel_psr_short_pulse(intel_dp);
5376
5377         switch (intel_dp->compliance.test_type) {
5378         case DP_TEST_LINK_TRAINING:
5379                 drm_dbg_kms(&dev_priv->drm,
5380                             "Link Training Compliance Test requested\n");
5381                 /* Send a Hotplug Uevent to userspace to start modeset */
5382                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5383                 break;
5384         case DP_TEST_LINK_PHY_TEST_PATTERN:
5385                 drm_dbg_kms(&dev_priv->drm,
5386                             "PHY test pattern Compliance Test requested\n");
5387                 /*
5388                  * Schedule long hpd to do the test
5389                  *
5390                  * FIXME get rid of the ad-hoc phy test modeset code
5391                  * and properly incorporate it into the normal modeset.
5392                  */
5393                 return false;
5394         }
5395
5396         return true;
5397 }
5398
5399 /* XXX this is probably wrong for multiple downstream ports */
5400 static enum drm_connector_status
5401 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5402 {
5403         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5404         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5405         u8 *dpcd = intel_dp->dpcd;
5406         u8 type;
5407
5408         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5409                 return connector_status_connected;
5410
5411         lspcon_resume(dig_port);
5412
5413         if (!intel_dp_get_dpcd(intel_dp))
5414                 return connector_status_disconnected;
5415
5416         /* if there's no downstream port, we're done */
5417         if (!drm_dp_is_branch(dpcd))
5418                 return connector_status_connected;
5419
5420         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5421         if (intel_dp_has_sink_count(intel_dp) &&
5422             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5423                 return intel_dp->sink_count ?
5424                 connector_status_connected : connector_status_disconnected;
5425         }
5426
5427         if (intel_dp_can_mst(intel_dp))
5428                 return connector_status_connected;
5429
5430         /* If no HPD, poke DDC gently */
5431         if (drm_probe_ddc(&intel_dp->aux.ddc))
5432                 return connector_status_connected;
5433
5434         /* Well we tried, say unknown for unreliable port types */
5435         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5436                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5437                 if (type == DP_DS_PORT_TYPE_VGA ||
5438                     type == DP_DS_PORT_TYPE_NON_EDID)
5439                         return connector_status_unknown;
5440         } else {
5441                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5442                         DP_DWN_STRM_PORT_TYPE_MASK;
5443                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5444                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5445                         return connector_status_unknown;
5446         }
5447
5448         /* Anything else is out of spec, warn and ignore */
5449         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5450         return connector_status_disconnected;
5451 }
5452
5453 static enum drm_connector_status
5454 edp_detect(struct intel_dp *intel_dp)
5455 {
5456         return connector_status_connected;
5457 }
5458
5459 /*
5460  * intel_digital_port_connected - is the specified port connected?
5461  * @encoder: intel_encoder
5462  *
5463  * In cases where there's a connector physically connected but it can't be used
5464  * by our hardware we also return false, since the rest of the driver should
5465  * pretty much treat the port as disconnected. This is relevant for type-C
5466  * (starting on ICL) where there's ownership involved.
5467  *
5468  * Return %true if port is connected, %false otherwise.
5469  */
5470 bool intel_digital_port_connected(struct intel_encoder *encoder)
5471 {
5472         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5473         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5474         bool is_connected = false;
5475         intel_wakeref_t wakeref;
5476
5477         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5478                 is_connected = dig_port->connected(encoder);
5479
5480         return is_connected;
5481 }
5482
5483 static const struct drm_edid *
5484 intel_dp_get_edid(struct intel_dp *intel_dp)
5485 {
5486         struct intel_connector *connector = intel_dp->attached_connector;
5487         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5488
5489         /* Use panel fixed edid if we have one */
5490         if (fixed_edid) {
5491                 /* invalid edid */
5492                 if (IS_ERR(fixed_edid))
5493                         return NULL;
5494
5495                 return drm_edid_dup(fixed_edid);
5496         }
5497
5498         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5499 }
5500
5501 static void
5502 intel_dp_update_dfp(struct intel_dp *intel_dp,
5503                     const struct drm_edid *drm_edid)
5504 {
5505         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5506         struct intel_connector *connector = intel_dp->attached_connector;
5507
5508         intel_dp->dfp.max_bpc =
5509                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5510                                           intel_dp->downstream_ports, drm_edid);
5511
5512         intel_dp->dfp.max_dotclock =
5513                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5514                                                intel_dp->downstream_ports);
5515
5516         intel_dp->dfp.min_tmds_clock =
5517                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5518                                                  intel_dp->downstream_ports,
5519                                                  drm_edid);
5520         intel_dp->dfp.max_tmds_clock =
5521                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5522                                                  intel_dp->downstream_ports,
5523                                                  drm_edid);
5524
5525         intel_dp->dfp.pcon_max_frl_bw =
5526                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5527                                            intel_dp->downstream_ports);
5528
5529         drm_dbg_kms(&i915->drm,
5530                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5531                     connector->base.base.id, connector->base.name,
5532                     intel_dp->dfp.max_bpc,
5533                     intel_dp->dfp.max_dotclock,
5534                     intel_dp->dfp.min_tmds_clock,
5535                     intel_dp->dfp.max_tmds_clock,
5536                     intel_dp->dfp.pcon_max_frl_bw);
5537
5538         intel_dp_get_pcon_dsc_cap(intel_dp);
5539 }
5540
5541 static bool
5542 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5543 {
5544         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5545             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5546                 return true;
5547
5548         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5549             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5550                 return true;
5551
5552         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5553             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5554                 return true;
5555
5556         return false;
5557 }
5558
5559 static void
5560 intel_dp_update_420(struct intel_dp *intel_dp)
5561 {
5562         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5563         struct intel_connector *connector = intel_dp->attached_connector;
5564
5565         intel_dp->dfp.ycbcr420_passthrough =
5566                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5567                                                   intel_dp->downstream_ports);
5568         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5569         intel_dp->dfp.ycbcr_444_to_420 =
5570                 dp_to_dig_port(intel_dp)->lspcon.active ||
5571                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5572                                                         intel_dp->downstream_ports);
5573         intel_dp->dfp.rgb_to_ycbcr =
5574                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5575                                                           intel_dp->downstream_ports,
5576                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5577
5578         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5579
5580         drm_dbg_kms(&i915->drm,
5581                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5582                     connector->base.base.id, connector->base.name,
5583                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5584                     str_yes_no(connector->base.ycbcr_420_allowed),
5585                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5586 }
5587
5588 static void
5589 intel_dp_set_edid(struct intel_dp *intel_dp)
5590 {
5591         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5592         struct intel_connector *connector = intel_dp->attached_connector;
5593         const struct drm_edid *drm_edid;
5594         bool vrr_capable;
5595
5596         intel_dp_unset_edid(intel_dp);
5597         drm_edid = intel_dp_get_edid(intel_dp);
5598         connector->detect_edid = drm_edid;
5599
5600         /* Below we depend on display info having been updated */
5601         drm_edid_connector_update(&connector->base, drm_edid);
5602
5603         vrr_capable = intel_vrr_is_capable(connector);
5604         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5605                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5606         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5607
5608         intel_dp_update_dfp(intel_dp, drm_edid);
5609         intel_dp_update_420(intel_dp);
5610
5611         drm_dp_cec_attach(&intel_dp->aux,
5612                           connector->base.display_info.source_physical_address);
5613 }
5614
5615 static void
5616 intel_dp_unset_edid(struct intel_dp *intel_dp)
5617 {
5618         struct intel_connector *connector = intel_dp->attached_connector;
5619
5620         drm_dp_cec_unset_edid(&intel_dp->aux);
5621         drm_edid_free(connector->detect_edid);
5622         connector->detect_edid = NULL;
5623
5624         intel_dp->dfp.max_bpc = 0;
5625         intel_dp->dfp.max_dotclock = 0;
5626         intel_dp->dfp.min_tmds_clock = 0;
5627         intel_dp->dfp.max_tmds_clock = 0;
5628
5629         intel_dp->dfp.pcon_max_frl_bw = 0;
5630
5631         intel_dp->dfp.ycbcr_444_to_420 = false;
5632         connector->base.ycbcr_420_allowed = false;
5633
5634         drm_connector_set_vrr_capable_property(&connector->base,
5635                                                false);
5636 }
5637
5638 static void
5639 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5640 {
5641         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5642
5643         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5644         if (!HAS_DSC(i915))
5645                 return;
5646
5647         if (intel_dp_is_edp(intel_dp))
5648                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5649                                            connector);
5650         else
5651                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5652                                           connector);
5653 }
5654
5655 static int
5656 intel_dp_detect(struct drm_connector *connector,
5657                 struct drm_modeset_acquire_ctx *ctx,
5658                 bool force)
5659 {
5660         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5661         struct intel_connector *intel_connector =
5662                 to_intel_connector(connector);
5663         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5664         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5665         struct intel_encoder *encoder = &dig_port->base;
5666         enum drm_connector_status status;
5667
5668         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5669                     connector->base.id, connector->name);
5670         drm_WARN_ON(&dev_priv->drm,
5671                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5672
5673         if (!intel_display_device_enabled(dev_priv))
5674                 return connector_status_disconnected;
5675
5676         /* Can't disconnect eDP */
5677         if (intel_dp_is_edp(intel_dp))
5678                 status = edp_detect(intel_dp);
5679         else if (intel_digital_port_connected(encoder))
5680                 status = intel_dp_detect_dpcd(intel_dp);
5681         else
5682                 status = connector_status_disconnected;
5683
5684         if (status == connector_status_disconnected) {
5685                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5686                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5687                 intel_dp->psr.sink_panel_replay_support = false;
5688
5689                 if (intel_dp->is_mst) {
5690                         drm_dbg_kms(&dev_priv->drm,
5691                                     "MST device may have disappeared %d vs %d\n",
5692                                     intel_dp->is_mst,
5693                                     intel_dp->mst_mgr.mst_state);
5694                         intel_dp->is_mst = false;
5695                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5696                                                         intel_dp->is_mst);
5697                 }
5698
5699                 goto out;
5700         }
5701
5702         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5703
5704         intel_dp_configure_mst(intel_dp);
5705
5706         /*
5707          * TODO: Reset link params when switching to MST mode, until MST
5708          * supports link training fallback params.
5709          */
5710         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5711                 intel_dp_reset_max_link_params(intel_dp);
5712                 intel_dp->reset_link_params = false;
5713         }
5714
5715         intel_dp_print_rates(intel_dp);
5716
5717         if (intel_dp->is_mst) {
5718                 /*
5719                  * If we are in MST mode then this connector
5720                  * won't appear connected or have anything
5721                  * with EDID on it
5722                  */
5723                 status = connector_status_disconnected;
5724                 goto out;
5725         }
5726
5727         /*
5728          * Some external monitors do not signal loss of link synchronization
5729          * with an IRQ_HPD, so force a link status check.
5730          */
5731         if (!intel_dp_is_edp(intel_dp)) {
5732                 int ret;
5733
5734                 ret = intel_dp_retrain_link(encoder, ctx);
5735                 if (ret)
5736                         return ret;
5737         }
5738
5739         /*
5740          * Clearing NACK and defer counts to get their exact values
5741          * while reading EDID which are required by Compliance tests
5742          * 4.2.2.4 and 4.2.2.5
5743          */
5744         intel_dp->aux.i2c_nack_count = 0;
5745         intel_dp->aux.i2c_defer_count = 0;
5746
5747         intel_dp_set_edid(intel_dp);
5748         if (intel_dp_is_edp(intel_dp) ||
5749             to_intel_connector(connector)->detect_edid)
5750                 status = connector_status_connected;
5751
5752         intel_dp_check_device_service_irq(intel_dp);
5753
5754 out:
5755         if (status != connector_status_connected && !intel_dp->is_mst)
5756                 intel_dp_unset_edid(intel_dp);
5757
5758         if (!intel_dp_is_edp(intel_dp))
5759                 drm_dp_set_subconnector_property(connector,
5760                                                  status,
5761                                                  intel_dp->dpcd,
5762                                                  intel_dp->downstream_ports);
5763         return status;
5764 }
5765
5766 static void
5767 intel_dp_force(struct drm_connector *connector)
5768 {
5769         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5770         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5771         struct intel_encoder *intel_encoder = &dig_port->base;
5772         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5773
5774         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5775                     connector->base.id, connector->name);
5776         intel_dp_unset_edid(intel_dp);
5777
5778         if (connector->status != connector_status_connected)
5779                 return;
5780
5781         intel_dp_set_edid(intel_dp);
5782 }
5783
5784 static int intel_dp_get_modes(struct drm_connector *connector)
5785 {
5786         struct intel_connector *intel_connector = to_intel_connector(connector);
5787         int num_modes;
5788
5789         /* drm_edid_connector_update() done in ->detect() or ->force() */
5790         num_modes = drm_edid_connector_add_modes(connector);
5791
5792         /* Also add fixed mode, which may or may not be present in EDID */
5793         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5794                 num_modes += intel_panel_get_modes(intel_connector);
5795
5796         if (num_modes)
5797                 return num_modes;
5798
5799         if (!intel_connector->detect_edid) {
5800                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5801                 struct drm_display_mode *mode;
5802
5803                 mode = drm_dp_downstream_mode(connector->dev,
5804                                               intel_dp->dpcd,
5805                                               intel_dp->downstream_ports);
5806                 if (mode) {
5807                         drm_mode_probed_add(connector, mode);
5808                         num_modes++;
5809                 }
5810         }
5811
5812         return num_modes;
5813 }
5814
5815 static int
5816 intel_dp_connector_register(struct drm_connector *connector)
5817 {
5818         struct drm_i915_private *i915 = to_i915(connector->dev);
5819         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5820         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5821         struct intel_lspcon *lspcon = &dig_port->lspcon;
5822         int ret;
5823
5824         ret = intel_connector_register(connector);
5825         if (ret)
5826                 return ret;
5827
5828         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5829                     intel_dp->aux.name, connector->kdev->kobj.name);
5830
5831         intel_dp->aux.dev = connector->kdev;
5832         ret = drm_dp_aux_register(&intel_dp->aux);
5833         if (!ret)
5834                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5835
5836         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5837                 return ret;
5838
5839         /*
5840          * ToDo: Clean this up to handle lspcon init and resume more
5841          * efficiently and streamlined.
5842          */
5843         if (lspcon_init(dig_port)) {
5844                 lspcon_detect_hdr_capability(lspcon);
5845                 if (lspcon->hdr_supported)
5846                         drm_connector_attach_hdr_output_metadata_property(connector);
5847         }
5848
5849         return ret;
5850 }
5851
5852 static void
5853 intel_dp_connector_unregister(struct drm_connector *connector)
5854 {
5855         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5856
5857         drm_dp_cec_unregister_connector(&intel_dp->aux);
5858         drm_dp_aux_unregister(&intel_dp->aux);
5859         intel_connector_unregister(connector);
5860 }
5861
5862 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5863 {
5864         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5865         struct intel_dp *intel_dp = &dig_port->dp;
5866
5867         intel_dp_mst_encoder_cleanup(dig_port);
5868
5869         intel_pps_vdd_off_sync(intel_dp);
5870
5871         /*
5872          * Ensure power off delay is respected on module remove, so that we can
5873          * reduce delays at driver probe. See pps_init_timestamps().
5874          */
5875         intel_pps_wait_power_cycle(intel_dp);
5876
5877         intel_dp_aux_fini(intel_dp);
5878 }
5879
5880 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5881 {
5882         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5883
5884         intel_pps_vdd_off_sync(intel_dp);
5885 }
5886
5887 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5888 {
5889         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5890
5891         intel_pps_wait_power_cycle(intel_dp);
5892 }
5893
5894 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5895                                     int tile_group_id)
5896 {
5897         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5898         struct drm_connector_list_iter conn_iter;
5899         struct drm_connector *connector;
5900         int ret = 0;
5901
5902         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5903         drm_for_each_connector_iter(connector, &conn_iter) {
5904                 struct drm_connector_state *conn_state;
5905                 struct intel_crtc_state *crtc_state;
5906                 struct intel_crtc *crtc;
5907
5908                 if (!connector->has_tile ||
5909                     connector->tile_group->id != tile_group_id)
5910                         continue;
5911
5912                 conn_state = drm_atomic_get_connector_state(&state->base,
5913                                                             connector);
5914                 if (IS_ERR(conn_state)) {
5915                         ret = PTR_ERR(conn_state);
5916                         break;
5917                 }
5918
5919                 crtc = to_intel_crtc(conn_state->crtc);
5920
5921                 if (!crtc)
5922                         continue;
5923
5924                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5925                 crtc_state->uapi.mode_changed = true;
5926
5927                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5928                 if (ret)
5929                         break;
5930         }
5931         drm_connector_list_iter_end(&conn_iter);
5932
5933         return ret;
5934 }
5935
5936 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5937 {
5938         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5939         struct intel_crtc *crtc;
5940
5941         if (transcoders == 0)
5942                 return 0;
5943
5944         for_each_intel_crtc(&dev_priv->drm, crtc) {
5945                 struct intel_crtc_state *crtc_state;
5946                 int ret;
5947
5948                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5949                 if (IS_ERR(crtc_state))
5950                         return PTR_ERR(crtc_state);
5951
5952                 if (!crtc_state->hw.enable)
5953                         continue;
5954
5955                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5956                         continue;
5957
5958                 crtc_state->uapi.mode_changed = true;
5959
5960                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5961                 if (ret)
5962                         return ret;
5963
5964                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5965                 if (ret)
5966                         return ret;
5967
5968                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5969         }
5970
5971         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5972
5973         return 0;
5974 }
5975
5976 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5977                                       struct drm_connector *connector)
5978 {
5979         const struct drm_connector_state *old_conn_state =
5980                 drm_atomic_get_old_connector_state(&state->base, connector);
5981         const struct intel_crtc_state *old_crtc_state;
5982         struct intel_crtc *crtc;
5983         u8 transcoders;
5984
5985         crtc = to_intel_crtc(old_conn_state->crtc);
5986         if (!crtc)
5987                 return 0;
5988
5989         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5990
5991         if (!old_crtc_state->hw.active)
5992                 return 0;
5993
5994         transcoders = old_crtc_state->sync_mode_slaves_mask;
5995         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5996                 transcoders |= BIT(old_crtc_state->master_transcoder);
5997
5998         return intel_modeset_affected_transcoders(state,
5999                                                   transcoders);
6000 }
6001
6002 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6003                                            struct drm_atomic_state *_state)
6004 {
6005         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6006         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6007         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6008         struct intel_connector *intel_conn = to_intel_connector(conn);
6009         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6010         int ret;
6011
6012         ret = intel_digital_connector_atomic_check(conn, &state->base);
6013         if (ret)
6014                 return ret;
6015
6016         if (intel_dp_mst_source_support(intel_dp)) {
6017                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6018                 if (ret)
6019                         return ret;
6020         }
6021
6022         /*
6023          * We don't enable port sync on BDW due to missing w/as and
6024          * due to not having adjusted the modeset sequence appropriately.
6025          */
6026         if (DISPLAY_VER(dev_priv) < 9)
6027                 return 0;
6028
6029         if (!intel_connector_needs_modeset(state, conn))
6030                 return 0;
6031
6032         if (conn->has_tile) {
6033                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6034                 if (ret)
6035                         return ret;
6036         }
6037
6038         return intel_modeset_synced_crtcs(state, conn);
6039 }
6040
6041 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6042                                        enum drm_connector_status hpd_state)
6043 {
6044         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6045         struct drm_i915_private *i915 = to_i915(connector->dev);
6046         bool hpd_high = hpd_state == connector_status_connected;
6047         unsigned int hpd_pin = encoder->hpd_pin;
6048         bool need_work = false;
6049
6050         spin_lock_irq(&i915->irq_lock);
6051         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6052                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
6053
6054                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6055                 need_work = true;
6056         }
6057         spin_unlock_irq(&i915->irq_lock);
6058
6059         if (need_work)
6060                 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
6061 }
6062
6063 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6064         .force = intel_dp_force,
6065         .fill_modes = drm_helper_probe_single_connector_modes,
6066         .atomic_get_property = intel_digital_connector_atomic_get_property,
6067         .atomic_set_property = intel_digital_connector_atomic_set_property,
6068         .late_register = intel_dp_connector_register,
6069         .early_unregister = intel_dp_connector_unregister,
6070         .destroy = intel_connector_destroy,
6071         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6072         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6073         .oob_hotplug_event = intel_dp_oob_hotplug_event,
6074 };
6075
6076 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6077         .detect_ctx = intel_dp_detect,
6078         .get_modes = intel_dp_get_modes,
6079         .mode_valid = intel_dp_mode_valid,
6080         .atomic_check = intel_dp_connector_atomic_check,
6081 };
6082
6083 enum irqreturn
6084 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6085 {
6086         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6087         struct intel_dp *intel_dp = &dig_port->dp;
6088
6089         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6090             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6091                 /*
6092                  * vdd off can generate a long/short pulse on eDP which
6093                  * would require vdd on to handle it, and thus we
6094                  * would end up in an endless cycle of
6095                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6096                  */
6097                 drm_dbg_kms(&i915->drm,
6098                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6099                             long_hpd ? "long" : "short",
6100                             dig_port->base.base.base.id,
6101                             dig_port->base.base.name);
6102                 return IRQ_HANDLED;
6103         }
6104
6105         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6106                     dig_port->base.base.base.id,
6107                     dig_port->base.base.name,
6108                     long_hpd ? "long" : "short");
6109
6110         if (long_hpd) {
6111                 intel_dp->reset_link_params = true;
6112                 return IRQ_NONE;
6113         }
6114
6115         if (intel_dp->is_mst) {
6116                 if (!intel_dp_check_mst_status(intel_dp))
6117                         return IRQ_NONE;
6118         } else if (!intel_dp_short_pulse(intel_dp)) {
6119                 return IRQ_NONE;
6120         }
6121
6122         return IRQ_HANDLED;
6123 }
6124
6125 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6126                                   const struct intel_bios_encoder_data *devdata,
6127                                   enum port port)
6128 {
6129         /*
6130          * eDP not supported on g4x. so bail out early just
6131          * for a bit extra safety in case the VBT is bonkers.
6132          */
6133         if (DISPLAY_VER(dev_priv) < 5)
6134                 return false;
6135
6136         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6137                 return true;
6138
6139         return devdata && intel_bios_encoder_supports_edp(devdata);
6140 }
6141
6142 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
6143 {
6144         const struct intel_bios_encoder_data *devdata =
6145                 intel_bios_encoder_data_lookup(i915, port);
6146
6147         return _intel_dp_is_port_edp(i915, devdata, port);
6148 }
6149
6150 static bool
6151 has_gamut_metadata_dip(struct intel_encoder *encoder)
6152 {
6153         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6154         enum port port = encoder->port;
6155
6156         if (intel_bios_encoder_is_lspcon(encoder->devdata))
6157                 return false;
6158
6159         if (DISPLAY_VER(i915) >= 11)
6160                 return true;
6161
6162         if (port == PORT_A)
6163                 return false;
6164
6165         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6166             DISPLAY_VER(i915) >= 9)
6167                 return true;
6168
6169         return false;
6170 }
6171
6172 static void
6173 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6174 {
6175         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6176         enum port port = dp_to_dig_port(intel_dp)->base.port;
6177
6178         if (!intel_dp_is_edp(intel_dp))
6179                 drm_connector_attach_dp_subconnector_property(connector);
6180
6181         if (!IS_G4X(dev_priv) && port != PORT_A)
6182                 intel_attach_force_audio_property(connector);
6183
6184         intel_attach_broadcast_rgb_property(connector);
6185         if (HAS_GMCH(dev_priv))
6186                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6187         else if (DISPLAY_VER(dev_priv) >= 5)
6188                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6189
6190         /* Register HDMI colorspace for case of lspcon */
6191         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6192                 drm_connector_attach_content_type_property(connector);
6193                 intel_attach_hdmi_colorspace_property(connector);
6194         } else {
6195                 intel_attach_dp_colorspace_property(connector);
6196         }
6197
6198         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6199                 drm_connector_attach_hdr_output_metadata_property(connector);
6200
6201         if (HAS_VRR(dev_priv))
6202                 drm_connector_attach_vrr_capable_property(connector);
6203 }
6204
6205 static void
6206 intel_edp_add_properties(struct intel_dp *intel_dp)
6207 {
6208         struct intel_connector *connector = intel_dp->attached_connector;
6209         struct drm_i915_private *i915 = to_i915(connector->base.dev);
6210         const struct drm_display_mode *fixed_mode =
6211                 intel_panel_preferred_fixed_mode(connector);
6212
6213         intel_attach_scaling_mode_property(&connector->base);
6214
6215         drm_connector_set_panel_orientation_with_quirk(&connector->base,
6216                                                        i915->display.vbt.orientation,
6217                                                        fixed_mode->hdisplay,
6218                                                        fixed_mode->vdisplay);
6219 }
6220
6221 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6222                                       struct intel_connector *connector)
6223 {
6224         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6225         enum pipe pipe = INVALID_PIPE;
6226
6227         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
6228                 /*
6229                  * Figure out the current pipe for the initial backlight setup.
6230                  * If the current pipe isn't valid, try the PPS pipe, and if that
6231                  * fails just assume pipe A.
6232                  */
6233                 pipe = vlv_active_pipe(intel_dp);
6234
6235                 if (pipe != PIPE_A && pipe != PIPE_B)
6236                         pipe = intel_dp->pps.pps_pipe;
6237
6238                 if (pipe != PIPE_A && pipe != PIPE_B)
6239                         pipe = PIPE_A;
6240         }
6241
6242         intel_backlight_setup(connector, pipe);
6243 }
6244
6245 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6246                                      struct intel_connector *intel_connector)
6247 {
6248         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6249         struct drm_connector *connector = &intel_connector->base;
6250         struct drm_display_mode *fixed_mode;
6251         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6252         bool has_dpcd;
6253         const struct drm_edid *drm_edid;
6254
6255         if (!intel_dp_is_edp(intel_dp))
6256                 return true;
6257
6258         /*
6259          * On IBX/CPT we may get here with LVDS already registered. Since the
6260          * driver uses the only internal power sequencer available for both
6261          * eDP and LVDS bail out early in this case to prevent interfering
6262          * with an already powered-on LVDS power sequencer.
6263          */
6264         if (intel_get_lvds_encoder(dev_priv)) {
6265                 drm_WARN_ON(&dev_priv->drm,
6266                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6267                 drm_info(&dev_priv->drm,
6268                          "LVDS was detected, not registering eDP\n");
6269
6270                 return false;
6271         }
6272
6273         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
6274                                     encoder->devdata);
6275
6276         if (!intel_pps_init(intel_dp)) {
6277                 drm_info(&dev_priv->drm,
6278                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6279                          encoder->base.base.id, encoder->base.name);
6280                 /*
6281                  * The BIOS may have still enabled VDD on the PPS even
6282                  * though it's unusable. Make sure we turn it back off
6283                  * and to release the power domain references/etc.
6284                  */
6285                 goto out_vdd_off;
6286         }
6287
6288         /*
6289          * Enable HPD sense for live status check.
6290          * intel_hpd_irq_setup() will turn it off again
6291          * if it's no longer needed later.
6292          *
6293          * The DPCD probe below will make sure VDD is on.
6294          */
6295         intel_hpd_enable_detection(encoder);
6296
6297         /* Cache DPCD and EDID for edp. */
6298         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6299
6300         if (!has_dpcd) {
6301                 /* if this fails, presume the device is a ghost */
6302                 drm_info(&dev_priv->drm,
6303                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6304                          encoder->base.base.id, encoder->base.name);
6305                 goto out_vdd_off;
6306         }
6307
6308         /*
6309          * VBT and straps are liars. Also check HPD as that seems
6310          * to be the most reliable piece of information available.
6311          *
6312          * ... expect on devices that forgot to hook HPD up for eDP
6313          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6314          * ports are attempting to use the same AUX CH, according to VBT.
6315          */
6316         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6317                 /*
6318                  * If this fails, presume the DPCD answer came
6319                  * from some other port using the same AUX CH.
6320                  *
6321                  * FIXME maybe cleaner to check this before the
6322                  * DPCD read? Would need sort out the VDD handling...
6323                  */
6324                 if (!intel_digital_port_connected(encoder)) {
6325                         drm_info(&dev_priv->drm,
6326                                  "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6327                                  encoder->base.base.id, encoder->base.name);
6328                         goto out_vdd_off;
6329                 }
6330
6331                 /*
6332                  * Unfortunately even the HPD based detection fails on
6333                  * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6334                  * back to checking for a VGA branch device. Only do this
6335                  * on known affected platforms to minimize false positives.
6336                  */
6337                 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6338                     (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6339                     DP_DWN_STRM_PORT_TYPE_ANALOG) {
6340                         drm_info(&dev_priv->drm,
6341                                  "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6342                                  encoder->base.base.id, encoder->base.name);
6343                         goto out_vdd_off;
6344                 }
6345         }
6346
6347         mutex_lock(&dev_priv->drm.mode_config.mutex);
6348         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6349         if (!drm_edid) {
6350                 /* Fallback to EDID from ACPI OpRegion, if any */
6351                 drm_edid = intel_opregion_get_edid(intel_connector);
6352                 if (drm_edid)
6353                         drm_dbg_kms(&dev_priv->drm,
6354                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6355                                     connector->base.id, connector->name);
6356         }
6357         if (drm_edid) {
6358                 if (drm_edid_connector_update(connector, drm_edid) ||
6359                     !drm_edid_connector_add_modes(connector)) {
6360                         drm_edid_connector_update(connector, NULL);
6361                         drm_edid_free(drm_edid);
6362                         drm_edid = ERR_PTR(-EINVAL);
6363                 }
6364         } else {
6365                 drm_edid = ERR_PTR(-ENOENT);
6366         }
6367
6368         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6369                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6370
6371         intel_panel_add_edid_fixed_modes(intel_connector, true);
6372
6373         /* MSO requires information from the EDID */
6374         intel_edp_mso_init(intel_dp);
6375
6376         /* multiply the mode clock and horizontal timings for MSO */
6377         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6378                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6379
6380         /* fallback to VBT if available for eDP */
6381         if (!intel_panel_preferred_fixed_mode(intel_connector))
6382                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6383
6384         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6385
6386         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6387                 drm_info(&dev_priv->drm,
6388                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6389                          encoder->base.base.id, encoder->base.name);
6390                 goto out_vdd_off;
6391         }
6392
6393         intel_panel_init(intel_connector, drm_edid);
6394
6395         intel_edp_backlight_setup(intel_dp, intel_connector);
6396
6397         intel_edp_add_properties(intel_dp);
6398
6399         intel_pps_init_late(intel_dp);
6400
6401         return true;
6402
6403 out_vdd_off:
6404         intel_pps_vdd_off_sync(intel_dp);
6405
6406         return false;
6407 }
6408
6409 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6410 {
6411         struct intel_connector *intel_connector;
6412         struct drm_connector *connector;
6413
6414         intel_connector = container_of(work, typeof(*intel_connector),
6415                                        modeset_retry_work);
6416         connector = &intel_connector->base;
6417         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6418                     connector->name);
6419
6420         /* Grab the locks before changing connector property*/
6421         mutex_lock(&connector->dev->mode_config.mutex);
6422         /* Set connector link status to BAD and send a Uevent to notify
6423          * userspace to do a modeset.
6424          */
6425         drm_connector_set_link_status_property(connector,
6426                                                DRM_MODE_LINK_STATUS_BAD);
6427         mutex_unlock(&connector->dev->mode_config.mutex);
6428         /* Send Hotplug uevent so userspace can reprobe */
6429         drm_kms_helper_connector_hotplug_event(connector);
6430 }
6431
6432 bool
6433 intel_dp_init_connector(struct intel_digital_port *dig_port,
6434                         struct intel_connector *intel_connector)
6435 {
6436         struct drm_connector *connector = &intel_connector->base;
6437         struct intel_dp *intel_dp = &dig_port->dp;
6438         struct intel_encoder *intel_encoder = &dig_port->base;
6439         struct drm_device *dev = intel_encoder->base.dev;
6440         struct drm_i915_private *dev_priv = to_i915(dev);
6441         enum port port = intel_encoder->port;
6442         enum phy phy = intel_port_to_phy(dev_priv, port);
6443         int type;
6444
6445         /* Initialize the work for modeset in case of link train failure */
6446         INIT_WORK(&intel_connector->modeset_retry_work,
6447                   intel_dp_modeset_retry_work_fn);
6448
6449         if (drm_WARN(dev, dig_port->max_lanes < 1,
6450                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6451                      dig_port->max_lanes, intel_encoder->base.base.id,
6452                      intel_encoder->base.name))
6453                 return false;
6454
6455         intel_dp->reset_link_params = true;
6456         intel_dp->pps.pps_pipe = INVALID_PIPE;
6457         intel_dp->pps.active_pipe = INVALID_PIPE;
6458
6459         /* Preserve the current hw state. */
6460         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6461         intel_dp->attached_connector = intel_connector;
6462
6463         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6464                 /*
6465                  * Currently we don't support eDP on TypeC ports, although in
6466                  * theory it could work on TypeC legacy ports.
6467                  */
6468                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6469                 type = DRM_MODE_CONNECTOR_eDP;
6470                 intel_encoder->type = INTEL_OUTPUT_EDP;
6471
6472                 /* eDP only on port B and/or C on vlv/chv */
6473                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6474                                       IS_CHERRYVIEW(dev_priv)) &&
6475                                 port != PORT_B && port != PORT_C))
6476                         return false;
6477         } else {
6478                 type = DRM_MODE_CONNECTOR_DisplayPort;
6479         }
6480
6481         intel_dp_set_default_sink_rates(intel_dp);
6482         intel_dp_set_default_max_sink_lane_count(intel_dp);
6483
6484         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6485                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6486
6487         intel_dp_aux_init(intel_dp);
6488         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6489
6490         drm_dbg_kms(&dev_priv->drm,
6491                     "Adding %s connector on [ENCODER:%d:%s]\n",
6492                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6493                     intel_encoder->base.base.id, intel_encoder->base.name);
6494
6495         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6496                                     type, &intel_dp->aux.ddc);
6497         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6498
6499         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6500                 connector->interlace_allowed = true;
6501
6502         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6503
6504         intel_connector_attach_encoder(intel_connector, intel_encoder);
6505
6506         if (HAS_DDI(dev_priv))
6507                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6508         else
6509                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6510
6511         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6512                 intel_dp_aux_fini(intel_dp);
6513                 goto fail;
6514         }
6515
6516         intel_dp_set_source_rates(intel_dp);
6517         intel_dp_set_common_rates(intel_dp);
6518         intel_dp_reset_max_link_params(intel_dp);
6519
6520         /* init MST on ports that can support it */
6521         intel_dp_mst_encoder_init(dig_port,
6522                                   intel_connector->base.base.id);
6523
6524         intel_dp_add_properties(intel_dp, connector);
6525
6526         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6527                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6528                 if (ret)
6529                         drm_dbg_kms(&dev_priv->drm,
6530                                     "HDCP init failed, skipping.\n");
6531         }
6532
6533         intel_dp->frl.is_trained = false;
6534         intel_dp->frl.trained_rate_gbps = 0;
6535
6536         intel_psr_init(intel_dp);
6537
6538         return true;
6539
6540 fail:
6541         intel_display_power_flush_work(dev_priv);
6542         drm_connector_cleanup(connector);
6543
6544         return false;
6545 }
6546
6547 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6548 {
6549         struct intel_encoder *encoder;
6550
6551         if (!HAS_DISPLAY(dev_priv))
6552                 return;
6553
6554         for_each_intel_encoder(&dev_priv->drm, encoder) {
6555                 struct intel_dp *intel_dp;
6556
6557                 if (encoder->type != INTEL_OUTPUT_DDI)
6558                         continue;
6559
6560                 intel_dp = enc_to_intel_dp(encoder);
6561
6562                 if (!intel_dp_mst_source_support(intel_dp))
6563                         continue;
6564
6565                 if (intel_dp->is_mst)
6566                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6567         }
6568 }
6569
6570 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6571 {
6572         struct intel_encoder *encoder;
6573
6574         if (!HAS_DISPLAY(dev_priv))
6575                 return;
6576
6577         for_each_intel_encoder(&dev_priv->drm, encoder) {
6578                 struct intel_dp *intel_dp;
6579                 int ret;
6580
6581                 if (encoder->type != INTEL_OUTPUT_DDI)
6582                         continue;
6583
6584                 intel_dp = enc_to_intel_dp(encoder);
6585
6586                 if (!intel_dp_mst_source_support(intel_dp))
6587                         continue;
6588
6589                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6590                                                      true);
6591                 if (ret) {
6592                         intel_dp->is_mst = false;
6593                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6594                                                         false);
6595                 }
6596         }
6597 }