drivers/gpu/drm/i915/display/intel_dmc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_reg.h"
  29 #include "intel_de.h"
  30 #include "intel_dmc.h"
  31
  32 /**
  33  * DOC: DMC Firmware Support
  34  *
  35  * From gen9 onwards we have newly added DMC (Display microcontroller) in display
  36  * engine to save and restore the state of display engine when it enter into
  37  * low-power state and comes back to normal.
  38  */
  39
  40 #define DMC_PATH(platform, major, minor) \
  41         "i915/"                          \
  42         __stringify(platform) "_dmc_ver" \
  43         __stringify(major) "_"           \
  44         __stringify(minor) ".bin"
  45
  46 #define GEN12_DMC_MAX_FW_SIZE           ICL_DMC_MAX_FW_SIZE
  47
  48 #define ADLS_DMC_PATH                   DMC_PATH(adls, 2, 01)
  49 #define ADLS_DMC_VERSION_REQUIRED       DMC_VERSION(2, 1)
  50 MODULE_FIRMWARE(ADLS_DMC_PATH);
  51
  52 #define DG1_DMC_PATH                    DMC_PATH(dg1, 2, 02)
  53 #define DG1_DMC_VERSION_REQUIRED        DMC_VERSION(2, 2)
  54 MODULE_FIRMWARE(DG1_DMC_PATH);
  55
  56 #define RKL_DMC_PATH                    DMC_PATH(rkl, 2, 02)
  57 #define RKL_DMC_VERSION_REQUIRED        DMC_VERSION(2, 2)
  58 MODULE_FIRMWARE(RKL_DMC_PATH);
  59
  60 #define TGL_DMC_PATH                    DMC_PATH(tgl, 2, 08)
  61 #define TGL_DMC_VERSION_REQUIRED        DMC_VERSION(2, 8)
  62 MODULE_FIRMWARE(TGL_DMC_PATH);
  63
  64 #define ICL_DMC_PATH                    DMC_PATH(icl, 1, 09)
  65 #define ICL_DMC_VERSION_REQUIRED        DMC_VERSION(1, 9)
  66 #define ICL_DMC_MAX_FW_SIZE             0x6000
  67 MODULE_FIRMWARE(ICL_DMC_PATH);
  68
  69 #define CNL_DMC_PATH                    DMC_PATH(cnl, 1, 07)
  70 #define CNL_DMC_VERSION_REQUIRED        DMC_VERSION(1, 7)
  71 #define CNL_DMC_MAX_FW_SIZE             GLK_DMC_MAX_FW_SIZE
  72 MODULE_FIRMWARE(CNL_DMC_PATH);
  73
  74 #define GLK_DMC_PATH                    DMC_PATH(glk, 1, 04)
  75 #define GLK_DMC_VERSION_REQUIRED        DMC_VERSION(1, 4)
  76 #define GLK_DMC_MAX_FW_SIZE             0x4000
  77 MODULE_FIRMWARE(GLK_DMC_PATH);
  78
  79 #define KBL_DMC_PATH                    DMC_PATH(kbl, 1, 04)
  80 #define KBL_DMC_VERSION_REQUIRED        DMC_VERSION(1, 4)
  81 #define KBL_DMC_MAX_FW_SIZE             BXT_DMC_MAX_FW_SIZE
  82 MODULE_FIRMWARE(KBL_DMC_PATH);
  83
  84 #define SKL_DMC_PATH                    DMC_PATH(skl, 1, 27)
  85 #define SKL_DMC_VERSION_REQUIRED        DMC_VERSION(1, 27)
  86 #define SKL_DMC_MAX_FW_SIZE             BXT_DMC_MAX_FW_SIZE
  87 MODULE_FIRMWARE(SKL_DMC_PATH);
  88
  89 #define BXT_DMC_PATH                    DMC_PATH(bxt, 1, 07)
  90 #define BXT_DMC_VERSION_REQUIRED        DMC_VERSION(1, 7)
  91 #define BXT_DMC_MAX_FW_SIZE             0x3000
  92 MODULE_FIRMWARE(BXT_DMC_PATH);
  93
  94 #define DMC_DEFAULT_FW_OFFSET           0xFFFFFFFF
  95 #define PACKAGE_MAX_FW_INFO_ENTRIES     20
  96 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES  32
  97 #define DMC_V1_MAX_MMIO_COUNT           8
  98 #define DMC_V3_MAX_MMIO_COUNT           20
  99
 100 struct intel_css_header {
 101         /* 0x09 for DMC */
 102         u32 module_type;
 103
 104         /* Includes the DMC specific header in dwords */
 105         u32 header_len;
 106
 107         /* always value would be 0x10000 */
 108         u32 header_ver;
 109
 110         /* Not used */
 111         u32 module_id;
 112
 113         /* Not used */
 114         u32 module_vendor;
 115
 116         /* in YYYYMMDD format */
 117         u32 date;
 118
 119         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
 120         u32 size;
 121
 122         /* Not used */
 123         u32 key_size;
 124
 125         /* Not used */
 126         u32 modulus_size;
 127
 128         /* Not used */
 129         u32 exponent_size;
 130
 131         /* Not used */
 132         u32 reserved1[12];
 133
 134         /* Major Minor */
 135         u32 version;
 136
 137         /* Not used */
 138         u32 reserved2[8];
 139
 140         /* Not used */
 141         u32 kernel_header_info;
 142 } __packed;
 143
 144 struct intel_fw_info {
 145         u8 reserved1;
 146
 147         /* reserved on package_header version 1, must be 0 on version 2 */
 148         u8 dmc_id;
 149
 150         /* Stepping (A, B, C, ..., *). * is a wildcard */
 151         char stepping;
 152
 153         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 154         char substepping;
 155
 156         u32 offset;
 157         u32 reserved2;
 158 } __packed;
 159
 160 struct intel_package_header {
 161         /* DMC container header length in dwords */
 162         u8 header_len;
 163
 164         /* 0x01, 0x02 */
 165         u8 header_ver;
 166
 167         u8 reserved[10];
 168
 169         /* Number of valid entries in the FWInfo array below */
 170         u32 num_entries;
 171 } __packed;
 172
 173 struct intel_dmc_header_base {
 174         /* always value would be 0x40403E3E */
 175         u32 signature;
 176
 177         /* DMC binary header length */
 178         u8 header_len;
 179
 180         /* 0x01 */
 181         u8 header_ver;
 182
 183         /* Reserved */
 184         u16 dmcc_ver;
 185
 186         /* Major, Minor */
 187         u32 project;
 188
 189         /* Firmware program size (excluding header) in dwords */
 190         u32 fw_size;
 191
 192         /* Major Minor version */
 193         u32 fw_version;
 194 } __packed;
 195
 196 struct intel_dmc_header_v1 {
 197         struct intel_dmc_header_base base;
 198
 199         /* Number of valid MMIO cycles present. */
 200         u32 mmio_count;
 201
 202         /* MMIO address */
 203         u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
 204
 205         /* MMIO data */
 206         u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
 207
 208         /* FW filename  */
 209         char dfile[32];
 210
 211         u32 reserved1[2];
 212 } __packed;
 213
 214 struct intel_dmc_header_v3 {
 215         struct intel_dmc_header_base base;
 216
 217         /* DMC RAM start MMIO address */
 218         u32 start_mmioaddr;
 219
 220         u32 reserved[9];
 221
 222         /* FW filename */
 223         char dfile[32];
 224
 225         /* Number of valid MMIO cycles present. */
 226         u32 mmio_count;
 227
 228         /* MMIO address */
 229         u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
 230
 231         /* MMIO data */
 232         u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
 233 } __packed;
 234
 235 struct stepping_info {
 236         char stepping;
 237         char substepping;
 238 };
 239
 240 static const struct stepping_info skl_stepping_info[] = {
 241         {'A', '0'}, {'B', '0'}, {'C', '0'},
 242         {'D', '0'}, {'E', '0'}, {'F', '0'},
 243         {'G', '0'}, {'H', '0'}, {'I', '0'},
 244         {'J', '0'}, {'K', '0'}
 245 };
 246
 247 static const struct stepping_info bxt_stepping_info[] = {
 248         {'A', '0'}, {'A', '1'}, {'A', '2'},
 249         {'B', '0'}, {'B', '1'}, {'B', '2'}
 250 };
 251
 252 static const struct stepping_info icl_stepping_info[] = {
 253         {'A', '0'}, {'A', '1'}, {'A', '2'},
 254         {'B', '0'}, {'B', '2'},
 255         {'C', '0'}
 256 };
 257
 258 static const struct stepping_info no_stepping_info = { '*', '*' };
 259
 260 static const struct stepping_info *
 261 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 262 {
 263         const struct stepping_info *si;
 264         unsigned int size;
 265
 266         if (IS_ICELAKE(dev_priv)) {
 267                 size = ARRAY_SIZE(icl_stepping_info);
 268                 si = icl_stepping_info;
 269         } else if (IS_SKYLAKE(dev_priv)) {
 270                 size = ARRAY_SIZE(skl_stepping_info);
 271                 si = skl_stepping_info;
 272         } else if (IS_BROXTON(dev_priv)) {
 273                 size = ARRAY_SIZE(bxt_stepping_info);
 274                 si = bxt_stepping_info;
 275         } else {
 276                 size = 0;
 277                 si = NULL;
 278         }
 279
 280         if (INTEL_REVID(dev_priv) < size)
 281                 return si + INTEL_REVID(dev_priv);
 282
 283         return &no_stepping_info;
 284 }
 285
 286 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 287 {
 288         u32 val, mask;
 289
 290         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 291
 292         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 293                 mask |= DC_STATE_DEBUG_MASK_CORES;
 294
 295         /* The below bit doesn't need to be cleared ever afterwards */
 296         val = intel_de_read(dev_priv, DC_STATE_DEBUG);
 297         if ((val & mask) != mask) {
 298                 val |= mask;
 299                 intel_de_write(dev_priv, DC_STATE_DEBUG, val);
 300                 intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 301         }
 302 }
 303
 304 /**
 305  * intel_dmc_load_program() - write the firmware from memory to register.
 306  * @dev_priv: i915 drm device.
 307  *
 308  * DMC firmware is read from a .bin file and kept in internal memory one time.
 309  * Everytime display comes back from low power state this function is called to
 310  * copy the firmware from internal memory to registers.
 311  */
 312 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 313 {
 314         u32 *payload = dev_priv->dmc.dmc_payload;
 315         u32 i, fw_size;
 316
 317         if (!HAS_DMC(dev_priv)) {
 318                 drm_err(&dev_priv->drm,
 319                         "No DMC support available for this platform\n");
 320                 return;
 321         }
 322
 323         if (!dev_priv->dmc.dmc_payload) {
 324                 drm_err(&dev_priv->drm,
 325                         "Tried to program CSR with empty payload\n");
 326                 return;
 327         }
 328
 329         fw_size = dev_priv->dmc.dmc_fw_size;
 330         assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 331
 332         preempt_disable();
 333
 334         for (i = 0; i < fw_size; i++)
 335                 intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
 336                                       payload[i]);
 337
 338         preempt_enable();
 339
 340         for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
 341                 intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
 342                                dev_priv->dmc.mmiodata[i]);
 343         }
 344
 345         dev_priv->dmc.dc_state = 0;
 346
 347         gen9_set_dc_state_debugmask(dev_priv);
 348 }
 349
 350 /*
 351  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
 352  * already sanitized.
 353  */
 354 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
 355                               unsigned int num_entries,
 356                               const struct stepping_info *si,
 357                               u8 package_ver)
 358 {
 359         u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
 360         unsigned int i;
 361
 362         for (i = 0; i < num_entries; i++) {
 363                 if (package_ver > 1 && fw_info[i].dmc_id != 0)
 364                         continue;
 365
 366                 if (fw_info[i].substepping == '*' &&
 367                     si->stepping == fw_info[i].stepping) {
 368                         dmc_offset = fw_info[i].offset;
 369                         break;
 370                 }
 371
 372                 if (si->stepping == fw_info[i].stepping &&
 373                     si->substepping == fw_info[i].substepping) {
 374                         dmc_offset = fw_info[i].offset;
 375                         break;
 376                 }
 377
 378                 if (fw_info[i].stepping == '*' &&
 379                     fw_info[i].substepping == '*') {
 380                         /*
 381                          * In theory we should stop the search as generic
 382                          * entries should always come after the more specific
 383                          * ones, but let's continue to make sure to work even
 384                          * with "broken" firmwares. If we don't find a more
 385                          * specific one, then we use this entry
 386                          */
 387                         dmc_offset = fw_info[i].offset;
 388                 }
 389         }
 390
 391         return dmc_offset;
 392 }
 393
 394 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 395                                const struct intel_dmc_header_base *dmc_header,
 396                                size_t rem_size)
 397 {
 398         unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 399         const u32 *mmioaddr, *mmiodata;
 400         u32 mmio_count, mmio_count_max;
 401         u8 *payload;
 402
 403         BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
 404                      ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 405
 406         /*
 407          * Check if we can access common fields, we will checkc again below
 408          * after we have read the version
 409          */
 410         if (rem_size < sizeof(struct intel_dmc_header_base))
 411                 goto error_truncated;
 412
 413         /* Cope with small differences between v1 and v3 */
 414         if (dmc_header->header_ver == 3) {
 415                 const struct intel_dmc_header_v3 *v3 =
 416                         (const struct intel_dmc_header_v3 *)dmc_header;
 417
 418                 if (rem_size < sizeof(struct intel_dmc_header_v3))
 419                         goto error_truncated;
 420
 421                 mmioaddr = v3->mmioaddr;
 422                 mmiodata = v3->mmiodata;
 423                 mmio_count = v3->mmio_count;
 424                 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 425                 /* header_len is in dwords */
 426                 header_len_bytes = dmc_header->header_len * 4;
 427                 dmc_header_size = sizeof(*v3);
 428         } else if (dmc_header->header_ver == 1) {
 429                 const struct intel_dmc_header_v1 *v1 =
 430                         (const struct intel_dmc_header_v1 *)dmc_header;
 431
 432                 if (rem_size < sizeof(struct intel_dmc_header_v1))
 433                         goto error_truncated;
 434
 435                 mmioaddr = v1->mmioaddr;
 436                 mmiodata = v1->mmiodata;
 437                 mmio_count = v1->mmio_count;
 438                 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 439                 header_len_bytes = dmc_header->header_len;
 440                 dmc_header_size = sizeof(*v1);
 441         } else {
 442                 DRM_ERROR("Unknown DMC fw header version: %u\n",
 443                           dmc_header->header_ver);
 444                 return 0;
 445         }
 446
 447         if (header_len_bytes != dmc_header_size) {
 448                 DRM_ERROR("DMC firmware has wrong dmc header length "
 449                           "(%u bytes)\n", header_len_bytes);
 450                 return 0;
 451         }
 452
 453         /* Cache the dmc header info. */
 454         if (mmio_count > mmio_count_max) {
 455                 DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
 456                 return 0;
 457         }
 458
 459         for (i = 0; i < mmio_count; i++) {
 460                 if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
 461                     mmioaddr[i] > DMC_MMIO_END_RANGE) {
 462                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 463                                   mmioaddr[i]);
 464                         return 0;
 465                 }
 466                 dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
 467                 dmc->mmiodata[i] = mmiodata[i];
 468         }
 469         dmc->mmio_count = mmio_count;
 470
 471         rem_size -= header_len_bytes;
 472
 473         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 474         payload_size = dmc_header->fw_size * 4;
 475         if (rem_size < payload_size)
 476                 goto error_truncated;
 477
 478         if (payload_size > dmc->max_fw_size) {
 479                 DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
 480                 return 0;
 481         }
 482         dmc->dmc_fw_size = dmc_header->fw_size;
 483
 484         dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
 485         if (!dmc->dmc_payload) {
 486                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 487                 return 0;
 488         }
 489
 490         payload = (u8 *)(dmc_header) + header_len_bytes;
 491         memcpy(dmc->dmc_payload, payload, payload_size);
 492
 493         return header_len_bytes + payload_size;
 494
 495 error_truncated:
 496         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 497         return 0;
 498 }
 499
 500 static u32
 501 parse_dmc_fw_package(struct intel_dmc *dmc,
 502                      const struct intel_package_header *package_header,
 503                      const struct stepping_info *si,
 504                      size_t rem_size)
 505 {
 506         u32 package_size = sizeof(struct intel_package_header);
 507         u32 num_entries, max_entries, dmc_offset;
 508         const struct intel_fw_info *fw_info;
 509
 510         if (rem_size < package_size)
 511                 goto error_truncated;
 512
 513         if (package_header->header_ver == 1) {
 514                 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
 515         } else if (package_header->header_ver == 2) {
 516                 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
 517         } else {
 518                 DRM_ERROR("DMC firmware has unknown header version %u\n",
 519                           package_header->header_ver);
 520                 return 0;
 521         }
 522
 523         /*
 524          * We should always have space for max_entries,
 525          * even if not all are used
 526          */
 527         package_size += max_entries * sizeof(struct intel_fw_info);
 528         if (rem_size < package_size)
 529                 goto error_truncated;
 530
 531         if (package_header->header_len * 4 != package_size) {
 532                 DRM_ERROR("DMC firmware has wrong package header length "
 533                           "(%u bytes)\n", package_size);
 534                 return 0;
 535         }
 536
 537         num_entries = package_header->num_entries;
 538         if (WARN_ON(package_header->num_entries > max_entries))
 539                 num_entries = max_entries;
 540
 541         fw_info = (const struct intel_fw_info *)
 542                 ((u8 *)package_header + sizeof(*package_header));
 543         dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
 544                                         package_header->header_ver);
 545         if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
 546                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 547                           si->stepping);
 548                 return 0;
 549         }
 550
 551         /* dmc_offset is in dwords */
 552         return package_size + dmc_offset * 4;
 553
 554 error_truncated:
 555         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 556         return 0;
 557 }
 558
 559 /* Return number of bytes parsed or 0 on error */
 560 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
 561                             struct intel_css_header *css_header,
 562                             size_t rem_size)
 563 {
 564         if (rem_size < sizeof(struct intel_css_header)) {
 565                 DRM_ERROR("Truncated DMC firmware, refusing.\n");
 566                 return 0;
 567         }
 568
 569         if (sizeof(struct intel_css_header) !=
 570             (css_header->header_len * 4)) {
 571                 DRM_ERROR("DMC firmware has wrong CSS header length "
 572                           "(%u bytes)\n",
 573                           (css_header->header_len * 4));
 574                 return 0;
 575         }
 576
 577         if (dmc->required_version &&
 578             css_header->version != dmc->required_version) {
 579                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 580                          " please use v%u.%u\n",
 581                          DMC_VERSION_MAJOR(css_header->version),
 582                          DMC_VERSION_MINOR(css_header->version),
 583                          DMC_VERSION_MAJOR(dmc->required_version),
 584                          DMC_VERSION_MINOR(dmc->required_version));
 585                 return 0;
 586         }
 587
 588         dmc->version = css_header->version;
 589
 590         return sizeof(struct intel_css_header);
 591 }
 592
 593 static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 594                          const struct firmware *fw)
 595 {
 596         struct intel_css_header *css_header;
 597         struct intel_package_header *package_header;
 598         struct intel_dmc_header_base *dmc_header;
 599         struct intel_dmc *dmc = &dev_priv->dmc;
 600         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 601         u32 readcount = 0;
 602         u32 r;
 603
 604         if (!fw)
 605                 return;
 606
 607         /* Extract CSS Header information */
 608         css_header = (struct intel_css_header *)fw->data;
 609         r = parse_dmc_fw_css(dmc, css_header, fw->size);
 610         if (!r)
 611                 return;
 612
 613         readcount += r;
 614
 615         /* Extract Package Header information */
 616         package_header = (struct intel_package_header *)&fw->data[readcount];
 617         r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
 618         if (!r)
 619                 return;
 620
 621         readcount += r;
 622
 623         /* Extract dmc_header information */
 624         dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
 625         parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
 626 }
 627
 628 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
 629 {
 630         drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
 631         dev_priv->dmc.wakeref =
 632                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 633 }
 634
 635 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
 636 {
 637         intel_wakeref_t wakeref __maybe_unused =
 638                 fetch_and_zero(&dev_priv->dmc.wakeref);
 639
 640         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 641 }
 642
 643 static void dmc_load_work_fn(struct work_struct *work)
 644 {
 645         struct drm_i915_private *dev_priv;
 646         struct intel_dmc *dmc;
 647         const struct firmware *fw = NULL;
 648
 649         dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
 650         dmc = &dev_priv->dmc;
 651
 652         request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
 653         parse_dmc_fw(dev_priv, fw);
 654
 655         if (dev_priv->dmc.dmc_payload) {
 656                 intel_dmc_load_program(dev_priv);
 657                 intel_dmc_runtime_pm_put(dev_priv);
 658
 659                 drm_info(&dev_priv->drm,
 660                          "Finished loading DMC firmware %s (v%u.%u)\n",
 661                          dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
 662                          DMC_VERSION_MINOR(dmc->version));
 663         } else {
 664                 drm_notice(&dev_priv->drm,
 665                            "Failed to load DMC firmware %s."
 666                            " Disabling runtime power management.\n",
 667                            dmc->fw_path);
 668                 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
 669                            INTEL_UC_FIRMWARE_URL);
 670         }
 671
 672         release_firmware(fw);
 673 }
 674
 675 /**
 676  * intel_dmc_ucode_init() - initialize the firmware loading.
 677  * @dev_priv: i915 drm device.
 678  *
 679  * This function is called at the time of loading the display driver to read
 680  * firmware from a .bin file and copied into a internal memory.
 681  */
 682 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 683 {
 684         struct intel_dmc *dmc = &dev_priv->dmc;
 685
 686         INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
 687
 688         if (!HAS_DMC(dev_priv))
 689                 return;
 690
 691         /*
 692          * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
 693          * runtime-suspend.
 694          *
 695          * On error, we return with the rpm wakeref held to prevent runtime
 696          * suspend as runtime suspend *requires* a working DMC for whatever
 697          * reason.
 698          */
 699         intel_dmc_runtime_pm_get(dev_priv);
 700
 701         if (IS_ALDERLAKE_S(dev_priv)) {
 702                 dmc->fw_path = ADLS_DMC_PATH;
 703                 dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
 704                 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
 705         } else if (IS_DG1(dev_priv)) {
 706                 dmc->fw_path = DG1_DMC_PATH;
 707                 dmc->required_version = DG1_DMC_VERSION_REQUIRED;
 708                 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
 709         } else if (IS_ROCKETLAKE(dev_priv)) {
 710                 dmc->fw_path = RKL_DMC_PATH;
 711                 dmc->required_version = RKL_DMC_VERSION_REQUIRED;
 712                 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
 713         } else if (DISPLAY_VER(dev_priv) >= 12) {
 714                 dmc->fw_path = TGL_DMC_PATH;
 715                 dmc->required_version = TGL_DMC_VERSION_REQUIRED;
 716                 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
 717         } else if (DISPLAY_VER(dev_priv) == 11) {
 718                 dmc->fw_path = ICL_DMC_PATH;
 719                 dmc->required_version = ICL_DMC_VERSION_REQUIRED;
 720                 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
 721         } else if (IS_CANNONLAKE(dev_priv)) {
 722                 dmc->fw_path = CNL_DMC_PATH;
 723                 dmc->required_version = CNL_DMC_VERSION_REQUIRED;
 724                 dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
 725         } else if (IS_GEMINILAKE(dev_priv)) {
 726                 dmc->fw_path = GLK_DMC_PATH;
 727                 dmc->required_version = GLK_DMC_VERSION_REQUIRED;
 728                 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
 729         } else if (IS_KABYLAKE(dev_priv) ||
 730                    IS_COFFEELAKE(dev_priv) ||
 731                    IS_COMETLAKE(dev_priv)) {
 732                 dmc->fw_path = KBL_DMC_PATH;
 733                 dmc->required_version = KBL_DMC_VERSION_REQUIRED;
 734                 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
 735         } else if (IS_SKYLAKE(dev_priv)) {
 736                 dmc->fw_path = SKL_DMC_PATH;
 737                 dmc->required_version = SKL_DMC_VERSION_REQUIRED;
 738                 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
 739         } else if (IS_BROXTON(dev_priv)) {
 740                 dmc->fw_path = BXT_DMC_PATH;
 741                 dmc->required_version = BXT_DMC_VERSION_REQUIRED;
 742                 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
 743         }
 744
 745         if (dev_priv->params.dmc_firmware_path) {
 746                 if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
 747                         dmc->fw_path = NULL;
 748                         drm_info(&dev_priv->drm,
 749                                  "Disabling DMC firmware and runtime PM\n");
 750                         return;
 751                 }
 752
 753                 dmc->fw_path = dev_priv->params.dmc_firmware_path;
 754                 /* Bypass version check for firmware override. */
 755                 dmc->required_version = 0;
 756         }
 757
 758         if (!dmc->fw_path) {
 759                 drm_dbg_kms(&dev_priv->drm,
 760                             "No known DMC firmware for platform, disabling runtime PM\n");
 761                 return;
 762         }
 763
 764         drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
 765         schedule_work(&dev_priv->dmc.work);
 766 }
 767
 768 /**
 769  * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
 770  * @dev_priv: i915 drm device
 771  *
 772  * Prepare the DMC firmware before entering system suspend. This includes
 773  * flushing pending work items and releasing any resources acquired during
 774  * init.
 775  */
 776 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
 777 {
 778         if (!HAS_DMC(dev_priv))
 779                 return;
 780
 781         flush_work(&dev_priv->dmc.work);
 782
 783         /* Drop the reference held in case DMC isn't loaded. */
 784         if (!dev_priv->dmc.dmc_payload)
 785                 intel_dmc_runtime_pm_put(dev_priv);
 786 }
 787
 788 /**
 789  * intel_dmc_ucode_resume() - init DMC firmware during system resume
 790  * @dev_priv: i915 drm device
 791  *
 792  * Reinitialize the DMC firmware during system resume, reacquiring any
 793  * resources released in intel_dmc_ucode_suspend().
 794  */
 795 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
 796 {
 797         if (!HAS_DMC(dev_priv))
 798                 return;
 799
 800         /*
 801          * Reacquire the reference to keep RPM disabled in case DMC isn't
 802          * loaded.
 803          */
 804         if (!dev_priv->dmc.dmc_payload)
 805                 intel_dmc_runtime_pm_get(dev_priv);
 806 }
 807
 808 /**
 809  * intel_dmc_ucode_fini() - unload the DMC firmware.
 810  * @dev_priv: i915 drm device.
 811  *
 812  * Firmmware unloading includes freeing the internal memory and reset the
 813  * firmware loading status.
 814  */
 815 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
 816 {
 817         if (!HAS_DMC(dev_priv))
 818                 return;
 819
 820         intel_dmc_ucode_suspend(dev_priv);
 821         drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
 822
 823         kfree(dev_priv->dmc.dmc_payload);
 824 }