2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_rect.h>
43 #include <drm/drm_vblank.h>
44 #include <drm/i915_mei_hdcp_interface.h>
45 #include <media/cec-notifier.h>
51 struct __intel_global_objs_state;
54 * Display related stuff
57 /* these are outputs from the chip - integrated only
58 external chips are via DVO or SDVO output */
59 enum intel_output_type {
60 INTEL_OUTPUT_UNUSED = 0,
61 INTEL_OUTPUT_ANALOG = 1,
63 INTEL_OUTPUT_SDVO = 3,
64 INTEL_OUTPUT_LVDS = 4,
65 INTEL_OUTPUT_TVOUT = 5,
66 INTEL_OUTPUT_HDMI = 6,
70 INTEL_OUTPUT_DDI = 10,
71 INTEL_OUTPUT_DP_MST = 11,
74 enum hdmi_force_audio {
75 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
76 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
77 HDMI_AUDIO_AUTO, /* trust EDID */
78 HDMI_AUDIO_ON, /* force turn on HDMI audio */
81 /* "Broadcast RGB" property */
82 enum intel_broadcast_rgb {
83 INTEL_BROADCAST_RGB_AUTO,
84 INTEL_BROADCAST_RGB_FULL,
85 INTEL_BROADCAST_RGB_LIMITED,
88 struct intel_fb_view {
90 * The remap information used in the remapped and rotated views to
91 * create the DMA scatter-gather list for each FB color plane. This sg
92 * list is created along with the view type (gtt.type) specific
93 * i915_vma object and contains the list of FB object pages (reordered
94 * in the rotated view) that are visible in the view.
95 * In the normal view the FB object's backing store sg list is used
96 * directly and hence the remap information here is not used.
98 struct i915_ggtt_view gtt;
101 * The GTT view (gtt.type) specific information for each FB color
102 * plane. In the normal GTT view all formats (up to 4 color planes),
103 * in the rotated and remapped GTT view all no-CCS formats (up to 2
104 * color planes) are supported.
106 * TODO: add support for CCS formats in the remapped GTT view.
108 * The view information shared by all FB color planes in the FB,
109 * like dst x/y and src/dst width, is stored separately in
112 struct i915_color_plane_view {
117 * bytes for 0/180 degree rotation
118 * pixels for 90/270 degree rotation
124 struct intel_framebuffer {
125 struct drm_framebuffer base;
126 struct intel_frontbuffer *frontbuffer;
128 /* Params to remap the FB pages and program the plane registers in each view. */
129 struct intel_fb_view normal_view;
130 struct intel_fb_view rotated_view;
131 struct intel_fb_view remapped_view;
135 struct drm_fb_helper helper;
136 struct intel_framebuffer *fb;
137 struct i915_vma *vma;
138 unsigned long vma_flags;
139 async_cookie_t cookie;
142 /* Whether or not fbdev hpd processing is temporarily suspended */
143 bool hpd_suspended : 1;
144 /* Set when a hotplug was received while HPD processing was
147 bool hpd_waiting : 1;
149 /* Protects hpd_suspended */
150 struct mutex hpd_lock;
153 enum intel_hotplug_state {
154 INTEL_HOTPLUG_UNCHANGED,
155 INTEL_HOTPLUG_CHANGED,
159 struct intel_encoder {
160 struct drm_encoder base;
162 enum intel_output_type type;
166 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
167 struct intel_connector *connector);
168 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
169 struct intel_crtc_state *,
170 struct drm_connector_state *);
171 int (*compute_config)(struct intel_encoder *,
172 struct intel_crtc_state *,
173 struct drm_connector_state *);
174 int (*compute_config_late)(struct intel_encoder *,
175 struct intel_crtc_state *,
176 struct drm_connector_state *);
177 void (*update_prepare)(struct intel_atomic_state *,
178 struct intel_encoder *,
179 struct intel_crtc *);
180 void (*pre_pll_enable)(struct intel_atomic_state *,
181 struct intel_encoder *,
182 const struct intel_crtc_state *,
183 const struct drm_connector_state *);
184 void (*pre_enable)(struct intel_atomic_state *,
185 struct intel_encoder *,
186 const struct intel_crtc_state *,
187 const struct drm_connector_state *);
188 void (*enable)(struct intel_atomic_state *,
189 struct intel_encoder *,
190 const struct intel_crtc_state *,
191 const struct drm_connector_state *);
192 void (*update_complete)(struct intel_atomic_state *,
193 struct intel_encoder *,
194 struct intel_crtc *);
195 void (*disable)(struct intel_atomic_state *,
196 struct intel_encoder *,
197 const struct intel_crtc_state *,
198 const struct drm_connector_state *);
199 void (*post_disable)(struct intel_atomic_state *,
200 struct intel_encoder *,
201 const struct intel_crtc_state *,
202 const struct drm_connector_state *);
203 void (*post_pll_disable)(struct intel_atomic_state *,
204 struct intel_encoder *,
205 const struct intel_crtc_state *,
206 const struct drm_connector_state *);
207 void (*update_pipe)(struct intel_atomic_state *,
208 struct intel_encoder *,
209 const struct intel_crtc_state *,
210 const struct drm_connector_state *);
211 /* Read out the current hw state of this connector, returning true if
212 * the encoder is active. If the encoder is enabled it also set the pipe
213 * it is connected to in the pipe parameter. */
214 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
215 /* Reconstructs the equivalent mode flags for the current hardware
216 * state. This must be called _after_ display->get_pipe_config has
217 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
218 * be set correctly before calling this function. */
219 void (*get_config)(struct intel_encoder *,
220 struct intel_crtc_state *pipe_config);
223 * Optional hook called during init/resume to sync any state
224 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
226 void (*sync_state)(struct intel_encoder *encoder,
227 const struct intel_crtc_state *crtc_state);
230 * Optional hook, returning true if this encoder allows a fastset
231 * during the initial commit, false otherwise.
233 bool (*initial_fastset_check)(struct intel_encoder *encoder,
234 struct intel_crtc_state *crtc_state);
237 * Acquires the power domains needed for an active encoder during
238 * hardware state readout.
240 void (*get_power_domains)(struct intel_encoder *encoder,
241 struct intel_crtc_state *crtc_state);
243 * Called during system suspend after all pending requests for the
244 * encoder are flushed (for example for DP AUX transactions) and
245 * device interrupts are disabled.
247 void (*suspend)(struct intel_encoder *);
249 * Called during system reboot/shutdown after all the
250 * encoders have been disabled and suspended.
252 void (*shutdown)(struct intel_encoder *encoder);
254 * Enable/disable the clock to the port.
256 void (*enable_clock)(struct intel_encoder *encoder,
257 const struct intel_crtc_state *crtc_state);
258 void (*disable_clock)(struct intel_encoder *encoder);
260 * Returns whether the port clock is enabled or not.
262 bool (*is_clock_enabled)(struct intel_encoder *encoder);
263 enum hpd_pin hpd_pin;
264 enum intel_display_power_domain power_domain;
265 /* for communication with audio component; protected by av_mutex */
266 const struct drm_connector *audio_connector;
268 /* VBT information for this encoder (may be NULL for older platforms) */
269 const struct intel_bios_encoder_data *devdata;
272 struct intel_panel_bl_funcs {
273 /* Connector and platform specific backlight functions */
274 int (*setup)(struct intel_connector *connector, enum pipe pipe);
275 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
276 void (*set)(const struct drm_connector_state *conn_state, u32 level);
277 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
278 void (*enable)(const struct intel_crtc_state *crtc_state,
279 const struct drm_connector_state *conn_state, u32 level);
280 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
284 struct drm_display_mode *fixed_mode;
285 struct drm_display_mode *downclock_mode;
294 bool combination_mode; /* gen 2/4 only */
296 bool alternate_pwm_increment; /* lpt+ */
302 bool util_pin_active_low; /* bxt+ */
303 u8 controller; /* bxt+ only */
304 struct pwm_device *pwm;
305 struct pwm_state pwm_state;
317 struct backlight_device *device;
319 const struct intel_panel_bl_funcs *funcs;
320 const struct intel_panel_bl_funcs *pwm_funcs;
321 void (*power)(struct intel_connector *, bool enable);
325 struct intel_digital_port;
327 enum check_link_response {
328 HDCP_LINK_PROTECTED = 0,
329 HDCP_TOPOLOGY_CHANGE,
330 HDCP_LINK_INTEGRITY_FAILURE,
335 * This structure serves as a translation layer between the generic HDCP code
336 * and the bus-specific code. What that means is that HDCP over HDMI differs
337 * from HDCP over DP, so to account for these differences, we need to
338 * communicate with the receiver through this shim.
340 * For completeness, the 2 buses differ in the following ways:
342 * HDCP registers on the receiver are set via DP AUX for DP, and
343 * they are set via DDC for HDMI.
344 * - Receiver register offsets
345 * The offsets of the registers are different for DP vs. HDMI
346 * - Receiver register masks/offsets
347 * For instance, the ready bit for the KSV fifo is in a different
348 * place on DP vs HDMI
349 * - Receiver register names
350 * Seriously. In the DP spec, the 16-bit register containing
351 * downstream information is called BINFO, on HDMI it's called
352 * BSTATUS. To confuse matters further, DP has a BSTATUS register
353 * with a completely different definition.
355 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
356 * be read 3 keys at a time
358 * Since Aksv is hidden in hardware, there's different procedures
359 * to send it over DP AUX vs DDC
361 struct intel_hdcp_shim {
362 /* Outputs the transmitter's An and Aksv values to the receiver. */
363 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
365 /* Reads the receiver's key selection vector */
366 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
369 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
370 * definitions are the same in the respective specs, but the names are
371 * different. Call it BSTATUS since that's the name the HDMI spec
372 * uses and it was there first.
374 int (*read_bstatus)(struct intel_digital_port *dig_port,
377 /* Determines whether a repeater is present downstream */
378 int (*repeater_present)(struct intel_digital_port *dig_port,
379 bool *repeater_present);
381 /* Reads the receiver's Ri' value */
382 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
384 /* Determines if the receiver's KSV FIFO is ready for consumption */
385 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
388 /* Reads the ksv fifo for num_downstream devices */
389 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
390 int num_downstream, u8 *ksv_fifo);
392 /* Reads a 32-bit part of V' from the receiver */
393 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
396 /* Enables HDCP signalling on the port */
397 int (*toggle_signalling)(struct intel_digital_port *dig_port,
398 enum transcoder cpu_transcoder,
401 /* Enable/Disable stream encryption on DP MST Transport Link */
402 int (*stream_encryption)(struct intel_connector *connector,
405 /* Ensures the link is still protected */
406 bool (*check_link)(struct intel_digital_port *dig_port,
407 struct intel_connector *connector);
409 /* Detects panel's hdcp capability. This is optional for HDMI. */
410 int (*hdcp_capable)(struct intel_digital_port *dig_port,
413 /* HDCP adaptation(DP/HDMI) required on the port */
414 enum hdcp_wired_protocol protocol;
416 /* Detects whether sink is HDCP2.2 capable */
417 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
420 /* Detects whether a HDCP 1.4 sink connected in MST topology */
421 int (*streams_type1_capable)(struct intel_connector *connector,
424 /* Write HDCP2.2 messages */
425 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
426 void *buf, size_t size);
428 /* Read HDCP2.2 messages */
429 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
430 u8 msg_id, void *buf, size_t size);
433 * Implementation of DP HDCP2.2 Errata for the communication of stream
434 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
435 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
437 int (*config_stream_type)(struct intel_digital_port *dig_port,
438 bool is_repeater, u8 type);
440 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
441 int (*stream_2_2_encryption)(struct intel_connector *connector,
444 /* HDCP2.2 Link Integrity Check */
445 int (*check_2_2_link)(struct intel_digital_port *dig_port,
446 struct intel_connector *connector);
450 const struct intel_hdcp_shim *shim;
451 /* Mutex for hdcp state of the connector */
454 struct delayed_work check_work;
455 struct work_struct prop_work;
457 /* HDCP1.4 Encryption status */
460 /* HDCP2.2 related definitions */
461 /* Flag indicates whether this connector supports HDCP2.2 or not. */
462 bool hdcp2_supported;
464 /* HDCP2.2 Encryption status */
465 bool hdcp2_encrypted;
468 * Content Stream Type defined by content owner. TYPE0(0x0) content can
469 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
470 * content can flow only through a link protected by HDCP2.2.
478 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
479 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
480 * When it rolls over re-auth has to be triggered.
485 * Count of RepeaterAuth_Stream_Manage msg propagated.
486 * Initialized to 0 on AKE_INIT. Incremented after every successful
487 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
488 * over re-Auth has to be triggered.
493 * Work queue to signal the CP_IRQ. Used for the waiters to read the
494 * available information from HDCP DP sink.
496 wait_queue_head_t cp_irq_queue;
497 atomic_t cp_irq_count;
498 int cp_irq_count_cached;
501 * HDCP register access for gen12+ need the transcoder associated.
502 * Transcoder attached to the connector could be changed at modeset.
503 * Hence caching the transcoder here.
505 enum transcoder cpu_transcoder;
506 /* Only used for DP MST stream encryption */
507 enum transcoder stream_transcoder;
510 struct intel_connector {
511 struct drm_connector base;
513 * The fixed encoder this connector is connected to.
515 struct intel_encoder *encoder;
517 /* ACPI device id for ACPI and driver cooperation */
520 /* Reads out the current hw, returning true if the connector is enabled
521 * and active (i.e. dpms ON state). */
522 bool (*get_hw_state)(struct intel_connector *);
524 /* Panel info for eDP and LVDS */
525 struct intel_panel panel;
527 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
529 struct edid *detect_edid;
531 /* Number of times hotplug detection was tried after an HPD interrupt */
534 /* since POLL and HPD connectors may use the same HPD line keep the native
535 state of connector->polled in case hotplug storm detection changes it */
538 struct drm_dp_mst_port *port;
540 struct intel_dp *mst_port;
542 /* Work struct to schedule a uevent on link train failure */
543 struct work_struct modeset_retry_work;
545 struct intel_hdcp hdcp;
548 struct intel_digital_connector_state {
549 struct drm_connector_state base;
551 enum hdmi_force_audio force_audio;
555 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
569 struct intel_atomic_state {
570 struct drm_atomic_state base;
572 intel_wakeref_t wakeref;
574 struct __intel_global_objs_state *global_objs;
577 bool dpll_set, modeset;
579 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
582 * Current watermarks can't be trusted during hardware readout, so
583 * don't bother calculating intermediate watermarks.
585 bool skip_intermediate_wm;
587 bool rps_interactive;
589 struct i915_sw_fence commit_ready;
591 struct llist_node freed;
594 struct intel_plane_state {
595 struct drm_plane_state uapi;
598 * actual hardware state, the state we program to the hardware.
599 * The following members are used to verify the hardware state:
600 * During initial hw readout, they need to be copied from uapi.
603 struct drm_crtc *crtc;
604 struct drm_framebuffer *fb;
607 u16 pixel_blend_mode;
608 unsigned int rotation;
609 enum drm_color_encoding color_encoding;
610 enum drm_color_range color_range;
611 enum drm_scaling_filter scaling_filter;
614 struct i915_vma *vma;
616 #define PLANE_HAS_FENCE BIT(0)
618 struct intel_fb_view view;
620 /* plane control register */
623 /* plane color control register */
626 /* chroma upsampler control register */
631 * = -1 : not using a scaler
632 * >= 0 : using a scalers
634 * plane requiring a scaler:
635 * - During check_plane, its bit is set in
636 * crtc_state->scaler_state.scaler_users by calling helper function
637 * update_scaler_plane.
638 * - scaler_id indicates the scaler it got assigned.
640 * plane doesn't require a scaler:
641 * - this can happen when scaling is no more required or plane simply
643 * - During check_plane, corresponding bit is reset in
644 * crtc_state->scaler_state.scaler_users by calling helper function
645 * update_scaler_plane.
650 * planar_linked_plane:
652 * ICL planar formats require 2 planes that are updated as pairs.
653 * This member is used to make sure the other plane is also updated
654 * when required, and for update_slave() to find the correct
655 * plane_state to pass as argument.
657 struct intel_plane *planar_linked_plane;
661 * If set don't update use the linked plane's state for updating
662 * this plane during atomic commit with the update_slave() callback.
664 * It's also used by the watermark code to ignore wm calculations on
665 * this plane. They're calculated by the linked plane's wm code.
669 struct drm_intel_sprite_colorkey ckey;
671 struct drm_rect psr2_sel_fetch_area;
673 /* Clear Color Value */
677 struct intel_initial_plane_config {
678 struct intel_framebuffer *fb;
679 struct i915_vma *vma;
686 struct intel_scaler {
691 struct intel_crtc_scaler_state {
692 #define SKL_NUM_SCALERS 2
693 struct intel_scaler scalers[SKL_NUM_SCALERS];
696 * scaler_users: keeps track of users requesting scalers on this crtc.
698 * If a bit is set, a user is using a scaler.
699 * Here user can be a plane or crtc as defined below:
700 * bits 0-30 - plane (bit position is index from drm_plane_index)
703 * Instead of creating a new index to cover planes and crtc, using
704 * existing drm_plane_index for planes which is well less than 31
705 * planes and bit 31 for crtc. This should be fine to cover all
708 * intel_atomic_setup_scalers will setup available scalers to users
709 * requesting scalers. It will gracefully fail if request exceeds
712 #define SKL_CRTC_INDEX 31
713 unsigned scaler_users;
715 /* scaler used by crtc for panel fitting purpose */
719 /* {crtc,crtc_state}->mode_flags */
720 /* Flag to get scanline using frame time stamps */
721 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
722 /* Flag to use the scanline counter instead of the pixel counter */
723 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
725 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
726 * is operating in command mode.
727 * Flag to use TE from DSI0 instead of VBI in command mode
729 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
730 /* Flag to use TE from DSI1 instead of VBI in command mode */
731 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
732 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
733 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
734 /* Do tricks to make vblank timestamps sane with VRR? */
735 #define I915_MODE_FLAG_VRR (1<<6)
737 struct intel_wm_level {
745 struct intel_pipe_wm {
746 struct intel_wm_level wm[5];
749 bool sprites_enabled;
753 struct skl_wm_level {
762 struct skl_plane_wm {
763 struct skl_wm_level wm[8];
764 struct skl_wm_level uv_wm[8];
765 struct skl_wm_level trans_wm;
767 struct skl_wm_level wm0;
768 struct skl_wm_level trans_wm;
774 struct skl_plane_wm planes[I915_MAX_PLANES];
781 VLV_WM_LEVEL_DDR_DVFS,
785 struct vlv_wm_state {
786 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
787 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
792 struct vlv_fifo_state {
793 u16 plane[I915_MAX_PLANES];
803 struct g4x_wm_state {
804 struct g4x_pipe_wm wm;
806 struct g4x_sr_wm hpll;
812 struct intel_crtc_wm_state {
816 * The "raw" watermark values produced by the formula
817 * given the plane's current state. They do not consider
818 * how much FIFO is actually allocated for each plane.
821 * The "optimal" watermark values given the current
822 * state of the planes and the amount of FIFO
823 * allocated to each, ignoring any previous state
827 * The "intermediate" watermark values when transitioning
828 * between the old and new "optimal" values. Used when
829 * the watermark registers are single buffered and hence
830 * their state changes asynchronously with regards to the
831 * actual plane registers. These are essentially the
832 * worst case combination of the old and new "optimal"
833 * watermarks, which are therefore safe to use when the
834 * plane is in either its old or new state.
837 struct intel_pipe_wm intermediate;
838 struct intel_pipe_wm optimal;
842 struct skl_pipe_wm raw;
843 /* gen9+ only needs 1-step wm programming */
844 struct skl_pipe_wm optimal;
845 struct skl_ddb_entry ddb;
846 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
847 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
851 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
852 struct vlv_wm_state intermediate; /* inverted */
853 struct vlv_wm_state optimal; /* inverted */
854 struct vlv_fifo_state fifo_state;
858 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
859 struct g4x_wm_state intermediate;
860 struct g4x_wm_state optimal;
865 * Platforms with two-step watermark programming will need to
866 * update watermark programming post-vblank to switch from the
867 * safe intermediate watermarks to the optimal final
870 bool need_postvbl_update;
873 enum intel_output_format {
874 INTEL_OUTPUT_FORMAT_RGB,
875 INTEL_OUTPUT_FORMAT_YCBCR420,
876 INTEL_OUTPUT_FORMAT_YCBCR444,
879 struct intel_crtc_state {
881 * uapi (drm) state. This is the software state shown to userspace.
882 * In particular, the following members are used for bookkeeping:
890 struct drm_crtc_state uapi;
893 * actual hardware state, the state we program to the hardware.
894 * The following members are used to verify the hardware state:
897 * - mode / pipe_mode / adjusted_mode
898 * - color property blobs.
900 * During initial hw readout, they need to be copied to uapi.
902 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
903 * Use the pipe_mode for calculations like watermarks, pipe
904 * scaler, and bandwidth.
906 * Use adjusted_mode for things that need to know the full
907 * mode on the transcoder, which spans all pipes.
911 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
912 struct drm_display_mode mode, pipe_mode, adjusted_mode;
913 enum drm_scaling_filter scaling_filter;
917 * quirks - bitfield with hw state readout quirks
919 * For various reasons the hw state readout code might not be able to
920 * completely faithfully read out the current state. These cases are
921 * tracked with quirk flags so that fastboot and state checker can act
924 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
925 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
926 unsigned long quirks;
928 unsigned fb_bits; /* framebuffers to flip */
929 bool update_pipe; /* can a fast modeset be performed? */
931 bool update_wm_pre, update_wm_post; /* watermarks are updated */
932 bool fifo_changed; /* FIFO split is changed */
934 bool inherited; /* state inherited from BIOS? */
936 /* Pipe source size (ie. panel fitter input size)
937 * All planes will be positioned inside this space,
938 * and get clipped at the edges. */
939 int pipe_src_w, pipe_src_h;
942 * Pipe pixel rate, adjusted for
943 * panel fitter/pipe scaler downscaling.
945 unsigned int pixel_rate;
947 /* Whether to set up the PCH/FDI. Note that we never allow sharing
948 * between pch encoders and cpu encoders. */
949 bool has_pch_encoder;
951 /* Are we sending infoframes on the attached port */
954 /* CPU Transcoder for the pipe. Currently this can only differ from the
955 * pipe on Haswell and later (where we have a special eDP transcoder)
956 * and Broxton (where we have special DSI transcoders). */
957 enum transcoder cpu_transcoder;
960 * Use reduced/limited/broadcast rbg range, compressing from the full
961 * range fed into the crtcs.
963 bool limited_color_range;
965 /* Bitmask of encoder types (enum intel_output_type)
966 * driven by the pipe.
968 unsigned int output_types;
970 /* Whether we should send NULL infoframes. Required for audio. */
973 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
974 * has_dp_encoder is set. */
978 * Enable dithering, used when the selected pipe bpp doesn't match the
984 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
985 * compliance video pattern tests.
986 * Disable dither only if it is a compliance test request for
989 bool dither_force_disable;
991 /* Controls for the clock computation, to override various stages. */
994 /* SDVO TV has a bunch of special case. To make multifunction encoders
995 * work correctly, we need to track this at runtime.*/
999 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1000 * required. This is set in the 2nd loop of calling encoder's
1001 * ->compute_config if the first pick doesn't work out.
1003 bool bw_constrained;
1005 /* Settings for the intel dpll used on pretty much everything but
1009 /* Selected dpll when shared or NULL. */
1010 struct intel_shared_dpll *shared_dpll;
1012 /* Actual register state of the dpll, for shared dpll cross-checking. */
1013 struct intel_dpll_hw_state dpll_hw_state;
1016 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1017 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1019 struct icl_port_dpll {
1020 struct intel_shared_dpll *pll;
1021 struct intel_dpll_hw_state hw_state;
1022 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1024 /* DSI PLL registers */
1030 struct intel_link_m_n dp_m_n;
1032 /* m2_n2 for eDP downclock */
1033 struct intel_link_m_n dp_m2_n2;
1038 bool enable_psr2_sel_fetch;
1042 * Frequence the dpll for the port should run at. Differs from the
1043 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1044 * already multiplied by pixel_multiplier.
1048 /* Used by SDVO (and if we ever fix it, HDMI). */
1049 unsigned pixel_multiplier;
1051 /* I915_MODE_FLAG_* */
1057 * Used by platforms having DP/HDMI PHY with programmable lane
1058 * latency optimization.
1060 u8 lane_lat_optim_mask;
1062 /* minimum acceptable voltage level */
1063 u8 min_voltage_level;
1065 /* Panel fitter controls for gen2-gen4 + VLV */
1069 u32 lvds_border_bits;
1072 /* Panel fitter placement and size for Ironlake+ */
1074 struct drm_rect dst;
1079 /* FDI configuration, only valid if has_pch_encoder is set. */
1081 struct intel_link_m_n fdi_m_n;
1093 struct intel_crtc_scaler_state scaler_state;
1095 /* w/a for waiting 2 vblanks during crtc enable */
1096 enum pipe hsw_workaround_pipe;
1098 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1101 struct intel_crtc_wm_state wm;
1103 int min_cdclk[I915_MAX_PLANES];
1105 u32 data_rate[I915_MAX_PLANES];
1107 /* FIXME unify with data_rate[] */
1108 u64 plane_data_rate[I915_MAX_PLANES];
1109 u64 uv_plane_data_rate[I915_MAX_PLANES];
1111 /* Gamma mode programmed on the pipe */
1115 /* CSC mode programmed on the pipe */
1122 /* bitmask of logically enabled planes (enum plane_id) */
1125 /* bitmask of actually visible planes (enum plane_id) */
1130 /* bitmask of planes that will be updated during the commit */
1136 union hdmi_infoframe avi;
1137 union hdmi_infoframe spd;
1138 union hdmi_infoframe hdmi;
1139 union hdmi_infoframe drm;
1140 struct drm_dp_vsc_sdp vsc;
1143 /* HDMI scrambling status */
1144 bool hdmi_scrambling;
1146 /* HDMI High TMDS char rate ratio */
1147 bool hdmi_high_tmds_clock_ratio;
1149 /* Output format RGB/YCBCR etc */
1150 enum intel_output_format output_format;
1152 /* enable pipe gamma? */
1155 /* enable pipe csc? */
1158 /* enable pipe big joiner? */
1161 /* big joiner slave crtc? */
1162 bool bigjoiner_slave;
1164 /* linked crtc for bigjoiner, either slave or master */
1165 struct intel_crtc *bigjoiner_linked_crtc;
1167 /* Display Stream compression state */
1169 bool compression_enable;
1173 struct drm_dsc_config config;
1176 /* HSW+ linetime watermarks */
1180 /* Forward Error correction State */
1183 /* Pointer to master transcoder in case of tiled displays */
1184 enum transcoder master_transcoder;
1186 /* Bitmask to indicate slaves attached */
1187 u8 sync_mode_slaves_mask;
1189 /* Only valid on TGL+ */
1190 enum transcoder mst_master_transcoder;
1192 /* For DSB related info */
1193 struct intel_dsb *dsb;
1195 u32 psr2_man_track_ctl;
1197 /* Variable Refresh Rate state */
1201 u16 flipline, vmin, vmax;
1204 /* Stream Splitter for eDP MSO */
1212 enum intel_pipe_crc_source {
1213 INTEL_PIPE_CRC_SOURCE_NONE,
1214 INTEL_PIPE_CRC_SOURCE_PLANE1,
1215 INTEL_PIPE_CRC_SOURCE_PLANE2,
1216 INTEL_PIPE_CRC_SOURCE_PLANE3,
1217 INTEL_PIPE_CRC_SOURCE_PLANE4,
1218 INTEL_PIPE_CRC_SOURCE_PLANE5,
1219 INTEL_PIPE_CRC_SOURCE_PLANE6,
1220 INTEL_PIPE_CRC_SOURCE_PLANE7,
1221 INTEL_PIPE_CRC_SOURCE_PIPE,
1222 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1223 INTEL_PIPE_CRC_SOURCE_TV,
1224 INTEL_PIPE_CRC_SOURCE_DP_B,
1225 INTEL_PIPE_CRC_SOURCE_DP_C,
1226 INTEL_PIPE_CRC_SOURCE_DP_D,
1227 INTEL_PIPE_CRC_SOURCE_AUTO,
1228 INTEL_PIPE_CRC_SOURCE_MAX,
1231 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1232 struct intel_pipe_crc {
1235 enum intel_pipe_crc_source source;
1239 struct drm_crtc base;
1242 * Whether the crtc and the connected output pipeline is active. Implies
1243 * that crtc->enabled is set, i.e. the current mode configuration has
1244 * some outputs connected to this crtc.
1249 /* I915_MODE_FLAG_* */
1252 u16 vmax_vblank_start;
1254 struct intel_display_power_domain_set enabled_power_domains;
1255 struct intel_overlay *overlay;
1257 struct intel_crtc_state *config;
1259 /* Access to these should be protected by dev_priv->irq_lock. */
1260 bool cpu_fifo_underrun_disabled;
1261 bool pch_fifo_underrun_disabled;
1263 /* per-pipe watermark state */
1265 /* watermarks currently being used */
1267 struct intel_pipe_wm ilk;
1268 struct vlv_wm_state vlv;
1269 struct g4x_wm_state g4x;
1273 int scanline_offset;
1276 unsigned start_vbl_count;
1277 ktime_t start_vbl_time;
1278 int min_vbl, max_vbl;
1280 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1286 unsigned int times[17]; /* [1us, 16ms] */
1291 /* scalers available on this crtc */
1294 #ifdef CONFIG_DEBUG_FS
1295 struct intel_pipe_crc pipe_crc;
1299 struct intel_plane {
1300 struct drm_plane base;
1301 enum i9xx_plane_id i9xx_plane;
1306 bool need_async_flip_disable_wa;
1307 u32 frontbuffer_bit;
1310 u32 base, cntl, size;
1314 * NOTE: Do not place new plane state fields here (e.g., when adding
1315 * new plane properties). New runtime state should now be placed in
1316 * the intel_plane_state structure and accessed via plane_state.
1319 int (*min_width)(const struct drm_framebuffer *fb,
1321 unsigned int rotation);
1322 int (*max_width)(const struct drm_framebuffer *fb,
1324 unsigned int rotation);
1325 int (*max_height)(const struct drm_framebuffer *fb,
1327 unsigned int rotation);
1328 unsigned int (*max_stride)(struct intel_plane *plane,
1329 u32 pixel_format, u64 modifier,
1330 unsigned int rotation);
1331 void (*update_plane)(struct intel_plane *plane,
1332 const struct intel_crtc_state *crtc_state,
1333 const struct intel_plane_state *plane_state);
1334 void (*disable_plane)(struct intel_plane *plane,
1335 const struct intel_crtc_state *crtc_state);
1336 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1337 int (*check_plane)(struct intel_crtc_state *crtc_state,
1338 struct intel_plane_state *plane_state);
1339 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1340 const struct intel_plane_state *plane_state);
1341 void (*async_flip)(struct intel_plane *plane,
1342 const struct intel_crtc_state *crtc_state,
1343 const struct intel_plane_state *plane_state,
1345 void (*enable_flip_done)(struct intel_plane *plane);
1346 void (*disable_flip_done)(struct intel_plane *plane);
1349 struct intel_watermark_params {
1357 struct cxsr_latency {
1358 bool is_desktop : 1;
1363 u16 display_hpll_disable;
1365 u16 cursor_hpll_disable;
1368 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1369 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1370 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1371 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1372 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1373 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1374 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1375 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1376 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1379 i915_reg_t hdmi_reg;
1382 enum drm_dp_dual_mode_type type;
1387 struct intel_connector *attached_connector;
1388 struct cec_notifier *cec_notifier;
1391 struct intel_dp_mst_encoder;
1393 * enum link_m_n_set:
1394 * When platform provides two set of M_N registers for dp, we can
1395 * program them and switch between them incase of DRRS.
1396 * But When only one such register is provided, we have to program the
1397 * required divider value on that registers itself based on the DRRS state.
1399 * M1_N1 : Program dp_m_n on M1_N1 registers
1400 * dp_m2_n2 on M2_N2 registers (If supported)
1402 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1403 * M2_N2 registers are not supported
1407 /* Sets the m1_n1 and m2_n2 */
1412 struct intel_dp_compliance_data {
1415 u16 hdisplay, vdisplay;
1417 struct drm_dp_phy_test_params phytest;
1420 struct intel_dp_compliance {
1421 unsigned long test_type;
1422 struct intel_dp_compliance_data test_data;
1428 struct intel_dp_pcon_frl {
1430 int trained_rate_gbps;
1434 int panel_power_up_delay;
1435 int panel_power_down_delay;
1436 int panel_power_cycle_delay;
1437 int backlight_on_delay;
1438 int backlight_off_delay;
1439 struct delayed_work panel_vdd_work;
1440 bool want_panel_vdd;
1441 unsigned long last_power_on;
1442 unsigned long last_backlight_off;
1443 ktime_t panel_power_off_time;
1444 intel_wakeref_t vdd_wakeref;
1447 * Pipe whose power sequencer is currently locked into
1448 * this port. Only relevant on VLV/CHV.
1452 * Pipe currently driving the port. Used for preventing
1453 * the use of the PPS for any pipe currentrly driving
1454 * external DP as that will mess things up on VLV.
1456 enum pipe active_pipe;
1458 * Set if the sequencer may be reset due to a power transition,
1459 * requiring a reinitialization. Only relevant on BXT.
1462 struct edp_power_seq pps_delays;
1466 /* Mutex for PSR state of the transcoder */
1469 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1470 #define I915_PSR_DEBUG_DEFAULT 0x00
1471 #define I915_PSR_DEBUG_DISABLE 0x01
1472 #define I915_PSR_DEBUG_ENABLE 0x02
1473 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1474 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1475 #define I915_PSR_DEBUG_IRQ 0x10
1479 bool source_support;
1482 enum transcoder transcoder;
1484 struct work_struct work;
1485 unsigned int busy_frontbuffer_bits;
1486 bool sink_psr2_support;
1488 bool colorimetry_support;
1490 bool psr2_sel_fetch_enabled;
1491 u8 sink_sync_latency;
1492 ktime_t last_entry_attempt;
1494 bool sink_not_reliable;
1496 u16 su_x_granularity;
1498 u32 dc3co_exit_delay;
1499 struct delayed_work dc3co_work;
1500 struct drm_dp_vsc_sdp vsc;
1504 i915_reg_t output_reg;
1512 bool reset_link_params;
1513 bool use_max_params;
1514 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1515 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1516 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1517 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1518 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1519 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1520 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1522 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1524 int num_source_rates;
1525 const int *source_rates;
1526 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1528 int sink_rates[DP_MAX_SUPPORTED_RATES];
1529 bool use_rate_select;
1530 /* intersection of source and sink rates */
1531 int num_common_rates;
1532 int common_rates[DP_MAX_SUPPORTED_RATES];
1533 /* Max lane count for the current link */
1534 int max_link_lane_count;
1535 /* Max rate for the current link */
1538 int mso_pixel_overlap;
1539 /* sink or branch descriptor */
1540 struct drm_dp_desc desc;
1541 struct drm_dp_aux aux;
1542 u32 aux_busy_last_status;
1545 struct intel_pps pps;
1547 bool can_mst; /* this port supports mst */
1549 int active_mst_links;
1551 /* connector directly attached - won't be use for modeset in mst world */
1552 struct intel_connector *attached_connector;
1554 /* mst connector list */
1555 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1556 struct drm_dp_mst_topology_mgr mst_mgr;
1558 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1560 * This function returns the value we have to program the AUX_CTL
1561 * register with to kick off an AUX transaction.
1563 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1564 u32 aux_clock_divider);
1566 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1567 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1569 /* This is called before a link training is starterd */
1570 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1571 const struct intel_crtc_state *crtc_state);
1572 void (*set_link_train)(struct intel_dp *intel_dp,
1573 const struct intel_crtc_state *crtc_state,
1575 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1576 const struct intel_crtc_state *crtc_state);
1577 void (*set_signal_levels)(struct intel_dp *intel_dp,
1578 const struct intel_crtc_state *crtc_state);
1580 u8 (*preemph_max)(struct intel_dp *intel_dp);
1581 u8 (*voltage_max)(struct intel_dp *intel_dp,
1582 const struct intel_crtc_state *crtc_state);
1584 /* Displayport compliance testing */
1585 struct intel_dp_compliance compliance;
1587 /* Downstream facing port caps */
1589 int min_tmds_clock, max_tmds_clock;
1591 int pcon_max_frl_bw;
1593 bool ycbcr_444_to_420;
1597 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1598 struct pm_qos_request pm_qos;
1600 /* Display stream compression testing */
1606 struct intel_dp_pcon_frl frl;
1608 struct intel_psr psr;
1611 enum lspcon_vendor {
1613 LSPCON_VENDOR_PARADE
1616 struct intel_lspcon {
1619 enum drm_lspcon_mode mode;
1620 enum lspcon_vendor vendor;
1623 struct intel_digital_port {
1624 struct intel_encoder base;
1625 u32 saved_port_bits;
1627 struct intel_hdmi hdmi;
1628 struct intel_lspcon lspcon;
1629 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1630 bool release_cl2_override;
1632 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1634 enum intel_display_power_domain ddi_io_power_domain;
1635 intel_wakeref_t ddi_io_wakeref;
1636 intel_wakeref_t aux_wakeref;
1637 struct mutex tc_lock; /* protects the TypeC port mode */
1638 intel_wakeref_t tc_lock_wakeref;
1639 int tc_link_refcount;
1640 bool tc_legacy_port:1;
1641 char tc_port_name[8];
1642 enum tc_port_mode tc_mode;
1643 enum phy_fia tc_phy_fia;
1646 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1647 struct mutex hdcp_mutex;
1648 /* the number of pipes using HDCP signalling out of this port */
1649 unsigned int num_hdcp_streams;
1650 /* port HDCP auth status */
1651 bool hdcp_auth_status;
1652 /* HDCP port data need to pass to security f/w */
1653 struct hdcp_port_data hdcp_port_data;
1655 void (*write_infoframe)(struct intel_encoder *encoder,
1656 const struct intel_crtc_state *crtc_state,
1658 const void *frame, ssize_t len);
1659 void (*read_infoframe)(struct intel_encoder *encoder,
1660 const struct intel_crtc_state *crtc_state,
1662 void *frame, ssize_t len);
1663 void (*set_infoframes)(struct intel_encoder *encoder,
1665 const struct intel_crtc_state *crtc_state,
1666 const struct drm_connector_state *conn_state);
1667 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1668 const struct intel_crtc_state *pipe_config);
1669 bool (*connected)(struct intel_encoder *encoder);
1672 struct intel_dp_mst_encoder {
1673 struct intel_encoder base;
1675 struct intel_digital_port *primary;
1676 struct intel_connector *connector;
1679 static inline enum dpio_channel
1680 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1682 switch (dig_port->base.port) {
1693 static inline enum dpio_phy
1694 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1696 switch (dig_port->base.port) {
1707 static inline enum dpio_channel
1708 vlv_pipe_to_channel(enum pipe pipe)
1721 static inline struct intel_crtc *
1722 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1724 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1727 static inline struct intel_crtc *
1728 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1730 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1731 drm_WARN_ON(&dev_priv->drm,
1732 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1733 return dev_priv->pipe_to_crtc_mapping[pipe];
1736 static inline struct intel_crtc *
1737 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1739 return dev_priv->plane_to_crtc_mapping[plane];
1742 struct intel_load_detect_pipe {
1743 struct drm_atomic_state *restore_state;
1746 static inline struct intel_encoder *
1747 intel_attached_encoder(struct intel_connector *connector)
1749 return connector->encoder;
1752 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1754 switch (encoder->type) {
1755 case INTEL_OUTPUT_DDI:
1756 case INTEL_OUTPUT_DP:
1757 case INTEL_OUTPUT_EDP:
1758 case INTEL_OUTPUT_HDMI:
1765 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1767 return encoder->type == INTEL_OUTPUT_DP_MST;
1770 static inline struct intel_dp_mst_encoder *
1771 enc_to_mst(struct intel_encoder *encoder)
1773 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1777 static inline struct intel_digital_port *
1778 enc_to_dig_port(struct intel_encoder *encoder)
1780 struct intel_encoder *intel_encoder = encoder;
1782 if (intel_encoder_is_dig_port(intel_encoder))
1783 return container_of(&encoder->base, struct intel_digital_port,
1785 else if (intel_encoder_is_mst(intel_encoder))
1786 return enc_to_mst(encoder)->primary;
1791 static inline struct intel_digital_port *
1792 intel_attached_dig_port(struct intel_connector *connector)
1794 return enc_to_dig_port(intel_attached_encoder(connector));
1797 static inline struct intel_hdmi *
1798 enc_to_intel_hdmi(struct intel_encoder *encoder)
1800 return &enc_to_dig_port(encoder)->hdmi;
1803 static inline struct intel_hdmi *
1804 intel_attached_hdmi(struct intel_connector *connector)
1806 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1809 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1811 return &enc_to_dig_port(encoder)->dp;
1814 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1816 return enc_to_intel_dp(intel_attached_encoder(connector));
1819 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1821 switch (encoder->type) {
1822 case INTEL_OUTPUT_DP:
1823 case INTEL_OUTPUT_EDP:
1825 case INTEL_OUTPUT_DDI:
1826 /* Skip pure HDMI/DVI DDI encoders */
1827 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1833 static inline struct intel_lspcon *
1834 enc_to_intel_lspcon(struct intel_encoder *encoder)
1836 return &enc_to_dig_port(encoder)->lspcon;
1839 static inline struct intel_digital_port *
1840 dp_to_dig_port(struct intel_dp *intel_dp)
1842 return container_of(intel_dp, struct intel_digital_port, dp);
1845 static inline struct intel_lspcon *
1846 dp_to_lspcon(struct intel_dp *intel_dp)
1848 return &dp_to_dig_port(intel_dp)->lspcon;
1851 static inline struct drm_i915_private *
1852 dp_to_i915(struct intel_dp *intel_dp)
1854 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1857 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1858 (intel_dp)->psr.source_support)
1860 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1862 if (!intel_encoder_is_dp(encoder))
1865 return CAN_PSR(enc_to_intel_dp(encoder));
1868 static inline struct intel_digital_port *
1869 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1871 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1874 static inline struct intel_plane_state *
1875 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1876 struct intel_plane *plane)
1878 struct drm_plane_state *ret =
1879 drm_atomic_get_plane_state(&state->base, &plane->base);
1882 return ERR_CAST(ret);
1884 return to_intel_plane_state(ret);
1887 static inline struct intel_plane_state *
1888 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1889 struct intel_plane *plane)
1891 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1895 static inline struct intel_plane_state *
1896 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1897 struct intel_plane *plane)
1899 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1903 static inline struct intel_crtc_state *
1904 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1905 struct intel_crtc *crtc)
1907 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1911 static inline struct intel_crtc_state *
1912 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1913 struct intel_crtc *crtc)
1915 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1919 static inline struct intel_digital_connector_state *
1920 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1921 struct intel_connector *connector)
1923 return to_intel_digital_connector_state(
1924 drm_atomic_get_new_connector_state(&state->base,
1928 static inline struct intel_digital_connector_state *
1929 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1930 struct intel_connector *connector)
1932 return to_intel_digital_connector_state(
1933 drm_atomic_get_old_connector_state(&state->base,
1937 /* intel_display.c */
1939 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1940 enum intel_output_type type)
1942 return crtc_state->output_types & (1 << type);
1945 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1947 return crtc_state->output_types &
1948 ((1 << INTEL_OUTPUT_DP) |
1949 (1 << INTEL_OUTPUT_DP_MST) |
1950 (1 << INTEL_OUTPUT_EDP));
1954 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
1956 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1960 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1962 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1964 drm_crtc_wait_one_vblank(&crtc->base);
1968 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1970 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1973 intel_wait_for_vblank(dev_priv, pipe);
1976 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1978 return i915_ggtt_offset(state->vma);
1981 static inline struct intel_frontbuffer *
1982 to_intel_frontbuffer(struct drm_framebuffer *fb)
1984 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
1987 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
1989 if (dev_priv->params.panel_use_ssc >= 0)
1990 return dev_priv->params.panel_use_ssc != 0;
1991 return dev_priv->vbt.lvds_use_ssc
1992 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
1995 static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
1997 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
2000 static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
2001 const struct intel_crtc_state *pipe_config)
2003 if (HAS_DDI(dev_priv))
2004 return pipe_config->port_clock; /* SPLL */
2006 return dev_priv->fdi_pll_freq;
2009 static inline bool is_ccs_modifier(u64 modifier)
2011 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2012 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2013 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2014 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2015 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2018 static inline bool is_gen12_ccs_modifier(u64 modifier)
2020 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2021 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2022 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2025 #endif /* __INTEL_DISPLAY_TYPES_H__ */