2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/sched/clock.h>
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_dp_dual_mode_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_encoder.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_vblank.h>
42 #include <drm/i915_drm.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
50 struct __intel_global_objs_state;
53 * Display related stuff
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
92 /* for each plane in the normal GTT view */
96 /* for each plane in the rotated GTT view for no-CCS formats */
99 unsigned int pitch; /* pixels */
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
116 bool hpd_waiting : 1;
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
128 struct intel_encoder {
129 struct drm_encoder base;
131 enum intel_output_type type;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector,
138 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
139 struct intel_crtc_state *,
140 struct drm_connector_state *);
141 int (*compute_config)(struct intel_encoder *,
142 struct intel_crtc_state *,
143 struct drm_connector_state *);
144 void (*update_prepare)(struct intel_atomic_state *,
145 struct intel_encoder *,
146 struct intel_crtc *);
147 void (*pre_pll_enable)(struct intel_encoder *,
148 const struct intel_crtc_state *,
149 const struct drm_connector_state *);
150 void (*pre_enable)(struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*enable)(struct intel_encoder *,
154 const struct intel_crtc_state *,
155 const struct drm_connector_state *);
156 void (*update_complete)(struct intel_atomic_state *,
157 struct intel_encoder *,
158 struct intel_crtc *);
159 void (*disable)(struct intel_encoder *,
160 const struct intel_crtc_state *,
161 const struct drm_connector_state *);
162 void (*post_disable)(struct intel_encoder *,
163 const struct intel_crtc_state *,
164 const struct drm_connector_state *);
165 void (*post_pll_disable)(struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*update_pipe)(struct intel_encoder *,
169 const struct intel_crtc_state *,
170 const struct drm_connector_state *);
171 /* Read out the current hw state of this connector, returning true if
172 * the encoder is active. If the encoder is enabled it also set the pipe
173 * it is connected to in the pipe parameter. */
174 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
175 /* Reconstructs the equivalent mode flags for the current hardware
176 * state. This must be called _after_ display->get_pipe_config has
177 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
178 * be set correctly before calling this function. */
179 void (*get_config)(struct intel_encoder *,
180 struct intel_crtc_state *pipe_config);
182 * Acquires the power domains needed for an active encoder during
183 * hardware state readout.
185 void (*get_power_domains)(struct intel_encoder *encoder,
186 struct intel_crtc_state *crtc_state);
188 * Called during system suspend after all pending requests for the
189 * encoder are flushed (for example for DP AUX transactions) and
190 * device interrupts are disabled.
192 void (*suspend)(struct intel_encoder *);
193 enum hpd_pin hpd_pin;
194 enum intel_display_power_domain power_domain;
195 /* for communication with audio component; protected by av_mutex */
196 const struct drm_connector *audio_connector;
200 struct drm_display_mode *fixed_mode;
201 struct drm_display_mode *downclock_mode;
210 bool combination_mode; /* gen 2/4 only */
212 bool alternate_pwm_increment; /* lpt+ */
215 bool util_pin_active_low; /* bxt+ */
216 u8 controller; /* bxt+ only */
217 struct pwm_device *pwm;
222 struct backlight_device *device;
224 /* Connector and platform specific backlight functions */
225 int (*setup)(struct intel_connector *connector, enum pipe pipe);
226 u32 (*get)(struct intel_connector *connector);
227 void (*set)(const struct drm_connector_state *conn_state, u32 level);
228 void (*disable)(const struct drm_connector_state *conn_state);
229 void (*enable)(const struct intel_crtc_state *crtc_state,
230 const struct drm_connector_state *conn_state);
231 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
232 void (*power)(struct intel_connector *, bool enable);
236 struct intel_digital_port;
238 enum check_link_response {
239 HDCP_LINK_PROTECTED = 0,
240 HDCP_TOPOLOGY_CHANGE,
241 HDCP_LINK_INTEGRITY_FAILURE,
246 * This structure serves as a translation layer between the generic HDCP code
247 * and the bus-specific code. What that means is that HDCP over HDMI differs
248 * from HDCP over DP, so to account for these differences, we need to
249 * communicate with the receiver through this shim.
251 * For completeness, the 2 buses differ in the following ways:
253 * HDCP registers on the receiver are set via DP AUX for DP, and
254 * they are set via DDC for HDMI.
255 * - Receiver register offsets
256 * The offsets of the registers are different for DP vs. HDMI
257 * - Receiver register masks/offsets
258 * For instance, the ready bit for the KSV fifo is in a different
259 * place on DP vs HDMI
260 * - Receiver register names
261 * Seriously. In the DP spec, the 16-bit register containing
262 * downstream information is called BINFO, on HDMI it's called
263 * BSTATUS. To confuse matters further, DP has a BSTATUS register
264 * with a completely different definition.
266 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
267 * be read 3 keys at a time
269 * Since Aksv is hidden in hardware, there's different procedures
270 * to send it over DP AUX vs DDC
272 struct intel_hdcp_shim {
273 /* Outputs the transmitter's An and Aksv values to the receiver. */
274 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
276 /* Reads the receiver's key selection vector */
277 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
280 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
281 * definitions are the same in the respective specs, but the names are
282 * different. Call it BSTATUS since that's the name the HDMI spec
283 * uses and it was there first.
285 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
288 /* Determines whether a repeater is present downstream */
289 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
290 bool *repeater_present);
292 /* Reads the receiver's Ri' value */
293 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
295 /* Determines if the receiver's KSV FIFO is ready for consumption */
296 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
299 /* Reads the ksv fifo for num_downstream devices */
300 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
301 int num_downstream, u8 *ksv_fifo);
303 /* Reads a 32-bit part of V' from the receiver */
304 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
307 /* Enables HDCP signalling on the port */
308 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
311 /* Ensures the link is still protected */
312 bool (*check_link)(struct intel_digital_port *intel_dig_port);
314 /* Detects panel's hdcp capability. This is optional for HDMI. */
315 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
318 /* HDCP adaptation(DP/HDMI) required on the port */
319 enum hdcp_wired_protocol protocol;
321 /* Detects whether sink is HDCP2.2 capable */
322 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
325 /* Write HDCP2.2 messages */
326 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
327 void *buf, size_t size);
329 /* Read HDCP2.2 messages */
330 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
331 u8 msg_id, void *buf, size_t size);
334 * Implementation of DP HDCP2.2 Errata for the communication of stream
335 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
336 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
338 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
339 bool is_repeater, u8 type);
341 /* HDCP2.2 Link Integrity Check */
342 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
346 const struct intel_hdcp_shim *shim;
347 /* Mutex for hdcp state of the connector */
350 struct delayed_work check_work;
351 struct work_struct prop_work;
353 /* HDCP1.4 Encryption status */
356 /* HDCP2.2 related definitions */
357 /* Flag indicates whether this connector supports HDCP2.2 or not. */
358 bool hdcp2_supported;
360 /* HDCP2.2 Encryption status */
361 bool hdcp2_encrypted;
364 * Content Stream Type defined by content owner. TYPE0(0x0) content can
365 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
366 * content can flow only through a link protected by HDCP2.2.
369 struct hdcp_port_data port_data;
375 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
376 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
377 * When it rolls over re-auth has to be triggered.
382 * Count of RepeaterAuth_Stream_Manage msg propagated.
383 * Initialized to 0 on AKE_INIT. Incremented after every successful
384 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
385 * over re-Auth has to be triggered.
390 * Work queue to signal the CP_IRQ. Used for the waiters to read the
391 * available information from HDCP DP sink.
393 wait_queue_head_t cp_irq_queue;
394 atomic_t cp_irq_count;
395 int cp_irq_count_cached;
398 * HDCP register access for gen12+ need the transcoder associated.
399 * Transcoder attached to the connector could be changed at modeset.
400 * Hence caching the transcoder here.
402 enum transcoder cpu_transcoder;
405 struct intel_connector {
406 struct drm_connector base;
408 * The fixed encoder this connector is connected to.
410 struct intel_encoder *encoder;
412 /* ACPI device id for ACPI and driver cooperation */
415 /* Reads out the current hw, returning true if the connector is enabled
416 * and active (i.e. dpms ON state). */
417 bool (*get_hw_state)(struct intel_connector *);
419 /* Panel info for eDP and LVDS */
420 struct intel_panel panel;
422 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
424 struct edid *detect_edid;
426 /* since POLL and HPD connectors may use the same HPD line keep the native
427 state of connector->polled in case hotplug storm detection changes it */
430 void *port; /* store this opaque as its illegal to dereference it */
432 struct intel_dp *mst_port;
434 /* Work struct to schedule a uevent on link train failure */
435 struct work_struct modeset_retry_work;
437 struct intel_hdcp hdcp;
440 struct intel_digital_connector_state {
441 struct drm_connector_state base;
443 enum hdmi_force_audio force_audio;
447 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
461 struct intel_atomic_state {
462 struct drm_atomic_state base;
464 intel_wakeref_t wakeref;
466 struct __intel_global_objs_state *global_objs;
469 bool dpll_set, modeset;
472 * Does this transaction change the pipes that are active? This mask
473 * tracks which CRTC's have changed their active state at the end of
474 * the transaction (not counting the temporary disable during modesets).
475 * This mask should only be non-zero when intel_state->modeset is true,
476 * but the converse is not necessarily true; simply changing a mode may
477 * not flip the final active status of any CRTC's
479 u8 active_pipe_changes;
483 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
486 * Current watermarks can't be trusted during hardware readout, so
487 * don't bother calculating intermediate watermarks.
489 bool skip_intermediate_wm;
491 bool rps_interactive;
496 bool global_state_changed;
499 struct skl_ddb_values wm_results;
501 struct i915_sw_fence commit_ready;
503 struct llist_node freed;
506 struct intel_plane_state {
507 struct drm_plane_state uapi;
510 * actual hardware state, the state we program to the hardware.
511 * The following members are used to verify the hardware state:
512 * During initial hw readout, they need to be copied from uapi.
515 struct drm_crtc *crtc;
516 struct drm_framebuffer *fb;
519 uint16_t pixel_blend_mode;
520 unsigned int rotation;
521 enum drm_color_encoding color_encoding;
522 enum drm_color_range color_range;
525 struct i915_ggtt_view view;
526 struct i915_vma *vma;
528 #define PLANE_HAS_FENCE BIT(0)
534 * bytes for 0/180 degree rotation
535 * pixels for 90/270 degree rotation
541 /* plane control register */
544 /* plane color control register */
547 /* chroma upsampler control register */
552 * = -1 : not using a scaler
553 * >= 0 : using a scalers
555 * plane requiring a scaler:
556 * - During check_plane, its bit is set in
557 * crtc_state->scaler_state.scaler_users by calling helper function
558 * update_scaler_plane.
559 * - scaler_id indicates the scaler it got assigned.
561 * plane doesn't require a scaler:
562 * - this can happen when scaling is no more required or plane simply
564 * - During check_plane, corresponding bit is reset in
565 * crtc_state->scaler_state.scaler_users by calling helper function
566 * update_scaler_plane.
571 * planar_linked_plane:
573 * ICL planar formats require 2 planes that are updated as pairs.
574 * This member is used to make sure the other plane is also updated
575 * when required, and for update_slave() to find the correct
576 * plane_state to pass as argument.
578 struct intel_plane *planar_linked_plane;
582 * If set don't update use the linked plane's state for updating
583 * this plane during atomic commit with the update_slave() callback.
585 * It's also used by the watermark code to ignore wm calculations on
586 * this plane. They're calculated by the linked plane's wm code.
590 struct drm_intel_sprite_colorkey ckey;
593 struct intel_initial_plane_config {
594 struct intel_framebuffer *fb;
601 struct intel_scaler {
606 struct intel_crtc_scaler_state {
607 #define SKL_NUM_SCALERS 2
608 struct intel_scaler scalers[SKL_NUM_SCALERS];
611 * scaler_users: keeps track of users requesting scalers on this crtc.
613 * If a bit is set, a user is using a scaler.
614 * Here user can be a plane or crtc as defined below:
615 * bits 0-30 - plane (bit position is index from drm_plane_index)
618 * Instead of creating a new index to cover planes and crtc, using
619 * existing drm_plane_index for planes which is well less than 31
620 * planes and bit 31 for crtc. This should be fine to cover all
623 * intel_atomic_setup_scalers will setup available scalers to users
624 * requesting scalers. It will gracefully fail if request exceeds
627 #define SKL_CRTC_INDEX 31
628 unsigned scaler_users;
630 /* scaler used by crtc for panel fitting purpose */
634 /* drm_mode->private_flags */
635 #define I915_MODE_FLAG_INHERITED (1<<0)
636 /* Flag to get scanline using frame time stamps */
637 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
638 /* Flag to use the scanline counter instead of the pixel counter */
639 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
641 struct intel_pipe_wm {
642 struct intel_wm_level wm[5];
645 bool sprites_enabled;
649 struct skl_plane_wm {
650 struct skl_wm_level wm[8];
651 struct skl_wm_level uv_wm[8];
652 struct skl_wm_level trans_wm;
657 struct skl_plane_wm planes[I915_MAX_PLANES];
663 VLV_WM_LEVEL_DDR_DVFS,
667 struct vlv_wm_state {
668 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
669 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
674 struct vlv_fifo_state {
675 u16 plane[I915_MAX_PLANES];
685 struct g4x_wm_state {
686 struct g4x_pipe_wm wm;
688 struct g4x_sr_wm hpll;
694 struct intel_crtc_wm_state {
698 * Intermediate watermarks; these can be
699 * programmed immediately since they satisfy
700 * both the current configuration we're
701 * switching away from and the new
702 * configuration we're switching to.
704 struct intel_pipe_wm intermediate;
707 * Optimal watermarks, programmed post-vblank
708 * when this state is committed.
710 struct intel_pipe_wm optimal;
714 /* gen9+ only needs 1-step wm programming */
715 struct skl_pipe_wm optimal;
716 struct skl_ddb_entry ddb;
717 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
718 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
722 /* "raw" watermarks (not inverted) */
723 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
724 /* intermediate watermarks (inverted) */
725 struct vlv_wm_state intermediate;
726 /* optimal watermarks (inverted) */
727 struct vlv_wm_state optimal;
728 /* display FIFO split */
729 struct vlv_fifo_state fifo_state;
733 /* "raw" watermarks */
734 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
735 /* intermediate watermarks */
736 struct g4x_wm_state intermediate;
737 /* optimal watermarks */
738 struct g4x_wm_state optimal;
743 * Platforms with two-step watermark programming will need to
744 * update watermark programming post-vblank to switch from the
745 * safe intermediate watermarks to the optimal final
748 bool need_postvbl_update;
751 enum intel_output_format {
752 INTEL_OUTPUT_FORMAT_INVALID,
753 INTEL_OUTPUT_FORMAT_RGB,
754 INTEL_OUTPUT_FORMAT_YCBCR420,
755 INTEL_OUTPUT_FORMAT_YCBCR444,
758 struct intel_crtc_state {
760 * uapi (drm) state. This is the software state shown to userspace.
761 * In particular, the following members are used for bookkeeping:
769 struct drm_crtc_state uapi;
772 * actual hardware state, the state we program to the hardware.
773 * The following members are used to verify the hardware state:
776 * - mode / adjusted_mode
777 * - color property blobs.
779 * During initial hw readout, they need to be copied to uapi.
783 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
784 struct drm_display_mode mode, adjusted_mode;
788 * quirks - bitfield with hw state readout quirks
790 * For various reasons the hw state readout code might not be able to
791 * completely faithfully read out the current state. These cases are
792 * tracked with quirk flags so that fastboot and state checker can act
795 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
796 unsigned long quirks;
798 unsigned fb_bits; /* framebuffers to flip */
799 bool update_pipe; /* can a fast modeset be performed? */
801 bool update_wm_pre, update_wm_post; /* watermarks are updated */
802 bool fifo_changed; /* FIFO split is changed */
805 /* Pipe source size (ie. panel fitter input size)
806 * All planes will be positioned inside this space,
807 * and get clipped at the edges. */
808 int pipe_src_w, pipe_src_h;
811 * Pipe pixel rate, adjusted for
812 * panel fitter/pipe scaler downscaling.
814 unsigned int pixel_rate;
816 /* Whether to set up the PCH/FDI. Note that we never allow sharing
817 * between pch encoders and cpu encoders. */
818 bool has_pch_encoder;
820 /* Are we sending infoframes on the attached port */
823 /* CPU Transcoder for the pipe. Currently this can only differ from the
824 * pipe on Haswell and later (where we have a special eDP transcoder)
825 * and Broxton (where we have special DSI transcoders). */
826 enum transcoder cpu_transcoder;
829 * Use reduced/limited/broadcast rbg range, compressing from the full
830 * range fed into the crtcs.
832 bool limited_color_range;
834 /* Bitmask of encoder types (enum intel_output_type)
835 * driven by the pipe.
837 unsigned int output_types;
839 /* Whether we should send NULL infoframes. Required for audio. */
842 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
843 * has_dp_encoder is set. */
847 * Enable dithering, used when the selected pipe bpp doesn't match the
853 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
854 * compliance video pattern tests.
855 * Disable dither only if it is a compliance test request for
858 bool dither_force_disable;
860 /* Controls for the clock computation, to override various stages. */
863 /* SDVO TV has a bunch of special case. To make multifunction encoders
864 * work correctly, we need to track this at runtime.*/
868 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
869 * required. This is set in the 2nd loop of calling encoder's
870 * ->compute_config if the first pick doesn't work out.
874 /* Settings for the intel dpll used on pretty much everything but
878 /* Selected dpll when shared or NULL. */
879 struct intel_shared_dpll *shared_dpll;
881 /* Actual register state of the dpll, for shared dpll cross-checking. */
882 struct intel_dpll_hw_state dpll_hw_state;
885 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
886 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
888 struct icl_port_dpll {
889 struct intel_shared_dpll *pll;
890 struct intel_dpll_hw_state hw_state;
891 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
893 /* DSI PLL registers */
899 struct intel_link_m_n dp_m_n;
901 /* m2_n2 for eDP downclock */
902 struct intel_link_m_n dp_m2_n2;
910 * Frequence the dpll for the port should run at. Differs from the
911 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
912 * already multiplied by pixel_multiplier.
916 /* Used by SDVO (and if we ever fix it, HDMI). */
917 unsigned pixel_multiplier;
922 * Used by platforms having DP/HDMI PHY with programmable lane
923 * latency optimization.
925 u8 lane_lat_optim_mask;
927 /* minimum acceptable voltage level */
928 u8 min_voltage_level;
930 /* Panel fitter controls for gen2-gen4 + VLV */
934 u32 lvds_border_bits;
937 /* Panel fitter placement and size for Ironlake+ */
945 /* FDI configuration, only valid if has_pch_encoder is set. */
947 struct intel_link_m_n fdi_m_n;
959 struct intel_crtc_scaler_state scaler_state;
961 /* w/a for waiting 2 vblanks during crtc enable */
962 enum pipe hsw_workaround_pipe;
964 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
967 struct intel_crtc_wm_state wm;
969 int min_cdclk[I915_MAX_PLANES];
971 u32 data_rate[I915_MAX_PLANES];
973 /* Gamma mode programmed on the pipe */
977 /* CSC mode programmed on the pipe */
984 /* bitmask of visible planes (enum plane_id) */
989 /* bitmask of planes that will be updated during the commit */
995 union hdmi_infoframe avi;
996 union hdmi_infoframe spd;
997 union hdmi_infoframe hdmi;
998 union hdmi_infoframe drm;
1001 /* HDMI scrambling status */
1002 bool hdmi_scrambling;
1004 /* HDMI High TMDS char rate ratio */
1005 bool hdmi_high_tmds_clock_ratio;
1007 /* Output format RGB/YCBCR etc */
1008 enum intel_output_format output_format;
1010 /* Output down scaling is done in LSPCON device */
1011 bool lspcon_downsampling;
1013 /* enable pipe gamma? */
1016 /* enable pipe csc? */
1019 /* Display Stream compression state */
1021 bool compression_enable;
1025 struct drm_dsc_config config;
1028 /* HSW+ linetime watermarks */
1032 /* Forward Error correction State */
1035 /* Pointer to master transcoder in case of tiled displays */
1036 enum transcoder master_transcoder;
1038 /* Bitmask to indicate slaves attached */
1039 u8 sync_mode_slaves_mask;
1041 /* Only valid on TGL+ */
1042 enum transcoder mst_master_transcoder;
1046 struct drm_crtc base;
1049 * Whether the crtc and the connected output pipeline is active. Implies
1050 * that crtc->enabled is set, i.e. the current mode configuration has
1051 * some outputs connected to this crtc.
1055 unsigned long long enabled_power_domains;
1056 struct intel_overlay *overlay;
1058 struct intel_crtc_state *config;
1060 /* Access to these should be protected by dev_priv->irq_lock. */
1061 bool cpu_fifo_underrun_disabled;
1062 bool pch_fifo_underrun_disabled;
1064 /* per-pipe watermark state */
1066 /* watermarks currently being used */
1068 struct intel_pipe_wm ilk;
1069 struct vlv_wm_state vlv;
1070 struct g4x_wm_state g4x;
1074 int scanline_offset;
1077 unsigned start_vbl_count;
1078 ktime_t start_vbl_time;
1079 int min_vbl, max_vbl;
1083 /* scalers available on this crtc */
1086 /* per pipe DSB related info */
1087 struct intel_dsb dsb;
1090 struct intel_plane {
1091 struct drm_plane base;
1092 enum i9xx_plane_id i9xx_plane;
1097 u32 frontbuffer_bit;
1100 u32 base, cntl, size;
1104 * NOTE: Do not place new plane state fields here (e.g., when adding
1105 * new plane properties). New runtime state should now be placed in
1106 * the intel_plane_state structure and accessed via plane_state.
1109 unsigned int (*max_stride)(struct intel_plane *plane,
1110 u32 pixel_format, u64 modifier,
1111 unsigned int rotation);
1112 void (*update_plane)(struct intel_plane *plane,
1113 const struct intel_crtc_state *crtc_state,
1114 const struct intel_plane_state *plane_state);
1115 void (*disable_plane)(struct intel_plane *plane,
1116 const struct intel_crtc_state *crtc_state);
1117 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1118 int (*check_plane)(struct intel_crtc_state *crtc_state,
1119 struct intel_plane_state *plane_state);
1120 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1121 const struct intel_plane_state *plane_state);
1124 struct intel_watermark_params {
1132 struct cxsr_latency {
1133 bool is_desktop : 1;
1138 u16 display_hpll_disable;
1140 u16 cursor_hpll_disable;
1143 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1144 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1145 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1146 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1147 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1148 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1149 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1150 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1151 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1154 i915_reg_t hdmi_reg;
1157 enum drm_dp_dual_mode_type type;
1162 struct intel_connector *attached_connector;
1163 struct cec_notifier *cec_notifier;
1166 struct intel_dp_mst_encoder;
1167 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1170 * enum link_m_n_set:
1171 * When platform provides two set of M_N registers for dp, we can
1172 * program them and switch between them incase of DRRS.
1173 * But When only one such register is provided, we have to program the
1174 * required divider value on that registers itself based on the DRRS state.
1176 * M1_N1 : Program dp_m_n on M1_N1 registers
1177 * dp_m2_n2 on M2_N2 registers (If supported)
1179 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1180 * M2_N2 registers are not supported
1184 /* Sets the m1_n1 and m2_n2 */
1189 struct intel_dp_compliance_data {
1192 u16 hdisplay, vdisplay;
1196 struct intel_dp_compliance {
1197 unsigned long test_type;
1198 struct intel_dp_compliance_data test_data;
1205 i915_reg_t output_reg;
1213 bool reset_link_params;
1214 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1215 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1216 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1217 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1218 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1221 int num_source_rates;
1222 const int *source_rates;
1223 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1225 int sink_rates[DP_MAX_SUPPORTED_RATES];
1226 bool use_rate_select;
1227 /* intersection of source and sink rates */
1228 int num_common_rates;
1229 int common_rates[DP_MAX_SUPPORTED_RATES];
1230 /* Max lane count for the current link */
1231 int max_link_lane_count;
1232 /* Max rate for the current link */
1234 /* sink or branch descriptor */
1235 struct drm_dp_desc desc;
1236 struct drm_dp_aux aux;
1237 u32 aux_busy_last_status;
1239 int panel_power_up_delay;
1240 int panel_power_down_delay;
1241 int panel_power_cycle_delay;
1242 int backlight_on_delay;
1243 int backlight_off_delay;
1244 struct delayed_work panel_vdd_work;
1245 bool want_panel_vdd;
1246 unsigned long last_power_on;
1247 unsigned long last_backlight_off;
1248 ktime_t panel_power_off_time;
1250 struct notifier_block edp_notifier;
1253 * Pipe whose power sequencer is currently locked into
1254 * this port. Only relevant on VLV/CHV.
1258 * Pipe currently driving the port. Used for preventing
1259 * the use of the PPS for any pipe currentrly driving
1260 * external DP as that will mess things up on VLV.
1262 enum pipe active_pipe;
1264 * Set if the sequencer may be reset due to a power transition,
1265 * requiring a reinitialization. Only relevant on BXT.
1268 struct edp_power_seq pps_delays;
1270 bool can_mst; /* this port supports mst */
1272 int active_mst_links;
1275 * DP_TP_* registers may be either on port or transcoder register space.
1278 i915_reg_t dp_tp_ctl;
1279 i915_reg_t dp_tp_status;
1282 /* connector directly attached - won't be use for modeset in mst world */
1283 struct intel_connector *attached_connector;
1285 /* mst connector list */
1286 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1287 struct drm_dp_mst_topology_mgr mst_mgr;
1289 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1291 * This function returns the value we have to program the AUX_CTL
1292 * register with to kick off an AUX transaction.
1294 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1295 u32 aux_clock_divider);
1297 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1298 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1300 /* This is called before a link training is starterd */
1301 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1303 /* Displayport compliance testing */
1304 struct intel_dp_compliance compliance;
1306 /* Display stream compression testing */
1310 enum lspcon_vendor {
1312 LSPCON_VENDOR_PARADE
1315 struct intel_lspcon {
1317 enum drm_lspcon_mode mode;
1318 enum lspcon_vendor vendor;
1321 struct intel_digital_port {
1322 struct intel_encoder base;
1323 u32 saved_port_bits;
1325 struct intel_hdmi hdmi;
1326 struct intel_lspcon lspcon;
1327 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1328 bool release_cl2_override;
1330 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1332 enum intel_display_power_domain ddi_io_power_domain;
1333 struct mutex tc_lock; /* protects the TypeC port mode */
1334 intel_wakeref_t tc_lock_wakeref;
1335 int tc_link_refcount;
1336 bool tc_legacy_port:1;
1337 char tc_port_name[8];
1338 enum tc_port_mode tc_mode;
1339 enum phy_fia tc_phy_fia;
1342 void (*write_infoframe)(struct intel_encoder *encoder,
1343 const struct intel_crtc_state *crtc_state,
1345 const void *frame, ssize_t len);
1346 void (*read_infoframe)(struct intel_encoder *encoder,
1347 const struct intel_crtc_state *crtc_state,
1349 void *frame, ssize_t len);
1350 void (*set_infoframes)(struct intel_encoder *encoder,
1352 const struct intel_crtc_state *crtc_state,
1353 const struct drm_connector_state *conn_state);
1354 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1355 const struct intel_crtc_state *pipe_config);
1358 struct intel_dp_mst_encoder {
1359 struct intel_encoder base;
1361 struct intel_digital_port *primary;
1362 struct intel_connector *connector;
1365 static inline enum dpio_channel
1366 vlv_dport_to_channel(struct intel_digital_port *dport)
1368 switch (dport->base.port) {
1379 static inline enum dpio_phy
1380 vlv_dport_to_phy(struct intel_digital_port *dport)
1382 switch (dport->base.port) {
1393 static inline enum dpio_channel
1394 vlv_pipe_to_channel(enum pipe pipe)
1407 static inline struct intel_crtc *
1408 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1410 return dev_priv->pipe_to_crtc_mapping[pipe];
1413 static inline struct intel_crtc *
1414 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1416 return dev_priv->plane_to_crtc_mapping[plane];
1419 struct intel_load_detect_pipe {
1420 struct drm_atomic_state *restore_state;
1423 static inline struct intel_encoder *
1424 intel_attached_encoder(struct intel_connector *connector)
1426 return connector->encoder;
1429 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1431 switch (encoder->type) {
1432 case INTEL_OUTPUT_DDI:
1433 case INTEL_OUTPUT_DP:
1434 case INTEL_OUTPUT_EDP:
1435 case INTEL_OUTPUT_HDMI:
1442 static inline struct intel_digital_port *
1443 enc_to_dig_port(struct intel_encoder *encoder)
1445 struct intel_encoder *intel_encoder = encoder;
1447 if (intel_encoder_is_dig_port(intel_encoder))
1448 return container_of(&encoder->base, struct intel_digital_port,
1454 static inline struct intel_digital_port *
1455 intel_attached_dig_port(struct intel_connector *connector)
1457 return enc_to_dig_port(intel_attached_encoder(connector));
1460 static inline struct intel_dp_mst_encoder *
1461 enc_to_mst(struct intel_encoder *encoder)
1463 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1467 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1469 return &enc_to_dig_port(encoder)->dp;
1472 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1474 return enc_to_intel_dp(intel_attached_encoder(connector));
1477 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1479 switch (encoder->type) {
1480 case INTEL_OUTPUT_DP:
1481 case INTEL_OUTPUT_EDP:
1483 case INTEL_OUTPUT_DDI:
1484 /* Skip pure HDMI/DVI DDI encoders */
1485 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1491 static inline struct intel_lspcon *
1492 enc_to_intel_lspcon(struct intel_encoder *encoder)
1494 return &enc_to_dig_port(encoder)->lspcon;
1497 static inline struct intel_digital_port *
1498 dp_to_dig_port(struct intel_dp *intel_dp)
1500 return container_of(intel_dp, struct intel_digital_port, dp);
1503 static inline struct intel_lspcon *
1504 dp_to_lspcon(struct intel_dp *intel_dp)
1506 return &dp_to_dig_port(intel_dp)->lspcon;
1509 static inline struct drm_i915_private *
1510 dp_to_i915(struct intel_dp *intel_dp)
1512 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1515 static inline struct intel_digital_port *
1516 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1518 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1521 static inline struct intel_plane_state *
1522 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1523 struct intel_plane *plane)
1525 struct drm_plane_state *ret =
1526 drm_atomic_get_plane_state(&state->base, &plane->base);
1529 return ERR_CAST(ret);
1531 return to_intel_plane_state(ret);
1534 static inline struct intel_plane_state *
1535 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1536 struct intel_plane *plane)
1538 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1542 static inline struct intel_plane_state *
1543 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1544 struct intel_plane *plane)
1546 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1550 static inline struct intel_crtc_state *
1551 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1552 struct intel_crtc *crtc)
1554 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1558 static inline struct intel_crtc_state *
1559 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1560 struct intel_crtc *crtc)
1562 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1566 static inline struct intel_digital_connector_state *
1567 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1568 struct intel_connector *connector)
1570 return to_intel_digital_connector_state(
1571 drm_atomic_get_new_connector_state(&state->base,
1575 static inline struct intel_digital_connector_state *
1576 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1577 struct intel_connector *connector)
1579 return to_intel_digital_connector_state(
1580 drm_atomic_get_old_connector_state(&state->base,
1584 /* intel_display.c */
1586 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1587 enum intel_output_type type)
1589 return crtc_state->output_types & (1 << type);
1592 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1594 return crtc_state->output_types &
1595 ((1 << INTEL_OUTPUT_DP) |
1596 (1 << INTEL_OUTPUT_DP_MST) |
1597 (1 << INTEL_OUTPUT_EDP));
1600 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1602 drm_wait_one_vblank(&dev_priv->drm, pipe);
1605 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1607 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1610 intel_wait_for_vblank(dev_priv, pipe);
1613 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1615 return i915_ggtt_offset(state->vma);
1618 #endif /* __INTEL_DISPLAY_TYPES_H__ */