2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/sched/clock.h>
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_dp_dual_mode_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_encoder.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_vblank.h>
42 #include <drm/i915_mei_hdcp_interface.h>
43 #include <media/cec-notifier.h>
49 struct __intel_global_objs_state;
52 * Display related stuff
55 /* these are outputs from the chip - integrated only
56 external chips are via DVO or SDVO output */
57 enum intel_output_type {
58 INTEL_OUTPUT_UNUSED = 0,
59 INTEL_OUTPUT_ANALOG = 1,
61 INTEL_OUTPUT_SDVO = 3,
62 INTEL_OUTPUT_LVDS = 4,
63 INTEL_OUTPUT_TVOUT = 5,
64 INTEL_OUTPUT_HDMI = 6,
68 INTEL_OUTPUT_DDI = 10,
69 INTEL_OUTPUT_DP_MST = 11,
72 enum hdmi_force_audio {
73 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
74 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
75 HDMI_AUDIO_AUTO, /* trust EDID */
76 HDMI_AUDIO_ON, /* force turn on HDMI audio */
79 /* "Broadcast RGB" property */
80 enum intel_broadcast_rgb {
81 INTEL_BROADCAST_RGB_AUTO,
82 INTEL_BROADCAST_RGB_FULL,
83 INTEL_BROADCAST_RGB_LIMITED,
86 struct intel_framebuffer {
87 struct drm_framebuffer base;
88 struct intel_frontbuffer *frontbuffer;
89 struct intel_rotation_info rot_info;
91 /* for each plane in the normal GTT view */
95 /* for each plane in the rotated GTT view for no-CCS formats */
98 unsigned int pitch; /* pixels */
103 struct drm_fb_helper helper;
104 struct intel_framebuffer *fb;
105 struct i915_vma *vma;
106 unsigned long vma_flags;
107 async_cookie_t cookie;
110 /* Whether or not fbdev hpd processing is temporarily suspended */
111 bool hpd_suspended : 1;
112 /* Set when a hotplug was received while HPD processing was
115 bool hpd_waiting : 1;
117 /* Protects hpd_suspended */
118 struct mutex hpd_lock;
121 enum intel_hotplug_state {
122 INTEL_HOTPLUG_UNCHANGED,
123 INTEL_HOTPLUG_CHANGED,
127 struct intel_encoder {
128 struct drm_encoder base;
130 enum intel_output_type type;
134 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
135 struct intel_connector *connector);
136 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
137 struct intel_crtc_state *,
138 struct drm_connector_state *);
139 int (*compute_config)(struct intel_encoder *,
140 struct intel_crtc_state *,
141 struct drm_connector_state *);
142 int (*compute_config_late)(struct intel_encoder *,
143 struct intel_crtc_state *,
144 struct drm_connector_state *);
145 void (*update_prepare)(struct intel_atomic_state *,
146 struct intel_encoder *,
147 struct intel_crtc *);
148 void (*pre_pll_enable)(struct intel_atomic_state *,
149 struct intel_encoder *,
150 const struct intel_crtc_state *,
151 const struct drm_connector_state *);
152 void (*pre_enable)(struct intel_atomic_state *,
153 struct intel_encoder *,
154 const struct intel_crtc_state *,
155 const struct drm_connector_state *);
156 void (*enable)(struct intel_atomic_state *,
157 struct intel_encoder *,
158 const struct intel_crtc_state *,
159 const struct drm_connector_state *);
160 void (*update_complete)(struct intel_atomic_state *,
161 struct intel_encoder *,
162 struct intel_crtc *);
163 void (*disable)(struct intel_atomic_state *,
164 struct intel_encoder *,
165 const struct intel_crtc_state *,
166 const struct drm_connector_state *);
167 void (*post_disable)(struct intel_atomic_state *,
168 struct intel_encoder *,
169 const struct intel_crtc_state *,
170 const struct drm_connector_state *);
171 void (*post_pll_disable)(struct intel_atomic_state *,
172 struct intel_encoder *,
173 const struct intel_crtc_state *,
174 const struct drm_connector_state *);
175 void (*update_pipe)(struct intel_atomic_state *,
176 struct intel_encoder *,
177 const struct intel_crtc_state *,
178 const struct drm_connector_state *);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config)(struct intel_encoder *,
188 struct intel_crtc_state *pipe_config);
190 * Acquires the power domains needed for an active encoder during
191 * hardware state readout.
193 void (*get_power_domains)(struct intel_encoder *encoder,
194 struct intel_crtc_state *crtc_state);
196 * Called during system suspend after all pending requests for the
197 * encoder are flushed (for example for DP AUX transactions) and
198 * device interrupts are disabled.
200 void (*suspend)(struct intel_encoder *);
201 enum hpd_pin hpd_pin;
202 enum intel_display_power_domain power_domain;
203 /* for communication with audio component; protected by av_mutex */
204 const struct drm_connector *audio_connector;
208 struct drm_display_mode *fixed_mode;
209 struct drm_display_mode *downclock_mode;
218 bool combination_mode; /* gen 2/4 only */
220 bool alternate_pwm_increment; /* lpt+ */
223 bool util_pin_active_low; /* bxt+ */
224 u8 controller; /* bxt+ only */
225 struct pwm_device *pwm;
230 struct backlight_device *device;
232 /* Connector and platform specific backlight functions */
233 int (*setup)(struct intel_connector *connector, enum pipe pipe);
234 u32 (*get)(struct intel_connector *connector);
235 void (*set)(const struct drm_connector_state *conn_state, u32 level);
236 void (*disable)(const struct drm_connector_state *conn_state);
237 void (*enable)(const struct intel_crtc_state *crtc_state,
238 const struct drm_connector_state *conn_state);
239 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
240 void (*power)(struct intel_connector *, bool enable);
244 struct intel_digital_port;
246 enum check_link_response {
247 HDCP_LINK_PROTECTED = 0,
248 HDCP_TOPOLOGY_CHANGE,
249 HDCP_LINK_INTEGRITY_FAILURE,
254 * This structure serves as a translation layer between the generic HDCP code
255 * and the bus-specific code. What that means is that HDCP over HDMI differs
256 * from HDCP over DP, so to account for these differences, we need to
257 * communicate with the receiver through this shim.
259 * For completeness, the 2 buses differ in the following ways:
261 * HDCP registers on the receiver are set via DP AUX for DP, and
262 * they are set via DDC for HDMI.
263 * - Receiver register offsets
264 * The offsets of the registers are different for DP vs. HDMI
265 * - Receiver register masks/offsets
266 * For instance, the ready bit for the KSV fifo is in a different
267 * place on DP vs HDMI
268 * - Receiver register names
269 * Seriously. In the DP spec, the 16-bit register containing
270 * downstream information is called BINFO, on HDMI it's called
271 * BSTATUS. To confuse matters further, DP has a BSTATUS register
272 * with a completely different definition.
274 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
275 * be read 3 keys at a time
277 * Since Aksv is hidden in hardware, there's different procedures
278 * to send it over DP AUX vs DDC
280 struct intel_hdcp_shim {
281 /* Outputs the transmitter's An and Aksv values to the receiver. */
282 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
284 /* Reads the receiver's key selection vector */
285 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
288 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
289 * definitions are the same in the respective specs, but the names are
290 * different. Call it BSTATUS since that's the name the HDMI spec
291 * uses and it was there first.
293 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
296 /* Determines whether a repeater is present downstream */
297 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
298 bool *repeater_present);
300 /* Reads the receiver's Ri' value */
301 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
303 /* Determines if the receiver's KSV FIFO is ready for consumption */
304 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
307 /* Reads the ksv fifo for num_downstream devices */
308 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
309 int num_downstream, u8 *ksv_fifo);
311 /* Reads a 32-bit part of V' from the receiver */
312 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
315 /* Enables HDCP signalling on the port */
316 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
319 /* Ensures the link is still protected */
320 bool (*check_link)(struct intel_digital_port *intel_dig_port);
322 /* Detects panel's hdcp capability. This is optional for HDMI. */
323 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
326 /* HDCP adaptation(DP/HDMI) required on the port */
327 enum hdcp_wired_protocol protocol;
329 /* Detects whether sink is HDCP2.2 capable */
330 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
333 /* Write HDCP2.2 messages */
334 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
335 void *buf, size_t size);
337 /* Read HDCP2.2 messages */
338 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
339 u8 msg_id, void *buf, size_t size);
342 * Implementation of DP HDCP2.2 Errata for the communication of stream
343 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
344 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
346 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
347 bool is_repeater, u8 type);
349 /* HDCP2.2 Link Integrity Check */
350 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
354 const struct intel_hdcp_shim *shim;
355 /* Mutex for hdcp state of the connector */
358 struct delayed_work check_work;
359 struct work_struct prop_work;
361 /* HDCP1.4 Encryption status */
364 /* HDCP2.2 related definitions */
365 /* Flag indicates whether this connector supports HDCP2.2 or not. */
366 bool hdcp2_supported;
368 /* HDCP2.2 Encryption status */
369 bool hdcp2_encrypted;
372 * Content Stream Type defined by content owner. TYPE0(0x0) content can
373 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
374 * content can flow only through a link protected by HDCP2.2.
377 struct hdcp_port_data port_data;
383 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
384 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
385 * When it rolls over re-auth has to be triggered.
390 * Count of RepeaterAuth_Stream_Manage msg propagated.
391 * Initialized to 0 on AKE_INIT. Incremented after every successful
392 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
393 * over re-Auth has to be triggered.
398 * Work queue to signal the CP_IRQ. Used for the waiters to read the
399 * available information from HDCP DP sink.
401 wait_queue_head_t cp_irq_queue;
402 atomic_t cp_irq_count;
403 int cp_irq_count_cached;
406 * HDCP register access for gen12+ need the transcoder associated.
407 * Transcoder attached to the connector could be changed at modeset.
408 * Hence caching the transcoder here.
410 enum transcoder cpu_transcoder;
413 struct intel_connector {
414 struct drm_connector base;
416 * The fixed encoder this connector is connected to.
418 struct intel_encoder *encoder;
420 /* ACPI device id for ACPI and driver cooperation */
423 /* Reads out the current hw, returning true if the connector is enabled
424 * and active (i.e. dpms ON state). */
425 bool (*get_hw_state)(struct intel_connector *);
427 /* Panel info for eDP and LVDS */
428 struct intel_panel panel;
430 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
432 struct edid *detect_edid;
434 /* Number of times hotplug detection was tried after an HPD interrupt */
437 /* since POLL and HPD connectors may use the same HPD line keep the native
438 state of connector->polled in case hotplug storm detection changes it */
441 void *port; /* store this opaque as its illegal to dereference it */
443 struct intel_dp *mst_port;
445 /* Work struct to schedule a uevent on link train failure */
446 struct work_struct modeset_retry_work;
448 struct intel_hdcp hdcp;
451 struct intel_digital_connector_state {
452 struct drm_connector_state base;
454 enum hdmi_force_audio force_audio;
458 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
472 struct intel_atomic_state {
473 struct drm_atomic_state base;
475 intel_wakeref_t wakeref;
477 struct __intel_global_objs_state *global_objs;
480 bool dpll_set, modeset;
483 * Does this transaction change the pipes that are active? This mask
484 * tracks which CRTC's have changed their active state at the end of
485 * the transaction (not counting the temporary disable during modesets).
486 * This mask should only be non-zero when intel_state->modeset is true,
487 * but the converse is not necessarily true; simply changing a mode may
488 * not flip the final active status of any CRTC's
490 u8 active_pipe_changes;
494 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
497 * Current watermarks can't be trusted during hardware readout, so
498 * don't bother calculating intermediate watermarks.
500 bool skip_intermediate_wm;
502 bool rps_interactive;
507 bool global_state_changed;
509 /* Number of enabled DBuf slices */
510 u8 enabled_dbuf_slices_mask;
512 struct i915_sw_fence commit_ready;
514 struct llist_node freed;
517 struct intel_plane_state {
518 struct drm_plane_state uapi;
521 * actual hardware state, the state we program to the hardware.
522 * The following members are used to verify the hardware state:
523 * During initial hw readout, they need to be copied from uapi.
526 struct drm_crtc *crtc;
527 struct drm_framebuffer *fb;
530 uint16_t pixel_blend_mode;
531 unsigned int rotation;
532 enum drm_color_encoding color_encoding;
533 enum drm_color_range color_range;
536 struct i915_ggtt_view view;
537 struct i915_vma *vma;
539 #define PLANE_HAS_FENCE BIT(0)
545 * bytes for 0/180 degree rotation
546 * pixels for 90/270 degree rotation
552 /* plane control register */
555 /* plane color control register */
558 /* chroma upsampler control register */
563 * = -1 : not using a scaler
564 * >= 0 : using a scalers
566 * plane requiring a scaler:
567 * - During check_plane, its bit is set in
568 * crtc_state->scaler_state.scaler_users by calling helper function
569 * update_scaler_plane.
570 * - scaler_id indicates the scaler it got assigned.
572 * plane doesn't require a scaler:
573 * - this can happen when scaling is no more required or plane simply
575 * - During check_plane, corresponding bit is reset in
576 * crtc_state->scaler_state.scaler_users by calling helper function
577 * update_scaler_plane.
582 * planar_linked_plane:
584 * ICL planar formats require 2 planes that are updated as pairs.
585 * This member is used to make sure the other plane is also updated
586 * when required, and for update_slave() to find the correct
587 * plane_state to pass as argument.
589 struct intel_plane *planar_linked_plane;
593 * If set don't update use the linked plane's state for updating
594 * this plane during atomic commit with the update_slave() callback.
596 * It's also used by the watermark code to ignore wm calculations on
597 * this plane. They're calculated by the linked plane's wm code.
601 struct drm_intel_sprite_colorkey ckey;
604 struct intel_initial_plane_config {
605 struct intel_framebuffer *fb;
606 struct i915_vma *vma;
613 struct intel_scaler {
618 struct intel_crtc_scaler_state {
619 #define SKL_NUM_SCALERS 2
620 struct intel_scaler scalers[SKL_NUM_SCALERS];
623 * scaler_users: keeps track of users requesting scalers on this crtc.
625 * If a bit is set, a user is using a scaler.
626 * Here user can be a plane or crtc as defined below:
627 * bits 0-30 - plane (bit position is index from drm_plane_index)
630 * Instead of creating a new index to cover planes and crtc, using
631 * existing drm_plane_index for planes which is well less than 31
632 * planes and bit 31 for crtc. This should be fine to cover all
635 * intel_atomic_setup_scalers will setup available scalers to users
636 * requesting scalers. It will gracefully fail if request exceeds
639 #define SKL_CRTC_INDEX 31
640 unsigned scaler_users;
642 /* scaler used by crtc for panel fitting purpose */
646 /* drm_mode->private_flags */
647 #define I915_MODE_FLAG_INHERITED (1<<0)
648 /* Flag to get scanline using frame time stamps */
649 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
650 /* Flag to use the scanline counter instead of the pixel counter */
651 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
653 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
654 * is operating in command mode.
655 * Flag to use TE from DSI0 instead of VBI in command mode
657 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
658 /* Flag to use TE from DSI1 instead of VBI in command mode */
659 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
660 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
661 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
663 struct intel_wm_level {
671 struct intel_pipe_wm {
672 struct intel_wm_level wm[5];
675 bool sprites_enabled;
679 struct skl_wm_level {
687 struct skl_plane_wm {
688 struct skl_wm_level wm[8];
689 struct skl_wm_level uv_wm[8];
690 struct skl_wm_level trans_wm;
695 struct skl_plane_wm planes[I915_MAX_PLANES];
701 VLV_WM_LEVEL_DDR_DVFS,
705 struct vlv_wm_state {
706 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
707 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
712 struct vlv_fifo_state {
713 u16 plane[I915_MAX_PLANES];
723 struct g4x_wm_state {
724 struct g4x_pipe_wm wm;
726 struct g4x_sr_wm hpll;
732 struct intel_crtc_wm_state {
736 * Intermediate watermarks; these can be
737 * programmed immediately since they satisfy
738 * both the current configuration we're
739 * switching away from and the new
740 * configuration we're switching to.
742 struct intel_pipe_wm intermediate;
745 * Optimal watermarks, programmed post-vblank
746 * when this state is committed.
748 struct intel_pipe_wm optimal;
752 /* gen9+ only needs 1-step wm programming */
753 struct skl_pipe_wm optimal;
754 struct skl_ddb_entry ddb;
755 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
756 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
760 /* "raw" watermarks (not inverted) */
761 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
762 /* intermediate watermarks (inverted) */
763 struct vlv_wm_state intermediate;
764 /* optimal watermarks (inverted) */
765 struct vlv_wm_state optimal;
766 /* display FIFO split */
767 struct vlv_fifo_state fifo_state;
771 /* "raw" watermarks */
772 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
773 /* intermediate watermarks */
774 struct g4x_wm_state intermediate;
775 /* optimal watermarks */
776 struct g4x_wm_state optimal;
781 * Platforms with two-step watermark programming will need to
782 * update watermark programming post-vblank to switch from the
783 * safe intermediate watermarks to the optimal final
786 bool need_postvbl_update;
789 enum intel_output_format {
790 INTEL_OUTPUT_FORMAT_INVALID,
791 INTEL_OUTPUT_FORMAT_RGB,
792 INTEL_OUTPUT_FORMAT_YCBCR420,
793 INTEL_OUTPUT_FORMAT_YCBCR444,
796 struct intel_crtc_state {
798 * uapi (drm) state. This is the software state shown to userspace.
799 * In particular, the following members are used for bookkeeping:
807 struct drm_crtc_state uapi;
810 * actual hardware state, the state we program to the hardware.
811 * The following members are used to verify the hardware state:
814 * - mode / adjusted_mode
815 * - color property blobs.
817 * During initial hw readout, they need to be copied to uapi.
821 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
822 struct drm_display_mode mode, adjusted_mode;
826 * quirks - bitfield with hw state readout quirks
828 * For various reasons the hw state readout code might not be able to
829 * completely faithfully read out the current state. These cases are
830 * tracked with quirk flags so that fastboot and state checker can act
833 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
834 unsigned long quirks;
836 unsigned fb_bits; /* framebuffers to flip */
837 bool update_pipe; /* can a fast modeset be performed? */
839 bool update_wm_pre, update_wm_post; /* watermarks are updated */
840 bool fifo_changed; /* FIFO split is changed */
843 /* Pipe source size (ie. panel fitter input size)
844 * All planes will be positioned inside this space,
845 * and get clipped at the edges. */
846 int pipe_src_w, pipe_src_h;
849 * Pipe pixel rate, adjusted for
850 * panel fitter/pipe scaler downscaling.
852 unsigned int pixel_rate;
854 /* Whether to set up the PCH/FDI. Note that we never allow sharing
855 * between pch encoders and cpu encoders. */
856 bool has_pch_encoder;
858 /* Are we sending infoframes on the attached port */
861 /* CPU Transcoder for the pipe. Currently this can only differ from the
862 * pipe on Haswell and later (where we have a special eDP transcoder)
863 * and Broxton (where we have special DSI transcoders). */
864 enum transcoder cpu_transcoder;
867 * Use reduced/limited/broadcast rbg range, compressing from the full
868 * range fed into the crtcs.
870 bool limited_color_range;
872 /* Bitmask of encoder types (enum intel_output_type)
873 * driven by the pipe.
875 unsigned int output_types;
877 /* Whether we should send NULL infoframes. Required for audio. */
880 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
881 * has_dp_encoder is set. */
885 * Enable dithering, used when the selected pipe bpp doesn't match the
891 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
892 * compliance video pattern tests.
893 * Disable dither only if it is a compliance test request for
896 bool dither_force_disable;
898 /* Controls for the clock computation, to override various stages. */
901 /* SDVO TV has a bunch of special case. To make multifunction encoders
902 * work correctly, we need to track this at runtime.*/
906 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
907 * required. This is set in the 2nd loop of calling encoder's
908 * ->compute_config if the first pick doesn't work out.
912 /* Settings for the intel dpll used on pretty much everything but
916 /* Selected dpll when shared or NULL. */
917 struct intel_shared_dpll *shared_dpll;
919 /* Actual register state of the dpll, for shared dpll cross-checking. */
920 struct intel_dpll_hw_state dpll_hw_state;
923 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
924 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
926 struct icl_port_dpll {
927 struct intel_shared_dpll *pll;
928 struct intel_dpll_hw_state hw_state;
929 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
931 /* DSI PLL registers */
937 struct intel_link_m_n dp_m_n;
939 /* m2_n2 for eDP downclock */
940 struct intel_link_m_n dp_m2_n2;
948 * Frequence the dpll for the port should run at. Differs from the
949 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
950 * already multiplied by pixel_multiplier.
954 /* Used by SDVO (and if we ever fix it, HDMI). */
955 unsigned pixel_multiplier;
960 * Used by platforms having DP/HDMI PHY with programmable lane
961 * latency optimization.
963 u8 lane_lat_optim_mask;
965 /* minimum acceptable voltage level */
966 u8 min_voltage_level;
968 /* Panel fitter controls for gen2-gen4 + VLV */
972 u32 lvds_border_bits;
975 /* Panel fitter placement and size for Ironlake+ */
983 /* FDI configuration, only valid if has_pch_encoder is set. */
985 struct intel_link_m_n fdi_m_n;
997 struct intel_crtc_scaler_state scaler_state;
999 /* w/a for waiting 2 vblanks during crtc enable */
1000 enum pipe hsw_workaround_pipe;
1002 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1005 struct intel_crtc_wm_state wm;
1007 int min_cdclk[I915_MAX_PLANES];
1009 u32 data_rate[I915_MAX_PLANES];
1011 /* Gamma mode programmed on the pipe */
1015 /* CSC mode programmed on the pipe */
1022 /* bitmask of visible planes (enum plane_id) */
1027 /* bitmask of planes that will be updated during the commit */
1033 union hdmi_infoframe avi;
1034 union hdmi_infoframe spd;
1035 union hdmi_infoframe hdmi;
1036 union hdmi_infoframe drm;
1037 struct drm_dp_vsc_sdp vsc;
1040 /* HDMI scrambling status */
1041 bool hdmi_scrambling;
1043 /* HDMI High TMDS char rate ratio */
1044 bool hdmi_high_tmds_clock_ratio;
1046 /* Output format RGB/YCBCR etc */
1047 enum intel_output_format output_format;
1049 /* Output down scaling is done in LSPCON device */
1050 bool lspcon_downsampling;
1052 /* enable pipe gamma? */
1055 /* enable pipe csc? */
1058 /* Display Stream compression state */
1060 bool compression_enable;
1064 struct drm_dsc_config config;
1067 /* HSW+ linetime watermarks */
1071 /* Forward Error correction State */
1074 /* Pointer to master transcoder in case of tiled displays */
1075 enum transcoder master_transcoder;
1077 /* Bitmask to indicate slaves attached */
1078 u8 sync_mode_slaves_mask;
1080 /* Only valid on TGL+ */
1081 enum transcoder mst_master_transcoder;
1084 enum intel_pipe_crc_source {
1085 INTEL_PIPE_CRC_SOURCE_NONE,
1086 INTEL_PIPE_CRC_SOURCE_PLANE1,
1087 INTEL_PIPE_CRC_SOURCE_PLANE2,
1088 INTEL_PIPE_CRC_SOURCE_PLANE3,
1089 INTEL_PIPE_CRC_SOURCE_PLANE4,
1090 INTEL_PIPE_CRC_SOURCE_PLANE5,
1091 INTEL_PIPE_CRC_SOURCE_PLANE6,
1092 INTEL_PIPE_CRC_SOURCE_PLANE7,
1093 INTEL_PIPE_CRC_SOURCE_PIPE,
1094 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1095 INTEL_PIPE_CRC_SOURCE_TV,
1096 INTEL_PIPE_CRC_SOURCE_DP_B,
1097 INTEL_PIPE_CRC_SOURCE_DP_C,
1098 INTEL_PIPE_CRC_SOURCE_DP_D,
1099 INTEL_PIPE_CRC_SOURCE_AUTO,
1100 INTEL_PIPE_CRC_SOURCE_MAX,
1103 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1104 struct intel_pipe_crc {
1107 enum intel_pipe_crc_source source;
1111 struct drm_crtc base;
1114 * Whether the crtc and the connected output pipeline is active. Implies
1115 * that crtc->enabled is set, i.e. the current mode configuration has
1116 * some outputs connected to this crtc.
1120 unsigned long long enabled_power_domains;
1121 struct intel_overlay *overlay;
1123 struct intel_crtc_state *config;
1125 /* Access to these should be protected by dev_priv->irq_lock. */
1126 bool cpu_fifo_underrun_disabled;
1127 bool pch_fifo_underrun_disabled;
1129 /* per-pipe watermark state */
1131 /* watermarks currently being used */
1133 struct intel_pipe_wm ilk;
1134 struct vlv_wm_state vlv;
1135 struct g4x_wm_state g4x;
1139 int scanline_offset;
1142 unsigned start_vbl_count;
1143 ktime_t start_vbl_time;
1144 int min_vbl, max_vbl;
1148 /* scalers available on this crtc */
1151 /* per pipe DSB related info */
1152 struct intel_dsb dsb;
1154 #ifdef CONFIG_DEBUG_FS
1155 struct intel_pipe_crc pipe_crc;
1159 struct intel_plane {
1160 struct drm_plane base;
1161 enum i9xx_plane_id i9xx_plane;
1166 u32 frontbuffer_bit;
1169 u32 base, cntl, size;
1173 * NOTE: Do not place new plane state fields here (e.g., when adding
1174 * new plane properties). New runtime state should now be placed in
1175 * the intel_plane_state structure and accessed via plane_state.
1178 unsigned int (*max_stride)(struct intel_plane *plane,
1179 u32 pixel_format, u64 modifier,
1180 unsigned int rotation);
1181 void (*update_plane)(struct intel_plane *plane,
1182 const struct intel_crtc_state *crtc_state,
1183 const struct intel_plane_state *plane_state);
1184 void (*disable_plane)(struct intel_plane *plane,
1185 const struct intel_crtc_state *crtc_state);
1186 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1187 int (*check_plane)(struct intel_crtc_state *crtc_state,
1188 struct intel_plane_state *plane_state);
1189 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1190 const struct intel_plane_state *plane_state);
1193 struct intel_watermark_params {
1201 struct cxsr_latency {
1202 bool is_desktop : 1;
1207 u16 display_hpll_disable;
1209 u16 cursor_hpll_disable;
1212 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1213 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1214 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1215 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1216 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1217 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1218 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1219 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1220 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1223 i915_reg_t hdmi_reg;
1226 enum drm_dp_dual_mode_type type;
1231 struct intel_connector *attached_connector;
1232 struct cec_notifier *cec_notifier;
1235 struct intel_dp_mst_encoder;
1237 * enum link_m_n_set:
1238 * When platform provides two set of M_N registers for dp, we can
1239 * program them and switch between them incase of DRRS.
1240 * But When only one such register is provided, we have to program the
1241 * required divider value on that registers itself based on the DRRS state.
1243 * M1_N1 : Program dp_m_n on M1_N1 registers
1244 * dp_m2_n2 on M2_N2 registers (If supported)
1246 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1247 * M2_N2 registers are not supported
1251 /* Sets the m1_n1 and m2_n2 */
1256 struct intel_dp_compliance_data {
1259 u16 hdisplay, vdisplay;
1261 struct drm_dp_phy_test_params phytest;
1264 struct intel_dp_compliance {
1265 unsigned long test_type;
1266 struct intel_dp_compliance_data test_data;
1273 i915_reg_t output_reg;
1281 bool reset_link_params;
1282 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1283 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1284 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1285 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1286 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1289 int num_source_rates;
1290 const int *source_rates;
1291 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1293 int sink_rates[DP_MAX_SUPPORTED_RATES];
1294 bool use_rate_select;
1295 /* intersection of source and sink rates */
1296 int num_common_rates;
1297 int common_rates[DP_MAX_SUPPORTED_RATES];
1298 /* Max lane count for the current link */
1299 int max_link_lane_count;
1300 /* Max rate for the current link */
1302 /* sink or branch descriptor */
1303 struct drm_dp_desc desc;
1305 struct drm_dp_aux aux;
1306 u32 aux_busy_last_status;
1308 int panel_power_up_delay;
1309 int panel_power_down_delay;
1310 int panel_power_cycle_delay;
1311 int backlight_on_delay;
1312 int backlight_off_delay;
1313 struct delayed_work panel_vdd_work;
1314 bool want_panel_vdd;
1315 unsigned long last_power_on;
1316 unsigned long last_backlight_off;
1317 ktime_t panel_power_off_time;
1319 struct notifier_block edp_notifier;
1322 * Pipe whose power sequencer is currently locked into
1323 * this port. Only relevant on VLV/CHV.
1327 * Pipe currently driving the port. Used for preventing
1328 * the use of the PPS for any pipe currentrly driving
1329 * external DP as that will mess things up on VLV.
1331 enum pipe active_pipe;
1333 * Set if the sequencer may be reset due to a power transition,
1334 * requiring a reinitialization. Only relevant on BXT.
1337 struct edp_power_seq pps_delays;
1339 bool can_mst; /* this port supports mst */
1341 int active_mst_links;
1344 * DP_TP_* registers may be either on port or transcoder register space.
1347 i915_reg_t dp_tp_ctl;
1348 i915_reg_t dp_tp_status;
1351 /* connector directly attached - won't be use for modeset in mst world */
1352 struct intel_connector *attached_connector;
1354 /* mst connector list */
1355 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1356 struct drm_dp_mst_topology_mgr mst_mgr;
1358 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1360 * This function returns the value we have to program the AUX_CTL
1361 * register with to kick off an AUX transaction.
1363 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1364 u32 aux_clock_divider);
1366 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1367 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1369 /* This is called before a link training is starterd */
1370 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1372 /* Displayport compliance testing */
1373 struct intel_dp_compliance compliance;
1375 /* Display stream compression testing */
1379 enum lspcon_vendor {
1381 LSPCON_VENDOR_PARADE
1384 struct intel_lspcon {
1386 enum drm_lspcon_mode mode;
1387 enum lspcon_vendor vendor;
1390 struct intel_digital_port {
1391 struct intel_encoder base;
1392 u32 saved_port_bits;
1394 struct intel_hdmi hdmi;
1395 struct intel_lspcon lspcon;
1396 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1397 bool release_cl2_override;
1399 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1401 enum intel_display_power_domain ddi_io_power_domain;
1402 struct mutex tc_lock; /* protects the TypeC port mode */
1403 intel_wakeref_t tc_lock_wakeref;
1404 int tc_link_refcount;
1405 bool tc_legacy_port:1;
1406 char tc_port_name[8];
1407 enum tc_port_mode tc_mode;
1408 enum phy_fia tc_phy_fia;
1411 void (*write_infoframe)(struct intel_encoder *encoder,
1412 const struct intel_crtc_state *crtc_state,
1414 const void *frame, ssize_t len);
1415 void (*read_infoframe)(struct intel_encoder *encoder,
1416 const struct intel_crtc_state *crtc_state,
1418 void *frame, ssize_t len);
1419 void (*set_infoframes)(struct intel_encoder *encoder,
1421 const struct intel_crtc_state *crtc_state,
1422 const struct drm_connector_state *conn_state);
1423 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1424 const struct intel_crtc_state *pipe_config);
1427 struct intel_dp_mst_encoder {
1428 struct intel_encoder base;
1430 struct intel_digital_port *primary;
1431 struct intel_connector *connector;
1434 static inline enum dpio_channel
1435 vlv_dport_to_channel(struct intel_digital_port *dport)
1437 switch (dport->base.port) {
1448 static inline enum dpio_phy
1449 vlv_dport_to_phy(struct intel_digital_port *dport)
1451 switch (dport->base.port) {
1462 static inline enum dpio_channel
1463 vlv_pipe_to_channel(enum pipe pipe)
1476 static inline struct intel_crtc *
1477 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1479 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1482 static inline struct intel_crtc *
1483 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1485 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1486 drm_WARN_ON(&dev_priv->drm,
1487 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1488 return dev_priv->pipe_to_crtc_mapping[pipe];
1491 static inline struct intel_crtc *
1492 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1494 return dev_priv->plane_to_crtc_mapping[plane];
1497 struct intel_load_detect_pipe {
1498 struct drm_atomic_state *restore_state;
1501 static inline struct intel_encoder *
1502 intel_attached_encoder(struct intel_connector *connector)
1504 return connector->encoder;
1507 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1509 switch (encoder->type) {
1510 case INTEL_OUTPUT_DDI:
1511 case INTEL_OUTPUT_DP:
1512 case INTEL_OUTPUT_EDP:
1513 case INTEL_OUTPUT_HDMI:
1520 static inline struct intel_digital_port *
1521 enc_to_dig_port(struct intel_encoder *encoder)
1523 struct intel_encoder *intel_encoder = encoder;
1525 if (intel_encoder_is_dig_port(intel_encoder))
1526 return container_of(&encoder->base, struct intel_digital_port,
1532 static inline struct intel_digital_port *
1533 intel_attached_dig_port(struct intel_connector *connector)
1535 return enc_to_dig_port(intel_attached_encoder(connector));
1538 static inline struct intel_dp_mst_encoder *
1539 enc_to_mst(struct intel_encoder *encoder)
1541 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1545 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1547 return &enc_to_dig_port(encoder)->dp;
1550 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1552 return enc_to_intel_dp(intel_attached_encoder(connector));
1555 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1557 switch (encoder->type) {
1558 case INTEL_OUTPUT_DP:
1559 case INTEL_OUTPUT_EDP:
1561 case INTEL_OUTPUT_DDI:
1562 /* Skip pure HDMI/DVI DDI encoders */
1563 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1569 static inline struct intel_lspcon *
1570 enc_to_intel_lspcon(struct intel_encoder *encoder)
1572 return &enc_to_dig_port(encoder)->lspcon;
1575 static inline struct intel_digital_port *
1576 dp_to_dig_port(struct intel_dp *intel_dp)
1578 return container_of(intel_dp, struct intel_digital_port, dp);
1581 static inline struct intel_lspcon *
1582 dp_to_lspcon(struct intel_dp *intel_dp)
1584 return &dp_to_dig_port(intel_dp)->lspcon;
1587 static inline struct drm_i915_private *
1588 dp_to_i915(struct intel_dp *intel_dp)
1590 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1593 static inline struct intel_digital_port *
1594 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1596 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1599 static inline struct intel_plane_state *
1600 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1601 struct intel_plane *plane)
1603 struct drm_plane_state *ret =
1604 drm_atomic_get_plane_state(&state->base, &plane->base);
1607 return ERR_CAST(ret);
1609 return to_intel_plane_state(ret);
1612 static inline struct intel_plane_state *
1613 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1614 struct intel_plane *plane)
1616 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1620 static inline struct intel_plane_state *
1621 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1622 struct intel_plane *plane)
1624 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1628 static inline struct intel_crtc_state *
1629 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1630 struct intel_crtc *crtc)
1632 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1636 static inline struct intel_crtc_state *
1637 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1638 struct intel_crtc *crtc)
1640 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1644 static inline struct intel_digital_connector_state *
1645 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1646 struct intel_connector *connector)
1648 return to_intel_digital_connector_state(
1649 drm_atomic_get_new_connector_state(&state->base,
1653 static inline struct intel_digital_connector_state *
1654 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1655 struct intel_connector *connector)
1657 return to_intel_digital_connector_state(
1658 drm_atomic_get_old_connector_state(&state->base,
1662 /* intel_display.c */
1664 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1665 enum intel_output_type type)
1667 return crtc_state->output_types & (1 << type);
1670 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1672 return crtc_state->output_types &
1673 ((1 << INTEL_OUTPUT_DP) |
1674 (1 << INTEL_OUTPUT_DP_MST) |
1675 (1 << INTEL_OUTPUT_EDP));
1679 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1681 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1683 drm_crtc_wait_one_vblank(&crtc->base);
1687 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1689 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1692 intel_wait_for_vblank(dev_priv, pipe);
1695 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1697 return i915_ggtt_offset(state->vma);
1700 #endif /* __INTEL_DISPLAY_TYPES_H__ */