2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/sched/clock.h>
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_dp_dual_mode_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_encoder.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_vblank.h>
42 #include <drm/i915_drm.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
51 * Display related stuff
54 /* these are outputs from the chip - integrated only
55 external chips are via DVO or SDVO output */
56 enum intel_output_type {
57 INTEL_OUTPUT_UNUSED = 0,
58 INTEL_OUTPUT_ANALOG = 1,
60 INTEL_OUTPUT_SDVO = 3,
61 INTEL_OUTPUT_LVDS = 4,
62 INTEL_OUTPUT_TVOUT = 5,
63 INTEL_OUTPUT_HDMI = 6,
67 INTEL_OUTPUT_DDI = 10,
68 INTEL_OUTPUT_DP_MST = 11,
71 enum hdmi_force_audio {
72 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
73 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
74 HDMI_AUDIO_AUTO, /* trust EDID */
75 HDMI_AUDIO_ON, /* force turn on HDMI audio */
78 /* "Broadcast RGB" property */
79 enum intel_broadcast_rgb {
80 INTEL_BROADCAST_RGB_AUTO,
81 INTEL_BROADCAST_RGB_FULL,
82 INTEL_BROADCAST_RGB_LIMITED,
85 struct intel_framebuffer {
86 struct drm_framebuffer base;
87 struct intel_frontbuffer *frontbuffer;
88 struct intel_rotation_info rot_info;
90 /* for each plane in the normal GTT view */
94 /* for each plane in the rotated GTT view */
97 unsigned int pitch; /* pixels */
102 struct drm_fb_helper helper;
103 struct intel_framebuffer *fb;
104 struct i915_vma *vma;
105 unsigned long vma_flags;
106 async_cookie_t cookie;
109 /* Whether or not fbdev hpd processing is temporarily suspended */
110 bool hpd_suspended : 1;
111 /* Set when a hotplug was received while HPD processing was
114 bool hpd_waiting : 1;
116 /* Protects hpd_suspended */
117 struct mutex hpd_lock;
120 enum intel_hotplug_state {
121 INTEL_HOTPLUG_UNCHANGED,
122 INTEL_HOTPLUG_CHANGED,
126 struct intel_encoder {
127 struct drm_encoder base;
129 enum intel_output_type type;
133 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
134 struct intel_connector *connector,
136 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
137 struct intel_crtc_state *,
138 struct drm_connector_state *);
139 int (*compute_config)(struct intel_encoder *,
140 struct intel_crtc_state *,
141 struct drm_connector_state *);
142 void (*update_prepare)(struct intel_atomic_state *,
143 struct intel_encoder *,
144 struct intel_crtc *);
145 void (*pre_pll_enable)(struct intel_encoder *,
146 const struct intel_crtc_state *,
147 const struct drm_connector_state *);
148 void (*pre_enable)(struct intel_encoder *,
149 const struct intel_crtc_state *,
150 const struct drm_connector_state *);
151 void (*enable)(struct intel_encoder *,
152 const struct intel_crtc_state *,
153 const struct drm_connector_state *);
154 void (*update_complete)(struct intel_atomic_state *,
155 struct intel_encoder *,
156 struct intel_crtc *);
157 void (*disable)(struct intel_encoder *,
158 const struct intel_crtc_state *,
159 const struct drm_connector_state *);
160 void (*post_disable)(struct intel_encoder *,
161 const struct intel_crtc_state *,
162 const struct drm_connector_state *);
163 void (*post_pll_disable)(struct intel_encoder *,
164 const struct intel_crtc_state *,
165 const struct drm_connector_state *);
166 void (*update_pipe)(struct intel_encoder *,
167 const struct intel_crtc_state *,
168 const struct drm_connector_state *);
169 /* Read out the current hw state of this connector, returning true if
170 * the encoder is active. If the encoder is enabled it also set the pipe
171 * it is connected to in the pipe parameter. */
172 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
173 /* Reconstructs the equivalent mode flags for the current hardware
174 * state. This must be called _after_ display->get_pipe_config has
175 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
176 * be set correctly before calling this function. */
177 void (*get_config)(struct intel_encoder *,
178 struct intel_crtc_state *pipe_config);
180 * Acquires the power domains needed for an active encoder during
181 * hardware state readout.
183 void (*get_power_domains)(struct intel_encoder *encoder,
184 struct intel_crtc_state *crtc_state);
186 * Called during system suspend after all pending requests for the
187 * encoder are flushed (for example for DP AUX transactions) and
188 * device interrupts are disabled.
190 void (*suspend)(struct intel_encoder *);
191 enum hpd_pin hpd_pin;
192 enum intel_display_power_domain power_domain;
193 /* for communication with audio component; protected by av_mutex */
194 const struct drm_connector *audio_connector;
198 struct drm_display_mode *fixed_mode;
199 struct drm_display_mode *downclock_mode;
208 bool combination_mode; /* gen 2/4 only */
210 bool alternate_pwm_increment; /* lpt+ */
213 bool util_pin_active_low; /* bxt+ */
214 u8 controller; /* bxt+ only */
215 struct pwm_device *pwm;
217 struct backlight_device *device;
219 /* Connector and platform specific backlight functions */
220 int (*setup)(struct intel_connector *connector, enum pipe pipe);
221 u32 (*get)(struct intel_connector *connector);
222 void (*set)(const struct drm_connector_state *conn_state, u32 level);
223 void (*disable)(const struct drm_connector_state *conn_state);
224 void (*enable)(const struct intel_crtc_state *crtc_state,
225 const struct drm_connector_state *conn_state);
226 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
227 void (*power)(struct intel_connector *, bool enable);
231 struct intel_digital_port;
233 enum check_link_response {
234 HDCP_LINK_PROTECTED = 0,
235 HDCP_TOPOLOGY_CHANGE,
236 HDCP_LINK_INTEGRITY_FAILURE,
241 * This structure serves as a translation layer between the generic HDCP code
242 * and the bus-specific code. What that means is that HDCP over HDMI differs
243 * from HDCP over DP, so to account for these differences, we need to
244 * communicate with the receiver through this shim.
246 * For completeness, the 2 buses differ in the following ways:
248 * HDCP registers on the receiver are set via DP AUX for DP, and
249 * they are set via DDC for HDMI.
250 * - Receiver register offsets
251 * The offsets of the registers are different for DP vs. HDMI
252 * - Receiver register masks/offsets
253 * For instance, the ready bit for the KSV fifo is in a different
254 * place on DP vs HDMI
255 * - Receiver register names
256 * Seriously. In the DP spec, the 16-bit register containing
257 * downstream information is called BINFO, on HDMI it's called
258 * BSTATUS. To confuse matters further, DP has a BSTATUS register
259 * with a completely different definition.
261 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
262 * be read 3 keys at a time
264 * Since Aksv is hidden in hardware, there's different procedures
265 * to send it over DP AUX vs DDC
267 struct intel_hdcp_shim {
268 /* Outputs the transmitter's An and Aksv values to the receiver. */
269 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
271 /* Reads the receiver's key selection vector */
272 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
275 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
276 * definitions are the same in the respective specs, but the names are
277 * different. Call it BSTATUS since that's the name the HDMI spec
278 * uses and it was there first.
280 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
283 /* Determines whether a repeater is present downstream */
284 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
285 bool *repeater_present);
287 /* Reads the receiver's Ri' value */
288 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
290 /* Determines if the receiver's KSV FIFO is ready for consumption */
291 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
294 /* Reads the ksv fifo for num_downstream devices */
295 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
296 int num_downstream, u8 *ksv_fifo);
298 /* Reads a 32-bit part of V' from the receiver */
299 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
302 /* Enables HDCP signalling on the port */
303 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
306 /* Ensures the link is still protected */
307 bool (*check_link)(struct intel_digital_port *intel_dig_port);
309 /* Detects panel's hdcp capability. This is optional for HDMI. */
310 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
313 /* HDCP adaptation(DP/HDMI) required on the port */
314 enum hdcp_wired_protocol protocol;
316 /* Detects whether sink is HDCP2.2 capable */
317 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
320 /* Write HDCP2.2 messages */
321 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
322 void *buf, size_t size);
324 /* Read HDCP2.2 messages */
325 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
326 u8 msg_id, void *buf, size_t size);
329 * Implementation of DP HDCP2.2 Errata for the communication of stream
330 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
331 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
333 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
334 bool is_repeater, u8 type);
336 /* HDCP2.2 Link Integrity Check */
337 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
341 const struct intel_hdcp_shim *shim;
342 /* Mutex for hdcp state of the connector */
345 struct delayed_work check_work;
346 struct work_struct prop_work;
348 /* HDCP1.4 Encryption status */
351 /* HDCP2.2 related definitions */
352 /* Flag indicates whether this connector supports HDCP2.2 or not. */
353 bool hdcp2_supported;
355 /* HDCP2.2 Encryption status */
356 bool hdcp2_encrypted;
359 * Content Stream Type defined by content owner. TYPE0(0x0) content can
360 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
361 * content can flow only through a link protected by HDCP2.2.
364 struct hdcp_port_data port_data;
370 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
371 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
372 * When it rolls over re-auth has to be triggered.
377 * Count of RepeaterAuth_Stream_Manage msg propagated.
378 * Initialized to 0 on AKE_INIT. Incremented after every successful
379 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
380 * over re-Auth has to be triggered.
385 * Work queue to signal the CP_IRQ. Used for the waiters to read the
386 * available information from HDCP DP sink.
388 wait_queue_head_t cp_irq_queue;
389 atomic_t cp_irq_count;
390 int cp_irq_count_cached;
393 * HDCP register access for gen12+ need the transcoder associated.
394 * Transcoder attached to the connector could be changed at modeset.
395 * Hence caching the transcoder here.
397 enum transcoder cpu_transcoder;
400 struct intel_connector {
401 struct drm_connector base;
403 * The fixed encoder this connector is connected to.
405 struct intel_encoder *encoder;
407 /* ACPI device id for ACPI and driver cooperation */
410 /* Reads out the current hw, returning true if the connector is enabled
411 * and active (i.e. dpms ON state). */
412 bool (*get_hw_state)(struct intel_connector *);
414 /* Panel info for eDP and LVDS */
415 struct intel_panel panel;
417 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
419 struct edid *detect_edid;
421 /* since POLL and HPD connectors may use the same HPD line keep the native
422 state of connector->polled in case hotplug storm detection changes it */
425 void *port; /* store this opaque as its illegal to dereference it */
427 struct intel_dp *mst_port;
429 /* Work struct to schedule a uevent on link train failure */
430 struct work_struct modeset_retry_work;
432 struct intel_hdcp hdcp;
435 struct intel_digital_connector_state {
436 struct drm_connector_state base;
438 enum hdmi_force_audio force_audio;
442 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
456 struct intel_atomic_state {
457 struct drm_atomic_state base;
459 intel_wakeref_t wakeref;
463 * Logical state of cdclk (used for all scaling, watermark,
464 * etc. calculations and checks). This is computed as if all
465 * enabled crtcs were active.
467 struct intel_cdclk_state logical;
470 * Actual state of cdclk, can be different from the logical
471 * state only when all crtc's are DPMS off.
473 struct intel_cdclk_state actual;
476 bool force_min_cdclk_changed;
477 /* pipe to which cd2x update is synchronized */
481 bool dpll_set, modeset;
484 * Does this transaction change the pipes that are active? This mask
485 * tracks which CRTC's have changed their active state at the end of
486 * the transaction (not counting the temporary disable during modesets).
487 * This mask should only be non-zero when intel_state->modeset is true,
488 * but the converse is not necessarily true; simply changing a mode may
489 * not flip the final active status of any CRTC's
491 u8 active_pipe_changes;
494 /* minimum acceptable cdclk for each pipe */
495 int min_cdclk[I915_MAX_PIPES];
496 /* minimum acceptable voltage level for each pipe */
497 u8 min_voltage_level[I915_MAX_PIPES];
499 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
502 * Current watermarks can't be trusted during hardware readout, so
503 * don't bother calculating intermediate watermarks.
505 bool skip_intermediate_wm;
507 bool rps_interactive;
512 * min_voltage_level[]
515 bool global_state_changed;
518 struct skl_ddb_values wm_results;
520 struct i915_sw_fence commit_ready;
522 struct llist_node freed;
525 struct intel_plane_state {
526 struct drm_plane_state uapi;
529 * actual hardware state, the state we program to the hardware.
530 * The following members are used to verify the hardware state:
531 * During initial hw readout, they need to be copied from uapi.
534 struct drm_crtc *crtc;
535 struct drm_framebuffer *fb;
538 uint16_t pixel_blend_mode;
539 unsigned int rotation;
540 enum drm_color_encoding color_encoding;
541 enum drm_color_range color_range;
544 struct i915_ggtt_view view;
545 struct i915_vma *vma;
547 #define PLANE_HAS_FENCE BIT(0)
553 * bytes for 0/180 degree rotation
554 * pixels for 90/270 degree rotation
560 /* plane control register */
563 /* plane color control register */
566 /* chroma upsampler control register */
571 * = -1 : not using a scaler
572 * >= 0 : using a scalers
574 * plane requiring a scaler:
575 * - During check_plane, its bit is set in
576 * crtc_state->scaler_state.scaler_users by calling helper function
577 * update_scaler_plane.
578 * - scaler_id indicates the scaler it got assigned.
580 * plane doesn't require a scaler:
581 * - this can happen when scaling is no more required or plane simply
583 * - During check_plane, corresponding bit is reset in
584 * crtc_state->scaler_state.scaler_users by calling helper function
585 * update_scaler_plane.
590 * planar_linked_plane:
592 * ICL planar formats require 2 planes that are updated as pairs.
593 * This member is used to make sure the other plane is also updated
594 * when required, and for update_slave() to find the correct
595 * plane_state to pass as argument.
597 struct intel_plane *planar_linked_plane;
601 * If set don't update use the linked plane's state for updating
602 * this plane during atomic commit with the update_slave() callback.
604 * It's also used by the watermark code to ignore wm calculations on
605 * this plane. They're calculated by the linked plane's wm code.
609 struct drm_intel_sprite_colorkey ckey;
612 struct intel_initial_plane_config {
613 struct intel_framebuffer *fb;
620 struct intel_scaler {
625 struct intel_crtc_scaler_state {
626 #define SKL_NUM_SCALERS 2
627 struct intel_scaler scalers[SKL_NUM_SCALERS];
630 * scaler_users: keeps track of users requesting scalers on this crtc.
632 * If a bit is set, a user is using a scaler.
633 * Here user can be a plane or crtc as defined below:
634 * bits 0-30 - plane (bit position is index from drm_plane_index)
637 * Instead of creating a new index to cover planes and crtc, using
638 * existing drm_plane_index for planes which is well less than 31
639 * planes and bit 31 for crtc. This should be fine to cover all
642 * intel_atomic_setup_scalers will setup available scalers to users
643 * requesting scalers. It will gracefully fail if request exceeds
646 #define SKL_CRTC_INDEX 31
647 unsigned scaler_users;
649 /* scaler used by crtc for panel fitting purpose */
653 /* drm_mode->private_flags */
654 #define I915_MODE_FLAG_INHERITED (1<<0)
655 /* Flag to get scanline using frame time stamps */
656 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
657 /* Flag to use the scanline counter instead of the pixel counter */
658 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
660 struct intel_pipe_wm {
661 struct intel_wm_level wm[5];
665 bool sprites_enabled;
669 struct skl_plane_wm {
670 struct skl_wm_level wm[8];
671 struct skl_wm_level uv_wm[8];
672 struct skl_wm_level trans_wm;
677 struct skl_plane_wm planes[I915_MAX_PLANES];
684 VLV_WM_LEVEL_DDR_DVFS,
688 struct vlv_wm_state {
689 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
690 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
695 struct vlv_fifo_state {
696 u16 plane[I915_MAX_PLANES];
706 struct g4x_wm_state {
707 struct g4x_pipe_wm wm;
709 struct g4x_sr_wm hpll;
715 struct intel_crtc_wm_state {
719 * Intermediate watermarks; these can be
720 * programmed immediately since they satisfy
721 * both the current configuration we're
722 * switching away from and the new
723 * configuration we're switching to.
725 struct intel_pipe_wm intermediate;
728 * Optimal watermarks, programmed post-vblank
729 * when this state is committed.
731 struct intel_pipe_wm optimal;
735 /* gen9+ only needs 1-step wm programming */
736 struct skl_pipe_wm optimal;
737 struct skl_ddb_entry ddb;
738 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
739 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
743 /* "raw" watermarks (not inverted) */
744 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
745 /* intermediate watermarks (inverted) */
746 struct vlv_wm_state intermediate;
747 /* optimal watermarks (inverted) */
748 struct vlv_wm_state optimal;
749 /* display FIFO split */
750 struct vlv_fifo_state fifo_state;
754 /* "raw" watermarks */
755 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
756 /* intermediate watermarks */
757 struct g4x_wm_state intermediate;
758 /* optimal watermarks */
759 struct g4x_wm_state optimal;
764 * Platforms with two-step watermark programming will need to
765 * update watermark programming post-vblank to switch from the
766 * safe intermediate watermarks to the optimal final
769 bool need_postvbl_update;
772 enum intel_output_format {
773 INTEL_OUTPUT_FORMAT_INVALID,
774 INTEL_OUTPUT_FORMAT_RGB,
775 INTEL_OUTPUT_FORMAT_YCBCR420,
776 INTEL_OUTPUT_FORMAT_YCBCR444,
779 struct intel_crtc_state {
781 * uapi (drm) state. This is the software state shown to userspace.
782 * In particular, the following members are used for bookkeeping:
790 struct drm_crtc_state uapi;
793 * actual hardware state, the state we program to the hardware.
794 * The following members are used to verify the hardware state:
797 * - mode / adjusted_mode
798 * - color property blobs.
800 * During initial hw readout, they need to be copied to uapi.
804 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
805 struct drm_display_mode mode, adjusted_mode;
809 * quirks - bitfield with hw state readout quirks
811 * For various reasons the hw state readout code might not be able to
812 * completely faithfully read out the current state. These cases are
813 * tracked with quirk flags so that fastboot and state checker can act
816 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
817 unsigned long quirks;
819 unsigned fb_bits; /* framebuffers to flip */
820 bool update_pipe; /* can a fast modeset be performed? */
822 bool update_wm_pre, update_wm_post; /* watermarks are updated */
823 bool fifo_changed; /* FIFO split is changed */
826 /* Pipe source size (ie. panel fitter input size)
827 * All planes will be positioned inside this space,
828 * and get clipped at the edges. */
829 int pipe_src_w, pipe_src_h;
832 * Pipe pixel rate, adjusted for
833 * panel fitter/pipe scaler downscaling.
835 unsigned int pixel_rate;
837 /* Whether to set up the PCH/FDI. Note that we never allow sharing
838 * between pch encoders and cpu encoders. */
839 bool has_pch_encoder;
841 /* Are we sending infoframes on the attached port */
844 /* CPU Transcoder for the pipe. Currently this can only differ from the
845 * pipe on Haswell and later (where we have a special eDP transcoder)
846 * and Broxton (where we have special DSI transcoders). */
847 enum transcoder cpu_transcoder;
850 * Use reduced/limited/broadcast rbg range, compressing from the full
851 * range fed into the crtcs.
853 bool limited_color_range;
855 /* Bitmask of encoder types (enum intel_output_type)
856 * driven by the pipe.
858 unsigned int output_types;
860 /* Whether we should send NULL infoframes. Required for audio. */
863 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
864 * has_dp_encoder is set. */
868 * Enable dithering, used when the selected pipe bpp doesn't match the
874 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
875 * compliance video pattern tests.
876 * Disable dither only if it is a compliance test request for
879 bool dither_force_disable;
881 /* Controls for the clock computation, to override various stages. */
884 /* SDVO TV has a bunch of special case. To make multifunction encoders
885 * work correctly, we need to track this at runtime.*/
889 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
890 * required. This is set in the 2nd loop of calling encoder's
891 * ->compute_config if the first pick doesn't work out.
895 /* Settings for the intel dpll used on pretty much everything but
899 /* Selected dpll when shared or NULL. */
900 struct intel_shared_dpll *shared_dpll;
902 /* Actual register state of the dpll, for shared dpll cross-checking. */
903 struct intel_dpll_hw_state dpll_hw_state;
906 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
907 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
909 struct icl_port_dpll {
910 struct intel_shared_dpll *pll;
911 struct intel_dpll_hw_state hw_state;
912 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
914 /* DSI PLL registers */
920 struct intel_link_m_n dp_m_n;
922 /* m2_n2 for eDP downclock */
923 struct intel_link_m_n dp_m2_n2;
931 * Frequence the dpll for the port should run at. Differs from the
932 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
933 * already multiplied by pixel_multiplier.
937 /* Used by SDVO (and if we ever fix it, HDMI). */
938 unsigned pixel_multiplier;
943 * Used by platforms having DP/HDMI PHY with programmable lane
944 * latency optimization.
946 u8 lane_lat_optim_mask;
948 /* minimum acceptable voltage level */
949 u8 min_voltage_level;
951 /* Panel fitter controls for gen2-gen4 + VLV */
955 u32 lvds_border_bits;
958 /* Panel fitter placement and size for Ironlake+ */
966 /* FDI configuration, only valid if has_pch_encoder is set. */
968 struct intel_link_m_n fdi_m_n;
980 struct intel_crtc_scaler_state scaler_state;
982 /* w/a for waiting 2 vblanks during crtc enable */
983 enum pipe hsw_workaround_pipe;
985 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
988 struct intel_crtc_wm_state wm;
990 int min_cdclk[I915_MAX_PLANES];
992 u32 data_rate[I915_MAX_PLANES];
994 /* Gamma mode programmed on the pipe */
998 /* CSC mode programmed on the pipe */
1005 /* bitmask of visible planes (enum plane_id) */
1010 /* bitmask of planes that will be updated during the commit */
1016 union hdmi_infoframe avi;
1017 union hdmi_infoframe spd;
1018 union hdmi_infoframe hdmi;
1019 union hdmi_infoframe drm;
1022 /* HDMI scrambling status */
1023 bool hdmi_scrambling;
1025 /* HDMI High TMDS char rate ratio */
1026 bool hdmi_high_tmds_clock_ratio;
1028 /* Output format RGB/YCBCR etc */
1029 enum intel_output_format output_format;
1031 /* Output down scaling is done in LSPCON device */
1032 bool lspcon_downsampling;
1034 /* enable pipe gamma? */
1037 /* enable pipe csc? */
1040 /* Display Stream compression state */
1042 bool compression_enable;
1046 struct drm_dsc_config config;
1049 /* Forward Error correction State */
1052 /* Pointer to master transcoder in case of tiled displays */
1053 enum transcoder master_transcoder;
1055 /* Bitmask to indicate slaves attached */
1056 u8 sync_mode_slaves_mask;
1060 struct drm_crtc base;
1063 * Whether the crtc and the connected output pipeline is active. Implies
1064 * that crtc->enabled is set, i.e. the current mode configuration has
1065 * some outputs connected to this crtc.
1069 unsigned long long enabled_power_domains;
1070 struct intel_overlay *overlay;
1072 struct intel_crtc_state *config;
1074 /* Access to these should be protected by dev_priv->irq_lock. */
1075 bool cpu_fifo_underrun_disabled;
1076 bool pch_fifo_underrun_disabled;
1078 /* per-pipe watermark state */
1080 /* watermarks currently being used */
1082 struct intel_pipe_wm ilk;
1083 struct vlv_wm_state vlv;
1084 struct g4x_wm_state g4x;
1088 int scanline_offset;
1091 unsigned start_vbl_count;
1092 ktime_t start_vbl_time;
1093 int min_vbl, max_vbl;
1097 /* scalers available on this crtc */
1100 /* per pipe DSB related info */
1101 struct intel_dsb dsb;
1104 struct intel_plane {
1105 struct drm_plane base;
1106 enum i9xx_plane_id i9xx_plane;
1111 u32 frontbuffer_bit;
1114 u32 base, cntl, size;
1118 * NOTE: Do not place new plane state fields here (e.g., when adding
1119 * new plane properties). New runtime state should now be placed in
1120 * the intel_plane_state structure and accessed via plane_state.
1123 unsigned int (*max_stride)(struct intel_plane *plane,
1124 u32 pixel_format, u64 modifier,
1125 unsigned int rotation);
1126 void (*update_plane)(struct intel_plane *plane,
1127 const struct intel_crtc_state *crtc_state,
1128 const struct intel_plane_state *plane_state);
1129 void (*disable_plane)(struct intel_plane *plane,
1130 const struct intel_crtc_state *crtc_state);
1131 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1132 int (*check_plane)(struct intel_crtc_state *crtc_state,
1133 struct intel_plane_state *plane_state);
1134 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1135 const struct intel_plane_state *plane_state);
1138 struct intel_watermark_params {
1146 struct cxsr_latency {
1147 bool is_desktop : 1;
1152 u16 display_hpll_disable;
1154 u16 cursor_hpll_disable;
1157 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1158 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1159 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1160 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1161 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1162 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1163 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1164 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1165 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1168 i915_reg_t hdmi_reg;
1171 enum drm_dp_dual_mode_type type;
1176 struct intel_connector *attached_connector;
1177 struct cec_notifier *cec_notifier;
1180 struct intel_dp_mst_encoder;
1181 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1184 * enum link_m_n_set:
1185 * When platform provides two set of M_N registers for dp, we can
1186 * program them and switch between them incase of DRRS.
1187 * But When only one such register is provided, we have to program the
1188 * required divider value on that registers itself based on the DRRS state.
1190 * M1_N1 : Program dp_m_n on M1_N1 registers
1191 * dp_m2_n2 on M2_N2 registers (If supported)
1193 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1194 * M2_N2 registers are not supported
1198 /* Sets the m1_n1 and m2_n2 */
1203 struct intel_dp_compliance_data {
1206 u16 hdisplay, vdisplay;
1210 struct intel_dp_compliance {
1211 unsigned long test_type;
1212 struct intel_dp_compliance_data test_data;
1219 i915_reg_t output_reg;
1227 bool reset_link_params;
1228 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1229 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1230 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1231 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1232 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1235 int num_source_rates;
1236 const int *source_rates;
1237 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1239 int sink_rates[DP_MAX_SUPPORTED_RATES];
1240 bool use_rate_select;
1241 /* intersection of source and sink rates */
1242 int num_common_rates;
1243 int common_rates[DP_MAX_SUPPORTED_RATES];
1244 /* Max lane count for the current link */
1245 int max_link_lane_count;
1246 /* Max rate for the current link */
1248 /* sink or branch descriptor */
1249 struct drm_dp_desc desc;
1250 struct drm_dp_aux aux;
1251 u32 aux_busy_last_status;
1253 int panel_power_up_delay;
1254 int panel_power_down_delay;
1255 int panel_power_cycle_delay;
1256 int backlight_on_delay;
1257 int backlight_off_delay;
1258 struct delayed_work panel_vdd_work;
1259 bool want_panel_vdd;
1260 unsigned long last_power_on;
1261 unsigned long last_backlight_off;
1262 ktime_t panel_power_off_time;
1264 struct notifier_block edp_notifier;
1267 * Pipe whose power sequencer is currently locked into
1268 * this port. Only relevant on VLV/CHV.
1272 * Pipe currently driving the port. Used for preventing
1273 * the use of the PPS for any pipe currentrly driving
1274 * external DP as that will mess things up on VLV.
1276 enum pipe active_pipe;
1278 * Set if the sequencer may be reset due to a power transition,
1279 * requiring a reinitialization. Only relevant on BXT.
1282 struct edp_power_seq pps_delays;
1284 bool can_mst; /* this port supports mst */
1286 int active_mst_links;
1289 * DP_TP_* registers may be either on port or transcoder register space.
1292 i915_reg_t dp_tp_ctl;
1293 i915_reg_t dp_tp_status;
1296 /* connector directly attached - won't be use for modeset in mst world */
1297 struct intel_connector *attached_connector;
1299 /* mst connector list */
1300 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1301 struct drm_dp_mst_topology_mgr mst_mgr;
1303 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1305 * This function returns the value we have to program the AUX_CTL
1306 * register with to kick off an AUX transaction.
1308 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1309 u32 aux_clock_divider);
1311 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1312 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1314 /* This is called before a link training is starterd */
1315 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1317 /* Displayport compliance testing */
1318 struct intel_dp_compliance compliance;
1320 /* Display stream compression testing */
1324 enum lspcon_vendor {
1326 LSPCON_VENDOR_PARADE
1329 struct intel_lspcon {
1331 enum drm_lspcon_mode mode;
1332 enum lspcon_vendor vendor;
1335 struct intel_digital_port {
1336 struct intel_encoder base;
1337 u32 saved_port_bits;
1339 struct intel_hdmi hdmi;
1340 struct intel_lspcon lspcon;
1341 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1342 bool release_cl2_override;
1344 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1346 enum intel_display_power_domain ddi_io_power_domain;
1347 struct mutex tc_lock; /* protects the TypeC port mode */
1348 intel_wakeref_t tc_lock_wakeref;
1349 int tc_link_refcount;
1350 bool tc_legacy_port:1;
1351 char tc_port_name[8];
1352 enum tc_port_mode tc_mode;
1353 enum phy_fia tc_phy_fia;
1356 void (*write_infoframe)(struct intel_encoder *encoder,
1357 const struct intel_crtc_state *crtc_state,
1359 const void *frame, ssize_t len);
1360 void (*read_infoframe)(struct intel_encoder *encoder,
1361 const struct intel_crtc_state *crtc_state,
1363 void *frame, ssize_t len);
1364 void (*set_infoframes)(struct intel_encoder *encoder,
1366 const struct intel_crtc_state *crtc_state,
1367 const struct drm_connector_state *conn_state);
1368 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1369 const struct intel_crtc_state *pipe_config);
1372 struct intel_dp_mst_encoder {
1373 struct intel_encoder base;
1375 struct intel_digital_port *primary;
1376 struct intel_connector *connector;
1379 static inline enum dpio_channel
1380 vlv_dport_to_channel(struct intel_digital_port *dport)
1382 switch (dport->base.port) {
1393 static inline enum dpio_phy
1394 vlv_dport_to_phy(struct intel_digital_port *dport)
1396 switch (dport->base.port) {
1407 static inline enum dpio_channel
1408 vlv_pipe_to_channel(enum pipe pipe)
1421 static inline struct intel_crtc *
1422 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1424 return dev_priv->pipe_to_crtc_mapping[pipe];
1427 static inline struct intel_crtc *
1428 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1430 return dev_priv->plane_to_crtc_mapping[plane];
1433 struct intel_load_detect_pipe {
1434 struct drm_atomic_state *restore_state;
1437 static inline struct intel_encoder *
1438 intel_attached_encoder(struct drm_connector *connector)
1440 return to_intel_connector(connector)->encoder;
1443 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1445 switch (encoder->type) {
1446 case INTEL_OUTPUT_DDI:
1447 case INTEL_OUTPUT_DP:
1448 case INTEL_OUTPUT_EDP:
1449 case INTEL_OUTPUT_HDMI:
1456 static inline struct intel_digital_port *
1457 enc_to_dig_port(struct drm_encoder *encoder)
1459 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1461 if (intel_encoder_is_dig_port(intel_encoder))
1462 return container_of(encoder, struct intel_digital_port,
1468 static inline struct intel_digital_port *
1469 conn_to_dig_port(struct intel_connector *connector)
1471 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1474 static inline struct intel_dp_mst_encoder *
1475 enc_to_mst(struct drm_encoder *encoder)
1477 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1480 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1482 return &enc_to_dig_port(encoder)->dp;
1485 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1487 switch (encoder->type) {
1488 case INTEL_OUTPUT_DP:
1489 case INTEL_OUTPUT_EDP:
1491 case INTEL_OUTPUT_DDI:
1492 /* Skip pure HDMI/DVI DDI encoders */
1493 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1499 static inline struct intel_lspcon *
1500 enc_to_intel_lspcon(struct drm_encoder *encoder)
1502 return &enc_to_dig_port(encoder)->lspcon;
1505 static inline struct intel_digital_port *
1506 dp_to_dig_port(struct intel_dp *intel_dp)
1508 return container_of(intel_dp, struct intel_digital_port, dp);
1511 static inline struct intel_lspcon *
1512 dp_to_lspcon(struct intel_dp *intel_dp)
1514 return &dp_to_dig_port(intel_dp)->lspcon;
1517 static inline struct drm_i915_private *
1518 dp_to_i915(struct intel_dp *intel_dp)
1520 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1523 static inline struct intel_digital_port *
1524 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1526 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1529 static inline struct intel_plane_state *
1530 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1531 struct intel_plane *plane)
1533 struct drm_plane_state *ret =
1534 drm_atomic_get_plane_state(&state->base, &plane->base);
1537 return ERR_CAST(ret);
1539 return to_intel_plane_state(ret);
1542 static inline struct intel_plane_state *
1543 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1544 struct intel_plane *plane)
1546 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1550 static inline struct intel_plane_state *
1551 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1552 struct intel_plane *plane)
1554 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1558 static inline struct intel_crtc_state *
1559 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1560 struct intel_crtc *crtc)
1562 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1566 static inline struct intel_crtc_state *
1567 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1568 struct intel_crtc *crtc)
1570 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1574 static inline struct intel_digital_connector_state *
1575 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1576 struct intel_connector *connector)
1578 return to_intel_digital_connector_state(
1579 drm_atomic_get_new_connector_state(&state->base,
1583 static inline struct intel_digital_connector_state *
1584 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1585 struct intel_connector *connector)
1587 return to_intel_digital_connector_state(
1588 drm_atomic_get_old_connector_state(&state->base,
1592 /* intel_display.c */
1594 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1595 enum intel_output_type type)
1597 return crtc_state->output_types & (1 << type);
1600 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1602 return crtc_state->output_types &
1603 ((1 << INTEL_OUTPUT_DP) |
1604 (1 << INTEL_OUTPUT_DP_MST) |
1605 (1 << INTEL_OUTPUT_EDP));
1608 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1610 drm_wait_one_vblank(&dev_priv->drm, pipe);
1613 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1615 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1618 intel_wait_for_vblank(dev_priv, pipe);
1621 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1623 return i915_ggtt_offset(state->vma);
1626 #endif /* __INTEL_DISPLAY_TYPES_H__ */