2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
50 struct __intel_global_objs_state;
53 * Display related stuff
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
92 /* for each plane in the normal GTT view */
96 /* for each plane in the rotated GTT view for no-CCS formats */
99 unsigned int pitch; /* pixels */
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
116 bool hpd_waiting : 1;
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
128 struct intel_encoder {
129 struct drm_encoder base;
131 enum intel_output_type type;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector);
137 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
138 struct intel_crtc_state *,
139 struct drm_connector_state *);
140 int (*compute_config)(struct intel_encoder *,
141 struct intel_crtc_state *,
142 struct drm_connector_state *);
143 int (*compute_config_late)(struct intel_encoder *,
144 struct intel_crtc_state *,
145 struct drm_connector_state *);
146 void (*update_prepare)(struct intel_atomic_state *,
147 struct intel_encoder *,
148 struct intel_crtc *);
149 void (*pre_pll_enable)(struct intel_atomic_state *,
150 struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*pre_enable)(struct intel_atomic_state *,
154 struct intel_encoder *,
155 const struct intel_crtc_state *,
156 const struct drm_connector_state *);
157 void (*enable)(struct intel_atomic_state *,
158 struct intel_encoder *,
159 const struct intel_crtc_state *,
160 const struct drm_connector_state *);
161 void (*update_complete)(struct intel_atomic_state *,
162 struct intel_encoder *,
163 struct intel_crtc *);
164 void (*disable)(struct intel_atomic_state *,
165 struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*post_disable)(struct intel_atomic_state *,
169 struct intel_encoder *,
170 const struct intel_crtc_state *,
171 const struct drm_connector_state *);
172 void (*post_pll_disable)(struct intel_atomic_state *,
173 struct intel_encoder *,
174 const struct intel_crtc_state *,
175 const struct drm_connector_state *);
176 void (*update_pipe)(struct intel_atomic_state *,
177 struct intel_encoder *,
178 const struct intel_crtc_state *,
179 const struct drm_connector_state *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
192 * Optional hook called during init/resume to sync any state
193 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
195 void (*sync_state)(struct intel_encoder *encoder,
196 const struct intel_crtc_state *crtc_state);
199 * Optional hook, returning true if this encoder allows a fastset
200 * during the initial commit, false otherwise.
202 bool (*initial_fastset_check)(struct intel_encoder *encoder,
203 struct intel_crtc_state *crtc_state);
206 * Acquires the power domains needed for an active encoder during
207 * hardware state readout.
209 void (*get_power_domains)(struct intel_encoder *encoder,
210 struct intel_crtc_state *crtc_state);
212 * Called during system suspend after all pending requests for the
213 * encoder are flushed (for example for DP AUX transactions) and
214 * device interrupts are disabled.
216 void (*suspend)(struct intel_encoder *);
218 * Called during system reboot/shutdown after all the
219 * encoders have been disabled and suspended.
221 void (*shutdown)(struct intel_encoder *encoder);
222 enum hpd_pin hpd_pin;
223 enum intel_display_power_domain power_domain;
224 /* for communication with audio component; protected by av_mutex */
225 const struct drm_connector *audio_connector;
228 struct intel_panel_bl_funcs {
229 /* Connector and platform specific backlight functions */
230 int (*setup)(struct intel_connector *connector, enum pipe pipe);
231 u32 (*get)(struct intel_connector *connector);
232 void (*set)(const struct drm_connector_state *conn_state, u32 level);
233 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
234 void (*enable)(const struct intel_crtc_state *crtc_state,
235 const struct drm_connector_state *conn_state, u32 level);
236 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
240 struct drm_display_mode *fixed_mode;
241 struct drm_display_mode *downclock_mode;
250 bool combination_mode; /* gen 2/4 only */
252 bool alternate_pwm_increment; /* lpt+ */
255 bool util_pin_active_low; /* bxt+ */
256 u8 controller; /* bxt+ only */
257 struct pwm_device *pwm;
258 struct pwm_state pwm_state;
263 struct backlight_device *device;
265 const struct intel_panel_bl_funcs *funcs;
266 void (*power)(struct intel_connector *, bool enable);
270 struct intel_digital_port;
272 enum check_link_response {
273 HDCP_LINK_PROTECTED = 0,
274 HDCP_TOPOLOGY_CHANGE,
275 HDCP_LINK_INTEGRITY_FAILURE,
280 * This structure serves as a translation layer between the generic HDCP code
281 * and the bus-specific code. What that means is that HDCP over HDMI differs
282 * from HDCP over DP, so to account for these differences, we need to
283 * communicate with the receiver through this shim.
285 * For completeness, the 2 buses differ in the following ways:
287 * HDCP registers on the receiver are set via DP AUX for DP, and
288 * they are set via DDC for HDMI.
289 * - Receiver register offsets
290 * The offsets of the registers are different for DP vs. HDMI
291 * - Receiver register masks/offsets
292 * For instance, the ready bit for the KSV fifo is in a different
293 * place on DP vs HDMI
294 * - Receiver register names
295 * Seriously. In the DP spec, the 16-bit register containing
296 * downstream information is called BINFO, on HDMI it's called
297 * BSTATUS. To confuse matters further, DP has a BSTATUS register
298 * with a completely different definition.
300 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
301 * be read 3 keys at a time
303 * Since Aksv is hidden in hardware, there's different procedures
304 * to send it over DP AUX vs DDC
306 struct intel_hdcp_shim {
307 /* Outputs the transmitter's An and Aksv values to the receiver. */
308 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
310 /* Reads the receiver's key selection vector */
311 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
314 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
315 * definitions are the same in the respective specs, but the names are
316 * different. Call it BSTATUS since that's the name the HDMI spec
317 * uses and it was there first.
319 int (*read_bstatus)(struct intel_digital_port *dig_port,
322 /* Determines whether a repeater is present downstream */
323 int (*repeater_present)(struct intel_digital_port *dig_port,
324 bool *repeater_present);
326 /* Reads the receiver's Ri' value */
327 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
329 /* Determines if the receiver's KSV FIFO is ready for consumption */
330 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
333 /* Reads the ksv fifo for num_downstream devices */
334 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
335 int num_downstream, u8 *ksv_fifo);
337 /* Reads a 32-bit part of V' from the receiver */
338 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
341 /* Enables HDCP signalling on the port */
342 int (*toggle_signalling)(struct intel_digital_port *dig_port,
343 enum transcoder cpu_transcoder,
346 /* Enable/Disable stream encryption on DP MST Transport Link */
347 int (*stream_encryption)(struct intel_connector *connector,
350 /* Ensures the link is still protected */
351 bool (*check_link)(struct intel_digital_port *dig_port,
352 struct intel_connector *connector);
354 /* Detects panel's hdcp capability. This is optional for HDMI. */
355 int (*hdcp_capable)(struct intel_digital_port *dig_port,
358 /* HDCP adaptation(DP/HDMI) required on the port */
359 enum hdcp_wired_protocol protocol;
361 /* Detects whether sink is HDCP2.2 capable */
362 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
365 /* Write HDCP2.2 messages */
366 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
367 void *buf, size_t size);
369 /* Read HDCP2.2 messages */
370 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
371 u8 msg_id, void *buf, size_t size);
374 * Implementation of DP HDCP2.2 Errata for the communication of stream
375 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
376 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
378 int (*config_stream_type)(struct intel_digital_port *dig_port,
379 bool is_repeater, u8 type);
381 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
382 int (*stream_2_2_encryption)(struct intel_connector *connector,
385 /* HDCP2.2 Link Integrity Check */
386 int (*check_2_2_link)(struct intel_digital_port *dig_port,
387 struct intel_connector *connector);
391 const struct intel_hdcp_shim *shim;
392 /* Mutex for hdcp state of the connector */
395 struct delayed_work check_work;
396 struct work_struct prop_work;
398 /* HDCP1.4 Encryption status */
401 /* HDCP2.2 related definitions */
402 /* Flag indicates whether this connector supports HDCP2.2 or not. */
403 bool hdcp2_supported;
405 /* HDCP2.2 Encryption status */
406 bool hdcp2_encrypted;
409 * Content Stream Type defined by content owner. TYPE0(0x0) content can
410 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
411 * content can flow only through a link protected by HDCP2.2.
419 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
420 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
421 * When it rolls over re-auth has to be triggered.
426 * Count of RepeaterAuth_Stream_Manage msg propagated.
427 * Initialized to 0 on AKE_INIT. Incremented after every successful
428 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
429 * over re-Auth has to be triggered.
434 * Work queue to signal the CP_IRQ. Used for the waiters to read the
435 * available information from HDCP DP sink.
437 wait_queue_head_t cp_irq_queue;
438 atomic_t cp_irq_count;
439 int cp_irq_count_cached;
442 * HDCP register access for gen12+ need the transcoder associated.
443 * Transcoder attached to the connector could be changed at modeset.
444 * Hence caching the transcoder here.
446 enum transcoder cpu_transcoder;
447 /* Only used for DP MST stream encryption */
448 enum transcoder stream_transcoder;
451 struct intel_connector {
452 struct drm_connector base;
454 * The fixed encoder this connector is connected to.
456 struct intel_encoder *encoder;
458 /* ACPI device id for ACPI and driver cooperation */
461 /* Reads out the current hw, returning true if the connector is enabled
462 * and active (i.e. dpms ON state). */
463 bool (*get_hw_state)(struct intel_connector *);
465 /* Panel info for eDP and LVDS */
466 struct intel_panel panel;
468 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
470 struct edid *detect_edid;
472 /* Number of times hotplug detection was tried after an HPD interrupt */
475 /* since POLL and HPD connectors may use the same HPD line keep the native
476 state of connector->polled in case hotplug storm detection changes it */
479 struct drm_dp_mst_port *port;
481 struct intel_dp *mst_port;
483 /* Work struct to schedule a uevent on link train failure */
484 struct work_struct modeset_retry_work;
486 struct intel_hdcp hdcp;
489 struct intel_digital_connector_state {
490 struct drm_connector_state base;
492 enum hdmi_force_audio force_audio;
496 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
510 struct intel_atomic_state {
511 struct drm_atomic_state base;
513 intel_wakeref_t wakeref;
515 struct __intel_global_objs_state *global_objs;
518 bool dpll_set, modeset;
520 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
523 * Current watermarks can't be trusted during hardware readout, so
524 * don't bother calculating intermediate watermarks.
526 bool skip_intermediate_wm;
528 bool rps_interactive;
530 struct i915_sw_fence commit_ready;
532 struct llist_node freed;
535 struct intel_plane_state {
536 struct drm_plane_state uapi;
539 * actual hardware state, the state we program to the hardware.
540 * The following members are used to verify the hardware state:
541 * During initial hw readout, they need to be copied from uapi.
544 struct drm_crtc *crtc;
545 struct drm_framebuffer *fb;
548 u16 pixel_blend_mode;
549 unsigned int rotation;
550 enum drm_color_encoding color_encoding;
551 enum drm_color_range color_range;
552 enum drm_scaling_filter scaling_filter;
555 struct i915_ggtt_view view;
556 struct i915_vma *vma;
558 #define PLANE_HAS_FENCE BIT(0)
564 * bytes for 0/180 degree rotation
565 * pixels for 90/270 degree rotation
571 /* plane control register */
574 /* plane color control register */
577 /* chroma upsampler control register */
582 * = -1 : not using a scaler
583 * >= 0 : using a scalers
585 * plane requiring a scaler:
586 * - During check_plane, its bit is set in
587 * crtc_state->scaler_state.scaler_users by calling helper function
588 * update_scaler_plane.
589 * - scaler_id indicates the scaler it got assigned.
591 * plane doesn't require a scaler:
592 * - this can happen when scaling is no more required or plane simply
594 * - During check_plane, corresponding bit is reset in
595 * crtc_state->scaler_state.scaler_users by calling helper function
596 * update_scaler_plane.
601 * planar_linked_plane:
603 * ICL planar formats require 2 planes that are updated as pairs.
604 * This member is used to make sure the other plane is also updated
605 * when required, and for update_slave() to find the correct
606 * plane_state to pass as argument.
608 struct intel_plane *planar_linked_plane;
612 * If set don't update use the linked plane's state for updating
613 * this plane during atomic commit with the update_slave() callback.
615 * It's also used by the watermark code to ignore wm calculations on
616 * this plane. They're calculated by the linked plane's wm code.
620 struct drm_intel_sprite_colorkey ckey;
622 struct drm_rect psr2_sel_fetch_area;
625 struct intel_initial_plane_config {
626 struct intel_framebuffer *fb;
627 struct i915_vma *vma;
634 struct intel_scaler {
639 struct intel_crtc_scaler_state {
640 #define SKL_NUM_SCALERS 2
641 struct intel_scaler scalers[SKL_NUM_SCALERS];
644 * scaler_users: keeps track of users requesting scalers on this crtc.
646 * If a bit is set, a user is using a scaler.
647 * Here user can be a plane or crtc as defined below:
648 * bits 0-30 - plane (bit position is index from drm_plane_index)
651 * Instead of creating a new index to cover planes and crtc, using
652 * existing drm_plane_index for planes which is well less than 31
653 * planes and bit 31 for crtc. This should be fine to cover all
656 * intel_atomic_setup_scalers will setup available scalers to users
657 * requesting scalers. It will gracefully fail if request exceeds
660 #define SKL_CRTC_INDEX 31
661 unsigned scaler_users;
663 /* scaler used by crtc for panel fitting purpose */
667 /* {crtc,crtc_state}->mode_flags */
668 /* Flag to get scanline using frame time stamps */
669 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
670 /* Flag to use the scanline counter instead of the pixel counter */
671 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
673 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
674 * is operating in command mode.
675 * Flag to use TE from DSI0 instead of VBI in command mode
677 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
678 /* Flag to use TE from DSI1 instead of VBI in command mode */
679 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
680 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
681 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
683 struct intel_wm_level {
691 struct intel_pipe_wm {
692 struct intel_wm_level wm[5];
695 bool sprites_enabled;
699 struct skl_wm_level {
708 struct skl_plane_wm {
709 struct skl_wm_level wm[8];
710 struct skl_wm_level uv_wm[8];
711 struct skl_wm_level trans_wm;
712 struct skl_wm_level sagv_wm0;
717 struct skl_plane_wm planes[I915_MAX_PLANES];
724 VLV_WM_LEVEL_DDR_DVFS,
728 struct vlv_wm_state {
729 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
730 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
735 struct vlv_fifo_state {
736 u16 plane[I915_MAX_PLANES];
746 struct g4x_wm_state {
747 struct g4x_pipe_wm wm;
749 struct g4x_sr_wm hpll;
755 struct intel_crtc_wm_state {
759 * The "raw" watermark values produced by the formula
760 * given the plane's current state. They do not consider
761 * how much FIFO is actually allocated for each plane.
764 * The "optimal" watermark values given the current
765 * state of the planes and the amount of FIFO
766 * allocated to each, ignoring any previous state
770 * The "intermediate" watermark values when transitioning
771 * between the old and new "optimal" values. Used when
772 * the watermark registers are single buffered and hence
773 * their state changes asynchronously with regards to the
774 * actual plane registers. These are essentially the
775 * worst case combination of the old and new "optimal"
776 * watermarks, which are therefore safe to use when the
777 * plane is in either its old or new state.
780 struct intel_pipe_wm intermediate;
781 struct intel_pipe_wm optimal;
785 struct skl_pipe_wm raw;
786 /* gen9+ only needs 1-step wm programming */
787 struct skl_pipe_wm optimal;
788 struct skl_ddb_entry ddb;
789 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
790 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
794 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
795 struct vlv_wm_state intermediate; /* inverted */
796 struct vlv_wm_state optimal; /* inverted */
797 struct vlv_fifo_state fifo_state;
801 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
802 struct g4x_wm_state intermediate;
803 struct g4x_wm_state optimal;
808 * Platforms with two-step watermark programming will need to
809 * update watermark programming post-vblank to switch from the
810 * safe intermediate watermarks to the optimal final
813 bool need_postvbl_update;
816 enum intel_output_format {
817 INTEL_OUTPUT_FORMAT_INVALID,
818 INTEL_OUTPUT_FORMAT_RGB,
819 INTEL_OUTPUT_FORMAT_YCBCR420,
820 INTEL_OUTPUT_FORMAT_YCBCR444,
823 struct intel_crtc_state {
825 * uapi (drm) state. This is the software state shown to userspace.
826 * In particular, the following members are used for bookkeeping:
834 struct drm_crtc_state uapi;
837 * actual hardware state, the state we program to the hardware.
838 * The following members are used to verify the hardware state:
841 * - mode / pipe_mode / adjusted_mode
842 * - color property blobs.
844 * During initial hw readout, they need to be copied to uapi.
846 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
847 * Use the pipe_mode for calculations like watermarks, pipe
848 * scaler, and bandwidth.
850 * Use adjusted_mode for things that need to know the full
851 * mode on the transcoder, which spans all pipes.
855 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
856 struct drm_display_mode mode, pipe_mode, adjusted_mode;
857 enum drm_scaling_filter scaling_filter;
861 * quirks - bitfield with hw state readout quirks
863 * For various reasons the hw state readout code might not be able to
864 * completely faithfully read out the current state. These cases are
865 * tracked with quirk flags so that fastboot and state checker can act
868 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
869 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
870 unsigned long quirks;
872 unsigned fb_bits; /* framebuffers to flip */
873 bool update_pipe; /* can a fast modeset be performed? */
875 bool update_wm_pre, update_wm_post; /* watermarks are updated */
876 bool fifo_changed; /* FIFO split is changed */
878 bool inherited; /* state inherited from BIOS? */
880 /* Pipe source size (ie. panel fitter input size)
881 * All planes will be positioned inside this space,
882 * and get clipped at the edges. */
883 int pipe_src_w, pipe_src_h;
886 * Pipe pixel rate, adjusted for
887 * panel fitter/pipe scaler downscaling.
889 unsigned int pixel_rate;
891 /* Whether to set up the PCH/FDI. Note that we never allow sharing
892 * between pch encoders and cpu encoders. */
893 bool has_pch_encoder;
895 /* Are we sending infoframes on the attached port */
898 /* CPU Transcoder for the pipe. Currently this can only differ from the
899 * pipe on Haswell and later (where we have a special eDP transcoder)
900 * and Broxton (where we have special DSI transcoders). */
901 enum transcoder cpu_transcoder;
904 * Use reduced/limited/broadcast rbg range, compressing from the full
905 * range fed into the crtcs.
907 bool limited_color_range;
909 /* Bitmask of encoder types (enum intel_output_type)
910 * driven by the pipe.
912 unsigned int output_types;
914 /* Whether we should send NULL infoframes. Required for audio. */
917 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
918 * has_dp_encoder is set. */
922 * Enable dithering, used when the selected pipe bpp doesn't match the
928 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
929 * compliance video pattern tests.
930 * Disable dither only if it is a compliance test request for
933 bool dither_force_disable;
935 /* Controls for the clock computation, to override various stages. */
938 /* SDVO TV has a bunch of special case. To make multifunction encoders
939 * work correctly, we need to track this at runtime.*/
943 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
944 * required. This is set in the 2nd loop of calling encoder's
945 * ->compute_config if the first pick doesn't work out.
949 /* Settings for the intel dpll used on pretty much everything but
953 /* Selected dpll when shared or NULL. */
954 struct intel_shared_dpll *shared_dpll;
956 /* Actual register state of the dpll, for shared dpll cross-checking. */
957 struct intel_dpll_hw_state dpll_hw_state;
960 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
961 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
963 struct icl_port_dpll {
964 struct intel_shared_dpll *pll;
965 struct intel_dpll_hw_state hw_state;
966 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
968 /* DSI PLL registers */
974 struct intel_link_m_n dp_m_n;
976 /* m2_n2 for eDP downclock */
977 struct intel_link_m_n dp_m2_n2;
982 bool enable_psr2_sel_fetch;
986 * Frequence the dpll for the port should run at. Differs from the
987 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
988 * already multiplied by pixel_multiplier.
992 /* Used by SDVO (and if we ever fix it, HDMI). */
993 unsigned pixel_multiplier;
995 /* I915_MODE_FLAG_* */
1001 * Used by platforms having DP/HDMI PHY with programmable lane
1002 * latency optimization.
1004 u8 lane_lat_optim_mask;
1006 /* minimum acceptable voltage level */
1007 u8 min_voltage_level;
1009 /* Panel fitter controls for gen2-gen4 + VLV */
1013 u32 lvds_border_bits;
1016 /* Panel fitter placement and size for Ironlake+ */
1018 struct drm_rect dst;
1023 /* FDI configuration, only valid if has_pch_encoder is set. */
1025 struct intel_link_m_n fdi_m_n;
1037 struct intel_crtc_scaler_state scaler_state;
1039 /* w/a for waiting 2 vblanks during crtc enable */
1040 enum pipe hsw_workaround_pipe;
1042 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1045 struct intel_crtc_wm_state wm;
1047 int min_cdclk[I915_MAX_PLANES];
1049 u32 data_rate[I915_MAX_PLANES];
1051 /* FIXME unify with data_rate[] */
1052 u64 plane_data_rate[I915_MAX_PLANES];
1053 u64 uv_plane_data_rate[I915_MAX_PLANES];
1055 /* Gamma mode programmed on the pipe */
1059 /* CSC mode programmed on the pipe */
1066 /* bitmask of logically enabled planes (enum plane_id) */
1069 /* bitmask of actually visible planes (enum plane_id) */
1074 /* bitmask of planes that will be updated during the commit */
1080 union hdmi_infoframe avi;
1081 union hdmi_infoframe spd;
1082 union hdmi_infoframe hdmi;
1083 union hdmi_infoframe drm;
1084 struct drm_dp_vsc_sdp vsc;
1087 /* HDMI scrambling status */
1088 bool hdmi_scrambling;
1090 /* HDMI High TMDS char rate ratio */
1091 bool hdmi_high_tmds_clock_ratio;
1093 /* Output format RGB/YCBCR etc */
1094 enum intel_output_format output_format;
1096 /* enable pipe gamma? */
1099 /* enable pipe csc? */
1102 /* enable pipe big joiner? */
1105 /* big joiner slave crtc? */
1106 bool bigjoiner_slave;
1108 /* linked crtc for bigjoiner, either slave or master */
1109 struct intel_crtc *bigjoiner_linked_crtc;
1111 /* Display Stream compression state */
1113 bool compression_enable;
1117 struct drm_dsc_config config;
1120 /* HSW+ linetime watermarks */
1124 /* Forward Error correction State */
1127 /* Pointer to master transcoder in case of tiled displays */
1128 enum transcoder master_transcoder;
1130 /* Bitmask to indicate slaves attached */
1131 u8 sync_mode_slaves_mask;
1133 /* Only valid on TGL+ */
1134 enum transcoder mst_master_transcoder;
1136 /* For DSB related info */
1137 struct intel_dsb *dsb;
1139 u32 psr2_man_track_ctl;
1142 enum intel_pipe_crc_source {
1143 INTEL_PIPE_CRC_SOURCE_NONE,
1144 INTEL_PIPE_CRC_SOURCE_PLANE1,
1145 INTEL_PIPE_CRC_SOURCE_PLANE2,
1146 INTEL_PIPE_CRC_SOURCE_PLANE3,
1147 INTEL_PIPE_CRC_SOURCE_PLANE4,
1148 INTEL_PIPE_CRC_SOURCE_PLANE5,
1149 INTEL_PIPE_CRC_SOURCE_PLANE6,
1150 INTEL_PIPE_CRC_SOURCE_PLANE7,
1151 INTEL_PIPE_CRC_SOURCE_PIPE,
1152 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1153 INTEL_PIPE_CRC_SOURCE_TV,
1154 INTEL_PIPE_CRC_SOURCE_DP_B,
1155 INTEL_PIPE_CRC_SOURCE_DP_C,
1156 INTEL_PIPE_CRC_SOURCE_DP_D,
1157 INTEL_PIPE_CRC_SOURCE_AUTO,
1158 INTEL_PIPE_CRC_SOURCE_MAX,
1161 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1162 struct intel_pipe_crc {
1165 enum intel_pipe_crc_source source;
1169 struct drm_crtc base;
1172 * Whether the crtc and the connected output pipeline is active. Implies
1173 * that crtc->enabled is set, i.e. the current mode configuration has
1174 * some outputs connected to this crtc.
1179 /* I915_MODE_FLAG_* */
1182 struct intel_display_power_domain_set enabled_power_domains;
1183 struct intel_overlay *overlay;
1185 struct intel_crtc_state *config;
1187 /* Access to these should be protected by dev_priv->irq_lock. */
1188 bool cpu_fifo_underrun_disabled;
1189 bool pch_fifo_underrun_disabled;
1191 /* per-pipe watermark state */
1193 /* watermarks currently being used */
1195 struct intel_pipe_wm ilk;
1196 struct vlv_wm_state vlv;
1197 struct g4x_wm_state g4x;
1201 int scanline_offset;
1204 unsigned start_vbl_count;
1205 ktime_t start_vbl_time;
1206 int min_vbl, max_vbl;
1208 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1214 unsigned int times[17]; /* [1us, 16ms] */
1219 /* scalers available on this crtc */
1222 #ifdef CONFIG_DEBUG_FS
1223 struct intel_pipe_crc pipe_crc;
1227 struct intel_plane {
1228 struct drm_plane base;
1229 enum i9xx_plane_id i9xx_plane;
1234 u32 frontbuffer_bit;
1237 u32 base, cntl, size;
1241 * NOTE: Do not place new plane state fields here (e.g., when adding
1242 * new plane properties). New runtime state should now be placed in
1243 * the intel_plane_state structure and accessed via plane_state.
1246 int (*min_width)(const struct drm_framebuffer *fb,
1248 unsigned int rotation);
1249 int (*max_width)(const struct drm_framebuffer *fb,
1251 unsigned int rotation);
1252 int (*max_height)(const struct drm_framebuffer *fb,
1254 unsigned int rotation);
1255 unsigned int (*max_stride)(struct intel_plane *plane,
1256 u32 pixel_format, u64 modifier,
1257 unsigned int rotation);
1258 void (*update_plane)(struct intel_plane *plane,
1259 const struct intel_crtc_state *crtc_state,
1260 const struct intel_plane_state *plane_state);
1261 void (*disable_plane)(struct intel_plane *plane,
1262 const struct intel_crtc_state *crtc_state);
1263 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1264 int (*check_plane)(struct intel_crtc_state *crtc_state,
1265 struct intel_plane_state *plane_state);
1266 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1267 const struct intel_plane_state *plane_state);
1268 void (*async_flip)(struct intel_plane *plane,
1269 const struct intel_crtc_state *crtc_state,
1270 const struct intel_plane_state *plane_state);
1273 struct intel_watermark_params {
1281 struct cxsr_latency {
1282 bool is_desktop : 1;
1287 u16 display_hpll_disable;
1289 u16 cursor_hpll_disable;
1292 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1293 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1294 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1295 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1296 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1297 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1298 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1299 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1300 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1303 i915_reg_t hdmi_reg;
1306 enum drm_dp_dual_mode_type type;
1311 struct intel_connector *attached_connector;
1312 struct cec_notifier *cec_notifier;
1315 struct intel_dp_mst_encoder;
1317 * enum link_m_n_set:
1318 * When platform provides two set of M_N registers for dp, we can
1319 * program them and switch between them incase of DRRS.
1320 * But When only one such register is provided, we have to program the
1321 * required divider value on that registers itself based on the DRRS state.
1323 * M1_N1 : Program dp_m_n on M1_N1 registers
1324 * dp_m2_n2 on M2_N2 registers (If supported)
1326 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1327 * M2_N2 registers are not supported
1331 /* Sets the m1_n1 and m2_n2 */
1336 struct intel_dp_compliance_data {
1339 u16 hdisplay, vdisplay;
1341 struct drm_dp_phy_test_params phytest;
1344 struct intel_dp_compliance {
1345 unsigned long test_type;
1346 struct intel_dp_compliance_data test_data;
1352 struct intel_dp_pcon_frl {
1354 int trained_rate_gbps;
1358 i915_reg_t output_reg;
1366 bool reset_link_params;
1367 bool use_max_params;
1368 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1369 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1370 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1371 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1372 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1373 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1374 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1376 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1378 int num_source_rates;
1379 const int *source_rates;
1380 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1382 int sink_rates[DP_MAX_SUPPORTED_RATES];
1383 bool use_rate_select;
1384 /* intersection of source and sink rates */
1385 int num_common_rates;
1386 int common_rates[DP_MAX_SUPPORTED_RATES];
1387 /* Max lane count for the current link */
1388 int max_link_lane_count;
1389 /* Max rate for the current link */
1391 /* sink or branch descriptor */
1392 struct drm_dp_desc desc;
1394 struct drm_dp_aux aux;
1395 u32 aux_busy_last_status;
1397 int panel_power_up_delay;
1398 int panel_power_down_delay;
1399 int panel_power_cycle_delay;
1400 int backlight_on_delay;
1401 int backlight_off_delay;
1402 struct delayed_work panel_vdd_work;
1403 bool want_panel_vdd;
1404 unsigned long last_power_on;
1405 unsigned long last_backlight_off;
1406 ktime_t panel_power_off_time;
1407 intel_wakeref_t vdd_wakeref;
1410 * Pipe whose power sequencer is currently locked into
1411 * this port. Only relevant on VLV/CHV.
1415 * Pipe currently driving the port. Used for preventing
1416 * the use of the PPS for any pipe currentrly driving
1417 * external DP as that will mess things up on VLV.
1419 enum pipe active_pipe;
1421 * Set if the sequencer may be reset due to a power transition,
1422 * requiring a reinitialization. Only relevant on BXT.
1425 struct edp_power_seq pps_delays;
1427 bool can_mst; /* this port supports mst */
1429 int active_mst_links;
1431 /* connector directly attached - won't be use for modeset in mst world */
1432 struct intel_connector *attached_connector;
1434 /* mst connector list */
1435 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1436 struct drm_dp_mst_topology_mgr mst_mgr;
1438 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1440 * This function returns the value we have to program the AUX_CTL
1441 * register with to kick off an AUX transaction.
1443 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1444 u32 aux_clock_divider);
1446 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1447 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1449 /* This is called before a link training is starterd */
1450 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1451 const struct intel_crtc_state *crtc_state);
1452 void (*set_link_train)(struct intel_dp *intel_dp,
1453 const struct intel_crtc_state *crtc_state,
1455 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1456 const struct intel_crtc_state *crtc_state);
1457 void (*set_signal_levels)(struct intel_dp *intel_dp,
1458 const struct intel_crtc_state *crtc_state);
1460 u8 (*preemph_max)(struct intel_dp *intel_dp);
1461 u8 (*voltage_max)(struct intel_dp *intel_dp,
1462 const struct intel_crtc_state *crtc_state);
1464 /* Displayport compliance testing */
1465 struct intel_dp_compliance compliance;
1467 /* Downstream facing port caps */
1469 int min_tmds_clock, max_tmds_clock;
1471 int pcon_max_frl_bw;
1473 bool ycbcr_444_to_420;
1477 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1478 struct pm_qos_request pm_qos;
1480 /* Display stream compression testing */
1486 struct intel_dp_pcon_frl frl;
1489 enum lspcon_vendor {
1491 LSPCON_VENDOR_PARADE
1494 struct intel_lspcon {
1497 enum drm_lspcon_mode mode;
1498 enum lspcon_vendor vendor;
1501 struct intel_digital_port {
1502 struct intel_encoder base;
1503 u32 saved_port_bits;
1505 struct intel_hdmi hdmi;
1506 struct intel_lspcon lspcon;
1507 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1508 bool release_cl2_override;
1510 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1512 enum intel_display_power_domain ddi_io_power_domain;
1513 intel_wakeref_t ddi_io_wakeref;
1514 intel_wakeref_t aux_wakeref;
1515 struct mutex tc_lock; /* protects the TypeC port mode */
1516 intel_wakeref_t tc_lock_wakeref;
1517 int tc_link_refcount;
1518 bool tc_legacy_port:1;
1519 char tc_port_name[8];
1520 enum tc_port_mode tc_mode;
1521 enum phy_fia tc_phy_fia;
1524 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1525 struct mutex hdcp_mutex;
1526 /* the number of pipes using HDCP signalling out of this port */
1527 unsigned int num_hdcp_streams;
1528 /* port HDCP auth status */
1529 bool hdcp_auth_status;
1530 /* HDCP port data need to pass to security f/w */
1531 struct hdcp_port_data hdcp_port_data;
1533 void (*write_infoframe)(struct intel_encoder *encoder,
1534 const struct intel_crtc_state *crtc_state,
1536 const void *frame, ssize_t len);
1537 void (*read_infoframe)(struct intel_encoder *encoder,
1538 const struct intel_crtc_state *crtc_state,
1540 void *frame, ssize_t len);
1541 void (*set_infoframes)(struct intel_encoder *encoder,
1543 const struct intel_crtc_state *crtc_state,
1544 const struct drm_connector_state *conn_state);
1545 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1546 const struct intel_crtc_state *pipe_config);
1547 bool (*connected)(struct intel_encoder *encoder);
1550 struct intel_dp_mst_encoder {
1551 struct intel_encoder base;
1553 struct intel_digital_port *primary;
1554 struct intel_connector *connector;
1557 static inline enum dpio_channel
1558 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1560 switch (dig_port->base.port) {
1571 static inline enum dpio_phy
1572 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1574 switch (dig_port->base.port) {
1585 static inline enum dpio_channel
1586 vlv_pipe_to_channel(enum pipe pipe)
1599 static inline struct intel_crtc *
1600 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1602 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1605 static inline struct intel_crtc *
1606 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1608 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1609 drm_WARN_ON(&dev_priv->drm,
1610 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1611 return dev_priv->pipe_to_crtc_mapping[pipe];
1614 static inline struct intel_crtc *
1615 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1617 return dev_priv->plane_to_crtc_mapping[plane];
1620 struct intel_load_detect_pipe {
1621 struct drm_atomic_state *restore_state;
1624 static inline struct intel_encoder *
1625 intel_attached_encoder(struct intel_connector *connector)
1627 return connector->encoder;
1630 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1632 switch (encoder->type) {
1633 case INTEL_OUTPUT_DDI:
1634 case INTEL_OUTPUT_DP:
1635 case INTEL_OUTPUT_EDP:
1636 case INTEL_OUTPUT_HDMI:
1643 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1645 return encoder->type == INTEL_OUTPUT_DP_MST;
1648 static inline struct intel_dp_mst_encoder *
1649 enc_to_mst(struct intel_encoder *encoder)
1651 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1655 static inline struct intel_digital_port *
1656 enc_to_dig_port(struct intel_encoder *encoder)
1658 struct intel_encoder *intel_encoder = encoder;
1660 if (intel_encoder_is_dig_port(intel_encoder))
1661 return container_of(&encoder->base, struct intel_digital_port,
1663 else if (intel_encoder_is_mst(intel_encoder))
1664 return enc_to_mst(encoder)->primary;
1669 static inline struct intel_digital_port *
1670 intel_attached_dig_port(struct intel_connector *connector)
1672 return enc_to_dig_port(intel_attached_encoder(connector));
1675 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1677 return &enc_to_dig_port(encoder)->dp;
1680 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1682 return enc_to_intel_dp(intel_attached_encoder(connector));
1685 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1687 switch (encoder->type) {
1688 case INTEL_OUTPUT_DP:
1689 case INTEL_OUTPUT_EDP:
1691 case INTEL_OUTPUT_DDI:
1692 /* Skip pure HDMI/DVI DDI encoders */
1693 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1699 static inline struct intel_lspcon *
1700 enc_to_intel_lspcon(struct intel_encoder *encoder)
1702 return &enc_to_dig_port(encoder)->lspcon;
1705 static inline struct intel_digital_port *
1706 dp_to_dig_port(struct intel_dp *intel_dp)
1708 return container_of(intel_dp, struct intel_digital_port, dp);
1711 static inline struct intel_lspcon *
1712 dp_to_lspcon(struct intel_dp *intel_dp)
1714 return &dp_to_dig_port(intel_dp)->lspcon;
1717 static inline struct drm_i915_private *
1718 dp_to_i915(struct intel_dp *intel_dp)
1720 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1723 static inline struct intel_digital_port *
1724 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1726 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1729 static inline struct intel_plane_state *
1730 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1731 struct intel_plane *plane)
1733 struct drm_plane_state *ret =
1734 drm_atomic_get_plane_state(&state->base, &plane->base);
1737 return ERR_CAST(ret);
1739 return to_intel_plane_state(ret);
1742 static inline struct intel_plane_state *
1743 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1744 struct intel_plane *plane)
1746 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1750 static inline struct intel_plane_state *
1751 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1752 struct intel_plane *plane)
1754 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1758 static inline struct intel_crtc_state *
1759 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1760 struct intel_crtc *crtc)
1762 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1766 static inline struct intel_crtc_state *
1767 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1768 struct intel_crtc *crtc)
1770 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1774 static inline struct intel_digital_connector_state *
1775 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1776 struct intel_connector *connector)
1778 return to_intel_digital_connector_state(
1779 drm_atomic_get_new_connector_state(&state->base,
1783 static inline struct intel_digital_connector_state *
1784 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1785 struct intel_connector *connector)
1787 return to_intel_digital_connector_state(
1788 drm_atomic_get_old_connector_state(&state->base,
1792 /* intel_display.c */
1794 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1795 enum intel_output_type type)
1797 return crtc_state->output_types & (1 << type);
1800 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1802 return crtc_state->output_types &
1803 ((1 << INTEL_OUTPUT_DP) |
1804 (1 << INTEL_OUTPUT_DP_MST) |
1805 (1 << INTEL_OUTPUT_EDP));
1809 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
1811 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1815 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1817 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1819 drm_crtc_wait_one_vblank(&crtc->base);
1823 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1825 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1828 intel_wait_for_vblank(dev_priv, pipe);
1831 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1833 return i915_ggtt_offset(state->vma);
1836 static inline struct intel_frontbuffer *
1837 to_intel_frontbuffer(struct drm_framebuffer *fb)
1839 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
1842 #endif /* __INTEL_DISPLAY_TYPES_H__ */