drivers/gpu/drm/i915/display/intel_display_power.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DISPLAY_POWER_H__
   7 #define __INTEL_DISPLAY_POWER_H__
   8
   9 #include "intel_display.h"
  10 #include "intel_runtime_pm.h"
  11 #include "i915_reg.h"
  12
  13 struct drm_i915_private;
  14 struct intel_encoder;
  15
  16 enum intel_display_power_domain {
  17         POWER_DOMAIN_DISPLAY_CORE,
  18         POWER_DOMAIN_PIPE_A,
  19         POWER_DOMAIN_PIPE_B,
  20         POWER_DOMAIN_PIPE_C,
  21         POWER_DOMAIN_PIPE_D,
  22         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  23         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  24         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  25         POWER_DOMAIN_PIPE_D_PANEL_FITTER,
  26         POWER_DOMAIN_TRANSCODER_A,
  27         POWER_DOMAIN_TRANSCODER_B,
  28         POWER_DOMAIN_TRANSCODER_C,
  29         POWER_DOMAIN_TRANSCODER_D,
  30         POWER_DOMAIN_TRANSCODER_EDP,
  31         /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
  32         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
  33         POWER_DOMAIN_TRANSCODER_DSI_A,
  34         POWER_DOMAIN_TRANSCODER_DSI_C,
  35         POWER_DOMAIN_PORT_DDI_A_LANES,
  36         POWER_DOMAIN_PORT_DDI_B_LANES,
  37         POWER_DOMAIN_PORT_DDI_C_LANES,
  38         POWER_DOMAIN_PORT_DDI_D_LANES,
  39         POWER_DOMAIN_PORT_DDI_E_LANES,
  40         POWER_DOMAIN_PORT_DDI_F_LANES,
  41         POWER_DOMAIN_PORT_DDI_G_LANES,
  42         POWER_DOMAIN_PORT_DDI_H_LANES,
  43         POWER_DOMAIN_PORT_DDI_I_LANES,
  44
  45         POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */
  46         POWER_DOMAIN_PORT_DDI_LANES_TC2,
  47         POWER_DOMAIN_PORT_DDI_LANES_TC3,
  48         POWER_DOMAIN_PORT_DDI_LANES_TC4,
  49         POWER_DOMAIN_PORT_DDI_LANES_TC5,
  50         POWER_DOMAIN_PORT_DDI_LANES_TC6,
  51
  52         POWER_DOMAIN_PORT_DDI_A_IO,
  53         POWER_DOMAIN_PORT_DDI_B_IO,
  54         POWER_DOMAIN_PORT_DDI_C_IO,
  55         POWER_DOMAIN_PORT_DDI_D_IO,
  56         POWER_DOMAIN_PORT_DDI_E_IO,
  57         POWER_DOMAIN_PORT_DDI_F_IO,
  58         POWER_DOMAIN_PORT_DDI_G_IO,
  59         POWER_DOMAIN_PORT_DDI_H_IO,
  60         POWER_DOMAIN_PORT_DDI_I_IO,
  61
  62         POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */
  63         POWER_DOMAIN_PORT_DDI_IO_TC2,
  64         POWER_DOMAIN_PORT_DDI_IO_TC3,
  65         POWER_DOMAIN_PORT_DDI_IO_TC4,
  66         POWER_DOMAIN_PORT_DDI_IO_TC5,
  67         POWER_DOMAIN_PORT_DDI_IO_TC6,
  68
  69         POWER_DOMAIN_PORT_DSI,
  70         POWER_DOMAIN_PORT_CRT,
  71         POWER_DOMAIN_PORT_OTHER,
  72         POWER_DOMAIN_VGA,
  73         POWER_DOMAIN_AUDIO,
  74         POWER_DOMAIN_AUX_A,
  75         POWER_DOMAIN_AUX_B,
  76         POWER_DOMAIN_AUX_C,
  77         POWER_DOMAIN_AUX_D,
  78         POWER_DOMAIN_AUX_E,
  79         POWER_DOMAIN_AUX_F,
  80         POWER_DOMAIN_AUX_G,
  81         POWER_DOMAIN_AUX_H,
  82         POWER_DOMAIN_AUX_I,
  83
  84         POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */
  85         POWER_DOMAIN_AUX_USBC2,
  86         POWER_DOMAIN_AUX_USBC3,
  87         POWER_DOMAIN_AUX_USBC4,
  88         POWER_DOMAIN_AUX_USBC5,
  89         POWER_DOMAIN_AUX_USBC6,
  90
  91         POWER_DOMAIN_AUX_IO_A,
  92         POWER_DOMAIN_AUX_C_TBT,
  93         POWER_DOMAIN_AUX_D_TBT,
  94         POWER_DOMAIN_AUX_E_TBT,
  95         POWER_DOMAIN_AUX_F_TBT,
  96         POWER_DOMAIN_AUX_G_TBT,
  97         POWER_DOMAIN_AUX_H_TBT,
  98         POWER_DOMAIN_AUX_I_TBT,
  99
 100         POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */
 101         POWER_DOMAIN_AUX_TBT2,
 102         POWER_DOMAIN_AUX_TBT3,
 103         POWER_DOMAIN_AUX_TBT4,
 104         POWER_DOMAIN_AUX_TBT5,
 105         POWER_DOMAIN_AUX_TBT6,
 106
 107         POWER_DOMAIN_GMBUS,
 108         POWER_DOMAIN_MODESET,
 109         POWER_DOMAIN_GT_IRQ,
 110         POWER_DOMAIN_DPLL_DC_OFF,
 111         POWER_DOMAIN_TC_COLD_OFF,
 112         POWER_DOMAIN_INIT,
 113
 114         POWER_DOMAIN_NUM,
 115 };
 116
 117 /*
 118  * i915_power_well_id:
 119  *
 120  * IDs used to look up power wells. Power wells accessed directly bypassing
 121  * the power domains framework must be assigned a unique ID. The rest of power
 122  * wells must be assigned DISP_PW_ID_NONE.
 123  */
 124 enum i915_power_well_id {
 125         DISP_PW_ID_NONE,
 126
 127         VLV_DISP_PW_DISP2D,
 128         BXT_DISP_PW_DPIO_CMN_A,
 129         VLV_DISP_PW_DPIO_CMN_BC,
 130         GLK_DISP_PW_DPIO_CMN_C,
 131         CHV_DISP_PW_DPIO_CMN_D,
 132         HSW_DISP_PW_GLOBAL,
 133         SKL_DISP_PW_MISC_IO,
 134         SKL_DISP_PW_1,
 135         SKL_DISP_PW_2,
 136         CNL_DISP_PW_DDI_F_IO,
 137         CNL_DISP_PW_DDI_F_AUX,
 138         ICL_DISP_PW_3,
 139         SKL_DISP_DC_OFF,
 140         TGL_DISP_PW_TC_COLD_OFF,
 141 };
 142
 143 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 144 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 145                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 146 #define POWER_DOMAIN_TRANSCODER(tran) \
 147         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 148          (tran) + POWER_DOMAIN_TRANSCODER_A)
 149
 150 struct i915_power_well;
 151
 152 struct i915_power_well_ops {
 153         /*
 154          * Synchronize the well's hw state to match the current sw state, for
 155          * example enable/disable it based on the current refcount. Called
 156          * during driver init and resume time, possibly after first calling
 157          * the enable/disable handlers.
 158          */
 159         void (*sync_hw)(struct drm_i915_private *dev_priv,
 160                         struct i915_power_well *power_well);
 161         /*
 162          * Enable the well and resources that depend on it (for example
 163          * interrupts located on the well). Called after the 0->1 refcount
 164          * transition.
 165          */
 166         void (*enable)(struct drm_i915_private *dev_priv,
 167                        struct i915_power_well *power_well);
 168         /*
 169          * Disable the well and resources that depend on it. Called after
 170          * the 1->0 refcount transition.
 171          */
 172         void (*disable)(struct drm_i915_private *dev_priv,
 173                         struct i915_power_well *power_well);
 174         /* Returns the hw enabled state. */
 175         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 176                            struct i915_power_well *power_well);
 177 };
 178
 179 struct i915_power_well_regs {
 180         i915_reg_t bios;
 181         i915_reg_t driver;
 182         i915_reg_t kvmr;
 183         i915_reg_t debug;
 184 };
 185
 186 /* Power well structure for haswell */
 187 struct i915_power_well_desc {
 188         const char *name;
 189         bool always_on;
 190         u64 domains;
 191         /* unique identifier for this power well */
 192         enum i915_power_well_id id;
 193         /*
 194          * Arbitraty data associated with this power well. Platform and power
 195          * well specific.
 196          */
 197         union {
 198                 struct {
 199                         /*
 200                          * request/status flag index in the PUNIT power well
 201                          * control/status registers.
 202                          */
 203                         u8 idx;
 204                 } vlv;
 205                 struct {
 206                         enum dpio_phy phy;
 207                 } bxt;
 208                 struct {
 209                         const struct i915_power_well_regs *regs;
 210                         /*
 211                          * request/status flag index in the power well
 212                          * constrol/status registers.
 213                          */
 214                         u8 idx;
 215                         /* Mask of pipes whose IRQ logic is backed by the pw */
 216                         u8 irq_pipe_mask;
 217                         /* The pw is backing the VGA functionality */
 218                         bool has_vga:1;
 219                         bool has_fuses:1;
 220                         /*
 221                          * The pw is for an ICL+ TypeC PHY port in
 222                          * Thunderbolt mode.
 223                          */
 224                         bool is_tc_tbt:1;
 225                 } hsw;
 226         };
 227         const struct i915_power_well_ops *ops;
 228 };
 229
 230 struct i915_power_well {
 231         const struct i915_power_well_desc *desc;
 232         /* power well enable/disable usage count */
 233         int count;
 234         /* cached hw enabled state */
 235         bool hw_enabled;
 236 };
 237
 238 struct i915_power_domains {
 239         /*
 240          * Power wells needed for initialization at driver init and suspend
 241          * time are on. They are kept on until after the first modeset.
 242          */
 243         bool initializing;
 244         bool display_core_suspended;
 245         int power_well_count;
 246
 247         intel_wakeref_t init_wakeref;
 248         intel_wakeref_t disable_wakeref;
 249
 250         struct mutex lock;
 251         int domain_use_count[POWER_DOMAIN_NUM];
 252
 253         struct delayed_work async_put_work;
 254         intel_wakeref_t async_put_wakeref;
 255         u64 async_put_domains[2];
 256
 257         struct i915_power_well *power_wells;
 258 };
 259
 260 struct intel_display_power_domain_set {
 261         u64 mask;
 262 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
 263         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
 264 #endif
 265 };
 266
 267 #define for_each_power_domain(domain, mask)                             \
 268         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 269                 for_each_if(BIT_ULL(domain) & (mask))
 270
 271 #define for_each_power_well(__dev_priv, __power_well)                           \
 272         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 273              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 274                 (__dev_priv)->power_domains.power_well_count;           \
 275              (__power_well)++)
 276
 277 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 278         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 279                               (__dev_priv)->power_domains.power_well_count - 1; \
 280              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 281              (__power_well)--)
 282
 283 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 284         for_each_power_well(__dev_priv, __power_well)                           \
 285                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 286
 287 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 288         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 289                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 290
 291 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 292 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 293 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 294 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 295 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 296 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 297 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
 298                                  enum i915_drm_suspend_mode);
 299 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
 300
 301 void intel_display_power_suspend_late(struct drm_i915_private *i915);
 302 void intel_display_power_resume_early(struct drm_i915_private *i915);
 303 void intel_display_power_suspend(struct drm_i915_private *i915);
 304 void intel_display_power_resume(struct drm_i915_private *i915);
 305 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 306                                              u32 state);
 307
 308 const char *
 309 intel_display_power_domain_str(enum intel_display_power_domain domain);
 310
 311 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 312                                     enum intel_display_power_domain domain);
 313 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 314                                          enum i915_power_well_id power_well_id);
 315 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 316                                       enum intel_display_power_domain domain);
 317 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 318                                         enum intel_display_power_domain domain);
 319 intel_wakeref_t
 320 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 321                                    enum intel_display_power_domain domain);
 322 void __intel_display_power_put_async(struct drm_i915_private *i915,
 323                                      enum intel_display_power_domain domain,
 324                                      intel_wakeref_t wakeref);
 325 void intel_display_power_flush_work(struct drm_i915_private *i915);
 326 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 327 void intel_display_power_put(struct drm_i915_private *dev_priv,
 328                              enum intel_display_power_domain domain,
 329                              intel_wakeref_t wakeref);
 330 static inline void
 331 intel_display_power_put_async(struct drm_i915_private *i915,
 332                               enum intel_display_power_domain domain,
 333                               intel_wakeref_t wakeref)
 334 {
 335         __intel_display_power_put_async(i915, domain, wakeref);
 336 }
 337 #else
 338 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 339                                        enum intel_display_power_domain domain);
 340
 341 static inline void
 342 intel_display_power_put(struct drm_i915_private *i915,
 343                         enum intel_display_power_domain domain,
 344                         intel_wakeref_t wakeref)
 345 {
 346         intel_display_power_put_unchecked(i915, domain);
 347 }
 348
 349 static inline void
 350 intel_display_power_put_async(struct drm_i915_private *i915,
 351                               enum intel_display_power_domain domain,
 352                               intel_wakeref_t wakeref)
 353 {
 354         __intel_display_power_put_async(i915, domain, -1);
 355 }
 356 #endif
 357
 358 void
 359 intel_display_power_get_in_set(struct drm_i915_private *i915,
 360                                struct intel_display_power_domain_set *power_domain_set,
 361                                enum intel_display_power_domain domain);
 362
 363 bool
 364 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
 365                                           struct intel_display_power_domain_set *power_domain_set,
 366                                           enum intel_display_power_domain domain);
 367
 368 void
 369 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 370                                     struct intel_display_power_domain_set *power_domain_set,
 371                                     u64 mask);
 372
 373 static inline void
 374 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
 375                                    struct intel_display_power_domain_set *power_domain_set)
 376 {
 377         intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
 378 }
 379
 380 enum dbuf_slice {
 381         DBUF_S1,
 382         DBUF_S2,
 383         DBUF_S3,
 384         DBUF_S4,
 385         I915_MAX_DBUF_SLICES
 386 };
 387
 388 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 389                              u8 req_slices);
 390
 391 #define with_intel_display_power(i915, domain, wf) \
 392         for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
 393              intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
 394
 395 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 396                              bool override, unsigned int mask);
 397 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 398                           enum dpio_channel ch, bool override);
 399
 400 #endif /* __INTEL_DISPLAY_POWER_H__ */