1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
6 #ifndef __INTEL_DISPLAY_POWER_H__
7 #define __INTEL_DISPLAY_POWER_H__
9 #include "intel_display.h"
10 #include "intel_runtime_pm.h"
13 struct drm_i915_private;
16 enum intel_display_power_domain {
17 POWER_DOMAIN_DISPLAY_CORE,
22 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
23 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
24 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
25 POWER_DOMAIN_PIPE_D_PANEL_FITTER,
26 POWER_DOMAIN_TRANSCODER_A,
27 POWER_DOMAIN_TRANSCODER_B,
28 POWER_DOMAIN_TRANSCODER_C,
29 POWER_DOMAIN_TRANSCODER_D,
30 POWER_DOMAIN_TRANSCODER_EDP,
31 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
32 POWER_DOMAIN_TRANSCODER_VDSC_PW2,
33 POWER_DOMAIN_TRANSCODER_DSI_A,
34 POWER_DOMAIN_TRANSCODER_DSI_C,
35 POWER_DOMAIN_PORT_DDI_A_LANES,
36 POWER_DOMAIN_PORT_DDI_B_LANES,
37 POWER_DOMAIN_PORT_DDI_C_LANES,
38 POWER_DOMAIN_PORT_DDI_D_LANES,
39 POWER_DOMAIN_PORT_DDI_E_LANES,
40 POWER_DOMAIN_PORT_DDI_F_LANES,
41 POWER_DOMAIN_PORT_DDI_G_LANES,
42 POWER_DOMAIN_PORT_DDI_H_LANES,
43 POWER_DOMAIN_PORT_DDI_I_LANES,
44 POWER_DOMAIN_PORT_DDI_A_IO,
45 POWER_DOMAIN_PORT_DDI_B_IO,
46 POWER_DOMAIN_PORT_DDI_C_IO,
47 POWER_DOMAIN_PORT_DDI_D_IO,
48 POWER_DOMAIN_PORT_DDI_E_IO,
49 POWER_DOMAIN_PORT_DDI_F_IO,
50 POWER_DOMAIN_PORT_DDI_G_IO,
51 POWER_DOMAIN_PORT_DDI_H_IO,
52 POWER_DOMAIN_PORT_DDI_I_IO,
53 POWER_DOMAIN_PORT_DSI,
54 POWER_DOMAIN_PORT_CRT,
55 POWER_DOMAIN_PORT_OTHER,
67 POWER_DOMAIN_AUX_IO_A,
68 POWER_DOMAIN_AUX_C_TBT,
69 POWER_DOMAIN_AUX_D_TBT,
70 POWER_DOMAIN_AUX_E_TBT,
71 POWER_DOMAIN_AUX_F_TBT,
72 POWER_DOMAIN_AUX_G_TBT,
73 POWER_DOMAIN_AUX_H_TBT,
74 POWER_DOMAIN_AUX_I_TBT,
78 POWER_DOMAIN_DPLL_DC_OFF,
79 POWER_DOMAIN_TC_COLD_OFF,
88 * IDs used to look up power wells. Power wells accessed directly bypassing
89 * the power domains framework must be assigned a unique ID. The rest of power
90 * wells must be assigned DISP_PW_ID_NONE.
92 enum i915_power_well_id {
96 BXT_DISP_PW_DPIO_CMN_A,
97 VLV_DISP_PW_DPIO_CMN_BC,
98 GLK_DISP_PW_DPIO_CMN_C,
99 CHV_DISP_PW_DPIO_CMN_D,
104 CNL_DISP_PW_DDI_F_IO,
105 CNL_DISP_PW_DDI_F_AUX,
110 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
111 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
112 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
113 #define POWER_DOMAIN_TRANSCODER(tran) \
114 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
115 (tran) + POWER_DOMAIN_TRANSCODER_A)
117 struct i915_power_well;
119 struct i915_power_well_ops {
121 * Synchronize the well's hw state to match the current sw state, for
122 * example enable/disable it based on the current refcount. Called
123 * during driver init and resume time, possibly after first calling
124 * the enable/disable handlers.
126 void (*sync_hw)(struct drm_i915_private *dev_priv,
127 struct i915_power_well *power_well);
129 * Enable the well and resources that depend on it (for example
130 * interrupts located on the well). Called after the 0->1 refcount
133 void (*enable)(struct drm_i915_private *dev_priv,
134 struct i915_power_well *power_well);
136 * Disable the well and resources that depend on it. Called after
137 * the 1->0 refcount transition.
139 void (*disable)(struct drm_i915_private *dev_priv,
140 struct i915_power_well *power_well);
141 /* Returns the hw enabled state. */
142 bool (*is_enabled)(struct drm_i915_private *dev_priv,
143 struct i915_power_well *power_well);
146 struct i915_power_well_regs {
153 /* Power well structure for haswell */
154 struct i915_power_well_desc {
158 /* unique identifier for this power well */
159 enum i915_power_well_id id;
161 * Arbitraty data associated with this power well. Platform and power
167 * request/status flag index in the PUNIT power well
168 * control/status registers.
176 const struct i915_power_well_regs *regs;
178 * request/status flag index in the power well
179 * constrol/status registers.
182 /* Mask of pipes whose IRQ logic is backed by the pw */
184 /* The pw is backing the VGA functionality */
188 * The pw is for an ICL+ TypeC PHY port in
194 const struct i915_power_well_ops *ops;
197 struct i915_power_well {
198 const struct i915_power_well_desc *desc;
199 /* power well enable/disable usage count */
201 /* cached hw enabled state */
205 struct i915_power_domains {
207 * Power wells needed for initialization at driver init and suspend
208 * time are on. They are kept on until after the first modeset.
211 bool display_core_suspended;
212 int power_well_count;
214 intel_wakeref_t wakeref;
217 int domain_use_count[POWER_DOMAIN_NUM];
219 struct delayed_work async_put_work;
220 intel_wakeref_t async_put_wakeref;
221 u64 async_put_domains[2];
223 struct i915_power_well *power_wells;
226 #define for_each_power_domain(domain, mask) \
227 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
228 for_each_if(BIT_ULL(domain) & (mask))
230 #define for_each_power_well(__dev_priv, __power_well) \
231 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
232 (__power_well) - (__dev_priv)->power_domains.power_wells < \
233 (__dev_priv)->power_domains.power_well_count; \
236 #define for_each_power_well_reverse(__dev_priv, __power_well) \
237 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
238 (__dev_priv)->power_domains.power_well_count - 1; \
239 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
242 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
243 for_each_power_well(__dev_priv, __power_well) \
244 for_each_if((__power_well)->desc->domains & (__domain_mask))
246 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
247 for_each_power_well_reverse(__dev_priv, __power_well) \
248 for_each_if((__power_well)->desc->domains & (__domain_mask))
250 int intel_power_domains_init(struct drm_i915_private *dev_priv);
251 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
252 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
253 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
254 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
255 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
256 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
257 enum i915_drm_suspend_mode);
258 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
260 void intel_display_power_suspend_late(struct drm_i915_private *i915);
261 void intel_display_power_resume_early(struct drm_i915_private *i915);
262 void intel_display_power_suspend(struct drm_i915_private *i915);
263 void intel_display_power_resume(struct drm_i915_private *i915);
264 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
268 intel_display_power_domain_str(enum intel_display_power_domain domain);
270 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
271 enum intel_display_power_domain domain);
272 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
273 enum i915_power_well_id power_well_id);
274 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
275 enum intel_display_power_domain domain);
276 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
277 enum intel_display_power_domain domain);
279 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
280 enum intel_display_power_domain domain);
281 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
282 enum intel_display_power_domain domain);
283 void __intel_display_power_put_async(struct drm_i915_private *i915,
284 enum intel_display_power_domain domain,
285 intel_wakeref_t wakeref);
286 void intel_display_power_flush_work(struct drm_i915_private *i915);
287 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
288 void intel_display_power_put(struct drm_i915_private *dev_priv,
289 enum intel_display_power_domain domain,
290 intel_wakeref_t wakeref);
292 intel_display_power_put_async(struct drm_i915_private *i915,
293 enum intel_display_power_domain domain,
294 intel_wakeref_t wakeref)
296 __intel_display_power_put_async(i915, domain, wakeref);
300 intel_display_power_put(struct drm_i915_private *i915,
301 enum intel_display_power_domain domain,
302 intel_wakeref_t wakeref)
304 intel_display_power_put_unchecked(i915, domain);
308 intel_display_power_put_async(struct drm_i915_private *i915,
309 enum intel_display_power_domain domain,
310 intel_wakeref_t wakeref)
312 __intel_display_power_put_async(i915, domain, -1);
322 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
325 #define with_intel_display_power(i915, domain, wf) \
326 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
327 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
329 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
330 bool override, unsigned int mask);
331 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
332 enum dpio_channel ch, bool override);
334 #endif /* __INTEL_DISPLAY_POWER_H__ */