1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
6 #include "display/intel_crt.h"
10 #include "intel_cdclk.h"
11 #include "intel_combo_phy.h"
12 #include "intel_display_power.h"
14 #include "intel_display_types.h"
15 #include "intel_dmc.h"
16 #include "intel_dpio_phy.h"
17 #include "intel_hotplug.h"
19 #include "intel_pps.h"
20 #include "intel_sideband.h"
22 #include "intel_vga.h"
24 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
25 enum i915_power_well_id power_well_id);
28 intel_display_power_domain_str(enum intel_display_power_domain domain)
31 case POWER_DOMAIN_DISPLAY_CORE:
32 return "DISPLAY_CORE";
33 case POWER_DOMAIN_PIPE_A:
35 case POWER_DOMAIN_PIPE_B:
37 case POWER_DOMAIN_PIPE_C:
39 case POWER_DOMAIN_PIPE_D:
41 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
42 return "PIPE_A_PANEL_FITTER";
43 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
44 return "PIPE_B_PANEL_FITTER";
45 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
46 return "PIPE_C_PANEL_FITTER";
47 case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
48 return "PIPE_D_PANEL_FITTER";
49 case POWER_DOMAIN_TRANSCODER_A:
50 return "TRANSCODER_A";
51 case POWER_DOMAIN_TRANSCODER_B:
52 return "TRANSCODER_B";
53 case POWER_DOMAIN_TRANSCODER_C:
54 return "TRANSCODER_C";
55 case POWER_DOMAIN_TRANSCODER_D:
56 return "TRANSCODER_D";
57 case POWER_DOMAIN_TRANSCODER_EDP:
58 return "TRANSCODER_EDP";
59 case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
60 return "TRANSCODER_VDSC_PW2";
61 case POWER_DOMAIN_TRANSCODER_DSI_A:
62 return "TRANSCODER_DSI_A";
63 case POWER_DOMAIN_TRANSCODER_DSI_C:
64 return "TRANSCODER_DSI_C";
65 case POWER_DOMAIN_PORT_DDI_A_LANES:
66 return "PORT_DDI_A_LANES";
67 case POWER_DOMAIN_PORT_DDI_B_LANES:
68 return "PORT_DDI_B_LANES";
69 case POWER_DOMAIN_PORT_DDI_C_LANES:
70 return "PORT_DDI_C_LANES";
71 case POWER_DOMAIN_PORT_DDI_D_LANES:
72 return "PORT_DDI_D_LANES";
73 case POWER_DOMAIN_PORT_DDI_E_LANES:
74 return "PORT_DDI_E_LANES";
75 case POWER_DOMAIN_PORT_DDI_F_LANES:
76 return "PORT_DDI_F_LANES";
77 case POWER_DOMAIN_PORT_DDI_G_LANES:
78 return "PORT_DDI_G_LANES";
79 case POWER_DOMAIN_PORT_DDI_H_LANES:
80 return "PORT_DDI_H_LANES";
81 case POWER_DOMAIN_PORT_DDI_I_LANES:
82 return "PORT_DDI_I_LANES";
83 case POWER_DOMAIN_PORT_DDI_A_IO:
84 return "PORT_DDI_A_IO";
85 case POWER_DOMAIN_PORT_DDI_B_IO:
86 return "PORT_DDI_B_IO";
87 case POWER_DOMAIN_PORT_DDI_C_IO:
88 return "PORT_DDI_C_IO";
89 case POWER_DOMAIN_PORT_DDI_D_IO:
90 return "PORT_DDI_D_IO";
91 case POWER_DOMAIN_PORT_DDI_E_IO:
92 return "PORT_DDI_E_IO";
93 case POWER_DOMAIN_PORT_DDI_F_IO:
94 return "PORT_DDI_F_IO";
95 case POWER_DOMAIN_PORT_DDI_G_IO:
96 return "PORT_DDI_G_IO";
97 case POWER_DOMAIN_PORT_DDI_H_IO:
98 return "PORT_DDI_H_IO";
99 case POWER_DOMAIN_PORT_DDI_I_IO:
100 return "PORT_DDI_I_IO";
101 case POWER_DOMAIN_PORT_DSI:
103 case POWER_DOMAIN_PORT_CRT:
105 case POWER_DOMAIN_PORT_OTHER:
107 case POWER_DOMAIN_VGA:
109 case POWER_DOMAIN_AUDIO:
111 case POWER_DOMAIN_AUX_A:
113 case POWER_DOMAIN_AUX_B:
115 case POWER_DOMAIN_AUX_C:
117 case POWER_DOMAIN_AUX_D:
119 case POWER_DOMAIN_AUX_E:
121 case POWER_DOMAIN_AUX_F:
123 case POWER_DOMAIN_AUX_G:
125 case POWER_DOMAIN_AUX_H:
127 case POWER_DOMAIN_AUX_I:
129 case POWER_DOMAIN_AUX_IO_A:
131 case POWER_DOMAIN_AUX_C_TBT:
133 case POWER_DOMAIN_AUX_D_TBT:
135 case POWER_DOMAIN_AUX_E_TBT:
137 case POWER_DOMAIN_AUX_F_TBT:
139 case POWER_DOMAIN_AUX_G_TBT:
141 case POWER_DOMAIN_AUX_H_TBT:
143 case POWER_DOMAIN_AUX_I_TBT:
145 case POWER_DOMAIN_GMBUS:
147 case POWER_DOMAIN_INIT:
149 case POWER_DOMAIN_MODESET:
151 case POWER_DOMAIN_GT_IRQ:
153 case POWER_DOMAIN_DPLL_DC_OFF:
154 return "DPLL_DC_OFF";
155 case POWER_DOMAIN_TC_COLD_OFF:
156 return "TC_COLD_OFF";
158 MISSING_CASE(domain);
163 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
164 struct i915_power_well *power_well)
166 drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name);
167 power_well->desc->ops->enable(dev_priv, power_well);
168 power_well->hw_enabled = true;
171 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
172 struct i915_power_well *power_well)
174 drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name);
175 power_well->hw_enabled = false;
176 power_well->desc->ops->disable(dev_priv, power_well);
179 static void intel_power_well_get(struct drm_i915_private *dev_priv,
180 struct i915_power_well *power_well)
182 if (!power_well->count++)
183 intel_power_well_enable(dev_priv, power_well);
186 static void intel_power_well_put(struct drm_i915_private *dev_priv,
187 struct i915_power_well *power_well)
189 drm_WARN(&dev_priv->drm, !power_well->count,
190 "Use count on power well %s is already zero",
191 power_well->desc->name);
193 if (!--power_well->count)
194 intel_power_well_disable(dev_priv, power_well);
198 * __intel_display_power_is_enabled - unlocked check for a power domain
199 * @dev_priv: i915 device instance
200 * @domain: power domain to check
202 * This is the unlocked version of intel_display_power_is_enabled() and should
203 * only be used from error capture and recovery code where deadlocks are
207 * True when the power domain is enabled, false otherwise.
209 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
210 enum intel_display_power_domain domain)
212 struct i915_power_well *power_well;
215 if (dev_priv->runtime_pm.suspended)
220 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
221 if (power_well->desc->always_on)
224 if (!power_well->hw_enabled) {
234 * intel_display_power_is_enabled - check for a power domain
235 * @dev_priv: i915 device instance
236 * @domain: power domain to check
238 * This function can be used to check the hw power domain state. It is mostly
239 * used in hardware state readout functions. Everywhere else code should rely
240 * upon explicit power domain reference counting to ensure that the hardware
241 * block is powered up before accessing it.
243 * Callers must hold the relevant modesetting locks to ensure that concurrent
244 * threads can't disable the power well while the caller tries to read a few
248 * True when the power domain is enabled, false otherwise.
250 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
251 enum intel_display_power_domain domain)
253 struct i915_power_domains *power_domains;
256 power_domains = &dev_priv->power_domains;
258 mutex_lock(&power_domains->lock);
259 ret = __intel_display_power_is_enabled(dev_priv, domain);
260 mutex_unlock(&power_domains->lock);
266 * Starting with Haswell, we have a "Power Down Well" that can be turned off
267 * when not needed anymore. We have 4 registers that can request the power well
268 * to be enabled, and it will only be disabled if none of the registers is
269 * requesting it to be enabled.
271 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
272 u8 irq_pipe_mask, bool has_vga)
275 intel_vga_reset_io_mem(dev_priv);
278 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
281 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
285 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
288 #define ICL_AUX_PW_TO_CH(pw_idx) \
289 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
291 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
292 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
294 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
296 int pw_idx = power_well->desc->hsw.idx;
298 return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
299 ICL_AUX_PW_TO_CH(pw_idx);
302 static struct intel_digital_port *
303 aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
306 struct intel_digital_port *dig_port = NULL;
307 struct intel_encoder *encoder;
309 for_each_intel_encoder(&dev_priv->drm, encoder) {
310 /* We'll check the MST primary port */
311 if (encoder->type == INTEL_OUTPUT_DP_MST)
314 dig_port = enc_to_dig_port(encoder);
318 if (dig_port->aux_ch != aux_ch) {
329 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
330 const struct i915_power_well *power_well)
332 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
333 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
335 return intel_port_to_phy(i915, dig_port->base.port);
338 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
339 struct i915_power_well *power_well,
340 bool timeout_expected)
342 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
343 int pw_idx = power_well->desc->hsw.idx;
345 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
346 if (intel_de_wait_for_set(dev_priv, regs->driver,
347 HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
348 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
349 power_well->desc->name);
351 drm_WARN_ON(&dev_priv->drm, !timeout_expected);
356 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
357 const struct i915_power_well_regs *regs,
360 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
363 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
364 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
366 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
367 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
372 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
373 struct i915_power_well *power_well)
375 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
376 int pw_idx = power_well->desc->hsw.idx;
381 * Bspec doesn't require waiting for PWs to get disabled, but still do
382 * this for paranoia. The known cases where a PW will be forced on:
383 * - a KVMR request on any power well via the KVMR request register
384 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
385 * DEBUG request registers
386 * Skip the wait in case any of the request bits are set and print a
387 * diagnostic message.
389 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
390 HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
391 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
395 drm_dbg_kms(&dev_priv->drm,
396 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
397 power_well->desc->name,
398 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
401 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
402 enum skl_power_gate pg)
404 /* Timeout 5us for PG#0, for other PGs 1us */
405 drm_WARN_ON(&dev_priv->drm,
406 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
407 SKL_FUSE_PG_DIST_STATUS(pg), 1));
410 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
411 struct i915_power_well *power_well)
413 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
414 int pw_idx = power_well->desc->hsw.idx;
417 if (power_well->desc->hsw.has_fuses) {
418 enum skl_power_gate pg;
420 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
421 SKL_PW_CTL_IDX_TO_PG(pw_idx);
423 * For PW1 we have to wait both for the PW0/PG0 fuse state
424 * before enabling the power well and PW1/PG1's own fuse
425 * state after the enabling. For all other power wells with
426 * fuses we only have to wait for that PW/PG's fuse state
427 * after the enabling.
430 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
433 val = intel_de_read(dev_priv, regs->driver);
434 intel_de_write(dev_priv, regs->driver,
435 val | HSW_PWR_WELL_CTL_REQ(pw_idx));
437 hsw_wait_for_power_well_enable(dev_priv, power_well, false);
439 /* Display WA #1178: cnl */
440 if (IS_CANNONLAKE(dev_priv) &&
441 pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
442 pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
445 val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
446 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
447 intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
450 if (power_well->desc->hsw.has_fuses) {
451 enum skl_power_gate pg;
453 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
454 SKL_PW_CTL_IDX_TO_PG(pw_idx);
455 gen9_wait_for_power_well_fuses(dev_priv, pg);
458 hsw_power_well_post_enable(dev_priv,
459 power_well->desc->hsw.irq_pipe_mask,
460 power_well->desc->hsw.has_vga);
463 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
464 struct i915_power_well *power_well)
466 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
467 int pw_idx = power_well->desc->hsw.idx;
470 hsw_power_well_pre_disable(dev_priv,
471 power_well->desc->hsw.irq_pipe_mask);
473 val = intel_de_read(dev_priv, regs->driver);
474 intel_de_write(dev_priv, regs->driver,
475 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
476 hsw_wait_for_power_well_disable(dev_priv, power_well);
480 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
481 struct i915_power_well *power_well)
483 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
484 int pw_idx = power_well->desc->hsw.idx;
485 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
488 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
490 val = intel_de_read(dev_priv, regs->driver);
491 intel_de_write(dev_priv, regs->driver,
492 val | HSW_PWR_WELL_CTL_REQ(pw_idx));
494 if (DISPLAY_VER(dev_priv) < 12) {
495 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
496 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
497 val | ICL_LANE_ENABLE_AUX);
500 hsw_wait_for_power_well_enable(dev_priv, power_well, false);
502 /* Display WA #1178: icl */
503 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
504 !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
505 val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx));
506 val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
507 intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val);
512 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
513 struct i915_power_well *power_well)
515 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
516 int pw_idx = power_well->desc->hsw.idx;
517 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
520 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
522 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
523 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
524 val & ~ICL_LANE_ENABLE_AUX);
526 val = intel_de_read(dev_priv, regs->driver);
527 intel_de_write(dev_priv, regs->driver,
528 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
530 hsw_wait_for_power_well_disable(dev_priv, power_well);
533 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
535 static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
537 static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
538 struct i915_power_well *power_well)
540 int refs = hweight64(power_well->desc->domains &
541 async_put_domains_mask(&dev_priv->power_domains));
543 drm_WARN_ON(&dev_priv->drm, refs > power_well->count);
548 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
549 struct i915_power_well *power_well,
550 struct intel_digital_port *dig_port)
552 /* Bypass the check if all references are released asynchronously */
553 if (power_well_async_ref_count(dev_priv, power_well) ==
557 if (drm_WARN_ON(&dev_priv->drm, !dig_port))
560 if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
563 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
568 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
569 struct i915_power_well *power_well,
570 struct intel_digital_port *dig_port)
576 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
578 static void icl_tc_cold_exit(struct drm_i915_private *i915)
583 ret = sandybridge_pcode_write_timeout(i915,
584 ICL_PCODE_EXIT_TCCOLD,
586 if (ret != -EAGAIN || ++tries == 3)
591 /* Spec states that TC cold exit can take up to 1ms to complete */
595 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
596 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
601 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
602 struct i915_power_well *power_well)
604 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
605 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
606 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
607 bool is_tbt = power_well->desc->hsw.is_tc_tbt;
608 bool timeout_expected;
611 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
613 val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
614 val &= ~DP_AUX_CH_CTL_TBT_IO;
616 val |= DP_AUX_CH_CTL_TBT_IO;
617 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
619 val = intel_de_read(dev_priv, regs->driver);
620 intel_de_write(dev_priv, regs->driver,
621 val | HSW_PWR_WELL_CTL_REQ(power_well->desc->hsw.idx));
624 * An AUX timeout is expected if the TBT DP tunnel is down,
625 * or need to enable AUX on a legacy TypeC port as part of the TC-cold
628 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
629 if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
630 icl_tc_cold_exit(dev_priv);
632 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
634 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
635 enum tc_port tc_port;
637 tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
638 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
639 HIP_INDEX_VAL(tc_port, 0x2));
641 if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
642 DKL_CMN_UC_DW27_UC_HEALTH, 1))
643 drm_warn(&dev_priv->drm,
644 "Timeout waiting TC uC health\n");
649 icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
650 struct i915_power_well *power_well)
652 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
653 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
655 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
657 hsw_power_well_disable(dev_priv, power_well);
661 icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
662 struct i915_power_well *power_well)
664 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
666 if (intel_phy_is_tc(dev_priv, phy))
667 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
668 else if (IS_ICELAKE(dev_priv))
669 return icl_combo_phy_aux_power_well_enable(dev_priv,
672 return hsw_power_well_enable(dev_priv, power_well);
676 icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
677 struct i915_power_well *power_well)
679 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
681 if (intel_phy_is_tc(dev_priv, phy))
682 return icl_tc_phy_aux_power_well_disable(dev_priv, power_well);
683 else if (IS_ICELAKE(dev_priv))
684 return icl_combo_phy_aux_power_well_disable(dev_priv,
687 return hsw_power_well_disable(dev_priv, power_well);
691 * We should only use the power well if we explicitly asked the hardware to
692 * enable it, so check if it's enabled and also check if we've requested it to
695 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
696 struct i915_power_well *power_well)
698 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
699 enum i915_power_well_id id = power_well->desc->id;
700 int pw_idx = power_well->desc->hsw.idx;
701 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
702 HSW_PWR_WELL_CTL_STATE(pw_idx);
705 val = intel_de_read(dev_priv, regs->driver);
708 * On GEN9 big core due to a DMC bug the driver's request bits for PW1
709 * and the MISC_IO PW will be not restored, so check instead for the
710 * BIOS's own request bits, which are forced-on for these power wells
711 * when exiting DC5/6.
713 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
714 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
715 val |= intel_de_read(dev_priv, regs->bios);
717 return (val & mask) == mask;
720 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
722 drm_WARN_ONCE(&dev_priv->drm,
723 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
724 "DC9 already programmed to be enabled.\n");
725 drm_WARN_ONCE(&dev_priv->drm,
726 intel_de_read(dev_priv, DC_STATE_EN) &
727 DC_STATE_EN_UPTO_DC5,
728 "DC5 still not disabled to enable DC9.\n");
729 drm_WARN_ONCE(&dev_priv->drm,
730 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
731 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
732 "Power well 2 on.\n");
733 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
734 "Interrupts not disabled yet.\n");
737 * TODO: check for the following to verify the conditions to enter DC9
738 * state are satisfied:
739 * 1] Check relevant display engine registers to verify if mode set
740 * disable sequence was followed.
741 * 2] Check if display uninitialize sequence is initialized.
745 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
747 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
748 "Interrupts not disabled yet.\n");
749 drm_WARN_ONCE(&dev_priv->drm,
750 intel_de_read(dev_priv, DC_STATE_EN) &
751 DC_STATE_EN_UPTO_DC5,
752 "DC5 still not disabled.\n");
755 * TODO: check for the following to verify DC9 state was indeed
756 * entered before programming to disable it:
757 * 1] Check relevant display engine registers to verify if mode
758 * set disable sequence was followed.
759 * 2] Check if display uninitialize sequence is initialized.
763 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
770 intel_de_write(dev_priv, DC_STATE_EN, state);
772 /* It has been observed that disabling the dc6 state sometimes
773 * doesn't stick and dmc keeps returning old value. Make sure
774 * the write really sticks enough times and also force rewrite until
775 * we are confident that state is exactly what we want.
778 v = intel_de_read(dev_priv, DC_STATE_EN);
781 intel_de_write(dev_priv, DC_STATE_EN, state);
784 } else if (rereads++ > 5) {
788 } while (rewrites < 100);
791 drm_err(&dev_priv->drm,
792 "Writing dc state to 0x%x failed, now 0x%x\n",
795 /* Most of the times we need one retry, avoid spam */
797 drm_dbg_kms(&dev_priv->drm,
798 "Rewrote dc state to 0x%x %d times\n",
802 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
806 mask = DC_STATE_EN_UPTO_DC5;
808 if (DISPLAY_VER(dev_priv) >= 12)
809 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
811 else if (DISPLAY_VER(dev_priv) == 11)
812 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
813 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
814 mask |= DC_STATE_EN_DC9;
816 mask |= DC_STATE_EN_UPTO_DC6;
821 static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
825 if (!HAS_DISPLAY(dev_priv))
828 val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
830 drm_dbg_kms(&dev_priv->drm,
831 "Resetting DC state tracking from %02x to %02x\n",
832 dev_priv->dmc.dc_state, val);
833 dev_priv->dmc.dc_state = val;
837 * gen9_set_dc_state - set target display C power state
838 * @dev_priv: i915 device instance
839 * @state: target DC power state
841 * - DC_STATE_EN_UPTO_DC5
842 * - DC_STATE_EN_UPTO_DC6
845 * Signal to DMC firmware/HW the target DC power state passed in @state.
846 * DMC/HW can turn off individual display clocks and power rails when entering
847 * a deeper DC power state (higher in number) and turns these back when exiting
848 * that state to a shallower power state (lower in number). The HW will decide
849 * when to actually enter a given state on an on-demand basis, for instance
850 * depending on the active state of display pipes. The state of display
851 * registers backed by affected power rails are saved/restored as needed.
853 * Based on the above enabling a deeper DC power state is asynchronous wrt.
854 * enabling it. Disabling a deeper power state is synchronous: for instance
855 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
856 * back on and register state is restored. This is guaranteed by the MMIO write
857 * to DC_STATE_EN blocking until the state is restored.
859 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
864 if (!HAS_DISPLAY(dev_priv))
867 if (drm_WARN_ON_ONCE(&dev_priv->drm,
868 state & ~dev_priv->dmc.allowed_dc_mask))
869 state &= dev_priv->dmc.allowed_dc_mask;
871 val = intel_de_read(dev_priv, DC_STATE_EN);
872 mask = gen9_dc_mask(dev_priv);
873 drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
876 /* Check if DMC is ignoring our DC state requests */
877 if ((val & mask) != dev_priv->dmc.dc_state)
878 drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
879 dev_priv->dmc.dc_state, val & mask);
884 gen9_write_dc_state(dev_priv, val);
886 dev_priv->dmc.dc_state = val & mask;
890 sanitize_target_dc_state(struct drm_i915_private *dev_priv,
894 DC_STATE_EN_UPTO_DC6,
895 DC_STATE_EN_UPTO_DC5,
901 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
902 if (target_dc_state != states[i])
905 if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
908 target_dc_state = states[i + 1];
911 return target_dc_state;
914 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
916 drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
917 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
920 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
924 drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
925 val = intel_de_read(dev_priv, DC_STATE_EN);
926 val &= ~DC_STATE_DC3CO_STATUS;
927 intel_de_write(dev_priv, DC_STATE_EN, val);
928 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
930 * Delay of 200us DC3CO Exit time B.Spec 49196
932 usleep_range(200, 210);
935 static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
937 assert_can_enable_dc9(dev_priv);
939 drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
941 * Power sequencer reset is not needed on
942 * platforms with South Display Engine on PCH,
943 * because PPS registers are always on.
945 if (!HAS_PCH_SPLIT(dev_priv))
946 intel_pps_reset_all(dev_priv);
947 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
950 static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
952 assert_can_disable_dc9(dev_priv);
954 drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
956 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
958 intel_pps_unlock_regs_wa(dev_priv);
961 static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
963 drm_WARN_ONCE(&dev_priv->drm,
964 !intel_de_read(dev_priv, DMC_PROGRAM(0)),
965 "DMC program storage start is NULL\n");
966 drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
967 "DMC SSP Base Not fine\n");
968 drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
969 "DMC HTP Not fine\n");
972 static struct i915_power_well *
973 lookup_power_well(struct drm_i915_private *dev_priv,
974 enum i915_power_well_id power_well_id)
976 struct i915_power_well *power_well;
978 for_each_power_well(dev_priv, power_well)
979 if (power_well->desc->id == power_well_id)
983 * It's not feasible to add error checking code to the callers since
984 * this condition really shouldn't happen and it doesn't even make sense
985 * to abort things like display initialization sequences. Just return
986 * the first power well and hope the WARN gets reported so we can fix
989 drm_WARN(&dev_priv->drm, 1,
990 "Power well %d not defined for this platform\n",
992 return &dev_priv->power_domains.power_wells[0];
996 * intel_display_power_set_target_dc_state - Set target dc state.
997 * @dev_priv: i915 device
998 * @state: state which needs to be set as target_dc_state.
1000 * This function set the "DC off" power well target_dc_state,
1001 * based upon this target_dc_stste, "DC off" power well will
1002 * enable desired DC state.
1004 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
1007 struct i915_power_well *power_well;
1008 bool dc_off_enabled;
1009 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1011 mutex_lock(&power_domains->lock);
1012 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
1014 if (drm_WARN_ON(&dev_priv->drm, !power_well))
1017 state = sanitize_target_dc_state(dev_priv, state);
1019 if (state == dev_priv->dmc.target_dc_state)
1022 dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
1025 * If DC off power well is disabled, need to enable and disable the
1026 * DC off power well to effect target DC state.
1028 if (!dc_off_enabled)
1029 power_well->desc->ops->enable(dev_priv, power_well);
1031 dev_priv->dmc.target_dc_state = state;
1033 if (!dc_off_enabled)
1034 power_well->desc->ops->disable(dev_priv, power_well);
1037 mutex_unlock(&power_domains->lock);
1040 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
1042 enum i915_power_well_id high_pg;
1044 /* Power wells at this level and above must be disabled for DC5 entry */
1045 if (DISPLAY_VER(dev_priv) == 12)
1046 high_pg = ICL_DISP_PW_3;
1048 high_pg = SKL_DISP_PW_2;
1050 drm_WARN_ONCE(&dev_priv->drm,
1051 intel_display_power_well_is_enabled(dev_priv, high_pg),
1052 "Power wells above platform's DC5 limit still enabled.\n");
1054 drm_WARN_ONCE(&dev_priv->drm,
1055 (intel_de_read(dev_priv, DC_STATE_EN) &
1056 DC_STATE_EN_UPTO_DC5),
1057 "DC5 already programmed to be enabled.\n");
1058 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
1060 assert_dmc_loaded(dev_priv);
1063 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
1065 assert_can_enable_dc5(dev_priv);
1067 drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
1069 /* Wa Display #1183: skl,kbl,cfl */
1070 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1071 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
1072 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
1074 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
1077 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
1079 drm_WARN_ONCE(&dev_priv->drm,
1080 intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
1081 "Backlight is not disabled.\n");
1082 drm_WARN_ONCE(&dev_priv->drm,
1083 (intel_de_read(dev_priv, DC_STATE_EN) &
1084 DC_STATE_EN_UPTO_DC6),
1085 "DC6 already programmed to be enabled.\n");
1087 assert_dmc_loaded(dev_priv);
1090 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
1092 assert_can_enable_dc6(dev_priv);
1094 drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
1096 /* Wa Display #1183: skl,kbl,cfl */
1097 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1098 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
1099 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
1101 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1104 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
1105 struct i915_power_well *power_well)
1107 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
1108 int pw_idx = power_well->desc->hsw.idx;
1109 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
1110 u32 bios_req = intel_de_read(dev_priv, regs->bios);
1112 /* Take over the request bit if set by BIOS. */
1113 if (bios_req & mask) {
1114 u32 drv_req = intel_de_read(dev_priv, regs->driver);
1116 if (!(drv_req & mask))
1117 intel_de_write(dev_priv, regs->driver, drv_req | mask);
1118 intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
1122 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1123 struct i915_power_well *power_well)
1125 bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
1128 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1129 struct i915_power_well *power_well)
1131 bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
1134 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
1135 struct i915_power_well *power_well)
1137 return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
1140 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
1142 struct i915_power_well *power_well;
1144 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
1145 if (power_well->count > 0)
1146 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
1148 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1149 if (power_well->count > 0)
1150 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
1152 if (IS_GEMINILAKE(dev_priv)) {
1153 power_well = lookup_power_well(dev_priv,
1154 GLK_DISP_PW_DPIO_CMN_C);
1155 if (power_well->count > 0)
1156 bxt_ddi_phy_verify_state(dev_priv,
1157 power_well->desc->bxt.phy);
1161 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
1162 struct i915_power_well *power_well)
1164 return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
1165 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
1168 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
1170 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
1171 u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
1173 drm_WARN(&dev_priv->drm,
1174 hw_enabled_dbuf_slices != enabled_dbuf_slices,
1175 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
1176 hw_enabled_dbuf_slices,
1177 enabled_dbuf_slices);
1180 static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
1182 struct intel_cdclk_config cdclk_config = {};
1184 if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
1185 tgl_disable_dc3co(dev_priv);
1189 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1191 if (!HAS_DISPLAY(dev_priv))
1194 dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
1195 /* Can't read out voltage_level so can't use intel_cdclk_changed() */
1196 drm_WARN_ON(&dev_priv->drm,
1197 intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
1200 gen9_assert_dbuf_enabled(dev_priv);
1202 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1203 bxt_verify_ddi_phy_power_wells(dev_priv);
1205 if (DISPLAY_VER(dev_priv) >= 11)
1207 * DMC retains HW context only for port A, the other combo
1208 * PHY's HW context for port B is lost after DC transitions,
1209 * so we need to restore it manually.
1211 intel_combo_phy_init(dev_priv);
1214 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
1215 struct i915_power_well *power_well)
1217 gen9_disable_dc_states(dev_priv);
1220 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
1221 struct i915_power_well *power_well)
1223 if (!intel_dmc_has_payload(dev_priv))
1226 switch (dev_priv->dmc.target_dc_state) {
1227 case DC_STATE_EN_DC3CO:
1228 tgl_enable_dc3co(dev_priv);
1230 case DC_STATE_EN_UPTO_DC6:
1231 skl_enable_dc6(dev_priv);
1233 case DC_STATE_EN_UPTO_DC5:
1234 gen9_enable_dc5(dev_priv);
1239 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
1240 struct i915_power_well *power_well)
1244 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
1245 struct i915_power_well *power_well)
1249 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
1250 struct i915_power_well *power_well)
1255 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
1256 struct i915_power_well *power_well)
1258 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
1259 i830_enable_pipe(dev_priv, PIPE_A);
1260 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
1261 i830_enable_pipe(dev_priv, PIPE_B);
1264 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
1265 struct i915_power_well *power_well)
1267 i830_disable_pipe(dev_priv, PIPE_B);
1268 i830_disable_pipe(dev_priv, PIPE_A);
1271 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
1272 struct i915_power_well *power_well)
1274 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
1275 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1278 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
1279 struct i915_power_well *power_well)
1281 if (power_well->count > 0)
1282 i830_pipes_power_well_enable(dev_priv, power_well);
1284 i830_pipes_power_well_disable(dev_priv, power_well);
1287 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
1288 struct i915_power_well *power_well, bool enable)
1290 int pw_idx = power_well->desc->vlv.idx;
1295 mask = PUNIT_PWRGT_MASK(pw_idx);
1296 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
1297 PUNIT_PWRGT_PWR_GATE(pw_idx);
1299 vlv_punit_get(dev_priv);
1302 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1307 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1310 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1312 if (wait_for(COND, 100))
1313 drm_err(&dev_priv->drm,
1314 "timeout setting power well state %08x (%08x)\n",
1316 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1321 vlv_punit_put(dev_priv);
1324 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1325 struct i915_power_well *power_well)
1327 vlv_set_power_well(dev_priv, power_well, true);
1330 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1331 struct i915_power_well *power_well)
1333 vlv_set_power_well(dev_priv, power_well, false);
1336 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1337 struct i915_power_well *power_well)
1339 int pw_idx = power_well->desc->vlv.idx;
1340 bool enabled = false;
1345 mask = PUNIT_PWRGT_MASK(pw_idx);
1346 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
1348 vlv_punit_get(dev_priv);
1350 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1352 * We only ever set the power-on and power-gate states, anything
1353 * else is unexpected.
1355 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
1356 state != PUNIT_PWRGT_PWR_GATE(pw_idx));
1361 * A transient state at this point would mean some unexpected party
1362 * is poking at the power controls too.
1364 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1365 drm_WARN_ON(&dev_priv->drm, ctrl != state);
1367 vlv_punit_put(dev_priv);
1372 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1377 * On driver load, a pipe may be active and driving a DSI display.
1378 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1379 * (and never recovering) in this case. intel_dsi_post_disable() will
1380 * clear it when we turn off the display.
1382 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
1383 val &= DPOUNIT_CLOCK_GATE_DISABLE;
1384 val |= VRHUNIT_CLOCK_GATE_DISABLE;
1385 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
1388 * Disable trickle feed and enable pnd deadline calculation
1390 intel_de_write(dev_priv, MI_ARB_VLV,
1391 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1392 intel_de_write(dev_priv, CBR1_VLV, 0);
1394 drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
1395 intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
1396 DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
1400 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1402 struct intel_encoder *encoder;
1406 * Enable the CRI clock source so we can get at the
1407 * display and the reference clock for VGA
1408 * hotplug / manual detection. Supposedly DSI also
1409 * needs the ref clock up and running.
1411 * CHV DPLL B/C have some issues if VGA mode is enabled.
1413 for_each_pipe(dev_priv, pipe) {
1414 u32 val = intel_de_read(dev_priv, DPLL(pipe));
1416 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1418 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1420 intel_de_write(dev_priv, DPLL(pipe), val);
1423 vlv_init_display_clock_gating(dev_priv);
1425 spin_lock_irq(&dev_priv->irq_lock);
1426 valleyview_enable_display_irqs(dev_priv);
1427 spin_unlock_irq(&dev_priv->irq_lock);
1430 * During driver initialization/resume we can avoid restoring the
1431 * part of the HW/SW state that will be inited anyway explicitly.
1433 if (dev_priv->power_domains.initializing)
1436 intel_hpd_init(dev_priv);
1437 intel_hpd_poll_disable(dev_priv);
1439 /* Re-enable the ADPA, if we have one */
1440 for_each_intel_encoder(&dev_priv->drm, encoder) {
1441 if (encoder->type == INTEL_OUTPUT_ANALOG)
1442 intel_crt_reset(&encoder->base);
1445 intel_vga_redisable_power_on(dev_priv);
1447 intel_pps_unlock_regs_wa(dev_priv);
1450 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1452 spin_lock_irq(&dev_priv->irq_lock);
1453 valleyview_disable_display_irqs(dev_priv);
1454 spin_unlock_irq(&dev_priv->irq_lock);
1456 /* make sure we're done processing display irqs */
1457 intel_synchronize_irq(dev_priv);
1459 intel_pps_reset_all(dev_priv);
1461 /* Prevent us from re-enabling polling on accident in late suspend */
1462 if (!dev_priv->drm.dev->power.is_suspended)
1463 intel_hpd_poll_enable(dev_priv);
1466 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1467 struct i915_power_well *power_well)
1469 vlv_set_power_well(dev_priv, power_well, true);
1471 vlv_display_power_well_init(dev_priv);
1474 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1475 struct i915_power_well *power_well)
1477 vlv_display_power_well_deinit(dev_priv);
1479 vlv_set_power_well(dev_priv, power_well, false);
1482 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1483 struct i915_power_well *power_well)
1485 /* since ref/cri clock was enabled */
1486 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1488 vlv_set_power_well(dev_priv, power_well, true);
1491 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1492 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1493 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1494 * b. The other bits such as sfr settings / modesel may all
1497 * This should only be done on init and resume from S3 with
1498 * both PLLs disabled, or we risk losing DPIO and PLL
1501 intel_de_write(dev_priv, DPIO_CTL,
1502 intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST);
1505 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1506 struct i915_power_well *power_well)
1510 for_each_pipe(dev_priv, pipe)
1511 assert_pll_disabled(dev_priv, pipe);
1513 /* Assert common reset */
1514 intel_de_write(dev_priv, DPIO_CTL,
1515 intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST);
1517 vlv_set_power_well(dev_priv, power_well, false);
1520 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
1522 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1524 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1526 struct i915_power_well *cmn_bc =
1527 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1528 struct i915_power_well *cmn_d =
1529 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1530 u32 phy_control = dev_priv->chv_phy_control;
1532 u32 phy_status_mask = 0xffffffff;
1535 * The BIOS can leave the PHY is some weird state
1536 * where it doesn't fully power down some parts.
1537 * Disable the asserts until the PHY has been fully
1538 * reset (ie. the power well has been disabled at
1541 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1542 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1543 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1544 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1545 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1546 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1547 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1549 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1550 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1551 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1552 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1554 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
1555 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1557 /* this assumes override is only used to enable lanes */
1558 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1559 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1561 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1562 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1564 /* CL1 is on whenever anything is on in either channel */
1565 if (BITS_SET(phy_control,
1566 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1567 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1568 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1571 * The DPLLB check accounts for the pipe B + port A usage
1572 * with CL2 powered up but all the lanes in the second channel
1575 if (BITS_SET(phy_control,
1576 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1577 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1578 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1580 if (BITS_SET(phy_control,
1581 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1582 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1583 if (BITS_SET(phy_control,
1584 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1585 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1587 if (BITS_SET(phy_control,
1588 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1589 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1590 if (BITS_SET(phy_control,
1591 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1592 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1595 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
1596 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1598 /* this assumes override is only used to enable lanes */
1599 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1600 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1602 if (BITS_SET(phy_control,
1603 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1604 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1606 if (BITS_SET(phy_control,
1607 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1608 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1609 if (BITS_SET(phy_control,
1610 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1611 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1614 phy_status &= phy_status_mask;
1617 * The PHY may be busy with some initial calibration and whatnot,
1618 * so the power state can take a while to actually change.
1620 if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
1621 phy_status_mask, phy_status, 10))
1622 drm_err(&dev_priv->drm,
1623 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1624 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1625 phy_status, dev_priv->chv_phy_control);
1630 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1631 struct i915_power_well *power_well)
1637 drm_WARN_ON_ONCE(&dev_priv->drm,
1638 power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1639 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1641 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1649 /* since ref/cri clock was enabled */
1650 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1651 vlv_set_power_well(dev_priv, power_well, true);
1653 /* Poll for phypwrgood signal */
1654 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1655 PHY_POWERGOOD(phy), 1))
1656 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1659 vlv_dpio_get(dev_priv);
1661 /* Enable dynamic power down */
1662 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1663 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1664 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1667 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1668 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1669 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1670 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1673 * Force the non-existing CL2 off. BXT does this
1674 * too, so maybe it saves some power even though
1675 * CL2 doesn't exist?
1677 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1678 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1679 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1682 vlv_dpio_put(dev_priv);
1684 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1685 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1686 dev_priv->chv_phy_control);
1688 drm_dbg_kms(&dev_priv->drm,
1689 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1690 phy, dev_priv->chv_phy_control);
1692 assert_chv_phy_status(dev_priv);
1695 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1696 struct i915_power_well *power_well)
1700 drm_WARN_ON_ONCE(&dev_priv->drm,
1701 power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
1702 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
1704 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
1706 assert_pll_disabled(dev_priv, PIPE_A);
1707 assert_pll_disabled(dev_priv, PIPE_B);
1710 assert_pll_disabled(dev_priv, PIPE_C);
1713 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1714 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1715 dev_priv->chv_phy_control);
1717 vlv_set_power_well(dev_priv, power_well, false);
1719 drm_dbg_kms(&dev_priv->drm,
1720 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1721 phy, dev_priv->chv_phy_control);
1723 /* PHY is fully reset now, so we can enable the PHY state asserts */
1724 dev_priv->chv_phy_assert[phy] = true;
1726 assert_chv_phy_status(dev_priv);
1729 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1730 enum dpio_channel ch, bool override, unsigned int mask)
1732 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1733 u32 reg, val, expected, actual;
1736 * The BIOS can leave the PHY is some weird state
1737 * where it doesn't fully power down some parts.
1738 * Disable the asserts until the PHY has been fully
1739 * reset (ie. the power well has been disabled at
1742 if (!dev_priv->chv_phy_assert[phy])
1746 reg = _CHV_CMN_DW0_CH0;
1748 reg = _CHV_CMN_DW6_CH1;
1750 vlv_dpio_get(dev_priv);
1751 val = vlv_dpio_read(dev_priv, pipe, reg);
1752 vlv_dpio_put(dev_priv);
1755 * This assumes !override is only used when the port is disabled.
1756 * All lanes should power down even without the override when
1757 * the port is disabled.
1759 if (!override || mask == 0xf) {
1760 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1762 * If CH1 common lane is not active anymore
1763 * (eg. for pipe B DPLL) the entire channel will
1764 * shut down, which causes the common lane registers
1765 * to read as 0. That means we can't actually check
1766 * the lane power down status bits, but as the entire
1767 * register reads as 0 it's a good indication that the
1768 * channel is indeed entirely powered down.
1770 if (ch == DPIO_CH1 && val == 0)
1772 } else if (mask != 0x0) {
1773 expected = DPIO_ANYDL_POWERDOWN;
1779 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1781 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1782 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1784 drm_WARN(&dev_priv->drm, actual != expected,
1785 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1786 !!(actual & DPIO_ALLDL_POWERDOWN),
1787 !!(actual & DPIO_ANYDL_POWERDOWN),
1788 !!(expected & DPIO_ALLDL_POWERDOWN),
1789 !!(expected & DPIO_ANYDL_POWERDOWN),
1793 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1794 enum dpio_channel ch, bool override)
1796 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1799 mutex_lock(&power_domains->lock);
1801 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1803 if (override == was_override)
1807 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1809 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1811 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1812 dev_priv->chv_phy_control);
1814 drm_dbg_kms(&dev_priv->drm,
1815 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1816 phy, ch, dev_priv->chv_phy_control);
1818 assert_chv_phy_status(dev_priv);
1821 mutex_unlock(&power_domains->lock);
1823 return was_override;
1826 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1827 bool override, unsigned int mask)
1829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1830 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1831 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1832 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1834 mutex_lock(&power_domains->lock);
1836 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1837 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1840 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1842 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1844 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1845 dev_priv->chv_phy_control);
1847 drm_dbg_kms(&dev_priv->drm,
1848 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1849 phy, ch, mask, dev_priv->chv_phy_control);
1851 assert_chv_phy_status(dev_priv);
1853 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1855 mutex_unlock(&power_domains->lock);
1858 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1859 struct i915_power_well *power_well)
1861 enum pipe pipe = PIPE_A;
1865 vlv_punit_get(dev_priv);
1867 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
1869 * We only ever set the power-on and power-gate states, anything
1870 * else is unexpected.
1872 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
1873 state != DP_SSS_PWR_GATE(pipe));
1874 enabled = state == DP_SSS_PWR_ON(pipe);
1877 * A transient state at this point would mean some unexpected party
1878 * is poking at the power controls too.
1880 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
1881 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
1883 vlv_punit_put(dev_priv);
1888 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1889 struct i915_power_well *power_well,
1892 enum pipe pipe = PIPE_A;
1896 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1898 vlv_punit_get(dev_priv);
1901 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1906 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
1907 ctrl &= ~DP_SSC_MASK(pipe);
1908 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1909 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
1911 if (wait_for(COND, 100))
1912 drm_err(&dev_priv->drm,
1913 "timeout setting power well state %08x (%08x)\n",
1915 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
1920 vlv_punit_put(dev_priv);
1923 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1924 struct i915_power_well *power_well)
1926 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1927 dev_priv->chv_phy_control);
1930 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1931 struct i915_power_well *power_well)
1933 chv_set_pipe_power_well(dev_priv, power_well, true);
1935 vlv_display_power_well_init(dev_priv);
1938 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1939 struct i915_power_well *power_well)
1941 vlv_display_power_well_deinit(dev_priv);
1943 chv_set_pipe_power_well(dev_priv, power_well, false);
1946 static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
1948 return power_domains->async_put_domains[0] |
1949 power_domains->async_put_domains[1];
1952 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1955 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
1957 struct drm_i915_private *i915 = container_of(power_domains,
1958 struct drm_i915_private,
1960 return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
1961 power_domains->async_put_domains[1]);
1965 __async_put_domains_state_ok(struct i915_power_domains *power_domains)
1967 struct drm_i915_private *i915 = container_of(power_domains,
1968 struct drm_i915_private,
1970 enum intel_display_power_domain domain;
1973 err |= !assert_async_put_domain_masks_disjoint(power_domains);
1974 err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
1975 !!__async_put_domains_mask(power_domains));
1977 for_each_power_domain(domain, __async_put_domains_mask(power_domains))
1978 err |= drm_WARN_ON(&i915->drm,
1979 power_domains->domain_use_count[domain] != 1);
1984 static void print_power_domains(struct i915_power_domains *power_domains,
1985 const char *prefix, u64 mask)
1987 struct drm_i915_private *i915 = container_of(power_domains,
1988 struct drm_i915_private,
1990 enum intel_display_power_domain domain;
1992 drm_dbg(&i915->drm, "%s (%lu):\n", prefix, hweight64(mask));
1993 for_each_power_domain(domain, mask)
1994 drm_dbg(&i915->drm, "%s use_count %d\n",
1995 intel_display_power_domain_str(domain),
1996 power_domains->domain_use_count[domain]);
2000 print_async_put_domains_state(struct i915_power_domains *power_domains)
2002 struct drm_i915_private *i915 = container_of(power_domains,
2003 struct drm_i915_private,
2006 drm_dbg(&i915->drm, "async_put_wakeref %u\n",
2007 power_domains->async_put_wakeref);
2009 print_power_domains(power_domains, "async_put_domains[0]",
2010 power_domains->async_put_domains[0]);
2011 print_power_domains(power_domains, "async_put_domains[1]",
2012 power_domains->async_put_domains[1]);
2016 verify_async_put_domains_state(struct i915_power_domains *power_domains)
2018 if (!__async_put_domains_state_ok(power_domains))
2019 print_async_put_domains_state(power_domains);
2025 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
2030 verify_async_put_domains_state(struct i915_power_domains *power_domains)
2034 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
2036 static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
2038 assert_async_put_domain_masks_disjoint(power_domains);
2040 return __async_put_domains_mask(power_domains);
2044 async_put_domains_clear_domain(struct i915_power_domains *power_domains,
2045 enum intel_display_power_domain domain)
2047 assert_async_put_domain_masks_disjoint(power_domains);
2049 power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
2050 power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
2054 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
2055 enum intel_display_power_domain domain)
2057 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2060 if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
2063 async_put_domains_clear_domain(power_domains, domain);
2067 if (async_put_domains_mask(power_domains))
2070 cancel_delayed_work(&power_domains->async_put_work);
2071 intel_runtime_pm_put_raw(&dev_priv->runtime_pm,
2072 fetch_and_zero(&power_domains->async_put_wakeref));
2074 verify_async_put_domains_state(power_domains);
2080 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
2081 enum intel_display_power_domain domain)
2083 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2084 struct i915_power_well *power_well;
2086 if (intel_display_power_grab_async_put_ref(dev_priv, domain))
2089 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
2090 intel_power_well_get(dev_priv, power_well);
2092 power_domains->domain_use_count[domain]++;
2096 * intel_display_power_get - grab a power domain reference
2097 * @dev_priv: i915 device instance
2098 * @domain: power domain to reference
2100 * This function grabs a power domain reference for @domain and ensures that the
2101 * power domain and all its parents are powered up. Therefore users should only
2102 * grab a reference to the innermost power domain they need.
2104 * Any power domain reference obtained by this function must have a symmetric
2105 * call to intel_display_power_put() to release the reference again.
2107 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2108 enum intel_display_power_domain domain)
2110 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2111 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2113 mutex_lock(&power_domains->lock);
2114 __intel_display_power_get_domain(dev_priv, domain);
2115 mutex_unlock(&power_domains->lock);
2121 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
2122 * @dev_priv: i915 device instance
2123 * @domain: power domain to reference
2125 * This function grabs a power domain reference for @domain and ensures that the
2126 * power domain and all its parents are powered up. Therefore users should only
2127 * grab a reference to the innermost power domain they need.
2129 * Any power domain reference obtained by this function must have a symmetric
2130 * call to intel_display_power_put() to release the reference again.
2133 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2134 enum intel_display_power_domain domain)
2136 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2137 intel_wakeref_t wakeref;
2140 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
2144 mutex_lock(&power_domains->lock);
2146 if (__intel_display_power_is_enabled(dev_priv, domain)) {
2147 __intel_display_power_get_domain(dev_priv, domain);
2153 mutex_unlock(&power_domains->lock);
2156 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2164 __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
2165 enum intel_display_power_domain domain)
2167 struct i915_power_domains *power_domains;
2168 struct i915_power_well *power_well;
2169 const char *name = intel_display_power_domain_str(domain);
2171 power_domains = &dev_priv->power_domains;
2173 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
2174 "Use count on domain %s is already zero\n",
2176 drm_WARN(&dev_priv->drm,
2177 async_put_domains_mask(power_domains) & BIT_ULL(domain),
2178 "Async disabling of domain %s is pending\n",
2181 power_domains->domain_use_count[domain]--;
2183 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
2184 intel_power_well_put(dev_priv, power_well);
2187 static void __intel_display_power_put(struct drm_i915_private *dev_priv,
2188 enum intel_display_power_domain domain)
2190 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2192 mutex_lock(&power_domains->lock);
2193 __intel_display_power_put_domain(dev_priv, domain);
2194 mutex_unlock(&power_domains->lock);
2198 queue_async_put_domains_work(struct i915_power_domains *power_domains,
2199 intel_wakeref_t wakeref)
2201 struct drm_i915_private *i915 = container_of(power_domains,
2202 struct drm_i915_private,
2204 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
2205 power_domains->async_put_wakeref = wakeref;
2206 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
2207 &power_domains->async_put_work,
2208 msecs_to_jiffies(100)));
2212 release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
2214 struct drm_i915_private *dev_priv =
2215 container_of(power_domains, struct drm_i915_private,
2217 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2218 enum intel_display_power_domain domain;
2219 intel_wakeref_t wakeref;
2222 * The caller must hold already raw wakeref, upgrade that to a proper
2223 * wakeref to make the state checker happy about the HW access during
2224 * power well disabling.
2226 assert_rpm_raw_wakeref_held(rpm);
2227 wakeref = intel_runtime_pm_get(rpm);
2229 for_each_power_domain(domain, mask) {
2230 /* Clear before put, so put's sanity check is happy. */
2231 async_put_domains_clear_domain(power_domains, domain);
2232 __intel_display_power_put_domain(dev_priv, domain);
2235 intel_runtime_pm_put(rpm, wakeref);
2239 intel_display_power_put_async_work(struct work_struct *work)
2241 struct drm_i915_private *dev_priv =
2242 container_of(work, struct drm_i915_private,
2243 power_domains.async_put_work.work);
2244 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2245 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2246 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
2247 intel_wakeref_t old_work_wakeref = 0;
2249 mutex_lock(&power_domains->lock);
2252 * Bail out if all the domain refs pending to be released were grabbed
2253 * by subsequent gets or a flush_work.
2255 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
2256 if (!old_work_wakeref)
2259 release_async_put_domains(power_domains,
2260 power_domains->async_put_domains[0]);
2262 /* Requeue the work if more domains were async put meanwhile. */
2263 if (power_domains->async_put_domains[1]) {
2264 power_domains->async_put_domains[0] =
2265 fetch_and_zero(&power_domains->async_put_domains[1]);
2266 queue_async_put_domains_work(power_domains,
2267 fetch_and_zero(&new_work_wakeref));
2270 * Cancel the work that got queued after this one got dequeued,
2271 * since here we released the corresponding async-put reference.
2273 cancel_delayed_work(&power_domains->async_put_work);
2277 verify_async_put_domains_state(power_domains);
2279 mutex_unlock(&power_domains->lock);
2281 if (old_work_wakeref)
2282 intel_runtime_pm_put_raw(rpm, old_work_wakeref);
2283 if (new_work_wakeref)
2284 intel_runtime_pm_put_raw(rpm, new_work_wakeref);
2288 * intel_display_power_put_async - release a power domain reference asynchronously
2289 * @i915: i915 device instance
2290 * @domain: power domain to reference
2291 * @wakeref: wakeref acquired for the reference that is being released
2293 * This function drops the power domain reference obtained by
2294 * intel_display_power_get*() and schedules a work to power down the
2295 * corresponding hardware block if this is the last reference.
2297 void __intel_display_power_put_async(struct drm_i915_private *i915,
2298 enum intel_display_power_domain domain,
2299 intel_wakeref_t wakeref)
2301 struct i915_power_domains *power_domains = &i915->power_domains;
2302 struct intel_runtime_pm *rpm = &i915->runtime_pm;
2303 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
2305 mutex_lock(&power_domains->lock);
2307 if (power_domains->domain_use_count[domain] > 1) {
2308 __intel_display_power_put_domain(i915, domain);
2313 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
2315 /* Let a pending work requeue itself or queue a new one. */
2316 if (power_domains->async_put_wakeref) {
2317 power_domains->async_put_domains[1] |= BIT_ULL(domain);
2319 power_domains->async_put_domains[0] |= BIT_ULL(domain);
2320 queue_async_put_domains_work(power_domains,
2321 fetch_and_zero(&work_wakeref));
2325 verify_async_put_domains_state(power_domains);
2327 mutex_unlock(&power_domains->lock);
2330 intel_runtime_pm_put_raw(rpm, work_wakeref);
2332 intel_runtime_pm_put(rpm, wakeref);
2336 * intel_display_power_flush_work - flushes the async display power disabling work
2337 * @i915: i915 device instance
2339 * Flushes any pending work that was scheduled by a preceding
2340 * intel_display_power_put_async() call, completing the disabling of the
2341 * corresponding power domains.
2343 * Note that the work handler function may still be running after this
2344 * function returns; to ensure that the work handler isn't running use
2345 * intel_display_power_flush_work_sync() instead.
2347 void intel_display_power_flush_work(struct drm_i915_private *i915)
2349 struct i915_power_domains *power_domains = &i915->power_domains;
2350 intel_wakeref_t work_wakeref;
2352 mutex_lock(&power_domains->lock);
2354 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
2358 release_async_put_domains(power_domains,
2359 async_put_domains_mask(power_domains));
2360 cancel_delayed_work(&power_domains->async_put_work);
2363 verify_async_put_domains_state(power_domains);
2365 mutex_unlock(&power_domains->lock);
2368 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref);
2372 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
2373 * @i915: i915 device instance
2375 * Like intel_display_power_flush_work(), but also ensure that the work
2376 * handler function is not running any more when this function returns.
2379 intel_display_power_flush_work_sync(struct drm_i915_private *i915)
2381 struct i915_power_domains *power_domains = &i915->power_domains;
2383 intel_display_power_flush_work(i915);
2384 cancel_delayed_work_sync(&power_domains->async_put_work);
2386 verify_async_put_domains_state(power_domains);
2388 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
2391 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2393 * intel_display_power_put - release a power domain reference
2394 * @dev_priv: i915 device instance
2395 * @domain: power domain to reference
2396 * @wakeref: wakeref acquired for the reference that is being released
2398 * This function drops the power domain reference obtained by
2399 * intel_display_power_get() and might power down the corresponding hardware
2400 * block right away if this is the last reference.
2402 void intel_display_power_put(struct drm_i915_private *dev_priv,
2403 enum intel_display_power_domain domain,
2404 intel_wakeref_t wakeref)
2406 __intel_display_power_put(dev_priv, domain);
2407 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2411 * intel_display_power_put_unchecked - release an unchecked power domain reference
2412 * @dev_priv: i915 device instance
2413 * @domain: power domain to reference
2415 * This function drops the power domain reference obtained by
2416 * intel_display_power_get() and might power down the corresponding hardware
2417 * block right away if this is the last reference.
2419 * This function is only for the power domain code's internal use to suppress wakeref
2420 * tracking when the correspondig debug kconfig option is disabled, should not
2421 * be used otherwise.
2423 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2424 enum intel_display_power_domain domain)
2426 __intel_display_power_put(dev_priv, domain);
2427 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
2432 intel_display_power_get_in_set(struct drm_i915_private *i915,
2433 struct intel_display_power_domain_set *power_domain_set,
2434 enum intel_display_power_domain domain)
2436 intel_wakeref_t __maybe_unused wf;
2438 drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
2440 wf = intel_display_power_get(i915, domain);
2441 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2442 power_domain_set->wakerefs[domain] = wf;
2444 power_domain_set->mask |= BIT_ULL(domain);
2448 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
2449 struct intel_display_power_domain_set *power_domain_set,
2450 enum intel_display_power_domain domain)
2454 drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
2456 wf = intel_display_power_get_if_enabled(i915, domain);
2460 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2461 power_domain_set->wakerefs[domain] = wf;
2463 power_domain_set->mask |= BIT_ULL(domain);
2469 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
2470 struct intel_display_power_domain_set *power_domain_set,
2473 enum intel_display_power_domain domain;
2475 drm_WARN_ON(&i915->drm, mask & ~power_domain_set->mask);
2477 for_each_power_domain(domain, mask) {
2478 intel_wakeref_t __maybe_unused wf = -1;
2480 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2481 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
2483 intel_display_power_put(i915, domain, wf);
2484 power_domain_set->mask &= ~BIT_ULL(domain);
2488 #define I830_PIPES_POWER_DOMAINS ( \
2489 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
2490 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2491 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
2492 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2493 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2494 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2495 BIT_ULL(POWER_DOMAIN_INIT))
2497 #define VLV_DISPLAY_POWER_DOMAINS ( \
2498 BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
2499 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
2500 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2501 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
2502 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2503 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2504 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2505 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2506 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2507 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
2508 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
2509 BIT_ULL(POWER_DOMAIN_VGA) | \
2510 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2511 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2512 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2513 BIT_ULL(POWER_DOMAIN_GMBUS) | \
2514 BIT_ULL(POWER_DOMAIN_INIT))
2516 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
2517 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2518 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2519 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
2520 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2521 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2522 BIT_ULL(POWER_DOMAIN_INIT))
2524 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
2525 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2526 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2527 BIT_ULL(POWER_DOMAIN_INIT))
2529 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
2530 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2531 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2532 BIT_ULL(POWER_DOMAIN_INIT))
2534 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
2535 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2536 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2537 BIT_ULL(POWER_DOMAIN_INIT))
2539 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
2540 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2541 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2542 BIT_ULL(POWER_DOMAIN_INIT))
2544 #define CHV_DISPLAY_POWER_DOMAINS ( \
2545 BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
2546 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
2547 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2548 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2549 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
2550 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2551 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2552 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2553 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2554 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2555 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2556 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2557 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2558 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
2559 BIT_ULL(POWER_DOMAIN_VGA) | \
2560 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2561 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2562 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2563 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2564 BIT_ULL(POWER_DOMAIN_GMBUS) | \
2565 BIT_ULL(POWER_DOMAIN_INIT))
2567 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
2568 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2569 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2570 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2571 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2572 BIT_ULL(POWER_DOMAIN_INIT))
2574 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
2575 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2576 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2577 BIT_ULL(POWER_DOMAIN_INIT))
2579 #define HSW_DISPLAY_POWER_DOMAINS ( \
2580 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2581 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2582 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
2583 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2584 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2585 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2586 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2587 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2588 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2589 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2590 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2591 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
2592 BIT_ULL(POWER_DOMAIN_VGA) | \
2593 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2594 BIT_ULL(POWER_DOMAIN_INIT))
2596 #define BDW_DISPLAY_POWER_DOMAINS ( \
2597 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2598 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2599 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2600 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2601 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2602 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2603 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2604 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2605 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2606 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2607 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
2608 BIT_ULL(POWER_DOMAIN_VGA) | \
2609 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2610 BIT_ULL(POWER_DOMAIN_INIT))
2612 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
2613 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2614 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2615 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2616 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2617 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2618 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2619 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2620 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2621 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2622 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2623 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
2624 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2625 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2626 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2627 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2628 BIT_ULL(POWER_DOMAIN_VGA) | \
2629 BIT_ULL(POWER_DOMAIN_INIT))
2630 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
2631 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
2632 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
2633 BIT_ULL(POWER_DOMAIN_INIT))
2634 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
2635 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
2636 BIT_ULL(POWER_DOMAIN_INIT))
2637 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
2638 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
2639 BIT_ULL(POWER_DOMAIN_INIT))
2640 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
2641 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
2642 BIT_ULL(POWER_DOMAIN_INIT))
2643 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2644 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
2645 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
2646 BIT_ULL(POWER_DOMAIN_MODESET) | \
2647 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2648 BIT_ULL(POWER_DOMAIN_INIT))
2650 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
2651 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2652 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2653 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2654 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2655 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2656 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2657 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2658 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2659 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2660 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2661 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2662 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2663 BIT_ULL(POWER_DOMAIN_VGA) | \
2664 BIT_ULL(POWER_DOMAIN_INIT))
2665 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2666 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
2667 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
2668 BIT_ULL(POWER_DOMAIN_MODESET) | \
2669 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2670 BIT_ULL(POWER_DOMAIN_GMBUS) | \
2671 BIT_ULL(POWER_DOMAIN_INIT))
2672 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
2673 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
2674 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2675 BIT_ULL(POWER_DOMAIN_INIT))
2676 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
2677 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2678 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2679 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2680 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2681 BIT_ULL(POWER_DOMAIN_INIT))
2683 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
2684 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2685 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2686 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2687 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2688 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2689 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2690 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2691 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2692 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2693 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2694 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2695 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2696 BIT_ULL(POWER_DOMAIN_VGA) | \
2697 BIT_ULL(POWER_DOMAIN_INIT))
2698 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
2699 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
2700 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
2701 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
2702 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
2703 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
2704 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
2705 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
2706 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2707 BIT_ULL(POWER_DOMAIN_INIT))
2708 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
2709 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2710 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2711 BIT_ULL(POWER_DOMAIN_INIT))
2712 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
2713 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2714 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2715 BIT_ULL(POWER_DOMAIN_INIT))
2716 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
2717 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2718 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
2719 BIT_ULL(POWER_DOMAIN_INIT))
2720 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
2721 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2722 BIT_ULL(POWER_DOMAIN_INIT))
2723 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
2724 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2725 BIT_ULL(POWER_DOMAIN_INIT))
2726 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2727 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
2728 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
2729 BIT_ULL(POWER_DOMAIN_MODESET) | \
2730 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2731 BIT_ULL(POWER_DOMAIN_GMBUS) | \
2732 BIT_ULL(POWER_DOMAIN_INIT))
2734 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
2735 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2736 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2737 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2738 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2739 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2740 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2741 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2742 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2743 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2744 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2745 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
2746 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2747 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2748 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2749 BIT_ULL(POWER_DOMAIN_AUX_F) | \
2750 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2751 BIT_ULL(POWER_DOMAIN_VGA) | \
2752 BIT_ULL(POWER_DOMAIN_INIT))
2753 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
2754 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
2755 BIT_ULL(POWER_DOMAIN_INIT))
2756 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
2757 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
2758 BIT_ULL(POWER_DOMAIN_INIT))
2759 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
2760 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
2761 BIT_ULL(POWER_DOMAIN_INIT))
2762 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
2763 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
2764 BIT_ULL(POWER_DOMAIN_INIT))
2765 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
2766 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2767 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
2768 BIT_ULL(POWER_DOMAIN_INIT))
2769 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
2770 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2771 BIT_ULL(POWER_DOMAIN_INIT))
2772 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
2773 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2774 BIT_ULL(POWER_DOMAIN_INIT))
2775 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
2776 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2777 BIT_ULL(POWER_DOMAIN_INIT))
2778 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
2779 BIT_ULL(POWER_DOMAIN_AUX_F) | \
2780 BIT_ULL(POWER_DOMAIN_INIT))
2781 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
2782 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
2783 BIT_ULL(POWER_DOMAIN_INIT))
2784 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2785 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
2786 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
2787 BIT_ULL(POWER_DOMAIN_MODESET) | \
2788 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2789 BIT_ULL(POWER_DOMAIN_INIT))
2792 * ICL PW_0/PG_0 domains (HW/DMC control):
2794 * - clocks except port PLL
2795 * - central power except FBC
2796 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
2797 * ICL PW_1/PG_1 domains (HW/DMC control):
2799 * - PIPE_A and its planes, except VGA
2800 * - transcoder EDP + PSR
2805 #define ICL_PW_4_POWER_DOMAINS ( \
2806 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2807 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2808 BIT_ULL(POWER_DOMAIN_INIT))
2810 #define ICL_PW_3_POWER_DOMAINS ( \
2811 ICL_PW_4_POWER_DOMAINS | \
2812 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2813 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
2814 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2815 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2816 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2817 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
2818 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
2819 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2820 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
2821 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
2822 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2823 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2824 BIT_ULL(POWER_DOMAIN_AUX_D) | \
2825 BIT_ULL(POWER_DOMAIN_AUX_E) | \
2826 BIT_ULL(POWER_DOMAIN_AUX_F) | \
2827 BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
2828 BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
2829 BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
2830 BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
2831 BIT_ULL(POWER_DOMAIN_VGA) | \
2832 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2833 BIT_ULL(POWER_DOMAIN_INIT))
2836 * - KVMR (HW control)
2838 #define ICL_PW_2_POWER_DOMAINS ( \
2839 ICL_PW_3_POWER_DOMAINS | \
2840 BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
2841 BIT_ULL(POWER_DOMAIN_INIT))
2843 * - KVMR (HW control)
2845 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2846 ICL_PW_2_POWER_DOMAINS | \
2847 BIT_ULL(POWER_DOMAIN_MODESET) | \
2848 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2849 BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) | \
2850 BIT_ULL(POWER_DOMAIN_INIT))
2852 #define ICL_DDI_IO_A_POWER_DOMAINS ( \
2853 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
2854 #define ICL_DDI_IO_B_POWER_DOMAINS ( \
2855 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
2856 #define ICL_DDI_IO_C_POWER_DOMAINS ( \
2857 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
2858 #define ICL_DDI_IO_D_POWER_DOMAINS ( \
2859 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
2860 #define ICL_DDI_IO_E_POWER_DOMAINS ( \
2861 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
2862 #define ICL_DDI_IO_F_POWER_DOMAINS ( \
2863 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
2865 #define ICL_AUX_A_IO_POWER_DOMAINS ( \
2866 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
2867 BIT_ULL(POWER_DOMAIN_AUX_A))
2868 #define ICL_AUX_B_IO_POWER_DOMAINS ( \
2869 BIT_ULL(POWER_DOMAIN_AUX_B))
2870 #define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
2871 BIT_ULL(POWER_DOMAIN_AUX_C))
2872 #define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
2873 BIT_ULL(POWER_DOMAIN_AUX_D))
2874 #define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
2875 BIT_ULL(POWER_DOMAIN_AUX_E))
2876 #define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
2877 BIT_ULL(POWER_DOMAIN_AUX_F))
2878 #define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
2879 BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
2880 #define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
2881 BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
2882 #define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
2883 BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
2884 #define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
2885 BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
2887 #define TGL_PW_5_POWER_DOMAINS ( \
2888 BIT_ULL(POWER_DOMAIN_PIPE_D) | \
2889 BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
2890 BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
2891 BIT_ULL(POWER_DOMAIN_INIT))
2893 #define TGL_PW_4_POWER_DOMAINS ( \
2894 TGL_PW_5_POWER_DOMAINS | \
2895 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2896 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2897 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2898 BIT_ULL(POWER_DOMAIN_INIT))
2900 #define TGL_PW_3_POWER_DOMAINS ( \
2901 TGL_PW_4_POWER_DOMAINS | \
2902 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2903 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2904 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2905 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
2906 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
2907 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
2908 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
2909 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
2910 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
2911 BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2912 BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
2913 BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
2914 BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
2915 BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
2916 BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
2917 BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
2918 BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
2919 BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
2920 BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
2921 BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
2922 BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
2923 BIT_ULL(POWER_DOMAIN_VGA) | \
2924 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2925 BIT_ULL(POWER_DOMAIN_INIT))
2927 #define TGL_PW_2_POWER_DOMAINS ( \
2928 TGL_PW_3_POWER_DOMAINS | \
2929 BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
2930 BIT_ULL(POWER_DOMAIN_INIT))
2932 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
2933 TGL_PW_3_POWER_DOMAINS | \
2934 BIT_ULL(POWER_DOMAIN_MODESET) | \
2935 BIT_ULL(POWER_DOMAIN_AUX_A) | \
2936 BIT_ULL(POWER_DOMAIN_AUX_B) | \
2937 BIT_ULL(POWER_DOMAIN_AUX_C) | \
2938 BIT_ULL(POWER_DOMAIN_INIT))
2940 #define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
2941 #define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
2942 #define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
2943 #define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
2944 #define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
2945 #define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
2947 #define TGL_AUX_A_IO_POWER_DOMAINS ( \
2948 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
2949 BIT_ULL(POWER_DOMAIN_AUX_A))
2950 #define TGL_AUX_B_IO_POWER_DOMAINS ( \
2951 BIT_ULL(POWER_DOMAIN_AUX_B))
2952 #define TGL_AUX_C_IO_POWER_DOMAINS ( \
2953 BIT_ULL(POWER_DOMAIN_AUX_C))
2955 #define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
2956 #define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
2957 #define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
2958 #define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
2959 #define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
2960 #define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
2962 #define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
2963 #define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
2964 #define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
2965 #define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
2966 #define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
2967 #define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
2969 #define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
2970 BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2971 BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
2972 BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
2973 BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
2974 BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
2975 BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
2976 BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
2977 BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
2978 BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
2979 BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
2980 BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
2981 BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
2982 BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
2984 #define RKL_PW_4_POWER_DOMAINS ( \
2985 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
2986 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
2987 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
2988 BIT_ULL(POWER_DOMAIN_INIT))
2990 #define RKL_PW_3_POWER_DOMAINS ( \
2991 RKL_PW_4_POWER_DOMAINS | \
2992 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
2993 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2994 BIT_ULL(POWER_DOMAIN_AUDIO) | \
2995 BIT_ULL(POWER_DOMAIN_VGA) | \
2996 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2997 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
2998 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
2999 BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
3000 BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
3001 BIT_ULL(POWER_DOMAIN_INIT))
3004 * There is no PW_2/PG_2 on RKL.
3006 * RKL PW_1/PG_1 domains (under HW/DMC control):
3007 * - DBUF function (note: registers are in PW0)
3008 * - PIPE_A and its planes and VDSC/joining, except VGA
3013 * RKL PW_0/PG_0 domains (under HW/DMC control):
3015 * - clocks except port PLL
3016 * - shared functions:
3017 * * interrupts except pipe interrupts
3018 * * MBus except PIPE_MBUS_DBOX_CTL
3020 * - central power except FBC
3021 * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
3024 #define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
3025 RKL_PW_3_POWER_DOMAINS | \
3026 BIT_ULL(POWER_DOMAIN_MODESET) | \
3027 BIT_ULL(POWER_DOMAIN_AUX_A) | \
3028 BIT_ULL(POWER_DOMAIN_AUX_B) | \
3029 BIT_ULL(POWER_DOMAIN_INIT))
3032 * XE_LPD Power Domains
3034 * Previous platforms required that PG(n-1) be enabled before PG(n). That
3035 * dependency chain turns into a dependency tree on XE_LPD:
3045 * Power wells must be enabled from top to bottom and disabled from bottom
3046 * to top. This allows pipes to be power gated independently.
3049 #define XELPD_PW_D_POWER_DOMAINS ( \
3050 BIT_ULL(POWER_DOMAIN_PIPE_D) | \
3051 BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
3052 BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
3053 BIT_ULL(POWER_DOMAIN_INIT))
3055 #define XELPD_PW_C_POWER_DOMAINS ( \
3056 BIT_ULL(POWER_DOMAIN_PIPE_C) | \
3057 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
3058 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
3059 BIT_ULL(POWER_DOMAIN_INIT))
3061 #define XELPD_PW_B_POWER_DOMAINS ( \
3062 BIT_ULL(POWER_DOMAIN_PIPE_B) | \
3063 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
3064 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
3065 BIT_ULL(POWER_DOMAIN_INIT))
3067 #define XELPD_PW_A_POWER_DOMAINS ( \
3068 BIT_ULL(POWER_DOMAIN_PIPE_A) | \
3069 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
3070 BIT_ULL(POWER_DOMAIN_INIT))
3072 #define XELPD_PW_2_POWER_DOMAINS ( \
3073 XELPD_PW_B_POWER_DOMAINS | \
3074 XELPD_PW_C_POWER_DOMAINS | \
3075 XELPD_PW_D_POWER_DOMAINS | \
3076 BIT_ULL(POWER_DOMAIN_AUDIO) | \
3077 BIT_ULL(POWER_DOMAIN_VGA) | \
3078 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
3079 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
3080 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
3081 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
3082 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
3083 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
3084 BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
3085 BIT_ULL(POWER_DOMAIN_AUX_C) | \
3086 BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
3087 BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
3088 BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
3089 BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
3090 BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
3091 BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
3092 BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
3093 BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
3094 BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
3095 BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
3096 BIT_ULL(POWER_DOMAIN_INIT))
3099 * XELPD PW_1/PG_1 domains (under HW/DMC control):
3100 * - DBUF function (registers are in PW0)
3104 * XELPD PW_0/PW_1 domains (under HW/DMC control):
3106 * - Clocks except port PLL
3107 * - Shared functions:
3108 * * interrupts except pipe interrupts
3109 * * MBus except PIPE_MBUS_DBOX_CTL
3111 * - Central power except FBC
3112 * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
3115 #define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
3116 XELPD_PW_2_POWER_DOMAINS | \
3117 BIT_ULL(POWER_DOMAIN_MODESET) | \
3118 BIT_ULL(POWER_DOMAIN_AUX_A) | \
3119 BIT_ULL(POWER_DOMAIN_AUX_B) | \
3120 BIT_ULL(POWER_DOMAIN_INIT))
3122 #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
3123 #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
3124 #define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
3125 #define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
3126 #define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
3127 #define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
3129 #define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
3130 #define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
3131 #define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
3132 #define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
3134 #define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
3135 #define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
3136 #define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
3137 #define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
3138 #define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
3139 #define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
3141 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
3142 .sync_hw = i9xx_power_well_sync_hw_noop,
3143 .enable = i9xx_always_on_power_well_noop,
3144 .disable = i9xx_always_on_power_well_noop,
3145 .is_enabled = i9xx_always_on_power_well_enabled,
3148 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
3149 .sync_hw = chv_pipe_power_well_sync_hw,
3150 .enable = chv_pipe_power_well_enable,
3151 .disable = chv_pipe_power_well_disable,
3152 .is_enabled = chv_pipe_power_well_enabled,
3155 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
3156 .sync_hw = i9xx_power_well_sync_hw_noop,
3157 .enable = chv_dpio_cmn_power_well_enable,
3158 .disable = chv_dpio_cmn_power_well_disable,
3159 .is_enabled = vlv_power_well_enabled,
3162 static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
3164 .name = "always-on",
3166 .domains = POWER_DOMAIN_MASK,
3167 .ops = &i9xx_always_on_power_well_ops,
3168 .id = DISP_PW_ID_NONE,
3172 static const struct i915_power_well_ops i830_pipes_power_well_ops = {
3173 .sync_hw = i830_pipes_power_well_sync_hw,
3174 .enable = i830_pipes_power_well_enable,
3175 .disable = i830_pipes_power_well_disable,
3176 .is_enabled = i830_pipes_power_well_enabled,
3179 static const struct i915_power_well_desc i830_power_wells[] = {
3181 .name = "always-on",
3183 .domains = POWER_DOMAIN_MASK,
3184 .ops = &i9xx_always_on_power_well_ops,
3185 .id = DISP_PW_ID_NONE,
3189 .domains = I830_PIPES_POWER_DOMAINS,
3190 .ops = &i830_pipes_power_well_ops,
3191 .id = DISP_PW_ID_NONE,
3195 static const struct i915_power_well_ops hsw_power_well_ops = {
3196 .sync_hw = hsw_power_well_sync_hw,
3197 .enable = hsw_power_well_enable,
3198 .disable = hsw_power_well_disable,
3199 .is_enabled = hsw_power_well_enabled,
3202 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
3203 .sync_hw = i9xx_power_well_sync_hw_noop,
3204 .enable = gen9_dc_off_power_well_enable,
3205 .disable = gen9_dc_off_power_well_disable,
3206 .is_enabled = gen9_dc_off_power_well_enabled,
3209 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
3210 .sync_hw = i9xx_power_well_sync_hw_noop,
3211 .enable = bxt_dpio_cmn_power_well_enable,
3212 .disable = bxt_dpio_cmn_power_well_disable,
3213 .is_enabled = bxt_dpio_cmn_power_well_enabled,
3216 static const struct i915_power_well_regs hsw_power_well_regs = {
3217 .bios = HSW_PWR_WELL_CTL1,
3218 .driver = HSW_PWR_WELL_CTL2,
3219 .kvmr = HSW_PWR_WELL_CTL3,
3220 .debug = HSW_PWR_WELL_CTL4,
3223 static const struct i915_power_well_desc hsw_power_wells[] = {
3225 .name = "always-on",
3227 .domains = POWER_DOMAIN_MASK,
3228 .ops = &i9xx_always_on_power_well_ops,
3229 .id = DISP_PW_ID_NONE,
3233 .domains = HSW_DISPLAY_POWER_DOMAINS,
3234 .ops = &hsw_power_well_ops,
3235 .id = HSW_DISP_PW_GLOBAL,
3237 .hsw.regs = &hsw_power_well_regs,
3238 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
3239 .hsw.has_vga = true,
3244 static const struct i915_power_well_desc bdw_power_wells[] = {
3246 .name = "always-on",
3248 .domains = POWER_DOMAIN_MASK,
3249 .ops = &i9xx_always_on_power_well_ops,
3250 .id = DISP_PW_ID_NONE,
3254 .domains = BDW_DISPLAY_POWER_DOMAINS,
3255 .ops = &hsw_power_well_ops,
3256 .id = HSW_DISP_PW_GLOBAL,
3258 .hsw.regs = &hsw_power_well_regs,
3259 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
3260 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3261 .hsw.has_vga = true,
3266 static const struct i915_power_well_ops vlv_display_power_well_ops = {
3267 .sync_hw = i9xx_power_well_sync_hw_noop,
3268 .enable = vlv_display_power_well_enable,
3269 .disable = vlv_display_power_well_disable,
3270 .is_enabled = vlv_power_well_enabled,
3273 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
3274 .sync_hw = i9xx_power_well_sync_hw_noop,
3275 .enable = vlv_dpio_cmn_power_well_enable,
3276 .disable = vlv_dpio_cmn_power_well_disable,
3277 .is_enabled = vlv_power_well_enabled,
3280 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
3281 .sync_hw = i9xx_power_well_sync_hw_noop,
3282 .enable = vlv_power_well_enable,
3283 .disable = vlv_power_well_disable,
3284 .is_enabled = vlv_power_well_enabled,
3287 static const struct i915_power_well_desc vlv_power_wells[] = {
3289 .name = "always-on",
3291 .domains = POWER_DOMAIN_MASK,
3292 .ops = &i9xx_always_on_power_well_ops,
3293 .id = DISP_PW_ID_NONE,
3297 .domains = VLV_DISPLAY_POWER_DOMAINS,
3298 .ops = &vlv_display_power_well_ops,
3299 .id = VLV_DISP_PW_DISP2D,
3301 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
3305 .name = "dpio-tx-b-01",
3306 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
3307 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
3308 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
3309 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
3310 .ops = &vlv_dpio_power_well_ops,
3311 .id = DISP_PW_ID_NONE,
3313 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
3317 .name = "dpio-tx-b-23",
3318 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
3319 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
3320 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
3321 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
3322 .ops = &vlv_dpio_power_well_ops,
3323 .id = DISP_PW_ID_NONE,
3325 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
3329 .name = "dpio-tx-c-01",
3330 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
3331 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
3332 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
3333 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
3334 .ops = &vlv_dpio_power_well_ops,
3335 .id = DISP_PW_ID_NONE,
3337 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
3341 .name = "dpio-tx-c-23",
3342 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
3343 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
3344 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
3345 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
3346 .ops = &vlv_dpio_power_well_ops,
3347 .id = DISP_PW_ID_NONE,
3349 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
3353 .name = "dpio-common",
3354 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
3355 .ops = &vlv_dpio_cmn_power_well_ops,
3356 .id = VLV_DISP_PW_DPIO_CMN_BC,
3358 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
3363 static const struct i915_power_well_desc chv_power_wells[] = {
3365 .name = "always-on",
3367 .domains = POWER_DOMAIN_MASK,
3368 .ops = &i9xx_always_on_power_well_ops,
3369 .id = DISP_PW_ID_NONE,
3374 * Pipe A power well is the new disp2d well. Pipe B and C
3375 * power wells don't actually exist. Pipe A power well is
3376 * required for any pipe to work.
3378 .domains = CHV_DISPLAY_POWER_DOMAINS,
3379 .ops = &chv_pipe_power_well_ops,
3380 .id = DISP_PW_ID_NONE,
3383 .name = "dpio-common-bc",
3384 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
3385 .ops = &chv_dpio_cmn_power_well_ops,
3386 .id = VLV_DISP_PW_DPIO_CMN_BC,
3388 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
3392 .name = "dpio-common-d",
3393 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
3394 .ops = &chv_dpio_cmn_power_well_ops,
3395 .id = CHV_DISP_PW_DPIO_CMN_D,
3397 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
3402 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
3403 enum i915_power_well_id power_well_id)
3405 struct i915_power_well *power_well;
3408 power_well = lookup_power_well(dev_priv, power_well_id);
3409 ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
3414 static const struct i915_power_well_desc skl_power_wells[] = {
3416 .name = "always-on",
3418 .domains = POWER_DOMAIN_MASK,
3419 .ops = &i9xx_always_on_power_well_ops,
3420 .id = DISP_PW_ID_NONE,
3423 .name = "power well 1",
3424 /* Handled by the DMC firmware */
3427 .ops = &hsw_power_well_ops,
3428 .id = SKL_DISP_PW_1,
3430 .hsw.regs = &hsw_power_well_regs,
3431 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
3432 .hsw.has_fuses = true,
3436 .name = "MISC IO power well",
3437 /* Handled by the DMC firmware */
3440 .ops = &hsw_power_well_ops,
3441 .id = SKL_DISP_PW_MISC_IO,
3443 .hsw.regs = &hsw_power_well_regs,
3444 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
3449 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
3450 .ops = &gen9_dc_off_power_well_ops,
3451 .id = SKL_DISP_DC_OFF,
3454 .name = "power well 2",
3455 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
3456 .ops = &hsw_power_well_ops,
3457 .id = SKL_DISP_PW_2,
3459 .hsw.regs = &hsw_power_well_regs,
3460 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
3461 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3462 .hsw.has_vga = true,
3463 .hsw.has_fuses = true,
3467 .name = "DDI A/E IO power well",
3468 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
3469 .ops = &hsw_power_well_ops,
3470 .id = DISP_PW_ID_NONE,
3472 .hsw.regs = &hsw_power_well_regs,
3473 .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
3477 .name = "DDI B IO power well",
3478 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
3479 .ops = &hsw_power_well_ops,
3480 .id = DISP_PW_ID_NONE,
3482 .hsw.regs = &hsw_power_well_regs,
3483 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
3487 .name = "DDI C IO power well",
3488 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
3489 .ops = &hsw_power_well_ops,
3490 .id = DISP_PW_ID_NONE,
3492 .hsw.regs = &hsw_power_well_regs,
3493 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
3497 .name = "DDI D IO power well",
3498 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
3499 .ops = &hsw_power_well_ops,
3500 .id = DISP_PW_ID_NONE,
3502 .hsw.regs = &hsw_power_well_regs,
3503 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
3508 static const struct i915_power_well_desc bxt_power_wells[] = {
3510 .name = "always-on",
3512 .domains = POWER_DOMAIN_MASK,
3513 .ops = &i9xx_always_on_power_well_ops,
3514 .id = DISP_PW_ID_NONE,
3517 .name = "power well 1",
3518 /* Handled by the DMC firmware */
3521 .ops = &hsw_power_well_ops,
3522 .id = SKL_DISP_PW_1,
3524 .hsw.regs = &hsw_power_well_regs,
3525 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
3526 .hsw.has_fuses = true,
3531 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
3532 .ops = &gen9_dc_off_power_well_ops,
3533 .id = SKL_DISP_DC_OFF,
3536 .name = "power well 2",
3537 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
3538 .ops = &hsw_power_well_ops,
3539 .id = SKL_DISP_PW_2,
3541 .hsw.regs = &hsw_power_well_regs,
3542 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
3543 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3544 .hsw.has_vga = true,
3545 .hsw.has_fuses = true,
3549 .name = "dpio-common-a",
3550 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
3551 .ops = &bxt_dpio_cmn_power_well_ops,
3552 .id = BXT_DISP_PW_DPIO_CMN_A,
3554 .bxt.phy = DPIO_PHY1,
3558 .name = "dpio-common-bc",
3559 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
3560 .ops = &bxt_dpio_cmn_power_well_ops,
3561 .id = VLV_DISP_PW_DPIO_CMN_BC,
3563 .bxt.phy = DPIO_PHY0,
3568 static const struct i915_power_well_desc glk_power_wells[] = {
3570 .name = "always-on",
3572 .domains = POWER_DOMAIN_MASK,
3573 .ops = &i9xx_always_on_power_well_ops,
3574 .id = DISP_PW_ID_NONE,
3577 .name = "power well 1",
3578 /* Handled by the DMC firmware */
3581 .ops = &hsw_power_well_ops,
3582 .id = SKL_DISP_PW_1,
3584 .hsw.regs = &hsw_power_well_regs,
3585 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
3586 .hsw.has_fuses = true,
3591 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
3592 .ops = &gen9_dc_off_power_well_ops,
3593 .id = SKL_DISP_DC_OFF,
3596 .name = "power well 2",
3597 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
3598 .ops = &hsw_power_well_ops,
3599 .id = SKL_DISP_PW_2,
3601 .hsw.regs = &hsw_power_well_regs,
3602 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
3603 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3604 .hsw.has_vga = true,
3605 .hsw.has_fuses = true,
3609 .name = "dpio-common-a",
3610 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
3611 .ops = &bxt_dpio_cmn_power_well_ops,
3612 .id = BXT_DISP_PW_DPIO_CMN_A,
3614 .bxt.phy = DPIO_PHY1,
3618 .name = "dpio-common-b",
3619 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
3620 .ops = &bxt_dpio_cmn_power_well_ops,
3621 .id = VLV_DISP_PW_DPIO_CMN_BC,
3623 .bxt.phy = DPIO_PHY0,
3627 .name = "dpio-common-c",
3628 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
3629 .ops = &bxt_dpio_cmn_power_well_ops,
3630 .id = GLK_DISP_PW_DPIO_CMN_C,
3632 .bxt.phy = DPIO_PHY2,
3637 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
3638 .ops = &hsw_power_well_ops,
3639 .id = DISP_PW_ID_NONE,
3641 .hsw.regs = &hsw_power_well_regs,
3642 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
3647 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
3648 .ops = &hsw_power_well_ops,
3649 .id = DISP_PW_ID_NONE,
3651 .hsw.regs = &hsw_power_well_regs,
3652 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
3657 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
3658 .ops = &hsw_power_well_ops,
3659 .id = DISP_PW_ID_NONE,
3661 .hsw.regs = &hsw_power_well_regs,
3662 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
3666 .name = "DDI A IO power well",
3667 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
3668 .ops = &hsw_power_well_ops,
3669 .id = DISP_PW_ID_NONE,
3671 .hsw.regs = &hsw_power_well_regs,
3672 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
3676 .name = "DDI B IO power well",
3677 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
3678 .ops = &hsw_power_well_ops,
3679 .id = DISP_PW_ID_NONE,
3681 .hsw.regs = &hsw_power_well_regs,
3682 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
3686 .name = "DDI C IO power well",
3687 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
3688 .ops = &hsw_power_well_ops,
3689 .id = DISP_PW_ID_NONE,
3691 .hsw.regs = &hsw_power_well_regs,
3692 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
3697 static const struct i915_power_well_desc cnl_power_wells[] = {
3699 .name = "always-on",
3701 .domains = POWER_DOMAIN_MASK,
3702 .ops = &i9xx_always_on_power_well_ops,
3703 .id = DISP_PW_ID_NONE,
3706 .name = "power well 1",
3707 /* Handled by the DMC firmware */
3710 .ops = &hsw_power_well_ops,
3711 .id = SKL_DISP_PW_1,
3713 .hsw.regs = &hsw_power_well_regs,
3714 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
3715 .hsw.has_fuses = true,
3720 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
3721 .ops = &hsw_power_well_ops,
3722 .id = DISP_PW_ID_NONE,
3724 .hsw.regs = &hsw_power_well_regs,
3725 .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
3730 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
3731 .ops = &hsw_power_well_ops,
3732 .id = DISP_PW_ID_NONE,
3734 .hsw.regs = &hsw_power_well_regs,
3735 .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
3740 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
3741 .ops = &hsw_power_well_ops,
3742 .id = DISP_PW_ID_NONE,
3744 .hsw.regs = &hsw_power_well_regs,
3745 .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
3750 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
3751 .ops = &hsw_power_well_ops,
3752 .id = DISP_PW_ID_NONE,
3754 .hsw.regs = &hsw_power_well_regs,
3755 .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
3760 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
3761 .ops = &gen9_dc_off_power_well_ops,
3762 .id = SKL_DISP_DC_OFF,
3765 .name = "power well 2",
3766 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
3767 .ops = &hsw_power_well_ops,
3768 .id = SKL_DISP_PW_2,
3770 .hsw.regs = &hsw_power_well_regs,
3771 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
3772 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3773 .hsw.has_vga = true,
3774 .hsw.has_fuses = true,
3778 .name = "DDI A IO power well",
3779 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
3780 .ops = &hsw_power_well_ops,
3781 .id = DISP_PW_ID_NONE,
3783 .hsw.regs = &hsw_power_well_regs,
3784 .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
3788 .name = "DDI B IO power well",
3789 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
3790 .ops = &hsw_power_well_ops,
3791 .id = DISP_PW_ID_NONE,
3793 .hsw.regs = &hsw_power_well_regs,
3794 .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
3798 .name = "DDI C IO power well",
3799 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
3800 .ops = &hsw_power_well_ops,
3801 .id = DISP_PW_ID_NONE,
3803 .hsw.regs = &hsw_power_well_regs,
3804 .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
3808 .name = "DDI D IO power well",
3809 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
3810 .ops = &hsw_power_well_ops,
3811 .id = DISP_PW_ID_NONE,
3813 .hsw.regs = &hsw_power_well_regs,
3814 .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
3818 .name = "DDI F IO power well",
3819 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
3820 .ops = &hsw_power_well_ops,
3821 .id = CNL_DISP_PW_DDI_F_IO,
3823 .hsw.regs = &hsw_power_well_regs,
3824 .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
3829 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
3830 .ops = &hsw_power_well_ops,
3831 .id = CNL_DISP_PW_DDI_F_AUX,
3833 .hsw.regs = &hsw_power_well_regs,
3834 .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
3839 static const struct i915_power_well_ops icl_aux_power_well_ops = {
3840 .sync_hw = hsw_power_well_sync_hw,
3841 .enable = icl_aux_power_well_enable,
3842 .disable = icl_aux_power_well_disable,
3843 .is_enabled = hsw_power_well_enabled,
3846 static const struct i915_power_well_regs icl_aux_power_well_regs = {
3847 .bios = ICL_PWR_WELL_CTL_AUX1,
3848 .driver = ICL_PWR_WELL_CTL_AUX2,
3849 .debug = ICL_PWR_WELL_CTL_AUX4,
3852 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
3853 .bios = ICL_PWR_WELL_CTL_DDI1,
3854 .driver = ICL_PWR_WELL_CTL_DDI2,
3855 .debug = ICL_PWR_WELL_CTL_DDI4,
3858 static const struct i915_power_well_desc icl_power_wells[] = {
3860 .name = "always-on",
3862 .domains = POWER_DOMAIN_MASK,
3863 .ops = &i9xx_always_on_power_well_ops,
3864 .id = DISP_PW_ID_NONE,
3867 .name = "power well 1",
3868 /* Handled by the DMC firmware */
3871 .ops = &hsw_power_well_ops,
3872 .id = SKL_DISP_PW_1,
3874 .hsw.regs = &hsw_power_well_regs,
3875 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
3876 .hsw.has_fuses = true,
3881 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
3882 .ops = &gen9_dc_off_power_well_ops,
3883 .id = SKL_DISP_DC_OFF,
3886 .name = "power well 2",
3887 .domains = ICL_PW_2_POWER_DOMAINS,
3888 .ops = &hsw_power_well_ops,
3889 .id = SKL_DISP_PW_2,
3891 .hsw.regs = &hsw_power_well_regs,
3892 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
3893 .hsw.has_fuses = true,
3897 .name = "power well 3",
3898 .domains = ICL_PW_3_POWER_DOMAINS,
3899 .ops = &hsw_power_well_ops,
3900 .id = ICL_DISP_PW_3,
3902 .hsw.regs = &hsw_power_well_regs,
3903 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
3904 .hsw.irq_pipe_mask = BIT(PIPE_B),
3905 .hsw.has_vga = true,
3906 .hsw.has_fuses = true,
3911 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
3912 .ops = &hsw_power_well_ops,
3913 .id = DISP_PW_ID_NONE,
3915 .hsw.regs = &icl_ddi_power_well_regs,
3916 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
3921 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
3922 .ops = &hsw_power_well_ops,
3923 .id = DISP_PW_ID_NONE,
3925 .hsw.regs = &icl_ddi_power_well_regs,
3926 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
3931 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
3932 .ops = &hsw_power_well_ops,
3933 .id = DISP_PW_ID_NONE,
3935 .hsw.regs = &icl_ddi_power_well_regs,
3936 .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
3941 .domains = ICL_DDI_IO_D_POWER_DOMAINS,
3942 .ops = &hsw_power_well_ops,
3943 .id = DISP_PW_ID_NONE,
3945 .hsw.regs = &icl_ddi_power_well_regs,
3946 .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
3951 .domains = ICL_DDI_IO_E_POWER_DOMAINS,
3952 .ops = &hsw_power_well_ops,
3953 .id = DISP_PW_ID_NONE,
3955 .hsw.regs = &icl_ddi_power_well_regs,
3956 .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
3961 .domains = ICL_DDI_IO_F_POWER_DOMAINS,
3962 .ops = &hsw_power_well_ops,
3963 .id = DISP_PW_ID_NONE,
3965 .hsw.regs = &icl_ddi_power_well_regs,
3966 .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
3971 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
3972 .ops = &icl_aux_power_well_ops,
3973 .id = DISP_PW_ID_NONE,
3975 .hsw.regs = &icl_aux_power_well_regs,
3976 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
3981 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
3982 .ops = &icl_aux_power_well_ops,
3983 .id = DISP_PW_ID_NONE,
3985 .hsw.regs = &icl_aux_power_well_regs,
3986 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
3990 .name = "AUX C TC1",
3991 .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
3992 .ops = &icl_aux_power_well_ops,
3993 .id = DISP_PW_ID_NONE,
3995 .hsw.regs = &icl_aux_power_well_regs,
3996 .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
3997 .hsw.is_tc_tbt = false,
4001 .name = "AUX D TC2",
4002 .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
4003 .ops = &icl_aux_power_well_ops,
4004 .id = DISP_PW_ID_NONE,
4006 .hsw.regs = &icl_aux_power_well_regs,
4007 .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
4008 .hsw.is_tc_tbt = false,
4012 .name = "AUX E TC3",
4013 .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
4014 .ops = &icl_aux_power_well_ops,
4015 .id = DISP_PW_ID_NONE,
4017 .hsw.regs = &icl_aux_power_well_regs,
4018 .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
4019 .hsw.is_tc_tbt = false,
4023 .name = "AUX F TC4",
4024 .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
4025 .ops = &icl_aux_power_well_ops,
4026 .id = DISP_PW_ID_NONE,
4028 .hsw.regs = &icl_aux_power_well_regs,
4029 .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
4030 .hsw.is_tc_tbt = false,
4034 .name = "AUX C TBT1",
4035 .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
4036 .ops = &icl_aux_power_well_ops,
4037 .id = DISP_PW_ID_NONE,
4039 .hsw.regs = &icl_aux_power_well_regs,
4040 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
4041 .hsw.is_tc_tbt = true,
4045 .name = "AUX D TBT2",
4046 .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
4047 .ops = &icl_aux_power_well_ops,
4048 .id = DISP_PW_ID_NONE,
4050 .hsw.regs = &icl_aux_power_well_regs,
4051 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
4052 .hsw.is_tc_tbt = true,
4056 .name = "AUX E TBT3",
4057 .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
4058 .ops = &icl_aux_power_well_ops,
4059 .id = DISP_PW_ID_NONE,
4061 .hsw.regs = &icl_aux_power_well_regs,
4062 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
4063 .hsw.is_tc_tbt = true,
4067 .name = "AUX F TBT4",
4068 .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
4069 .ops = &icl_aux_power_well_ops,
4070 .id = DISP_PW_ID_NONE,
4072 .hsw.regs = &icl_aux_power_well_regs,
4073 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
4074 .hsw.is_tc_tbt = true,
4078 .name = "power well 4",
4079 .domains = ICL_PW_4_POWER_DOMAINS,
4080 .ops = &hsw_power_well_ops,
4081 .id = DISP_PW_ID_NONE,
4083 .hsw.regs = &hsw_power_well_regs,
4084 .hsw.idx = ICL_PW_CTL_IDX_PW_4,
4085 .hsw.has_fuses = true,
4086 .hsw.irq_pipe_mask = BIT(PIPE_C),
4092 tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
4102 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
4104 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
4107 * Spec states that we should timeout the request after 200us
4108 * but the function below will timeout after 500us
4110 ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
4114 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
4127 drm_err(&i915->drm, "TC cold %sblock failed\n",
4130 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
4135 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
4136 struct i915_power_well *power_well)
4138 tgl_tc_cold_request(i915, true);
4142 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
4143 struct i915_power_well *power_well)
4145 tgl_tc_cold_request(i915, false);
4149 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
4150 struct i915_power_well *power_well)
4152 if (power_well->count > 0)
4153 tgl_tc_cold_off_power_well_enable(i915, power_well);
4155 tgl_tc_cold_off_power_well_disable(i915, power_well);
4159 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
4160 struct i915_power_well *power_well)
4163 * Not the correctly implementation but there is no way to just read it
4164 * from PCODE, so returning count to avoid state mismatch errors
4166 return power_well->count;
4169 static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
4170 .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
4171 .enable = tgl_tc_cold_off_power_well_enable,
4172 .disable = tgl_tc_cold_off_power_well_disable,
4173 .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
4176 static const struct i915_power_well_desc tgl_power_wells[] = {
4178 .name = "always-on",
4180 .domains = POWER_DOMAIN_MASK,
4181 .ops = &i9xx_always_on_power_well_ops,
4182 .id = DISP_PW_ID_NONE,
4185 .name = "power well 1",
4186 /* Handled by the DMC firmware */
4189 .ops = &hsw_power_well_ops,
4190 .id = SKL_DISP_PW_1,
4192 .hsw.regs = &hsw_power_well_regs,
4193 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
4194 .hsw.has_fuses = true,
4199 .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
4200 .ops = &gen9_dc_off_power_well_ops,
4201 .id = SKL_DISP_DC_OFF,
4204 .name = "power well 2",
4205 .domains = TGL_PW_2_POWER_DOMAINS,
4206 .ops = &hsw_power_well_ops,
4207 .id = SKL_DISP_PW_2,
4209 .hsw.regs = &hsw_power_well_regs,
4210 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
4211 .hsw.has_fuses = true,
4215 .name = "power well 3",
4216 .domains = TGL_PW_3_POWER_DOMAINS,
4217 .ops = &hsw_power_well_ops,
4218 .id = ICL_DISP_PW_3,
4220 .hsw.regs = &hsw_power_well_regs,
4221 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
4222 .hsw.irq_pipe_mask = BIT(PIPE_B),
4223 .hsw.has_vga = true,
4224 .hsw.has_fuses = true,
4229 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
4230 .ops = &hsw_power_well_ops,
4231 .id = DISP_PW_ID_NONE,
4233 .hsw.regs = &icl_ddi_power_well_regs,
4234 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
4239 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
4240 .ops = &hsw_power_well_ops,
4241 .id = DISP_PW_ID_NONE,
4243 .hsw.regs = &icl_ddi_power_well_regs,
4244 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
4249 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
4250 .ops = &hsw_power_well_ops,
4251 .id = DISP_PW_ID_NONE,
4253 .hsw.regs = &icl_ddi_power_well_regs,
4254 .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
4258 .name = "DDI IO TC1",
4259 .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
4260 .ops = &hsw_power_well_ops,
4261 .id = DISP_PW_ID_NONE,
4263 .hsw.regs = &icl_ddi_power_well_regs,
4264 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
4268 .name = "DDI IO TC2",
4269 .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
4270 .ops = &hsw_power_well_ops,
4271 .id = DISP_PW_ID_NONE,
4273 .hsw.regs = &icl_ddi_power_well_regs,
4274 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
4278 .name = "DDI IO TC3",
4279 .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
4280 .ops = &hsw_power_well_ops,
4281 .id = DISP_PW_ID_NONE,
4283 .hsw.regs = &icl_ddi_power_well_regs,
4284 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
4288 .name = "DDI IO TC4",
4289 .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
4290 .ops = &hsw_power_well_ops,
4291 .id = DISP_PW_ID_NONE,
4293 .hsw.regs = &icl_ddi_power_well_regs,
4294 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
4298 .name = "DDI IO TC5",
4299 .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
4300 .ops = &hsw_power_well_ops,
4301 .id = DISP_PW_ID_NONE,
4303 .hsw.regs = &icl_ddi_power_well_regs,
4304 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
4308 .name = "DDI IO TC6",
4309 .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
4310 .ops = &hsw_power_well_ops,
4311 .id = DISP_PW_ID_NONE,
4313 .hsw.regs = &icl_ddi_power_well_regs,
4314 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
4318 .name = "TC cold off",
4319 .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
4320 .ops = &tgl_tc_cold_off_ops,
4321 .id = TGL_DISP_PW_TC_COLD_OFF,
4325 .domains = TGL_AUX_A_IO_POWER_DOMAINS,
4326 .ops = &icl_aux_power_well_ops,
4327 .id = DISP_PW_ID_NONE,
4329 .hsw.regs = &icl_aux_power_well_regs,
4330 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
4335 .domains = TGL_AUX_B_IO_POWER_DOMAINS,
4336 .ops = &icl_aux_power_well_ops,
4337 .id = DISP_PW_ID_NONE,
4339 .hsw.regs = &icl_aux_power_well_regs,
4340 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
4345 .domains = TGL_AUX_C_IO_POWER_DOMAINS,
4346 .ops = &icl_aux_power_well_ops,
4347 .id = DISP_PW_ID_NONE,
4349 .hsw.regs = &icl_aux_power_well_regs,
4350 .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
4354 .name = "AUX USBC1",
4355 .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
4356 .ops = &icl_aux_power_well_ops,
4357 .id = DISP_PW_ID_NONE,
4359 .hsw.regs = &icl_aux_power_well_regs,
4360 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
4361 .hsw.is_tc_tbt = false,
4365 .name = "AUX USBC2",
4366 .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
4367 .ops = &icl_aux_power_well_ops,
4368 .id = DISP_PW_ID_NONE,
4370 .hsw.regs = &icl_aux_power_well_regs,
4371 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
4372 .hsw.is_tc_tbt = false,
4376 .name = "AUX USBC3",
4377 .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
4378 .ops = &icl_aux_power_well_ops,
4379 .id = DISP_PW_ID_NONE,
4381 .hsw.regs = &icl_aux_power_well_regs,
4382 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
4383 .hsw.is_tc_tbt = false,
4387 .name = "AUX USBC4",
4388 .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
4389 .ops = &icl_aux_power_well_ops,
4390 .id = DISP_PW_ID_NONE,
4392 .hsw.regs = &icl_aux_power_well_regs,
4393 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
4394 .hsw.is_tc_tbt = false,
4398 .name = "AUX USBC5",
4399 .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
4400 .ops = &icl_aux_power_well_ops,
4401 .id = DISP_PW_ID_NONE,
4403 .hsw.regs = &icl_aux_power_well_regs,
4404 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
4405 .hsw.is_tc_tbt = false,
4409 .name = "AUX USBC6",
4410 .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
4411 .ops = &icl_aux_power_well_ops,
4412 .id = DISP_PW_ID_NONE,
4414 .hsw.regs = &icl_aux_power_well_regs,
4415 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
4416 .hsw.is_tc_tbt = false,
4421 .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
4422 .ops = &icl_aux_power_well_ops,
4423 .id = DISP_PW_ID_NONE,
4425 .hsw.regs = &icl_aux_power_well_regs,
4426 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
4427 .hsw.is_tc_tbt = true,
4432 .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
4433 .ops = &icl_aux_power_well_ops,
4434 .id = DISP_PW_ID_NONE,
4436 .hsw.regs = &icl_aux_power_well_regs,
4437 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
4438 .hsw.is_tc_tbt = true,
4443 .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
4444 .ops = &icl_aux_power_well_ops,
4445 .id = DISP_PW_ID_NONE,
4447 .hsw.regs = &icl_aux_power_well_regs,
4448 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
4449 .hsw.is_tc_tbt = true,
4454 .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
4455 .ops = &icl_aux_power_well_ops,
4456 .id = DISP_PW_ID_NONE,
4458 .hsw.regs = &icl_aux_power_well_regs,
4459 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
4460 .hsw.is_tc_tbt = true,
4465 .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
4466 .ops = &icl_aux_power_well_ops,
4467 .id = DISP_PW_ID_NONE,
4469 .hsw.regs = &icl_aux_power_well_regs,
4470 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
4471 .hsw.is_tc_tbt = true,
4476 .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
4477 .ops = &icl_aux_power_well_ops,
4478 .id = DISP_PW_ID_NONE,
4480 .hsw.regs = &icl_aux_power_well_regs,
4481 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
4482 .hsw.is_tc_tbt = true,
4486 .name = "power well 4",
4487 .domains = TGL_PW_4_POWER_DOMAINS,
4488 .ops = &hsw_power_well_ops,
4489 .id = DISP_PW_ID_NONE,
4491 .hsw.regs = &hsw_power_well_regs,
4492 .hsw.idx = ICL_PW_CTL_IDX_PW_4,
4493 .hsw.has_fuses = true,
4494 .hsw.irq_pipe_mask = BIT(PIPE_C),
4498 .name = "power well 5",
4499 .domains = TGL_PW_5_POWER_DOMAINS,
4500 .ops = &hsw_power_well_ops,
4501 .id = DISP_PW_ID_NONE,
4503 .hsw.regs = &hsw_power_well_regs,
4504 .hsw.idx = TGL_PW_CTL_IDX_PW_5,
4505 .hsw.has_fuses = true,
4506 .hsw.irq_pipe_mask = BIT(PIPE_D),
4511 static const struct i915_power_well_desc rkl_power_wells[] = {
4513 .name = "always-on",
4515 .domains = POWER_DOMAIN_MASK,
4516 .ops = &i9xx_always_on_power_well_ops,
4517 .id = DISP_PW_ID_NONE,
4520 .name = "power well 1",
4521 /* Handled by the DMC firmware */
4524 .ops = &hsw_power_well_ops,
4525 .id = SKL_DISP_PW_1,
4527 .hsw.regs = &hsw_power_well_regs,
4528 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
4529 .hsw.has_fuses = true,
4534 .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
4535 .ops = &gen9_dc_off_power_well_ops,
4536 .id = SKL_DISP_DC_OFF,
4539 .name = "power well 3",
4540 .domains = RKL_PW_3_POWER_DOMAINS,
4541 .ops = &hsw_power_well_ops,
4542 .id = ICL_DISP_PW_3,
4544 .hsw.regs = &hsw_power_well_regs,
4545 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
4546 .hsw.irq_pipe_mask = BIT(PIPE_B),
4547 .hsw.has_vga = true,
4548 .hsw.has_fuses = true,
4552 .name = "power well 4",
4553 .domains = RKL_PW_4_POWER_DOMAINS,
4554 .ops = &hsw_power_well_ops,
4555 .id = DISP_PW_ID_NONE,
4557 .hsw.regs = &hsw_power_well_regs,
4558 .hsw.idx = ICL_PW_CTL_IDX_PW_4,
4559 .hsw.has_fuses = true,
4560 .hsw.irq_pipe_mask = BIT(PIPE_C),
4565 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
4566 .ops = &hsw_power_well_ops,
4567 .id = DISP_PW_ID_NONE,
4569 .hsw.regs = &icl_ddi_power_well_regs,
4570 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
4575 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
4576 .ops = &hsw_power_well_ops,
4577 .id = DISP_PW_ID_NONE,
4579 .hsw.regs = &icl_ddi_power_well_regs,
4580 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
4584 .name = "DDI IO TC1",
4585 .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
4586 .ops = &hsw_power_well_ops,
4587 .id = DISP_PW_ID_NONE,
4589 .hsw.regs = &icl_ddi_power_well_regs,
4590 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
4594 .name = "DDI IO TC2",
4595 .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
4596 .ops = &hsw_power_well_ops,
4597 .id = DISP_PW_ID_NONE,
4599 .hsw.regs = &icl_ddi_power_well_regs,
4600 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
4605 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
4606 .ops = &icl_aux_power_well_ops,
4607 .id = DISP_PW_ID_NONE,
4609 .hsw.regs = &icl_aux_power_well_regs,
4610 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
4615 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
4616 .ops = &icl_aux_power_well_ops,
4617 .id = DISP_PW_ID_NONE,
4619 .hsw.regs = &icl_aux_power_well_regs,
4620 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
4624 .name = "AUX USBC1",
4625 .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
4626 .ops = &icl_aux_power_well_ops,
4627 .id = DISP_PW_ID_NONE,
4629 .hsw.regs = &icl_aux_power_well_regs,
4630 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
4634 .name = "AUX USBC2",
4635 .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
4636 .ops = &icl_aux_power_well_ops,
4637 .id = DISP_PW_ID_NONE,
4639 .hsw.regs = &icl_aux_power_well_regs,
4640 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
4645 static const struct i915_power_well_desc xelpd_power_wells[] = {
4647 .name = "always-on",
4649 .domains = POWER_DOMAIN_MASK,
4650 .ops = &i9xx_always_on_power_well_ops,
4651 .id = DISP_PW_ID_NONE,
4654 .name = "power well 1",
4655 /* Handled by the DMC firmware */
4658 .ops = &hsw_power_well_ops,
4659 .id = SKL_DISP_PW_1,
4661 .hsw.regs = &hsw_power_well_regs,
4662 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
4663 .hsw.has_fuses = true,
4668 .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
4669 .ops = &gen9_dc_off_power_well_ops,
4670 .id = SKL_DISP_DC_OFF,
4673 .name = "power well 2",
4674 .domains = XELPD_PW_2_POWER_DOMAINS,
4675 .ops = &hsw_power_well_ops,
4676 .id = SKL_DISP_PW_2,
4678 .hsw.regs = &hsw_power_well_regs,
4679 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
4680 .hsw.has_vga = true,
4681 .hsw.has_fuses = true,
4685 .name = "power well A",
4686 .domains = XELPD_PW_A_POWER_DOMAINS,
4687 .ops = &hsw_power_well_ops,
4688 .id = DISP_PW_ID_NONE,
4690 .hsw.regs = &hsw_power_well_regs,
4691 .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
4692 .hsw.irq_pipe_mask = BIT(PIPE_A),
4693 .hsw.has_fuses = true,
4697 .name = "power well B",
4698 .domains = XELPD_PW_B_POWER_DOMAINS,
4699 .ops = &hsw_power_well_ops,
4700 .id = DISP_PW_ID_NONE,
4702 .hsw.regs = &hsw_power_well_regs,
4703 .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
4704 .hsw.irq_pipe_mask = BIT(PIPE_B),
4705 .hsw.has_fuses = true,
4709 .name = "power well C",
4710 .domains = XELPD_PW_C_POWER_DOMAINS,
4711 .ops = &hsw_power_well_ops,
4712 .id = DISP_PW_ID_NONE,
4714 .hsw.regs = &hsw_power_well_regs,
4715 .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
4716 .hsw.irq_pipe_mask = BIT(PIPE_C),
4717 .hsw.has_fuses = true,
4721 .name = "power well D",
4722 .domains = XELPD_PW_D_POWER_DOMAINS,
4723 .ops = &hsw_power_well_ops,
4724 .id = DISP_PW_ID_NONE,
4726 .hsw.regs = &hsw_power_well_regs,
4727 .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
4728 .hsw.irq_pipe_mask = BIT(PIPE_D),
4729 .hsw.has_fuses = true,
4734 .domains = ICL_DDI_IO_A_POWER_DOMAINS,
4735 .ops = &hsw_power_well_ops,
4736 .id = DISP_PW_ID_NONE,
4738 .hsw.regs = &icl_ddi_power_well_regs,
4739 .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
4744 .domains = ICL_DDI_IO_B_POWER_DOMAINS,
4745 .ops = &hsw_power_well_ops,
4746 .id = DISP_PW_ID_NONE,
4748 .hsw.regs = &icl_ddi_power_well_regs,
4749 .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
4754 .domains = ICL_DDI_IO_C_POWER_DOMAINS,
4755 .ops = &hsw_power_well_ops,
4756 .id = DISP_PW_ID_NONE,
4758 .hsw.regs = &icl_ddi_power_well_regs,
4759 .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
4763 .name = "DDI IO D_XELPD",
4764 .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
4765 .ops = &hsw_power_well_ops,
4766 .id = DISP_PW_ID_NONE,
4768 .hsw.regs = &icl_ddi_power_well_regs,
4769 .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
4773 .name = "DDI IO E_XELPD",
4774 .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
4775 .ops = &hsw_power_well_ops,
4776 .id = DISP_PW_ID_NONE,
4778 .hsw.regs = &icl_ddi_power_well_regs,
4779 .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
4783 .name = "DDI IO TC1",
4784 .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
4785 .ops = &hsw_power_well_ops,
4786 .id = DISP_PW_ID_NONE,
4788 .hsw.regs = &icl_ddi_power_well_regs,
4789 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
4793 .name = "DDI IO TC2",
4794 .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
4795 .ops = &hsw_power_well_ops,
4796 .id = DISP_PW_ID_NONE,
4798 .hsw.regs = &icl_ddi_power_well_regs,
4799 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
4803 .name = "DDI IO TC3",
4804 .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
4805 .ops = &hsw_power_well_ops,
4806 .id = DISP_PW_ID_NONE,
4808 .hsw.regs = &icl_ddi_power_well_regs,
4809 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
4813 .name = "DDI IO TC4",
4814 .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
4815 .ops = &hsw_power_well_ops,
4816 .id = DISP_PW_ID_NONE,
4818 .hsw.regs = &icl_ddi_power_well_regs,
4819 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
4824 .domains = ICL_AUX_A_IO_POWER_DOMAINS,
4825 .ops = &icl_aux_power_well_ops,
4826 .id = DISP_PW_ID_NONE,
4828 .hsw.regs = &icl_aux_power_well_regs,
4829 .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
4834 .domains = ICL_AUX_B_IO_POWER_DOMAINS,
4835 .ops = &icl_aux_power_well_ops,
4836 .id = DISP_PW_ID_NONE,
4838 .hsw.regs = &icl_aux_power_well_regs,
4839 .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
4844 .domains = TGL_AUX_C_IO_POWER_DOMAINS,
4845 .ops = &icl_aux_power_well_ops,
4846 .id = DISP_PW_ID_NONE,
4848 .hsw.regs = &icl_aux_power_well_regs,
4849 .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
4853 .name = "AUX D_XELPD",
4854 .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
4855 .ops = &icl_aux_power_well_ops,
4856 .id = DISP_PW_ID_NONE,
4858 .hsw.regs = &icl_aux_power_well_regs,
4859 .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
4863 .name = "AUX E_XELPD",
4864 .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
4865 .ops = &icl_aux_power_well_ops,
4866 .id = DISP_PW_ID_NONE,
4868 .hsw.regs = &icl_aux_power_well_regs,
4869 .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
4873 .name = "AUX USBC1",
4874 .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
4875 .ops = &icl_aux_power_well_ops,
4876 .id = DISP_PW_ID_NONE,
4878 .hsw.regs = &icl_aux_power_well_regs,
4879 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
4883 .name = "AUX USBC2",
4884 .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
4885 .ops = &icl_aux_power_well_ops,
4886 .id = DISP_PW_ID_NONE,
4888 .hsw.regs = &icl_aux_power_well_regs,
4889 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
4893 .name = "AUX USBC3",
4894 .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
4895 .ops = &icl_aux_power_well_ops,
4896 .id = DISP_PW_ID_NONE,
4898 .hsw.regs = &icl_aux_power_well_regs,
4899 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
4903 .name = "AUX USBC4",
4904 .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
4905 .ops = &icl_aux_power_well_ops,
4906 .id = DISP_PW_ID_NONE,
4908 .hsw.regs = &icl_aux_power_well_regs,
4909 .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
4914 .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
4915 .ops = &icl_aux_power_well_ops,
4916 .id = DISP_PW_ID_NONE,
4918 .hsw.regs = &icl_aux_power_well_regs,
4919 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
4920 .hsw.is_tc_tbt = true,
4925 .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
4926 .ops = &icl_aux_power_well_ops,
4927 .id = DISP_PW_ID_NONE,
4929 .hsw.regs = &icl_aux_power_well_regs,
4930 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
4931 .hsw.is_tc_tbt = true,
4936 .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
4937 .ops = &icl_aux_power_well_ops,
4938 .id = DISP_PW_ID_NONE,
4940 .hsw.regs = &icl_aux_power_well_regs,
4941 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
4942 .hsw.is_tc_tbt = true,
4947 .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
4948 .ops = &icl_aux_power_well_ops,
4949 .id = DISP_PW_ID_NONE,
4951 .hsw.regs = &icl_aux_power_well_regs,
4952 .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
4953 .hsw.is_tc_tbt = true,
4959 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
4960 int disable_power_well)
4962 if (disable_power_well >= 0)
4963 return !!disable_power_well;
4968 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
4975 if (!HAS_DISPLAY(dev_priv))
4978 if (IS_DG1(dev_priv))
4980 else if (DISPLAY_VER(dev_priv) >= 12)
4982 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4984 else if (DISPLAY_VER(dev_priv) >= 9)
4990 * DC9 has a separate HW flow from the rest of the DC states,
4991 * not depending on the DMC firmware. It's needed by system
4992 * suspend/resume, so allow it unconditionally.
4994 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
4995 DISPLAY_VER(dev_priv) >= 11 ?
4996 DC_STATE_EN_DC9 : 0;
4998 if (!dev_priv->params.disable_power_well)
5001 if (enable_dc >= 0 && enable_dc <= max_dc) {
5002 requested_dc = enable_dc;
5003 } else if (enable_dc == -1) {
5004 requested_dc = max_dc;
5005 } else if (enable_dc > max_dc && enable_dc <= 4) {
5006 drm_dbg_kms(&dev_priv->drm,
5007 "Adjusting requested max DC state (%d->%d)\n",
5009 requested_dc = max_dc;
5011 drm_err(&dev_priv->drm,
5012 "Unexpected value for enable_dc (%d)\n", enable_dc);
5013 requested_dc = max_dc;
5016 switch (requested_dc) {
5018 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
5021 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
5024 mask |= DC_STATE_EN_UPTO_DC6;
5027 mask |= DC_STATE_EN_UPTO_DC5;
5031 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
5037 __set_power_wells(struct i915_power_domains *power_domains,
5038 const struct i915_power_well_desc *power_well_descs,
5039 int power_well_descs_sz, u64 skip_mask)
5041 struct drm_i915_private *i915 = container_of(power_domains,
5042 struct drm_i915_private,
5044 u64 power_well_ids = 0;
5045 int power_well_count = 0;
5048 for (i = 0; i < power_well_descs_sz; i++)
5049 if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
5052 power_domains->power_well_count = power_well_count;
5053 power_domains->power_wells =
5054 kcalloc(power_well_count,
5055 sizeof(*power_domains->power_wells),
5057 if (!power_domains->power_wells)
5060 for (i = 0; i < power_well_descs_sz; i++) {
5061 enum i915_power_well_id id = power_well_descs[i].id;
5063 if (BIT_ULL(id) & skip_mask)
5066 power_domains->power_wells[plt_idx++].desc =
5067 &power_well_descs[i];
5069 if (id == DISP_PW_ID_NONE)
5072 drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
5073 drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
5074 power_well_ids |= BIT_ULL(id);
5080 #define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
5081 __set_power_wells(power_domains, __power_well_descs, \
5082 ARRAY_SIZE(__power_well_descs), skip_mask)
5084 #define set_power_wells(power_domains, __power_well_descs) \
5085 set_power_wells_mask(power_domains, __power_well_descs, 0)
5088 * intel_power_domains_init - initializes the power domain structures
5089 * @dev_priv: i915 device instance
5091 * Initializes the power domain structures for @dev_priv depending upon the
5092 * supported platform.
5094 int intel_power_domains_init(struct drm_i915_private *dev_priv)
5096 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5099 dev_priv->params.disable_power_well =
5100 sanitize_disable_power_well_option(dev_priv,
5101 dev_priv->params.disable_power_well);
5102 dev_priv->dmc.allowed_dc_mask =
5103 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
5105 dev_priv->dmc.target_dc_state =
5106 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
5108 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
5110 mutex_init(&power_domains->lock);
5112 INIT_DELAYED_WORK(&power_domains->async_put_work,
5113 intel_display_power_put_async_work);
5116 * The enabling order will be from lower to higher indexed wells,
5117 * the disabling order is reversed.
5119 if (!HAS_DISPLAY(dev_priv)) {
5120 power_domains->power_well_count = 0;
5122 } else if (DISPLAY_VER(dev_priv) >= 13) {
5123 err = set_power_wells(power_domains, xelpd_power_wells);
5124 } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
5125 err = set_power_wells_mask(power_domains, tgl_power_wells,
5126 BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
5127 } else if (IS_ROCKETLAKE(dev_priv)) {
5128 err = set_power_wells(power_domains, rkl_power_wells);
5129 } else if (DISPLAY_VER(dev_priv) == 12) {
5130 err = set_power_wells(power_domains, tgl_power_wells);
5131 } else if (DISPLAY_VER(dev_priv) == 11) {
5132 err = set_power_wells(power_domains, icl_power_wells);
5133 } else if (IS_CNL_WITH_PORT_F(dev_priv)) {
5134 err = set_power_wells(power_domains, cnl_power_wells);
5135 } else if (IS_CANNONLAKE(dev_priv)) {
5136 err = set_power_wells_mask(power_domains, cnl_power_wells,
5137 BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
5138 BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
5139 } else if (IS_GEMINILAKE(dev_priv)) {
5140 err = set_power_wells(power_domains, glk_power_wells);
5141 } else if (IS_BROXTON(dev_priv)) {
5142 err = set_power_wells(power_domains, bxt_power_wells);
5143 } else if (DISPLAY_VER(dev_priv) == 9) {
5144 err = set_power_wells(power_domains, skl_power_wells);
5145 } else if (IS_CHERRYVIEW(dev_priv)) {
5146 err = set_power_wells(power_domains, chv_power_wells);
5147 } else if (IS_BROADWELL(dev_priv)) {
5148 err = set_power_wells(power_domains, bdw_power_wells);
5149 } else if (IS_HASWELL(dev_priv)) {
5150 err = set_power_wells(power_domains, hsw_power_wells);
5151 } else if (IS_VALLEYVIEW(dev_priv)) {
5152 err = set_power_wells(power_domains, vlv_power_wells);
5153 } else if (IS_I830(dev_priv)) {
5154 err = set_power_wells(power_domains, i830_power_wells);
5156 err = set_power_wells(power_domains, i9xx_always_on_power_well);
5163 * intel_power_domains_cleanup - clean up power domains resources
5164 * @dev_priv: i915 device instance
5166 * Release any resources acquired by intel_power_domains_init()
5168 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
5170 kfree(dev_priv->power_domains.power_wells);
5173 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
5175 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5176 struct i915_power_well *power_well;
5178 mutex_lock(&power_domains->lock);
5179 for_each_power_well(dev_priv, power_well) {
5180 power_well->desc->ops->sync_hw(dev_priv, power_well);
5181 power_well->hw_enabled =
5182 power_well->desc->ops->is_enabled(dev_priv, power_well);
5184 mutex_unlock(&power_domains->lock);
5187 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
5188 enum dbuf_slice slice, bool enable)
5190 i915_reg_t reg = DBUF_CTL_S(slice);
5193 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
5194 enable ? DBUF_POWER_REQUEST : 0);
5195 intel_de_posting_read(dev_priv, reg);
5198 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
5199 drm_WARN(&dev_priv->drm, enable != state,
5200 "DBuf slice %d power %s timeout!\n",
5201 slice, enabledisable(enable));
5204 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
5207 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5208 u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
5209 enum dbuf_slice slice;
5211 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
5212 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
5213 req_slices, slice_mask);
5215 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
5219 * Might be running this in parallel to gen9_dc_off_power_well_enable
5220 * being called from intel_dp_detect for instance,
5221 * which causes assertion triggered by race condition,
5222 * as gen9_assert_dbuf_enabled might preempt this when registers
5223 * were already updated, while dev_priv was not.
5225 mutex_lock(&power_domains->lock);
5227 for_each_dbuf_slice(dev_priv, slice)
5228 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
5230 dev_priv->dbuf.enabled_slices = req_slices;
5232 mutex_unlock(&power_domains->lock);
5235 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
5237 dev_priv->dbuf.enabled_slices =
5238 intel_enabled_dbuf_slices_mask(dev_priv);
5241 * Just power up at least 1 slice, we will
5242 * figure out later which slices we have and what we need.
5244 gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
5245 dev_priv->dbuf.enabled_slices);
5248 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
5250 gen9_dbuf_slices_update(dev_priv, 0);
5253 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
5255 enum dbuf_slice slice;
5257 if (IS_ALDERLAKE_P(dev_priv))
5260 for_each_dbuf_slice(dev_priv, slice)
5261 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
5262 DBUF_TRACKER_STATE_SERVICE_MASK,
5263 DBUF_TRACKER_STATE_SERVICE(8));
5266 static void icl_mbus_init(struct drm_i915_private *dev_priv)
5268 unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
5271 if (IS_ALDERLAKE_P(dev_priv))
5274 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
5275 MBUS_ABOX_BT_CREDIT_POOL2_MASK |
5276 MBUS_ABOX_B_CREDIT_MASK |
5277 MBUS_ABOX_BW_CREDIT_MASK;
5278 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
5279 MBUS_ABOX_BT_CREDIT_POOL2(16) |
5280 MBUS_ABOX_B_CREDIT(1) |
5281 MBUS_ABOX_BW_CREDIT(1);
5284 * gen12 platforms that use abox1 and abox2 for pixel data reads still
5285 * expect us to program the abox_ctl0 register as well, even though
5286 * we don't have to program other instance-0 registers like BW_BUDDY.
5288 if (DISPLAY_VER(dev_priv) == 12)
5289 abox_regs |= BIT(0);
5291 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
5292 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
5295 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
5297 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
5300 * The LCPLL register should be turned on by the BIOS. For now
5301 * let's just check its state and print errors in case
5302 * something is wrong. Don't even try to turn it on.
5305 if (val & LCPLL_CD_SOURCE_FCLK)
5306 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
5308 if (val & LCPLL_PLL_DISABLE)
5309 drm_err(&dev_priv->drm, "LCPLL is disabled\n");
5311 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
5312 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
5315 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5317 struct drm_device *dev = &dev_priv->drm;
5318 struct intel_crtc *crtc;
5320 for_each_intel_crtc(dev, crtc)
5321 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
5322 pipe_name(crtc->pipe));
5324 I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
5325 "Display power well on\n");
5326 I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
5328 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
5329 "WRPLL1 enabled\n");
5330 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
5331 "WRPLL2 enabled\n");
5332 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON,
5333 "Panel power on\n");
5334 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5335 "CPU PWM1 enabled\n");
5336 if (IS_HASWELL(dev_priv))
5337 I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5338 "CPU PWM2 enabled\n");
5339 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5340 "PCH PWM1 enabled\n");
5341 I915_STATE_WARN(intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5342 "Utility pin enabled\n");
5343 I915_STATE_WARN(intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
5344 "PCH GTC enabled\n");
5347 * In theory we can still leave IRQs enabled, as long as only the HPD
5348 * interrupts remain enabled. We used to check for that, but since it's
5349 * gen-specific and since we only disable LCPLL after we fully disable
5350 * the interrupts, the check below should be enough.
5352 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
5355 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
5357 if (IS_HASWELL(dev_priv))
5358 return intel_de_read(dev_priv, D_COMP_HSW);
5360 return intel_de_read(dev_priv, D_COMP_BDW);
5363 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
5365 if (IS_HASWELL(dev_priv)) {
5366 if (sandybridge_pcode_write(dev_priv,
5367 GEN6_PCODE_WRITE_D_COMP, val))
5368 drm_dbg_kms(&dev_priv->drm,
5369 "Failed to write to D_COMP\n");
5371 intel_de_write(dev_priv, D_COMP_BDW, val);
5372 intel_de_posting_read(dev_priv, D_COMP_BDW);
5377 * This function implements pieces of two sequences from BSpec:
5378 * - Sequence for display software to disable LCPLL
5379 * - Sequence for display software to allow package C8+
5380 * The steps implemented here are just the steps that actually touch the LCPLL
5381 * register. Callers should take care of disabling all the display engine
5382 * functions, doing the mode unset, fixing interrupts, etc.
5384 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5385 bool switch_to_fclk, bool allow_power_down)
5389 assert_can_disable_lcpll(dev_priv);
5391 val = intel_de_read(dev_priv, LCPLL_CTL);
5393 if (switch_to_fclk) {
5394 val |= LCPLL_CD_SOURCE_FCLK;
5395 intel_de_write(dev_priv, LCPLL_CTL, val);
5397 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
5398 LCPLL_CD_SOURCE_FCLK_DONE, 1))
5399 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
5401 val = intel_de_read(dev_priv, LCPLL_CTL);
5404 val |= LCPLL_PLL_DISABLE;
5405 intel_de_write(dev_priv, LCPLL_CTL, val);
5406 intel_de_posting_read(dev_priv, LCPLL_CTL);
5408 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
5409 drm_err(&dev_priv->drm, "LCPLL still locked\n");
5411 val = hsw_read_dcomp(dev_priv);
5412 val |= D_COMP_COMP_DISABLE;
5413 hsw_write_dcomp(dev_priv, val);
5416 if (wait_for((hsw_read_dcomp(dev_priv) &
5417 D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
5418 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
5420 if (allow_power_down) {
5421 val = intel_de_read(dev_priv, LCPLL_CTL);
5422 val |= LCPLL_POWER_DOWN_ALLOW;
5423 intel_de_write(dev_priv, LCPLL_CTL, val);
5424 intel_de_posting_read(dev_priv, LCPLL_CTL);
5429 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
5432 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
5436 val = intel_de_read(dev_priv, LCPLL_CTL);
5438 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
5439 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
5443 * Make sure we're not on PC8 state before disabling PC8, otherwise
5444 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
5446 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
5448 if (val & LCPLL_POWER_DOWN_ALLOW) {
5449 val &= ~LCPLL_POWER_DOWN_ALLOW;
5450 intel_de_write(dev_priv, LCPLL_CTL, val);
5451 intel_de_posting_read(dev_priv, LCPLL_CTL);
5454 val = hsw_read_dcomp(dev_priv);
5455 val |= D_COMP_COMP_FORCE;
5456 val &= ~D_COMP_COMP_DISABLE;
5457 hsw_write_dcomp(dev_priv, val);
5459 val = intel_de_read(dev_priv, LCPLL_CTL);
5460 val &= ~LCPLL_PLL_DISABLE;
5461 intel_de_write(dev_priv, LCPLL_CTL, val);
5463 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
5464 drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
5466 if (val & LCPLL_CD_SOURCE_FCLK) {
5467 val = intel_de_read(dev_priv, LCPLL_CTL);
5468 val &= ~LCPLL_CD_SOURCE_FCLK;
5469 intel_de_write(dev_priv, LCPLL_CTL, val);
5471 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
5472 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
5473 drm_err(&dev_priv->drm,
5474 "Switching back to LCPLL failed\n");
5477 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
5479 intel_update_cdclk(dev_priv);
5480 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
5484 * Package states C8 and deeper are really deep PC states that can only be
5485 * reached when all the devices on the system allow it, so even if the graphics
5486 * device allows PC8+, it doesn't mean the system will actually get to these
5487 * states. Our driver only allows PC8+ when going into runtime PM.
5489 * The requirements for PC8+ are that all the outputs are disabled, the power
5490 * well is disabled and most interrupts are disabled, and these are also
5491 * requirements for runtime PM. When these conditions are met, we manually do
5492 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
5493 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
5496 * When we really reach PC8 or deeper states (not just when we allow it) we lose
5497 * the state of some registers, so when we come back from PC8+ we need to
5498 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
5499 * need to take care of the registers kept by RC6. Notice that this happens even
5500 * if we don't put the device in PCI D3 state (which is what currently happens
5501 * because of the runtime PM support).
5503 * For more, read "Display Sequences for Package C8" on the hardware
5506 static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
5510 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
5512 if (HAS_PCH_LPT_LP(dev_priv)) {
5513 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
5514 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5515 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
5518 lpt_disable_clkout_dp(dev_priv);
5519 hsw_disable_lcpll(dev_priv, true, true);
5522 static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
5526 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
5528 hsw_restore_lcpll(dev_priv);
5529 intel_init_pch_refclk(dev_priv);
5531 if (HAS_PCH_LPT_LP(dev_priv)) {
5532 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
5533 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
5534 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
5538 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
5542 u32 reset_bits, val;
5544 if (IS_IVYBRIDGE(dev_priv)) {
5546 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
5548 reg = HSW_NDE_RSTWRN_OPT;
5549 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
5552 val = intel_de_read(dev_priv, reg);
5559 intel_de_write(dev_priv, reg, val);
5562 static void skl_display_core_init(struct drm_i915_private *dev_priv,
5565 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5566 struct i915_power_well *well;
5568 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
5570 /* enable PCH reset handshake */
5571 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
5573 if (!HAS_DISPLAY(dev_priv))
5576 /* enable PG1 and Misc I/O */
5577 mutex_lock(&power_domains->lock);
5579 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5580 intel_power_well_enable(dev_priv, well);
5582 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
5583 intel_power_well_enable(dev_priv, well);
5585 mutex_unlock(&power_domains->lock);
5587 intel_cdclk_init_hw(dev_priv);
5589 gen9_dbuf_enable(dev_priv);
5591 if (resume && intel_dmc_has_payload(dev_priv))
5592 intel_dmc_load_program(dev_priv);
5595 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
5597 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5598 struct i915_power_well *well;
5600 if (!HAS_DISPLAY(dev_priv))
5603 gen9_disable_dc_states(dev_priv);
5605 gen9_dbuf_disable(dev_priv);
5607 intel_cdclk_uninit_hw(dev_priv);
5609 /* The spec doesn't call for removing the reset handshake flag */
5610 /* disable PG1 and Misc I/O */
5612 mutex_lock(&power_domains->lock);
5615 * BSpec says to keep the MISC IO power well enabled here, only
5616 * remove our request for power well 1.
5617 * Note that even though the driver's request is removed power well 1
5618 * may stay enabled after this due to DMC's own request on it.
5620 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5621 intel_power_well_disable(dev_priv, well);
5623 mutex_unlock(&power_domains->lock);
5625 usleep_range(10, 30); /* 10 us delay per Bspec */
5628 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
5630 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5631 struct i915_power_well *well;
5633 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
5636 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5637 * or else the reset will hang because there is no PCH to respond.
5638 * Move the handshake programming to initialization sequence.
5639 * Previously was left up to BIOS.
5641 intel_pch_reset_handshake(dev_priv, false);
5643 if (!HAS_DISPLAY(dev_priv))
5647 mutex_lock(&power_domains->lock);
5649 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5650 intel_power_well_enable(dev_priv, well);
5652 mutex_unlock(&power_domains->lock);
5654 intel_cdclk_init_hw(dev_priv);
5656 gen9_dbuf_enable(dev_priv);
5658 if (resume && intel_dmc_has_payload(dev_priv))
5659 intel_dmc_load_program(dev_priv);
5662 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
5664 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5665 struct i915_power_well *well;
5667 if (!HAS_DISPLAY(dev_priv))
5670 gen9_disable_dc_states(dev_priv);
5672 gen9_dbuf_disable(dev_priv);
5674 intel_cdclk_uninit_hw(dev_priv);
5676 /* The spec doesn't call for removing the reset handshake flag */
5679 * Disable PW1 (PG1).
5680 * Note that even though the driver's request is removed power well 1
5681 * may stay enabled after this due to DMC's own request on it.
5683 mutex_lock(&power_domains->lock);
5685 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5686 intel_power_well_disable(dev_priv, well);
5688 mutex_unlock(&power_domains->lock);
5690 usleep_range(10, 30); /* 10 us delay per Bspec */
5693 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
5695 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5696 struct i915_power_well *well;
5698 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
5700 /* 1. Enable PCH Reset Handshake */
5701 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
5703 if (!HAS_DISPLAY(dev_priv))
5707 intel_combo_phy_init(dev_priv);
5710 * 4. Enable Power Well 1 (PG1).
5711 * The AUX IO power wells will be enabled on demand.
5713 mutex_lock(&power_domains->lock);
5714 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5715 intel_power_well_enable(dev_priv, well);
5716 mutex_unlock(&power_domains->lock);
5718 /* 5. Enable CD clock */
5719 intel_cdclk_init_hw(dev_priv);
5721 /* 6. Enable DBUF */
5722 gen9_dbuf_enable(dev_priv);
5724 if (resume && intel_dmc_has_payload(dev_priv))
5725 intel_dmc_load_program(dev_priv);
5728 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
5730 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5731 struct i915_power_well *well;
5733 if (!HAS_DISPLAY(dev_priv))
5736 gen9_disable_dc_states(dev_priv);
5738 /* 1. Disable all display engine functions -> aready done */
5740 /* 2. Disable DBUF */
5741 gen9_dbuf_disable(dev_priv);
5743 /* 3. Disable CD clock */
5744 intel_cdclk_uninit_hw(dev_priv);
5747 * 4. Disable Power Well 1 (PG1).
5748 * The AUX IO power wells are toggled on demand, so they are already
5749 * disabled at this point.
5751 mutex_lock(&power_domains->lock);
5752 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5753 intel_power_well_disable(dev_priv, well);
5754 mutex_unlock(&power_domains->lock);
5756 usleep_range(10, 30); /* 10 us delay per Bspec */
5759 intel_combo_phy_uninit(dev_priv);
5762 struct buddy_page_mask {
5768 static const struct buddy_page_mask tgl_buddy_page_masks[] = {
5769 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
5770 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
5771 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
5772 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
5773 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
5774 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
5775 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
5776 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
5780 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
5781 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
5782 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
5783 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
5784 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
5785 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
5786 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
5787 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
5788 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
5792 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
5794 enum intel_dram_type type = dev_priv->dram_info.type;
5795 u8 num_channels = dev_priv->dram_info.num_channels;
5796 const struct buddy_page_mask *table;
5797 unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
5800 if (IS_ALDERLAKE_S(dev_priv) ||
5801 IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
5802 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
5803 /* Wa_1409767108:tgl,dg1,adl-s */
5804 table = wa_1409767108_buddy_page_masks;
5806 table = tgl_buddy_page_masks;
5808 for (config = 0; table[config].page_mask != 0; config++)
5809 if (table[config].num_channels == num_channels &&
5810 table[config].type == type)
5813 if (table[config].page_mask == 0) {
5814 drm_dbg(&dev_priv->drm,
5815 "Unknown memory configuration; disabling address buddy logic.\n");
5816 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
5817 intel_de_write(dev_priv, BW_BUDDY_CTL(i),
5820 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
5821 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
5822 table[config].page_mask);
5824 /* Wa_22010178259:tgl,rkl */
5825 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
5826 BW_BUDDY_TLB_REQ_TIMER_MASK,
5827 BW_BUDDY_TLB_REQ_TIMER(0x8));
5832 static void icl_display_core_init(struct drm_i915_private *dev_priv,
5835 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5836 struct i915_power_well *well;
5839 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
5841 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
5842 if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
5843 INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
5844 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
5845 PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
5847 /* 1. Enable PCH reset handshake. */
5848 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
5850 if (!HAS_DISPLAY(dev_priv))
5853 /* 2. Initialize all combo phys */
5854 intel_combo_phy_init(dev_priv);
5857 * 3. Enable Power Well 1 (PG1).
5858 * The AUX IO power wells will be enabled on demand.
5860 mutex_lock(&power_domains->lock);
5861 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5862 intel_power_well_enable(dev_priv, well);
5863 mutex_unlock(&power_domains->lock);
5865 /* 4. Enable CDCLK. */
5866 intel_cdclk_init_hw(dev_priv);
5868 if (DISPLAY_VER(dev_priv) >= 12)
5869 gen12_dbuf_slices_config(dev_priv);
5871 /* 5. Enable DBUF. */
5872 gen9_dbuf_enable(dev_priv);
5874 /* 6. Setup MBUS. */
5875 icl_mbus_init(dev_priv);
5877 /* 7. Program arbiter BW_BUDDY registers */
5878 if (DISPLAY_VER(dev_priv) >= 12)
5879 tgl_bw_buddy_init(dev_priv);
5881 if (resume && intel_dmc_has_payload(dev_priv))
5882 intel_dmc_load_program(dev_priv);
5884 /* Wa_14011508470 */
5885 if (DISPLAY_VER(dev_priv) == 12) {
5886 val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
5887 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
5888 intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
5891 /* Wa_14011503030:xelpd */
5892 if (DISPLAY_VER(dev_priv) >= 13)
5893 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
5896 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
5898 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5899 struct i915_power_well *well;
5901 if (!HAS_DISPLAY(dev_priv))
5904 gen9_disable_dc_states(dev_priv);
5906 /* 1. Disable all display engine functions -> aready done */
5908 /* 2. Disable DBUF */
5909 gen9_dbuf_disable(dev_priv);
5911 /* 3. Disable CD clock */
5912 intel_cdclk_uninit_hw(dev_priv);
5915 * 4. Disable Power Well 1 (PG1).
5916 * The AUX IO power wells are toggled on demand, so they are already
5917 * disabled at this point.
5919 mutex_lock(&power_domains->lock);
5920 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
5921 intel_power_well_disable(dev_priv, well);
5922 mutex_unlock(&power_domains->lock);
5925 intel_combo_phy_uninit(dev_priv);
5928 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
5930 struct i915_power_well *cmn_bc =
5931 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
5932 struct i915_power_well *cmn_d =
5933 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
5936 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
5937 * workaround never ever read DISPLAY_PHY_CONTROL, and
5938 * instead maintain a shadow copy ourselves. Use the actual
5939 * power well state and lane status to reconstruct the
5940 * expected initial value.
5942 dev_priv->chv_phy_control =
5943 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
5944 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
5945 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
5946 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
5947 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
5950 * If all lanes are disabled we leave the override disabled
5951 * with all power down bits cleared to match the state we
5952 * would use after disabling the port. Otherwise enable the
5953 * override and set the lane powerdown bits accding to the
5954 * current lane status.
5956 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
5957 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
5960 mask = status & DPLL_PORTB_READY_MASK;
5964 dev_priv->chv_phy_control |=
5965 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
5967 dev_priv->chv_phy_control |=
5968 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
5970 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
5974 dev_priv->chv_phy_control |=
5975 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
5977 dev_priv->chv_phy_control |=
5978 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
5980 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
5982 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
5984 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
5987 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
5988 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
5991 mask = status & DPLL_PORTD_READY_MASK;
5996 dev_priv->chv_phy_control |=
5997 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
5999 dev_priv->chv_phy_control |=
6000 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
6002 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
6004 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
6006 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
6009 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
6010 dev_priv->chv_phy_control);
6012 /* Defer application of initial phy_control to enabling the powerwell */
6015 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6017 struct i915_power_well *cmn =
6018 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
6019 struct i915_power_well *disp2d =
6020 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
6022 /* If the display might be already active skip this */
6023 if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
6024 disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
6025 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
6028 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
6030 /* cmnlane needs DPLL registers */
6031 disp2d->desc->ops->enable(dev_priv, disp2d);
6034 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6035 * Need to assert and de-assert PHY SB reset by gating the
6036 * common lane power, then un-gating it.
6037 * Simply ungating isn't enough to reset the PHY enough to get
6038 * ports and lanes running.
6040 cmn->desc->ops->disable(dev_priv, cmn);
6043 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
6047 vlv_punit_get(dev_priv);
6048 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
6049 vlv_punit_put(dev_priv);
6054 static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
6056 drm_WARN(&dev_priv->drm,
6057 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
6058 "VED not power gated\n");
6061 static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
6063 static const struct pci_device_id isp_ids[] = {
6064 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
6065 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
6069 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
6070 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
6071 "ISP not power gated\n");
6074 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
6077 * intel_power_domains_init_hw - initialize hardware power domain state
6078 * @i915: i915 device instance
6079 * @resume: Called from resume code paths or not
6081 * This function initializes the hardware power domain state and enables all
6082 * power wells belonging to the INIT power domain. Power wells in other
6083 * domains (and not in the INIT domain) are referenced or disabled by
6084 * intel_modeset_readout_hw_state(). After that the reference count of each
6085 * power well must match its HW enabled state, see
6086 * intel_power_domains_verify_state().
6088 * It will return with power domains disabled (to be enabled later by
6089 * intel_power_domains_enable()) and must be paired with
6090 * intel_power_domains_driver_remove().
6092 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
6094 struct i915_power_domains *power_domains = &i915->power_domains;
6096 power_domains->initializing = true;
6098 if (DISPLAY_VER(i915) >= 11) {
6099 icl_display_core_init(i915, resume);
6100 } else if (IS_CANNONLAKE(i915)) {
6101 cnl_display_core_init(i915, resume);
6102 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
6103 bxt_display_core_init(i915, resume);
6104 } else if (DISPLAY_VER(i915) == 9) {
6105 skl_display_core_init(i915, resume);
6106 } else if (IS_CHERRYVIEW(i915)) {
6107 mutex_lock(&power_domains->lock);
6108 chv_phy_control_init(i915);
6109 mutex_unlock(&power_domains->lock);
6110 assert_isp_power_gated(i915);
6111 } else if (IS_VALLEYVIEW(i915)) {
6112 mutex_lock(&power_domains->lock);
6113 vlv_cmnlane_wa(i915);
6114 mutex_unlock(&power_domains->lock);
6115 assert_ved_power_gated(i915);
6116 assert_isp_power_gated(i915);
6117 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
6118 hsw_assert_cdclk(i915);
6119 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
6120 } else if (IS_IVYBRIDGE(i915)) {
6121 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
6125 * Keep all power wells enabled for any dependent HW access during
6126 * initialization and to make sure we keep BIOS enabled display HW
6127 * resources powered until display HW readout is complete. We drop
6128 * this reference in intel_power_domains_enable().
6130 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
6131 power_domains->init_wakeref =
6132 intel_display_power_get(i915, POWER_DOMAIN_INIT);
6134 /* Disable power support if the user asked so. */
6135 if (!i915->params.disable_power_well) {
6136 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
6137 i915->power_domains.disable_wakeref = intel_display_power_get(i915,
6140 intel_power_domains_sync_hw(i915);
6142 power_domains->initializing = false;
6146 * intel_power_domains_driver_remove - deinitialize hw power domain state
6147 * @i915: i915 device instance
6149 * De-initializes the display power domain HW state. It also ensures that the
6150 * device stays powered up so that the driver can be reloaded.
6152 * It must be called with power domains already disabled (after a call to
6153 * intel_power_domains_disable()) and must be paired with
6154 * intel_power_domains_init_hw().
6156 void intel_power_domains_driver_remove(struct drm_i915_private *i915)
6158 intel_wakeref_t wakeref __maybe_unused =
6159 fetch_and_zero(&i915->power_domains.init_wakeref);
6161 /* Remove the refcount we took to keep power well support disabled. */
6162 if (!i915->params.disable_power_well)
6163 intel_display_power_put(i915, POWER_DOMAIN_INIT,
6164 fetch_and_zero(&i915->power_domains.disable_wakeref));
6166 intel_display_power_flush_work_sync(i915);
6168 intel_power_domains_verify_state(i915);
6170 /* Keep the power well enabled, but cancel its rpm wakeref. */
6171 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
6175 * intel_power_domains_enable - enable toggling of display power wells
6176 * @i915: i915 device instance
6178 * Enable the ondemand enabling/disabling of the display power wells. Note that
6179 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
6180 * only at specific points of the display modeset sequence, thus they are not
6181 * affected by the intel_power_domains_enable()/disable() calls. The purpose
6182 * of these function is to keep the rest of power wells enabled until the end
6183 * of display HW readout (which will acquire the power references reflecting
6184 * the current HW state).
6186 void intel_power_domains_enable(struct drm_i915_private *i915)
6188 intel_wakeref_t wakeref __maybe_unused =
6189 fetch_and_zero(&i915->power_domains.init_wakeref);
6191 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
6192 intel_power_domains_verify_state(i915);
6196 * intel_power_domains_disable - disable toggling of display power wells
6197 * @i915: i915 device instance
6199 * Disable the ondemand enabling/disabling of the display power wells. See
6200 * intel_power_domains_enable() for which power wells this call controls.
6202 void intel_power_domains_disable(struct drm_i915_private *i915)
6204 struct i915_power_domains *power_domains = &i915->power_domains;
6206 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
6207 power_domains->init_wakeref =
6208 intel_display_power_get(i915, POWER_DOMAIN_INIT);
6210 intel_power_domains_verify_state(i915);
6214 * intel_power_domains_suspend - suspend power domain state
6215 * @i915: i915 device instance
6216 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
6218 * This function prepares the hardware power domain state before entering
6221 * It must be called with power domains already disabled (after a call to
6222 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
6224 void intel_power_domains_suspend(struct drm_i915_private *i915,
6225 enum i915_drm_suspend_mode suspend_mode)
6227 struct i915_power_domains *power_domains = &i915->power_domains;
6228 intel_wakeref_t wakeref __maybe_unused =
6229 fetch_and_zero(&power_domains->init_wakeref);
6231 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
6234 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
6235 * support don't manually deinit the power domains. This also means the
6236 * DMC firmware will stay active, it will power down any HW
6237 * resources as required and also enable deeper system power states
6238 * that would be blocked if the firmware was inactive.
6240 if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
6241 suspend_mode == I915_DRM_SUSPEND_IDLE &&
6242 intel_dmc_has_payload(i915)) {
6243 intel_display_power_flush_work(i915);
6244 intel_power_domains_verify_state(i915);
6249 * Even if power well support was disabled we still want to disable
6250 * power wells if power domains must be deinitialized for suspend.
6252 if (!i915->params.disable_power_well)
6253 intel_display_power_put(i915, POWER_DOMAIN_INIT,
6254 fetch_and_zero(&i915->power_domains.disable_wakeref));
6256 intel_display_power_flush_work(i915);
6257 intel_power_domains_verify_state(i915);
6259 if (DISPLAY_VER(i915) >= 11)
6260 icl_display_core_uninit(i915);
6261 else if (IS_CANNONLAKE(i915))
6262 cnl_display_core_uninit(i915);
6263 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
6264 bxt_display_core_uninit(i915);
6265 else if (DISPLAY_VER(i915) == 9)
6266 skl_display_core_uninit(i915);
6268 power_domains->display_core_suspended = true;
6272 * intel_power_domains_resume - resume power domain state
6273 * @i915: i915 device instance
6275 * This function resume the hardware power domain state during system resume.
6277 * It will return with power domain support disabled (to be enabled later by
6278 * intel_power_domains_enable()) and must be paired with
6279 * intel_power_domains_suspend().
6281 void intel_power_domains_resume(struct drm_i915_private *i915)
6283 struct i915_power_domains *power_domains = &i915->power_domains;
6285 if (power_domains->display_core_suspended) {
6286 intel_power_domains_init_hw(i915, true);
6287 power_domains->display_core_suspended = false;
6289 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
6290 power_domains->init_wakeref =
6291 intel_display_power_get(i915, POWER_DOMAIN_INIT);
6294 intel_power_domains_verify_state(i915);
6297 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
6299 static void intel_power_domains_dump_info(struct drm_i915_private *i915)
6301 struct i915_power_domains *power_domains = &i915->power_domains;
6302 struct i915_power_well *power_well;
6304 for_each_power_well(i915, power_well) {
6305 enum intel_display_power_domain domain;
6307 drm_dbg(&i915->drm, "%-25s %d\n",
6308 power_well->desc->name, power_well->count);
6310 for_each_power_domain(domain, power_well->desc->domains)
6311 drm_dbg(&i915->drm, " %-23s %d\n",
6312 intel_display_power_domain_str(domain),
6313 power_domains->domain_use_count[domain]);
6318 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
6319 * @i915: i915 device instance
6321 * Verify if the reference count of each power well matches its HW enabled
6322 * state and the total refcount of the domains it belongs to. This must be
6323 * called after modeset HW state sanitization, which is responsible for
6324 * acquiring reference counts for any power wells in use and disabling the
6325 * ones left on by BIOS but not required by any active output.
6327 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
6329 struct i915_power_domains *power_domains = &i915->power_domains;
6330 struct i915_power_well *power_well;
6331 bool dump_domain_info;
6333 mutex_lock(&power_domains->lock);
6335 verify_async_put_domains_state(power_domains);
6337 dump_domain_info = false;
6338 for_each_power_well(i915, power_well) {
6339 enum intel_display_power_domain domain;
6343 enabled = power_well->desc->ops->is_enabled(i915, power_well);
6344 if ((power_well->count || power_well->desc->always_on) !=
6347 "power well %s state mismatch (refcount %d/enabled %d)",
6348 power_well->desc->name,
6349 power_well->count, enabled);
6352 for_each_power_domain(domain, power_well->desc->domains)
6353 domains_count += power_domains->domain_use_count[domain];
6355 if (power_well->count != domains_count) {
6357 "power well %s refcount/domain refcount mismatch "
6358 "(refcount %d/domains refcount %d)\n",
6359 power_well->desc->name, power_well->count,
6361 dump_domain_info = true;
6365 if (dump_domain_info) {
6369 intel_power_domains_dump_info(i915);
6374 mutex_unlock(&power_domains->lock);
6379 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
6385 void intel_display_power_suspend_late(struct drm_i915_private *i915)
6387 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
6389 bxt_enable_dc9(i915);
6390 /* Tweaked Wa_14010685332:icp,jsp,mcc */
6391 if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
6392 intel_de_rmw(i915, SOUTH_CHICKEN1,
6393 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
6394 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6395 hsw_enable_pc8(i915);
6399 void intel_display_power_resume_early(struct drm_i915_private *i915)
6401 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
6403 gen9_sanitize_dc_state(i915);
6404 bxt_disable_dc9(i915);
6405 /* Tweaked Wa_14010685332:icp,jsp,mcc */
6406 if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
6407 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
6409 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6410 hsw_disable_pc8(i915);
6414 void intel_display_power_suspend(struct drm_i915_private *i915)
6416 if (DISPLAY_VER(i915) >= 11) {
6417 icl_display_core_uninit(i915);
6418 bxt_enable_dc9(i915);
6419 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
6420 bxt_display_core_uninit(i915);
6421 bxt_enable_dc9(i915);
6422 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6423 hsw_enable_pc8(i915);
6427 void intel_display_power_resume(struct drm_i915_private *i915)
6429 if (DISPLAY_VER(i915) >= 11) {
6430 bxt_disable_dc9(i915);
6431 icl_display_core_init(i915, true);
6432 if (intel_dmc_has_payload(i915)) {
6433 if (i915->dmc.allowed_dc_mask &
6434 DC_STATE_EN_UPTO_DC6)
6435 skl_enable_dc6(i915);
6436 else if (i915->dmc.allowed_dc_mask &
6437 DC_STATE_EN_UPTO_DC5)
6438 gen9_enable_dc5(i915);
6440 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
6441 bxt_disable_dc9(i915);
6442 bxt_display_core_init(i915, true);
6443 if (intel_dmc_has_payload(i915) &&
6444 (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
6445 gen9_enable_dc5(i915);
6446 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6447 hsw_disable_pc8(i915);