drivers/gpu/drm/i915/display/intel_display_debugfs.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <drm/drm_debugfs.h>
   7 #include <drm/drm_fourcc.h>
   8
   9 #include "i915_debugfs.h"
  10 #include "intel_de.h"
  11 #include "intel_display_debugfs.h"
  12 #include "intel_display_power.h"
  13 #include "intel_display_types.h"
  14 #include "intel_dmc.h"
  15 #include "intel_dp.h"
  16 #include "intel_dp_mst.h"
  17 #include "intel_drrs.h"
  18 #include "intel_fbc.h"
  19 #include "intel_hdcp.h"
  20 #include "intel_hdmi.h"
  21 #include "intel_pm.h"
  22 #include "intel_psr.h"
  23 #include "intel_sprite.h"
  24
  25 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  26 {
  27         return to_i915(node->minor->dev);
  28 }
  29
  30 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
  31 {
  32         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  33
  34         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
  35                    dev_priv->fb_tracking.busy_bits);
  36
  37         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
  38                    dev_priv->fb_tracking.flip_bits);
  39
  40         return 0;
  41 }
  42
  43 static int i915_fbc_status(struct seq_file *m, void *unused)
  44 {
  45         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  46         struct intel_fbc *fbc = &dev_priv->fbc;
  47         intel_wakeref_t wakeref;
  48
  49         if (!HAS_FBC(dev_priv))
  50                 return -ENODEV;
  51
  52         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
  53         mutex_lock(&fbc->lock);
  54
  55         if (intel_fbc_is_active(dev_priv))
  56                 seq_puts(m, "FBC enabled\n");
  57         else
  58                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
  59
  60         if (intel_fbc_is_active(dev_priv)) {
  61                 u32 mask;
  62
  63                 if (DISPLAY_VER(dev_priv) >= 8)
  64                         mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
  65                 else if (DISPLAY_VER(dev_priv) >= 7)
  66                         mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
  67                 else if (DISPLAY_VER(dev_priv) >= 5)
  68                         mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
  69                 else if (IS_G4X(dev_priv))
  70                         mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
  71                 else
  72                         mask = intel_de_read(dev_priv, FBC_STATUS) &
  73                                 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
  74
  75                 seq_printf(m, "Compressing: %s\n", yesno(mask));
  76         }
  77
  78         mutex_unlock(&fbc->lock);
  79         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
  80
  81         return 0;
  82 }
  83
  84 static int i915_fbc_false_color_get(void *data, u64 *val)
  85 {
  86         struct drm_i915_private *dev_priv = data;
  87
  88         if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
  89                 return -ENODEV;
  90
  91         *val = dev_priv->fbc.false_color;
  92
  93         return 0;
  94 }
  95
  96 static int i915_fbc_false_color_set(void *data, u64 val)
  97 {
  98         struct drm_i915_private *dev_priv = data;
  99         u32 reg;
 100
 101         if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
 102                 return -ENODEV;
 103
 104         mutex_lock(&dev_priv->fbc.lock);
 105
 106         reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 107         dev_priv->fbc.false_color = val;
 108
 109         intel_de_write(dev_priv, ILK_DPFC_CONTROL,
 110                        val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
 111
 112         mutex_unlock(&dev_priv->fbc.lock);
 113         return 0;
 114 }
 115
 116 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
 117                         i915_fbc_false_color_get, i915_fbc_false_color_set,
 118                         "%llu\n");
 119
 120 static int i915_ips_status(struct seq_file *m, void *unused)
 121 {
 122         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 123         intel_wakeref_t wakeref;
 124
 125         if (!HAS_IPS(dev_priv))
 126                 return -ENODEV;
 127
 128         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 129
 130         seq_printf(m, "Enabled by kernel parameter: %s\n",
 131                    yesno(dev_priv->params.enable_ips));
 132
 133         if (DISPLAY_VER(dev_priv) >= 8) {
 134                 seq_puts(m, "Currently: unknown\n");
 135         } else {
 136                 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
 137                         seq_puts(m, "Currently: enabled\n");
 138                 else
 139                         seq_puts(m, "Currently: disabled\n");
 140         }
 141
 142         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 143
 144         return 0;
 145 }
 146
 147 static int i915_sr_status(struct seq_file *m, void *unused)
 148 {
 149         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 150         intel_wakeref_t wakeref;
 151         bool sr_enabled = false;
 152
 153         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 154
 155         if (DISPLAY_VER(dev_priv) >= 9)
 156                 /* no global SR status; inspect per-plane WM */;
 157         else if (HAS_PCH_SPLIT(dev_priv))
 158                 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
 159         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
 160                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
 161                 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
 162         else if (IS_I915GM(dev_priv))
 163                 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
 164         else if (IS_PINEVIEW(dev_priv))
 165                 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
 166         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 167                 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 168
 169         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 170
 171         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
 172
 173         return 0;
 174 }
 175
 176 static int i915_opregion(struct seq_file *m, void *unused)
 177 {
 178         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
 179
 180         if (opregion->header)
 181                 seq_write(m, opregion->header, OPREGION_SIZE);
 182
 183         return 0;
 184 }
 185
 186 static int i915_vbt(struct seq_file *m, void *unused)
 187 {
 188         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
 189
 190         if (opregion->vbt)
 191                 seq_write(m, opregion->vbt, opregion->vbt_size);
 192
 193         return 0;
 194 }
 195
 196 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
 197 {
 198         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 199         struct drm_device *dev = &dev_priv->drm;
 200         struct intel_framebuffer *fbdev_fb = NULL;
 201         struct drm_framebuffer *drm_fb;
 202
 203 #ifdef CONFIG_DRM_FBDEV_EMULATION
 204         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
 205                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
 206
 207                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
 208                            fbdev_fb->base.width,
 209                            fbdev_fb->base.height,
 210                            fbdev_fb->base.format->depth,
 211                            fbdev_fb->base.format->cpp[0] * 8,
 212                            fbdev_fb->base.modifier,
 213                            drm_framebuffer_read_refcount(&fbdev_fb->base));
 214                 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base));
 215                 seq_putc(m, '\n');
 216         }
 217 #endif
 218
 219         mutex_lock(&dev->mode_config.fb_lock);
 220         drm_for_each_fb(drm_fb, dev) {
 221                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
 222                 if (fb == fbdev_fb)
 223                         continue;
 224
 225                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
 226                            fb->base.width,
 227                            fb->base.height,
 228                            fb->base.format->depth,
 229                            fb->base.format->cpp[0] * 8,
 230                            fb->base.modifier,
 231                            drm_framebuffer_read_refcount(&fb->base));
 232                 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base));
 233                 seq_putc(m, '\n');
 234         }
 235         mutex_unlock(&dev->mode_config.fb_lock);
 236
 237         return 0;
 238 }
 239
 240 static int i915_psr_sink_status_show(struct seq_file *m, void *data)
 241 {
 242         u8 val;
 243         static const char * const sink_status[] = {
 244                 "inactive",
 245                 "transition to active, capture and display",
 246                 "active, display from RFB",
 247                 "active, capture and display on sink device timings",
 248                 "transition to inactive, capture and display, timing re-sync",
 249                 "reserved",
 250                 "reserved",
 251                 "sink internal error",
 252         };
 253         struct drm_connector *connector = m->private;
 254         struct intel_dp *intel_dp =
 255                 intel_attached_dp(to_intel_connector(connector));
 256         int ret;
 257
 258         if (!CAN_PSR(intel_dp)) {
 259                 seq_puts(m, "PSR Unsupported\n");
 260                 return -ENODEV;
 261         }
 262
 263         if (connector->status != connector_status_connected)
 264                 return -ENODEV;
 265
 266         ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
 267
 268         if (ret == 1) {
 269                 const char *str = "unknown";
 270
 271                 val &= DP_PSR_SINK_STATE_MASK;
 272                 if (val < ARRAY_SIZE(sink_status))
 273                         str = sink_status[val];
 274                 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
 275         } else {
 276                 return ret;
 277         }
 278
 279         return 0;
 280 }
 281 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
 282
 283 static void
 284 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 285 {
 286         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 287         const char *status = "unknown";
 288         u32 val, status_val;
 289
 290         if (intel_dp->psr.psr2_enabled) {
 291                 static const char * const live_status[] = {
 292                         "IDLE",
 293                         "CAPTURE",
 294                         "CAPTURE_FS",
 295                         "SLEEP",
 296                         "BUFON_FW",
 297                         "ML_UP",
 298                         "SU_STANDBY",
 299                         "FAST_SLEEP",
 300                         "DEEP_SLEEP",
 301                         "BUF_ON",
 302                         "TG_ON"
 303                 };
 304                 val = intel_de_read(dev_priv,
 305                                     EDP_PSR2_STATUS(intel_dp->psr.transcoder));
 306                 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
 307                 if (status_val < ARRAY_SIZE(live_status))
 308                         status = live_status[status_val];
 309         } else {
 310                 static const char * const live_status[] = {
 311                         "IDLE",
 312                         "SRDONACK",
 313                         "SRDENT",
 314                         "BUFOFF",
 315                         "BUFON",
 316                         "AUXACK",
 317                         "SRDOFFACK",
 318                         "SRDENT_ON",
 319                 };
 320                 val = intel_de_read(dev_priv,
 321                                     EDP_PSR_STATUS(intel_dp->psr.transcoder));
 322                 status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
 323                               EDP_PSR_STATUS_STATE_SHIFT;
 324                 if (status_val < ARRAY_SIZE(live_status))
 325                         status = live_status[status_val];
 326         }
 327
 328         seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
 329 }
 330
 331 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 332 {
 333         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 334         struct intel_psr *psr = &intel_dp->psr;
 335         intel_wakeref_t wakeref;
 336         const char *status;
 337         bool enabled;
 338         u32 val;
 339
 340         seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
 341         if (psr->sink_support)
 342                 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
 343         seq_puts(m, "\n");
 344
 345         if (!psr->sink_support)
 346                 return 0;
 347
 348         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 349         mutex_lock(&psr->lock);
 350
 351         if (psr->enabled)
 352                 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
 353         else
 354                 status = "disabled";
 355         seq_printf(m, "PSR mode: %s\n", status);
 356
 357         if (!psr->enabled) {
 358                 seq_printf(m, "PSR sink not reliable: %s\n",
 359                            yesno(psr->sink_not_reliable));
 360
 361                 goto unlock;
 362         }
 363
 364         if (psr->psr2_enabled) {
 365                 val = intel_de_read(dev_priv,
 366                                     EDP_PSR2_CTL(intel_dp->psr.transcoder));
 367                 enabled = val & EDP_PSR2_ENABLE;
 368         } else {
 369                 val = intel_de_read(dev_priv,
 370                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
 371                 enabled = val & EDP_PSR_ENABLE;
 372         }
 373         seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
 374                    enableddisabled(enabled), val);
 375         psr_source_status(intel_dp, m);
 376         seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
 377                    psr->busy_frontbuffer_bits);
 378
 379         /*
 380          * SKL+ Perf counter is reset to 0 everytime DC state is entered
 381          */
 382         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 383                 val = intel_de_read(dev_priv,
 384                                     EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
 385                 val &= EDP_PSR_PERF_CNT_MASK;
 386                 seq_printf(m, "Performance counter: %u\n", val);
 387         }
 388
 389         if (psr->debug & I915_PSR_DEBUG_IRQ) {
 390                 seq_printf(m, "Last attempted entry at: %lld\n",
 391                            psr->last_entry_attempt);
 392                 seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
 393         }
 394
 395         if (psr->psr2_enabled) {
 396                 u32 su_frames_val[3];
 397                 int frame;
 398
 399                 /*
 400                  * Reading all 3 registers before hand to minimize crossing a
 401                  * frame boundary between register reads
 402                  */
 403                 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
 404                         val = intel_de_read(dev_priv,
 405                                             PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
 406                         su_frames_val[frame / 3] = val;
 407                 }
 408
 409                 seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
 410
 411                 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
 412                         u32 su_blocks;
 413
 414                         su_blocks = su_frames_val[frame / 3] &
 415                                     PSR2_SU_STATUS_MASK(frame);
 416                         su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
 417                         seq_printf(m, "%d\t%d\n", frame, su_blocks);
 418                 }
 419
 420                 seq_printf(m, "PSR2 selective fetch: %s\n",
 421                            enableddisabled(psr->psr2_sel_fetch_enabled));
 422         }
 423
 424 unlock:
 425         mutex_unlock(&psr->lock);
 426         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 427
 428         return 0;
 429 }
 430
 431 static int i915_edp_psr_status(struct seq_file *m, void *data)
 432 {
 433         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 434         struct intel_dp *intel_dp = NULL;
 435         struct intel_encoder *encoder;
 436
 437         if (!HAS_PSR(dev_priv))
 438                 return -ENODEV;
 439
 440         /* Find the first EDP which supports PSR */
 441         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 442                 intel_dp = enc_to_intel_dp(encoder);
 443                 break;
 444         }
 445
 446         if (!intel_dp)
 447                 return -ENODEV;
 448
 449         return intel_psr_status(m, intel_dp);
 450 }
 451
 452 static int
 453 i915_edp_psr_debug_set(void *data, u64 val)
 454 {
 455         struct drm_i915_private *dev_priv = data;
 456         struct intel_encoder *encoder;
 457         intel_wakeref_t wakeref;
 458         int ret = -ENODEV;
 459
 460         if (!HAS_PSR(dev_priv))
 461                 return ret;
 462
 463         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 464                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 465
 466                 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
 467
 468                 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 469
 470                 // TODO: split to each transcoder's PSR debug state
 471                 ret = intel_psr_debug_set(intel_dp, val);
 472
 473                 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 474         }
 475
 476         return ret;
 477 }
 478
 479 static int
 480 i915_edp_psr_debug_get(void *data, u64 *val)
 481 {
 482         struct drm_i915_private *dev_priv = data;
 483         struct intel_encoder *encoder;
 484
 485         if (!HAS_PSR(dev_priv))
 486                 return -ENODEV;
 487
 488         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 489                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 490
 491                 // TODO: split to each transcoder's PSR debug state
 492                 *val = READ_ONCE(intel_dp->psr.debug);
 493                 return 0;
 494         }
 495
 496         return -ENODEV;
 497 }
 498
 499 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
 500                         i915_edp_psr_debug_get, i915_edp_psr_debug_set,
 501                         "%llu\n");
 502
 503 static int i915_power_domain_info(struct seq_file *m, void *unused)
 504 {
 505         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 506         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 507         int i;
 508
 509         mutex_lock(&power_domains->lock);
 510
 511         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
 512         for (i = 0; i < power_domains->power_well_count; i++) {
 513                 struct i915_power_well *power_well;
 514                 enum intel_display_power_domain power_domain;
 515
 516                 power_well = &power_domains->power_wells[i];
 517                 seq_printf(m, "%-25s %d\n", power_well->desc->name,
 518                            power_well->count);
 519
 520                 for_each_power_domain(power_domain, power_well->desc->domains)
 521                         seq_printf(m, "  %-23s %d\n",
 522                                  intel_display_power_domain_str(power_domain),
 523                                  power_domains->domain_use_count[power_domain]);
 524         }
 525
 526         mutex_unlock(&power_domains->lock);
 527
 528         return 0;
 529 }
 530
 531 static int i915_dmc_info(struct seq_file *m, void *unused)
 532 {
 533         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 534         intel_wakeref_t wakeref;
 535         struct intel_dmc *dmc;
 536         i915_reg_t dc5_reg, dc6_reg = {};
 537
 538         if (!HAS_DMC(dev_priv))
 539                 return -ENODEV;
 540
 541         dmc = &dev_priv->dmc;
 542
 543         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 544
 545         seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
 546         seq_printf(m, "path: %s\n", dmc->fw_path);
 547         seq_printf(m, "Pipe A fw support: %s\n",
 548                    yesno(GRAPHICS_VER(dev_priv) >= 12));
 549         seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
 550         seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv)));
 551         seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
 552
 553         if (!intel_dmc_has_payload(dev_priv))
 554                 goto out;
 555
 556         seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
 557                    DMC_VERSION_MINOR(dmc->version));
 558
 559         if (DISPLAY_VER(dev_priv) >= 12) {
 560                 if (IS_DGFX(dev_priv)) {
 561                         dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
 562                 } else {
 563                         dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
 564                         dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
 565                 }
 566
 567                 /*
 568                  * NOTE: DMC_DEBUG3 is a general purpose reg.
 569                  * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
 570                  * reg for DC3CO debugging and validation,
 571                  * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
 572                  */
 573                 seq_printf(m, "DC3CO count: %d\n",
 574                            intel_de_read(dev_priv, DMC_DEBUG3));
 575         } else {
 576                 dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
 577                                                  SKL_DMC_DC3_DC5_COUNT;
 578                 if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
 579                         dc6_reg = SKL_DMC_DC5_DC6_COUNT;
 580         }
 581
 582         seq_printf(m, "DC3 -> DC5 count: %d\n",
 583                    intel_de_read(dev_priv, dc5_reg));
 584         if (dc6_reg.reg)
 585                 seq_printf(m, "DC5 -> DC6 count: %d\n",
 586                            intel_de_read(dev_priv, dc6_reg));
 587
 588 out:
 589         seq_printf(m, "program base: 0x%08x\n",
 590                    intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
 591         seq_printf(m, "ssp base: 0x%08x\n",
 592                    intel_de_read(dev_priv, DMC_SSP_BASE));
 593         seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
 594
 595         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 596
 597         return 0;
 598 }
 599
 600 static void intel_seq_print_mode(struct seq_file *m, int tabs,
 601                                  const struct drm_display_mode *mode)
 602 {
 603         int i;
 604
 605         for (i = 0; i < tabs; i++)
 606                 seq_putc(m, '\t');
 607
 608         seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
 609 }
 610
 611 static void intel_encoder_info(struct seq_file *m,
 612                                struct intel_crtc *crtc,
 613                                struct intel_encoder *encoder)
 614 {
 615         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 616         struct drm_connector_list_iter conn_iter;
 617         struct drm_connector *connector;
 618
 619         seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
 620                    encoder->base.base.id, encoder->base.name);
 621
 622         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
 623         drm_for_each_connector_iter(connector, &conn_iter) {
 624                 const struct drm_connector_state *conn_state =
 625                         connector->state;
 626
 627                 if (conn_state->best_encoder != &encoder->base)
 628                         continue;
 629
 630                 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n",
 631                            connector->base.id, connector->name);
 632         }
 633         drm_connector_list_iter_end(&conn_iter);
 634 }
 635
 636 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
 637 {
 638         const struct drm_display_mode *mode = panel->fixed_mode;
 639
 640         seq_printf(m, "\tfixed mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
 641 }
 642
 643 static void intel_hdcp_info(struct seq_file *m,
 644                             struct intel_connector *intel_connector)
 645 {
 646         bool hdcp_cap, hdcp2_cap;
 647
 648         if (!intel_connector->hdcp.shim) {
 649                 seq_puts(m, "No Connector Support");
 650                 goto out;
 651         }
 652
 653         hdcp_cap = intel_hdcp_capable(intel_connector);
 654         hdcp2_cap = intel_hdcp2_capable(intel_connector);
 655
 656         if (hdcp_cap)
 657                 seq_puts(m, "HDCP1.4 ");
 658         if (hdcp2_cap)
 659                 seq_puts(m, "HDCP2.2 ");
 660
 661         if (!hdcp_cap && !hdcp2_cap)
 662                 seq_puts(m, "None");
 663
 664 out:
 665         seq_puts(m, "\n");
 666 }
 667
 668 static void intel_dp_info(struct seq_file *m,
 669                           struct intel_connector *intel_connector)
 670 {
 671         struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
 672         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
 673         const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr;
 674
 675         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
 676         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
 677         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 678                 intel_panel_info(m, &intel_connector->panel);
 679
 680         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
 681                                 edid ? edid->data : NULL, &intel_dp->aux);
 682 }
 683
 684 static void intel_dp_mst_info(struct seq_file *m,
 685                               struct intel_connector *intel_connector)
 686 {
 687         bool has_audio = intel_connector->port->has_audio;
 688
 689         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
 690 }
 691
 692 static void intel_hdmi_info(struct seq_file *m,
 693                             struct intel_connector *intel_connector)
 694 {
 695         struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
 696         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder);
 697
 698         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
 699 }
 700
 701 static void intel_lvds_info(struct seq_file *m,
 702                             struct intel_connector *intel_connector)
 703 {
 704         intel_panel_info(m, &intel_connector->panel);
 705 }
 706
 707 static void intel_connector_info(struct seq_file *m,
 708                                  struct drm_connector *connector)
 709 {
 710         struct intel_connector *intel_connector = to_intel_connector(connector);
 711         const struct drm_connector_state *conn_state = connector->state;
 712         struct intel_encoder *encoder =
 713                 to_intel_encoder(conn_state->best_encoder);
 714         const struct drm_display_mode *mode;
 715
 716         seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n",
 717                    connector->base.id, connector->name,
 718                    drm_get_connector_status_name(connector->status));
 719
 720         if (connector->status == connector_status_disconnected)
 721                 return;
 722
 723         seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
 724                    connector->display_info.width_mm,
 725                    connector->display_info.height_mm);
 726         seq_printf(m, "\tsubpixel order: %s\n",
 727                    drm_get_subpixel_order_name(connector->display_info.subpixel_order));
 728         seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev);
 729
 730         if (!encoder)
 731                 return;
 732
 733         switch (connector->connector_type) {
 734         case DRM_MODE_CONNECTOR_DisplayPort:
 735         case DRM_MODE_CONNECTOR_eDP:
 736                 if (encoder->type == INTEL_OUTPUT_DP_MST)
 737                         intel_dp_mst_info(m, intel_connector);
 738                 else
 739                         intel_dp_info(m, intel_connector);
 740                 break;
 741         case DRM_MODE_CONNECTOR_LVDS:
 742                 if (encoder->type == INTEL_OUTPUT_LVDS)
 743                         intel_lvds_info(m, intel_connector);
 744                 break;
 745         case DRM_MODE_CONNECTOR_HDMIA:
 746                 if (encoder->type == INTEL_OUTPUT_HDMI ||
 747                     encoder->type == INTEL_OUTPUT_DDI)
 748                         intel_hdmi_info(m, intel_connector);
 749                 break;
 750         default:
 751                 break;
 752         }
 753
 754         seq_puts(m, "\tHDCP version: ");
 755         intel_hdcp_info(m, intel_connector);
 756
 757         seq_printf(m, "\tmodes:\n");
 758         list_for_each_entry(mode, &connector->modes, head)
 759                 intel_seq_print_mode(m, 2, mode);
 760 }
 761
 762 static const char *plane_type(enum drm_plane_type type)
 763 {
 764         switch (type) {
 765         case DRM_PLANE_TYPE_OVERLAY:
 766                 return "OVL";
 767         case DRM_PLANE_TYPE_PRIMARY:
 768                 return "PRI";
 769         case DRM_PLANE_TYPE_CURSOR:
 770                 return "CUR";
 771         /*
 772          * Deliberately omitting default: to generate compiler warnings
 773          * when a new drm_plane_type gets added.
 774          */
 775         }
 776
 777         return "unknown";
 778 }
 779
 780 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
 781 {
 782         /*
 783          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
 784          * will print them all to visualize if the values are misused
 785          */
 786         snprintf(buf, bufsize,
 787                  "%s%s%s%s%s%s(0x%08x)",
 788                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
 789                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
 790                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
 791                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
 792                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
 793                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
 794                  rotation);
 795 }
 796
 797 static const char *plane_visibility(const struct intel_plane_state *plane_state)
 798 {
 799         if (plane_state->uapi.visible)
 800                 return "visible";
 801
 802         if (plane_state->planar_slave)
 803                 return "planar-slave";
 804
 805         return "hidden";
 806 }
 807
 808 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
 809 {
 810         const struct intel_plane_state *plane_state =
 811                 to_intel_plane_state(plane->base.state);
 812         const struct drm_framebuffer *fb = plane_state->uapi.fb;
 813         struct drm_rect src, dst;
 814         char rot_str[48];
 815
 816         src = drm_plane_state_src(&plane_state->uapi);
 817         dst = drm_plane_state_dest(&plane_state->uapi);
 818
 819         plane_rotation(rot_str, sizeof(rot_str),
 820                        plane_state->uapi.rotation);
 821
 822         seq_puts(m, "\t\tuapi: [FB:");
 823         if (fb)
 824                 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id,
 825                            &fb->format->format, fb->modifier, fb->width,
 826                            fb->height);
 827         else
 828                 seq_puts(m, "0] n/a,0x0,0x0,");
 829         seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT
 830                    ", rotation=%s\n", plane_visibility(plane_state),
 831                    DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str);
 832
 833         if (plane_state->planar_linked_plane)
 834                 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
 835                            plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
 836                            plane_state->planar_slave ? "slave" : "master");
 837 }
 838
 839 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
 840 {
 841         const struct intel_plane_state *plane_state =
 842                 to_intel_plane_state(plane->base.state);
 843         const struct drm_framebuffer *fb = plane_state->hw.fb;
 844         char rot_str[48];
 845
 846         if (!fb)
 847                 return;
 848
 849         plane_rotation(rot_str, sizeof(rot_str),
 850                        plane_state->hw.rotation);
 851
 852         seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src="
 853                    DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
 854                    fb->base.id, &fb->format->format,
 855                    fb->modifier, fb->width, fb->height,
 856                    yesno(plane_state->uapi.visible),
 857                    DRM_RECT_FP_ARG(&plane_state->uapi.src),
 858                    DRM_RECT_ARG(&plane_state->uapi.dst),
 859                    rot_str);
 860 }
 861
 862 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
 863 {
 864         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 865         struct intel_plane *plane;
 866
 867         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 868                 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
 869                            plane->base.base.id, plane->base.name,
 870                            plane_type(plane->base.type));
 871                 intel_plane_uapi_info(m, plane);
 872                 intel_plane_hw_info(m, plane);
 873         }
 874 }
 875
 876 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
 877 {
 878         const struct intel_crtc_state *crtc_state =
 879                 to_intel_crtc_state(crtc->base.state);
 880         int num_scalers = crtc->num_scalers;
 881         int i;
 882
 883         /* Not all platformas have a scaler */
 884         if (num_scalers) {
 885                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
 886                            num_scalers,
 887                            crtc_state->scaler_state.scaler_users,
 888                            crtc_state->scaler_state.scaler_id);
 889
 890                 for (i = 0; i < num_scalers; i++) {
 891                         const struct intel_scaler *sc =
 892                                 &crtc_state->scaler_state.scalers[i];
 893
 894                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
 895                                    i, yesno(sc->in_use), sc->mode);
 896                 }
 897                 seq_puts(m, "\n");
 898         } else {
 899                 seq_puts(m, "\tNo scalers available on this platform\n");
 900         }
 901 }
 902
 903 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
 904 static void crtc_updates_info(struct seq_file *m,
 905                               struct intel_crtc *crtc,
 906                               const char *hdr)
 907 {
 908         u64 count;
 909         int row;
 910
 911         count = 0;
 912         for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++)
 913                 count += crtc->debug.vbl.times[row];
 914         seq_printf(m, "%sUpdates: %llu\n", hdr, count);
 915         if (!count)
 916                 return;
 917
 918         for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) {
 919                 char columns[80] = "       |";
 920                 unsigned int x;
 921
 922                 if (row & 1) {
 923                         const char *units;
 924
 925                         if (row > 10) {
 926                                 x = 1000000;
 927                                 units = "ms";
 928                         } else {
 929                                 x = 1000;
 930                                 units = "us";
 931                         }
 932
 933                         snprintf(columns, sizeof(columns), "%4ld%s |",
 934                                  DIV_ROUND_CLOSEST(BIT(row + 9), x), units);
 935                 }
 936
 937                 if (crtc->debug.vbl.times[row]) {
 938                         x = ilog2(crtc->debug.vbl.times[row]);
 939                         memset(columns + 8, '*', x);
 940                         columns[8 + x] = '\0';
 941                 }
 942
 943                 seq_printf(m, "%s%s\n", hdr, columns);
 944         }
 945
 946         seq_printf(m, "%sMin update: %lluns\n",
 947                    hdr, crtc->debug.vbl.min);
 948         seq_printf(m, "%sMax update: %lluns\n",
 949                    hdr, crtc->debug.vbl.max);
 950         seq_printf(m, "%sAverage update: %lluns\n",
 951                    hdr, div64_u64(crtc->debug.vbl.sum,  count));
 952         seq_printf(m, "%sOverruns > %uus: %u\n",
 953                    hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
 954 }
 955
 956 static int crtc_updates_show(struct seq_file *m, void *data)
 957 {
 958         crtc_updates_info(m, m->private, "");
 959         return 0;
 960 }
 961
 962 static int crtc_updates_open(struct inode *inode, struct file *file)
 963 {
 964         return single_open(file, crtc_updates_show, inode->i_private);
 965 }
 966
 967 static ssize_t crtc_updates_write(struct file *file,
 968                                   const char __user *ubuf,
 969                                   size_t len, loff_t *offp)
 970 {
 971         struct seq_file *m = file->private_data;
 972         struct intel_crtc *crtc = m->private;
 973
 974         /* May race with an update. Meh. */
 975         memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl));
 976
 977         return len;
 978 }
 979
 980 static const struct file_operations crtc_updates_fops = {
 981         .owner = THIS_MODULE,
 982         .open = crtc_updates_open,
 983         .read = seq_read,
 984         .llseek = seq_lseek,
 985         .release = single_release,
 986         .write = crtc_updates_write
 987 };
 988
 989 static void crtc_updates_add(struct drm_crtc *crtc)
 990 {
 991         debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry,
 992                             to_intel_crtc(crtc), &crtc_updates_fops);
 993 }
 994
 995 #else
 996 static void crtc_updates_info(struct seq_file *m,
 997                               struct intel_crtc *crtc,
 998                               const char *hdr)
 999 {
1000 }
1001
1002 static void crtc_updates_add(struct drm_crtc *crtc)
1003 {
1004 }
1005 #endif
1006
1007 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
1008 {
1009         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1010         const struct intel_crtc_state *crtc_state =
1011                 to_intel_crtc_state(crtc->base.state);
1012         struct intel_encoder *encoder;
1013
1014         seq_printf(m, "[CRTC:%d:%s]:\n",
1015                    crtc->base.base.id, crtc->base.name);
1016
1017         seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n",
1018                    yesno(crtc_state->uapi.enable),
1019                    yesno(crtc_state->uapi.active),
1020                    DRM_MODE_ARG(&crtc_state->uapi.mode));
1021
1022         if (crtc_state->hw.enable) {
1023                 seq_printf(m, "\thw: active=%s, adjusted_mode=" DRM_MODE_FMT "\n",
1024                            yesno(crtc_state->hw.active),
1025                            DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
1026
1027                 seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n",
1028                            crtc_state->pipe_src_w, crtc_state->pipe_src_h,
1029                            yesno(crtc_state->dither), crtc_state->pipe_bpp);
1030
1031                 intel_scaler_info(m, crtc);
1032         }
1033
1034         if (crtc_state->bigjoiner)
1035                 seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
1036                            crtc_state->bigjoiner_linked_crtc->base.base.id,
1037                            crtc_state->bigjoiner_linked_crtc->base.name,
1038                            crtc_state->bigjoiner_slave ? "slave" : "master");
1039
1040         for_each_intel_encoder_mask(&dev_priv->drm, encoder,
1041                                     crtc_state->uapi.encoder_mask)
1042                 intel_encoder_info(m, crtc, encoder);
1043
1044         intel_plane_info(m, crtc);
1045
1046         seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n",
1047                    yesno(!crtc->cpu_fifo_underrun_disabled),
1048                    yesno(!crtc->pch_fifo_underrun_disabled));
1049
1050         crtc_updates_info(m, crtc, "\t");
1051 }
1052
1053 static int i915_display_info(struct seq_file *m, void *unused)
1054 {
1055         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1056         struct drm_device *dev = &dev_priv->drm;
1057         struct intel_crtc *crtc;
1058         struct drm_connector *connector;
1059         struct drm_connector_list_iter conn_iter;
1060         intel_wakeref_t wakeref;
1061
1062         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1063
1064         drm_modeset_lock_all(dev);
1065
1066         seq_printf(m, "CRTC info\n");
1067         seq_printf(m, "---------\n");
1068         for_each_intel_crtc(dev, crtc)
1069                 intel_crtc_info(m, crtc);
1070
1071         seq_printf(m, "\n");
1072         seq_printf(m, "Connector info\n");
1073         seq_printf(m, "--------------\n");
1074         drm_connector_list_iter_begin(dev, &conn_iter);
1075         drm_for_each_connector_iter(connector, &conn_iter)
1076                 intel_connector_info(m, connector);
1077         drm_connector_list_iter_end(&conn_iter);
1078
1079         drm_modeset_unlock_all(dev);
1080
1081         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1082
1083         return 0;
1084 }
1085
1086 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
1087 {
1088         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1089         struct drm_device *dev = &dev_priv->drm;
1090         int i;
1091
1092         drm_modeset_lock_all(dev);
1093
1094         seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
1095                    dev_priv->dpll.ref_clks.nssc,
1096                    dev_priv->dpll.ref_clks.ssc);
1097
1098         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
1099                 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
1100
1101                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
1102                            pll->info->id);
1103                 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
1104                            pll->state.pipe_mask, pll->active_mask, yesno(pll->on));
1105                 seq_printf(m, " tracked hardware state:\n");
1106                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
1107                 seq_printf(m, " dpll_md: 0x%08x\n",
1108                            pll->state.hw_state.dpll_md);
1109                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
1110                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
1111                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
1112                 seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
1113                 seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
1114                 seq_printf(m, " mg_refclkin_ctl:        0x%08x\n",
1115                            pll->state.hw_state.mg_refclkin_ctl);
1116                 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
1117                            pll->state.hw_state.mg_clktop2_coreclkctl1);
1118                 seq_printf(m, " mg_clktop2_hsclkctl:    0x%08x\n",
1119                            pll->state.hw_state.mg_clktop2_hsclkctl);
1120                 seq_printf(m, " mg_pll_div0:  0x%08x\n",
1121                            pll->state.hw_state.mg_pll_div0);
1122                 seq_printf(m, " mg_pll_div1:  0x%08x\n",
1123                            pll->state.hw_state.mg_pll_div1);
1124                 seq_printf(m, " mg_pll_lf:    0x%08x\n",
1125                            pll->state.hw_state.mg_pll_lf);
1126                 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
1127                            pll->state.hw_state.mg_pll_frac_lock);
1128                 seq_printf(m, " mg_pll_ssc:   0x%08x\n",
1129                            pll->state.hw_state.mg_pll_ssc);
1130                 seq_printf(m, " mg_pll_bias:  0x%08x\n",
1131                            pll->state.hw_state.mg_pll_bias);
1132                 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
1133                            pll->state.hw_state.mg_pll_tdc_coldst_bias);
1134         }
1135         drm_modeset_unlock_all(dev);
1136
1137         return 0;
1138 }
1139
1140 static int i915_ipc_status_show(struct seq_file *m, void *data)
1141 {
1142         struct drm_i915_private *dev_priv = m->private;
1143
1144         seq_printf(m, "Isochronous Priority Control: %s\n",
1145                         yesno(dev_priv->ipc_enabled));
1146         return 0;
1147 }
1148
1149 static int i915_ipc_status_open(struct inode *inode, struct file *file)
1150 {
1151         struct drm_i915_private *dev_priv = inode->i_private;
1152
1153         if (!HAS_IPC(dev_priv))
1154                 return -ENODEV;
1155
1156         return single_open(file, i915_ipc_status_show, dev_priv);
1157 }
1158
1159 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
1160                                      size_t len, loff_t *offp)
1161 {
1162         struct seq_file *m = file->private_data;
1163         struct drm_i915_private *dev_priv = m->private;
1164         intel_wakeref_t wakeref;
1165         bool enable;
1166         int ret;
1167
1168         ret = kstrtobool_from_user(ubuf, len, &enable);
1169         if (ret < 0)
1170                 return ret;
1171
1172         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
1173                 if (!dev_priv->ipc_enabled && enable)
1174                         drm_info(&dev_priv->drm,
1175                                  "Enabling IPC: WM will be proper only after next commit\n");
1176                 dev_priv->ipc_enabled = enable;
1177                 intel_enable_ipc(dev_priv);
1178         }
1179
1180         return len;
1181 }
1182
1183 static const struct file_operations i915_ipc_status_fops = {
1184         .owner = THIS_MODULE,
1185         .open = i915_ipc_status_open,
1186         .read = seq_read,
1187         .llseek = seq_lseek,
1188         .release = single_release,
1189         .write = i915_ipc_status_write
1190 };
1191
1192 static int i915_ddb_info(struct seq_file *m, void *unused)
1193 {
1194         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1195         struct drm_device *dev = &dev_priv->drm;
1196         struct skl_ddb_entry *entry;
1197         struct intel_crtc *crtc;
1198
1199         if (DISPLAY_VER(dev_priv) < 9)
1200                 return -ENODEV;
1201
1202         drm_modeset_lock_all(dev);
1203
1204         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
1205
1206         for_each_intel_crtc(&dev_priv->drm, crtc) {
1207                 struct intel_crtc_state *crtc_state =
1208                         to_intel_crtc_state(crtc->base.state);
1209                 enum pipe pipe = crtc->pipe;
1210                 enum plane_id plane_id;
1211
1212                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
1213
1214                 for_each_plane_id_on_crtc(crtc, plane_id) {
1215                         entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
1216                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
1217                                    entry->start, entry->end,
1218                                    skl_ddb_entry_size(entry));
1219                 }
1220
1221                 entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
1222                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
1223                            entry->end, skl_ddb_entry_size(entry));
1224         }
1225
1226         drm_modeset_unlock_all(dev);
1227
1228         return 0;
1229 }
1230
1231 static void drrs_status_per_crtc(struct seq_file *m,
1232                                  struct drm_device *dev,
1233                                  struct intel_crtc *crtc)
1234 {
1235         struct drm_i915_private *dev_priv = to_i915(dev);
1236         struct i915_drrs *drrs = &dev_priv->drrs;
1237         int vrefresh = 0;
1238         struct drm_connector *connector;
1239         struct drm_connector_list_iter conn_iter;
1240
1241         drm_connector_list_iter_begin(dev, &conn_iter);
1242         drm_for_each_connector_iter(connector, &conn_iter) {
1243                 bool supported = false;
1244
1245                 if (connector->state->crtc != &crtc->base)
1246                         continue;
1247
1248                 seq_printf(m, "%s:\n", connector->name);
1249
1250                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
1251                     drrs->type == SEAMLESS_DRRS_SUPPORT)
1252                         supported = true;
1253
1254                 seq_printf(m, "\tDRRS Supported: %s\n", yesno(supported));
1255         }
1256         drm_connector_list_iter_end(&conn_iter);
1257
1258         seq_puts(m, "\n");
1259
1260         if (to_intel_crtc_state(crtc->base.state)->has_drrs) {
1261                 struct intel_panel *panel;
1262
1263                 mutex_lock(&drrs->mutex);
1264                 /* DRRS Supported */
1265                 seq_puts(m, "\tDRRS Enabled: Yes\n");
1266
1267                 /* disable_drrs() will make drrs->dp NULL */
1268                 if (!drrs->dp) {
1269                         seq_puts(m, "Idleness DRRS: Disabled\n");
1270                         mutex_unlock(&drrs->mutex);
1271                         return;
1272                 }
1273
1274                 panel = &drrs->dp->attached_connector->panel;
1275                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
1276                                         drrs->busy_frontbuffer_bits);
1277
1278                 seq_puts(m, "\n\t\t");
1279                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
1280                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
1281                         vrefresh = drm_mode_vrefresh(panel->fixed_mode);
1282                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
1283                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
1284                         vrefresh = drm_mode_vrefresh(panel->downclock_mode);
1285                 } else {
1286                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
1287                                                 drrs->refresh_rate_type);
1288                         mutex_unlock(&drrs->mutex);
1289                         return;
1290                 }
1291                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
1292
1293                 seq_puts(m, "\n\t\t");
1294                 mutex_unlock(&drrs->mutex);
1295         } else {
1296                 /* DRRS not supported. Print the VBT parameter*/
1297                 seq_puts(m, "\tDRRS Enabled : No");
1298         }
1299         seq_puts(m, "\n");
1300 }
1301
1302 static int i915_drrs_status(struct seq_file *m, void *unused)
1303 {
1304         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1305         struct drm_device *dev = &dev_priv->drm;
1306         struct intel_crtc *crtc;
1307         int active_crtc_cnt = 0;
1308
1309         drm_modeset_lock_all(dev);
1310         for_each_intel_crtc(dev, crtc) {
1311                 if (crtc->base.state->active) {
1312                         active_crtc_cnt++;
1313                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
1314
1315                         drrs_status_per_crtc(m, dev, crtc);
1316                 }
1317         }
1318         drm_modeset_unlock_all(dev);
1319
1320         if (!active_crtc_cnt)
1321                 seq_puts(m, "No active crtc found\n");
1322
1323         return 0;
1324 }
1325
1326 static bool
1327 intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
1328                               enum i915_power_well_id power_well_id)
1329 {
1330         intel_wakeref_t wakeref;
1331         bool is_enabled;
1332
1333         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1334         is_enabled = intel_display_power_well_is_enabled(i915,
1335                                                          power_well_id);
1336         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1337
1338         return is_enabled;
1339 }
1340
1341 static int i915_lpsp_status(struct seq_file *m, void *unused)
1342 {
1343         struct drm_i915_private *i915 = node_to_i915(m->private);
1344         bool lpsp_enabled = false;
1345
1346         if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
1347                 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
1348         } else if (IS_DISPLAY_VER(i915, 11, 12)) {
1349                 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
1350         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1351                 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
1352         } else {
1353                 seq_puts(m, "LPSP: not supported\n");
1354                 return 0;
1355         }
1356
1357         seq_printf(m, "LPSP: %s\n", enableddisabled(lpsp_enabled));
1358
1359         return 0;
1360 }
1361
1362 static int i915_dp_mst_info(struct seq_file *m, void *unused)
1363 {
1364         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1365         struct drm_device *dev = &dev_priv->drm;
1366         struct intel_encoder *intel_encoder;
1367         struct intel_digital_port *dig_port;
1368         struct drm_connector *connector;
1369         struct drm_connector_list_iter conn_iter;
1370
1371         drm_connector_list_iter_begin(dev, &conn_iter);
1372         drm_for_each_connector_iter(connector, &conn_iter) {
1373                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
1374                         continue;
1375
1376                 intel_encoder = intel_attached_encoder(to_intel_connector(connector));
1377                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
1378                         continue;
1379
1380                 dig_port = enc_to_dig_port(intel_encoder);
1381                 if (!intel_dp_mst_source_support(&dig_port->dp))
1382                         continue;
1383
1384                 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n",
1385                            dig_port->base.base.base.id,
1386                            dig_port->base.base.name);
1387                 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr);
1388         }
1389         drm_connector_list_iter_end(&conn_iter);
1390
1391         return 0;
1392 }
1393
1394 static ssize_t i915_displayport_test_active_write(struct file *file,
1395                                                   const char __user *ubuf,
1396                                                   size_t len, loff_t *offp)
1397 {
1398         char *input_buffer;
1399         int status = 0;
1400         struct drm_device *dev;
1401         struct drm_connector *connector;
1402         struct drm_connector_list_iter conn_iter;
1403         struct intel_dp *intel_dp;
1404         int val = 0;
1405
1406         dev = ((struct seq_file *)file->private_data)->private;
1407
1408         if (len == 0)
1409                 return 0;
1410
1411         input_buffer = memdup_user_nul(ubuf, len);
1412         if (IS_ERR(input_buffer))
1413                 return PTR_ERR(input_buffer);
1414
1415         drm_dbg(&to_i915(dev)->drm,
1416                 "Copied %d bytes from user\n", (unsigned int)len);
1417
1418         drm_connector_list_iter_begin(dev, &conn_iter);
1419         drm_for_each_connector_iter(connector, &conn_iter) {
1420                 struct intel_encoder *encoder;
1421
1422                 if (connector->connector_type !=
1423                     DRM_MODE_CONNECTOR_DisplayPort)
1424                         continue;
1425
1426                 encoder = to_intel_encoder(connector->encoder);
1427                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1428                         continue;
1429
1430                 if (encoder && connector->status == connector_status_connected) {
1431                         intel_dp = enc_to_intel_dp(encoder);
1432                         status = kstrtoint(input_buffer, 10, &val);
1433                         if (status < 0)
1434                                 break;
1435                         drm_dbg(&to_i915(dev)->drm,
1436                                 "Got %d for test active\n", val);
1437                         /* To prevent erroneous activation of the compliance
1438                          * testing code, only accept an actual value of 1 here
1439                          */
1440                         if (val == 1)
1441                                 intel_dp->compliance.test_active = true;
1442                         else
1443                                 intel_dp->compliance.test_active = false;
1444                 }
1445         }
1446         drm_connector_list_iter_end(&conn_iter);
1447         kfree(input_buffer);
1448         if (status < 0)
1449                 return status;
1450
1451         *offp += len;
1452         return len;
1453 }
1454
1455 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
1456 {
1457         struct drm_i915_private *dev_priv = m->private;
1458         struct drm_device *dev = &dev_priv->drm;
1459         struct drm_connector *connector;
1460         struct drm_connector_list_iter conn_iter;
1461         struct intel_dp *intel_dp;
1462
1463         drm_connector_list_iter_begin(dev, &conn_iter);
1464         drm_for_each_connector_iter(connector, &conn_iter) {
1465                 struct intel_encoder *encoder;
1466
1467                 if (connector->connector_type !=
1468                     DRM_MODE_CONNECTOR_DisplayPort)
1469                         continue;
1470
1471                 encoder = to_intel_encoder(connector->encoder);
1472                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1473                         continue;
1474
1475                 if (encoder && connector->status == connector_status_connected) {
1476                         intel_dp = enc_to_intel_dp(encoder);
1477                         if (intel_dp->compliance.test_active)
1478                                 seq_puts(m, "1");
1479                         else
1480                                 seq_puts(m, "0");
1481                 } else
1482                         seq_puts(m, "0");
1483         }
1484         drm_connector_list_iter_end(&conn_iter);
1485
1486         return 0;
1487 }
1488
1489 static int i915_displayport_test_active_open(struct inode *inode,
1490                                              struct file *file)
1491 {
1492         return single_open(file, i915_displayport_test_active_show,
1493                            inode->i_private);
1494 }
1495
1496 static const struct file_operations i915_displayport_test_active_fops = {
1497         .owner = THIS_MODULE,
1498         .open = i915_displayport_test_active_open,
1499         .read = seq_read,
1500         .llseek = seq_lseek,
1501         .release = single_release,
1502         .write = i915_displayport_test_active_write
1503 };
1504
1505 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
1506 {
1507         struct drm_i915_private *dev_priv = m->private;
1508         struct drm_device *dev = &dev_priv->drm;
1509         struct drm_connector *connector;
1510         struct drm_connector_list_iter conn_iter;
1511         struct intel_dp *intel_dp;
1512
1513         drm_connector_list_iter_begin(dev, &conn_iter);
1514         drm_for_each_connector_iter(connector, &conn_iter) {
1515                 struct intel_encoder *encoder;
1516
1517                 if (connector->connector_type !=
1518                     DRM_MODE_CONNECTOR_DisplayPort)
1519                         continue;
1520
1521                 encoder = to_intel_encoder(connector->encoder);
1522                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1523                         continue;
1524
1525                 if (encoder && connector->status == connector_status_connected) {
1526                         intel_dp = enc_to_intel_dp(encoder);
1527                         if (intel_dp->compliance.test_type ==
1528                             DP_TEST_LINK_EDID_READ)
1529                                 seq_printf(m, "%lx",
1530                                            intel_dp->compliance.test_data.edid);
1531                         else if (intel_dp->compliance.test_type ==
1532                                  DP_TEST_LINK_VIDEO_PATTERN) {
1533                                 seq_printf(m, "hdisplay: %d\n",
1534                                            intel_dp->compliance.test_data.hdisplay);
1535                                 seq_printf(m, "vdisplay: %d\n",
1536                                            intel_dp->compliance.test_data.vdisplay);
1537                                 seq_printf(m, "bpc: %u\n",
1538                                            intel_dp->compliance.test_data.bpc);
1539                         } else if (intel_dp->compliance.test_type ==
1540                                    DP_TEST_LINK_PHY_TEST_PATTERN) {
1541                                 seq_printf(m, "pattern: %d\n",
1542                                            intel_dp->compliance.test_data.phytest.phy_pattern);
1543                                 seq_printf(m, "Number of lanes: %d\n",
1544                                            intel_dp->compliance.test_data.phytest.num_lanes);
1545                                 seq_printf(m, "Link Rate: %d\n",
1546                                            intel_dp->compliance.test_data.phytest.link_rate);
1547                                 seq_printf(m, "level: %02x\n",
1548                                            intel_dp->train_set[0]);
1549                         }
1550                 } else
1551                         seq_puts(m, "0");
1552         }
1553         drm_connector_list_iter_end(&conn_iter);
1554
1555         return 0;
1556 }
1557 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
1558
1559 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
1560 {
1561         struct drm_i915_private *dev_priv = m->private;
1562         struct drm_device *dev = &dev_priv->drm;
1563         struct drm_connector *connector;
1564         struct drm_connector_list_iter conn_iter;
1565         struct intel_dp *intel_dp;
1566
1567         drm_connector_list_iter_begin(dev, &conn_iter);
1568         drm_for_each_connector_iter(connector, &conn_iter) {
1569                 struct intel_encoder *encoder;
1570
1571                 if (connector->connector_type !=
1572                     DRM_MODE_CONNECTOR_DisplayPort)
1573                         continue;
1574
1575                 encoder = to_intel_encoder(connector->encoder);
1576                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1577                         continue;
1578
1579                 if (encoder && connector->status == connector_status_connected) {
1580                         intel_dp = enc_to_intel_dp(encoder);
1581                         seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
1582                 } else
1583                         seq_puts(m, "0");
1584         }
1585         drm_connector_list_iter_end(&conn_iter);
1586
1587         return 0;
1588 }
1589 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
1590
1591 static void wm_latency_show(struct seq_file *m, const u16 wm[8])
1592 {
1593         struct drm_i915_private *dev_priv = m->private;
1594         struct drm_device *dev = &dev_priv->drm;
1595         int level;
1596         int num_levels;
1597
1598         if (IS_CHERRYVIEW(dev_priv))
1599                 num_levels = 3;
1600         else if (IS_VALLEYVIEW(dev_priv))
1601                 num_levels = 1;
1602         else if (IS_G4X(dev_priv))
1603                 num_levels = 3;
1604         else
1605                 num_levels = ilk_wm_max_level(dev_priv) + 1;
1606
1607         drm_modeset_lock_all(dev);
1608
1609         for (level = 0; level < num_levels; level++) {
1610                 unsigned int latency = wm[level];
1611
1612                 /*
1613                  * - WM1+ latency values in 0.5us units
1614                  * - latencies are in us on gen9/vlv/chv
1615                  */
1616                 if (DISPLAY_VER(dev_priv) >= 9 ||
1617                     IS_VALLEYVIEW(dev_priv) ||
1618                     IS_CHERRYVIEW(dev_priv) ||
1619                     IS_G4X(dev_priv))
1620                         latency *= 10;
1621                 else if (level > 0)
1622                         latency *= 5;
1623
1624                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
1625                            level, wm[level], latency / 10, latency % 10);
1626         }
1627
1628         drm_modeset_unlock_all(dev);
1629 }
1630
1631 static int pri_wm_latency_show(struct seq_file *m, void *data)
1632 {
1633         struct drm_i915_private *dev_priv = m->private;
1634         const u16 *latencies;
1635
1636         if (DISPLAY_VER(dev_priv) >= 9)
1637                 latencies = dev_priv->wm.skl_latency;
1638         else
1639                 latencies = dev_priv->wm.pri_latency;
1640
1641         wm_latency_show(m, latencies);
1642
1643         return 0;
1644 }
1645
1646 static int spr_wm_latency_show(struct seq_file *m, void *data)
1647 {
1648         struct drm_i915_private *dev_priv = m->private;
1649         const u16 *latencies;
1650
1651         if (DISPLAY_VER(dev_priv) >= 9)
1652                 latencies = dev_priv->wm.skl_latency;
1653         else
1654                 latencies = dev_priv->wm.spr_latency;
1655
1656         wm_latency_show(m, latencies);
1657
1658         return 0;
1659 }
1660
1661 static int cur_wm_latency_show(struct seq_file *m, void *data)
1662 {
1663         struct drm_i915_private *dev_priv = m->private;
1664         const u16 *latencies;
1665
1666         if (DISPLAY_VER(dev_priv) >= 9)
1667                 latencies = dev_priv->wm.skl_latency;
1668         else
1669                 latencies = dev_priv->wm.cur_latency;
1670
1671         wm_latency_show(m, latencies);
1672
1673         return 0;
1674 }
1675
1676 static int pri_wm_latency_open(struct inode *inode, struct file *file)
1677 {
1678         struct drm_i915_private *dev_priv = inode->i_private;
1679
1680         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
1681                 return -ENODEV;
1682
1683         return single_open(file, pri_wm_latency_show, dev_priv);
1684 }
1685
1686 static int spr_wm_latency_open(struct inode *inode, struct file *file)
1687 {
1688         struct drm_i915_private *dev_priv = inode->i_private;
1689
1690         if (HAS_GMCH(dev_priv))
1691                 return -ENODEV;
1692
1693         return single_open(file, spr_wm_latency_show, dev_priv);
1694 }
1695
1696 static int cur_wm_latency_open(struct inode *inode, struct file *file)
1697 {
1698         struct drm_i915_private *dev_priv = inode->i_private;
1699
1700         if (HAS_GMCH(dev_priv))
1701                 return -ENODEV;
1702
1703         return single_open(file, cur_wm_latency_show, dev_priv);
1704 }
1705
1706 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
1707                                 size_t len, loff_t *offp, u16 wm[8])
1708 {
1709         struct seq_file *m = file->private_data;
1710         struct drm_i915_private *dev_priv = m->private;
1711         struct drm_device *dev = &dev_priv->drm;
1712         u16 new[8] = { 0 };
1713         int num_levels;
1714         int level;
1715         int ret;
1716         char tmp[32];
1717
1718         if (IS_CHERRYVIEW(dev_priv))
1719                 num_levels = 3;
1720         else if (IS_VALLEYVIEW(dev_priv))
1721                 num_levels = 1;
1722         else if (IS_G4X(dev_priv))
1723                 num_levels = 3;
1724         else
1725                 num_levels = ilk_wm_max_level(dev_priv) + 1;
1726
1727         if (len >= sizeof(tmp))
1728                 return -EINVAL;
1729
1730         if (copy_from_user(tmp, ubuf, len))
1731                 return -EFAULT;
1732
1733         tmp[len] = '\0';
1734
1735         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
1736                      &new[0], &new[1], &new[2], &new[3],
1737                      &new[4], &new[5], &new[6], &new[7]);
1738         if (ret != num_levels)
1739                 return -EINVAL;
1740
1741         drm_modeset_lock_all(dev);
1742
1743         for (level = 0; level < num_levels; level++)
1744                 wm[level] = new[level];
1745
1746         drm_modeset_unlock_all(dev);
1747
1748         return len;
1749 }
1750
1751
1752 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
1753                                     size_t len, loff_t *offp)
1754 {
1755         struct seq_file *m = file->private_data;
1756         struct drm_i915_private *dev_priv = m->private;
1757         u16 *latencies;
1758
1759         if (DISPLAY_VER(dev_priv) >= 9)
1760                 latencies = dev_priv->wm.skl_latency;
1761         else
1762                 latencies = dev_priv->wm.pri_latency;
1763
1764         return wm_latency_write(file, ubuf, len, offp, latencies);
1765 }
1766
1767 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
1768                                     size_t len, loff_t *offp)
1769 {
1770         struct seq_file *m = file->private_data;
1771         struct drm_i915_private *dev_priv = m->private;
1772         u16 *latencies;
1773
1774         if (DISPLAY_VER(dev_priv) >= 9)
1775                 latencies = dev_priv->wm.skl_latency;
1776         else
1777                 latencies = dev_priv->wm.spr_latency;
1778
1779         return wm_latency_write(file, ubuf, len, offp, latencies);
1780 }
1781
1782 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
1783                                     size_t len, loff_t *offp)
1784 {
1785         struct seq_file *m = file->private_data;
1786         struct drm_i915_private *dev_priv = m->private;
1787         u16 *latencies;
1788
1789         if (DISPLAY_VER(dev_priv) >= 9)
1790                 latencies = dev_priv->wm.skl_latency;
1791         else
1792                 latencies = dev_priv->wm.cur_latency;
1793
1794         return wm_latency_write(file, ubuf, len, offp, latencies);
1795 }
1796
1797 static const struct file_operations i915_pri_wm_latency_fops = {
1798         .owner = THIS_MODULE,
1799         .open = pri_wm_latency_open,
1800         .read = seq_read,
1801         .llseek = seq_lseek,
1802         .release = single_release,
1803         .write = pri_wm_latency_write
1804 };
1805
1806 static const struct file_operations i915_spr_wm_latency_fops = {
1807         .owner = THIS_MODULE,
1808         .open = spr_wm_latency_open,
1809         .read = seq_read,
1810         .llseek = seq_lseek,
1811         .release = single_release,
1812         .write = spr_wm_latency_write
1813 };
1814
1815 static const struct file_operations i915_cur_wm_latency_fops = {
1816         .owner = THIS_MODULE,
1817         .open = cur_wm_latency_open,
1818         .read = seq_read,
1819         .llseek = seq_lseek,
1820         .release = single_release,
1821         .write = cur_wm_latency_write
1822 };
1823
1824 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
1825 {
1826         struct drm_i915_private *dev_priv = m->private;
1827         struct i915_hotplug *hotplug = &dev_priv->hotplug;
1828
1829         /* Synchronize with everything first in case there's been an HPD
1830          * storm, but we haven't finished handling it in the kernel yet
1831          */
1832         intel_synchronize_irq(dev_priv);
1833         flush_work(&dev_priv->hotplug.dig_port_work);
1834         flush_delayed_work(&dev_priv->hotplug.hotplug_work);
1835
1836         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
1837         seq_printf(m, "Detected: %s\n",
1838                    yesno(delayed_work_pending(&hotplug->reenable_work)));
1839
1840         return 0;
1841 }
1842
1843 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
1844                                         const char __user *ubuf, size_t len,
1845                                         loff_t *offp)
1846 {
1847         struct seq_file *m = file->private_data;
1848         struct drm_i915_private *dev_priv = m->private;
1849         struct i915_hotplug *hotplug = &dev_priv->hotplug;
1850         unsigned int new_threshold;
1851         int i;
1852         char *newline;
1853         char tmp[16];
1854
1855         if (len >= sizeof(tmp))
1856                 return -EINVAL;
1857
1858         if (copy_from_user(tmp, ubuf, len))
1859                 return -EFAULT;
1860
1861         tmp[len] = '\0';
1862
1863         /* Strip newline, if any */
1864         newline = strchr(tmp, '\n');
1865         if (newline)
1866                 *newline = '\0';
1867
1868         if (strcmp(tmp, "reset") == 0)
1869                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
1870         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
1871                 return -EINVAL;
1872
1873         if (new_threshold > 0)
1874                 drm_dbg_kms(&dev_priv->drm,
1875                             "Setting HPD storm detection threshold to %d\n",
1876                             new_threshold);
1877         else
1878                 drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n");
1879
1880         spin_lock_irq(&dev_priv->irq_lock);
1881         hotplug->hpd_storm_threshold = new_threshold;
1882         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1883         for_each_hpd_pin(i)
1884                 hotplug->stats[i].count = 0;
1885         spin_unlock_irq(&dev_priv->irq_lock);
1886
1887         /* Re-enable hpd immediately if we were in an irq storm */
1888         flush_delayed_work(&dev_priv->hotplug.reenable_work);
1889
1890         return len;
1891 }
1892
1893 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
1894 {
1895         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
1896 }
1897
1898 static const struct file_operations i915_hpd_storm_ctl_fops = {
1899         .owner = THIS_MODULE,
1900         .open = i915_hpd_storm_ctl_open,
1901         .read = seq_read,
1902         .llseek = seq_lseek,
1903         .release = single_release,
1904         .write = i915_hpd_storm_ctl_write
1905 };
1906
1907 static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
1908 {
1909         struct drm_i915_private *dev_priv = m->private;
1910
1911         seq_printf(m, "Enabled: %s\n",
1912                    yesno(dev_priv->hotplug.hpd_short_storm_enabled));
1913
1914         return 0;
1915 }
1916
1917 static int
1918 i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file)
1919 {
1920         return single_open(file, i915_hpd_short_storm_ctl_show,
1921                            inode->i_private);
1922 }
1923
1924 static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
1925                                               const char __user *ubuf,
1926                                               size_t len, loff_t *offp)
1927 {
1928         struct seq_file *m = file->private_data;
1929         struct drm_i915_private *dev_priv = m->private;
1930         struct i915_hotplug *hotplug = &dev_priv->hotplug;
1931         char *newline;
1932         char tmp[16];
1933         int i;
1934         bool new_state;
1935
1936         if (len >= sizeof(tmp))
1937                 return -EINVAL;
1938
1939         if (copy_from_user(tmp, ubuf, len))
1940                 return -EFAULT;
1941
1942         tmp[len] = '\0';
1943
1944         /* Strip newline, if any */
1945         newline = strchr(tmp, '\n');
1946         if (newline)
1947                 *newline = '\0';
1948
1949         /* Reset to the "default" state for this system */
1950         if (strcmp(tmp, "reset") == 0)
1951                 new_state = !HAS_DP_MST(dev_priv);
1952         else if (kstrtobool(tmp, &new_state) != 0)
1953                 return -EINVAL;
1954
1955         drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
1956                     new_state ? "En" : "Dis");
1957
1958         spin_lock_irq(&dev_priv->irq_lock);
1959         hotplug->hpd_short_storm_enabled = new_state;
1960         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1961         for_each_hpd_pin(i)
1962                 hotplug->stats[i].count = 0;
1963         spin_unlock_irq(&dev_priv->irq_lock);
1964
1965         /* Re-enable hpd immediately if we were in an irq storm */
1966         flush_delayed_work(&dev_priv->hotplug.reenable_work);
1967
1968         return len;
1969 }
1970
1971 static const struct file_operations i915_hpd_short_storm_ctl_fops = {
1972         .owner = THIS_MODULE,
1973         .open = i915_hpd_short_storm_ctl_open,
1974         .read = seq_read,
1975         .llseek = seq_lseek,
1976         .release = single_release,
1977         .write = i915_hpd_short_storm_ctl_write,
1978 };
1979
1980 static int i915_drrs_ctl_set(void *data, u64 val)
1981 {
1982         struct drm_i915_private *dev_priv = data;
1983         struct drm_device *dev = &dev_priv->drm;
1984         struct intel_crtc *crtc;
1985
1986         if (DISPLAY_VER(dev_priv) < 7)
1987                 return -ENODEV;
1988
1989         for_each_intel_crtc(dev, crtc) {
1990                 struct drm_connector_list_iter conn_iter;
1991                 struct intel_crtc_state *crtc_state;
1992                 struct drm_connector *connector;
1993                 struct drm_crtc_commit *commit;
1994                 int ret;
1995
1996                 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
1997                 if (ret)
1998                         return ret;
1999
2000                 crtc_state = to_intel_crtc_state(crtc->base.state);
2001
2002                 if (!crtc_state->hw.active ||
2003                     !crtc_state->has_drrs)
2004                         goto out;
2005
2006                 commit = crtc_state->uapi.commit;
2007                 if (commit) {
2008                         ret = wait_for_completion_interruptible(&commit->hw_done);
2009                         if (ret)
2010                                 goto out;
2011                 }
2012
2013                 drm_connector_list_iter_begin(dev, &conn_iter);
2014                 drm_for_each_connector_iter(connector, &conn_iter) {
2015                         struct intel_encoder *encoder;
2016                         struct intel_dp *intel_dp;
2017
2018                         if (!(crtc_state->uapi.connector_mask &
2019                               drm_connector_mask(connector)))
2020                                 continue;
2021
2022                         encoder = intel_attached_encoder(to_intel_connector(connector));
2023                         if (encoder->type != INTEL_OUTPUT_EDP)
2024                                 continue;
2025
2026                         drm_dbg(&dev_priv->drm,
2027                                 "Manually %sabling DRRS. %llu\n",
2028                                 val ? "en" : "dis", val);
2029
2030                         intel_dp = enc_to_intel_dp(encoder);
2031                         if (val)
2032                                 intel_drrs_enable(intel_dp, crtc_state);
2033                         else
2034                                 intel_drrs_disable(intel_dp, crtc_state);
2035                 }
2036                 drm_connector_list_iter_end(&conn_iter);
2037
2038 out:
2039                 drm_modeset_unlock(&crtc->base.mutex);
2040                 if (ret)
2041                         return ret;
2042         }
2043
2044         return 0;
2045 }
2046
2047 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
2048
2049 static ssize_t
2050 i915_fifo_underrun_reset_write(struct file *filp,
2051                                const char __user *ubuf,
2052                                size_t cnt, loff_t *ppos)
2053 {
2054         struct drm_i915_private *dev_priv = filp->private_data;
2055         struct intel_crtc *crtc;
2056         struct drm_device *dev = &dev_priv->drm;
2057         int ret;
2058         bool reset;
2059
2060         ret = kstrtobool_from_user(ubuf, cnt, &reset);
2061         if (ret)
2062                 return ret;
2063
2064         if (!reset)
2065                 return cnt;
2066
2067         for_each_intel_crtc(dev, crtc) {
2068                 struct drm_crtc_commit *commit;
2069                 struct intel_crtc_state *crtc_state;
2070
2071                 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
2072                 if (ret)
2073                         return ret;
2074
2075                 crtc_state = to_intel_crtc_state(crtc->base.state);
2076                 commit = crtc_state->uapi.commit;
2077                 if (commit) {
2078                         ret = wait_for_completion_interruptible(&commit->hw_done);
2079                         if (!ret)
2080                                 ret = wait_for_completion_interruptible(&commit->flip_done);
2081                 }
2082
2083                 if (!ret && crtc_state->hw.active) {
2084                         drm_dbg_kms(&dev_priv->drm,
2085                                     "Re-arming FIFO underruns on pipe %c\n",
2086                                     pipe_name(crtc->pipe));
2087
2088                         intel_crtc_arm_fifo_underrun(crtc, crtc_state);
2089                 }
2090
2091                 drm_modeset_unlock(&crtc->base.mutex);
2092
2093                 if (ret)
2094                         return ret;
2095         }
2096
2097         ret = intel_fbc_reset_underrun(dev_priv);
2098         if (ret)
2099                 return ret;
2100
2101         return cnt;
2102 }
2103
2104 static const struct file_operations i915_fifo_underrun_reset_ops = {
2105         .owner = THIS_MODULE,
2106         .open = simple_open,
2107         .write = i915_fifo_underrun_reset_write,
2108         .llseek = default_llseek,
2109 };
2110
2111 static const struct drm_info_list intel_display_debugfs_list[] = {
2112         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
2113         {"i915_fbc_status", i915_fbc_status, 0},
2114         {"i915_ips_status", i915_ips_status, 0},
2115         {"i915_sr_status", i915_sr_status, 0},
2116         {"i915_opregion", i915_opregion, 0},
2117         {"i915_vbt", i915_vbt, 0},
2118         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2119         {"i915_edp_psr_status", i915_edp_psr_status, 0},
2120         {"i915_power_domain_info", i915_power_domain_info, 0},
2121         {"i915_dmc_info", i915_dmc_info, 0},
2122         {"i915_display_info", i915_display_info, 0},
2123         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
2124         {"i915_dp_mst_info", i915_dp_mst_info, 0},
2125         {"i915_ddb_info", i915_ddb_info, 0},
2126         {"i915_drrs_status", i915_drrs_status, 0},
2127         {"i915_lpsp_status", i915_lpsp_status, 0},
2128 };
2129
2130 static const struct {
2131         const char *name;
2132         const struct file_operations *fops;
2133 } intel_display_debugfs_files[] = {
2134         {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
2135         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
2136         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
2137         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
2138         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
2139         {"i915_dp_test_data", &i915_displayport_test_data_fops},
2140         {"i915_dp_test_type", &i915_displayport_test_type_fops},
2141         {"i915_dp_test_active", &i915_displayport_test_active_fops},
2142         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
2143         {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops},
2144         {"i915_ipc_status", &i915_ipc_status_fops},
2145         {"i915_drrs_ctl", &i915_drrs_ctl_fops},
2146         {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
2147 };
2148
2149 void intel_display_debugfs_register(struct drm_i915_private *i915)
2150 {
2151         struct drm_minor *minor = i915->drm.primary;
2152         int i;
2153
2154         for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
2155                 debugfs_create_file(intel_display_debugfs_files[i].name,
2156                                     S_IRUGO | S_IWUSR,
2157                                     minor->debugfs_root,
2158                                     to_i915(minor->dev),
2159                                     intel_display_debugfs_files[i].fops);
2160         }
2161
2162         drm_debugfs_create_files(intel_display_debugfs_list,
2163                                  ARRAY_SIZE(intel_display_debugfs_list),
2164                                  minor->debugfs_root, minor);
2165 }
2166
2167 static int i915_panel_show(struct seq_file *m, void *data)
2168 {
2169         struct drm_connector *connector = m->private;
2170         struct intel_dp *intel_dp =
2171                 intel_attached_dp(to_intel_connector(connector));
2172
2173         if (connector->status != connector_status_connected)
2174                 return -ENODEV;
2175
2176         seq_printf(m, "Panel power up delay: %d\n",
2177                    intel_dp->pps.panel_power_up_delay);
2178         seq_printf(m, "Panel power down delay: %d\n",
2179                    intel_dp->pps.panel_power_down_delay);
2180         seq_printf(m, "Backlight on delay: %d\n",
2181                    intel_dp->pps.backlight_on_delay);
2182         seq_printf(m, "Backlight off delay: %d\n",
2183                    intel_dp->pps.backlight_off_delay);
2184
2185         return 0;
2186 }
2187 DEFINE_SHOW_ATTRIBUTE(i915_panel);
2188
2189 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
2190 {
2191         struct drm_connector *connector = m->private;
2192         struct drm_i915_private *i915 = to_i915(connector->dev);
2193         struct intel_connector *intel_connector = to_intel_connector(connector);
2194         int ret;
2195
2196         ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
2197         if (ret)
2198                 return ret;
2199
2200         if (!connector->encoder || connector->status != connector_status_connected) {
2201                 ret = -ENODEV;
2202                 goto out;
2203         }
2204
2205         seq_printf(m, "%s:%d HDCP version: ", connector->name,
2206                    connector->base.id);
2207         intel_hdcp_info(m, intel_connector);
2208
2209 out:
2210         drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
2211
2212         return ret;
2213 }
2214 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
2215
2216 static int i915_psr_status_show(struct seq_file *m, void *data)
2217 {
2218         struct drm_connector *connector = m->private;
2219         struct intel_dp *intel_dp =
2220                 intel_attached_dp(to_intel_connector(connector));
2221
2222         return intel_psr_status(m, intel_dp);
2223 }
2224 DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
2225
2226 static int i915_lpsp_capability_show(struct seq_file *m, void *data)
2227 {
2228         struct drm_connector *connector = m->private;
2229         struct drm_i915_private *i915 = to_i915(connector->dev);
2230         struct intel_encoder *encoder;
2231         bool lpsp_capable = false;
2232
2233         encoder = intel_attached_encoder(to_intel_connector(connector));
2234         if (!encoder)
2235                 return -ENODEV;
2236
2237         if (connector->status != connector_status_connected)
2238                 return -ENODEV;
2239
2240         if (DISPLAY_VER(i915) >= 13)
2241                 lpsp_capable = encoder->port <= PORT_B;
2242         else if (DISPLAY_VER(i915) >= 12)
2243                 /*
2244                  * Actually TGL can drive LPSP on port till DDI_C
2245                  * but there is no physical connected DDI_C on TGL sku's,
2246                  * even driver is not initilizing DDI_C port for gen12.
2247                  */
2248                 lpsp_capable = encoder->port <= PORT_B;
2249         else if (DISPLAY_VER(i915) == 11)
2250                 lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2251                                 connector->connector_type == DRM_MODE_CONNECTOR_eDP);
2252         else if (IS_DISPLAY_VER(i915, 9, 10))
2253                 lpsp_capable = (encoder->port == PORT_A &&
2254                                 (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2255                                  connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2256                                  connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort));
2257         else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
2258                 lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP;
2259
2260         seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable");
2261
2262         return 0;
2263 }
2264 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
2265
2266 static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
2267 {
2268         struct drm_connector *connector = m->private;
2269         struct drm_device *dev = connector->dev;
2270         struct drm_crtc *crtc;
2271         struct intel_dp *intel_dp;
2272         struct drm_modeset_acquire_ctx ctx;
2273         struct intel_crtc_state *crtc_state = NULL;
2274         int ret = 0;
2275         bool try_again = false;
2276
2277         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2278
2279         do {
2280                 try_again = false;
2281                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
2282                                        &ctx);
2283                 if (ret) {
2284                         if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
2285                                 try_again = true;
2286                                 continue;
2287                         }
2288                         break;
2289                 }
2290                 crtc = connector->state->crtc;
2291                 if (connector->status != connector_status_connected || !crtc) {
2292                         ret = -ENODEV;
2293                         break;
2294                 }
2295                 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2296                 if (ret == -EDEADLK) {
2297                         ret = drm_modeset_backoff(&ctx);
2298                         if (!ret) {
2299                                 try_again = true;
2300                                 continue;
2301                         }
2302                         break;
2303                 } else if (ret) {
2304                         break;
2305                 }
2306                 intel_dp = intel_attached_dp(to_intel_connector(connector));
2307                 crtc_state = to_intel_crtc_state(crtc->state);
2308                 seq_printf(m, "DSC_Enabled: %s\n",
2309                            yesno(crtc_state->dsc.compression_enable));
2310                 seq_printf(m, "DSC_Sink_Support: %s\n",
2311                            yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
2312                 seq_printf(m, "Force_DSC_Enable: %s\n",
2313                            yesno(intel_dp->force_dsc_en));
2314                 if (!intel_dp_is_edp(intel_dp))
2315                         seq_printf(m, "FEC_Sink_Support: %s\n",
2316                                    yesno(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
2317         } while (try_again);
2318
2319         drm_modeset_drop_locks(&ctx);
2320         drm_modeset_acquire_fini(&ctx);
2321
2322         return ret;
2323 }
2324
2325 static ssize_t i915_dsc_fec_support_write(struct file *file,
2326                                           const char __user *ubuf,
2327                                           size_t len, loff_t *offp)
2328 {
2329         bool dsc_enable = false;
2330         int ret;
2331         struct drm_connector *connector =
2332                 ((struct seq_file *)file->private_data)->private;
2333         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2334         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2335         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2336
2337         if (len == 0)
2338                 return 0;
2339
2340         drm_dbg(&i915->drm,
2341                 "Copied %zu bytes from user to force DSC\n", len);
2342
2343         ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
2344         if (ret < 0)
2345                 return ret;
2346
2347         drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
2348                 (dsc_enable) ? "true" : "false");
2349         intel_dp->force_dsc_en = dsc_enable;
2350
2351         *offp += len;
2352         return len;
2353 }
2354
2355 static int i915_dsc_fec_support_open(struct inode *inode,
2356                                      struct file *file)
2357 {
2358         return single_open(file, i915_dsc_fec_support_show,
2359                            inode->i_private);
2360 }
2361
2362 static const struct file_operations i915_dsc_fec_support_fops = {
2363         .owner = THIS_MODULE,
2364         .open = i915_dsc_fec_support_open,
2365         .read = seq_read,
2366         .llseek = seq_lseek,
2367         .release = single_release,
2368         .write = i915_dsc_fec_support_write
2369 };
2370
2371 static int i915_dsc_bpp_show(struct seq_file *m, void *data)
2372 {
2373         struct drm_connector *connector = m->private;
2374         struct drm_device *dev = connector->dev;
2375         struct drm_crtc *crtc;
2376         struct intel_crtc_state *crtc_state;
2377         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2378         int ret;
2379
2380         if (!encoder)
2381                 return -ENODEV;
2382
2383         ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
2384         if (ret)
2385                 return ret;
2386
2387         crtc = connector->state->crtc;
2388         if (connector->status != connector_status_connected || !crtc) {
2389                 ret = -ENODEV;
2390                 goto out;
2391         }
2392
2393         crtc_state = to_intel_crtc_state(crtc->state);
2394         seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp);
2395
2396 out:    drm_modeset_unlock(&dev->mode_config.connection_mutex);
2397
2398         return ret;
2399 }
2400
2401 static ssize_t i915_dsc_bpp_write(struct file *file,
2402                                   const char __user *ubuf,
2403                                   size_t len, loff_t *offp)
2404 {
2405         struct drm_connector *connector =
2406                 ((struct seq_file *)file->private_data)->private;
2407         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2408         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2409         int dsc_bpp = 0;
2410         int ret;
2411
2412         ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp);
2413         if (ret < 0)
2414                 return ret;
2415
2416         intel_dp->force_dsc_bpp = dsc_bpp;
2417         *offp += len;
2418
2419         return len;
2420 }
2421
2422 static int i915_dsc_bpp_open(struct inode *inode,
2423                              struct file *file)
2424 {
2425         return single_open(file, i915_dsc_bpp_show,
2426                            inode->i_private);
2427 }
2428
2429 static const struct file_operations i915_dsc_bpp_fops = {
2430         .owner = THIS_MODULE,
2431         .open = i915_dsc_bpp_open,
2432         .read = seq_read,
2433         .llseek = seq_lseek,
2434         .release = single_release,
2435         .write = i915_dsc_bpp_write
2436 };
2437
2438 /**
2439  * intel_connector_debugfs_add - add i915 specific connector debugfs files
2440  * @connector: pointer to a registered drm_connector
2441  *
2442  * Cleanup will be done by drm_connector_unregister() through a call to
2443  * drm_debugfs_connector_remove().
2444  */
2445 void intel_connector_debugfs_add(struct intel_connector *intel_connector)
2446 {
2447         struct drm_connector *connector = &intel_connector->base;
2448         struct dentry *root = connector->debugfs_entry;
2449         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2450
2451         /* The connector must have been registered beforehands. */
2452         if (!root)
2453                 return;
2454
2455         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2456                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
2457                                     connector, &i915_panel_fops);
2458                 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
2459                                     connector, &i915_psr_sink_status_fops);
2460         }
2461
2462         if (HAS_PSR(dev_priv) &&
2463             connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2464                 debugfs_create_file("i915_psr_status", 0444, root,
2465                                     connector, &i915_psr_status_fops);
2466         }
2467
2468         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2469             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2470             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
2471                 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,
2472                                     connector, &i915_hdcp_sink_capability_fops);
2473         }
2474
2475         if (DISPLAY_VER(dev_priv) >= 11 &&
2476             ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
2477             !to_intel_connector(connector)->mst_port) ||
2478             connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
2479                 debugfs_create_file("i915_dsc_fec_support", 0644, root,
2480                                     connector, &i915_dsc_fec_support_fops);
2481
2482                 debugfs_create_file("i915_dsc_bpp", 0644, root,
2483                                     connector, &i915_dsc_bpp_fops);
2484         }
2485
2486         if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2487             connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2488             connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2489             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2490             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
2491                 debugfs_create_file("i915_lpsp_capability", 0444, root,
2492                                     connector, &i915_lpsp_capability_fops);
2493 }
2494
2495 /**
2496  * intel_crtc_debugfs_add - add i915 specific crtc debugfs files
2497  * @crtc: pointer to a drm_crtc
2498  *
2499  * Failure to add debugfs entries should generally be ignored.
2500  */
2501 void intel_crtc_debugfs_add(struct drm_crtc *crtc)
2502 {
2503         if (crtc->debugfs_entry)
2504                 crtc_updates_add(crtc);
2505 }