1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <drm/drm_debugfs.h>
7 #include <drm/drm_fourcc.h>
9 #include "i915_debugfs.h"
10 #include "intel_csr.h"
11 #include "intel_display_debugfs.h"
12 #include "intel_display_power.h"
14 #include "intel_display_types.h"
16 #include "intel_fbc.h"
17 #include "intel_hdcp.h"
18 #include "intel_hdmi.h"
20 #include "intel_psr.h"
21 #include "intel_sideband.h"
22 #include "intel_sprite.h"
24 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
26 return to_i915(node->minor->dev);
29 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
31 struct drm_i915_private *dev_priv = node_to_i915(m->private);
33 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
34 dev_priv->fb_tracking.busy_bits);
36 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
37 dev_priv->fb_tracking.flip_bits);
42 static int i915_fbc_status(struct seq_file *m, void *unused)
44 struct drm_i915_private *dev_priv = node_to_i915(m->private);
45 struct intel_fbc *fbc = &dev_priv->fbc;
46 intel_wakeref_t wakeref;
48 if (!HAS_FBC(dev_priv))
51 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
52 mutex_lock(&fbc->lock);
54 if (intel_fbc_is_active(dev_priv))
55 seq_puts(m, "FBC enabled\n");
57 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
59 if (intel_fbc_is_active(dev_priv)) {
62 if (DISPLAY_VER(dev_priv) >= 8)
63 mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
64 else if (DISPLAY_VER(dev_priv) >= 7)
65 mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
66 else if (DISPLAY_VER(dev_priv) >= 5)
67 mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
68 else if (IS_G4X(dev_priv))
69 mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
71 mask = intel_de_read(dev_priv, FBC_STATUS) &
72 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
74 seq_printf(m, "Compressing: %s\n", yesno(mask));
77 mutex_unlock(&fbc->lock);
78 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
83 static int i915_fbc_false_color_get(void *data, u64 *val)
85 struct drm_i915_private *dev_priv = data;
87 if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
90 *val = dev_priv->fbc.false_color;
95 static int i915_fbc_false_color_set(void *data, u64 val)
97 struct drm_i915_private *dev_priv = data;
100 if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
103 mutex_lock(&dev_priv->fbc.lock);
105 reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
106 dev_priv->fbc.false_color = val;
108 intel_de_write(dev_priv, ILK_DPFC_CONTROL,
109 val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
111 mutex_unlock(&dev_priv->fbc.lock);
115 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
116 i915_fbc_false_color_get, i915_fbc_false_color_set,
119 static int i915_ips_status(struct seq_file *m, void *unused)
121 struct drm_i915_private *dev_priv = node_to_i915(m->private);
122 intel_wakeref_t wakeref;
124 if (!HAS_IPS(dev_priv))
127 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
129 seq_printf(m, "Enabled by kernel parameter: %s\n",
130 yesno(dev_priv->params.enable_ips));
132 if (DISPLAY_VER(dev_priv) >= 8) {
133 seq_puts(m, "Currently: unknown\n");
135 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
136 seq_puts(m, "Currently: enabled\n");
138 seq_puts(m, "Currently: disabled\n");
141 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
146 static int i915_sr_status(struct seq_file *m, void *unused)
148 struct drm_i915_private *dev_priv = node_to_i915(m->private);
149 intel_wakeref_t wakeref;
150 bool sr_enabled = false;
152 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
154 if (DISPLAY_VER(dev_priv) >= 9)
155 /* no global SR status; inspect per-plane WM */;
156 else if (HAS_PCH_SPLIT(dev_priv))
157 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
158 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
159 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
160 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
161 else if (IS_I915GM(dev_priv))
162 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
163 else if (IS_PINEVIEW(dev_priv))
164 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
165 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
166 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
168 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
170 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
175 static int i915_opregion(struct seq_file *m, void *unused)
177 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
179 if (opregion->header)
180 seq_write(m, opregion->header, OPREGION_SIZE);
185 static int i915_vbt(struct seq_file *m, void *unused)
187 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
190 seq_write(m, opregion->vbt, opregion->vbt_size);
195 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
197 struct drm_i915_private *dev_priv = node_to_i915(m->private);
198 struct drm_device *dev = &dev_priv->drm;
199 struct intel_framebuffer *fbdev_fb = NULL;
200 struct drm_framebuffer *drm_fb;
202 #ifdef CONFIG_DRM_FBDEV_EMULATION
203 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
204 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
206 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
207 fbdev_fb->base.width,
208 fbdev_fb->base.height,
209 fbdev_fb->base.format->depth,
210 fbdev_fb->base.format->cpp[0] * 8,
211 fbdev_fb->base.modifier,
212 drm_framebuffer_read_refcount(&fbdev_fb->base));
213 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base));
218 mutex_lock(&dev->mode_config.fb_lock);
219 drm_for_each_fb(drm_fb, dev) {
220 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
224 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
227 fb->base.format->depth,
228 fb->base.format->cpp[0] * 8,
230 drm_framebuffer_read_refcount(&fb->base));
231 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base));
234 mutex_unlock(&dev->mode_config.fb_lock);
239 static int i915_psr_sink_status_show(struct seq_file *m, void *data)
242 static const char * const sink_status[] = {
244 "transition to active, capture and display",
245 "active, display from RFB",
246 "active, capture and display on sink device timings",
247 "transition to inactive, capture and display, timing re-sync",
250 "sink internal error",
252 struct drm_connector *connector = m->private;
253 struct intel_dp *intel_dp =
254 intel_attached_dp(to_intel_connector(connector));
257 if (!CAN_PSR(intel_dp)) {
258 seq_puts(m, "PSR Unsupported\n");
262 if (connector->status != connector_status_connected)
265 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
268 const char *str = "unknown";
270 val &= DP_PSR_SINK_STATE_MASK;
271 if (val < ARRAY_SIZE(sink_status))
272 str = sink_status[val];
273 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
280 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
283 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
285 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
286 const char *status = "unknown";
289 if (intel_dp->psr.psr2_enabled) {
290 static const char * const live_status[] = {
303 val = intel_de_read(dev_priv,
304 EDP_PSR2_STATUS(intel_dp->psr.transcoder));
305 status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
306 EDP_PSR2_STATUS_STATE_SHIFT;
307 if (status_val < ARRAY_SIZE(live_status))
308 status = live_status[status_val];
310 static const char * const live_status[] = {
320 val = intel_de_read(dev_priv,
321 EDP_PSR_STATUS(intel_dp->psr.transcoder));
322 status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
323 EDP_PSR_STATUS_STATE_SHIFT;
324 if (status_val < ARRAY_SIZE(live_status))
325 status = live_status[status_val];
328 seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
331 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
333 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
334 struct intel_psr *psr = &intel_dp->psr;
335 intel_wakeref_t wakeref;
340 seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
341 if (psr->sink_support)
342 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
345 if (!psr->sink_support)
348 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
349 mutex_lock(&psr->lock);
352 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
355 seq_printf(m, "PSR mode: %s\n", status);
358 seq_printf(m, "PSR sink not reliable: %s\n",
359 yesno(psr->sink_not_reliable));
364 if (psr->psr2_enabled) {
365 val = intel_de_read(dev_priv,
366 EDP_PSR2_CTL(intel_dp->psr.transcoder));
367 enabled = val & EDP_PSR2_ENABLE;
369 val = intel_de_read(dev_priv,
370 EDP_PSR_CTL(intel_dp->psr.transcoder));
371 enabled = val & EDP_PSR_ENABLE;
373 seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
374 enableddisabled(enabled), val);
375 psr_source_status(intel_dp, m);
376 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
377 psr->busy_frontbuffer_bits);
380 * SKL+ Perf counter is reset to 0 everytime DC state is entered
382 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
383 val = intel_de_read(dev_priv,
384 EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
385 val &= EDP_PSR_PERF_CNT_MASK;
386 seq_printf(m, "Performance counter: %u\n", val);
389 if (psr->debug & I915_PSR_DEBUG_IRQ) {
390 seq_printf(m, "Last attempted entry at: %lld\n",
391 psr->last_entry_attempt);
392 seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
395 if (psr->psr2_enabled) {
396 u32 su_frames_val[3];
400 * Reading all 3 registers before hand to minimize crossing a
401 * frame boundary between register reads
403 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
404 val = intel_de_read(dev_priv,
405 PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
406 su_frames_val[frame / 3] = val;
409 seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
411 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
414 su_blocks = su_frames_val[frame / 3] &
415 PSR2_SU_STATUS_MASK(frame);
416 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
417 seq_printf(m, "%d\t%d\n", frame, su_blocks);
420 seq_printf(m, "PSR2 selective fetch: %s\n",
421 enableddisabled(psr->psr2_sel_fetch_enabled));
425 mutex_unlock(&psr->lock);
426 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
431 static int i915_edp_psr_status(struct seq_file *m, void *data)
433 struct drm_i915_private *dev_priv = node_to_i915(m->private);
434 struct intel_dp *intel_dp = NULL;
435 struct intel_encoder *encoder;
437 if (!HAS_PSR(dev_priv))
440 /* Find the first EDP which supports PSR */
441 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
442 intel_dp = enc_to_intel_dp(encoder);
449 return intel_psr_status(m, intel_dp);
453 i915_edp_psr_debug_set(void *data, u64 val)
455 struct drm_i915_private *dev_priv = data;
456 struct intel_encoder *encoder;
457 intel_wakeref_t wakeref;
460 if (!HAS_PSR(dev_priv))
463 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
464 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
466 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
468 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
470 // TODO: split to each transcoder's PSR debug state
471 ret = intel_psr_debug_set(intel_dp, val);
473 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
480 i915_edp_psr_debug_get(void *data, u64 *val)
482 struct drm_i915_private *dev_priv = data;
483 struct intel_encoder *encoder;
485 if (!HAS_PSR(dev_priv))
488 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
489 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
491 // TODO: split to each transcoder's PSR debug state
492 *val = READ_ONCE(intel_dp->psr.debug);
499 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
500 i915_edp_psr_debug_get, i915_edp_psr_debug_set,
503 static int i915_power_domain_info(struct seq_file *m, void *unused)
505 struct drm_i915_private *dev_priv = node_to_i915(m->private);
506 struct i915_power_domains *power_domains = &dev_priv->power_domains;
509 mutex_lock(&power_domains->lock);
511 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
512 for (i = 0; i < power_domains->power_well_count; i++) {
513 struct i915_power_well *power_well;
514 enum intel_display_power_domain power_domain;
516 power_well = &power_domains->power_wells[i];
517 seq_printf(m, "%-25s %d\n", power_well->desc->name,
520 for_each_power_domain(power_domain, power_well->desc->domains)
521 seq_printf(m, " %-23s %d\n",
522 intel_display_power_domain_str(power_domain),
523 power_domains->domain_use_count[power_domain]);
526 mutex_unlock(&power_domains->lock);
531 static int i915_dmc_info(struct seq_file *m, void *unused)
533 struct drm_i915_private *dev_priv = node_to_i915(m->private);
534 intel_wakeref_t wakeref;
535 struct intel_csr *csr;
536 i915_reg_t dc5_reg, dc6_reg = {};
538 if (!HAS_CSR(dev_priv))
541 csr = &dev_priv->csr;
543 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
545 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
546 seq_printf(m, "path: %s\n", csr->fw_path);
548 if (!csr->dmc_payload)
551 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
552 CSR_VERSION_MINOR(csr->version));
554 if (DISPLAY_VER(dev_priv) >= 12) {
555 if (IS_DGFX(dev_priv)) {
556 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
558 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
559 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
563 * NOTE: DMC_DEBUG3 is a general purpose reg.
564 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
565 * reg for DC3CO debugging and validation,
566 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
568 seq_printf(m, "DC3CO count: %d\n",
569 intel_de_read(dev_priv, DMC_DEBUG3));
571 dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
572 SKL_CSR_DC3_DC5_COUNT;
573 if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
574 dc6_reg = SKL_CSR_DC5_DC6_COUNT;
577 seq_printf(m, "DC3 -> DC5 count: %d\n",
578 intel_de_read(dev_priv, dc5_reg));
580 seq_printf(m, "DC5 -> DC6 count: %d\n",
581 intel_de_read(dev_priv, dc6_reg));
584 seq_printf(m, "program base: 0x%08x\n",
585 intel_de_read(dev_priv, CSR_PROGRAM(0)));
586 seq_printf(m, "ssp base: 0x%08x\n",
587 intel_de_read(dev_priv, CSR_SSP_BASE));
588 seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
590 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
595 static void intel_seq_print_mode(struct seq_file *m, int tabs,
596 const struct drm_display_mode *mode)
600 for (i = 0; i < tabs; i++)
603 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
606 static void intel_encoder_info(struct seq_file *m,
607 struct intel_crtc *crtc,
608 struct intel_encoder *encoder)
610 struct drm_i915_private *dev_priv = node_to_i915(m->private);
611 struct drm_connector_list_iter conn_iter;
612 struct drm_connector *connector;
614 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
615 encoder->base.base.id, encoder->base.name);
617 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
618 drm_for_each_connector_iter(connector, &conn_iter) {
619 const struct drm_connector_state *conn_state =
622 if (conn_state->best_encoder != &encoder->base)
625 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n",
626 connector->base.id, connector->name);
628 drm_connector_list_iter_end(&conn_iter);
631 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
633 const struct drm_display_mode *mode = panel->fixed_mode;
635 seq_printf(m, "\tfixed mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
638 static void intel_hdcp_info(struct seq_file *m,
639 struct intel_connector *intel_connector)
641 bool hdcp_cap, hdcp2_cap;
643 if (!intel_connector->hdcp.shim) {
644 seq_puts(m, "No Connector Support");
648 hdcp_cap = intel_hdcp_capable(intel_connector);
649 hdcp2_cap = intel_hdcp2_capable(intel_connector);
652 seq_puts(m, "HDCP1.4 ");
654 seq_puts(m, "HDCP2.2 ");
656 if (!hdcp_cap && !hdcp2_cap)
663 static void intel_dp_info(struct seq_file *m,
664 struct intel_connector *intel_connector)
666 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
667 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
668 const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr;
670 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
671 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
672 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
673 intel_panel_info(m, &intel_connector->panel);
675 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
676 edid ? edid->data : NULL, &intel_dp->aux);
679 static void intel_dp_mst_info(struct seq_file *m,
680 struct intel_connector *intel_connector)
682 bool has_audio = intel_connector->port->has_audio;
684 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
687 static void intel_hdmi_info(struct seq_file *m,
688 struct intel_connector *intel_connector)
690 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
691 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder);
693 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
696 static void intel_lvds_info(struct seq_file *m,
697 struct intel_connector *intel_connector)
699 intel_panel_info(m, &intel_connector->panel);
702 static void intel_connector_info(struct seq_file *m,
703 struct drm_connector *connector)
705 struct intel_connector *intel_connector = to_intel_connector(connector);
706 const struct drm_connector_state *conn_state = connector->state;
707 struct intel_encoder *encoder =
708 to_intel_encoder(conn_state->best_encoder);
709 const struct drm_display_mode *mode;
711 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n",
712 connector->base.id, connector->name,
713 drm_get_connector_status_name(connector->status));
715 if (connector->status == connector_status_disconnected)
718 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
719 connector->display_info.width_mm,
720 connector->display_info.height_mm);
721 seq_printf(m, "\tsubpixel order: %s\n",
722 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
723 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev);
728 switch (connector->connector_type) {
729 case DRM_MODE_CONNECTOR_DisplayPort:
730 case DRM_MODE_CONNECTOR_eDP:
731 if (encoder->type == INTEL_OUTPUT_DP_MST)
732 intel_dp_mst_info(m, intel_connector);
734 intel_dp_info(m, intel_connector);
736 case DRM_MODE_CONNECTOR_LVDS:
737 if (encoder->type == INTEL_OUTPUT_LVDS)
738 intel_lvds_info(m, intel_connector);
740 case DRM_MODE_CONNECTOR_HDMIA:
741 if (encoder->type == INTEL_OUTPUT_HDMI ||
742 encoder->type == INTEL_OUTPUT_DDI)
743 intel_hdmi_info(m, intel_connector);
749 seq_puts(m, "\tHDCP version: ");
750 intel_hdcp_info(m, intel_connector);
752 seq_printf(m, "\tmodes:\n");
753 list_for_each_entry(mode, &connector->modes, head)
754 intel_seq_print_mode(m, 2, mode);
757 static const char *plane_type(enum drm_plane_type type)
760 case DRM_PLANE_TYPE_OVERLAY:
762 case DRM_PLANE_TYPE_PRIMARY:
764 case DRM_PLANE_TYPE_CURSOR:
767 * Deliberately omitting default: to generate compiler warnings
768 * when a new drm_plane_type gets added.
775 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
778 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
779 * will print them all to visualize if the values are misused
781 snprintf(buf, bufsize,
782 "%s%s%s%s%s%s(0x%08x)",
783 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
784 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
785 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
786 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
787 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
788 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
792 static const char *plane_visibility(const struct intel_plane_state *plane_state)
794 if (plane_state->uapi.visible)
797 if (plane_state->planar_slave)
798 return "planar-slave";
803 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
805 const struct intel_plane_state *plane_state =
806 to_intel_plane_state(plane->base.state);
807 const struct drm_framebuffer *fb = plane_state->uapi.fb;
808 struct drm_rect src, dst;
811 src = drm_plane_state_src(&plane_state->uapi);
812 dst = drm_plane_state_dest(&plane_state->uapi);
814 plane_rotation(rot_str, sizeof(rot_str),
815 plane_state->uapi.rotation);
817 seq_puts(m, "\t\tuapi: [FB:");
819 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id,
820 &fb->format->format, fb->modifier, fb->width,
823 seq_puts(m, "0] n/a,0x0,0x0,");
824 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT
825 ", rotation=%s\n", plane_visibility(plane_state),
826 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str);
828 if (plane_state->planar_linked_plane)
829 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
830 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
831 plane_state->planar_slave ? "slave" : "master");
834 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
836 const struct intel_plane_state *plane_state =
837 to_intel_plane_state(plane->base.state);
838 const struct drm_framebuffer *fb = plane_state->hw.fb;
844 plane_rotation(rot_str, sizeof(rot_str),
845 plane_state->hw.rotation);
847 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src="
848 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
849 fb->base.id, &fb->format->format,
850 fb->modifier, fb->width, fb->height,
851 yesno(plane_state->uapi.visible),
852 DRM_RECT_FP_ARG(&plane_state->uapi.src),
853 DRM_RECT_ARG(&plane_state->uapi.dst),
857 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
859 struct drm_i915_private *dev_priv = node_to_i915(m->private);
860 struct intel_plane *plane;
862 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
863 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
864 plane->base.base.id, plane->base.name,
865 plane_type(plane->base.type));
866 intel_plane_uapi_info(m, plane);
867 intel_plane_hw_info(m, plane);
871 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
873 const struct intel_crtc_state *crtc_state =
874 to_intel_crtc_state(crtc->base.state);
875 int num_scalers = crtc->num_scalers;
878 /* Not all platformas have a scaler */
880 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
882 crtc_state->scaler_state.scaler_users,
883 crtc_state->scaler_state.scaler_id);
885 for (i = 0; i < num_scalers; i++) {
886 const struct intel_scaler *sc =
887 &crtc_state->scaler_state.scalers[i];
889 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
890 i, yesno(sc->in_use), sc->mode);
894 seq_puts(m, "\tNo scalers available on this platform\n");
898 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
899 static void crtc_updates_info(struct seq_file *m,
900 struct intel_crtc *crtc,
907 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++)
908 count += crtc->debug.vbl.times[row];
909 seq_printf(m, "%sUpdates: %llu\n", hdr, count);
913 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) {
914 char columns[80] = " |";
928 snprintf(columns, sizeof(columns), "%4ld%s |",
929 DIV_ROUND_CLOSEST(BIT(row + 9), x), units);
932 if (crtc->debug.vbl.times[row]) {
933 x = ilog2(crtc->debug.vbl.times[row]);
934 memset(columns + 8, '*', x);
935 columns[8 + x] = '\0';
938 seq_printf(m, "%s%s\n", hdr, columns);
941 seq_printf(m, "%sMin update: %lluns\n",
942 hdr, crtc->debug.vbl.min);
943 seq_printf(m, "%sMax update: %lluns\n",
944 hdr, crtc->debug.vbl.max);
945 seq_printf(m, "%sAverage update: %lluns\n",
946 hdr, div64_u64(crtc->debug.vbl.sum, count));
947 seq_printf(m, "%sOverruns > %uus: %u\n",
948 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
951 static int crtc_updates_show(struct seq_file *m, void *data)
953 crtc_updates_info(m, m->private, "");
957 static int crtc_updates_open(struct inode *inode, struct file *file)
959 return single_open(file, crtc_updates_show, inode->i_private);
962 static ssize_t crtc_updates_write(struct file *file,
963 const char __user *ubuf,
964 size_t len, loff_t *offp)
966 struct seq_file *m = file->private_data;
967 struct intel_crtc *crtc = m->private;
969 /* May race with an update. Meh. */
970 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl));
975 static const struct file_operations crtc_updates_fops = {
976 .owner = THIS_MODULE,
977 .open = crtc_updates_open,
980 .release = single_release,
981 .write = crtc_updates_write
984 static void crtc_updates_add(struct drm_crtc *crtc)
986 debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry,
987 to_intel_crtc(crtc), &crtc_updates_fops);
991 static void crtc_updates_info(struct seq_file *m,
992 struct intel_crtc *crtc,
997 static void crtc_updates_add(struct drm_crtc *crtc)
1002 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
1004 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1005 const struct intel_crtc_state *crtc_state =
1006 to_intel_crtc_state(crtc->base.state);
1007 struct intel_encoder *encoder;
1009 seq_printf(m, "[CRTC:%d:%s]:\n",
1010 crtc->base.base.id, crtc->base.name);
1012 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n",
1013 yesno(crtc_state->uapi.enable),
1014 yesno(crtc_state->uapi.active),
1015 DRM_MODE_ARG(&crtc_state->uapi.mode));
1017 if (crtc_state->hw.enable) {
1018 seq_printf(m, "\thw: active=%s, adjusted_mode=" DRM_MODE_FMT "\n",
1019 yesno(crtc_state->hw.active),
1020 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
1022 seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n",
1023 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
1024 yesno(crtc_state->dither), crtc_state->pipe_bpp);
1026 intel_scaler_info(m, crtc);
1029 if (crtc_state->bigjoiner)
1030 seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
1031 crtc_state->bigjoiner_linked_crtc->base.base.id,
1032 crtc_state->bigjoiner_linked_crtc->base.name,
1033 crtc_state->bigjoiner_slave ? "slave" : "master");
1035 for_each_intel_encoder_mask(&dev_priv->drm, encoder,
1036 crtc_state->uapi.encoder_mask)
1037 intel_encoder_info(m, crtc, encoder);
1039 intel_plane_info(m, crtc);
1041 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n",
1042 yesno(!crtc->cpu_fifo_underrun_disabled),
1043 yesno(!crtc->pch_fifo_underrun_disabled));
1045 crtc_updates_info(m, crtc, "\t");
1048 static int i915_display_info(struct seq_file *m, void *unused)
1050 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1051 struct drm_device *dev = &dev_priv->drm;
1052 struct intel_crtc *crtc;
1053 struct drm_connector *connector;
1054 struct drm_connector_list_iter conn_iter;
1055 intel_wakeref_t wakeref;
1057 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1059 drm_modeset_lock_all(dev);
1061 seq_printf(m, "CRTC info\n");
1062 seq_printf(m, "---------\n");
1063 for_each_intel_crtc(dev, crtc)
1064 intel_crtc_info(m, crtc);
1066 seq_printf(m, "\n");
1067 seq_printf(m, "Connector info\n");
1068 seq_printf(m, "--------------\n");
1069 drm_connector_list_iter_begin(dev, &conn_iter);
1070 drm_for_each_connector_iter(connector, &conn_iter)
1071 intel_connector_info(m, connector);
1072 drm_connector_list_iter_end(&conn_iter);
1074 drm_modeset_unlock_all(dev);
1076 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1081 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
1083 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1084 struct drm_device *dev = &dev_priv->drm;
1087 drm_modeset_lock_all(dev);
1089 seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
1090 dev_priv->dpll.ref_clks.nssc,
1091 dev_priv->dpll.ref_clks.ssc);
1093 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
1094 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
1096 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
1098 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
1099 pll->state.pipe_mask, pll->active_mask, yesno(pll->on));
1100 seq_printf(m, " tracked hardware state:\n");
1101 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
1102 seq_printf(m, " dpll_md: 0x%08x\n",
1103 pll->state.hw_state.dpll_md);
1104 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
1105 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
1106 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
1107 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
1108 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
1109 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n",
1110 pll->state.hw_state.mg_refclkin_ctl);
1111 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
1112 pll->state.hw_state.mg_clktop2_coreclkctl1);
1113 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n",
1114 pll->state.hw_state.mg_clktop2_hsclkctl);
1115 seq_printf(m, " mg_pll_div0: 0x%08x\n",
1116 pll->state.hw_state.mg_pll_div0);
1117 seq_printf(m, " mg_pll_div1: 0x%08x\n",
1118 pll->state.hw_state.mg_pll_div1);
1119 seq_printf(m, " mg_pll_lf: 0x%08x\n",
1120 pll->state.hw_state.mg_pll_lf);
1121 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
1122 pll->state.hw_state.mg_pll_frac_lock);
1123 seq_printf(m, " mg_pll_ssc: 0x%08x\n",
1124 pll->state.hw_state.mg_pll_ssc);
1125 seq_printf(m, " mg_pll_bias: 0x%08x\n",
1126 pll->state.hw_state.mg_pll_bias);
1127 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
1128 pll->state.hw_state.mg_pll_tdc_coldst_bias);
1130 drm_modeset_unlock_all(dev);
1135 static int i915_ipc_status_show(struct seq_file *m, void *data)
1137 struct drm_i915_private *dev_priv = m->private;
1139 seq_printf(m, "Isochronous Priority Control: %s\n",
1140 yesno(dev_priv->ipc_enabled));
1144 static int i915_ipc_status_open(struct inode *inode, struct file *file)
1146 struct drm_i915_private *dev_priv = inode->i_private;
1148 if (!HAS_IPC(dev_priv))
1151 return single_open(file, i915_ipc_status_show, dev_priv);
1154 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
1155 size_t len, loff_t *offp)
1157 struct seq_file *m = file->private_data;
1158 struct drm_i915_private *dev_priv = m->private;
1159 intel_wakeref_t wakeref;
1163 ret = kstrtobool_from_user(ubuf, len, &enable);
1167 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
1168 if (!dev_priv->ipc_enabled && enable)
1169 drm_info(&dev_priv->drm,
1170 "Enabling IPC: WM will be proper only after next commit\n");
1171 dev_priv->ipc_enabled = enable;
1172 intel_enable_ipc(dev_priv);
1178 static const struct file_operations i915_ipc_status_fops = {
1179 .owner = THIS_MODULE,
1180 .open = i915_ipc_status_open,
1182 .llseek = seq_lseek,
1183 .release = single_release,
1184 .write = i915_ipc_status_write
1187 static int i915_ddb_info(struct seq_file *m, void *unused)
1189 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1190 struct drm_device *dev = &dev_priv->drm;
1191 struct skl_ddb_entry *entry;
1192 struct intel_crtc *crtc;
1194 if (DISPLAY_VER(dev_priv) < 9)
1197 drm_modeset_lock_all(dev);
1199 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
1201 for_each_intel_crtc(&dev_priv->drm, crtc) {
1202 struct intel_crtc_state *crtc_state =
1203 to_intel_crtc_state(crtc->base.state);
1204 enum pipe pipe = crtc->pipe;
1205 enum plane_id plane_id;
1207 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
1209 for_each_plane_id_on_crtc(crtc, plane_id) {
1210 entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
1211 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1,
1212 entry->start, entry->end,
1213 skl_ddb_entry_size(entry));
1216 entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
1217 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
1218 entry->end, skl_ddb_entry_size(entry));
1221 drm_modeset_unlock_all(dev);
1226 static void drrs_status_per_crtc(struct seq_file *m,
1227 struct drm_device *dev,
1228 struct intel_crtc *intel_crtc)
1230 struct drm_i915_private *dev_priv = to_i915(dev);
1231 struct i915_drrs *drrs = &dev_priv->drrs;
1233 struct drm_connector *connector;
1234 struct drm_connector_list_iter conn_iter;
1236 drm_connector_list_iter_begin(dev, &conn_iter);
1237 drm_for_each_connector_iter(connector, &conn_iter) {
1238 bool supported = false;
1240 if (connector->state->crtc != &intel_crtc->base)
1243 seq_printf(m, "%s:\n", connector->name);
1245 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
1246 drrs->type == SEAMLESS_DRRS_SUPPORT)
1249 seq_printf(m, "\tDRRS Supported: %s\n", yesno(supported));
1251 drm_connector_list_iter_end(&conn_iter);
1255 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
1256 struct intel_panel *panel;
1258 mutex_lock(&drrs->mutex);
1259 /* DRRS Supported */
1260 seq_puts(m, "\tDRRS Enabled: Yes\n");
1262 /* disable_drrs() will make drrs->dp NULL */
1264 seq_puts(m, "Idleness DRRS: Disabled\n");
1265 mutex_unlock(&drrs->mutex);
1269 panel = &drrs->dp->attached_connector->panel;
1270 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
1271 drrs->busy_frontbuffer_bits);
1273 seq_puts(m, "\n\t\t");
1274 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
1275 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
1276 vrefresh = drm_mode_vrefresh(panel->fixed_mode);
1277 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
1278 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
1279 vrefresh = drm_mode_vrefresh(panel->downclock_mode);
1281 seq_printf(m, "DRRS_State: Unknown(%d)\n",
1282 drrs->refresh_rate_type);
1283 mutex_unlock(&drrs->mutex);
1286 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
1288 seq_puts(m, "\n\t\t");
1289 mutex_unlock(&drrs->mutex);
1291 /* DRRS not supported. Print the VBT parameter*/
1292 seq_puts(m, "\tDRRS Enabled : No");
1297 static int i915_drrs_status(struct seq_file *m, void *unused)
1299 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1300 struct drm_device *dev = &dev_priv->drm;
1301 struct intel_crtc *intel_crtc;
1302 int active_crtc_cnt = 0;
1304 drm_modeset_lock_all(dev);
1305 for_each_intel_crtc(dev, intel_crtc) {
1306 if (intel_crtc->base.state->active) {
1308 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
1310 drrs_status_per_crtc(m, dev, intel_crtc);
1313 drm_modeset_unlock_all(dev);
1315 if (!active_crtc_cnt)
1316 seq_puts(m, "No active crtc found\n");
1321 #define LPSP_STATUS(COND) (COND ? seq_puts(m, "LPSP: enabled\n") : \
1322 seq_puts(m, "LPSP: disabled\n"))
1325 intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
1326 enum i915_power_well_id power_well_id)
1328 intel_wakeref_t wakeref;
1331 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1332 is_enabled = intel_display_power_well_is_enabled(i915,
1334 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1339 static int i915_lpsp_status(struct seq_file *m, void *unused)
1341 struct drm_i915_private *i915 = node_to_i915(m->private);
1343 if (DISPLAY_VER(i915) >= 13) {
1344 LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
1349 switch (DISPLAY_VER(i915)) {
1352 LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3));
1356 LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2));
1360 * Apart from HASWELL/BROADWELL other legacy platform doesn't
1363 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
1364 LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL));
1366 seq_puts(m, "LPSP: not supported\n");
1372 static int i915_dp_mst_info(struct seq_file *m, void *unused)
1374 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1375 struct drm_device *dev = &dev_priv->drm;
1376 struct intel_encoder *intel_encoder;
1377 struct intel_digital_port *dig_port;
1378 struct drm_connector *connector;
1379 struct drm_connector_list_iter conn_iter;
1381 drm_connector_list_iter_begin(dev, &conn_iter);
1382 drm_for_each_connector_iter(connector, &conn_iter) {
1383 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
1386 intel_encoder = intel_attached_encoder(to_intel_connector(connector));
1387 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
1390 dig_port = enc_to_dig_port(intel_encoder);
1391 if (!dig_port->dp.can_mst)
1394 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n",
1395 dig_port->base.base.base.id,
1396 dig_port->base.base.name);
1397 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr);
1399 drm_connector_list_iter_end(&conn_iter);
1404 static ssize_t i915_displayport_test_active_write(struct file *file,
1405 const char __user *ubuf,
1406 size_t len, loff_t *offp)
1410 struct drm_device *dev;
1411 struct drm_connector *connector;
1412 struct drm_connector_list_iter conn_iter;
1413 struct intel_dp *intel_dp;
1416 dev = ((struct seq_file *)file->private_data)->private;
1421 input_buffer = memdup_user_nul(ubuf, len);
1422 if (IS_ERR(input_buffer))
1423 return PTR_ERR(input_buffer);
1425 drm_dbg(&to_i915(dev)->drm,
1426 "Copied %d bytes from user\n", (unsigned int)len);
1428 drm_connector_list_iter_begin(dev, &conn_iter);
1429 drm_for_each_connector_iter(connector, &conn_iter) {
1430 struct intel_encoder *encoder;
1432 if (connector->connector_type !=
1433 DRM_MODE_CONNECTOR_DisplayPort)
1436 encoder = to_intel_encoder(connector->encoder);
1437 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1440 if (encoder && connector->status == connector_status_connected) {
1441 intel_dp = enc_to_intel_dp(encoder);
1442 status = kstrtoint(input_buffer, 10, &val);
1445 drm_dbg(&to_i915(dev)->drm,
1446 "Got %d for test active\n", val);
1447 /* To prevent erroneous activation of the compliance
1448 * testing code, only accept an actual value of 1 here
1451 intel_dp->compliance.test_active = true;
1453 intel_dp->compliance.test_active = false;
1456 drm_connector_list_iter_end(&conn_iter);
1457 kfree(input_buffer);
1465 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
1467 struct drm_i915_private *dev_priv = m->private;
1468 struct drm_device *dev = &dev_priv->drm;
1469 struct drm_connector *connector;
1470 struct drm_connector_list_iter conn_iter;
1471 struct intel_dp *intel_dp;
1473 drm_connector_list_iter_begin(dev, &conn_iter);
1474 drm_for_each_connector_iter(connector, &conn_iter) {
1475 struct intel_encoder *encoder;
1477 if (connector->connector_type !=
1478 DRM_MODE_CONNECTOR_DisplayPort)
1481 encoder = to_intel_encoder(connector->encoder);
1482 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1485 if (encoder && connector->status == connector_status_connected) {
1486 intel_dp = enc_to_intel_dp(encoder);
1487 if (intel_dp->compliance.test_active)
1494 drm_connector_list_iter_end(&conn_iter);
1499 static int i915_displayport_test_active_open(struct inode *inode,
1502 return single_open(file, i915_displayport_test_active_show,
1506 static const struct file_operations i915_displayport_test_active_fops = {
1507 .owner = THIS_MODULE,
1508 .open = i915_displayport_test_active_open,
1510 .llseek = seq_lseek,
1511 .release = single_release,
1512 .write = i915_displayport_test_active_write
1515 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
1517 struct drm_i915_private *dev_priv = m->private;
1518 struct drm_device *dev = &dev_priv->drm;
1519 struct drm_connector *connector;
1520 struct drm_connector_list_iter conn_iter;
1521 struct intel_dp *intel_dp;
1523 drm_connector_list_iter_begin(dev, &conn_iter);
1524 drm_for_each_connector_iter(connector, &conn_iter) {
1525 struct intel_encoder *encoder;
1527 if (connector->connector_type !=
1528 DRM_MODE_CONNECTOR_DisplayPort)
1531 encoder = to_intel_encoder(connector->encoder);
1532 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1535 if (encoder && connector->status == connector_status_connected) {
1536 intel_dp = enc_to_intel_dp(encoder);
1537 if (intel_dp->compliance.test_type ==
1538 DP_TEST_LINK_EDID_READ)
1539 seq_printf(m, "%lx",
1540 intel_dp->compliance.test_data.edid);
1541 else if (intel_dp->compliance.test_type ==
1542 DP_TEST_LINK_VIDEO_PATTERN) {
1543 seq_printf(m, "hdisplay: %d\n",
1544 intel_dp->compliance.test_data.hdisplay);
1545 seq_printf(m, "vdisplay: %d\n",
1546 intel_dp->compliance.test_data.vdisplay);
1547 seq_printf(m, "bpc: %u\n",
1548 intel_dp->compliance.test_data.bpc);
1549 } else if (intel_dp->compliance.test_type ==
1550 DP_TEST_LINK_PHY_TEST_PATTERN) {
1551 seq_printf(m, "pattern: %d\n",
1552 intel_dp->compliance.test_data.phytest.phy_pattern);
1553 seq_printf(m, "Number of lanes: %d\n",
1554 intel_dp->compliance.test_data.phytest.num_lanes);
1555 seq_printf(m, "Link Rate: %d\n",
1556 intel_dp->compliance.test_data.phytest.link_rate);
1557 seq_printf(m, "level: %02x\n",
1558 intel_dp->train_set[0]);
1563 drm_connector_list_iter_end(&conn_iter);
1567 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
1569 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
1571 struct drm_i915_private *dev_priv = m->private;
1572 struct drm_device *dev = &dev_priv->drm;
1573 struct drm_connector *connector;
1574 struct drm_connector_list_iter conn_iter;
1575 struct intel_dp *intel_dp;
1577 drm_connector_list_iter_begin(dev, &conn_iter);
1578 drm_for_each_connector_iter(connector, &conn_iter) {
1579 struct intel_encoder *encoder;
1581 if (connector->connector_type !=
1582 DRM_MODE_CONNECTOR_DisplayPort)
1585 encoder = to_intel_encoder(connector->encoder);
1586 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1589 if (encoder && connector->status == connector_status_connected) {
1590 intel_dp = enc_to_intel_dp(encoder);
1591 seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
1595 drm_connector_list_iter_end(&conn_iter);
1599 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
1601 static void wm_latency_show(struct seq_file *m, const u16 wm[8])
1603 struct drm_i915_private *dev_priv = m->private;
1604 struct drm_device *dev = &dev_priv->drm;
1608 if (IS_CHERRYVIEW(dev_priv))
1610 else if (IS_VALLEYVIEW(dev_priv))
1612 else if (IS_G4X(dev_priv))
1615 num_levels = ilk_wm_max_level(dev_priv) + 1;
1617 drm_modeset_lock_all(dev);
1619 for (level = 0; level < num_levels; level++) {
1620 unsigned int latency = wm[level];
1623 * - WM1+ latency values in 0.5us units
1624 * - latencies are in us on gen9/vlv/chv
1626 if (DISPLAY_VER(dev_priv) >= 9 ||
1627 IS_VALLEYVIEW(dev_priv) ||
1628 IS_CHERRYVIEW(dev_priv) ||
1634 seq_printf(m, "WM%d %u (%u.%u usec)\n",
1635 level, wm[level], latency / 10, latency % 10);
1638 drm_modeset_unlock_all(dev);
1641 static int pri_wm_latency_show(struct seq_file *m, void *data)
1643 struct drm_i915_private *dev_priv = m->private;
1644 const u16 *latencies;
1646 if (DISPLAY_VER(dev_priv) >= 9)
1647 latencies = dev_priv->wm.skl_latency;
1649 latencies = dev_priv->wm.pri_latency;
1651 wm_latency_show(m, latencies);
1656 static int spr_wm_latency_show(struct seq_file *m, void *data)
1658 struct drm_i915_private *dev_priv = m->private;
1659 const u16 *latencies;
1661 if (DISPLAY_VER(dev_priv) >= 9)
1662 latencies = dev_priv->wm.skl_latency;
1664 latencies = dev_priv->wm.spr_latency;
1666 wm_latency_show(m, latencies);
1671 static int cur_wm_latency_show(struct seq_file *m, void *data)
1673 struct drm_i915_private *dev_priv = m->private;
1674 const u16 *latencies;
1676 if (DISPLAY_VER(dev_priv) >= 9)
1677 latencies = dev_priv->wm.skl_latency;
1679 latencies = dev_priv->wm.cur_latency;
1681 wm_latency_show(m, latencies);
1686 static int pri_wm_latency_open(struct inode *inode, struct file *file)
1688 struct drm_i915_private *dev_priv = inode->i_private;
1690 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
1693 return single_open(file, pri_wm_latency_show, dev_priv);
1696 static int spr_wm_latency_open(struct inode *inode, struct file *file)
1698 struct drm_i915_private *dev_priv = inode->i_private;
1700 if (HAS_GMCH(dev_priv))
1703 return single_open(file, spr_wm_latency_show, dev_priv);
1706 static int cur_wm_latency_open(struct inode *inode, struct file *file)
1708 struct drm_i915_private *dev_priv = inode->i_private;
1710 if (HAS_GMCH(dev_priv))
1713 return single_open(file, cur_wm_latency_show, dev_priv);
1716 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
1717 size_t len, loff_t *offp, u16 wm[8])
1719 struct seq_file *m = file->private_data;
1720 struct drm_i915_private *dev_priv = m->private;
1721 struct drm_device *dev = &dev_priv->drm;
1728 if (IS_CHERRYVIEW(dev_priv))
1730 else if (IS_VALLEYVIEW(dev_priv))
1732 else if (IS_G4X(dev_priv))
1735 num_levels = ilk_wm_max_level(dev_priv) + 1;
1737 if (len >= sizeof(tmp))
1740 if (copy_from_user(tmp, ubuf, len))
1745 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
1746 &new[0], &new[1], &new[2], &new[3],
1747 &new[4], &new[5], &new[6], &new[7]);
1748 if (ret != num_levels)
1751 drm_modeset_lock_all(dev);
1753 for (level = 0; level < num_levels; level++)
1754 wm[level] = new[level];
1756 drm_modeset_unlock_all(dev);
1762 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
1763 size_t len, loff_t *offp)
1765 struct seq_file *m = file->private_data;
1766 struct drm_i915_private *dev_priv = m->private;
1769 if (DISPLAY_VER(dev_priv) >= 9)
1770 latencies = dev_priv->wm.skl_latency;
1772 latencies = dev_priv->wm.pri_latency;
1774 return wm_latency_write(file, ubuf, len, offp, latencies);
1777 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
1778 size_t len, loff_t *offp)
1780 struct seq_file *m = file->private_data;
1781 struct drm_i915_private *dev_priv = m->private;
1784 if (DISPLAY_VER(dev_priv) >= 9)
1785 latencies = dev_priv->wm.skl_latency;
1787 latencies = dev_priv->wm.spr_latency;
1789 return wm_latency_write(file, ubuf, len, offp, latencies);
1792 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
1793 size_t len, loff_t *offp)
1795 struct seq_file *m = file->private_data;
1796 struct drm_i915_private *dev_priv = m->private;
1799 if (DISPLAY_VER(dev_priv) >= 9)
1800 latencies = dev_priv->wm.skl_latency;
1802 latencies = dev_priv->wm.cur_latency;
1804 return wm_latency_write(file, ubuf, len, offp, latencies);
1807 static const struct file_operations i915_pri_wm_latency_fops = {
1808 .owner = THIS_MODULE,
1809 .open = pri_wm_latency_open,
1811 .llseek = seq_lseek,
1812 .release = single_release,
1813 .write = pri_wm_latency_write
1816 static const struct file_operations i915_spr_wm_latency_fops = {
1817 .owner = THIS_MODULE,
1818 .open = spr_wm_latency_open,
1820 .llseek = seq_lseek,
1821 .release = single_release,
1822 .write = spr_wm_latency_write
1825 static const struct file_operations i915_cur_wm_latency_fops = {
1826 .owner = THIS_MODULE,
1827 .open = cur_wm_latency_open,
1829 .llseek = seq_lseek,
1830 .release = single_release,
1831 .write = cur_wm_latency_write
1834 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
1836 struct drm_i915_private *dev_priv = m->private;
1837 struct i915_hotplug *hotplug = &dev_priv->hotplug;
1839 /* Synchronize with everything first in case there's been an HPD
1840 * storm, but we haven't finished handling it in the kernel yet
1842 intel_synchronize_irq(dev_priv);
1843 flush_work(&dev_priv->hotplug.dig_port_work);
1844 flush_delayed_work(&dev_priv->hotplug.hotplug_work);
1846 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
1847 seq_printf(m, "Detected: %s\n",
1848 yesno(delayed_work_pending(&hotplug->reenable_work)));
1853 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
1854 const char __user *ubuf, size_t len,
1857 struct seq_file *m = file->private_data;
1858 struct drm_i915_private *dev_priv = m->private;
1859 struct i915_hotplug *hotplug = &dev_priv->hotplug;
1860 unsigned int new_threshold;
1865 if (len >= sizeof(tmp))
1868 if (copy_from_user(tmp, ubuf, len))
1873 /* Strip newline, if any */
1874 newline = strchr(tmp, '\n');
1878 if (strcmp(tmp, "reset") == 0)
1879 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
1880 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
1883 if (new_threshold > 0)
1884 drm_dbg_kms(&dev_priv->drm,
1885 "Setting HPD storm detection threshold to %d\n",
1888 drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n");
1890 spin_lock_irq(&dev_priv->irq_lock);
1891 hotplug->hpd_storm_threshold = new_threshold;
1892 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1894 hotplug->stats[i].count = 0;
1895 spin_unlock_irq(&dev_priv->irq_lock);
1897 /* Re-enable hpd immediately if we were in an irq storm */
1898 flush_delayed_work(&dev_priv->hotplug.reenable_work);
1903 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
1905 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
1908 static const struct file_operations i915_hpd_storm_ctl_fops = {
1909 .owner = THIS_MODULE,
1910 .open = i915_hpd_storm_ctl_open,
1912 .llseek = seq_lseek,
1913 .release = single_release,
1914 .write = i915_hpd_storm_ctl_write
1917 static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
1919 struct drm_i915_private *dev_priv = m->private;
1921 seq_printf(m, "Enabled: %s\n",
1922 yesno(dev_priv->hotplug.hpd_short_storm_enabled));
1928 i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file)
1930 return single_open(file, i915_hpd_short_storm_ctl_show,
1934 static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
1935 const char __user *ubuf,
1936 size_t len, loff_t *offp)
1938 struct seq_file *m = file->private_data;
1939 struct drm_i915_private *dev_priv = m->private;
1940 struct i915_hotplug *hotplug = &dev_priv->hotplug;
1946 if (len >= sizeof(tmp))
1949 if (copy_from_user(tmp, ubuf, len))
1954 /* Strip newline, if any */
1955 newline = strchr(tmp, '\n');
1959 /* Reset to the "default" state for this system */
1960 if (strcmp(tmp, "reset") == 0)
1961 new_state = !HAS_DP_MST(dev_priv);
1962 else if (kstrtobool(tmp, &new_state) != 0)
1965 drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
1966 new_state ? "En" : "Dis");
1968 spin_lock_irq(&dev_priv->irq_lock);
1969 hotplug->hpd_short_storm_enabled = new_state;
1970 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1972 hotplug->stats[i].count = 0;
1973 spin_unlock_irq(&dev_priv->irq_lock);
1975 /* Re-enable hpd immediately if we were in an irq storm */
1976 flush_delayed_work(&dev_priv->hotplug.reenable_work);
1981 static const struct file_operations i915_hpd_short_storm_ctl_fops = {
1982 .owner = THIS_MODULE,
1983 .open = i915_hpd_short_storm_ctl_open,
1985 .llseek = seq_lseek,
1986 .release = single_release,
1987 .write = i915_hpd_short_storm_ctl_write,
1990 static int i915_drrs_ctl_set(void *data, u64 val)
1992 struct drm_i915_private *dev_priv = data;
1993 struct drm_device *dev = &dev_priv->drm;
1994 struct intel_crtc *crtc;
1996 if (DISPLAY_VER(dev_priv) < 7)
1999 for_each_intel_crtc(dev, crtc) {
2000 struct drm_connector_list_iter conn_iter;
2001 struct intel_crtc_state *crtc_state;
2002 struct drm_connector *connector;
2003 struct drm_crtc_commit *commit;
2006 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
2010 crtc_state = to_intel_crtc_state(crtc->base.state);
2012 if (!crtc_state->hw.active ||
2013 !crtc_state->has_drrs)
2016 commit = crtc_state->uapi.commit;
2018 ret = wait_for_completion_interruptible(&commit->hw_done);
2023 drm_connector_list_iter_begin(dev, &conn_iter);
2024 drm_for_each_connector_iter(connector, &conn_iter) {
2025 struct intel_encoder *encoder;
2026 struct intel_dp *intel_dp;
2028 if (!(crtc_state->uapi.connector_mask &
2029 drm_connector_mask(connector)))
2032 encoder = intel_attached_encoder(to_intel_connector(connector));
2033 if (encoder->type != INTEL_OUTPUT_EDP)
2036 drm_dbg(&dev_priv->drm,
2037 "Manually %sabling DRRS. %llu\n",
2038 val ? "en" : "dis", val);
2040 intel_dp = enc_to_intel_dp(encoder);
2042 intel_edp_drrs_enable(intel_dp,
2045 intel_edp_drrs_disable(intel_dp,
2048 drm_connector_list_iter_end(&conn_iter);
2051 drm_modeset_unlock(&crtc->base.mutex);
2059 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
2062 i915_fifo_underrun_reset_write(struct file *filp,
2063 const char __user *ubuf,
2064 size_t cnt, loff_t *ppos)
2066 struct drm_i915_private *dev_priv = filp->private_data;
2067 struct intel_crtc *intel_crtc;
2068 struct drm_device *dev = &dev_priv->drm;
2072 ret = kstrtobool_from_user(ubuf, cnt, &reset);
2079 for_each_intel_crtc(dev, intel_crtc) {
2080 struct drm_crtc_commit *commit;
2081 struct intel_crtc_state *crtc_state;
2083 ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex);
2087 crtc_state = to_intel_crtc_state(intel_crtc->base.state);
2088 commit = crtc_state->uapi.commit;
2090 ret = wait_for_completion_interruptible(&commit->hw_done);
2092 ret = wait_for_completion_interruptible(&commit->flip_done);
2095 if (!ret && crtc_state->hw.active) {
2096 drm_dbg_kms(&dev_priv->drm,
2097 "Re-arming FIFO underruns on pipe %c\n",
2098 pipe_name(intel_crtc->pipe));
2100 intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state);
2103 drm_modeset_unlock(&intel_crtc->base.mutex);
2109 ret = intel_fbc_reset_underrun(dev_priv);
2116 static const struct file_operations i915_fifo_underrun_reset_ops = {
2117 .owner = THIS_MODULE,
2118 .open = simple_open,
2119 .write = i915_fifo_underrun_reset_write,
2120 .llseek = default_llseek,
2123 static const struct drm_info_list intel_display_debugfs_list[] = {
2124 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
2125 {"i915_fbc_status", i915_fbc_status, 0},
2126 {"i915_ips_status", i915_ips_status, 0},
2127 {"i915_sr_status", i915_sr_status, 0},
2128 {"i915_opregion", i915_opregion, 0},
2129 {"i915_vbt", i915_vbt, 0},
2130 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2131 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2132 {"i915_power_domain_info", i915_power_domain_info, 0},
2133 {"i915_dmc_info", i915_dmc_info, 0},
2134 {"i915_display_info", i915_display_info, 0},
2135 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
2136 {"i915_dp_mst_info", i915_dp_mst_info, 0},
2137 {"i915_ddb_info", i915_ddb_info, 0},
2138 {"i915_drrs_status", i915_drrs_status, 0},
2139 {"i915_lpsp_status", i915_lpsp_status, 0},
2142 static const struct {
2144 const struct file_operations *fops;
2145 } intel_display_debugfs_files[] = {
2146 {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
2147 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
2148 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
2149 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
2150 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
2151 {"i915_dp_test_data", &i915_displayport_test_data_fops},
2152 {"i915_dp_test_type", &i915_displayport_test_type_fops},
2153 {"i915_dp_test_active", &i915_displayport_test_active_fops},
2154 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
2155 {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops},
2156 {"i915_ipc_status", &i915_ipc_status_fops},
2157 {"i915_drrs_ctl", &i915_drrs_ctl_fops},
2158 {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
2161 void intel_display_debugfs_register(struct drm_i915_private *i915)
2163 struct drm_minor *minor = i915->drm.primary;
2166 for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
2167 debugfs_create_file(intel_display_debugfs_files[i].name,
2169 minor->debugfs_root,
2170 to_i915(minor->dev),
2171 intel_display_debugfs_files[i].fops);
2174 drm_debugfs_create_files(intel_display_debugfs_list,
2175 ARRAY_SIZE(intel_display_debugfs_list),
2176 minor->debugfs_root, minor);
2179 static int i915_panel_show(struct seq_file *m, void *data)
2181 struct drm_connector *connector = m->private;
2182 struct intel_dp *intel_dp =
2183 intel_attached_dp(to_intel_connector(connector));
2185 if (connector->status != connector_status_connected)
2188 seq_printf(m, "Panel power up delay: %d\n",
2189 intel_dp->pps.panel_power_up_delay);
2190 seq_printf(m, "Panel power down delay: %d\n",
2191 intel_dp->pps.panel_power_down_delay);
2192 seq_printf(m, "Backlight on delay: %d\n",
2193 intel_dp->pps.backlight_on_delay);
2194 seq_printf(m, "Backlight off delay: %d\n",
2195 intel_dp->pps.backlight_off_delay);
2199 DEFINE_SHOW_ATTRIBUTE(i915_panel);
2201 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
2203 struct drm_connector *connector = m->private;
2204 struct drm_i915_private *i915 = to_i915(connector->dev);
2205 struct intel_connector *intel_connector = to_intel_connector(connector);
2208 ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
2212 if (!connector->encoder || connector->status != connector_status_connected) {
2217 seq_printf(m, "%s:%d HDCP version: ", connector->name,
2218 connector->base.id);
2219 intel_hdcp_info(m, intel_connector);
2222 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
2226 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
2228 static int i915_psr_status_show(struct seq_file *m, void *data)
2230 struct drm_connector *connector = m->private;
2231 struct intel_dp *intel_dp =
2232 intel_attached_dp(to_intel_connector(connector));
2234 return intel_psr_status(m, intel_dp);
2236 DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
2238 #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
2239 seq_puts(m, "LPSP: incapable\n"))
2241 static int i915_lpsp_capability_show(struct seq_file *m, void *data)
2243 struct drm_connector *connector = m->private;
2244 struct drm_i915_private *i915 = to_i915(connector->dev);
2245 struct intel_encoder *encoder;
2247 encoder = intel_attached_encoder(to_intel_connector(connector));
2251 if (connector->status != connector_status_connected)
2254 switch (DISPLAY_VER(i915)) {
2257 * Actually TGL can drive LPSP on port till DDI_C
2258 * but there is no physical connected DDI_C on TGL sku's,
2259 * even driver is not initilizing DDI_C port for gen12.
2261 LPSP_CAPABLE(encoder->port <= PORT_B);
2264 LPSP_CAPABLE(connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2265 connector->connector_type == DRM_MODE_CONNECTOR_eDP);
2269 LPSP_CAPABLE(encoder->port == PORT_A &&
2270 (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2271 connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2272 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort));
2275 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
2276 LPSP_CAPABLE(connector->connector_type == DRM_MODE_CONNECTOR_eDP);
2281 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
2283 static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
2285 struct drm_connector *connector = m->private;
2286 struct drm_device *dev = connector->dev;
2287 struct drm_crtc *crtc;
2288 struct intel_dp *intel_dp;
2289 struct drm_modeset_acquire_ctx ctx;
2290 struct intel_crtc_state *crtc_state = NULL;
2292 bool try_again = false;
2294 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2298 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
2301 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
2307 crtc = connector->state->crtc;
2308 if (connector->status != connector_status_connected || !crtc) {
2312 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2313 if (ret == -EDEADLK) {
2314 ret = drm_modeset_backoff(&ctx);
2323 intel_dp = intel_attached_dp(to_intel_connector(connector));
2324 crtc_state = to_intel_crtc_state(crtc->state);
2325 seq_printf(m, "DSC_Enabled: %s\n",
2326 yesno(crtc_state->dsc.compression_enable));
2327 seq_printf(m, "DSC_Sink_Support: %s\n",
2328 yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
2329 seq_printf(m, "Force_DSC_Enable: %s\n",
2330 yesno(intel_dp->force_dsc_en));
2331 if (!intel_dp_is_edp(intel_dp))
2332 seq_printf(m, "FEC_Sink_Support: %s\n",
2333 yesno(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
2334 } while (try_again);
2336 drm_modeset_drop_locks(&ctx);
2337 drm_modeset_acquire_fini(&ctx);
2342 static ssize_t i915_dsc_fec_support_write(struct file *file,
2343 const char __user *ubuf,
2344 size_t len, loff_t *offp)
2346 bool dsc_enable = false;
2348 struct drm_connector *connector =
2349 ((struct seq_file *)file->private_data)->private;
2350 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2351 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2352 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2358 "Copied %zu bytes from user to force DSC\n", len);
2360 ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
2364 drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
2365 (dsc_enable) ? "true" : "false");
2366 intel_dp->force_dsc_en = dsc_enable;
2372 static int i915_dsc_fec_support_open(struct inode *inode,
2375 return single_open(file, i915_dsc_fec_support_show,
2379 static const struct file_operations i915_dsc_fec_support_fops = {
2380 .owner = THIS_MODULE,
2381 .open = i915_dsc_fec_support_open,
2383 .llseek = seq_lseek,
2384 .release = single_release,
2385 .write = i915_dsc_fec_support_write
2389 * intel_connector_debugfs_add - add i915 specific connector debugfs files
2390 * @connector: pointer to a registered drm_connector
2392 * Cleanup will be done by drm_connector_unregister() through a call to
2393 * drm_debugfs_connector_remove().
2395 * Returns 0 on success, negative error codes on error.
2397 int intel_connector_debugfs_add(struct drm_connector *connector)
2399 struct dentry *root = connector->debugfs_entry;
2400 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2402 /* The connector must have been registered beforehands. */
2406 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2407 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
2408 connector, &i915_panel_fops);
2409 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
2410 connector, &i915_psr_sink_status_fops);
2413 if (HAS_PSR(dev_priv) &&
2414 connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2415 debugfs_create_file("i915_psr_status", 0444, root,
2416 connector, &i915_psr_status_fops);
2419 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2420 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2421 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
2422 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,
2423 connector, &i915_hdcp_sink_capability_fops);
2426 if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && !to_intel_connector(connector)->mst_port) || connector->connector_type == DRM_MODE_CONNECTOR_eDP))
2427 debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
2428 connector, &i915_dsc_fec_support_fops);
2430 /* Legacy panels doesn't lpsp on any platform */
2431 if ((DISPLAY_VER(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
2432 IS_BROADWELL(dev_priv)) &&
2433 (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2434 connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2435 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2436 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2437 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB))
2438 debugfs_create_file("i915_lpsp_capability", 0444, root,
2439 connector, &i915_lpsp_capability_fops);
2445 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files
2446 * @crtc: pointer to a drm_crtc
2448 * Returns 0 on success, negative error codes on error.
2450 * Failure to add debugfs entries should generally be ignored.
2452 int intel_crtc_debugfs_add(struct drm_crtc *crtc)
2454 if (!crtc->debugfs_entry)
2457 crtc_updates_add(crtc);