drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 enum link_m_n_set;
  31 enum drm_scaling_filter;
  32 struct dpll;
  33 struct drm_connector;
  34 struct drm_device;
  35 struct drm_display_mode;
  36 struct drm_encoder;
  37 struct drm_file;
  38 struct drm_format_info;
  39 struct drm_framebuffer;
  40 struct drm_i915_error_state_buf;
  41 struct drm_i915_gem_object;
  42 struct drm_i915_private;
  43 struct drm_mode_fb_cmd2;
  44 struct drm_modeset_acquire_ctx;
  45 struct drm_plane;
  46 struct drm_plane_state;
  47 struct i915_ggtt_view;
  48 struct intel_atomic_state;
  49 struct intel_crtc;
  50 struct intel_crtc_state;
  51 struct intel_crtc_state;
  52 struct intel_digital_port;
  53 struct intel_dp;
  54 struct intel_encoder;
  55 struct intel_load_detect_pipe;
  56 struct intel_plane;
  57 struct intel_plane_state;
  58 struct intel_remapped_info;
  59 struct intel_rotation_info;
  60
  61 enum i915_gpio {
  62         GPIOA,
  63         GPIOB,
  64         GPIOC,
  65         GPIOD,
  66         GPIOE,
  67         GPIOF,
  68         GPIOG,
  69         GPIOH,
  70         __GPIOI_UNUSED,
  71         GPIOJ,
  72         GPIOK,
  73         GPIOL,
  74         GPIOM,
  75         GPION,
  76         GPIOO,
  77 };
  78
  79 /*
  80  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  81  * rest have consecutive values and match the enum values of transcoders
  82  * with a 1:1 transcoder -> pipe mapping.
  83  */
  84 enum pipe {
  85         INVALID_PIPE = -1,
  86
  87         PIPE_A = 0,
  88         PIPE_B,
  89         PIPE_C,
  90         PIPE_D,
  91         _PIPE_EDP,
  92
  93         I915_MAX_PIPES = _PIPE_EDP
  94 };
  95
  96 #define pipe_name(p) ((p) + 'A')
  97
  98 enum transcoder {
  99         INVALID_TRANSCODER = -1,
 100         /*
 101          * The following transcoders have a 1:1 transcoder -> pipe mapping,
 102          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
 103          * rest have consecutive values and match the enum values of the pipes
 104          * they map to.
 105          */
 106         TRANSCODER_A = PIPE_A,
 107         TRANSCODER_B = PIPE_B,
 108         TRANSCODER_C = PIPE_C,
 109         TRANSCODER_D = PIPE_D,
 110
 111         /*
 112          * The following transcoders can map to any pipe, their enum value
 113          * doesn't need to stay fixed.
 114          */
 115         TRANSCODER_EDP,
 116         TRANSCODER_DSI_0,
 117         TRANSCODER_DSI_1,
 118         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
 119         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
 120
 121         I915_MAX_TRANSCODERS
 122 };
 123
 124 static inline const char *transcoder_name(enum transcoder transcoder)
 125 {
 126         switch (transcoder) {
 127         case TRANSCODER_A:
 128                 return "A";
 129         case TRANSCODER_B:
 130                 return "B";
 131         case TRANSCODER_C:
 132                 return "C";
 133         case TRANSCODER_D:
 134                 return "D";
 135         case TRANSCODER_EDP:
 136                 return "EDP";
 137         case TRANSCODER_DSI_A:
 138                 return "DSI A";
 139         case TRANSCODER_DSI_C:
 140                 return "DSI C";
 141         default:
 142                 return "<invalid>";
 143         }
 144 }
 145
 146 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 147 {
 148         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 149 }
 150
 151 /*
 152  * Global legacy plane identifier. Valid only for primary/sprite
 153  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 154  */
 155 enum i9xx_plane_id {
 156         PLANE_A,
 157         PLANE_B,
 158         PLANE_C,
 159 };
 160
 161 #define plane_name(p) ((p) + 'A')
 162 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 163
 164 /*
 165  * Per-pipe plane identifier.
 166  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 167  * number of planes per CRTC.  Not all platforms really have this many planes,
 168  * which means some arrays of size I915_MAX_PLANES may have unused entries
 169  * between the topmost sprite plane and the cursor plane.
 170  *
 171  * This is expected to be passed to various register macros
 172  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 173  */
 174 enum plane_id {
 175         PLANE_PRIMARY,
 176         PLANE_SPRITE0,
 177         PLANE_SPRITE1,
 178         PLANE_SPRITE2,
 179         PLANE_SPRITE3,
 180         PLANE_SPRITE4,
 181         PLANE_SPRITE5,
 182         PLANE_CURSOR,
 183
 184         I915_MAX_PLANES,
 185 };
 186
 187 #define for_each_plane_id_on_crtc(__crtc, __p) \
 188         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 189                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 190
 191 #define for_each_dbuf_slice_in_mask(__slice, __mask) \
 192         for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
 193                 for_each_if((BIT(__slice)) & (__mask))
 194
 195 #define for_each_dbuf_slice(__slice) \
 196         for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
 197
 198 enum port {
 199         PORT_NONE = -1,
 200
 201         PORT_A = 0,
 202         PORT_B,
 203         PORT_C,
 204         PORT_D,
 205         PORT_E,
 206         PORT_F,
 207         PORT_G,
 208         PORT_H,
 209         PORT_I,
 210
 211         I915_MAX_PORTS
 212 };
 213
 214 #define port_name(p) ((p) + 'A')
 215
 216 /*
 217  * Ports identifier referenced from other drivers.
 218  * Expected to remain stable over time
 219  */
 220 static inline const char *port_identifier(enum port port)
 221 {
 222         switch (port) {
 223         case PORT_A:
 224                 return "Port A";
 225         case PORT_B:
 226                 return "Port B";
 227         case PORT_C:
 228                 return "Port C";
 229         case PORT_D:
 230                 return "Port D";
 231         case PORT_E:
 232                 return "Port E";
 233         case PORT_F:
 234                 return "Port F";
 235         case PORT_G:
 236                 return "Port G";
 237         case PORT_H:
 238                 return "Port H";
 239         case PORT_I:
 240                 return "Port I";
 241         default:
 242                 return "<invalid>";
 243         }
 244 }
 245
 246 enum tc_port {
 247         TC_PORT_NONE = -1,
 248
 249         TC_PORT_1 = 0,
 250         TC_PORT_2,
 251         TC_PORT_3,
 252         TC_PORT_4,
 253         TC_PORT_5,
 254         TC_PORT_6,
 255
 256         I915_MAX_TC_PORTS
 257 };
 258
 259 enum tc_port_mode {
 260         TC_PORT_TBT_ALT,
 261         TC_PORT_DP_ALT,
 262         TC_PORT_LEGACY,
 263 };
 264
 265 enum dpio_channel {
 266         DPIO_CH0,
 267         DPIO_CH1
 268 };
 269
 270 enum dpio_phy {
 271         DPIO_PHY0,
 272         DPIO_PHY1,
 273         DPIO_PHY2,
 274 };
 275
 276 enum aux_ch {
 277         AUX_CH_A,
 278         AUX_CH_B,
 279         AUX_CH_C,
 280         AUX_CH_D,
 281         AUX_CH_E, /* ICL+ */
 282         AUX_CH_F,
 283         AUX_CH_G,
 284         AUX_CH_H,
 285         AUX_CH_I,
 286 };
 287
 288 #define aux_ch_name(a) ((a) + 'A')
 289
 290 /* Used by dp and fdi links */
 291 struct intel_link_m_n {
 292         u32 tu;
 293         u32 gmch_m;
 294         u32 gmch_n;
 295         u32 link_m;
 296         u32 link_n;
 297 };
 298
 299 enum phy {
 300         PHY_NONE = -1,
 301
 302         PHY_A = 0,
 303         PHY_B,
 304         PHY_C,
 305         PHY_D,
 306         PHY_E,
 307         PHY_F,
 308         PHY_G,
 309         PHY_H,
 310         PHY_I,
 311
 312         I915_MAX_PHYS
 313 };
 314
 315 #define phy_name(a) ((a) + 'A')
 316
 317 enum phy_fia {
 318         FIA1,
 319         FIA2,
 320         FIA3,
 321 };
 322
 323 #define for_each_pipe(__dev_priv, __p) \
 324         for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
 325                 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
 326
 327 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 328         for_each_pipe(__dev_priv, __p) \
 329                 for_each_if((__mask) & BIT(__p))
 330
 331 #define for_each_cpu_transcoder(__dev_priv, __t) \
 332         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 333                 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
 334
 335 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 336         for_each_cpu_transcoder(__dev_priv, __t) \
 337                 for_each_if ((__mask) & BIT(__t))
 338
 339 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 340         for ((__p) = 0;                                                 \
 341              (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;       \
 342              (__p)++)
 343
 344 #define for_each_sprite(__dev_priv, __p, __s)                           \
 345         for ((__s) = 0;                                                 \
 346              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 347              (__s)++)
 348
 349 #define for_each_port(__port) \
 350         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
 351
 352 #define for_each_port_masked(__port, __ports_mask)                      \
 353         for_each_port(__port)                                           \
 354                 for_each_if((__ports_mask) & BIT(__port))
 355
 356 #define for_each_phy_masked(__phy, __phys_mask) \
 357         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 358                 for_each_if((__phys_mask) & BIT(__phy))
 359
 360 #define for_each_crtc(dev, crtc) \
 361         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 362
 363 #define for_each_intel_plane(dev, intel_plane) \
 364         list_for_each_entry(intel_plane,                        \
 365                             &(dev)->mode_config.plane_list,     \
 366                             base.head)
 367
 368 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 369         list_for_each_entry(intel_plane,                                \
 370                             &(dev)->mode_config.plane_list,             \
 371                             base.head)                                  \
 372                 for_each_if((plane_mask) &                              \
 373                             drm_plane_mask(&intel_plane->base))
 374
 375 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 376         list_for_each_entry(intel_plane,                                \
 377                             &(dev)->mode_config.plane_list,             \
 378                             base.head)                                  \
 379                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 380
 381 #define for_each_intel_crtc(dev, intel_crtc)                            \
 382         list_for_each_entry(intel_crtc,                                 \
 383                             &(dev)->mode_config.crtc_list,              \
 384                             base.head)
 385
 386 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 387         list_for_each_entry(intel_crtc,                                 \
 388                             &(dev)->mode_config.crtc_list,              \
 389                             base.head)                                  \
 390                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 391
 392 #define for_each_intel_encoder(dev, intel_encoder)              \
 393         list_for_each_entry(intel_encoder,                      \
 394                             &(dev)->mode_config.encoder_list,   \
 395                             base.head)
 396
 397 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
 398         list_for_each_entry(intel_encoder,                              \
 399                             &(dev)->mode_config.encoder_list,           \
 400                             base.head)                                  \
 401                 for_each_if((encoder_mask) &                            \
 402                             drm_encoder_mask(&intel_encoder->base))
 403
 404 #define for_each_intel_dp(dev, intel_encoder)                   \
 405         for_each_intel_encoder(dev, intel_encoder)              \
 406                 for_each_if(intel_encoder_is_dp(intel_encoder))
 407
 408 #define for_each_intel_connector_iter(intel_connector, iter) \
 409         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 410
 411 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 412         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 413                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 414
 415 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 416         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 417                 for_each_if((intel_connector)->base.encoder == (__encoder))
 418
 419 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 420         for ((__i) = 0; \
 421              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 422                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 423                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 424              (__i)++) \
 425                 for_each_if(plane)
 426
 427 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 428         for ((__i) = 0; \
 429              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 430                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 431                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 432              (__i)++) \
 433                 for_each_if(plane)
 434
 435 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 436         for ((__i) = 0; \
 437              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 438                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 439                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 440              (__i)++) \
 441                 for_each_if(crtc)
 442
 443 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 444         for ((__i) = 0; \
 445              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 446                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 447                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 448                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 449              (__i)++) \
 450                 for_each_if(plane)
 451
 452 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 453         for ((__i) = 0; \
 454              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 455                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 456                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 457                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 458              (__i)++) \
 459                 for_each_if(crtc)
 460
 461 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 462         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 463              (__i) >= 0  && \
 464              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 465               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 466               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 467              (__i)--) \
 468                 for_each_if(crtc)
 469
 470 #define intel_atomic_crtc_state_for_each_plane_state( \
 471                   plane, plane_state, \
 472                   crtc_state) \
 473         for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
 474                                 ((crtc_state)->uapi.plane_mask)) \
 475                 for_each_if ((plane_state = \
 476                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 477
 478 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
 479         for ((__i) = 0; \
 480              (__i) < (__state)->base.num_connector; \
 481              (__i)++) \
 482                 for_each_if ((__state)->base.connectors[__i].ptr && \
 483                              ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 484                              (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 485
 486 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 487                            u8 active_pipes);
 488 void intel_link_compute_m_n(u16 bpp, int nlanes,
 489                             int pixel_clock, int link_clock,
 490                             struct intel_link_m_n *m_n,
 491                             bool constant_n, bool fec_enable);
 492 bool is_ccs_modifier(u64 modifier);
 493 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
 494 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 495 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 496                               u32 pixel_format, u64 modifier);
 497 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 498 enum drm_mode_status
 499 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 500                                 const struct drm_display_mode *mode);
 501 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 502 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 503
 504 void intel_plane_destroy(struct drm_plane *plane);
 505 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
 506 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
 507 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 508 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 509 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
 510 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 511 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 512                       const char *name, u32 reg, int ref_freq);
 513 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 514                            const char *name, u32 reg);
 515 void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
 516 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 517 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
 518 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 519 unsigned int intel_fb_xy_to_linear(int x, int y,
 520                                    const struct intel_plane_state *state,
 521                                    int plane);
 522 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 523                                    int color_plane, unsigned int height);
 524 void intel_add_fb_offsets(int *x, int *y,
 525                           const struct intel_plane_state *state, int plane);
 526 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 527 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 528 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 529 int intel_display_suspend(struct drm_device *dev);
 530 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 531 void intel_encoder_destroy(struct drm_encoder *encoder);
 532 struct drm_display_mode *
 533 intel_encoder_current_mode(struct intel_encoder *encoder);
 534 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 535 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 536 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 537                               enum port port);
 538 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 539                                       struct drm_file *file_priv);
 540 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
 541 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
 542 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
 543
 544 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
 545 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 546                          struct intel_digital_port *dig_port,
 547                          unsigned int expected_mask);
 548 int intel_get_load_detect_pipe(struct drm_connector *connector,
 549                                struct intel_load_detect_pipe *old,
 550                                struct drm_modeset_acquire_ctx *ctx);
 551 void intel_release_load_detect_pipe(struct drm_connector *connector,
 552                                     struct intel_load_detect_pipe *old,
 553                                     struct drm_modeset_acquire_ctx *ctx);
 554 struct i915_vma *
 555 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 556                            const struct i915_ggtt_view *view,
 557                            bool uses_fence,
 558                            unsigned long *out_flags);
 559 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 560 struct drm_framebuffer *
 561 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 562                          struct drm_mode_fb_cmd2 *mode_cmd);
 563 int intel_prepare_plane_fb(struct drm_plane *plane,
 564                            struct drm_plane_state *new_state);
 565 void intel_cleanup_plane_fb(struct drm_plane *plane,
 566                             struct drm_plane_state *old_state);
 567
 568 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 569                                     enum pipe pipe);
 570
 571 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
 572                      const struct dpll *dpll);
 573 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
 574 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
 575 bool intel_fuzzy_clock_check(int clock1, int clock2);
 576
 577 void intel_prepare_reset(struct drm_i915_private *dev_priv);
 578 void intel_finish_reset(struct drm_i915_private *dev_priv);
 579 void intel_dp_get_m_n(struct intel_crtc *crtc,
 580                       struct intel_crtc_state *pipe_config);
 581 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 582                       enum link_m_n_set m_n);
 583 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 584 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 585                         struct dpll *best_clock);
 586 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 587
 588 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 589 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
 590 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 591 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 592 enum intel_display_power_domain
 593 intel_aux_power_domain(struct intel_digital_port *dig_port);
 594 enum intel_display_power_domain
 595 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
 596 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 597                                  struct intel_crtc_state *pipe_config);
 598 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 599                                   struct intel_crtc_state *crtc_state);
 600
 601 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
 602 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
 603 u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set);
 604 void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
 605                              int id, int set, enum drm_scaling_filter filter);
 606 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 607 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 608                         const struct intel_plane_state *plane_state);
 609 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
 610 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 611                   const struct intel_plane_state *plane_state);
 612 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
 613 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 614                      int plane);
 615 int skl_check_plane_surface(struct intel_plane_state *plane_state);
 616 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
 617 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 618 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
 619                                    u32 pixel_format, u64 modifier,
 620                                    unsigned int rotation);
 621 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
 622 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
 623
 624 struct intel_display_error_state *
 625 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
 626 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 627                                      struct intel_display_error_state *error);
 628
 629 bool
 630 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
 631                                     uint64_t modifier);
 632
 633 /* modesetting */
 634 void intel_modeset_init_hw(struct drm_i915_private *i915);
 635 int intel_modeset_init_noirq(struct drm_i915_private *i915);
 636 int intel_modeset_init_nogem(struct drm_i915_private *i915);
 637 int intel_modeset_init(struct drm_i915_private *i915);
 638 void intel_modeset_driver_remove(struct drm_i915_private *i915);
 639 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
 640 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
 641 void intel_display_resume(struct drm_device *dev);
 642 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 643
 644 /* modesetting asserts */
 645 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 646                            enum pipe pipe);
 647 void assert_pll(struct drm_i915_private *dev_priv,
 648                 enum pipe pipe, bool state);
 649 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 650 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 651 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
 652 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 653 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 654 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 655                        enum pipe pipe, bool state);
 656 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 657 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 658 void assert_pipe(struct drm_i915_private *dev_priv,
 659                  enum transcoder cpu_transcoder, bool state);
 660 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
 661 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
 662
 663 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 664  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 665  * which may not necessarily be a user visible problem.  This will either
 666  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 667  * enable distros and users to tailor their preferred amount of i915 abrt
 668  * spam.
 669  */
 670 #define I915_STATE_WARN(condition, format...) ({                        \
 671         int __ret_warn_on = !!(condition);                              \
 672         if (unlikely(__ret_warn_on))                                    \
 673                 if (!WARN(i915_modparams.verbose_state_checks, format)) \
 674                         DRM_ERROR(format);                              \
 675         unlikely(__ret_warn_on);                                        \
 676 })
 677
 678 #define I915_STATE_WARN_ON(x)                                           \
 679         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 680
 681 #endif