drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 #include "i915_reg_defs.h"
  31 #include "intel_display_limits.h"
  32
  33 enum drm_scaling_filter;
  34 struct dpll;
  35 struct drm_atomic_state;
  36 struct drm_connector;
  37 struct drm_device;
  38 struct drm_display_mode;
  39 struct drm_encoder;
  40 struct drm_file;
  41 struct drm_format_info;
  42 struct drm_framebuffer;
  43 struct drm_i915_gem_object;
  44 struct drm_i915_private;
  45 struct drm_mode_fb_cmd2;
  46 struct drm_modeset_acquire_ctx;
  47 struct drm_plane;
  48 struct drm_plane_state;
  49 struct i915_address_space;
  50 struct i915_gtt_view;
  51 struct intel_atomic_state;
  52 struct intel_crtc;
  53 struct intel_crtc_state;
  54 struct intel_digital_port;
  55 struct intel_dp;
  56 struct intel_encoder;
  57 struct intel_initial_plane_config;
  58 struct intel_link_m_n;
  59 struct intel_plane;
  60 struct intel_plane_state;
  61 struct intel_power_domain_mask;
  62 struct intel_remapped_info;
  63 struct intel_rotation_info;
  64 struct pci_dev;
  65 struct work_struct;
  66
  67
  68 #define pipe_name(p) ((p) + 'A')
  69
  70 static inline const char *transcoder_name(enum transcoder transcoder)
  71 {
  72         switch (transcoder) {
  73         case TRANSCODER_A:
  74                 return "A";
  75         case TRANSCODER_B:
  76                 return "B";
  77         case TRANSCODER_C:
  78                 return "C";
  79         case TRANSCODER_D:
  80                 return "D";
  81         case TRANSCODER_EDP:
  82                 return "EDP";
  83         case TRANSCODER_DSI_A:
  84                 return "DSI A";
  85         case TRANSCODER_DSI_C:
  86                 return "DSI C";
  87         default:
  88                 return "<invalid>";
  89         }
  90 }
  91
  92 static inline bool transcoder_is_dsi(enum transcoder transcoder)
  93 {
  94         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
  95 }
  96
  97 /*
  98  * Global legacy plane identifier. Valid only for primary/sprite
  99  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 100  */
 101 enum i9xx_plane_id {
 102         PLANE_A,
 103         PLANE_B,
 104         PLANE_C,
 105 };
 106
 107 #define plane_name(p) ((p) + 'A')
 108 #define sprite_name(p, s) ((p) * DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 109
 110 #define for_each_plane_id_on_crtc(__crtc, __p) \
 111         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 112                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 113
 114 #define for_each_dbuf_slice(__dev_priv, __slice) \
 115         for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
 116                 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
 117
 118 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
 119         for_each_dbuf_slice((__dev_priv), (__slice)) \
 120                 for_each_if((__mask) & BIT(__slice))
 121
 122 #define port_name(p) ((p) + 'A')
 123
 124 /*
 125  * Ports identifier referenced from other drivers.
 126  * Expected to remain stable over time
 127  */
 128 static inline const char *port_identifier(enum port port)
 129 {
 130         switch (port) {
 131         case PORT_A:
 132                 return "Port A";
 133         case PORT_B:
 134                 return "Port B";
 135         case PORT_C:
 136                 return "Port C";
 137         case PORT_D:
 138                 return "Port D";
 139         case PORT_E:
 140                 return "Port E";
 141         case PORT_F:
 142                 return "Port F";
 143         case PORT_G:
 144                 return "Port G";
 145         case PORT_H:
 146                 return "Port H";
 147         case PORT_I:
 148                 return "Port I";
 149         default:
 150                 return "<invalid>";
 151         }
 152 }
 153
 154 enum tc_port {
 155         TC_PORT_NONE = -1,
 156
 157         TC_PORT_1 = 0,
 158         TC_PORT_2,
 159         TC_PORT_3,
 160         TC_PORT_4,
 161         TC_PORT_5,
 162         TC_PORT_6,
 163
 164         I915_MAX_TC_PORTS
 165 };
 166
 167 enum aux_ch {
 168         AUX_CH_NONE = -1,
 169
 170         AUX_CH_A,
 171         AUX_CH_B,
 172         AUX_CH_C,
 173         AUX_CH_D,
 174         AUX_CH_E, /* ICL+ */
 175         AUX_CH_F,
 176         AUX_CH_G,
 177         AUX_CH_H,
 178         AUX_CH_I,
 179
 180         /* tgl+ */
 181         AUX_CH_USBC1 = AUX_CH_D,
 182         AUX_CH_USBC2,
 183         AUX_CH_USBC3,
 184         AUX_CH_USBC4,
 185         AUX_CH_USBC5,
 186         AUX_CH_USBC6,
 187
 188         /* XE_LPD repositions D/E offsets and bitfields */
 189         AUX_CH_D_XELPD = AUX_CH_USBC5,
 190         AUX_CH_E_XELPD,
 191 };
 192
 193 enum phy {
 194         PHY_NONE = -1,
 195
 196         PHY_A = 0,
 197         PHY_B,
 198         PHY_C,
 199         PHY_D,
 200         PHY_E,
 201         PHY_F,
 202         PHY_G,
 203         PHY_H,
 204         PHY_I,
 205
 206         I915_MAX_PHYS
 207 };
 208
 209 #define phy_name(a) ((a) + 'A')
 210
 211 enum phy_fia {
 212         FIA1,
 213         FIA2,
 214         FIA3,
 215 };
 216
 217 #define for_each_hpd_pin(__pin) \
 218         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 219
 220 #define for_each_pipe(__dev_priv, __p) \
 221         for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
 222                 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
 223
 224 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 225         for_each_pipe(__dev_priv, __p) \
 226                 for_each_if((__mask) & BIT(__p))
 227
 228 #define for_each_cpu_transcoder(__dev_priv, __t) \
 229         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 230                 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
 231
 232 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 233         for_each_cpu_transcoder(__dev_priv, __t) \
 234                 for_each_if ((__mask) & BIT(__t))
 235
 236 #define for_each_sprite(__dev_priv, __p, __s)                           \
 237         for ((__s) = 0;                                                 \
 238              (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 239              (__s)++)
 240
 241 #define for_each_port(__port) \
 242         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
 243
 244 #define for_each_port_masked(__port, __ports_mask)                      \
 245         for_each_port(__port)                                           \
 246                 for_each_if((__ports_mask) & BIT(__port))
 247
 248 #define for_each_phy_masked(__phy, __phys_mask) \
 249         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 250                 for_each_if((__phys_mask) & BIT(__phy))
 251
 252 #define for_each_crtc(dev, crtc) \
 253         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 254
 255 #define for_each_intel_plane(dev, intel_plane) \
 256         list_for_each_entry(intel_plane,                        \
 257                             &(dev)->mode_config.plane_list,     \
 258                             base.head)
 259
 260 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 261         list_for_each_entry(intel_plane,                                \
 262                             &(dev)->mode_config.plane_list,             \
 263                             base.head)                                  \
 264                 for_each_if((plane_mask) &                              \
 265                             drm_plane_mask(&intel_plane->base))
 266
 267 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 268         list_for_each_entry(intel_plane,                                \
 269                             &(dev)->mode_config.plane_list,             \
 270                             base.head)                                  \
 271                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 272
 273 #define for_each_intel_crtc(dev, intel_crtc)                            \
 274         list_for_each_entry(intel_crtc,                                 \
 275                             &(dev)->mode_config.crtc_list,              \
 276                             base.head)
 277
 278 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask)    \
 279         list_for_each_entry(intel_crtc,                                 \
 280                             &(dev)->mode_config.crtc_list,              \
 281                             base.head)                                  \
 282                 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
 283
 284 #define for_each_intel_encoder(dev, intel_encoder)              \
 285         list_for_each_entry(intel_encoder,                      \
 286                             &(dev)->mode_config.encoder_list,   \
 287                             base.head)
 288
 289 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
 290         list_for_each_entry(intel_encoder,                              \
 291                             &(dev)->mode_config.encoder_list,           \
 292                             base.head)                                  \
 293                 for_each_if((encoder_mask) &                            \
 294                             drm_encoder_mask(&intel_encoder->base))
 295
 296 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
 297         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 298                 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
 299                             intel_encoder_can_psr(intel_encoder))
 300
 301 #define for_each_intel_dp(dev, intel_encoder)                   \
 302         for_each_intel_encoder(dev, intel_encoder)              \
 303                 for_each_if(intel_encoder_is_dp(intel_encoder))
 304
 305 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
 306         for_each_intel_encoder((dev), (intel_encoder)) \
 307                 for_each_if(intel_encoder_can_psr(intel_encoder))
 308
 309 #define for_each_intel_connector_iter(intel_connector, iter) \
 310         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 311
 312 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 313         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 314                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 315
 316 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 317         for ((__i) = 0; \
 318              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 319                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 320                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 321              (__i)++) \
 322                 for_each_if(plane)
 323
 324 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
 325         for ((__i) = 0; \
 326              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 327                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 328                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
 329              (__i)++) \
 330                 for_each_if(crtc)
 331
 332 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 333         for ((__i) = 0; \
 334              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 335                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 336                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 337              (__i)++) \
 338                 for_each_if(plane)
 339
 340 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 341         for ((__i) = 0; \
 342              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 343                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 344                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 345              (__i)++) \
 346                 for_each_if(crtc)
 347
 348 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 349         for ((__i) = 0; \
 350              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 351                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 352                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 353                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 354              (__i)++) \
 355                 for_each_if(plane)
 356
 357 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 358         for ((__i) = 0; \
 359              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 360                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 361                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 362                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 363              (__i)++) \
 364                 for_each_if(crtc)
 365
 366 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 367         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 368              (__i) >= 0  && \
 369              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 370               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 371               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 372              (__i)--) \
 373                 for_each_if(crtc)
 374
 375 #define intel_atomic_crtc_state_for_each_plane_state( \
 376                   plane, plane_state, \
 377                   crtc_state) \
 378         for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
 379                                 ((crtc_state)->uapi.plane_mask)) \
 380                 for_each_if ((plane_state = \
 381                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 382
 383 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
 384         for ((__i) = 0; \
 385              (__i) < (__state)->base.num_connector; \
 386              (__i)++) \
 387                 for_each_if ((__state)->base.connectors[__i].ptr && \
 388                              ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 389                              (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 390
 391 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
 392 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
 393                                      struct intel_crtc *crtc);
 394 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 395                            u8 active_pipes);
 396 void intel_link_compute_m_n(u16 bpp, int nlanes,
 397                             int pixel_clock, int link_clock,
 398                             struct intel_link_m_n *m_n,
 399                             bool fec_enable);
 400 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 401                               u32 pixel_format, u64 modifier);
 402 enum drm_mode_status
 403 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 404                                 const struct drm_display_mode *mode,
 405                                 bool bigjoiner);
 406 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 407 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 408 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
 409 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
 410 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 411 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 412 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
 413 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
 414 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 415                                const struct intel_crtc_state *pipe_config,
 416                                bool fastset);
 417
 418 void intel_plane_destroy(struct drm_plane *plane);
 419 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 420 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 421 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
 422 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
 423 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 424 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 425 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 426 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 427                       const char *name, u32 reg, int ref_freq);
 428 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 429                            const char *name, u32 reg);
 430 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 431 unsigned int intel_fb_xy_to_linear(int x, int y,
 432                                    const struct intel_plane_state *state,
 433                                    int plane);
 434 void intel_add_fb_offsets(int *x, int *y,
 435                           const struct intel_plane_state *state, int plane);
 436 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 437 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 438 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 439 void intel_encoder_destroy(struct drm_encoder *encoder);
 440 struct drm_display_mode *
 441 intel_encoder_current_mode(struct intel_encoder *encoder);
 442 void intel_encoder_get_config(struct intel_encoder *encoder,
 443                               struct intel_crtc_state *crtc_state);
 444 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 445 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 446 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
 447 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 448                               enum port port);
 449 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 450                                       struct drm_file *file_priv);
 451
 452 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
 453 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 454                          struct intel_digital_port *dig_port,
 455                          unsigned int expected_mask);
 456 struct drm_framebuffer *
 457 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 458                          struct drm_mode_fb_cmd2 *mode_cmd);
 459
 460 bool intel_fuzzy_clock_check(int clock1, int clock2);
 461
 462 void intel_zero_m_n(struct intel_link_m_n *m_n);
 463 void intel_set_m_n(struct drm_i915_private *i915,
 464                    const struct intel_link_m_n *m_n,
 465                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 466                    i915_reg_t link_m_reg, i915_reg_t link_n_reg);
 467 void intel_get_m_n(struct drm_i915_private *i915,
 468                    struct intel_link_m_n *m_n,
 469                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 470                    i915_reg_t link_m_reg, i915_reg_t link_n_reg);
 471 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
 472                                     enum transcoder transcoder);
 473 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 474                                     enum transcoder cpu_transcoder,
 475                                     const struct intel_link_m_n *m_n);
 476 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 477                                     enum transcoder cpu_transcoder,
 478                                     const struct intel_link_m_n *m_n);
 479 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 480                                     enum transcoder cpu_transcoder,
 481                                     struct intel_link_m_n *m_n);
 482 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 483                                     enum transcoder cpu_transcoder,
 484                                     struct intel_link_m_n *m_n);
 485 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 486                          struct intel_crtc_state *pipe_config);
 487 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 488 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 489 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 490 enum intel_display_power_domain
 491 intel_aux_power_domain(struct intel_digital_port *dig_port);
 492 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 493                                   struct intel_crtc_state *crtc_state);
 494 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 495
 496 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
 497 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
 498
 499 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
 500
 501 struct intel_encoder *
 502 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 503                            const struct intel_crtc_state *crtc_state);
 504 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 505                                   struct intel_plane *plane);
 506 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 507                              struct intel_plane_state *plane_state,
 508                              bool visible);
 509 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
 510
 511 void intel_update_watermarks(struct drm_i915_private *i915);
 512
 513 /* modesetting */
 514 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
 515                                       const char *reason, u8 pipe_mask);
 516 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
 517                                  const char *reason);
 518 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
 519                                           struct intel_power_domain_mask *old_domains);
 520 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
 521                                           struct intel_power_domain_mask *domains);
 522
 523 /* interface for intel_display_driver.c */
 524 void intel_setup_outputs(struct drm_i915_private *i915);
 525 int intel_initial_commit(struct drm_device *dev);
 526 void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
 527 void intel_update_czclk(struct drm_i915_private *i915);
 528 void intel_atomic_helper_free_state_worker(struct work_struct *work);
 529 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
 530                                       const struct drm_display_mode *mode);
 531 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
 532                         bool nonblock);
 533
 534 void intel_hpd_poll_fini(struct drm_i915_private *i915);
 535
 536 /* modesetting asserts */
 537 void assert_transcoder(struct drm_i915_private *dev_priv,
 538                        enum transcoder cpu_transcoder, bool state);
 539 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
 540 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
 541
 542 bool assert_port_valid(struct drm_i915_private *i915, enum port port);
 543
 544 /*
 545  * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity
 546  * checks to check for unexpected conditions which may not necessarily be a user
 547  * visible problem. This will either WARN() or DRM_ERROR() depending on the
 548  * verbose_state_checks module param, to enable distros and users to tailor
 549  * their preferred amount of i915 abrt spam.
 550  */
 551 #define I915_STATE_WARN(__i915, condition, format...) ({                \
 552         struct drm_device *drm = &(__i915)->drm;                        \
 553         int __ret_warn_on = !!(condition);                              \
 554         if (unlikely(__ret_warn_on))                                    \
 555                 if (!drm_WARN(drm, i915_modparams.verbose_state_checks, format)) \
 556                         drm_err(drm, format);                           \
 557         unlikely(__ret_warn_on);                                        \
 558 })
 559
 560 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
 561
 562 #endif