2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812 u32 mode_flags = crtc->mode_flags;
1815 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
1816 * have updated at the beginning of TE, if we want to use
1817 * the hw counter, then we would find it updated in only
1818 * the next TE, hence switching to sw counter.
1820 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
1824 * On i965gm the hardware frame counter reads
1825 * zero when the TV encoder is enabled :(
1827 if (IS_I965GM(dev_priv) &&
1828 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1831 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1832 return 0xffffffff; /* full 32 bit counter */
1833 else if (INTEL_GEN(dev_priv) >= 3)
1834 return 0xffffff; /* only 24 bits of frame count */
1836 return 0; /* Gen2 doesn't have a hardware frame counter */
1839 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1843 assert_vblank_disabled(&crtc->base);
1844 drm_crtc_set_max_vblank_count(&crtc->base,
1845 intel_crtc_max_vblank_count(crtc_state));
1846 drm_crtc_vblank_on(&crtc->base);
1849 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1853 drm_crtc_vblank_off(&crtc->base);
1854 assert_vblank_disabled(&crtc->base);
1857 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1862 enum pipe pipe = crtc->pipe;
1866 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1868 assert_planes_disabled(crtc);
1871 * A pipe without a PLL won't actually be able to drive bits from
1872 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1875 if (HAS_GMCH(dev_priv)) {
1876 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1877 assert_dsi_pll_enabled(dev_priv);
1879 assert_pll_enabled(dev_priv, pipe);
1881 if (new_crtc_state->has_pch_encoder) {
1882 /* if driving the PCH, we need FDI enabled */
1883 assert_fdi_rx_pll_enabled(dev_priv,
1884 intel_crtc_pch_transcoder(crtc));
1885 assert_fdi_tx_pll_enabled(dev_priv,
1886 (enum pipe) cpu_transcoder);
1888 /* FIXME: assert CPU port conditions for SNB+ */
1891 trace_intel_pipe_enable(crtc);
1893 reg = PIPECONF(cpu_transcoder);
1894 val = intel_de_read(dev_priv, reg);
1895 if (val & PIPECONF_ENABLE) {
1896 /* we keep both pipes enabled on 830 */
1897 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1901 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1902 intel_de_posting_read(dev_priv, reg);
1905 * Until the pipe starts PIPEDSL reads will return a stale value,
1906 * which causes an apparent vblank timestamp jump when PIPEDSL
1907 * resets to its proper value. That also messes up the frame count
1908 * when it's derived from the timestamps. So let's wait for the
1909 * pipe to start properly before we call drm_crtc_vblank_on()
1911 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1912 intel_wait_for_pipe_scanline_moving(crtc);
1915 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1919 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1920 enum pipe pipe = crtc->pipe;
1924 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1927 * Make sure planes won't keep trying to pump pixels to us,
1928 * or we might hang the display.
1930 assert_planes_disabled(crtc);
1932 trace_intel_pipe_disable(crtc);
1934 reg = PIPECONF(cpu_transcoder);
1935 val = intel_de_read(dev_priv, reg);
1936 if ((val & PIPECONF_ENABLE) == 0)
1940 * Double wide has implications for planes
1941 * so best keep it disabled when not needed.
1943 if (old_crtc_state->double_wide)
1944 val &= ~PIPECONF_DOUBLE_WIDE;
1946 /* Don't disable pipe or pipe PLLs if needed */
1947 if (!IS_I830(dev_priv))
1948 val &= ~PIPECONF_ENABLE;
1950 intel_de_write(dev_priv, reg, val);
1951 if ((val & PIPECONF_ENABLE) == 0)
1952 intel_wait_for_pipe_off(old_crtc_state);
1955 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1960 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 if (!is_ccs_modifier(fb->modifier))
1965 return plane >= fb->format->num_planes / 2;
1968 static bool is_gen12_ccs_modifier(u64 modifier)
1970 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1971 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1975 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1977 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1980 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1982 if (is_ccs_modifier(fb->modifier))
1983 return is_ccs_plane(fb, plane);
1988 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1990 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1991 (main_plane && main_plane >= fb->format->num_planes / 2));
1993 return fb->format->num_planes / 2 + main_plane;
1996 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1998 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1999 ccs_plane < fb->format->num_planes / 2);
2001 return ccs_plane - fb->format->num_planes / 2;
2004 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
2006 struct drm_i915_private *i915 = to_i915(fb->dev);
2008 if (is_ccs_modifier(fb->modifier))
2009 return main_to_ccs_plane(fb, main_plane);
2010 else if (INTEL_GEN(i915) < 11 &&
2011 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
2018 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2021 return info->is_yuv &&
2022 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2025 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2028 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2033 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2035 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 unsigned int cpp = fb->format->cpp[color_plane];
2038 switch (fb->modifier) {
2039 case DRM_FORMAT_MOD_LINEAR:
2040 return intel_tile_size(dev_priv);
2041 case I915_FORMAT_MOD_X_TILED:
2042 if (IS_GEN(dev_priv, 2))
2046 case I915_FORMAT_MOD_Y_TILED_CCS:
2047 if (is_ccs_plane(fb, color_plane))
2050 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2051 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2052 if (is_ccs_plane(fb, color_plane))
2055 case I915_FORMAT_MOD_Y_TILED:
2056 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 if (is_ccs_plane(fb, color_plane))
2064 case I915_FORMAT_MOD_Yf_TILED:
2080 MISSING_CASE(fb->modifier);
2086 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2088 if (is_gen12_ccs_plane(fb, color_plane))
2091 return intel_tile_size(to_i915(fb->dev)) /
2092 intel_tile_width_bytes(fb, color_plane);
2095 /* Return the tile dimensions in pixel units */
2096 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2097 unsigned int *tile_width,
2098 unsigned int *tile_height)
2100 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2101 unsigned int cpp = fb->format->cpp[color_plane];
2103 *tile_width = tile_width_bytes / cpp;
2104 *tile_height = intel_tile_height(fb, color_plane);
2107 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2110 unsigned int tile_width, tile_height;
2112 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2114 return fb->pitches[color_plane] * tile_height;
2118 intel_fb_align_height(const struct drm_framebuffer *fb,
2119 int color_plane, unsigned int height)
2121 unsigned int tile_height = intel_tile_height(fb, color_plane);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2137 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2139 unsigned int size = 0;
2142 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2143 size += rem_info->plane[i].width * rem_info->plane[i].height;
2149 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2150 const struct drm_framebuffer *fb,
2151 unsigned int rotation)
2153 view->type = I915_GGTT_VIEW_NORMAL;
2154 if (drm_rotation_90_or_270(rotation)) {
2155 view->type = I915_GGTT_VIEW_ROTATED;
2156 view->rotated = to_intel_framebuffer(fb)->rot_info;
2160 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2162 if (IS_I830(dev_priv))
2164 else if (IS_I85X(dev_priv))
2166 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2172 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2174 if (INTEL_GEN(dev_priv) >= 9)
2176 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2177 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2179 else if (INTEL_GEN(dev_priv) >= 4)
2185 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2188 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2190 /* AUX_DIST needs only 4K alignment */
2191 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2192 is_ccs_plane(fb, color_plane))
2195 switch (fb->modifier) {
2196 case DRM_FORMAT_MOD_LINEAR:
2197 return intel_linear_alignment(dev_priv);
2198 case I915_FORMAT_MOD_X_TILED:
2199 if (INTEL_GEN(dev_priv) >= 9)
2202 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2203 if (is_semiplanar_uv_plane(fb, color_plane))
2204 return intel_tile_row_size(fb, color_plane);
2206 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2208 case I915_FORMAT_MOD_Y_TILED_CCS:
2209 case I915_FORMAT_MOD_Yf_TILED_CCS:
2210 case I915_FORMAT_MOD_Y_TILED:
2211 if (INTEL_GEN(dev_priv) >= 12 &&
2212 is_semiplanar_uv_plane(fb, color_plane))
2213 return intel_tile_row_size(fb, color_plane);
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2218 MISSING_CASE(fb->modifier);
2223 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2226 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2228 return INTEL_GEN(dev_priv) < 4 ||
2230 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2234 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2235 const struct i915_ggtt_view *view,
2237 unsigned long *out_flags)
2239 struct drm_device *dev = fb->dev;
2240 struct drm_i915_private *dev_priv = to_i915(dev);
2241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2242 intel_wakeref_t wakeref;
2243 struct i915_vma *vma;
2244 unsigned int pinctl;
2247 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2248 return ERR_PTR(-EINVAL);
2250 alignment = intel_surf_alignment(fb, 0);
2251 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2252 return ERR_PTR(-EINVAL);
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2259 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2269 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2271 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2274 * Valleyview is definitely limited to scanning out the first
2275 * 512MiB. Lets presume this behaviour was inherited from the
2276 * g4x display engine and that all earlier gen are similarly
2277 * limited. Testing suggests that it is a little more
2278 * complicated than this. For example, Cherryview appears quite
2279 * happy to scanout from anywhere within its global aperture.
2282 if (HAS_GMCH(dev_priv))
2283 pinctl |= PIN_MAPPABLE;
2285 vma = i915_gem_object_pin_to_display_plane(obj,
2286 alignment, view, pinctl);
2290 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2294 * Install a fence for tiled scan-out. Pre-i965 always needs a
2295 * fence, whereas 965+ only requires a fence if using
2296 * framebuffer compression. For simplicity, we always, when
2297 * possible, install a fence as the cost is not that onerous.
2299 * If we fail to fence the tiled scanout, then either the
2300 * modeset will reject the change (which is highly unlikely as
2301 * the affected systems, all but one, do not have unmappable
2302 * space) or we will not be able to enable full powersaving
2303 * techniques (also likely not to apply due to various limits
2304 * FBC and the like impose on the size of the buffer, which
2305 * presumably we violated anyway with this unmappable buffer).
2306 * Anyway, it is presumably better to stumble onwards with
2307 * something and try to run the system in a "less than optimal"
2308 * mode that matches the user configuration.
2310 ret = i915_vma_pin_fence(vma);
2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2312 i915_gem_object_unpin_from_display_plane(vma);
2317 if (ret == 0 && vma->fence)
2318 *out_flags |= PLANE_HAS_FENCE;
2323 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2324 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2330 i915_gem_object_lock(vma->obj, NULL);
2331 if (flags & PLANE_HAS_FENCE)
2332 i915_vma_unpin_fence(vma);
2333 i915_gem_object_unpin_from_display_plane(vma);
2334 i915_gem_object_unlock(vma->obj);
2339 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2340 unsigned int rotation)
2342 if (drm_rotation_90_or_270(rotation))
2343 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2345 return fb->pitches[color_plane];
2349 * Convert the x/y offsets into a linear offset.
2350 * Only valid with 0/180 degree rotation, which is fine since linear
2351 * offset is only used with linear buffers on pre-hsw and tiled buffers
2352 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2354 u32 intel_fb_xy_to_linear(int x, int y,
2355 const struct intel_plane_state *state,
2358 const struct drm_framebuffer *fb = state->hw.fb;
2359 unsigned int cpp = fb->format->cpp[color_plane];
2360 unsigned int pitch = state->color_plane[color_plane].stride;
2362 return y * pitch + x * cpp;
2366 * Add the x/y offsets derived from fb->offsets[] to the user
2367 * specified plane src x/y offsets. The resulting x/y offsets
2368 * specify the start of scanout from the beginning of the gtt mapping.
2370 void intel_add_fb_offsets(int *x, int *y,
2371 const struct intel_plane_state *state,
2375 *x += state->color_plane[color_plane].x;
2376 *y += state->color_plane[color_plane].y;
2379 static u32 intel_adjust_tile_offset(int *x, int *y,
2380 unsigned int tile_width,
2381 unsigned int tile_height,
2382 unsigned int tile_size,
2383 unsigned int pitch_tiles,
2387 unsigned int pitch_pixels = pitch_tiles * tile_width;
2390 WARN_ON(old_offset & (tile_size - 1));
2391 WARN_ON(new_offset & (tile_size - 1));
2392 WARN_ON(new_offset > old_offset);
2394 tiles = (old_offset - new_offset) / tile_size;
2396 *y += tiles / pitch_tiles * tile_height;
2397 *x += tiles % pitch_tiles * tile_width;
2399 /* minimize x in case it got needlessly big */
2400 *y += *x / pitch_pixels * tile_height;
2406 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2408 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2409 is_gen12_ccs_plane(fb, color_plane);
2412 static u32 intel_adjust_aligned_offset(int *x, int *y,
2413 const struct drm_framebuffer *fb,
2415 unsigned int rotation,
2417 u32 old_offset, u32 new_offset)
2419 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2420 unsigned int cpp = fb->format->cpp[color_plane];
2422 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2424 if (!is_surface_linear(fb, color_plane)) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int pitch_tiles;
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2431 if (drm_rotation_90_or_270(rotation)) {
2432 pitch_tiles = pitch / tile_height;
2433 swap(tile_width, tile_height);
2435 pitch_tiles = pitch / (tile_width * cpp);
2438 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 old_offset, new_offset);
2442 old_offset += *y * pitch + *x * cpp;
2444 *y = (old_offset - new_offset) / pitch;
2445 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2452 * Adjust the tile offset by moving the difference into
2455 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2456 const struct intel_plane_state *state,
2458 u32 old_offset, u32 new_offset)
2460 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2462 state->color_plane[color_plane].stride,
2463 old_offset, new_offset);
2467 * Computes the aligned offset to the base tile and adjusts
2468 * x, y. bytes per pixel is assumed to be a power-of-two.
2470 * In the 90/270 rotated case, x and y are assumed
2471 * to be already rotated to match the rotated GTT view, and
2472 * pitch is the tile_height aligned framebuffer height.
2474 * This function is used when computing the derived information
2475 * under intel_framebuffer, so using any of that information
2476 * here is not allowed. Anything under drm_framebuffer can be
2477 * used. This is why the user has to pass in the pitch since it
2478 * is specified in the rotated orientation.
2480 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2482 const struct drm_framebuffer *fb,
2485 unsigned int rotation,
2488 unsigned int cpp = fb->format->cpp[color_plane];
2489 u32 offset, offset_aligned;
2491 if (!is_surface_linear(fb, color_plane)) {
2492 unsigned int tile_size, tile_width, tile_height;
2493 unsigned int tile_rows, tiles, pitch_tiles;
2495 tile_size = intel_tile_size(dev_priv);
2496 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2498 if (drm_rotation_90_or_270(rotation)) {
2499 pitch_tiles = pitch / tile_height;
2500 swap(tile_width, tile_height);
2502 pitch_tiles = pitch / (tile_width * cpp);
2505 tile_rows = *y / tile_height;
2508 tiles = *x / tile_width;
2511 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2513 offset_aligned = offset;
2515 offset_aligned = rounddown(offset_aligned, alignment);
2517 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2518 tile_size, pitch_tiles,
2519 offset, offset_aligned);
2521 offset = *y * pitch + *x * cpp;
2522 offset_aligned = offset;
2524 offset_aligned = rounddown(offset_aligned, alignment);
2525 *y = (offset % alignment) / pitch;
2526 *x = ((offset % alignment) - *y * pitch) / cpp;
2532 return offset_aligned;
2535 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2536 const struct intel_plane_state *state,
2539 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2540 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2541 const struct drm_framebuffer *fb = state->hw.fb;
2542 unsigned int rotation = state->hw.rotation;
2543 int pitch = state->color_plane[color_plane].stride;
2546 if (intel_plane->id == PLANE_CURSOR)
2547 alignment = intel_cursor_alignment(dev_priv);
2549 alignment = intel_surf_alignment(fb, color_plane);
2551 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2552 pitch, rotation, alignment);
2555 /* Convert the fb->offset[] into x/y offsets */
2556 static int intel_fb_offset_to_xy(int *x, int *y,
2557 const struct drm_framebuffer *fb,
2560 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561 unsigned int height;
2564 if (INTEL_GEN(dev_priv) >= 12 &&
2565 is_semiplanar_uv_plane(fb, color_plane))
2566 alignment = intel_tile_row_size(fb, color_plane);
2567 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2568 alignment = intel_tile_size(dev_priv);
2572 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2573 drm_dbg_kms(&dev_priv->drm,
2574 "Misaligned offset 0x%08x for color plane %d\n",
2575 fb->offsets[color_plane], color_plane);
2579 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2580 height = ALIGN(height, intel_tile_height(fb, color_plane));
2582 /* Catch potential overflows early */
2583 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2584 fb->offsets[color_plane])) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2587 fb->offsets[color_plane], fb->pitches[color_plane],
2595 intel_adjust_aligned_offset(x, y,
2596 fb, color_plane, DRM_MODE_ROTATE_0,
2597 fb->pitches[color_plane],
2598 fb->offsets[color_plane], 0);
2603 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2605 switch (fb_modifier) {
2606 case I915_FORMAT_MOD_X_TILED:
2607 return I915_TILING_X;
2608 case I915_FORMAT_MOD_Y_TILED:
2609 case I915_FORMAT_MOD_Y_TILED_CCS:
2610 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2611 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2612 return I915_TILING_Y;
2614 return I915_TILING_NONE;
2619 * From the Sky Lake PRM:
2620 * "The Color Control Surface (CCS) contains the compression status of
2621 * the cache-line pairs. The compression state of the cache-line pair
2622 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2623 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2624 * cache-line-pairs. CCS is always Y tiled."
2626 * Since cache line pairs refers to horizontally adjacent cache lines,
2627 * each cache line in the CCS corresponds to an area of 32x16 cache
2628 * lines on the main surface. Since each pixel is 4 bytes, this gives
2629 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2632 static const struct drm_format_info skl_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2635 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2636 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2637 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2638 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2639 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2640 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2644 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2645 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2646 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2647 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2650 static const struct drm_format_info gen12_ccs_formats[] = {
2651 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2652 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 1, .vsub = 1, },
2654 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2655 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 1, .vsub = 1, },
2657 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2658 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 1, .vsub = 1, .has_alpha = true },
2660 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2661 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2662 .hsub = 1, .vsub = 1, .has_alpha = true },
2663 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2664 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2665 .hsub = 2, .vsub = 1, .is_yuv = true },
2666 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2667 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2668 .hsub = 2, .vsub = 1, .is_yuv = true },
2669 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2670 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2671 .hsub = 2, .vsub = 1, .is_yuv = true },
2672 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2673 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2674 .hsub = 2, .vsub = 1, .is_yuv = true },
2675 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2676 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2677 .hsub = 2, .vsub = 2, .is_yuv = true },
2678 { .format = DRM_FORMAT_P010, .num_planes = 4,
2679 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2680 .hsub = 2, .vsub = 2, .is_yuv = true },
2681 { .format = DRM_FORMAT_P012, .num_planes = 4,
2682 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2683 .hsub = 2, .vsub = 2, .is_yuv = true },
2684 { .format = DRM_FORMAT_P016, .num_planes = 4,
2685 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2686 .hsub = 2, .vsub = 2, .is_yuv = true },
2689 static const struct drm_format_info *
2690 lookup_format_info(const struct drm_format_info formats[],
2691 int num_formats, u32 format)
2695 for (i = 0; i < num_formats; i++) {
2696 if (formats[i].format == format)
2703 static const struct drm_format_info *
2704 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2706 switch (cmd->modifier[0]) {
2707 case I915_FORMAT_MOD_Y_TILED_CCS:
2708 case I915_FORMAT_MOD_Yf_TILED_CCS:
2709 return lookup_format_info(skl_ccs_formats,
2710 ARRAY_SIZE(skl_ccs_formats),
2712 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2713 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2714 return lookup_format_info(gen12_ccs_formats,
2715 ARRAY_SIZE(gen12_ccs_formats),
2722 bool is_ccs_modifier(u64 modifier)
2724 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2725 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2726 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2727 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2730 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2732 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2736 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2737 u32 pixel_format, u64 modifier)
2739 struct intel_crtc *crtc;
2740 struct intel_plane *plane;
2743 * We assume the primary plane for pipe A has
2744 * the highest stride limits of them all,
2745 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2747 crtc = intel_get_first_crtc(dev_priv);
2751 plane = to_intel_plane(crtc->base.primary);
2753 return plane->max_stride(plane, pixel_format, modifier,
2758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2759 u32 pixel_format, u64 modifier)
2762 * Arbitrary limit for gen4+ chosen to match the
2763 * render engine max stride.
2765 * The new CCS hash mode makes remapping impossible
2767 if (!is_ccs_modifier(modifier)) {
2768 if (INTEL_GEN(dev_priv) >= 7)
2770 else if (INTEL_GEN(dev_priv) >= 4)
2774 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2778 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2780 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2783 if (is_surface_linear(fb, color_plane)) {
2784 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2789 * To make remapping with linear generally feasible
2790 * we need the stride to be page aligned.
2792 if (fb->pitches[color_plane] > max_stride &&
2793 !is_ccs_modifier(fb->modifier))
2794 return intel_tile_size(dev_priv);
2799 tile_width = intel_tile_width_bytes(fb, color_plane);
2800 if (is_ccs_modifier(fb->modifier)) {
2802 * Display WA #0531: skl,bxt,kbl,glk
2804 * Render decompression and plane width > 3840
2805 * combined with horizontal panning requires the
2806 * plane stride to be a multiple of 4. We'll just
2807 * require the entire fb to accommodate that to avoid
2808 * potential runtime errors at plane configuration time.
2810 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2813 * The main surface pitch must be padded to a multiple of four
2816 else if (INTEL_GEN(dev_priv) >= 12)
2822 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2824 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2825 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2826 const struct drm_framebuffer *fb = plane_state->hw.fb;
2829 /* We don't want to deal with remapping with cursors */
2830 if (plane->id == PLANE_CURSOR)
2834 * The display engine limits already match/exceed the
2835 * render engine limits, so not much point in remapping.
2836 * Would also need to deal with the fence POT alignment
2837 * and gen2 2KiB GTT tile size.
2839 if (INTEL_GEN(dev_priv) < 4)
2843 * The new CCS hash mode isn't compatible with remapping as
2844 * the virtual address of the pages affects the compressed data.
2846 if (is_ccs_modifier(fb->modifier))
2849 /* Linear needs a page aligned stride for remapping */
2850 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2851 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2853 for (i = 0; i < fb->format->num_planes; i++) {
2854 if (fb->pitches[i] & alignment)
2862 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2864 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2865 const struct drm_framebuffer *fb = plane_state->hw.fb;
2866 unsigned int rotation = plane_state->hw.rotation;
2867 u32 stride, max_stride;
2870 * No remapping for invisible planes since we don't have
2871 * an actual source viewport to remap.
2873 if (!plane_state->uapi.visible)
2876 if (!intel_plane_can_remap(plane_state))
2880 * FIXME: aux plane limits on gen9+ are
2881 * unclear in Bspec, for now no checking.
2883 stride = intel_fb_pitch(fb, 0, rotation);
2884 max_stride = plane->max_stride(plane, fb->format->format,
2885 fb->modifier, rotation);
2887 return stride > max_stride;
2891 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2892 const struct drm_framebuffer *fb,
2897 if (color_plane == 0) {
2905 * TODO: Deduct the subsampling from the char block for all CCS
2906 * formats and planes.
2908 if (!is_gen12_ccs_plane(fb, color_plane)) {
2909 *hsub = fb->format->hsub;
2910 *vsub = fb->format->vsub;
2915 main_plane = ccs_to_main_plane(fb, color_plane);
2916 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2917 drm_format_info_block_width(fb->format, main_plane);
2920 * The min stride check in the core framebuffer_check() function
2921 * assumes that format->hsub applies to every plane except for the
2922 * first plane. That's incorrect for the CCS AUX plane of the first
2923 * plane, but for the above check to pass we must define the block
2924 * width with that subsampling applied to it. Adjust the width here
2925 * accordingly, so we can calculate the actual subsampling factor.
2927 if (main_plane == 0)
2928 *hsub *= fb->format->hsub;
2933 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2935 struct drm_i915_private *i915 = to_i915(fb->dev);
2936 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2939 int tile_width, tile_height;
2943 if (!is_ccs_plane(fb, ccs_plane))
2946 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2947 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2950 tile_height *= vsub;
2952 ccs_x = (x * hsub) % tile_width;
2953 ccs_y = (y * vsub) % tile_height;
2955 main_plane = ccs_to_main_plane(fb, ccs_plane);
2956 main_x = intel_fb->normal[main_plane].x % tile_width;
2957 main_y = intel_fb->normal[main_plane].y % tile_height;
2960 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2961 * x/y offsets must match between CCS and the main surface.
2963 if (main_x != ccs_x || main_y != ccs_y) {
2964 drm_dbg_kms(&i915->drm,
2965 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2968 intel_fb->normal[main_plane].x,
2969 intel_fb->normal[main_plane].y,
2978 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2980 int main_plane = is_ccs_plane(fb, color_plane) ?
2981 ccs_to_main_plane(fb, color_plane) : 0;
2982 int main_hsub, main_vsub;
2985 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2986 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2987 *w = fb->width / main_hsub / hsub;
2988 *h = fb->height / main_vsub / vsub;
2992 * Setup the rotated view for an FB plane and return the size the GTT mapping
2993 * requires for this view.
2996 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2997 u32 gtt_offset_rotated, int x, int y,
2998 unsigned int width, unsigned int height,
2999 unsigned int tile_size,
3000 unsigned int tile_width, unsigned int tile_height,
3001 struct drm_framebuffer *fb)
3003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3004 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
3005 unsigned int pitch_tiles;
3008 /* Y or Yf modifiers required for 90/270 rotation */
3009 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3010 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3013 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3016 rot_info->plane[plane] = *plane_info;
3018 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3020 /* rotate the x/y offsets to match the GTT view */
3021 drm_rect_init(&r, x, y, width, height);
3023 plane_info->width * tile_width,
3024 plane_info->height * tile_height,
3025 DRM_MODE_ROTATE_270);
3029 /* rotate the tile dimensions to match the GTT view */
3030 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3031 swap(tile_width, tile_height);
3034 * We only keep the x/y offsets, so push all of the
3035 * gtt offset into the x/y offsets.
3037 intel_adjust_tile_offset(&x, &y,
3038 tile_width, tile_height,
3039 tile_size, pitch_tiles,
3040 gtt_offset_rotated * tile_size, 0);
3043 * First pixel of the framebuffer from
3044 * the start of the rotated gtt mapping.
3046 intel_fb->rotated[plane].x = x;
3047 intel_fb->rotated[plane].y = y;
3049 return plane_info->width * plane_info->height;
3053 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3054 struct drm_framebuffer *fb)
3056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3058 u32 gtt_offset_rotated = 0;
3059 unsigned int max_size = 0;
3060 int i, num_planes = fb->format->num_planes;
3061 unsigned int tile_size = intel_tile_size(dev_priv);
3063 for (i = 0; i < num_planes; i++) {
3064 unsigned int width, height;
3065 unsigned int cpp, size;
3070 cpp = fb->format->cpp[i];
3071 intel_fb_plane_dims(&width, &height, fb, i);
3073 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3075 drm_dbg_kms(&dev_priv->drm,
3076 "bad fb plane %d offset: 0x%x\n",
3081 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3086 * The fence (if used) is aligned to the start of the object
3087 * so having the framebuffer wrap around across the edge of the
3088 * fenced region doesn't really work. We have no API to configure
3089 * the fence start offset within the object (nor could we probably
3090 * on gen2/3). So it's just easier if we just require that the
3091 * fb layout agrees with the fence layout. We already check that the
3092 * fb stride matches the fence stride elsewhere.
3094 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3095 (x + width) * cpp > fb->pitches[i]) {
3096 drm_dbg_kms(&dev_priv->drm,
3097 "bad fb plane %d offset: 0x%x\n",
3103 * First pixel of the framebuffer from
3104 * the start of the normal gtt mapping.
3106 intel_fb->normal[i].x = x;
3107 intel_fb->normal[i].y = y;
3109 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3113 offset /= tile_size;
3115 if (!is_surface_linear(fb, i)) {
3116 struct intel_remapped_plane_info plane_info;
3117 unsigned int tile_width, tile_height;
3119 intel_tile_dims(fb, i, &tile_width, &tile_height);
3121 plane_info.offset = offset;
3122 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3124 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3125 plane_info.height = DIV_ROUND_UP(y + height,
3128 /* how many tiles does this plane need */
3129 size = plane_info.stride * plane_info.height;
3131 * If the plane isn't horizontally tile aligned,
3132 * we need one more tile.
3137 gtt_offset_rotated +=
3138 setup_fb_rotation(i, &plane_info,
3140 x, y, width, height,
3142 tile_width, tile_height,
3145 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3146 x * cpp, tile_size);
3149 /* how many tiles in total needed in the bo */
3150 max_size = max(max_size, offset + size);
3153 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3154 drm_dbg_kms(&dev_priv->drm,
3155 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3156 mul_u32_u32(max_size, tile_size), obj->base.size);
3164 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3166 struct drm_i915_private *dev_priv =
3167 to_i915(plane_state->uapi.plane->dev);
3168 struct drm_framebuffer *fb = plane_state->hw.fb;
3169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3170 struct intel_rotation_info *info = &plane_state->view.rotated;
3171 unsigned int rotation = plane_state->hw.rotation;
3172 int i, num_planes = fb->format->num_planes;
3173 unsigned int tile_size = intel_tile_size(dev_priv);
3174 unsigned int src_x, src_y;
3175 unsigned int src_w, src_h;
3178 memset(&plane_state->view, 0, sizeof(plane_state->view));
3179 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3180 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3182 src_x = plane_state->uapi.src.x1 >> 16;
3183 src_y = plane_state->uapi.src.y1 >> 16;
3184 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3185 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3187 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3189 /* Make src coordinates relative to the viewport */
3190 drm_rect_translate(&plane_state->uapi.src,
3191 -(src_x << 16), -(src_y << 16));
3193 /* Rotate src coordinates to match rotated GTT view */
3194 if (drm_rotation_90_or_270(rotation))
3195 drm_rect_rotate(&plane_state->uapi.src,
3196 src_w << 16, src_h << 16,
3197 DRM_MODE_ROTATE_270);
3199 for (i = 0; i < num_planes; i++) {
3200 unsigned int hsub = i ? fb->format->hsub : 1;
3201 unsigned int vsub = i ? fb->format->vsub : 1;
3202 unsigned int cpp = fb->format->cpp[i];
3203 unsigned int tile_width, tile_height;
3204 unsigned int width, height;
3205 unsigned int pitch_tiles;
3209 intel_tile_dims(fb, i, &tile_width, &tile_height);
3213 width = src_w / hsub;
3214 height = src_h / vsub;
3217 * First pixel of the src viewport from the
3218 * start of the normal gtt mapping.
3220 x += intel_fb->normal[i].x;
3221 y += intel_fb->normal[i].y;
3223 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3224 fb, i, fb->pitches[i],
3225 DRM_MODE_ROTATE_0, tile_size);
3226 offset /= tile_size;
3228 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3229 info->plane[i].offset = offset;
3230 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3232 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3233 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3235 if (drm_rotation_90_or_270(rotation)) {
3238 /* rotate the x/y offsets to match the GTT view */
3239 drm_rect_init(&r, x, y, width, height);
3241 info->plane[i].width * tile_width,
3242 info->plane[i].height * tile_height,
3243 DRM_MODE_ROTATE_270);
3247 pitch_tiles = info->plane[i].height;
3248 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3250 /* rotate the tile dimensions to match the GTT view */
3251 swap(tile_width, tile_height);
3253 pitch_tiles = info->plane[i].width;
3254 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3258 * We only keep the x/y offsets, so push all of the
3259 * gtt offset into the x/y offsets.
3261 intel_adjust_tile_offset(&x, &y,
3262 tile_width, tile_height,
3263 tile_size, pitch_tiles,
3264 gtt_offset * tile_size, 0);
3266 gtt_offset += info->plane[i].width * info->plane[i].height;
3268 plane_state->color_plane[i].offset = 0;
3269 plane_state->color_plane[i].x = x;
3270 plane_state->color_plane[i].y = y;
3275 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3277 const struct intel_framebuffer *fb =
3278 to_intel_framebuffer(plane_state->hw.fb);
3279 unsigned int rotation = plane_state->hw.rotation;
3285 num_planes = fb->base.format->num_planes;
3287 if (intel_plane_needs_remap(plane_state)) {
3288 intel_plane_remap_gtt(plane_state);
3291 * Sometimes even remapping can't overcome
3292 * the stride limitations :( Can happen with
3293 * big plane sizes and suitably misaligned
3296 return intel_plane_check_stride(plane_state);
3299 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3301 for (i = 0; i < num_planes; i++) {
3302 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3303 plane_state->color_plane[i].offset = 0;
3305 if (drm_rotation_90_or_270(rotation)) {
3306 plane_state->color_plane[i].x = fb->rotated[i].x;
3307 plane_state->color_plane[i].y = fb->rotated[i].y;
3309 plane_state->color_plane[i].x = fb->normal[i].x;
3310 plane_state->color_plane[i].y = fb->normal[i].y;
3314 /* Rotate src coordinates to match rotated GTT view */
3315 if (drm_rotation_90_or_270(rotation))
3316 drm_rect_rotate(&plane_state->uapi.src,
3317 fb->base.width << 16, fb->base.height << 16,
3318 DRM_MODE_ROTATE_270);
3320 return intel_plane_check_stride(plane_state);
3323 static int i9xx_format_to_fourcc(int format)
3326 case DISPPLANE_8BPP:
3327 return DRM_FORMAT_C8;
3328 case DISPPLANE_BGRA555:
3329 return DRM_FORMAT_ARGB1555;
3330 case DISPPLANE_BGRX555:
3331 return DRM_FORMAT_XRGB1555;
3332 case DISPPLANE_BGRX565:
3333 return DRM_FORMAT_RGB565;
3335 case DISPPLANE_BGRX888:
3336 return DRM_FORMAT_XRGB8888;
3337 case DISPPLANE_RGBX888:
3338 return DRM_FORMAT_XBGR8888;
3339 case DISPPLANE_BGRA888:
3340 return DRM_FORMAT_ARGB8888;
3341 case DISPPLANE_RGBA888:
3342 return DRM_FORMAT_ABGR8888;
3343 case DISPPLANE_BGRX101010:
3344 return DRM_FORMAT_XRGB2101010;
3345 case DISPPLANE_RGBX101010:
3346 return DRM_FORMAT_XBGR2101010;
3347 case DISPPLANE_BGRA101010:
3348 return DRM_FORMAT_ARGB2101010;
3349 case DISPPLANE_RGBA101010:
3350 return DRM_FORMAT_ABGR2101010;
3351 case DISPPLANE_RGBX161616:
3352 return DRM_FORMAT_XBGR16161616F;
3356 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3359 case PLANE_CTL_FORMAT_RGB_565:
3360 return DRM_FORMAT_RGB565;
3361 case PLANE_CTL_FORMAT_NV12:
3362 return DRM_FORMAT_NV12;
3363 case PLANE_CTL_FORMAT_XYUV:
3364 return DRM_FORMAT_XYUV8888;
3365 case PLANE_CTL_FORMAT_P010:
3366 return DRM_FORMAT_P010;
3367 case PLANE_CTL_FORMAT_P012:
3368 return DRM_FORMAT_P012;
3369 case PLANE_CTL_FORMAT_P016:
3370 return DRM_FORMAT_P016;
3371 case PLANE_CTL_FORMAT_Y210:
3372 return DRM_FORMAT_Y210;
3373 case PLANE_CTL_FORMAT_Y212:
3374 return DRM_FORMAT_Y212;
3375 case PLANE_CTL_FORMAT_Y216:
3376 return DRM_FORMAT_Y216;
3377 case PLANE_CTL_FORMAT_Y410:
3378 return DRM_FORMAT_XVYU2101010;
3379 case PLANE_CTL_FORMAT_Y412:
3380 return DRM_FORMAT_XVYU12_16161616;
3381 case PLANE_CTL_FORMAT_Y416:
3382 return DRM_FORMAT_XVYU16161616;
3384 case PLANE_CTL_FORMAT_XRGB_8888:
3387 return DRM_FORMAT_ABGR8888;
3389 return DRM_FORMAT_XBGR8888;
3392 return DRM_FORMAT_ARGB8888;
3394 return DRM_FORMAT_XRGB8888;
3396 case PLANE_CTL_FORMAT_XRGB_2101010:
3399 return DRM_FORMAT_ABGR2101010;
3401 return DRM_FORMAT_XBGR2101010;
3404 return DRM_FORMAT_ARGB2101010;
3406 return DRM_FORMAT_XRGB2101010;
3408 case PLANE_CTL_FORMAT_XRGB_16161616F:
3411 return DRM_FORMAT_ABGR16161616F;
3413 return DRM_FORMAT_XBGR16161616F;
3416 return DRM_FORMAT_ARGB16161616F;
3418 return DRM_FORMAT_XRGB16161616F;
3423 static struct i915_vma *
3424 initial_plane_vma(struct drm_i915_private *i915,
3425 struct intel_initial_plane_config *plane_config)
3427 struct drm_i915_gem_object *obj;
3428 struct i915_vma *vma;
3431 if (plane_config->size == 0)
3434 base = round_down(plane_config->base,
3435 I915_GTT_MIN_ALIGNMENT);
3436 size = round_up(plane_config->base + plane_config->size,
3437 I915_GTT_MIN_ALIGNMENT);
3441 * If the FB is too big, just don't use it since fbdev is not very
3442 * important and we should probably use that space with FBC or other
3445 if (size * 2 > i915->stolen_usable_size)
3448 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3453 * Mark it WT ahead of time to avoid changing the
3454 * cache_level during fbdev initialization. The
3455 * unbind there would get stuck waiting for rcu.
3457 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3458 I915_CACHE_WT : I915_CACHE_NONE);
3460 switch (plane_config->tiling) {
3461 case I915_TILING_NONE:
3465 obj->tiling_and_stride =
3466 plane_config->fb->base.pitches[0] |
3467 plane_config->tiling;
3470 MISSING_CASE(plane_config->tiling);
3474 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3478 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3481 if (i915_gem_object_is_tiled(obj) &&
3482 !i915_vma_is_map_and_fenceable(vma))
3488 i915_gem_object_put(obj);
3493 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3494 struct intel_initial_plane_config *plane_config)
3496 struct drm_device *dev = crtc->base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3499 struct drm_framebuffer *fb = &plane_config->fb->base;
3500 struct i915_vma *vma;
3502 switch (fb->modifier) {
3503 case DRM_FORMAT_MOD_LINEAR:
3504 case I915_FORMAT_MOD_X_TILED:
3505 case I915_FORMAT_MOD_Y_TILED:
3508 drm_dbg(&dev_priv->drm,
3509 "Unsupported modifier for initial FB: 0x%llx\n",
3514 vma = initial_plane_vma(dev_priv, plane_config);
3518 mode_cmd.pixel_format = fb->format->format;
3519 mode_cmd.width = fb->width;
3520 mode_cmd.height = fb->height;
3521 mode_cmd.pitches[0] = fb->pitches[0];
3522 mode_cmd.modifier[0] = fb->modifier;
3523 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3525 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3526 vma->obj, &mode_cmd)) {
3527 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3531 plane_config->vma = vma;
3540 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3541 struct intel_plane_state *plane_state,
3544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3546 plane_state->uapi.visible = visible;
3549 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3551 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3554 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3556 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3557 struct drm_plane *plane;
3560 * Active_planes aliases if multiple "primary" or cursor planes
3561 * have been used on the same (or wrong) pipe. plane_mask uses
3562 * unique ids, hence we can use that to reconstruct active_planes.
3564 crtc_state->active_planes = 0;
3566 drm_for_each_plane_mask(plane, &dev_priv->drm,
3567 crtc_state->uapi.plane_mask)
3568 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3571 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3572 struct intel_plane *plane)
3574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3575 struct intel_crtc_state *crtc_state =
3576 to_intel_crtc_state(crtc->base.state);
3577 struct intel_plane_state *plane_state =
3578 to_intel_plane_state(plane->base.state);
3580 drm_dbg_kms(&dev_priv->drm,
3581 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3582 plane->base.base.id, plane->base.name,
3583 crtc->base.base.id, crtc->base.name);
3585 intel_set_plane_visible(crtc_state, plane_state, false);
3586 fixup_active_planes(crtc_state);
3587 crtc_state->data_rate[plane->id] = 0;
3588 crtc_state->min_cdclk[plane->id] = 0;
3590 if (plane->id == PLANE_PRIMARY)
3591 hsw_disable_ips(crtc_state);
3594 * Vblank time updates from the shadow to live plane control register
3595 * are blocked if the memory self-refresh mode is active at that
3596 * moment. So to make sure the plane gets truly disabled, disable
3597 * first the self-refresh mode. The self-refresh enable bit in turn
3598 * will be checked/applied by the HW only at the next frame start
3599 * event which is after the vblank start event, so we need to have a
3600 * wait-for-vblank between disabling the plane and the pipe.
3602 if (HAS_GMCH(dev_priv) &&
3603 intel_set_memory_cxsr(dev_priv, false))
3604 intel_wait_for_vblank(dev_priv, crtc->pipe);
3607 * Gen2 reports pipe underruns whenever all planes are disabled.
3608 * So disable underrun reporting before all the planes get disabled.
3610 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3611 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3613 intel_disable_plane(plane, crtc_state);
3616 static struct intel_frontbuffer *
3617 to_intel_frontbuffer(struct drm_framebuffer *fb)
3619 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3623 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3624 struct intel_initial_plane_config *plane_config)
3626 struct drm_device *dev = intel_crtc->base.dev;
3627 struct drm_i915_private *dev_priv = to_i915(dev);
3629 struct drm_plane *primary = intel_crtc->base.primary;
3630 struct drm_plane_state *plane_state = primary->state;
3631 struct intel_plane *intel_plane = to_intel_plane(primary);
3632 struct intel_plane_state *intel_state =
3633 to_intel_plane_state(plane_state);
3634 struct drm_framebuffer *fb;
3635 struct i915_vma *vma;
3637 if (!plane_config->fb)
3640 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3641 fb = &plane_config->fb->base;
3642 vma = plane_config->vma;
3647 * Failed to alloc the obj, check to see if we should share
3648 * an fb with another CRTC instead
3650 for_each_crtc(dev, c) {
3651 struct intel_plane_state *state;
3653 if (c == &intel_crtc->base)
3656 if (!to_intel_crtc(c)->active)
3659 state = to_intel_plane_state(c->primary->state);
3663 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3671 * We've failed to reconstruct the BIOS FB. Current display state
3672 * indicates that the primary plane is visible, but has a NULL FB,
3673 * which will lead to problems later if we don't fix it up. The
3674 * simplest solution is to just disable the primary plane now and
3675 * pretend the BIOS never had it enabled.
3677 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3682 intel_state->hw.rotation = plane_config->rotation;
3683 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3684 intel_state->hw.rotation);
3685 intel_state->color_plane[0].stride =
3686 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3688 __i915_vma_pin(vma);
3689 intel_state->vma = i915_vma_get(vma);
3690 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3692 intel_state->flags |= PLANE_HAS_FENCE;
3694 plane_state->src_x = 0;
3695 plane_state->src_y = 0;
3696 plane_state->src_w = fb->width << 16;
3697 plane_state->src_h = fb->height << 16;
3699 plane_state->crtc_x = 0;
3700 plane_state->crtc_y = 0;
3701 plane_state->crtc_w = fb->width;
3702 plane_state->crtc_h = fb->height;
3704 intel_state->uapi.src = drm_plane_state_src(plane_state);
3705 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3707 if (plane_config->tiling)
3708 dev_priv->preserve_bios_swizzle = true;
3710 plane_state->fb = fb;
3711 drm_framebuffer_get(fb);
3713 plane_state->crtc = &intel_crtc->base;
3714 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3716 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3718 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3719 &to_intel_frontbuffer(fb)->bits);
3722 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3724 unsigned int rotation)
3726 int cpp = fb->format->cpp[color_plane];
3728 switch (fb->modifier) {
3729 case DRM_FORMAT_MOD_LINEAR:
3730 case I915_FORMAT_MOD_X_TILED:
3732 * Validated limit is 4k, but has 5k should
3733 * work apart from the following features:
3734 * - Ytile (already limited to 4k)
3735 * - FP16 (already limited to 4k)
3736 * - render compression (already limited to 4k)
3737 * - KVMR sprite and cursor (don't care)
3738 * - horizontal panning (TODO verify this)
3739 * - pipe and plane scaling (TODO verify this)
3745 case I915_FORMAT_MOD_Y_TILED_CCS:
3746 case I915_FORMAT_MOD_Yf_TILED_CCS:
3747 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3748 /* FIXME AUX plane? */
3749 case I915_FORMAT_MOD_Y_TILED:
3750 case I915_FORMAT_MOD_Yf_TILED:
3756 MISSING_CASE(fb->modifier);
3761 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3763 unsigned int rotation)
3765 int cpp = fb->format->cpp[color_plane];
3767 switch (fb->modifier) {
3768 case DRM_FORMAT_MOD_LINEAR:
3769 case I915_FORMAT_MOD_X_TILED:
3774 case I915_FORMAT_MOD_Y_TILED_CCS:
3775 case I915_FORMAT_MOD_Yf_TILED_CCS:
3776 /* FIXME AUX plane? */
3777 case I915_FORMAT_MOD_Y_TILED:
3778 case I915_FORMAT_MOD_Yf_TILED:
3784 MISSING_CASE(fb->modifier);
3789 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3791 /* Wa_14011264657, Wa_14011050563: gen11+ */
3792 switch (fb->format->format) {
3795 case DRM_FORMAT_RGB565:
3797 case DRM_FORMAT_XRGB8888:
3798 case DRM_FORMAT_XBGR8888:
3799 case DRM_FORMAT_ARGB8888:
3800 case DRM_FORMAT_ABGR8888:
3801 case DRM_FORMAT_XRGB2101010:
3802 case DRM_FORMAT_XBGR2101010:
3803 case DRM_FORMAT_ARGB2101010:
3804 case DRM_FORMAT_ABGR2101010:
3805 case DRM_FORMAT_XVYU2101010:
3806 case DRM_FORMAT_Y212:
3807 case DRM_FORMAT_Y216:
3809 case DRM_FORMAT_NV12:
3811 case DRM_FORMAT_P010:
3812 case DRM_FORMAT_P012:
3813 case DRM_FORMAT_P016:
3815 case DRM_FORMAT_XRGB16161616F:
3816 case DRM_FORMAT_XBGR16161616F:
3817 case DRM_FORMAT_ARGB16161616F:
3818 case DRM_FORMAT_ABGR16161616F:
3819 case DRM_FORMAT_XVYU12_16161616:
3820 case DRM_FORMAT_XVYU16161616:
3827 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3829 unsigned int rotation)
3834 static int skl_max_plane_height(void)
3839 static int icl_max_plane_height(void)
3845 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3846 int main_x, int main_y, u32 main_offset,
3849 const struct drm_framebuffer *fb = plane_state->hw.fb;
3850 int aux_x = plane_state->color_plane[ccs_plane].x;
3851 int aux_y = plane_state->color_plane[ccs_plane].y;
3852 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3853 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3857 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3858 while (aux_offset >= main_offset && aux_y <= main_y) {
3861 if (aux_x == main_x && aux_y == main_y)
3864 if (aux_offset == 0)
3869 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3875 aux_x = x * hsub + aux_x % hsub;
3876 aux_y = y * vsub + aux_y % vsub;
3879 if (aux_x != main_x || aux_y != main_y)
3882 plane_state->color_plane[ccs_plane].offset = aux_offset;
3883 plane_state->color_plane[ccs_plane].x = aux_x;
3884 plane_state->color_plane[ccs_plane].y = aux_y;
3890 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3894 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3895 plane_state->color_plane[0].offset, 0);
3900 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3902 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3903 const struct drm_framebuffer *fb = plane_state->hw.fb;
3904 unsigned int rotation = plane_state->hw.rotation;
3905 int x = plane_state->uapi.src.x1 >> 16;
3906 int y = plane_state->uapi.src.y1 >> 16;
3907 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3908 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3909 int max_width, min_width, max_height;
3910 u32 alignment, offset;
3911 int aux_plane = intel_main_to_aux_plane(fb, 0);
3912 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3914 if (INTEL_GEN(dev_priv) >= 11) {
3915 max_width = icl_max_plane_width(fb, 0, rotation);
3916 min_width = icl_min_plane_width(fb);
3917 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3918 max_width = glk_max_plane_width(fb, 0, rotation);
3921 max_width = skl_max_plane_width(fb, 0, rotation);
3925 if (INTEL_GEN(dev_priv) >= 11)
3926 max_height = icl_max_plane_height();
3928 max_height = skl_max_plane_height();
3930 if (w > max_width || w < min_width || h > max_height) {
3931 drm_dbg_kms(&dev_priv->drm,
3932 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3933 w, h, min_width, max_width, max_height);
3937 intel_add_fb_offsets(&x, &y, plane_state, 0);
3938 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3939 alignment = intel_surf_alignment(fb, 0);
3940 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3944 * AUX surface offset is specified as the distance from the
3945 * main surface offset, and it must be non-negative. Make
3946 * sure that is what we will get.
3948 if (aux_plane && offset > aux_offset)
3949 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3950 offset, aux_offset & ~(alignment - 1));
3953 * When using an X-tiled surface, the plane blows up
3954 * if the x offset + width exceed the stride.
3956 * TODO: linear and Y-tiled seem fine, Yf untested,
3958 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3959 int cpp = fb->format->cpp[0];
3961 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3963 drm_dbg_kms(&dev_priv->drm,
3964 "Unable to find suitable display surface offset due to X-tiling\n");
3968 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969 offset, offset - alignment);
3974 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3975 * they match with the main surface x/y offsets.
3977 if (is_ccs_modifier(fb->modifier)) {
3978 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3979 offset, aux_plane)) {
3983 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3984 offset, offset - alignment);
3987 if (x != plane_state->color_plane[aux_plane].x ||
3988 y != plane_state->color_plane[aux_plane].y) {
3989 drm_dbg_kms(&dev_priv->drm,
3990 "Unable to find suitable display surface offset due to CCS\n");
3995 plane_state->color_plane[0].offset = offset;
3996 plane_state->color_plane[0].x = x;
3997 plane_state->color_plane[0].y = y;
4000 * Put the final coordinates back so that the src
4001 * coordinate checks will see the right values.
4003 drm_rect_translate_to(&plane_state->uapi.src,
4009 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
4011 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
4012 const struct drm_framebuffer *fb = plane_state->hw.fb;
4013 unsigned int rotation = plane_state->hw.rotation;
4015 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4016 int max_height = 4096;
4017 int x = plane_state->uapi.src.x1 >> 17;
4018 int y = plane_state->uapi.src.y1 >> 17;
4019 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4020 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4023 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4024 offset = intel_plane_compute_aligned_offset(&x, &y,
4025 plane_state, uv_plane);
4027 /* FIXME not quite sure how/if these apply to the chroma plane */
4028 if (w > max_width || h > max_height) {
4029 drm_dbg_kms(&i915->drm,
4030 "CbCr source size %dx%d too big (limit %dx%d)\n",
4031 w, h, max_width, max_height);
4035 if (is_ccs_modifier(fb->modifier)) {
4036 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4037 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
4038 u32 alignment = intel_surf_alignment(fb, uv_plane);
4040 if (offset > aux_offset)
4041 offset = intel_plane_adjust_aligned_offset(&x, &y,
4045 aux_offset & ~(alignment - 1));
4047 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4048 offset, ccs_plane)) {
4052 offset = intel_plane_adjust_aligned_offset(&x, &y,
4055 offset, offset - alignment);
4058 if (x != plane_state->color_plane[ccs_plane].x ||
4059 y != plane_state->color_plane[ccs_plane].y) {
4060 drm_dbg_kms(&i915->drm,
4061 "Unable to find suitable display surface offset due to CCS\n");
4066 plane_state->color_plane[uv_plane].offset = offset;
4067 plane_state->color_plane[uv_plane].x = x;
4068 plane_state->color_plane[uv_plane].y = y;
4073 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4075 const struct drm_framebuffer *fb = plane_state->hw.fb;
4076 int src_x = plane_state->uapi.src.x1 >> 16;
4077 int src_y = plane_state->uapi.src.y1 >> 16;
4081 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4082 int main_hsub, main_vsub;
4086 if (!is_ccs_plane(fb, ccs_plane))
4089 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4090 ccs_to_main_plane(fb, ccs_plane));
4091 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4098 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4100 offset = intel_plane_compute_aligned_offset(&x, &y,
4104 plane_state->color_plane[ccs_plane].offset = offset;
4105 plane_state->color_plane[ccs_plane].x = (x * hsub +
4108 plane_state->color_plane[ccs_plane].y = (y * vsub +
4116 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4118 const struct drm_framebuffer *fb = plane_state->hw.fb;
4121 ret = intel_plane_compute_gtt(plane_state);
4125 if (!plane_state->uapi.visible)
4129 * Handle the AUX surface first since the main surface setup depends on
4132 if (is_ccs_modifier(fb->modifier)) {
4133 ret = skl_check_ccs_aux_surface(plane_state);
4138 if (intel_format_info_is_yuv_semiplanar(fb->format,
4140 ret = skl_check_nv12_aux_surface(plane_state);
4145 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4146 plane_state->color_plane[i].offset = 0;
4147 plane_state->color_plane[i].x = 0;
4148 plane_state->color_plane[i].y = 0;
4151 ret = skl_check_main_surface(plane_state);
4158 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4159 const struct intel_plane_state *plane_state,
4160 unsigned int *num, unsigned int *den)
4162 const struct drm_framebuffer *fb = plane_state->hw.fb;
4163 unsigned int cpp = fb->format->cpp[0];
4166 * g4x bspec says 64bpp pixel rate can't exceed 80%
4167 * of cdclk when the sprite plane is enabled on the
4168 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4169 * never allowed to exceed 80% of cdclk. Let's just go
4170 * with the ilk/snb limit always.
4181 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4182 const struct intel_plane_state *plane_state)
4184 unsigned int pixel_rate;
4185 unsigned int num, den;
4188 * Note that crtc_state->pixel_rate accounts for both
4189 * horizontal and vertical panel fitter downscaling factors.
4190 * Pre-HSW bspec tells us to only consider the horizontal
4191 * downscaling factor here. We ignore that and just consider
4192 * both for simplicity.
4194 pixel_rate = crtc_state->pixel_rate;
4196 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4198 /* two pixels per clock with double wide pipe */
4199 if (crtc_state->double_wide)
4202 return DIV_ROUND_UP(pixel_rate * num, den);
4206 i9xx_plane_max_stride(struct intel_plane *plane,
4207 u32 pixel_format, u64 modifier,
4208 unsigned int rotation)
4210 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4212 if (!HAS_GMCH(dev_priv)) {
4214 } else if (INTEL_GEN(dev_priv) >= 4) {
4215 if (modifier == I915_FORMAT_MOD_X_TILED)
4219 } else if (INTEL_GEN(dev_priv) >= 3) {
4220 if (modifier == I915_FORMAT_MOD_X_TILED)
4225 if (plane->i9xx_plane == PLANE_C)
4232 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4238 if (crtc_state->gamma_enable)
4239 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4241 if (crtc_state->csc_enable)
4242 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4244 if (INTEL_GEN(dev_priv) < 5)
4245 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4250 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4251 const struct intel_plane_state *plane_state)
4253 struct drm_i915_private *dev_priv =
4254 to_i915(plane_state->uapi.plane->dev);
4255 const struct drm_framebuffer *fb = plane_state->hw.fb;
4256 unsigned int rotation = plane_state->hw.rotation;
4259 dspcntr = DISPLAY_PLANE_ENABLE;
4261 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4262 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4263 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4265 switch (fb->format->format) {
4267 dspcntr |= DISPPLANE_8BPP;
4269 case DRM_FORMAT_XRGB1555:
4270 dspcntr |= DISPPLANE_BGRX555;
4272 case DRM_FORMAT_ARGB1555:
4273 dspcntr |= DISPPLANE_BGRA555;
4275 case DRM_FORMAT_RGB565:
4276 dspcntr |= DISPPLANE_BGRX565;
4278 case DRM_FORMAT_XRGB8888:
4279 dspcntr |= DISPPLANE_BGRX888;
4281 case DRM_FORMAT_XBGR8888:
4282 dspcntr |= DISPPLANE_RGBX888;
4284 case DRM_FORMAT_ARGB8888:
4285 dspcntr |= DISPPLANE_BGRA888;
4287 case DRM_FORMAT_ABGR8888:
4288 dspcntr |= DISPPLANE_RGBA888;
4290 case DRM_FORMAT_XRGB2101010:
4291 dspcntr |= DISPPLANE_BGRX101010;
4293 case DRM_FORMAT_XBGR2101010:
4294 dspcntr |= DISPPLANE_RGBX101010;
4296 case DRM_FORMAT_ARGB2101010:
4297 dspcntr |= DISPPLANE_BGRA101010;
4299 case DRM_FORMAT_ABGR2101010:
4300 dspcntr |= DISPPLANE_RGBA101010;
4302 case DRM_FORMAT_XBGR16161616F:
4303 dspcntr |= DISPPLANE_RGBX161616;
4306 MISSING_CASE(fb->format->format);
4310 if (INTEL_GEN(dev_priv) >= 4 &&
4311 fb->modifier == I915_FORMAT_MOD_X_TILED)
4312 dspcntr |= DISPPLANE_TILED;
4314 if (rotation & DRM_MODE_ROTATE_180)
4315 dspcntr |= DISPPLANE_ROTATE_180;
4317 if (rotation & DRM_MODE_REFLECT_X)
4318 dspcntr |= DISPPLANE_MIRROR;
4323 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4325 struct drm_i915_private *dev_priv =
4326 to_i915(plane_state->uapi.plane->dev);
4327 const struct drm_framebuffer *fb = plane_state->hw.fb;
4328 int src_x, src_y, src_w;
4332 ret = intel_plane_compute_gtt(plane_state);
4336 if (!plane_state->uapi.visible)
4339 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4340 src_x = plane_state->uapi.src.x1 >> 16;
4341 src_y = plane_state->uapi.src.y1 >> 16;
4343 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4344 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4347 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4349 if (INTEL_GEN(dev_priv) >= 4)
4350 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4356 * Put the final coordinates back so that the src
4357 * coordinate checks will see the right values.
4359 drm_rect_translate_to(&plane_state->uapi.src,
4360 src_x << 16, src_y << 16);
4362 /* HSW/BDW do this automagically in hardware */
4363 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4364 unsigned int rotation = plane_state->hw.rotation;
4365 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4366 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4368 if (rotation & DRM_MODE_ROTATE_180) {
4371 } else if (rotation & DRM_MODE_REFLECT_X) {
4376 plane_state->color_plane[0].offset = offset;
4377 plane_state->color_plane[0].x = src_x;
4378 plane_state->color_plane[0].y = src_y;
4383 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4385 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4386 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4388 if (IS_CHERRYVIEW(dev_priv))
4389 return i9xx_plane == PLANE_B;
4390 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4392 else if (IS_GEN(dev_priv, 4))
4393 return i9xx_plane == PLANE_C;
4395 return i9xx_plane == PLANE_B ||
4396 i9xx_plane == PLANE_C;
4400 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4401 struct intel_plane_state *plane_state)
4403 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4406 ret = chv_plane_check_rotation(plane_state);
4410 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4412 DRM_PLANE_HELPER_NO_SCALING,
4413 DRM_PLANE_HELPER_NO_SCALING,
4414 i9xx_plane_has_windowing(plane),
4419 ret = i9xx_check_plane_surface(plane_state);
4423 if (!plane_state->uapi.visible)
4426 ret = intel_plane_check_src_coordinates(plane_state);
4430 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4435 static void i9xx_update_plane(struct intel_plane *plane,
4436 const struct intel_crtc_state *crtc_state,
4437 const struct intel_plane_state *plane_state)
4439 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4440 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4442 int x = plane_state->color_plane[0].x;
4443 int y = plane_state->color_plane[0].y;
4444 int crtc_x = plane_state->uapi.dst.x1;
4445 int crtc_y = plane_state->uapi.dst.y1;
4446 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4447 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4448 unsigned long irqflags;
4452 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4454 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4456 if (INTEL_GEN(dev_priv) >= 4)
4457 dspaddr_offset = plane_state->color_plane[0].offset;
4459 dspaddr_offset = linear_offset;
4461 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4463 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4464 plane_state->color_plane[0].stride);
4466 if (INTEL_GEN(dev_priv) < 4) {
4468 * PLANE_A doesn't actually have a full window
4469 * generator but let's assume we still need to
4470 * program whatever is there.
4472 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4473 (crtc_y << 16) | crtc_x);
4474 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4475 ((crtc_h - 1) << 16) | (crtc_w - 1));
4476 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4477 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4478 (crtc_y << 16) | crtc_x);
4479 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4480 ((crtc_h - 1) << 16) | (crtc_w - 1));
4481 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4484 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4485 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4487 } else if (INTEL_GEN(dev_priv) >= 4) {
4488 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4490 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4495 * The control register self-arms if the plane was previously
4496 * disabled. Try to make the plane enable atomic by writing
4497 * the control register just before the surface register.
4499 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4500 if (INTEL_GEN(dev_priv) >= 4)
4501 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4502 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4504 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4505 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4507 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4510 static void i9xx_disable_plane(struct intel_plane *plane,
4511 const struct intel_crtc_state *crtc_state)
4513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4514 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4515 unsigned long irqflags;
4519 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4520 * enable on ilk+ affect the pipe bottom color as
4521 * well, so we must configure them even if the plane
4524 * On pre-g4x there is no way to gamma correct the
4525 * pipe bottom color but we'll keep on doing this
4526 * anyway so that the crtc state readout works correctly.
4528 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4532 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4533 if (INTEL_GEN(dev_priv) >= 4)
4534 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4536 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4538 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4541 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4544 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4545 enum intel_display_power_domain power_domain;
4546 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4547 intel_wakeref_t wakeref;
4552 * Not 100% correct for planes that can move between pipes,
4553 * but that's only the case for gen2-4 which don't have any
4554 * display power wells.
4556 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4557 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4561 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4563 ret = val & DISPLAY_PLANE_ENABLE;
4565 if (INTEL_GEN(dev_priv) >= 5)
4566 *pipe = plane->pipe;
4568 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4569 DISPPLANE_SEL_PIPE_SHIFT;
4571 intel_display_power_put(dev_priv, power_domain, wakeref);
4576 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4578 struct drm_device *dev = intel_crtc->base.dev;
4579 struct drm_i915_private *dev_priv = to_i915(dev);
4580 unsigned long irqflags;
4582 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4584 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4585 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4586 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4588 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4592 * This function detaches (aka. unbinds) unused scalers in hardware
4594 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4597 const struct intel_crtc_scaler_state *scaler_state =
4598 &crtc_state->scaler_state;
4601 /* loop through and disable scalers that aren't in use */
4602 for (i = 0; i < intel_crtc->num_scalers; i++) {
4603 if (!scaler_state->scalers[i].in_use)
4604 skl_detach_scaler(intel_crtc, i);
4608 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4609 int color_plane, unsigned int rotation)
4612 * The stride is either expressed as a multiple of 64 bytes chunks for
4613 * linear buffers or in number of tiles for tiled buffers.
4615 if (is_surface_linear(fb, color_plane))
4617 else if (drm_rotation_90_or_270(rotation))
4618 return intel_tile_height(fb, color_plane);
4620 return intel_tile_width_bytes(fb, color_plane);
4623 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4626 const struct drm_framebuffer *fb = plane_state->hw.fb;
4627 unsigned int rotation = plane_state->hw.rotation;
4628 u32 stride = plane_state->color_plane[color_plane].stride;
4630 if (color_plane >= fb->format->num_planes)
4633 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4636 static u32 skl_plane_ctl_format(u32 pixel_format)
4638 switch (pixel_format) {
4640 return PLANE_CTL_FORMAT_INDEXED;
4641 case DRM_FORMAT_RGB565:
4642 return PLANE_CTL_FORMAT_RGB_565;
4643 case DRM_FORMAT_XBGR8888:
4644 case DRM_FORMAT_ABGR8888:
4645 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4646 case DRM_FORMAT_XRGB8888:
4647 case DRM_FORMAT_ARGB8888:
4648 return PLANE_CTL_FORMAT_XRGB_8888;
4649 case DRM_FORMAT_XBGR2101010:
4650 case DRM_FORMAT_ABGR2101010:
4651 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4652 case DRM_FORMAT_XRGB2101010:
4653 case DRM_FORMAT_ARGB2101010:
4654 return PLANE_CTL_FORMAT_XRGB_2101010;
4655 case DRM_FORMAT_XBGR16161616F:
4656 case DRM_FORMAT_ABGR16161616F:
4657 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4658 case DRM_FORMAT_XRGB16161616F:
4659 case DRM_FORMAT_ARGB16161616F:
4660 return PLANE_CTL_FORMAT_XRGB_16161616F;
4661 case DRM_FORMAT_XYUV8888:
4662 return PLANE_CTL_FORMAT_XYUV;
4663 case DRM_FORMAT_YUYV:
4664 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4665 case DRM_FORMAT_YVYU:
4666 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4667 case DRM_FORMAT_UYVY:
4668 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4669 case DRM_FORMAT_VYUY:
4670 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4671 case DRM_FORMAT_NV12:
4672 return PLANE_CTL_FORMAT_NV12;
4673 case DRM_FORMAT_P010:
4674 return PLANE_CTL_FORMAT_P010;
4675 case DRM_FORMAT_P012:
4676 return PLANE_CTL_FORMAT_P012;
4677 case DRM_FORMAT_P016:
4678 return PLANE_CTL_FORMAT_P016;
4679 case DRM_FORMAT_Y210:
4680 return PLANE_CTL_FORMAT_Y210;
4681 case DRM_FORMAT_Y212:
4682 return PLANE_CTL_FORMAT_Y212;
4683 case DRM_FORMAT_Y216:
4684 return PLANE_CTL_FORMAT_Y216;
4685 case DRM_FORMAT_XVYU2101010:
4686 return PLANE_CTL_FORMAT_Y410;
4687 case DRM_FORMAT_XVYU12_16161616:
4688 return PLANE_CTL_FORMAT_Y412;
4689 case DRM_FORMAT_XVYU16161616:
4690 return PLANE_CTL_FORMAT_Y416;
4692 MISSING_CASE(pixel_format);
4698 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4700 if (!plane_state->hw.fb->format->has_alpha)
4701 return PLANE_CTL_ALPHA_DISABLE;
4703 switch (plane_state->hw.pixel_blend_mode) {
4704 case DRM_MODE_BLEND_PIXEL_NONE:
4705 return PLANE_CTL_ALPHA_DISABLE;
4706 case DRM_MODE_BLEND_PREMULTI:
4707 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4708 case DRM_MODE_BLEND_COVERAGE:
4709 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4711 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4712 return PLANE_CTL_ALPHA_DISABLE;
4716 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4718 if (!plane_state->hw.fb->format->has_alpha)
4719 return PLANE_COLOR_ALPHA_DISABLE;
4721 switch (plane_state->hw.pixel_blend_mode) {
4722 case DRM_MODE_BLEND_PIXEL_NONE:
4723 return PLANE_COLOR_ALPHA_DISABLE;
4724 case DRM_MODE_BLEND_PREMULTI:
4725 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4726 case DRM_MODE_BLEND_COVERAGE:
4727 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4729 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4730 return PLANE_COLOR_ALPHA_DISABLE;
4734 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4736 switch (fb_modifier) {
4737 case DRM_FORMAT_MOD_LINEAR:
4739 case I915_FORMAT_MOD_X_TILED:
4740 return PLANE_CTL_TILED_X;
4741 case I915_FORMAT_MOD_Y_TILED:
4742 return PLANE_CTL_TILED_Y;
4743 case I915_FORMAT_MOD_Y_TILED_CCS:
4744 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4745 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4746 return PLANE_CTL_TILED_Y |
4747 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4748 PLANE_CTL_CLEAR_COLOR_DISABLE;
4749 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4750 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4751 case I915_FORMAT_MOD_Yf_TILED:
4752 return PLANE_CTL_TILED_YF;
4753 case I915_FORMAT_MOD_Yf_TILED_CCS:
4754 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4756 MISSING_CASE(fb_modifier);
4762 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4765 case DRM_MODE_ROTATE_0:
4768 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4769 * while i915 HW rotation is clockwise, thats why this swapping.
4771 case DRM_MODE_ROTATE_90:
4772 return PLANE_CTL_ROTATE_270;
4773 case DRM_MODE_ROTATE_180:
4774 return PLANE_CTL_ROTATE_180;
4775 case DRM_MODE_ROTATE_270:
4776 return PLANE_CTL_ROTATE_90;
4778 MISSING_CASE(rotate);
4784 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4789 case DRM_MODE_REFLECT_X:
4790 return PLANE_CTL_FLIP_HORIZONTAL;
4791 case DRM_MODE_REFLECT_Y:
4793 MISSING_CASE(reflect);
4799 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4801 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4804 if (crtc_state->uapi.async_flip)
4805 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
4807 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4810 if (crtc_state->gamma_enable)
4811 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4813 if (crtc_state->csc_enable)
4814 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4819 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4820 const struct intel_plane_state *plane_state)
4822 struct drm_i915_private *dev_priv =
4823 to_i915(plane_state->uapi.plane->dev);
4824 const struct drm_framebuffer *fb = plane_state->hw.fb;
4825 unsigned int rotation = plane_state->hw.rotation;
4826 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4829 plane_ctl = PLANE_CTL_ENABLE;
4831 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4832 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4833 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4835 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4836 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4838 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4839 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4842 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4843 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4844 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4846 if (INTEL_GEN(dev_priv) >= 10)
4847 plane_ctl |= cnl_plane_ctl_flip(rotation &
4848 DRM_MODE_REFLECT_MASK);
4850 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4851 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4852 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4853 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4858 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4860 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4861 u32 plane_color_ctl = 0;
4863 if (INTEL_GEN(dev_priv) >= 11)
4864 return plane_color_ctl;
4866 if (crtc_state->gamma_enable)
4867 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4869 if (crtc_state->csc_enable)
4870 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4872 return plane_color_ctl;
4875 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4876 const struct intel_plane_state *plane_state)
4878 struct drm_i915_private *dev_priv =
4879 to_i915(plane_state->uapi.plane->dev);
4880 const struct drm_framebuffer *fb = plane_state->hw.fb;
4881 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4882 u32 plane_color_ctl = 0;
4884 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4885 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4887 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4888 switch (plane_state->hw.color_encoding) {
4889 case DRM_COLOR_YCBCR_BT709:
4890 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4892 case DRM_COLOR_YCBCR_BT2020:
4894 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4898 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4900 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4901 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4902 } else if (fb->format->is_yuv) {
4903 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4906 return plane_color_ctl;
4910 __intel_display_resume(struct drm_device *dev,
4911 struct drm_atomic_state *state,
4912 struct drm_modeset_acquire_ctx *ctx)
4914 struct drm_crtc_state *crtc_state;
4915 struct drm_crtc *crtc;
4918 intel_modeset_setup_hw_state(dev, ctx);
4919 intel_vga_redisable(to_i915(dev));
4925 * We've duplicated the state, pointers to the old state are invalid.
4927 * Don't attempt to use the old state until we commit the duplicated state.
4929 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4931 * Force recalculation even if we restore
4932 * current state. With fast modeset this may not result
4933 * in a modeset when the state is compatible.
4935 crtc_state->mode_changed = true;
4938 /* ignore any reset values/BIOS leftovers in the WM registers */
4939 if (!HAS_GMCH(to_i915(dev)))
4940 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4942 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4944 drm_WARN_ON(dev, ret == -EDEADLK);
4948 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4950 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4951 intel_has_gpu_reset(&dev_priv->gt));
4954 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4956 struct drm_device *dev = &dev_priv->drm;
4957 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4958 struct drm_atomic_state *state;
4961 /* reset doesn't touch the display */
4962 if (!dev_priv->params.force_reset_modeset_test &&
4963 !gpu_reset_clobbers_display(dev_priv))
4966 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4967 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4968 smp_mb__after_atomic();
4969 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4971 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4972 drm_dbg_kms(&dev_priv->drm,
4973 "Modeset potentially stuck, unbreaking through wedging\n");
4974 intel_gt_set_wedged(&dev_priv->gt);
4978 * Need mode_config.mutex so that we don't
4979 * trample ongoing ->detect() and whatnot.
4981 mutex_lock(&dev->mode_config.mutex);
4982 drm_modeset_acquire_init(ctx, 0);
4984 ret = drm_modeset_lock_all_ctx(dev, ctx);
4985 if (ret != -EDEADLK)
4988 drm_modeset_backoff(ctx);
4991 * Disabling the crtcs gracefully seems nicer. Also the
4992 * g33 docs say we should at least disable all the planes.
4994 state = drm_atomic_helper_duplicate_state(dev, ctx);
4995 if (IS_ERR(state)) {
4996 ret = PTR_ERR(state);
4997 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
5002 ret = drm_atomic_helper_disable_all(dev, ctx);
5004 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
5006 drm_atomic_state_put(state);
5010 dev_priv->modeset_restore_state = state;
5011 state->acquire_ctx = ctx;
5014 void intel_finish_reset(struct drm_i915_private *dev_priv)
5016 struct drm_device *dev = &dev_priv->drm;
5017 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5018 struct drm_atomic_state *state;
5021 /* reset doesn't touch the display */
5022 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5025 state = fetch_and_zero(&dev_priv->modeset_restore_state);
5029 /* reset doesn't touch the display */
5030 if (!gpu_reset_clobbers_display(dev_priv)) {
5031 /* for testing only restore the display */
5032 ret = __intel_display_resume(dev, state, ctx);
5034 drm_err(&dev_priv->drm,
5035 "Restoring old state failed with %i\n", ret);
5038 * The display has been reset as well,
5039 * so need a full re-initialization.
5041 intel_pps_unlock_regs_wa(dev_priv);
5042 intel_modeset_init_hw(dev_priv);
5043 intel_init_clock_gating(dev_priv);
5044 intel_hpd_init(dev_priv);
5046 ret = __intel_display_resume(dev, state, ctx);
5048 drm_err(&dev_priv->drm,
5049 "Restoring old state failed with %i\n", ret);
5051 intel_hpd_poll_disable(dev_priv);
5054 drm_atomic_state_put(state);
5056 drm_modeset_drop_locks(ctx);
5057 drm_modeset_acquire_fini(ctx);
5058 mutex_unlock(&dev->mode_config.mutex);
5060 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5063 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5066 enum pipe pipe = crtc->pipe;
5069 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5072 * Display WA #1153: icl
5073 * enable hardware to bypass the alpha math
5074 * and rounding for per-pixel values 00 and 0xff
5076 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5078 * Display WA # 1605353570: icl
5079 * Set the pixel rounding bit to 1 for allowing
5080 * passthrough of Frame buffer pixels unmodified
5083 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5084 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5087 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = to_i915(dev);
5091 enum pipe pipe = crtc->pipe;
5095 /* enable normal train */
5096 reg = FDI_TX_CTL(pipe);
5097 temp = intel_de_read(dev_priv, reg);
5098 if (IS_IVYBRIDGE(dev_priv)) {
5099 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5100 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5102 temp &= ~FDI_LINK_TRAIN_NONE;
5103 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5105 intel_de_write(dev_priv, reg, temp);
5107 reg = FDI_RX_CTL(pipe);
5108 temp = intel_de_read(dev_priv, reg);
5109 if (HAS_PCH_CPT(dev_priv)) {
5110 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5111 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5113 temp &= ~FDI_LINK_TRAIN_NONE;
5114 temp |= FDI_LINK_TRAIN_NONE;
5116 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5118 /* wait one idle pattern time */
5119 intel_de_posting_read(dev_priv, reg);
5122 /* IVB wants error correction enabled */
5123 if (IS_IVYBRIDGE(dev_priv))
5124 intel_de_write(dev_priv, reg,
5125 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5128 /* The FDI link training functions for ILK/Ibexpeak. */
5129 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5130 const struct intel_crtc_state *crtc_state)
5132 struct drm_device *dev = crtc->base.dev;
5133 struct drm_i915_private *dev_priv = to_i915(dev);
5134 enum pipe pipe = crtc->pipe;
5138 /* FDI needs bits from pipe first */
5139 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5143 reg = FDI_RX_IMR(pipe);
5144 temp = intel_de_read(dev_priv, reg);
5145 temp &= ~FDI_RX_SYMBOL_LOCK;
5146 temp &= ~FDI_RX_BIT_LOCK;
5147 intel_de_write(dev_priv, reg, temp);
5148 intel_de_read(dev_priv, reg);
5151 /* enable CPU FDI TX and PCH FDI RX */
5152 reg = FDI_TX_CTL(pipe);
5153 temp = intel_de_read(dev_priv, reg);
5154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5155 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5156 temp &= ~FDI_LINK_TRAIN_NONE;
5157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5158 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5160 reg = FDI_RX_CTL(pipe);
5161 temp = intel_de_read(dev_priv, reg);
5162 temp &= ~FDI_LINK_TRAIN_NONE;
5163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5164 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5166 intel_de_posting_read(dev_priv, reg);
5169 /* Ironlake workaround, enable clock pointer after FDI enable*/
5170 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5171 FDI_RX_PHASE_SYNC_POINTER_OVR);
5172 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5173 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5175 reg = FDI_RX_IIR(pipe);
5176 for (tries = 0; tries < 5; tries++) {
5177 temp = intel_de_read(dev_priv, reg);
5178 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5180 if ((temp & FDI_RX_BIT_LOCK)) {
5181 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5182 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5187 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5190 reg = FDI_TX_CTL(pipe);
5191 temp = intel_de_read(dev_priv, reg);
5192 temp &= ~FDI_LINK_TRAIN_NONE;
5193 temp |= FDI_LINK_TRAIN_PATTERN_2;
5194 intel_de_write(dev_priv, reg, temp);
5196 reg = FDI_RX_CTL(pipe);
5197 temp = intel_de_read(dev_priv, reg);
5198 temp &= ~FDI_LINK_TRAIN_NONE;
5199 temp |= FDI_LINK_TRAIN_PATTERN_2;
5200 intel_de_write(dev_priv, reg, temp);
5202 intel_de_posting_read(dev_priv, reg);
5205 reg = FDI_RX_IIR(pipe);
5206 for (tries = 0; tries < 5; tries++) {
5207 temp = intel_de_read(dev_priv, reg);
5208 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5210 if (temp & FDI_RX_SYMBOL_LOCK) {
5211 intel_de_write(dev_priv, reg,
5212 temp | FDI_RX_SYMBOL_LOCK);
5213 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5218 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5220 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5224 static const int snb_b_fdi_train_param[] = {
5225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5231 /* The FDI link training functions for SNB/Cougarpoint. */
5232 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5233 const struct intel_crtc_state *crtc_state)
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 enum pipe pipe = crtc->pipe;
5241 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5243 reg = FDI_RX_IMR(pipe);
5244 temp = intel_de_read(dev_priv, reg);
5245 temp &= ~FDI_RX_SYMBOL_LOCK;
5246 temp &= ~FDI_RX_BIT_LOCK;
5247 intel_de_write(dev_priv, reg, temp);
5249 intel_de_posting_read(dev_priv, reg);
5252 /* enable CPU FDI TX and PCH FDI RX */
5253 reg = FDI_TX_CTL(pipe);
5254 temp = intel_de_read(dev_priv, reg);
5255 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5256 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5257 temp &= ~FDI_LINK_TRAIN_NONE;
5258 temp |= FDI_LINK_TRAIN_PATTERN_1;
5259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5261 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5262 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5264 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5267 reg = FDI_RX_CTL(pipe);
5268 temp = intel_de_read(dev_priv, reg);
5269 if (HAS_PCH_CPT(dev_priv)) {
5270 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5271 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5273 temp &= ~FDI_LINK_TRAIN_NONE;
5274 temp |= FDI_LINK_TRAIN_PATTERN_1;
5276 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5278 intel_de_posting_read(dev_priv, reg);
5281 for (i = 0; i < 4; i++) {
5282 reg = FDI_TX_CTL(pipe);
5283 temp = intel_de_read(dev_priv, reg);
5284 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5285 temp |= snb_b_fdi_train_param[i];
5286 intel_de_write(dev_priv, reg, temp);
5288 intel_de_posting_read(dev_priv, reg);
5291 for (retry = 0; retry < 5; retry++) {
5292 reg = FDI_RX_IIR(pipe);
5293 temp = intel_de_read(dev_priv, reg);
5294 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5295 if (temp & FDI_RX_BIT_LOCK) {
5296 intel_de_write(dev_priv, reg,
5297 temp | FDI_RX_BIT_LOCK);
5298 drm_dbg_kms(&dev_priv->drm,
5299 "FDI train 1 done.\n");
5308 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5311 reg = FDI_TX_CTL(pipe);
5312 temp = intel_de_read(dev_priv, reg);
5313 temp &= ~FDI_LINK_TRAIN_NONE;
5314 temp |= FDI_LINK_TRAIN_PATTERN_2;
5315 if (IS_GEN(dev_priv, 6)) {
5316 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5318 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5320 intel_de_write(dev_priv, reg, temp);
5322 reg = FDI_RX_CTL(pipe);
5323 temp = intel_de_read(dev_priv, reg);
5324 if (HAS_PCH_CPT(dev_priv)) {
5325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5326 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5328 temp &= ~FDI_LINK_TRAIN_NONE;
5329 temp |= FDI_LINK_TRAIN_PATTERN_2;
5331 intel_de_write(dev_priv, reg, temp);
5333 intel_de_posting_read(dev_priv, reg);
5336 for (i = 0; i < 4; i++) {
5337 reg = FDI_TX_CTL(pipe);
5338 temp = intel_de_read(dev_priv, reg);
5339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5340 temp |= snb_b_fdi_train_param[i];
5341 intel_de_write(dev_priv, reg, temp);
5343 intel_de_posting_read(dev_priv, reg);
5346 for (retry = 0; retry < 5; retry++) {
5347 reg = FDI_RX_IIR(pipe);
5348 temp = intel_de_read(dev_priv, reg);
5349 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5350 if (temp & FDI_RX_SYMBOL_LOCK) {
5351 intel_de_write(dev_priv, reg,
5352 temp | FDI_RX_SYMBOL_LOCK);
5353 drm_dbg_kms(&dev_priv->drm,
5354 "FDI train 2 done.\n");
5363 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5365 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5368 /* Manual link training for Ivy Bridge A0 parts */
5369 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5370 const struct intel_crtc_state *crtc_state)
5372 struct drm_device *dev = crtc->base.dev;
5373 struct drm_i915_private *dev_priv = to_i915(dev);
5374 enum pipe pipe = crtc->pipe;
5378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5380 reg = FDI_RX_IMR(pipe);
5381 temp = intel_de_read(dev_priv, reg);
5382 temp &= ~FDI_RX_SYMBOL_LOCK;
5383 temp &= ~FDI_RX_BIT_LOCK;
5384 intel_de_write(dev_priv, reg, temp);
5386 intel_de_posting_read(dev_priv, reg);
5389 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5390 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5392 /* Try each vswing and preemphasis setting twice before moving on */
5393 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5394 /* disable first in case we need to retry */
5395 reg = FDI_TX_CTL(pipe);
5396 temp = intel_de_read(dev_priv, reg);
5397 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5398 temp &= ~FDI_TX_ENABLE;
5399 intel_de_write(dev_priv, reg, temp);
5401 reg = FDI_RX_CTL(pipe);
5402 temp = intel_de_read(dev_priv, reg);
5403 temp &= ~FDI_LINK_TRAIN_AUTO;
5404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5405 temp &= ~FDI_RX_ENABLE;
5406 intel_de_write(dev_priv, reg, temp);
5408 /* enable CPU FDI TX and PCH FDI RX */
5409 reg = FDI_TX_CTL(pipe);
5410 temp = intel_de_read(dev_priv, reg);
5411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5412 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5413 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5415 temp |= snb_b_fdi_train_param[j/2];
5416 temp |= FDI_COMPOSITE_SYNC;
5417 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5419 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5422 reg = FDI_RX_CTL(pipe);
5423 temp = intel_de_read(dev_priv, reg);
5424 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5425 temp |= FDI_COMPOSITE_SYNC;
5426 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5428 intel_de_posting_read(dev_priv, reg);
5429 udelay(1); /* should be 0.5us */
5431 for (i = 0; i < 4; i++) {
5432 reg = FDI_RX_IIR(pipe);
5433 temp = intel_de_read(dev_priv, reg);
5434 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5436 if (temp & FDI_RX_BIT_LOCK ||
5437 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5438 intel_de_write(dev_priv, reg,
5439 temp | FDI_RX_BIT_LOCK);
5440 drm_dbg_kms(&dev_priv->drm,
5441 "FDI train 1 done, level %i.\n",
5445 udelay(1); /* should be 0.5us */
5448 drm_dbg_kms(&dev_priv->drm,
5449 "FDI train 1 fail on vswing %d\n", j / 2);
5454 reg = FDI_TX_CTL(pipe);
5455 temp = intel_de_read(dev_priv, reg);
5456 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5457 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5458 intel_de_write(dev_priv, reg, temp);
5460 reg = FDI_RX_CTL(pipe);
5461 temp = intel_de_read(dev_priv, reg);
5462 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5463 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5464 intel_de_write(dev_priv, reg, temp);
5466 intel_de_posting_read(dev_priv, reg);
5467 udelay(2); /* should be 1.5us */
5469 for (i = 0; i < 4; i++) {
5470 reg = FDI_RX_IIR(pipe);
5471 temp = intel_de_read(dev_priv, reg);
5472 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5474 if (temp & FDI_RX_SYMBOL_LOCK ||
5475 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5476 intel_de_write(dev_priv, reg,
5477 temp | FDI_RX_SYMBOL_LOCK);
5478 drm_dbg_kms(&dev_priv->drm,
5479 "FDI train 2 done, level %i.\n",
5483 udelay(2); /* should be 1.5us */
5486 drm_dbg_kms(&dev_priv->drm,
5487 "FDI train 2 fail on vswing %d\n", j / 2);
5491 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5494 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5497 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5498 enum pipe pipe = intel_crtc->pipe;
5502 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5503 reg = FDI_RX_CTL(pipe);
5504 temp = intel_de_read(dev_priv, reg);
5505 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5506 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5507 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5508 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5510 intel_de_posting_read(dev_priv, reg);
5513 /* Switch from Rawclk to PCDclk */
5514 temp = intel_de_read(dev_priv, reg);
5515 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5517 intel_de_posting_read(dev_priv, reg);
5520 /* Enable CPU FDI TX PLL, always on for Ironlake */
5521 reg = FDI_TX_CTL(pipe);
5522 temp = intel_de_read(dev_priv, reg);
5523 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5524 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5526 intel_de_posting_read(dev_priv, reg);
5531 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5533 struct drm_device *dev = intel_crtc->base.dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 enum pipe pipe = intel_crtc->pipe;
5539 /* Switch from PCDclk to Rawclk */
5540 reg = FDI_RX_CTL(pipe);
5541 temp = intel_de_read(dev_priv, reg);
5542 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5544 /* Disable CPU FDI TX PLL */
5545 reg = FDI_TX_CTL(pipe);
5546 temp = intel_de_read(dev_priv, reg);
5547 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5549 intel_de_posting_read(dev_priv, reg);
5552 reg = FDI_RX_CTL(pipe);
5553 temp = intel_de_read(dev_priv, reg);
5554 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5556 /* Wait for the clocks to turn off. */
5557 intel_de_posting_read(dev_priv, reg);
5561 static void ilk_fdi_disable(struct intel_crtc *crtc)
5563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5564 enum pipe pipe = crtc->pipe;
5568 /* disable CPU FDI tx and PCH FDI rx */
5569 reg = FDI_TX_CTL(pipe);
5570 temp = intel_de_read(dev_priv, reg);
5571 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5572 intel_de_posting_read(dev_priv, reg);
5574 reg = FDI_RX_CTL(pipe);
5575 temp = intel_de_read(dev_priv, reg);
5576 temp &= ~(0x7 << 16);
5577 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5578 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5580 intel_de_posting_read(dev_priv, reg);
5583 /* Ironlake workaround, disable clock pointer after downing FDI */
5584 if (HAS_PCH_IBX(dev_priv))
5585 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5586 FDI_RX_PHASE_SYNC_POINTER_OVR);
5588 /* still set train pattern 1 */
5589 reg = FDI_TX_CTL(pipe);
5590 temp = intel_de_read(dev_priv, reg);
5591 temp &= ~FDI_LINK_TRAIN_NONE;
5592 temp |= FDI_LINK_TRAIN_PATTERN_1;
5593 intel_de_write(dev_priv, reg, temp);
5595 reg = FDI_RX_CTL(pipe);
5596 temp = intel_de_read(dev_priv, reg);
5597 if (HAS_PCH_CPT(dev_priv)) {
5598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5601 temp &= ~FDI_LINK_TRAIN_NONE;
5602 temp |= FDI_LINK_TRAIN_PATTERN_1;
5604 /* BPC in FDI rx is consistent with that in PIPECONF */
5605 temp &= ~(0x07 << 16);
5606 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5607 intel_de_write(dev_priv, reg, temp);
5609 intel_de_posting_read(dev_priv, reg);
5613 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5615 struct drm_crtc *crtc;
5618 drm_for_each_crtc(crtc, &dev_priv->drm) {
5619 struct drm_crtc_commit *commit;
5620 spin_lock(&crtc->commit_lock);
5621 commit = list_first_entry_or_null(&crtc->commit_list,
5622 struct drm_crtc_commit, commit_entry);
5623 cleanup_done = commit ?
5624 try_wait_for_completion(&commit->cleanup_done) : true;
5625 spin_unlock(&crtc->commit_lock);
5630 drm_crtc_wait_one_vblank(crtc);
5638 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5642 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5644 mutex_lock(&dev_priv->sb_lock);
5646 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5647 temp |= SBI_SSCCTL_DISABLE;
5648 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5650 mutex_unlock(&dev_priv->sb_lock);
5653 /* Program iCLKIP clock to the desired frequency */
5654 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5658 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5659 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5662 lpt_disable_iclkip(dev_priv);
5664 /* The iCLK virtual clock root frequency is in MHz,
5665 * but the adjusted_mode->crtc_clock in in KHz. To get the
5666 * divisors, it is necessary to divide one by another, so we
5667 * convert the virtual clock precision to KHz here for higher
5670 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5671 u32 iclk_virtual_root_freq = 172800 * 1000;
5672 u32 iclk_pi_range = 64;
5673 u32 desired_divisor;
5675 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5677 divsel = (desired_divisor / iclk_pi_range) - 2;
5678 phaseinc = desired_divisor % iclk_pi_range;
5681 * Near 20MHz is a corner case which is
5682 * out of range for the 7-bit divisor
5688 /* This should not happen with any sane values */
5689 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5690 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5691 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5692 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5694 drm_dbg_kms(&dev_priv->drm,
5695 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5696 clock, auxdiv, divsel, phasedir, phaseinc);
5698 mutex_lock(&dev_priv->sb_lock);
5700 /* Program SSCDIVINTPHASE6 */
5701 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5702 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5703 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5704 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5705 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5706 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5707 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5708 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5710 /* Program SSCAUXDIV */
5711 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5712 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5713 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5714 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5716 /* Enable modulator and associated divider */
5717 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5718 temp &= ~SBI_SSCCTL_DISABLE;
5719 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5721 mutex_unlock(&dev_priv->sb_lock);
5723 /* Wait for initialization time */
5726 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5729 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5731 u32 divsel, phaseinc, auxdiv;
5732 u32 iclk_virtual_root_freq = 172800 * 1000;
5733 u32 iclk_pi_range = 64;
5734 u32 desired_divisor;
5737 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5740 mutex_lock(&dev_priv->sb_lock);
5742 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5743 if (temp & SBI_SSCCTL_DISABLE) {
5744 mutex_unlock(&dev_priv->sb_lock);
5748 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5749 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5750 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5751 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5752 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5754 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5755 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5756 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5758 mutex_unlock(&dev_priv->sb_lock);
5760 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5762 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5763 desired_divisor << auxdiv);
5766 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5767 enum pipe pch_transcoder)
5769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5771 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5773 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5774 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5775 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5776 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5777 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5778 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5780 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5781 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5782 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5783 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5784 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5785 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5786 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5787 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5790 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5794 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5795 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5798 drm_WARN_ON(&dev_priv->drm,
5799 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5801 drm_WARN_ON(&dev_priv->drm,
5802 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5805 temp &= ~FDI_BC_BIFURCATION_SELECT;
5807 temp |= FDI_BC_BIFURCATION_SELECT;
5809 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5810 enable ? "en" : "dis");
5811 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5812 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5815 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5818 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5820 switch (crtc->pipe) {
5824 if (crtc_state->fdi_lanes > 2)
5825 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5827 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5831 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5840 * Finds the encoder associated with the given CRTC. This can only be
5841 * used when we know that the CRTC isn't feeding multiple encoders!
5843 static struct intel_encoder *
5844 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5845 const struct intel_crtc_state *crtc_state)
5847 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5848 const struct drm_connector_state *connector_state;
5849 const struct drm_connector *connector;
5850 struct intel_encoder *encoder = NULL;
5851 int num_encoders = 0;
5854 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5855 if (connector_state->crtc != &crtc->base)
5858 encoder = to_intel_encoder(connector_state->best_encoder);
5862 drm_WARN(encoder->base.dev, num_encoders != 1,
5863 "%d encoders for pipe %c\n",
5864 num_encoders, pipe_name(crtc->pipe));
5870 * Enable PCH resources required for PCH ports:
5872 * - FDI training & RX/TX
5873 * - update transcoder timings
5874 * - DP transcoding bits
5877 static void ilk_pch_enable(const struct intel_atomic_state *state,
5878 const struct intel_crtc_state *crtc_state)
5880 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5881 struct drm_device *dev = crtc->base.dev;
5882 struct drm_i915_private *dev_priv = to_i915(dev);
5883 enum pipe pipe = crtc->pipe;
5886 assert_pch_transcoder_disabled(dev_priv, pipe);
5888 if (IS_IVYBRIDGE(dev_priv))
5889 ivb_update_fdi_bc_bifurcation(crtc_state);
5891 /* Write the TU size bits before fdi link training, so that error
5892 * detection works. */
5893 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5894 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5896 /* For PCH output, training FDI link */
5897 dev_priv->display.fdi_link_train(crtc, crtc_state);
5899 /* We need to program the right clock selection before writing the pixel
5900 * mutliplier into the DPLL. */
5901 if (HAS_PCH_CPT(dev_priv)) {
5904 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5905 temp |= TRANS_DPLL_ENABLE(pipe);
5906 sel = TRANS_DPLLB_SEL(pipe);
5907 if (crtc_state->shared_dpll ==
5908 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5912 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5915 /* XXX: pch pll's can be enabled any time before we enable the PCH
5916 * transcoder, and we actually should do this to not upset any PCH
5917 * transcoder that already use the clock when we share it.
5919 * Note that enable_shared_dpll tries to do the right thing, but
5920 * get_shared_dpll unconditionally resets the pll - we need that to have
5921 * the right LVDS enable sequence. */
5922 intel_enable_shared_dpll(crtc_state);
5924 /* set transcoder timing, panel must allow it */
5925 assert_panel_unlocked(dev_priv, pipe);
5926 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5928 intel_fdi_normal_train(crtc);
5930 /* For PCH DP, enable TRANS_DP_CTL */
5931 if (HAS_PCH_CPT(dev_priv) &&
5932 intel_crtc_has_dp_encoder(crtc_state)) {
5933 const struct drm_display_mode *adjusted_mode =
5934 &crtc_state->hw.adjusted_mode;
5935 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5936 i915_reg_t reg = TRANS_DP_CTL(pipe);
5939 temp = intel_de_read(dev_priv, reg);
5940 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5941 TRANS_DP_SYNC_MASK |
5943 temp |= TRANS_DP_OUTPUT_ENABLE;
5944 temp |= bpc << 9; /* same format but at 11:9 */
5946 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5947 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5948 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5949 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5951 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5952 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5953 temp |= TRANS_DP_PORT_SEL(port);
5955 intel_de_write(dev_priv, reg, temp);
5958 ilk_enable_pch_transcoder(crtc_state);
5961 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5963 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5965 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5967 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5969 lpt_program_iclkip(crtc_state);
5971 /* Set transcoder timing. */
5972 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5974 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5977 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5980 i915_reg_t dslreg = PIPEDSL(pipe);
5983 temp = intel_de_read(dev_priv, dslreg);
5985 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5986 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5987 drm_err(&dev_priv->drm,
5988 "mode set failed: pipe %c stuck\n",
5994 * The hardware phase 0.0 refers to the center of the pixel.
5995 * We want to start from the top/left edge which is phase
5996 * -0.5. That matches how the hardware calculates the scaling
5997 * factors (from top-left of the first pixel to bottom-right
5998 * of the last pixel, as opposed to the pixel centers).
6000 * For 4:2:0 subsampled chroma planes we obviously have to
6001 * adjust that so that the chroma sample position lands in
6004 * Note that for packed YCbCr 4:2:2 formats there is no way to
6005 * control chroma siting. The hardware simply replicates the
6006 * chroma samples for both of the luma samples, and thus we don't
6007 * actually get the expected MPEG2 chroma siting convention :(
6008 * The same behaviour is observed on pre-SKL platforms as well.
6010 * Theory behind the formula (note that we ignore sub-pixel
6011 * source coordinates):
6012 * s = source sample position
6013 * d = destination sample position
6018 * | | 1.5 (initial phase)
6026 * | -0.375 (initial phase)
6033 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6035 int phase = -0x8000;
6039 phase += (sub - 1) * 0x8000 / sub;
6041 phase += scale / (2 * sub);
6044 * Hardware initial phase limited to [-0.5:1.5].
6045 * Since the max hardware scale factor is 3.0, we
6046 * should never actually excdeed 1.0 here.
6048 WARN_ON(phase < -0x8000 || phase > 0x18000);
6051 phase = 0x10000 + phase;
6053 trip = PS_PHASE_TRIP;
6055 return ((phase >> 2) & PS_PHASE_MASK) | trip;
6058 #define SKL_MIN_SRC_W 8
6059 #define SKL_MAX_SRC_W 4096
6060 #define SKL_MIN_SRC_H 8
6061 #define SKL_MAX_SRC_H 4096
6062 #define SKL_MIN_DST_W 8
6063 #define SKL_MAX_DST_W 4096
6064 #define SKL_MIN_DST_H 8
6065 #define SKL_MAX_DST_H 4096
6066 #define ICL_MAX_SRC_W 5120
6067 #define ICL_MAX_SRC_H 4096
6068 #define ICL_MAX_DST_W 5120
6069 #define ICL_MAX_DST_H 4096
6070 #define SKL_MIN_YUV_420_SRC_W 16
6071 #define SKL_MIN_YUV_420_SRC_H 16
6074 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6075 unsigned int scaler_user, int *scaler_id,
6076 int src_w, int src_h, int dst_w, int dst_h,
6077 const struct drm_format_info *format,
6078 u64 modifier, bool need_scaler)
6080 struct intel_crtc_scaler_state *scaler_state =
6081 &crtc_state->scaler_state;
6082 struct intel_crtc *intel_crtc =
6083 to_intel_crtc(crtc_state->uapi.crtc);
6084 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6085 const struct drm_display_mode *adjusted_mode =
6086 &crtc_state->hw.adjusted_mode;
6089 * Src coordinates are already rotated by 270 degrees for
6090 * the 90/270 degree plane rotation cases (to match the
6091 * GTT mapping), hence no need to account for rotation here.
6093 if (src_w != dst_w || src_h != dst_h)
6097 * Scaling/fitting not supported in IF-ID mode in GEN9+
6098 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6099 * Once NV12 is enabled, handle it here while allocating scaler
6102 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6103 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6104 drm_dbg_kms(&dev_priv->drm,
6105 "Pipe/Plane scaling not supported with IF-ID mode\n");
6110 * if plane is being disabled or scaler is no more required or force detach
6111 * - free scaler binded to this plane/crtc
6112 * - in order to do this, update crtc->scaler_usage
6114 * Here scaler state in crtc_state is set free so that
6115 * scaler can be assigned to other user. Actual register
6116 * update to free the scaler is done in plane/panel-fit programming.
6117 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6119 if (force_detach || !need_scaler) {
6120 if (*scaler_id >= 0) {
6121 scaler_state->scaler_users &= ~(1 << scaler_user);
6122 scaler_state->scalers[*scaler_id].in_use = 0;
6124 drm_dbg_kms(&dev_priv->drm,
6125 "scaler_user index %u.%u: "
6126 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6127 intel_crtc->pipe, scaler_user, *scaler_id,
6128 scaler_state->scaler_users);
6134 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6135 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6136 drm_dbg_kms(&dev_priv->drm,
6137 "Planar YUV: src dimensions not met\n");
6142 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6143 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6144 (INTEL_GEN(dev_priv) >= 11 &&
6145 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6146 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6147 (INTEL_GEN(dev_priv) < 11 &&
6148 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6149 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6150 drm_dbg_kms(&dev_priv->drm,
6151 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6152 "size is out of scaler range\n",
6153 intel_crtc->pipe, scaler_user, src_w, src_h,
6158 /* mark this plane as a scaler user in crtc_state */
6159 scaler_state->scaler_users |= (1 << scaler_user);
6160 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6161 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6162 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6163 scaler_state->scaler_users);
6168 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6170 const struct drm_display_mode *adjusted_mode =
6171 &crtc_state->hw.adjusted_mode;
6174 if (crtc_state->pch_pfit.enabled) {
6175 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6176 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6178 width = adjusted_mode->crtc_hdisplay;
6179 height = adjusted_mode->crtc_vdisplay;
6182 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6184 &crtc_state->scaler_state.scaler_id,
6185 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6186 width, height, NULL, 0,
6187 crtc_state->pch_pfit.enabled);
6191 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6192 * @crtc_state: crtc's scaler state
6193 * @plane_state: atomic plane state to update
6196 * 0 - scaler_usage updated successfully
6197 * error - requested scaling cannot be supported or other error condition
6199 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6200 struct intel_plane_state *plane_state)
6202 struct intel_plane *intel_plane =
6203 to_intel_plane(plane_state->uapi.plane);
6204 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6205 struct drm_framebuffer *fb = plane_state->hw.fb;
6207 bool force_detach = !fb || !plane_state->uapi.visible;
6208 bool need_scaler = false;
6210 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6211 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6212 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6215 ret = skl_update_scaler(crtc_state, force_detach,
6216 drm_plane_index(&intel_plane->base),
6217 &plane_state->scaler_id,
6218 drm_rect_width(&plane_state->uapi.src) >> 16,
6219 drm_rect_height(&plane_state->uapi.src) >> 16,
6220 drm_rect_width(&plane_state->uapi.dst),
6221 drm_rect_height(&plane_state->uapi.dst),
6222 fb ? fb->format : NULL,
6223 fb ? fb->modifier : 0,
6226 if (ret || plane_state->scaler_id < 0)
6229 /* check colorkey */
6230 if (plane_state->ckey.flags) {
6231 drm_dbg_kms(&dev_priv->drm,
6232 "[PLANE:%d:%s] scaling with color key not allowed",
6233 intel_plane->base.base.id,
6234 intel_plane->base.name);
6238 /* Check src format */
6239 switch (fb->format->format) {
6240 case DRM_FORMAT_RGB565:
6241 case DRM_FORMAT_XBGR8888:
6242 case DRM_FORMAT_XRGB8888:
6243 case DRM_FORMAT_ABGR8888:
6244 case DRM_FORMAT_ARGB8888:
6245 case DRM_FORMAT_XRGB2101010:
6246 case DRM_FORMAT_XBGR2101010:
6247 case DRM_FORMAT_ARGB2101010:
6248 case DRM_FORMAT_ABGR2101010:
6249 case DRM_FORMAT_YUYV:
6250 case DRM_FORMAT_YVYU:
6251 case DRM_FORMAT_UYVY:
6252 case DRM_FORMAT_VYUY:
6253 case DRM_FORMAT_NV12:
6254 case DRM_FORMAT_XYUV8888:
6255 case DRM_FORMAT_P010:
6256 case DRM_FORMAT_P012:
6257 case DRM_FORMAT_P016:
6258 case DRM_FORMAT_Y210:
6259 case DRM_FORMAT_Y212:
6260 case DRM_FORMAT_Y216:
6261 case DRM_FORMAT_XVYU2101010:
6262 case DRM_FORMAT_XVYU12_16161616:
6263 case DRM_FORMAT_XVYU16161616:
6265 case DRM_FORMAT_XBGR16161616F:
6266 case DRM_FORMAT_ABGR16161616F:
6267 case DRM_FORMAT_XRGB16161616F:
6268 case DRM_FORMAT_ARGB16161616F:
6269 if (INTEL_GEN(dev_priv) >= 11)
6273 drm_dbg_kms(&dev_priv->drm,
6274 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6275 intel_plane->base.base.id, intel_plane->base.name,
6276 fb->base.id, fb->format->format);
6283 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6285 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6288 for (i = 0; i < crtc->num_scalers; i++)
6289 skl_detach_scaler(crtc, i);
6292 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6294 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6296 const struct intel_crtc_scaler_state *scaler_state =
6297 &crtc_state->scaler_state;
6298 struct drm_rect src = {
6299 .x2 = crtc_state->pipe_src_w << 16,
6300 .y2 = crtc_state->pipe_src_h << 16,
6302 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6303 u16 uv_rgb_hphase, uv_rgb_vphase;
6304 enum pipe pipe = crtc->pipe;
6305 int width = drm_rect_width(dst);
6306 int height = drm_rect_height(dst);
6310 unsigned long irqflags;
6313 if (!crtc_state->pch_pfit.enabled)
6316 if (drm_WARN_ON(&dev_priv->drm,
6317 crtc_state->scaler_state.scaler_id < 0))
6320 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6321 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6323 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6324 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6326 id = scaler_state->scaler_id;
6328 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6330 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6331 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6332 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6333 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6334 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6335 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6336 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6338 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6339 width << 16 | height);
6341 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6344 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6346 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6348 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6349 enum pipe pipe = crtc->pipe;
6350 int width = drm_rect_width(dst);
6351 int height = drm_rect_height(dst);
6355 if (!crtc_state->pch_pfit.enabled)
6358 /* Force use of hard-coded filter coefficients
6359 * as some pre-programmed values are broken,
6362 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6363 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6364 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6366 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6368 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6369 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6372 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6374 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6375 struct drm_device *dev = crtc->base.dev;
6376 struct drm_i915_private *dev_priv = to_i915(dev);
6378 if (!crtc_state->ips_enabled)
6382 * We can only enable IPS after we enable a plane and wait for a vblank
6383 * This function is called from post_plane_update, which is run after
6386 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6388 if (IS_BROADWELL(dev_priv)) {
6389 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6390 IPS_ENABLE | IPS_PCODE_CONTROL));
6391 /* Quoting Art Runyan: "its not safe to expect any particular
6392 * value in IPS_CTL bit 31 after enabling IPS through the
6393 * mailbox." Moreover, the mailbox may return a bogus state,
6394 * so we need to just enable it and continue on.
6397 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6398 /* The bit only becomes 1 in the next vblank, so this wait here
6399 * is essentially intel_wait_for_vblank. If we don't have this
6400 * and don't wait for vblanks until the end of crtc_enable, then
6401 * the HW state readout code will complain that the expected
6402 * IPS_CTL value is not the one we read. */
6403 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6404 drm_err(&dev_priv->drm,
6405 "Timed out waiting for IPS enable\n");
6409 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6412 struct drm_device *dev = crtc->base.dev;
6413 struct drm_i915_private *dev_priv = to_i915(dev);
6415 if (!crtc_state->ips_enabled)
6418 if (IS_BROADWELL(dev_priv)) {
6420 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6422 * Wait for PCODE to finish disabling IPS. The BSpec specified
6423 * 42ms timeout value leads to occasional timeouts so use 100ms
6426 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6427 drm_err(&dev_priv->drm,
6428 "Timed out waiting for IPS disable\n");
6430 intel_de_write(dev_priv, IPS_CTL, 0);
6431 intel_de_posting_read(dev_priv, IPS_CTL);
6434 /* We need to wait for a vblank before we can disable the plane. */
6435 intel_wait_for_vblank(dev_priv, crtc->pipe);
6438 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6440 if (intel_crtc->overlay)
6441 (void) intel_overlay_switch_off(intel_crtc->overlay);
6443 /* Let userspace switch the overlay on again. In most cases userspace
6444 * has to recompute where to put it anyway.
6448 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6449 const struct intel_crtc_state *new_crtc_state)
6451 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6454 if (!old_crtc_state->ips_enabled)
6457 if (needs_modeset(new_crtc_state))
6461 * Workaround : Do not read or write the pipe palette/gamma data while
6462 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6464 * Disable IPS before we program the LUT.
6466 if (IS_HASWELL(dev_priv) &&
6467 (new_crtc_state->uapi.color_mgmt_changed ||
6468 new_crtc_state->update_pipe) &&
6469 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6472 return !new_crtc_state->ips_enabled;
6475 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6476 const struct intel_crtc_state *new_crtc_state)
6478 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6481 if (!new_crtc_state->ips_enabled)
6484 if (needs_modeset(new_crtc_state))
6488 * Workaround : Do not read or write the pipe palette/gamma data while
6489 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6491 * Re-enable IPS after the LUT has been programmed.
6493 if (IS_HASWELL(dev_priv) &&
6494 (new_crtc_state->uapi.color_mgmt_changed ||
6495 new_crtc_state->update_pipe) &&
6496 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6500 * We can't read out IPS on broadwell, assume the worst and
6501 * forcibly enable IPS on the first fastset.
6503 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6506 return !old_crtc_state->ips_enabled;
6509 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6511 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6513 if (!crtc_state->nv12_planes)
6516 /* WA Display #0827: Gen9:all */
6517 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6523 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6525 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6527 /* Wa_2006604312:icl,ehl */
6528 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6534 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6535 const struct intel_crtc_state *new_crtc_state)
6537 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6538 new_crtc_state->active_planes;
6541 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6542 const struct intel_crtc_state *new_crtc_state)
6544 return old_crtc_state->active_planes &&
6545 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6548 static void intel_post_plane_update(struct intel_atomic_state *state,
6549 struct intel_crtc *crtc)
6551 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6552 const struct intel_crtc_state *old_crtc_state =
6553 intel_atomic_get_old_crtc_state(state, crtc);
6554 const struct intel_crtc_state *new_crtc_state =
6555 intel_atomic_get_new_crtc_state(state, crtc);
6556 enum pipe pipe = crtc->pipe;
6558 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6560 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6561 intel_update_watermarks(crtc);
6563 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6564 hsw_enable_ips(new_crtc_state);
6566 intel_fbc_post_update(state, crtc);
6568 if (needs_nv12_wa(old_crtc_state) &&
6569 !needs_nv12_wa(new_crtc_state))
6570 skl_wa_827(dev_priv, pipe, false);
6572 if (needs_scalerclk_wa(old_crtc_state) &&
6573 !needs_scalerclk_wa(new_crtc_state))
6574 icl_wa_scalerclkgating(dev_priv, pipe, false);
6577 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
6578 struct intel_crtc *crtc,
6579 const struct intel_crtc_state *new_crtc_state)
6581 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6582 struct intel_plane *plane;
6583 struct intel_plane_state *new_plane_state;
6586 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
6587 u32 update_mask = new_crtc_state->update_planes;
6588 u32 plane_ctl, surf_addr;
6589 enum plane_id plane_id;
6590 unsigned long irqflags;
6593 if (crtc->pipe != plane->pipe ||
6594 !(update_mask & BIT(plane->id)))
6597 plane_id = plane->id;
6600 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6601 plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
6602 surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
6604 plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
6606 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
6607 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
6608 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6611 intel_wait_for_vblank(dev_priv, crtc->pipe);
6614 static void intel_pre_plane_update(struct intel_atomic_state *state,
6615 struct intel_crtc *crtc)
6617 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6618 const struct intel_crtc_state *old_crtc_state =
6619 intel_atomic_get_old_crtc_state(state, crtc);
6620 const struct intel_crtc_state *new_crtc_state =
6621 intel_atomic_get_new_crtc_state(state, crtc);
6622 enum pipe pipe = crtc->pipe;
6624 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6625 hsw_disable_ips(old_crtc_state);
6627 if (intel_fbc_pre_update(state, crtc))
6628 intel_wait_for_vblank(dev_priv, pipe);
6630 /* Display WA 827 */
6631 if (!needs_nv12_wa(old_crtc_state) &&
6632 needs_nv12_wa(new_crtc_state))
6633 skl_wa_827(dev_priv, pipe, true);
6635 /* Wa_2006604312:icl,ehl */
6636 if (!needs_scalerclk_wa(old_crtc_state) &&
6637 needs_scalerclk_wa(new_crtc_state))
6638 icl_wa_scalerclkgating(dev_priv, pipe, true);
6641 * Vblank time updates from the shadow to live plane control register
6642 * are blocked if the memory self-refresh mode is active at that
6643 * moment. So to make sure the plane gets truly disabled, disable
6644 * first the self-refresh mode. The self-refresh enable bit in turn
6645 * will be checked/applied by the HW only at the next frame start
6646 * event which is after the vblank start event, so we need to have a
6647 * wait-for-vblank between disabling the plane and the pipe.
6649 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6650 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6651 intel_wait_for_vblank(dev_priv, pipe);
6654 * IVB workaround: must disable low power watermarks for at least
6655 * one frame before enabling scaling. LP watermarks can be re-enabled
6656 * when scaling is disabled.
6658 * WaCxSRDisabledForSpriteScaling:ivb
6660 if (old_crtc_state->hw.active &&
6661 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6662 intel_wait_for_vblank(dev_priv, pipe);
6665 * If we're doing a modeset we don't need to do any
6666 * pre-vblank watermark programming here.
6668 if (!needs_modeset(new_crtc_state)) {
6670 * For platforms that support atomic watermarks, program the
6671 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6672 * will be the intermediate values that are safe for both pre- and
6673 * post- vblank; when vblank happens, the 'active' values will be set
6674 * to the final 'target' values and we'll do this again to get the
6675 * optimal watermarks. For gen9+ platforms, the values we program here
6676 * will be the final target values which will get automatically latched
6677 * at vblank time; no further programming will be necessary.
6679 * If a platform hasn't been transitioned to atomic watermarks yet,
6680 * we'll continue to update watermarks the old way, if flags tell
6683 if (dev_priv->display.initial_watermarks)
6684 dev_priv->display.initial_watermarks(state, crtc);
6685 else if (new_crtc_state->update_wm_pre)
6686 intel_update_watermarks(crtc);
6690 * Gen2 reports pipe underruns whenever all planes are disabled.
6691 * So disable underrun reporting before all the planes get disabled.
6693 * We do this after .initial_watermarks() so that we have a
6694 * chance of catching underruns with the intermediate watermarks
6695 * vs. the old plane configuration.
6697 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6698 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6701 * WA for platforms where async address update enable bit
6702 * is double buffered and only latched at start of vblank.
6704 if (old_crtc_state->uapi.async_flip &&
6705 !new_crtc_state->uapi.async_flip &&
6706 IS_GEN_RANGE(dev_priv, 9, 10))
6707 skl_disable_async_flip_wa(state, crtc, new_crtc_state);
6710 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6711 struct intel_crtc *crtc)
6713 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6714 const struct intel_crtc_state *new_crtc_state =
6715 intel_atomic_get_new_crtc_state(state, crtc);
6716 unsigned int update_mask = new_crtc_state->update_planes;
6717 const struct intel_plane_state *old_plane_state;
6718 struct intel_plane *plane;
6719 unsigned fb_bits = 0;
6722 intel_crtc_dpms_overlay_disable(crtc);
6724 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6725 if (crtc->pipe != plane->pipe ||
6726 !(update_mask & BIT(plane->id)))
6729 intel_disable_plane(plane, new_crtc_state);
6731 if (old_plane_state->uapi.visible)
6732 fb_bits |= plane->frontbuffer_bit;
6735 intel_frontbuffer_flip(dev_priv, fb_bits);
6739 * intel_connector_primary_encoder - get the primary encoder for a connector
6740 * @connector: connector for which to return the encoder
6742 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6743 * all connectors to their encoder, except for DP-MST connectors which have
6744 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6745 * pointed to by as many DP-MST connectors as there are pipes.
6747 static struct intel_encoder *
6748 intel_connector_primary_encoder(struct intel_connector *connector)
6750 struct intel_encoder *encoder;
6752 if (connector->mst_port)
6753 return &dp_to_dig_port(connector->mst_port)->base;
6755 encoder = intel_attached_encoder(connector);
6756 drm_WARN_ON(connector->base.dev, !encoder);
6761 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6763 struct drm_connector_state *new_conn_state;
6764 struct drm_connector *connector;
6767 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6769 struct intel_connector *intel_connector;
6770 struct intel_encoder *encoder;
6771 struct intel_crtc *crtc;
6773 if (!intel_connector_needs_modeset(state, connector))
6776 intel_connector = to_intel_connector(connector);
6777 encoder = intel_connector_primary_encoder(intel_connector);
6778 if (!encoder->update_prepare)
6781 crtc = new_conn_state->crtc ?
6782 to_intel_crtc(new_conn_state->crtc) : NULL;
6783 encoder->update_prepare(state, encoder, crtc);
6787 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6789 struct drm_connector_state *new_conn_state;
6790 struct drm_connector *connector;
6793 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6795 struct intel_connector *intel_connector;
6796 struct intel_encoder *encoder;
6797 struct intel_crtc *crtc;
6799 if (!intel_connector_needs_modeset(state, connector))
6802 intel_connector = to_intel_connector(connector);
6803 encoder = intel_connector_primary_encoder(intel_connector);
6804 if (!encoder->update_complete)
6807 crtc = new_conn_state->crtc ?
6808 to_intel_crtc(new_conn_state->crtc) : NULL;
6809 encoder->update_complete(state, encoder, crtc);
6813 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6814 struct intel_crtc *crtc)
6816 const struct intel_crtc_state *crtc_state =
6817 intel_atomic_get_new_crtc_state(state, crtc);
6818 const struct drm_connector_state *conn_state;
6819 struct drm_connector *conn;
6822 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6823 struct intel_encoder *encoder =
6824 to_intel_encoder(conn_state->best_encoder);
6826 if (conn_state->crtc != &crtc->base)
6829 if (encoder->pre_pll_enable)
6830 encoder->pre_pll_enable(state, encoder,
6831 crtc_state, conn_state);
6835 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6836 struct intel_crtc *crtc)
6838 const struct intel_crtc_state *crtc_state =
6839 intel_atomic_get_new_crtc_state(state, crtc);
6840 const struct drm_connector_state *conn_state;
6841 struct drm_connector *conn;
6844 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6845 struct intel_encoder *encoder =
6846 to_intel_encoder(conn_state->best_encoder);
6848 if (conn_state->crtc != &crtc->base)
6851 if (encoder->pre_enable)
6852 encoder->pre_enable(state, encoder,
6853 crtc_state, conn_state);
6857 static void intel_encoders_enable(struct intel_atomic_state *state,
6858 struct intel_crtc *crtc)
6860 const struct intel_crtc_state *crtc_state =
6861 intel_atomic_get_new_crtc_state(state, crtc);
6862 const struct drm_connector_state *conn_state;
6863 struct drm_connector *conn;
6866 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6867 struct intel_encoder *encoder =
6868 to_intel_encoder(conn_state->best_encoder);
6870 if (conn_state->crtc != &crtc->base)
6873 if (encoder->enable)
6874 encoder->enable(state, encoder,
6875 crtc_state, conn_state);
6876 intel_opregion_notify_encoder(encoder, true);
6880 static void intel_encoders_disable(struct intel_atomic_state *state,
6881 struct intel_crtc *crtc)
6883 const struct intel_crtc_state *old_crtc_state =
6884 intel_atomic_get_old_crtc_state(state, crtc);
6885 const struct drm_connector_state *old_conn_state;
6886 struct drm_connector *conn;
6889 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6890 struct intel_encoder *encoder =
6891 to_intel_encoder(old_conn_state->best_encoder);
6893 if (old_conn_state->crtc != &crtc->base)
6896 intel_opregion_notify_encoder(encoder, false);
6897 if (encoder->disable)
6898 encoder->disable(state, encoder,
6899 old_crtc_state, old_conn_state);
6903 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6904 struct intel_crtc *crtc)
6906 const struct intel_crtc_state *old_crtc_state =
6907 intel_atomic_get_old_crtc_state(state, crtc);
6908 const struct drm_connector_state *old_conn_state;
6909 struct drm_connector *conn;
6912 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6913 struct intel_encoder *encoder =
6914 to_intel_encoder(old_conn_state->best_encoder);
6916 if (old_conn_state->crtc != &crtc->base)
6919 if (encoder->post_disable)
6920 encoder->post_disable(state, encoder,
6921 old_crtc_state, old_conn_state);
6925 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6926 struct intel_crtc *crtc)
6928 const struct intel_crtc_state *old_crtc_state =
6929 intel_atomic_get_old_crtc_state(state, crtc);
6930 const struct drm_connector_state *old_conn_state;
6931 struct drm_connector *conn;
6934 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6935 struct intel_encoder *encoder =
6936 to_intel_encoder(old_conn_state->best_encoder);
6938 if (old_conn_state->crtc != &crtc->base)
6941 if (encoder->post_pll_disable)
6942 encoder->post_pll_disable(state, encoder,
6943 old_crtc_state, old_conn_state);
6947 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6948 struct intel_crtc *crtc)
6950 const struct intel_crtc_state *crtc_state =
6951 intel_atomic_get_new_crtc_state(state, crtc);
6952 const struct drm_connector_state *conn_state;
6953 struct drm_connector *conn;
6956 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6957 struct intel_encoder *encoder =
6958 to_intel_encoder(conn_state->best_encoder);
6960 if (conn_state->crtc != &crtc->base)
6963 if (encoder->update_pipe)
6964 encoder->update_pipe(state, encoder,
6965 crtc_state, conn_state);
6969 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6972 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6974 plane->disable_plane(plane, crtc_state);
6977 static void ilk_crtc_enable(struct intel_atomic_state *state,
6978 struct intel_crtc *crtc)
6980 const struct intel_crtc_state *new_crtc_state =
6981 intel_atomic_get_new_crtc_state(state, crtc);
6982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6983 enum pipe pipe = crtc->pipe;
6985 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6989 * Sometimes spurious CPU pipe underruns happen during FDI
6990 * training, at least with VGA+HDMI cloning. Suppress them.
6992 * On ILK we get an occasional spurious CPU pipe underruns
6993 * between eDP port A enable and vdd enable. Also PCH port
6994 * enable seems to result in the occasional CPU pipe underrun.
6996 * Spurious PCH underruns also occur during PCH enabling.
6998 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6999 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7001 if (new_crtc_state->has_pch_encoder)
7002 intel_prepare_shared_dpll(new_crtc_state);
7004 if (intel_crtc_has_dp_encoder(new_crtc_state))
7005 intel_dp_set_m_n(new_crtc_state, M1_N1);
7007 intel_set_transcoder_timings(new_crtc_state);
7008 intel_set_pipe_src_size(new_crtc_state);
7010 if (new_crtc_state->has_pch_encoder)
7011 intel_cpu_transcoder_set_m_n(new_crtc_state,
7012 &new_crtc_state->fdi_m_n, NULL);
7014 ilk_set_pipeconf(new_crtc_state);
7016 crtc->active = true;
7018 intel_encoders_pre_enable(state, crtc);
7020 if (new_crtc_state->has_pch_encoder) {
7021 /* Note: FDI PLL enabling _must_ be done before we enable the
7022 * cpu pipes, hence this is separate from all the other fdi/pch
7024 ilk_fdi_pll_enable(new_crtc_state);
7026 assert_fdi_tx_disabled(dev_priv, pipe);
7027 assert_fdi_rx_disabled(dev_priv, pipe);
7030 ilk_pfit_enable(new_crtc_state);
7033 * On ILK+ LUT must be loaded before the pipe is running but with
7036 intel_color_load_luts(new_crtc_state);
7037 intel_color_commit(new_crtc_state);
7038 /* update DSPCNTR to configure gamma for pipe bottom color */
7039 intel_disable_primary_plane(new_crtc_state);
7041 if (dev_priv->display.initial_watermarks)
7042 dev_priv->display.initial_watermarks(state, crtc);
7043 intel_enable_pipe(new_crtc_state);
7045 if (new_crtc_state->has_pch_encoder)
7046 ilk_pch_enable(state, new_crtc_state);
7048 intel_crtc_vblank_on(new_crtc_state);
7050 intel_encoders_enable(state, crtc);
7052 if (HAS_PCH_CPT(dev_priv))
7053 cpt_verify_modeset(dev_priv, pipe);
7056 * Must wait for vblank to avoid spurious PCH FIFO underruns.
7057 * And a second vblank wait is needed at least on ILK with
7058 * some interlaced HDMI modes. Let's do the double wait always
7059 * in case there are more corner cases we don't know about.
7061 if (new_crtc_state->has_pch_encoder) {
7062 intel_wait_for_vblank(dev_priv, pipe);
7063 intel_wait_for_vblank(dev_priv, pipe);
7065 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7066 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7069 /* IPS only exists on ULT machines and is tied to pipe A. */
7070 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7072 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7075 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7076 enum pipe pipe, bool apply)
7078 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7079 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7086 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7089 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7091 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7092 enum pipe pipe = crtc->pipe;
7095 val = MBUS_DBOX_A_CREDIT(2);
7097 if (INTEL_GEN(dev_priv) >= 12) {
7098 val |= MBUS_DBOX_BW_CREDIT(2);
7099 val |= MBUS_DBOX_B_CREDIT(12);
7101 val |= MBUS_DBOX_BW_CREDIT(1);
7102 val |= MBUS_DBOX_B_CREDIT(8);
7105 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7108 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7113 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7114 HSW_LINETIME(crtc_state->linetime) |
7115 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7118 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7120 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7121 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7122 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7125 val = intel_de_read(dev_priv, reg);
7126 val &= ~HSW_FRAME_START_DELAY_MASK;
7127 val |= HSW_FRAME_START_DELAY(0);
7128 intel_de_write(dev_priv, reg, val);
7131 static void hsw_crtc_enable(struct intel_atomic_state *state,
7132 struct intel_crtc *crtc)
7134 const struct intel_crtc_state *new_crtc_state =
7135 intel_atomic_get_new_crtc_state(state, crtc);
7136 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7137 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7138 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7139 bool psl_clkgate_wa;
7141 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7144 intel_encoders_pre_pll_enable(state, crtc);
7146 if (new_crtc_state->shared_dpll)
7147 intel_enable_shared_dpll(new_crtc_state);
7149 intel_encoders_pre_enable(state, crtc);
7151 if (!transcoder_is_dsi(cpu_transcoder))
7152 intel_set_transcoder_timings(new_crtc_state);
7154 intel_set_pipe_src_size(new_crtc_state);
7156 if (cpu_transcoder != TRANSCODER_EDP &&
7157 !transcoder_is_dsi(cpu_transcoder))
7158 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7159 new_crtc_state->pixel_multiplier - 1);
7161 if (new_crtc_state->has_pch_encoder)
7162 intel_cpu_transcoder_set_m_n(new_crtc_state,
7163 &new_crtc_state->fdi_m_n, NULL);
7165 if (!transcoder_is_dsi(cpu_transcoder)) {
7166 hsw_set_frame_start_delay(new_crtc_state);
7167 hsw_set_pipeconf(new_crtc_state);
7170 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7171 bdw_set_pipemisc(new_crtc_state);
7173 crtc->active = true;
7175 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7176 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7177 new_crtc_state->pch_pfit.enabled;
7179 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7181 if (INTEL_GEN(dev_priv) >= 9)
7182 skl_pfit_enable(new_crtc_state);
7184 ilk_pfit_enable(new_crtc_state);
7187 * On ILK+ LUT must be loaded before the pipe is running but with
7190 intel_color_load_luts(new_crtc_state);
7191 intel_color_commit(new_crtc_state);
7192 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7193 if (INTEL_GEN(dev_priv) < 9)
7194 intel_disable_primary_plane(new_crtc_state);
7196 hsw_set_linetime_wm(new_crtc_state);
7198 if (INTEL_GEN(dev_priv) >= 11)
7199 icl_set_pipe_chicken(crtc);
7201 if (dev_priv->display.initial_watermarks)
7202 dev_priv->display.initial_watermarks(state, crtc);
7204 if (INTEL_GEN(dev_priv) >= 11)
7205 icl_pipe_mbus_enable(crtc);
7207 intel_encoders_enable(state, crtc);
7209 if (psl_clkgate_wa) {
7210 intel_wait_for_vblank(dev_priv, pipe);
7211 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7214 /* If we change the relative order between pipe/planes enabling, we need
7215 * to change the workaround. */
7216 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7217 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7218 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7219 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7223 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7225 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7226 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7227 enum pipe pipe = crtc->pipe;
7229 /* To avoid upsetting the power well on haswell only disable the pfit if
7230 * it's in use. The hw state code will make sure we get this right. */
7231 if (!old_crtc_state->pch_pfit.enabled)
7234 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7235 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7236 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7239 static void ilk_crtc_disable(struct intel_atomic_state *state,
7240 struct intel_crtc *crtc)
7242 const struct intel_crtc_state *old_crtc_state =
7243 intel_atomic_get_old_crtc_state(state, crtc);
7244 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7245 enum pipe pipe = crtc->pipe;
7248 * Sometimes spurious CPU pipe underruns happen when the
7249 * pipe is already disabled, but FDI RX/TX is still enabled.
7250 * Happens at least with VGA+HDMI cloning. Suppress them.
7252 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7253 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7255 intel_encoders_disable(state, crtc);
7257 intel_crtc_vblank_off(old_crtc_state);
7259 intel_disable_pipe(old_crtc_state);
7261 ilk_pfit_disable(old_crtc_state);
7263 if (old_crtc_state->has_pch_encoder)
7264 ilk_fdi_disable(crtc);
7266 intel_encoders_post_disable(state, crtc);
7268 if (old_crtc_state->has_pch_encoder) {
7269 ilk_disable_pch_transcoder(dev_priv, pipe);
7271 if (HAS_PCH_CPT(dev_priv)) {
7275 /* disable TRANS_DP_CTL */
7276 reg = TRANS_DP_CTL(pipe);
7277 temp = intel_de_read(dev_priv, reg);
7278 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7279 TRANS_DP_PORT_SEL_MASK);
7280 temp |= TRANS_DP_PORT_SEL_NONE;
7281 intel_de_write(dev_priv, reg, temp);
7283 /* disable DPLL_SEL */
7284 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7285 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7286 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7289 ilk_fdi_pll_disable(crtc);
7292 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7293 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7296 static void hsw_crtc_disable(struct intel_atomic_state *state,
7297 struct intel_crtc *crtc)
7300 * FIXME collapse everything to one hook.
7301 * Need care with mst->ddi interactions.
7303 intel_encoders_disable(state, crtc);
7304 intel_encoders_post_disable(state, crtc);
7307 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7309 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7310 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7312 if (!crtc_state->gmch_pfit.control)
7316 * The panel fitter should only be adjusted whilst the pipe is disabled,
7317 * according to register description and PRM.
7319 drm_WARN_ON(&dev_priv->drm,
7320 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7321 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7323 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7324 crtc_state->gmch_pfit.pgm_ratios);
7325 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7327 /* Border color in case we don't scale up to the full screen. Black by
7328 * default, change to something else for debugging. */
7329 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7332 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7334 if (phy == PHY_NONE)
7336 else if (IS_ROCKETLAKE(dev_priv))
7337 return phy <= PHY_D;
7338 else if (IS_JSL_EHL(dev_priv))
7339 return phy <= PHY_C;
7340 else if (INTEL_GEN(dev_priv) >= 11)
7341 return phy <= PHY_B;
7346 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7348 if (IS_ROCKETLAKE(dev_priv))
7350 else if (INTEL_GEN(dev_priv) >= 12)
7351 return phy >= PHY_D && phy <= PHY_I;
7352 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
7353 return phy >= PHY_C && phy <= PHY_F;
7358 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7360 if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7361 return (enum phy)port - 1;
7362 else if (IS_JSL_EHL(i915) && port == PORT_D)
7365 return (enum phy)port;
7368 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7370 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7371 return PORT_TC_NONE;
7373 if (INTEL_GEN(dev_priv) >= 12)
7374 return port - PORT_D;
7376 return port - PORT_C;
7379 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7383 return POWER_DOMAIN_PORT_DDI_A_LANES;
7385 return POWER_DOMAIN_PORT_DDI_B_LANES;
7387 return POWER_DOMAIN_PORT_DDI_C_LANES;
7389 return POWER_DOMAIN_PORT_DDI_D_LANES;
7391 return POWER_DOMAIN_PORT_DDI_E_LANES;
7393 return POWER_DOMAIN_PORT_DDI_F_LANES;
7395 return POWER_DOMAIN_PORT_DDI_G_LANES;
7397 return POWER_DOMAIN_PORT_DDI_H_LANES;
7399 return POWER_DOMAIN_PORT_DDI_I_LANES;
7402 return POWER_DOMAIN_PORT_OTHER;
7406 enum intel_display_power_domain
7407 intel_aux_power_domain(struct intel_digital_port *dig_port)
7409 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7410 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7412 if (intel_phy_is_tc(dev_priv, phy) &&
7413 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7414 switch (dig_port->aux_ch) {
7416 return POWER_DOMAIN_AUX_C_TBT;
7418 return POWER_DOMAIN_AUX_D_TBT;
7420 return POWER_DOMAIN_AUX_E_TBT;
7422 return POWER_DOMAIN_AUX_F_TBT;
7424 return POWER_DOMAIN_AUX_G_TBT;
7426 return POWER_DOMAIN_AUX_H_TBT;
7428 return POWER_DOMAIN_AUX_I_TBT;
7430 MISSING_CASE(dig_port->aux_ch);
7431 return POWER_DOMAIN_AUX_C_TBT;
7435 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7439 * Converts aux_ch to power_domain without caring about TBT ports for that use
7440 * intel_aux_power_domain()
7442 enum intel_display_power_domain
7443 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7447 return POWER_DOMAIN_AUX_A;
7449 return POWER_DOMAIN_AUX_B;
7451 return POWER_DOMAIN_AUX_C;
7453 return POWER_DOMAIN_AUX_D;
7455 return POWER_DOMAIN_AUX_E;
7457 return POWER_DOMAIN_AUX_F;
7459 return POWER_DOMAIN_AUX_G;
7461 return POWER_DOMAIN_AUX_H;
7463 return POWER_DOMAIN_AUX_I;
7465 MISSING_CASE(aux_ch);
7466 return POWER_DOMAIN_AUX_A;
7470 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7474 struct drm_encoder *encoder;
7475 enum pipe pipe = crtc->pipe;
7477 enum transcoder transcoder = crtc_state->cpu_transcoder;
7479 if (!crtc_state->hw.active)
7482 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7483 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7484 if (crtc_state->pch_pfit.enabled ||
7485 crtc_state->pch_pfit.force_thru)
7486 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7488 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7489 crtc_state->uapi.encoder_mask) {
7490 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7492 mask |= BIT_ULL(intel_encoder->power_domain);
7495 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7496 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7498 if (crtc_state->shared_dpll)
7499 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7505 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7507 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7508 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7509 enum intel_display_power_domain domain;
7510 u64 domains, new_domains, old_domains;
7512 old_domains = crtc->enabled_power_domains;
7513 crtc->enabled_power_domains = new_domains =
7514 get_crtc_power_domains(crtc_state);
7516 domains = new_domains & ~old_domains;
7518 for_each_power_domain(domain, domains)
7519 intel_display_power_get(dev_priv, domain);
7521 return old_domains & ~new_domains;
7524 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7527 enum intel_display_power_domain domain;
7529 for_each_power_domain(domain, domains)
7530 intel_display_power_put_unchecked(dev_priv, domain);
7533 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7534 struct intel_crtc *crtc)
7536 const struct intel_crtc_state *new_crtc_state =
7537 intel_atomic_get_new_crtc_state(state, crtc);
7538 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7539 enum pipe pipe = crtc->pipe;
7541 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7544 if (intel_crtc_has_dp_encoder(new_crtc_state))
7545 intel_dp_set_m_n(new_crtc_state, M1_N1);
7547 intel_set_transcoder_timings(new_crtc_state);
7548 intel_set_pipe_src_size(new_crtc_state);
7550 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7551 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7552 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7555 i9xx_set_pipeconf(new_crtc_state);
7557 crtc->active = true;
7559 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7561 intel_encoders_pre_pll_enable(state, crtc);
7563 if (IS_CHERRYVIEW(dev_priv)) {
7564 chv_prepare_pll(crtc, new_crtc_state);
7565 chv_enable_pll(crtc, new_crtc_state);
7567 vlv_prepare_pll(crtc, new_crtc_state);
7568 vlv_enable_pll(crtc, new_crtc_state);
7571 intel_encoders_pre_enable(state, crtc);
7573 i9xx_pfit_enable(new_crtc_state);
7575 intel_color_load_luts(new_crtc_state);
7576 intel_color_commit(new_crtc_state);
7577 /* update DSPCNTR to configure gamma for pipe bottom color */
7578 intel_disable_primary_plane(new_crtc_state);
7580 dev_priv->display.initial_watermarks(state, crtc);
7581 intel_enable_pipe(new_crtc_state);
7583 intel_crtc_vblank_on(new_crtc_state);
7585 intel_encoders_enable(state, crtc);
7588 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7593 intel_de_write(dev_priv, FP0(crtc->pipe),
7594 crtc_state->dpll_hw_state.fp0);
7595 intel_de_write(dev_priv, FP1(crtc->pipe),
7596 crtc_state->dpll_hw_state.fp1);
7599 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7600 struct intel_crtc *crtc)
7602 const struct intel_crtc_state *new_crtc_state =
7603 intel_atomic_get_new_crtc_state(state, crtc);
7604 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7605 enum pipe pipe = crtc->pipe;
7607 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7610 i9xx_set_pll_dividers(new_crtc_state);
7612 if (intel_crtc_has_dp_encoder(new_crtc_state))
7613 intel_dp_set_m_n(new_crtc_state, M1_N1);
7615 intel_set_transcoder_timings(new_crtc_state);
7616 intel_set_pipe_src_size(new_crtc_state);
7618 i9xx_set_pipeconf(new_crtc_state);
7620 crtc->active = true;
7622 if (!IS_GEN(dev_priv, 2))
7623 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7625 intel_encoders_pre_enable(state, crtc);
7627 i9xx_enable_pll(crtc, new_crtc_state);
7629 i9xx_pfit_enable(new_crtc_state);
7631 intel_color_load_luts(new_crtc_state);
7632 intel_color_commit(new_crtc_state);
7633 /* update DSPCNTR to configure gamma for pipe bottom color */
7634 intel_disable_primary_plane(new_crtc_state);
7636 if (dev_priv->display.initial_watermarks)
7637 dev_priv->display.initial_watermarks(state, crtc);
7639 intel_update_watermarks(crtc);
7640 intel_enable_pipe(new_crtc_state);
7642 intel_crtc_vblank_on(new_crtc_state);
7644 intel_encoders_enable(state, crtc);
7646 /* prevents spurious underruns */
7647 if (IS_GEN(dev_priv, 2))
7648 intel_wait_for_vblank(dev_priv, pipe);
7651 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7653 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7656 if (!old_crtc_state->gmch_pfit.control)
7659 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7661 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7662 intel_de_read(dev_priv, PFIT_CONTROL));
7663 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7666 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7667 struct intel_crtc *crtc)
7669 struct intel_crtc_state *old_crtc_state =
7670 intel_atomic_get_old_crtc_state(state, crtc);
7671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7672 enum pipe pipe = crtc->pipe;
7675 * On gen2 planes are double buffered but the pipe isn't, so we must
7676 * wait for planes to fully turn off before disabling the pipe.
7678 if (IS_GEN(dev_priv, 2))
7679 intel_wait_for_vblank(dev_priv, pipe);
7681 intel_encoders_disable(state, crtc);
7683 intel_crtc_vblank_off(old_crtc_state);
7685 intel_disable_pipe(old_crtc_state);
7687 i9xx_pfit_disable(old_crtc_state);
7689 intel_encoders_post_disable(state, crtc);
7691 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7692 if (IS_CHERRYVIEW(dev_priv))
7693 chv_disable_pll(dev_priv, pipe);
7694 else if (IS_VALLEYVIEW(dev_priv))
7695 vlv_disable_pll(dev_priv, pipe);
7697 i9xx_disable_pll(old_crtc_state);
7700 intel_encoders_post_pll_disable(state, crtc);
7702 if (!IS_GEN(dev_priv, 2))
7703 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7705 if (!dev_priv->display.initial_watermarks)
7706 intel_update_watermarks(crtc);
7708 /* clock the pipe down to 640x480@60 to potentially save power */
7709 if (IS_I830(dev_priv))
7710 i830_enable_pipe(dev_priv, pipe);
7713 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7714 struct drm_modeset_acquire_ctx *ctx)
7716 struct intel_encoder *encoder;
7717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7718 struct intel_bw_state *bw_state =
7719 to_intel_bw_state(dev_priv->bw_obj.state);
7720 struct intel_cdclk_state *cdclk_state =
7721 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7722 struct intel_dbuf_state *dbuf_state =
7723 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7724 struct intel_crtc_state *crtc_state =
7725 to_intel_crtc_state(crtc->base.state);
7726 enum intel_display_power_domain domain;
7727 struct intel_plane *plane;
7728 struct drm_atomic_state *state;
7729 struct intel_crtc_state *temp_crtc_state;
7730 enum pipe pipe = crtc->pipe;
7734 if (!crtc_state->hw.active)
7737 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7738 const struct intel_plane_state *plane_state =
7739 to_intel_plane_state(plane->base.state);
7741 if (plane_state->uapi.visible)
7742 intel_plane_disable_noatomic(crtc, plane);
7745 state = drm_atomic_state_alloc(&dev_priv->drm);
7747 drm_dbg_kms(&dev_priv->drm,
7748 "failed to disable [CRTC:%d:%s], out of memory",
7749 crtc->base.base.id, crtc->base.name);
7753 state->acquire_ctx = ctx;
7755 /* Everything's already locked, -EDEADLK can't happen. */
7756 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7757 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7759 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7761 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7763 drm_atomic_state_put(state);
7765 drm_dbg_kms(&dev_priv->drm,
7766 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7767 crtc->base.base.id, crtc->base.name);
7769 crtc->active = false;
7770 crtc->base.enabled = false;
7772 drm_WARN_ON(&dev_priv->drm,
7773 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7774 crtc_state->uapi.active = false;
7775 crtc_state->uapi.connector_mask = 0;
7776 crtc_state->uapi.encoder_mask = 0;
7777 intel_crtc_free_hw_state(crtc_state);
7778 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7780 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7781 encoder->base.crtc = NULL;
7783 intel_fbc_disable(crtc);
7784 intel_update_watermarks(crtc);
7785 intel_disable_shared_dpll(crtc_state);
7787 domains = crtc->enabled_power_domains;
7788 for_each_power_domain(domain, domains)
7789 intel_display_power_put_unchecked(dev_priv, domain);
7790 crtc->enabled_power_domains = 0;
7792 dev_priv->active_pipes &= ~BIT(pipe);
7793 cdclk_state->min_cdclk[pipe] = 0;
7794 cdclk_state->min_voltage_level[pipe] = 0;
7795 cdclk_state->active_pipes &= ~BIT(pipe);
7797 dbuf_state->active_pipes &= ~BIT(pipe);
7799 bw_state->data_rate[pipe] = 0;
7800 bw_state->num_active_planes[pipe] = 0;
7804 * turn all crtc's off, but do not adjust state
7805 * This has to be paired with a call to intel_modeset_setup_hw_state.
7807 int intel_display_suspend(struct drm_device *dev)
7809 struct drm_i915_private *dev_priv = to_i915(dev);
7810 struct drm_atomic_state *state;
7813 state = drm_atomic_helper_suspend(dev);
7814 ret = PTR_ERR_OR_ZERO(state);
7816 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7819 dev_priv->modeset_restore_state = state;
7823 void intel_encoder_destroy(struct drm_encoder *encoder)
7825 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7827 drm_encoder_cleanup(encoder);
7828 kfree(intel_encoder);
7831 /* Cross check the actual hw state with our own modeset state tracking (and it's
7832 * internal consistency). */
7833 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7834 struct drm_connector_state *conn_state)
7836 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7837 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7839 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7840 connector->base.base.id, connector->base.name);
7842 if (connector->get_hw_state(connector)) {
7843 struct intel_encoder *encoder = intel_attached_encoder(connector);
7845 I915_STATE_WARN(!crtc_state,
7846 "connector enabled without attached crtc\n");
7851 I915_STATE_WARN(!crtc_state->hw.active,
7852 "connector is active, but attached crtc isn't\n");
7854 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7857 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7858 "atomic encoder doesn't match attached encoder\n");
7860 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7861 "attached encoder crtc differs from connector crtc\n");
7863 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7864 "attached crtc is active, but connector isn't\n");
7865 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7866 "best encoder set without crtc!\n");
7870 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7872 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7873 return crtc_state->fdi_lanes;
7878 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7879 struct intel_crtc_state *pipe_config)
7881 struct drm_i915_private *dev_priv = to_i915(dev);
7882 struct drm_atomic_state *state = pipe_config->uapi.state;
7883 struct intel_crtc *other_crtc;
7884 struct intel_crtc_state *other_crtc_state;
7886 drm_dbg_kms(&dev_priv->drm,
7887 "checking fdi config on pipe %c, lanes %i\n",
7888 pipe_name(pipe), pipe_config->fdi_lanes);
7889 if (pipe_config->fdi_lanes > 4) {
7890 drm_dbg_kms(&dev_priv->drm,
7891 "invalid fdi lane config on pipe %c: %i lanes\n",
7892 pipe_name(pipe), pipe_config->fdi_lanes);
7896 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7897 if (pipe_config->fdi_lanes > 2) {
7898 drm_dbg_kms(&dev_priv->drm,
7899 "only 2 lanes on haswell, required: %i lanes\n",
7900 pipe_config->fdi_lanes);
7907 if (INTEL_NUM_PIPES(dev_priv) == 2)
7910 /* Ivybridge 3 pipe is really complicated */
7915 if (pipe_config->fdi_lanes <= 2)
7918 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7920 intel_atomic_get_crtc_state(state, other_crtc);
7921 if (IS_ERR(other_crtc_state))
7922 return PTR_ERR(other_crtc_state);
7924 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7925 drm_dbg_kms(&dev_priv->drm,
7926 "invalid shared fdi lane config on pipe %c: %i lanes\n",
7927 pipe_name(pipe), pipe_config->fdi_lanes);
7932 if (pipe_config->fdi_lanes > 2) {
7933 drm_dbg_kms(&dev_priv->drm,
7934 "only 2 lanes on pipe %c: required %i lanes\n",
7935 pipe_name(pipe), pipe_config->fdi_lanes);
7939 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7941 intel_atomic_get_crtc_state(state, other_crtc);
7942 if (IS_ERR(other_crtc_state))
7943 return PTR_ERR(other_crtc_state);
7945 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7946 drm_dbg_kms(&dev_priv->drm,
7947 "fdi link B uses too many lanes to enable link C\n");
7957 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7958 struct intel_crtc_state *pipe_config)
7960 struct drm_device *dev = intel_crtc->base.dev;
7961 struct drm_i915_private *i915 = to_i915(dev);
7962 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7963 int lane, link_bw, fdi_dotclock, ret;
7964 bool needs_recompute = false;
7967 /* FDI is a binary signal running at ~2.7GHz, encoding
7968 * each output octet as 10 bits. The actual frequency
7969 * is stored as a divider into a 100MHz clock, and the
7970 * mode pixel clock is stored in units of 1KHz.
7971 * Hence the bw of each lane in terms of the mode signal
7974 link_bw = intel_fdi_link_freq(i915, pipe_config);
7976 fdi_dotclock = adjusted_mode->crtc_clock;
7978 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7979 pipe_config->pipe_bpp);
7981 pipe_config->fdi_lanes = lane;
7983 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7984 link_bw, &pipe_config->fdi_m_n, false, false);
7986 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7987 if (ret == -EDEADLK)
7990 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7991 pipe_config->pipe_bpp -= 2*3;
7992 drm_dbg_kms(&i915->drm,
7993 "fdi link bw constraint, reducing pipe bpp to %i\n",
7994 pipe_config->pipe_bpp);
7995 needs_recompute = true;
7996 pipe_config->bw_constrained = true;
8001 if (needs_recompute)
8007 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
8009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8012 /* IPS only exists on ULT machines and is tied to pipe A. */
8013 if (!hsw_crtc_supports_ips(crtc))
8016 if (!dev_priv->params.enable_ips)
8019 if (crtc_state->pipe_bpp > 24)
8023 * We compare against max which means we must take
8024 * the increased cdclk requirement into account when
8025 * calculating the new cdclk.
8027 * Should measure whether using a lower cdclk w/o IPS
8029 if (IS_BROADWELL(dev_priv) &&
8030 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
8036 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
8038 struct drm_i915_private *dev_priv =
8039 to_i915(crtc_state->uapi.crtc->dev);
8040 struct intel_atomic_state *state =
8041 to_intel_atomic_state(crtc_state->uapi.state);
8043 crtc_state->ips_enabled = false;
8045 if (!hsw_crtc_state_ips_capable(crtc_state))
8049 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
8050 * enabled and disabled dynamically based on package C states,
8051 * user space can't make reliable use of the CRCs, so let's just
8052 * completely disable it.
8054 if (crtc_state->crc_enabled)
8057 /* IPS should be fine as long as at least one plane is enabled. */
8058 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8061 if (IS_BROADWELL(dev_priv)) {
8062 const struct intel_cdclk_state *cdclk_state;
8064 cdclk_state = intel_atomic_get_cdclk_state(state);
8065 if (IS_ERR(cdclk_state))
8066 return PTR_ERR(cdclk_state);
8068 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8069 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8073 crtc_state->ips_enabled = true;
8078 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8080 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8082 /* GDG double wide on either pipe, otherwise pipe A only */
8083 return INTEL_GEN(dev_priv) < 4 &&
8084 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8087 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8089 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8090 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8093 * We only use IF-ID interlacing. If we ever use
8094 * PF-ID we'll need to adjust the pixel_rate here.
8097 if (!crtc_state->pch_pfit.enabled)
8100 pipe_w = crtc_state->pipe_src_w;
8101 pipe_h = crtc_state->pipe_src_h;
8103 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8104 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8106 if (pipe_w < pfit_w)
8108 if (pipe_h < pfit_h)
8111 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8112 !pfit_w || !pfit_h))
8115 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8119 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8121 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8123 if (HAS_GMCH(dev_priv))
8124 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8125 crtc_state->pixel_rate =
8126 crtc_state->hw.adjusted_mode.crtc_clock;
8128 crtc_state->pixel_rate =
8129 ilk_pipe_pixel_rate(crtc_state);
8132 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8133 struct intel_crtc_state *pipe_config)
8135 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8136 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8137 int clock_limit = dev_priv->max_dotclk_freq;
8139 if (INTEL_GEN(dev_priv) < 4) {
8140 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8143 * Enable double wide mode when the dot clock
8144 * is > 90% of the (display) core speed.
8146 if (intel_crtc_supports_double_wide(crtc) &&
8147 adjusted_mode->crtc_clock > clock_limit) {
8148 clock_limit = dev_priv->max_dotclk_freq;
8149 pipe_config->double_wide = true;
8153 if (adjusted_mode->crtc_clock > clock_limit) {
8154 drm_dbg_kms(&dev_priv->drm,
8155 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8156 adjusted_mode->crtc_clock, clock_limit,
8157 yesno(pipe_config->double_wide));
8161 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8162 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8163 pipe_config->hw.ctm) {
8165 * There is only one pipe CSC unit per pipe, and we need that
8166 * for output conversion from RGB->YCBCR. So if CTM is already
8167 * applied we can't support YCBCR420 output.
8169 drm_dbg_kms(&dev_priv->drm,
8170 "YCBCR420 and CTM together are not possible\n");
8175 * Pipe horizontal size must be even in:
8177 * - LVDS dual channel mode
8178 * - Double wide pipe
8180 if (pipe_config->pipe_src_w & 1) {
8181 if (pipe_config->double_wide) {
8182 drm_dbg_kms(&dev_priv->drm,
8183 "Odd pipe source width not supported with double wide pipe\n");
8187 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8188 intel_is_dual_link_lvds(dev_priv)) {
8189 drm_dbg_kms(&dev_priv->drm,
8190 "Odd pipe source width not supported with dual link LVDS\n");
8195 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8196 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8198 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8199 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8202 intel_crtc_compute_pixel_rate(pipe_config);
8204 if (pipe_config->has_pch_encoder)
8205 return ilk_fdi_compute_config(crtc, pipe_config);
8211 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8213 while (*num > DATA_LINK_M_N_MASK ||
8214 *den > DATA_LINK_M_N_MASK) {
8220 static void compute_m_n(unsigned int m, unsigned int n,
8221 u32 *ret_m, u32 *ret_n,
8225 * Several DP dongles in particular seem to be fussy about
8226 * too large link M/N values. Give N value as 0x8000 that
8227 * should be acceptable by specific devices. 0x8000 is the
8228 * specified fixed N value for asynchronous clock mode,
8229 * which the devices expect also in synchronous clock mode.
8234 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8236 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8237 intel_reduce_m_n_ratio(ret_m, ret_n);
8241 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8242 int pixel_clock, int link_clock,
8243 struct intel_link_m_n *m_n,
8244 bool constant_n, bool fec_enable)
8246 u32 data_clock = bits_per_pixel * pixel_clock;
8249 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8252 compute_m_n(data_clock,
8253 link_clock * nlanes * 8,
8254 &m_n->gmch_m, &m_n->gmch_n,
8257 compute_m_n(pixel_clock, link_clock,
8258 &m_n->link_m, &m_n->link_n,
8262 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8265 * There may be no VBT; and if the BIOS enabled SSC we can
8266 * just keep using it to avoid unnecessary flicker. Whereas if the
8267 * BIOS isn't using it, don't assume it will work even if the VBT
8268 * indicates as much.
8270 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8271 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8275 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8276 drm_dbg_kms(&dev_priv->drm,
8277 "SSC %s by BIOS, overriding VBT which says %s\n",
8278 enableddisabled(bios_lvds_use_ssc),
8279 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8280 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8285 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8287 if (dev_priv->params.panel_use_ssc >= 0)
8288 return dev_priv->params.panel_use_ssc != 0;
8289 return dev_priv->vbt.lvds_use_ssc
8290 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8293 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8295 return (1 << dpll->n) << 16 | dpll->m2;
8298 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8300 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8303 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8304 struct intel_crtc_state *crtc_state,
8305 struct dpll *reduced_clock)
8307 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8310 if (IS_PINEVIEW(dev_priv)) {
8311 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8313 fp2 = pnv_dpll_compute_fp(reduced_clock);
8315 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8317 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8320 crtc_state->dpll_hw_state.fp0 = fp;
8322 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8324 crtc_state->dpll_hw_state.fp1 = fp2;
8326 crtc_state->dpll_hw_state.fp1 = fp;
8330 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8336 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8337 * and set it to a reasonable value instead.
8339 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8340 reg_val &= 0xffffff00;
8341 reg_val |= 0x00000030;
8342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8344 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8345 reg_val &= 0x00ffffff;
8346 reg_val |= 0x8c000000;
8347 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8349 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8350 reg_val &= 0xffffff00;
8351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8354 reg_val &= 0x00ffffff;
8355 reg_val |= 0xb0000000;
8356 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8359 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8360 const struct intel_link_m_n *m_n)
8362 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8363 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8364 enum pipe pipe = crtc->pipe;
8366 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8367 TU_SIZE(m_n->tu) | m_n->gmch_m);
8368 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8369 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8370 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8373 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8374 enum transcoder transcoder)
8376 if (IS_HASWELL(dev_priv))
8377 return transcoder == TRANSCODER_EDP;
8380 * Strictly speaking some registers are available before
8381 * gen7, but we only support DRRS on gen7+
8383 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8386 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8387 const struct intel_link_m_n *m_n,
8388 const struct intel_link_m_n *m2_n2)
8390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8392 enum pipe pipe = crtc->pipe;
8393 enum transcoder transcoder = crtc_state->cpu_transcoder;
8395 if (INTEL_GEN(dev_priv) >= 5) {
8396 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8397 TU_SIZE(m_n->tu) | m_n->gmch_m);
8398 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8400 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8402 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8405 * M2_N2 registers are set only if DRRS is supported
8406 * (to make sure the registers are not unnecessarily accessed).
8408 if (m2_n2 && crtc_state->has_drrs &&
8409 transcoder_has_m2_n2(dev_priv, transcoder)) {
8410 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8411 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8412 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8414 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8416 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8420 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8421 TU_SIZE(m_n->tu) | m_n->gmch_m);
8422 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8423 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8424 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8428 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8430 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8431 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8434 dp_m_n = &crtc_state->dp_m_n;
8435 dp_m2_n2 = &crtc_state->dp_m2_n2;
8436 } else if (m_n == M2_N2) {
8439 * M2_N2 registers are not supported. Hence m2_n2 divider value
8440 * needs to be programmed into M1_N1.
8442 dp_m_n = &crtc_state->dp_m2_n2;
8444 drm_err(&i915->drm, "Unsupported divider value\n");
8448 if (crtc_state->has_pch_encoder)
8449 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8451 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8454 static void vlv_compute_dpll(struct intel_crtc *crtc,
8455 struct intel_crtc_state *pipe_config)
8457 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8458 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8459 if (crtc->pipe != PIPE_A)
8460 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8462 /* DPLL not used with DSI, but still need the rest set up */
8463 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8464 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8465 DPLL_EXT_BUFFER_ENABLE_VLV;
8467 pipe_config->dpll_hw_state.dpll_md =
8468 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8471 static void chv_compute_dpll(struct intel_crtc *crtc,
8472 struct intel_crtc_state *pipe_config)
8474 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8475 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8476 if (crtc->pipe != PIPE_A)
8477 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8479 /* DPLL not used with DSI, but still need the rest set up */
8480 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8481 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8483 pipe_config->dpll_hw_state.dpll_md =
8484 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8487 static void vlv_prepare_pll(struct intel_crtc *crtc,
8488 const struct intel_crtc_state *pipe_config)
8490 struct drm_device *dev = crtc->base.dev;
8491 struct drm_i915_private *dev_priv = to_i915(dev);
8492 enum pipe pipe = crtc->pipe;
8494 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8495 u32 coreclk, reg_val;
8498 intel_de_write(dev_priv, DPLL(pipe),
8499 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8501 /* No need to actually set up the DPLL with DSI */
8502 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8505 vlv_dpio_get(dev_priv);
8507 bestn = pipe_config->dpll.n;
8508 bestm1 = pipe_config->dpll.m1;
8509 bestm2 = pipe_config->dpll.m2;
8510 bestp1 = pipe_config->dpll.p1;
8511 bestp2 = pipe_config->dpll.p2;
8513 /* See eDP HDMI DPIO driver vbios notes doc */
8515 /* PLL B needs special handling */
8517 vlv_pllb_recal_opamp(dev_priv, pipe);
8519 /* Set up Tx target for periodic Rcomp update */
8520 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8522 /* Disable target IRef on PLL */
8523 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8524 reg_val &= 0x00ffffff;
8525 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8527 /* Disable fast lock */
8528 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8530 /* Set idtafcrecal before PLL is enabled */
8531 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8532 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8533 mdiv |= ((bestn << DPIO_N_SHIFT));
8534 mdiv |= (1 << DPIO_K_SHIFT);
8537 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8538 * but we don't support that).
8539 * Note: don't use the DAC post divider as it seems unstable.
8541 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8542 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8544 mdiv |= DPIO_ENABLE_CALIBRATION;
8545 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8547 /* Set HBR and RBR LPF coefficients */
8548 if (pipe_config->port_clock == 162000 ||
8549 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8550 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8551 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8554 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8557 if (intel_crtc_has_dp_encoder(pipe_config)) {
8558 /* Use SSC source */
8560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8563 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8565 } else { /* HDMI or VGA */
8566 /* Use bend source */
8568 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8571 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8575 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8576 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8577 if (intel_crtc_has_dp_encoder(pipe_config))
8578 coreclk |= 0x01000000;
8579 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8583 vlv_dpio_put(dev_priv);
8586 static void chv_prepare_pll(struct intel_crtc *crtc,
8587 const struct intel_crtc_state *pipe_config)
8589 struct drm_device *dev = crtc->base.dev;
8590 struct drm_i915_private *dev_priv = to_i915(dev);
8591 enum pipe pipe = crtc->pipe;
8592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8593 u32 loopfilter, tribuf_calcntr;
8594 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8598 /* Enable Refclk and SSC */
8599 intel_de_write(dev_priv, DPLL(pipe),
8600 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8602 /* No need to actually set up the DPLL with DSI */
8603 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8606 bestn = pipe_config->dpll.n;
8607 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8608 bestm1 = pipe_config->dpll.m1;
8609 bestm2 = pipe_config->dpll.m2 >> 22;
8610 bestp1 = pipe_config->dpll.p1;
8611 bestp2 = pipe_config->dpll.p2;
8612 vco = pipe_config->dpll.vco;
8616 vlv_dpio_get(dev_priv);
8618 /* p1 and p2 divider */
8619 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8620 5 << DPIO_CHV_S1_DIV_SHIFT |
8621 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8622 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8623 1 << DPIO_CHV_K_DIV_SHIFT);
8625 /* Feedback post-divider - m2 */
8626 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8628 /* Feedback refclk divider - n and m1 */
8629 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8630 DPIO_CHV_M1_DIV_BY_2 |
8631 1 << DPIO_CHV_N_DIV_SHIFT);
8633 /* M2 fraction division */
8634 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8636 /* M2 fraction division enable */
8637 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8638 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8639 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8641 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8642 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8644 /* Program digital lock detect threshold */
8645 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8646 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8647 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8648 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8650 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8651 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8654 if (vco == 5400000) {
8655 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8656 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8657 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8658 tribuf_calcntr = 0x9;
8659 } else if (vco <= 6200000) {
8660 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8661 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8662 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8663 tribuf_calcntr = 0x9;
8664 } else if (vco <= 6480000) {
8665 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8666 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8667 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8668 tribuf_calcntr = 0x8;
8670 /* Not supported. Apply the same limits as in the max case */
8671 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8672 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8673 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8676 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8678 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8679 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8680 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8681 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8685 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8688 vlv_dpio_put(dev_priv);
8692 * vlv_force_pll_on - forcibly enable just the PLL
8693 * @dev_priv: i915 private structure
8694 * @pipe: pipe PLL to enable
8695 * @dpll: PLL configuration
8697 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8698 * in cases where we need the PLL enabled even when @pipe is not going to
8701 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8702 const struct dpll *dpll)
8704 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8705 struct intel_crtc_state *pipe_config;
8707 pipe_config = intel_crtc_state_alloc(crtc);
8711 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8712 pipe_config->pixel_multiplier = 1;
8713 pipe_config->dpll = *dpll;
8715 if (IS_CHERRYVIEW(dev_priv)) {
8716 chv_compute_dpll(crtc, pipe_config);
8717 chv_prepare_pll(crtc, pipe_config);
8718 chv_enable_pll(crtc, pipe_config);
8720 vlv_compute_dpll(crtc, pipe_config);
8721 vlv_prepare_pll(crtc, pipe_config);
8722 vlv_enable_pll(crtc, pipe_config);
8731 * vlv_force_pll_off - forcibly disable just the PLL
8732 * @dev_priv: i915 private structure
8733 * @pipe: pipe PLL to disable
8735 * Disable the PLL for @pipe. To be used in cases where we need
8736 * the PLL enabled even when @pipe is not going to be enabled.
8738 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8740 if (IS_CHERRYVIEW(dev_priv))
8741 chv_disable_pll(dev_priv, pipe);
8743 vlv_disable_pll(dev_priv, pipe);
8746 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8747 struct intel_crtc_state *crtc_state,
8748 struct dpll *reduced_clock)
8750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8752 struct dpll *clock = &crtc_state->dpll;
8754 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8756 dpll = DPLL_VGA_MODE_DIS;
8758 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8759 dpll |= DPLLB_MODE_LVDS;
8761 dpll |= DPLLB_MODE_DAC_SERIAL;
8763 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8764 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8765 dpll |= (crtc_state->pixel_multiplier - 1)
8766 << SDVO_MULTIPLIER_SHIFT_HIRES;
8769 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8770 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8771 dpll |= DPLL_SDVO_HIGH_SPEED;
8773 if (intel_crtc_has_dp_encoder(crtc_state))
8774 dpll |= DPLL_SDVO_HIGH_SPEED;
8776 /* compute bitmask from p1 value */
8777 if (IS_PINEVIEW(dev_priv))
8778 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8780 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8781 if (IS_G4X(dev_priv) && reduced_clock)
8782 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8784 switch (clock->p2) {
8786 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8789 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8798 if (INTEL_GEN(dev_priv) >= 4)
8799 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8801 if (crtc_state->sdvo_tv_clock)
8802 dpll |= PLL_REF_INPUT_TVCLKINBC;
8803 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8804 intel_panel_use_ssc(dev_priv))
8805 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8807 dpll |= PLL_REF_INPUT_DREFCLK;
8809 dpll |= DPLL_VCO_ENABLE;
8810 crtc_state->dpll_hw_state.dpll = dpll;
8812 if (INTEL_GEN(dev_priv) >= 4) {
8813 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8814 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8815 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8819 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8820 struct intel_crtc_state *crtc_state,
8821 struct dpll *reduced_clock)
8823 struct drm_device *dev = crtc->base.dev;
8824 struct drm_i915_private *dev_priv = to_i915(dev);
8826 struct dpll *clock = &crtc_state->dpll;
8828 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8830 dpll = DPLL_VGA_MODE_DIS;
8832 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8833 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8836 dpll |= PLL_P1_DIVIDE_BY_TWO;
8838 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8840 dpll |= PLL_P2_DIVIDE_BY_4;
8845 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8846 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8847 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8848 * Enable) must be set to “1” in both the DPLL A Control Register
8849 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8851 * For simplicity We simply keep both bits always enabled in
8852 * both DPLLS. The spec says we should disable the DVO 2X clock
8853 * when not needed, but this seems to work fine in practice.
8855 if (IS_I830(dev_priv) ||
8856 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8857 dpll |= DPLL_DVO_2X_MODE;
8859 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8860 intel_panel_use_ssc(dev_priv))
8861 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8863 dpll |= PLL_REF_INPUT_DREFCLK;
8865 dpll |= DPLL_VCO_ENABLE;
8866 crtc_state->dpll_hw_state.dpll = dpll;
8869 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
8871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8873 enum pipe pipe = crtc->pipe;
8874 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8875 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8876 u32 crtc_vtotal, crtc_vblank_end;
8879 /* We need to be careful not to changed the adjusted mode, for otherwise
8880 * the hw state checker will get angry at the mismatch. */
8881 crtc_vtotal = adjusted_mode->crtc_vtotal;
8882 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8884 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8885 /* the chip adds 2 halflines automatically */
8887 crtc_vblank_end -= 1;
8889 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8890 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8892 vsyncshift = adjusted_mode->crtc_hsync_start -
8893 adjusted_mode->crtc_htotal / 2;
8895 vsyncshift += adjusted_mode->crtc_htotal;
8898 if (INTEL_GEN(dev_priv) > 3)
8899 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8902 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8903 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8904 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8905 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8906 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8907 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8909 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8910 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8911 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8912 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8913 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8914 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8916 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8917 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8918 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8920 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8921 (pipe == PIPE_B || pipe == PIPE_C))
8922 intel_de_write(dev_priv, VTOTAL(pipe),
8923 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8927 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8930 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8931 enum pipe pipe = crtc->pipe;
8933 /* pipesrc controls the size that is scaled from, which should
8934 * always be the user's requested size.
8936 intel_de_write(dev_priv, PIPESRC(pipe),
8937 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8940 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8942 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8943 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8945 if (IS_GEN(dev_priv, 2))
8948 if (INTEL_GEN(dev_priv) >= 9 ||
8949 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8950 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8952 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8955 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
8956 struct intel_crtc_state *pipe_config)
8958 struct drm_device *dev = crtc->base.dev;
8959 struct drm_i915_private *dev_priv = to_i915(dev);
8960 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8963 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8964 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8965 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8967 if (!transcoder_is_dsi(cpu_transcoder)) {
8968 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8969 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8971 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8972 ((tmp >> 16) & 0xffff) + 1;
8974 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8975 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8976 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8978 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8979 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8980 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8982 if (!transcoder_is_dsi(cpu_transcoder)) {
8983 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8984 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8986 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8987 ((tmp >> 16) & 0xffff) + 1;
8989 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8990 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8991 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8993 if (intel_pipe_is_interlaced(pipe_config)) {
8994 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8995 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8996 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
9000 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
9001 struct intel_crtc_state *pipe_config)
9003 struct drm_device *dev = crtc->base.dev;
9004 struct drm_i915_private *dev_priv = to_i915(dev);
9007 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
9008 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
9009 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
9011 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
9012 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
9015 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
9016 struct intel_crtc_state *pipe_config)
9018 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
9019 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
9020 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
9021 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
9023 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
9024 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
9025 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
9026 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
9028 mode->flags = pipe_config->hw.adjusted_mode.flags;
9029 mode->type = DRM_MODE_TYPE_DRIVER;
9031 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
9033 drm_mode_set_name(mode);
9036 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
9038 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9044 /* we keep both pipes enabled on 830 */
9045 if (IS_I830(dev_priv))
9046 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
9048 if (crtc_state->double_wide)
9049 pipeconf |= PIPECONF_DOUBLE_WIDE;
9051 /* only g4x and later have fancy bpc/dither controls */
9052 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9053 IS_CHERRYVIEW(dev_priv)) {
9054 /* Bspec claims that we can't use dithering for 30bpp pipes. */
9055 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
9056 pipeconf |= PIPECONF_DITHER_EN |
9057 PIPECONF_DITHER_TYPE_SP;
9059 switch (crtc_state->pipe_bpp) {
9061 pipeconf |= PIPECONF_6BPC;
9064 pipeconf |= PIPECONF_8BPC;
9067 pipeconf |= PIPECONF_10BPC;
9070 /* Case prevented by intel_choose_pipe_bpp_dither. */
9075 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9076 if (INTEL_GEN(dev_priv) < 4 ||
9077 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9078 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9080 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9082 pipeconf |= PIPECONF_PROGRESSIVE;
9085 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9086 crtc_state->limited_color_range)
9087 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9089 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9091 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9093 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9094 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9097 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9098 struct intel_crtc_state *crtc_state)
9100 struct drm_device *dev = crtc->base.dev;
9101 struct drm_i915_private *dev_priv = to_i915(dev);
9102 const struct intel_limit *limit;
9105 memset(&crtc_state->dpll_hw_state, 0,
9106 sizeof(crtc_state->dpll_hw_state));
9108 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9109 if (intel_panel_use_ssc(dev_priv)) {
9110 refclk = dev_priv->vbt.lvds_ssc_freq;
9111 drm_dbg_kms(&dev_priv->drm,
9112 "using SSC reference clock of %d kHz\n",
9116 limit = &intel_limits_i8xx_lvds;
9117 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9118 limit = &intel_limits_i8xx_dvo;
9120 limit = &intel_limits_i8xx_dac;
9123 if (!crtc_state->clock_set &&
9124 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9125 refclk, NULL, &crtc_state->dpll)) {
9126 drm_err(&dev_priv->drm,
9127 "Couldn't find PLL settings for mode!\n");
9131 i8xx_compute_dpll(crtc, crtc_state, NULL);
9136 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9137 struct intel_crtc_state *crtc_state)
9139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9140 const struct intel_limit *limit;
9143 memset(&crtc_state->dpll_hw_state, 0,
9144 sizeof(crtc_state->dpll_hw_state));
9146 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9147 if (intel_panel_use_ssc(dev_priv)) {
9148 refclk = dev_priv->vbt.lvds_ssc_freq;
9149 drm_dbg_kms(&dev_priv->drm,
9150 "using SSC reference clock of %d kHz\n",
9154 if (intel_is_dual_link_lvds(dev_priv))
9155 limit = &intel_limits_g4x_dual_channel_lvds;
9157 limit = &intel_limits_g4x_single_channel_lvds;
9158 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9159 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9160 limit = &intel_limits_g4x_hdmi;
9161 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9162 limit = &intel_limits_g4x_sdvo;
9164 /* The option is for other outputs */
9165 limit = &intel_limits_i9xx_sdvo;
9168 if (!crtc_state->clock_set &&
9169 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9170 refclk, NULL, &crtc_state->dpll)) {
9171 drm_err(&dev_priv->drm,
9172 "Couldn't find PLL settings for mode!\n");
9176 i9xx_compute_dpll(crtc, crtc_state, NULL);
9181 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9182 struct intel_crtc_state *crtc_state)
9184 struct drm_device *dev = crtc->base.dev;
9185 struct drm_i915_private *dev_priv = to_i915(dev);
9186 const struct intel_limit *limit;
9189 memset(&crtc_state->dpll_hw_state, 0,
9190 sizeof(crtc_state->dpll_hw_state));
9192 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9193 if (intel_panel_use_ssc(dev_priv)) {
9194 refclk = dev_priv->vbt.lvds_ssc_freq;
9195 drm_dbg_kms(&dev_priv->drm,
9196 "using SSC reference clock of %d kHz\n",
9200 limit = &pnv_limits_lvds;
9202 limit = &pnv_limits_sdvo;
9205 if (!crtc_state->clock_set &&
9206 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9207 refclk, NULL, &crtc_state->dpll)) {
9208 drm_err(&dev_priv->drm,
9209 "Couldn't find PLL settings for mode!\n");
9213 i9xx_compute_dpll(crtc, crtc_state, NULL);
9218 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9219 struct intel_crtc_state *crtc_state)
9221 struct drm_device *dev = crtc->base.dev;
9222 struct drm_i915_private *dev_priv = to_i915(dev);
9223 const struct intel_limit *limit;
9226 memset(&crtc_state->dpll_hw_state, 0,
9227 sizeof(crtc_state->dpll_hw_state));
9229 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9230 if (intel_panel_use_ssc(dev_priv)) {
9231 refclk = dev_priv->vbt.lvds_ssc_freq;
9232 drm_dbg_kms(&dev_priv->drm,
9233 "using SSC reference clock of %d kHz\n",
9237 limit = &intel_limits_i9xx_lvds;
9239 limit = &intel_limits_i9xx_sdvo;
9242 if (!crtc_state->clock_set &&
9243 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9244 refclk, NULL, &crtc_state->dpll)) {
9245 drm_err(&dev_priv->drm,
9246 "Couldn't find PLL settings for mode!\n");
9250 i9xx_compute_dpll(crtc, crtc_state, NULL);
9255 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9256 struct intel_crtc_state *crtc_state)
9258 int refclk = 100000;
9259 const struct intel_limit *limit = &intel_limits_chv;
9260 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9262 memset(&crtc_state->dpll_hw_state, 0,
9263 sizeof(crtc_state->dpll_hw_state));
9265 if (!crtc_state->clock_set &&
9266 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9267 refclk, NULL, &crtc_state->dpll)) {
9268 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9272 chv_compute_dpll(crtc, crtc_state);
9277 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9278 struct intel_crtc_state *crtc_state)
9280 int refclk = 100000;
9281 const struct intel_limit *limit = &intel_limits_vlv;
9282 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9284 memset(&crtc_state->dpll_hw_state, 0,
9285 sizeof(crtc_state->dpll_hw_state));
9287 if (!crtc_state->clock_set &&
9288 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9289 refclk, NULL, &crtc_state->dpll)) {
9290 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9294 vlv_compute_dpll(crtc, crtc_state);
9299 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9301 if (IS_I830(dev_priv))
9304 return INTEL_GEN(dev_priv) >= 4 ||
9305 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9308 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9310 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9314 if (!i9xx_has_pfit(dev_priv))
9317 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9318 if (!(tmp & PFIT_ENABLE))
9321 /* Check whether the pfit is attached to our pipe. */
9322 if (INTEL_GEN(dev_priv) < 4) {
9323 if (crtc->pipe != PIPE_B)
9326 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9330 crtc_state->gmch_pfit.control = tmp;
9331 crtc_state->gmch_pfit.pgm_ratios =
9332 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9335 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9336 struct intel_crtc_state *pipe_config)
9338 struct drm_device *dev = crtc->base.dev;
9339 struct drm_i915_private *dev_priv = to_i915(dev);
9340 enum pipe pipe = crtc->pipe;
9343 int refclk = 100000;
9345 /* In case of DSI, DPLL will not be used */
9346 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9349 vlv_dpio_get(dev_priv);
9350 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9351 vlv_dpio_put(dev_priv);
9353 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9354 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9355 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9356 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9357 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9359 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9363 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9364 struct intel_initial_plane_config *plane_config)
9366 struct drm_device *dev = crtc->base.dev;
9367 struct drm_i915_private *dev_priv = to_i915(dev);
9368 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9369 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9371 u32 val, base, offset;
9372 int fourcc, pixel_format;
9373 unsigned int aligned_height;
9374 struct drm_framebuffer *fb;
9375 struct intel_framebuffer *intel_fb;
9377 if (!plane->get_hw_state(plane, &pipe))
9380 drm_WARN_ON(dev, pipe != crtc->pipe);
9382 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9384 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9388 fb = &intel_fb->base;
9392 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9394 if (INTEL_GEN(dev_priv) >= 4) {
9395 if (val & DISPPLANE_TILED) {
9396 plane_config->tiling = I915_TILING_X;
9397 fb->modifier = I915_FORMAT_MOD_X_TILED;
9400 if (val & DISPPLANE_ROTATE_180)
9401 plane_config->rotation = DRM_MODE_ROTATE_180;
9404 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9405 val & DISPPLANE_MIRROR)
9406 plane_config->rotation |= DRM_MODE_REFLECT_X;
9408 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9409 fourcc = i9xx_format_to_fourcc(pixel_format);
9410 fb->format = drm_format_info(fourcc);
9412 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9413 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9414 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9415 } else if (INTEL_GEN(dev_priv) >= 4) {
9416 if (plane_config->tiling)
9417 offset = intel_de_read(dev_priv,
9418 DSPTILEOFF(i9xx_plane));
9420 offset = intel_de_read(dev_priv,
9421 DSPLINOFF(i9xx_plane));
9422 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9424 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9426 plane_config->base = base;
9428 val = intel_de_read(dev_priv, PIPESRC(pipe));
9429 fb->width = ((val >> 16) & 0xfff) + 1;
9430 fb->height = ((val >> 0) & 0xfff) + 1;
9432 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9433 fb->pitches[0] = val & 0xffffffc0;
9435 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9437 plane_config->size = fb->pitches[0] * aligned_height;
9439 drm_dbg_kms(&dev_priv->drm,
9440 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9441 crtc->base.name, plane->base.name, fb->width, fb->height,
9442 fb->format->cpp[0] * 8, base, fb->pitches[0],
9443 plane_config->size);
9445 plane_config->fb = intel_fb;
9448 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9449 struct intel_crtc_state *pipe_config)
9451 struct drm_device *dev = crtc->base.dev;
9452 struct drm_i915_private *dev_priv = to_i915(dev);
9453 enum pipe pipe = crtc->pipe;
9454 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9456 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9457 int refclk = 100000;
9459 /* In case of DSI, DPLL will not be used */
9460 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9463 vlv_dpio_get(dev_priv);
9464 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9465 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9466 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9467 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9468 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9469 vlv_dpio_put(dev_priv);
9471 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9472 clock.m2 = (pll_dw0 & 0xff) << 22;
9473 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9474 clock.m2 |= pll_dw2 & 0x3fffff;
9475 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9476 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9477 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9479 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9482 static enum intel_output_format
9483 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9488 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9490 if (tmp & PIPEMISC_YUV420_ENABLE) {
9491 /* We support 4:2:0 in full blend mode only */
9492 drm_WARN_ON(&dev_priv->drm,
9493 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9495 return INTEL_OUTPUT_FORMAT_YCBCR420;
9496 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9497 return INTEL_OUTPUT_FORMAT_YCBCR444;
9499 return INTEL_OUTPUT_FORMAT_RGB;
9503 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9505 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9506 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9507 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9508 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9511 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9513 if (tmp & DISPPLANE_GAMMA_ENABLE)
9514 crtc_state->gamma_enable = true;
9516 if (!HAS_GMCH(dev_priv) &&
9517 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9518 crtc_state->csc_enable = true;
9521 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9522 struct intel_crtc_state *pipe_config)
9524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9525 enum intel_display_power_domain power_domain;
9526 intel_wakeref_t wakeref;
9530 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9531 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9535 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9536 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9537 pipe_config->shared_dpll = NULL;
9541 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9542 if (!(tmp & PIPECONF_ENABLE))
9545 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9546 IS_CHERRYVIEW(dev_priv)) {
9547 switch (tmp & PIPECONF_BPC_MASK) {
9549 pipe_config->pipe_bpp = 18;
9552 pipe_config->pipe_bpp = 24;
9554 case PIPECONF_10BPC:
9555 pipe_config->pipe_bpp = 30;
9562 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9563 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9564 pipe_config->limited_color_range = true;
9566 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9567 PIPECONF_GAMMA_MODE_SHIFT;
9569 if (IS_CHERRYVIEW(dev_priv))
9570 pipe_config->cgm_mode = intel_de_read(dev_priv,
9571 CGM_PIPE_MODE(crtc->pipe));
9573 i9xx_get_pipe_color_config(pipe_config);
9574 intel_color_get_config(pipe_config);
9576 if (INTEL_GEN(dev_priv) < 4)
9577 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9579 intel_get_transcoder_timings(crtc, pipe_config);
9580 intel_get_pipe_src_size(crtc, pipe_config);
9582 i9xx_get_pfit_config(pipe_config);
9584 if (INTEL_GEN(dev_priv) >= 4) {
9585 /* No way to read it out on pipes B and C */
9586 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9587 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9589 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9590 pipe_config->pixel_multiplier =
9591 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9592 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9593 pipe_config->dpll_hw_state.dpll_md = tmp;
9594 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9595 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9596 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9597 pipe_config->pixel_multiplier =
9598 ((tmp & SDVO_MULTIPLIER_MASK)
9599 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9601 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9602 * port and will be fixed up in the encoder->get_config
9604 pipe_config->pixel_multiplier = 1;
9606 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9608 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9609 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9611 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9614 /* Mask out read-only status bits. */
9615 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9616 DPLL_PORTC_READY_MASK |
9617 DPLL_PORTB_READY_MASK);
9620 if (IS_CHERRYVIEW(dev_priv))
9621 chv_crtc_clock_get(crtc, pipe_config);
9622 else if (IS_VALLEYVIEW(dev_priv))
9623 vlv_crtc_clock_get(crtc, pipe_config);
9625 i9xx_crtc_clock_get(crtc, pipe_config);
9628 * Normally the dotclock is filled in by the encoder .get_config()
9629 * but in case the pipe is enabled w/o any ports we need a sane
9632 pipe_config->hw.adjusted_mode.crtc_clock =
9633 pipe_config->port_clock / pipe_config->pixel_multiplier;
9638 intel_display_power_put(dev_priv, power_domain, wakeref);
9643 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9645 struct intel_encoder *encoder;
9648 bool has_lvds = false;
9649 bool has_cpu_edp = false;
9650 bool has_panel = false;
9651 bool has_ck505 = false;
9652 bool can_ssc = false;
9653 bool using_ssc_source = false;
9655 /* We need to take the global config into account */
9656 for_each_intel_encoder(&dev_priv->drm, encoder) {
9657 switch (encoder->type) {
9658 case INTEL_OUTPUT_LVDS:
9662 case INTEL_OUTPUT_EDP:
9664 if (encoder->port == PORT_A)
9672 if (HAS_PCH_IBX(dev_priv)) {
9673 has_ck505 = dev_priv->vbt.display_clock_mode;
9674 can_ssc = has_ck505;
9680 /* Check if any DPLLs are using the SSC source */
9681 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9682 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9684 if (!(temp & DPLL_VCO_ENABLE))
9687 if ((temp & PLL_REF_INPUT_MASK) ==
9688 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9689 using_ssc_source = true;
9694 drm_dbg_kms(&dev_priv->drm,
9695 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9696 has_panel, has_lvds, has_ck505, using_ssc_source);
9698 /* Ironlake: try to setup display ref clock before DPLL
9699 * enabling. This is only under driver's control after
9700 * PCH B stepping, previous chipset stepping should be
9701 * ignoring this setting.
9703 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9705 /* As we must carefully and slowly disable/enable each source in turn,
9706 * compute the final state we want first and check if we need to
9707 * make any changes at all.
9710 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9712 final |= DREF_NONSPREAD_CK505_ENABLE;
9714 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9716 final &= ~DREF_SSC_SOURCE_MASK;
9717 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9718 final &= ~DREF_SSC1_ENABLE;
9721 final |= DREF_SSC_SOURCE_ENABLE;
9723 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9724 final |= DREF_SSC1_ENABLE;
9727 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9728 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9730 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9732 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9733 } else if (using_ssc_source) {
9734 final |= DREF_SSC_SOURCE_ENABLE;
9735 final |= DREF_SSC1_ENABLE;
9741 /* Always enable nonspread source */
9742 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9745 val |= DREF_NONSPREAD_CK505_ENABLE;
9747 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9750 val &= ~DREF_SSC_SOURCE_MASK;
9751 val |= DREF_SSC_SOURCE_ENABLE;
9753 /* SSC must be turned on before enabling the CPU output */
9754 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9755 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9756 val |= DREF_SSC1_ENABLE;
9758 val &= ~DREF_SSC1_ENABLE;
9760 /* Get SSC going before enabling the outputs */
9761 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9762 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9765 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9767 /* Enable CPU source on CPU attached eDP */
9769 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9770 drm_dbg_kms(&dev_priv->drm,
9771 "Using SSC on eDP\n");
9772 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9774 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9776 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9778 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9779 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9782 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9784 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9786 /* Turn off CPU output */
9787 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9789 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9790 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9793 if (!using_ssc_source) {
9794 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9796 /* Turn off the SSC source */
9797 val &= ~DREF_SSC_SOURCE_MASK;
9798 val |= DREF_SSC_SOURCE_DISABLE;
9801 val &= ~DREF_SSC1_ENABLE;
9803 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9804 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9809 BUG_ON(val != final);
9812 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9816 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9817 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9818 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9820 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9821 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9822 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9824 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9825 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9826 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9828 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9829 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9830 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9833 /* WaMPhyProgramming:hsw */
9834 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9838 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9839 tmp &= ~(0xFF << 24);
9840 tmp |= (0x12 << 24);
9841 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9843 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9845 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9847 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9849 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9851 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9852 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9853 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9855 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9856 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9857 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9859 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9862 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9864 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9867 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9869 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9872 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9874 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9877 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9879 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9880 tmp &= ~(0xFF << 16);
9881 tmp |= (0x1C << 16);
9882 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9884 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9885 tmp &= ~(0xFF << 16);
9886 tmp |= (0x1C << 16);
9887 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9889 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9891 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9893 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9895 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9897 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9898 tmp &= ~(0xF << 28);
9900 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9902 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9903 tmp &= ~(0xF << 28);
9905 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9908 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9909 * Programming" based on the parameters passed:
9910 * - Sequence to enable CLKOUT_DP
9911 * - Sequence to enable CLKOUT_DP without spread
9912 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9914 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9915 bool with_spread, bool with_fdi)
9919 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9920 "FDI requires downspread\n"))
9922 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9923 with_fdi, "LP PCH doesn't have FDI\n"))
9926 mutex_lock(&dev_priv->sb_lock);
9928 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9929 tmp &= ~SBI_SSCCTL_DISABLE;
9930 tmp |= SBI_SSCCTL_PATHALT;
9931 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9936 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9937 tmp &= ~SBI_SSCCTL_PATHALT;
9938 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9941 lpt_reset_fdi_mphy(dev_priv);
9942 lpt_program_fdi_mphy(dev_priv);
9946 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9947 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9948 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9949 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9951 mutex_unlock(&dev_priv->sb_lock);
9954 /* Sequence to disable CLKOUT_DP */
9955 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9959 mutex_lock(&dev_priv->sb_lock);
9961 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9962 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9963 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9964 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9966 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9967 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9968 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9969 tmp |= SBI_SSCCTL_PATHALT;
9970 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9973 tmp |= SBI_SSCCTL_DISABLE;
9974 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9977 mutex_unlock(&dev_priv->sb_lock);
9980 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9982 static const u16 sscdivintphase[] = {
9983 [BEND_IDX( 50)] = 0x3B23,
9984 [BEND_IDX( 45)] = 0x3B23,
9985 [BEND_IDX( 40)] = 0x3C23,
9986 [BEND_IDX( 35)] = 0x3C23,
9987 [BEND_IDX( 30)] = 0x3D23,
9988 [BEND_IDX( 25)] = 0x3D23,
9989 [BEND_IDX( 20)] = 0x3E23,
9990 [BEND_IDX( 15)] = 0x3E23,
9991 [BEND_IDX( 10)] = 0x3F23,
9992 [BEND_IDX( 5)] = 0x3F23,
9993 [BEND_IDX( 0)] = 0x0025,
9994 [BEND_IDX( -5)] = 0x0025,
9995 [BEND_IDX(-10)] = 0x0125,
9996 [BEND_IDX(-15)] = 0x0125,
9997 [BEND_IDX(-20)] = 0x0225,
9998 [BEND_IDX(-25)] = 0x0225,
9999 [BEND_IDX(-30)] = 0x0325,
10000 [BEND_IDX(-35)] = 0x0325,
10001 [BEND_IDX(-40)] = 0x0425,
10002 [BEND_IDX(-45)] = 0x0425,
10003 [BEND_IDX(-50)] = 0x0525,
10008 * steps -50 to 50 inclusive, in steps of 5
10009 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
10010 * change in clock period = -(steps / 10) * 5.787 ps
10012 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
10015 int idx = BEND_IDX(steps);
10017 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
10020 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
10023 mutex_lock(&dev_priv->sb_lock);
10025 if (steps % 10 != 0)
10029 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
10031 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
10033 tmp |= sscdivintphase[idx];
10034 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
10036 mutex_unlock(&dev_priv->sb_lock);
10041 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
10043 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10044 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
10046 if ((ctl & SPLL_PLL_ENABLE) == 0)
10049 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
10050 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10053 if (IS_BROADWELL(dev_priv) &&
10054 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10060 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10061 enum intel_dpll_id id)
10063 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10064 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10066 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10069 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10072 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10073 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10074 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10080 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10082 struct intel_encoder *encoder;
10083 bool has_fdi = false;
10085 for_each_intel_encoder(&dev_priv->drm, encoder) {
10086 switch (encoder->type) {
10087 case INTEL_OUTPUT_ANALOG:
10096 * The BIOS may have decided to use the PCH SSC
10097 * reference so we must not disable it until the
10098 * relevant PLLs have stopped relying on it. We'll
10099 * just leave the PCH SSC reference enabled in case
10100 * any active PLL is using it. It will get disabled
10101 * after runtime suspend if we don't have FDI.
10103 * TODO: Move the whole reference clock handling
10104 * to the modeset sequence proper so that we can
10105 * actually enable/disable/reconfigure these things
10106 * safely. To do that we need to introduce a real
10107 * clock hierarchy. That would also allow us to do
10108 * clock bending finally.
10110 dev_priv->pch_ssc_use = 0;
10112 if (spll_uses_pch_ssc(dev_priv)) {
10113 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10114 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10117 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10118 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10119 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10122 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10123 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10124 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10127 if (dev_priv->pch_ssc_use)
10131 lpt_bend_clkout_dp(dev_priv, 0);
10132 lpt_enable_clkout_dp(dev_priv, true, true);
10134 lpt_disable_clkout_dp(dev_priv);
10139 * Initialize reference clocks when the driver loads
10141 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10143 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10144 ilk_init_pch_refclk(dev_priv);
10145 else if (HAS_PCH_LPT(dev_priv))
10146 lpt_init_pch_refclk(dev_priv);
10149 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10152 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10153 enum pipe pipe = crtc->pipe;
10158 switch (crtc_state->pipe_bpp) {
10160 val |= PIPECONF_6BPC;
10163 val |= PIPECONF_8BPC;
10166 val |= PIPECONF_10BPC;
10169 val |= PIPECONF_12BPC;
10172 /* Case prevented by intel_choose_pipe_bpp_dither. */
10176 if (crtc_state->dither)
10177 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10179 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10180 val |= PIPECONF_INTERLACED_ILK;
10182 val |= PIPECONF_PROGRESSIVE;
10185 * This would end up with an odd purple hue over
10186 * the entire display. Make sure we don't do it.
10188 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10189 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10191 if (crtc_state->limited_color_range &&
10192 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10193 val |= PIPECONF_COLOR_RANGE_SELECT;
10195 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10196 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10198 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10200 val |= PIPECONF_FRAME_START_DELAY(0);
10202 intel_de_write(dev_priv, PIPECONF(pipe), val);
10203 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10206 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10210 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10213 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10214 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10216 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10217 val |= PIPECONF_INTERLACED_ILK;
10219 val |= PIPECONF_PROGRESSIVE;
10221 if (IS_HASWELL(dev_priv) &&
10222 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10223 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10225 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10226 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10229 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10231 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10232 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10235 switch (crtc_state->pipe_bpp) {
10237 val |= PIPEMISC_DITHER_6_BPC;
10240 val |= PIPEMISC_DITHER_8_BPC;
10243 val |= PIPEMISC_DITHER_10_BPC;
10246 val |= PIPEMISC_DITHER_12_BPC;
10249 MISSING_CASE(crtc_state->pipe_bpp);
10253 if (crtc_state->dither)
10254 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10256 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10257 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10258 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10260 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10261 val |= PIPEMISC_YUV420_ENABLE |
10262 PIPEMISC_YUV420_MODE_FULL_BLEND;
10264 if (INTEL_GEN(dev_priv) >= 11 &&
10265 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10266 BIT(PLANE_CURSOR))) == 0)
10267 val |= PIPEMISC_HDR_MODE_PRECISION;
10269 if (INTEL_GEN(dev_priv) >= 12)
10270 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10272 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10275 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10277 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10280 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10282 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10283 case PIPEMISC_DITHER_6_BPC:
10285 case PIPEMISC_DITHER_8_BPC:
10287 case PIPEMISC_DITHER_10_BPC:
10289 case PIPEMISC_DITHER_12_BPC:
10297 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10300 * Account for spread spectrum to avoid
10301 * oversubscribing the link. Max center spread
10302 * is 2.5%; use 5% for safety's sake.
10304 u32 bps = target_clock * bpp * 21 / 20;
10305 return DIV_ROUND_UP(bps, link_bw * 8);
10308 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10310 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10313 static void ilk_compute_dpll(struct intel_crtc *crtc,
10314 struct intel_crtc_state *crtc_state,
10315 struct dpll *reduced_clock)
10317 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10321 /* Enable autotuning of the PLL clock (if permissible) */
10323 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10324 if ((intel_panel_use_ssc(dev_priv) &&
10325 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10326 (HAS_PCH_IBX(dev_priv) &&
10327 intel_is_dual_link_lvds(dev_priv)))
10329 } else if (crtc_state->sdvo_tv_clock) {
10333 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10335 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10338 if (reduced_clock) {
10339 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10341 if (reduced_clock->m < factor * reduced_clock->n)
10349 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10350 dpll |= DPLLB_MODE_LVDS;
10352 dpll |= DPLLB_MODE_DAC_SERIAL;
10354 dpll |= (crtc_state->pixel_multiplier - 1)
10355 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10357 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10358 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10359 dpll |= DPLL_SDVO_HIGH_SPEED;
10361 if (intel_crtc_has_dp_encoder(crtc_state))
10362 dpll |= DPLL_SDVO_HIGH_SPEED;
10365 * The high speed IO clock is only really required for
10366 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10367 * possible to share the DPLL between CRT and HDMI. Enabling
10368 * the clock needlessly does no real harm, except use up a
10369 * bit of power potentially.
10371 * We'll limit this to IVB with 3 pipes, since it has only two
10372 * DPLLs and so DPLL sharing is the only way to get three pipes
10373 * driving PCH ports at the same time. On SNB we could do this,
10374 * and potentially avoid enabling the second DPLL, but it's not
10375 * clear if it''s a win or loss power wise. No point in doing
10376 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10378 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10379 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10380 dpll |= DPLL_SDVO_HIGH_SPEED;
10382 /* compute bitmask from p1 value */
10383 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10385 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10387 switch (crtc_state->dpll.p2) {
10389 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10392 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10395 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10398 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10402 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10403 intel_panel_use_ssc(dev_priv))
10404 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10406 dpll |= PLL_REF_INPUT_DREFCLK;
10408 dpll |= DPLL_VCO_ENABLE;
10410 crtc_state->dpll_hw_state.dpll = dpll;
10411 crtc_state->dpll_hw_state.fp0 = fp;
10412 crtc_state->dpll_hw_state.fp1 = fp2;
10415 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10416 struct intel_crtc_state *crtc_state)
10418 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10419 struct intel_atomic_state *state =
10420 to_intel_atomic_state(crtc_state->uapi.state);
10421 const struct intel_limit *limit;
10422 int refclk = 120000;
10424 memset(&crtc_state->dpll_hw_state, 0,
10425 sizeof(crtc_state->dpll_hw_state));
10427 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10428 if (!crtc_state->has_pch_encoder)
10431 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10432 if (intel_panel_use_ssc(dev_priv)) {
10433 drm_dbg_kms(&dev_priv->drm,
10434 "using SSC reference clock of %d kHz\n",
10435 dev_priv->vbt.lvds_ssc_freq);
10436 refclk = dev_priv->vbt.lvds_ssc_freq;
10439 if (intel_is_dual_link_lvds(dev_priv)) {
10440 if (refclk == 100000)
10441 limit = &ilk_limits_dual_lvds_100m;
10443 limit = &ilk_limits_dual_lvds;
10445 if (refclk == 100000)
10446 limit = &ilk_limits_single_lvds_100m;
10448 limit = &ilk_limits_single_lvds;
10451 limit = &ilk_limits_dac;
10454 if (!crtc_state->clock_set &&
10455 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10456 refclk, NULL, &crtc_state->dpll)) {
10457 drm_err(&dev_priv->drm,
10458 "Couldn't find PLL settings for mode!\n");
10462 ilk_compute_dpll(crtc, crtc_state, NULL);
10464 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10465 drm_dbg_kms(&dev_priv->drm,
10466 "failed to find PLL for pipe %c\n",
10467 pipe_name(crtc->pipe));
10474 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10475 struct intel_link_m_n *m_n)
10477 struct drm_device *dev = crtc->base.dev;
10478 struct drm_i915_private *dev_priv = to_i915(dev);
10479 enum pipe pipe = crtc->pipe;
10481 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10482 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10483 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10485 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10486 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10487 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10490 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10491 enum transcoder transcoder,
10492 struct intel_link_m_n *m_n,
10493 struct intel_link_m_n *m2_n2)
10495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10496 enum pipe pipe = crtc->pipe;
10498 if (INTEL_GEN(dev_priv) >= 5) {
10499 m_n->link_m = intel_de_read(dev_priv,
10500 PIPE_LINK_M1(transcoder));
10501 m_n->link_n = intel_de_read(dev_priv,
10502 PIPE_LINK_N1(transcoder));
10503 m_n->gmch_m = intel_de_read(dev_priv,
10504 PIPE_DATA_M1(transcoder))
10506 m_n->gmch_n = intel_de_read(dev_priv,
10507 PIPE_DATA_N1(transcoder));
10508 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10509 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10511 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10512 m2_n2->link_m = intel_de_read(dev_priv,
10513 PIPE_LINK_M2(transcoder));
10514 m2_n2->link_n = intel_de_read(dev_priv,
10515 PIPE_LINK_N2(transcoder));
10516 m2_n2->gmch_m = intel_de_read(dev_priv,
10517 PIPE_DATA_M2(transcoder))
10519 m2_n2->gmch_n = intel_de_read(dev_priv,
10520 PIPE_DATA_N2(transcoder));
10521 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10522 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10525 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10526 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10527 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10529 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10530 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10531 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10535 void intel_dp_get_m_n(struct intel_crtc *crtc,
10536 struct intel_crtc_state *pipe_config)
10538 if (pipe_config->has_pch_encoder)
10539 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10541 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10542 &pipe_config->dp_m_n,
10543 &pipe_config->dp_m2_n2);
10546 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10547 struct intel_crtc_state *pipe_config)
10549 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10550 &pipe_config->fdi_m_n, NULL);
10553 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10556 drm_rect_init(&crtc_state->pch_pfit.dst,
10557 pos >> 16, pos & 0xffff,
10558 size >> 16, size & 0xffff);
10561 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10563 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10564 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10565 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10569 /* find scaler attached to this pipe */
10570 for (i = 0; i < crtc->num_scalers; i++) {
10571 u32 ctl, pos, size;
10573 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10574 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10578 crtc_state->pch_pfit.enabled = true;
10580 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10581 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10583 ilk_get_pfit_pos_size(crtc_state, pos, size);
10585 scaler_state->scalers[i].in_use = true;
10589 scaler_state->scaler_id = id;
10591 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10593 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10597 skl_get_initial_plane_config(struct intel_crtc *crtc,
10598 struct intel_initial_plane_config *plane_config)
10600 struct drm_device *dev = crtc->base.dev;
10601 struct drm_i915_private *dev_priv = to_i915(dev);
10602 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10603 enum plane_id plane_id = plane->id;
10605 u32 val, base, offset, stride_mult, tiling, alpha;
10606 int fourcc, pixel_format;
10607 unsigned int aligned_height;
10608 struct drm_framebuffer *fb;
10609 struct intel_framebuffer *intel_fb;
10611 if (!plane->get_hw_state(plane, &pipe))
10614 drm_WARN_ON(dev, pipe != crtc->pipe);
10616 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10618 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10622 fb = &intel_fb->base;
10626 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10628 if (INTEL_GEN(dev_priv) >= 11)
10629 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10631 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10633 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10634 alpha = intel_de_read(dev_priv,
10635 PLANE_COLOR_CTL(pipe, plane_id));
10636 alpha &= PLANE_COLOR_ALPHA_MASK;
10638 alpha = val & PLANE_CTL_ALPHA_MASK;
10641 fourcc = skl_format_to_fourcc(pixel_format,
10642 val & PLANE_CTL_ORDER_RGBX, alpha);
10643 fb->format = drm_format_info(fourcc);
10645 tiling = val & PLANE_CTL_TILED_MASK;
10647 case PLANE_CTL_TILED_LINEAR:
10648 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10650 case PLANE_CTL_TILED_X:
10651 plane_config->tiling = I915_TILING_X;
10652 fb->modifier = I915_FORMAT_MOD_X_TILED;
10654 case PLANE_CTL_TILED_Y:
10655 plane_config->tiling = I915_TILING_Y;
10656 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10657 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10658 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10659 I915_FORMAT_MOD_Y_TILED_CCS;
10660 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10661 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10663 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10665 case PLANE_CTL_TILED_YF:
10666 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10667 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10669 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10672 MISSING_CASE(tiling);
10677 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10678 * while i915 HW rotation is clockwise, thats why this swapping.
10680 switch (val & PLANE_CTL_ROTATE_MASK) {
10681 case PLANE_CTL_ROTATE_0:
10682 plane_config->rotation = DRM_MODE_ROTATE_0;
10684 case PLANE_CTL_ROTATE_90:
10685 plane_config->rotation = DRM_MODE_ROTATE_270;
10687 case PLANE_CTL_ROTATE_180:
10688 plane_config->rotation = DRM_MODE_ROTATE_180;
10690 case PLANE_CTL_ROTATE_270:
10691 plane_config->rotation = DRM_MODE_ROTATE_90;
10695 if (INTEL_GEN(dev_priv) >= 10 &&
10696 val & PLANE_CTL_FLIP_HORIZONTAL)
10697 plane_config->rotation |= DRM_MODE_REFLECT_X;
10699 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10700 plane_config->base = base;
10702 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10704 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10705 fb->height = ((val >> 16) & 0xffff) + 1;
10706 fb->width = ((val >> 0) & 0xffff) + 1;
10708 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10709 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10710 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10712 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10714 plane_config->size = fb->pitches[0] * aligned_height;
10716 drm_dbg_kms(&dev_priv->drm,
10717 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10718 crtc->base.name, plane->base.name, fb->width, fb->height,
10719 fb->format->cpp[0] * 8, base, fb->pitches[0],
10720 plane_config->size);
10722 plane_config->fb = intel_fb;
10729 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10733 u32 ctl, pos, size;
10735 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10736 if ((ctl & PF_ENABLE) == 0)
10739 crtc_state->pch_pfit.enabled = true;
10741 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10742 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10744 ilk_get_pfit_pos_size(crtc_state, pos, size);
10747 * We currently do not free assignements of panel fitters on
10748 * ivb/hsw (since we don't use the higher upscaling modes which
10749 * differentiates them) so just WARN about this case for now.
10751 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10752 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10755 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10756 struct intel_crtc_state *pipe_config)
10758 struct drm_device *dev = crtc->base.dev;
10759 struct drm_i915_private *dev_priv = to_i915(dev);
10760 enum intel_display_power_domain power_domain;
10761 intel_wakeref_t wakeref;
10765 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10766 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10770 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10771 pipe_config->shared_dpll = NULL;
10774 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10775 if (!(tmp & PIPECONF_ENABLE))
10778 switch (tmp & PIPECONF_BPC_MASK) {
10779 case PIPECONF_6BPC:
10780 pipe_config->pipe_bpp = 18;
10782 case PIPECONF_8BPC:
10783 pipe_config->pipe_bpp = 24;
10785 case PIPECONF_10BPC:
10786 pipe_config->pipe_bpp = 30;
10788 case PIPECONF_12BPC:
10789 pipe_config->pipe_bpp = 36;
10795 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10796 pipe_config->limited_color_range = true;
10798 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10799 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10800 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10801 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10804 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10808 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10809 PIPECONF_GAMMA_MODE_SHIFT;
10811 pipe_config->csc_mode = intel_de_read(dev_priv,
10812 PIPE_CSC_MODE(crtc->pipe));
10814 i9xx_get_pipe_color_config(pipe_config);
10815 intel_color_get_config(pipe_config);
10817 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10818 struct intel_shared_dpll *pll;
10819 enum intel_dpll_id pll_id;
10821 pipe_config->has_pch_encoder = true;
10823 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10824 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10825 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10827 ilk_get_fdi_m_n_config(crtc, pipe_config);
10829 if (HAS_PCH_IBX(dev_priv)) {
10831 * The pipe->pch transcoder and pch transcoder->pll
10832 * mapping is fixed.
10834 pll_id = (enum intel_dpll_id) crtc->pipe;
10836 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10837 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10838 pll_id = DPLL_ID_PCH_PLL_B;
10840 pll_id= DPLL_ID_PCH_PLL_A;
10843 pipe_config->shared_dpll =
10844 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10845 pll = pipe_config->shared_dpll;
10847 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10848 &pipe_config->dpll_hw_state));
10850 tmp = pipe_config->dpll_hw_state.dpll;
10851 pipe_config->pixel_multiplier =
10852 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10853 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10855 ilk_pch_clock_get(crtc, pipe_config);
10857 pipe_config->pixel_multiplier = 1;
10860 intel_get_transcoder_timings(crtc, pipe_config);
10861 intel_get_pipe_src_size(crtc, pipe_config);
10863 ilk_get_pfit_config(pipe_config);
10868 intel_display_power_put(dev_priv, power_domain, wakeref);
10873 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10874 struct intel_crtc_state *crtc_state)
10876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10877 struct intel_atomic_state *state =
10878 to_intel_atomic_state(crtc_state->uapi.state);
10880 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10881 INTEL_GEN(dev_priv) >= 11) {
10882 struct intel_encoder *encoder =
10883 intel_get_crtc_new_encoder(state, crtc_state);
10885 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10886 drm_dbg_kms(&dev_priv->drm,
10887 "failed to find PLL for pipe %c\n",
10888 pipe_name(crtc->pipe));
10896 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10897 struct intel_crtc_state *pipe_config)
10899 enum intel_dpll_id id;
10902 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10903 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10905 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10908 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10911 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10912 struct intel_crtc_state *pipe_config)
10914 enum phy phy = intel_port_to_phy(dev_priv, port);
10915 enum icl_port_dpll_id port_dpll_id;
10916 enum intel_dpll_id id;
10919 if (intel_phy_is_combo(dev_priv, phy)) {
10922 if (IS_ROCKETLAKE(dev_priv)) {
10923 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10924 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10926 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10927 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10930 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10931 id = temp >> shift;
10932 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10933 } else if (intel_phy_is_tc(dev_priv, phy)) {
10934 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10936 if (clk_sel == DDI_CLK_SEL_MG) {
10937 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10939 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10941 drm_WARN_ON(&dev_priv->drm,
10942 clk_sel < DDI_CLK_SEL_TBT_162);
10943 id = DPLL_ID_ICL_TBTPLL;
10944 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10947 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10951 pipe_config->icl_port_dplls[port_dpll_id].pll =
10952 intel_get_shared_dpll_by_id(dev_priv, id);
10954 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10957 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10959 struct intel_crtc_state *pipe_config)
10961 enum intel_dpll_id id;
10965 id = DPLL_ID_SKL_DPLL0;
10968 id = DPLL_ID_SKL_DPLL1;
10971 id = DPLL_ID_SKL_DPLL2;
10974 drm_err(&dev_priv->drm, "Incorrect port type\n");
10978 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10981 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10982 struct intel_crtc_state *pipe_config)
10984 enum intel_dpll_id id;
10987 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10988 id = temp >> (port * 3 + 1);
10990 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10993 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10996 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10997 struct intel_crtc_state *pipe_config)
10999 enum intel_dpll_id id;
11000 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
11002 switch (ddi_pll_sel) {
11003 case PORT_CLK_SEL_WRPLL1:
11004 id = DPLL_ID_WRPLL1;
11006 case PORT_CLK_SEL_WRPLL2:
11007 id = DPLL_ID_WRPLL2;
11009 case PORT_CLK_SEL_SPLL:
11012 case PORT_CLK_SEL_LCPLL_810:
11013 id = DPLL_ID_LCPLL_810;
11015 case PORT_CLK_SEL_LCPLL_1350:
11016 id = DPLL_ID_LCPLL_1350;
11018 case PORT_CLK_SEL_LCPLL_2700:
11019 id = DPLL_ID_LCPLL_2700;
11022 MISSING_CASE(ddi_pll_sel);
11024 case PORT_CLK_SEL_NONE:
11028 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11031 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
11032 struct intel_crtc_state *pipe_config,
11033 u64 *power_domain_mask,
11034 intel_wakeref_t *wakerefs)
11036 struct drm_device *dev = crtc->base.dev;
11037 struct drm_i915_private *dev_priv = to_i915(dev);
11038 enum intel_display_power_domain power_domain;
11039 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
11040 unsigned long enabled_panel_transcoders = 0;
11041 enum transcoder panel_transcoder;
11042 intel_wakeref_t wf;
11045 if (INTEL_GEN(dev_priv) >= 11)
11046 panel_transcoder_mask |=
11047 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
11050 * The pipe->transcoder mapping is fixed with the exception of the eDP
11051 * and DSI transcoders handled below.
11053 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11056 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11057 * consistency and less surprising code; it's in always on power).
11059 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11060 panel_transcoder_mask) {
11061 bool force_thru = false;
11062 enum pipe trans_pipe;
11064 tmp = intel_de_read(dev_priv,
11065 TRANS_DDI_FUNC_CTL(panel_transcoder));
11066 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11070 * Log all enabled ones, only use the first one.
11072 * FIXME: This won't work for two separate DSI displays.
11074 enabled_panel_transcoders |= BIT(panel_transcoder);
11075 if (enabled_panel_transcoders != BIT(panel_transcoder))
11078 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11081 "unknown pipe linked to transcoder %s\n",
11082 transcoder_name(panel_transcoder));
11084 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11087 case TRANS_DDI_EDP_INPUT_A_ON:
11088 trans_pipe = PIPE_A;
11090 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11091 trans_pipe = PIPE_B;
11093 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11094 trans_pipe = PIPE_C;
11096 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11097 trans_pipe = PIPE_D;
11101 if (trans_pipe == crtc->pipe) {
11102 pipe_config->cpu_transcoder = panel_transcoder;
11103 pipe_config->pch_pfit.force_thru = force_thru;
11108 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11110 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11111 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11113 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11114 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11116 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11120 wakerefs[power_domain] = wf;
11121 *power_domain_mask |= BIT_ULL(power_domain);
11123 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11125 return tmp & PIPECONF_ENABLE;
11128 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11129 struct intel_crtc_state *pipe_config,
11130 u64 *power_domain_mask,
11131 intel_wakeref_t *wakerefs)
11133 struct drm_device *dev = crtc->base.dev;
11134 struct drm_i915_private *dev_priv = to_i915(dev);
11135 enum intel_display_power_domain power_domain;
11136 enum transcoder cpu_transcoder;
11137 intel_wakeref_t wf;
11141 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11142 if (port == PORT_A)
11143 cpu_transcoder = TRANSCODER_DSI_A;
11145 cpu_transcoder = TRANSCODER_DSI_C;
11147 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11148 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11150 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11154 wakerefs[power_domain] = wf;
11155 *power_domain_mask |= BIT_ULL(power_domain);
11158 * The PLL needs to be enabled with a valid divider
11159 * configuration, otherwise accessing DSI registers will hang
11160 * the machine. See BSpec North Display Engine
11161 * registers/MIPI[BXT]. We can break out here early, since we
11162 * need the same DSI PLL to be enabled for both DSI ports.
11164 if (!bxt_dsi_pll_is_enabled(dev_priv))
11167 /* XXX: this works for video mode only */
11168 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11169 if (!(tmp & DPI_ENABLE))
11172 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11173 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11176 pipe_config->cpu_transcoder = cpu_transcoder;
11180 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11183 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11184 struct intel_crtc_state *pipe_config)
11186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11187 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11188 struct intel_shared_dpll *pll;
11192 if (transcoder_is_dsi(cpu_transcoder)) {
11193 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11196 tmp = intel_de_read(dev_priv,
11197 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11198 if (INTEL_GEN(dev_priv) >= 12)
11199 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11201 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11204 if (INTEL_GEN(dev_priv) >= 11)
11205 icl_get_ddi_pll(dev_priv, port, pipe_config);
11206 else if (IS_CANNONLAKE(dev_priv))
11207 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11208 else if (IS_GEN9_BC(dev_priv))
11209 skl_get_ddi_pll(dev_priv, port, pipe_config);
11210 else if (IS_GEN9_LP(dev_priv))
11211 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11213 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11215 pll = pipe_config->shared_dpll;
11217 drm_WARN_ON(&dev_priv->drm,
11218 !pll->info->funcs->get_hw_state(dev_priv, pll,
11219 &pipe_config->dpll_hw_state));
11223 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11224 * DDI E. So just check whether this pipe is wired to DDI E and whether
11225 * the PCH transcoder is on.
11227 if (INTEL_GEN(dev_priv) < 9 &&
11228 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11229 pipe_config->has_pch_encoder = true;
11231 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11232 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11233 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11235 ilk_get_fdi_m_n_config(crtc, pipe_config);
11239 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11240 struct intel_crtc_state *pipe_config)
11242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11243 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11244 enum intel_display_power_domain power_domain;
11245 u64 power_domain_mask;
11249 pipe_config->master_transcoder = INVALID_TRANSCODER;
11251 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11252 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11256 wakerefs[power_domain] = wf;
11257 power_domain_mask = BIT_ULL(power_domain);
11259 pipe_config->shared_dpll = NULL;
11261 active = hsw_get_transcoder_state(crtc, pipe_config,
11262 &power_domain_mask, wakerefs);
11264 if (IS_GEN9_LP(dev_priv) &&
11265 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11266 &power_domain_mask, wakerefs)) {
11267 drm_WARN_ON(&dev_priv->drm, active);
11274 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11275 INTEL_GEN(dev_priv) >= 11) {
11276 hsw_get_ddi_port_state(crtc, pipe_config);
11277 intel_get_transcoder_timings(crtc, pipe_config);
11280 intel_get_pipe_src_size(crtc, pipe_config);
11282 if (IS_HASWELL(dev_priv)) {
11283 u32 tmp = intel_de_read(dev_priv,
11284 PIPECONF(pipe_config->cpu_transcoder));
11286 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11287 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11289 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11291 pipe_config->output_format =
11292 bdw_get_pipemisc_output_format(crtc);
11295 pipe_config->gamma_mode = intel_de_read(dev_priv,
11296 GAMMA_MODE(crtc->pipe));
11298 pipe_config->csc_mode = intel_de_read(dev_priv,
11299 PIPE_CSC_MODE(crtc->pipe));
11301 if (INTEL_GEN(dev_priv) >= 9) {
11302 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11304 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11305 pipe_config->gamma_enable = true;
11307 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11308 pipe_config->csc_enable = true;
11310 i9xx_get_pipe_color_config(pipe_config);
11313 intel_color_get_config(pipe_config);
11315 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11316 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11317 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11318 pipe_config->ips_linetime =
11319 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11321 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11322 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11324 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11326 wakerefs[power_domain] = wf;
11327 power_domain_mask |= BIT_ULL(power_domain);
11329 if (INTEL_GEN(dev_priv) >= 9)
11330 skl_get_pfit_config(pipe_config);
11332 ilk_get_pfit_config(pipe_config);
11335 if (hsw_crtc_supports_ips(crtc)) {
11336 if (IS_HASWELL(dev_priv))
11337 pipe_config->ips_enabled = intel_de_read(dev_priv,
11338 IPS_CTL) & IPS_ENABLE;
11341 * We cannot readout IPS state on broadwell, set to
11342 * true so we can set it to a defined state on first
11345 pipe_config->ips_enabled = true;
11349 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11350 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11351 pipe_config->pixel_multiplier =
11352 intel_de_read(dev_priv,
11353 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11355 pipe_config->pixel_multiplier = 1;
11359 for_each_power_domain(power_domain, power_domain_mask)
11360 intel_display_power_put(dev_priv,
11361 power_domain, wakerefs[power_domain]);
11366 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11368 struct drm_i915_private *dev_priv =
11369 to_i915(plane_state->uapi.plane->dev);
11370 const struct drm_framebuffer *fb = plane_state->hw.fb;
11371 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11374 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11375 base = sg_dma_address(obj->mm.pages->sgl);
11377 base = intel_plane_ggtt_offset(plane_state);
11379 return base + plane_state->color_plane[0].offset;
11382 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11384 int x = plane_state->uapi.dst.x1;
11385 int y = plane_state->uapi.dst.y1;
11389 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11392 pos |= x << CURSOR_X_SHIFT;
11395 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11398 pos |= y << CURSOR_Y_SHIFT;
11403 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11405 const struct drm_mode_config *config =
11406 &plane_state->uapi.plane->dev->mode_config;
11407 int width = drm_rect_width(&plane_state->uapi.dst);
11408 int height = drm_rect_height(&plane_state->uapi.dst);
11410 return width > 0 && width <= config->cursor_width &&
11411 height > 0 && height <= config->cursor_height;
11414 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11416 struct drm_i915_private *dev_priv =
11417 to_i915(plane_state->uapi.plane->dev);
11418 unsigned int rotation = plane_state->hw.rotation;
11423 ret = intel_plane_compute_gtt(plane_state);
11427 if (!plane_state->uapi.visible)
11430 src_x = plane_state->uapi.src.x1 >> 16;
11431 src_y = plane_state->uapi.src.y1 >> 16;
11433 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11434 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11437 if (src_x != 0 || src_y != 0) {
11438 drm_dbg_kms(&dev_priv->drm,
11439 "Arbitrary cursor panning not supported\n");
11444 * Put the final coordinates back so that the src
11445 * coordinate checks will see the right values.
11447 drm_rect_translate_to(&plane_state->uapi.src,
11448 src_x << 16, src_y << 16);
11450 /* ILK+ do this automagically in hardware */
11451 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11452 const struct drm_framebuffer *fb = plane_state->hw.fb;
11453 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11454 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11456 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11459 plane_state->color_plane[0].offset = offset;
11460 plane_state->color_plane[0].x = src_x;
11461 plane_state->color_plane[0].y = src_y;
11466 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11467 struct intel_plane_state *plane_state)
11469 const struct drm_framebuffer *fb = plane_state->hw.fb;
11470 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11473 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11474 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11478 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11480 DRM_PLANE_HELPER_NO_SCALING,
11481 DRM_PLANE_HELPER_NO_SCALING,
11486 /* Use the unclipped src/dst rectangles, which we program to hw */
11487 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11488 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11490 ret = intel_cursor_check_surface(plane_state);
11494 if (!plane_state->uapi.visible)
11497 ret = intel_plane_check_src_coordinates(plane_state);
11504 static unsigned int
11505 i845_cursor_max_stride(struct intel_plane *plane,
11506 u32 pixel_format, u64 modifier,
11507 unsigned int rotation)
11512 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11516 if (crtc_state->gamma_enable)
11517 cntl |= CURSOR_GAMMA_ENABLE;
11522 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11523 const struct intel_plane_state *plane_state)
11525 return CURSOR_ENABLE |
11526 CURSOR_FORMAT_ARGB |
11527 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11530 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11532 int width = drm_rect_width(&plane_state->uapi.dst);
11535 * 845g/865g are only limited by the width of their cursors,
11536 * the height is arbitrary up to the precision of the register.
11538 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11541 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11542 struct intel_plane_state *plane_state)
11544 const struct drm_framebuffer *fb = plane_state->hw.fb;
11545 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11548 ret = intel_check_cursor(crtc_state, plane_state);
11552 /* if we want to turn off the cursor ignore width and height */
11556 /* Check for which cursor types we support */
11557 if (!i845_cursor_size_ok(plane_state)) {
11558 drm_dbg_kms(&i915->drm,
11559 "Cursor dimension %dx%d not supported\n",
11560 drm_rect_width(&plane_state->uapi.dst),
11561 drm_rect_height(&plane_state->uapi.dst));
11565 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11566 plane_state->color_plane[0].stride != fb->pitches[0]);
11568 switch (fb->pitches[0]) {
11575 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11580 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11585 static void i845_update_cursor(struct intel_plane *plane,
11586 const struct intel_crtc_state *crtc_state,
11587 const struct intel_plane_state *plane_state)
11589 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11590 u32 cntl = 0, base = 0, pos = 0, size = 0;
11591 unsigned long irqflags;
11593 if (plane_state && plane_state->uapi.visible) {
11594 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11595 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11597 cntl = plane_state->ctl |
11598 i845_cursor_ctl_crtc(crtc_state);
11600 size = (height << 12) | width;
11602 base = intel_cursor_base(plane_state);
11603 pos = intel_cursor_position(plane_state);
11606 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11608 /* On these chipsets we can only modify the base/size/stride
11609 * whilst the cursor is disabled.
11611 if (plane->cursor.base != base ||
11612 plane->cursor.size != size ||
11613 plane->cursor.cntl != cntl) {
11614 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11615 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11616 intel_de_write_fw(dev_priv, CURSIZE, size);
11617 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11618 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11620 plane->cursor.base = base;
11621 plane->cursor.size = size;
11622 plane->cursor.cntl = cntl;
11624 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11627 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11630 static void i845_disable_cursor(struct intel_plane *plane,
11631 const struct intel_crtc_state *crtc_state)
11633 i845_update_cursor(plane, crtc_state, NULL);
11636 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11639 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11640 enum intel_display_power_domain power_domain;
11641 intel_wakeref_t wakeref;
11644 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11645 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11649 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11653 intel_display_power_put(dev_priv, power_domain, wakeref);
11658 static unsigned int
11659 i9xx_cursor_max_stride(struct intel_plane *plane,
11660 u32 pixel_format, u64 modifier,
11661 unsigned int rotation)
11663 return plane->base.dev->mode_config.cursor_width * 4;
11666 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11668 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11669 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11672 if (INTEL_GEN(dev_priv) >= 11)
11675 if (crtc_state->gamma_enable)
11676 cntl = MCURSOR_GAMMA_ENABLE;
11678 if (crtc_state->csc_enable)
11679 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11681 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11682 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11687 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11688 const struct intel_plane_state *plane_state)
11690 struct drm_i915_private *dev_priv =
11691 to_i915(plane_state->uapi.plane->dev);
11694 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11695 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11697 switch (drm_rect_width(&plane_state->uapi.dst)) {
11699 cntl |= MCURSOR_MODE_64_ARGB_AX;
11702 cntl |= MCURSOR_MODE_128_ARGB_AX;
11705 cntl |= MCURSOR_MODE_256_ARGB_AX;
11708 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11712 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11713 cntl |= MCURSOR_ROTATE_180;
11718 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11720 struct drm_i915_private *dev_priv =
11721 to_i915(plane_state->uapi.plane->dev);
11722 int width = drm_rect_width(&plane_state->uapi.dst);
11723 int height = drm_rect_height(&plane_state->uapi.dst);
11725 if (!intel_cursor_size_ok(plane_state))
11728 /* Cursor width is limited to a few power-of-two sizes */
11739 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11740 * height from 8 lines up to the cursor width, when the
11741 * cursor is not rotated. Everything else requires square
11744 if (HAS_CUR_FBC(dev_priv) &&
11745 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11746 if (height < 8 || height > width)
11749 if (height != width)
11756 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11757 struct intel_plane_state *plane_state)
11759 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11760 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11761 const struct drm_framebuffer *fb = plane_state->hw.fb;
11762 enum pipe pipe = plane->pipe;
11765 ret = intel_check_cursor(crtc_state, plane_state);
11769 /* if we want to turn off the cursor ignore width and height */
11773 /* Check for which cursor types we support */
11774 if (!i9xx_cursor_size_ok(plane_state)) {
11775 drm_dbg(&dev_priv->drm,
11776 "Cursor dimension %dx%d not supported\n",
11777 drm_rect_width(&plane_state->uapi.dst),
11778 drm_rect_height(&plane_state->uapi.dst));
11782 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11783 plane_state->color_plane[0].stride != fb->pitches[0]);
11785 if (fb->pitches[0] !=
11786 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11787 drm_dbg_kms(&dev_priv->drm,
11788 "Invalid cursor stride (%u) (cursor width %d)\n",
11790 drm_rect_width(&plane_state->uapi.dst));
11795 * There's something wrong with the cursor on CHV pipe C.
11796 * If it straddles the left edge of the screen then
11797 * moving it away from the edge or disabling it often
11798 * results in a pipe underrun, and often that can lead to
11799 * dead pipe (constant underrun reported, and it scans
11800 * out just a solid color). To recover from that, the
11801 * display power well must be turned off and on again.
11802 * Refuse the put the cursor into that compromised position.
11804 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11805 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11806 drm_dbg_kms(&dev_priv->drm,
11807 "CHV cursor C not allowed to straddle the left screen edge\n");
11811 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11816 static void i9xx_update_cursor(struct intel_plane *plane,
11817 const struct intel_crtc_state *crtc_state,
11818 const struct intel_plane_state *plane_state)
11820 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11821 enum pipe pipe = plane->pipe;
11822 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11823 unsigned long irqflags;
11825 if (plane_state && plane_state->uapi.visible) {
11826 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11827 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11829 cntl = plane_state->ctl |
11830 i9xx_cursor_ctl_crtc(crtc_state);
11832 if (width != height)
11833 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11835 base = intel_cursor_base(plane_state);
11836 pos = intel_cursor_position(plane_state);
11839 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11842 * On some platforms writing CURCNTR first will also
11843 * cause CURPOS to be armed by the CURBASE write.
11844 * Without the CURCNTR write the CURPOS write would
11845 * arm itself. Thus we always update CURCNTR before
11848 * On other platforms CURPOS always requires the
11849 * CURBASE write to arm the update. Additonally
11850 * a write to any of the cursor register will cancel
11851 * an already armed cursor update. Thus leaving out
11852 * the CURBASE write after CURPOS could lead to a
11853 * cursor that doesn't appear to move, or even change
11854 * shape. Thus we always write CURBASE.
11856 * The other registers are armed by by the CURBASE write
11857 * except when the plane is getting enabled at which time
11858 * the CURCNTR write arms the update.
11861 if (INTEL_GEN(dev_priv) >= 9)
11862 skl_write_cursor_wm(plane, crtc_state);
11864 if (!needs_modeset(crtc_state))
11865 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
11867 if (plane->cursor.base != base ||
11868 plane->cursor.size != fbc_ctl ||
11869 plane->cursor.cntl != cntl) {
11870 if (HAS_CUR_FBC(dev_priv))
11871 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11873 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11874 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11875 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11877 plane->cursor.base = base;
11878 plane->cursor.size = fbc_ctl;
11879 plane->cursor.cntl = cntl;
11881 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11882 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11885 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11888 static void i9xx_disable_cursor(struct intel_plane *plane,
11889 const struct intel_crtc_state *crtc_state)
11891 i9xx_update_cursor(plane, crtc_state, NULL);
11894 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11897 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11898 enum intel_display_power_domain power_domain;
11899 intel_wakeref_t wakeref;
11904 * Not 100% correct for planes that can move between pipes,
11905 * but that's only the case for gen2-3 which don't have any
11906 * display power wells.
11908 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11909 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11913 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11915 ret = val & MCURSOR_MODE;
11917 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11918 *pipe = plane->pipe;
11920 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11921 MCURSOR_PIPE_SELECT_SHIFT;
11923 intel_display_power_put(dev_priv, power_domain, wakeref);
11928 /* VESA 640x480x72Hz mode to set on the pipe */
11929 static const struct drm_display_mode load_detect_mode = {
11930 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11931 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11934 struct drm_framebuffer *
11935 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11936 struct drm_mode_fb_cmd2 *mode_cmd)
11938 struct intel_framebuffer *intel_fb;
11941 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11943 return ERR_PTR(-ENOMEM);
11945 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11949 return &intel_fb->base;
11953 return ERR_PTR(ret);
11956 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11957 struct drm_crtc *crtc)
11959 struct drm_plane *plane;
11960 struct drm_plane_state *plane_state;
11963 ret = drm_atomic_add_affected_planes(state, crtc);
11967 for_each_new_plane_in_state(state, plane, plane_state, i) {
11968 if (plane_state->crtc != crtc)
11971 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11975 drm_atomic_set_fb_for_plane(plane_state, NULL);
11981 int intel_get_load_detect_pipe(struct drm_connector *connector,
11982 struct intel_load_detect_pipe *old,
11983 struct drm_modeset_acquire_ctx *ctx)
11985 struct intel_crtc *intel_crtc;
11986 struct intel_encoder *intel_encoder =
11987 intel_attached_encoder(to_intel_connector(connector));
11988 struct drm_crtc *possible_crtc;
11989 struct drm_encoder *encoder = &intel_encoder->base;
11990 struct drm_crtc *crtc = NULL;
11991 struct drm_device *dev = encoder->dev;
11992 struct drm_i915_private *dev_priv = to_i915(dev);
11993 struct drm_mode_config *config = &dev->mode_config;
11994 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11995 struct drm_connector_state *connector_state;
11996 struct intel_crtc_state *crtc_state;
11999 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12000 connector->base.id, connector->name,
12001 encoder->base.id, encoder->name);
12003 old->restore_state = NULL;
12005 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
12008 * Algorithm gets a little messy:
12010 * - if the connector already has an assigned crtc, use it (but make
12011 * sure it's on first)
12013 * - try to find the first unused crtc that can drive this connector,
12014 * and use that if we find one
12017 /* See if we already have a CRTC for this connector */
12018 if (connector->state->crtc) {
12019 crtc = connector->state->crtc;
12021 ret = drm_modeset_lock(&crtc->mutex, ctx);
12025 /* Make sure the crtc and connector are running */
12029 /* Find an unused one (if possible) */
12030 for_each_crtc(dev, possible_crtc) {
12032 if (!(encoder->possible_crtcs & (1 << i)))
12035 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
12039 if (possible_crtc->state->enable) {
12040 drm_modeset_unlock(&possible_crtc->mutex);
12044 crtc = possible_crtc;
12049 * If we didn't find an unused CRTC, don't use any.
12052 drm_dbg_kms(&dev_priv->drm,
12053 "no pipe available for load-detect\n");
12059 intel_crtc = to_intel_crtc(crtc);
12061 state = drm_atomic_state_alloc(dev);
12062 restore_state = drm_atomic_state_alloc(dev);
12063 if (!state || !restore_state) {
12068 state->acquire_ctx = ctx;
12069 restore_state->acquire_ctx = ctx;
12071 connector_state = drm_atomic_get_connector_state(state, connector);
12072 if (IS_ERR(connector_state)) {
12073 ret = PTR_ERR(connector_state);
12077 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12081 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12082 if (IS_ERR(crtc_state)) {
12083 ret = PTR_ERR(crtc_state);
12087 crtc_state->uapi.active = true;
12089 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12090 &load_detect_mode);
12094 ret = intel_modeset_disable_planes(state, crtc);
12098 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12100 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12102 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12104 drm_dbg_kms(&dev_priv->drm,
12105 "Failed to create a copy of old state to restore: %i\n",
12110 ret = drm_atomic_commit(state);
12112 drm_dbg_kms(&dev_priv->drm,
12113 "failed to set mode on load-detect pipe\n");
12117 old->restore_state = restore_state;
12118 drm_atomic_state_put(state);
12120 /* let the connector get through one full cycle before testing */
12121 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12126 drm_atomic_state_put(state);
12129 if (restore_state) {
12130 drm_atomic_state_put(restore_state);
12131 restore_state = NULL;
12134 if (ret == -EDEADLK)
12140 void intel_release_load_detect_pipe(struct drm_connector *connector,
12141 struct intel_load_detect_pipe *old,
12142 struct drm_modeset_acquire_ctx *ctx)
12144 struct intel_encoder *intel_encoder =
12145 intel_attached_encoder(to_intel_connector(connector));
12146 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12147 struct drm_encoder *encoder = &intel_encoder->base;
12148 struct drm_atomic_state *state = old->restore_state;
12151 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12152 connector->base.id, connector->name,
12153 encoder->base.id, encoder->name);
12158 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12160 drm_dbg_kms(&i915->drm,
12161 "Couldn't release load detect pipe: %i\n", ret);
12162 drm_atomic_state_put(state);
12165 static int i9xx_pll_refclk(struct drm_device *dev,
12166 const struct intel_crtc_state *pipe_config)
12168 struct drm_i915_private *dev_priv = to_i915(dev);
12169 u32 dpll = pipe_config->dpll_hw_state.dpll;
12171 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12172 return dev_priv->vbt.lvds_ssc_freq;
12173 else if (HAS_PCH_SPLIT(dev_priv))
12175 else if (!IS_GEN(dev_priv, 2))
12181 /* Returns the clock of the currently programmed mode of the given pipe. */
12182 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12183 struct intel_crtc_state *pipe_config)
12185 struct drm_device *dev = crtc->base.dev;
12186 struct drm_i915_private *dev_priv = to_i915(dev);
12187 enum pipe pipe = crtc->pipe;
12188 u32 dpll = pipe_config->dpll_hw_state.dpll;
12192 int refclk = i9xx_pll_refclk(dev, pipe_config);
12194 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12195 fp = pipe_config->dpll_hw_state.fp0;
12197 fp = pipe_config->dpll_hw_state.fp1;
12199 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12200 if (IS_PINEVIEW(dev_priv)) {
12201 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12202 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12204 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12205 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12208 if (!IS_GEN(dev_priv, 2)) {
12209 if (IS_PINEVIEW(dev_priv))
12210 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12211 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12213 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12214 DPLL_FPA01_P1_POST_DIV_SHIFT);
12216 switch (dpll & DPLL_MODE_MASK) {
12217 case DPLLB_MODE_DAC_SERIAL:
12218 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12221 case DPLLB_MODE_LVDS:
12222 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12226 drm_dbg_kms(&dev_priv->drm,
12227 "Unknown DPLL mode %08x in programmed "
12228 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12232 if (IS_PINEVIEW(dev_priv))
12233 port_clock = pnv_calc_dpll_params(refclk, &clock);
12235 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12237 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12239 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12242 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12243 DPLL_FPA01_P1_POST_DIV_SHIFT);
12245 if (lvds & LVDS_CLKB_POWER_UP)
12250 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12253 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12254 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12256 if (dpll & PLL_P2_DIVIDE_BY_4)
12262 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12266 * This value includes pixel_multiplier. We will use
12267 * port_clock to compute adjusted_mode.crtc_clock in the
12268 * encoder's get_config() function.
12270 pipe_config->port_clock = port_clock;
12273 int intel_dotclock_calculate(int link_freq,
12274 const struct intel_link_m_n *m_n)
12277 * The calculation for the data clock is:
12278 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12279 * But we want to avoid losing precison if possible, so:
12280 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12282 * and the link clock is simpler:
12283 * link_clock = (m * link_clock) / n
12289 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12292 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12293 struct intel_crtc_state *pipe_config)
12295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12297 /* read out port_clock from the DPLL */
12298 i9xx_crtc_clock_get(crtc, pipe_config);
12301 * In case there is an active pipe without active ports,
12302 * we may need some idea for the dotclock anyway.
12303 * Calculate one based on the FDI configuration.
12305 pipe_config->hw.adjusted_mode.crtc_clock =
12306 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12307 &pipe_config->fdi_m_n);
12310 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12311 struct intel_crtc *crtc)
12313 memset(crtc_state, 0, sizeof(*crtc_state));
12315 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12317 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12318 crtc_state->master_transcoder = INVALID_TRANSCODER;
12319 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12320 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12321 crtc_state->scaler_state.scaler_id = -1;
12322 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12325 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12327 struct intel_crtc_state *crtc_state;
12329 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12332 intel_crtc_state_reset(crtc_state, crtc);
12337 /* Returns the currently programmed mode of the given encoder. */
12338 struct drm_display_mode *
12339 intel_encoder_current_mode(struct intel_encoder *encoder)
12341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12342 struct intel_crtc_state *crtc_state;
12343 struct drm_display_mode *mode;
12344 struct intel_crtc *crtc;
12347 if (!encoder->get_hw_state(encoder, &pipe))
12350 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12352 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12356 crtc_state = intel_crtc_state_alloc(crtc);
12362 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12368 encoder->get_config(encoder, crtc_state);
12370 intel_mode_from_pipe_config(mode, crtc_state);
12377 static void intel_crtc_destroy(struct drm_crtc *crtc)
12379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12381 drm_crtc_cleanup(crtc);
12386 * intel_wm_need_update - Check whether watermarks need updating
12387 * @cur: current plane state
12388 * @new: new plane state
12390 * Check current plane state versus the new one to determine whether
12391 * watermarks need to be recalculated.
12393 * Returns true or false.
12395 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12396 struct intel_plane_state *new)
12398 /* Update watermarks on tiling or size changes. */
12399 if (new->uapi.visible != cur->uapi.visible)
12402 if (!cur->hw.fb || !new->hw.fb)
12405 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12406 cur->hw.rotation != new->hw.rotation ||
12407 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12408 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12409 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12410 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12416 static bool needs_scaling(const struct intel_plane_state *state)
12418 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12419 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12420 int dst_w = drm_rect_width(&state->uapi.dst);
12421 int dst_h = drm_rect_height(&state->uapi.dst);
12423 return (src_w != dst_w || src_h != dst_h);
12426 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12427 struct intel_crtc_state *crtc_state,
12428 const struct intel_plane_state *old_plane_state,
12429 struct intel_plane_state *plane_state)
12431 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12432 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12434 bool mode_changed = needs_modeset(crtc_state);
12435 bool was_crtc_enabled = old_crtc_state->hw.active;
12436 bool is_crtc_enabled = crtc_state->hw.active;
12437 bool turn_off, turn_on, visible, was_visible;
12440 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12441 ret = skl_update_scaler_plane(crtc_state, plane_state);
12446 was_visible = old_plane_state->uapi.visible;
12447 visible = plane_state->uapi.visible;
12449 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12450 was_visible = false;
12453 * Visibility is calculated as if the crtc was on, but
12454 * after scaler setup everything depends on it being off
12455 * when the crtc isn't active.
12457 * FIXME this is wrong for watermarks. Watermarks should also
12458 * be computed as if the pipe would be active. Perhaps move
12459 * per-plane wm computation to the .check_plane() hook, and
12460 * only combine the results from all planes in the current place?
12462 if (!is_crtc_enabled) {
12463 intel_plane_set_invisible(crtc_state, plane_state);
12467 if (!was_visible && !visible)
12470 turn_off = was_visible && (!visible || mode_changed);
12471 turn_on = visible && (!was_visible || mode_changed);
12473 drm_dbg_atomic(&dev_priv->drm,
12474 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12475 crtc->base.base.id, crtc->base.name,
12476 plane->base.base.id, plane->base.name,
12477 was_visible, visible,
12478 turn_off, turn_on, mode_changed);
12481 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12482 crtc_state->update_wm_pre = true;
12484 /* must disable cxsr around plane enable/disable */
12485 if (plane->id != PLANE_CURSOR)
12486 crtc_state->disable_cxsr = true;
12487 } else if (turn_off) {
12488 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12489 crtc_state->update_wm_post = true;
12491 /* must disable cxsr around plane enable/disable */
12492 if (plane->id != PLANE_CURSOR)
12493 crtc_state->disable_cxsr = true;
12494 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12495 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12496 /* FIXME bollocks */
12497 crtc_state->update_wm_pre = true;
12498 crtc_state->update_wm_post = true;
12502 if (visible || was_visible)
12503 crtc_state->fb_bits |= plane->frontbuffer_bit;
12506 * ILK/SNB DVSACNTR/Sprite Enable
12507 * IVB SPR_CTL/Sprite Enable
12508 * "When in Self Refresh Big FIFO mode, a write to enable the
12509 * plane will be internally buffered and delayed while Big FIFO
12510 * mode is exiting."
12512 * Which means that enabling the sprite can take an extra frame
12513 * when we start in big FIFO mode (LP1+). Thus we need to drop
12514 * down to LP0 and wait for vblank in order to make sure the
12515 * sprite gets enabled on the next vblank after the register write.
12516 * Doing otherwise would risk enabling the sprite one frame after
12517 * we've already signalled flip completion. We can resume LP1+
12518 * once the sprite has been enabled.
12521 * WaCxSRDisabledForSpriteScaling:ivb
12522 * IVB SPR_SCALE/Scaling Enable
12523 * "Low Power watermarks must be disabled for at least one
12524 * frame before enabling sprite scaling, and kept disabled
12525 * until sprite scaling is disabled."
12527 * ILK/SNB DVSASCALE/Scaling Enable
12528 * "When in Self Refresh Big FIFO mode, scaling enable will be
12529 * masked off while Big FIFO mode is exiting."
12531 * Despite the w/a only being listed for IVB we assume that
12532 * the ILK/SNB note has similar ramifications, hence we apply
12533 * the w/a on all three platforms.
12535 * With experimental results seems this is needed also for primary
12536 * plane, not only sprite plane.
12538 if (plane->id != PLANE_CURSOR &&
12539 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12540 IS_IVYBRIDGE(dev_priv)) &&
12541 (turn_on || (!needs_scaling(old_plane_state) &&
12542 needs_scaling(plane_state))))
12543 crtc_state->disable_lp_wm = true;
12548 static bool encoders_cloneable(const struct intel_encoder *a,
12549 const struct intel_encoder *b)
12551 /* masks could be asymmetric, so check both ways */
12552 return a == b || (a->cloneable & (1 << b->type) &&
12553 b->cloneable & (1 << a->type));
12556 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12557 struct intel_crtc *crtc,
12558 struct intel_encoder *encoder)
12560 struct intel_encoder *source_encoder;
12561 struct drm_connector *connector;
12562 struct drm_connector_state *connector_state;
12565 for_each_new_connector_in_state(state, connector, connector_state, i) {
12566 if (connector_state->crtc != &crtc->base)
12570 to_intel_encoder(connector_state->best_encoder);
12571 if (!encoders_cloneable(encoder, source_encoder))
12578 static int icl_add_linked_planes(struct intel_atomic_state *state)
12580 struct intel_plane *plane, *linked;
12581 struct intel_plane_state *plane_state, *linked_plane_state;
12584 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12585 linked = plane_state->planar_linked_plane;
12590 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12591 if (IS_ERR(linked_plane_state))
12592 return PTR_ERR(linked_plane_state);
12594 drm_WARN_ON(state->base.dev,
12595 linked_plane_state->planar_linked_plane != plane);
12596 drm_WARN_ON(state->base.dev,
12597 linked_plane_state->planar_slave == plane_state->planar_slave);
12603 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12605 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12607 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12608 struct intel_plane *plane, *linked;
12609 struct intel_plane_state *plane_state;
12612 if (INTEL_GEN(dev_priv) < 11)
12616 * Destroy all old plane links and make the slave plane invisible
12617 * in the crtc_state->active_planes mask.
12619 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12620 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12623 plane_state->planar_linked_plane = NULL;
12624 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12625 crtc_state->active_planes &= ~BIT(plane->id);
12626 crtc_state->update_planes |= BIT(plane->id);
12629 plane_state->planar_slave = false;
12632 if (!crtc_state->nv12_planes)
12635 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12636 struct intel_plane_state *linked_state = NULL;
12638 if (plane->pipe != crtc->pipe ||
12639 !(crtc_state->nv12_planes & BIT(plane->id)))
12642 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12643 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12646 if (crtc_state->active_planes & BIT(linked->id))
12649 linked_state = intel_atomic_get_plane_state(state, linked);
12650 if (IS_ERR(linked_state))
12651 return PTR_ERR(linked_state);
12656 if (!linked_state) {
12657 drm_dbg_kms(&dev_priv->drm,
12658 "Need %d free Y planes for planar YUV\n",
12659 hweight8(crtc_state->nv12_planes));
12664 plane_state->planar_linked_plane = linked;
12666 linked_state->planar_slave = true;
12667 linked_state->planar_linked_plane = plane;
12668 crtc_state->active_planes |= BIT(linked->id);
12669 crtc_state->update_planes |= BIT(linked->id);
12670 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12671 linked->base.name, plane->base.name);
12673 /* Copy parameters to slave plane */
12674 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12675 linked_state->color_ctl = plane_state->color_ctl;
12676 linked_state->view = plane_state->view;
12677 memcpy(linked_state->color_plane, plane_state->color_plane,
12678 sizeof(linked_state->color_plane));
12680 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12681 linked_state->uapi.src = plane_state->uapi.src;
12682 linked_state->uapi.dst = plane_state->uapi.dst;
12684 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12685 if (linked->id == PLANE_SPRITE5)
12686 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12687 else if (linked->id == PLANE_SPRITE4)
12688 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12689 else if (linked->id == PLANE_SPRITE3)
12690 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12691 else if (linked->id == PLANE_SPRITE2)
12692 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12694 MISSING_CASE(linked->id);
12701 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12703 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12704 struct intel_atomic_state *state =
12705 to_intel_atomic_state(new_crtc_state->uapi.state);
12706 const struct intel_crtc_state *old_crtc_state =
12707 intel_atomic_get_old_crtc_state(state, crtc);
12709 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12712 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12714 const struct drm_display_mode *adjusted_mode =
12715 &crtc_state->hw.adjusted_mode;
12718 if (!crtc_state->hw.enable)
12721 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12722 adjusted_mode->crtc_clock);
12724 return min(linetime_wm, 0x1ff);
12727 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12728 const struct intel_cdclk_state *cdclk_state)
12730 const struct drm_display_mode *adjusted_mode =
12731 &crtc_state->hw.adjusted_mode;
12734 if (!crtc_state->hw.enable)
12737 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12738 cdclk_state->logical.cdclk);
12740 return min(linetime_wm, 0x1ff);
12743 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12745 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12747 const struct drm_display_mode *adjusted_mode =
12748 &crtc_state->hw.adjusted_mode;
12751 if (!crtc_state->hw.enable)
12754 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12755 crtc_state->pixel_rate);
12757 /* Display WA #1135: BXT:ALL GLK:ALL */
12758 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12761 return min(linetime_wm, 0x1ff);
12764 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12765 struct intel_crtc *crtc)
12767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12768 struct intel_crtc_state *crtc_state =
12769 intel_atomic_get_new_crtc_state(state, crtc);
12770 const struct intel_cdclk_state *cdclk_state;
12772 if (INTEL_GEN(dev_priv) >= 9)
12773 crtc_state->linetime = skl_linetime_wm(crtc_state);
12775 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12777 if (!hsw_crtc_supports_ips(crtc))
12780 cdclk_state = intel_atomic_get_cdclk_state(state);
12781 if (IS_ERR(cdclk_state))
12782 return PTR_ERR(cdclk_state);
12784 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12790 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12791 struct intel_crtc *crtc)
12793 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12794 struct intel_crtc_state *crtc_state =
12795 intel_atomic_get_new_crtc_state(state, crtc);
12796 bool mode_changed = needs_modeset(crtc_state);
12799 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12800 mode_changed && !crtc_state->hw.active)
12801 crtc_state->update_wm_post = true;
12803 if (mode_changed && crtc_state->hw.enable &&
12804 dev_priv->display.crtc_compute_clock &&
12805 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12806 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12812 * May need to update pipe gamma enable bits
12813 * when C8 planes are getting enabled/disabled.
12815 if (c8_planes_changed(crtc_state))
12816 crtc_state->uapi.color_mgmt_changed = true;
12818 if (mode_changed || crtc_state->update_pipe ||
12819 crtc_state->uapi.color_mgmt_changed) {
12820 ret = intel_color_check(crtc_state);
12825 if (dev_priv->display.compute_pipe_wm) {
12826 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12828 drm_dbg_kms(&dev_priv->drm,
12829 "Target pipe watermarks are invalid\n");
12834 if (dev_priv->display.compute_intermediate_wm) {
12835 if (drm_WARN_ON(&dev_priv->drm,
12836 !dev_priv->display.compute_pipe_wm))
12840 * Calculate 'intermediate' watermarks that satisfy both the
12841 * old state and the new state. We can program these
12844 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12846 drm_dbg_kms(&dev_priv->drm,
12847 "No valid intermediate pipe watermarks are possible\n");
12852 if (INTEL_GEN(dev_priv) >= 9) {
12853 if (mode_changed || crtc_state->update_pipe) {
12854 ret = skl_update_scaler_crtc(crtc_state);
12859 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12864 if (HAS_IPS(dev_priv)) {
12865 ret = hsw_compute_ips_config(crtc_state);
12870 if (INTEL_GEN(dev_priv) >= 9 ||
12871 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12872 ret = hsw_compute_linetime_wm(state, crtc);
12878 if (!mode_changed) {
12879 ret = intel_psr2_sel_fetch_update(state, crtc);
12887 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12889 struct intel_connector *connector;
12890 struct drm_connector_list_iter conn_iter;
12892 drm_connector_list_iter_begin(dev, &conn_iter);
12893 for_each_intel_connector_iter(connector, &conn_iter) {
12894 if (connector->base.state->crtc)
12895 drm_connector_put(&connector->base);
12897 if (connector->base.encoder) {
12898 connector->base.state->best_encoder =
12899 connector->base.encoder;
12900 connector->base.state->crtc =
12901 connector->base.encoder->crtc;
12903 drm_connector_get(&connector->base);
12905 connector->base.state->best_encoder = NULL;
12906 connector->base.state->crtc = NULL;
12909 drm_connector_list_iter_end(&conn_iter);
12913 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12914 struct intel_crtc_state *pipe_config)
12916 struct drm_connector *connector = conn_state->connector;
12917 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12918 const struct drm_display_info *info = &connector->display_info;
12921 switch (conn_state->max_bpc) {
12938 if (bpp < pipe_config->pipe_bpp) {
12939 drm_dbg_kms(&i915->drm,
12940 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12941 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12942 connector->base.id, connector->name,
12943 bpp, 3 * info->bpc,
12944 3 * conn_state->max_requested_bpc,
12945 pipe_config->pipe_bpp);
12947 pipe_config->pipe_bpp = bpp;
12954 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12955 struct intel_crtc_state *pipe_config)
12957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12958 struct drm_atomic_state *state = pipe_config->uapi.state;
12959 struct drm_connector *connector;
12960 struct drm_connector_state *connector_state;
12963 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12964 IS_CHERRYVIEW(dev_priv)))
12966 else if (INTEL_GEN(dev_priv) >= 5)
12971 pipe_config->pipe_bpp = bpp;
12973 /* Clamp display bpp to connector max bpp */
12974 for_each_new_connector_in_state(state, connector, connector_state, i) {
12977 if (connector_state->crtc != &crtc->base)
12980 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12988 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12989 const struct drm_display_mode *mode)
12991 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12992 "type: 0x%x flags: 0x%x\n",
12994 mode->crtc_hdisplay, mode->crtc_hsync_start,
12995 mode->crtc_hsync_end, mode->crtc_htotal,
12996 mode->crtc_vdisplay, mode->crtc_vsync_start,
12997 mode->crtc_vsync_end, mode->crtc_vtotal,
12998 mode->type, mode->flags);
13002 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
13003 const char *id, unsigned int lane_count,
13004 const struct intel_link_m_n *m_n)
13006 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13008 drm_dbg_kms(&i915->drm,
13009 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
13011 m_n->gmch_m, m_n->gmch_n,
13012 m_n->link_m, m_n->link_n, m_n->tu);
13016 intel_dump_infoframe(struct drm_i915_private *dev_priv,
13017 const union hdmi_infoframe *frame)
13019 if (!drm_debug_enabled(DRM_UT_KMS))
13022 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
13026 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
13027 const struct drm_dp_vsc_sdp *vsc)
13029 if (!drm_debug_enabled(DRM_UT_KMS))
13032 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
13035 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
13037 static const char * const output_type_str[] = {
13038 OUTPUT_TYPE(UNUSED),
13039 OUTPUT_TYPE(ANALOG),
13043 OUTPUT_TYPE(TVOUT),
13049 OUTPUT_TYPE(DP_MST),
13054 static void snprintf_output_types(char *buf, size_t len,
13055 unsigned int output_types)
13062 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13065 if ((output_types & BIT(i)) == 0)
13068 r = snprintf(str, len, "%s%s",
13069 str != buf ? "," : "", output_type_str[i]);
13075 output_types &= ~BIT(i);
13078 WARN_ON_ONCE(output_types != 0);
13081 static const char * const output_format_str[] = {
13082 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13083 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13084 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13085 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13088 static const char *output_formats(enum intel_output_format format)
13090 if (format >= ARRAY_SIZE(output_format_str))
13091 format = INTEL_OUTPUT_FORMAT_INVALID;
13092 return output_format_str[format];
13095 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13097 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13098 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13099 const struct drm_framebuffer *fb = plane_state->hw.fb;
13100 struct drm_format_name_buf format_name;
13103 drm_dbg_kms(&i915->drm,
13104 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13105 plane->base.base.id, plane->base.name,
13106 yesno(plane_state->uapi.visible));
13110 drm_dbg_kms(&i915->drm,
13111 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13112 plane->base.base.id, plane->base.name,
13113 fb->base.id, fb->width, fb->height,
13114 drm_get_format_name(fb->format->format, &format_name),
13115 yesno(plane_state->uapi.visible));
13116 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13117 plane_state->hw.rotation, plane_state->scaler_id);
13118 if (plane_state->uapi.visible)
13119 drm_dbg_kms(&i915->drm,
13120 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13121 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13122 DRM_RECT_ARG(&plane_state->uapi.dst));
13125 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13126 struct intel_atomic_state *state,
13127 const char *context)
13129 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13130 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13131 const struct intel_plane_state *plane_state;
13132 struct intel_plane *plane;
13136 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13137 crtc->base.base.id, crtc->base.name,
13138 yesno(pipe_config->hw.enable), context);
13140 if (!pipe_config->hw.enable)
13143 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13144 drm_dbg_kms(&dev_priv->drm,
13145 "active: %s, output_types: %s (0x%x), output format: %s\n",
13146 yesno(pipe_config->hw.active),
13147 buf, pipe_config->output_types,
13148 output_formats(pipe_config->output_format));
13150 drm_dbg_kms(&dev_priv->drm,
13151 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13152 transcoder_name(pipe_config->cpu_transcoder),
13153 pipe_config->pipe_bpp, pipe_config->dither);
13155 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13156 transcoder_name(pipe_config->mst_master_transcoder));
13158 drm_dbg_kms(&dev_priv->drm,
13159 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13160 transcoder_name(pipe_config->master_transcoder),
13161 pipe_config->sync_mode_slaves_mask);
13163 if (pipe_config->has_pch_encoder)
13164 intel_dump_m_n_config(pipe_config, "fdi",
13165 pipe_config->fdi_lanes,
13166 &pipe_config->fdi_m_n);
13168 if (intel_crtc_has_dp_encoder(pipe_config)) {
13169 intel_dump_m_n_config(pipe_config, "dp m_n",
13170 pipe_config->lane_count, &pipe_config->dp_m_n);
13171 if (pipe_config->has_drrs)
13172 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13173 pipe_config->lane_count,
13174 &pipe_config->dp_m2_n2);
13177 drm_dbg_kms(&dev_priv->drm,
13178 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13179 pipe_config->has_audio, pipe_config->has_infoframe,
13180 pipe_config->infoframes.enable);
13182 if (pipe_config->infoframes.enable &
13183 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13184 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13185 pipe_config->infoframes.gcp);
13186 if (pipe_config->infoframes.enable &
13187 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13188 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13189 if (pipe_config->infoframes.enable &
13190 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13191 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13192 if (pipe_config->infoframes.enable &
13193 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13194 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13195 if (pipe_config->infoframes.enable &
13196 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13197 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13198 if (pipe_config->infoframes.enable &
13199 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13200 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13201 if (pipe_config->infoframes.enable &
13202 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13203 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13205 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13206 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13207 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13208 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13209 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13210 drm_dbg_kms(&dev_priv->drm,
13211 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13212 pipe_config->port_clock,
13213 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13214 pipe_config->pixel_rate);
13216 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13217 pipe_config->linetime, pipe_config->ips_linetime);
13219 if (INTEL_GEN(dev_priv) >= 9)
13220 drm_dbg_kms(&dev_priv->drm,
13221 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13223 pipe_config->scaler_state.scaler_users,
13224 pipe_config->scaler_state.scaler_id);
13226 if (HAS_GMCH(dev_priv))
13227 drm_dbg_kms(&dev_priv->drm,
13228 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13229 pipe_config->gmch_pfit.control,
13230 pipe_config->gmch_pfit.pgm_ratios,
13231 pipe_config->gmch_pfit.lvds_border_bits);
13233 drm_dbg_kms(&dev_priv->drm,
13234 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13235 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13236 enableddisabled(pipe_config->pch_pfit.enabled),
13237 yesno(pipe_config->pch_pfit.force_thru));
13239 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13240 pipe_config->ips_enabled, pipe_config->double_wide);
13242 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13244 if (IS_CHERRYVIEW(dev_priv))
13245 drm_dbg_kms(&dev_priv->drm,
13246 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13247 pipe_config->cgm_mode, pipe_config->gamma_mode,
13248 pipe_config->gamma_enable, pipe_config->csc_enable);
13250 drm_dbg_kms(&dev_priv->drm,
13251 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13252 pipe_config->csc_mode, pipe_config->gamma_mode,
13253 pipe_config->gamma_enable, pipe_config->csc_enable);
13255 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
13256 pipe_config->hw.degamma_lut ?
13257 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
13258 pipe_config->hw.gamma_lut ?
13259 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
13265 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13266 if (plane->pipe == crtc->pipe)
13267 intel_dump_plane_state(plane_state);
13271 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13273 struct drm_device *dev = state->base.dev;
13274 struct drm_connector *connector;
13275 struct drm_connector_list_iter conn_iter;
13276 unsigned int used_ports = 0;
13277 unsigned int used_mst_ports = 0;
13281 * We're going to peek into connector->state,
13282 * hence connection_mutex must be held.
13284 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13287 * Walk the connector list instead of the encoder
13288 * list to detect the problem on ddi platforms
13289 * where there's just one encoder per digital port.
13291 drm_connector_list_iter_begin(dev, &conn_iter);
13292 drm_for_each_connector_iter(connector, &conn_iter) {
13293 struct drm_connector_state *connector_state;
13294 struct intel_encoder *encoder;
13297 drm_atomic_get_new_connector_state(&state->base,
13299 if (!connector_state)
13300 connector_state = connector->state;
13302 if (!connector_state->best_encoder)
13305 encoder = to_intel_encoder(connector_state->best_encoder);
13307 drm_WARN_ON(dev, !connector_state->crtc);
13309 switch (encoder->type) {
13310 case INTEL_OUTPUT_DDI:
13311 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13314 case INTEL_OUTPUT_DP:
13315 case INTEL_OUTPUT_HDMI:
13316 case INTEL_OUTPUT_EDP:
13317 /* the same port mustn't appear more than once */
13318 if (used_ports & BIT(encoder->port))
13321 used_ports |= BIT(encoder->port);
13323 case INTEL_OUTPUT_DP_MST:
13325 1 << encoder->port;
13331 drm_connector_list_iter_end(&conn_iter);
13333 /* can't mix MST and SST/HDMI on the same port */
13334 if (used_ports & used_mst_ports)
13341 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13343 intel_crtc_copy_color_blobs(crtc_state);
13347 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13349 crtc_state->hw.enable = crtc_state->uapi.enable;
13350 crtc_state->hw.active = crtc_state->uapi.active;
13351 crtc_state->hw.mode = crtc_state->uapi.mode;
13352 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13353 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13356 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13358 crtc_state->uapi.enable = crtc_state->hw.enable;
13359 crtc_state->uapi.active = crtc_state->hw.active;
13360 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13361 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13363 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13365 /* copy color blobs to uapi */
13366 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13367 crtc_state->hw.degamma_lut);
13368 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13369 crtc_state->hw.gamma_lut);
13370 drm_property_replace_blob(&crtc_state->uapi.ctm,
13371 crtc_state->hw.ctm);
13375 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13377 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13379 struct intel_crtc_state *saved_state;
13381 saved_state = intel_crtc_state_alloc(crtc);
13385 /* free the old crtc_state->hw members */
13386 intel_crtc_free_hw_state(crtc_state);
13388 /* FIXME: before the switch to atomic started, a new pipe_config was
13389 * kzalloc'd. Code that depends on any field being zero should be
13390 * fixed, so that the crtc_state can be safely duplicated. For now,
13391 * only fields that are know to not cause problems are preserved. */
13393 saved_state->uapi = crtc_state->uapi;
13394 saved_state->scaler_state = crtc_state->scaler_state;
13395 saved_state->shared_dpll = crtc_state->shared_dpll;
13396 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13397 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13398 sizeof(saved_state->icl_port_dplls));
13399 saved_state->crc_enabled = crtc_state->crc_enabled;
13400 if (IS_G4X(dev_priv) ||
13401 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13402 saved_state->wm = crtc_state->wm;
13404 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13405 kfree(saved_state);
13407 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13413 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13415 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13416 struct drm_atomic_state *state = pipe_config->uapi.state;
13417 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13418 struct drm_connector *connector;
13419 struct drm_connector_state *connector_state;
13420 int base_bpp, ret, i;
13423 pipe_config->cpu_transcoder =
13424 (enum transcoder) to_intel_crtc(crtc)->pipe;
13427 * Sanitize sync polarity flags based on requested ones. If neither
13428 * positive or negative polarity is requested, treat this as meaning
13429 * negative polarity.
13431 if (!(pipe_config->hw.adjusted_mode.flags &
13432 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13433 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13435 if (!(pipe_config->hw.adjusted_mode.flags &
13436 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13437 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13439 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13444 base_bpp = pipe_config->pipe_bpp;
13447 * Determine the real pipe dimensions. Note that stereo modes can
13448 * increase the actual pipe size due to the frame doubling and
13449 * insertion of additional space for blanks between the frame. This
13450 * is stored in the crtc timings. We use the requested mode to do this
13451 * computation to clearly distinguish it from the adjusted mode, which
13452 * can be changed by the connectors in the below retry loop.
13454 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13455 &pipe_config->pipe_src_w,
13456 &pipe_config->pipe_src_h);
13458 for_each_new_connector_in_state(state, connector, connector_state, i) {
13459 struct intel_encoder *encoder =
13460 to_intel_encoder(connector_state->best_encoder);
13462 if (connector_state->crtc != crtc)
13465 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13466 drm_dbg_kms(&i915->drm,
13467 "rejecting invalid cloning configuration\n");
13472 * Determine output_types before calling the .compute_config()
13473 * hooks so that the hooks can use this information safely.
13475 if (encoder->compute_output_type)
13476 pipe_config->output_types |=
13477 BIT(encoder->compute_output_type(encoder, pipe_config,
13480 pipe_config->output_types |= BIT(encoder->type);
13484 /* Ensure the port clock defaults are reset when retrying. */
13485 pipe_config->port_clock = 0;
13486 pipe_config->pixel_multiplier = 1;
13488 /* Fill in default crtc timings, allow encoders to overwrite them. */
13489 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13490 CRTC_STEREO_DOUBLE);
13492 /* Pass our mode to the connectors and the CRTC to give them a chance to
13493 * adjust it according to limitations or connector properties, and also
13494 * a chance to reject the mode entirely.
13496 for_each_new_connector_in_state(state, connector, connector_state, i) {
13497 struct intel_encoder *encoder =
13498 to_intel_encoder(connector_state->best_encoder);
13500 if (connector_state->crtc != crtc)
13503 ret = encoder->compute_config(encoder, pipe_config,
13506 if (ret != -EDEADLK)
13507 drm_dbg_kms(&i915->drm,
13508 "Encoder config failure: %d\n",
13514 /* Set default port clock if not overwritten by the encoder. Needs to be
13515 * done afterwards in case the encoder adjusts the mode. */
13516 if (!pipe_config->port_clock)
13517 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13518 * pipe_config->pixel_multiplier;
13520 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13521 if (ret == -EDEADLK)
13524 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13528 if (ret == RETRY) {
13529 if (drm_WARN(&i915->drm, !retry,
13530 "loop in pipe configuration computation\n"))
13533 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13535 goto encoder_retry;
13538 /* Dithering seems to not pass-through bits correctly when it should, so
13539 * only enable it on 6bpc panels and when its not a compliance
13540 * test requesting 6bpc video pattern.
13542 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13543 !pipe_config->dither_force_disable;
13544 drm_dbg_kms(&i915->drm,
13545 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13546 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13549 * Make drm_calc_timestamping_constants in
13550 * drm_atomic_helper_update_legacy_modeset_state() happy
13552 pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13558 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13560 struct intel_atomic_state *state =
13561 to_intel_atomic_state(crtc_state->uapi.state);
13562 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13563 struct drm_connector_state *conn_state;
13564 struct drm_connector *connector;
13567 for_each_new_connector_in_state(&state->base, connector,
13569 struct intel_encoder *encoder =
13570 to_intel_encoder(conn_state->best_encoder);
13573 if (conn_state->crtc != &crtc->base ||
13574 !encoder->compute_config_late)
13577 ret = encoder->compute_config_late(encoder, crtc_state,
13586 bool intel_fuzzy_clock_check(int clock1, int clock2)
13590 if (clock1 == clock2)
13593 if (!clock1 || !clock2)
13596 diff = abs(clock1 - clock2);
13598 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13605 intel_compare_m_n(unsigned int m, unsigned int n,
13606 unsigned int m2, unsigned int n2,
13609 if (m == m2 && n == n2)
13612 if (exact || !m || !n || !m2 || !n2)
13615 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13622 } else if (n < n2) {
13632 return intel_fuzzy_clock_check(m, m2);
13636 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13637 const struct intel_link_m_n *m2_n2,
13640 return m_n->tu == m2_n2->tu &&
13641 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13642 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13643 intel_compare_m_n(m_n->link_m, m_n->link_n,
13644 m2_n2->link_m, m2_n2->link_n, exact);
13648 intel_compare_infoframe(const union hdmi_infoframe *a,
13649 const union hdmi_infoframe *b)
13651 return memcmp(a, b, sizeof(*a)) == 0;
13655 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13656 const struct drm_dp_vsc_sdp *b)
13658 return memcmp(a, b, sizeof(*a)) == 0;
13662 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13663 bool fastset, const char *name,
13664 const union hdmi_infoframe *a,
13665 const union hdmi_infoframe *b)
13668 if (!drm_debug_enabled(DRM_UT_KMS))
13671 drm_dbg_kms(&dev_priv->drm,
13672 "fastset mismatch in %s infoframe\n", name);
13673 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13674 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13675 drm_dbg_kms(&dev_priv->drm, "found:\n");
13676 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13678 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13679 drm_err(&dev_priv->drm, "expected:\n");
13680 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13681 drm_err(&dev_priv->drm, "found:\n");
13682 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13687 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13688 bool fastset, const char *name,
13689 const struct drm_dp_vsc_sdp *a,
13690 const struct drm_dp_vsc_sdp *b)
13693 if (!drm_debug_enabled(DRM_UT_KMS))
13696 drm_dbg_kms(&dev_priv->drm,
13697 "fastset mismatch in %s dp sdp\n", name);
13698 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13699 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13700 drm_dbg_kms(&dev_priv->drm, "found:\n");
13701 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13703 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13704 drm_err(&dev_priv->drm, "expected:\n");
13705 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13706 drm_err(&dev_priv->drm, "found:\n");
13707 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13711 static void __printf(4, 5)
13712 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13713 const char *name, const char *format, ...)
13715 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13716 struct va_format vaf;
13719 va_start(args, format);
13724 drm_dbg_kms(&i915->drm,
13725 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13726 crtc->base.base.id, crtc->base.name, name, &vaf);
13728 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13729 crtc->base.base.id, crtc->base.name, name, &vaf);
13734 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13736 if (dev_priv->params.fastboot != -1)
13737 return dev_priv->params.fastboot;
13739 /* Enable fastboot by default on Skylake and newer */
13740 if (INTEL_GEN(dev_priv) >= 9)
13743 /* Enable fastboot by default on VLV and CHV */
13744 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13747 /* Disabled by default on all others */
13752 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13753 const struct intel_crtc_state *pipe_config,
13756 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13757 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13760 bool fixup_inherited = fastset &&
13761 current_config->inherited && !pipe_config->inherited;
13763 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13764 drm_dbg_kms(&dev_priv->drm,
13765 "initial modeset and fastboot not set\n");
13769 #define PIPE_CONF_CHECK_X(name) do { \
13770 if (current_config->name != pipe_config->name) { \
13771 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13772 "(expected 0x%08x, found 0x%08x)", \
13773 current_config->name, \
13774 pipe_config->name); \
13779 #define PIPE_CONF_CHECK_I(name) do { \
13780 if (current_config->name != pipe_config->name) { \
13781 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13782 "(expected %i, found %i)", \
13783 current_config->name, \
13784 pipe_config->name); \
13789 #define PIPE_CONF_CHECK_BOOL(name) do { \
13790 if (current_config->name != pipe_config->name) { \
13791 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13792 "(expected %s, found %s)", \
13793 yesno(current_config->name), \
13794 yesno(pipe_config->name)); \
13800 * Checks state where we only read out the enabling, but not the entire
13801 * state itself (like full infoframes or ELD for audio). These states
13802 * require a full modeset on bootup to fix up.
13804 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13805 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13806 PIPE_CONF_CHECK_BOOL(name); \
13808 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13809 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13810 yesno(current_config->name), \
13811 yesno(pipe_config->name)); \
13816 #define PIPE_CONF_CHECK_P(name) do { \
13817 if (current_config->name != pipe_config->name) { \
13818 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13819 "(expected %p, found %p)", \
13820 current_config->name, \
13821 pipe_config->name); \
13826 #define PIPE_CONF_CHECK_M_N(name) do { \
13827 if (!intel_compare_link_m_n(¤t_config->name, \
13828 &pipe_config->name,\
13830 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13831 "(expected tu %i gmch %i/%i link %i/%i, " \
13832 "found tu %i, gmch %i/%i link %i/%i)", \
13833 current_config->name.tu, \
13834 current_config->name.gmch_m, \
13835 current_config->name.gmch_n, \
13836 current_config->name.link_m, \
13837 current_config->name.link_n, \
13838 pipe_config->name.tu, \
13839 pipe_config->name.gmch_m, \
13840 pipe_config->name.gmch_n, \
13841 pipe_config->name.link_m, \
13842 pipe_config->name.link_n); \
13847 /* This is required for BDW+ where there is only one set of registers for
13848 * switching between high and low RR.
13849 * This macro can be used whenever a comparison has to be made between one
13850 * hw state and multiple sw state variables.
13852 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13853 if (!intel_compare_link_m_n(¤t_config->name, \
13854 &pipe_config->name, !fastset) && \
13855 !intel_compare_link_m_n(¤t_config->alt_name, \
13856 &pipe_config->name, !fastset)) { \
13857 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13858 "(expected tu %i gmch %i/%i link %i/%i, " \
13859 "or tu %i gmch %i/%i link %i/%i, " \
13860 "found tu %i, gmch %i/%i link %i/%i)", \
13861 current_config->name.tu, \
13862 current_config->name.gmch_m, \
13863 current_config->name.gmch_n, \
13864 current_config->name.link_m, \
13865 current_config->name.link_n, \
13866 current_config->alt_name.tu, \
13867 current_config->alt_name.gmch_m, \
13868 current_config->alt_name.gmch_n, \
13869 current_config->alt_name.link_m, \
13870 current_config->alt_name.link_n, \
13871 pipe_config->name.tu, \
13872 pipe_config->name.gmch_m, \
13873 pipe_config->name.gmch_n, \
13874 pipe_config->name.link_m, \
13875 pipe_config->name.link_n); \
13880 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13881 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13882 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13883 "(%x) (expected %i, found %i)", \
13885 current_config->name & (mask), \
13886 pipe_config->name & (mask)); \
13891 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13892 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13893 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13894 "(expected %i, found %i)", \
13895 current_config->name, \
13896 pipe_config->name); \
13901 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13902 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
13903 &pipe_config->infoframes.name)) { \
13904 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13905 ¤t_config->infoframes.name, \
13906 &pipe_config->infoframes.name); \
13911 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13912 if (!current_config->has_psr && !pipe_config->has_psr && \
13913 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
13914 &pipe_config->infoframes.name)) { \
13915 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13916 ¤t_config->infoframes.name, \
13917 &pipe_config->infoframes.name); \
13922 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13923 if (current_config->name1 != pipe_config->name1) { \
13924 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13925 "(expected %i, found %i, won't compare lut values)", \
13926 current_config->name1, \
13927 pipe_config->name1); \
13930 if (!intel_color_lut_equal(current_config->name2, \
13931 pipe_config->name2, pipe_config->name1, \
13932 bit_precision)) { \
13933 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13934 "hw_state doesn't match sw_state"); \
13940 #define PIPE_CONF_QUIRK(quirk) \
13941 ((current_config->quirks | pipe_config->quirks) & (quirk))
13943 PIPE_CONF_CHECK_I(cpu_transcoder);
13945 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13946 PIPE_CONF_CHECK_I(fdi_lanes);
13947 PIPE_CONF_CHECK_M_N(fdi_m_n);
13949 PIPE_CONF_CHECK_I(lane_count);
13950 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13952 if (INTEL_GEN(dev_priv) < 8) {
13953 PIPE_CONF_CHECK_M_N(dp_m_n);
13955 if (current_config->has_drrs)
13956 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13958 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13960 PIPE_CONF_CHECK_X(output_types);
13962 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13963 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13964 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13965 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13966 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13967 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13969 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13970 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13971 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13972 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13973 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13974 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13976 PIPE_CONF_CHECK_I(pixel_multiplier);
13977 PIPE_CONF_CHECK_I(output_format);
13978 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13979 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13980 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13981 PIPE_CONF_CHECK_BOOL(limited_color_range);
13983 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13984 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13985 PIPE_CONF_CHECK_BOOL(has_infoframe);
13986 PIPE_CONF_CHECK_BOOL(fec_enable);
13988 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13990 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13991 DRM_MODE_FLAG_INTERLACE);
13993 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13994 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13995 DRM_MODE_FLAG_PHSYNC);
13996 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13997 DRM_MODE_FLAG_NHSYNC);
13998 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13999 DRM_MODE_FLAG_PVSYNC);
14000 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14001 DRM_MODE_FLAG_NVSYNC);
14004 PIPE_CONF_CHECK_X(gmch_pfit.control);
14005 /* pfit ratios are autocomputed by the hw on gen4+ */
14006 if (INTEL_GEN(dev_priv) < 4)
14007 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
14008 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
14011 * Changing the EDP transcoder input mux
14012 * (A_ONOFF vs. A_ON) requires a full modeset.
14014 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
14017 PIPE_CONF_CHECK_I(pipe_src_w);
14018 PIPE_CONF_CHECK_I(pipe_src_h);
14020 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
14021 if (current_config->pch_pfit.enabled) {
14022 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
14023 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
14024 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
14025 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
14028 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
14029 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
14031 PIPE_CONF_CHECK_X(gamma_mode);
14032 if (IS_CHERRYVIEW(dev_priv))
14033 PIPE_CONF_CHECK_X(cgm_mode);
14035 PIPE_CONF_CHECK_X(csc_mode);
14036 PIPE_CONF_CHECK_BOOL(gamma_enable);
14037 PIPE_CONF_CHECK_BOOL(csc_enable);
14039 PIPE_CONF_CHECK_I(linetime);
14040 PIPE_CONF_CHECK_I(ips_linetime);
14042 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
14044 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
14047 PIPE_CONF_CHECK_BOOL(double_wide);
14049 PIPE_CONF_CHECK_P(shared_dpll);
14050 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
14051 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
14052 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
14053 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
14054 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
14055 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
14056 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
14057 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
14058 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
14059 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
14060 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
14061 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14062 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14063 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14064 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14065 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14066 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14067 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14068 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14069 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14070 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14071 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14072 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14073 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14074 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14075 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14076 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14077 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14078 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14079 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14080 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14082 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14083 PIPE_CONF_CHECK_X(dsi_pll.div);
14085 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14086 PIPE_CONF_CHECK_I(pipe_bpp);
14088 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14089 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14091 PIPE_CONF_CHECK_I(min_voltage_level);
14093 PIPE_CONF_CHECK_X(infoframes.enable);
14094 PIPE_CONF_CHECK_X(infoframes.gcp);
14095 PIPE_CONF_CHECK_INFOFRAME(avi);
14096 PIPE_CONF_CHECK_INFOFRAME(spd);
14097 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14098 PIPE_CONF_CHECK_INFOFRAME(drm);
14099 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14101 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14102 PIPE_CONF_CHECK_I(master_transcoder);
14104 PIPE_CONF_CHECK_I(dsc.compression_enable);
14105 PIPE_CONF_CHECK_I(dsc.dsc_split);
14106 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14108 PIPE_CONF_CHECK_I(mst_master_transcoder);
14110 #undef PIPE_CONF_CHECK_X
14111 #undef PIPE_CONF_CHECK_I
14112 #undef PIPE_CONF_CHECK_BOOL
14113 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14114 #undef PIPE_CONF_CHECK_P
14115 #undef PIPE_CONF_CHECK_FLAGS
14116 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14117 #undef PIPE_CONF_CHECK_COLOR_LUT
14118 #undef PIPE_CONF_QUIRK
14123 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14124 const struct intel_crtc_state *pipe_config)
14126 if (pipe_config->has_pch_encoder) {
14127 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14128 &pipe_config->fdi_m_n);
14129 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14132 * FDI already provided one idea for the dotclock.
14133 * Yell if the encoder disagrees.
14135 drm_WARN(&dev_priv->drm,
14136 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14137 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14138 fdi_dotclock, dotclock);
14142 static void verify_wm_state(struct intel_crtc *crtc,
14143 struct intel_crtc_state *new_crtc_state)
14145 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14146 struct skl_hw_state {
14147 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14148 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14149 struct skl_pipe_wm wm;
14151 struct skl_pipe_wm *sw_wm;
14152 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14153 u8 hw_enabled_slices;
14154 const enum pipe pipe = crtc->pipe;
14155 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14157 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14160 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14164 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14165 sw_wm = &new_crtc_state->wm.skl.optimal;
14167 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14169 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14171 if (INTEL_GEN(dev_priv) >= 11 &&
14172 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14173 drm_err(&dev_priv->drm,
14174 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14175 dev_priv->dbuf.enabled_slices,
14176 hw_enabled_slices);
14179 for_each_universal_plane(dev_priv, pipe, plane) {
14180 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14182 hw_plane_wm = &hw->wm.planes[plane];
14183 sw_plane_wm = &sw_wm->planes[plane];
14186 for (level = 0; level <= max_level; level++) {
14187 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14188 &sw_plane_wm->wm[level]) ||
14189 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14190 &sw_plane_wm->sagv_wm0)))
14193 drm_err(&dev_priv->drm,
14194 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14195 pipe_name(pipe), plane + 1, level,
14196 sw_plane_wm->wm[level].plane_en,
14197 sw_plane_wm->wm[level].plane_res_b,
14198 sw_plane_wm->wm[level].plane_res_l,
14199 hw_plane_wm->wm[level].plane_en,
14200 hw_plane_wm->wm[level].plane_res_b,
14201 hw_plane_wm->wm[level].plane_res_l);
14204 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14205 &sw_plane_wm->trans_wm)) {
14206 drm_err(&dev_priv->drm,
14207 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14208 pipe_name(pipe), plane + 1,
14209 sw_plane_wm->trans_wm.plane_en,
14210 sw_plane_wm->trans_wm.plane_res_b,
14211 sw_plane_wm->trans_wm.plane_res_l,
14212 hw_plane_wm->trans_wm.plane_en,
14213 hw_plane_wm->trans_wm.plane_res_b,
14214 hw_plane_wm->trans_wm.plane_res_l);
14218 hw_ddb_entry = &hw->ddb_y[plane];
14219 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14221 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14222 drm_err(&dev_priv->drm,
14223 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14224 pipe_name(pipe), plane + 1,
14225 sw_ddb_entry->start, sw_ddb_entry->end,
14226 hw_ddb_entry->start, hw_ddb_entry->end);
14232 * If the cursor plane isn't active, we may not have updated it's ddb
14233 * allocation. In that case since the ddb allocation will be updated
14234 * once the plane becomes visible, we can skip this check
14237 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14239 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14240 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14243 for (level = 0; level <= max_level; level++) {
14244 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14245 &sw_plane_wm->wm[level]) ||
14246 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14247 &sw_plane_wm->sagv_wm0)))
14250 drm_err(&dev_priv->drm,
14251 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14252 pipe_name(pipe), level,
14253 sw_plane_wm->wm[level].plane_en,
14254 sw_plane_wm->wm[level].plane_res_b,
14255 sw_plane_wm->wm[level].plane_res_l,
14256 hw_plane_wm->wm[level].plane_en,
14257 hw_plane_wm->wm[level].plane_res_b,
14258 hw_plane_wm->wm[level].plane_res_l);
14261 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14262 &sw_plane_wm->trans_wm)) {
14263 drm_err(&dev_priv->drm,
14264 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14266 sw_plane_wm->trans_wm.plane_en,
14267 sw_plane_wm->trans_wm.plane_res_b,
14268 sw_plane_wm->trans_wm.plane_res_l,
14269 hw_plane_wm->trans_wm.plane_en,
14270 hw_plane_wm->trans_wm.plane_res_b,
14271 hw_plane_wm->trans_wm.plane_res_l);
14275 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14276 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14278 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14279 drm_err(&dev_priv->drm,
14280 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14282 sw_ddb_entry->start, sw_ddb_entry->end,
14283 hw_ddb_entry->start, hw_ddb_entry->end);
14291 verify_connector_state(struct intel_atomic_state *state,
14292 struct intel_crtc *crtc)
14294 struct drm_connector *connector;
14295 struct drm_connector_state *new_conn_state;
14298 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14299 struct drm_encoder *encoder = connector->encoder;
14300 struct intel_crtc_state *crtc_state = NULL;
14302 if (new_conn_state->crtc != &crtc->base)
14306 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14308 intel_connector_verify_state(crtc_state, new_conn_state);
14310 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14311 "connector's atomic encoder doesn't match legacy encoder\n");
14316 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14318 struct intel_encoder *encoder;
14319 struct drm_connector *connector;
14320 struct drm_connector_state *old_conn_state, *new_conn_state;
14323 for_each_intel_encoder(&dev_priv->drm, encoder) {
14324 bool enabled = false, found = false;
14327 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14328 encoder->base.base.id,
14329 encoder->base.name);
14331 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14332 new_conn_state, i) {
14333 if (old_conn_state->best_encoder == &encoder->base)
14336 if (new_conn_state->best_encoder != &encoder->base)
14338 found = enabled = true;
14340 I915_STATE_WARN(new_conn_state->crtc !=
14341 encoder->base.crtc,
14342 "connector's crtc doesn't match encoder crtc\n");
14348 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14349 "encoder's enabled state mismatch "
14350 "(expected %i, found %i)\n",
14351 !!encoder->base.crtc, enabled);
14353 if (!encoder->base.crtc) {
14356 active = encoder->get_hw_state(encoder, &pipe);
14357 I915_STATE_WARN(active,
14358 "encoder detached but still enabled on pipe %c.\n",
14365 verify_crtc_state(struct intel_crtc *crtc,
14366 struct intel_crtc_state *old_crtc_state,
14367 struct intel_crtc_state *new_crtc_state)
14369 struct drm_device *dev = crtc->base.dev;
14370 struct drm_i915_private *dev_priv = to_i915(dev);
14371 struct intel_encoder *encoder;
14372 struct intel_crtc_state *pipe_config = old_crtc_state;
14373 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14375 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14376 intel_crtc_free_hw_state(old_crtc_state);
14377 intel_crtc_state_reset(old_crtc_state, crtc);
14378 old_crtc_state->uapi.state = state;
14380 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14383 pipe_config->hw.enable = new_crtc_state->hw.enable;
14385 pipe_config->hw.active =
14386 dev_priv->display.get_pipe_config(crtc, pipe_config);
14388 /* we keep both pipes enabled on 830 */
14389 if (IS_I830(dev_priv) && pipe_config->hw.active)
14390 pipe_config->hw.active = new_crtc_state->hw.active;
14392 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14393 "crtc active state doesn't match with hw state "
14394 "(expected %i, found %i)\n",
14395 new_crtc_state->hw.active, pipe_config->hw.active);
14397 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14398 "transitional active state does not match atomic hw state "
14399 "(expected %i, found %i)\n",
14400 new_crtc_state->hw.active, crtc->active);
14402 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14406 active = encoder->get_hw_state(encoder, &pipe);
14407 I915_STATE_WARN(active != new_crtc_state->hw.active,
14408 "[ENCODER:%i] active %i with crtc active %i\n",
14409 encoder->base.base.id, active,
14410 new_crtc_state->hw.active);
14412 I915_STATE_WARN(active && crtc->pipe != pipe,
14413 "Encoder connected to wrong pipe %c\n",
14417 encoder->get_config(encoder, pipe_config);
14420 intel_crtc_compute_pixel_rate(pipe_config);
14422 if (!new_crtc_state->hw.active)
14425 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14427 if (!intel_pipe_config_compare(new_crtc_state,
14428 pipe_config, false)) {
14429 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14430 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14431 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14436 intel_verify_planes(struct intel_atomic_state *state)
14438 struct intel_plane *plane;
14439 const struct intel_plane_state *plane_state;
14442 for_each_new_intel_plane_in_state(state, plane,
14444 assert_plane(plane, plane_state->planar_slave ||
14445 plane_state->uapi.visible);
14449 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14450 struct intel_shared_dpll *pll,
14451 struct intel_crtc *crtc,
14452 struct intel_crtc_state *new_crtc_state)
14454 struct intel_dpll_hw_state dpll_hw_state;
14455 unsigned int crtc_mask;
14458 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14460 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14462 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14464 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14465 I915_STATE_WARN(!pll->on && pll->active_mask,
14466 "pll in active use but not on in sw tracking\n");
14467 I915_STATE_WARN(pll->on && !pll->active_mask,
14468 "pll is on but not used by any active crtc\n");
14469 I915_STATE_WARN(pll->on != active,
14470 "pll on state mismatch (expected %i, found %i)\n",
14475 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14476 "more active pll users than references: %x vs %x\n",
14477 pll->active_mask, pll->state.crtc_mask);
14482 crtc_mask = drm_crtc_mask(&crtc->base);
14484 if (new_crtc_state->hw.active)
14485 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14486 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14487 pipe_name(crtc->pipe), pll->active_mask);
14489 I915_STATE_WARN(pll->active_mask & crtc_mask,
14490 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14491 pipe_name(crtc->pipe), pll->active_mask);
14493 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14494 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14495 crtc_mask, pll->state.crtc_mask);
14497 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14499 sizeof(dpll_hw_state)),
14500 "pll hw state mismatch\n");
14504 verify_shared_dpll_state(struct intel_crtc *crtc,
14505 struct intel_crtc_state *old_crtc_state,
14506 struct intel_crtc_state *new_crtc_state)
14508 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14510 if (new_crtc_state->shared_dpll)
14511 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14513 if (old_crtc_state->shared_dpll &&
14514 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14515 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14516 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14518 I915_STATE_WARN(pll->active_mask & crtc_mask,
14519 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14520 pipe_name(crtc->pipe));
14521 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14522 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14523 pipe_name(crtc->pipe));
14528 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14529 struct intel_atomic_state *state,
14530 struct intel_crtc_state *old_crtc_state,
14531 struct intel_crtc_state *new_crtc_state)
14533 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14536 verify_wm_state(crtc, new_crtc_state);
14537 verify_connector_state(state, crtc);
14538 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14539 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14543 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14547 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14548 verify_single_dpll_state(dev_priv,
14549 &dev_priv->dpll.shared_dplls[i],
14554 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14555 struct intel_atomic_state *state)
14557 verify_encoder_state(dev_priv, state);
14558 verify_connector_state(state, NULL);
14559 verify_disabled_dpll_state(dev_priv);
14563 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14567 const struct drm_display_mode *adjusted_mode =
14568 &crtc_state->hw.adjusted_mode;
14570 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14572 crtc->mode_flags = crtc_state->mode_flags;
14575 * The scanline counter increments at the leading edge of hsync.
14577 * On most platforms it starts counting from vtotal-1 on the
14578 * first active line. That means the scanline counter value is
14579 * always one less than what we would expect. Ie. just after
14580 * start of vblank, which also occurs at start of hsync (on the
14581 * last active line), the scanline counter will read vblank_start-1.
14583 * On gen2 the scanline counter starts counting from 1 instead
14584 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14585 * to keep the value positive), instead of adding one.
14587 * On HSW+ the behaviour of the scanline counter depends on the output
14588 * type. For DP ports it behaves like most other platforms, but on HDMI
14589 * there's an extra 1 line difference. So we need to add two instead of
14590 * one to the value.
14592 * On VLV/CHV DSI the scanline counter would appear to increment
14593 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14594 * that means we can't tell whether we're in vblank or not while
14595 * we're on that particular line. We must still set scanline_offset
14596 * to 1 so that the vblank timestamps come out correct when we query
14597 * the scanline counter from within the vblank interrupt handler.
14598 * However if queried just before the start of vblank we'll get an
14599 * answer that's slightly in the future.
14601 if (IS_GEN(dev_priv, 2)) {
14604 vtotal = adjusted_mode->crtc_vtotal;
14605 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14608 crtc->scanline_offset = vtotal - 1;
14609 } else if (HAS_DDI(dev_priv) &&
14610 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14611 crtc->scanline_offset = 2;
14613 crtc->scanline_offset = 1;
14617 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14619 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14620 struct intel_crtc_state *new_crtc_state;
14621 struct intel_crtc *crtc;
14624 if (!dev_priv->display.crtc_compute_clock)
14627 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14628 if (!needs_modeset(new_crtc_state))
14631 intel_release_shared_dplls(state, crtc);
14636 * This implements the workaround described in the "notes" section of the mode
14637 * set sequence documentation. When going from no pipes or single pipe to
14638 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14639 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14641 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14643 struct intel_crtc_state *crtc_state;
14644 struct intel_crtc *crtc;
14645 struct intel_crtc_state *first_crtc_state = NULL;
14646 struct intel_crtc_state *other_crtc_state = NULL;
14647 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14650 /* look at all crtc's that are going to be enabled in during modeset */
14651 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14652 if (!crtc_state->hw.active ||
14653 !needs_modeset(crtc_state))
14656 if (first_crtc_state) {
14657 other_crtc_state = crtc_state;
14660 first_crtc_state = crtc_state;
14661 first_pipe = crtc->pipe;
14665 /* No workaround needed? */
14666 if (!first_crtc_state)
14669 /* w/a possibly needed, check how many crtc's are already enabled. */
14670 for_each_intel_crtc(state->base.dev, crtc) {
14671 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14672 if (IS_ERR(crtc_state))
14673 return PTR_ERR(crtc_state);
14675 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14677 if (!crtc_state->hw.active ||
14678 needs_modeset(crtc_state))
14681 /* 2 or more enabled crtcs means no need for w/a */
14682 if (enabled_pipe != INVALID_PIPE)
14685 enabled_pipe = crtc->pipe;
14688 if (enabled_pipe != INVALID_PIPE)
14689 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14690 else if (other_crtc_state)
14691 other_crtc_state->hsw_workaround_pipe = first_pipe;
14696 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14699 const struct intel_crtc_state *crtc_state;
14700 struct intel_crtc *crtc;
14703 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14704 if (crtc_state->hw.active)
14705 active_pipes |= BIT(crtc->pipe);
14707 active_pipes &= ~BIT(crtc->pipe);
14710 return active_pipes;
14713 static int intel_modeset_checks(struct intel_atomic_state *state)
14715 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14717 state->modeset = true;
14719 if (IS_HASWELL(dev_priv))
14720 return hsw_mode_set_planes_workaround(state);
14726 * Handle calculation of various watermark data at the end of the atomic check
14727 * phase. The code here should be run after the per-crtc and per-plane 'check'
14728 * handlers to ensure that all derived state has been updated.
14730 static int calc_watermark_data(struct intel_atomic_state *state)
14732 struct drm_device *dev = state->base.dev;
14733 struct drm_i915_private *dev_priv = to_i915(dev);
14735 /* Is there platform-specific watermark information to calculate? */
14736 if (dev_priv->display.compute_global_watermarks)
14737 return dev_priv->display.compute_global_watermarks(state);
14742 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14743 struct intel_crtc_state *new_crtc_state)
14745 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14748 new_crtc_state->uapi.mode_changed = false;
14749 new_crtc_state->update_pipe = true;
14752 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14753 struct intel_crtc_state *new_crtc_state)
14756 * If we're not doing the full modeset we want to
14757 * keep the current M/N values as they may be
14758 * sufficiently different to the computed values
14759 * to cause problems.
14761 * FIXME: should really copy more fuzzy state here
14763 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14764 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14765 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14766 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14769 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14770 struct intel_crtc *crtc,
14773 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14774 struct intel_plane *plane;
14776 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14777 struct intel_plane_state *plane_state;
14779 if ((plane_ids_mask & BIT(plane->id)) == 0)
14782 plane_state = intel_atomic_get_plane_state(state, plane);
14783 if (IS_ERR(plane_state))
14784 return PTR_ERR(plane_state);
14790 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14792 /* See {hsw,vlv,ivb}_plane_ratio() */
14793 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14794 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14795 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14798 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14800 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14801 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14802 struct intel_plane_state *plane_state;
14803 struct intel_plane *plane;
14804 struct intel_crtc *crtc;
14807 ret = icl_add_linked_planes(state);
14811 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14812 ret = intel_plane_atomic_check(state, plane);
14814 drm_dbg_atomic(&dev_priv->drm,
14815 "[PLANE:%d:%s] atomic driver check failed\n",
14816 plane->base.base.id, plane->base.name);
14821 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14822 new_crtc_state, i) {
14823 u8 old_active_planes, new_active_planes;
14825 ret = icl_check_nv12_planes(new_crtc_state);
14830 * On some platforms the number of active planes affects
14831 * the planes' minimum cdclk calculation. Add such planes
14832 * to the state before we compute the minimum cdclk.
14834 if (!active_planes_affects_min_cdclk(dev_priv))
14837 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14838 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14841 * Not only the number of planes, but if the plane configuration had
14842 * changed might already mean we need to recompute min CDCLK,
14843 * because different planes might consume different amount of Dbuf bandwidth
14844 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14846 if (old_active_planes == new_active_planes)
14849 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14857 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14858 bool *need_cdclk_calc)
14860 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14861 const struct intel_cdclk_state *old_cdclk_state;
14862 const struct intel_cdclk_state *new_cdclk_state;
14863 struct intel_plane_state *plane_state;
14864 struct intel_bw_state *new_bw_state;
14865 struct intel_plane *plane;
14871 * active_planes bitmask has been updated, and potentially
14872 * affected planes are part of the state. We can now
14873 * compute the minimum cdclk for each plane.
14875 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14876 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14881 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14882 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14884 if (new_cdclk_state &&
14885 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14886 *need_cdclk_calc = true;
14888 ret = dev_priv->display.bw_calc_min_cdclk(state);
14892 new_bw_state = intel_atomic_get_new_bw_state(state);
14894 if (!new_cdclk_state || !new_bw_state)
14897 for_each_pipe(dev_priv, pipe) {
14898 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14901 * Currently do this change only if we need to increase
14903 if (new_bw_state->min_cdclk > min_cdclk)
14904 *need_cdclk_calc = true;
14910 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14912 struct intel_crtc_state *crtc_state;
14913 struct intel_crtc *crtc;
14916 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14917 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14920 ret = intel_crtc_atomic_check(state, crtc);
14922 drm_dbg_atomic(&i915->drm,
14923 "[CRTC:%d:%s] atomic driver check failed\n",
14924 crtc->base.base.id, crtc->base.name);
14932 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14935 const struct intel_crtc_state *new_crtc_state;
14936 struct intel_crtc *crtc;
14939 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14940 if (new_crtc_state->hw.enable &&
14941 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14942 needs_modeset(new_crtc_state))
14950 * DOC: asynchronous flip implementation
14952 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
14953 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
14954 * Correspondingly, support is currently added for primary plane only.
14956 * Async flip can only change the plane surface address, so anything else
14957 * changing is rejected from the intel_atomic_check_async() function.
14958 * Once this check is cleared, flip done interrupt is enabled using
14959 * the skl_enable_flip_done() function.
14961 * As soon as the surface address register is written, flip done interrupt is
14962 * generated and the requested events are sent to the usersapce in the interrupt
14963 * handler itself. The timestamp and sequence sent during the flip done event
14964 * correspond to the last vblank and have no relation to the actual time when
14965 * the flip done event was sent.
14967 static int intel_atomic_check_async(struct intel_atomic_state *state)
14969 struct drm_i915_private *i915 = to_i915(state->base.dev);
14970 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14971 const struct intel_plane_state *new_plane_state, *old_plane_state;
14972 struct intel_crtc *crtc;
14973 struct intel_plane *plane;
14976 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14977 new_crtc_state, i) {
14978 if (needs_modeset(new_crtc_state)) {
14979 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
14983 if (!new_crtc_state->hw.active) {
14984 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
14987 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
14988 drm_dbg_kms(&i915->drm,
14989 "Active planes cannot be changed during async flip\n");
14994 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14995 new_plane_state, i) {
14997 * TODO: Async flip is only supported through the page flip IOCTL
14998 * as of now. So support currently added for primary plane only.
14999 * Support for other planes on platforms on which supports
15000 * this(vlv/chv and icl+) should be added when async flip is
15001 * enabled in the atomic IOCTL path.
15003 if (plane->id != PLANE_PRIMARY)
15007 * FIXME: This check is kept generic for all platforms.
15008 * Need to verify this for all gen9 and gen10 platforms to enable
15009 * this selectively if required.
15011 switch (new_plane_state->hw.fb->modifier) {
15012 case I915_FORMAT_MOD_X_TILED:
15013 case I915_FORMAT_MOD_Y_TILED:
15014 case I915_FORMAT_MOD_Yf_TILED:
15017 drm_dbg_kms(&i915->drm,
15018 "Linear memory/CCS does not support async flips\n");
15022 if (old_plane_state->color_plane[0].stride !=
15023 new_plane_state->color_plane[0].stride) {
15024 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
15028 if (old_plane_state->hw.fb->modifier !=
15029 new_plane_state->hw.fb->modifier) {
15030 drm_dbg_kms(&i915->drm,
15031 "Framebuffer modifiers cannot be changed in async flip\n");
15035 if (old_plane_state->hw.fb->format !=
15036 new_plane_state->hw.fb->format) {
15037 drm_dbg_kms(&i915->drm,
15038 "Framebuffer format cannot be changed in async flip\n");
15042 if (old_plane_state->hw.rotation !=
15043 new_plane_state->hw.rotation) {
15044 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
15048 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
15049 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
15050 drm_dbg_kms(&i915->drm,
15051 "Plane size/co-ordinates cannot be changed in async flip\n");
15055 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
15056 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
15060 if (old_plane_state->hw.pixel_blend_mode !=
15061 new_plane_state->hw.pixel_blend_mode) {
15062 drm_dbg_kms(&i915->drm,
15063 "Pixel blend mode cannot be changed in async flip\n");
15067 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
15068 drm_dbg_kms(&i915->drm,
15069 "Color encoding cannot be changed in async flip\n");
15073 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
15074 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
15083 * intel_atomic_check - validate state object
15085 * @_state: state to validate
15087 static int intel_atomic_check(struct drm_device *dev,
15088 struct drm_atomic_state *_state)
15090 struct drm_i915_private *dev_priv = to_i915(dev);
15091 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15092 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15093 struct intel_crtc *crtc;
15095 bool any_ms = false;
15097 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15098 new_crtc_state, i) {
15099 if (new_crtc_state->inherited != old_crtc_state->inherited)
15100 new_crtc_state->uapi.mode_changed = true;
15103 ret = drm_atomic_helper_check_modeset(dev, &state->base);
15107 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15108 new_crtc_state, i) {
15109 if (!needs_modeset(new_crtc_state)) {
15111 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
15116 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
15120 if (!new_crtc_state->hw.enable)
15123 ret = intel_modeset_pipe_config(new_crtc_state);
15128 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15129 new_crtc_state, i) {
15130 if (!needs_modeset(new_crtc_state))
15133 ret = intel_modeset_pipe_config_late(new_crtc_state);
15137 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
15141 * Check if fastset is allowed by external dependencies like other
15142 * pipes and transcoders.
15144 * Right now it only forces a fullmodeset when the MST master
15145 * transcoder did not changed but the pipe of the master transcoder
15146 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
15147 * in case of port synced crtcs, if one of the synced crtcs
15148 * needs a full modeset, all other synced crtcs should be
15149 * forced a full modeset.
15151 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15152 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
15155 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
15156 enum transcoder master = new_crtc_state->mst_master_transcoder;
15158 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
15159 new_crtc_state->uapi.mode_changed = true;
15160 new_crtc_state->update_pipe = false;
15164 if (is_trans_port_sync_mode(new_crtc_state)) {
15165 u8 trans = new_crtc_state->sync_mode_slaves_mask;
15167 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
15168 trans |= BIT(new_crtc_state->master_transcoder);
15170 if (intel_cpu_transcoders_need_modeset(state, trans)) {
15171 new_crtc_state->uapi.mode_changed = true;
15172 new_crtc_state->update_pipe = false;
15177 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15178 new_crtc_state, i) {
15179 if (needs_modeset(new_crtc_state)) {
15184 if (!new_crtc_state->update_pipe)
15187 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
15190 if (any_ms && !check_digital_port_conflicts(state)) {
15191 drm_dbg_kms(&dev_priv->drm,
15192 "rejecting conflicting digital port configuration\n");
15197 ret = drm_dp_mst_atomic_check(&state->base);
15201 ret = intel_atomic_check_planes(state);
15206 * distrust_bios_wm will force a full dbuf recomputation
15207 * but the hardware state will only get updated accordingly
15208 * if state->modeset==true. Hence distrust_bios_wm==true &&
15209 * state->modeset==false is an invalid combination which
15210 * would cause the hardware and software dbuf state to get
15211 * out of sync. We must prevent that.
15213 * FIXME clean up this mess and introduce better
15214 * state tracking for dbuf.
15216 if (dev_priv->wm.distrust_bios_wm)
15219 intel_fbc_choose_crtc(dev_priv, state);
15220 ret = calc_watermark_data(state);
15224 ret = intel_bw_atomic_check(state);
15228 ret = intel_atomic_check_cdclk(state, &any_ms);
15233 ret = intel_modeset_checks(state);
15237 ret = intel_modeset_calc_cdclk(state);
15241 intel_modeset_clear_plls(state);
15244 ret = intel_atomic_check_crtcs(state);
15248 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15249 new_crtc_state, i) {
15250 if (new_crtc_state->uapi.async_flip) {
15251 ret = intel_atomic_check_async(state);
15256 if (!needs_modeset(new_crtc_state) &&
15257 !new_crtc_state->update_pipe)
15260 intel_dump_pipe_config(new_crtc_state, state,
15261 needs_modeset(new_crtc_state) ?
15262 "[modeset]" : "[fastset]");
15268 if (ret == -EDEADLK)
15272 * FIXME would probably be nice to know which crtc specifically
15273 * caused the failure, in cases where we can pinpoint it.
15275 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15277 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15282 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15284 struct intel_crtc_state *crtc_state;
15285 struct intel_crtc *crtc;
15288 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15292 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15293 bool mode_changed = needs_modeset(crtc_state);
15295 if (mode_changed || crtc_state->update_pipe ||
15296 crtc_state->uapi.color_mgmt_changed) {
15297 intel_dsb_prepare(crtc_state);
15304 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15306 struct drm_device *dev = crtc->base.dev;
15307 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15309 if (!vblank->max_vblank_count)
15310 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15312 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15315 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15316 struct intel_crtc_state *crtc_state)
15318 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15320 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15321 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15323 if (crtc_state->has_pch_encoder) {
15324 enum pipe pch_transcoder =
15325 intel_crtc_pch_transcoder(crtc);
15327 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15331 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15332 const struct intel_crtc_state *new_crtc_state)
15334 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15338 * Update pipe size and adjust fitter if needed: the reason for this is
15339 * that in compute_mode_changes we check the native mode (not the pfit
15340 * mode) to see if we can flip rather than do a full mode set. In the
15341 * fastboot case, we'll flip, but if we don't update the pipesrc and
15342 * pfit state, we'll end up with a big fb scanned out into the wrong
15345 intel_set_pipe_src_size(new_crtc_state);
15347 /* on skylake this is done by detaching scalers */
15348 if (INTEL_GEN(dev_priv) >= 9) {
15349 skl_detach_scalers(new_crtc_state);
15351 if (new_crtc_state->pch_pfit.enabled)
15352 skl_pfit_enable(new_crtc_state);
15353 } else if (HAS_PCH_SPLIT(dev_priv)) {
15354 if (new_crtc_state->pch_pfit.enabled)
15355 ilk_pfit_enable(new_crtc_state);
15356 else if (old_crtc_state->pch_pfit.enabled)
15357 ilk_pfit_disable(old_crtc_state);
15361 * The register is supposedly single buffered so perhaps
15362 * not 100% correct to do this here. But SKL+ calculate
15363 * this based on the adjust pixel rate so pfit changes do
15364 * affect it and so it must be updated for fastsets.
15365 * HSW/BDW only really need this here for fastboot, after
15366 * that the value should not change without a full modeset.
15368 if (INTEL_GEN(dev_priv) >= 9 ||
15369 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15370 hsw_set_linetime_wm(new_crtc_state);
15372 if (INTEL_GEN(dev_priv) >= 11)
15373 icl_set_pipe_chicken(crtc);
15376 static void commit_pipe_config(struct intel_atomic_state *state,
15377 struct intel_crtc *crtc)
15379 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15380 const struct intel_crtc_state *old_crtc_state =
15381 intel_atomic_get_old_crtc_state(state, crtc);
15382 const struct intel_crtc_state *new_crtc_state =
15383 intel_atomic_get_new_crtc_state(state, crtc);
15384 bool modeset = needs_modeset(new_crtc_state);
15387 * During modesets pipe configuration was programmed as the
15388 * CRTC was enabled.
15391 if (new_crtc_state->uapi.color_mgmt_changed ||
15392 new_crtc_state->update_pipe)
15393 intel_color_commit(new_crtc_state);
15395 if (INTEL_GEN(dev_priv) >= 9)
15396 skl_detach_scalers(new_crtc_state);
15398 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15399 bdw_set_pipemisc(new_crtc_state);
15401 if (new_crtc_state->update_pipe)
15402 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15404 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15407 if (dev_priv->display.atomic_update_watermarks)
15408 dev_priv->display.atomic_update_watermarks(state, crtc);
15411 static void intel_enable_crtc(struct intel_atomic_state *state,
15412 struct intel_crtc *crtc)
15414 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15415 const struct intel_crtc_state *new_crtc_state =
15416 intel_atomic_get_new_crtc_state(state, crtc);
15418 if (!needs_modeset(new_crtc_state))
15421 intel_crtc_update_active_timings(new_crtc_state);
15423 dev_priv->display.crtc_enable(state, crtc);
15425 /* vblanks work again, re-enable pipe CRC. */
15426 intel_crtc_enable_pipe_crc(crtc);
15429 static void intel_update_crtc(struct intel_atomic_state *state,
15430 struct intel_crtc *crtc)
15432 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15433 const struct intel_crtc_state *old_crtc_state =
15434 intel_atomic_get_old_crtc_state(state, crtc);
15435 struct intel_crtc_state *new_crtc_state =
15436 intel_atomic_get_new_crtc_state(state, crtc);
15437 bool modeset = needs_modeset(new_crtc_state);
15440 if (new_crtc_state->preload_luts &&
15441 (new_crtc_state->uapi.color_mgmt_changed ||
15442 new_crtc_state->update_pipe))
15443 intel_color_load_luts(new_crtc_state);
15445 intel_pre_plane_update(state, crtc);
15447 if (new_crtc_state->update_pipe)
15448 intel_encoders_update_pipe(state, crtc);
15451 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15452 intel_fbc_disable(crtc);
15454 intel_fbc_enable(state, crtc);
15456 /* Perform vblank evasion around commit operation */
15457 intel_pipe_update_start(new_crtc_state);
15459 commit_pipe_config(state, crtc);
15461 if (INTEL_GEN(dev_priv) >= 9)
15462 skl_update_planes_on_crtc(state, crtc);
15464 i9xx_update_planes_on_crtc(state, crtc);
15466 intel_pipe_update_end(new_crtc_state);
15469 * We usually enable FIFO underrun interrupts as part of the
15470 * CRTC enable sequence during modesets. But when we inherit a
15471 * valid pipe configuration from the BIOS we need to take care
15472 * of enabling them on the CRTC's first fastset.
15474 if (new_crtc_state->update_pipe && !modeset &&
15475 old_crtc_state->inherited)
15476 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15480 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15481 struct intel_crtc_state *old_crtc_state,
15482 struct intel_crtc_state *new_crtc_state,
15483 struct intel_crtc *crtc)
15485 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15487 intel_crtc_disable_planes(state, crtc);
15490 * We need to disable pipe CRC before disabling the pipe,
15491 * or we race against vblank off.
15493 intel_crtc_disable_pipe_crc(crtc);
15495 dev_priv->display.crtc_disable(state, crtc);
15496 crtc->active = false;
15497 intel_fbc_disable(crtc);
15498 intel_disable_shared_dpll(old_crtc_state);
15500 /* FIXME unify this for all platforms */
15501 if (!new_crtc_state->hw.active &&
15502 !HAS_GMCH(dev_priv) &&
15503 dev_priv->display.initial_watermarks)
15504 dev_priv->display.initial_watermarks(state, crtc);
15507 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15509 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15510 struct intel_crtc *crtc;
15514 /* Only disable port sync and MST slaves */
15515 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15516 new_crtc_state, i) {
15517 if (!needs_modeset(new_crtc_state))
15520 if (!old_crtc_state->hw.active)
15523 /* In case of Transcoder port Sync master slave CRTCs can be
15524 * assigned in any order and we need to make sure that
15525 * slave CRTCs are disabled first and then master CRTC since
15526 * Slave vblanks are masked till Master Vblanks.
15528 if (!is_trans_port_sync_slave(old_crtc_state) &&
15529 !intel_dp_mst_is_slave_trans(old_crtc_state))
15532 intel_pre_plane_update(state, crtc);
15533 intel_old_crtc_state_disables(state, old_crtc_state,
15534 new_crtc_state, crtc);
15535 handled |= BIT(crtc->pipe);
15538 /* Disable everything else left on */
15539 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15540 new_crtc_state, i) {
15541 if (!needs_modeset(new_crtc_state) ||
15542 (handled & BIT(crtc->pipe)))
15545 intel_pre_plane_update(state, crtc);
15546 if (old_crtc_state->hw.active)
15547 intel_old_crtc_state_disables(state, old_crtc_state,
15548 new_crtc_state, crtc);
15552 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15554 struct intel_crtc_state *new_crtc_state;
15555 struct intel_crtc *crtc;
15558 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15559 if (!new_crtc_state->hw.active)
15562 intel_enable_crtc(state, crtc);
15563 intel_update_crtc(state, crtc);
15567 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15569 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15570 struct intel_crtc *crtc;
15571 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15572 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15573 u8 update_pipes = 0, modeset_pipes = 0;
15576 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15577 enum pipe pipe = crtc->pipe;
15579 if (!new_crtc_state->hw.active)
15582 /* ignore allocations for crtc's that have been turned off. */
15583 if (!needs_modeset(new_crtc_state)) {
15584 entries[pipe] = old_crtc_state->wm.skl.ddb;
15585 update_pipes |= BIT(pipe);
15587 modeset_pipes |= BIT(pipe);
15592 * Whenever the number of active pipes changes, we need to make sure we
15593 * update the pipes in the right order so that their ddb allocations
15594 * never overlap with each other between CRTC updates. Otherwise we'll
15595 * cause pipe underruns and other bad stuff.
15597 * So first lets enable all pipes that do not need a fullmodeset as
15598 * those don't have any external dependency.
15600 while (update_pipes) {
15601 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15602 new_crtc_state, i) {
15603 enum pipe pipe = crtc->pipe;
15605 if ((update_pipes & BIT(pipe)) == 0)
15608 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15609 entries, I915_MAX_PIPES, pipe))
15612 entries[pipe] = new_crtc_state->wm.skl.ddb;
15613 update_pipes &= ~BIT(pipe);
15615 intel_update_crtc(state, crtc);
15618 * If this is an already active pipe, it's DDB changed,
15619 * and this isn't the last pipe that needs updating
15620 * then we need to wait for a vblank to pass for the
15621 * new ddb allocation to take effect.
15623 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15624 &old_crtc_state->wm.skl.ddb) &&
15625 (update_pipes | modeset_pipes))
15626 intel_wait_for_vblank(dev_priv, pipe);
15630 update_pipes = modeset_pipes;
15633 * Enable all pipes that needs a modeset and do not depends on other
15636 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15637 enum pipe pipe = crtc->pipe;
15639 if ((modeset_pipes & BIT(pipe)) == 0)
15642 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15643 is_trans_port_sync_master(new_crtc_state))
15646 modeset_pipes &= ~BIT(pipe);
15648 intel_enable_crtc(state, crtc);
15652 * Then we enable all remaining pipes that depend on other
15653 * pipes: MST slaves and port sync masters.
15655 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15656 enum pipe pipe = crtc->pipe;
15658 if ((modeset_pipes & BIT(pipe)) == 0)
15661 modeset_pipes &= ~BIT(pipe);
15663 intel_enable_crtc(state, crtc);
15667 * Finally we do the plane updates/etc. for all pipes that got enabled.
15669 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15670 enum pipe pipe = crtc->pipe;
15672 if ((update_pipes & BIT(pipe)) == 0)
15675 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15676 entries, I915_MAX_PIPES, pipe));
15678 entries[pipe] = new_crtc_state->wm.skl.ddb;
15679 update_pipes &= ~BIT(pipe);
15681 intel_update_crtc(state, crtc);
15684 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15685 drm_WARN_ON(&dev_priv->drm, update_pipes);
15688 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15690 struct intel_atomic_state *state, *next;
15691 struct llist_node *freed;
15693 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15694 llist_for_each_entry_safe(state, next, freed, freed)
15695 drm_atomic_state_put(&state->base);
15698 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15700 struct drm_i915_private *dev_priv =
15701 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15703 intel_atomic_helper_free_state(dev_priv);
15706 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15708 struct wait_queue_entry wait_fence, wait_reset;
15709 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15711 init_wait_entry(&wait_fence, 0);
15712 init_wait_entry(&wait_reset, 0);
15714 prepare_to_wait(&intel_state->commit_ready.wait,
15715 &wait_fence, TASK_UNINTERRUPTIBLE);
15716 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15717 I915_RESET_MODESET),
15718 &wait_reset, TASK_UNINTERRUPTIBLE);
15721 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15722 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15727 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15728 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15729 I915_RESET_MODESET),
15733 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15735 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15736 struct intel_crtc *crtc;
15739 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15741 intel_dsb_cleanup(old_crtc_state);
15744 static void intel_atomic_cleanup_work(struct work_struct *work)
15746 struct intel_atomic_state *state =
15747 container_of(work, struct intel_atomic_state, base.commit_work);
15748 struct drm_i915_private *i915 = to_i915(state->base.dev);
15750 intel_cleanup_dsbs(state);
15751 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15752 drm_atomic_helper_commit_cleanup_done(&state->base);
15753 drm_atomic_state_put(&state->base);
15755 intel_atomic_helper_free_state(i915);
15758 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15760 struct drm_device *dev = state->base.dev;
15761 struct drm_i915_private *dev_priv = to_i915(dev);
15762 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15763 struct intel_crtc *crtc;
15764 u64 put_domains[I915_MAX_PIPES] = {};
15765 intel_wakeref_t wakeref = 0;
15768 intel_atomic_commit_fence_wait(state);
15770 drm_atomic_helper_wait_for_dependencies(&state->base);
15772 if (state->modeset)
15773 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15775 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15776 new_crtc_state, i) {
15777 if (needs_modeset(new_crtc_state) ||
15778 new_crtc_state->update_pipe) {
15780 put_domains[crtc->pipe] =
15781 modeset_get_crtc_power_domains(new_crtc_state);
15785 intel_commit_modeset_disables(state);
15787 /* FIXME: Eventually get rid of our crtc->config pointer */
15788 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15789 crtc->config = new_crtc_state;
15791 if (state->modeset) {
15792 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15794 intel_set_cdclk_pre_plane_update(state);
15796 intel_modeset_verify_disabled(dev_priv, state);
15799 intel_sagv_pre_plane_update(state);
15801 /* Complete the events for pipes that have now been disabled */
15802 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15803 bool modeset = needs_modeset(new_crtc_state);
15805 /* Complete events for now disable pipes here. */
15806 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15807 spin_lock_irq(&dev->event_lock);
15808 drm_crtc_send_vblank_event(&crtc->base,
15809 new_crtc_state->uapi.event);
15810 spin_unlock_irq(&dev->event_lock);
15812 new_crtc_state->uapi.event = NULL;
15816 if (state->modeset)
15817 intel_encoders_update_prepare(state);
15819 intel_dbuf_pre_plane_update(state);
15821 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15822 if (new_crtc_state->uapi.async_flip)
15823 skl_enable_flip_done(crtc);
15826 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15827 dev_priv->display.commit_modeset_enables(state);
15829 if (state->modeset) {
15830 intel_encoders_update_complete(state);
15832 intel_set_cdclk_post_plane_update(state);
15835 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15836 * already, but still need the state for the delayed optimization. To
15838 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15839 * - schedule that vblank worker _before_ calling hw_done
15840 * - at the start of commit_tail, cancel it _synchrously
15841 * - switch over to the vblank wait helper in the core after that since
15842 * we don't need out special handling any more.
15844 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15846 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15847 if (new_crtc_state->uapi.async_flip)
15848 skl_disable_flip_done(crtc);
15850 if (new_crtc_state->hw.active &&
15851 !needs_modeset(new_crtc_state) &&
15852 !new_crtc_state->preload_luts &&
15853 (new_crtc_state->uapi.color_mgmt_changed ||
15854 new_crtc_state->update_pipe))
15855 intel_color_load_luts(new_crtc_state);
15859 * Now that the vblank has passed, we can go ahead and program the
15860 * optimal watermarks on platforms that need two-step watermark
15863 * TODO: Move this (and other cleanup) to an async worker eventually.
15865 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15866 new_crtc_state, i) {
15868 * Gen2 reports pipe underruns whenever all planes are disabled.
15869 * So re-enable underrun reporting after some planes get enabled.
15871 * We do this before .optimize_watermarks() so that we have a
15872 * chance of catching underruns with the intermediate watermarks
15873 * vs. the new plane configuration.
15875 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15876 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15878 if (dev_priv->display.optimize_watermarks)
15879 dev_priv->display.optimize_watermarks(state, crtc);
15882 intel_dbuf_post_plane_update(state);
15884 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15885 intel_post_plane_update(state, crtc);
15887 if (put_domains[i])
15888 modeset_put_power_domains(dev_priv, put_domains[i]);
15890 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15893 * DSB cleanup is done in cleanup_work aligning with framebuffer
15894 * cleanup. So copy and reset the dsb structure to sync with
15895 * commit_done and later do dsb cleanup in cleanup_work.
15897 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15900 /* Underruns don't always raise interrupts, so check manually */
15901 intel_check_cpu_fifo_underruns(dev_priv);
15902 intel_check_pch_fifo_underruns(dev_priv);
15904 if (state->modeset)
15905 intel_verify_planes(state);
15907 intel_sagv_post_plane_update(state);
15909 drm_atomic_helper_commit_hw_done(&state->base);
15911 if (state->modeset) {
15912 /* As one of the primary mmio accessors, KMS has a high
15913 * likelihood of triggering bugs in unclaimed access. After we
15914 * finish modesetting, see if an error has been flagged, and if
15915 * so enable debugging for the next modeset - and hope we catch
15918 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15919 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15921 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15924 * Defer the cleanup of the old state to a separate worker to not
15925 * impede the current task (userspace for blocking modesets) that
15926 * are executed inline. For out-of-line asynchronous modesets/flips,
15927 * deferring to a new worker seems overkill, but we would place a
15928 * schedule point (cond_resched()) here anyway to keep latencies
15931 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15932 queue_work(system_highpri_wq, &state->base.commit_work);
15935 static void intel_atomic_commit_work(struct work_struct *work)
15937 struct intel_atomic_state *state =
15938 container_of(work, struct intel_atomic_state, base.commit_work);
15940 intel_atomic_commit_tail(state);
15943 static int __i915_sw_fence_call
15944 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15945 enum i915_sw_fence_notify notify)
15947 struct intel_atomic_state *state =
15948 container_of(fence, struct intel_atomic_state, commit_ready);
15951 case FENCE_COMPLETE:
15952 /* we do blocking waits in the worker, nothing to do here */
15956 struct intel_atomic_helper *helper =
15957 &to_i915(state->base.dev)->atomic_helper;
15959 if (llist_add(&state->freed, &helper->free_list))
15960 schedule_work(&helper->free_work);
15965 return NOTIFY_DONE;
15968 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15970 struct intel_plane_state *old_plane_state, *new_plane_state;
15971 struct intel_plane *plane;
15974 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15975 new_plane_state, i)
15976 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15977 to_intel_frontbuffer(new_plane_state->hw.fb),
15978 plane->frontbuffer_bit);
15981 static int intel_atomic_commit(struct drm_device *dev,
15982 struct drm_atomic_state *_state,
15985 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15986 struct drm_i915_private *dev_priv = to_i915(dev);
15989 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15991 drm_atomic_state_get(&state->base);
15992 i915_sw_fence_init(&state->commit_ready,
15993 intel_atomic_commit_ready);
15996 * The intel_legacy_cursor_update() fast path takes care
15997 * of avoiding the vblank waits for simple cursor
15998 * movement and flips. For cursor on/off and size changes,
15999 * we want to perform the vblank waits so that watermark
16000 * updates happen during the correct frames. Gen9+ have
16001 * double buffered watermarks and so shouldn't need this.
16003 * Unset state->legacy_cursor_update before the call to
16004 * drm_atomic_helper_setup_commit() because otherwise
16005 * drm_atomic_helper_wait_for_flip_done() is a noop and
16006 * we get FIFO underruns because we didn't wait
16009 * FIXME doing watermarks and fb cleanup from a vblank worker
16010 * (assuming we had any) would solve these problems.
16012 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
16013 struct intel_crtc_state *new_crtc_state;
16014 struct intel_crtc *crtc;
16017 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16018 if (new_crtc_state->wm.need_postvbl_update ||
16019 new_crtc_state->update_wm_post)
16020 state->base.legacy_cursor_update = false;
16023 ret = intel_atomic_prepare_commit(state);
16025 drm_dbg_atomic(&dev_priv->drm,
16026 "Preparing state failed with %i\n", ret);
16027 i915_sw_fence_commit(&state->commit_ready);
16028 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16032 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
16034 ret = drm_atomic_helper_swap_state(&state->base, true);
16036 intel_atomic_swap_global_state(state);
16039 struct intel_crtc_state *new_crtc_state;
16040 struct intel_crtc *crtc;
16043 i915_sw_fence_commit(&state->commit_ready);
16045 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16046 intel_dsb_cleanup(new_crtc_state);
16048 drm_atomic_helper_cleanup_planes(dev, &state->base);
16049 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16052 dev_priv->wm.distrust_bios_wm = false;
16053 intel_shared_dpll_swap_state(state);
16054 intel_atomic_track_fbs(state);
16056 drm_atomic_state_get(&state->base);
16057 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
16059 i915_sw_fence_commit(&state->commit_ready);
16060 if (nonblock && state->modeset) {
16061 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
16062 } else if (nonblock) {
16063 queue_work(dev_priv->flip_wq, &state->base.commit_work);
16065 if (state->modeset)
16066 flush_workqueue(dev_priv->modeset_wq);
16067 intel_atomic_commit_tail(state);
16073 struct wait_rps_boost {
16074 struct wait_queue_entry wait;
16076 struct drm_crtc *crtc;
16077 struct i915_request *request;
16080 static int do_rps_boost(struct wait_queue_entry *_wait,
16081 unsigned mode, int sync, void *key)
16083 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
16084 struct i915_request *rq = wait->request;
16087 * If we missed the vblank, but the request is already running it
16088 * is reasonable to assume that it will complete before the next
16089 * vblank without our intervention, so leave RPS alone.
16091 if (!i915_request_started(rq))
16092 intel_rps_boost(rq);
16093 i915_request_put(rq);
16095 drm_crtc_vblank_put(wait->crtc);
16097 list_del(&wait->wait.entry);
16102 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
16103 struct dma_fence *fence)
16105 struct wait_rps_boost *wait;
16107 if (!dma_fence_is_i915(fence))
16110 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
16113 if (drm_crtc_vblank_get(crtc))
16116 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
16118 drm_crtc_vblank_put(crtc);
16122 wait->request = to_request(dma_fence_get(fence));
16125 wait->wait.func = do_rps_boost;
16126 wait->wait.flags = 0;
16128 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
16131 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
16133 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
16134 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16135 struct drm_framebuffer *fb = plane_state->hw.fb;
16136 struct i915_vma *vma;
16138 if (plane->id == PLANE_CURSOR &&
16139 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
16140 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16141 const int align = intel_cursor_alignment(dev_priv);
16144 err = i915_gem_object_attach_phys(obj, align);
16149 vma = intel_pin_and_fence_fb_obj(fb,
16150 &plane_state->view,
16151 intel_plane_uses_fence(plane_state),
16152 &plane_state->flags);
16154 return PTR_ERR(vma);
16156 plane_state->vma = vma;
16161 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
16163 struct i915_vma *vma;
16165 vma = fetch_and_zero(&old_plane_state->vma);
16167 intel_unpin_fb_vma(vma, old_plane_state->flags);
16170 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
16172 struct i915_sched_attr attr = {
16173 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
16176 i915_gem_object_wait_priority(obj, 0, &attr);
16180 * intel_prepare_plane_fb - Prepare fb for usage on plane
16181 * @_plane: drm plane to prepare for
16182 * @_new_plane_state: the plane state being prepared
16184 * Prepares a framebuffer for usage on a display plane. Generally this
16185 * involves pinning the underlying object and updating the frontbuffer tracking
16186 * bits. Some older platforms need special physical address handling for
16189 * Returns 0 on success, negative error code on failure.
16192 intel_prepare_plane_fb(struct drm_plane *_plane,
16193 struct drm_plane_state *_new_plane_state)
16195 struct intel_plane *plane = to_intel_plane(_plane);
16196 struct intel_plane_state *new_plane_state =
16197 to_intel_plane_state(_new_plane_state);
16198 struct intel_atomic_state *state =
16199 to_intel_atomic_state(new_plane_state->uapi.state);
16200 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16201 const struct intel_plane_state *old_plane_state =
16202 intel_atomic_get_old_plane_state(state, plane);
16203 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
16204 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
16208 const struct intel_crtc_state *crtc_state =
16209 intel_atomic_get_new_crtc_state(state,
16210 to_intel_crtc(old_plane_state->hw.crtc));
16212 /* Big Hammer, we also need to ensure that any pending
16213 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16214 * current scanout is retired before unpinning the old
16215 * framebuffer. Note that we rely on userspace rendering
16216 * into the buffer attached to the pipe they are waiting
16217 * on. If not, userspace generates a GPU hang with IPEHR
16218 * point to the MI_WAIT_FOR_EVENT.
16220 * This should only fail upon a hung GPU, in which case we
16221 * can safely continue.
16223 if (needs_modeset(crtc_state)) {
16224 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16225 old_obj->base.resv, NULL,
16233 if (new_plane_state->uapi.fence) { /* explicit fencing */
16234 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16235 new_plane_state->uapi.fence,
16236 i915_fence_timeout(dev_priv),
16245 ret = i915_gem_object_pin_pages(obj);
16249 ret = intel_plane_pin_fb(new_plane_state);
16251 i915_gem_object_unpin_pages(obj);
16255 fb_obj_bump_render_priority(obj);
16256 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16258 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16259 struct dma_fence *fence;
16261 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16262 obj->base.resv, NULL,
16264 i915_fence_timeout(dev_priv),
16269 fence = dma_resv_get_excl_rcu(obj->base.resv);
16271 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16273 dma_fence_put(fence);
16276 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16277 new_plane_state->uapi.fence);
16281 * We declare pageflips to be interactive and so merit a small bias
16282 * towards upclocking to deliver the frame on time. By only changing
16283 * the RPS thresholds to sample more regularly and aim for higher
16284 * clocks we can hopefully deliver low power workloads (like kodi)
16285 * that are not quite steady state without resorting to forcing
16286 * maximum clocks following a vblank miss (see do_rps_boost()).
16288 if (!state->rps_interactive) {
16289 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16290 state->rps_interactive = true;
16296 intel_plane_unpin_fb(new_plane_state);
16302 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16303 * @plane: drm plane to clean up for
16304 * @_old_plane_state: the state from the previous modeset
16306 * Cleans up a framebuffer that has just been removed from a plane.
16309 intel_cleanup_plane_fb(struct drm_plane *plane,
16310 struct drm_plane_state *_old_plane_state)
16312 struct intel_plane_state *old_plane_state =
16313 to_intel_plane_state(_old_plane_state);
16314 struct intel_atomic_state *state =
16315 to_intel_atomic_state(old_plane_state->uapi.state);
16316 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16317 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16322 if (state->rps_interactive) {
16323 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16324 state->rps_interactive = false;
16327 /* Should only be called after a successful intel_prepare_plane_fb()! */
16328 intel_plane_unpin_fb(old_plane_state);
16332 * intel_plane_destroy - destroy a plane
16333 * @plane: plane to destroy
16335 * Common destruction function for all types of planes (primary, cursor,
16338 void intel_plane_destroy(struct drm_plane *plane)
16340 drm_plane_cleanup(plane);
16341 kfree(to_intel_plane(plane));
16344 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16345 u32 format, u64 modifier)
16347 switch (modifier) {
16348 case DRM_FORMAT_MOD_LINEAR:
16349 case I915_FORMAT_MOD_X_TILED:
16356 case DRM_FORMAT_C8:
16357 case DRM_FORMAT_RGB565:
16358 case DRM_FORMAT_XRGB1555:
16359 case DRM_FORMAT_XRGB8888:
16360 return modifier == DRM_FORMAT_MOD_LINEAR ||
16361 modifier == I915_FORMAT_MOD_X_TILED;
16367 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16368 u32 format, u64 modifier)
16370 switch (modifier) {
16371 case DRM_FORMAT_MOD_LINEAR:
16372 case I915_FORMAT_MOD_X_TILED:
16379 case DRM_FORMAT_C8:
16380 case DRM_FORMAT_RGB565:
16381 case DRM_FORMAT_XRGB8888:
16382 case DRM_FORMAT_XBGR8888:
16383 case DRM_FORMAT_ARGB8888:
16384 case DRM_FORMAT_ABGR8888:
16385 case DRM_FORMAT_XRGB2101010:
16386 case DRM_FORMAT_XBGR2101010:
16387 case DRM_FORMAT_ARGB2101010:
16388 case DRM_FORMAT_ABGR2101010:
16389 case DRM_FORMAT_XBGR16161616F:
16390 return modifier == DRM_FORMAT_MOD_LINEAR ||
16391 modifier == I915_FORMAT_MOD_X_TILED;
16397 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16398 u32 format, u64 modifier)
16400 return modifier == DRM_FORMAT_MOD_LINEAR &&
16401 format == DRM_FORMAT_ARGB8888;
16404 static const struct drm_plane_funcs i965_plane_funcs = {
16405 .update_plane = drm_atomic_helper_update_plane,
16406 .disable_plane = drm_atomic_helper_disable_plane,
16407 .destroy = intel_plane_destroy,
16408 .atomic_duplicate_state = intel_plane_duplicate_state,
16409 .atomic_destroy_state = intel_plane_destroy_state,
16410 .format_mod_supported = i965_plane_format_mod_supported,
16413 static const struct drm_plane_funcs i8xx_plane_funcs = {
16414 .update_plane = drm_atomic_helper_update_plane,
16415 .disable_plane = drm_atomic_helper_disable_plane,
16416 .destroy = intel_plane_destroy,
16417 .atomic_duplicate_state = intel_plane_duplicate_state,
16418 .atomic_destroy_state = intel_plane_destroy_state,
16419 .format_mod_supported = i8xx_plane_format_mod_supported,
16423 intel_legacy_cursor_update(struct drm_plane *_plane,
16424 struct drm_crtc *_crtc,
16425 struct drm_framebuffer *fb,
16426 int crtc_x, int crtc_y,
16427 unsigned int crtc_w, unsigned int crtc_h,
16428 u32 src_x, u32 src_y,
16429 u32 src_w, u32 src_h,
16430 struct drm_modeset_acquire_ctx *ctx)
16432 struct intel_plane *plane = to_intel_plane(_plane);
16433 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16434 struct intel_plane_state *old_plane_state =
16435 to_intel_plane_state(plane->base.state);
16436 struct intel_plane_state *new_plane_state;
16437 struct intel_crtc_state *crtc_state =
16438 to_intel_crtc_state(crtc->base.state);
16439 struct intel_crtc_state *new_crtc_state;
16443 * When crtc is inactive or there is a modeset pending,
16444 * wait for it to complete in the slowpath
16446 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16447 crtc_state->update_pipe)
16451 * Don't do an async update if there is an outstanding commit modifying
16452 * the plane. This prevents our async update's changes from getting
16453 * overridden by a previous synchronous update's state.
16455 if (old_plane_state->uapi.commit &&
16456 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16460 * If any parameters change that may affect watermarks,
16461 * take the slowpath. Only changing fb or position should be
16464 if (old_plane_state->uapi.crtc != &crtc->base ||
16465 old_plane_state->uapi.src_w != src_w ||
16466 old_plane_state->uapi.src_h != src_h ||
16467 old_plane_state->uapi.crtc_w != crtc_w ||
16468 old_plane_state->uapi.crtc_h != crtc_h ||
16469 !old_plane_state->uapi.fb != !fb)
16472 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16473 if (!new_plane_state)
16476 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16477 if (!new_crtc_state) {
16482 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16484 new_plane_state->uapi.src_x = src_x;
16485 new_plane_state->uapi.src_y = src_y;
16486 new_plane_state->uapi.src_w = src_w;
16487 new_plane_state->uapi.src_h = src_h;
16488 new_plane_state->uapi.crtc_x = crtc_x;
16489 new_plane_state->uapi.crtc_y = crtc_y;
16490 new_plane_state->uapi.crtc_w = crtc_w;
16491 new_plane_state->uapi.crtc_h = crtc_h;
16493 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16495 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16496 old_plane_state, new_plane_state);
16500 ret = intel_plane_pin_fb(new_plane_state);
16504 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16506 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16507 to_intel_frontbuffer(new_plane_state->hw.fb),
16508 plane->frontbuffer_bit);
16510 /* Swap plane state */
16511 plane->base.state = &new_plane_state->uapi;
16514 * We cannot swap crtc_state as it may be in use by an atomic commit or
16515 * page flip that's running simultaneously. If we swap crtc_state and
16516 * destroy the old state, we will cause a use-after-free there.
16518 * Only update active_planes, which is needed for our internal
16519 * bookkeeping. Either value will do the right thing when updating
16520 * planes atomically. If the cursor was part of the atomic update then
16521 * we would have taken the slowpath.
16523 crtc_state->active_planes = new_crtc_state->active_planes;
16525 if (new_plane_state->uapi.visible)
16526 intel_update_plane(plane, crtc_state, new_plane_state);
16528 intel_disable_plane(plane, crtc_state);
16530 intel_plane_unpin_fb(old_plane_state);
16533 if (new_crtc_state)
16534 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16536 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16538 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16542 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16543 crtc_x, crtc_y, crtc_w, crtc_h,
16544 src_x, src_y, src_w, src_h, ctx);
16547 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16548 .update_plane = intel_legacy_cursor_update,
16549 .disable_plane = drm_atomic_helper_disable_plane,
16550 .destroy = intel_plane_destroy,
16551 .atomic_duplicate_state = intel_plane_duplicate_state,
16552 .atomic_destroy_state = intel_plane_destroy_state,
16553 .format_mod_supported = intel_cursor_format_mod_supported,
16556 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16557 enum i9xx_plane_id i9xx_plane)
16559 if (!HAS_FBC(dev_priv))
16562 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16563 return i9xx_plane == PLANE_A; /* tied to pipe A */
16564 else if (IS_IVYBRIDGE(dev_priv))
16565 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16566 i9xx_plane == PLANE_C;
16567 else if (INTEL_GEN(dev_priv) >= 4)
16568 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16570 return i9xx_plane == PLANE_A;
16573 static struct intel_plane *
16574 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16576 struct intel_plane *plane;
16577 const struct drm_plane_funcs *plane_funcs;
16578 unsigned int supported_rotations;
16579 const u32 *formats;
16583 if (INTEL_GEN(dev_priv) >= 9)
16584 return skl_universal_plane_create(dev_priv, pipe,
16587 plane = intel_plane_alloc();
16591 plane->pipe = pipe;
16593 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16594 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16596 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16597 INTEL_NUM_PIPES(dev_priv) == 2)
16598 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16600 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16601 plane->id = PLANE_PRIMARY;
16602 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16604 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16605 if (plane->has_fbc) {
16606 struct intel_fbc *fbc = &dev_priv->fbc;
16608 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16611 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16612 formats = vlv_primary_formats;
16613 num_formats = ARRAY_SIZE(vlv_primary_formats);
16614 } else if (INTEL_GEN(dev_priv) >= 4) {
16616 * WaFP16GammaEnabling:ivb
16617 * "Workaround : When using the 64-bit format, the plane
16618 * output on each color channel has one quarter amplitude.
16619 * It can be brought up to full amplitude by using pipe
16620 * gamma correction or pipe color space conversion to
16621 * multiply the plane output by four."
16623 * There is no dedicated plane gamma for the primary plane,
16624 * and using the pipe gamma/csc could conflict with other
16625 * planes, so we choose not to expose fp16 on IVB primary
16626 * planes. HSW primary planes no longer have this problem.
16628 if (IS_IVYBRIDGE(dev_priv)) {
16629 formats = ivb_primary_formats;
16630 num_formats = ARRAY_SIZE(ivb_primary_formats);
16632 formats = i965_primary_formats;
16633 num_formats = ARRAY_SIZE(i965_primary_formats);
16636 formats = i8xx_primary_formats;
16637 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16640 if (INTEL_GEN(dev_priv) >= 4)
16641 plane_funcs = &i965_plane_funcs;
16643 plane_funcs = &i8xx_plane_funcs;
16645 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16646 plane->min_cdclk = vlv_plane_min_cdclk;
16647 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16648 plane->min_cdclk = hsw_plane_min_cdclk;
16649 else if (IS_IVYBRIDGE(dev_priv))
16650 plane->min_cdclk = ivb_plane_min_cdclk;
16652 plane->min_cdclk = i9xx_plane_min_cdclk;
16654 plane->max_stride = i9xx_plane_max_stride;
16655 plane->update_plane = i9xx_update_plane;
16656 plane->disable_plane = i9xx_disable_plane;
16657 plane->get_hw_state = i9xx_plane_get_hw_state;
16658 plane->check_plane = i9xx_plane_check;
16660 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16661 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16663 formats, num_formats,
16664 i9xx_format_modifiers,
16665 DRM_PLANE_TYPE_PRIMARY,
16666 "primary %c", pipe_name(pipe));
16668 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16670 formats, num_formats,
16671 i9xx_format_modifiers,
16672 DRM_PLANE_TYPE_PRIMARY,
16674 plane_name(plane->i9xx_plane));
16678 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16679 supported_rotations =
16680 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16681 DRM_MODE_REFLECT_X;
16682 } else if (INTEL_GEN(dev_priv) >= 4) {
16683 supported_rotations =
16684 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16686 supported_rotations = DRM_MODE_ROTATE_0;
16689 if (INTEL_GEN(dev_priv) >= 4)
16690 drm_plane_create_rotation_property(&plane->base,
16692 supported_rotations);
16695 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16697 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16702 intel_plane_free(plane);
16704 return ERR_PTR(ret);
16707 static struct intel_plane *
16708 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16711 struct intel_plane *cursor;
16714 cursor = intel_plane_alloc();
16715 if (IS_ERR(cursor))
16718 cursor->pipe = pipe;
16719 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16720 cursor->id = PLANE_CURSOR;
16721 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16723 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16724 cursor->max_stride = i845_cursor_max_stride;
16725 cursor->update_plane = i845_update_cursor;
16726 cursor->disable_plane = i845_disable_cursor;
16727 cursor->get_hw_state = i845_cursor_get_hw_state;
16728 cursor->check_plane = i845_check_cursor;
16730 cursor->max_stride = i9xx_cursor_max_stride;
16731 cursor->update_plane = i9xx_update_cursor;
16732 cursor->disable_plane = i9xx_disable_cursor;
16733 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16734 cursor->check_plane = i9xx_check_cursor;
16737 cursor->cursor.base = ~0;
16738 cursor->cursor.cntl = ~0;
16740 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16741 cursor->cursor.size = ~0;
16743 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16744 0, &intel_cursor_plane_funcs,
16745 intel_cursor_formats,
16746 ARRAY_SIZE(intel_cursor_formats),
16747 cursor_format_modifiers,
16748 DRM_PLANE_TYPE_CURSOR,
16749 "cursor %c", pipe_name(pipe));
16753 if (INTEL_GEN(dev_priv) >= 4)
16754 drm_plane_create_rotation_property(&cursor->base,
16756 DRM_MODE_ROTATE_0 |
16757 DRM_MODE_ROTATE_180);
16759 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16760 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16762 if (INTEL_GEN(dev_priv) >= 12)
16763 drm_plane_enable_fb_damage_clips(&cursor->base);
16765 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16770 intel_plane_free(cursor);
16772 return ERR_PTR(ret);
16775 #define INTEL_CRTC_FUNCS \
16776 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16777 .set_config = drm_atomic_helper_set_config, \
16778 .destroy = intel_crtc_destroy, \
16779 .page_flip = drm_atomic_helper_page_flip, \
16780 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16781 .atomic_destroy_state = intel_crtc_destroy_state, \
16782 .set_crc_source = intel_crtc_set_crc_source, \
16783 .verify_crc_source = intel_crtc_verify_crc_source, \
16784 .get_crc_sources = intel_crtc_get_crc_sources
16786 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16789 .get_vblank_counter = g4x_get_vblank_counter,
16790 .enable_vblank = bdw_enable_vblank,
16791 .disable_vblank = bdw_disable_vblank,
16792 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16795 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16798 .get_vblank_counter = g4x_get_vblank_counter,
16799 .enable_vblank = ilk_enable_vblank,
16800 .disable_vblank = ilk_disable_vblank,
16801 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16804 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16807 .get_vblank_counter = g4x_get_vblank_counter,
16808 .enable_vblank = i965_enable_vblank,
16809 .disable_vblank = i965_disable_vblank,
16810 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16813 static const struct drm_crtc_funcs i965_crtc_funcs = {
16816 .get_vblank_counter = i915_get_vblank_counter,
16817 .enable_vblank = i965_enable_vblank,
16818 .disable_vblank = i965_disable_vblank,
16819 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16822 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16825 .get_vblank_counter = i915_get_vblank_counter,
16826 .enable_vblank = i915gm_enable_vblank,
16827 .disable_vblank = i915gm_disable_vblank,
16828 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16831 static const struct drm_crtc_funcs i915_crtc_funcs = {
16834 .get_vblank_counter = i915_get_vblank_counter,
16835 .enable_vblank = i8xx_enable_vblank,
16836 .disable_vblank = i8xx_disable_vblank,
16837 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16840 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16843 /* no hw vblank counter */
16844 .enable_vblank = i8xx_enable_vblank,
16845 .disable_vblank = i8xx_disable_vblank,
16846 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16849 static struct intel_crtc *intel_crtc_alloc(void)
16851 struct intel_crtc_state *crtc_state;
16852 struct intel_crtc *crtc;
16854 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16856 return ERR_PTR(-ENOMEM);
16858 crtc_state = intel_crtc_state_alloc(crtc);
16861 return ERR_PTR(-ENOMEM);
16864 crtc->base.state = &crtc_state->uapi;
16865 crtc->config = crtc_state;
16870 static void intel_crtc_free(struct intel_crtc *crtc)
16872 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16876 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16878 struct intel_plane *plane;
16880 for_each_intel_plane(&dev_priv->drm, plane) {
16881 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16884 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16888 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16890 struct intel_plane *primary, *cursor;
16891 const struct drm_crtc_funcs *funcs;
16892 struct intel_crtc *crtc;
16895 crtc = intel_crtc_alloc();
16897 return PTR_ERR(crtc);
16900 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16902 primary = intel_primary_plane_create(dev_priv, pipe);
16903 if (IS_ERR(primary)) {
16904 ret = PTR_ERR(primary);
16907 crtc->plane_ids_mask |= BIT(primary->id);
16909 for_each_sprite(dev_priv, pipe, sprite) {
16910 struct intel_plane *plane;
16912 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16913 if (IS_ERR(plane)) {
16914 ret = PTR_ERR(plane);
16917 crtc->plane_ids_mask |= BIT(plane->id);
16920 cursor = intel_cursor_plane_create(dev_priv, pipe);
16921 if (IS_ERR(cursor)) {
16922 ret = PTR_ERR(cursor);
16925 crtc->plane_ids_mask |= BIT(cursor->id);
16927 if (HAS_GMCH(dev_priv)) {
16928 if (IS_CHERRYVIEW(dev_priv) ||
16929 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16930 funcs = &g4x_crtc_funcs;
16931 else if (IS_GEN(dev_priv, 4))
16932 funcs = &i965_crtc_funcs;
16933 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16934 funcs = &i915gm_crtc_funcs;
16935 else if (IS_GEN(dev_priv, 3))
16936 funcs = &i915_crtc_funcs;
16938 funcs = &i8xx_crtc_funcs;
16940 if (INTEL_GEN(dev_priv) >= 8)
16941 funcs = &bdw_crtc_funcs;
16943 funcs = &ilk_crtc_funcs;
16946 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16947 &primary->base, &cursor->base,
16948 funcs, "pipe %c", pipe_name(pipe));
16952 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16953 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16954 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16956 if (INTEL_GEN(dev_priv) < 9) {
16957 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16959 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16960 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16961 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16964 intel_color_init(crtc);
16966 intel_crtc_crc_init(crtc);
16968 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16973 intel_crtc_free(crtc);
16978 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16979 struct drm_file *file)
16981 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16982 struct drm_crtc *drmmode_crtc;
16983 struct intel_crtc *crtc;
16985 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16989 crtc = to_intel_crtc(drmmode_crtc);
16990 pipe_from_crtc_id->pipe = crtc->pipe;
16995 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16997 struct drm_device *dev = encoder->base.dev;
16998 struct intel_encoder *source_encoder;
16999 u32 possible_clones = 0;
17001 for_each_intel_encoder(dev, source_encoder) {
17002 if (encoders_cloneable(encoder, source_encoder))
17003 possible_clones |= drm_encoder_mask(&source_encoder->base);
17006 return possible_clones;
17009 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
17011 struct drm_device *dev = encoder->base.dev;
17012 struct intel_crtc *crtc;
17013 u32 possible_crtcs = 0;
17015 for_each_intel_crtc(dev, crtc) {
17016 if (encoder->pipe_mask & BIT(crtc->pipe))
17017 possible_crtcs |= drm_crtc_mask(&crtc->base);
17020 return possible_crtcs;
17023 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
17025 if (!IS_MOBILE(dev_priv))
17028 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
17031 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
17037 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
17039 if (INTEL_GEN(dev_priv) >= 9)
17042 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
17045 if (HAS_PCH_LPT_H(dev_priv) &&
17046 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
17049 /* DDI E can't be used if DDI A requires 4 lanes */
17050 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
17053 if (!dev_priv->vbt.int_crt_support)
17059 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
17064 if (HAS_DDI(dev_priv))
17067 * This w/a is needed at least on CPT/PPT, but to be sure apply it
17068 * everywhere where registers can be write protected.
17070 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17075 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
17076 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
17078 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
17079 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
17083 static void intel_pps_init(struct drm_i915_private *dev_priv)
17085 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
17086 dev_priv->pps_mmio_base = PCH_PPS_BASE;
17087 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17088 dev_priv->pps_mmio_base = VLV_PPS_BASE;
17090 dev_priv->pps_mmio_base = PPS_BASE;
17092 intel_pps_unlock_regs_wa(dev_priv);
17095 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
17097 struct intel_encoder *encoder;
17098 bool dpd_is_edp = false;
17100 intel_pps_init(dev_priv);
17102 if (!HAS_DISPLAY(dev_priv))
17105 if (IS_ROCKETLAKE(dev_priv)) {
17106 intel_ddi_init(dev_priv, PORT_A);
17107 intel_ddi_init(dev_priv, PORT_B);
17108 intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
17109 intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
17110 } else if (INTEL_GEN(dev_priv) >= 12) {
17111 intel_ddi_init(dev_priv, PORT_A);
17112 intel_ddi_init(dev_priv, PORT_B);
17113 intel_ddi_init(dev_priv, PORT_D);
17114 intel_ddi_init(dev_priv, PORT_E);
17115 intel_ddi_init(dev_priv, PORT_F);
17116 intel_ddi_init(dev_priv, PORT_G);
17117 intel_ddi_init(dev_priv, PORT_H);
17118 intel_ddi_init(dev_priv, PORT_I);
17119 icl_dsi_init(dev_priv);
17120 } else if (IS_JSL_EHL(dev_priv)) {
17121 intel_ddi_init(dev_priv, PORT_A);
17122 intel_ddi_init(dev_priv, PORT_B);
17123 intel_ddi_init(dev_priv, PORT_C);
17124 intel_ddi_init(dev_priv, PORT_D);
17125 icl_dsi_init(dev_priv);
17126 } else if (IS_GEN(dev_priv, 11)) {
17127 intel_ddi_init(dev_priv, PORT_A);
17128 intel_ddi_init(dev_priv, PORT_B);
17129 intel_ddi_init(dev_priv, PORT_C);
17130 intel_ddi_init(dev_priv, PORT_D);
17131 intel_ddi_init(dev_priv, PORT_E);
17133 * On some ICL SKUs port F is not present. No strap bits for
17134 * this, so rely on VBT.
17135 * Work around broken VBTs on SKUs known to have no port F.
17137 if (IS_ICL_WITH_PORT_F(dev_priv) &&
17138 intel_bios_is_port_present(dev_priv, PORT_F))
17139 intel_ddi_init(dev_priv, PORT_F);
17141 icl_dsi_init(dev_priv);
17142 } else if (IS_GEN9_LP(dev_priv)) {
17144 * FIXME: Broxton doesn't support port detection via the
17145 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
17146 * detect the ports.
17148 intel_ddi_init(dev_priv, PORT_A);
17149 intel_ddi_init(dev_priv, PORT_B);
17150 intel_ddi_init(dev_priv, PORT_C);
17152 vlv_dsi_init(dev_priv);
17153 } else if (HAS_DDI(dev_priv)) {
17156 if (intel_ddi_crt_present(dev_priv))
17157 intel_crt_init(dev_priv);
17160 * Haswell uses DDI functions to detect digital outputs.
17161 * On SKL pre-D0 the strap isn't connected, so we assume
17164 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
17165 /* WaIgnoreDDIAStrap: skl */
17166 if (found || IS_GEN9_BC(dev_priv))
17167 intel_ddi_init(dev_priv, PORT_A);
17169 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
17171 found = intel_de_read(dev_priv, SFUSE_STRAP);
17173 if (found & SFUSE_STRAP_DDIB_DETECTED)
17174 intel_ddi_init(dev_priv, PORT_B);
17175 if (found & SFUSE_STRAP_DDIC_DETECTED)
17176 intel_ddi_init(dev_priv, PORT_C);
17177 if (found & SFUSE_STRAP_DDID_DETECTED)
17178 intel_ddi_init(dev_priv, PORT_D);
17179 if (found & SFUSE_STRAP_DDIF_DETECTED)
17180 intel_ddi_init(dev_priv, PORT_F);
17182 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
17184 if (IS_GEN9_BC(dev_priv) &&
17185 intel_bios_is_port_present(dev_priv, PORT_E))
17186 intel_ddi_init(dev_priv, PORT_E);
17188 } else if (HAS_PCH_SPLIT(dev_priv)) {
17192 * intel_edp_init_connector() depends on this completing first,
17193 * to prevent the registration of both eDP and LVDS and the
17194 * incorrect sharing of the PPS.
17196 intel_lvds_init(dev_priv);
17197 intel_crt_init(dev_priv);
17199 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
17201 if (ilk_has_edp_a(dev_priv))
17202 intel_dp_init(dev_priv, DP_A, PORT_A);
17204 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
17205 /* PCH SDVOB multiplex with HDMIB */
17206 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
17208 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
17209 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
17210 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17213 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17214 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17216 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17217 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17219 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17220 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17222 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17223 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17224 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17225 bool has_edp, has_port;
17227 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17228 intel_crt_init(dev_priv);
17231 * The DP_DETECTED bit is the latched state of the DDC
17232 * SDA pin at boot. However since eDP doesn't require DDC
17233 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17234 * eDP ports may have been muxed to an alternate function.
17235 * Thus we can't rely on the DP_DETECTED bit alone to detect
17236 * eDP ports. Consult the VBT as well as DP_DETECTED to
17237 * detect eDP ports.
17239 * Sadly the straps seem to be missing sometimes even for HDMI
17240 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17241 * and VBT for the presence of the port. Additionally we can't
17242 * trust the port type the VBT declares as we've seen at least
17243 * HDMI ports that the VBT claim are DP or eDP.
17245 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17246 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17247 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17248 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17249 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17250 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17252 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17253 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17254 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17255 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17256 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17257 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17259 if (IS_CHERRYVIEW(dev_priv)) {
17261 * eDP not supported on port D,
17262 * so no need to worry about it
17264 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17265 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17266 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17267 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17268 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17271 vlv_dsi_init(dev_priv);
17272 } else if (IS_PINEVIEW(dev_priv)) {
17273 intel_lvds_init(dev_priv);
17274 intel_crt_init(dev_priv);
17275 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17276 bool found = false;
17278 if (IS_MOBILE(dev_priv))
17279 intel_lvds_init(dev_priv);
17281 intel_crt_init(dev_priv);
17283 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17284 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17285 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17286 if (!found && IS_G4X(dev_priv)) {
17287 drm_dbg_kms(&dev_priv->drm,
17288 "probing HDMI on SDVOB\n");
17289 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17292 if (!found && IS_G4X(dev_priv))
17293 intel_dp_init(dev_priv, DP_B, PORT_B);
17296 /* Before G4X SDVOC doesn't have its own detect register */
17298 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17299 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17300 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17303 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17305 if (IS_G4X(dev_priv)) {
17306 drm_dbg_kms(&dev_priv->drm,
17307 "probing HDMI on SDVOC\n");
17308 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17310 if (IS_G4X(dev_priv))
17311 intel_dp_init(dev_priv, DP_C, PORT_C);
17314 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17315 intel_dp_init(dev_priv, DP_D, PORT_D);
17317 if (SUPPORTS_TV(dev_priv))
17318 intel_tv_init(dev_priv);
17319 } else if (IS_GEN(dev_priv, 2)) {
17320 if (IS_I85X(dev_priv))
17321 intel_lvds_init(dev_priv);
17323 intel_crt_init(dev_priv);
17324 intel_dvo_init(dev_priv);
17327 intel_psr_init(dev_priv);
17329 for_each_intel_encoder(&dev_priv->drm, encoder) {
17330 encoder->base.possible_crtcs =
17331 intel_encoder_possible_crtcs(encoder);
17332 encoder->base.possible_clones =
17333 intel_encoder_possible_clones(encoder);
17336 intel_init_pch_refclk(dev_priv);
17338 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17341 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17343 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17345 drm_framebuffer_cleanup(fb);
17346 intel_frontbuffer_put(intel_fb->frontbuffer);
17351 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17352 struct drm_file *file,
17353 unsigned int *handle)
17355 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17356 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17358 if (obj->userptr.mm) {
17359 drm_dbg(&i915->drm,
17360 "attempting to use a userptr for a framebuffer, denied\n");
17364 return drm_gem_handle_create(file, &obj->base, handle);
17367 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17368 struct drm_file *file,
17369 unsigned flags, unsigned color,
17370 struct drm_clip_rect *clips,
17371 unsigned num_clips)
17373 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17375 i915_gem_object_flush_if_display(obj);
17376 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17381 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17382 .destroy = intel_user_framebuffer_destroy,
17383 .create_handle = intel_user_framebuffer_create_handle,
17384 .dirty = intel_user_framebuffer_dirty,
17387 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17388 struct drm_i915_gem_object *obj,
17389 struct drm_mode_fb_cmd2 *mode_cmd)
17391 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17392 struct drm_framebuffer *fb = &intel_fb->base;
17394 unsigned int tiling, stride;
17398 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17399 if (!intel_fb->frontbuffer)
17402 i915_gem_object_lock(obj, NULL);
17403 tiling = i915_gem_object_get_tiling(obj);
17404 stride = i915_gem_object_get_stride(obj);
17405 i915_gem_object_unlock(obj);
17407 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17409 * If there's a fence, enforce that
17410 * the fb modifier and tiling mode match.
17412 if (tiling != I915_TILING_NONE &&
17413 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17414 drm_dbg_kms(&dev_priv->drm,
17415 "tiling_mode doesn't match fb modifier\n");
17419 if (tiling == I915_TILING_X) {
17420 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17421 } else if (tiling == I915_TILING_Y) {
17422 drm_dbg_kms(&dev_priv->drm,
17423 "No Y tiling for legacy addfb\n");
17428 if (!drm_any_plane_has_format(&dev_priv->drm,
17429 mode_cmd->pixel_format,
17430 mode_cmd->modifier[0])) {
17431 struct drm_format_name_buf format_name;
17433 drm_dbg_kms(&dev_priv->drm,
17434 "unsupported pixel format %s / modifier 0x%llx\n",
17435 drm_get_format_name(mode_cmd->pixel_format,
17437 mode_cmd->modifier[0]);
17442 * gen2/3 display engine uses the fence if present,
17443 * so the tiling mode must match the fb modifier exactly.
17445 if (INTEL_GEN(dev_priv) < 4 &&
17446 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17447 drm_dbg_kms(&dev_priv->drm,
17448 "tiling_mode must match fb modifier exactly on gen2/3\n");
17452 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17453 mode_cmd->modifier[0]);
17454 if (mode_cmd->pitches[0] > max_stride) {
17455 drm_dbg_kms(&dev_priv->drm,
17456 "%s pitch (%u) must be at most %d\n",
17457 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17458 "tiled" : "linear",
17459 mode_cmd->pitches[0], max_stride);
17464 * If there's a fence, enforce that
17465 * the fb pitch and fence stride match.
17467 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17468 drm_dbg_kms(&dev_priv->drm,
17469 "pitch (%d) must match tiling stride (%d)\n",
17470 mode_cmd->pitches[0], stride);
17474 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17475 if (mode_cmd->offsets[0] != 0) {
17476 drm_dbg_kms(&dev_priv->drm,
17477 "plane 0 offset (0x%08x) must be 0\n",
17478 mode_cmd->offsets[0]);
17482 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17484 for (i = 0; i < fb->format->num_planes; i++) {
17485 u32 stride_alignment;
17487 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17488 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17493 stride_alignment = intel_fb_stride_alignment(fb, i);
17494 if (fb->pitches[i] & (stride_alignment - 1)) {
17495 drm_dbg_kms(&dev_priv->drm,
17496 "plane %d pitch (%d) must be at least %u byte aligned\n",
17497 i, fb->pitches[i], stride_alignment);
17501 if (is_gen12_ccs_plane(fb, i)) {
17502 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17504 if (fb->pitches[i] != ccs_aux_stride) {
17505 drm_dbg_kms(&dev_priv->drm,
17506 "ccs aux plane %d pitch (%d) must be %d\n",
17508 fb->pitches[i], ccs_aux_stride);
17513 fb->obj[i] = &obj->base;
17516 ret = intel_fill_fb_info(dev_priv, fb);
17520 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17522 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17529 intel_frontbuffer_put(intel_fb->frontbuffer);
17533 static struct drm_framebuffer *
17534 intel_user_framebuffer_create(struct drm_device *dev,
17535 struct drm_file *filp,
17536 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17538 struct drm_framebuffer *fb;
17539 struct drm_i915_gem_object *obj;
17540 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17542 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17544 return ERR_PTR(-ENOENT);
17546 fb = intel_framebuffer_create(obj, &mode_cmd);
17547 i915_gem_object_put(obj);
17552 static enum drm_mode_status
17553 intel_mode_valid(struct drm_device *dev,
17554 const struct drm_display_mode *mode)
17556 struct drm_i915_private *dev_priv = to_i915(dev);
17557 int hdisplay_max, htotal_max;
17558 int vdisplay_max, vtotal_max;
17561 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17562 * of DBLSCAN modes to the output's mode list when they detect
17563 * the scaling mode property on the connector. And they don't
17564 * ask the kernel to validate those modes in any way until
17565 * modeset time at which point the client gets a protocol error.
17566 * So in order to not upset those clients we silently ignore the
17567 * DBLSCAN flag on such connectors. For other connectors we will
17568 * reject modes with the DBLSCAN flag in encoder->compute_config().
17569 * And we always reject DBLSCAN modes in connector->mode_valid()
17570 * as we never want such modes on the connector's mode list.
17573 if (mode->vscan > 1)
17574 return MODE_NO_VSCAN;
17576 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17577 return MODE_H_ILLEGAL;
17579 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17580 DRM_MODE_FLAG_NCSYNC |
17581 DRM_MODE_FLAG_PCSYNC))
17584 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17585 DRM_MODE_FLAG_PIXMUX |
17586 DRM_MODE_FLAG_CLKDIV2))
17589 /* Transcoder timing limits */
17590 if (INTEL_GEN(dev_priv) >= 11) {
17591 hdisplay_max = 16384;
17592 vdisplay_max = 8192;
17593 htotal_max = 16384;
17595 } else if (INTEL_GEN(dev_priv) >= 9 ||
17596 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17597 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17598 vdisplay_max = 4096;
17601 } else if (INTEL_GEN(dev_priv) >= 3) {
17602 hdisplay_max = 4096;
17603 vdisplay_max = 4096;
17607 hdisplay_max = 2048;
17608 vdisplay_max = 2048;
17613 if (mode->hdisplay > hdisplay_max ||
17614 mode->hsync_start > htotal_max ||
17615 mode->hsync_end > htotal_max ||
17616 mode->htotal > htotal_max)
17617 return MODE_H_ILLEGAL;
17619 if (mode->vdisplay > vdisplay_max ||
17620 mode->vsync_start > vtotal_max ||
17621 mode->vsync_end > vtotal_max ||
17622 mode->vtotal > vtotal_max)
17623 return MODE_V_ILLEGAL;
17625 if (INTEL_GEN(dev_priv) >= 5) {
17626 if (mode->hdisplay < 64 ||
17627 mode->htotal - mode->hdisplay < 32)
17628 return MODE_H_ILLEGAL;
17630 if (mode->vtotal - mode->vdisplay < 5)
17631 return MODE_V_ILLEGAL;
17633 if (mode->htotal - mode->hdisplay < 32)
17634 return MODE_H_ILLEGAL;
17636 if (mode->vtotal - mode->vdisplay < 3)
17637 return MODE_V_ILLEGAL;
17643 enum drm_mode_status
17644 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17645 const struct drm_display_mode *mode)
17647 int plane_width_max, plane_height_max;
17650 * intel_mode_valid() should be
17651 * sufficient on older platforms.
17653 if (INTEL_GEN(dev_priv) < 9)
17657 * Most people will probably want a fullscreen
17658 * plane so let's not advertize modes that are
17659 * too big for that.
17661 if (INTEL_GEN(dev_priv) >= 11) {
17662 plane_width_max = 5120;
17663 plane_height_max = 4320;
17665 plane_width_max = 5120;
17666 plane_height_max = 4096;
17669 if (mode->hdisplay > plane_width_max)
17670 return MODE_H_ILLEGAL;
17672 if (mode->vdisplay > plane_height_max)
17673 return MODE_V_ILLEGAL;
17678 static const struct drm_mode_config_funcs intel_mode_funcs = {
17679 .fb_create = intel_user_framebuffer_create,
17680 .get_format_info = intel_get_format_info,
17681 .output_poll_changed = intel_fbdev_output_poll_changed,
17682 .mode_valid = intel_mode_valid,
17683 .atomic_check = intel_atomic_check,
17684 .atomic_commit = intel_atomic_commit,
17685 .atomic_state_alloc = intel_atomic_state_alloc,
17686 .atomic_state_clear = intel_atomic_state_clear,
17687 .atomic_state_free = intel_atomic_state_free,
17691 * intel_init_display_hooks - initialize the display modesetting hooks
17692 * @dev_priv: device private
17694 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17696 intel_init_cdclk_hooks(dev_priv);
17698 if (INTEL_GEN(dev_priv) >= 9) {
17699 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17700 dev_priv->display.get_initial_plane_config =
17701 skl_get_initial_plane_config;
17702 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17703 dev_priv->display.crtc_enable = hsw_crtc_enable;
17704 dev_priv->display.crtc_disable = hsw_crtc_disable;
17705 } else if (HAS_DDI(dev_priv)) {
17706 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17707 dev_priv->display.get_initial_plane_config =
17708 i9xx_get_initial_plane_config;
17709 dev_priv->display.crtc_compute_clock =
17710 hsw_crtc_compute_clock;
17711 dev_priv->display.crtc_enable = hsw_crtc_enable;
17712 dev_priv->display.crtc_disable = hsw_crtc_disable;
17713 } else if (HAS_PCH_SPLIT(dev_priv)) {
17714 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17715 dev_priv->display.get_initial_plane_config =
17716 i9xx_get_initial_plane_config;
17717 dev_priv->display.crtc_compute_clock =
17718 ilk_crtc_compute_clock;
17719 dev_priv->display.crtc_enable = ilk_crtc_enable;
17720 dev_priv->display.crtc_disable = ilk_crtc_disable;
17721 } else if (IS_CHERRYVIEW(dev_priv)) {
17722 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17723 dev_priv->display.get_initial_plane_config =
17724 i9xx_get_initial_plane_config;
17725 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17726 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17727 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17728 } else if (IS_VALLEYVIEW(dev_priv)) {
17729 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17730 dev_priv->display.get_initial_plane_config =
17731 i9xx_get_initial_plane_config;
17732 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17733 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17734 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17735 } else if (IS_G4X(dev_priv)) {
17736 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17737 dev_priv->display.get_initial_plane_config =
17738 i9xx_get_initial_plane_config;
17739 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17740 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17741 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17742 } else if (IS_PINEVIEW(dev_priv)) {
17743 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17744 dev_priv->display.get_initial_plane_config =
17745 i9xx_get_initial_plane_config;
17746 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17747 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17748 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17749 } else if (!IS_GEN(dev_priv, 2)) {
17750 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17751 dev_priv->display.get_initial_plane_config =
17752 i9xx_get_initial_plane_config;
17753 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17754 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17755 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17757 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17758 dev_priv->display.get_initial_plane_config =
17759 i9xx_get_initial_plane_config;
17760 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17761 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17762 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17765 if (IS_GEN(dev_priv, 5)) {
17766 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17767 } else if (IS_GEN(dev_priv, 6)) {
17768 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17769 } else if (IS_IVYBRIDGE(dev_priv)) {
17770 /* FIXME: detect B0+ stepping and use auto training */
17771 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17774 if (INTEL_GEN(dev_priv) >= 9)
17775 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17777 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17781 void intel_modeset_init_hw(struct drm_i915_private *i915)
17783 struct intel_cdclk_state *cdclk_state =
17784 to_intel_cdclk_state(i915->cdclk.obj.state);
17785 struct intel_dbuf_state *dbuf_state =
17786 to_intel_dbuf_state(i915->dbuf.obj.state);
17788 intel_update_cdclk(i915);
17789 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17790 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17792 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17795 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17797 struct drm_plane *plane;
17798 struct intel_crtc *crtc;
17800 for_each_intel_crtc(state->dev, crtc) {
17801 struct intel_crtc_state *crtc_state;
17803 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17804 if (IS_ERR(crtc_state))
17805 return PTR_ERR(crtc_state);
17807 if (crtc_state->hw.active) {
17809 * Preserve the inherited flag to avoid
17810 * taking the full modeset path.
17812 crtc_state->inherited = true;
17816 drm_for_each_plane(plane, state->dev) {
17817 struct drm_plane_state *plane_state;
17819 plane_state = drm_atomic_get_plane_state(state, plane);
17820 if (IS_ERR(plane_state))
17821 return PTR_ERR(plane_state);
17828 * Calculate what we think the watermarks should be for the state we've read
17829 * out of the hardware and then immediately program those watermarks so that
17830 * we ensure the hardware settings match our internal state.
17832 * We can calculate what we think WM's should be by creating a duplicate of the
17833 * current state (which was constructed during hardware readout) and running it
17834 * through the atomic check code to calculate new watermark values in the
17837 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17839 struct drm_atomic_state *state;
17840 struct intel_atomic_state *intel_state;
17841 struct intel_crtc *crtc;
17842 struct intel_crtc_state *crtc_state;
17843 struct drm_modeset_acquire_ctx ctx;
17847 /* Only supported on platforms that use atomic watermark design */
17848 if (!dev_priv->display.optimize_watermarks)
17851 state = drm_atomic_state_alloc(&dev_priv->drm);
17852 if (drm_WARN_ON(&dev_priv->drm, !state))
17855 intel_state = to_intel_atomic_state(state);
17857 drm_modeset_acquire_init(&ctx, 0);
17860 state->acquire_ctx = &ctx;
17863 * Hardware readout is the only time we don't want to calculate
17864 * intermediate watermarks (since we don't trust the current
17867 if (!HAS_GMCH(dev_priv))
17868 intel_state->skip_intermediate_wm = true;
17870 ret = sanitize_watermarks_add_affected(state);
17874 ret = intel_atomic_check(&dev_priv->drm, state);
17878 /* Write calculated watermark values back */
17879 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17880 crtc_state->wm.need_postvbl_update = true;
17881 dev_priv->display.optimize_watermarks(intel_state, crtc);
17883 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17887 if (ret == -EDEADLK) {
17888 drm_atomic_state_clear(state);
17889 drm_modeset_backoff(&ctx);
17894 * If we fail here, it means that the hardware appears to be
17895 * programmed in a way that shouldn't be possible, given our
17896 * understanding of watermark requirements. This might mean a
17897 * mistake in the hardware readout code or a mistake in the
17898 * watermark calculations for a given platform. Raise a WARN
17899 * so that this is noticeable.
17901 * If this actually happens, we'll have to just leave the
17902 * BIOS-programmed watermarks untouched and hope for the best.
17904 drm_WARN(&dev_priv->drm, ret,
17905 "Could not determine valid watermarks for inherited state\n");
17907 drm_atomic_state_put(state);
17909 drm_modeset_drop_locks(&ctx);
17910 drm_modeset_acquire_fini(&ctx);
17913 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17915 if (IS_GEN(dev_priv, 5)) {
17917 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17919 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17920 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17921 dev_priv->fdi_pll_freq = 270000;
17926 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17929 static int intel_initial_commit(struct drm_device *dev)
17931 struct drm_atomic_state *state = NULL;
17932 struct drm_modeset_acquire_ctx ctx;
17933 struct intel_crtc *crtc;
17936 state = drm_atomic_state_alloc(dev);
17940 drm_modeset_acquire_init(&ctx, 0);
17943 state->acquire_ctx = &ctx;
17945 for_each_intel_crtc(dev, crtc) {
17946 struct intel_crtc_state *crtc_state =
17947 intel_atomic_get_crtc_state(state, crtc);
17949 if (IS_ERR(crtc_state)) {
17950 ret = PTR_ERR(crtc_state);
17954 if (crtc_state->hw.active) {
17955 struct intel_encoder *encoder;
17958 * We've not yet detected sink capabilities
17959 * (audio,infoframes,etc.) and thus we don't want to
17960 * force a full state recomputation yet. We want that to
17961 * happen only for the first real commit from userspace.
17962 * So preserve the inherited flag for the time being.
17964 crtc_state->inherited = true;
17966 ret = drm_atomic_add_affected_planes(state, &crtc->base);
17971 * FIXME hack to force a LUT update to avoid the
17972 * plane update forcing the pipe gamma on without
17973 * having a proper LUT loaded. Remove once we
17974 * have readout for pipe gamma enable.
17976 crtc_state->uapi.color_mgmt_changed = true;
17978 for_each_intel_encoder_mask(dev, encoder,
17979 crtc_state->uapi.encoder_mask) {
17980 if (encoder->initial_fastset_check &&
17981 !encoder->initial_fastset_check(encoder, crtc_state)) {
17982 ret = drm_atomic_add_affected_connectors(state,
17991 ret = drm_atomic_commit(state);
17994 if (ret == -EDEADLK) {
17995 drm_atomic_state_clear(state);
17996 drm_modeset_backoff(&ctx);
18000 drm_atomic_state_put(state);
18002 drm_modeset_drop_locks(&ctx);
18003 drm_modeset_acquire_fini(&ctx);
18008 static void intel_mode_config_init(struct drm_i915_private *i915)
18010 struct drm_mode_config *mode_config = &i915->drm.mode_config;
18012 drm_mode_config_init(&i915->drm);
18013 INIT_LIST_HEAD(&i915->global_obj_list);
18015 mode_config->min_width = 0;
18016 mode_config->min_height = 0;
18018 mode_config->preferred_depth = 24;
18019 mode_config->prefer_shadow = 1;
18021 mode_config->allow_fb_modifiers = true;
18023 mode_config->funcs = &intel_mode_funcs;
18025 if (INTEL_GEN(i915) >= 9)
18026 mode_config->async_page_flip = true;
18029 * Maximum framebuffer dimensions, chosen to match
18030 * the maximum render engine surface size on gen4+.
18032 if (INTEL_GEN(i915) >= 7) {
18033 mode_config->max_width = 16384;
18034 mode_config->max_height = 16384;
18035 } else if (INTEL_GEN(i915) >= 4) {
18036 mode_config->max_width = 8192;
18037 mode_config->max_height = 8192;
18038 } else if (IS_GEN(i915, 3)) {
18039 mode_config->max_width = 4096;
18040 mode_config->max_height = 4096;
18042 mode_config->max_width = 2048;
18043 mode_config->max_height = 2048;
18046 if (IS_I845G(i915) || IS_I865G(i915)) {
18047 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
18048 mode_config->cursor_height = 1023;
18049 } else if (IS_I830(i915) || IS_I85X(i915) ||
18050 IS_I915G(i915) || IS_I915GM(i915)) {
18051 mode_config->cursor_width = 64;
18052 mode_config->cursor_height = 64;
18054 mode_config->cursor_width = 256;
18055 mode_config->cursor_height = 256;
18059 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
18061 intel_atomic_global_obj_cleanup(i915);
18062 drm_mode_config_cleanup(&i915->drm);
18065 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
18067 if (plane_config->fb) {
18068 struct drm_framebuffer *fb = &plane_config->fb->base;
18070 /* We may only have the stub and not a full framebuffer */
18071 if (drm_framebuffer_read_refcount(fb))
18072 drm_framebuffer_put(fb);
18077 if (plane_config->vma)
18078 i915_vma_put(plane_config->vma);
18081 /* part #1: call before irq install */
18082 int intel_modeset_init_noirq(struct drm_i915_private *i915)
18086 if (i915_inject_probe_failure(i915))
18089 if (HAS_DISPLAY(i915)) {
18090 ret = drm_vblank_init(&i915->drm,
18091 INTEL_NUM_PIPES(i915));
18096 intel_bios_init(i915);
18098 ret = intel_vga_register(i915);
18102 /* FIXME: completely on the wrong abstraction layer */
18103 intel_power_domains_init_hw(i915, false);
18105 intel_csr_ucode_init(i915);
18107 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
18108 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
18109 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
18111 intel_mode_config_init(i915);
18113 ret = intel_cdclk_init(i915);
18115 goto cleanup_vga_client_pw_domain_csr;
18117 ret = intel_dbuf_init(i915);
18119 goto cleanup_vga_client_pw_domain_csr;
18121 ret = intel_bw_init(i915);
18123 goto cleanup_vga_client_pw_domain_csr;
18125 init_llist_head(&i915->atomic_helper.free_list);
18126 INIT_WORK(&i915->atomic_helper.free_work,
18127 intel_atomic_helper_free_state_worker);
18129 intel_init_quirks(i915);
18131 intel_fbc_init(i915);
18135 cleanup_vga_client_pw_domain_csr:
18136 intel_csr_ucode_fini(i915);
18137 intel_power_domains_driver_remove(i915);
18138 intel_vga_unregister(i915);
18140 intel_bios_driver_remove(i915);
18145 /* part #2: call after irq install, but before gem init */
18146 int intel_modeset_init_nogem(struct drm_i915_private *i915)
18148 struct drm_device *dev = &i915->drm;
18150 struct intel_crtc *crtc;
18153 intel_init_pm(i915);
18155 intel_panel_sanitize_ssc(i915);
18157 intel_gmbus_setup(i915);
18159 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
18160 INTEL_NUM_PIPES(i915),
18161 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
18163 if (HAS_DISPLAY(i915)) {
18164 for_each_pipe(i915, pipe) {
18165 ret = intel_crtc_init(i915, pipe);
18167 intel_mode_config_cleanup(i915);
18173 intel_plane_possible_crtcs_init(i915);
18174 intel_shared_dpll_init(dev);
18175 intel_update_fdi_pll_freq(i915);
18177 intel_update_czclk(i915);
18178 intel_modeset_init_hw(i915);
18180 intel_hdcp_component_init(i915);
18182 if (i915->max_cdclk_freq == 0)
18183 intel_update_max_cdclk(i915);
18186 * If the platform has HTI, we need to find out whether it has reserved
18187 * any display resources before we create our display outputs.
18189 if (INTEL_INFO(i915)->display.has_hti)
18190 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
18192 /* Just disable it once at startup */
18193 intel_vga_disable(i915);
18194 intel_setup_outputs(i915);
18196 drm_modeset_lock_all(dev);
18197 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
18198 drm_modeset_unlock_all(dev);
18200 for_each_intel_crtc(dev, crtc) {
18201 struct intel_initial_plane_config plane_config = {};
18207 * Note that reserving the BIOS fb up front prevents us
18208 * from stuffing other stolen allocations like the ring
18209 * on top. This prevents some ugliness at boot time, and
18210 * can even allow for smooth boot transitions if the BIOS
18211 * fb is large enough for the active pipe configuration.
18213 i915->display.get_initial_plane_config(crtc, &plane_config);
18216 * If the fb is shared between multiple heads, we'll
18217 * just get the first one.
18219 intel_find_initial_plane_obj(crtc, &plane_config);
18221 plane_config_fini(&plane_config);
18225 * Make sure hardware watermarks really match the state we read out.
18226 * Note that we need to do this after reconstructing the BIOS fb's
18227 * since the watermark calculation done here will use pstate->fb.
18229 if (!HAS_GMCH(i915))
18230 sanitize_watermarks(i915);
18233 * Force all active planes to recompute their states. So that on
18234 * mode_setcrtc after probe, all the intel_plane_state variables
18235 * are already calculated and there is no assert_plane warnings
18238 ret = intel_initial_commit(dev);
18240 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18245 /* part #3: call after gem init */
18246 int intel_modeset_init(struct drm_i915_private *i915)
18250 intel_overlay_setup(i915);
18252 if (!HAS_DISPLAY(i915))
18255 ret = intel_fbdev_init(&i915->drm);
18259 /* Only enable hotplug handling once the fbdev is fully set up. */
18260 intel_hpd_init(i915);
18261 intel_hpd_poll_disable(i915);
18263 intel_init_ipc(i915);
18265 intel_psr_set_force_mode_changed(i915->psr.dp);
18270 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18272 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18273 /* 640x480@60Hz, ~25175 kHz */
18274 struct dpll clock = {
18284 drm_WARN_ON(&dev_priv->drm,
18285 i9xx_calc_dpll_params(48000, &clock) != 25154);
18287 drm_dbg_kms(&dev_priv->drm,
18288 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18289 pipe_name(pipe), clock.vco, clock.dot);
18291 fp = i9xx_dpll_compute_fp(&clock);
18292 dpll = DPLL_DVO_2X_MODE |
18293 DPLL_VGA_MODE_DIS |
18294 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18295 PLL_P2_DIVIDE_BY_4 |
18296 PLL_REF_INPUT_DREFCLK |
18299 intel_de_write(dev_priv, FP0(pipe), fp);
18300 intel_de_write(dev_priv, FP1(pipe), fp);
18302 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18303 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18304 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18305 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18306 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18307 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18308 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18311 * Apparently we need to have VGA mode enabled prior to changing
18312 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18313 * dividers, even though the register value does change.
18315 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18316 intel_de_write(dev_priv, DPLL(pipe), dpll);
18318 /* Wait for the clocks to stabilize. */
18319 intel_de_posting_read(dev_priv, DPLL(pipe));
18322 /* The pixel multiplier can only be updated once the
18323 * DPLL is enabled and the clocks are stable.
18325 * So write it again.
18327 intel_de_write(dev_priv, DPLL(pipe), dpll);
18329 /* We do this three times for luck */
18330 for (i = 0; i < 3 ; i++) {
18331 intel_de_write(dev_priv, DPLL(pipe), dpll);
18332 intel_de_posting_read(dev_priv, DPLL(pipe));
18333 udelay(150); /* wait for warmup */
18336 intel_de_write(dev_priv, PIPECONF(pipe),
18337 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18338 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18340 intel_wait_for_pipe_scanline_moving(crtc);
18343 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18345 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18347 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18350 drm_WARN_ON(&dev_priv->drm,
18351 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18352 DISPLAY_PLANE_ENABLE);
18353 drm_WARN_ON(&dev_priv->drm,
18354 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18355 DISPLAY_PLANE_ENABLE);
18356 drm_WARN_ON(&dev_priv->drm,
18357 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18358 DISPLAY_PLANE_ENABLE);
18359 drm_WARN_ON(&dev_priv->drm,
18360 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18361 drm_WARN_ON(&dev_priv->drm,
18362 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18364 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18365 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18367 intel_wait_for_pipe_scanline_stopped(crtc);
18369 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18370 intel_de_posting_read(dev_priv, DPLL(pipe));
18374 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18376 struct intel_crtc *crtc;
18378 if (INTEL_GEN(dev_priv) >= 4)
18381 for_each_intel_crtc(&dev_priv->drm, crtc) {
18382 struct intel_plane *plane =
18383 to_intel_plane(crtc->base.primary);
18384 struct intel_crtc *plane_crtc;
18387 if (!plane->get_hw_state(plane, &pipe))
18390 if (pipe == crtc->pipe)
18393 drm_dbg_kms(&dev_priv->drm,
18394 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18395 plane->base.base.id, plane->base.name);
18397 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18398 intel_plane_disable_noatomic(plane_crtc, plane);
18402 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18404 struct drm_device *dev = crtc->base.dev;
18405 struct intel_encoder *encoder;
18407 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18413 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18415 struct drm_device *dev = encoder->base.dev;
18416 struct intel_connector *connector;
18418 for_each_connector_on_encoder(dev, &encoder->base, connector)
18424 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18425 enum pipe pch_transcoder)
18427 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18428 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18431 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18435 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18437 if (INTEL_GEN(dev_priv) >= 9 ||
18438 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18439 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18442 if (transcoder_is_dsi(cpu_transcoder))
18445 val = intel_de_read(dev_priv, reg);
18446 val &= ~HSW_FRAME_START_DELAY_MASK;
18447 val |= HSW_FRAME_START_DELAY(0);
18448 intel_de_write(dev_priv, reg, val);
18450 i915_reg_t reg = PIPECONF(cpu_transcoder);
18453 val = intel_de_read(dev_priv, reg);
18454 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18455 val |= PIPECONF_FRAME_START_DELAY(0);
18456 intel_de_write(dev_priv, reg, val);
18459 if (!crtc_state->has_pch_encoder)
18462 if (HAS_PCH_IBX(dev_priv)) {
18463 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18466 val = intel_de_read(dev_priv, reg);
18467 val &= ~TRANS_FRAME_START_DELAY_MASK;
18468 val |= TRANS_FRAME_START_DELAY(0);
18469 intel_de_write(dev_priv, reg, val);
18471 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18472 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18475 val = intel_de_read(dev_priv, reg);
18476 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18477 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18478 intel_de_write(dev_priv, reg, val);
18482 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18483 struct drm_modeset_acquire_ctx *ctx)
18485 struct drm_device *dev = crtc->base.dev;
18486 struct drm_i915_private *dev_priv = to_i915(dev);
18487 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18489 if (crtc_state->hw.active) {
18490 struct intel_plane *plane;
18492 /* Clear any frame start delays used for debugging left by the BIOS */
18493 intel_sanitize_frame_start_delay(crtc_state);
18495 /* Disable everything but the primary plane */
18496 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18497 const struct intel_plane_state *plane_state =
18498 to_intel_plane_state(plane->base.state);
18500 if (plane_state->uapi.visible &&
18501 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18502 intel_plane_disable_noatomic(crtc, plane);
18506 * Disable any background color set by the BIOS, but enable the
18507 * gamma and CSC to match how we program our planes.
18509 if (INTEL_GEN(dev_priv) >= 9)
18510 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18511 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18514 /* Adjust the state of the output pipe according to whether we
18515 * have active connectors/encoders. */
18516 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18517 intel_crtc_disable_noatomic(crtc, ctx);
18519 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18521 * We start out with underrun reporting disabled to avoid races.
18522 * For correct bookkeeping mark this on active crtcs.
18524 * Also on gmch platforms we dont have any hardware bits to
18525 * disable the underrun reporting. Which means we need to start
18526 * out with underrun reporting disabled also on inactive pipes,
18527 * since otherwise we'll complain about the garbage we read when
18528 * e.g. coming up after runtime pm.
18530 * No protection against concurrent access is required - at
18531 * worst a fifo underrun happens which also sets this to false.
18533 crtc->cpu_fifo_underrun_disabled = true;
18535 * We track the PCH trancoder underrun reporting state
18536 * within the crtc. With crtc for pipe A housing the underrun
18537 * reporting state for PCH transcoder A, crtc for pipe B housing
18538 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18539 * and marking underrun reporting as disabled for the non-existing
18540 * PCH transcoders B and C would prevent enabling the south
18541 * error interrupt (see cpt_can_enable_serr_int()).
18543 if (has_pch_trancoder(dev_priv, crtc->pipe))
18544 crtc->pch_fifo_underrun_disabled = true;
18548 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18550 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18553 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18554 * the hardware when a high res displays plugged in. DPLL P
18555 * divider is zero, and the pipe timings are bonkers. We'll
18556 * try to disable everything in that case.
18558 * FIXME would be nice to be able to sanitize this state
18559 * without several WARNs, but for now let's take the easy
18562 return IS_GEN(dev_priv, 6) &&
18563 crtc_state->hw.active &&
18564 crtc_state->shared_dpll &&
18565 crtc_state->port_clock == 0;
18568 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18571 struct intel_connector *connector;
18572 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18573 struct intel_crtc_state *crtc_state = crtc ?
18574 to_intel_crtc_state(crtc->base.state) : NULL;
18576 /* We need to check both for a crtc link (meaning that the
18577 * encoder is active and trying to read from a pipe) and the
18578 * pipe itself being active. */
18579 bool has_active_crtc = crtc_state &&
18580 crtc_state->hw.active;
18582 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18583 drm_dbg_kms(&dev_priv->drm,
18584 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18585 pipe_name(crtc->pipe));
18586 has_active_crtc = false;
18589 connector = intel_encoder_find_connector(encoder);
18590 if (connector && !has_active_crtc) {
18591 drm_dbg_kms(&dev_priv->drm,
18592 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18593 encoder->base.base.id,
18594 encoder->base.name);
18596 /* Connector is active, but has no active pipe. This is
18597 * fallout from our resume register restoring. Disable
18598 * the encoder manually again. */
18600 struct drm_encoder *best_encoder;
18602 drm_dbg_kms(&dev_priv->drm,
18603 "[ENCODER:%d:%s] manually disabled\n",
18604 encoder->base.base.id,
18605 encoder->base.name);
18607 /* avoid oopsing in case the hooks consult best_encoder */
18608 best_encoder = connector->base.state->best_encoder;
18609 connector->base.state->best_encoder = &encoder->base;
18611 /* FIXME NULL atomic state passed! */
18612 if (encoder->disable)
18613 encoder->disable(NULL, encoder, crtc_state,
18614 connector->base.state);
18615 if (encoder->post_disable)
18616 encoder->post_disable(NULL, encoder, crtc_state,
18617 connector->base.state);
18619 connector->base.state->best_encoder = best_encoder;
18621 encoder->base.crtc = NULL;
18623 /* Inconsistent output/port/pipe state happens presumably due to
18624 * a bug in one of the get_hw_state functions. Or someplace else
18625 * in our code, like the register restore mess on resume. Clamp
18626 * things to off as a safer default. */
18628 connector->base.dpms = DRM_MODE_DPMS_OFF;
18629 connector->base.encoder = NULL;
18632 /* notify opregion of the sanitized encoder state */
18633 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18635 if (INTEL_GEN(dev_priv) >= 11)
18636 icl_sanitize_encoder_pll_mapping(encoder);
18639 /* FIXME read out full plane state for all planes */
18640 static void readout_plane_state(struct drm_i915_private *dev_priv)
18642 struct intel_plane *plane;
18643 struct intel_crtc *crtc;
18645 for_each_intel_plane(&dev_priv->drm, plane) {
18646 struct intel_plane_state *plane_state =
18647 to_intel_plane_state(plane->base.state);
18648 struct intel_crtc_state *crtc_state;
18649 enum pipe pipe = PIPE_A;
18652 visible = plane->get_hw_state(plane, &pipe);
18654 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18655 crtc_state = to_intel_crtc_state(crtc->base.state);
18657 intel_set_plane_visible(crtc_state, plane_state, visible);
18659 drm_dbg_kms(&dev_priv->drm,
18660 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18661 plane->base.base.id, plane->base.name,
18662 enableddisabled(visible), pipe_name(pipe));
18665 for_each_intel_crtc(&dev_priv->drm, crtc) {
18666 struct intel_crtc_state *crtc_state =
18667 to_intel_crtc_state(crtc->base.state);
18669 fixup_active_planes(crtc_state);
18673 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18675 struct drm_i915_private *dev_priv = to_i915(dev);
18676 struct intel_cdclk_state *cdclk_state =
18677 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18678 struct intel_dbuf_state *dbuf_state =
18679 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18681 struct intel_crtc *crtc;
18682 struct intel_encoder *encoder;
18683 struct intel_connector *connector;
18684 struct drm_connector_list_iter conn_iter;
18685 u8 active_pipes = 0;
18687 for_each_intel_crtc(dev, crtc) {
18688 struct intel_crtc_state *crtc_state =
18689 to_intel_crtc_state(crtc->base.state);
18691 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18692 intel_crtc_free_hw_state(crtc_state);
18693 intel_crtc_state_reset(crtc_state, crtc);
18695 crtc_state->hw.active = crtc_state->hw.enable =
18696 dev_priv->display.get_pipe_config(crtc, crtc_state);
18698 crtc->base.enabled = crtc_state->hw.enable;
18699 crtc->active = crtc_state->hw.active;
18701 if (crtc_state->hw.active)
18702 active_pipes |= BIT(crtc->pipe);
18704 drm_dbg_kms(&dev_priv->drm,
18705 "[CRTC:%d:%s] hw state readout: %s\n",
18706 crtc->base.base.id, crtc->base.name,
18707 enableddisabled(crtc_state->hw.active));
18710 dev_priv->active_pipes = cdclk_state->active_pipes =
18711 dbuf_state->active_pipes = active_pipes;
18713 readout_plane_state(dev_priv);
18715 intel_dpll_readout_hw_state(dev_priv);
18717 for_each_intel_encoder(dev, encoder) {
18720 if (encoder->get_hw_state(encoder, &pipe)) {
18721 struct intel_crtc_state *crtc_state;
18723 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18724 crtc_state = to_intel_crtc_state(crtc->base.state);
18726 encoder->base.crtc = &crtc->base;
18727 encoder->get_config(encoder, crtc_state);
18728 if (encoder->sync_state)
18729 encoder->sync_state(encoder, crtc_state);
18731 encoder->base.crtc = NULL;
18734 drm_dbg_kms(&dev_priv->drm,
18735 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18736 encoder->base.base.id, encoder->base.name,
18737 enableddisabled(encoder->base.crtc),
18741 drm_connector_list_iter_begin(dev, &conn_iter);
18742 for_each_intel_connector_iter(connector, &conn_iter) {
18743 if (connector->get_hw_state(connector)) {
18744 struct intel_crtc_state *crtc_state;
18745 struct intel_crtc *crtc;
18747 connector->base.dpms = DRM_MODE_DPMS_ON;
18749 encoder = intel_attached_encoder(connector);
18750 connector->base.encoder = &encoder->base;
18752 crtc = to_intel_crtc(encoder->base.crtc);
18753 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18755 if (crtc_state && crtc_state->hw.active) {
18757 * This has to be done during hardware readout
18758 * because anything calling .crtc_disable may
18759 * rely on the connector_mask being accurate.
18761 crtc_state->uapi.connector_mask |=
18762 drm_connector_mask(&connector->base);
18763 crtc_state->uapi.encoder_mask |=
18764 drm_encoder_mask(&encoder->base);
18767 connector->base.dpms = DRM_MODE_DPMS_OFF;
18768 connector->base.encoder = NULL;
18770 drm_dbg_kms(&dev_priv->drm,
18771 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18772 connector->base.base.id, connector->base.name,
18773 enableddisabled(connector->base.encoder));
18775 drm_connector_list_iter_end(&conn_iter);
18777 for_each_intel_crtc(dev, crtc) {
18778 struct intel_bw_state *bw_state =
18779 to_intel_bw_state(dev_priv->bw_obj.state);
18780 struct intel_crtc_state *crtc_state =
18781 to_intel_crtc_state(crtc->base.state);
18782 struct intel_plane *plane;
18785 if (crtc_state->hw.active) {
18786 struct drm_display_mode *mode = &crtc_state->hw.mode;
18788 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18791 *mode = crtc_state->hw.adjusted_mode;
18792 mode->hdisplay = crtc_state->pipe_src_w;
18793 mode->vdisplay = crtc_state->pipe_src_h;
18796 * The initial mode needs to be set in order to keep
18797 * the atomic core happy. It wants a valid mode if the
18798 * crtc's enabled, so we do the above call.
18800 * But we don't set all the derived state fully, hence
18801 * set a flag to indicate that a full recalculation is
18802 * needed on the next commit.
18804 crtc_state->inherited = true;
18806 intel_crtc_compute_pixel_rate(crtc_state);
18808 intel_crtc_update_active_timings(crtc_state);
18810 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18813 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18814 const struct intel_plane_state *plane_state =
18815 to_intel_plane_state(plane->base.state);
18818 * FIXME don't have the fb yet, so can't
18819 * use intel_plane_data_rate() :(
18821 if (plane_state->uapi.visible)
18822 crtc_state->data_rate[plane->id] =
18823 4 * crtc_state->pixel_rate;
18825 * FIXME don't have the fb yet, so can't
18826 * use plane->min_cdclk() :(
18828 if (plane_state->uapi.visible && plane->min_cdclk) {
18829 if (crtc_state->double_wide ||
18830 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18831 crtc_state->min_cdclk[plane->id] =
18832 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18834 crtc_state->min_cdclk[plane->id] =
18835 crtc_state->pixel_rate;
18837 drm_dbg_kms(&dev_priv->drm,
18838 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18839 plane->base.base.id, plane->base.name,
18840 crtc_state->min_cdclk[plane->id]);
18843 if (crtc_state->hw.active) {
18844 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18845 if (drm_WARN_ON(dev, min_cdclk < 0))
18849 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18850 cdclk_state->min_voltage_level[crtc->pipe] =
18851 crtc_state->min_voltage_level;
18853 intel_bw_crtc_update(bw_state, crtc_state);
18855 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18860 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18862 struct intel_encoder *encoder;
18864 for_each_intel_encoder(&dev_priv->drm, encoder) {
18865 struct intel_crtc_state *crtc_state;
18867 if (!encoder->get_power_domains)
18871 * MST-primary and inactive encoders don't have a crtc state
18872 * and neither of these require any power domain references.
18874 if (!encoder->base.crtc)
18877 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18878 encoder->get_power_domains(encoder, crtc_state);
18882 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18885 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18886 * Also known as Wa_14010480278.
18888 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18889 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18890 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18892 if (IS_HASWELL(dev_priv)) {
18894 * WaRsPkgCStateDisplayPMReq:hsw
18895 * System hang if this isn't done before disabling all planes!
18897 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18898 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18901 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
18902 /* Display WA #1142:kbl,cfl,cml */
18903 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
18904 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
18905 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
18906 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
18907 KBL_ARB_FILL_SPARE_14);
18911 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18912 enum port port, i915_reg_t hdmi_reg)
18914 u32 val = intel_de_read(dev_priv, hdmi_reg);
18916 if (val & SDVO_ENABLE ||
18917 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18920 drm_dbg_kms(&dev_priv->drm,
18921 "Sanitizing transcoder select for HDMI %c\n",
18924 val &= ~SDVO_PIPE_SEL_MASK;
18925 val |= SDVO_PIPE_SEL(PIPE_A);
18927 intel_de_write(dev_priv, hdmi_reg, val);
18930 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18931 enum port port, i915_reg_t dp_reg)
18933 u32 val = intel_de_read(dev_priv, dp_reg);
18935 if (val & DP_PORT_EN ||
18936 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18939 drm_dbg_kms(&dev_priv->drm,
18940 "Sanitizing transcoder select for DP %c\n",
18943 val &= ~DP_PIPE_SEL_MASK;
18944 val |= DP_PIPE_SEL(PIPE_A);
18946 intel_de_write(dev_priv, dp_reg, val);
18949 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18952 * The BIOS may select transcoder B on some of the PCH
18953 * ports even it doesn't enable the port. This would trip
18954 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18955 * Sanitize the transcoder select bits to prevent that. We
18956 * assume that the BIOS never actually enabled the port,
18957 * because if it did we'd actually have to toggle the port
18958 * on and back off to make the transcoder A select stick
18959 * (see. intel_dp_link_down(), intel_disable_hdmi(),
18960 * intel_disable_sdvo()).
18962 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18963 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18964 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18966 /* PCH SDVOB multiplex with HDMIB */
18967 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18968 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18969 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18972 /* Scan out the current hw modeset state,
18973 * and sanitizes it to the current state
18976 intel_modeset_setup_hw_state(struct drm_device *dev,
18977 struct drm_modeset_acquire_ctx *ctx)
18979 struct drm_i915_private *dev_priv = to_i915(dev);
18980 struct intel_encoder *encoder;
18981 struct intel_crtc *crtc;
18982 intel_wakeref_t wakeref;
18984 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18986 intel_early_display_was(dev_priv);
18987 intel_modeset_readout_hw_state(dev);
18989 /* HW state is read out, now we need to sanitize this mess. */
18991 /* Sanitize the TypeC port mode upfront, encoders depend on this */
18992 for_each_intel_encoder(dev, encoder) {
18993 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18995 /* We need to sanitize only the MST primary port. */
18996 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18997 intel_phy_is_tc(dev_priv, phy))
18998 intel_tc_port_sanitize(enc_to_dig_port(encoder));
19001 get_encoder_power_domains(dev_priv);
19003 if (HAS_PCH_IBX(dev_priv))
19004 ibx_sanitize_pch_ports(dev_priv);
19007 * intel_sanitize_plane_mapping() may need to do vblank
19008 * waits, so we need vblank interrupts restored beforehand.
19010 for_each_intel_crtc(&dev_priv->drm, crtc) {
19011 struct intel_crtc_state *crtc_state =
19012 to_intel_crtc_state(crtc->base.state);
19014 drm_crtc_vblank_reset(&crtc->base);
19016 if (crtc_state->hw.active)
19017 intel_crtc_vblank_on(crtc_state);
19020 intel_sanitize_plane_mapping(dev_priv);
19022 for_each_intel_encoder(dev, encoder)
19023 intel_sanitize_encoder(encoder);
19025 for_each_intel_crtc(&dev_priv->drm, crtc) {
19026 struct intel_crtc_state *crtc_state =
19027 to_intel_crtc_state(crtc->base.state);
19029 intel_sanitize_crtc(crtc, ctx);
19030 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
19033 intel_modeset_update_connector_atomic_state(dev);
19035 intel_dpll_sanitize_state(dev_priv);
19037 if (IS_G4X(dev_priv)) {
19038 g4x_wm_get_hw_state(dev_priv);
19039 g4x_wm_sanitize(dev_priv);
19040 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
19041 vlv_wm_get_hw_state(dev_priv);
19042 vlv_wm_sanitize(dev_priv);
19043 } else if (INTEL_GEN(dev_priv) >= 9) {
19044 skl_wm_get_hw_state(dev_priv);
19045 } else if (HAS_PCH_SPLIT(dev_priv)) {
19046 ilk_wm_get_hw_state(dev_priv);
19049 for_each_intel_crtc(dev, crtc) {
19050 struct intel_crtc_state *crtc_state =
19051 to_intel_crtc_state(crtc->base.state);
19054 put_domains = modeset_get_crtc_power_domains(crtc_state);
19055 if (drm_WARN_ON(dev, put_domains))
19056 modeset_put_power_domains(dev_priv, put_domains);
19059 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
19062 void intel_display_resume(struct drm_device *dev)
19064 struct drm_i915_private *dev_priv = to_i915(dev);
19065 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
19066 struct drm_modeset_acquire_ctx ctx;
19069 dev_priv->modeset_restore_state = NULL;
19071 state->acquire_ctx = &ctx;
19073 drm_modeset_acquire_init(&ctx, 0);
19076 ret = drm_modeset_lock_all_ctx(dev, &ctx);
19077 if (ret != -EDEADLK)
19080 drm_modeset_backoff(&ctx);
19084 ret = __intel_display_resume(dev, state, &ctx);
19086 intel_enable_ipc(dev_priv);
19087 drm_modeset_drop_locks(&ctx);
19088 drm_modeset_acquire_fini(&ctx);
19091 drm_err(&dev_priv->drm,
19092 "Restoring old state failed with %i\n", ret);
19094 drm_atomic_state_put(state);
19097 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
19099 struct intel_connector *connector;
19100 struct drm_connector_list_iter conn_iter;
19102 /* Kill all the work that may have been queued by hpd. */
19103 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
19104 for_each_intel_connector_iter(connector, &conn_iter) {
19105 if (connector->modeset_retry_work.func)
19106 cancel_work_sync(&connector->modeset_retry_work);
19107 if (connector->hdcp.shim) {
19108 cancel_delayed_work_sync(&connector->hdcp.check_work);
19109 cancel_work_sync(&connector->hdcp.prop_work);
19112 drm_connector_list_iter_end(&conn_iter);
19115 /* part #1: call before irq uninstall */
19116 void intel_modeset_driver_remove(struct drm_i915_private *i915)
19118 flush_workqueue(i915->flip_wq);
19119 flush_workqueue(i915->modeset_wq);
19121 flush_work(&i915->atomic_helper.free_work);
19122 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
19125 /* part #2: call after irq uninstall */
19126 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
19129 * Due to the hpd irq storm handling the hotplug work can re-arm the
19130 * poll handlers. Hence disable polling after hpd handling is shut down.
19132 intel_hpd_poll_fini(i915);
19135 * MST topology needs to be suspended so we don't have any calls to
19136 * fbdev after it's finalized. MST will be destroyed later as part of
19137 * drm_mode_config_cleanup()
19139 intel_dp_mst_suspend(i915);
19141 /* poll work can call into fbdev, hence clean that up afterwards */
19142 intel_fbdev_fini(i915);
19144 intel_unregister_dsm_handler();
19146 intel_fbc_global_disable(i915);
19148 /* flush any delayed tasks or pending work */
19149 flush_scheduled_work();
19151 intel_hdcp_component_fini(i915);
19153 intel_mode_config_cleanup(i915);
19155 intel_overlay_cleanup(i915);
19157 intel_gmbus_teardown(i915);
19159 destroy_workqueue(i915->flip_wq);
19160 destroy_workqueue(i915->modeset_wq);
19162 intel_fbc_cleanup_cfb(i915);
19165 /* part #3: call after gem init */
19166 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
19168 intel_csr_ucode_fini(i915);
19170 intel_power_domains_driver_remove(i915);
19172 intel_vga_unregister(i915);
19174 intel_bios_driver_remove(i915);
19177 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
19179 struct intel_display_error_state {
19181 u32 power_well_driver;
19183 struct intel_cursor_error_state {
19188 } cursor[I915_MAX_PIPES];
19190 struct intel_pipe_error_state {
19191 bool power_domain_on;
19194 } pipe[I915_MAX_PIPES];
19196 struct intel_plane_error_state {
19204 } plane[I915_MAX_PIPES];
19206 struct intel_transcoder_error_state {
19208 bool power_domain_on;
19209 enum transcoder cpu_transcoder;
19222 struct intel_display_error_state *
19223 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19225 struct intel_display_error_state *error;
19226 int transcoders[] = {
19235 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19237 if (!HAS_DISPLAY(dev_priv))
19240 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19244 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19245 error->power_well_driver = intel_de_read(dev_priv,
19246 HSW_PWR_WELL_CTL2);
19248 for_each_pipe(dev_priv, i) {
19249 error->pipe[i].power_domain_on =
19250 __intel_display_power_is_enabled(dev_priv,
19251 POWER_DOMAIN_PIPE(i));
19252 if (!error->pipe[i].power_domain_on)
19255 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19256 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19257 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19259 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19260 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19261 if (INTEL_GEN(dev_priv) <= 3) {
19262 error->plane[i].size = intel_de_read(dev_priv,
19264 error->plane[i].pos = intel_de_read(dev_priv,
19267 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19268 error->plane[i].addr = intel_de_read(dev_priv,
19270 if (INTEL_GEN(dev_priv) >= 4) {
19271 error->plane[i].surface = intel_de_read(dev_priv,
19273 error->plane[i].tile_offset = intel_de_read(dev_priv,
19277 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19279 if (HAS_GMCH(dev_priv))
19280 error->pipe[i].stat = intel_de_read(dev_priv,
19284 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19285 enum transcoder cpu_transcoder = transcoders[i];
19287 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19290 error->transcoder[i].available = true;
19291 error->transcoder[i].power_domain_on =
19292 __intel_display_power_is_enabled(dev_priv,
19293 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19294 if (!error->transcoder[i].power_domain_on)
19297 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19299 error->transcoder[i].conf = intel_de_read(dev_priv,
19300 PIPECONF(cpu_transcoder));
19301 error->transcoder[i].htotal = intel_de_read(dev_priv,
19302 HTOTAL(cpu_transcoder));
19303 error->transcoder[i].hblank = intel_de_read(dev_priv,
19304 HBLANK(cpu_transcoder));
19305 error->transcoder[i].hsync = intel_de_read(dev_priv,
19306 HSYNC(cpu_transcoder));
19307 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19308 VTOTAL(cpu_transcoder));
19309 error->transcoder[i].vblank = intel_de_read(dev_priv,
19310 VBLANK(cpu_transcoder));
19311 error->transcoder[i].vsync = intel_de_read(dev_priv,
19312 VSYNC(cpu_transcoder));
19318 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19321 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19322 struct intel_display_error_state *error)
19324 struct drm_i915_private *dev_priv = m->i915;
19330 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19331 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19332 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19333 error->power_well_driver);
19334 for_each_pipe(dev_priv, i) {
19335 err_printf(m, "Pipe [%d]:\n", i);
19336 err_printf(m, " Power: %s\n",
19337 onoff(error->pipe[i].power_domain_on));
19338 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19339 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19341 err_printf(m, "Plane [%d]:\n", i);
19342 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19343 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19344 if (INTEL_GEN(dev_priv) <= 3) {
19345 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19346 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19348 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19349 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19350 if (INTEL_GEN(dev_priv) >= 4) {
19351 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19352 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19355 err_printf(m, "Cursor [%d]:\n", i);
19356 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19357 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19358 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19361 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19362 if (!error->transcoder[i].available)
19365 err_printf(m, "CPU transcoder: %s\n",
19366 transcoder_name(error->transcoder[i].cpu_transcoder));
19367 err_printf(m, " Power: %s\n",
19368 onoff(error->transcoder[i].power_domain_on));
19369 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19370 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19371 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19372 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19373 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19374 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19375 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);