2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812 u32 mode_flags = crtc->mode_flags;
1815 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
1816 * have updated at the beginning of TE, if we want to use
1817 * the hw counter, then we would find it updated in only
1818 * the next TE, hence switching to sw counter.
1820 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
1824 * On i965gm the hardware frame counter reads
1825 * zero when the TV encoder is enabled :(
1827 if (IS_I965GM(dev_priv) &&
1828 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1831 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1832 return 0xffffffff; /* full 32 bit counter */
1833 else if (INTEL_GEN(dev_priv) >= 3)
1834 return 0xffffff; /* only 24 bits of frame count */
1836 return 0; /* Gen2 doesn't have a hardware frame counter */
1839 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1843 assert_vblank_disabled(&crtc->base);
1844 drm_crtc_set_max_vblank_count(&crtc->base,
1845 intel_crtc_max_vblank_count(crtc_state));
1846 drm_crtc_vblank_on(&crtc->base);
1849 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1853 drm_crtc_vblank_off(&crtc->base);
1854 assert_vblank_disabled(&crtc->base);
1857 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1862 enum pipe pipe = crtc->pipe;
1866 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1868 assert_planes_disabled(crtc);
1871 * A pipe without a PLL won't actually be able to drive bits from
1872 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1875 if (HAS_GMCH(dev_priv)) {
1876 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1877 assert_dsi_pll_enabled(dev_priv);
1879 assert_pll_enabled(dev_priv, pipe);
1881 if (new_crtc_state->has_pch_encoder) {
1882 /* if driving the PCH, we need FDI enabled */
1883 assert_fdi_rx_pll_enabled(dev_priv,
1884 intel_crtc_pch_transcoder(crtc));
1885 assert_fdi_tx_pll_enabled(dev_priv,
1886 (enum pipe) cpu_transcoder);
1888 /* FIXME: assert CPU port conditions for SNB+ */
1891 trace_intel_pipe_enable(crtc);
1893 reg = PIPECONF(cpu_transcoder);
1894 val = intel_de_read(dev_priv, reg);
1895 if (val & PIPECONF_ENABLE) {
1896 /* we keep both pipes enabled on 830 */
1897 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1901 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1902 intel_de_posting_read(dev_priv, reg);
1905 * Until the pipe starts PIPEDSL reads will return a stale value,
1906 * which causes an apparent vblank timestamp jump when PIPEDSL
1907 * resets to its proper value. That also messes up the frame count
1908 * when it's derived from the timestamps. So let's wait for the
1909 * pipe to start properly before we call drm_crtc_vblank_on()
1911 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1912 intel_wait_for_pipe_scanline_moving(crtc);
1915 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1919 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1920 enum pipe pipe = crtc->pipe;
1924 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1927 * Make sure planes won't keep trying to pump pixels to us,
1928 * or we might hang the display.
1930 assert_planes_disabled(crtc);
1932 trace_intel_pipe_disable(crtc);
1934 reg = PIPECONF(cpu_transcoder);
1935 val = intel_de_read(dev_priv, reg);
1936 if ((val & PIPECONF_ENABLE) == 0)
1940 * Double wide has implications for planes
1941 * so best keep it disabled when not needed.
1943 if (old_crtc_state->double_wide)
1944 val &= ~PIPECONF_DOUBLE_WIDE;
1946 /* Don't disable pipe or pipe PLLs if needed */
1947 if (!IS_I830(dev_priv))
1948 val &= ~PIPECONF_ENABLE;
1950 intel_de_write(dev_priv, reg, val);
1951 if ((val & PIPECONF_ENABLE) == 0)
1952 intel_wait_for_pipe_off(old_crtc_state);
1955 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1960 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 if (!is_ccs_modifier(fb->modifier))
1965 return plane >= fb->format->num_planes / 2;
1968 static bool is_gen12_ccs_modifier(u64 modifier)
1970 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1971 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1975 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1977 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1980 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1982 if (is_ccs_modifier(fb->modifier))
1983 return is_ccs_plane(fb, plane);
1988 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1990 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1991 (main_plane && main_plane >= fb->format->num_planes / 2));
1993 return fb->format->num_planes / 2 + main_plane;
1996 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1998 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1999 ccs_plane < fb->format->num_planes / 2);
2001 return ccs_plane - fb->format->num_planes / 2;
2004 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
2006 struct drm_i915_private *i915 = to_i915(fb->dev);
2008 if (is_ccs_modifier(fb->modifier))
2009 return main_to_ccs_plane(fb, main_plane);
2010 else if (INTEL_GEN(i915) < 11 &&
2011 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
2018 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2021 return info->is_yuv &&
2022 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2025 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2028 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2033 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2035 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 unsigned int cpp = fb->format->cpp[color_plane];
2038 switch (fb->modifier) {
2039 case DRM_FORMAT_MOD_LINEAR:
2040 return intel_tile_size(dev_priv);
2041 case I915_FORMAT_MOD_X_TILED:
2042 if (IS_GEN(dev_priv, 2))
2046 case I915_FORMAT_MOD_Y_TILED_CCS:
2047 if (is_ccs_plane(fb, color_plane))
2050 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2051 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2052 if (is_ccs_plane(fb, color_plane))
2055 case I915_FORMAT_MOD_Y_TILED:
2056 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 if (is_ccs_plane(fb, color_plane))
2064 case I915_FORMAT_MOD_Yf_TILED:
2080 MISSING_CASE(fb->modifier);
2086 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2088 if (is_gen12_ccs_plane(fb, color_plane))
2091 return intel_tile_size(to_i915(fb->dev)) /
2092 intel_tile_width_bytes(fb, color_plane);
2095 /* Return the tile dimensions in pixel units */
2096 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2097 unsigned int *tile_width,
2098 unsigned int *tile_height)
2100 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2101 unsigned int cpp = fb->format->cpp[color_plane];
2103 *tile_width = tile_width_bytes / cpp;
2104 *tile_height = intel_tile_height(fb, color_plane);
2107 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2110 unsigned int tile_width, tile_height;
2112 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2114 return fb->pitches[color_plane] * tile_height;
2118 intel_fb_align_height(const struct drm_framebuffer *fb,
2119 int color_plane, unsigned int height)
2121 unsigned int tile_height = intel_tile_height(fb, color_plane);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2137 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2139 unsigned int size = 0;
2142 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2143 size += rem_info->plane[i].width * rem_info->plane[i].height;
2149 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2150 const struct drm_framebuffer *fb,
2151 unsigned int rotation)
2153 view->type = I915_GGTT_VIEW_NORMAL;
2154 if (drm_rotation_90_or_270(rotation)) {
2155 view->type = I915_GGTT_VIEW_ROTATED;
2156 view->rotated = to_intel_framebuffer(fb)->rot_info;
2160 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2162 if (IS_I830(dev_priv))
2164 else if (IS_I85X(dev_priv))
2166 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2172 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2174 if (INTEL_GEN(dev_priv) >= 9)
2176 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2177 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2179 else if (INTEL_GEN(dev_priv) >= 4)
2185 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2188 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2190 /* AUX_DIST needs only 4K alignment */
2191 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2192 is_ccs_plane(fb, color_plane))
2195 switch (fb->modifier) {
2196 case DRM_FORMAT_MOD_LINEAR:
2197 return intel_linear_alignment(dev_priv);
2198 case I915_FORMAT_MOD_X_TILED:
2199 if (INTEL_GEN(dev_priv) >= 9)
2202 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2203 if (is_semiplanar_uv_plane(fb, color_plane))
2204 return intel_tile_row_size(fb, color_plane);
2206 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2208 case I915_FORMAT_MOD_Y_TILED_CCS:
2209 case I915_FORMAT_MOD_Yf_TILED_CCS:
2210 case I915_FORMAT_MOD_Y_TILED:
2211 if (INTEL_GEN(dev_priv) >= 12 &&
2212 is_semiplanar_uv_plane(fb, color_plane))
2213 return intel_tile_row_size(fb, color_plane);
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2218 MISSING_CASE(fb->modifier);
2223 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2226 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2228 return INTEL_GEN(dev_priv) < 4 ||
2230 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2234 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2235 const struct i915_ggtt_view *view,
2237 unsigned long *out_flags)
2239 struct drm_device *dev = fb->dev;
2240 struct drm_i915_private *dev_priv = to_i915(dev);
2241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2242 intel_wakeref_t wakeref;
2243 struct i915_vma *vma;
2244 unsigned int pinctl;
2247 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2248 return ERR_PTR(-EINVAL);
2250 alignment = intel_surf_alignment(fb, 0);
2251 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2252 return ERR_PTR(-EINVAL);
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2259 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2269 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2271 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2274 * Valleyview is definitely limited to scanning out the first
2275 * 512MiB. Lets presume this behaviour was inherited from the
2276 * g4x display engine and that all earlier gen are similarly
2277 * limited. Testing suggests that it is a little more
2278 * complicated than this. For example, Cherryview appears quite
2279 * happy to scanout from anywhere within its global aperture.
2282 if (HAS_GMCH(dev_priv))
2283 pinctl |= PIN_MAPPABLE;
2285 vma = i915_gem_object_pin_to_display_plane(obj,
2286 alignment, view, pinctl);
2290 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2294 * Install a fence for tiled scan-out. Pre-i965 always needs a
2295 * fence, whereas 965+ only requires a fence if using
2296 * framebuffer compression. For simplicity, we always, when
2297 * possible, install a fence as the cost is not that onerous.
2299 * If we fail to fence the tiled scanout, then either the
2300 * modeset will reject the change (which is highly unlikely as
2301 * the affected systems, all but one, do not have unmappable
2302 * space) or we will not be able to enable full powersaving
2303 * techniques (also likely not to apply due to various limits
2304 * FBC and the like impose on the size of the buffer, which
2305 * presumably we violated anyway with this unmappable buffer).
2306 * Anyway, it is presumably better to stumble onwards with
2307 * something and try to run the system in a "less than optimal"
2308 * mode that matches the user configuration.
2310 ret = i915_vma_pin_fence(vma);
2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2312 i915_gem_object_unpin_from_display_plane(vma);
2317 if (ret == 0 && vma->fence)
2318 *out_flags |= PLANE_HAS_FENCE;
2323 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2324 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2330 i915_gem_object_lock(vma->obj, NULL);
2331 if (flags & PLANE_HAS_FENCE)
2332 i915_vma_unpin_fence(vma);
2333 i915_gem_object_unpin_from_display_plane(vma);
2334 i915_gem_object_unlock(vma->obj);
2339 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2340 unsigned int rotation)
2342 if (drm_rotation_90_or_270(rotation))
2343 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2345 return fb->pitches[color_plane];
2349 * Convert the x/y offsets into a linear offset.
2350 * Only valid with 0/180 degree rotation, which is fine since linear
2351 * offset is only used with linear buffers on pre-hsw and tiled buffers
2352 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2354 u32 intel_fb_xy_to_linear(int x, int y,
2355 const struct intel_plane_state *state,
2358 const struct drm_framebuffer *fb = state->hw.fb;
2359 unsigned int cpp = fb->format->cpp[color_plane];
2360 unsigned int pitch = state->color_plane[color_plane].stride;
2362 return y * pitch + x * cpp;
2366 * Add the x/y offsets derived from fb->offsets[] to the user
2367 * specified plane src x/y offsets. The resulting x/y offsets
2368 * specify the start of scanout from the beginning of the gtt mapping.
2370 void intel_add_fb_offsets(int *x, int *y,
2371 const struct intel_plane_state *state,
2375 *x += state->color_plane[color_plane].x;
2376 *y += state->color_plane[color_plane].y;
2379 static u32 intel_adjust_tile_offset(int *x, int *y,
2380 unsigned int tile_width,
2381 unsigned int tile_height,
2382 unsigned int tile_size,
2383 unsigned int pitch_tiles,
2387 unsigned int pitch_pixels = pitch_tiles * tile_width;
2390 WARN_ON(old_offset & (tile_size - 1));
2391 WARN_ON(new_offset & (tile_size - 1));
2392 WARN_ON(new_offset > old_offset);
2394 tiles = (old_offset - new_offset) / tile_size;
2396 *y += tiles / pitch_tiles * tile_height;
2397 *x += tiles % pitch_tiles * tile_width;
2399 /* minimize x in case it got needlessly big */
2400 *y += *x / pitch_pixels * tile_height;
2406 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2408 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2409 is_gen12_ccs_plane(fb, color_plane);
2412 static u32 intel_adjust_aligned_offset(int *x, int *y,
2413 const struct drm_framebuffer *fb,
2415 unsigned int rotation,
2417 u32 old_offset, u32 new_offset)
2419 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2420 unsigned int cpp = fb->format->cpp[color_plane];
2422 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2424 if (!is_surface_linear(fb, color_plane)) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int pitch_tiles;
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2431 if (drm_rotation_90_or_270(rotation)) {
2432 pitch_tiles = pitch / tile_height;
2433 swap(tile_width, tile_height);
2435 pitch_tiles = pitch / (tile_width * cpp);
2438 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 old_offset, new_offset);
2442 old_offset += *y * pitch + *x * cpp;
2444 *y = (old_offset - new_offset) / pitch;
2445 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2452 * Adjust the tile offset by moving the difference into
2455 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2456 const struct intel_plane_state *state,
2458 u32 old_offset, u32 new_offset)
2460 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2462 state->color_plane[color_plane].stride,
2463 old_offset, new_offset);
2467 * Computes the aligned offset to the base tile and adjusts
2468 * x, y. bytes per pixel is assumed to be a power-of-two.
2470 * In the 90/270 rotated case, x and y are assumed
2471 * to be already rotated to match the rotated GTT view, and
2472 * pitch is the tile_height aligned framebuffer height.
2474 * This function is used when computing the derived information
2475 * under intel_framebuffer, so using any of that information
2476 * here is not allowed. Anything under drm_framebuffer can be
2477 * used. This is why the user has to pass in the pitch since it
2478 * is specified in the rotated orientation.
2480 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2482 const struct drm_framebuffer *fb,
2485 unsigned int rotation,
2488 unsigned int cpp = fb->format->cpp[color_plane];
2489 u32 offset, offset_aligned;
2491 if (!is_surface_linear(fb, color_plane)) {
2492 unsigned int tile_size, tile_width, tile_height;
2493 unsigned int tile_rows, tiles, pitch_tiles;
2495 tile_size = intel_tile_size(dev_priv);
2496 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2498 if (drm_rotation_90_or_270(rotation)) {
2499 pitch_tiles = pitch / tile_height;
2500 swap(tile_width, tile_height);
2502 pitch_tiles = pitch / (tile_width * cpp);
2505 tile_rows = *y / tile_height;
2508 tiles = *x / tile_width;
2511 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2513 offset_aligned = offset;
2515 offset_aligned = rounddown(offset_aligned, alignment);
2517 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2518 tile_size, pitch_tiles,
2519 offset, offset_aligned);
2521 offset = *y * pitch + *x * cpp;
2522 offset_aligned = offset;
2524 offset_aligned = rounddown(offset_aligned, alignment);
2525 *y = (offset % alignment) / pitch;
2526 *x = ((offset % alignment) - *y * pitch) / cpp;
2532 return offset_aligned;
2535 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2536 const struct intel_plane_state *state,
2539 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2540 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2541 const struct drm_framebuffer *fb = state->hw.fb;
2542 unsigned int rotation = state->hw.rotation;
2543 int pitch = state->color_plane[color_plane].stride;
2546 if (intel_plane->id == PLANE_CURSOR)
2547 alignment = intel_cursor_alignment(dev_priv);
2549 alignment = intel_surf_alignment(fb, color_plane);
2551 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2552 pitch, rotation, alignment);
2555 /* Convert the fb->offset[] into x/y offsets */
2556 static int intel_fb_offset_to_xy(int *x, int *y,
2557 const struct drm_framebuffer *fb,
2560 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561 unsigned int height;
2564 if (INTEL_GEN(dev_priv) >= 12 &&
2565 is_semiplanar_uv_plane(fb, color_plane))
2566 alignment = intel_tile_row_size(fb, color_plane);
2567 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2568 alignment = intel_tile_size(dev_priv);
2572 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2573 drm_dbg_kms(&dev_priv->drm,
2574 "Misaligned offset 0x%08x for color plane %d\n",
2575 fb->offsets[color_plane], color_plane);
2579 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2580 height = ALIGN(height, intel_tile_height(fb, color_plane));
2582 /* Catch potential overflows early */
2583 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2584 fb->offsets[color_plane])) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2587 fb->offsets[color_plane], fb->pitches[color_plane],
2595 intel_adjust_aligned_offset(x, y,
2596 fb, color_plane, DRM_MODE_ROTATE_0,
2597 fb->pitches[color_plane],
2598 fb->offsets[color_plane], 0);
2603 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2605 switch (fb_modifier) {
2606 case I915_FORMAT_MOD_X_TILED:
2607 return I915_TILING_X;
2608 case I915_FORMAT_MOD_Y_TILED:
2609 case I915_FORMAT_MOD_Y_TILED_CCS:
2610 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2611 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2612 return I915_TILING_Y;
2614 return I915_TILING_NONE;
2619 * From the Sky Lake PRM:
2620 * "The Color Control Surface (CCS) contains the compression status of
2621 * the cache-line pairs. The compression state of the cache-line pair
2622 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2623 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2624 * cache-line-pairs. CCS is always Y tiled."
2626 * Since cache line pairs refers to horizontally adjacent cache lines,
2627 * each cache line in the CCS corresponds to an area of 32x16 cache
2628 * lines on the main surface. Since each pixel is 4 bytes, this gives
2629 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2632 static const struct drm_format_info skl_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2635 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2636 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2637 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2638 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2639 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2640 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2644 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2645 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2646 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2647 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2650 static const struct drm_format_info gen12_ccs_formats[] = {
2651 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2652 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 1, .vsub = 1, },
2654 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2655 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 1, .vsub = 1, },
2657 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2658 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 1, .vsub = 1, .has_alpha = true },
2660 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2661 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2662 .hsub = 1, .vsub = 1, .has_alpha = true },
2663 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2664 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2665 .hsub = 2, .vsub = 1, .is_yuv = true },
2666 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2667 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2668 .hsub = 2, .vsub = 1, .is_yuv = true },
2669 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2670 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2671 .hsub = 2, .vsub = 1, .is_yuv = true },
2672 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2673 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2674 .hsub = 2, .vsub = 1, .is_yuv = true },
2675 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2676 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2677 .hsub = 2, .vsub = 2, .is_yuv = true },
2678 { .format = DRM_FORMAT_P010, .num_planes = 4,
2679 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2680 .hsub = 2, .vsub = 2, .is_yuv = true },
2681 { .format = DRM_FORMAT_P012, .num_planes = 4,
2682 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2683 .hsub = 2, .vsub = 2, .is_yuv = true },
2684 { .format = DRM_FORMAT_P016, .num_planes = 4,
2685 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2686 .hsub = 2, .vsub = 2, .is_yuv = true },
2689 static const struct drm_format_info *
2690 lookup_format_info(const struct drm_format_info formats[],
2691 int num_formats, u32 format)
2695 for (i = 0; i < num_formats; i++) {
2696 if (formats[i].format == format)
2703 static const struct drm_format_info *
2704 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2706 switch (cmd->modifier[0]) {
2707 case I915_FORMAT_MOD_Y_TILED_CCS:
2708 case I915_FORMAT_MOD_Yf_TILED_CCS:
2709 return lookup_format_info(skl_ccs_formats,
2710 ARRAY_SIZE(skl_ccs_formats),
2712 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2713 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2714 return lookup_format_info(gen12_ccs_formats,
2715 ARRAY_SIZE(gen12_ccs_formats),
2722 bool is_ccs_modifier(u64 modifier)
2724 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2725 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2726 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2727 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2730 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2732 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2736 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2737 u32 pixel_format, u64 modifier)
2739 struct intel_crtc *crtc;
2740 struct intel_plane *plane;
2743 * We assume the primary plane for pipe A has
2744 * the highest stride limits of them all,
2745 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2747 crtc = intel_get_first_crtc(dev_priv);
2751 plane = to_intel_plane(crtc->base.primary);
2753 return plane->max_stride(plane, pixel_format, modifier,
2758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2759 u32 pixel_format, u64 modifier)
2762 * Arbitrary limit for gen4+ chosen to match the
2763 * render engine max stride.
2765 * The new CCS hash mode makes remapping impossible
2767 if (!is_ccs_modifier(modifier)) {
2768 if (INTEL_GEN(dev_priv) >= 7)
2770 else if (INTEL_GEN(dev_priv) >= 4)
2774 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2778 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2780 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2783 if (is_surface_linear(fb, color_plane)) {
2784 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2789 * To make remapping with linear generally feasible
2790 * we need the stride to be page aligned.
2792 if (fb->pitches[color_plane] > max_stride &&
2793 !is_ccs_modifier(fb->modifier))
2794 return intel_tile_size(dev_priv);
2799 tile_width = intel_tile_width_bytes(fb, color_plane);
2800 if (is_ccs_modifier(fb->modifier)) {
2802 * Display WA #0531: skl,bxt,kbl,glk
2804 * Render decompression and plane width > 3840
2805 * combined with horizontal panning requires the
2806 * plane stride to be a multiple of 4. We'll just
2807 * require the entire fb to accommodate that to avoid
2808 * potential runtime errors at plane configuration time.
2810 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2813 * The main surface pitch must be padded to a multiple of four
2816 else if (INTEL_GEN(dev_priv) >= 12)
2822 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2824 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2825 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2826 const struct drm_framebuffer *fb = plane_state->hw.fb;
2829 /* We don't want to deal with remapping with cursors */
2830 if (plane->id == PLANE_CURSOR)
2834 * The display engine limits already match/exceed the
2835 * render engine limits, so not much point in remapping.
2836 * Would also need to deal with the fence POT alignment
2837 * and gen2 2KiB GTT tile size.
2839 if (INTEL_GEN(dev_priv) < 4)
2843 * The new CCS hash mode isn't compatible with remapping as
2844 * the virtual address of the pages affects the compressed data.
2846 if (is_ccs_modifier(fb->modifier))
2849 /* Linear needs a page aligned stride for remapping */
2850 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2851 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2853 for (i = 0; i < fb->format->num_planes; i++) {
2854 if (fb->pitches[i] & alignment)
2862 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2864 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2865 const struct drm_framebuffer *fb = plane_state->hw.fb;
2866 unsigned int rotation = plane_state->hw.rotation;
2867 u32 stride, max_stride;
2870 * No remapping for invisible planes since we don't have
2871 * an actual source viewport to remap.
2873 if (!plane_state->uapi.visible)
2876 if (!intel_plane_can_remap(plane_state))
2880 * FIXME: aux plane limits on gen9+ are
2881 * unclear in Bspec, for now no checking.
2883 stride = intel_fb_pitch(fb, 0, rotation);
2884 max_stride = plane->max_stride(plane, fb->format->format,
2885 fb->modifier, rotation);
2887 return stride > max_stride;
2891 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2892 const struct drm_framebuffer *fb,
2897 if (color_plane == 0) {
2905 * TODO: Deduct the subsampling from the char block for all CCS
2906 * formats and planes.
2908 if (!is_gen12_ccs_plane(fb, color_plane)) {
2909 *hsub = fb->format->hsub;
2910 *vsub = fb->format->vsub;
2915 main_plane = ccs_to_main_plane(fb, color_plane);
2916 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2917 drm_format_info_block_width(fb->format, main_plane);
2920 * The min stride check in the core framebuffer_check() function
2921 * assumes that format->hsub applies to every plane except for the
2922 * first plane. That's incorrect for the CCS AUX plane of the first
2923 * plane, but for the above check to pass we must define the block
2924 * width with that subsampling applied to it. Adjust the width here
2925 * accordingly, so we can calculate the actual subsampling factor.
2927 if (main_plane == 0)
2928 *hsub *= fb->format->hsub;
2933 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2935 struct drm_i915_private *i915 = to_i915(fb->dev);
2936 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2939 int tile_width, tile_height;
2943 if (!is_ccs_plane(fb, ccs_plane))
2946 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2947 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2950 tile_height *= vsub;
2952 ccs_x = (x * hsub) % tile_width;
2953 ccs_y = (y * vsub) % tile_height;
2955 main_plane = ccs_to_main_plane(fb, ccs_plane);
2956 main_x = intel_fb->normal[main_plane].x % tile_width;
2957 main_y = intel_fb->normal[main_plane].y % tile_height;
2960 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2961 * x/y offsets must match between CCS and the main surface.
2963 if (main_x != ccs_x || main_y != ccs_y) {
2964 drm_dbg_kms(&i915->drm,
2965 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2968 intel_fb->normal[main_plane].x,
2969 intel_fb->normal[main_plane].y,
2978 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2980 int main_plane = is_ccs_plane(fb, color_plane) ?
2981 ccs_to_main_plane(fb, color_plane) : 0;
2982 int main_hsub, main_vsub;
2985 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2986 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2987 *w = fb->width / main_hsub / hsub;
2988 *h = fb->height / main_vsub / vsub;
2992 * Setup the rotated view for an FB plane and return the size the GTT mapping
2993 * requires for this view.
2996 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2997 u32 gtt_offset_rotated, int x, int y,
2998 unsigned int width, unsigned int height,
2999 unsigned int tile_size,
3000 unsigned int tile_width, unsigned int tile_height,
3001 struct drm_framebuffer *fb)
3003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3004 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
3005 unsigned int pitch_tiles;
3008 /* Y or Yf modifiers required for 90/270 rotation */
3009 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3010 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3013 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3016 rot_info->plane[plane] = *plane_info;
3018 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3020 /* rotate the x/y offsets to match the GTT view */
3021 drm_rect_init(&r, x, y, width, height);
3023 plane_info->width * tile_width,
3024 plane_info->height * tile_height,
3025 DRM_MODE_ROTATE_270);
3029 /* rotate the tile dimensions to match the GTT view */
3030 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3031 swap(tile_width, tile_height);
3034 * We only keep the x/y offsets, so push all of the
3035 * gtt offset into the x/y offsets.
3037 intel_adjust_tile_offset(&x, &y,
3038 tile_width, tile_height,
3039 tile_size, pitch_tiles,
3040 gtt_offset_rotated * tile_size, 0);
3043 * First pixel of the framebuffer from
3044 * the start of the rotated gtt mapping.
3046 intel_fb->rotated[plane].x = x;
3047 intel_fb->rotated[plane].y = y;
3049 return plane_info->width * plane_info->height;
3053 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3054 struct drm_framebuffer *fb)
3056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3058 u32 gtt_offset_rotated = 0;
3059 unsigned int max_size = 0;
3060 int i, num_planes = fb->format->num_planes;
3061 unsigned int tile_size = intel_tile_size(dev_priv);
3063 for (i = 0; i < num_planes; i++) {
3064 unsigned int width, height;
3065 unsigned int cpp, size;
3070 cpp = fb->format->cpp[i];
3071 intel_fb_plane_dims(&width, &height, fb, i);
3073 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3075 drm_dbg_kms(&dev_priv->drm,
3076 "bad fb plane %d offset: 0x%x\n",
3081 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3086 * The fence (if used) is aligned to the start of the object
3087 * so having the framebuffer wrap around across the edge of the
3088 * fenced region doesn't really work. We have no API to configure
3089 * the fence start offset within the object (nor could we probably
3090 * on gen2/3). So it's just easier if we just require that the
3091 * fb layout agrees with the fence layout. We already check that the
3092 * fb stride matches the fence stride elsewhere.
3094 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3095 (x + width) * cpp > fb->pitches[i]) {
3096 drm_dbg_kms(&dev_priv->drm,
3097 "bad fb plane %d offset: 0x%x\n",
3103 * First pixel of the framebuffer from
3104 * the start of the normal gtt mapping.
3106 intel_fb->normal[i].x = x;
3107 intel_fb->normal[i].y = y;
3109 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3113 offset /= tile_size;
3115 if (!is_surface_linear(fb, i)) {
3116 struct intel_remapped_plane_info plane_info;
3117 unsigned int tile_width, tile_height;
3119 intel_tile_dims(fb, i, &tile_width, &tile_height);
3121 plane_info.offset = offset;
3122 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3124 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3125 plane_info.height = DIV_ROUND_UP(y + height,
3128 /* how many tiles does this plane need */
3129 size = plane_info.stride * plane_info.height;
3131 * If the plane isn't horizontally tile aligned,
3132 * we need one more tile.
3137 gtt_offset_rotated +=
3138 setup_fb_rotation(i, &plane_info,
3140 x, y, width, height,
3142 tile_width, tile_height,
3145 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3146 x * cpp, tile_size);
3149 /* how many tiles in total needed in the bo */
3150 max_size = max(max_size, offset + size);
3153 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3154 drm_dbg_kms(&dev_priv->drm,
3155 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3156 mul_u32_u32(max_size, tile_size), obj->base.size);
3164 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3166 struct drm_i915_private *dev_priv =
3167 to_i915(plane_state->uapi.plane->dev);
3168 struct drm_framebuffer *fb = plane_state->hw.fb;
3169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3170 struct intel_rotation_info *info = &plane_state->view.rotated;
3171 unsigned int rotation = plane_state->hw.rotation;
3172 int i, num_planes = fb->format->num_planes;
3173 unsigned int tile_size = intel_tile_size(dev_priv);
3174 unsigned int src_x, src_y;
3175 unsigned int src_w, src_h;
3178 memset(&plane_state->view, 0, sizeof(plane_state->view));
3179 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3180 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3182 src_x = plane_state->uapi.src.x1 >> 16;
3183 src_y = plane_state->uapi.src.y1 >> 16;
3184 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3185 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3187 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3189 /* Make src coordinates relative to the viewport */
3190 drm_rect_translate(&plane_state->uapi.src,
3191 -(src_x << 16), -(src_y << 16));
3193 /* Rotate src coordinates to match rotated GTT view */
3194 if (drm_rotation_90_or_270(rotation))
3195 drm_rect_rotate(&plane_state->uapi.src,
3196 src_w << 16, src_h << 16,
3197 DRM_MODE_ROTATE_270);
3199 for (i = 0; i < num_planes; i++) {
3200 unsigned int hsub = i ? fb->format->hsub : 1;
3201 unsigned int vsub = i ? fb->format->vsub : 1;
3202 unsigned int cpp = fb->format->cpp[i];
3203 unsigned int tile_width, tile_height;
3204 unsigned int width, height;
3205 unsigned int pitch_tiles;
3209 intel_tile_dims(fb, i, &tile_width, &tile_height);
3213 width = src_w / hsub;
3214 height = src_h / vsub;
3217 * First pixel of the src viewport from the
3218 * start of the normal gtt mapping.
3220 x += intel_fb->normal[i].x;
3221 y += intel_fb->normal[i].y;
3223 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3224 fb, i, fb->pitches[i],
3225 DRM_MODE_ROTATE_0, tile_size);
3226 offset /= tile_size;
3228 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3229 info->plane[i].offset = offset;
3230 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3232 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3233 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3235 if (drm_rotation_90_or_270(rotation)) {
3238 /* rotate the x/y offsets to match the GTT view */
3239 drm_rect_init(&r, x, y, width, height);
3241 info->plane[i].width * tile_width,
3242 info->plane[i].height * tile_height,
3243 DRM_MODE_ROTATE_270);
3247 pitch_tiles = info->plane[i].height;
3248 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3250 /* rotate the tile dimensions to match the GTT view */
3251 swap(tile_width, tile_height);
3253 pitch_tiles = info->plane[i].width;
3254 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3258 * We only keep the x/y offsets, so push all of the
3259 * gtt offset into the x/y offsets.
3261 intel_adjust_tile_offset(&x, &y,
3262 tile_width, tile_height,
3263 tile_size, pitch_tiles,
3264 gtt_offset * tile_size, 0);
3266 gtt_offset += info->plane[i].width * info->plane[i].height;
3268 plane_state->color_plane[i].offset = 0;
3269 plane_state->color_plane[i].x = x;
3270 plane_state->color_plane[i].y = y;
3275 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3277 const struct intel_framebuffer *fb =
3278 to_intel_framebuffer(plane_state->hw.fb);
3279 unsigned int rotation = plane_state->hw.rotation;
3285 num_planes = fb->base.format->num_planes;
3287 if (intel_plane_needs_remap(plane_state)) {
3288 intel_plane_remap_gtt(plane_state);
3291 * Sometimes even remapping can't overcome
3292 * the stride limitations :( Can happen with
3293 * big plane sizes and suitably misaligned
3296 return intel_plane_check_stride(plane_state);
3299 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3301 for (i = 0; i < num_planes; i++) {
3302 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3303 plane_state->color_plane[i].offset = 0;
3305 if (drm_rotation_90_or_270(rotation)) {
3306 plane_state->color_plane[i].x = fb->rotated[i].x;
3307 plane_state->color_plane[i].y = fb->rotated[i].y;
3309 plane_state->color_plane[i].x = fb->normal[i].x;
3310 plane_state->color_plane[i].y = fb->normal[i].y;
3314 /* Rotate src coordinates to match rotated GTT view */
3315 if (drm_rotation_90_or_270(rotation))
3316 drm_rect_rotate(&plane_state->uapi.src,
3317 fb->base.width << 16, fb->base.height << 16,
3318 DRM_MODE_ROTATE_270);
3320 return intel_plane_check_stride(plane_state);
3323 static int i9xx_format_to_fourcc(int format)
3326 case DISPPLANE_8BPP:
3327 return DRM_FORMAT_C8;
3328 case DISPPLANE_BGRA555:
3329 return DRM_FORMAT_ARGB1555;
3330 case DISPPLANE_BGRX555:
3331 return DRM_FORMAT_XRGB1555;
3332 case DISPPLANE_BGRX565:
3333 return DRM_FORMAT_RGB565;
3335 case DISPPLANE_BGRX888:
3336 return DRM_FORMAT_XRGB8888;
3337 case DISPPLANE_RGBX888:
3338 return DRM_FORMAT_XBGR8888;
3339 case DISPPLANE_BGRA888:
3340 return DRM_FORMAT_ARGB8888;
3341 case DISPPLANE_RGBA888:
3342 return DRM_FORMAT_ABGR8888;
3343 case DISPPLANE_BGRX101010:
3344 return DRM_FORMAT_XRGB2101010;
3345 case DISPPLANE_RGBX101010:
3346 return DRM_FORMAT_XBGR2101010;
3347 case DISPPLANE_BGRA101010:
3348 return DRM_FORMAT_ARGB2101010;
3349 case DISPPLANE_RGBA101010:
3350 return DRM_FORMAT_ABGR2101010;
3351 case DISPPLANE_RGBX161616:
3352 return DRM_FORMAT_XBGR16161616F;
3356 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3359 case PLANE_CTL_FORMAT_RGB_565:
3360 return DRM_FORMAT_RGB565;
3361 case PLANE_CTL_FORMAT_NV12:
3362 return DRM_FORMAT_NV12;
3363 case PLANE_CTL_FORMAT_XYUV:
3364 return DRM_FORMAT_XYUV8888;
3365 case PLANE_CTL_FORMAT_P010:
3366 return DRM_FORMAT_P010;
3367 case PLANE_CTL_FORMAT_P012:
3368 return DRM_FORMAT_P012;
3369 case PLANE_CTL_FORMAT_P016:
3370 return DRM_FORMAT_P016;
3371 case PLANE_CTL_FORMAT_Y210:
3372 return DRM_FORMAT_Y210;
3373 case PLANE_CTL_FORMAT_Y212:
3374 return DRM_FORMAT_Y212;
3375 case PLANE_CTL_FORMAT_Y216:
3376 return DRM_FORMAT_Y216;
3377 case PLANE_CTL_FORMAT_Y410:
3378 return DRM_FORMAT_XVYU2101010;
3379 case PLANE_CTL_FORMAT_Y412:
3380 return DRM_FORMAT_XVYU12_16161616;
3381 case PLANE_CTL_FORMAT_Y416:
3382 return DRM_FORMAT_XVYU16161616;
3384 case PLANE_CTL_FORMAT_XRGB_8888:
3387 return DRM_FORMAT_ABGR8888;
3389 return DRM_FORMAT_XBGR8888;
3392 return DRM_FORMAT_ARGB8888;
3394 return DRM_FORMAT_XRGB8888;
3396 case PLANE_CTL_FORMAT_XRGB_2101010:
3399 return DRM_FORMAT_ABGR2101010;
3401 return DRM_FORMAT_XBGR2101010;
3404 return DRM_FORMAT_ARGB2101010;
3406 return DRM_FORMAT_XRGB2101010;
3408 case PLANE_CTL_FORMAT_XRGB_16161616F:
3411 return DRM_FORMAT_ABGR16161616F;
3413 return DRM_FORMAT_XBGR16161616F;
3416 return DRM_FORMAT_ARGB16161616F;
3418 return DRM_FORMAT_XRGB16161616F;
3423 static struct i915_vma *
3424 initial_plane_vma(struct drm_i915_private *i915,
3425 struct intel_initial_plane_config *plane_config)
3427 struct drm_i915_gem_object *obj;
3428 struct i915_vma *vma;
3431 if (plane_config->size == 0)
3434 base = round_down(plane_config->base,
3435 I915_GTT_MIN_ALIGNMENT);
3436 size = round_up(plane_config->base + plane_config->size,
3437 I915_GTT_MIN_ALIGNMENT);
3441 * If the FB is too big, just don't use it since fbdev is not very
3442 * important and we should probably use that space with FBC or other
3445 if (size * 2 > i915->stolen_usable_size)
3448 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3453 * Mark it WT ahead of time to avoid changing the
3454 * cache_level during fbdev initialization. The
3455 * unbind there would get stuck waiting for rcu.
3457 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3458 I915_CACHE_WT : I915_CACHE_NONE);
3460 switch (plane_config->tiling) {
3461 case I915_TILING_NONE:
3465 obj->tiling_and_stride =
3466 plane_config->fb->base.pitches[0] |
3467 plane_config->tiling;
3470 MISSING_CASE(plane_config->tiling);
3474 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3478 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3481 if (i915_gem_object_is_tiled(obj) &&
3482 !i915_vma_is_map_and_fenceable(vma))
3488 i915_gem_object_put(obj);
3493 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3494 struct intel_initial_plane_config *plane_config)
3496 struct drm_device *dev = crtc->base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3499 struct drm_framebuffer *fb = &plane_config->fb->base;
3500 struct i915_vma *vma;
3502 switch (fb->modifier) {
3503 case DRM_FORMAT_MOD_LINEAR:
3504 case I915_FORMAT_MOD_X_TILED:
3505 case I915_FORMAT_MOD_Y_TILED:
3508 drm_dbg(&dev_priv->drm,
3509 "Unsupported modifier for initial FB: 0x%llx\n",
3514 vma = initial_plane_vma(dev_priv, plane_config);
3518 mode_cmd.pixel_format = fb->format->format;
3519 mode_cmd.width = fb->width;
3520 mode_cmd.height = fb->height;
3521 mode_cmd.pitches[0] = fb->pitches[0];
3522 mode_cmd.modifier[0] = fb->modifier;
3523 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3525 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3526 vma->obj, &mode_cmd)) {
3527 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3531 plane_config->vma = vma;
3540 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3541 struct intel_plane_state *plane_state,
3544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3546 plane_state->uapi.visible = visible;
3549 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3551 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3554 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3556 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3557 struct drm_plane *plane;
3560 * Active_planes aliases if multiple "primary" or cursor planes
3561 * have been used on the same (or wrong) pipe. plane_mask uses
3562 * unique ids, hence we can use that to reconstruct active_planes.
3564 crtc_state->active_planes = 0;
3566 drm_for_each_plane_mask(plane, &dev_priv->drm,
3567 crtc_state->uapi.plane_mask)
3568 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3571 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3572 struct intel_plane *plane)
3574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3575 struct intel_crtc_state *crtc_state =
3576 to_intel_crtc_state(crtc->base.state);
3577 struct intel_plane_state *plane_state =
3578 to_intel_plane_state(plane->base.state);
3580 drm_dbg_kms(&dev_priv->drm,
3581 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3582 plane->base.base.id, plane->base.name,
3583 crtc->base.base.id, crtc->base.name);
3585 intel_set_plane_visible(crtc_state, plane_state, false);
3586 fixup_active_planes(crtc_state);
3587 crtc_state->data_rate[plane->id] = 0;
3588 crtc_state->min_cdclk[plane->id] = 0;
3590 if (plane->id == PLANE_PRIMARY)
3591 hsw_disable_ips(crtc_state);
3594 * Vblank time updates from the shadow to live plane control register
3595 * are blocked if the memory self-refresh mode is active at that
3596 * moment. So to make sure the plane gets truly disabled, disable
3597 * first the self-refresh mode. The self-refresh enable bit in turn
3598 * will be checked/applied by the HW only at the next frame start
3599 * event which is after the vblank start event, so we need to have a
3600 * wait-for-vblank between disabling the plane and the pipe.
3602 if (HAS_GMCH(dev_priv) &&
3603 intel_set_memory_cxsr(dev_priv, false))
3604 intel_wait_for_vblank(dev_priv, crtc->pipe);
3607 * Gen2 reports pipe underruns whenever all planes are disabled.
3608 * So disable underrun reporting before all the planes get disabled.
3610 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3611 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3613 intel_disable_plane(plane, crtc_state);
3616 static struct intel_frontbuffer *
3617 to_intel_frontbuffer(struct drm_framebuffer *fb)
3619 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3623 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3624 struct intel_initial_plane_config *plane_config)
3626 struct drm_device *dev = intel_crtc->base.dev;
3627 struct drm_i915_private *dev_priv = to_i915(dev);
3629 struct drm_plane *primary = intel_crtc->base.primary;
3630 struct drm_plane_state *plane_state = primary->state;
3631 struct intel_plane *intel_plane = to_intel_plane(primary);
3632 struct intel_plane_state *intel_state =
3633 to_intel_plane_state(plane_state);
3634 struct drm_framebuffer *fb;
3635 struct i915_vma *vma;
3637 if (!plane_config->fb)
3640 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3641 fb = &plane_config->fb->base;
3642 vma = plane_config->vma;
3647 * Failed to alloc the obj, check to see if we should share
3648 * an fb with another CRTC instead
3650 for_each_crtc(dev, c) {
3651 struct intel_plane_state *state;
3653 if (c == &intel_crtc->base)
3656 if (!to_intel_crtc(c)->active)
3659 state = to_intel_plane_state(c->primary->state);
3663 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3671 * We've failed to reconstruct the BIOS FB. Current display state
3672 * indicates that the primary plane is visible, but has a NULL FB,
3673 * which will lead to problems later if we don't fix it up. The
3674 * simplest solution is to just disable the primary plane now and
3675 * pretend the BIOS never had it enabled.
3677 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3682 intel_state->hw.rotation = plane_config->rotation;
3683 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3684 intel_state->hw.rotation);
3685 intel_state->color_plane[0].stride =
3686 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3688 __i915_vma_pin(vma);
3689 intel_state->vma = i915_vma_get(vma);
3690 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3692 intel_state->flags |= PLANE_HAS_FENCE;
3694 plane_state->src_x = 0;
3695 plane_state->src_y = 0;
3696 plane_state->src_w = fb->width << 16;
3697 plane_state->src_h = fb->height << 16;
3699 plane_state->crtc_x = 0;
3700 plane_state->crtc_y = 0;
3701 plane_state->crtc_w = fb->width;
3702 plane_state->crtc_h = fb->height;
3704 intel_state->uapi.src = drm_plane_state_src(plane_state);
3705 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3707 if (plane_config->tiling)
3708 dev_priv->preserve_bios_swizzle = true;
3710 plane_state->fb = fb;
3711 drm_framebuffer_get(fb);
3713 plane_state->crtc = &intel_crtc->base;
3714 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3716 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3718 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3719 &to_intel_frontbuffer(fb)->bits);
3722 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3724 unsigned int rotation)
3726 int cpp = fb->format->cpp[color_plane];
3728 switch (fb->modifier) {
3729 case DRM_FORMAT_MOD_LINEAR:
3730 case I915_FORMAT_MOD_X_TILED:
3732 * Validated limit is 4k, but has 5k should
3733 * work apart from the following features:
3734 * - Ytile (already limited to 4k)
3735 * - FP16 (already limited to 4k)
3736 * - render compression (already limited to 4k)
3737 * - KVMR sprite and cursor (don't care)
3738 * - horizontal panning (TODO verify this)
3739 * - pipe and plane scaling (TODO verify this)
3745 case I915_FORMAT_MOD_Y_TILED_CCS:
3746 case I915_FORMAT_MOD_Yf_TILED_CCS:
3747 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3748 /* FIXME AUX plane? */
3749 case I915_FORMAT_MOD_Y_TILED:
3750 case I915_FORMAT_MOD_Yf_TILED:
3756 MISSING_CASE(fb->modifier);
3761 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3763 unsigned int rotation)
3765 int cpp = fb->format->cpp[color_plane];
3767 switch (fb->modifier) {
3768 case DRM_FORMAT_MOD_LINEAR:
3769 case I915_FORMAT_MOD_X_TILED:
3774 case I915_FORMAT_MOD_Y_TILED_CCS:
3775 case I915_FORMAT_MOD_Yf_TILED_CCS:
3776 /* FIXME AUX plane? */
3777 case I915_FORMAT_MOD_Y_TILED:
3778 case I915_FORMAT_MOD_Yf_TILED:
3784 MISSING_CASE(fb->modifier);
3789 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3791 /* Wa_14011264657, Wa_14011050563: gen11+ */
3792 switch (fb->format->format) {
3795 case DRM_FORMAT_RGB565:
3797 case DRM_FORMAT_XRGB8888:
3798 case DRM_FORMAT_XBGR8888:
3799 case DRM_FORMAT_ARGB8888:
3800 case DRM_FORMAT_ABGR8888:
3801 case DRM_FORMAT_XRGB2101010:
3802 case DRM_FORMAT_XBGR2101010:
3803 case DRM_FORMAT_ARGB2101010:
3804 case DRM_FORMAT_ABGR2101010:
3805 case DRM_FORMAT_XVYU2101010:
3806 case DRM_FORMAT_Y212:
3807 case DRM_FORMAT_Y216:
3809 case DRM_FORMAT_NV12:
3811 case DRM_FORMAT_P010:
3812 case DRM_FORMAT_P012:
3813 case DRM_FORMAT_P016:
3815 case DRM_FORMAT_XRGB16161616F:
3816 case DRM_FORMAT_XBGR16161616F:
3817 case DRM_FORMAT_ARGB16161616F:
3818 case DRM_FORMAT_ABGR16161616F:
3819 case DRM_FORMAT_XVYU12_16161616:
3820 case DRM_FORMAT_XVYU16161616:
3827 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3829 unsigned int rotation)
3834 static int skl_max_plane_height(void)
3839 static int icl_max_plane_height(void)
3845 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3846 int main_x, int main_y, u32 main_offset,
3849 const struct drm_framebuffer *fb = plane_state->hw.fb;
3850 int aux_x = plane_state->color_plane[ccs_plane].x;
3851 int aux_y = plane_state->color_plane[ccs_plane].y;
3852 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3853 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3857 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3858 while (aux_offset >= main_offset && aux_y <= main_y) {
3861 if (aux_x == main_x && aux_y == main_y)
3864 if (aux_offset == 0)
3869 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3875 aux_x = x * hsub + aux_x % hsub;
3876 aux_y = y * vsub + aux_y % vsub;
3879 if (aux_x != main_x || aux_y != main_y)
3882 plane_state->color_plane[ccs_plane].offset = aux_offset;
3883 plane_state->color_plane[ccs_plane].x = aux_x;
3884 plane_state->color_plane[ccs_plane].y = aux_y;
3890 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3894 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3895 plane_state->color_plane[0].offset, 0);
3900 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3902 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3903 const struct drm_framebuffer *fb = plane_state->hw.fb;
3904 unsigned int rotation = plane_state->hw.rotation;
3905 int x = plane_state->uapi.src.x1 >> 16;
3906 int y = plane_state->uapi.src.y1 >> 16;
3907 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3908 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3909 int max_width, min_width, max_height;
3910 u32 alignment, offset;
3911 int aux_plane = intel_main_to_aux_plane(fb, 0);
3912 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3914 if (INTEL_GEN(dev_priv) >= 11) {
3915 max_width = icl_max_plane_width(fb, 0, rotation);
3916 min_width = icl_min_plane_width(fb);
3917 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3918 max_width = glk_max_plane_width(fb, 0, rotation);
3921 max_width = skl_max_plane_width(fb, 0, rotation);
3925 if (INTEL_GEN(dev_priv) >= 11)
3926 max_height = icl_max_plane_height();
3928 max_height = skl_max_plane_height();
3930 if (w > max_width || w < min_width || h > max_height) {
3931 drm_dbg_kms(&dev_priv->drm,
3932 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3933 w, h, min_width, max_width, max_height);
3937 intel_add_fb_offsets(&x, &y, plane_state, 0);
3938 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3939 alignment = intel_surf_alignment(fb, 0);
3940 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3944 * AUX surface offset is specified as the distance from the
3945 * main surface offset, and it must be non-negative. Make
3946 * sure that is what we will get.
3948 if (aux_plane && offset > aux_offset)
3949 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3950 offset, aux_offset & ~(alignment - 1));
3953 * When using an X-tiled surface, the plane blows up
3954 * if the x offset + width exceed the stride.
3956 * TODO: linear and Y-tiled seem fine, Yf untested,
3958 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3959 int cpp = fb->format->cpp[0];
3961 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3963 drm_dbg_kms(&dev_priv->drm,
3964 "Unable to find suitable display surface offset due to X-tiling\n");
3968 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969 offset, offset - alignment);
3974 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3975 * they match with the main surface x/y offsets.
3977 if (is_ccs_modifier(fb->modifier)) {
3978 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3979 offset, aux_plane)) {
3983 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3984 offset, offset - alignment);
3987 if (x != plane_state->color_plane[aux_plane].x ||
3988 y != plane_state->color_plane[aux_plane].y) {
3989 drm_dbg_kms(&dev_priv->drm,
3990 "Unable to find suitable display surface offset due to CCS\n");
3995 plane_state->color_plane[0].offset = offset;
3996 plane_state->color_plane[0].x = x;
3997 plane_state->color_plane[0].y = y;
4000 * Put the final coordinates back so that the src
4001 * coordinate checks will see the right values.
4003 drm_rect_translate_to(&plane_state->uapi.src,
4009 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
4011 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
4012 const struct drm_framebuffer *fb = plane_state->hw.fb;
4013 unsigned int rotation = plane_state->hw.rotation;
4015 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4016 int max_height = 4096;
4017 int x = plane_state->uapi.src.x1 >> 17;
4018 int y = plane_state->uapi.src.y1 >> 17;
4019 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4020 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4023 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4024 offset = intel_plane_compute_aligned_offset(&x, &y,
4025 plane_state, uv_plane);
4027 /* FIXME not quite sure how/if these apply to the chroma plane */
4028 if (w > max_width || h > max_height) {
4029 drm_dbg_kms(&i915->drm,
4030 "CbCr source size %dx%d too big (limit %dx%d)\n",
4031 w, h, max_width, max_height);
4035 if (is_ccs_modifier(fb->modifier)) {
4036 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4037 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
4038 u32 alignment = intel_surf_alignment(fb, uv_plane);
4040 if (offset > aux_offset)
4041 offset = intel_plane_adjust_aligned_offset(&x, &y,
4045 aux_offset & ~(alignment - 1));
4047 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4048 offset, ccs_plane)) {
4052 offset = intel_plane_adjust_aligned_offset(&x, &y,
4055 offset, offset - alignment);
4058 if (x != plane_state->color_plane[ccs_plane].x ||
4059 y != plane_state->color_plane[ccs_plane].y) {
4060 drm_dbg_kms(&i915->drm,
4061 "Unable to find suitable display surface offset due to CCS\n");
4066 plane_state->color_plane[uv_plane].offset = offset;
4067 plane_state->color_plane[uv_plane].x = x;
4068 plane_state->color_plane[uv_plane].y = y;
4073 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4075 const struct drm_framebuffer *fb = plane_state->hw.fb;
4076 int src_x = plane_state->uapi.src.x1 >> 16;
4077 int src_y = plane_state->uapi.src.y1 >> 16;
4081 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4082 int main_hsub, main_vsub;
4086 if (!is_ccs_plane(fb, ccs_plane))
4089 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4090 ccs_to_main_plane(fb, ccs_plane));
4091 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4098 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4100 offset = intel_plane_compute_aligned_offset(&x, &y,
4104 plane_state->color_plane[ccs_plane].offset = offset;
4105 plane_state->color_plane[ccs_plane].x = (x * hsub +
4108 plane_state->color_plane[ccs_plane].y = (y * vsub +
4116 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4118 const struct drm_framebuffer *fb = plane_state->hw.fb;
4121 ret = intel_plane_compute_gtt(plane_state);
4125 if (!plane_state->uapi.visible)
4129 * Handle the AUX surface first since the main surface setup depends on
4132 if (is_ccs_modifier(fb->modifier)) {
4133 ret = skl_check_ccs_aux_surface(plane_state);
4138 if (intel_format_info_is_yuv_semiplanar(fb->format,
4140 ret = skl_check_nv12_aux_surface(plane_state);
4145 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4146 plane_state->color_plane[i].offset = 0;
4147 plane_state->color_plane[i].x = 0;
4148 plane_state->color_plane[i].y = 0;
4151 ret = skl_check_main_surface(plane_state);
4158 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4159 const struct intel_plane_state *plane_state,
4160 unsigned int *num, unsigned int *den)
4162 const struct drm_framebuffer *fb = plane_state->hw.fb;
4163 unsigned int cpp = fb->format->cpp[0];
4166 * g4x bspec says 64bpp pixel rate can't exceed 80%
4167 * of cdclk when the sprite plane is enabled on the
4168 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4169 * never allowed to exceed 80% of cdclk. Let's just go
4170 * with the ilk/snb limit always.
4181 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4182 const struct intel_plane_state *plane_state)
4184 unsigned int pixel_rate;
4185 unsigned int num, den;
4188 * Note that crtc_state->pixel_rate accounts for both
4189 * horizontal and vertical panel fitter downscaling factors.
4190 * Pre-HSW bspec tells us to only consider the horizontal
4191 * downscaling factor here. We ignore that and just consider
4192 * both for simplicity.
4194 pixel_rate = crtc_state->pixel_rate;
4196 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4198 /* two pixels per clock with double wide pipe */
4199 if (crtc_state->double_wide)
4202 return DIV_ROUND_UP(pixel_rate * num, den);
4206 i9xx_plane_max_stride(struct intel_plane *plane,
4207 u32 pixel_format, u64 modifier,
4208 unsigned int rotation)
4210 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4212 if (!HAS_GMCH(dev_priv)) {
4214 } else if (INTEL_GEN(dev_priv) >= 4) {
4215 if (modifier == I915_FORMAT_MOD_X_TILED)
4219 } else if (INTEL_GEN(dev_priv) >= 3) {
4220 if (modifier == I915_FORMAT_MOD_X_TILED)
4225 if (plane->i9xx_plane == PLANE_C)
4232 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4238 if (crtc_state->gamma_enable)
4239 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4241 if (crtc_state->csc_enable)
4242 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4244 if (INTEL_GEN(dev_priv) < 5)
4245 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4250 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4251 const struct intel_plane_state *plane_state)
4253 struct drm_i915_private *dev_priv =
4254 to_i915(plane_state->uapi.plane->dev);
4255 const struct drm_framebuffer *fb = plane_state->hw.fb;
4256 unsigned int rotation = plane_state->hw.rotation;
4259 dspcntr = DISPLAY_PLANE_ENABLE;
4261 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4262 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4263 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4265 switch (fb->format->format) {
4267 dspcntr |= DISPPLANE_8BPP;
4269 case DRM_FORMAT_XRGB1555:
4270 dspcntr |= DISPPLANE_BGRX555;
4272 case DRM_FORMAT_ARGB1555:
4273 dspcntr |= DISPPLANE_BGRA555;
4275 case DRM_FORMAT_RGB565:
4276 dspcntr |= DISPPLANE_BGRX565;
4278 case DRM_FORMAT_XRGB8888:
4279 dspcntr |= DISPPLANE_BGRX888;
4281 case DRM_FORMAT_XBGR8888:
4282 dspcntr |= DISPPLANE_RGBX888;
4284 case DRM_FORMAT_ARGB8888:
4285 dspcntr |= DISPPLANE_BGRA888;
4287 case DRM_FORMAT_ABGR8888:
4288 dspcntr |= DISPPLANE_RGBA888;
4290 case DRM_FORMAT_XRGB2101010:
4291 dspcntr |= DISPPLANE_BGRX101010;
4293 case DRM_FORMAT_XBGR2101010:
4294 dspcntr |= DISPPLANE_RGBX101010;
4296 case DRM_FORMAT_ARGB2101010:
4297 dspcntr |= DISPPLANE_BGRA101010;
4299 case DRM_FORMAT_ABGR2101010:
4300 dspcntr |= DISPPLANE_RGBA101010;
4302 case DRM_FORMAT_XBGR16161616F:
4303 dspcntr |= DISPPLANE_RGBX161616;
4306 MISSING_CASE(fb->format->format);
4310 if (INTEL_GEN(dev_priv) >= 4 &&
4311 fb->modifier == I915_FORMAT_MOD_X_TILED)
4312 dspcntr |= DISPPLANE_TILED;
4314 if (rotation & DRM_MODE_ROTATE_180)
4315 dspcntr |= DISPPLANE_ROTATE_180;
4317 if (rotation & DRM_MODE_REFLECT_X)
4318 dspcntr |= DISPPLANE_MIRROR;
4323 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4325 struct drm_i915_private *dev_priv =
4326 to_i915(plane_state->uapi.plane->dev);
4327 const struct drm_framebuffer *fb = plane_state->hw.fb;
4328 int src_x, src_y, src_w;
4332 ret = intel_plane_compute_gtt(plane_state);
4336 if (!plane_state->uapi.visible)
4339 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4340 src_x = plane_state->uapi.src.x1 >> 16;
4341 src_y = plane_state->uapi.src.y1 >> 16;
4343 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4344 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4347 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4349 if (INTEL_GEN(dev_priv) >= 4)
4350 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4356 * Put the final coordinates back so that the src
4357 * coordinate checks will see the right values.
4359 drm_rect_translate_to(&plane_state->uapi.src,
4360 src_x << 16, src_y << 16);
4362 /* HSW/BDW do this automagically in hardware */
4363 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4364 unsigned int rotation = plane_state->hw.rotation;
4365 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4366 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4368 if (rotation & DRM_MODE_ROTATE_180) {
4371 } else if (rotation & DRM_MODE_REFLECT_X) {
4376 plane_state->color_plane[0].offset = offset;
4377 plane_state->color_plane[0].x = src_x;
4378 plane_state->color_plane[0].y = src_y;
4383 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4385 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4386 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4388 if (IS_CHERRYVIEW(dev_priv))
4389 return i9xx_plane == PLANE_B;
4390 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4392 else if (IS_GEN(dev_priv, 4))
4393 return i9xx_plane == PLANE_C;
4395 return i9xx_plane == PLANE_B ||
4396 i9xx_plane == PLANE_C;
4400 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4401 struct intel_plane_state *plane_state)
4403 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4406 ret = chv_plane_check_rotation(plane_state);
4410 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4412 DRM_PLANE_HELPER_NO_SCALING,
4413 DRM_PLANE_HELPER_NO_SCALING,
4414 i9xx_plane_has_windowing(plane),
4419 ret = i9xx_check_plane_surface(plane_state);
4423 if (!plane_state->uapi.visible)
4426 ret = intel_plane_check_src_coordinates(plane_state);
4430 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4435 static void i9xx_update_plane(struct intel_plane *plane,
4436 const struct intel_crtc_state *crtc_state,
4437 const struct intel_plane_state *plane_state)
4439 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4440 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4442 int x = plane_state->color_plane[0].x;
4443 int y = plane_state->color_plane[0].y;
4444 int crtc_x = plane_state->uapi.dst.x1;
4445 int crtc_y = plane_state->uapi.dst.y1;
4446 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4447 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4448 unsigned long irqflags;
4452 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4454 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4456 if (INTEL_GEN(dev_priv) >= 4)
4457 dspaddr_offset = plane_state->color_plane[0].offset;
4459 dspaddr_offset = linear_offset;
4461 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4463 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4464 plane_state->color_plane[0].stride);
4466 if (INTEL_GEN(dev_priv) < 4) {
4468 * PLANE_A doesn't actually have a full window
4469 * generator but let's assume we still need to
4470 * program whatever is there.
4472 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4473 (crtc_y << 16) | crtc_x);
4474 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4475 ((crtc_h - 1) << 16) | (crtc_w - 1));
4476 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4477 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4478 (crtc_y << 16) | crtc_x);
4479 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4480 ((crtc_h - 1) << 16) | (crtc_w - 1));
4481 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4484 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4485 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4487 } else if (INTEL_GEN(dev_priv) >= 4) {
4488 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4490 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4495 * The control register self-arms if the plane was previously
4496 * disabled. Try to make the plane enable atomic by writing
4497 * the control register just before the surface register.
4499 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4500 if (INTEL_GEN(dev_priv) >= 4)
4501 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4502 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4504 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4505 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4507 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4510 static void i9xx_disable_plane(struct intel_plane *plane,
4511 const struct intel_crtc_state *crtc_state)
4513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4514 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4515 unsigned long irqflags;
4519 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4520 * enable on ilk+ affect the pipe bottom color as
4521 * well, so we must configure them even if the plane
4524 * On pre-g4x there is no way to gamma correct the
4525 * pipe bottom color but we'll keep on doing this
4526 * anyway so that the crtc state readout works correctly.
4528 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4532 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4533 if (INTEL_GEN(dev_priv) >= 4)
4534 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4536 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4538 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4541 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4544 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4545 enum intel_display_power_domain power_domain;
4546 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4547 intel_wakeref_t wakeref;
4552 * Not 100% correct for planes that can move between pipes,
4553 * but that's only the case for gen2-4 which don't have any
4554 * display power wells.
4556 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4557 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4561 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4563 ret = val & DISPLAY_PLANE_ENABLE;
4565 if (INTEL_GEN(dev_priv) >= 5)
4566 *pipe = plane->pipe;
4568 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4569 DISPPLANE_SEL_PIPE_SHIFT;
4571 intel_display_power_put(dev_priv, power_domain, wakeref);
4576 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4578 struct drm_device *dev = intel_crtc->base.dev;
4579 struct drm_i915_private *dev_priv = to_i915(dev);
4580 unsigned long irqflags;
4582 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4584 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4585 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4586 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4588 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4592 * This function detaches (aka. unbinds) unused scalers in hardware
4594 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4597 const struct intel_crtc_scaler_state *scaler_state =
4598 &crtc_state->scaler_state;
4601 /* loop through and disable scalers that aren't in use */
4602 for (i = 0; i < intel_crtc->num_scalers; i++) {
4603 if (!scaler_state->scalers[i].in_use)
4604 skl_detach_scaler(intel_crtc, i);
4608 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4609 int color_plane, unsigned int rotation)
4612 * The stride is either expressed as a multiple of 64 bytes chunks for
4613 * linear buffers or in number of tiles for tiled buffers.
4615 if (is_surface_linear(fb, color_plane))
4617 else if (drm_rotation_90_or_270(rotation))
4618 return intel_tile_height(fb, color_plane);
4620 return intel_tile_width_bytes(fb, color_plane);
4623 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4626 const struct drm_framebuffer *fb = plane_state->hw.fb;
4627 unsigned int rotation = plane_state->hw.rotation;
4628 u32 stride = plane_state->color_plane[color_plane].stride;
4630 if (color_plane >= fb->format->num_planes)
4633 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4636 static u32 skl_plane_ctl_format(u32 pixel_format)
4638 switch (pixel_format) {
4640 return PLANE_CTL_FORMAT_INDEXED;
4641 case DRM_FORMAT_RGB565:
4642 return PLANE_CTL_FORMAT_RGB_565;
4643 case DRM_FORMAT_XBGR8888:
4644 case DRM_FORMAT_ABGR8888:
4645 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4646 case DRM_FORMAT_XRGB8888:
4647 case DRM_FORMAT_ARGB8888:
4648 return PLANE_CTL_FORMAT_XRGB_8888;
4649 case DRM_FORMAT_XBGR2101010:
4650 case DRM_FORMAT_ABGR2101010:
4651 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4652 case DRM_FORMAT_XRGB2101010:
4653 case DRM_FORMAT_ARGB2101010:
4654 return PLANE_CTL_FORMAT_XRGB_2101010;
4655 case DRM_FORMAT_XBGR16161616F:
4656 case DRM_FORMAT_ABGR16161616F:
4657 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4658 case DRM_FORMAT_XRGB16161616F:
4659 case DRM_FORMAT_ARGB16161616F:
4660 return PLANE_CTL_FORMAT_XRGB_16161616F;
4661 case DRM_FORMAT_XYUV8888:
4662 return PLANE_CTL_FORMAT_XYUV;
4663 case DRM_FORMAT_YUYV:
4664 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4665 case DRM_FORMAT_YVYU:
4666 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4667 case DRM_FORMAT_UYVY:
4668 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4669 case DRM_FORMAT_VYUY:
4670 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4671 case DRM_FORMAT_NV12:
4672 return PLANE_CTL_FORMAT_NV12;
4673 case DRM_FORMAT_P010:
4674 return PLANE_CTL_FORMAT_P010;
4675 case DRM_FORMAT_P012:
4676 return PLANE_CTL_FORMAT_P012;
4677 case DRM_FORMAT_P016:
4678 return PLANE_CTL_FORMAT_P016;
4679 case DRM_FORMAT_Y210:
4680 return PLANE_CTL_FORMAT_Y210;
4681 case DRM_FORMAT_Y212:
4682 return PLANE_CTL_FORMAT_Y212;
4683 case DRM_FORMAT_Y216:
4684 return PLANE_CTL_FORMAT_Y216;
4685 case DRM_FORMAT_XVYU2101010:
4686 return PLANE_CTL_FORMAT_Y410;
4687 case DRM_FORMAT_XVYU12_16161616:
4688 return PLANE_CTL_FORMAT_Y412;
4689 case DRM_FORMAT_XVYU16161616:
4690 return PLANE_CTL_FORMAT_Y416;
4692 MISSING_CASE(pixel_format);
4698 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4700 if (!plane_state->hw.fb->format->has_alpha)
4701 return PLANE_CTL_ALPHA_DISABLE;
4703 switch (plane_state->hw.pixel_blend_mode) {
4704 case DRM_MODE_BLEND_PIXEL_NONE:
4705 return PLANE_CTL_ALPHA_DISABLE;
4706 case DRM_MODE_BLEND_PREMULTI:
4707 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4708 case DRM_MODE_BLEND_COVERAGE:
4709 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4711 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4712 return PLANE_CTL_ALPHA_DISABLE;
4716 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4718 if (!plane_state->hw.fb->format->has_alpha)
4719 return PLANE_COLOR_ALPHA_DISABLE;
4721 switch (plane_state->hw.pixel_blend_mode) {
4722 case DRM_MODE_BLEND_PIXEL_NONE:
4723 return PLANE_COLOR_ALPHA_DISABLE;
4724 case DRM_MODE_BLEND_PREMULTI:
4725 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4726 case DRM_MODE_BLEND_COVERAGE:
4727 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4729 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4730 return PLANE_COLOR_ALPHA_DISABLE;
4734 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4736 switch (fb_modifier) {
4737 case DRM_FORMAT_MOD_LINEAR:
4739 case I915_FORMAT_MOD_X_TILED:
4740 return PLANE_CTL_TILED_X;
4741 case I915_FORMAT_MOD_Y_TILED:
4742 return PLANE_CTL_TILED_Y;
4743 case I915_FORMAT_MOD_Y_TILED_CCS:
4744 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4745 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4746 return PLANE_CTL_TILED_Y |
4747 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4748 PLANE_CTL_CLEAR_COLOR_DISABLE;
4749 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4750 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4751 case I915_FORMAT_MOD_Yf_TILED:
4752 return PLANE_CTL_TILED_YF;
4753 case I915_FORMAT_MOD_Yf_TILED_CCS:
4754 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4756 MISSING_CASE(fb_modifier);
4762 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4765 case DRM_MODE_ROTATE_0:
4768 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4769 * while i915 HW rotation is clockwise, thats why this swapping.
4771 case DRM_MODE_ROTATE_90:
4772 return PLANE_CTL_ROTATE_270;
4773 case DRM_MODE_ROTATE_180:
4774 return PLANE_CTL_ROTATE_180;
4775 case DRM_MODE_ROTATE_270:
4776 return PLANE_CTL_ROTATE_90;
4778 MISSING_CASE(rotate);
4784 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4789 case DRM_MODE_REFLECT_X:
4790 return PLANE_CTL_FLIP_HORIZONTAL;
4791 case DRM_MODE_REFLECT_Y:
4793 MISSING_CASE(reflect);
4799 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4801 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4804 if (crtc_state->uapi.async_flip)
4805 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
4807 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4810 if (crtc_state->gamma_enable)
4811 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4813 if (crtc_state->csc_enable)
4814 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4819 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4820 const struct intel_plane_state *plane_state)
4822 struct drm_i915_private *dev_priv =
4823 to_i915(plane_state->uapi.plane->dev);
4824 const struct drm_framebuffer *fb = plane_state->hw.fb;
4825 unsigned int rotation = plane_state->hw.rotation;
4826 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4829 plane_ctl = PLANE_CTL_ENABLE;
4831 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4832 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4833 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4835 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4836 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4838 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4839 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4842 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4843 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4844 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4846 if (INTEL_GEN(dev_priv) >= 10)
4847 plane_ctl |= cnl_plane_ctl_flip(rotation &
4848 DRM_MODE_REFLECT_MASK);
4850 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4851 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4852 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4853 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4858 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4860 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4861 u32 plane_color_ctl = 0;
4863 if (INTEL_GEN(dev_priv) >= 11)
4864 return plane_color_ctl;
4866 if (crtc_state->gamma_enable)
4867 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4869 if (crtc_state->csc_enable)
4870 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4872 return plane_color_ctl;
4875 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4876 const struct intel_plane_state *plane_state)
4878 struct drm_i915_private *dev_priv =
4879 to_i915(plane_state->uapi.plane->dev);
4880 const struct drm_framebuffer *fb = plane_state->hw.fb;
4881 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4882 u32 plane_color_ctl = 0;
4884 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4885 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4887 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4888 switch (plane_state->hw.color_encoding) {
4889 case DRM_COLOR_YCBCR_BT709:
4890 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4892 case DRM_COLOR_YCBCR_BT2020:
4894 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4898 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4900 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4901 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4902 } else if (fb->format->is_yuv) {
4903 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4906 return plane_color_ctl;
4910 __intel_display_resume(struct drm_device *dev,
4911 struct drm_atomic_state *state,
4912 struct drm_modeset_acquire_ctx *ctx)
4914 struct drm_crtc_state *crtc_state;
4915 struct drm_crtc *crtc;
4918 intel_modeset_setup_hw_state(dev, ctx);
4919 intel_vga_redisable(to_i915(dev));
4925 * We've duplicated the state, pointers to the old state are invalid.
4927 * Don't attempt to use the old state until we commit the duplicated state.
4929 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4931 * Force recalculation even if we restore
4932 * current state. With fast modeset this may not result
4933 * in a modeset when the state is compatible.
4935 crtc_state->mode_changed = true;
4938 /* ignore any reset values/BIOS leftovers in the WM registers */
4939 if (!HAS_GMCH(to_i915(dev)))
4940 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4942 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4944 drm_WARN_ON(dev, ret == -EDEADLK);
4948 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4950 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4951 intel_has_gpu_reset(&dev_priv->gt));
4954 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4956 struct drm_device *dev = &dev_priv->drm;
4957 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4958 struct drm_atomic_state *state;
4961 /* reset doesn't touch the display */
4962 if (!dev_priv->params.force_reset_modeset_test &&
4963 !gpu_reset_clobbers_display(dev_priv))
4966 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4967 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4968 smp_mb__after_atomic();
4969 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4971 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4972 drm_dbg_kms(&dev_priv->drm,
4973 "Modeset potentially stuck, unbreaking through wedging\n");
4974 intel_gt_set_wedged(&dev_priv->gt);
4978 * Need mode_config.mutex so that we don't
4979 * trample ongoing ->detect() and whatnot.
4981 mutex_lock(&dev->mode_config.mutex);
4982 drm_modeset_acquire_init(ctx, 0);
4984 ret = drm_modeset_lock_all_ctx(dev, ctx);
4985 if (ret != -EDEADLK)
4988 drm_modeset_backoff(ctx);
4991 * Disabling the crtcs gracefully seems nicer. Also the
4992 * g33 docs say we should at least disable all the planes.
4994 state = drm_atomic_helper_duplicate_state(dev, ctx);
4995 if (IS_ERR(state)) {
4996 ret = PTR_ERR(state);
4997 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
5002 ret = drm_atomic_helper_disable_all(dev, ctx);
5004 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
5006 drm_atomic_state_put(state);
5010 dev_priv->modeset_restore_state = state;
5011 state->acquire_ctx = ctx;
5014 void intel_finish_reset(struct drm_i915_private *dev_priv)
5016 struct drm_device *dev = &dev_priv->drm;
5017 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5018 struct drm_atomic_state *state;
5021 /* reset doesn't touch the display */
5022 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5025 state = fetch_and_zero(&dev_priv->modeset_restore_state);
5029 /* reset doesn't touch the display */
5030 if (!gpu_reset_clobbers_display(dev_priv)) {
5031 /* for testing only restore the display */
5032 ret = __intel_display_resume(dev, state, ctx);
5034 drm_err(&dev_priv->drm,
5035 "Restoring old state failed with %i\n", ret);
5038 * The display has been reset as well,
5039 * so need a full re-initialization.
5041 intel_pps_unlock_regs_wa(dev_priv);
5042 intel_modeset_init_hw(dev_priv);
5043 intel_init_clock_gating(dev_priv);
5044 intel_hpd_init(dev_priv);
5046 ret = __intel_display_resume(dev, state, ctx);
5048 drm_err(&dev_priv->drm,
5049 "Restoring old state failed with %i\n", ret);
5051 intel_hpd_poll_disable(dev_priv);
5054 drm_atomic_state_put(state);
5056 drm_modeset_drop_locks(ctx);
5057 drm_modeset_acquire_fini(ctx);
5058 mutex_unlock(&dev->mode_config.mutex);
5060 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5063 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5066 enum pipe pipe = crtc->pipe;
5069 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5072 * Display WA #1153: icl
5073 * enable hardware to bypass the alpha math
5074 * and rounding for per-pixel values 00 and 0xff
5076 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5078 * Display WA # 1605353570: icl
5079 * Set the pixel rounding bit to 1 for allowing
5080 * passthrough of Frame buffer pixels unmodified
5083 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5084 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5087 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = to_i915(dev);
5091 enum pipe pipe = crtc->pipe;
5095 /* enable normal train */
5096 reg = FDI_TX_CTL(pipe);
5097 temp = intel_de_read(dev_priv, reg);
5098 if (IS_IVYBRIDGE(dev_priv)) {
5099 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5100 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5102 temp &= ~FDI_LINK_TRAIN_NONE;
5103 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5105 intel_de_write(dev_priv, reg, temp);
5107 reg = FDI_RX_CTL(pipe);
5108 temp = intel_de_read(dev_priv, reg);
5109 if (HAS_PCH_CPT(dev_priv)) {
5110 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5111 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5113 temp &= ~FDI_LINK_TRAIN_NONE;
5114 temp |= FDI_LINK_TRAIN_NONE;
5116 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5118 /* wait one idle pattern time */
5119 intel_de_posting_read(dev_priv, reg);
5122 /* IVB wants error correction enabled */
5123 if (IS_IVYBRIDGE(dev_priv))
5124 intel_de_write(dev_priv, reg,
5125 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5128 /* The FDI link training functions for ILK/Ibexpeak. */
5129 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5130 const struct intel_crtc_state *crtc_state)
5132 struct drm_device *dev = crtc->base.dev;
5133 struct drm_i915_private *dev_priv = to_i915(dev);
5134 enum pipe pipe = crtc->pipe;
5138 /* FDI needs bits from pipe first */
5139 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5143 reg = FDI_RX_IMR(pipe);
5144 temp = intel_de_read(dev_priv, reg);
5145 temp &= ~FDI_RX_SYMBOL_LOCK;
5146 temp &= ~FDI_RX_BIT_LOCK;
5147 intel_de_write(dev_priv, reg, temp);
5148 intel_de_read(dev_priv, reg);
5151 /* enable CPU FDI TX and PCH FDI RX */
5152 reg = FDI_TX_CTL(pipe);
5153 temp = intel_de_read(dev_priv, reg);
5154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5155 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5156 temp &= ~FDI_LINK_TRAIN_NONE;
5157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5158 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5160 reg = FDI_RX_CTL(pipe);
5161 temp = intel_de_read(dev_priv, reg);
5162 temp &= ~FDI_LINK_TRAIN_NONE;
5163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5164 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5166 intel_de_posting_read(dev_priv, reg);
5169 /* Ironlake workaround, enable clock pointer after FDI enable*/
5170 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5171 FDI_RX_PHASE_SYNC_POINTER_OVR);
5172 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5173 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5175 reg = FDI_RX_IIR(pipe);
5176 for (tries = 0; tries < 5; tries++) {
5177 temp = intel_de_read(dev_priv, reg);
5178 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5180 if ((temp & FDI_RX_BIT_LOCK)) {
5181 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5182 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5187 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5190 reg = FDI_TX_CTL(pipe);
5191 temp = intel_de_read(dev_priv, reg);
5192 temp &= ~FDI_LINK_TRAIN_NONE;
5193 temp |= FDI_LINK_TRAIN_PATTERN_2;
5194 intel_de_write(dev_priv, reg, temp);
5196 reg = FDI_RX_CTL(pipe);
5197 temp = intel_de_read(dev_priv, reg);
5198 temp &= ~FDI_LINK_TRAIN_NONE;
5199 temp |= FDI_LINK_TRAIN_PATTERN_2;
5200 intel_de_write(dev_priv, reg, temp);
5202 intel_de_posting_read(dev_priv, reg);
5205 reg = FDI_RX_IIR(pipe);
5206 for (tries = 0; tries < 5; tries++) {
5207 temp = intel_de_read(dev_priv, reg);
5208 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5210 if (temp & FDI_RX_SYMBOL_LOCK) {
5211 intel_de_write(dev_priv, reg,
5212 temp | FDI_RX_SYMBOL_LOCK);
5213 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5218 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5220 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5224 static const int snb_b_fdi_train_param[] = {
5225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5231 /* The FDI link training functions for SNB/Cougarpoint. */
5232 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5233 const struct intel_crtc_state *crtc_state)
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = to_i915(dev);
5237 enum pipe pipe = crtc->pipe;
5241 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5243 reg = FDI_RX_IMR(pipe);
5244 temp = intel_de_read(dev_priv, reg);
5245 temp &= ~FDI_RX_SYMBOL_LOCK;
5246 temp &= ~FDI_RX_BIT_LOCK;
5247 intel_de_write(dev_priv, reg, temp);
5249 intel_de_posting_read(dev_priv, reg);
5252 /* enable CPU FDI TX and PCH FDI RX */
5253 reg = FDI_TX_CTL(pipe);
5254 temp = intel_de_read(dev_priv, reg);
5255 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5256 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5257 temp &= ~FDI_LINK_TRAIN_NONE;
5258 temp |= FDI_LINK_TRAIN_PATTERN_1;
5259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5261 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5262 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5264 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5267 reg = FDI_RX_CTL(pipe);
5268 temp = intel_de_read(dev_priv, reg);
5269 if (HAS_PCH_CPT(dev_priv)) {
5270 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5271 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5273 temp &= ~FDI_LINK_TRAIN_NONE;
5274 temp |= FDI_LINK_TRAIN_PATTERN_1;
5276 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5278 intel_de_posting_read(dev_priv, reg);
5281 for (i = 0; i < 4; i++) {
5282 reg = FDI_TX_CTL(pipe);
5283 temp = intel_de_read(dev_priv, reg);
5284 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5285 temp |= snb_b_fdi_train_param[i];
5286 intel_de_write(dev_priv, reg, temp);
5288 intel_de_posting_read(dev_priv, reg);
5291 for (retry = 0; retry < 5; retry++) {
5292 reg = FDI_RX_IIR(pipe);
5293 temp = intel_de_read(dev_priv, reg);
5294 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5295 if (temp & FDI_RX_BIT_LOCK) {
5296 intel_de_write(dev_priv, reg,
5297 temp | FDI_RX_BIT_LOCK);
5298 drm_dbg_kms(&dev_priv->drm,
5299 "FDI train 1 done.\n");
5308 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5311 reg = FDI_TX_CTL(pipe);
5312 temp = intel_de_read(dev_priv, reg);
5313 temp &= ~FDI_LINK_TRAIN_NONE;
5314 temp |= FDI_LINK_TRAIN_PATTERN_2;
5315 if (IS_GEN(dev_priv, 6)) {
5316 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5318 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5320 intel_de_write(dev_priv, reg, temp);
5322 reg = FDI_RX_CTL(pipe);
5323 temp = intel_de_read(dev_priv, reg);
5324 if (HAS_PCH_CPT(dev_priv)) {
5325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5326 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5328 temp &= ~FDI_LINK_TRAIN_NONE;
5329 temp |= FDI_LINK_TRAIN_PATTERN_2;
5331 intel_de_write(dev_priv, reg, temp);
5333 intel_de_posting_read(dev_priv, reg);
5336 for (i = 0; i < 4; i++) {
5337 reg = FDI_TX_CTL(pipe);
5338 temp = intel_de_read(dev_priv, reg);
5339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5340 temp |= snb_b_fdi_train_param[i];
5341 intel_de_write(dev_priv, reg, temp);
5343 intel_de_posting_read(dev_priv, reg);
5346 for (retry = 0; retry < 5; retry++) {
5347 reg = FDI_RX_IIR(pipe);
5348 temp = intel_de_read(dev_priv, reg);
5349 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5350 if (temp & FDI_RX_SYMBOL_LOCK) {
5351 intel_de_write(dev_priv, reg,
5352 temp | FDI_RX_SYMBOL_LOCK);
5353 drm_dbg_kms(&dev_priv->drm,
5354 "FDI train 2 done.\n");
5363 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5365 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5368 /* Manual link training for Ivy Bridge A0 parts */
5369 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5370 const struct intel_crtc_state *crtc_state)
5372 struct drm_device *dev = crtc->base.dev;
5373 struct drm_i915_private *dev_priv = to_i915(dev);
5374 enum pipe pipe = crtc->pipe;
5378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5380 reg = FDI_RX_IMR(pipe);
5381 temp = intel_de_read(dev_priv, reg);
5382 temp &= ~FDI_RX_SYMBOL_LOCK;
5383 temp &= ~FDI_RX_BIT_LOCK;
5384 intel_de_write(dev_priv, reg, temp);
5386 intel_de_posting_read(dev_priv, reg);
5389 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5390 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5392 /* Try each vswing and preemphasis setting twice before moving on */
5393 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5394 /* disable first in case we need to retry */
5395 reg = FDI_TX_CTL(pipe);
5396 temp = intel_de_read(dev_priv, reg);
5397 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5398 temp &= ~FDI_TX_ENABLE;
5399 intel_de_write(dev_priv, reg, temp);
5401 reg = FDI_RX_CTL(pipe);
5402 temp = intel_de_read(dev_priv, reg);
5403 temp &= ~FDI_LINK_TRAIN_AUTO;
5404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5405 temp &= ~FDI_RX_ENABLE;
5406 intel_de_write(dev_priv, reg, temp);
5408 /* enable CPU FDI TX and PCH FDI RX */
5409 reg = FDI_TX_CTL(pipe);
5410 temp = intel_de_read(dev_priv, reg);
5411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5412 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5413 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5415 temp |= snb_b_fdi_train_param[j/2];
5416 temp |= FDI_COMPOSITE_SYNC;
5417 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5419 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5422 reg = FDI_RX_CTL(pipe);
5423 temp = intel_de_read(dev_priv, reg);
5424 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5425 temp |= FDI_COMPOSITE_SYNC;
5426 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5428 intel_de_posting_read(dev_priv, reg);
5429 udelay(1); /* should be 0.5us */
5431 for (i = 0; i < 4; i++) {
5432 reg = FDI_RX_IIR(pipe);
5433 temp = intel_de_read(dev_priv, reg);
5434 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5436 if (temp & FDI_RX_BIT_LOCK ||
5437 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5438 intel_de_write(dev_priv, reg,
5439 temp | FDI_RX_BIT_LOCK);
5440 drm_dbg_kms(&dev_priv->drm,
5441 "FDI train 1 done, level %i.\n",
5445 udelay(1); /* should be 0.5us */
5448 drm_dbg_kms(&dev_priv->drm,
5449 "FDI train 1 fail on vswing %d\n", j / 2);
5454 reg = FDI_TX_CTL(pipe);
5455 temp = intel_de_read(dev_priv, reg);
5456 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5457 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5458 intel_de_write(dev_priv, reg, temp);
5460 reg = FDI_RX_CTL(pipe);
5461 temp = intel_de_read(dev_priv, reg);
5462 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5463 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5464 intel_de_write(dev_priv, reg, temp);
5466 intel_de_posting_read(dev_priv, reg);
5467 udelay(2); /* should be 1.5us */
5469 for (i = 0; i < 4; i++) {
5470 reg = FDI_RX_IIR(pipe);
5471 temp = intel_de_read(dev_priv, reg);
5472 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5474 if (temp & FDI_RX_SYMBOL_LOCK ||
5475 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5476 intel_de_write(dev_priv, reg,
5477 temp | FDI_RX_SYMBOL_LOCK);
5478 drm_dbg_kms(&dev_priv->drm,
5479 "FDI train 2 done, level %i.\n",
5483 udelay(2); /* should be 1.5us */
5486 drm_dbg_kms(&dev_priv->drm,
5487 "FDI train 2 fail on vswing %d\n", j / 2);
5491 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5494 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5497 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5498 enum pipe pipe = intel_crtc->pipe;
5502 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5503 reg = FDI_RX_CTL(pipe);
5504 temp = intel_de_read(dev_priv, reg);
5505 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5506 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5507 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5508 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5510 intel_de_posting_read(dev_priv, reg);
5513 /* Switch from Rawclk to PCDclk */
5514 temp = intel_de_read(dev_priv, reg);
5515 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5517 intel_de_posting_read(dev_priv, reg);
5520 /* Enable CPU FDI TX PLL, always on for Ironlake */
5521 reg = FDI_TX_CTL(pipe);
5522 temp = intel_de_read(dev_priv, reg);
5523 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5524 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5526 intel_de_posting_read(dev_priv, reg);
5531 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5533 struct drm_device *dev = intel_crtc->base.dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 enum pipe pipe = intel_crtc->pipe;
5539 /* Switch from PCDclk to Rawclk */
5540 reg = FDI_RX_CTL(pipe);
5541 temp = intel_de_read(dev_priv, reg);
5542 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5544 /* Disable CPU FDI TX PLL */
5545 reg = FDI_TX_CTL(pipe);
5546 temp = intel_de_read(dev_priv, reg);
5547 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5549 intel_de_posting_read(dev_priv, reg);
5552 reg = FDI_RX_CTL(pipe);
5553 temp = intel_de_read(dev_priv, reg);
5554 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5556 /* Wait for the clocks to turn off. */
5557 intel_de_posting_read(dev_priv, reg);
5561 static void ilk_fdi_disable(struct intel_crtc *crtc)
5563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5564 enum pipe pipe = crtc->pipe;
5568 /* disable CPU FDI tx and PCH FDI rx */
5569 reg = FDI_TX_CTL(pipe);
5570 temp = intel_de_read(dev_priv, reg);
5571 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5572 intel_de_posting_read(dev_priv, reg);
5574 reg = FDI_RX_CTL(pipe);
5575 temp = intel_de_read(dev_priv, reg);
5576 temp &= ~(0x7 << 16);
5577 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5578 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5580 intel_de_posting_read(dev_priv, reg);
5583 /* Ironlake workaround, disable clock pointer after downing FDI */
5584 if (HAS_PCH_IBX(dev_priv))
5585 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5586 FDI_RX_PHASE_SYNC_POINTER_OVR);
5588 /* still set train pattern 1 */
5589 reg = FDI_TX_CTL(pipe);
5590 temp = intel_de_read(dev_priv, reg);
5591 temp &= ~FDI_LINK_TRAIN_NONE;
5592 temp |= FDI_LINK_TRAIN_PATTERN_1;
5593 intel_de_write(dev_priv, reg, temp);
5595 reg = FDI_RX_CTL(pipe);
5596 temp = intel_de_read(dev_priv, reg);
5597 if (HAS_PCH_CPT(dev_priv)) {
5598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5601 temp &= ~FDI_LINK_TRAIN_NONE;
5602 temp |= FDI_LINK_TRAIN_PATTERN_1;
5604 /* BPC in FDI rx is consistent with that in PIPECONF */
5605 temp &= ~(0x07 << 16);
5606 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5607 intel_de_write(dev_priv, reg, temp);
5609 intel_de_posting_read(dev_priv, reg);
5613 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5615 struct drm_crtc *crtc;
5618 drm_for_each_crtc(crtc, &dev_priv->drm) {
5619 struct drm_crtc_commit *commit;
5620 spin_lock(&crtc->commit_lock);
5621 commit = list_first_entry_or_null(&crtc->commit_list,
5622 struct drm_crtc_commit, commit_entry);
5623 cleanup_done = commit ?
5624 try_wait_for_completion(&commit->cleanup_done) : true;
5625 spin_unlock(&crtc->commit_lock);
5630 drm_crtc_wait_one_vblank(crtc);
5638 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5642 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5644 mutex_lock(&dev_priv->sb_lock);
5646 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5647 temp |= SBI_SSCCTL_DISABLE;
5648 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5650 mutex_unlock(&dev_priv->sb_lock);
5653 /* Program iCLKIP clock to the desired frequency */
5654 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5658 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5659 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5662 lpt_disable_iclkip(dev_priv);
5664 /* The iCLK virtual clock root frequency is in MHz,
5665 * but the adjusted_mode->crtc_clock in in KHz. To get the
5666 * divisors, it is necessary to divide one by another, so we
5667 * convert the virtual clock precision to KHz here for higher
5670 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5671 u32 iclk_virtual_root_freq = 172800 * 1000;
5672 u32 iclk_pi_range = 64;
5673 u32 desired_divisor;
5675 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5677 divsel = (desired_divisor / iclk_pi_range) - 2;
5678 phaseinc = desired_divisor % iclk_pi_range;
5681 * Near 20MHz is a corner case which is
5682 * out of range for the 7-bit divisor
5688 /* This should not happen with any sane values */
5689 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5690 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5691 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5692 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5694 drm_dbg_kms(&dev_priv->drm,
5695 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5696 clock, auxdiv, divsel, phasedir, phaseinc);
5698 mutex_lock(&dev_priv->sb_lock);
5700 /* Program SSCDIVINTPHASE6 */
5701 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5702 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5703 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5704 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5705 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5706 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5707 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5708 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5710 /* Program SSCAUXDIV */
5711 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5712 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5713 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5714 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5716 /* Enable modulator and associated divider */
5717 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5718 temp &= ~SBI_SSCCTL_DISABLE;
5719 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5721 mutex_unlock(&dev_priv->sb_lock);
5723 /* Wait for initialization time */
5726 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5729 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5731 u32 divsel, phaseinc, auxdiv;
5732 u32 iclk_virtual_root_freq = 172800 * 1000;
5733 u32 iclk_pi_range = 64;
5734 u32 desired_divisor;
5737 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5740 mutex_lock(&dev_priv->sb_lock);
5742 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5743 if (temp & SBI_SSCCTL_DISABLE) {
5744 mutex_unlock(&dev_priv->sb_lock);
5748 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5749 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5750 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5751 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5752 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5754 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5755 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5756 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5758 mutex_unlock(&dev_priv->sb_lock);
5760 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5762 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5763 desired_divisor << auxdiv);
5766 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5767 enum pipe pch_transcoder)
5769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5771 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5773 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5774 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5775 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5776 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5777 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5778 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5780 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5781 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5782 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5783 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5784 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5785 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5786 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5787 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5790 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5794 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5795 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5798 drm_WARN_ON(&dev_priv->drm,
5799 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5801 drm_WARN_ON(&dev_priv->drm,
5802 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5805 temp &= ~FDI_BC_BIFURCATION_SELECT;
5807 temp |= FDI_BC_BIFURCATION_SELECT;
5809 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5810 enable ? "en" : "dis");
5811 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5812 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5815 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5818 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5820 switch (crtc->pipe) {
5824 if (crtc_state->fdi_lanes > 2)
5825 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5827 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5831 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5840 * Finds the encoder associated with the given CRTC. This can only be
5841 * used when we know that the CRTC isn't feeding multiple encoders!
5843 static struct intel_encoder *
5844 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5845 const struct intel_crtc_state *crtc_state)
5847 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5848 const struct drm_connector_state *connector_state;
5849 const struct drm_connector *connector;
5850 struct intel_encoder *encoder = NULL;
5851 int num_encoders = 0;
5854 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5855 if (connector_state->crtc != &crtc->base)
5858 encoder = to_intel_encoder(connector_state->best_encoder);
5862 drm_WARN(encoder->base.dev, num_encoders != 1,
5863 "%d encoders for pipe %c\n",
5864 num_encoders, pipe_name(crtc->pipe));
5870 * Enable PCH resources required for PCH ports:
5872 * - FDI training & RX/TX
5873 * - update transcoder timings
5874 * - DP transcoding bits
5877 static void ilk_pch_enable(const struct intel_atomic_state *state,
5878 const struct intel_crtc_state *crtc_state)
5880 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5881 struct drm_device *dev = crtc->base.dev;
5882 struct drm_i915_private *dev_priv = to_i915(dev);
5883 enum pipe pipe = crtc->pipe;
5886 assert_pch_transcoder_disabled(dev_priv, pipe);
5888 if (IS_IVYBRIDGE(dev_priv))
5889 ivb_update_fdi_bc_bifurcation(crtc_state);
5891 /* Write the TU size bits before fdi link training, so that error
5892 * detection works. */
5893 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5894 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5896 /* For PCH output, training FDI link */
5897 dev_priv->display.fdi_link_train(crtc, crtc_state);
5899 /* We need to program the right clock selection before writing the pixel
5900 * mutliplier into the DPLL. */
5901 if (HAS_PCH_CPT(dev_priv)) {
5904 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5905 temp |= TRANS_DPLL_ENABLE(pipe);
5906 sel = TRANS_DPLLB_SEL(pipe);
5907 if (crtc_state->shared_dpll ==
5908 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5912 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5915 /* XXX: pch pll's can be enabled any time before we enable the PCH
5916 * transcoder, and we actually should do this to not upset any PCH
5917 * transcoder that already use the clock when we share it.
5919 * Note that enable_shared_dpll tries to do the right thing, but
5920 * get_shared_dpll unconditionally resets the pll - we need that to have
5921 * the right LVDS enable sequence. */
5922 intel_enable_shared_dpll(crtc_state);
5924 /* set transcoder timing, panel must allow it */
5925 assert_panel_unlocked(dev_priv, pipe);
5926 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5928 intel_fdi_normal_train(crtc);
5930 /* For PCH DP, enable TRANS_DP_CTL */
5931 if (HAS_PCH_CPT(dev_priv) &&
5932 intel_crtc_has_dp_encoder(crtc_state)) {
5933 const struct drm_display_mode *adjusted_mode =
5934 &crtc_state->hw.adjusted_mode;
5935 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5936 i915_reg_t reg = TRANS_DP_CTL(pipe);
5939 temp = intel_de_read(dev_priv, reg);
5940 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5941 TRANS_DP_SYNC_MASK |
5943 temp |= TRANS_DP_OUTPUT_ENABLE;
5944 temp |= bpc << 9; /* same format but at 11:9 */
5946 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5947 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5948 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5949 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5951 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5952 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5953 temp |= TRANS_DP_PORT_SEL(port);
5955 intel_de_write(dev_priv, reg, temp);
5958 ilk_enable_pch_transcoder(crtc_state);
5961 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5963 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5965 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5967 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5969 lpt_program_iclkip(crtc_state);
5971 /* Set transcoder timing. */
5972 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5974 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5977 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5980 i915_reg_t dslreg = PIPEDSL(pipe);
5983 temp = intel_de_read(dev_priv, dslreg);
5985 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5986 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5987 drm_err(&dev_priv->drm,
5988 "mode set failed: pipe %c stuck\n",
5994 * The hardware phase 0.0 refers to the center of the pixel.
5995 * We want to start from the top/left edge which is phase
5996 * -0.5. That matches how the hardware calculates the scaling
5997 * factors (from top-left of the first pixel to bottom-right
5998 * of the last pixel, as opposed to the pixel centers).
6000 * For 4:2:0 subsampled chroma planes we obviously have to
6001 * adjust that so that the chroma sample position lands in
6004 * Note that for packed YCbCr 4:2:2 formats there is no way to
6005 * control chroma siting. The hardware simply replicates the
6006 * chroma samples for both of the luma samples, and thus we don't
6007 * actually get the expected MPEG2 chroma siting convention :(
6008 * The same behaviour is observed on pre-SKL platforms as well.
6010 * Theory behind the formula (note that we ignore sub-pixel
6011 * source coordinates):
6012 * s = source sample position
6013 * d = destination sample position
6018 * | | 1.5 (initial phase)
6026 * | -0.375 (initial phase)
6033 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6035 int phase = -0x8000;
6039 phase += (sub - 1) * 0x8000 / sub;
6041 phase += scale / (2 * sub);
6044 * Hardware initial phase limited to [-0.5:1.5].
6045 * Since the max hardware scale factor is 3.0, we
6046 * should never actually excdeed 1.0 here.
6048 WARN_ON(phase < -0x8000 || phase > 0x18000);
6051 phase = 0x10000 + phase;
6053 trip = PS_PHASE_TRIP;
6055 return ((phase >> 2) & PS_PHASE_MASK) | trip;
6058 #define SKL_MIN_SRC_W 8
6059 #define SKL_MAX_SRC_W 4096
6060 #define SKL_MIN_SRC_H 8
6061 #define SKL_MAX_SRC_H 4096
6062 #define SKL_MIN_DST_W 8
6063 #define SKL_MAX_DST_W 4096
6064 #define SKL_MIN_DST_H 8
6065 #define SKL_MAX_DST_H 4096
6066 #define ICL_MAX_SRC_W 5120
6067 #define ICL_MAX_SRC_H 4096
6068 #define ICL_MAX_DST_W 5120
6069 #define ICL_MAX_DST_H 4096
6070 #define SKL_MIN_YUV_420_SRC_W 16
6071 #define SKL_MIN_YUV_420_SRC_H 16
6074 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6075 unsigned int scaler_user, int *scaler_id,
6076 int src_w, int src_h, int dst_w, int dst_h,
6077 const struct drm_format_info *format,
6078 u64 modifier, bool need_scaler)
6080 struct intel_crtc_scaler_state *scaler_state =
6081 &crtc_state->scaler_state;
6082 struct intel_crtc *intel_crtc =
6083 to_intel_crtc(crtc_state->uapi.crtc);
6084 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6085 const struct drm_display_mode *adjusted_mode =
6086 &crtc_state->hw.adjusted_mode;
6089 * Src coordinates are already rotated by 270 degrees for
6090 * the 90/270 degree plane rotation cases (to match the
6091 * GTT mapping), hence no need to account for rotation here.
6093 if (src_w != dst_w || src_h != dst_h)
6097 * Scaling/fitting not supported in IF-ID mode in GEN9+
6098 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6099 * Once NV12 is enabled, handle it here while allocating scaler
6102 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6103 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6104 drm_dbg_kms(&dev_priv->drm,
6105 "Pipe/Plane scaling not supported with IF-ID mode\n");
6110 * if plane is being disabled or scaler is no more required or force detach
6111 * - free scaler binded to this plane/crtc
6112 * - in order to do this, update crtc->scaler_usage
6114 * Here scaler state in crtc_state is set free so that
6115 * scaler can be assigned to other user. Actual register
6116 * update to free the scaler is done in plane/panel-fit programming.
6117 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6119 if (force_detach || !need_scaler) {
6120 if (*scaler_id >= 0) {
6121 scaler_state->scaler_users &= ~(1 << scaler_user);
6122 scaler_state->scalers[*scaler_id].in_use = 0;
6124 drm_dbg_kms(&dev_priv->drm,
6125 "scaler_user index %u.%u: "
6126 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6127 intel_crtc->pipe, scaler_user, *scaler_id,
6128 scaler_state->scaler_users);
6134 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6135 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6136 drm_dbg_kms(&dev_priv->drm,
6137 "Planar YUV: src dimensions not met\n");
6142 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6143 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6144 (INTEL_GEN(dev_priv) >= 11 &&
6145 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6146 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6147 (INTEL_GEN(dev_priv) < 11 &&
6148 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6149 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6150 drm_dbg_kms(&dev_priv->drm,
6151 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6152 "size is out of scaler range\n",
6153 intel_crtc->pipe, scaler_user, src_w, src_h,
6158 /* mark this plane as a scaler user in crtc_state */
6159 scaler_state->scaler_users |= (1 << scaler_user);
6160 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6161 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6162 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6163 scaler_state->scaler_users);
6168 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6170 const struct drm_display_mode *adjusted_mode =
6171 &crtc_state->hw.adjusted_mode;
6174 if (crtc_state->pch_pfit.enabled) {
6175 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6176 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6178 width = adjusted_mode->crtc_hdisplay;
6179 height = adjusted_mode->crtc_vdisplay;
6182 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6184 &crtc_state->scaler_state.scaler_id,
6185 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6186 width, height, NULL, 0,
6187 crtc_state->pch_pfit.enabled);
6191 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6192 * @crtc_state: crtc's scaler state
6193 * @plane_state: atomic plane state to update
6196 * 0 - scaler_usage updated successfully
6197 * error - requested scaling cannot be supported or other error condition
6199 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6200 struct intel_plane_state *plane_state)
6202 struct intel_plane *intel_plane =
6203 to_intel_plane(plane_state->uapi.plane);
6204 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6205 struct drm_framebuffer *fb = plane_state->hw.fb;
6207 bool force_detach = !fb || !plane_state->uapi.visible;
6208 bool need_scaler = false;
6210 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6211 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6212 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6215 ret = skl_update_scaler(crtc_state, force_detach,
6216 drm_plane_index(&intel_plane->base),
6217 &plane_state->scaler_id,
6218 drm_rect_width(&plane_state->uapi.src) >> 16,
6219 drm_rect_height(&plane_state->uapi.src) >> 16,
6220 drm_rect_width(&plane_state->uapi.dst),
6221 drm_rect_height(&plane_state->uapi.dst),
6222 fb ? fb->format : NULL,
6223 fb ? fb->modifier : 0,
6226 if (ret || plane_state->scaler_id < 0)
6229 /* check colorkey */
6230 if (plane_state->ckey.flags) {
6231 drm_dbg_kms(&dev_priv->drm,
6232 "[PLANE:%d:%s] scaling with color key not allowed",
6233 intel_plane->base.base.id,
6234 intel_plane->base.name);
6238 /* Check src format */
6239 switch (fb->format->format) {
6240 case DRM_FORMAT_RGB565:
6241 case DRM_FORMAT_XBGR8888:
6242 case DRM_FORMAT_XRGB8888:
6243 case DRM_FORMAT_ABGR8888:
6244 case DRM_FORMAT_ARGB8888:
6245 case DRM_FORMAT_XRGB2101010:
6246 case DRM_FORMAT_XBGR2101010:
6247 case DRM_FORMAT_ARGB2101010:
6248 case DRM_FORMAT_ABGR2101010:
6249 case DRM_FORMAT_YUYV:
6250 case DRM_FORMAT_YVYU:
6251 case DRM_FORMAT_UYVY:
6252 case DRM_FORMAT_VYUY:
6253 case DRM_FORMAT_NV12:
6254 case DRM_FORMAT_XYUV8888:
6255 case DRM_FORMAT_P010:
6256 case DRM_FORMAT_P012:
6257 case DRM_FORMAT_P016:
6258 case DRM_FORMAT_Y210:
6259 case DRM_FORMAT_Y212:
6260 case DRM_FORMAT_Y216:
6261 case DRM_FORMAT_XVYU2101010:
6262 case DRM_FORMAT_XVYU12_16161616:
6263 case DRM_FORMAT_XVYU16161616:
6265 case DRM_FORMAT_XBGR16161616F:
6266 case DRM_FORMAT_ABGR16161616F:
6267 case DRM_FORMAT_XRGB16161616F:
6268 case DRM_FORMAT_ARGB16161616F:
6269 if (INTEL_GEN(dev_priv) >= 11)
6273 drm_dbg_kms(&dev_priv->drm,
6274 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6275 intel_plane->base.base.id, intel_plane->base.name,
6276 fb->base.id, fb->format->format);
6283 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6285 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6288 for (i = 0; i < crtc->num_scalers; i++)
6289 skl_detach_scaler(crtc, i);
6292 static int cnl_coef_tap(int i)
6297 static u16 cnl_nearest_filter_coef(int t)
6299 return t == 3 ? 0x0800 : 0x3000;
6303 * Theory behind setting nearest-neighbor integer scaling:
6305 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
6306 * The letter represents the filter tap (D is the center tap) and the number
6307 * represents the coefficient set for a phase (0-16).
6309 * +------------+------------------------+------------------------+
6310 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
6311 * +------------+------------------------+------------------------+
6313 * +------------+------------------------+------------------------+
6315 * +------------+------------------------+------------------------+
6317 * +------------+------------------------+------------------------+
6319 * +------------+------------------------+------------------------+
6321 * +------------+------------------------+------------------------+
6322 * | ... | ... | ... |
6323 * +------------+------------------------+------------------------+
6324 * | 38h | B16 | A16 |
6325 * +------------+------------------------+------------------------+
6326 * | 39h | D16 | C16 |
6327 * +------------+------------------------+------------------------+
6328 * | 3Ah | F16 | C16 |
6329 * +------------+------------------------+------------------------+
6330 * | 3Bh | Reserved | G16 |
6331 * +------------+------------------------+------------------------+
6333 * To enable nearest-neighbor scaling: program scaler coefficents with
6334 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
6335 * SCALER_COEFFICIENT_FORMAT
6339 static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
6340 enum pipe pipe, int id, int set)
6344 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
6345 PS_COEE_INDEX_AUTO_INC);
6347 for (i = 0; i < 17 * 7; i += 2) {
6351 t = cnl_coef_tap(i);
6352 tmp = cnl_nearest_filter_coef(t);
6354 t = cnl_coef_tap(i + 1);
6355 tmp |= cnl_nearest_filter_coef(t) << 16;
6357 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
6361 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
6364 inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
6366 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
6367 return (PS_FILTER_PROGRAMMED |
6368 PS_Y_VERT_FILTER_SELECT(set) |
6369 PS_Y_HORZ_FILTER_SELECT(set) |
6370 PS_UV_VERT_FILTER_SELECT(set) |
6371 PS_UV_HORZ_FILTER_SELECT(set));
6374 return PS_FILTER_MEDIUM;
6377 void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
6378 int id, int set, enum drm_scaling_filter filter)
6381 case DRM_SCALING_FILTER_DEFAULT:
6383 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
6384 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
6387 MISSING_CASE(filter);
6391 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6395 const struct intel_crtc_scaler_state *scaler_state =
6396 &crtc_state->scaler_state;
6397 struct drm_rect src = {
6398 .x2 = crtc_state->pipe_src_w << 16,
6399 .y2 = crtc_state->pipe_src_h << 16,
6401 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6402 u16 uv_rgb_hphase, uv_rgb_vphase;
6403 enum pipe pipe = crtc->pipe;
6404 int width = drm_rect_width(dst);
6405 int height = drm_rect_height(dst);
6409 unsigned long irqflags;
6412 if (!crtc_state->pch_pfit.enabled)
6415 if (drm_WARN_ON(&dev_priv->drm,
6416 crtc_state->scaler_state.scaler_id < 0))
6419 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6420 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6422 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6423 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6425 id = scaler_state->scaler_id;
6427 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6429 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6430 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6431 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6432 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6433 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6434 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6435 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6437 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6438 width << 16 | height);
6440 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6443 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6445 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6447 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6448 enum pipe pipe = crtc->pipe;
6449 int width = drm_rect_width(dst);
6450 int height = drm_rect_height(dst);
6454 if (!crtc_state->pch_pfit.enabled)
6457 /* Force use of hard-coded filter coefficients
6458 * as some pre-programmed values are broken,
6461 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6462 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6463 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6465 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6467 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6468 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6471 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6474 struct drm_device *dev = crtc->base.dev;
6475 struct drm_i915_private *dev_priv = to_i915(dev);
6477 if (!crtc_state->ips_enabled)
6481 * We can only enable IPS after we enable a plane and wait for a vblank
6482 * This function is called from post_plane_update, which is run after
6485 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6487 if (IS_BROADWELL(dev_priv)) {
6488 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6489 IPS_ENABLE | IPS_PCODE_CONTROL));
6490 /* Quoting Art Runyan: "its not safe to expect any particular
6491 * value in IPS_CTL bit 31 after enabling IPS through the
6492 * mailbox." Moreover, the mailbox may return a bogus state,
6493 * so we need to just enable it and continue on.
6496 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6497 /* The bit only becomes 1 in the next vblank, so this wait here
6498 * is essentially intel_wait_for_vblank. If we don't have this
6499 * and don't wait for vblanks until the end of crtc_enable, then
6500 * the HW state readout code will complain that the expected
6501 * IPS_CTL value is not the one we read. */
6502 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6503 drm_err(&dev_priv->drm,
6504 "Timed out waiting for IPS enable\n");
6508 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6510 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6511 struct drm_device *dev = crtc->base.dev;
6512 struct drm_i915_private *dev_priv = to_i915(dev);
6514 if (!crtc_state->ips_enabled)
6517 if (IS_BROADWELL(dev_priv)) {
6519 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6521 * Wait for PCODE to finish disabling IPS. The BSpec specified
6522 * 42ms timeout value leads to occasional timeouts so use 100ms
6525 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6526 drm_err(&dev_priv->drm,
6527 "Timed out waiting for IPS disable\n");
6529 intel_de_write(dev_priv, IPS_CTL, 0);
6530 intel_de_posting_read(dev_priv, IPS_CTL);
6533 /* We need to wait for a vblank before we can disable the plane. */
6534 intel_wait_for_vblank(dev_priv, crtc->pipe);
6537 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6539 if (intel_crtc->overlay)
6540 (void) intel_overlay_switch_off(intel_crtc->overlay);
6542 /* Let userspace switch the overlay on again. In most cases userspace
6543 * has to recompute where to put it anyway.
6547 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6548 const struct intel_crtc_state *new_crtc_state)
6550 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6553 if (!old_crtc_state->ips_enabled)
6556 if (needs_modeset(new_crtc_state))
6560 * Workaround : Do not read or write the pipe palette/gamma data while
6561 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6563 * Disable IPS before we program the LUT.
6565 if (IS_HASWELL(dev_priv) &&
6566 (new_crtc_state->uapi.color_mgmt_changed ||
6567 new_crtc_state->update_pipe) &&
6568 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6571 return !new_crtc_state->ips_enabled;
6574 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6575 const struct intel_crtc_state *new_crtc_state)
6577 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6580 if (!new_crtc_state->ips_enabled)
6583 if (needs_modeset(new_crtc_state))
6587 * Workaround : Do not read or write the pipe palette/gamma data while
6588 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6590 * Re-enable IPS after the LUT has been programmed.
6592 if (IS_HASWELL(dev_priv) &&
6593 (new_crtc_state->uapi.color_mgmt_changed ||
6594 new_crtc_state->update_pipe) &&
6595 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6599 * We can't read out IPS on broadwell, assume the worst and
6600 * forcibly enable IPS on the first fastset.
6602 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6605 return !old_crtc_state->ips_enabled;
6608 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6610 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6612 if (!crtc_state->nv12_planes)
6615 /* WA Display #0827: Gen9:all */
6616 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6622 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6624 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6626 /* Wa_2006604312:icl,ehl */
6627 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6633 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6634 const struct intel_crtc_state *new_crtc_state)
6636 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6637 new_crtc_state->active_planes;
6640 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6641 const struct intel_crtc_state *new_crtc_state)
6643 return old_crtc_state->active_planes &&
6644 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6647 static void intel_post_plane_update(struct intel_atomic_state *state,
6648 struct intel_crtc *crtc)
6650 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6651 const struct intel_crtc_state *old_crtc_state =
6652 intel_atomic_get_old_crtc_state(state, crtc);
6653 const struct intel_crtc_state *new_crtc_state =
6654 intel_atomic_get_new_crtc_state(state, crtc);
6655 enum pipe pipe = crtc->pipe;
6657 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6659 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6660 intel_update_watermarks(crtc);
6662 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6663 hsw_enable_ips(new_crtc_state);
6665 intel_fbc_post_update(state, crtc);
6667 if (needs_nv12_wa(old_crtc_state) &&
6668 !needs_nv12_wa(new_crtc_state))
6669 skl_wa_827(dev_priv, pipe, false);
6671 if (needs_scalerclk_wa(old_crtc_state) &&
6672 !needs_scalerclk_wa(new_crtc_state))
6673 icl_wa_scalerclkgating(dev_priv, pipe, false);
6676 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
6677 struct intel_crtc *crtc,
6678 const struct intel_crtc_state *new_crtc_state)
6680 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6681 struct intel_plane *plane;
6682 struct intel_plane_state *new_plane_state;
6685 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
6686 u32 update_mask = new_crtc_state->update_planes;
6687 u32 plane_ctl, surf_addr;
6688 enum plane_id plane_id;
6689 unsigned long irqflags;
6692 if (crtc->pipe != plane->pipe ||
6693 !(update_mask & BIT(plane->id)))
6696 plane_id = plane->id;
6699 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6700 plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
6701 surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
6703 plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
6705 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
6706 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
6707 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6710 intel_wait_for_vblank(dev_priv, crtc->pipe);
6713 static void intel_pre_plane_update(struct intel_atomic_state *state,
6714 struct intel_crtc *crtc)
6716 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6717 const struct intel_crtc_state *old_crtc_state =
6718 intel_atomic_get_old_crtc_state(state, crtc);
6719 const struct intel_crtc_state *new_crtc_state =
6720 intel_atomic_get_new_crtc_state(state, crtc);
6721 enum pipe pipe = crtc->pipe;
6723 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6724 hsw_disable_ips(old_crtc_state);
6726 if (intel_fbc_pre_update(state, crtc))
6727 intel_wait_for_vblank(dev_priv, pipe);
6729 /* Display WA 827 */
6730 if (!needs_nv12_wa(old_crtc_state) &&
6731 needs_nv12_wa(new_crtc_state))
6732 skl_wa_827(dev_priv, pipe, true);
6734 /* Wa_2006604312:icl,ehl */
6735 if (!needs_scalerclk_wa(old_crtc_state) &&
6736 needs_scalerclk_wa(new_crtc_state))
6737 icl_wa_scalerclkgating(dev_priv, pipe, true);
6740 * Vblank time updates from the shadow to live plane control register
6741 * are blocked if the memory self-refresh mode is active at that
6742 * moment. So to make sure the plane gets truly disabled, disable
6743 * first the self-refresh mode. The self-refresh enable bit in turn
6744 * will be checked/applied by the HW only at the next frame start
6745 * event which is after the vblank start event, so we need to have a
6746 * wait-for-vblank between disabling the plane and the pipe.
6748 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6749 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6750 intel_wait_for_vblank(dev_priv, pipe);
6753 * IVB workaround: must disable low power watermarks for at least
6754 * one frame before enabling scaling. LP watermarks can be re-enabled
6755 * when scaling is disabled.
6757 * WaCxSRDisabledForSpriteScaling:ivb
6759 if (old_crtc_state->hw.active &&
6760 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6761 intel_wait_for_vblank(dev_priv, pipe);
6764 * If we're doing a modeset we don't need to do any
6765 * pre-vblank watermark programming here.
6767 if (!needs_modeset(new_crtc_state)) {
6769 * For platforms that support atomic watermarks, program the
6770 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6771 * will be the intermediate values that are safe for both pre- and
6772 * post- vblank; when vblank happens, the 'active' values will be set
6773 * to the final 'target' values and we'll do this again to get the
6774 * optimal watermarks. For gen9+ platforms, the values we program here
6775 * will be the final target values which will get automatically latched
6776 * at vblank time; no further programming will be necessary.
6778 * If a platform hasn't been transitioned to atomic watermarks yet,
6779 * we'll continue to update watermarks the old way, if flags tell
6782 if (dev_priv->display.initial_watermarks)
6783 dev_priv->display.initial_watermarks(state, crtc);
6784 else if (new_crtc_state->update_wm_pre)
6785 intel_update_watermarks(crtc);
6789 * Gen2 reports pipe underruns whenever all planes are disabled.
6790 * So disable underrun reporting before all the planes get disabled.
6792 * We do this after .initial_watermarks() so that we have a
6793 * chance of catching underruns with the intermediate watermarks
6794 * vs. the old plane configuration.
6796 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6800 * WA for platforms where async address update enable bit
6801 * is double buffered and only latched at start of vblank.
6803 if (old_crtc_state->uapi.async_flip &&
6804 !new_crtc_state->uapi.async_flip &&
6805 IS_GEN_RANGE(dev_priv, 9, 10))
6806 skl_disable_async_flip_wa(state, crtc, new_crtc_state);
6809 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6810 struct intel_crtc *crtc)
6812 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6813 const struct intel_crtc_state *new_crtc_state =
6814 intel_atomic_get_new_crtc_state(state, crtc);
6815 unsigned int update_mask = new_crtc_state->update_planes;
6816 const struct intel_plane_state *old_plane_state;
6817 struct intel_plane *plane;
6818 unsigned fb_bits = 0;
6821 intel_crtc_dpms_overlay_disable(crtc);
6823 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6824 if (crtc->pipe != plane->pipe ||
6825 !(update_mask & BIT(plane->id)))
6828 intel_disable_plane(plane, new_crtc_state);
6830 if (old_plane_state->uapi.visible)
6831 fb_bits |= plane->frontbuffer_bit;
6834 intel_frontbuffer_flip(dev_priv, fb_bits);
6838 * intel_connector_primary_encoder - get the primary encoder for a connector
6839 * @connector: connector for which to return the encoder
6841 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6842 * all connectors to their encoder, except for DP-MST connectors which have
6843 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6844 * pointed to by as many DP-MST connectors as there are pipes.
6846 static struct intel_encoder *
6847 intel_connector_primary_encoder(struct intel_connector *connector)
6849 struct intel_encoder *encoder;
6851 if (connector->mst_port)
6852 return &dp_to_dig_port(connector->mst_port)->base;
6854 encoder = intel_attached_encoder(connector);
6855 drm_WARN_ON(connector->base.dev, !encoder);
6860 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6862 struct drm_connector_state *new_conn_state;
6863 struct drm_connector *connector;
6866 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6868 struct intel_connector *intel_connector;
6869 struct intel_encoder *encoder;
6870 struct intel_crtc *crtc;
6872 if (!intel_connector_needs_modeset(state, connector))
6875 intel_connector = to_intel_connector(connector);
6876 encoder = intel_connector_primary_encoder(intel_connector);
6877 if (!encoder->update_prepare)
6880 crtc = new_conn_state->crtc ?
6881 to_intel_crtc(new_conn_state->crtc) : NULL;
6882 encoder->update_prepare(state, encoder, crtc);
6886 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6888 struct drm_connector_state *new_conn_state;
6889 struct drm_connector *connector;
6892 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6894 struct intel_connector *intel_connector;
6895 struct intel_encoder *encoder;
6896 struct intel_crtc *crtc;
6898 if (!intel_connector_needs_modeset(state, connector))
6901 intel_connector = to_intel_connector(connector);
6902 encoder = intel_connector_primary_encoder(intel_connector);
6903 if (!encoder->update_complete)
6906 crtc = new_conn_state->crtc ?
6907 to_intel_crtc(new_conn_state->crtc) : NULL;
6908 encoder->update_complete(state, encoder, crtc);
6912 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6913 struct intel_crtc *crtc)
6915 const struct intel_crtc_state *crtc_state =
6916 intel_atomic_get_new_crtc_state(state, crtc);
6917 const struct drm_connector_state *conn_state;
6918 struct drm_connector *conn;
6921 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6922 struct intel_encoder *encoder =
6923 to_intel_encoder(conn_state->best_encoder);
6925 if (conn_state->crtc != &crtc->base)
6928 if (encoder->pre_pll_enable)
6929 encoder->pre_pll_enable(state, encoder,
6930 crtc_state, conn_state);
6934 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6935 struct intel_crtc *crtc)
6937 const struct intel_crtc_state *crtc_state =
6938 intel_atomic_get_new_crtc_state(state, crtc);
6939 const struct drm_connector_state *conn_state;
6940 struct drm_connector *conn;
6943 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6944 struct intel_encoder *encoder =
6945 to_intel_encoder(conn_state->best_encoder);
6947 if (conn_state->crtc != &crtc->base)
6950 if (encoder->pre_enable)
6951 encoder->pre_enable(state, encoder,
6952 crtc_state, conn_state);
6956 static void intel_encoders_enable(struct intel_atomic_state *state,
6957 struct intel_crtc *crtc)
6959 const struct intel_crtc_state *crtc_state =
6960 intel_atomic_get_new_crtc_state(state, crtc);
6961 const struct drm_connector_state *conn_state;
6962 struct drm_connector *conn;
6965 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6966 struct intel_encoder *encoder =
6967 to_intel_encoder(conn_state->best_encoder);
6969 if (conn_state->crtc != &crtc->base)
6972 if (encoder->enable)
6973 encoder->enable(state, encoder,
6974 crtc_state, conn_state);
6975 intel_opregion_notify_encoder(encoder, true);
6979 static void intel_encoders_disable(struct intel_atomic_state *state,
6980 struct intel_crtc *crtc)
6982 const struct intel_crtc_state *old_crtc_state =
6983 intel_atomic_get_old_crtc_state(state, crtc);
6984 const struct drm_connector_state *old_conn_state;
6985 struct drm_connector *conn;
6988 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6989 struct intel_encoder *encoder =
6990 to_intel_encoder(old_conn_state->best_encoder);
6992 if (old_conn_state->crtc != &crtc->base)
6995 intel_opregion_notify_encoder(encoder, false);
6996 if (encoder->disable)
6997 encoder->disable(state, encoder,
6998 old_crtc_state, old_conn_state);
7002 static void intel_encoders_post_disable(struct intel_atomic_state *state,
7003 struct intel_crtc *crtc)
7005 const struct intel_crtc_state *old_crtc_state =
7006 intel_atomic_get_old_crtc_state(state, crtc);
7007 const struct drm_connector_state *old_conn_state;
7008 struct drm_connector *conn;
7011 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
7012 struct intel_encoder *encoder =
7013 to_intel_encoder(old_conn_state->best_encoder);
7015 if (old_conn_state->crtc != &crtc->base)
7018 if (encoder->post_disable)
7019 encoder->post_disable(state, encoder,
7020 old_crtc_state, old_conn_state);
7024 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
7025 struct intel_crtc *crtc)
7027 const struct intel_crtc_state *old_crtc_state =
7028 intel_atomic_get_old_crtc_state(state, crtc);
7029 const struct drm_connector_state *old_conn_state;
7030 struct drm_connector *conn;
7033 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
7034 struct intel_encoder *encoder =
7035 to_intel_encoder(old_conn_state->best_encoder);
7037 if (old_conn_state->crtc != &crtc->base)
7040 if (encoder->post_pll_disable)
7041 encoder->post_pll_disable(state, encoder,
7042 old_crtc_state, old_conn_state);
7046 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
7047 struct intel_crtc *crtc)
7049 const struct intel_crtc_state *crtc_state =
7050 intel_atomic_get_new_crtc_state(state, crtc);
7051 const struct drm_connector_state *conn_state;
7052 struct drm_connector *conn;
7055 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
7056 struct intel_encoder *encoder =
7057 to_intel_encoder(conn_state->best_encoder);
7059 if (conn_state->crtc != &crtc->base)
7062 if (encoder->update_pipe)
7063 encoder->update_pipe(state, encoder,
7064 crtc_state, conn_state);
7068 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
7070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7071 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7073 plane->disable_plane(plane, crtc_state);
7076 static void ilk_crtc_enable(struct intel_atomic_state *state,
7077 struct intel_crtc *crtc)
7079 const struct intel_crtc_state *new_crtc_state =
7080 intel_atomic_get_new_crtc_state(state, crtc);
7081 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7082 enum pipe pipe = crtc->pipe;
7084 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7088 * Sometimes spurious CPU pipe underruns happen during FDI
7089 * training, at least with VGA+HDMI cloning. Suppress them.
7091 * On ILK we get an occasional spurious CPU pipe underruns
7092 * between eDP port A enable and vdd enable. Also PCH port
7093 * enable seems to result in the occasional CPU pipe underrun.
7095 * Spurious PCH underruns also occur during PCH enabling.
7097 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7098 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7100 if (new_crtc_state->has_pch_encoder)
7101 intel_prepare_shared_dpll(new_crtc_state);
7103 if (intel_crtc_has_dp_encoder(new_crtc_state))
7104 intel_dp_set_m_n(new_crtc_state, M1_N1);
7106 intel_set_transcoder_timings(new_crtc_state);
7107 intel_set_pipe_src_size(new_crtc_state);
7109 if (new_crtc_state->has_pch_encoder)
7110 intel_cpu_transcoder_set_m_n(new_crtc_state,
7111 &new_crtc_state->fdi_m_n, NULL);
7113 ilk_set_pipeconf(new_crtc_state);
7115 crtc->active = true;
7117 intel_encoders_pre_enable(state, crtc);
7119 if (new_crtc_state->has_pch_encoder) {
7120 /* Note: FDI PLL enabling _must_ be done before we enable the
7121 * cpu pipes, hence this is separate from all the other fdi/pch
7123 ilk_fdi_pll_enable(new_crtc_state);
7125 assert_fdi_tx_disabled(dev_priv, pipe);
7126 assert_fdi_rx_disabled(dev_priv, pipe);
7129 ilk_pfit_enable(new_crtc_state);
7132 * On ILK+ LUT must be loaded before the pipe is running but with
7135 intel_color_load_luts(new_crtc_state);
7136 intel_color_commit(new_crtc_state);
7137 /* update DSPCNTR to configure gamma for pipe bottom color */
7138 intel_disable_primary_plane(new_crtc_state);
7140 if (dev_priv->display.initial_watermarks)
7141 dev_priv->display.initial_watermarks(state, crtc);
7142 intel_enable_pipe(new_crtc_state);
7144 if (new_crtc_state->has_pch_encoder)
7145 ilk_pch_enable(state, new_crtc_state);
7147 intel_crtc_vblank_on(new_crtc_state);
7149 intel_encoders_enable(state, crtc);
7151 if (HAS_PCH_CPT(dev_priv))
7152 cpt_verify_modeset(dev_priv, pipe);
7155 * Must wait for vblank to avoid spurious PCH FIFO underruns.
7156 * And a second vblank wait is needed at least on ILK with
7157 * some interlaced HDMI modes. Let's do the double wait always
7158 * in case there are more corner cases we don't know about.
7160 if (new_crtc_state->has_pch_encoder) {
7161 intel_wait_for_vblank(dev_priv, pipe);
7162 intel_wait_for_vblank(dev_priv, pipe);
7164 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7165 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7168 /* IPS only exists on ULT machines and is tied to pipe A. */
7169 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7171 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7174 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7175 enum pipe pipe, bool apply)
7177 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7178 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7185 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7188 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7190 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7191 enum pipe pipe = crtc->pipe;
7194 val = MBUS_DBOX_A_CREDIT(2);
7196 if (INTEL_GEN(dev_priv) >= 12) {
7197 val |= MBUS_DBOX_BW_CREDIT(2);
7198 val |= MBUS_DBOX_B_CREDIT(12);
7200 val |= MBUS_DBOX_BW_CREDIT(1);
7201 val |= MBUS_DBOX_B_CREDIT(8);
7204 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7207 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7212 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7213 HSW_LINETIME(crtc_state->linetime) |
7214 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7217 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7221 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7224 val = intel_de_read(dev_priv, reg);
7225 val &= ~HSW_FRAME_START_DELAY_MASK;
7226 val |= HSW_FRAME_START_DELAY(0);
7227 intel_de_write(dev_priv, reg, val);
7230 static void hsw_crtc_enable(struct intel_atomic_state *state,
7231 struct intel_crtc *crtc)
7233 const struct intel_crtc_state *new_crtc_state =
7234 intel_atomic_get_new_crtc_state(state, crtc);
7235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7236 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7237 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7238 bool psl_clkgate_wa;
7240 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7243 intel_encoders_pre_pll_enable(state, crtc);
7245 if (new_crtc_state->shared_dpll)
7246 intel_enable_shared_dpll(new_crtc_state);
7248 intel_encoders_pre_enable(state, crtc);
7250 if (!transcoder_is_dsi(cpu_transcoder))
7251 intel_set_transcoder_timings(new_crtc_state);
7253 intel_set_pipe_src_size(new_crtc_state);
7255 if (cpu_transcoder != TRANSCODER_EDP &&
7256 !transcoder_is_dsi(cpu_transcoder))
7257 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7258 new_crtc_state->pixel_multiplier - 1);
7260 if (new_crtc_state->has_pch_encoder)
7261 intel_cpu_transcoder_set_m_n(new_crtc_state,
7262 &new_crtc_state->fdi_m_n, NULL);
7264 if (!transcoder_is_dsi(cpu_transcoder)) {
7265 hsw_set_frame_start_delay(new_crtc_state);
7266 hsw_set_pipeconf(new_crtc_state);
7269 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7270 bdw_set_pipemisc(new_crtc_state);
7272 crtc->active = true;
7274 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7275 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7276 new_crtc_state->pch_pfit.enabled;
7278 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7280 if (INTEL_GEN(dev_priv) >= 9)
7281 skl_pfit_enable(new_crtc_state);
7283 ilk_pfit_enable(new_crtc_state);
7286 * On ILK+ LUT must be loaded before the pipe is running but with
7289 intel_color_load_luts(new_crtc_state);
7290 intel_color_commit(new_crtc_state);
7291 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7292 if (INTEL_GEN(dev_priv) < 9)
7293 intel_disable_primary_plane(new_crtc_state);
7295 hsw_set_linetime_wm(new_crtc_state);
7297 if (INTEL_GEN(dev_priv) >= 11)
7298 icl_set_pipe_chicken(crtc);
7300 if (dev_priv->display.initial_watermarks)
7301 dev_priv->display.initial_watermarks(state, crtc);
7303 if (INTEL_GEN(dev_priv) >= 11)
7304 icl_pipe_mbus_enable(crtc);
7306 intel_encoders_enable(state, crtc);
7308 if (psl_clkgate_wa) {
7309 intel_wait_for_vblank(dev_priv, pipe);
7310 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7313 /* If we change the relative order between pipe/planes enabling, we need
7314 * to change the workaround. */
7315 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7316 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7317 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7318 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7322 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7324 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7325 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7326 enum pipe pipe = crtc->pipe;
7328 /* To avoid upsetting the power well on haswell only disable the pfit if
7329 * it's in use. The hw state code will make sure we get this right. */
7330 if (!old_crtc_state->pch_pfit.enabled)
7333 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7334 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7335 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7338 static void ilk_crtc_disable(struct intel_atomic_state *state,
7339 struct intel_crtc *crtc)
7341 const struct intel_crtc_state *old_crtc_state =
7342 intel_atomic_get_old_crtc_state(state, crtc);
7343 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7344 enum pipe pipe = crtc->pipe;
7347 * Sometimes spurious CPU pipe underruns happen when the
7348 * pipe is already disabled, but FDI RX/TX is still enabled.
7349 * Happens at least with VGA+HDMI cloning. Suppress them.
7351 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7352 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7354 intel_encoders_disable(state, crtc);
7356 intel_crtc_vblank_off(old_crtc_state);
7358 intel_disable_pipe(old_crtc_state);
7360 ilk_pfit_disable(old_crtc_state);
7362 if (old_crtc_state->has_pch_encoder)
7363 ilk_fdi_disable(crtc);
7365 intel_encoders_post_disable(state, crtc);
7367 if (old_crtc_state->has_pch_encoder) {
7368 ilk_disable_pch_transcoder(dev_priv, pipe);
7370 if (HAS_PCH_CPT(dev_priv)) {
7374 /* disable TRANS_DP_CTL */
7375 reg = TRANS_DP_CTL(pipe);
7376 temp = intel_de_read(dev_priv, reg);
7377 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7378 TRANS_DP_PORT_SEL_MASK);
7379 temp |= TRANS_DP_PORT_SEL_NONE;
7380 intel_de_write(dev_priv, reg, temp);
7382 /* disable DPLL_SEL */
7383 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7384 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7385 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7388 ilk_fdi_pll_disable(crtc);
7391 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7392 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7395 static void hsw_crtc_disable(struct intel_atomic_state *state,
7396 struct intel_crtc *crtc)
7399 * FIXME collapse everything to one hook.
7400 * Need care with mst->ddi interactions.
7402 intel_encoders_disable(state, crtc);
7403 intel_encoders_post_disable(state, crtc);
7406 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7408 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7411 if (!crtc_state->gmch_pfit.control)
7415 * The panel fitter should only be adjusted whilst the pipe is disabled,
7416 * according to register description and PRM.
7418 drm_WARN_ON(&dev_priv->drm,
7419 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7420 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7422 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7423 crtc_state->gmch_pfit.pgm_ratios);
7424 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7426 /* Border color in case we don't scale up to the full screen. Black by
7427 * default, change to something else for debugging. */
7428 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7431 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7433 if (phy == PHY_NONE)
7435 else if (IS_ROCKETLAKE(dev_priv))
7436 return phy <= PHY_D;
7437 else if (IS_JSL_EHL(dev_priv))
7438 return phy <= PHY_C;
7439 else if (INTEL_GEN(dev_priv) >= 11)
7440 return phy <= PHY_B;
7445 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7447 if (IS_ROCKETLAKE(dev_priv))
7449 else if (INTEL_GEN(dev_priv) >= 12)
7450 return phy >= PHY_D && phy <= PHY_I;
7451 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
7452 return phy >= PHY_C && phy <= PHY_F;
7457 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7459 if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7460 return (enum phy)port - 1;
7461 else if (IS_JSL_EHL(i915) && port == PORT_D)
7464 return (enum phy)port;
7467 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7469 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7470 return PORT_TC_NONE;
7472 if (INTEL_GEN(dev_priv) >= 12)
7473 return port - PORT_D;
7475 return port - PORT_C;
7478 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7482 return POWER_DOMAIN_PORT_DDI_A_LANES;
7484 return POWER_DOMAIN_PORT_DDI_B_LANES;
7486 return POWER_DOMAIN_PORT_DDI_C_LANES;
7488 return POWER_DOMAIN_PORT_DDI_D_LANES;
7490 return POWER_DOMAIN_PORT_DDI_E_LANES;
7492 return POWER_DOMAIN_PORT_DDI_F_LANES;
7494 return POWER_DOMAIN_PORT_DDI_G_LANES;
7496 return POWER_DOMAIN_PORT_DDI_H_LANES;
7498 return POWER_DOMAIN_PORT_DDI_I_LANES;
7501 return POWER_DOMAIN_PORT_OTHER;
7505 enum intel_display_power_domain
7506 intel_aux_power_domain(struct intel_digital_port *dig_port)
7508 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7509 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7511 if (intel_phy_is_tc(dev_priv, phy) &&
7512 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7513 switch (dig_port->aux_ch) {
7515 return POWER_DOMAIN_AUX_C_TBT;
7517 return POWER_DOMAIN_AUX_D_TBT;
7519 return POWER_DOMAIN_AUX_E_TBT;
7521 return POWER_DOMAIN_AUX_F_TBT;
7523 return POWER_DOMAIN_AUX_G_TBT;
7525 return POWER_DOMAIN_AUX_H_TBT;
7527 return POWER_DOMAIN_AUX_I_TBT;
7529 MISSING_CASE(dig_port->aux_ch);
7530 return POWER_DOMAIN_AUX_C_TBT;
7534 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7538 * Converts aux_ch to power_domain without caring about TBT ports for that use
7539 * intel_aux_power_domain()
7541 enum intel_display_power_domain
7542 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7546 return POWER_DOMAIN_AUX_A;
7548 return POWER_DOMAIN_AUX_B;
7550 return POWER_DOMAIN_AUX_C;
7552 return POWER_DOMAIN_AUX_D;
7554 return POWER_DOMAIN_AUX_E;
7556 return POWER_DOMAIN_AUX_F;
7558 return POWER_DOMAIN_AUX_G;
7560 return POWER_DOMAIN_AUX_H;
7562 return POWER_DOMAIN_AUX_I;
7564 MISSING_CASE(aux_ch);
7565 return POWER_DOMAIN_AUX_A;
7569 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7573 struct drm_encoder *encoder;
7574 enum pipe pipe = crtc->pipe;
7576 enum transcoder transcoder = crtc_state->cpu_transcoder;
7578 if (!crtc_state->hw.active)
7581 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7582 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7583 if (crtc_state->pch_pfit.enabled ||
7584 crtc_state->pch_pfit.force_thru)
7585 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7587 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7588 crtc_state->uapi.encoder_mask) {
7589 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7591 mask |= BIT_ULL(intel_encoder->power_domain);
7594 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7595 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7597 if (crtc_state->shared_dpll)
7598 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7604 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7608 enum intel_display_power_domain domain;
7609 u64 domains, new_domains, old_domains;
7611 old_domains = crtc->enabled_power_domains;
7612 crtc->enabled_power_domains = new_domains =
7613 get_crtc_power_domains(crtc_state);
7615 domains = new_domains & ~old_domains;
7617 for_each_power_domain(domain, domains)
7618 intel_display_power_get(dev_priv, domain);
7620 return old_domains & ~new_domains;
7623 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7626 enum intel_display_power_domain domain;
7628 for_each_power_domain(domain, domains)
7629 intel_display_power_put_unchecked(dev_priv, domain);
7632 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7633 struct intel_crtc *crtc)
7635 const struct intel_crtc_state *new_crtc_state =
7636 intel_atomic_get_new_crtc_state(state, crtc);
7637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7638 enum pipe pipe = crtc->pipe;
7640 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7643 if (intel_crtc_has_dp_encoder(new_crtc_state))
7644 intel_dp_set_m_n(new_crtc_state, M1_N1);
7646 intel_set_transcoder_timings(new_crtc_state);
7647 intel_set_pipe_src_size(new_crtc_state);
7649 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7650 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7651 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7654 i9xx_set_pipeconf(new_crtc_state);
7656 crtc->active = true;
7658 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7660 intel_encoders_pre_pll_enable(state, crtc);
7662 if (IS_CHERRYVIEW(dev_priv)) {
7663 chv_prepare_pll(crtc, new_crtc_state);
7664 chv_enable_pll(crtc, new_crtc_state);
7666 vlv_prepare_pll(crtc, new_crtc_state);
7667 vlv_enable_pll(crtc, new_crtc_state);
7670 intel_encoders_pre_enable(state, crtc);
7672 i9xx_pfit_enable(new_crtc_state);
7674 intel_color_load_luts(new_crtc_state);
7675 intel_color_commit(new_crtc_state);
7676 /* update DSPCNTR to configure gamma for pipe bottom color */
7677 intel_disable_primary_plane(new_crtc_state);
7679 dev_priv->display.initial_watermarks(state, crtc);
7680 intel_enable_pipe(new_crtc_state);
7682 intel_crtc_vblank_on(new_crtc_state);
7684 intel_encoders_enable(state, crtc);
7687 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7689 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7692 intel_de_write(dev_priv, FP0(crtc->pipe),
7693 crtc_state->dpll_hw_state.fp0);
7694 intel_de_write(dev_priv, FP1(crtc->pipe),
7695 crtc_state->dpll_hw_state.fp1);
7698 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7699 struct intel_crtc *crtc)
7701 const struct intel_crtc_state *new_crtc_state =
7702 intel_atomic_get_new_crtc_state(state, crtc);
7703 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7704 enum pipe pipe = crtc->pipe;
7706 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7709 i9xx_set_pll_dividers(new_crtc_state);
7711 if (intel_crtc_has_dp_encoder(new_crtc_state))
7712 intel_dp_set_m_n(new_crtc_state, M1_N1);
7714 intel_set_transcoder_timings(new_crtc_state);
7715 intel_set_pipe_src_size(new_crtc_state);
7717 i9xx_set_pipeconf(new_crtc_state);
7719 crtc->active = true;
7721 if (!IS_GEN(dev_priv, 2))
7722 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7724 intel_encoders_pre_enable(state, crtc);
7726 i9xx_enable_pll(crtc, new_crtc_state);
7728 i9xx_pfit_enable(new_crtc_state);
7730 intel_color_load_luts(new_crtc_state);
7731 intel_color_commit(new_crtc_state);
7732 /* update DSPCNTR to configure gamma for pipe bottom color */
7733 intel_disable_primary_plane(new_crtc_state);
7735 if (dev_priv->display.initial_watermarks)
7736 dev_priv->display.initial_watermarks(state, crtc);
7738 intel_update_watermarks(crtc);
7739 intel_enable_pipe(new_crtc_state);
7741 intel_crtc_vblank_on(new_crtc_state);
7743 intel_encoders_enable(state, crtc);
7745 /* prevents spurious underruns */
7746 if (IS_GEN(dev_priv, 2))
7747 intel_wait_for_vblank(dev_priv, pipe);
7750 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7752 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7753 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7755 if (!old_crtc_state->gmch_pfit.control)
7758 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7760 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7761 intel_de_read(dev_priv, PFIT_CONTROL));
7762 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7765 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7766 struct intel_crtc *crtc)
7768 struct intel_crtc_state *old_crtc_state =
7769 intel_atomic_get_old_crtc_state(state, crtc);
7770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7771 enum pipe pipe = crtc->pipe;
7774 * On gen2 planes are double buffered but the pipe isn't, so we must
7775 * wait for planes to fully turn off before disabling the pipe.
7777 if (IS_GEN(dev_priv, 2))
7778 intel_wait_for_vblank(dev_priv, pipe);
7780 intel_encoders_disable(state, crtc);
7782 intel_crtc_vblank_off(old_crtc_state);
7784 intel_disable_pipe(old_crtc_state);
7786 i9xx_pfit_disable(old_crtc_state);
7788 intel_encoders_post_disable(state, crtc);
7790 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7791 if (IS_CHERRYVIEW(dev_priv))
7792 chv_disable_pll(dev_priv, pipe);
7793 else if (IS_VALLEYVIEW(dev_priv))
7794 vlv_disable_pll(dev_priv, pipe);
7796 i9xx_disable_pll(old_crtc_state);
7799 intel_encoders_post_pll_disable(state, crtc);
7801 if (!IS_GEN(dev_priv, 2))
7802 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7804 if (!dev_priv->display.initial_watermarks)
7805 intel_update_watermarks(crtc);
7807 /* clock the pipe down to 640x480@60 to potentially save power */
7808 if (IS_I830(dev_priv))
7809 i830_enable_pipe(dev_priv, pipe);
7812 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7813 struct drm_modeset_acquire_ctx *ctx)
7815 struct intel_encoder *encoder;
7816 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7817 struct intel_bw_state *bw_state =
7818 to_intel_bw_state(dev_priv->bw_obj.state);
7819 struct intel_cdclk_state *cdclk_state =
7820 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7821 struct intel_dbuf_state *dbuf_state =
7822 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7823 struct intel_crtc_state *crtc_state =
7824 to_intel_crtc_state(crtc->base.state);
7825 enum intel_display_power_domain domain;
7826 struct intel_plane *plane;
7827 struct drm_atomic_state *state;
7828 struct intel_crtc_state *temp_crtc_state;
7829 enum pipe pipe = crtc->pipe;
7833 if (!crtc_state->hw.active)
7836 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7837 const struct intel_plane_state *plane_state =
7838 to_intel_plane_state(plane->base.state);
7840 if (plane_state->uapi.visible)
7841 intel_plane_disable_noatomic(crtc, plane);
7844 state = drm_atomic_state_alloc(&dev_priv->drm);
7846 drm_dbg_kms(&dev_priv->drm,
7847 "failed to disable [CRTC:%d:%s], out of memory",
7848 crtc->base.base.id, crtc->base.name);
7852 state->acquire_ctx = ctx;
7854 /* Everything's already locked, -EDEADLK can't happen. */
7855 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7856 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7858 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7860 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7862 drm_atomic_state_put(state);
7864 drm_dbg_kms(&dev_priv->drm,
7865 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7866 crtc->base.base.id, crtc->base.name);
7868 crtc->active = false;
7869 crtc->base.enabled = false;
7871 drm_WARN_ON(&dev_priv->drm,
7872 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7873 crtc_state->uapi.active = false;
7874 crtc_state->uapi.connector_mask = 0;
7875 crtc_state->uapi.encoder_mask = 0;
7876 intel_crtc_free_hw_state(crtc_state);
7877 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7879 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7880 encoder->base.crtc = NULL;
7882 intel_fbc_disable(crtc);
7883 intel_update_watermarks(crtc);
7884 intel_disable_shared_dpll(crtc_state);
7886 domains = crtc->enabled_power_domains;
7887 for_each_power_domain(domain, domains)
7888 intel_display_power_put_unchecked(dev_priv, domain);
7889 crtc->enabled_power_domains = 0;
7891 dev_priv->active_pipes &= ~BIT(pipe);
7892 cdclk_state->min_cdclk[pipe] = 0;
7893 cdclk_state->min_voltage_level[pipe] = 0;
7894 cdclk_state->active_pipes &= ~BIT(pipe);
7896 dbuf_state->active_pipes &= ~BIT(pipe);
7898 bw_state->data_rate[pipe] = 0;
7899 bw_state->num_active_planes[pipe] = 0;
7903 * turn all crtc's off, but do not adjust state
7904 * This has to be paired with a call to intel_modeset_setup_hw_state.
7906 int intel_display_suspend(struct drm_device *dev)
7908 struct drm_i915_private *dev_priv = to_i915(dev);
7909 struct drm_atomic_state *state;
7912 state = drm_atomic_helper_suspend(dev);
7913 ret = PTR_ERR_OR_ZERO(state);
7915 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7918 dev_priv->modeset_restore_state = state;
7922 void intel_encoder_destroy(struct drm_encoder *encoder)
7924 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7926 drm_encoder_cleanup(encoder);
7927 kfree(intel_encoder);
7930 /* Cross check the actual hw state with our own modeset state tracking (and it's
7931 * internal consistency). */
7932 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7933 struct drm_connector_state *conn_state)
7935 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7936 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7938 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7939 connector->base.base.id, connector->base.name);
7941 if (connector->get_hw_state(connector)) {
7942 struct intel_encoder *encoder = intel_attached_encoder(connector);
7944 I915_STATE_WARN(!crtc_state,
7945 "connector enabled without attached crtc\n");
7950 I915_STATE_WARN(!crtc_state->hw.active,
7951 "connector is active, but attached crtc isn't\n");
7953 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7956 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7957 "atomic encoder doesn't match attached encoder\n");
7959 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7960 "attached encoder crtc differs from connector crtc\n");
7962 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7963 "attached crtc is active, but connector isn't\n");
7964 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7965 "best encoder set without crtc!\n");
7969 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7971 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7972 return crtc_state->fdi_lanes;
7977 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7978 struct intel_crtc_state *pipe_config)
7980 struct drm_i915_private *dev_priv = to_i915(dev);
7981 struct drm_atomic_state *state = pipe_config->uapi.state;
7982 struct intel_crtc *other_crtc;
7983 struct intel_crtc_state *other_crtc_state;
7985 drm_dbg_kms(&dev_priv->drm,
7986 "checking fdi config on pipe %c, lanes %i\n",
7987 pipe_name(pipe), pipe_config->fdi_lanes);
7988 if (pipe_config->fdi_lanes > 4) {
7989 drm_dbg_kms(&dev_priv->drm,
7990 "invalid fdi lane config on pipe %c: %i lanes\n",
7991 pipe_name(pipe), pipe_config->fdi_lanes);
7995 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7996 if (pipe_config->fdi_lanes > 2) {
7997 drm_dbg_kms(&dev_priv->drm,
7998 "only 2 lanes on haswell, required: %i lanes\n",
7999 pipe_config->fdi_lanes);
8006 if (INTEL_NUM_PIPES(dev_priv) == 2)
8009 /* Ivybridge 3 pipe is really complicated */
8014 if (pipe_config->fdi_lanes <= 2)
8017 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
8019 intel_atomic_get_crtc_state(state, other_crtc);
8020 if (IS_ERR(other_crtc_state))
8021 return PTR_ERR(other_crtc_state);
8023 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
8024 drm_dbg_kms(&dev_priv->drm,
8025 "invalid shared fdi lane config on pipe %c: %i lanes\n",
8026 pipe_name(pipe), pipe_config->fdi_lanes);
8031 if (pipe_config->fdi_lanes > 2) {
8032 drm_dbg_kms(&dev_priv->drm,
8033 "only 2 lanes on pipe %c: required %i lanes\n",
8034 pipe_name(pipe), pipe_config->fdi_lanes);
8038 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
8040 intel_atomic_get_crtc_state(state, other_crtc);
8041 if (IS_ERR(other_crtc_state))
8042 return PTR_ERR(other_crtc_state);
8044 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
8045 drm_dbg_kms(&dev_priv->drm,
8046 "fdi link B uses too many lanes to enable link C\n");
8056 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
8057 struct intel_crtc_state *pipe_config)
8059 struct drm_device *dev = intel_crtc->base.dev;
8060 struct drm_i915_private *i915 = to_i915(dev);
8061 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8062 int lane, link_bw, fdi_dotclock, ret;
8063 bool needs_recompute = false;
8066 /* FDI is a binary signal running at ~2.7GHz, encoding
8067 * each output octet as 10 bits. The actual frequency
8068 * is stored as a divider into a 100MHz clock, and the
8069 * mode pixel clock is stored in units of 1KHz.
8070 * Hence the bw of each lane in terms of the mode signal
8073 link_bw = intel_fdi_link_freq(i915, pipe_config);
8075 fdi_dotclock = adjusted_mode->crtc_clock;
8077 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
8078 pipe_config->pipe_bpp);
8080 pipe_config->fdi_lanes = lane;
8082 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
8083 link_bw, &pipe_config->fdi_m_n, false, false);
8085 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
8086 if (ret == -EDEADLK)
8089 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
8090 pipe_config->pipe_bpp -= 2*3;
8091 drm_dbg_kms(&i915->drm,
8092 "fdi link bw constraint, reducing pipe bpp to %i\n",
8093 pipe_config->pipe_bpp);
8094 needs_recompute = true;
8095 pipe_config->bw_constrained = true;
8100 if (needs_recompute)
8106 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
8108 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8109 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8111 /* IPS only exists on ULT machines and is tied to pipe A. */
8112 if (!hsw_crtc_supports_ips(crtc))
8115 if (!dev_priv->params.enable_ips)
8118 if (crtc_state->pipe_bpp > 24)
8122 * We compare against max which means we must take
8123 * the increased cdclk requirement into account when
8124 * calculating the new cdclk.
8126 * Should measure whether using a lower cdclk w/o IPS
8128 if (IS_BROADWELL(dev_priv) &&
8129 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
8135 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
8137 struct drm_i915_private *dev_priv =
8138 to_i915(crtc_state->uapi.crtc->dev);
8139 struct intel_atomic_state *state =
8140 to_intel_atomic_state(crtc_state->uapi.state);
8142 crtc_state->ips_enabled = false;
8144 if (!hsw_crtc_state_ips_capable(crtc_state))
8148 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
8149 * enabled and disabled dynamically based on package C states,
8150 * user space can't make reliable use of the CRCs, so let's just
8151 * completely disable it.
8153 if (crtc_state->crc_enabled)
8156 /* IPS should be fine as long as at least one plane is enabled. */
8157 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8160 if (IS_BROADWELL(dev_priv)) {
8161 const struct intel_cdclk_state *cdclk_state;
8163 cdclk_state = intel_atomic_get_cdclk_state(state);
8164 if (IS_ERR(cdclk_state))
8165 return PTR_ERR(cdclk_state);
8167 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8168 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8172 crtc_state->ips_enabled = true;
8177 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8179 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8181 /* GDG double wide on either pipe, otherwise pipe A only */
8182 return INTEL_GEN(dev_priv) < 4 &&
8183 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8186 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8188 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8189 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8192 * We only use IF-ID interlacing. If we ever use
8193 * PF-ID we'll need to adjust the pixel_rate here.
8196 if (!crtc_state->pch_pfit.enabled)
8199 pipe_w = crtc_state->pipe_src_w;
8200 pipe_h = crtc_state->pipe_src_h;
8202 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8203 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8205 if (pipe_w < pfit_w)
8207 if (pipe_h < pfit_h)
8210 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8211 !pfit_w || !pfit_h))
8214 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8218 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8222 if (HAS_GMCH(dev_priv))
8223 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8224 crtc_state->pixel_rate =
8225 crtc_state->hw.adjusted_mode.crtc_clock;
8227 crtc_state->pixel_rate =
8228 ilk_pipe_pixel_rate(crtc_state);
8231 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8232 struct intel_crtc_state *pipe_config)
8234 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8235 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8236 int clock_limit = dev_priv->max_dotclk_freq;
8238 if (INTEL_GEN(dev_priv) < 4) {
8239 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8242 * Enable double wide mode when the dot clock
8243 * is > 90% of the (display) core speed.
8245 if (intel_crtc_supports_double_wide(crtc) &&
8246 adjusted_mode->crtc_clock > clock_limit) {
8247 clock_limit = dev_priv->max_dotclk_freq;
8248 pipe_config->double_wide = true;
8252 if (adjusted_mode->crtc_clock > clock_limit) {
8253 drm_dbg_kms(&dev_priv->drm,
8254 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8255 adjusted_mode->crtc_clock, clock_limit,
8256 yesno(pipe_config->double_wide));
8260 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8261 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8262 pipe_config->hw.ctm) {
8264 * There is only one pipe CSC unit per pipe, and we need that
8265 * for output conversion from RGB->YCBCR. So if CTM is already
8266 * applied we can't support YCBCR420 output.
8268 drm_dbg_kms(&dev_priv->drm,
8269 "YCBCR420 and CTM together are not possible\n");
8274 * Pipe horizontal size must be even in:
8276 * - LVDS dual channel mode
8277 * - Double wide pipe
8279 if (pipe_config->pipe_src_w & 1) {
8280 if (pipe_config->double_wide) {
8281 drm_dbg_kms(&dev_priv->drm,
8282 "Odd pipe source width not supported with double wide pipe\n");
8286 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8287 intel_is_dual_link_lvds(dev_priv)) {
8288 drm_dbg_kms(&dev_priv->drm,
8289 "Odd pipe source width not supported with dual link LVDS\n");
8294 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8295 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8297 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8298 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8301 intel_crtc_compute_pixel_rate(pipe_config);
8303 if (pipe_config->has_pch_encoder)
8304 return ilk_fdi_compute_config(crtc, pipe_config);
8310 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8312 while (*num > DATA_LINK_M_N_MASK ||
8313 *den > DATA_LINK_M_N_MASK) {
8319 static void compute_m_n(unsigned int m, unsigned int n,
8320 u32 *ret_m, u32 *ret_n,
8324 * Several DP dongles in particular seem to be fussy about
8325 * too large link M/N values. Give N value as 0x8000 that
8326 * should be acceptable by specific devices. 0x8000 is the
8327 * specified fixed N value for asynchronous clock mode,
8328 * which the devices expect also in synchronous clock mode.
8333 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8335 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8336 intel_reduce_m_n_ratio(ret_m, ret_n);
8340 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8341 int pixel_clock, int link_clock,
8342 struct intel_link_m_n *m_n,
8343 bool constant_n, bool fec_enable)
8345 u32 data_clock = bits_per_pixel * pixel_clock;
8348 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8351 compute_m_n(data_clock,
8352 link_clock * nlanes * 8,
8353 &m_n->gmch_m, &m_n->gmch_n,
8356 compute_m_n(pixel_clock, link_clock,
8357 &m_n->link_m, &m_n->link_n,
8361 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8364 * There may be no VBT; and if the BIOS enabled SSC we can
8365 * just keep using it to avoid unnecessary flicker. Whereas if the
8366 * BIOS isn't using it, don't assume it will work even if the VBT
8367 * indicates as much.
8369 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8370 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8374 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8375 drm_dbg_kms(&dev_priv->drm,
8376 "SSC %s by BIOS, overriding VBT which says %s\n",
8377 enableddisabled(bios_lvds_use_ssc),
8378 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8379 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8384 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8386 if (dev_priv->params.panel_use_ssc >= 0)
8387 return dev_priv->params.panel_use_ssc != 0;
8388 return dev_priv->vbt.lvds_use_ssc
8389 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8392 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8394 return (1 << dpll->n) << 16 | dpll->m2;
8397 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8399 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8402 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8403 struct intel_crtc_state *crtc_state,
8404 struct dpll *reduced_clock)
8406 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8409 if (IS_PINEVIEW(dev_priv)) {
8410 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8412 fp2 = pnv_dpll_compute_fp(reduced_clock);
8414 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8416 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8419 crtc_state->dpll_hw_state.fp0 = fp;
8421 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8423 crtc_state->dpll_hw_state.fp1 = fp2;
8425 crtc_state->dpll_hw_state.fp1 = fp;
8429 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8435 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8436 * and set it to a reasonable value instead.
8438 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8439 reg_val &= 0xffffff00;
8440 reg_val |= 0x00000030;
8441 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8443 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8444 reg_val &= 0x00ffffff;
8445 reg_val |= 0x8c000000;
8446 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8448 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8449 reg_val &= 0xffffff00;
8450 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8452 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8453 reg_val &= 0x00ffffff;
8454 reg_val |= 0xb0000000;
8455 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8458 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8459 const struct intel_link_m_n *m_n)
8461 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8463 enum pipe pipe = crtc->pipe;
8465 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8466 TU_SIZE(m_n->tu) | m_n->gmch_m);
8467 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8468 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8469 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8472 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8473 enum transcoder transcoder)
8475 if (IS_HASWELL(dev_priv))
8476 return transcoder == TRANSCODER_EDP;
8479 * Strictly speaking some registers are available before
8480 * gen7, but we only support DRRS on gen7+
8482 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8485 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8486 const struct intel_link_m_n *m_n,
8487 const struct intel_link_m_n *m2_n2)
8489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8491 enum pipe pipe = crtc->pipe;
8492 enum transcoder transcoder = crtc_state->cpu_transcoder;
8494 if (INTEL_GEN(dev_priv) >= 5) {
8495 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8496 TU_SIZE(m_n->tu) | m_n->gmch_m);
8497 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8499 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8501 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8504 * M2_N2 registers are set only if DRRS is supported
8505 * (to make sure the registers are not unnecessarily accessed).
8507 if (m2_n2 && crtc_state->has_drrs &&
8508 transcoder_has_m2_n2(dev_priv, transcoder)) {
8509 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8510 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8511 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8513 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8515 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8519 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8520 TU_SIZE(m_n->tu) | m_n->gmch_m);
8521 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8522 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8523 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8527 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8529 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8530 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8533 dp_m_n = &crtc_state->dp_m_n;
8534 dp_m2_n2 = &crtc_state->dp_m2_n2;
8535 } else if (m_n == M2_N2) {
8538 * M2_N2 registers are not supported. Hence m2_n2 divider value
8539 * needs to be programmed into M1_N1.
8541 dp_m_n = &crtc_state->dp_m2_n2;
8543 drm_err(&i915->drm, "Unsupported divider value\n");
8547 if (crtc_state->has_pch_encoder)
8548 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8550 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8553 static void vlv_compute_dpll(struct intel_crtc *crtc,
8554 struct intel_crtc_state *pipe_config)
8556 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8557 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8558 if (crtc->pipe != PIPE_A)
8559 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8561 /* DPLL not used with DSI, but still need the rest set up */
8562 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8563 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8564 DPLL_EXT_BUFFER_ENABLE_VLV;
8566 pipe_config->dpll_hw_state.dpll_md =
8567 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8570 static void chv_compute_dpll(struct intel_crtc *crtc,
8571 struct intel_crtc_state *pipe_config)
8573 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8574 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8575 if (crtc->pipe != PIPE_A)
8576 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8578 /* DPLL not used with DSI, but still need the rest set up */
8579 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8580 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8582 pipe_config->dpll_hw_state.dpll_md =
8583 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8586 static void vlv_prepare_pll(struct intel_crtc *crtc,
8587 const struct intel_crtc_state *pipe_config)
8589 struct drm_device *dev = crtc->base.dev;
8590 struct drm_i915_private *dev_priv = to_i915(dev);
8591 enum pipe pipe = crtc->pipe;
8593 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8594 u32 coreclk, reg_val;
8597 intel_de_write(dev_priv, DPLL(pipe),
8598 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8600 /* No need to actually set up the DPLL with DSI */
8601 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8604 vlv_dpio_get(dev_priv);
8606 bestn = pipe_config->dpll.n;
8607 bestm1 = pipe_config->dpll.m1;
8608 bestm2 = pipe_config->dpll.m2;
8609 bestp1 = pipe_config->dpll.p1;
8610 bestp2 = pipe_config->dpll.p2;
8612 /* See eDP HDMI DPIO driver vbios notes doc */
8614 /* PLL B needs special handling */
8616 vlv_pllb_recal_opamp(dev_priv, pipe);
8618 /* Set up Tx target for periodic Rcomp update */
8619 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8621 /* Disable target IRef on PLL */
8622 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8623 reg_val &= 0x00ffffff;
8624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8626 /* Disable fast lock */
8627 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8629 /* Set idtafcrecal before PLL is enabled */
8630 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8631 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8632 mdiv |= ((bestn << DPIO_N_SHIFT));
8633 mdiv |= (1 << DPIO_K_SHIFT);
8636 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8637 * but we don't support that).
8638 * Note: don't use the DAC post divider as it seems unstable.
8640 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8641 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8643 mdiv |= DPIO_ENABLE_CALIBRATION;
8644 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8646 /* Set HBR and RBR LPF coefficients */
8647 if (pipe_config->port_clock == 162000 ||
8648 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8649 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8653 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8656 if (intel_crtc_has_dp_encoder(pipe_config)) {
8657 /* Use SSC source */
8659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8662 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8664 } else { /* HDMI or VGA */
8665 /* Use bend source */
8667 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8670 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8674 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8675 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8676 if (intel_crtc_has_dp_encoder(pipe_config))
8677 coreclk |= 0x01000000;
8678 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8680 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8682 vlv_dpio_put(dev_priv);
8685 static void chv_prepare_pll(struct intel_crtc *crtc,
8686 const struct intel_crtc_state *pipe_config)
8688 struct drm_device *dev = crtc->base.dev;
8689 struct drm_i915_private *dev_priv = to_i915(dev);
8690 enum pipe pipe = crtc->pipe;
8691 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8692 u32 loopfilter, tribuf_calcntr;
8693 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8697 /* Enable Refclk and SSC */
8698 intel_de_write(dev_priv, DPLL(pipe),
8699 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8701 /* No need to actually set up the DPLL with DSI */
8702 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8705 bestn = pipe_config->dpll.n;
8706 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8707 bestm1 = pipe_config->dpll.m1;
8708 bestm2 = pipe_config->dpll.m2 >> 22;
8709 bestp1 = pipe_config->dpll.p1;
8710 bestp2 = pipe_config->dpll.p2;
8711 vco = pipe_config->dpll.vco;
8715 vlv_dpio_get(dev_priv);
8717 /* p1 and p2 divider */
8718 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8719 5 << DPIO_CHV_S1_DIV_SHIFT |
8720 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8721 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8722 1 << DPIO_CHV_K_DIV_SHIFT);
8724 /* Feedback post-divider - m2 */
8725 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8727 /* Feedback refclk divider - n and m1 */
8728 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8729 DPIO_CHV_M1_DIV_BY_2 |
8730 1 << DPIO_CHV_N_DIV_SHIFT);
8732 /* M2 fraction division */
8733 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8735 /* M2 fraction division enable */
8736 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8737 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8738 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8740 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8741 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8743 /* Program digital lock detect threshold */
8744 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8745 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8746 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8747 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8749 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8753 if (vco == 5400000) {
8754 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8755 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8756 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8757 tribuf_calcntr = 0x9;
8758 } else if (vco <= 6200000) {
8759 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8760 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8761 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8762 tribuf_calcntr = 0x9;
8763 } else if (vco <= 6480000) {
8764 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8765 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8766 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8767 tribuf_calcntr = 0x8;
8769 /* Not supported. Apply the same limits as in the max case */
8770 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8771 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8772 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8775 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8777 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8778 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8779 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8780 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8783 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8784 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8787 vlv_dpio_put(dev_priv);
8791 * vlv_force_pll_on - forcibly enable just the PLL
8792 * @dev_priv: i915 private structure
8793 * @pipe: pipe PLL to enable
8794 * @dpll: PLL configuration
8796 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8797 * in cases where we need the PLL enabled even when @pipe is not going to
8800 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8801 const struct dpll *dpll)
8803 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8804 struct intel_crtc_state *pipe_config;
8806 pipe_config = intel_crtc_state_alloc(crtc);
8810 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8811 pipe_config->pixel_multiplier = 1;
8812 pipe_config->dpll = *dpll;
8814 if (IS_CHERRYVIEW(dev_priv)) {
8815 chv_compute_dpll(crtc, pipe_config);
8816 chv_prepare_pll(crtc, pipe_config);
8817 chv_enable_pll(crtc, pipe_config);
8819 vlv_compute_dpll(crtc, pipe_config);
8820 vlv_prepare_pll(crtc, pipe_config);
8821 vlv_enable_pll(crtc, pipe_config);
8830 * vlv_force_pll_off - forcibly disable just the PLL
8831 * @dev_priv: i915 private structure
8832 * @pipe: pipe PLL to disable
8834 * Disable the PLL for @pipe. To be used in cases where we need
8835 * the PLL enabled even when @pipe is not going to be enabled.
8837 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8839 if (IS_CHERRYVIEW(dev_priv))
8840 chv_disable_pll(dev_priv, pipe);
8842 vlv_disable_pll(dev_priv, pipe);
8845 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8846 struct intel_crtc_state *crtc_state,
8847 struct dpll *reduced_clock)
8849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8851 struct dpll *clock = &crtc_state->dpll;
8853 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8855 dpll = DPLL_VGA_MODE_DIS;
8857 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8858 dpll |= DPLLB_MODE_LVDS;
8860 dpll |= DPLLB_MODE_DAC_SERIAL;
8862 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8863 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8864 dpll |= (crtc_state->pixel_multiplier - 1)
8865 << SDVO_MULTIPLIER_SHIFT_HIRES;
8868 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8869 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8870 dpll |= DPLL_SDVO_HIGH_SPEED;
8872 if (intel_crtc_has_dp_encoder(crtc_state))
8873 dpll |= DPLL_SDVO_HIGH_SPEED;
8875 /* compute bitmask from p1 value */
8876 if (IS_PINEVIEW(dev_priv))
8877 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8879 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8880 if (IS_G4X(dev_priv) && reduced_clock)
8881 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8883 switch (clock->p2) {
8885 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8888 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8891 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8894 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8897 if (INTEL_GEN(dev_priv) >= 4)
8898 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8900 if (crtc_state->sdvo_tv_clock)
8901 dpll |= PLL_REF_INPUT_TVCLKINBC;
8902 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8903 intel_panel_use_ssc(dev_priv))
8904 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8906 dpll |= PLL_REF_INPUT_DREFCLK;
8908 dpll |= DPLL_VCO_ENABLE;
8909 crtc_state->dpll_hw_state.dpll = dpll;
8911 if (INTEL_GEN(dev_priv) >= 4) {
8912 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8913 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8914 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8918 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8919 struct intel_crtc_state *crtc_state,
8920 struct dpll *reduced_clock)
8922 struct drm_device *dev = crtc->base.dev;
8923 struct drm_i915_private *dev_priv = to_i915(dev);
8925 struct dpll *clock = &crtc_state->dpll;
8927 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8929 dpll = DPLL_VGA_MODE_DIS;
8931 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8932 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8935 dpll |= PLL_P1_DIVIDE_BY_TWO;
8937 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8939 dpll |= PLL_P2_DIVIDE_BY_4;
8944 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8945 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8946 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8947 * Enable) must be set to “1” in both the DPLL A Control Register
8948 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8950 * For simplicity We simply keep both bits always enabled in
8951 * both DPLLS. The spec says we should disable the DVO 2X clock
8952 * when not needed, but this seems to work fine in practice.
8954 if (IS_I830(dev_priv) ||
8955 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8956 dpll |= DPLL_DVO_2X_MODE;
8958 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8959 intel_panel_use_ssc(dev_priv))
8960 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8962 dpll |= PLL_REF_INPUT_DREFCLK;
8964 dpll |= DPLL_VCO_ENABLE;
8965 crtc_state->dpll_hw_state.dpll = dpll;
8968 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
8970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8971 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8972 enum pipe pipe = crtc->pipe;
8973 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8974 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8975 u32 crtc_vtotal, crtc_vblank_end;
8978 /* We need to be careful not to changed the adjusted mode, for otherwise
8979 * the hw state checker will get angry at the mismatch. */
8980 crtc_vtotal = adjusted_mode->crtc_vtotal;
8981 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8983 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8984 /* the chip adds 2 halflines automatically */
8986 crtc_vblank_end -= 1;
8988 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8989 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8991 vsyncshift = adjusted_mode->crtc_hsync_start -
8992 adjusted_mode->crtc_htotal / 2;
8994 vsyncshift += adjusted_mode->crtc_htotal;
8997 if (INTEL_GEN(dev_priv) > 3)
8998 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
9001 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
9002 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
9003 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
9004 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
9005 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
9006 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
9008 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
9009 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
9010 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
9011 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
9012 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
9013 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
9015 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
9016 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
9017 * documented on the DDI_FUNC_CTL register description, EDP Input Select
9019 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
9020 (pipe == PIPE_B || pipe == PIPE_C))
9021 intel_de_write(dev_priv, VTOTAL(pipe),
9022 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
9026 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
9028 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9030 enum pipe pipe = crtc->pipe;
9032 /* pipesrc controls the size that is scaled from, which should
9033 * always be the user's requested size.
9035 intel_de_write(dev_priv, PIPESRC(pipe),
9036 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
9039 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
9041 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
9042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9044 if (IS_GEN(dev_priv, 2))
9047 if (INTEL_GEN(dev_priv) >= 9 ||
9048 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
9049 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
9051 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
9054 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
9055 struct intel_crtc_state *pipe_config)
9057 struct drm_device *dev = crtc->base.dev;
9058 struct drm_i915_private *dev_priv = to_i915(dev);
9059 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
9062 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
9063 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
9064 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
9066 if (!transcoder_is_dsi(cpu_transcoder)) {
9067 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
9068 pipe_config->hw.adjusted_mode.crtc_hblank_start =
9070 pipe_config->hw.adjusted_mode.crtc_hblank_end =
9071 ((tmp >> 16) & 0xffff) + 1;
9073 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
9074 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
9075 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
9077 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
9078 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
9079 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
9081 if (!transcoder_is_dsi(cpu_transcoder)) {
9082 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
9083 pipe_config->hw.adjusted_mode.crtc_vblank_start =
9085 pipe_config->hw.adjusted_mode.crtc_vblank_end =
9086 ((tmp >> 16) & 0xffff) + 1;
9088 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
9089 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
9090 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
9092 if (intel_pipe_is_interlaced(pipe_config)) {
9093 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
9094 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
9095 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
9099 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
9100 struct intel_crtc_state *pipe_config)
9102 struct drm_device *dev = crtc->base.dev;
9103 struct drm_i915_private *dev_priv = to_i915(dev);
9106 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
9107 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
9108 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
9110 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
9111 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
9114 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
9115 struct intel_crtc_state *pipe_config)
9117 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
9118 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
9119 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
9120 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
9122 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
9123 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
9124 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
9125 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
9127 mode->flags = pipe_config->hw.adjusted_mode.flags;
9128 mode->type = DRM_MODE_TYPE_DRIVER;
9130 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
9132 drm_mode_set_name(mode);
9135 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
9137 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9138 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9143 /* we keep both pipes enabled on 830 */
9144 if (IS_I830(dev_priv))
9145 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
9147 if (crtc_state->double_wide)
9148 pipeconf |= PIPECONF_DOUBLE_WIDE;
9150 /* only g4x and later have fancy bpc/dither controls */
9151 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9152 IS_CHERRYVIEW(dev_priv)) {
9153 /* Bspec claims that we can't use dithering for 30bpp pipes. */
9154 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
9155 pipeconf |= PIPECONF_DITHER_EN |
9156 PIPECONF_DITHER_TYPE_SP;
9158 switch (crtc_state->pipe_bpp) {
9160 pipeconf |= PIPECONF_6BPC;
9163 pipeconf |= PIPECONF_8BPC;
9166 pipeconf |= PIPECONF_10BPC;
9169 /* Case prevented by intel_choose_pipe_bpp_dither. */
9174 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9175 if (INTEL_GEN(dev_priv) < 4 ||
9176 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9177 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9179 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9181 pipeconf |= PIPECONF_PROGRESSIVE;
9184 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9185 crtc_state->limited_color_range)
9186 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9188 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9190 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9192 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9193 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9196 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9197 struct intel_crtc_state *crtc_state)
9199 struct drm_device *dev = crtc->base.dev;
9200 struct drm_i915_private *dev_priv = to_i915(dev);
9201 const struct intel_limit *limit;
9204 memset(&crtc_state->dpll_hw_state, 0,
9205 sizeof(crtc_state->dpll_hw_state));
9207 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9208 if (intel_panel_use_ssc(dev_priv)) {
9209 refclk = dev_priv->vbt.lvds_ssc_freq;
9210 drm_dbg_kms(&dev_priv->drm,
9211 "using SSC reference clock of %d kHz\n",
9215 limit = &intel_limits_i8xx_lvds;
9216 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9217 limit = &intel_limits_i8xx_dvo;
9219 limit = &intel_limits_i8xx_dac;
9222 if (!crtc_state->clock_set &&
9223 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9224 refclk, NULL, &crtc_state->dpll)) {
9225 drm_err(&dev_priv->drm,
9226 "Couldn't find PLL settings for mode!\n");
9230 i8xx_compute_dpll(crtc, crtc_state, NULL);
9235 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9236 struct intel_crtc_state *crtc_state)
9238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9239 const struct intel_limit *limit;
9242 memset(&crtc_state->dpll_hw_state, 0,
9243 sizeof(crtc_state->dpll_hw_state));
9245 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9246 if (intel_panel_use_ssc(dev_priv)) {
9247 refclk = dev_priv->vbt.lvds_ssc_freq;
9248 drm_dbg_kms(&dev_priv->drm,
9249 "using SSC reference clock of %d kHz\n",
9253 if (intel_is_dual_link_lvds(dev_priv))
9254 limit = &intel_limits_g4x_dual_channel_lvds;
9256 limit = &intel_limits_g4x_single_channel_lvds;
9257 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9258 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9259 limit = &intel_limits_g4x_hdmi;
9260 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9261 limit = &intel_limits_g4x_sdvo;
9263 /* The option is for other outputs */
9264 limit = &intel_limits_i9xx_sdvo;
9267 if (!crtc_state->clock_set &&
9268 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9269 refclk, NULL, &crtc_state->dpll)) {
9270 drm_err(&dev_priv->drm,
9271 "Couldn't find PLL settings for mode!\n");
9275 i9xx_compute_dpll(crtc, crtc_state, NULL);
9280 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9281 struct intel_crtc_state *crtc_state)
9283 struct drm_device *dev = crtc->base.dev;
9284 struct drm_i915_private *dev_priv = to_i915(dev);
9285 const struct intel_limit *limit;
9288 memset(&crtc_state->dpll_hw_state, 0,
9289 sizeof(crtc_state->dpll_hw_state));
9291 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9292 if (intel_panel_use_ssc(dev_priv)) {
9293 refclk = dev_priv->vbt.lvds_ssc_freq;
9294 drm_dbg_kms(&dev_priv->drm,
9295 "using SSC reference clock of %d kHz\n",
9299 limit = &pnv_limits_lvds;
9301 limit = &pnv_limits_sdvo;
9304 if (!crtc_state->clock_set &&
9305 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9306 refclk, NULL, &crtc_state->dpll)) {
9307 drm_err(&dev_priv->drm,
9308 "Couldn't find PLL settings for mode!\n");
9312 i9xx_compute_dpll(crtc, crtc_state, NULL);
9317 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9318 struct intel_crtc_state *crtc_state)
9320 struct drm_device *dev = crtc->base.dev;
9321 struct drm_i915_private *dev_priv = to_i915(dev);
9322 const struct intel_limit *limit;
9325 memset(&crtc_state->dpll_hw_state, 0,
9326 sizeof(crtc_state->dpll_hw_state));
9328 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9329 if (intel_panel_use_ssc(dev_priv)) {
9330 refclk = dev_priv->vbt.lvds_ssc_freq;
9331 drm_dbg_kms(&dev_priv->drm,
9332 "using SSC reference clock of %d kHz\n",
9336 limit = &intel_limits_i9xx_lvds;
9338 limit = &intel_limits_i9xx_sdvo;
9341 if (!crtc_state->clock_set &&
9342 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9343 refclk, NULL, &crtc_state->dpll)) {
9344 drm_err(&dev_priv->drm,
9345 "Couldn't find PLL settings for mode!\n");
9349 i9xx_compute_dpll(crtc, crtc_state, NULL);
9354 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9355 struct intel_crtc_state *crtc_state)
9357 int refclk = 100000;
9358 const struct intel_limit *limit = &intel_limits_chv;
9359 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9361 memset(&crtc_state->dpll_hw_state, 0,
9362 sizeof(crtc_state->dpll_hw_state));
9364 if (!crtc_state->clock_set &&
9365 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9366 refclk, NULL, &crtc_state->dpll)) {
9367 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9371 chv_compute_dpll(crtc, crtc_state);
9376 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9377 struct intel_crtc_state *crtc_state)
9379 int refclk = 100000;
9380 const struct intel_limit *limit = &intel_limits_vlv;
9381 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9383 memset(&crtc_state->dpll_hw_state, 0,
9384 sizeof(crtc_state->dpll_hw_state));
9386 if (!crtc_state->clock_set &&
9387 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9388 refclk, NULL, &crtc_state->dpll)) {
9389 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9393 vlv_compute_dpll(crtc, crtc_state);
9398 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9400 if (IS_I830(dev_priv))
9403 return INTEL_GEN(dev_priv) >= 4 ||
9404 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9407 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9410 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9413 if (!i9xx_has_pfit(dev_priv))
9416 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9417 if (!(tmp & PFIT_ENABLE))
9420 /* Check whether the pfit is attached to our pipe. */
9421 if (INTEL_GEN(dev_priv) < 4) {
9422 if (crtc->pipe != PIPE_B)
9425 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9429 crtc_state->gmch_pfit.control = tmp;
9430 crtc_state->gmch_pfit.pgm_ratios =
9431 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9434 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9435 struct intel_crtc_state *pipe_config)
9437 struct drm_device *dev = crtc->base.dev;
9438 struct drm_i915_private *dev_priv = to_i915(dev);
9439 enum pipe pipe = crtc->pipe;
9442 int refclk = 100000;
9444 /* In case of DSI, DPLL will not be used */
9445 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9448 vlv_dpio_get(dev_priv);
9449 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9450 vlv_dpio_put(dev_priv);
9452 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9453 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9454 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9455 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9456 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9458 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9462 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9463 struct intel_initial_plane_config *plane_config)
9465 struct drm_device *dev = crtc->base.dev;
9466 struct drm_i915_private *dev_priv = to_i915(dev);
9467 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9468 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9470 u32 val, base, offset;
9471 int fourcc, pixel_format;
9472 unsigned int aligned_height;
9473 struct drm_framebuffer *fb;
9474 struct intel_framebuffer *intel_fb;
9476 if (!plane->get_hw_state(plane, &pipe))
9479 drm_WARN_ON(dev, pipe != crtc->pipe);
9481 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9483 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9487 fb = &intel_fb->base;
9491 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9493 if (INTEL_GEN(dev_priv) >= 4) {
9494 if (val & DISPPLANE_TILED) {
9495 plane_config->tiling = I915_TILING_X;
9496 fb->modifier = I915_FORMAT_MOD_X_TILED;
9499 if (val & DISPPLANE_ROTATE_180)
9500 plane_config->rotation = DRM_MODE_ROTATE_180;
9503 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9504 val & DISPPLANE_MIRROR)
9505 plane_config->rotation |= DRM_MODE_REFLECT_X;
9507 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9508 fourcc = i9xx_format_to_fourcc(pixel_format);
9509 fb->format = drm_format_info(fourcc);
9511 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9512 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9513 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9514 } else if (INTEL_GEN(dev_priv) >= 4) {
9515 if (plane_config->tiling)
9516 offset = intel_de_read(dev_priv,
9517 DSPTILEOFF(i9xx_plane));
9519 offset = intel_de_read(dev_priv,
9520 DSPLINOFF(i9xx_plane));
9521 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9523 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9525 plane_config->base = base;
9527 val = intel_de_read(dev_priv, PIPESRC(pipe));
9528 fb->width = ((val >> 16) & 0xfff) + 1;
9529 fb->height = ((val >> 0) & 0xfff) + 1;
9531 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9532 fb->pitches[0] = val & 0xffffffc0;
9534 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9536 plane_config->size = fb->pitches[0] * aligned_height;
9538 drm_dbg_kms(&dev_priv->drm,
9539 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9540 crtc->base.name, plane->base.name, fb->width, fb->height,
9541 fb->format->cpp[0] * 8, base, fb->pitches[0],
9542 plane_config->size);
9544 plane_config->fb = intel_fb;
9547 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9548 struct intel_crtc_state *pipe_config)
9550 struct drm_device *dev = crtc->base.dev;
9551 struct drm_i915_private *dev_priv = to_i915(dev);
9552 enum pipe pipe = crtc->pipe;
9553 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9555 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9556 int refclk = 100000;
9558 /* In case of DSI, DPLL will not be used */
9559 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9562 vlv_dpio_get(dev_priv);
9563 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9564 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9565 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9566 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9567 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9568 vlv_dpio_put(dev_priv);
9570 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9571 clock.m2 = (pll_dw0 & 0xff) << 22;
9572 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9573 clock.m2 |= pll_dw2 & 0x3fffff;
9574 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9575 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9576 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9578 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9581 static enum intel_output_format
9582 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9587 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9589 if (tmp & PIPEMISC_YUV420_ENABLE) {
9590 /* We support 4:2:0 in full blend mode only */
9591 drm_WARN_ON(&dev_priv->drm,
9592 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9594 return INTEL_OUTPUT_FORMAT_YCBCR420;
9595 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9596 return INTEL_OUTPUT_FORMAT_YCBCR444;
9598 return INTEL_OUTPUT_FORMAT_RGB;
9602 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9605 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9607 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9610 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9612 if (tmp & DISPPLANE_GAMMA_ENABLE)
9613 crtc_state->gamma_enable = true;
9615 if (!HAS_GMCH(dev_priv) &&
9616 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9617 crtc_state->csc_enable = true;
9620 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9621 struct intel_crtc_state *pipe_config)
9623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9624 enum intel_display_power_domain power_domain;
9625 intel_wakeref_t wakeref;
9629 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9630 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9634 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9635 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9636 pipe_config->shared_dpll = NULL;
9640 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9641 if (!(tmp & PIPECONF_ENABLE))
9644 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9645 IS_CHERRYVIEW(dev_priv)) {
9646 switch (tmp & PIPECONF_BPC_MASK) {
9648 pipe_config->pipe_bpp = 18;
9651 pipe_config->pipe_bpp = 24;
9653 case PIPECONF_10BPC:
9654 pipe_config->pipe_bpp = 30;
9661 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9662 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9663 pipe_config->limited_color_range = true;
9665 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9666 PIPECONF_GAMMA_MODE_SHIFT;
9668 if (IS_CHERRYVIEW(dev_priv))
9669 pipe_config->cgm_mode = intel_de_read(dev_priv,
9670 CGM_PIPE_MODE(crtc->pipe));
9672 i9xx_get_pipe_color_config(pipe_config);
9673 intel_color_get_config(pipe_config);
9675 if (INTEL_GEN(dev_priv) < 4)
9676 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9678 intel_get_transcoder_timings(crtc, pipe_config);
9679 intel_get_pipe_src_size(crtc, pipe_config);
9681 i9xx_get_pfit_config(pipe_config);
9683 if (INTEL_GEN(dev_priv) >= 4) {
9684 /* No way to read it out on pipes B and C */
9685 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9686 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9688 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9689 pipe_config->pixel_multiplier =
9690 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9691 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9692 pipe_config->dpll_hw_state.dpll_md = tmp;
9693 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9694 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9695 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9696 pipe_config->pixel_multiplier =
9697 ((tmp & SDVO_MULTIPLIER_MASK)
9698 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9700 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9701 * port and will be fixed up in the encoder->get_config
9703 pipe_config->pixel_multiplier = 1;
9705 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9707 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9708 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9710 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9713 /* Mask out read-only status bits. */
9714 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9715 DPLL_PORTC_READY_MASK |
9716 DPLL_PORTB_READY_MASK);
9719 if (IS_CHERRYVIEW(dev_priv))
9720 chv_crtc_clock_get(crtc, pipe_config);
9721 else if (IS_VALLEYVIEW(dev_priv))
9722 vlv_crtc_clock_get(crtc, pipe_config);
9724 i9xx_crtc_clock_get(crtc, pipe_config);
9727 * Normally the dotclock is filled in by the encoder .get_config()
9728 * but in case the pipe is enabled w/o any ports we need a sane
9731 pipe_config->hw.adjusted_mode.crtc_clock =
9732 pipe_config->port_clock / pipe_config->pixel_multiplier;
9737 intel_display_power_put(dev_priv, power_domain, wakeref);
9742 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9744 struct intel_encoder *encoder;
9747 bool has_lvds = false;
9748 bool has_cpu_edp = false;
9749 bool has_panel = false;
9750 bool has_ck505 = false;
9751 bool can_ssc = false;
9752 bool using_ssc_source = false;
9754 /* We need to take the global config into account */
9755 for_each_intel_encoder(&dev_priv->drm, encoder) {
9756 switch (encoder->type) {
9757 case INTEL_OUTPUT_LVDS:
9761 case INTEL_OUTPUT_EDP:
9763 if (encoder->port == PORT_A)
9771 if (HAS_PCH_IBX(dev_priv)) {
9772 has_ck505 = dev_priv->vbt.display_clock_mode;
9773 can_ssc = has_ck505;
9779 /* Check if any DPLLs are using the SSC source */
9780 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9781 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9783 if (!(temp & DPLL_VCO_ENABLE))
9786 if ((temp & PLL_REF_INPUT_MASK) ==
9787 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9788 using_ssc_source = true;
9793 drm_dbg_kms(&dev_priv->drm,
9794 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9795 has_panel, has_lvds, has_ck505, using_ssc_source);
9797 /* Ironlake: try to setup display ref clock before DPLL
9798 * enabling. This is only under driver's control after
9799 * PCH B stepping, previous chipset stepping should be
9800 * ignoring this setting.
9802 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9804 /* As we must carefully and slowly disable/enable each source in turn,
9805 * compute the final state we want first and check if we need to
9806 * make any changes at all.
9809 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9811 final |= DREF_NONSPREAD_CK505_ENABLE;
9813 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9815 final &= ~DREF_SSC_SOURCE_MASK;
9816 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9817 final &= ~DREF_SSC1_ENABLE;
9820 final |= DREF_SSC_SOURCE_ENABLE;
9822 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9823 final |= DREF_SSC1_ENABLE;
9826 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9827 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9829 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9831 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9832 } else if (using_ssc_source) {
9833 final |= DREF_SSC_SOURCE_ENABLE;
9834 final |= DREF_SSC1_ENABLE;
9840 /* Always enable nonspread source */
9841 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9844 val |= DREF_NONSPREAD_CK505_ENABLE;
9846 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9849 val &= ~DREF_SSC_SOURCE_MASK;
9850 val |= DREF_SSC_SOURCE_ENABLE;
9852 /* SSC must be turned on before enabling the CPU output */
9853 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9854 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9855 val |= DREF_SSC1_ENABLE;
9857 val &= ~DREF_SSC1_ENABLE;
9859 /* Get SSC going before enabling the outputs */
9860 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9861 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9864 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9866 /* Enable CPU source on CPU attached eDP */
9868 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9869 drm_dbg_kms(&dev_priv->drm,
9870 "Using SSC on eDP\n");
9871 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9873 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9875 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9877 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9878 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9881 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9883 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9885 /* Turn off CPU output */
9886 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9888 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9889 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9892 if (!using_ssc_source) {
9893 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9895 /* Turn off the SSC source */
9896 val &= ~DREF_SSC_SOURCE_MASK;
9897 val |= DREF_SSC_SOURCE_DISABLE;
9900 val &= ~DREF_SSC1_ENABLE;
9902 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9903 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9908 BUG_ON(val != final);
9911 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9915 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9916 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9917 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9919 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9920 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9921 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9923 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9924 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9925 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9927 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9928 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9929 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9932 /* WaMPhyProgramming:hsw */
9933 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9937 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9938 tmp &= ~(0xFF << 24);
9939 tmp |= (0x12 << 24);
9940 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9942 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9944 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9946 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9948 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9950 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9951 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9952 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9954 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9955 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9956 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9958 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9961 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9963 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9966 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9968 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9971 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9973 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9976 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9978 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9979 tmp &= ~(0xFF << 16);
9980 tmp |= (0x1C << 16);
9981 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9983 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9984 tmp &= ~(0xFF << 16);
9985 tmp |= (0x1C << 16);
9986 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9988 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9990 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9992 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9994 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9996 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9997 tmp &= ~(0xF << 28);
9999 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
10001 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
10002 tmp &= ~(0xF << 28);
10004 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
10007 /* Implements 3 different sequences from BSpec chapter "Display iCLK
10008 * Programming" based on the parameters passed:
10009 * - Sequence to enable CLKOUT_DP
10010 * - Sequence to enable CLKOUT_DP without spread
10011 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
10013 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
10014 bool with_spread, bool with_fdi)
10018 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
10019 "FDI requires downspread\n"))
10020 with_spread = true;
10021 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
10022 with_fdi, "LP PCH doesn't have FDI\n"))
10025 mutex_lock(&dev_priv->sb_lock);
10027 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10028 tmp &= ~SBI_SSCCTL_DISABLE;
10029 tmp |= SBI_SSCCTL_PATHALT;
10030 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10035 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10036 tmp &= ~SBI_SSCCTL_PATHALT;
10037 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10040 lpt_reset_fdi_mphy(dev_priv);
10041 lpt_program_fdi_mphy(dev_priv);
10045 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
10046 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
10047 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
10048 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
10050 mutex_unlock(&dev_priv->sb_lock);
10053 /* Sequence to disable CLKOUT_DP */
10054 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
10058 mutex_lock(&dev_priv->sb_lock);
10060 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
10061 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
10062 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
10063 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
10065 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
10066 if (!(tmp & SBI_SSCCTL_DISABLE)) {
10067 if (!(tmp & SBI_SSCCTL_PATHALT)) {
10068 tmp |= SBI_SSCCTL_PATHALT;
10069 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10072 tmp |= SBI_SSCCTL_DISABLE;
10073 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
10076 mutex_unlock(&dev_priv->sb_lock);
10079 #define BEND_IDX(steps) ((50 + (steps)) / 5)
10081 static const u16 sscdivintphase[] = {
10082 [BEND_IDX( 50)] = 0x3B23,
10083 [BEND_IDX( 45)] = 0x3B23,
10084 [BEND_IDX( 40)] = 0x3C23,
10085 [BEND_IDX( 35)] = 0x3C23,
10086 [BEND_IDX( 30)] = 0x3D23,
10087 [BEND_IDX( 25)] = 0x3D23,
10088 [BEND_IDX( 20)] = 0x3E23,
10089 [BEND_IDX( 15)] = 0x3E23,
10090 [BEND_IDX( 10)] = 0x3F23,
10091 [BEND_IDX( 5)] = 0x3F23,
10092 [BEND_IDX( 0)] = 0x0025,
10093 [BEND_IDX( -5)] = 0x0025,
10094 [BEND_IDX(-10)] = 0x0125,
10095 [BEND_IDX(-15)] = 0x0125,
10096 [BEND_IDX(-20)] = 0x0225,
10097 [BEND_IDX(-25)] = 0x0225,
10098 [BEND_IDX(-30)] = 0x0325,
10099 [BEND_IDX(-35)] = 0x0325,
10100 [BEND_IDX(-40)] = 0x0425,
10101 [BEND_IDX(-45)] = 0x0425,
10102 [BEND_IDX(-50)] = 0x0525,
10107 * steps -50 to 50 inclusive, in steps of 5
10108 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
10109 * change in clock period = -(steps / 10) * 5.787 ps
10111 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
10114 int idx = BEND_IDX(steps);
10116 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
10119 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
10122 mutex_lock(&dev_priv->sb_lock);
10124 if (steps % 10 != 0)
10128 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
10130 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
10132 tmp |= sscdivintphase[idx];
10133 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
10135 mutex_unlock(&dev_priv->sb_lock);
10140 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
10142 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10143 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
10145 if ((ctl & SPLL_PLL_ENABLE) == 0)
10148 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
10149 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10152 if (IS_BROADWELL(dev_priv) &&
10153 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10159 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10160 enum intel_dpll_id id)
10162 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10163 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10165 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10168 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10171 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10172 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10173 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10179 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10181 struct intel_encoder *encoder;
10182 bool has_fdi = false;
10184 for_each_intel_encoder(&dev_priv->drm, encoder) {
10185 switch (encoder->type) {
10186 case INTEL_OUTPUT_ANALOG:
10195 * The BIOS may have decided to use the PCH SSC
10196 * reference so we must not disable it until the
10197 * relevant PLLs have stopped relying on it. We'll
10198 * just leave the PCH SSC reference enabled in case
10199 * any active PLL is using it. It will get disabled
10200 * after runtime suspend if we don't have FDI.
10202 * TODO: Move the whole reference clock handling
10203 * to the modeset sequence proper so that we can
10204 * actually enable/disable/reconfigure these things
10205 * safely. To do that we need to introduce a real
10206 * clock hierarchy. That would also allow us to do
10207 * clock bending finally.
10209 dev_priv->pch_ssc_use = 0;
10211 if (spll_uses_pch_ssc(dev_priv)) {
10212 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10213 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10216 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10217 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10218 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10221 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10222 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10223 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10226 if (dev_priv->pch_ssc_use)
10230 lpt_bend_clkout_dp(dev_priv, 0);
10231 lpt_enable_clkout_dp(dev_priv, true, true);
10233 lpt_disable_clkout_dp(dev_priv);
10238 * Initialize reference clocks when the driver loads
10240 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10242 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10243 ilk_init_pch_refclk(dev_priv);
10244 else if (HAS_PCH_LPT(dev_priv))
10245 lpt_init_pch_refclk(dev_priv);
10248 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10251 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10252 enum pipe pipe = crtc->pipe;
10257 switch (crtc_state->pipe_bpp) {
10259 val |= PIPECONF_6BPC;
10262 val |= PIPECONF_8BPC;
10265 val |= PIPECONF_10BPC;
10268 val |= PIPECONF_12BPC;
10271 /* Case prevented by intel_choose_pipe_bpp_dither. */
10275 if (crtc_state->dither)
10276 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10278 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10279 val |= PIPECONF_INTERLACED_ILK;
10281 val |= PIPECONF_PROGRESSIVE;
10284 * This would end up with an odd purple hue over
10285 * the entire display. Make sure we don't do it.
10287 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10288 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10290 if (crtc_state->limited_color_range &&
10291 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10292 val |= PIPECONF_COLOR_RANGE_SELECT;
10294 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10295 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10297 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10299 val |= PIPECONF_FRAME_START_DELAY(0);
10301 intel_de_write(dev_priv, PIPECONF(pipe), val);
10302 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10305 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10308 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10309 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10312 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10313 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10315 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10316 val |= PIPECONF_INTERLACED_ILK;
10318 val |= PIPECONF_PROGRESSIVE;
10320 if (IS_HASWELL(dev_priv) &&
10321 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10322 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10324 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10325 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10328 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10330 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10334 switch (crtc_state->pipe_bpp) {
10336 val |= PIPEMISC_DITHER_6_BPC;
10339 val |= PIPEMISC_DITHER_8_BPC;
10342 val |= PIPEMISC_DITHER_10_BPC;
10345 val |= PIPEMISC_DITHER_12_BPC;
10348 MISSING_CASE(crtc_state->pipe_bpp);
10352 if (crtc_state->dither)
10353 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10355 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10356 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10357 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10359 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10360 val |= PIPEMISC_YUV420_ENABLE |
10361 PIPEMISC_YUV420_MODE_FULL_BLEND;
10363 if (INTEL_GEN(dev_priv) >= 11 &&
10364 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10365 BIT(PLANE_CURSOR))) == 0)
10366 val |= PIPEMISC_HDR_MODE_PRECISION;
10368 if (INTEL_GEN(dev_priv) >= 12)
10369 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10371 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10374 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10379 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10381 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10382 case PIPEMISC_DITHER_6_BPC:
10384 case PIPEMISC_DITHER_8_BPC:
10386 case PIPEMISC_DITHER_10_BPC:
10388 case PIPEMISC_DITHER_12_BPC:
10396 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10399 * Account for spread spectrum to avoid
10400 * oversubscribing the link. Max center spread
10401 * is 2.5%; use 5% for safety's sake.
10403 u32 bps = target_clock * bpp * 21 / 20;
10404 return DIV_ROUND_UP(bps, link_bw * 8);
10407 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10409 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10412 static void ilk_compute_dpll(struct intel_crtc *crtc,
10413 struct intel_crtc_state *crtc_state,
10414 struct dpll *reduced_clock)
10416 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10420 /* Enable autotuning of the PLL clock (if permissible) */
10422 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10423 if ((intel_panel_use_ssc(dev_priv) &&
10424 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10425 (HAS_PCH_IBX(dev_priv) &&
10426 intel_is_dual_link_lvds(dev_priv)))
10428 } else if (crtc_state->sdvo_tv_clock) {
10432 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10434 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10437 if (reduced_clock) {
10438 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10440 if (reduced_clock->m < factor * reduced_clock->n)
10448 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10449 dpll |= DPLLB_MODE_LVDS;
10451 dpll |= DPLLB_MODE_DAC_SERIAL;
10453 dpll |= (crtc_state->pixel_multiplier - 1)
10454 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10456 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10457 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10458 dpll |= DPLL_SDVO_HIGH_SPEED;
10460 if (intel_crtc_has_dp_encoder(crtc_state))
10461 dpll |= DPLL_SDVO_HIGH_SPEED;
10464 * The high speed IO clock is only really required for
10465 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10466 * possible to share the DPLL between CRT and HDMI. Enabling
10467 * the clock needlessly does no real harm, except use up a
10468 * bit of power potentially.
10470 * We'll limit this to IVB with 3 pipes, since it has only two
10471 * DPLLs and so DPLL sharing is the only way to get three pipes
10472 * driving PCH ports at the same time. On SNB we could do this,
10473 * and potentially avoid enabling the second DPLL, but it's not
10474 * clear if it''s a win or loss power wise. No point in doing
10475 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10477 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10478 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10479 dpll |= DPLL_SDVO_HIGH_SPEED;
10481 /* compute bitmask from p1 value */
10482 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10484 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10486 switch (crtc_state->dpll.p2) {
10488 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10491 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10494 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10497 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10501 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10502 intel_panel_use_ssc(dev_priv))
10503 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10505 dpll |= PLL_REF_INPUT_DREFCLK;
10507 dpll |= DPLL_VCO_ENABLE;
10509 crtc_state->dpll_hw_state.dpll = dpll;
10510 crtc_state->dpll_hw_state.fp0 = fp;
10511 crtc_state->dpll_hw_state.fp1 = fp2;
10514 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10515 struct intel_crtc_state *crtc_state)
10517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10518 struct intel_atomic_state *state =
10519 to_intel_atomic_state(crtc_state->uapi.state);
10520 const struct intel_limit *limit;
10521 int refclk = 120000;
10523 memset(&crtc_state->dpll_hw_state, 0,
10524 sizeof(crtc_state->dpll_hw_state));
10526 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10527 if (!crtc_state->has_pch_encoder)
10530 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10531 if (intel_panel_use_ssc(dev_priv)) {
10532 drm_dbg_kms(&dev_priv->drm,
10533 "using SSC reference clock of %d kHz\n",
10534 dev_priv->vbt.lvds_ssc_freq);
10535 refclk = dev_priv->vbt.lvds_ssc_freq;
10538 if (intel_is_dual_link_lvds(dev_priv)) {
10539 if (refclk == 100000)
10540 limit = &ilk_limits_dual_lvds_100m;
10542 limit = &ilk_limits_dual_lvds;
10544 if (refclk == 100000)
10545 limit = &ilk_limits_single_lvds_100m;
10547 limit = &ilk_limits_single_lvds;
10550 limit = &ilk_limits_dac;
10553 if (!crtc_state->clock_set &&
10554 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10555 refclk, NULL, &crtc_state->dpll)) {
10556 drm_err(&dev_priv->drm,
10557 "Couldn't find PLL settings for mode!\n");
10561 ilk_compute_dpll(crtc, crtc_state, NULL);
10563 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10564 drm_dbg_kms(&dev_priv->drm,
10565 "failed to find PLL for pipe %c\n",
10566 pipe_name(crtc->pipe));
10573 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10574 struct intel_link_m_n *m_n)
10576 struct drm_device *dev = crtc->base.dev;
10577 struct drm_i915_private *dev_priv = to_i915(dev);
10578 enum pipe pipe = crtc->pipe;
10580 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10581 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10582 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10584 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10585 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10586 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10589 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10590 enum transcoder transcoder,
10591 struct intel_link_m_n *m_n,
10592 struct intel_link_m_n *m2_n2)
10594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10595 enum pipe pipe = crtc->pipe;
10597 if (INTEL_GEN(dev_priv) >= 5) {
10598 m_n->link_m = intel_de_read(dev_priv,
10599 PIPE_LINK_M1(transcoder));
10600 m_n->link_n = intel_de_read(dev_priv,
10601 PIPE_LINK_N1(transcoder));
10602 m_n->gmch_m = intel_de_read(dev_priv,
10603 PIPE_DATA_M1(transcoder))
10605 m_n->gmch_n = intel_de_read(dev_priv,
10606 PIPE_DATA_N1(transcoder));
10607 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10608 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10610 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10611 m2_n2->link_m = intel_de_read(dev_priv,
10612 PIPE_LINK_M2(transcoder));
10613 m2_n2->link_n = intel_de_read(dev_priv,
10614 PIPE_LINK_N2(transcoder));
10615 m2_n2->gmch_m = intel_de_read(dev_priv,
10616 PIPE_DATA_M2(transcoder))
10618 m2_n2->gmch_n = intel_de_read(dev_priv,
10619 PIPE_DATA_N2(transcoder));
10620 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10621 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10624 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10625 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10626 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10628 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10629 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10630 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10634 void intel_dp_get_m_n(struct intel_crtc *crtc,
10635 struct intel_crtc_state *pipe_config)
10637 if (pipe_config->has_pch_encoder)
10638 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10640 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10641 &pipe_config->dp_m_n,
10642 &pipe_config->dp_m2_n2);
10645 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10646 struct intel_crtc_state *pipe_config)
10648 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10649 &pipe_config->fdi_m_n, NULL);
10652 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10655 drm_rect_init(&crtc_state->pch_pfit.dst,
10656 pos >> 16, pos & 0xffff,
10657 size >> 16, size & 0xffff);
10660 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10662 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10663 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10664 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10668 /* find scaler attached to this pipe */
10669 for (i = 0; i < crtc->num_scalers; i++) {
10670 u32 ctl, pos, size;
10672 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10673 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10677 crtc_state->pch_pfit.enabled = true;
10679 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10680 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10682 ilk_get_pfit_pos_size(crtc_state, pos, size);
10684 scaler_state->scalers[i].in_use = true;
10688 scaler_state->scaler_id = id;
10690 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10692 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10696 skl_get_initial_plane_config(struct intel_crtc *crtc,
10697 struct intel_initial_plane_config *plane_config)
10699 struct drm_device *dev = crtc->base.dev;
10700 struct drm_i915_private *dev_priv = to_i915(dev);
10701 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10702 enum plane_id plane_id = plane->id;
10704 u32 val, base, offset, stride_mult, tiling, alpha;
10705 int fourcc, pixel_format;
10706 unsigned int aligned_height;
10707 struct drm_framebuffer *fb;
10708 struct intel_framebuffer *intel_fb;
10710 if (!plane->get_hw_state(plane, &pipe))
10713 drm_WARN_ON(dev, pipe != crtc->pipe);
10715 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10717 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10721 fb = &intel_fb->base;
10725 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10727 if (INTEL_GEN(dev_priv) >= 11)
10728 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10730 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10732 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10733 alpha = intel_de_read(dev_priv,
10734 PLANE_COLOR_CTL(pipe, plane_id));
10735 alpha &= PLANE_COLOR_ALPHA_MASK;
10737 alpha = val & PLANE_CTL_ALPHA_MASK;
10740 fourcc = skl_format_to_fourcc(pixel_format,
10741 val & PLANE_CTL_ORDER_RGBX, alpha);
10742 fb->format = drm_format_info(fourcc);
10744 tiling = val & PLANE_CTL_TILED_MASK;
10746 case PLANE_CTL_TILED_LINEAR:
10747 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10749 case PLANE_CTL_TILED_X:
10750 plane_config->tiling = I915_TILING_X;
10751 fb->modifier = I915_FORMAT_MOD_X_TILED;
10753 case PLANE_CTL_TILED_Y:
10754 plane_config->tiling = I915_TILING_Y;
10755 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10756 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10757 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10758 I915_FORMAT_MOD_Y_TILED_CCS;
10759 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10760 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10762 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10764 case PLANE_CTL_TILED_YF:
10765 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10766 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10768 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10771 MISSING_CASE(tiling);
10776 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10777 * while i915 HW rotation is clockwise, thats why this swapping.
10779 switch (val & PLANE_CTL_ROTATE_MASK) {
10780 case PLANE_CTL_ROTATE_0:
10781 plane_config->rotation = DRM_MODE_ROTATE_0;
10783 case PLANE_CTL_ROTATE_90:
10784 plane_config->rotation = DRM_MODE_ROTATE_270;
10786 case PLANE_CTL_ROTATE_180:
10787 plane_config->rotation = DRM_MODE_ROTATE_180;
10789 case PLANE_CTL_ROTATE_270:
10790 plane_config->rotation = DRM_MODE_ROTATE_90;
10794 if (INTEL_GEN(dev_priv) >= 10 &&
10795 val & PLANE_CTL_FLIP_HORIZONTAL)
10796 plane_config->rotation |= DRM_MODE_REFLECT_X;
10798 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10799 plane_config->base = base;
10801 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10803 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10804 fb->height = ((val >> 16) & 0xffff) + 1;
10805 fb->width = ((val >> 0) & 0xffff) + 1;
10807 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10808 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10809 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10811 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10813 plane_config->size = fb->pitches[0] * aligned_height;
10815 drm_dbg_kms(&dev_priv->drm,
10816 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10817 crtc->base.name, plane->base.name, fb->width, fb->height,
10818 fb->format->cpp[0] * 8, base, fb->pitches[0],
10819 plane_config->size);
10821 plane_config->fb = intel_fb;
10828 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10832 u32 ctl, pos, size;
10834 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10835 if ((ctl & PF_ENABLE) == 0)
10838 crtc_state->pch_pfit.enabled = true;
10840 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10841 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10843 ilk_get_pfit_pos_size(crtc_state, pos, size);
10846 * We currently do not free assignements of panel fitters on
10847 * ivb/hsw (since we don't use the higher upscaling modes which
10848 * differentiates them) so just WARN about this case for now.
10850 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10851 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10854 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10855 struct intel_crtc_state *pipe_config)
10857 struct drm_device *dev = crtc->base.dev;
10858 struct drm_i915_private *dev_priv = to_i915(dev);
10859 enum intel_display_power_domain power_domain;
10860 intel_wakeref_t wakeref;
10864 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10865 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10869 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10870 pipe_config->shared_dpll = NULL;
10873 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10874 if (!(tmp & PIPECONF_ENABLE))
10877 switch (tmp & PIPECONF_BPC_MASK) {
10878 case PIPECONF_6BPC:
10879 pipe_config->pipe_bpp = 18;
10881 case PIPECONF_8BPC:
10882 pipe_config->pipe_bpp = 24;
10884 case PIPECONF_10BPC:
10885 pipe_config->pipe_bpp = 30;
10887 case PIPECONF_12BPC:
10888 pipe_config->pipe_bpp = 36;
10894 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10895 pipe_config->limited_color_range = true;
10897 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10898 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10899 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10900 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10903 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10907 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10908 PIPECONF_GAMMA_MODE_SHIFT;
10910 pipe_config->csc_mode = intel_de_read(dev_priv,
10911 PIPE_CSC_MODE(crtc->pipe));
10913 i9xx_get_pipe_color_config(pipe_config);
10914 intel_color_get_config(pipe_config);
10916 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10917 struct intel_shared_dpll *pll;
10918 enum intel_dpll_id pll_id;
10920 pipe_config->has_pch_encoder = true;
10922 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10924 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10926 ilk_get_fdi_m_n_config(crtc, pipe_config);
10928 if (HAS_PCH_IBX(dev_priv)) {
10930 * The pipe->pch transcoder and pch transcoder->pll
10931 * mapping is fixed.
10933 pll_id = (enum intel_dpll_id) crtc->pipe;
10935 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10936 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10937 pll_id = DPLL_ID_PCH_PLL_B;
10939 pll_id= DPLL_ID_PCH_PLL_A;
10942 pipe_config->shared_dpll =
10943 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10944 pll = pipe_config->shared_dpll;
10946 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10947 &pipe_config->dpll_hw_state));
10949 tmp = pipe_config->dpll_hw_state.dpll;
10950 pipe_config->pixel_multiplier =
10951 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10952 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10954 ilk_pch_clock_get(crtc, pipe_config);
10956 pipe_config->pixel_multiplier = 1;
10959 intel_get_transcoder_timings(crtc, pipe_config);
10960 intel_get_pipe_src_size(crtc, pipe_config);
10962 ilk_get_pfit_config(pipe_config);
10967 intel_display_power_put(dev_priv, power_domain, wakeref);
10972 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10973 struct intel_crtc_state *crtc_state)
10975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10976 struct intel_atomic_state *state =
10977 to_intel_atomic_state(crtc_state->uapi.state);
10979 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10980 INTEL_GEN(dev_priv) >= 11) {
10981 struct intel_encoder *encoder =
10982 intel_get_crtc_new_encoder(state, crtc_state);
10984 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10985 drm_dbg_kms(&dev_priv->drm,
10986 "failed to find PLL for pipe %c\n",
10987 pipe_name(crtc->pipe));
10995 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10996 struct intel_crtc_state *pipe_config)
10998 enum intel_dpll_id id;
11001 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
11002 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
11004 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
11007 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11010 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11011 struct intel_crtc_state *pipe_config)
11013 enum phy phy = intel_port_to_phy(dev_priv, port);
11014 enum icl_port_dpll_id port_dpll_id;
11015 enum intel_dpll_id id;
11018 if (intel_phy_is_combo(dev_priv, phy)) {
11021 if (IS_ROCKETLAKE(dev_priv)) {
11022 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
11023 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
11025 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
11026 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
11029 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
11030 id = temp >> shift;
11031 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
11032 } else if (intel_phy_is_tc(dev_priv, phy)) {
11033 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
11035 if (clk_sel == DDI_CLK_SEL_MG) {
11036 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
11038 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
11040 drm_WARN_ON(&dev_priv->drm,
11041 clk_sel < DDI_CLK_SEL_TBT_162);
11042 id = DPLL_ID_ICL_TBTPLL;
11043 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
11046 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
11050 pipe_config->icl_port_dplls[port_dpll_id].pll =
11051 intel_get_shared_dpll_by_id(dev_priv, id);
11053 icl_set_active_port_dpll(pipe_config, port_dpll_id);
11056 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
11058 struct intel_crtc_state *pipe_config)
11060 enum intel_dpll_id id;
11064 id = DPLL_ID_SKL_DPLL0;
11067 id = DPLL_ID_SKL_DPLL1;
11070 id = DPLL_ID_SKL_DPLL2;
11073 drm_err(&dev_priv->drm, "Incorrect port type\n");
11077 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11080 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11081 struct intel_crtc_state *pipe_config)
11083 enum intel_dpll_id id;
11086 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
11087 id = temp >> (port * 3 + 1);
11089 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
11092 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11095 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11096 struct intel_crtc_state *pipe_config)
11098 enum intel_dpll_id id;
11099 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
11101 switch (ddi_pll_sel) {
11102 case PORT_CLK_SEL_WRPLL1:
11103 id = DPLL_ID_WRPLL1;
11105 case PORT_CLK_SEL_WRPLL2:
11106 id = DPLL_ID_WRPLL2;
11108 case PORT_CLK_SEL_SPLL:
11111 case PORT_CLK_SEL_LCPLL_810:
11112 id = DPLL_ID_LCPLL_810;
11114 case PORT_CLK_SEL_LCPLL_1350:
11115 id = DPLL_ID_LCPLL_1350;
11117 case PORT_CLK_SEL_LCPLL_2700:
11118 id = DPLL_ID_LCPLL_2700;
11121 MISSING_CASE(ddi_pll_sel);
11123 case PORT_CLK_SEL_NONE:
11127 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11130 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
11131 struct intel_crtc_state *pipe_config,
11132 u64 *power_domain_mask,
11133 intel_wakeref_t *wakerefs)
11135 struct drm_device *dev = crtc->base.dev;
11136 struct drm_i915_private *dev_priv = to_i915(dev);
11137 enum intel_display_power_domain power_domain;
11138 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
11139 unsigned long enabled_panel_transcoders = 0;
11140 enum transcoder panel_transcoder;
11141 intel_wakeref_t wf;
11144 if (INTEL_GEN(dev_priv) >= 11)
11145 panel_transcoder_mask |=
11146 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
11149 * The pipe->transcoder mapping is fixed with the exception of the eDP
11150 * and DSI transcoders handled below.
11152 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11155 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11156 * consistency and less surprising code; it's in always on power).
11158 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11159 panel_transcoder_mask) {
11160 bool force_thru = false;
11161 enum pipe trans_pipe;
11163 tmp = intel_de_read(dev_priv,
11164 TRANS_DDI_FUNC_CTL(panel_transcoder));
11165 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11169 * Log all enabled ones, only use the first one.
11171 * FIXME: This won't work for two separate DSI displays.
11173 enabled_panel_transcoders |= BIT(panel_transcoder);
11174 if (enabled_panel_transcoders != BIT(panel_transcoder))
11177 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11180 "unknown pipe linked to transcoder %s\n",
11181 transcoder_name(panel_transcoder));
11183 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11186 case TRANS_DDI_EDP_INPUT_A_ON:
11187 trans_pipe = PIPE_A;
11189 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11190 trans_pipe = PIPE_B;
11192 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11193 trans_pipe = PIPE_C;
11195 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11196 trans_pipe = PIPE_D;
11200 if (trans_pipe == crtc->pipe) {
11201 pipe_config->cpu_transcoder = panel_transcoder;
11202 pipe_config->pch_pfit.force_thru = force_thru;
11207 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11209 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11210 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11212 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11213 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11215 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11219 wakerefs[power_domain] = wf;
11220 *power_domain_mask |= BIT_ULL(power_domain);
11222 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11224 return tmp & PIPECONF_ENABLE;
11227 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11228 struct intel_crtc_state *pipe_config,
11229 u64 *power_domain_mask,
11230 intel_wakeref_t *wakerefs)
11232 struct drm_device *dev = crtc->base.dev;
11233 struct drm_i915_private *dev_priv = to_i915(dev);
11234 enum intel_display_power_domain power_domain;
11235 enum transcoder cpu_transcoder;
11236 intel_wakeref_t wf;
11240 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11241 if (port == PORT_A)
11242 cpu_transcoder = TRANSCODER_DSI_A;
11244 cpu_transcoder = TRANSCODER_DSI_C;
11246 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11247 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11249 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11253 wakerefs[power_domain] = wf;
11254 *power_domain_mask |= BIT_ULL(power_domain);
11257 * The PLL needs to be enabled with a valid divider
11258 * configuration, otherwise accessing DSI registers will hang
11259 * the machine. See BSpec North Display Engine
11260 * registers/MIPI[BXT]. We can break out here early, since we
11261 * need the same DSI PLL to be enabled for both DSI ports.
11263 if (!bxt_dsi_pll_is_enabled(dev_priv))
11266 /* XXX: this works for video mode only */
11267 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11268 if (!(tmp & DPI_ENABLE))
11271 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11272 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11275 pipe_config->cpu_transcoder = cpu_transcoder;
11279 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11282 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11283 struct intel_crtc_state *pipe_config)
11285 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11286 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11287 struct intel_shared_dpll *pll;
11291 if (transcoder_is_dsi(cpu_transcoder)) {
11292 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11295 tmp = intel_de_read(dev_priv,
11296 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11297 if (INTEL_GEN(dev_priv) >= 12)
11298 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11300 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11303 if (INTEL_GEN(dev_priv) >= 11)
11304 icl_get_ddi_pll(dev_priv, port, pipe_config);
11305 else if (IS_CANNONLAKE(dev_priv))
11306 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11307 else if (IS_GEN9_BC(dev_priv))
11308 skl_get_ddi_pll(dev_priv, port, pipe_config);
11309 else if (IS_GEN9_LP(dev_priv))
11310 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11312 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11314 pll = pipe_config->shared_dpll;
11316 drm_WARN_ON(&dev_priv->drm,
11317 !pll->info->funcs->get_hw_state(dev_priv, pll,
11318 &pipe_config->dpll_hw_state));
11322 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11323 * DDI E. So just check whether this pipe is wired to DDI E and whether
11324 * the PCH transcoder is on.
11326 if (INTEL_GEN(dev_priv) < 9 &&
11327 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11328 pipe_config->has_pch_encoder = true;
11330 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11331 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11332 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11334 ilk_get_fdi_m_n_config(crtc, pipe_config);
11338 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11339 struct intel_crtc_state *pipe_config)
11341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11342 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11343 enum intel_display_power_domain power_domain;
11344 u64 power_domain_mask;
11348 pipe_config->master_transcoder = INVALID_TRANSCODER;
11350 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11351 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11355 wakerefs[power_domain] = wf;
11356 power_domain_mask = BIT_ULL(power_domain);
11358 pipe_config->shared_dpll = NULL;
11360 active = hsw_get_transcoder_state(crtc, pipe_config,
11361 &power_domain_mask, wakerefs);
11363 if (IS_GEN9_LP(dev_priv) &&
11364 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11365 &power_domain_mask, wakerefs)) {
11366 drm_WARN_ON(&dev_priv->drm, active);
11373 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11374 INTEL_GEN(dev_priv) >= 11) {
11375 hsw_get_ddi_port_state(crtc, pipe_config);
11376 intel_get_transcoder_timings(crtc, pipe_config);
11379 intel_get_pipe_src_size(crtc, pipe_config);
11381 if (IS_HASWELL(dev_priv)) {
11382 u32 tmp = intel_de_read(dev_priv,
11383 PIPECONF(pipe_config->cpu_transcoder));
11385 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11386 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11388 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11390 pipe_config->output_format =
11391 bdw_get_pipemisc_output_format(crtc);
11394 pipe_config->gamma_mode = intel_de_read(dev_priv,
11395 GAMMA_MODE(crtc->pipe));
11397 pipe_config->csc_mode = intel_de_read(dev_priv,
11398 PIPE_CSC_MODE(crtc->pipe));
11400 if (INTEL_GEN(dev_priv) >= 9) {
11401 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11403 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11404 pipe_config->gamma_enable = true;
11406 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11407 pipe_config->csc_enable = true;
11409 i9xx_get_pipe_color_config(pipe_config);
11412 intel_color_get_config(pipe_config);
11414 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11415 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11416 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11417 pipe_config->ips_linetime =
11418 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11420 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11421 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11423 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11425 wakerefs[power_domain] = wf;
11426 power_domain_mask |= BIT_ULL(power_domain);
11428 if (INTEL_GEN(dev_priv) >= 9)
11429 skl_get_pfit_config(pipe_config);
11431 ilk_get_pfit_config(pipe_config);
11434 if (hsw_crtc_supports_ips(crtc)) {
11435 if (IS_HASWELL(dev_priv))
11436 pipe_config->ips_enabled = intel_de_read(dev_priv,
11437 IPS_CTL) & IPS_ENABLE;
11440 * We cannot readout IPS state on broadwell, set to
11441 * true so we can set it to a defined state on first
11444 pipe_config->ips_enabled = true;
11448 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11449 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11450 pipe_config->pixel_multiplier =
11451 intel_de_read(dev_priv,
11452 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11454 pipe_config->pixel_multiplier = 1;
11458 for_each_power_domain(power_domain, power_domain_mask)
11459 intel_display_power_put(dev_priv,
11460 power_domain, wakerefs[power_domain]);
11465 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11467 struct drm_i915_private *dev_priv =
11468 to_i915(plane_state->uapi.plane->dev);
11469 const struct drm_framebuffer *fb = plane_state->hw.fb;
11470 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11473 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11474 base = sg_dma_address(obj->mm.pages->sgl);
11476 base = intel_plane_ggtt_offset(plane_state);
11478 return base + plane_state->color_plane[0].offset;
11481 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11483 int x = plane_state->uapi.dst.x1;
11484 int y = plane_state->uapi.dst.y1;
11488 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11491 pos |= x << CURSOR_X_SHIFT;
11494 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11497 pos |= y << CURSOR_Y_SHIFT;
11502 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11504 const struct drm_mode_config *config =
11505 &plane_state->uapi.plane->dev->mode_config;
11506 int width = drm_rect_width(&plane_state->uapi.dst);
11507 int height = drm_rect_height(&plane_state->uapi.dst);
11509 return width > 0 && width <= config->cursor_width &&
11510 height > 0 && height <= config->cursor_height;
11513 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11515 struct drm_i915_private *dev_priv =
11516 to_i915(plane_state->uapi.plane->dev);
11517 unsigned int rotation = plane_state->hw.rotation;
11522 ret = intel_plane_compute_gtt(plane_state);
11526 if (!plane_state->uapi.visible)
11529 src_x = plane_state->uapi.src.x1 >> 16;
11530 src_y = plane_state->uapi.src.y1 >> 16;
11532 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11533 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11536 if (src_x != 0 || src_y != 0) {
11537 drm_dbg_kms(&dev_priv->drm,
11538 "Arbitrary cursor panning not supported\n");
11543 * Put the final coordinates back so that the src
11544 * coordinate checks will see the right values.
11546 drm_rect_translate_to(&plane_state->uapi.src,
11547 src_x << 16, src_y << 16);
11549 /* ILK+ do this automagically in hardware */
11550 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11551 const struct drm_framebuffer *fb = plane_state->hw.fb;
11552 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11553 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11555 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11558 plane_state->color_plane[0].offset = offset;
11559 plane_state->color_plane[0].x = src_x;
11560 plane_state->color_plane[0].y = src_y;
11565 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11566 struct intel_plane_state *plane_state)
11568 const struct drm_framebuffer *fb = plane_state->hw.fb;
11569 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11572 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11573 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11577 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11579 DRM_PLANE_HELPER_NO_SCALING,
11580 DRM_PLANE_HELPER_NO_SCALING,
11585 /* Use the unclipped src/dst rectangles, which we program to hw */
11586 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11587 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11589 ret = intel_cursor_check_surface(plane_state);
11593 if (!plane_state->uapi.visible)
11596 ret = intel_plane_check_src_coordinates(plane_state);
11603 static unsigned int
11604 i845_cursor_max_stride(struct intel_plane *plane,
11605 u32 pixel_format, u64 modifier,
11606 unsigned int rotation)
11611 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11615 if (crtc_state->gamma_enable)
11616 cntl |= CURSOR_GAMMA_ENABLE;
11621 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11622 const struct intel_plane_state *plane_state)
11624 return CURSOR_ENABLE |
11625 CURSOR_FORMAT_ARGB |
11626 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11629 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11631 int width = drm_rect_width(&plane_state->uapi.dst);
11634 * 845g/865g are only limited by the width of their cursors,
11635 * the height is arbitrary up to the precision of the register.
11637 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11640 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11641 struct intel_plane_state *plane_state)
11643 const struct drm_framebuffer *fb = plane_state->hw.fb;
11644 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11647 ret = intel_check_cursor(crtc_state, plane_state);
11651 /* if we want to turn off the cursor ignore width and height */
11655 /* Check for which cursor types we support */
11656 if (!i845_cursor_size_ok(plane_state)) {
11657 drm_dbg_kms(&i915->drm,
11658 "Cursor dimension %dx%d not supported\n",
11659 drm_rect_width(&plane_state->uapi.dst),
11660 drm_rect_height(&plane_state->uapi.dst));
11664 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11665 plane_state->color_plane[0].stride != fb->pitches[0]);
11667 switch (fb->pitches[0]) {
11674 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11679 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11684 static void i845_update_cursor(struct intel_plane *plane,
11685 const struct intel_crtc_state *crtc_state,
11686 const struct intel_plane_state *plane_state)
11688 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11689 u32 cntl = 0, base = 0, pos = 0, size = 0;
11690 unsigned long irqflags;
11692 if (plane_state && plane_state->uapi.visible) {
11693 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11694 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11696 cntl = plane_state->ctl |
11697 i845_cursor_ctl_crtc(crtc_state);
11699 size = (height << 12) | width;
11701 base = intel_cursor_base(plane_state);
11702 pos = intel_cursor_position(plane_state);
11705 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11707 /* On these chipsets we can only modify the base/size/stride
11708 * whilst the cursor is disabled.
11710 if (plane->cursor.base != base ||
11711 plane->cursor.size != size ||
11712 plane->cursor.cntl != cntl) {
11713 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11714 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11715 intel_de_write_fw(dev_priv, CURSIZE, size);
11716 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11717 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11719 plane->cursor.base = base;
11720 plane->cursor.size = size;
11721 plane->cursor.cntl = cntl;
11723 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11726 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11729 static void i845_disable_cursor(struct intel_plane *plane,
11730 const struct intel_crtc_state *crtc_state)
11732 i845_update_cursor(plane, crtc_state, NULL);
11735 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11738 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11739 enum intel_display_power_domain power_domain;
11740 intel_wakeref_t wakeref;
11743 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11744 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11748 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11752 intel_display_power_put(dev_priv, power_domain, wakeref);
11757 static unsigned int
11758 i9xx_cursor_max_stride(struct intel_plane *plane,
11759 u32 pixel_format, u64 modifier,
11760 unsigned int rotation)
11762 return plane->base.dev->mode_config.cursor_width * 4;
11765 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11768 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11771 if (INTEL_GEN(dev_priv) >= 11)
11774 if (crtc_state->gamma_enable)
11775 cntl = MCURSOR_GAMMA_ENABLE;
11777 if (crtc_state->csc_enable)
11778 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11780 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11781 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11786 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11787 const struct intel_plane_state *plane_state)
11789 struct drm_i915_private *dev_priv =
11790 to_i915(plane_state->uapi.plane->dev);
11793 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11794 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11796 switch (drm_rect_width(&plane_state->uapi.dst)) {
11798 cntl |= MCURSOR_MODE_64_ARGB_AX;
11801 cntl |= MCURSOR_MODE_128_ARGB_AX;
11804 cntl |= MCURSOR_MODE_256_ARGB_AX;
11807 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11811 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11812 cntl |= MCURSOR_ROTATE_180;
11817 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11819 struct drm_i915_private *dev_priv =
11820 to_i915(plane_state->uapi.plane->dev);
11821 int width = drm_rect_width(&plane_state->uapi.dst);
11822 int height = drm_rect_height(&plane_state->uapi.dst);
11824 if (!intel_cursor_size_ok(plane_state))
11827 /* Cursor width is limited to a few power-of-two sizes */
11838 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11839 * height from 8 lines up to the cursor width, when the
11840 * cursor is not rotated. Everything else requires square
11843 if (HAS_CUR_FBC(dev_priv) &&
11844 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11845 if (height < 8 || height > width)
11848 if (height != width)
11855 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11856 struct intel_plane_state *plane_state)
11858 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11859 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11860 const struct drm_framebuffer *fb = plane_state->hw.fb;
11861 enum pipe pipe = plane->pipe;
11864 ret = intel_check_cursor(crtc_state, plane_state);
11868 /* if we want to turn off the cursor ignore width and height */
11872 /* Check for which cursor types we support */
11873 if (!i9xx_cursor_size_ok(plane_state)) {
11874 drm_dbg(&dev_priv->drm,
11875 "Cursor dimension %dx%d not supported\n",
11876 drm_rect_width(&plane_state->uapi.dst),
11877 drm_rect_height(&plane_state->uapi.dst));
11881 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11882 plane_state->color_plane[0].stride != fb->pitches[0]);
11884 if (fb->pitches[0] !=
11885 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11886 drm_dbg_kms(&dev_priv->drm,
11887 "Invalid cursor stride (%u) (cursor width %d)\n",
11889 drm_rect_width(&plane_state->uapi.dst));
11894 * There's something wrong with the cursor on CHV pipe C.
11895 * If it straddles the left edge of the screen then
11896 * moving it away from the edge or disabling it often
11897 * results in a pipe underrun, and often that can lead to
11898 * dead pipe (constant underrun reported, and it scans
11899 * out just a solid color). To recover from that, the
11900 * display power well must be turned off and on again.
11901 * Refuse the put the cursor into that compromised position.
11903 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11904 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11905 drm_dbg_kms(&dev_priv->drm,
11906 "CHV cursor C not allowed to straddle the left screen edge\n");
11910 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11915 static void i9xx_update_cursor(struct intel_plane *plane,
11916 const struct intel_crtc_state *crtc_state,
11917 const struct intel_plane_state *plane_state)
11919 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11920 enum pipe pipe = plane->pipe;
11921 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11922 unsigned long irqflags;
11924 if (plane_state && plane_state->uapi.visible) {
11925 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11926 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11928 cntl = plane_state->ctl |
11929 i9xx_cursor_ctl_crtc(crtc_state);
11931 if (width != height)
11932 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11934 base = intel_cursor_base(plane_state);
11935 pos = intel_cursor_position(plane_state);
11938 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11941 * On some platforms writing CURCNTR first will also
11942 * cause CURPOS to be armed by the CURBASE write.
11943 * Without the CURCNTR write the CURPOS write would
11944 * arm itself. Thus we always update CURCNTR before
11947 * On other platforms CURPOS always requires the
11948 * CURBASE write to arm the update. Additonally
11949 * a write to any of the cursor register will cancel
11950 * an already armed cursor update. Thus leaving out
11951 * the CURBASE write after CURPOS could lead to a
11952 * cursor that doesn't appear to move, or even change
11953 * shape. Thus we always write CURBASE.
11955 * The other registers are armed by by the CURBASE write
11956 * except when the plane is getting enabled at which time
11957 * the CURCNTR write arms the update.
11960 if (INTEL_GEN(dev_priv) >= 9)
11961 skl_write_cursor_wm(plane, crtc_state);
11963 if (!needs_modeset(crtc_state))
11964 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
11966 if (plane->cursor.base != base ||
11967 plane->cursor.size != fbc_ctl ||
11968 plane->cursor.cntl != cntl) {
11969 if (HAS_CUR_FBC(dev_priv))
11970 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11972 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11973 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11974 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11976 plane->cursor.base = base;
11977 plane->cursor.size = fbc_ctl;
11978 plane->cursor.cntl = cntl;
11980 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11981 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11984 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11987 static void i9xx_disable_cursor(struct intel_plane *plane,
11988 const struct intel_crtc_state *crtc_state)
11990 i9xx_update_cursor(plane, crtc_state, NULL);
11993 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11996 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11997 enum intel_display_power_domain power_domain;
11998 intel_wakeref_t wakeref;
12003 * Not 100% correct for planes that can move between pipes,
12004 * but that's only the case for gen2-3 which don't have any
12005 * display power wells.
12007 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
12008 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
12012 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
12014 ret = val & MCURSOR_MODE;
12016 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
12017 *pipe = plane->pipe;
12019 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
12020 MCURSOR_PIPE_SELECT_SHIFT;
12022 intel_display_power_put(dev_priv, power_domain, wakeref);
12027 /* VESA 640x480x72Hz mode to set on the pipe */
12028 static const struct drm_display_mode load_detect_mode = {
12029 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
12030 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
12033 struct drm_framebuffer *
12034 intel_framebuffer_create(struct drm_i915_gem_object *obj,
12035 struct drm_mode_fb_cmd2 *mode_cmd)
12037 struct intel_framebuffer *intel_fb;
12040 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
12042 return ERR_PTR(-ENOMEM);
12044 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
12048 return &intel_fb->base;
12052 return ERR_PTR(ret);
12055 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
12056 struct drm_crtc *crtc)
12058 struct drm_plane *plane;
12059 struct drm_plane_state *plane_state;
12062 ret = drm_atomic_add_affected_planes(state, crtc);
12066 for_each_new_plane_in_state(state, plane, plane_state, i) {
12067 if (plane_state->crtc != crtc)
12070 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
12074 drm_atomic_set_fb_for_plane(plane_state, NULL);
12080 int intel_get_load_detect_pipe(struct drm_connector *connector,
12081 struct intel_load_detect_pipe *old,
12082 struct drm_modeset_acquire_ctx *ctx)
12084 struct intel_crtc *intel_crtc;
12085 struct intel_encoder *intel_encoder =
12086 intel_attached_encoder(to_intel_connector(connector));
12087 struct drm_crtc *possible_crtc;
12088 struct drm_encoder *encoder = &intel_encoder->base;
12089 struct drm_crtc *crtc = NULL;
12090 struct drm_device *dev = encoder->dev;
12091 struct drm_i915_private *dev_priv = to_i915(dev);
12092 struct drm_mode_config *config = &dev->mode_config;
12093 struct drm_atomic_state *state = NULL, *restore_state = NULL;
12094 struct drm_connector_state *connector_state;
12095 struct intel_crtc_state *crtc_state;
12098 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12099 connector->base.id, connector->name,
12100 encoder->base.id, encoder->name);
12102 old->restore_state = NULL;
12104 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
12107 * Algorithm gets a little messy:
12109 * - if the connector already has an assigned crtc, use it (but make
12110 * sure it's on first)
12112 * - try to find the first unused crtc that can drive this connector,
12113 * and use that if we find one
12116 /* See if we already have a CRTC for this connector */
12117 if (connector->state->crtc) {
12118 crtc = connector->state->crtc;
12120 ret = drm_modeset_lock(&crtc->mutex, ctx);
12124 /* Make sure the crtc and connector are running */
12128 /* Find an unused one (if possible) */
12129 for_each_crtc(dev, possible_crtc) {
12131 if (!(encoder->possible_crtcs & (1 << i)))
12134 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
12138 if (possible_crtc->state->enable) {
12139 drm_modeset_unlock(&possible_crtc->mutex);
12143 crtc = possible_crtc;
12148 * If we didn't find an unused CRTC, don't use any.
12151 drm_dbg_kms(&dev_priv->drm,
12152 "no pipe available for load-detect\n");
12158 intel_crtc = to_intel_crtc(crtc);
12160 state = drm_atomic_state_alloc(dev);
12161 restore_state = drm_atomic_state_alloc(dev);
12162 if (!state || !restore_state) {
12167 state->acquire_ctx = ctx;
12168 restore_state->acquire_ctx = ctx;
12170 connector_state = drm_atomic_get_connector_state(state, connector);
12171 if (IS_ERR(connector_state)) {
12172 ret = PTR_ERR(connector_state);
12176 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12180 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12181 if (IS_ERR(crtc_state)) {
12182 ret = PTR_ERR(crtc_state);
12186 crtc_state->uapi.active = true;
12188 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12189 &load_detect_mode);
12193 ret = intel_modeset_disable_planes(state, crtc);
12197 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12199 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12201 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12203 drm_dbg_kms(&dev_priv->drm,
12204 "Failed to create a copy of old state to restore: %i\n",
12209 ret = drm_atomic_commit(state);
12211 drm_dbg_kms(&dev_priv->drm,
12212 "failed to set mode on load-detect pipe\n");
12216 old->restore_state = restore_state;
12217 drm_atomic_state_put(state);
12219 /* let the connector get through one full cycle before testing */
12220 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12225 drm_atomic_state_put(state);
12228 if (restore_state) {
12229 drm_atomic_state_put(restore_state);
12230 restore_state = NULL;
12233 if (ret == -EDEADLK)
12239 void intel_release_load_detect_pipe(struct drm_connector *connector,
12240 struct intel_load_detect_pipe *old,
12241 struct drm_modeset_acquire_ctx *ctx)
12243 struct intel_encoder *intel_encoder =
12244 intel_attached_encoder(to_intel_connector(connector));
12245 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12246 struct drm_encoder *encoder = &intel_encoder->base;
12247 struct drm_atomic_state *state = old->restore_state;
12250 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12251 connector->base.id, connector->name,
12252 encoder->base.id, encoder->name);
12257 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12259 drm_dbg_kms(&i915->drm,
12260 "Couldn't release load detect pipe: %i\n", ret);
12261 drm_atomic_state_put(state);
12264 static int i9xx_pll_refclk(struct drm_device *dev,
12265 const struct intel_crtc_state *pipe_config)
12267 struct drm_i915_private *dev_priv = to_i915(dev);
12268 u32 dpll = pipe_config->dpll_hw_state.dpll;
12270 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12271 return dev_priv->vbt.lvds_ssc_freq;
12272 else if (HAS_PCH_SPLIT(dev_priv))
12274 else if (!IS_GEN(dev_priv, 2))
12280 /* Returns the clock of the currently programmed mode of the given pipe. */
12281 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12282 struct intel_crtc_state *pipe_config)
12284 struct drm_device *dev = crtc->base.dev;
12285 struct drm_i915_private *dev_priv = to_i915(dev);
12286 enum pipe pipe = crtc->pipe;
12287 u32 dpll = pipe_config->dpll_hw_state.dpll;
12291 int refclk = i9xx_pll_refclk(dev, pipe_config);
12293 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12294 fp = pipe_config->dpll_hw_state.fp0;
12296 fp = pipe_config->dpll_hw_state.fp1;
12298 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12299 if (IS_PINEVIEW(dev_priv)) {
12300 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12301 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12303 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12304 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12307 if (!IS_GEN(dev_priv, 2)) {
12308 if (IS_PINEVIEW(dev_priv))
12309 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12310 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12312 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12313 DPLL_FPA01_P1_POST_DIV_SHIFT);
12315 switch (dpll & DPLL_MODE_MASK) {
12316 case DPLLB_MODE_DAC_SERIAL:
12317 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12320 case DPLLB_MODE_LVDS:
12321 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12325 drm_dbg_kms(&dev_priv->drm,
12326 "Unknown DPLL mode %08x in programmed "
12327 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12331 if (IS_PINEVIEW(dev_priv))
12332 port_clock = pnv_calc_dpll_params(refclk, &clock);
12334 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12336 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12338 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12341 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12342 DPLL_FPA01_P1_POST_DIV_SHIFT);
12344 if (lvds & LVDS_CLKB_POWER_UP)
12349 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12352 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12353 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12355 if (dpll & PLL_P2_DIVIDE_BY_4)
12361 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12365 * This value includes pixel_multiplier. We will use
12366 * port_clock to compute adjusted_mode.crtc_clock in the
12367 * encoder's get_config() function.
12369 pipe_config->port_clock = port_clock;
12372 int intel_dotclock_calculate(int link_freq,
12373 const struct intel_link_m_n *m_n)
12376 * The calculation for the data clock is:
12377 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12378 * But we want to avoid losing precison if possible, so:
12379 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12381 * and the link clock is simpler:
12382 * link_clock = (m * link_clock) / n
12388 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12391 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12392 struct intel_crtc_state *pipe_config)
12394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12396 /* read out port_clock from the DPLL */
12397 i9xx_crtc_clock_get(crtc, pipe_config);
12400 * In case there is an active pipe without active ports,
12401 * we may need some idea for the dotclock anyway.
12402 * Calculate one based on the FDI configuration.
12404 pipe_config->hw.adjusted_mode.crtc_clock =
12405 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12406 &pipe_config->fdi_m_n);
12409 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12410 struct intel_crtc *crtc)
12412 memset(crtc_state, 0, sizeof(*crtc_state));
12414 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12416 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12417 crtc_state->master_transcoder = INVALID_TRANSCODER;
12418 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12419 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12420 crtc_state->scaler_state.scaler_id = -1;
12421 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12424 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12426 struct intel_crtc_state *crtc_state;
12428 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12431 intel_crtc_state_reset(crtc_state, crtc);
12436 /* Returns the currently programmed mode of the given encoder. */
12437 struct drm_display_mode *
12438 intel_encoder_current_mode(struct intel_encoder *encoder)
12440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12441 struct intel_crtc_state *crtc_state;
12442 struct drm_display_mode *mode;
12443 struct intel_crtc *crtc;
12446 if (!encoder->get_hw_state(encoder, &pipe))
12449 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12451 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12455 crtc_state = intel_crtc_state_alloc(crtc);
12461 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12467 encoder->get_config(encoder, crtc_state);
12469 intel_mode_from_pipe_config(mode, crtc_state);
12476 static void intel_crtc_destroy(struct drm_crtc *crtc)
12478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12480 drm_crtc_cleanup(crtc);
12485 * intel_wm_need_update - Check whether watermarks need updating
12486 * @cur: current plane state
12487 * @new: new plane state
12489 * Check current plane state versus the new one to determine whether
12490 * watermarks need to be recalculated.
12492 * Returns true or false.
12494 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12495 struct intel_plane_state *new)
12497 /* Update watermarks on tiling or size changes. */
12498 if (new->uapi.visible != cur->uapi.visible)
12501 if (!cur->hw.fb || !new->hw.fb)
12504 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12505 cur->hw.rotation != new->hw.rotation ||
12506 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12507 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12508 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12509 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12515 static bool needs_scaling(const struct intel_plane_state *state)
12517 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12518 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12519 int dst_w = drm_rect_width(&state->uapi.dst);
12520 int dst_h = drm_rect_height(&state->uapi.dst);
12522 return (src_w != dst_w || src_h != dst_h);
12525 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12526 struct intel_crtc_state *crtc_state,
12527 const struct intel_plane_state *old_plane_state,
12528 struct intel_plane_state *plane_state)
12530 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12531 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12533 bool mode_changed = needs_modeset(crtc_state);
12534 bool was_crtc_enabled = old_crtc_state->hw.active;
12535 bool is_crtc_enabled = crtc_state->hw.active;
12536 bool turn_off, turn_on, visible, was_visible;
12539 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12540 ret = skl_update_scaler_plane(crtc_state, plane_state);
12545 was_visible = old_plane_state->uapi.visible;
12546 visible = plane_state->uapi.visible;
12548 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12549 was_visible = false;
12552 * Visibility is calculated as if the crtc was on, but
12553 * after scaler setup everything depends on it being off
12554 * when the crtc isn't active.
12556 * FIXME this is wrong for watermarks. Watermarks should also
12557 * be computed as if the pipe would be active. Perhaps move
12558 * per-plane wm computation to the .check_plane() hook, and
12559 * only combine the results from all planes in the current place?
12561 if (!is_crtc_enabled) {
12562 intel_plane_set_invisible(crtc_state, plane_state);
12566 if (!was_visible && !visible)
12569 turn_off = was_visible && (!visible || mode_changed);
12570 turn_on = visible && (!was_visible || mode_changed);
12572 drm_dbg_atomic(&dev_priv->drm,
12573 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12574 crtc->base.base.id, crtc->base.name,
12575 plane->base.base.id, plane->base.name,
12576 was_visible, visible,
12577 turn_off, turn_on, mode_changed);
12580 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12581 crtc_state->update_wm_pre = true;
12583 /* must disable cxsr around plane enable/disable */
12584 if (plane->id != PLANE_CURSOR)
12585 crtc_state->disable_cxsr = true;
12586 } else if (turn_off) {
12587 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12588 crtc_state->update_wm_post = true;
12590 /* must disable cxsr around plane enable/disable */
12591 if (plane->id != PLANE_CURSOR)
12592 crtc_state->disable_cxsr = true;
12593 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12594 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12595 /* FIXME bollocks */
12596 crtc_state->update_wm_pre = true;
12597 crtc_state->update_wm_post = true;
12601 if (visible || was_visible)
12602 crtc_state->fb_bits |= plane->frontbuffer_bit;
12605 * ILK/SNB DVSACNTR/Sprite Enable
12606 * IVB SPR_CTL/Sprite Enable
12607 * "When in Self Refresh Big FIFO mode, a write to enable the
12608 * plane will be internally buffered and delayed while Big FIFO
12609 * mode is exiting."
12611 * Which means that enabling the sprite can take an extra frame
12612 * when we start in big FIFO mode (LP1+). Thus we need to drop
12613 * down to LP0 and wait for vblank in order to make sure the
12614 * sprite gets enabled on the next vblank after the register write.
12615 * Doing otherwise would risk enabling the sprite one frame after
12616 * we've already signalled flip completion. We can resume LP1+
12617 * once the sprite has been enabled.
12620 * WaCxSRDisabledForSpriteScaling:ivb
12621 * IVB SPR_SCALE/Scaling Enable
12622 * "Low Power watermarks must be disabled for at least one
12623 * frame before enabling sprite scaling, and kept disabled
12624 * until sprite scaling is disabled."
12626 * ILK/SNB DVSASCALE/Scaling Enable
12627 * "When in Self Refresh Big FIFO mode, scaling enable will be
12628 * masked off while Big FIFO mode is exiting."
12630 * Despite the w/a only being listed for IVB we assume that
12631 * the ILK/SNB note has similar ramifications, hence we apply
12632 * the w/a on all three platforms.
12634 * With experimental results seems this is needed also for primary
12635 * plane, not only sprite plane.
12637 if (plane->id != PLANE_CURSOR &&
12638 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12639 IS_IVYBRIDGE(dev_priv)) &&
12640 (turn_on || (!needs_scaling(old_plane_state) &&
12641 needs_scaling(plane_state))))
12642 crtc_state->disable_lp_wm = true;
12647 static bool encoders_cloneable(const struct intel_encoder *a,
12648 const struct intel_encoder *b)
12650 /* masks could be asymmetric, so check both ways */
12651 return a == b || (a->cloneable & (1 << b->type) &&
12652 b->cloneable & (1 << a->type));
12655 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12656 struct intel_crtc *crtc,
12657 struct intel_encoder *encoder)
12659 struct intel_encoder *source_encoder;
12660 struct drm_connector *connector;
12661 struct drm_connector_state *connector_state;
12664 for_each_new_connector_in_state(state, connector, connector_state, i) {
12665 if (connector_state->crtc != &crtc->base)
12669 to_intel_encoder(connector_state->best_encoder);
12670 if (!encoders_cloneable(encoder, source_encoder))
12677 static int icl_add_linked_planes(struct intel_atomic_state *state)
12679 struct intel_plane *plane, *linked;
12680 struct intel_plane_state *plane_state, *linked_plane_state;
12683 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12684 linked = plane_state->planar_linked_plane;
12689 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12690 if (IS_ERR(linked_plane_state))
12691 return PTR_ERR(linked_plane_state);
12693 drm_WARN_ON(state->base.dev,
12694 linked_plane_state->planar_linked_plane != plane);
12695 drm_WARN_ON(state->base.dev,
12696 linked_plane_state->planar_slave == plane_state->planar_slave);
12702 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12704 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12705 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12706 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12707 struct intel_plane *plane, *linked;
12708 struct intel_plane_state *plane_state;
12711 if (INTEL_GEN(dev_priv) < 11)
12715 * Destroy all old plane links and make the slave plane invisible
12716 * in the crtc_state->active_planes mask.
12718 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12719 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12722 plane_state->planar_linked_plane = NULL;
12723 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12724 crtc_state->active_planes &= ~BIT(plane->id);
12725 crtc_state->update_planes |= BIT(plane->id);
12728 plane_state->planar_slave = false;
12731 if (!crtc_state->nv12_planes)
12734 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12735 struct intel_plane_state *linked_state = NULL;
12737 if (plane->pipe != crtc->pipe ||
12738 !(crtc_state->nv12_planes & BIT(plane->id)))
12741 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12742 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12745 if (crtc_state->active_planes & BIT(linked->id))
12748 linked_state = intel_atomic_get_plane_state(state, linked);
12749 if (IS_ERR(linked_state))
12750 return PTR_ERR(linked_state);
12755 if (!linked_state) {
12756 drm_dbg_kms(&dev_priv->drm,
12757 "Need %d free Y planes for planar YUV\n",
12758 hweight8(crtc_state->nv12_planes));
12763 plane_state->planar_linked_plane = linked;
12765 linked_state->planar_slave = true;
12766 linked_state->planar_linked_plane = plane;
12767 crtc_state->active_planes |= BIT(linked->id);
12768 crtc_state->update_planes |= BIT(linked->id);
12769 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12770 linked->base.name, plane->base.name);
12772 /* Copy parameters to slave plane */
12773 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12774 linked_state->color_ctl = plane_state->color_ctl;
12775 linked_state->view = plane_state->view;
12776 memcpy(linked_state->color_plane, plane_state->color_plane,
12777 sizeof(linked_state->color_plane));
12779 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12780 linked_state->uapi.src = plane_state->uapi.src;
12781 linked_state->uapi.dst = plane_state->uapi.dst;
12783 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12784 if (linked->id == PLANE_SPRITE5)
12785 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12786 else if (linked->id == PLANE_SPRITE4)
12787 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12788 else if (linked->id == PLANE_SPRITE3)
12789 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12790 else if (linked->id == PLANE_SPRITE2)
12791 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12793 MISSING_CASE(linked->id);
12800 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12802 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12803 struct intel_atomic_state *state =
12804 to_intel_atomic_state(new_crtc_state->uapi.state);
12805 const struct intel_crtc_state *old_crtc_state =
12806 intel_atomic_get_old_crtc_state(state, crtc);
12808 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12811 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12813 const struct drm_display_mode *adjusted_mode =
12814 &crtc_state->hw.adjusted_mode;
12817 if (!crtc_state->hw.enable)
12820 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12821 adjusted_mode->crtc_clock);
12823 return min(linetime_wm, 0x1ff);
12826 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12827 const struct intel_cdclk_state *cdclk_state)
12829 const struct drm_display_mode *adjusted_mode =
12830 &crtc_state->hw.adjusted_mode;
12833 if (!crtc_state->hw.enable)
12836 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12837 cdclk_state->logical.cdclk);
12839 return min(linetime_wm, 0x1ff);
12842 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12846 const struct drm_display_mode *adjusted_mode =
12847 &crtc_state->hw.adjusted_mode;
12850 if (!crtc_state->hw.enable)
12853 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12854 crtc_state->pixel_rate);
12856 /* Display WA #1135: BXT:ALL GLK:ALL */
12857 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12860 return min(linetime_wm, 0x1ff);
12863 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12864 struct intel_crtc *crtc)
12866 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12867 struct intel_crtc_state *crtc_state =
12868 intel_atomic_get_new_crtc_state(state, crtc);
12869 const struct intel_cdclk_state *cdclk_state;
12871 if (INTEL_GEN(dev_priv) >= 9)
12872 crtc_state->linetime = skl_linetime_wm(crtc_state);
12874 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12876 if (!hsw_crtc_supports_ips(crtc))
12879 cdclk_state = intel_atomic_get_cdclk_state(state);
12880 if (IS_ERR(cdclk_state))
12881 return PTR_ERR(cdclk_state);
12883 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12889 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12890 struct intel_crtc *crtc)
12892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12893 struct intel_crtc_state *crtc_state =
12894 intel_atomic_get_new_crtc_state(state, crtc);
12895 bool mode_changed = needs_modeset(crtc_state);
12898 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12899 mode_changed && !crtc_state->hw.active)
12900 crtc_state->update_wm_post = true;
12902 if (mode_changed && crtc_state->hw.enable &&
12903 dev_priv->display.crtc_compute_clock &&
12904 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12905 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12911 * May need to update pipe gamma enable bits
12912 * when C8 planes are getting enabled/disabled.
12914 if (c8_planes_changed(crtc_state))
12915 crtc_state->uapi.color_mgmt_changed = true;
12917 if (mode_changed || crtc_state->update_pipe ||
12918 crtc_state->uapi.color_mgmt_changed) {
12919 ret = intel_color_check(crtc_state);
12924 if (dev_priv->display.compute_pipe_wm) {
12925 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12927 drm_dbg_kms(&dev_priv->drm,
12928 "Target pipe watermarks are invalid\n");
12933 if (dev_priv->display.compute_intermediate_wm) {
12934 if (drm_WARN_ON(&dev_priv->drm,
12935 !dev_priv->display.compute_pipe_wm))
12939 * Calculate 'intermediate' watermarks that satisfy both the
12940 * old state and the new state. We can program these
12943 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12945 drm_dbg_kms(&dev_priv->drm,
12946 "No valid intermediate pipe watermarks are possible\n");
12951 if (INTEL_GEN(dev_priv) >= 9) {
12952 if (mode_changed || crtc_state->update_pipe) {
12953 ret = skl_update_scaler_crtc(crtc_state);
12958 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12963 if (HAS_IPS(dev_priv)) {
12964 ret = hsw_compute_ips_config(crtc_state);
12969 if (INTEL_GEN(dev_priv) >= 9 ||
12970 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12971 ret = hsw_compute_linetime_wm(state, crtc);
12977 if (!mode_changed) {
12978 ret = intel_psr2_sel_fetch_update(state, crtc);
12986 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12988 struct intel_connector *connector;
12989 struct drm_connector_list_iter conn_iter;
12991 drm_connector_list_iter_begin(dev, &conn_iter);
12992 for_each_intel_connector_iter(connector, &conn_iter) {
12993 if (connector->base.state->crtc)
12994 drm_connector_put(&connector->base);
12996 if (connector->base.encoder) {
12997 connector->base.state->best_encoder =
12998 connector->base.encoder;
12999 connector->base.state->crtc =
13000 connector->base.encoder->crtc;
13002 drm_connector_get(&connector->base);
13004 connector->base.state->best_encoder = NULL;
13005 connector->base.state->crtc = NULL;
13008 drm_connector_list_iter_end(&conn_iter);
13012 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
13013 struct intel_crtc_state *pipe_config)
13015 struct drm_connector *connector = conn_state->connector;
13016 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13017 const struct drm_display_info *info = &connector->display_info;
13020 switch (conn_state->max_bpc) {
13037 if (bpp < pipe_config->pipe_bpp) {
13038 drm_dbg_kms(&i915->drm,
13039 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
13040 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
13041 connector->base.id, connector->name,
13042 bpp, 3 * info->bpc,
13043 3 * conn_state->max_requested_bpc,
13044 pipe_config->pipe_bpp);
13046 pipe_config->pipe_bpp = bpp;
13053 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
13054 struct intel_crtc_state *pipe_config)
13056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13057 struct drm_atomic_state *state = pipe_config->uapi.state;
13058 struct drm_connector *connector;
13059 struct drm_connector_state *connector_state;
13062 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13063 IS_CHERRYVIEW(dev_priv)))
13065 else if (INTEL_GEN(dev_priv) >= 5)
13070 pipe_config->pipe_bpp = bpp;
13072 /* Clamp display bpp to connector max bpp */
13073 for_each_new_connector_in_state(state, connector, connector_state, i) {
13076 if (connector_state->crtc != &crtc->base)
13079 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
13087 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
13088 const struct drm_display_mode *mode)
13090 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
13091 "type: 0x%x flags: 0x%x\n",
13093 mode->crtc_hdisplay, mode->crtc_hsync_start,
13094 mode->crtc_hsync_end, mode->crtc_htotal,
13095 mode->crtc_vdisplay, mode->crtc_vsync_start,
13096 mode->crtc_vsync_end, mode->crtc_vtotal,
13097 mode->type, mode->flags);
13101 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
13102 const char *id, unsigned int lane_count,
13103 const struct intel_link_m_n *m_n)
13105 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13107 drm_dbg_kms(&i915->drm,
13108 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
13110 m_n->gmch_m, m_n->gmch_n,
13111 m_n->link_m, m_n->link_n, m_n->tu);
13115 intel_dump_infoframe(struct drm_i915_private *dev_priv,
13116 const union hdmi_infoframe *frame)
13118 if (!drm_debug_enabled(DRM_UT_KMS))
13121 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
13125 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
13126 const struct drm_dp_vsc_sdp *vsc)
13128 if (!drm_debug_enabled(DRM_UT_KMS))
13131 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
13134 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
13136 static const char * const output_type_str[] = {
13137 OUTPUT_TYPE(UNUSED),
13138 OUTPUT_TYPE(ANALOG),
13142 OUTPUT_TYPE(TVOUT),
13148 OUTPUT_TYPE(DP_MST),
13153 static void snprintf_output_types(char *buf, size_t len,
13154 unsigned int output_types)
13161 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13164 if ((output_types & BIT(i)) == 0)
13167 r = snprintf(str, len, "%s%s",
13168 str != buf ? "," : "", output_type_str[i]);
13174 output_types &= ~BIT(i);
13177 WARN_ON_ONCE(output_types != 0);
13180 static const char * const output_format_str[] = {
13181 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13182 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13183 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13184 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13187 static const char *output_formats(enum intel_output_format format)
13189 if (format >= ARRAY_SIZE(output_format_str))
13190 format = INTEL_OUTPUT_FORMAT_INVALID;
13191 return output_format_str[format];
13194 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13196 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13197 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13198 const struct drm_framebuffer *fb = plane_state->hw.fb;
13199 struct drm_format_name_buf format_name;
13202 drm_dbg_kms(&i915->drm,
13203 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13204 plane->base.base.id, plane->base.name,
13205 yesno(plane_state->uapi.visible));
13209 drm_dbg_kms(&i915->drm,
13210 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13211 plane->base.base.id, plane->base.name,
13212 fb->base.id, fb->width, fb->height,
13213 drm_get_format_name(fb->format->format, &format_name),
13214 yesno(plane_state->uapi.visible));
13215 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13216 plane_state->hw.rotation, plane_state->scaler_id);
13217 if (plane_state->uapi.visible)
13218 drm_dbg_kms(&i915->drm,
13219 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13220 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13221 DRM_RECT_ARG(&plane_state->uapi.dst));
13224 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13225 struct intel_atomic_state *state,
13226 const char *context)
13228 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13230 const struct intel_plane_state *plane_state;
13231 struct intel_plane *plane;
13235 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13236 crtc->base.base.id, crtc->base.name,
13237 yesno(pipe_config->hw.enable), context);
13239 if (!pipe_config->hw.enable)
13242 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13243 drm_dbg_kms(&dev_priv->drm,
13244 "active: %s, output_types: %s (0x%x), output format: %s\n",
13245 yesno(pipe_config->hw.active),
13246 buf, pipe_config->output_types,
13247 output_formats(pipe_config->output_format));
13249 drm_dbg_kms(&dev_priv->drm,
13250 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13251 transcoder_name(pipe_config->cpu_transcoder),
13252 pipe_config->pipe_bpp, pipe_config->dither);
13254 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13255 transcoder_name(pipe_config->mst_master_transcoder));
13257 drm_dbg_kms(&dev_priv->drm,
13258 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13259 transcoder_name(pipe_config->master_transcoder),
13260 pipe_config->sync_mode_slaves_mask);
13262 if (pipe_config->has_pch_encoder)
13263 intel_dump_m_n_config(pipe_config, "fdi",
13264 pipe_config->fdi_lanes,
13265 &pipe_config->fdi_m_n);
13267 if (intel_crtc_has_dp_encoder(pipe_config)) {
13268 intel_dump_m_n_config(pipe_config, "dp m_n",
13269 pipe_config->lane_count, &pipe_config->dp_m_n);
13270 if (pipe_config->has_drrs)
13271 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13272 pipe_config->lane_count,
13273 &pipe_config->dp_m2_n2);
13276 drm_dbg_kms(&dev_priv->drm,
13277 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13278 pipe_config->has_audio, pipe_config->has_infoframe,
13279 pipe_config->infoframes.enable);
13281 if (pipe_config->infoframes.enable &
13282 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13283 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13284 pipe_config->infoframes.gcp);
13285 if (pipe_config->infoframes.enable &
13286 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13287 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13288 if (pipe_config->infoframes.enable &
13289 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13290 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13291 if (pipe_config->infoframes.enable &
13292 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13293 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13294 if (pipe_config->infoframes.enable &
13295 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13296 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13297 if (pipe_config->infoframes.enable &
13298 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13299 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13300 if (pipe_config->infoframes.enable &
13301 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13302 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13304 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13305 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13306 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13307 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13308 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13309 drm_dbg_kms(&dev_priv->drm,
13310 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13311 pipe_config->port_clock,
13312 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13313 pipe_config->pixel_rate);
13315 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13316 pipe_config->linetime, pipe_config->ips_linetime);
13318 if (INTEL_GEN(dev_priv) >= 9)
13319 drm_dbg_kms(&dev_priv->drm,
13320 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13322 pipe_config->scaler_state.scaler_users,
13323 pipe_config->scaler_state.scaler_id);
13325 if (HAS_GMCH(dev_priv))
13326 drm_dbg_kms(&dev_priv->drm,
13327 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13328 pipe_config->gmch_pfit.control,
13329 pipe_config->gmch_pfit.pgm_ratios,
13330 pipe_config->gmch_pfit.lvds_border_bits);
13332 drm_dbg_kms(&dev_priv->drm,
13333 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13334 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13335 enableddisabled(pipe_config->pch_pfit.enabled),
13336 yesno(pipe_config->pch_pfit.force_thru));
13338 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13339 pipe_config->ips_enabled, pipe_config->double_wide);
13341 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13343 if (IS_CHERRYVIEW(dev_priv))
13344 drm_dbg_kms(&dev_priv->drm,
13345 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13346 pipe_config->cgm_mode, pipe_config->gamma_mode,
13347 pipe_config->gamma_enable, pipe_config->csc_enable);
13349 drm_dbg_kms(&dev_priv->drm,
13350 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13351 pipe_config->csc_mode, pipe_config->gamma_mode,
13352 pipe_config->gamma_enable, pipe_config->csc_enable);
13354 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
13355 pipe_config->hw.degamma_lut ?
13356 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
13357 pipe_config->hw.gamma_lut ?
13358 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
13364 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13365 if (plane->pipe == crtc->pipe)
13366 intel_dump_plane_state(plane_state);
13370 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13372 struct drm_device *dev = state->base.dev;
13373 struct drm_connector *connector;
13374 struct drm_connector_list_iter conn_iter;
13375 unsigned int used_ports = 0;
13376 unsigned int used_mst_ports = 0;
13380 * We're going to peek into connector->state,
13381 * hence connection_mutex must be held.
13383 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13386 * Walk the connector list instead of the encoder
13387 * list to detect the problem on ddi platforms
13388 * where there's just one encoder per digital port.
13390 drm_connector_list_iter_begin(dev, &conn_iter);
13391 drm_for_each_connector_iter(connector, &conn_iter) {
13392 struct drm_connector_state *connector_state;
13393 struct intel_encoder *encoder;
13396 drm_atomic_get_new_connector_state(&state->base,
13398 if (!connector_state)
13399 connector_state = connector->state;
13401 if (!connector_state->best_encoder)
13404 encoder = to_intel_encoder(connector_state->best_encoder);
13406 drm_WARN_ON(dev, !connector_state->crtc);
13408 switch (encoder->type) {
13409 case INTEL_OUTPUT_DDI:
13410 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13413 case INTEL_OUTPUT_DP:
13414 case INTEL_OUTPUT_HDMI:
13415 case INTEL_OUTPUT_EDP:
13416 /* the same port mustn't appear more than once */
13417 if (used_ports & BIT(encoder->port))
13420 used_ports |= BIT(encoder->port);
13422 case INTEL_OUTPUT_DP_MST:
13424 1 << encoder->port;
13430 drm_connector_list_iter_end(&conn_iter);
13432 /* can't mix MST and SST/HDMI on the same port */
13433 if (used_ports & used_mst_ports)
13440 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13442 intel_crtc_copy_color_blobs(crtc_state);
13446 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13448 crtc_state->hw.enable = crtc_state->uapi.enable;
13449 crtc_state->hw.active = crtc_state->uapi.active;
13450 crtc_state->hw.mode = crtc_state->uapi.mode;
13451 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13452 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13455 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13457 crtc_state->uapi.enable = crtc_state->hw.enable;
13458 crtc_state->uapi.active = crtc_state->hw.active;
13459 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13460 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13462 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13464 /* copy color blobs to uapi */
13465 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13466 crtc_state->hw.degamma_lut);
13467 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13468 crtc_state->hw.gamma_lut);
13469 drm_property_replace_blob(&crtc_state->uapi.ctm,
13470 crtc_state->hw.ctm);
13474 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13476 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13478 struct intel_crtc_state *saved_state;
13480 saved_state = intel_crtc_state_alloc(crtc);
13484 /* free the old crtc_state->hw members */
13485 intel_crtc_free_hw_state(crtc_state);
13487 /* FIXME: before the switch to atomic started, a new pipe_config was
13488 * kzalloc'd. Code that depends on any field being zero should be
13489 * fixed, so that the crtc_state can be safely duplicated. For now,
13490 * only fields that are know to not cause problems are preserved. */
13492 saved_state->uapi = crtc_state->uapi;
13493 saved_state->scaler_state = crtc_state->scaler_state;
13494 saved_state->shared_dpll = crtc_state->shared_dpll;
13495 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13496 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13497 sizeof(saved_state->icl_port_dplls));
13498 saved_state->crc_enabled = crtc_state->crc_enabled;
13499 if (IS_G4X(dev_priv) ||
13500 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13501 saved_state->wm = crtc_state->wm;
13503 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13504 kfree(saved_state);
13506 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13512 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13514 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13515 struct drm_atomic_state *state = pipe_config->uapi.state;
13516 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13517 struct drm_connector *connector;
13518 struct drm_connector_state *connector_state;
13519 int base_bpp, ret, i;
13522 pipe_config->cpu_transcoder =
13523 (enum transcoder) to_intel_crtc(crtc)->pipe;
13526 * Sanitize sync polarity flags based on requested ones. If neither
13527 * positive or negative polarity is requested, treat this as meaning
13528 * negative polarity.
13530 if (!(pipe_config->hw.adjusted_mode.flags &
13531 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13532 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13534 if (!(pipe_config->hw.adjusted_mode.flags &
13535 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13536 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13538 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13543 base_bpp = pipe_config->pipe_bpp;
13546 * Determine the real pipe dimensions. Note that stereo modes can
13547 * increase the actual pipe size due to the frame doubling and
13548 * insertion of additional space for blanks between the frame. This
13549 * is stored in the crtc timings. We use the requested mode to do this
13550 * computation to clearly distinguish it from the adjusted mode, which
13551 * can be changed by the connectors in the below retry loop.
13553 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13554 &pipe_config->pipe_src_w,
13555 &pipe_config->pipe_src_h);
13557 for_each_new_connector_in_state(state, connector, connector_state, i) {
13558 struct intel_encoder *encoder =
13559 to_intel_encoder(connector_state->best_encoder);
13561 if (connector_state->crtc != crtc)
13564 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13565 drm_dbg_kms(&i915->drm,
13566 "rejecting invalid cloning configuration\n");
13571 * Determine output_types before calling the .compute_config()
13572 * hooks so that the hooks can use this information safely.
13574 if (encoder->compute_output_type)
13575 pipe_config->output_types |=
13576 BIT(encoder->compute_output_type(encoder, pipe_config,
13579 pipe_config->output_types |= BIT(encoder->type);
13583 /* Ensure the port clock defaults are reset when retrying. */
13584 pipe_config->port_clock = 0;
13585 pipe_config->pixel_multiplier = 1;
13587 /* Fill in default crtc timings, allow encoders to overwrite them. */
13588 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13589 CRTC_STEREO_DOUBLE);
13591 /* Pass our mode to the connectors and the CRTC to give them a chance to
13592 * adjust it according to limitations or connector properties, and also
13593 * a chance to reject the mode entirely.
13595 for_each_new_connector_in_state(state, connector, connector_state, i) {
13596 struct intel_encoder *encoder =
13597 to_intel_encoder(connector_state->best_encoder);
13599 if (connector_state->crtc != crtc)
13602 ret = encoder->compute_config(encoder, pipe_config,
13605 if (ret != -EDEADLK)
13606 drm_dbg_kms(&i915->drm,
13607 "Encoder config failure: %d\n",
13613 /* Set default port clock if not overwritten by the encoder. Needs to be
13614 * done afterwards in case the encoder adjusts the mode. */
13615 if (!pipe_config->port_clock)
13616 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13617 * pipe_config->pixel_multiplier;
13619 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13620 if (ret == -EDEADLK)
13623 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13627 if (ret == RETRY) {
13628 if (drm_WARN(&i915->drm, !retry,
13629 "loop in pipe configuration computation\n"))
13632 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13634 goto encoder_retry;
13637 /* Dithering seems to not pass-through bits correctly when it should, so
13638 * only enable it on 6bpc panels and when its not a compliance
13639 * test requesting 6bpc video pattern.
13641 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13642 !pipe_config->dither_force_disable;
13643 drm_dbg_kms(&i915->drm,
13644 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13645 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13648 * Make drm_calc_timestamping_constants in
13649 * drm_atomic_helper_update_legacy_modeset_state() happy
13651 pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13657 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13659 struct intel_atomic_state *state =
13660 to_intel_atomic_state(crtc_state->uapi.state);
13661 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13662 struct drm_connector_state *conn_state;
13663 struct drm_connector *connector;
13666 for_each_new_connector_in_state(&state->base, connector,
13668 struct intel_encoder *encoder =
13669 to_intel_encoder(conn_state->best_encoder);
13672 if (conn_state->crtc != &crtc->base ||
13673 !encoder->compute_config_late)
13676 ret = encoder->compute_config_late(encoder, crtc_state,
13685 bool intel_fuzzy_clock_check(int clock1, int clock2)
13689 if (clock1 == clock2)
13692 if (!clock1 || !clock2)
13695 diff = abs(clock1 - clock2);
13697 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13704 intel_compare_m_n(unsigned int m, unsigned int n,
13705 unsigned int m2, unsigned int n2,
13708 if (m == m2 && n == n2)
13711 if (exact || !m || !n || !m2 || !n2)
13714 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13721 } else if (n < n2) {
13731 return intel_fuzzy_clock_check(m, m2);
13735 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13736 const struct intel_link_m_n *m2_n2,
13739 return m_n->tu == m2_n2->tu &&
13740 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13741 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13742 intel_compare_m_n(m_n->link_m, m_n->link_n,
13743 m2_n2->link_m, m2_n2->link_n, exact);
13747 intel_compare_infoframe(const union hdmi_infoframe *a,
13748 const union hdmi_infoframe *b)
13750 return memcmp(a, b, sizeof(*a)) == 0;
13754 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13755 const struct drm_dp_vsc_sdp *b)
13757 return memcmp(a, b, sizeof(*a)) == 0;
13761 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13762 bool fastset, const char *name,
13763 const union hdmi_infoframe *a,
13764 const union hdmi_infoframe *b)
13767 if (!drm_debug_enabled(DRM_UT_KMS))
13770 drm_dbg_kms(&dev_priv->drm,
13771 "fastset mismatch in %s infoframe\n", name);
13772 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13773 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13774 drm_dbg_kms(&dev_priv->drm, "found:\n");
13775 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13777 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13778 drm_err(&dev_priv->drm, "expected:\n");
13779 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13780 drm_err(&dev_priv->drm, "found:\n");
13781 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13786 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13787 bool fastset, const char *name,
13788 const struct drm_dp_vsc_sdp *a,
13789 const struct drm_dp_vsc_sdp *b)
13792 if (!drm_debug_enabled(DRM_UT_KMS))
13795 drm_dbg_kms(&dev_priv->drm,
13796 "fastset mismatch in %s dp sdp\n", name);
13797 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13798 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13799 drm_dbg_kms(&dev_priv->drm, "found:\n");
13800 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13802 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13803 drm_err(&dev_priv->drm, "expected:\n");
13804 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13805 drm_err(&dev_priv->drm, "found:\n");
13806 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13810 static void __printf(4, 5)
13811 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13812 const char *name, const char *format, ...)
13814 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13815 struct va_format vaf;
13818 va_start(args, format);
13823 drm_dbg_kms(&i915->drm,
13824 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13825 crtc->base.base.id, crtc->base.name, name, &vaf);
13827 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13828 crtc->base.base.id, crtc->base.name, name, &vaf);
13833 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13835 if (dev_priv->params.fastboot != -1)
13836 return dev_priv->params.fastboot;
13838 /* Enable fastboot by default on Skylake and newer */
13839 if (INTEL_GEN(dev_priv) >= 9)
13842 /* Enable fastboot by default on VLV and CHV */
13843 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13846 /* Disabled by default on all others */
13851 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13852 const struct intel_crtc_state *pipe_config,
13855 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13856 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13859 bool fixup_inherited = fastset &&
13860 current_config->inherited && !pipe_config->inherited;
13862 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13863 drm_dbg_kms(&dev_priv->drm,
13864 "initial modeset and fastboot not set\n");
13868 #define PIPE_CONF_CHECK_X(name) do { \
13869 if (current_config->name != pipe_config->name) { \
13870 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13871 "(expected 0x%08x, found 0x%08x)", \
13872 current_config->name, \
13873 pipe_config->name); \
13878 #define PIPE_CONF_CHECK_I(name) do { \
13879 if (current_config->name != pipe_config->name) { \
13880 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13881 "(expected %i, found %i)", \
13882 current_config->name, \
13883 pipe_config->name); \
13888 #define PIPE_CONF_CHECK_BOOL(name) do { \
13889 if (current_config->name != pipe_config->name) { \
13890 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13891 "(expected %s, found %s)", \
13892 yesno(current_config->name), \
13893 yesno(pipe_config->name)); \
13899 * Checks state where we only read out the enabling, but not the entire
13900 * state itself (like full infoframes or ELD for audio). These states
13901 * require a full modeset on bootup to fix up.
13903 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13904 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13905 PIPE_CONF_CHECK_BOOL(name); \
13907 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13908 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13909 yesno(current_config->name), \
13910 yesno(pipe_config->name)); \
13915 #define PIPE_CONF_CHECK_P(name) do { \
13916 if (current_config->name != pipe_config->name) { \
13917 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13918 "(expected %p, found %p)", \
13919 current_config->name, \
13920 pipe_config->name); \
13925 #define PIPE_CONF_CHECK_M_N(name) do { \
13926 if (!intel_compare_link_m_n(¤t_config->name, \
13927 &pipe_config->name,\
13929 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13930 "(expected tu %i gmch %i/%i link %i/%i, " \
13931 "found tu %i, gmch %i/%i link %i/%i)", \
13932 current_config->name.tu, \
13933 current_config->name.gmch_m, \
13934 current_config->name.gmch_n, \
13935 current_config->name.link_m, \
13936 current_config->name.link_n, \
13937 pipe_config->name.tu, \
13938 pipe_config->name.gmch_m, \
13939 pipe_config->name.gmch_n, \
13940 pipe_config->name.link_m, \
13941 pipe_config->name.link_n); \
13946 /* This is required for BDW+ where there is only one set of registers for
13947 * switching between high and low RR.
13948 * This macro can be used whenever a comparison has to be made between one
13949 * hw state and multiple sw state variables.
13951 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13952 if (!intel_compare_link_m_n(¤t_config->name, \
13953 &pipe_config->name, !fastset) && \
13954 !intel_compare_link_m_n(¤t_config->alt_name, \
13955 &pipe_config->name, !fastset)) { \
13956 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13957 "(expected tu %i gmch %i/%i link %i/%i, " \
13958 "or tu %i gmch %i/%i link %i/%i, " \
13959 "found tu %i, gmch %i/%i link %i/%i)", \
13960 current_config->name.tu, \
13961 current_config->name.gmch_m, \
13962 current_config->name.gmch_n, \
13963 current_config->name.link_m, \
13964 current_config->name.link_n, \
13965 current_config->alt_name.tu, \
13966 current_config->alt_name.gmch_m, \
13967 current_config->alt_name.gmch_n, \
13968 current_config->alt_name.link_m, \
13969 current_config->alt_name.link_n, \
13970 pipe_config->name.tu, \
13971 pipe_config->name.gmch_m, \
13972 pipe_config->name.gmch_n, \
13973 pipe_config->name.link_m, \
13974 pipe_config->name.link_n); \
13979 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13980 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13981 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13982 "(%x) (expected %i, found %i)", \
13984 current_config->name & (mask), \
13985 pipe_config->name & (mask)); \
13990 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13991 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13992 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13993 "(expected %i, found %i)", \
13994 current_config->name, \
13995 pipe_config->name); \
14000 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
14001 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
14002 &pipe_config->infoframes.name)) { \
14003 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
14004 ¤t_config->infoframes.name, \
14005 &pipe_config->infoframes.name); \
14010 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
14011 if (!current_config->has_psr && !pipe_config->has_psr && \
14012 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
14013 &pipe_config->infoframes.name)) { \
14014 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
14015 ¤t_config->infoframes.name, \
14016 &pipe_config->infoframes.name); \
14021 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
14022 if (current_config->name1 != pipe_config->name1) { \
14023 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
14024 "(expected %i, found %i, won't compare lut values)", \
14025 current_config->name1, \
14026 pipe_config->name1); \
14029 if (!intel_color_lut_equal(current_config->name2, \
14030 pipe_config->name2, pipe_config->name1, \
14031 bit_precision)) { \
14032 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
14033 "hw_state doesn't match sw_state"); \
14039 #define PIPE_CONF_QUIRK(quirk) \
14040 ((current_config->quirks | pipe_config->quirks) & (quirk))
14042 PIPE_CONF_CHECK_I(cpu_transcoder);
14044 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
14045 PIPE_CONF_CHECK_I(fdi_lanes);
14046 PIPE_CONF_CHECK_M_N(fdi_m_n);
14048 PIPE_CONF_CHECK_I(lane_count);
14049 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
14051 if (INTEL_GEN(dev_priv) < 8) {
14052 PIPE_CONF_CHECK_M_N(dp_m_n);
14054 if (current_config->has_drrs)
14055 PIPE_CONF_CHECK_M_N(dp_m2_n2);
14057 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
14059 PIPE_CONF_CHECK_X(output_types);
14061 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
14062 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
14063 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
14064 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
14065 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
14066 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
14068 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
14069 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
14070 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
14071 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
14072 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
14073 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
14075 PIPE_CONF_CHECK_I(pixel_multiplier);
14076 PIPE_CONF_CHECK_I(output_format);
14077 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
14078 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
14079 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14080 PIPE_CONF_CHECK_BOOL(limited_color_range);
14082 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
14083 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
14084 PIPE_CONF_CHECK_BOOL(has_infoframe);
14085 PIPE_CONF_CHECK_BOOL(fec_enable);
14087 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
14089 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14090 DRM_MODE_FLAG_INTERLACE);
14092 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
14093 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14094 DRM_MODE_FLAG_PHSYNC);
14095 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14096 DRM_MODE_FLAG_NHSYNC);
14097 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14098 DRM_MODE_FLAG_PVSYNC);
14099 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14100 DRM_MODE_FLAG_NVSYNC);
14103 PIPE_CONF_CHECK_X(gmch_pfit.control);
14104 /* pfit ratios are autocomputed by the hw on gen4+ */
14105 if (INTEL_GEN(dev_priv) < 4)
14106 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
14107 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
14110 * Changing the EDP transcoder input mux
14111 * (A_ONOFF vs. A_ON) requires a full modeset.
14113 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
14116 PIPE_CONF_CHECK_I(pipe_src_w);
14117 PIPE_CONF_CHECK_I(pipe_src_h);
14119 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
14120 if (current_config->pch_pfit.enabled) {
14121 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
14122 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
14123 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
14124 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
14127 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
14128 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
14130 PIPE_CONF_CHECK_X(gamma_mode);
14131 if (IS_CHERRYVIEW(dev_priv))
14132 PIPE_CONF_CHECK_X(cgm_mode);
14134 PIPE_CONF_CHECK_X(csc_mode);
14135 PIPE_CONF_CHECK_BOOL(gamma_enable);
14136 PIPE_CONF_CHECK_BOOL(csc_enable);
14138 PIPE_CONF_CHECK_I(linetime);
14139 PIPE_CONF_CHECK_I(ips_linetime);
14141 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
14143 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
14146 PIPE_CONF_CHECK_BOOL(double_wide);
14148 PIPE_CONF_CHECK_P(shared_dpll);
14149 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
14150 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
14151 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
14152 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
14153 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
14154 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
14155 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
14156 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
14157 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
14158 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
14159 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
14160 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14161 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14162 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14163 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14164 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14165 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14166 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14167 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14168 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14169 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14170 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14171 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14172 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14173 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14174 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14175 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14176 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14177 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14178 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14179 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14181 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14182 PIPE_CONF_CHECK_X(dsi_pll.div);
14184 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14185 PIPE_CONF_CHECK_I(pipe_bpp);
14187 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14188 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14190 PIPE_CONF_CHECK_I(min_voltage_level);
14192 PIPE_CONF_CHECK_X(infoframes.enable);
14193 PIPE_CONF_CHECK_X(infoframes.gcp);
14194 PIPE_CONF_CHECK_INFOFRAME(avi);
14195 PIPE_CONF_CHECK_INFOFRAME(spd);
14196 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14197 PIPE_CONF_CHECK_INFOFRAME(drm);
14198 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14200 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14201 PIPE_CONF_CHECK_I(master_transcoder);
14203 PIPE_CONF_CHECK_I(dsc.compression_enable);
14204 PIPE_CONF_CHECK_I(dsc.dsc_split);
14205 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14207 PIPE_CONF_CHECK_I(mst_master_transcoder);
14209 #undef PIPE_CONF_CHECK_X
14210 #undef PIPE_CONF_CHECK_I
14211 #undef PIPE_CONF_CHECK_BOOL
14212 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14213 #undef PIPE_CONF_CHECK_P
14214 #undef PIPE_CONF_CHECK_FLAGS
14215 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14216 #undef PIPE_CONF_CHECK_COLOR_LUT
14217 #undef PIPE_CONF_QUIRK
14222 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14223 const struct intel_crtc_state *pipe_config)
14225 if (pipe_config->has_pch_encoder) {
14226 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14227 &pipe_config->fdi_m_n);
14228 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14231 * FDI already provided one idea for the dotclock.
14232 * Yell if the encoder disagrees.
14234 drm_WARN(&dev_priv->drm,
14235 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14236 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14237 fdi_dotclock, dotclock);
14241 static void verify_wm_state(struct intel_crtc *crtc,
14242 struct intel_crtc_state *new_crtc_state)
14244 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14245 struct skl_hw_state {
14246 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14247 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14248 struct skl_pipe_wm wm;
14250 struct skl_pipe_wm *sw_wm;
14251 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14252 u8 hw_enabled_slices;
14253 const enum pipe pipe = crtc->pipe;
14254 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14256 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14259 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14263 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14264 sw_wm = &new_crtc_state->wm.skl.optimal;
14266 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14268 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14270 if (INTEL_GEN(dev_priv) >= 11 &&
14271 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14272 drm_err(&dev_priv->drm,
14273 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14274 dev_priv->dbuf.enabled_slices,
14275 hw_enabled_slices);
14278 for_each_universal_plane(dev_priv, pipe, plane) {
14279 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14281 hw_plane_wm = &hw->wm.planes[plane];
14282 sw_plane_wm = &sw_wm->planes[plane];
14285 for (level = 0; level <= max_level; level++) {
14286 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14287 &sw_plane_wm->wm[level]) ||
14288 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14289 &sw_plane_wm->sagv_wm0)))
14292 drm_err(&dev_priv->drm,
14293 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14294 pipe_name(pipe), plane + 1, level,
14295 sw_plane_wm->wm[level].plane_en,
14296 sw_plane_wm->wm[level].plane_res_b,
14297 sw_plane_wm->wm[level].plane_res_l,
14298 hw_plane_wm->wm[level].plane_en,
14299 hw_plane_wm->wm[level].plane_res_b,
14300 hw_plane_wm->wm[level].plane_res_l);
14303 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14304 &sw_plane_wm->trans_wm)) {
14305 drm_err(&dev_priv->drm,
14306 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14307 pipe_name(pipe), plane + 1,
14308 sw_plane_wm->trans_wm.plane_en,
14309 sw_plane_wm->trans_wm.plane_res_b,
14310 sw_plane_wm->trans_wm.plane_res_l,
14311 hw_plane_wm->trans_wm.plane_en,
14312 hw_plane_wm->trans_wm.plane_res_b,
14313 hw_plane_wm->trans_wm.plane_res_l);
14317 hw_ddb_entry = &hw->ddb_y[plane];
14318 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14320 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14321 drm_err(&dev_priv->drm,
14322 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14323 pipe_name(pipe), plane + 1,
14324 sw_ddb_entry->start, sw_ddb_entry->end,
14325 hw_ddb_entry->start, hw_ddb_entry->end);
14331 * If the cursor plane isn't active, we may not have updated it's ddb
14332 * allocation. In that case since the ddb allocation will be updated
14333 * once the plane becomes visible, we can skip this check
14336 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14338 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14339 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14342 for (level = 0; level <= max_level; level++) {
14343 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14344 &sw_plane_wm->wm[level]) ||
14345 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14346 &sw_plane_wm->sagv_wm0)))
14349 drm_err(&dev_priv->drm,
14350 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14351 pipe_name(pipe), level,
14352 sw_plane_wm->wm[level].plane_en,
14353 sw_plane_wm->wm[level].plane_res_b,
14354 sw_plane_wm->wm[level].plane_res_l,
14355 hw_plane_wm->wm[level].plane_en,
14356 hw_plane_wm->wm[level].plane_res_b,
14357 hw_plane_wm->wm[level].plane_res_l);
14360 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14361 &sw_plane_wm->trans_wm)) {
14362 drm_err(&dev_priv->drm,
14363 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14365 sw_plane_wm->trans_wm.plane_en,
14366 sw_plane_wm->trans_wm.plane_res_b,
14367 sw_plane_wm->trans_wm.plane_res_l,
14368 hw_plane_wm->trans_wm.plane_en,
14369 hw_plane_wm->trans_wm.plane_res_b,
14370 hw_plane_wm->trans_wm.plane_res_l);
14374 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14375 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14377 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14378 drm_err(&dev_priv->drm,
14379 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14381 sw_ddb_entry->start, sw_ddb_entry->end,
14382 hw_ddb_entry->start, hw_ddb_entry->end);
14390 verify_connector_state(struct intel_atomic_state *state,
14391 struct intel_crtc *crtc)
14393 struct drm_connector *connector;
14394 struct drm_connector_state *new_conn_state;
14397 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14398 struct drm_encoder *encoder = connector->encoder;
14399 struct intel_crtc_state *crtc_state = NULL;
14401 if (new_conn_state->crtc != &crtc->base)
14405 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14407 intel_connector_verify_state(crtc_state, new_conn_state);
14409 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14410 "connector's atomic encoder doesn't match legacy encoder\n");
14415 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14417 struct intel_encoder *encoder;
14418 struct drm_connector *connector;
14419 struct drm_connector_state *old_conn_state, *new_conn_state;
14422 for_each_intel_encoder(&dev_priv->drm, encoder) {
14423 bool enabled = false, found = false;
14426 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14427 encoder->base.base.id,
14428 encoder->base.name);
14430 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14431 new_conn_state, i) {
14432 if (old_conn_state->best_encoder == &encoder->base)
14435 if (new_conn_state->best_encoder != &encoder->base)
14437 found = enabled = true;
14439 I915_STATE_WARN(new_conn_state->crtc !=
14440 encoder->base.crtc,
14441 "connector's crtc doesn't match encoder crtc\n");
14447 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14448 "encoder's enabled state mismatch "
14449 "(expected %i, found %i)\n",
14450 !!encoder->base.crtc, enabled);
14452 if (!encoder->base.crtc) {
14455 active = encoder->get_hw_state(encoder, &pipe);
14456 I915_STATE_WARN(active,
14457 "encoder detached but still enabled on pipe %c.\n",
14464 verify_crtc_state(struct intel_crtc *crtc,
14465 struct intel_crtc_state *old_crtc_state,
14466 struct intel_crtc_state *new_crtc_state)
14468 struct drm_device *dev = crtc->base.dev;
14469 struct drm_i915_private *dev_priv = to_i915(dev);
14470 struct intel_encoder *encoder;
14471 struct intel_crtc_state *pipe_config = old_crtc_state;
14472 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14474 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14475 intel_crtc_free_hw_state(old_crtc_state);
14476 intel_crtc_state_reset(old_crtc_state, crtc);
14477 old_crtc_state->uapi.state = state;
14479 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14482 pipe_config->hw.enable = new_crtc_state->hw.enable;
14484 pipe_config->hw.active =
14485 dev_priv->display.get_pipe_config(crtc, pipe_config);
14487 /* we keep both pipes enabled on 830 */
14488 if (IS_I830(dev_priv) && pipe_config->hw.active)
14489 pipe_config->hw.active = new_crtc_state->hw.active;
14491 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14492 "crtc active state doesn't match with hw state "
14493 "(expected %i, found %i)\n",
14494 new_crtc_state->hw.active, pipe_config->hw.active);
14496 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14497 "transitional active state does not match atomic hw state "
14498 "(expected %i, found %i)\n",
14499 new_crtc_state->hw.active, crtc->active);
14501 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14505 active = encoder->get_hw_state(encoder, &pipe);
14506 I915_STATE_WARN(active != new_crtc_state->hw.active,
14507 "[ENCODER:%i] active %i with crtc active %i\n",
14508 encoder->base.base.id, active,
14509 new_crtc_state->hw.active);
14511 I915_STATE_WARN(active && crtc->pipe != pipe,
14512 "Encoder connected to wrong pipe %c\n",
14516 encoder->get_config(encoder, pipe_config);
14519 intel_crtc_compute_pixel_rate(pipe_config);
14521 if (!new_crtc_state->hw.active)
14524 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14526 if (!intel_pipe_config_compare(new_crtc_state,
14527 pipe_config, false)) {
14528 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14529 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14530 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14535 intel_verify_planes(struct intel_atomic_state *state)
14537 struct intel_plane *plane;
14538 const struct intel_plane_state *plane_state;
14541 for_each_new_intel_plane_in_state(state, plane,
14543 assert_plane(plane, plane_state->planar_slave ||
14544 plane_state->uapi.visible);
14548 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14549 struct intel_shared_dpll *pll,
14550 struct intel_crtc *crtc,
14551 struct intel_crtc_state *new_crtc_state)
14553 struct intel_dpll_hw_state dpll_hw_state;
14554 unsigned int crtc_mask;
14557 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14559 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14561 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14563 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14564 I915_STATE_WARN(!pll->on && pll->active_mask,
14565 "pll in active use but not on in sw tracking\n");
14566 I915_STATE_WARN(pll->on && !pll->active_mask,
14567 "pll is on but not used by any active crtc\n");
14568 I915_STATE_WARN(pll->on != active,
14569 "pll on state mismatch (expected %i, found %i)\n",
14574 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14575 "more active pll users than references: %x vs %x\n",
14576 pll->active_mask, pll->state.crtc_mask);
14581 crtc_mask = drm_crtc_mask(&crtc->base);
14583 if (new_crtc_state->hw.active)
14584 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14585 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14586 pipe_name(crtc->pipe), pll->active_mask);
14588 I915_STATE_WARN(pll->active_mask & crtc_mask,
14589 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14590 pipe_name(crtc->pipe), pll->active_mask);
14592 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14593 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14594 crtc_mask, pll->state.crtc_mask);
14596 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14598 sizeof(dpll_hw_state)),
14599 "pll hw state mismatch\n");
14603 verify_shared_dpll_state(struct intel_crtc *crtc,
14604 struct intel_crtc_state *old_crtc_state,
14605 struct intel_crtc_state *new_crtc_state)
14607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14609 if (new_crtc_state->shared_dpll)
14610 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14612 if (old_crtc_state->shared_dpll &&
14613 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14614 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14615 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14617 I915_STATE_WARN(pll->active_mask & crtc_mask,
14618 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14619 pipe_name(crtc->pipe));
14620 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14621 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14622 pipe_name(crtc->pipe));
14627 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14628 struct intel_atomic_state *state,
14629 struct intel_crtc_state *old_crtc_state,
14630 struct intel_crtc_state *new_crtc_state)
14632 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14635 verify_wm_state(crtc, new_crtc_state);
14636 verify_connector_state(state, crtc);
14637 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14638 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14642 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14646 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14647 verify_single_dpll_state(dev_priv,
14648 &dev_priv->dpll.shared_dplls[i],
14653 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14654 struct intel_atomic_state *state)
14656 verify_encoder_state(dev_priv, state);
14657 verify_connector_state(state, NULL);
14658 verify_disabled_dpll_state(dev_priv);
14662 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14664 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14666 const struct drm_display_mode *adjusted_mode =
14667 &crtc_state->hw.adjusted_mode;
14669 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14671 crtc->mode_flags = crtc_state->mode_flags;
14674 * The scanline counter increments at the leading edge of hsync.
14676 * On most platforms it starts counting from vtotal-1 on the
14677 * first active line. That means the scanline counter value is
14678 * always one less than what we would expect. Ie. just after
14679 * start of vblank, which also occurs at start of hsync (on the
14680 * last active line), the scanline counter will read vblank_start-1.
14682 * On gen2 the scanline counter starts counting from 1 instead
14683 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14684 * to keep the value positive), instead of adding one.
14686 * On HSW+ the behaviour of the scanline counter depends on the output
14687 * type. For DP ports it behaves like most other platforms, but on HDMI
14688 * there's an extra 1 line difference. So we need to add two instead of
14689 * one to the value.
14691 * On VLV/CHV DSI the scanline counter would appear to increment
14692 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14693 * that means we can't tell whether we're in vblank or not while
14694 * we're on that particular line. We must still set scanline_offset
14695 * to 1 so that the vblank timestamps come out correct when we query
14696 * the scanline counter from within the vblank interrupt handler.
14697 * However if queried just before the start of vblank we'll get an
14698 * answer that's slightly in the future.
14700 if (IS_GEN(dev_priv, 2)) {
14703 vtotal = adjusted_mode->crtc_vtotal;
14704 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14707 crtc->scanline_offset = vtotal - 1;
14708 } else if (HAS_DDI(dev_priv) &&
14709 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14710 crtc->scanline_offset = 2;
14712 crtc->scanline_offset = 1;
14716 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14718 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14719 struct intel_crtc_state *new_crtc_state;
14720 struct intel_crtc *crtc;
14723 if (!dev_priv->display.crtc_compute_clock)
14726 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14727 if (!needs_modeset(new_crtc_state))
14730 intel_release_shared_dplls(state, crtc);
14735 * This implements the workaround described in the "notes" section of the mode
14736 * set sequence documentation. When going from no pipes or single pipe to
14737 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14738 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14740 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14742 struct intel_crtc_state *crtc_state;
14743 struct intel_crtc *crtc;
14744 struct intel_crtc_state *first_crtc_state = NULL;
14745 struct intel_crtc_state *other_crtc_state = NULL;
14746 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14749 /* look at all crtc's that are going to be enabled in during modeset */
14750 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14751 if (!crtc_state->hw.active ||
14752 !needs_modeset(crtc_state))
14755 if (first_crtc_state) {
14756 other_crtc_state = crtc_state;
14759 first_crtc_state = crtc_state;
14760 first_pipe = crtc->pipe;
14764 /* No workaround needed? */
14765 if (!first_crtc_state)
14768 /* w/a possibly needed, check how many crtc's are already enabled. */
14769 for_each_intel_crtc(state->base.dev, crtc) {
14770 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14771 if (IS_ERR(crtc_state))
14772 return PTR_ERR(crtc_state);
14774 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14776 if (!crtc_state->hw.active ||
14777 needs_modeset(crtc_state))
14780 /* 2 or more enabled crtcs means no need for w/a */
14781 if (enabled_pipe != INVALID_PIPE)
14784 enabled_pipe = crtc->pipe;
14787 if (enabled_pipe != INVALID_PIPE)
14788 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14789 else if (other_crtc_state)
14790 other_crtc_state->hsw_workaround_pipe = first_pipe;
14795 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14798 const struct intel_crtc_state *crtc_state;
14799 struct intel_crtc *crtc;
14802 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14803 if (crtc_state->hw.active)
14804 active_pipes |= BIT(crtc->pipe);
14806 active_pipes &= ~BIT(crtc->pipe);
14809 return active_pipes;
14812 static int intel_modeset_checks(struct intel_atomic_state *state)
14814 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14816 state->modeset = true;
14818 if (IS_HASWELL(dev_priv))
14819 return hsw_mode_set_planes_workaround(state);
14825 * Handle calculation of various watermark data at the end of the atomic check
14826 * phase. The code here should be run after the per-crtc and per-plane 'check'
14827 * handlers to ensure that all derived state has been updated.
14829 static int calc_watermark_data(struct intel_atomic_state *state)
14831 struct drm_device *dev = state->base.dev;
14832 struct drm_i915_private *dev_priv = to_i915(dev);
14834 /* Is there platform-specific watermark information to calculate? */
14835 if (dev_priv->display.compute_global_watermarks)
14836 return dev_priv->display.compute_global_watermarks(state);
14841 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14842 struct intel_crtc_state *new_crtc_state)
14844 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14847 new_crtc_state->uapi.mode_changed = false;
14848 new_crtc_state->update_pipe = true;
14851 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14852 struct intel_crtc_state *new_crtc_state)
14855 * If we're not doing the full modeset we want to
14856 * keep the current M/N values as they may be
14857 * sufficiently different to the computed values
14858 * to cause problems.
14860 * FIXME: should really copy more fuzzy state here
14862 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14863 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14864 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14865 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14868 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14869 struct intel_crtc *crtc,
14872 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14873 struct intel_plane *plane;
14875 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14876 struct intel_plane_state *plane_state;
14878 if ((plane_ids_mask & BIT(plane->id)) == 0)
14881 plane_state = intel_atomic_get_plane_state(state, plane);
14882 if (IS_ERR(plane_state))
14883 return PTR_ERR(plane_state);
14889 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14891 /* See {hsw,vlv,ivb}_plane_ratio() */
14892 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14893 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14894 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14897 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14899 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14900 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14901 struct intel_plane_state *plane_state;
14902 struct intel_plane *plane;
14903 struct intel_crtc *crtc;
14906 ret = icl_add_linked_planes(state);
14910 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14911 ret = intel_plane_atomic_check(state, plane);
14913 drm_dbg_atomic(&dev_priv->drm,
14914 "[PLANE:%d:%s] atomic driver check failed\n",
14915 plane->base.base.id, plane->base.name);
14920 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14921 new_crtc_state, i) {
14922 u8 old_active_planes, new_active_planes;
14924 ret = icl_check_nv12_planes(new_crtc_state);
14929 * On some platforms the number of active planes affects
14930 * the planes' minimum cdclk calculation. Add such planes
14931 * to the state before we compute the minimum cdclk.
14933 if (!active_planes_affects_min_cdclk(dev_priv))
14936 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14937 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14940 * Not only the number of planes, but if the plane configuration had
14941 * changed might already mean we need to recompute min CDCLK,
14942 * because different planes might consume different amount of Dbuf bandwidth
14943 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14945 if (old_active_planes == new_active_planes)
14948 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14956 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14957 bool *need_cdclk_calc)
14959 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14960 const struct intel_cdclk_state *old_cdclk_state;
14961 const struct intel_cdclk_state *new_cdclk_state;
14962 struct intel_plane_state *plane_state;
14963 struct intel_bw_state *new_bw_state;
14964 struct intel_plane *plane;
14970 * active_planes bitmask has been updated, and potentially
14971 * affected planes are part of the state. We can now
14972 * compute the minimum cdclk for each plane.
14974 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14975 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14980 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14981 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14983 if (new_cdclk_state &&
14984 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14985 *need_cdclk_calc = true;
14987 ret = dev_priv->display.bw_calc_min_cdclk(state);
14991 new_bw_state = intel_atomic_get_new_bw_state(state);
14993 if (!new_cdclk_state || !new_bw_state)
14996 for_each_pipe(dev_priv, pipe) {
14997 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
15000 * Currently do this change only if we need to increase
15002 if (new_bw_state->min_cdclk > min_cdclk)
15003 *need_cdclk_calc = true;
15009 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
15011 struct intel_crtc_state *crtc_state;
15012 struct intel_crtc *crtc;
15015 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15016 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
15019 ret = intel_crtc_atomic_check(state, crtc);
15021 drm_dbg_atomic(&i915->drm,
15022 "[CRTC:%d:%s] atomic driver check failed\n",
15023 crtc->base.base.id, crtc->base.name);
15031 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
15034 const struct intel_crtc_state *new_crtc_state;
15035 struct intel_crtc *crtc;
15038 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15039 if (new_crtc_state->hw.enable &&
15040 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
15041 needs_modeset(new_crtc_state))
15049 * DOC: asynchronous flip implementation
15051 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
15052 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
15053 * Correspondingly, support is currently added for primary plane only.
15055 * Async flip can only change the plane surface address, so anything else
15056 * changing is rejected from the intel_atomic_check_async() function.
15057 * Once this check is cleared, flip done interrupt is enabled using
15058 * the skl_enable_flip_done() function.
15060 * As soon as the surface address register is written, flip done interrupt is
15061 * generated and the requested events are sent to the usersapce in the interrupt
15062 * handler itself. The timestamp and sequence sent during the flip done event
15063 * correspond to the last vblank and have no relation to the actual time when
15064 * the flip done event was sent.
15066 static int intel_atomic_check_async(struct intel_atomic_state *state)
15068 struct drm_i915_private *i915 = to_i915(state->base.dev);
15069 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15070 const struct intel_plane_state *new_plane_state, *old_plane_state;
15071 struct intel_crtc *crtc;
15072 struct intel_plane *plane;
15075 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15076 new_crtc_state, i) {
15077 if (needs_modeset(new_crtc_state)) {
15078 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
15082 if (!new_crtc_state->hw.active) {
15083 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
15086 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
15087 drm_dbg_kms(&i915->drm,
15088 "Active planes cannot be changed during async flip\n");
15093 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15094 new_plane_state, i) {
15096 * TODO: Async flip is only supported through the page flip IOCTL
15097 * as of now. So support currently added for primary plane only.
15098 * Support for other planes on platforms on which supports
15099 * this(vlv/chv and icl+) should be added when async flip is
15100 * enabled in the atomic IOCTL path.
15102 if (plane->id != PLANE_PRIMARY)
15106 * FIXME: This check is kept generic for all platforms.
15107 * Need to verify this for all gen9 and gen10 platforms to enable
15108 * this selectively if required.
15110 switch (new_plane_state->hw.fb->modifier) {
15111 case I915_FORMAT_MOD_X_TILED:
15112 case I915_FORMAT_MOD_Y_TILED:
15113 case I915_FORMAT_MOD_Yf_TILED:
15116 drm_dbg_kms(&i915->drm,
15117 "Linear memory/CCS does not support async flips\n");
15121 if (old_plane_state->color_plane[0].stride !=
15122 new_plane_state->color_plane[0].stride) {
15123 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
15127 if (old_plane_state->hw.fb->modifier !=
15128 new_plane_state->hw.fb->modifier) {
15129 drm_dbg_kms(&i915->drm,
15130 "Framebuffer modifiers cannot be changed in async flip\n");
15134 if (old_plane_state->hw.fb->format !=
15135 new_plane_state->hw.fb->format) {
15136 drm_dbg_kms(&i915->drm,
15137 "Framebuffer format cannot be changed in async flip\n");
15141 if (old_plane_state->hw.rotation !=
15142 new_plane_state->hw.rotation) {
15143 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
15147 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
15148 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
15149 drm_dbg_kms(&i915->drm,
15150 "Plane size/co-ordinates cannot be changed in async flip\n");
15154 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
15155 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
15159 if (old_plane_state->hw.pixel_blend_mode !=
15160 new_plane_state->hw.pixel_blend_mode) {
15161 drm_dbg_kms(&i915->drm,
15162 "Pixel blend mode cannot be changed in async flip\n");
15166 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
15167 drm_dbg_kms(&i915->drm,
15168 "Color encoding cannot be changed in async flip\n");
15172 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
15173 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
15182 * intel_atomic_check - validate state object
15184 * @_state: state to validate
15186 static int intel_atomic_check(struct drm_device *dev,
15187 struct drm_atomic_state *_state)
15189 struct drm_i915_private *dev_priv = to_i915(dev);
15190 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15191 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15192 struct intel_crtc *crtc;
15194 bool any_ms = false;
15196 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15197 new_crtc_state, i) {
15198 if (new_crtc_state->inherited != old_crtc_state->inherited)
15199 new_crtc_state->uapi.mode_changed = true;
15202 ret = drm_atomic_helper_check_modeset(dev, &state->base);
15206 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15207 new_crtc_state, i) {
15208 if (!needs_modeset(new_crtc_state)) {
15210 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
15215 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
15219 if (!new_crtc_state->hw.enable)
15222 ret = intel_modeset_pipe_config(new_crtc_state);
15227 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15228 new_crtc_state, i) {
15229 if (!needs_modeset(new_crtc_state))
15232 ret = intel_modeset_pipe_config_late(new_crtc_state);
15236 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
15240 * Check if fastset is allowed by external dependencies like other
15241 * pipes and transcoders.
15243 * Right now it only forces a fullmodeset when the MST master
15244 * transcoder did not changed but the pipe of the master transcoder
15245 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
15246 * in case of port synced crtcs, if one of the synced crtcs
15247 * needs a full modeset, all other synced crtcs should be
15248 * forced a full modeset.
15250 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15251 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
15254 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
15255 enum transcoder master = new_crtc_state->mst_master_transcoder;
15257 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
15258 new_crtc_state->uapi.mode_changed = true;
15259 new_crtc_state->update_pipe = false;
15263 if (is_trans_port_sync_mode(new_crtc_state)) {
15264 u8 trans = new_crtc_state->sync_mode_slaves_mask;
15266 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
15267 trans |= BIT(new_crtc_state->master_transcoder);
15269 if (intel_cpu_transcoders_need_modeset(state, trans)) {
15270 new_crtc_state->uapi.mode_changed = true;
15271 new_crtc_state->update_pipe = false;
15276 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15277 new_crtc_state, i) {
15278 if (needs_modeset(new_crtc_state)) {
15283 if (!new_crtc_state->update_pipe)
15286 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
15289 if (any_ms && !check_digital_port_conflicts(state)) {
15290 drm_dbg_kms(&dev_priv->drm,
15291 "rejecting conflicting digital port configuration\n");
15296 ret = drm_dp_mst_atomic_check(&state->base);
15300 ret = intel_atomic_check_planes(state);
15305 * distrust_bios_wm will force a full dbuf recomputation
15306 * but the hardware state will only get updated accordingly
15307 * if state->modeset==true. Hence distrust_bios_wm==true &&
15308 * state->modeset==false is an invalid combination which
15309 * would cause the hardware and software dbuf state to get
15310 * out of sync. We must prevent that.
15312 * FIXME clean up this mess and introduce better
15313 * state tracking for dbuf.
15315 if (dev_priv->wm.distrust_bios_wm)
15318 intel_fbc_choose_crtc(dev_priv, state);
15319 ret = calc_watermark_data(state);
15323 ret = intel_bw_atomic_check(state);
15327 ret = intel_atomic_check_cdclk(state, &any_ms);
15332 ret = intel_modeset_checks(state);
15336 ret = intel_modeset_calc_cdclk(state);
15340 intel_modeset_clear_plls(state);
15343 ret = intel_atomic_check_crtcs(state);
15347 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15348 new_crtc_state, i) {
15349 if (new_crtc_state->uapi.async_flip) {
15350 ret = intel_atomic_check_async(state);
15355 if (!needs_modeset(new_crtc_state) &&
15356 !new_crtc_state->update_pipe)
15359 intel_dump_pipe_config(new_crtc_state, state,
15360 needs_modeset(new_crtc_state) ?
15361 "[modeset]" : "[fastset]");
15367 if (ret == -EDEADLK)
15371 * FIXME would probably be nice to know which crtc specifically
15372 * caused the failure, in cases where we can pinpoint it.
15374 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15376 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15381 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15383 struct intel_crtc_state *crtc_state;
15384 struct intel_crtc *crtc;
15387 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15391 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15392 bool mode_changed = needs_modeset(crtc_state);
15394 if (mode_changed || crtc_state->update_pipe ||
15395 crtc_state->uapi.color_mgmt_changed) {
15396 intel_dsb_prepare(crtc_state);
15403 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15405 struct drm_device *dev = crtc->base.dev;
15406 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15408 if (!vblank->max_vblank_count)
15409 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15411 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15414 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15415 struct intel_crtc_state *crtc_state)
15417 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15419 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15420 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15422 if (crtc_state->has_pch_encoder) {
15423 enum pipe pch_transcoder =
15424 intel_crtc_pch_transcoder(crtc);
15426 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15430 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15431 const struct intel_crtc_state *new_crtc_state)
15433 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15437 * Update pipe size and adjust fitter if needed: the reason for this is
15438 * that in compute_mode_changes we check the native mode (not the pfit
15439 * mode) to see if we can flip rather than do a full mode set. In the
15440 * fastboot case, we'll flip, but if we don't update the pipesrc and
15441 * pfit state, we'll end up with a big fb scanned out into the wrong
15444 intel_set_pipe_src_size(new_crtc_state);
15446 /* on skylake this is done by detaching scalers */
15447 if (INTEL_GEN(dev_priv) >= 9) {
15448 skl_detach_scalers(new_crtc_state);
15450 if (new_crtc_state->pch_pfit.enabled)
15451 skl_pfit_enable(new_crtc_state);
15452 } else if (HAS_PCH_SPLIT(dev_priv)) {
15453 if (new_crtc_state->pch_pfit.enabled)
15454 ilk_pfit_enable(new_crtc_state);
15455 else if (old_crtc_state->pch_pfit.enabled)
15456 ilk_pfit_disable(old_crtc_state);
15460 * The register is supposedly single buffered so perhaps
15461 * not 100% correct to do this here. But SKL+ calculate
15462 * this based on the adjust pixel rate so pfit changes do
15463 * affect it and so it must be updated for fastsets.
15464 * HSW/BDW only really need this here for fastboot, after
15465 * that the value should not change without a full modeset.
15467 if (INTEL_GEN(dev_priv) >= 9 ||
15468 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15469 hsw_set_linetime_wm(new_crtc_state);
15471 if (INTEL_GEN(dev_priv) >= 11)
15472 icl_set_pipe_chicken(crtc);
15475 static void commit_pipe_config(struct intel_atomic_state *state,
15476 struct intel_crtc *crtc)
15478 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15479 const struct intel_crtc_state *old_crtc_state =
15480 intel_atomic_get_old_crtc_state(state, crtc);
15481 const struct intel_crtc_state *new_crtc_state =
15482 intel_atomic_get_new_crtc_state(state, crtc);
15483 bool modeset = needs_modeset(new_crtc_state);
15486 * During modesets pipe configuration was programmed as the
15487 * CRTC was enabled.
15490 if (new_crtc_state->uapi.color_mgmt_changed ||
15491 new_crtc_state->update_pipe)
15492 intel_color_commit(new_crtc_state);
15494 if (INTEL_GEN(dev_priv) >= 9)
15495 skl_detach_scalers(new_crtc_state);
15497 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15498 bdw_set_pipemisc(new_crtc_state);
15500 if (new_crtc_state->update_pipe)
15501 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15503 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15506 if (dev_priv->display.atomic_update_watermarks)
15507 dev_priv->display.atomic_update_watermarks(state, crtc);
15510 static void intel_enable_crtc(struct intel_atomic_state *state,
15511 struct intel_crtc *crtc)
15513 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15514 const struct intel_crtc_state *new_crtc_state =
15515 intel_atomic_get_new_crtc_state(state, crtc);
15517 if (!needs_modeset(new_crtc_state))
15520 intel_crtc_update_active_timings(new_crtc_state);
15522 dev_priv->display.crtc_enable(state, crtc);
15524 /* vblanks work again, re-enable pipe CRC. */
15525 intel_crtc_enable_pipe_crc(crtc);
15528 static void intel_update_crtc(struct intel_atomic_state *state,
15529 struct intel_crtc *crtc)
15531 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15532 const struct intel_crtc_state *old_crtc_state =
15533 intel_atomic_get_old_crtc_state(state, crtc);
15534 struct intel_crtc_state *new_crtc_state =
15535 intel_atomic_get_new_crtc_state(state, crtc);
15536 bool modeset = needs_modeset(new_crtc_state);
15539 if (new_crtc_state->preload_luts &&
15540 (new_crtc_state->uapi.color_mgmt_changed ||
15541 new_crtc_state->update_pipe))
15542 intel_color_load_luts(new_crtc_state);
15544 intel_pre_plane_update(state, crtc);
15546 if (new_crtc_state->update_pipe)
15547 intel_encoders_update_pipe(state, crtc);
15550 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15551 intel_fbc_disable(crtc);
15553 intel_fbc_enable(state, crtc);
15555 /* Perform vblank evasion around commit operation */
15556 intel_pipe_update_start(new_crtc_state);
15558 commit_pipe_config(state, crtc);
15560 if (INTEL_GEN(dev_priv) >= 9)
15561 skl_update_planes_on_crtc(state, crtc);
15563 i9xx_update_planes_on_crtc(state, crtc);
15565 intel_pipe_update_end(new_crtc_state);
15568 * We usually enable FIFO underrun interrupts as part of the
15569 * CRTC enable sequence during modesets. But when we inherit a
15570 * valid pipe configuration from the BIOS we need to take care
15571 * of enabling them on the CRTC's first fastset.
15573 if (new_crtc_state->update_pipe && !modeset &&
15574 old_crtc_state->inherited)
15575 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15579 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15580 struct intel_crtc_state *old_crtc_state,
15581 struct intel_crtc_state *new_crtc_state,
15582 struct intel_crtc *crtc)
15584 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15586 intel_crtc_disable_planes(state, crtc);
15589 * We need to disable pipe CRC before disabling the pipe,
15590 * or we race against vblank off.
15592 intel_crtc_disable_pipe_crc(crtc);
15594 dev_priv->display.crtc_disable(state, crtc);
15595 crtc->active = false;
15596 intel_fbc_disable(crtc);
15597 intel_disable_shared_dpll(old_crtc_state);
15599 /* FIXME unify this for all platforms */
15600 if (!new_crtc_state->hw.active &&
15601 !HAS_GMCH(dev_priv) &&
15602 dev_priv->display.initial_watermarks)
15603 dev_priv->display.initial_watermarks(state, crtc);
15606 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15608 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15609 struct intel_crtc *crtc;
15613 /* Only disable port sync and MST slaves */
15614 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15615 new_crtc_state, i) {
15616 if (!needs_modeset(new_crtc_state))
15619 if (!old_crtc_state->hw.active)
15622 /* In case of Transcoder port Sync master slave CRTCs can be
15623 * assigned in any order and we need to make sure that
15624 * slave CRTCs are disabled first and then master CRTC since
15625 * Slave vblanks are masked till Master Vblanks.
15627 if (!is_trans_port_sync_slave(old_crtc_state) &&
15628 !intel_dp_mst_is_slave_trans(old_crtc_state))
15631 intel_pre_plane_update(state, crtc);
15632 intel_old_crtc_state_disables(state, old_crtc_state,
15633 new_crtc_state, crtc);
15634 handled |= BIT(crtc->pipe);
15637 /* Disable everything else left on */
15638 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15639 new_crtc_state, i) {
15640 if (!needs_modeset(new_crtc_state) ||
15641 (handled & BIT(crtc->pipe)))
15644 intel_pre_plane_update(state, crtc);
15645 if (old_crtc_state->hw.active)
15646 intel_old_crtc_state_disables(state, old_crtc_state,
15647 new_crtc_state, crtc);
15651 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15653 struct intel_crtc_state *new_crtc_state;
15654 struct intel_crtc *crtc;
15657 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15658 if (!new_crtc_state->hw.active)
15661 intel_enable_crtc(state, crtc);
15662 intel_update_crtc(state, crtc);
15666 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15668 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15669 struct intel_crtc *crtc;
15670 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15671 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15672 u8 update_pipes = 0, modeset_pipes = 0;
15675 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15676 enum pipe pipe = crtc->pipe;
15678 if (!new_crtc_state->hw.active)
15681 /* ignore allocations for crtc's that have been turned off. */
15682 if (!needs_modeset(new_crtc_state)) {
15683 entries[pipe] = old_crtc_state->wm.skl.ddb;
15684 update_pipes |= BIT(pipe);
15686 modeset_pipes |= BIT(pipe);
15691 * Whenever the number of active pipes changes, we need to make sure we
15692 * update the pipes in the right order so that their ddb allocations
15693 * never overlap with each other between CRTC updates. Otherwise we'll
15694 * cause pipe underruns and other bad stuff.
15696 * So first lets enable all pipes that do not need a fullmodeset as
15697 * those don't have any external dependency.
15699 while (update_pipes) {
15700 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15701 new_crtc_state, i) {
15702 enum pipe pipe = crtc->pipe;
15704 if ((update_pipes & BIT(pipe)) == 0)
15707 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15708 entries, I915_MAX_PIPES, pipe))
15711 entries[pipe] = new_crtc_state->wm.skl.ddb;
15712 update_pipes &= ~BIT(pipe);
15714 intel_update_crtc(state, crtc);
15717 * If this is an already active pipe, it's DDB changed,
15718 * and this isn't the last pipe that needs updating
15719 * then we need to wait for a vblank to pass for the
15720 * new ddb allocation to take effect.
15722 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15723 &old_crtc_state->wm.skl.ddb) &&
15724 (update_pipes | modeset_pipes))
15725 intel_wait_for_vblank(dev_priv, pipe);
15729 update_pipes = modeset_pipes;
15732 * Enable all pipes that needs a modeset and do not depends on other
15735 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15736 enum pipe pipe = crtc->pipe;
15738 if ((modeset_pipes & BIT(pipe)) == 0)
15741 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15742 is_trans_port_sync_master(new_crtc_state))
15745 modeset_pipes &= ~BIT(pipe);
15747 intel_enable_crtc(state, crtc);
15751 * Then we enable all remaining pipes that depend on other
15752 * pipes: MST slaves and port sync masters.
15754 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15755 enum pipe pipe = crtc->pipe;
15757 if ((modeset_pipes & BIT(pipe)) == 0)
15760 modeset_pipes &= ~BIT(pipe);
15762 intel_enable_crtc(state, crtc);
15766 * Finally we do the plane updates/etc. for all pipes that got enabled.
15768 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15769 enum pipe pipe = crtc->pipe;
15771 if ((update_pipes & BIT(pipe)) == 0)
15774 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15775 entries, I915_MAX_PIPES, pipe));
15777 entries[pipe] = new_crtc_state->wm.skl.ddb;
15778 update_pipes &= ~BIT(pipe);
15780 intel_update_crtc(state, crtc);
15783 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15784 drm_WARN_ON(&dev_priv->drm, update_pipes);
15787 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15789 struct intel_atomic_state *state, *next;
15790 struct llist_node *freed;
15792 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15793 llist_for_each_entry_safe(state, next, freed, freed)
15794 drm_atomic_state_put(&state->base);
15797 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15799 struct drm_i915_private *dev_priv =
15800 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15802 intel_atomic_helper_free_state(dev_priv);
15805 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15807 struct wait_queue_entry wait_fence, wait_reset;
15808 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15810 init_wait_entry(&wait_fence, 0);
15811 init_wait_entry(&wait_reset, 0);
15813 prepare_to_wait(&intel_state->commit_ready.wait,
15814 &wait_fence, TASK_UNINTERRUPTIBLE);
15815 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15816 I915_RESET_MODESET),
15817 &wait_reset, TASK_UNINTERRUPTIBLE);
15820 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15821 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15826 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15827 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15828 I915_RESET_MODESET),
15832 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15834 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15835 struct intel_crtc *crtc;
15838 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15840 intel_dsb_cleanup(old_crtc_state);
15843 static void intel_atomic_cleanup_work(struct work_struct *work)
15845 struct intel_atomic_state *state =
15846 container_of(work, struct intel_atomic_state, base.commit_work);
15847 struct drm_i915_private *i915 = to_i915(state->base.dev);
15849 intel_cleanup_dsbs(state);
15850 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15851 drm_atomic_helper_commit_cleanup_done(&state->base);
15852 drm_atomic_state_put(&state->base);
15854 intel_atomic_helper_free_state(i915);
15857 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15859 struct drm_device *dev = state->base.dev;
15860 struct drm_i915_private *dev_priv = to_i915(dev);
15861 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15862 struct intel_crtc *crtc;
15863 u64 put_domains[I915_MAX_PIPES] = {};
15864 intel_wakeref_t wakeref = 0;
15867 intel_atomic_commit_fence_wait(state);
15869 drm_atomic_helper_wait_for_dependencies(&state->base);
15871 if (state->modeset)
15872 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15874 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15875 new_crtc_state, i) {
15876 if (needs_modeset(new_crtc_state) ||
15877 new_crtc_state->update_pipe) {
15879 put_domains[crtc->pipe] =
15880 modeset_get_crtc_power_domains(new_crtc_state);
15884 intel_commit_modeset_disables(state);
15886 /* FIXME: Eventually get rid of our crtc->config pointer */
15887 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15888 crtc->config = new_crtc_state;
15890 if (state->modeset) {
15891 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15893 intel_set_cdclk_pre_plane_update(state);
15895 intel_modeset_verify_disabled(dev_priv, state);
15898 intel_sagv_pre_plane_update(state);
15900 /* Complete the events for pipes that have now been disabled */
15901 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15902 bool modeset = needs_modeset(new_crtc_state);
15904 /* Complete events for now disable pipes here. */
15905 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15906 spin_lock_irq(&dev->event_lock);
15907 drm_crtc_send_vblank_event(&crtc->base,
15908 new_crtc_state->uapi.event);
15909 spin_unlock_irq(&dev->event_lock);
15911 new_crtc_state->uapi.event = NULL;
15915 if (state->modeset)
15916 intel_encoders_update_prepare(state);
15918 intel_dbuf_pre_plane_update(state);
15920 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15921 if (new_crtc_state->uapi.async_flip)
15922 skl_enable_flip_done(crtc);
15925 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15926 dev_priv->display.commit_modeset_enables(state);
15928 if (state->modeset) {
15929 intel_encoders_update_complete(state);
15931 intel_set_cdclk_post_plane_update(state);
15934 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15935 * already, but still need the state for the delayed optimization. To
15937 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15938 * - schedule that vblank worker _before_ calling hw_done
15939 * - at the start of commit_tail, cancel it _synchrously
15940 * - switch over to the vblank wait helper in the core after that since
15941 * we don't need out special handling any more.
15943 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15945 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15946 if (new_crtc_state->uapi.async_flip)
15947 skl_disable_flip_done(crtc);
15949 if (new_crtc_state->hw.active &&
15950 !needs_modeset(new_crtc_state) &&
15951 !new_crtc_state->preload_luts &&
15952 (new_crtc_state->uapi.color_mgmt_changed ||
15953 new_crtc_state->update_pipe))
15954 intel_color_load_luts(new_crtc_state);
15958 * Now that the vblank has passed, we can go ahead and program the
15959 * optimal watermarks on platforms that need two-step watermark
15962 * TODO: Move this (and other cleanup) to an async worker eventually.
15964 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15965 new_crtc_state, i) {
15967 * Gen2 reports pipe underruns whenever all planes are disabled.
15968 * So re-enable underrun reporting after some planes get enabled.
15970 * We do this before .optimize_watermarks() so that we have a
15971 * chance of catching underruns with the intermediate watermarks
15972 * vs. the new plane configuration.
15974 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15975 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15977 if (dev_priv->display.optimize_watermarks)
15978 dev_priv->display.optimize_watermarks(state, crtc);
15981 intel_dbuf_post_plane_update(state);
15983 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15984 intel_post_plane_update(state, crtc);
15986 if (put_domains[i])
15987 modeset_put_power_domains(dev_priv, put_domains[i]);
15989 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15992 * DSB cleanup is done in cleanup_work aligning with framebuffer
15993 * cleanup. So copy and reset the dsb structure to sync with
15994 * commit_done and later do dsb cleanup in cleanup_work.
15996 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15999 /* Underruns don't always raise interrupts, so check manually */
16000 intel_check_cpu_fifo_underruns(dev_priv);
16001 intel_check_pch_fifo_underruns(dev_priv);
16003 if (state->modeset)
16004 intel_verify_planes(state);
16006 intel_sagv_post_plane_update(state);
16008 drm_atomic_helper_commit_hw_done(&state->base);
16010 if (state->modeset) {
16011 /* As one of the primary mmio accessors, KMS has a high
16012 * likelihood of triggering bugs in unclaimed access. After we
16013 * finish modesetting, see if an error has been flagged, and if
16014 * so enable debugging for the next modeset - and hope we catch
16017 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
16018 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
16020 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16023 * Defer the cleanup of the old state to a separate worker to not
16024 * impede the current task (userspace for blocking modesets) that
16025 * are executed inline. For out-of-line asynchronous modesets/flips,
16026 * deferring to a new worker seems overkill, but we would place a
16027 * schedule point (cond_resched()) here anyway to keep latencies
16030 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
16031 queue_work(system_highpri_wq, &state->base.commit_work);
16034 static void intel_atomic_commit_work(struct work_struct *work)
16036 struct intel_atomic_state *state =
16037 container_of(work, struct intel_atomic_state, base.commit_work);
16039 intel_atomic_commit_tail(state);
16042 static int __i915_sw_fence_call
16043 intel_atomic_commit_ready(struct i915_sw_fence *fence,
16044 enum i915_sw_fence_notify notify)
16046 struct intel_atomic_state *state =
16047 container_of(fence, struct intel_atomic_state, commit_ready);
16050 case FENCE_COMPLETE:
16051 /* we do blocking waits in the worker, nothing to do here */
16055 struct intel_atomic_helper *helper =
16056 &to_i915(state->base.dev)->atomic_helper;
16058 if (llist_add(&state->freed, &helper->free_list))
16059 schedule_work(&helper->free_work);
16064 return NOTIFY_DONE;
16067 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
16069 struct intel_plane_state *old_plane_state, *new_plane_state;
16070 struct intel_plane *plane;
16073 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
16074 new_plane_state, i)
16075 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16076 to_intel_frontbuffer(new_plane_state->hw.fb),
16077 plane->frontbuffer_bit);
16080 static int intel_atomic_commit(struct drm_device *dev,
16081 struct drm_atomic_state *_state,
16084 struct intel_atomic_state *state = to_intel_atomic_state(_state);
16085 struct drm_i915_private *dev_priv = to_i915(dev);
16088 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
16090 drm_atomic_state_get(&state->base);
16091 i915_sw_fence_init(&state->commit_ready,
16092 intel_atomic_commit_ready);
16095 * The intel_legacy_cursor_update() fast path takes care
16096 * of avoiding the vblank waits for simple cursor
16097 * movement and flips. For cursor on/off and size changes,
16098 * we want to perform the vblank waits so that watermark
16099 * updates happen during the correct frames. Gen9+ have
16100 * double buffered watermarks and so shouldn't need this.
16102 * Unset state->legacy_cursor_update before the call to
16103 * drm_atomic_helper_setup_commit() because otherwise
16104 * drm_atomic_helper_wait_for_flip_done() is a noop and
16105 * we get FIFO underruns because we didn't wait
16108 * FIXME doing watermarks and fb cleanup from a vblank worker
16109 * (assuming we had any) would solve these problems.
16111 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
16112 struct intel_crtc_state *new_crtc_state;
16113 struct intel_crtc *crtc;
16116 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16117 if (new_crtc_state->wm.need_postvbl_update ||
16118 new_crtc_state->update_wm_post)
16119 state->base.legacy_cursor_update = false;
16122 ret = intel_atomic_prepare_commit(state);
16124 drm_dbg_atomic(&dev_priv->drm,
16125 "Preparing state failed with %i\n", ret);
16126 i915_sw_fence_commit(&state->commit_ready);
16127 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16131 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
16133 ret = drm_atomic_helper_swap_state(&state->base, true);
16135 intel_atomic_swap_global_state(state);
16138 struct intel_crtc_state *new_crtc_state;
16139 struct intel_crtc *crtc;
16142 i915_sw_fence_commit(&state->commit_ready);
16144 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16145 intel_dsb_cleanup(new_crtc_state);
16147 drm_atomic_helper_cleanup_planes(dev, &state->base);
16148 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16151 dev_priv->wm.distrust_bios_wm = false;
16152 intel_shared_dpll_swap_state(state);
16153 intel_atomic_track_fbs(state);
16155 drm_atomic_state_get(&state->base);
16156 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
16158 i915_sw_fence_commit(&state->commit_ready);
16159 if (nonblock && state->modeset) {
16160 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
16161 } else if (nonblock) {
16162 queue_work(dev_priv->flip_wq, &state->base.commit_work);
16164 if (state->modeset)
16165 flush_workqueue(dev_priv->modeset_wq);
16166 intel_atomic_commit_tail(state);
16172 struct wait_rps_boost {
16173 struct wait_queue_entry wait;
16175 struct drm_crtc *crtc;
16176 struct i915_request *request;
16179 static int do_rps_boost(struct wait_queue_entry *_wait,
16180 unsigned mode, int sync, void *key)
16182 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
16183 struct i915_request *rq = wait->request;
16186 * If we missed the vblank, but the request is already running it
16187 * is reasonable to assume that it will complete before the next
16188 * vblank without our intervention, so leave RPS alone.
16190 if (!i915_request_started(rq))
16191 intel_rps_boost(rq);
16192 i915_request_put(rq);
16194 drm_crtc_vblank_put(wait->crtc);
16196 list_del(&wait->wait.entry);
16201 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
16202 struct dma_fence *fence)
16204 struct wait_rps_boost *wait;
16206 if (!dma_fence_is_i915(fence))
16209 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
16212 if (drm_crtc_vblank_get(crtc))
16215 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
16217 drm_crtc_vblank_put(crtc);
16221 wait->request = to_request(dma_fence_get(fence));
16224 wait->wait.func = do_rps_boost;
16225 wait->wait.flags = 0;
16227 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
16230 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
16232 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
16233 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16234 struct drm_framebuffer *fb = plane_state->hw.fb;
16235 struct i915_vma *vma;
16237 if (plane->id == PLANE_CURSOR &&
16238 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
16239 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16240 const int align = intel_cursor_alignment(dev_priv);
16243 err = i915_gem_object_attach_phys(obj, align);
16248 vma = intel_pin_and_fence_fb_obj(fb,
16249 &plane_state->view,
16250 intel_plane_uses_fence(plane_state),
16251 &plane_state->flags);
16253 return PTR_ERR(vma);
16255 plane_state->vma = vma;
16260 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
16262 struct i915_vma *vma;
16264 vma = fetch_and_zero(&old_plane_state->vma);
16266 intel_unpin_fb_vma(vma, old_plane_state->flags);
16269 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
16271 struct i915_sched_attr attr = {
16272 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
16275 i915_gem_object_wait_priority(obj, 0, &attr);
16279 * intel_prepare_plane_fb - Prepare fb for usage on plane
16280 * @_plane: drm plane to prepare for
16281 * @_new_plane_state: the plane state being prepared
16283 * Prepares a framebuffer for usage on a display plane. Generally this
16284 * involves pinning the underlying object and updating the frontbuffer tracking
16285 * bits. Some older platforms need special physical address handling for
16288 * Returns 0 on success, negative error code on failure.
16291 intel_prepare_plane_fb(struct drm_plane *_plane,
16292 struct drm_plane_state *_new_plane_state)
16294 struct intel_plane *plane = to_intel_plane(_plane);
16295 struct intel_plane_state *new_plane_state =
16296 to_intel_plane_state(_new_plane_state);
16297 struct intel_atomic_state *state =
16298 to_intel_atomic_state(new_plane_state->uapi.state);
16299 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16300 const struct intel_plane_state *old_plane_state =
16301 intel_atomic_get_old_plane_state(state, plane);
16302 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
16303 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
16307 const struct intel_crtc_state *crtc_state =
16308 intel_atomic_get_new_crtc_state(state,
16309 to_intel_crtc(old_plane_state->hw.crtc));
16311 /* Big Hammer, we also need to ensure that any pending
16312 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16313 * current scanout is retired before unpinning the old
16314 * framebuffer. Note that we rely on userspace rendering
16315 * into the buffer attached to the pipe they are waiting
16316 * on. If not, userspace generates a GPU hang with IPEHR
16317 * point to the MI_WAIT_FOR_EVENT.
16319 * This should only fail upon a hung GPU, in which case we
16320 * can safely continue.
16322 if (needs_modeset(crtc_state)) {
16323 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16324 old_obj->base.resv, NULL,
16332 if (new_plane_state->uapi.fence) { /* explicit fencing */
16333 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16334 new_plane_state->uapi.fence,
16335 i915_fence_timeout(dev_priv),
16344 ret = i915_gem_object_pin_pages(obj);
16348 ret = intel_plane_pin_fb(new_plane_state);
16350 i915_gem_object_unpin_pages(obj);
16354 fb_obj_bump_render_priority(obj);
16355 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16357 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16358 struct dma_fence *fence;
16360 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16361 obj->base.resv, NULL,
16363 i915_fence_timeout(dev_priv),
16368 fence = dma_resv_get_excl_rcu(obj->base.resv);
16370 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16372 dma_fence_put(fence);
16375 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16376 new_plane_state->uapi.fence);
16380 * We declare pageflips to be interactive and so merit a small bias
16381 * towards upclocking to deliver the frame on time. By only changing
16382 * the RPS thresholds to sample more regularly and aim for higher
16383 * clocks we can hopefully deliver low power workloads (like kodi)
16384 * that are not quite steady state without resorting to forcing
16385 * maximum clocks following a vblank miss (see do_rps_boost()).
16387 if (!state->rps_interactive) {
16388 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16389 state->rps_interactive = true;
16395 intel_plane_unpin_fb(new_plane_state);
16401 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16402 * @plane: drm plane to clean up for
16403 * @_old_plane_state: the state from the previous modeset
16405 * Cleans up a framebuffer that has just been removed from a plane.
16408 intel_cleanup_plane_fb(struct drm_plane *plane,
16409 struct drm_plane_state *_old_plane_state)
16411 struct intel_plane_state *old_plane_state =
16412 to_intel_plane_state(_old_plane_state);
16413 struct intel_atomic_state *state =
16414 to_intel_atomic_state(old_plane_state->uapi.state);
16415 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16416 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16421 if (state->rps_interactive) {
16422 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16423 state->rps_interactive = false;
16426 /* Should only be called after a successful intel_prepare_plane_fb()! */
16427 intel_plane_unpin_fb(old_plane_state);
16431 * intel_plane_destroy - destroy a plane
16432 * @plane: plane to destroy
16434 * Common destruction function for all types of planes (primary, cursor,
16437 void intel_plane_destroy(struct drm_plane *plane)
16439 drm_plane_cleanup(plane);
16440 kfree(to_intel_plane(plane));
16443 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16444 u32 format, u64 modifier)
16446 switch (modifier) {
16447 case DRM_FORMAT_MOD_LINEAR:
16448 case I915_FORMAT_MOD_X_TILED:
16455 case DRM_FORMAT_C8:
16456 case DRM_FORMAT_RGB565:
16457 case DRM_FORMAT_XRGB1555:
16458 case DRM_FORMAT_XRGB8888:
16459 return modifier == DRM_FORMAT_MOD_LINEAR ||
16460 modifier == I915_FORMAT_MOD_X_TILED;
16466 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16467 u32 format, u64 modifier)
16469 switch (modifier) {
16470 case DRM_FORMAT_MOD_LINEAR:
16471 case I915_FORMAT_MOD_X_TILED:
16478 case DRM_FORMAT_C8:
16479 case DRM_FORMAT_RGB565:
16480 case DRM_FORMAT_XRGB8888:
16481 case DRM_FORMAT_XBGR8888:
16482 case DRM_FORMAT_ARGB8888:
16483 case DRM_FORMAT_ABGR8888:
16484 case DRM_FORMAT_XRGB2101010:
16485 case DRM_FORMAT_XBGR2101010:
16486 case DRM_FORMAT_ARGB2101010:
16487 case DRM_FORMAT_ABGR2101010:
16488 case DRM_FORMAT_XBGR16161616F:
16489 return modifier == DRM_FORMAT_MOD_LINEAR ||
16490 modifier == I915_FORMAT_MOD_X_TILED;
16496 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16497 u32 format, u64 modifier)
16499 return modifier == DRM_FORMAT_MOD_LINEAR &&
16500 format == DRM_FORMAT_ARGB8888;
16503 static const struct drm_plane_funcs i965_plane_funcs = {
16504 .update_plane = drm_atomic_helper_update_plane,
16505 .disable_plane = drm_atomic_helper_disable_plane,
16506 .destroy = intel_plane_destroy,
16507 .atomic_duplicate_state = intel_plane_duplicate_state,
16508 .atomic_destroy_state = intel_plane_destroy_state,
16509 .format_mod_supported = i965_plane_format_mod_supported,
16512 static const struct drm_plane_funcs i8xx_plane_funcs = {
16513 .update_plane = drm_atomic_helper_update_plane,
16514 .disable_plane = drm_atomic_helper_disable_plane,
16515 .destroy = intel_plane_destroy,
16516 .atomic_duplicate_state = intel_plane_duplicate_state,
16517 .atomic_destroy_state = intel_plane_destroy_state,
16518 .format_mod_supported = i8xx_plane_format_mod_supported,
16522 intel_legacy_cursor_update(struct drm_plane *_plane,
16523 struct drm_crtc *_crtc,
16524 struct drm_framebuffer *fb,
16525 int crtc_x, int crtc_y,
16526 unsigned int crtc_w, unsigned int crtc_h,
16527 u32 src_x, u32 src_y,
16528 u32 src_w, u32 src_h,
16529 struct drm_modeset_acquire_ctx *ctx)
16531 struct intel_plane *plane = to_intel_plane(_plane);
16532 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16533 struct intel_plane_state *old_plane_state =
16534 to_intel_plane_state(plane->base.state);
16535 struct intel_plane_state *new_plane_state;
16536 struct intel_crtc_state *crtc_state =
16537 to_intel_crtc_state(crtc->base.state);
16538 struct intel_crtc_state *new_crtc_state;
16542 * When crtc is inactive or there is a modeset pending,
16543 * wait for it to complete in the slowpath
16545 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16546 crtc_state->update_pipe)
16550 * Don't do an async update if there is an outstanding commit modifying
16551 * the plane. This prevents our async update's changes from getting
16552 * overridden by a previous synchronous update's state.
16554 if (old_plane_state->uapi.commit &&
16555 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16559 * If any parameters change that may affect watermarks,
16560 * take the slowpath. Only changing fb or position should be
16563 if (old_plane_state->uapi.crtc != &crtc->base ||
16564 old_plane_state->uapi.src_w != src_w ||
16565 old_plane_state->uapi.src_h != src_h ||
16566 old_plane_state->uapi.crtc_w != crtc_w ||
16567 old_plane_state->uapi.crtc_h != crtc_h ||
16568 !old_plane_state->uapi.fb != !fb)
16571 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16572 if (!new_plane_state)
16575 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16576 if (!new_crtc_state) {
16581 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16583 new_plane_state->uapi.src_x = src_x;
16584 new_plane_state->uapi.src_y = src_y;
16585 new_plane_state->uapi.src_w = src_w;
16586 new_plane_state->uapi.src_h = src_h;
16587 new_plane_state->uapi.crtc_x = crtc_x;
16588 new_plane_state->uapi.crtc_y = crtc_y;
16589 new_plane_state->uapi.crtc_w = crtc_w;
16590 new_plane_state->uapi.crtc_h = crtc_h;
16592 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16594 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16595 old_plane_state, new_plane_state);
16599 ret = intel_plane_pin_fb(new_plane_state);
16603 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16605 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16606 to_intel_frontbuffer(new_plane_state->hw.fb),
16607 plane->frontbuffer_bit);
16609 /* Swap plane state */
16610 plane->base.state = &new_plane_state->uapi;
16613 * We cannot swap crtc_state as it may be in use by an atomic commit or
16614 * page flip that's running simultaneously. If we swap crtc_state and
16615 * destroy the old state, we will cause a use-after-free there.
16617 * Only update active_planes, which is needed for our internal
16618 * bookkeeping. Either value will do the right thing when updating
16619 * planes atomically. If the cursor was part of the atomic update then
16620 * we would have taken the slowpath.
16622 crtc_state->active_planes = new_crtc_state->active_planes;
16624 if (new_plane_state->uapi.visible)
16625 intel_update_plane(plane, crtc_state, new_plane_state);
16627 intel_disable_plane(plane, crtc_state);
16629 intel_plane_unpin_fb(old_plane_state);
16632 if (new_crtc_state)
16633 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16635 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16637 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16641 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16642 crtc_x, crtc_y, crtc_w, crtc_h,
16643 src_x, src_y, src_w, src_h, ctx);
16646 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16647 .update_plane = intel_legacy_cursor_update,
16648 .disable_plane = drm_atomic_helper_disable_plane,
16649 .destroy = intel_plane_destroy,
16650 .atomic_duplicate_state = intel_plane_duplicate_state,
16651 .atomic_destroy_state = intel_plane_destroy_state,
16652 .format_mod_supported = intel_cursor_format_mod_supported,
16655 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16656 enum i9xx_plane_id i9xx_plane)
16658 if (!HAS_FBC(dev_priv))
16661 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16662 return i9xx_plane == PLANE_A; /* tied to pipe A */
16663 else if (IS_IVYBRIDGE(dev_priv))
16664 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16665 i9xx_plane == PLANE_C;
16666 else if (INTEL_GEN(dev_priv) >= 4)
16667 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16669 return i9xx_plane == PLANE_A;
16672 static struct intel_plane *
16673 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16675 struct intel_plane *plane;
16676 const struct drm_plane_funcs *plane_funcs;
16677 unsigned int supported_rotations;
16678 const u32 *formats;
16682 if (INTEL_GEN(dev_priv) >= 9)
16683 return skl_universal_plane_create(dev_priv, pipe,
16686 plane = intel_plane_alloc();
16690 plane->pipe = pipe;
16692 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16693 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16695 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16696 INTEL_NUM_PIPES(dev_priv) == 2)
16697 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16699 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16700 plane->id = PLANE_PRIMARY;
16701 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16703 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16704 if (plane->has_fbc) {
16705 struct intel_fbc *fbc = &dev_priv->fbc;
16707 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16710 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16711 formats = vlv_primary_formats;
16712 num_formats = ARRAY_SIZE(vlv_primary_formats);
16713 } else if (INTEL_GEN(dev_priv) >= 4) {
16715 * WaFP16GammaEnabling:ivb
16716 * "Workaround : When using the 64-bit format, the plane
16717 * output on each color channel has one quarter amplitude.
16718 * It can be brought up to full amplitude by using pipe
16719 * gamma correction or pipe color space conversion to
16720 * multiply the plane output by four."
16722 * There is no dedicated plane gamma for the primary plane,
16723 * and using the pipe gamma/csc could conflict with other
16724 * planes, so we choose not to expose fp16 on IVB primary
16725 * planes. HSW primary planes no longer have this problem.
16727 if (IS_IVYBRIDGE(dev_priv)) {
16728 formats = ivb_primary_formats;
16729 num_formats = ARRAY_SIZE(ivb_primary_formats);
16731 formats = i965_primary_formats;
16732 num_formats = ARRAY_SIZE(i965_primary_formats);
16735 formats = i8xx_primary_formats;
16736 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16739 if (INTEL_GEN(dev_priv) >= 4)
16740 plane_funcs = &i965_plane_funcs;
16742 plane_funcs = &i8xx_plane_funcs;
16744 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16745 plane->min_cdclk = vlv_plane_min_cdclk;
16746 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16747 plane->min_cdclk = hsw_plane_min_cdclk;
16748 else if (IS_IVYBRIDGE(dev_priv))
16749 plane->min_cdclk = ivb_plane_min_cdclk;
16751 plane->min_cdclk = i9xx_plane_min_cdclk;
16753 plane->max_stride = i9xx_plane_max_stride;
16754 plane->update_plane = i9xx_update_plane;
16755 plane->disable_plane = i9xx_disable_plane;
16756 plane->get_hw_state = i9xx_plane_get_hw_state;
16757 plane->check_plane = i9xx_plane_check;
16759 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16760 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16762 formats, num_formats,
16763 i9xx_format_modifiers,
16764 DRM_PLANE_TYPE_PRIMARY,
16765 "primary %c", pipe_name(pipe));
16767 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16769 formats, num_formats,
16770 i9xx_format_modifiers,
16771 DRM_PLANE_TYPE_PRIMARY,
16773 plane_name(plane->i9xx_plane));
16777 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16778 supported_rotations =
16779 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16780 DRM_MODE_REFLECT_X;
16781 } else if (INTEL_GEN(dev_priv) >= 4) {
16782 supported_rotations =
16783 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16785 supported_rotations = DRM_MODE_ROTATE_0;
16788 if (INTEL_GEN(dev_priv) >= 4)
16789 drm_plane_create_rotation_property(&plane->base,
16791 supported_rotations);
16794 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16796 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16801 intel_plane_free(plane);
16803 return ERR_PTR(ret);
16806 static struct intel_plane *
16807 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16810 struct intel_plane *cursor;
16813 cursor = intel_plane_alloc();
16814 if (IS_ERR(cursor))
16817 cursor->pipe = pipe;
16818 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16819 cursor->id = PLANE_CURSOR;
16820 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16822 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16823 cursor->max_stride = i845_cursor_max_stride;
16824 cursor->update_plane = i845_update_cursor;
16825 cursor->disable_plane = i845_disable_cursor;
16826 cursor->get_hw_state = i845_cursor_get_hw_state;
16827 cursor->check_plane = i845_check_cursor;
16829 cursor->max_stride = i9xx_cursor_max_stride;
16830 cursor->update_plane = i9xx_update_cursor;
16831 cursor->disable_plane = i9xx_disable_cursor;
16832 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16833 cursor->check_plane = i9xx_check_cursor;
16836 cursor->cursor.base = ~0;
16837 cursor->cursor.cntl = ~0;
16839 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16840 cursor->cursor.size = ~0;
16842 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16843 0, &intel_cursor_plane_funcs,
16844 intel_cursor_formats,
16845 ARRAY_SIZE(intel_cursor_formats),
16846 cursor_format_modifiers,
16847 DRM_PLANE_TYPE_CURSOR,
16848 "cursor %c", pipe_name(pipe));
16852 if (INTEL_GEN(dev_priv) >= 4)
16853 drm_plane_create_rotation_property(&cursor->base,
16855 DRM_MODE_ROTATE_0 |
16856 DRM_MODE_ROTATE_180);
16858 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16859 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16861 if (INTEL_GEN(dev_priv) >= 12)
16862 drm_plane_enable_fb_damage_clips(&cursor->base);
16864 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16869 intel_plane_free(cursor);
16871 return ERR_PTR(ret);
16874 #define INTEL_CRTC_FUNCS \
16875 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16876 .set_config = drm_atomic_helper_set_config, \
16877 .destroy = intel_crtc_destroy, \
16878 .page_flip = drm_atomic_helper_page_flip, \
16879 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16880 .atomic_destroy_state = intel_crtc_destroy_state, \
16881 .set_crc_source = intel_crtc_set_crc_source, \
16882 .verify_crc_source = intel_crtc_verify_crc_source, \
16883 .get_crc_sources = intel_crtc_get_crc_sources
16885 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16888 .get_vblank_counter = g4x_get_vblank_counter,
16889 .enable_vblank = bdw_enable_vblank,
16890 .disable_vblank = bdw_disable_vblank,
16891 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16894 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16897 .get_vblank_counter = g4x_get_vblank_counter,
16898 .enable_vblank = ilk_enable_vblank,
16899 .disable_vblank = ilk_disable_vblank,
16900 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16903 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16906 .get_vblank_counter = g4x_get_vblank_counter,
16907 .enable_vblank = i965_enable_vblank,
16908 .disable_vblank = i965_disable_vblank,
16909 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16912 static const struct drm_crtc_funcs i965_crtc_funcs = {
16915 .get_vblank_counter = i915_get_vblank_counter,
16916 .enable_vblank = i965_enable_vblank,
16917 .disable_vblank = i965_disable_vblank,
16918 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16921 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16924 .get_vblank_counter = i915_get_vblank_counter,
16925 .enable_vblank = i915gm_enable_vblank,
16926 .disable_vblank = i915gm_disable_vblank,
16927 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16930 static const struct drm_crtc_funcs i915_crtc_funcs = {
16933 .get_vblank_counter = i915_get_vblank_counter,
16934 .enable_vblank = i8xx_enable_vblank,
16935 .disable_vblank = i8xx_disable_vblank,
16936 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16939 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16942 /* no hw vblank counter */
16943 .enable_vblank = i8xx_enable_vblank,
16944 .disable_vblank = i8xx_disable_vblank,
16945 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16948 static struct intel_crtc *intel_crtc_alloc(void)
16950 struct intel_crtc_state *crtc_state;
16951 struct intel_crtc *crtc;
16953 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16955 return ERR_PTR(-ENOMEM);
16957 crtc_state = intel_crtc_state_alloc(crtc);
16960 return ERR_PTR(-ENOMEM);
16963 crtc->base.state = &crtc_state->uapi;
16964 crtc->config = crtc_state;
16969 static void intel_crtc_free(struct intel_crtc *crtc)
16971 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16975 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16977 struct intel_plane *plane;
16979 for_each_intel_plane(&dev_priv->drm, plane) {
16980 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16983 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16987 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16989 struct intel_plane *primary, *cursor;
16990 const struct drm_crtc_funcs *funcs;
16991 struct intel_crtc *crtc;
16994 crtc = intel_crtc_alloc();
16996 return PTR_ERR(crtc);
16999 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
17001 primary = intel_primary_plane_create(dev_priv, pipe);
17002 if (IS_ERR(primary)) {
17003 ret = PTR_ERR(primary);
17006 crtc->plane_ids_mask |= BIT(primary->id);
17008 for_each_sprite(dev_priv, pipe, sprite) {
17009 struct intel_plane *plane;
17011 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
17012 if (IS_ERR(plane)) {
17013 ret = PTR_ERR(plane);
17016 crtc->plane_ids_mask |= BIT(plane->id);
17019 cursor = intel_cursor_plane_create(dev_priv, pipe);
17020 if (IS_ERR(cursor)) {
17021 ret = PTR_ERR(cursor);
17024 crtc->plane_ids_mask |= BIT(cursor->id);
17026 if (HAS_GMCH(dev_priv)) {
17027 if (IS_CHERRYVIEW(dev_priv) ||
17028 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
17029 funcs = &g4x_crtc_funcs;
17030 else if (IS_GEN(dev_priv, 4))
17031 funcs = &i965_crtc_funcs;
17032 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
17033 funcs = &i915gm_crtc_funcs;
17034 else if (IS_GEN(dev_priv, 3))
17035 funcs = &i915_crtc_funcs;
17037 funcs = &i8xx_crtc_funcs;
17039 if (INTEL_GEN(dev_priv) >= 8)
17040 funcs = &bdw_crtc_funcs;
17042 funcs = &ilk_crtc_funcs;
17045 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
17046 &primary->base, &cursor->base,
17047 funcs, "pipe %c", pipe_name(pipe));
17051 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
17052 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
17053 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
17055 if (INTEL_GEN(dev_priv) < 9) {
17056 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
17058 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
17059 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
17060 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
17063 intel_color_init(crtc);
17065 intel_crtc_crc_init(crtc);
17067 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
17072 intel_crtc_free(crtc);
17077 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
17078 struct drm_file *file)
17080 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
17081 struct drm_crtc *drmmode_crtc;
17082 struct intel_crtc *crtc;
17084 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
17088 crtc = to_intel_crtc(drmmode_crtc);
17089 pipe_from_crtc_id->pipe = crtc->pipe;
17094 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
17096 struct drm_device *dev = encoder->base.dev;
17097 struct intel_encoder *source_encoder;
17098 u32 possible_clones = 0;
17100 for_each_intel_encoder(dev, source_encoder) {
17101 if (encoders_cloneable(encoder, source_encoder))
17102 possible_clones |= drm_encoder_mask(&source_encoder->base);
17105 return possible_clones;
17108 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
17110 struct drm_device *dev = encoder->base.dev;
17111 struct intel_crtc *crtc;
17112 u32 possible_crtcs = 0;
17114 for_each_intel_crtc(dev, crtc) {
17115 if (encoder->pipe_mask & BIT(crtc->pipe))
17116 possible_crtcs |= drm_crtc_mask(&crtc->base);
17119 return possible_crtcs;
17122 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
17124 if (!IS_MOBILE(dev_priv))
17127 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
17130 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
17136 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
17138 if (INTEL_GEN(dev_priv) >= 9)
17141 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
17144 if (HAS_PCH_LPT_H(dev_priv) &&
17145 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
17148 /* DDI E can't be used if DDI A requires 4 lanes */
17149 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
17152 if (!dev_priv->vbt.int_crt_support)
17158 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
17163 if (HAS_DDI(dev_priv))
17166 * This w/a is needed at least on CPT/PPT, but to be sure apply it
17167 * everywhere where registers can be write protected.
17169 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17174 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
17175 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
17177 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
17178 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
17182 static void intel_pps_init(struct drm_i915_private *dev_priv)
17184 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
17185 dev_priv->pps_mmio_base = PCH_PPS_BASE;
17186 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17187 dev_priv->pps_mmio_base = VLV_PPS_BASE;
17189 dev_priv->pps_mmio_base = PPS_BASE;
17191 intel_pps_unlock_regs_wa(dev_priv);
17194 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
17196 struct intel_encoder *encoder;
17197 bool dpd_is_edp = false;
17199 intel_pps_init(dev_priv);
17201 if (!HAS_DISPLAY(dev_priv))
17204 if (IS_ROCKETLAKE(dev_priv)) {
17205 intel_ddi_init(dev_priv, PORT_A);
17206 intel_ddi_init(dev_priv, PORT_B);
17207 intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
17208 intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
17209 } else if (INTEL_GEN(dev_priv) >= 12) {
17210 intel_ddi_init(dev_priv, PORT_A);
17211 intel_ddi_init(dev_priv, PORT_B);
17212 intel_ddi_init(dev_priv, PORT_D);
17213 intel_ddi_init(dev_priv, PORT_E);
17214 intel_ddi_init(dev_priv, PORT_F);
17215 intel_ddi_init(dev_priv, PORT_G);
17216 intel_ddi_init(dev_priv, PORT_H);
17217 intel_ddi_init(dev_priv, PORT_I);
17218 icl_dsi_init(dev_priv);
17219 } else if (IS_JSL_EHL(dev_priv)) {
17220 intel_ddi_init(dev_priv, PORT_A);
17221 intel_ddi_init(dev_priv, PORT_B);
17222 intel_ddi_init(dev_priv, PORT_C);
17223 intel_ddi_init(dev_priv, PORT_D);
17224 icl_dsi_init(dev_priv);
17225 } else if (IS_GEN(dev_priv, 11)) {
17226 intel_ddi_init(dev_priv, PORT_A);
17227 intel_ddi_init(dev_priv, PORT_B);
17228 intel_ddi_init(dev_priv, PORT_C);
17229 intel_ddi_init(dev_priv, PORT_D);
17230 intel_ddi_init(dev_priv, PORT_E);
17232 * On some ICL SKUs port F is not present. No strap bits for
17233 * this, so rely on VBT.
17234 * Work around broken VBTs on SKUs known to have no port F.
17236 if (IS_ICL_WITH_PORT_F(dev_priv) &&
17237 intel_bios_is_port_present(dev_priv, PORT_F))
17238 intel_ddi_init(dev_priv, PORT_F);
17240 icl_dsi_init(dev_priv);
17241 } else if (IS_GEN9_LP(dev_priv)) {
17243 * FIXME: Broxton doesn't support port detection via the
17244 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
17245 * detect the ports.
17247 intel_ddi_init(dev_priv, PORT_A);
17248 intel_ddi_init(dev_priv, PORT_B);
17249 intel_ddi_init(dev_priv, PORT_C);
17251 vlv_dsi_init(dev_priv);
17252 } else if (HAS_DDI(dev_priv)) {
17255 if (intel_ddi_crt_present(dev_priv))
17256 intel_crt_init(dev_priv);
17259 * Haswell uses DDI functions to detect digital outputs.
17260 * On SKL pre-D0 the strap isn't connected, so we assume
17263 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
17264 /* WaIgnoreDDIAStrap: skl */
17265 if (found || IS_GEN9_BC(dev_priv))
17266 intel_ddi_init(dev_priv, PORT_A);
17268 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
17270 found = intel_de_read(dev_priv, SFUSE_STRAP);
17272 if (found & SFUSE_STRAP_DDIB_DETECTED)
17273 intel_ddi_init(dev_priv, PORT_B);
17274 if (found & SFUSE_STRAP_DDIC_DETECTED)
17275 intel_ddi_init(dev_priv, PORT_C);
17276 if (found & SFUSE_STRAP_DDID_DETECTED)
17277 intel_ddi_init(dev_priv, PORT_D);
17278 if (found & SFUSE_STRAP_DDIF_DETECTED)
17279 intel_ddi_init(dev_priv, PORT_F);
17281 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
17283 if (IS_GEN9_BC(dev_priv) &&
17284 intel_bios_is_port_present(dev_priv, PORT_E))
17285 intel_ddi_init(dev_priv, PORT_E);
17287 } else if (HAS_PCH_SPLIT(dev_priv)) {
17291 * intel_edp_init_connector() depends on this completing first,
17292 * to prevent the registration of both eDP and LVDS and the
17293 * incorrect sharing of the PPS.
17295 intel_lvds_init(dev_priv);
17296 intel_crt_init(dev_priv);
17298 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
17300 if (ilk_has_edp_a(dev_priv))
17301 intel_dp_init(dev_priv, DP_A, PORT_A);
17303 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
17304 /* PCH SDVOB multiplex with HDMIB */
17305 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
17307 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
17308 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
17309 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17312 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17313 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17315 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17316 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17318 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17319 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17321 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17322 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17323 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17324 bool has_edp, has_port;
17326 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17327 intel_crt_init(dev_priv);
17330 * The DP_DETECTED bit is the latched state of the DDC
17331 * SDA pin at boot. However since eDP doesn't require DDC
17332 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17333 * eDP ports may have been muxed to an alternate function.
17334 * Thus we can't rely on the DP_DETECTED bit alone to detect
17335 * eDP ports. Consult the VBT as well as DP_DETECTED to
17336 * detect eDP ports.
17338 * Sadly the straps seem to be missing sometimes even for HDMI
17339 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17340 * and VBT for the presence of the port. Additionally we can't
17341 * trust the port type the VBT declares as we've seen at least
17342 * HDMI ports that the VBT claim are DP or eDP.
17344 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17345 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17346 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17347 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17348 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17349 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17351 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17352 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17353 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17354 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17355 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17356 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17358 if (IS_CHERRYVIEW(dev_priv)) {
17360 * eDP not supported on port D,
17361 * so no need to worry about it
17363 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17364 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17365 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17366 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17367 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17370 vlv_dsi_init(dev_priv);
17371 } else if (IS_PINEVIEW(dev_priv)) {
17372 intel_lvds_init(dev_priv);
17373 intel_crt_init(dev_priv);
17374 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17375 bool found = false;
17377 if (IS_MOBILE(dev_priv))
17378 intel_lvds_init(dev_priv);
17380 intel_crt_init(dev_priv);
17382 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17383 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17384 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17385 if (!found && IS_G4X(dev_priv)) {
17386 drm_dbg_kms(&dev_priv->drm,
17387 "probing HDMI on SDVOB\n");
17388 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17391 if (!found && IS_G4X(dev_priv))
17392 intel_dp_init(dev_priv, DP_B, PORT_B);
17395 /* Before G4X SDVOC doesn't have its own detect register */
17397 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17398 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17399 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17402 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17404 if (IS_G4X(dev_priv)) {
17405 drm_dbg_kms(&dev_priv->drm,
17406 "probing HDMI on SDVOC\n");
17407 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17409 if (IS_G4X(dev_priv))
17410 intel_dp_init(dev_priv, DP_C, PORT_C);
17413 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17414 intel_dp_init(dev_priv, DP_D, PORT_D);
17416 if (SUPPORTS_TV(dev_priv))
17417 intel_tv_init(dev_priv);
17418 } else if (IS_GEN(dev_priv, 2)) {
17419 if (IS_I85X(dev_priv))
17420 intel_lvds_init(dev_priv);
17422 intel_crt_init(dev_priv);
17423 intel_dvo_init(dev_priv);
17426 intel_psr_init(dev_priv);
17428 for_each_intel_encoder(&dev_priv->drm, encoder) {
17429 encoder->base.possible_crtcs =
17430 intel_encoder_possible_crtcs(encoder);
17431 encoder->base.possible_clones =
17432 intel_encoder_possible_clones(encoder);
17435 intel_init_pch_refclk(dev_priv);
17437 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17440 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17442 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17444 drm_framebuffer_cleanup(fb);
17445 intel_frontbuffer_put(intel_fb->frontbuffer);
17450 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17451 struct drm_file *file,
17452 unsigned int *handle)
17454 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17455 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17457 if (obj->userptr.mm) {
17458 drm_dbg(&i915->drm,
17459 "attempting to use a userptr for a framebuffer, denied\n");
17463 return drm_gem_handle_create(file, &obj->base, handle);
17466 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17467 struct drm_file *file,
17468 unsigned flags, unsigned color,
17469 struct drm_clip_rect *clips,
17470 unsigned num_clips)
17472 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17474 i915_gem_object_flush_if_display(obj);
17475 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17480 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17481 .destroy = intel_user_framebuffer_destroy,
17482 .create_handle = intel_user_framebuffer_create_handle,
17483 .dirty = intel_user_framebuffer_dirty,
17486 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17487 struct drm_i915_gem_object *obj,
17488 struct drm_mode_fb_cmd2 *mode_cmd)
17490 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17491 struct drm_framebuffer *fb = &intel_fb->base;
17493 unsigned int tiling, stride;
17497 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17498 if (!intel_fb->frontbuffer)
17501 i915_gem_object_lock(obj, NULL);
17502 tiling = i915_gem_object_get_tiling(obj);
17503 stride = i915_gem_object_get_stride(obj);
17504 i915_gem_object_unlock(obj);
17506 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17508 * If there's a fence, enforce that
17509 * the fb modifier and tiling mode match.
17511 if (tiling != I915_TILING_NONE &&
17512 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17513 drm_dbg_kms(&dev_priv->drm,
17514 "tiling_mode doesn't match fb modifier\n");
17518 if (tiling == I915_TILING_X) {
17519 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17520 } else if (tiling == I915_TILING_Y) {
17521 drm_dbg_kms(&dev_priv->drm,
17522 "No Y tiling for legacy addfb\n");
17527 if (!drm_any_plane_has_format(&dev_priv->drm,
17528 mode_cmd->pixel_format,
17529 mode_cmd->modifier[0])) {
17530 struct drm_format_name_buf format_name;
17532 drm_dbg_kms(&dev_priv->drm,
17533 "unsupported pixel format %s / modifier 0x%llx\n",
17534 drm_get_format_name(mode_cmd->pixel_format,
17536 mode_cmd->modifier[0]);
17541 * gen2/3 display engine uses the fence if present,
17542 * so the tiling mode must match the fb modifier exactly.
17544 if (INTEL_GEN(dev_priv) < 4 &&
17545 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17546 drm_dbg_kms(&dev_priv->drm,
17547 "tiling_mode must match fb modifier exactly on gen2/3\n");
17551 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17552 mode_cmd->modifier[0]);
17553 if (mode_cmd->pitches[0] > max_stride) {
17554 drm_dbg_kms(&dev_priv->drm,
17555 "%s pitch (%u) must be at most %d\n",
17556 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17557 "tiled" : "linear",
17558 mode_cmd->pitches[0], max_stride);
17563 * If there's a fence, enforce that
17564 * the fb pitch and fence stride match.
17566 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17567 drm_dbg_kms(&dev_priv->drm,
17568 "pitch (%d) must match tiling stride (%d)\n",
17569 mode_cmd->pitches[0], stride);
17573 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17574 if (mode_cmd->offsets[0] != 0) {
17575 drm_dbg_kms(&dev_priv->drm,
17576 "plane 0 offset (0x%08x) must be 0\n",
17577 mode_cmd->offsets[0]);
17581 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17583 for (i = 0; i < fb->format->num_planes; i++) {
17584 u32 stride_alignment;
17586 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17587 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17592 stride_alignment = intel_fb_stride_alignment(fb, i);
17593 if (fb->pitches[i] & (stride_alignment - 1)) {
17594 drm_dbg_kms(&dev_priv->drm,
17595 "plane %d pitch (%d) must be at least %u byte aligned\n",
17596 i, fb->pitches[i], stride_alignment);
17600 if (is_gen12_ccs_plane(fb, i)) {
17601 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17603 if (fb->pitches[i] != ccs_aux_stride) {
17604 drm_dbg_kms(&dev_priv->drm,
17605 "ccs aux plane %d pitch (%d) must be %d\n",
17607 fb->pitches[i], ccs_aux_stride);
17612 fb->obj[i] = &obj->base;
17615 ret = intel_fill_fb_info(dev_priv, fb);
17619 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17621 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17628 intel_frontbuffer_put(intel_fb->frontbuffer);
17632 static struct drm_framebuffer *
17633 intel_user_framebuffer_create(struct drm_device *dev,
17634 struct drm_file *filp,
17635 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17637 struct drm_framebuffer *fb;
17638 struct drm_i915_gem_object *obj;
17639 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17641 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17643 return ERR_PTR(-ENOENT);
17645 fb = intel_framebuffer_create(obj, &mode_cmd);
17646 i915_gem_object_put(obj);
17651 static enum drm_mode_status
17652 intel_mode_valid(struct drm_device *dev,
17653 const struct drm_display_mode *mode)
17655 struct drm_i915_private *dev_priv = to_i915(dev);
17656 int hdisplay_max, htotal_max;
17657 int vdisplay_max, vtotal_max;
17660 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17661 * of DBLSCAN modes to the output's mode list when they detect
17662 * the scaling mode property on the connector. And they don't
17663 * ask the kernel to validate those modes in any way until
17664 * modeset time at which point the client gets a protocol error.
17665 * So in order to not upset those clients we silently ignore the
17666 * DBLSCAN flag on such connectors. For other connectors we will
17667 * reject modes with the DBLSCAN flag in encoder->compute_config().
17668 * And we always reject DBLSCAN modes in connector->mode_valid()
17669 * as we never want such modes on the connector's mode list.
17672 if (mode->vscan > 1)
17673 return MODE_NO_VSCAN;
17675 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17676 return MODE_H_ILLEGAL;
17678 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17679 DRM_MODE_FLAG_NCSYNC |
17680 DRM_MODE_FLAG_PCSYNC))
17683 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17684 DRM_MODE_FLAG_PIXMUX |
17685 DRM_MODE_FLAG_CLKDIV2))
17688 /* Transcoder timing limits */
17689 if (INTEL_GEN(dev_priv) >= 11) {
17690 hdisplay_max = 16384;
17691 vdisplay_max = 8192;
17692 htotal_max = 16384;
17694 } else if (INTEL_GEN(dev_priv) >= 9 ||
17695 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17696 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17697 vdisplay_max = 4096;
17700 } else if (INTEL_GEN(dev_priv) >= 3) {
17701 hdisplay_max = 4096;
17702 vdisplay_max = 4096;
17706 hdisplay_max = 2048;
17707 vdisplay_max = 2048;
17712 if (mode->hdisplay > hdisplay_max ||
17713 mode->hsync_start > htotal_max ||
17714 mode->hsync_end > htotal_max ||
17715 mode->htotal > htotal_max)
17716 return MODE_H_ILLEGAL;
17718 if (mode->vdisplay > vdisplay_max ||
17719 mode->vsync_start > vtotal_max ||
17720 mode->vsync_end > vtotal_max ||
17721 mode->vtotal > vtotal_max)
17722 return MODE_V_ILLEGAL;
17724 if (INTEL_GEN(dev_priv) >= 5) {
17725 if (mode->hdisplay < 64 ||
17726 mode->htotal - mode->hdisplay < 32)
17727 return MODE_H_ILLEGAL;
17729 if (mode->vtotal - mode->vdisplay < 5)
17730 return MODE_V_ILLEGAL;
17732 if (mode->htotal - mode->hdisplay < 32)
17733 return MODE_H_ILLEGAL;
17735 if (mode->vtotal - mode->vdisplay < 3)
17736 return MODE_V_ILLEGAL;
17742 enum drm_mode_status
17743 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17744 const struct drm_display_mode *mode)
17746 int plane_width_max, plane_height_max;
17749 * intel_mode_valid() should be
17750 * sufficient on older platforms.
17752 if (INTEL_GEN(dev_priv) < 9)
17756 * Most people will probably want a fullscreen
17757 * plane so let's not advertize modes that are
17758 * too big for that.
17760 if (INTEL_GEN(dev_priv) >= 11) {
17761 plane_width_max = 5120;
17762 plane_height_max = 4320;
17764 plane_width_max = 5120;
17765 plane_height_max = 4096;
17768 if (mode->hdisplay > plane_width_max)
17769 return MODE_H_ILLEGAL;
17771 if (mode->vdisplay > plane_height_max)
17772 return MODE_V_ILLEGAL;
17777 static const struct drm_mode_config_funcs intel_mode_funcs = {
17778 .fb_create = intel_user_framebuffer_create,
17779 .get_format_info = intel_get_format_info,
17780 .output_poll_changed = intel_fbdev_output_poll_changed,
17781 .mode_valid = intel_mode_valid,
17782 .atomic_check = intel_atomic_check,
17783 .atomic_commit = intel_atomic_commit,
17784 .atomic_state_alloc = intel_atomic_state_alloc,
17785 .atomic_state_clear = intel_atomic_state_clear,
17786 .atomic_state_free = intel_atomic_state_free,
17790 * intel_init_display_hooks - initialize the display modesetting hooks
17791 * @dev_priv: device private
17793 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17795 intel_init_cdclk_hooks(dev_priv);
17797 if (INTEL_GEN(dev_priv) >= 9) {
17798 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17799 dev_priv->display.get_initial_plane_config =
17800 skl_get_initial_plane_config;
17801 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17802 dev_priv->display.crtc_enable = hsw_crtc_enable;
17803 dev_priv->display.crtc_disable = hsw_crtc_disable;
17804 } else if (HAS_DDI(dev_priv)) {
17805 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17806 dev_priv->display.get_initial_plane_config =
17807 i9xx_get_initial_plane_config;
17808 dev_priv->display.crtc_compute_clock =
17809 hsw_crtc_compute_clock;
17810 dev_priv->display.crtc_enable = hsw_crtc_enable;
17811 dev_priv->display.crtc_disable = hsw_crtc_disable;
17812 } else if (HAS_PCH_SPLIT(dev_priv)) {
17813 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17814 dev_priv->display.get_initial_plane_config =
17815 i9xx_get_initial_plane_config;
17816 dev_priv->display.crtc_compute_clock =
17817 ilk_crtc_compute_clock;
17818 dev_priv->display.crtc_enable = ilk_crtc_enable;
17819 dev_priv->display.crtc_disable = ilk_crtc_disable;
17820 } else if (IS_CHERRYVIEW(dev_priv)) {
17821 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17822 dev_priv->display.get_initial_plane_config =
17823 i9xx_get_initial_plane_config;
17824 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17825 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17826 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17827 } else if (IS_VALLEYVIEW(dev_priv)) {
17828 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17829 dev_priv->display.get_initial_plane_config =
17830 i9xx_get_initial_plane_config;
17831 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17832 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17833 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17834 } else if (IS_G4X(dev_priv)) {
17835 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17836 dev_priv->display.get_initial_plane_config =
17837 i9xx_get_initial_plane_config;
17838 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17839 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17840 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17841 } else if (IS_PINEVIEW(dev_priv)) {
17842 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17843 dev_priv->display.get_initial_plane_config =
17844 i9xx_get_initial_plane_config;
17845 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17846 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17847 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17848 } else if (!IS_GEN(dev_priv, 2)) {
17849 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17850 dev_priv->display.get_initial_plane_config =
17851 i9xx_get_initial_plane_config;
17852 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17853 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17854 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17856 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17857 dev_priv->display.get_initial_plane_config =
17858 i9xx_get_initial_plane_config;
17859 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17860 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17861 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17864 if (IS_GEN(dev_priv, 5)) {
17865 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17866 } else if (IS_GEN(dev_priv, 6)) {
17867 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17868 } else if (IS_IVYBRIDGE(dev_priv)) {
17869 /* FIXME: detect B0+ stepping and use auto training */
17870 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17873 if (INTEL_GEN(dev_priv) >= 9)
17874 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17876 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17880 void intel_modeset_init_hw(struct drm_i915_private *i915)
17882 struct intel_cdclk_state *cdclk_state =
17883 to_intel_cdclk_state(i915->cdclk.obj.state);
17884 struct intel_dbuf_state *dbuf_state =
17885 to_intel_dbuf_state(i915->dbuf.obj.state);
17887 intel_update_cdclk(i915);
17888 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17889 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17891 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17894 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17896 struct drm_plane *plane;
17897 struct intel_crtc *crtc;
17899 for_each_intel_crtc(state->dev, crtc) {
17900 struct intel_crtc_state *crtc_state;
17902 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17903 if (IS_ERR(crtc_state))
17904 return PTR_ERR(crtc_state);
17906 if (crtc_state->hw.active) {
17908 * Preserve the inherited flag to avoid
17909 * taking the full modeset path.
17911 crtc_state->inherited = true;
17915 drm_for_each_plane(plane, state->dev) {
17916 struct drm_plane_state *plane_state;
17918 plane_state = drm_atomic_get_plane_state(state, plane);
17919 if (IS_ERR(plane_state))
17920 return PTR_ERR(plane_state);
17927 * Calculate what we think the watermarks should be for the state we've read
17928 * out of the hardware and then immediately program those watermarks so that
17929 * we ensure the hardware settings match our internal state.
17931 * We can calculate what we think WM's should be by creating a duplicate of the
17932 * current state (which was constructed during hardware readout) and running it
17933 * through the atomic check code to calculate new watermark values in the
17936 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17938 struct drm_atomic_state *state;
17939 struct intel_atomic_state *intel_state;
17940 struct intel_crtc *crtc;
17941 struct intel_crtc_state *crtc_state;
17942 struct drm_modeset_acquire_ctx ctx;
17946 /* Only supported on platforms that use atomic watermark design */
17947 if (!dev_priv->display.optimize_watermarks)
17950 state = drm_atomic_state_alloc(&dev_priv->drm);
17951 if (drm_WARN_ON(&dev_priv->drm, !state))
17954 intel_state = to_intel_atomic_state(state);
17956 drm_modeset_acquire_init(&ctx, 0);
17959 state->acquire_ctx = &ctx;
17962 * Hardware readout is the only time we don't want to calculate
17963 * intermediate watermarks (since we don't trust the current
17966 if (!HAS_GMCH(dev_priv))
17967 intel_state->skip_intermediate_wm = true;
17969 ret = sanitize_watermarks_add_affected(state);
17973 ret = intel_atomic_check(&dev_priv->drm, state);
17977 /* Write calculated watermark values back */
17978 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17979 crtc_state->wm.need_postvbl_update = true;
17980 dev_priv->display.optimize_watermarks(intel_state, crtc);
17982 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17986 if (ret == -EDEADLK) {
17987 drm_atomic_state_clear(state);
17988 drm_modeset_backoff(&ctx);
17993 * If we fail here, it means that the hardware appears to be
17994 * programmed in a way that shouldn't be possible, given our
17995 * understanding of watermark requirements. This might mean a
17996 * mistake in the hardware readout code or a mistake in the
17997 * watermark calculations for a given platform. Raise a WARN
17998 * so that this is noticeable.
18000 * If this actually happens, we'll have to just leave the
18001 * BIOS-programmed watermarks untouched and hope for the best.
18003 drm_WARN(&dev_priv->drm, ret,
18004 "Could not determine valid watermarks for inherited state\n");
18006 drm_atomic_state_put(state);
18008 drm_modeset_drop_locks(&ctx);
18009 drm_modeset_acquire_fini(&ctx);
18012 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
18014 if (IS_GEN(dev_priv, 5)) {
18016 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
18018 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
18019 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
18020 dev_priv->fdi_pll_freq = 270000;
18025 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
18028 static int intel_initial_commit(struct drm_device *dev)
18030 struct drm_atomic_state *state = NULL;
18031 struct drm_modeset_acquire_ctx ctx;
18032 struct intel_crtc *crtc;
18035 state = drm_atomic_state_alloc(dev);
18039 drm_modeset_acquire_init(&ctx, 0);
18042 state->acquire_ctx = &ctx;
18044 for_each_intel_crtc(dev, crtc) {
18045 struct intel_crtc_state *crtc_state =
18046 intel_atomic_get_crtc_state(state, crtc);
18048 if (IS_ERR(crtc_state)) {
18049 ret = PTR_ERR(crtc_state);
18053 if (crtc_state->hw.active) {
18054 struct intel_encoder *encoder;
18057 * We've not yet detected sink capabilities
18058 * (audio,infoframes,etc.) and thus we don't want to
18059 * force a full state recomputation yet. We want that to
18060 * happen only for the first real commit from userspace.
18061 * So preserve the inherited flag for the time being.
18063 crtc_state->inherited = true;
18065 ret = drm_atomic_add_affected_planes(state, &crtc->base);
18070 * FIXME hack to force a LUT update to avoid the
18071 * plane update forcing the pipe gamma on without
18072 * having a proper LUT loaded. Remove once we
18073 * have readout for pipe gamma enable.
18075 crtc_state->uapi.color_mgmt_changed = true;
18077 for_each_intel_encoder_mask(dev, encoder,
18078 crtc_state->uapi.encoder_mask) {
18079 if (encoder->initial_fastset_check &&
18080 !encoder->initial_fastset_check(encoder, crtc_state)) {
18081 ret = drm_atomic_add_affected_connectors(state,
18090 ret = drm_atomic_commit(state);
18093 if (ret == -EDEADLK) {
18094 drm_atomic_state_clear(state);
18095 drm_modeset_backoff(&ctx);
18099 drm_atomic_state_put(state);
18101 drm_modeset_drop_locks(&ctx);
18102 drm_modeset_acquire_fini(&ctx);
18107 static void intel_mode_config_init(struct drm_i915_private *i915)
18109 struct drm_mode_config *mode_config = &i915->drm.mode_config;
18111 drm_mode_config_init(&i915->drm);
18112 INIT_LIST_HEAD(&i915->global_obj_list);
18114 mode_config->min_width = 0;
18115 mode_config->min_height = 0;
18117 mode_config->preferred_depth = 24;
18118 mode_config->prefer_shadow = 1;
18120 mode_config->allow_fb_modifiers = true;
18122 mode_config->funcs = &intel_mode_funcs;
18124 if (INTEL_GEN(i915) >= 9)
18125 mode_config->async_page_flip = true;
18128 * Maximum framebuffer dimensions, chosen to match
18129 * the maximum render engine surface size on gen4+.
18131 if (INTEL_GEN(i915) >= 7) {
18132 mode_config->max_width = 16384;
18133 mode_config->max_height = 16384;
18134 } else if (INTEL_GEN(i915) >= 4) {
18135 mode_config->max_width = 8192;
18136 mode_config->max_height = 8192;
18137 } else if (IS_GEN(i915, 3)) {
18138 mode_config->max_width = 4096;
18139 mode_config->max_height = 4096;
18141 mode_config->max_width = 2048;
18142 mode_config->max_height = 2048;
18145 if (IS_I845G(i915) || IS_I865G(i915)) {
18146 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
18147 mode_config->cursor_height = 1023;
18148 } else if (IS_I830(i915) || IS_I85X(i915) ||
18149 IS_I915G(i915) || IS_I915GM(i915)) {
18150 mode_config->cursor_width = 64;
18151 mode_config->cursor_height = 64;
18153 mode_config->cursor_width = 256;
18154 mode_config->cursor_height = 256;
18158 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
18160 intel_atomic_global_obj_cleanup(i915);
18161 drm_mode_config_cleanup(&i915->drm);
18164 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
18166 if (plane_config->fb) {
18167 struct drm_framebuffer *fb = &plane_config->fb->base;
18169 /* We may only have the stub and not a full framebuffer */
18170 if (drm_framebuffer_read_refcount(fb))
18171 drm_framebuffer_put(fb);
18176 if (plane_config->vma)
18177 i915_vma_put(plane_config->vma);
18180 /* part #1: call before irq install */
18181 int intel_modeset_init_noirq(struct drm_i915_private *i915)
18185 if (i915_inject_probe_failure(i915))
18188 if (HAS_DISPLAY(i915)) {
18189 ret = drm_vblank_init(&i915->drm,
18190 INTEL_NUM_PIPES(i915));
18195 intel_bios_init(i915);
18197 ret = intel_vga_register(i915);
18201 /* FIXME: completely on the wrong abstraction layer */
18202 intel_power_domains_init_hw(i915, false);
18204 intel_csr_ucode_init(i915);
18206 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
18207 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
18208 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
18210 intel_mode_config_init(i915);
18212 ret = intel_cdclk_init(i915);
18214 goto cleanup_vga_client_pw_domain_csr;
18216 ret = intel_dbuf_init(i915);
18218 goto cleanup_vga_client_pw_domain_csr;
18220 ret = intel_bw_init(i915);
18222 goto cleanup_vga_client_pw_domain_csr;
18224 init_llist_head(&i915->atomic_helper.free_list);
18225 INIT_WORK(&i915->atomic_helper.free_work,
18226 intel_atomic_helper_free_state_worker);
18228 intel_init_quirks(i915);
18230 intel_fbc_init(i915);
18234 cleanup_vga_client_pw_domain_csr:
18235 intel_csr_ucode_fini(i915);
18236 intel_power_domains_driver_remove(i915);
18237 intel_vga_unregister(i915);
18239 intel_bios_driver_remove(i915);
18244 /* part #2: call after irq install, but before gem init */
18245 int intel_modeset_init_nogem(struct drm_i915_private *i915)
18247 struct drm_device *dev = &i915->drm;
18249 struct intel_crtc *crtc;
18252 intel_init_pm(i915);
18254 intel_panel_sanitize_ssc(i915);
18256 intel_gmbus_setup(i915);
18258 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
18259 INTEL_NUM_PIPES(i915),
18260 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
18262 if (HAS_DISPLAY(i915)) {
18263 for_each_pipe(i915, pipe) {
18264 ret = intel_crtc_init(i915, pipe);
18266 intel_mode_config_cleanup(i915);
18272 intel_plane_possible_crtcs_init(i915);
18273 intel_shared_dpll_init(dev);
18274 intel_update_fdi_pll_freq(i915);
18276 intel_update_czclk(i915);
18277 intel_modeset_init_hw(i915);
18279 intel_hdcp_component_init(i915);
18281 if (i915->max_cdclk_freq == 0)
18282 intel_update_max_cdclk(i915);
18285 * If the platform has HTI, we need to find out whether it has reserved
18286 * any display resources before we create our display outputs.
18288 if (INTEL_INFO(i915)->display.has_hti)
18289 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
18291 /* Just disable it once at startup */
18292 intel_vga_disable(i915);
18293 intel_setup_outputs(i915);
18295 drm_modeset_lock_all(dev);
18296 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
18297 drm_modeset_unlock_all(dev);
18299 for_each_intel_crtc(dev, crtc) {
18300 struct intel_initial_plane_config plane_config = {};
18306 * Note that reserving the BIOS fb up front prevents us
18307 * from stuffing other stolen allocations like the ring
18308 * on top. This prevents some ugliness at boot time, and
18309 * can even allow for smooth boot transitions if the BIOS
18310 * fb is large enough for the active pipe configuration.
18312 i915->display.get_initial_plane_config(crtc, &plane_config);
18315 * If the fb is shared between multiple heads, we'll
18316 * just get the first one.
18318 intel_find_initial_plane_obj(crtc, &plane_config);
18320 plane_config_fini(&plane_config);
18324 * Make sure hardware watermarks really match the state we read out.
18325 * Note that we need to do this after reconstructing the BIOS fb's
18326 * since the watermark calculation done here will use pstate->fb.
18328 if (!HAS_GMCH(i915))
18329 sanitize_watermarks(i915);
18332 * Force all active planes to recompute their states. So that on
18333 * mode_setcrtc after probe, all the intel_plane_state variables
18334 * are already calculated and there is no assert_plane warnings
18337 ret = intel_initial_commit(dev);
18339 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18344 /* part #3: call after gem init */
18345 int intel_modeset_init(struct drm_i915_private *i915)
18349 intel_overlay_setup(i915);
18351 if (!HAS_DISPLAY(i915))
18354 ret = intel_fbdev_init(&i915->drm);
18358 /* Only enable hotplug handling once the fbdev is fully set up. */
18359 intel_hpd_init(i915);
18360 intel_hpd_poll_disable(i915);
18362 intel_init_ipc(i915);
18364 intel_psr_set_force_mode_changed(i915->psr.dp);
18369 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18371 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18372 /* 640x480@60Hz, ~25175 kHz */
18373 struct dpll clock = {
18383 drm_WARN_ON(&dev_priv->drm,
18384 i9xx_calc_dpll_params(48000, &clock) != 25154);
18386 drm_dbg_kms(&dev_priv->drm,
18387 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18388 pipe_name(pipe), clock.vco, clock.dot);
18390 fp = i9xx_dpll_compute_fp(&clock);
18391 dpll = DPLL_DVO_2X_MODE |
18392 DPLL_VGA_MODE_DIS |
18393 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18394 PLL_P2_DIVIDE_BY_4 |
18395 PLL_REF_INPUT_DREFCLK |
18398 intel_de_write(dev_priv, FP0(pipe), fp);
18399 intel_de_write(dev_priv, FP1(pipe), fp);
18401 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18402 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18403 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18404 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18405 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18406 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18407 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18410 * Apparently we need to have VGA mode enabled prior to changing
18411 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18412 * dividers, even though the register value does change.
18414 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18415 intel_de_write(dev_priv, DPLL(pipe), dpll);
18417 /* Wait for the clocks to stabilize. */
18418 intel_de_posting_read(dev_priv, DPLL(pipe));
18421 /* The pixel multiplier can only be updated once the
18422 * DPLL is enabled and the clocks are stable.
18424 * So write it again.
18426 intel_de_write(dev_priv, DPLL(pipe), dpll);
18428 /* We do this three times for luck */
18429 for (i = 0; i < 3 ; i++) {
18430 intel_de_write(dev_priv, DPLL(pipe), dpll);
18431 intel_de_posting_read(dev_priv, DPLL(pipe));
18432 udelay(150); /* wait for warmup */
18435 intel_de_write(dev_priv, PIPECONF(pipe),
18436 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18437 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18439 intel_wait_for_pipe_scanline_moving(crtc);
18442 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18444 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18446 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18449 drm_WARN_ON(&dev_priv->drm,
18450 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18451 DISPLAY_PLANE_ENABLE);
18452 drm_WARN_ON(&dev_priv->drm,
18453 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18454 DISPLAY_PLANE_ENABLE);
18455 drm_WARN_ON(&dev_priv->drm,
18456 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18457 DISPLAY_PLANE_ENABLE);
18458 drm_WARN_ON(&dev_priv->drm,
18459 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18460 drm_WARN_ON(&dev_priv->drm,
18461 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18463 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18464 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18466 intel_wait_for_pipe_scanline_stopped(crtc);
18468 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18469 intel_de_posting_read(dev_priv, DPLL(pipe));
18473 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18475 struct intel_crtc *crtc;
18477 if (INTEL_GEN(dev_priv) >= 4)
18480 for_each_intel_crtc(&dev_priv->drm, crtc) {
18481 struct intel_plane *plane =
18482 to_intel_plane(crtc->base.primary);
18483 struct intel_crtc *plane_crtc;
18486 if (!plane->get_hw_state(plane, &pipe))
18489 if (pipe == crtc->pipe)
18492 drm_dbg_kms(&dev_priv->drm,
18493 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18494 plane->base.base.id, plane->base.name);
18496 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18497 intel_plane_disable_noatomic(plane_crtc, plane);
18501 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18503 struct drm_device *dev = crtc->base.dev;
18504 struct intel_encoder *encoder;
18506 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18512 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18514 struct drm_device *dev = encoder->base.dev;
18515 struct intel_connector *connector;
18517 for_each_connector_on_encoder(dev, &encoder->base, connector)
18523 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18524 enum pipe pch_transcoder)
18526 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18527 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18530 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18534 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18536 if (INTEL_GEN(dev_priv) >= 9 ||
18537 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18538 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18541 if (transcoder_is_dsi(cpu_transcoder))
18544 val = intel_de_read(dev_priv, reg);
18545 val &= ~HSW_FRAME_START_DELAY_MASK;
18546 val |= HSW_FRAME_START_DELAY(0);
18547 intel_de_write(dev_priv, reg, val);
18549 i915_reg_t reg = PIPECONF(cpu_transcoder);
18552 val = intel_de_read(dev_priv, reg);
18553 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18554 val |= PIPECONF_FRAME_START_DELAY(0);
18555 intel_de_write(dev_priv, reg, val);
18558 if (!crtc_state->has_pch_encoder)
18561 if (HAS_PCH_IBX(dev_priv)) {
18562 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18565 val = intel_de_read(dev_priv, reg);
18566 val &= ~TRANS_FRAME_START_DELAY_MASK;
18567 val |= TRANS_FRAME_START_DELAY(0);
18568 intel_de_write(dev_priv, reg, val);
18570 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18571 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18574 val = intel_de_read(dev_priv, reg);
18575 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18576 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18577 intel_de_write(dev_priv, reg, val);
18581 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18582 struct drm_modeset_acquire_ctx *ctx)
18584 struct drm_device *dev = crtc->base.dev;
18585 struct drm_i915_private *dev_priv = to_i915(dev);
18586 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18588 if (crtc_state->hw.active) {
18589 struct intel_plane *plane;
18591 /* Clear any frame start delays used for debugging left by the BIOS */
18592 intel_sanitize_frame_start_delay(crtc_state);
18594 /* Disable everything but the primary plane */
18595 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18596 const struct intel_plane_state *plane_state =
18597 to_intel_plane_state(plane->base.state);
18599 if (plane_state->uapi.visible &&
18600 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18601 intel_plane_disable_noatomic(crtc, plane);
18605 * Disable any background color set by the BIOS, but enable the
18606 * gamma and CSC to match how we program our planes.
18608 if (INTEL_GEN(dev_priv) >= 9)
18609 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18610 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18613 /* Adjust the state of the output pipe according to whether we
18614 * have active connectors/encoders. */
18615 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18616 intel_crtc_disable_noatomic(crtc, ctx);
18618 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18620 * We start out with underrun reporting disabled to avoid races.
18621 * For correct bookkeeping mark this on active crtcs.
18623 * Also on gmch platforms we dont have any hardware bits to
18624 * disable the underrun reporting. Which means we need to start
18625 * out with underrun reporting disabled also on inactive pipes,
18626 * since otherwise we'll complain about the garbage we read when
18627 * e.g. coming up after runtime pm.
18629 * No protection against concurrent access is required - at
18630 * worst a fifo underrun happens which also sets this to false.
18632 crtc->cpu_fifo_underrun_disabled = true;
18634 * We track the PCH trancoder underrun reporting state
18635 * within the crtc. With crtc for pipe A housing the underrun
18636 * reporting state for PCH transcoder A, crtc for pipe B housing
18637 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18638 * and marking underrun reporting as disabled for the non-existing
18639 * PCH transcoders B and C would prevent enabling the south
18640 * error interrupt (see cpt_can_enable_serr_int()).
18642 if (has_pch_trancoder(dev_priv, crtc->pipe))
18643 crtc->pch_fifo_underrun_disabled = true;
18647 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18649 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18652 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18653 * the hardware when a high res displays plugged in. DPLL P
18654 * divider is zero, and the pipe timings are bonkers. We'll
18655 * try to disable everything in that case.
18657 * FIXME would be nice to be able to sanitize this state
18658 * without several WARNs, but for now let's take the easy
18661 return IS_GEN(dev_priv, 6) &&
18662 crtc_state->hw.active &&
18663 crtc_state->shared_dpll &&
18664 crtc_state->port_clock == 0;
18667 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18669 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18670 struct intel_connector *connector;
18671 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18672 struct intel_crtc_state *crtc_state = crtc ?
18673 to_intel_crtc_state(crtc->base.state) : NULL;
18675 /* We need to check both for a crtc link (meaning that the
18676 * encoder is active and trying to read from a pipe) and the
18677 * pipe itself being active. */
18678 bool has_active_crtc = crtc_state &&
18679 crtc_state->hw.active;
18681 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18682 drm_dbg_kms(&dev_priv->drm,
18683 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18684 pipe_name(crtc->pipe));
18685 has_active_crtc = false;
18688 connector = intel_encoder_find_connector(encoder);
18689 if (connector && !has_active_crtc) {
18690 drm_dbg_kms(&dev_priv->drm,
18691 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18692 encoder->base.base.id,
18693 encoder->base.name);
18695 /* Connector is active, but has no active pipe. This is
18696 * fallout from our resume register restoring. Disable
18697 * the encoder manually again. */
18699 struct drm_encoder *best_encoder;
18701 drm_dbg_kms(&dev_priv->drm,
18702 "[ENCODER:%d:%s] manually disabled\n",
18703 encoder->base.base.id,
18704 encoder->base.name);
18706 /* avoid oopsing in case the hooks consult best_encoder */
18707 best_encoder = connector->base.state->best_encoder;
18708 connector->base.state->best_encoder = &encoder->base;
18710 /* FIXME NULL atomic state passed! */
18711 if (encoder->disable)
18712 encoder->disable(NULL, encoder, crtc_state,
18713 connector->base.state);
18714 if (encoder->post_disable)
18715 encoder->post_disable(NULL, encoder, crtc_state,
18716 connector->base.state);
18718 connector->base.state->best_encoder = best_encoder;
18720 encoder->base.crtc = NULL;
18722 /* Inconsistent output/port/pipe state happens presumably due to
18723 * a bug in one of the get_hw_state functions. Or someplace else
18724 * in our code, like the register restore mess on resume. Clamp
18725 * things to off as a safer default. */
18727 connector->base.dpms = DRM_MODE_DPMS_OFF;
18728 connector->base.encoder = NULL;
18731 /* notify opregion of the sanitized encoder state */
18732 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18734 if (INTEL_GEN(dev_priv) >= 11)
18735 icl_sanitize_encoder_pll_mapping(encoder);
18738 /* FIXME read out full plane state for all planes */
18739 static void readout_plane_state(struct drm_i915_private *dev_priv)
18741 struct intel_plane *plane;
18742 struct intel_crtc *crtc;
18744 for_each_intel_plane(&dev_priv->drm, plane) {
18745 struct intel_plane_state *plane_state =
18746 to_intel_plane_state(plane->base.state);
18747 struct intel_crtc_state *crtc_state;
18748 enum pipe pipe = PIPE_A;
18751 visible = plane->get_hw_state(plane, &pipe);
18753 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18754 crtc_state = to_intel_crtc_state(crtc->base.state);
18756 intel_set_plane_visible(crtc_state, plane_state, visible);
18758 drm_dbg_kms(&dev_priv->drm,
18759 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18760 plane->base.base.id, plane->base.name,
18761 enableddisabled(visible), pipe_name(pipe));
18764 for_each_intel_crtc(&dev_priv->drm, crtc) {
18765 struct intel_crtc_state *crtc_state =
18766 to_intel_crtc_state(crtc->base.state);
18768 fixup_active_planes(crtc_state);
18772 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18774 struct drm_i915_private *dev_priv = to_i915(dev);
18775 struct intel_cdclk_state *cdclk_state =
18776 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18777 struct intel_dbuf_state *dbuf_state =
18778 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18780 struct intel_crtc *crtc;
18781 struct intel_encoder *encoder;
18782 struct intel_connector *connector;
18783 struct drm_connector_list_iter conn_iter;
18784 u8 active_pipes = 0;
18786 for_each_intel_crtc(dev, crtc) {
18787 struct intel_crtc_state *crtc_state =
18788 to_intel_crtc_state(crtc->base.state);
18790 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18791 intel_crtc_free_hw_state(crtc_state);
18792 intel_crtc_state_reset(crtc_state, crtc);
18794 crtc_state->hw.active = crtc_state->hw.enable =
18795 dev_priv->display.get_pipe_config(crtc, crtc_state);
18797 crtc->base.enabled = crtc_state->hw.enable;
18798 crtc->active = crtc_state->hw.active;
18800 if (crtc_state->hw.active)
18801 active_pipes |= BIT(crtc->pipe);
18803 drm_dbg_kms(&dev_priv->drm,
18804 "[CRTC:%d:%s] hw state readout: %s\n",
18805 crtc->base.base.id, crtc->base.name,
18806 enableddisabled(crtc_state->hw.active));
18809 dev_priv->active_pipes = cdclk_state->active_pipes =
18810 dbuf_state->active_pipes = active_pipes;
18812 readout_plane_state(dev_priv);
18814 intel_dpll_readout_hw_state(dev_priv);
18816 for_each_intel_encoder(dev, encoder) {
18819 if (encoder->get_hw_state(encoder, &pipe)) {
18820 struct intel_crtc_state *crtc_state;
18822 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18823 crtc_state = to_intel_crtc_state(crtc->base.state);
18825 encoder->base.crtc = &crtc->base;
18826 encoder->get_config(encoder, crtc_state);
18827 if (encoder->sync_state)
18828 encoder->sync_state(encoder, crtc_state);
18830 encoder->base.crtc = NULL;
18833 drm_dbg_kms(&dev_priv->drm,
18834 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18835 encoder->base.base.id, encoder->base.name,
18836 enableddisabled(encoder->base.crtc),
18840 drm_connector_list_iter_begin(dev, &conn_iter);
18841 for_each_intel_connector_iter(connector, &conn_iter) {
18842 if (connector->get_hw_state(connector)) {
18843 struct intel_crtc_state *crtc_state;
18844 struct intel_crtc *crtc;
18846 connector->base.dpms = DRM_MODE_DPMS_ON;
18848 encoder = intel_attached_encoder(connector);
18849 connector->base.encoder = &encoder->base;
18851 crtc = to_intel_crtc(encoder->base.crtc);
18852 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18854 if (crtc_state && crtc_state->hw.active) {
18856 * This has to be done during hardware readout
18857 * because anything calling .crtc_disable may
18858 * rely on the connector_mask being accurate.
18860 crtc_state->uapi.connector_mask |=
18861 drm_connector_mask(&connector->base);
18862 crtc_state->uapi.encoder_mask |=
18863 drm_encoder_mask(&encoder->base);
18866 connector->base.dpms = DRM_MODE_DPMS_OFF;
18867 connector->base.encoder = NULL;
18869 drm_dbg_kms(&dev_priv->drm,
18870 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18871 connector->base.base.id, connector->base.name,
18872 enableddisabled(connector->base.encoder));
18874 drm_connector_list_iter_end(&conn_iter);
18876 for_each_intel_crtc(dev, crtc) {
18877 struct intel_bw_state *bw_state =
18878 to_intel_bw_state(dev_priv->bw_obj.state);
18879 struct intel_crtc_state *crtc_state =
18880 to_intel_crtc_state(crtc->base.state);
18881 struct intel_plane *plane;
18884 if (crtc_state->hw.active) {
18885 struct drm_display_mode *mode = &crtc_state->hw.mode;
18887 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18890 *mode = crtc_state->hw.adjusted_mode;
18891 mode->hdisplay = crtc_state->pipe_src_w;
18892 mode->vdisplay = crtc_state->pipe_src_h;
18895 * The initial mode needs to be set in order to keep
18896 * the atomic core happy. It wants a valid mode if the
18897 * crtc's enabled, so we do the above call.
18899 * But we don't set all the derived state fully, hence
18900 * set a flag to indicate that a full recalculation is
18901 * needed on the next commit.
18903 crtc_state->inherited = true;
18905 intel_crtc_compute_pixel_rate(crtc_state);
18907 intel_crtc_update_active_timings(crtc_state);
18909 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18912 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18913 const struct intel_plane_state *plane_state =
18914 to_intel_plane_state(plane->base.state);
18917 * FIXME don't have the fb yet, so can't
18918 * use intel_plane_data_rate() :(
18920 if (plane_state->uapi.visible)
18921 crtc_state->data_rate[plane->id] =
18922 4 * crtc_state->pixel_rate;
18924 * FIXME don't have the fb yet, so can't
18925 * use plane->min_cdclk() :(
18927 if (plane_state->uapi.visible && plane->min_cdclk) {
18928 if (crtc_state->double_wide ||
18929 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18930 crtc_state->min_cdclk[plane->id] =
18931 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18933 crtc_state->min_cdclk[plane->id] =
18934 crtc_state->pixel_rate;
18936 drm_dbg_kms(&dev_priv->drm,
18937 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18938 plane->base.base.id, plane->base.name,
18939 crtc_state->min_cdclk[plane->id]);
18942 if (crtc_state->hw.active) {
18943 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18944 if (drm_WARN_ON(dev, min_cdclk < 0))
18948 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18949 cdclk_state->min_voltage_level[crtc->pipe] =
18950 crtc_state->min_voltage_level;
18952 intel_bw_crtc_update(bw_state, crtc_state);
18954 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18959 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18961 struct intel_encoder *encoder;
18963 for_each_intel_encoder(&dev_priv->drm, encoder) {
18964 struct intel_crtc_state *crtc_state;
18966 if (!encoder->get_power_domains)
18970 * MST-primary and inactive encoders don't have a crtc state
18971 * and neither of these require any power domain references.
18973 if (!encoder->base.crtc)
18976 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18977 encoder->get_power_domains(encoder, crtc_state);
18981 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18984 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18985 * Also known as Wa_14010480278.
18987 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18988 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18989 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18991 if (IS_HASWELL(dev_priv)) {
18993 * WaRsPkgCStateDisplayPMReq:hsw
18994 * System hang if this isn't done before disabling all planes!
18996 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18997 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
19000 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
19001 /* Display WA #1142:kbl,cfl,cml */
19002 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
19003 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
19004 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
19005 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
19006 KBL_ARB_FILL_SPARE_14);
19010 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
19011 enum port port, i915_reg_t hdmi_reg)
19013 u32 val = intel_de_read(dev_priv, hdmi_reg);
19015 if (val & SDVO_ENABLE ||
19016 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
19019 drm_dbg_kms(&dev_priv->drm,
19020 "Sanitizing transcoder select for HDMI %c\n",
19023 val &= ~SDVO_PIPE_SEL_MASK;
19024 val |= SDVO_PIPE_SEL(PIPE_A);
19026 intel_de_write(dev_priv, hdmi_reg, val);
19029 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
19030 enum port port, i915_reg_t dp_reg)
19032 u32 val = intel_de_read(dev_priv, dp_reg);
19034 if (val & DP_PORT_EN ||
19035 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
19038 drm_dbg_kms(&dev_priv->drm,
19039 "Sanitizing transcoder select for DP %c\n",
19042 val &= ~DP_PIPE_SEL_MASK;
19043 val |= DP_PIPE_SEL(PIPE_A);
19045 intel_de_write(dev_priv, dp_reg, val);
19048 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
19051 * The BIOS may select transcoder B on some of the PCH
19052 * ports even it doesn't enable the port. This would trip
19053 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
19054 * Sanitize the transcoder select bits to prevent that. We
19055 * assume that the BIOS never actually enabled the port,
19056 * because if it did we'd actually have to toggle the port
19057 * on and back off to make the transcoder A select stick
19058 * (see. intel_dp_link_down(), intel_disable_hdmi(),
19059 * intel_disable_sdvo()).
19061 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
19062 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
19063 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
19065 /* PCH SDVOB multiplex with HDMIB */
19066 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
19067 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
19068 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
19071 /* Scan out the current hw modeset state,
19072 * and sanitizes it to the current state
19075 intel_modeset_setup_hw_state(struct drm_device *dev,
19076 struct drm_modeset_acquire_ctx *ctx)
19078 struct drm_i915_private *dev_priv = to_i915(dev);
19079 struct intel_encoder *encoder;
19080 struct intel_crtc *crtc;
19081 intel_wakeref_t wakeref;
19083 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
19085 intel_early_display_was(dev_priv);
19086 intel_modeset_readout_hw_state(dev);
19088 /* HW state is read out, now we need to sanitize this mess. */
19090 /* Sanitize the TypeC port mode upfront, encoders depend on this */
19091 for_each_intel_encoder(dev, encoder) {
19092 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
19094 /* We need to sanitize only the MST primary port. */
19095 if (encoder->type != INTEL_OUTPUT_DP_MST &&
19096 intel_phy_is_tc(dev_priv, phy))
19097 intel_tc_port_sanitize(enc_to_dig_port(encoder));
19100 get_encoder_power_domains(dev_priv);
19102 if (HAS_PCH_IBX(dev_priv))
19103 ibx_sanitize_pch_ports(dev_priv);
19106 * intel_sanitize_plane_mapping() may need to do vblank
19107 * waits, so we need vblank interrupts restored beforehand.
19109 for_each_intel_crtc(&dev_priv->drm, crtc) {
19110 struct intel_crtc_state *crtc_state =
19111 to_intel_crtc_state(crtc->base.state);
19113 drm_crtc_vblank_reset(&crtc->base);
19115 if (crtc_state->hw.active)
19116 intel_crtc_vblank_on(crtc_state);
19119 intel_sanitize_plane_mapping(dev_priv);
19121 for_each_intel_encoder(dev, encoder)
19122 intel_sanitize_encoder(encoder);
19124 for_each_intel_crtc(&dev_priv->drm, crtc) {
19125 struct intel_crtc_state *crtc_state =
19126 to_intel_crtc_state(crtc->base.state);
19128 intel_sanitize_crtc(crtc, ctx);
19129 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
19132 intel_modeset_update_connector_atomic_state(dev);
19134 intel_dpll_sanitize_state(dev_priv);
19136 if (IS_G4X(dev_priv)) {
19137 g4x_wm_get_hw_state(dev_priv);
19138 g4x_wm_sanitize(dev_priv);
19139 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
19140 vlv_wm_get_hw_state(dev_priv);
19141 vlv_wm_sanitize(dev_priv);
19142 } else if (INTEL_GEN(dev_priv) >= 9) {
19143 skl_wm_get_hw_state(dev_priv);
19144 } else if (HAS_PCH_SPLIT(dev_priv)) {
19145 ilk_wm_get_hw_state(dev_priv);
19148 for_each_intel_crtc(dev, crtc) {
19149 struct intel_crtc_state *crtc_state =
19150 to_intel_crtc_state(crtc->base.state);
19153 put_domains = modeset_get_crtc_power_domains(crtc_state);
19154 if (drm_WARN_ON(dev, put_domains))
19155 modeset_put_power_domains(dev_priv, put_domains);
19158 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
19161 void intel_display_resume(struct drm_device *dev)
19163 struct drm_i915_private *dev_priv = to_i915(dev);
19164 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
19165 struct drm_modeset_acquire_ctx ctx;
19168 dev_priv->modeset_restore_state = NULL;
19170 state->acquire_ctx = &ctx;
19172 drm_modeset_acquire_init(&ctx, 0);
19175 ret = drm_modeset_lock_all_ctx(dev, &ctx);
19176 if (ret != -EDEADLK)
19179 drm_modeset_backoff(&ctx);
19183 ret = __intel_display_resume(dev, state, &ctx);
19185 intel_enable_ipc(dev_priv);
19186 drm_modeset_drop_locks(&ctx);
19187 drm_modeset_acquire_fini(&ctx);
19190 drm_err(&dev_priv->drm,
19191 "Restoring old state failed with %i\n", ret);
19193 drm_atomic_state_put(state);
19196 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
19198 struct intel_connector *connector;
19199 struct drm_connector_list_iter conn_iter;
19201 /* Kill all the work that may have been queued by hpd. */
19202 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
19203 for_each_intel_connector_iter(connector, &conn_iter) {
19204 if (connector->modeset_retry_work.func)
19205 cancel_work_sync(&connector->modeset_retry_work);
19206 if (connector->hdcp.shim) {
19207 cancel_delayed_work_sync(&connector->hdcp.check_work);
19208 cancel_work_sync(&connector->hdcp.prop_work);
19211 drm_connector_list_iter_end(&conn_iter);
19214 /* part #1: call before irq uninstall */
19215 void intel_modeset_driver_remove(struct drm_i915_private *i915)
19217 flush_workqueue(i915->flip_wq);
19218 flush_workqueue(i915->modeset_wq);
19220 flush_work(&i915->atomic_helper.free_work);
19221 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
19224 /* part #2: call after irq uninstall */
19225 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
19228 * Due to the hpd irq storm handling the hotplug work can re-arm the
19229 * poll handlers. Hence disable polling after hpd handling is shut down.
19231 intel_hpd_poll_fini(i915);
19234 * MST topology needs to be suspended so we don't have any calls to
19235 * fbdev after it's finalized. MST will be destroyed later as part of
19236 * drm_mode_config_cleanup()
19238 intel_dp_mst_suspend(i915);
19240 /* poll work can call into fbdev, hence clean that up afterwards */
19241 intel_fbdev_fini(i915);
19243 intel_unregister_dsm_handler();
19245 intel_fbc_global_disable(i915);
19247 /* flush any delayed tasks or pending work */
19248 flush_scheduled_work();
19250 intel_hdcp_component_fini(i915);
19252 intel_mode_config_cleanup(i915);
19254 intel_overlay_cleanup(i915);
19256 intel_gmbus_teardown(i915);
19258 destroy_workqueue(i915->flip_wq);
19259 destroy_workqueue(i915->modeset_wq);
19261 intel_fbc_cleanup_cfb(i915);
19264 /* part #3: call after gem init */
19265 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
19267 intel_csr_ucode_fini(i915);
19269 intel_power_domains_driver_remove(i915);
19271 intel_vga_unregister(i915);
19273 intel_bios_driver_remove(i915);
19276 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
19278 struct intel_display_error_state {
19280 u32 power_well_driver;
19282 struct intel_cursor_error_state {
19287 } cursor[I915_MAX_PIPES];
19289 struct intel_pipe_error_state {
19290 bool power_domain_on;
19293 } pipe[I915_MAX_PIPES];
19295 struct intel_plane_error_state {
19303 } plane[I915_MAX_PIPES];
19305 struct intel_transcoder_error_state {
19307 bool power_domain_on;
19308 enum transcoder cpu_transcoder;
19321 struct intel_display_error_state *
19322 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19324 struct intel_display_error_state *error;
19325 int transcoders[] = {
19334 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19336 if (!HAS_DISPLAY(dev_priv))
19339 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19343 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19344 error->power_well_driver = intel_de_read(dev_priv,
19345 HSW_PWR_WELL_CTL2);
19347 for_each_pipe(dev_priv, i) {
19348 error->pipe[i].power_domain_on =
19349 __intel_display_power_is_enabled(dev_priv,
19350 POWER_DOMAIN_PIPE(i));
19351 if (!error->pipe[i].power_domain_on)
19354 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19355 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19356 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19358 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19359 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19360 if (INTEL_GEN(dev_priv) <= 3) {
19361 error->plane[i].size = intel_de_read(dev_priv,
19363 error->plane[i].pos = intel_de_read(dev_priv,
19366 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19367 error->plane[i].addr = intel_de_read(dev_priv,
19369 if (INTEL_GEN(dev_priv) >= 4) {
19370 error->plane[i].surface = intel_de_read(dev_priv,
19372 error->plane[i].tile_offset = intel_de_read(dev_priv,
19376 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19378 if (HAS_GMCH(dev_priv))
19379 error->pipe[i].stat = intel_de_read(dev_priv,
19383 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19384 enum transcoder cpu_transcoder = transcoders[i];
19386 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19389 error->transcoder[i].available = true;
19390 error->transcoder[i].power_domain_on =
19391 __intel_display_power_is_enabled(dev_priv,
19392 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19393 if (!error->transcoder[i].power_domain_on)
19396 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19398 error->transcoder[i].conf = intel_de_read(dev_priv,
19399 PIPECONF(cpu_transcoder));
19400 error->transcoder[i].htotal = intel_de_read(dev_priv,
19401 HTOTAL(cpu_transcoder));
19402 error->transcoder[i].hblank = intel_de_read(dev_priv,
19403 HBLANK(cpu_transcoder));
19404 error->transcoder[i].hsync = intel_de_read(dev_priv,
19405 HSYNC(cpu_transcoder));
19406 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19407 VTOTAL(cpu_transcoder));
19408 error->transcoder[i].vblank = intel_de_read(dev_priv,
19409 VBLANK(cpu_transcoder));
19410 error->transcoder[i].vsync = intel_de_read(dev_priv,
19411 VSYNC(cpu_transcoder));
19417 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19420 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19421 struct intel_display_error_state *error)
19423 struct drm_i915_private *dev_priv = m->i915;
19429 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19430 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19431 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19432 error->power_well_driver);
19433 for_each_pipe(dev_priv, i) {
19434 err_printf(m, "Pipe [%d]:\n", i);
19435 err_printf(m, " Power: %s\n",
19436 onoff(error->pipe[i].power_domain_on));
19437 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19438 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19440 err_printf(m, "Plane [%d]:\n", i);
19441 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19442 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19443 if (INTEL_GEN(dev_priv) <= 3) {
19444 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19445 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19447 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19448 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19449 if (INTEL_GEN(dev_priv) >= 4) {
19450 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19451 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19454 err_printf(m, "Cursor [%d]:\n", i);
19455 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19456 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19457 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19460 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19461 if (!error->transcoder[i].available)
19464 err_printf(m, "CPU transcoder: %s\n",
19465 transcoder_name(error->transcoder[i].cpu_transcoder));
19466 err_printf(m, " Power: %s\n",
19467 onoff(error->transcoder[i].power_domain_on));
19468 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19469 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19470 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19471 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19472 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19473 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19474 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);