drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_damage_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_rect.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dp_mst.h"
  50 #include "display/intel_dpll_mgr.h"
  51 #include "display/intel_dsi.h"
  52 #include "display/intel_dvo.h"
  53 #include "display/intel_gmbus.h"
  54 #include "display/intel_hdmi.h"
  55 #include "display/intel_lvds.h"
  56 #include "display/intel_sdvo.h"
  57 #include "display/intel_tv.h"
  58 #include "display/intel_vdsc.h"
  59
  60 #include "gt/intel_rps.h"
  61
  62 #include "i915_drv.h"
  63 #include "i915_trace.h"
  64 #include "intel_acpi.h"
  65 #include "intel_atomic.h"
  66 #include "intel_atomic_plane.h"
  67 #include "intel_bw.h"
  68 #include "intel_cdclk.h"
  69 #include "intel_color.h"
  70 #include "intel_csr.h"
  71 #include "intel_display_types.h"
  72 #include "intel_dp_link_training.h"
  73 #include "intel_fbc.h"
  74 #include "intel_fbdev.h"
  75 #include "intel_fifo_underrun.h"
  76 #include "intel_frontbuffer.h"
  77 #include "intel_hdcp.h"
  78 #include "intel_hotplug.h"
  79 #include "intel_overlay.h"
  80 #include "intel_pipe_crc.h"
  81 #include "intel_pm.h"
  82 #include "intel_psr.h"
  83 #include "intel_quirks.h"
  84 #include "intel_sideband.h"
  85 #include "intel_sprite.h"
  86 #include "intel_tc.h"
  87 #include "intel_vga.h"
  88
  89 /* Primary plane formats for gen <= 3 */
  90 static const u32 i8xx_primary_formats[] = {
  91         DRM_FORMAT_C8,
  92         DRM_FORMAT_XRGB1555,
  93         DRM_FORMAT_RGB565,
  94         DRM_FORMAT_XRGB8888,
  95 };
  96
  97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  98 static const u32 ivb_primary_formats[] = {
  99         DRM_FORMAT_C8,
 100         DRM_FORMAT_RGB565,
 101         DRM_FORMAT_XRGB8888,
 102         DRM_FORMAT_XBGR8888,
 103         DRM_FORMAT_XRGB2101010,
 104         DRM_FORMAT_XBGR2101010,
 105 };
 106
 107 /* Primary plane formats for gen >= 4, except ivb */
 108 static const u32 i965_primary_formats[] = {
 109         DRM_FORMAT_C8,
 110         DRM_FORMAT_RGB565,
 111         DRM_FORMAT_XRGB8888,
 112         DRM_FORMAT_XBGR8888,
 113         DRM_FORMAT_XRGB2101010,
 114         DRM_FORMAT_XBGR2101010,
 115         DRM_FORMAT_XBGR16161616F,
 116 };
 117
 118 /* Primary plane formats for vlv/chv */
 119 static const u32 vlv_primary_formats[] = {
 120         DRM_FORMAT_C8,
 121         DRM_FORMAT_RGB565,
 122         DRM_FORMAT_XRGB8888,
 123         DRM_FORMAT_XBGR8888,
 124         DRM_FORMAT_ARGB8888,
 125         DRM_FORMAT_ABGR8888,
 126         DRM_FORMAT_XRGB2101010,
 127         DRM_FORMAT_XBGR2101010,
 128         DRM_FORMAT_ARGB2101010,
 129         DRM_FORMAT_ABGR2101010,
 130         DRM_FORMAT_XBGR16161616F,
 131 };
 132
 133 static const u64 i9xx_format_modifiers[] = {
 134         I915_FORMAT_MOD_X_TILED,
 135         DRM_FORMAT_MOD_LINEAR,
 136         DRM_FORMAT_MOD_INVALID
 137 };
 138
 139 /* Cursor formats */
 140 static const u32 intel_cursor_formats[] = {
 141         DRM_FORMAT_ARGB8888,
 142 };
 143
 144 static const u64 cursor_format_modifiers[] = {
 145         DRM_FORMAT_MOD_LINEAR,
 146         DRM_FORMAT_MOD_INVALID
 147 };
 148
 149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 150                                 struct intel_crtc_state *pipe_config);
 151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
 152                               struct intel_crtc_state *pipe_config);
 153
 154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 155                                   struct drm_i915_gem_object *obj,
 156                                   struct drm_mode_fb_cmd2 *mode_cmd);
 157 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 160                                          const struct intel_link_m_n *m_n,
 161                                          const struct intel_link_m_n *m2_n2);
 162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 166 static void vlv_prepare_pll(struct intel_crtc *crtc,
 167                             const struct intel_crtc_state *pipe_config);
 168 static void chv_prepare_pll(struct intel_crtc *crtc,
 169                             const struct intel_crtc_state *pipe_config);
 170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
 171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 175
 176 struct intel_limit {
 177         struct {
 178                 int min, max;
 179         } dot, vco, n, m, m1, m2, p, p1;
 180
 181         struct {
 182                 int dot_limit;
 183                 int p2_slow, p2_fast;
 184         } p2;
 185 };
 186
 187 /* returns HPLL frequency in kHz */
 188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 189 {
 190         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 191
 192         /* Obtain SKU information */
 193         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 194                 CCK_FUSE_HPLL_FREQ_MASK;
 195
 196         return vco_freq[hpll_freq] * 1000;
 197 }
 198
 199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 200                       const char *name, u32 reg, int ref_freq)
 201 {
 202         u32 val;
 203         int divider;
 204
 205         val = vlv_cck_read(dev_priv, reg);
 206         divider = val & CCK_FREQUENCY_VALUES;
 207
 208         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 209                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 210                  "%s change in progress\n", name);
 211
 212         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 213 }
 214
 215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 216                            const char *name, u32 reg)
 217 {
 218         int hpll;
 219
 220         vlv_cck_get(dev_priv);
 221
 222         if (dev_priv->hpll_freq == 0)
 223                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 224
 225         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 226
 227         vlv_cck_put(dev_priv);
 228
 229         return hpll;
 230 }
 231
 232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 233 {
 234         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 235                 return;
 236
 237         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 238                                                       CCK_CZ_CLOCK_CONTROL);
 239
 240         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 241                 dev_priv->czclk_freq);
 242 }
 243
 244 /* units of 100MHz */
 245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 246                                const struct intel_crtc_state *pipe_config)
 247 {
 248         if (HAS_DDI(dev_priv))
 249                 return pipe_config->port_clock; /* SPLL */
 250         else
 251                 return dev_priv->fdi_pll_freq;
 252 }
 253
 254 static const struct intel_limit intel_limits_i8xx_dac = {
 255         .dot = { .min = 25000, .max = 350000 },
 256         .vco = { .min = 908000, .max = 1512000 },
 257         .n = { .min = 2, .max = 16 },
 258         .m = { .min = 96, .max = 140 },
 259         .m1 = { .min = 18, .max = 26 },
 260         .m2 = { .min = 6, .max = 16 },
 261         .p = { .min = 4, .max = 128 },
 262         .p1 = { .min = 2, .max = 33 },
 263         .p2 = { .dot_limit = 165000,
 264                 .p2_slow = 4, .p2_fast = 2 },
 265 };
 266
 267 static const struct intel_limit intel_limits_i8xx_dvo = {
 268         .dot = { .min = 25000, .max = 350000 },
 269         .vco = { .min = 908000, .max = 1512000 },
 270         .n = { .min = 2, .max = 16 },
 271         .m = { .min = 96, .max = 140 },
 272         .m1 = { .min = 18, .max = 26 },
 273         .m2 = { .min = 6, .max = 16 },
 274         .p = { .min = 4, .max = 128 },
 275         .p1 = { .min = 2, .max = 33 },
 276         .p2 = { .dot_limit = 165000,
 277                 .p2_slow = 4, .p2_fast = 4 },
 278 };
 279
 280 static const struct intel_limit intel_limits_i8xx_lvds = {
 281         .dot = { .min = 25000, .max = 350000 },
 282         .vco = { .min = 908000, .max = 1512000 },
 283         .n = { .min = 2, .max = 16 },
 284         .m = { .min = 96, .max = 140 },
 285         .m1 = { .min = 18, .max = 26 },
 286         .m2 = { .min = 6, .max = 16 },
 287         .p = { .min = 4, .max = 128 },
 288         .p1 = { .min = 1, .max = 6 },
 289         .p2 = { .dot_limit = 165000,
 290                 .p2_slow = 14, .p2_fast = 7 },
 291 };
 292
 293 static const struct intel_limit intel_limits_i9xx_sdvo = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1400000, .max = 2800000 },
 296         .n = { .min = 1, .max = 6 },
 297         .m = { .min = 70, .max = 120 },
 298         .m1 = { .min = 8, .max = 18 },
 299         .m2 = { .min = 3, .max = 7 },
 300         .p = { .min = 5, .max = 80 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 200000,
 303                 .p2_slow = 10, .p2_fast = 5 },
 304 };
 305
 306 static const struct intel_limit intel_limits_i9xx_lvds = {
 307         .dot = { .min = 20000, .max = 400000 },
 308         .vco = { .min = 1400000, .max = 2800000 },
 309         .n = { .min = 1, .max = 6 },
 310         .m = { .min = 70, .max = 120 },
 311         .m1 = { .min = 8, .max = 18 },
 312         .m2 = { .min = 3, .max = 7 },
 313         .p = { .min = 7, .max = 98 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 112000,
 316                 .p2_slow = 14, .p2_fast = 7 },
 317 };
 318
 319
 320 static const struct intel_limit intel_limits_g4x_sdvo = {
 321         .dot = { .min = 25000, .max = 270000 },
 322         .vco = { .min = 1750000, .max = 3500000},
 323         .n = { .min = 1, .max = 4 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 10, .max = 30 },
 328         .p1 = { .min = 1, .max = 3},
 329         .p2 = { .dot_limit = 270000,
 330                 .p2_slow = 10,
 331                 .p2_fast = 10
 332         },
 333 };
 334
 335 static const struct intel_limit intel_limits_g4x_hdmi = {
 336         .dot = { .min = 22000, .max = 400000 },
 337         .vco = { .min = 1750000, .max = 3500000},
 338         .n = { .min = 1, .max = 4 },
 339         .m = { .min = 104, .max = 138 },
 340         .m1 = { .min = 16, .max = 23 },
 341         .m2 = { .min = 5, .max = 11 },
 342         .p = { .min = 5, .max = 80 },
 343         .p1 = { .min = 1, .max = 8},
 344         .p2 = { .dot_limit = 165000,
 345                 .p2_slow = 10, .p2_fast = 5 },
 346 };
 347
 348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 349         .dot = { .min = 20000, .max = 115000 },
 350         .vco = { .min = 1750000, .max = 3500000 },
 351         .n = { .min = 1, .max = 3 },
 352         .m = { .min = 104, .max = 138 },
 353         .m1 = { .min = 17, .max = 23 },
 354         .m2 = { .min = 5, .max = 11 },
 355         .p = { .min = 28, .max = 112 },
 356         .p1 = { .min = 2, .max = 8 },
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 14, .p2_fast = 14
 359         },
 360 };
 361
 362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 363         .dot = { .min = 80000, .max = 224000 },
 364         .vco = { .min = 1750000, .max = 3500000 },
 365         .n = { .min = 1, .max = 3 },
 366         .m = { .min = 104, .max = 138 },
 367         .m1 = { .min = 17, .max = 23 },
 368         .m2 = { .min = 5, .max = 11 },
 369         .p = { .min = 14, .max = 42 },
 370         .p1 = { .min = 2, .max = 6 },
 371         .p2 = { .dot_limit = 0,
 372                 .p2_slow = 7, .p2_fast = 7
 373         },
 374 };
 375
 376 static const struct intel_limit pnv_limits_sdvo = {
 377         .dot = { .min = 20000, .max = 400000},
 378         .vco = { .min = 1700000, .max = 3500000 },
 379         /* Pineview's Ncounter is a ring counter */
 380         .n = { .min = 3, .max = 6 },
 381         .m = { .min = 2, .max = 256 },
 382         /* Pineview only has one combined m divider, which we treat as m2. */
 383         .m1 = { .min = 0, .max = 0 },
 384         .m2 = { .min = 0, .max = 254 },
 385         .p = { .min = 5, .max = 80 },
 386         .p1 = { .min = 1, .max = 8 },
 387         .p2 = { .dot_limit = 200000,
 388                 .p2_slow = 10, .p2_fast = 5 },
 389 };
 390
 391 static const struct intel_limit pnv_limits_lvds = {
 392         .dot = { .min = 20000, .max = 400000 },
 393         .vco = { .min = 1700000, .max = 3500000 },
 394         .n = { .min = 3, .max = 6 },
 395         .m = { .min = 2, .max = 256 },
 396         .m1 = { .min = 0, .max = 0 },
 397         .m2 = { .min = 0, .max = 254 },
 398         .p = { .min = 7, .max = 112 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 112000,
 401                 .p2_slow = 14, .p2_fast = 14 },
 402 };
 403
 404 /* Ironlake / Sandybridge
 405  *
 406  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 407  * the range value for them is (actual_value - 2).
 408  */
 409 static const struct intel_limit ilk_limits_dac = {
 410         .dot = { .min = 25000, .max = 350000 },
 411         .vco = { .min = 1760000, .max = 3510000 },
 412         .n = { .min = 1, .max = 5 },
 413         .m = { .min = 79, .max = 127 },
 414         .m1 = { .min = 12, .max = 22 },
 415         .m2 = { .min = 5, .max = 9 },
 416         .p = { .min = 5, .max = 80 },
 417         .p1 = { .min = 1, .max = 8 },
 418         .p2 = { .dot_limit = 225000,
 419                 .p2_slow = 10, .p2_fast = 5 },
 420 };
 421
 422 static const struct intel_limit ilk_limits_single_lvds = {
 423         .dot = { .min = 25000, .max = 350000 },
 424         .vco = { .min = 1760000, .max = 3510000 },
 425         .n = { .min = 1, .max = 3 },
 426         .m = { .min = 79, .max = 118 },
 427         .m1 = { .min = 12, .max = 22 },
 428         .m2 = { .min = 5, .max = 9 },
 429         .p = { .min = 28, .max = 112 },
 430         .p1 = { .min = 2, .max = 8 },
 431         .p2 = { .dot_limit = 225000,
 432                 .p2_slow = 14, .p2_fast = 14 },
 433 };
 434
 435 static const struct intel_limit ilk_limits_dual_lvds = {
 436         .dot = { .min = 25000, .max = 350000 },
 437         .vco = { .min = 1760000, .max = 3510000 },
 438         .n = { .min = 1, .max = 3 },
 439         .m = { .min = 79, .max = 127 },
 440         .m1 = { .min = 12, .max = 22 },
 441         .m2 = { .min = 5, .max = 9 },
 442         .p = { .min = 14, .max = 56 },
 443         .p1 = { .min = 2, .max = 8 },
 444         .p2 = { .dot_limit = 225000,
 445                 .p2_slow = 7, .p2_fast = 7 },
 446 };
 447
 448 /* LVDS 100mhz refclk limits. */
 449 static const struct intel_limit ilk_limits_single_lvds_100m = {
 450         .dot = { .min = 25000, .max = 350000 },
 451         .vco = { .min = 1760000, .max = 3510000 },
 452         .n = { .min = 1, .max = 2 },
 453         .m = { .min = 79, .max = 126 },
 454         .m1 = { .min = 12, .max = 22 },
 455         .m2 = { .min = 5, .max = 9 },
 456         .p = { .min = 28, .max = 112 },
 457         .p1 = { .min = 2, .max = 8 },
 458         .p2 = { .dot_limit = 225000,
 459                 .p2_slow = 14, .p2_fast = 14 },
 460 };
 461
 462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 463         .dot = { .min = 25000, .max = 350000 },
 464         .vco = { .min = 1760000, .max = 3510000 },
 465         .n = { .min = 1, .max = 3 },
 466         .m = { .min = 79, .max = 126 },
 467         .m1 = { .min = 12, .max = 22 },
 468         .m2 = { .min = 5, .max = 9 },
 469         .p = { .min = 14, .max = 42 },
 470         .p1 = { .min = 2, .max = 6 },
 471         .p2 = { .dot_limit = 225000,
 472                 .p2_slow = 7, .p2_fast = 7 },
 473 };
 474
 475 static const struct intel_limit intel_limits_vlv = {
 476          /*
 477           * These are the data rate limits (measured in fast clocks)
 478           * since those are the strictest limits we have. The fast
 479           * clock and actual rate limits are more relaxed, so checking
 480           * them would make no difference.
 481           */
 482         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 483         .vco = { .min = 4000000, .max = 6000000 },
 484         .n = { .min = 1, .max = 7 },
 485         .m1 = { .min = 2, .max = 3 },
 486         .m2 = { .min = 11, .max = 156 },
 487         .p1 = { .min = 2, .max = 3 },
 488         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 489 };
 490
 491 static const struct intel_limit intel_limits_chv = {
 492         /*
 493          * These are the data rate limits (measured in fast clocks)
 494          * since those are the strictest limits we have.  The fast
 495          * clock and actual rate limits are more relaxed, so checking
 496          * them would make no difference.
 497          */
 498         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 499         .vco = { .min = 4800000, .max = 6480000 },
 500         .n = { .min = 1, .max = 1 },
 501         .m1 = { .min = 2, .max = 2 },
 502         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 503         .p1 = { .min = 2, .max = 4 },
 504         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 505 };
 506
 507 static const struct intel_limit intel_limits_bxt = {
 508         /* FIXME: find real dot limits */
 509         .dot = { .min = 0, .max = INT_MAX },
 510         .vco = { .min = 4800000, .max = 6700000 },
 511         .n = { .min = 1, .max = 1 },
 512         .m1 = { .min = 2, .max = 2 },
 513         /* FIXME: find real m2 limits */
 514         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 515         .p1 = { .min = 2, .max = 4 },
 516         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 517 };
 518
 519 /* WA Display #0827: Gen9:all */
 520 static void
 521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 522 {
 523         if (enable)
 524                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 525                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 526         else
 527                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 528                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 529 }
 530
 531 /* Wa_2006604312:icl,ehl */
 532 static void
 533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 534                        bool enable)
 535 {
 536         if (enable)
 537                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 538                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 539         else
 540                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 541                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 542 }
 543
 544 static bool
 545 needs_modeset(const struct intel_crtc_state *state)
 546 {
 547         return drm_atomic_crtc_needs_modeset(&state->uapi);
 548 }
 549
 550 static bool
 551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 552 {
 553         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 554 }
 555
 556 static bool
 557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 558 {
 559         return crtc_state->sync_mode_slaves_mask != 0;
 560 }
 561
 562 bool
 563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 564 {
 565         return is_trans_port_sync_master(crtc_state) ||
 566                 is_trans_port_sync_slave(crtc_state);
 567 }
 568
 569 /*
 570  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 571  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 572  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 573  * The helpers' return value is the rate of the clock that is fed to the
 574  * display engine's pipe which can be the above fast dot clock rate or a
 575  * divided-down version of it.
 576  */
 577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 579 {
 580         clock->m = clock->m2 + 2;
 581         clock->p = clock->p1 * clock->p2;
 582         if (WARN_ON(clock->n == 0 || clock->p == 0))
 583                 return 0;
 584         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 585         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 586
 587         return clock->dot;
 588 }
 589
 590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 591 {
 592         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 593 }
 594
 595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 596 {
 597         clock->m = i9xx_dpll_compute_m(clock);
 598         clock->p = clock->p1 * clock->p2;
 599         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 600                 return 0;
 601         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 602         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 603
 604         return clock->dot;
 605 }
 606
 607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 608 {
 609         clock->m = clock->m1 * clock->m2;
 610         clock->p = clock->p1 * clock->p2;
 611         if (WARN_ON(clock->n == 0 || clock->p == 0))
 612                 return 0;
 613         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 614         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 615
 616         return clock->dot / 5;
 617 }
 618
 619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 620 {
 621         clock->m = clock->m1 * clock->m2;
 622         clock->p = clock->p1 * clock->p2;
 623         if (WARN_ON(clock->n == 0 || clock->p == 0))
 624                 return 0;
 625         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 626                                            clock->n << 22);
 627         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 628
 629         return clock->dot / 5;
 630 }
 631
 632 /*
 633  * Returns whether the given set of divisors are valid for a given refclk with
 634  * the given connectors.
 635  */
 636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 637                                const struct intel_limit *limit,
 638                                const struct dpll *clock)
 639 {
 640         if (clock->n < limit->n.min || limit->n.max < clock->n)
 641                 return false;
 642         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 643                 return false;
 644         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 645                 return false;
 646         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 647                 return false;
 648
 649         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 650             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 651                 if (clock->m1 <= clock->m2)
 652                         return false;
 653
 654         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 655             !IS_GEN9_LP(dev_priv)) {
 656                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 657                         return false;
 658                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 659                         return false;
 660         }
 661
 662         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 663                 return false;
 664         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 665          * connector, etc., rather than just a single range.
 666          */
 667         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 668                 return false;
 669
 670         return true;
 671 }
 672
 673 static int
 674 i9xx_select_p2_div(const struct intel_limit *limit,
 675                    const struct intel_crtc_state *crtc_state,
 676                    int target)
 677 {
 678         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 679
 680         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 681                 /*
 682                  * For LVDS just rely on its current settings for dual-channel.
 683                  * We haven't figured out how to reliably set up different
 684                  * single/dual channel state, if we even can.
 685                  */
 686                 if (intel_is_dual_link_lvds(dev_priv))
 687                         return limit->p2.p2_fast;
 688                 else
 689                         return limit->p2.p2_slow;
 690         } else {
 691                 if (target < limit->p2.dot_limit)
 692                         return limit->p2.p2_slow;
 693                 else
 694                         return limit->p2.p2_fast;
 695         }
 696 }
 697
 698 /*
 699  * Returns a set of divisors for the desired target clock with the given
 700  * refclk, or FALSE.  The returned values represent the clock equation:
 701  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 702  *
 703  * Target and reference clocks are specified in kHz.
 704  *
 705  * If match_clock is provided, then best_clock P divider must match the P
 706  * divider from @match_clock used for LVDS downclocking.
 707  */
 708 static bool
 709 i9xx_find_best_dpll(const struct intel_limit *limit,
 710                     struct intel_crtc_state *crtc_state,
 711                     int target, int refclk, struct dpll *match_clock,
 712                     struct dpll *best_clock)
 713 {
 714         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 715         struct dpll clock;
 716         int err = target;
 717
 718         memset(best_clock, 0, sizeof(*best_clock));
 719
 720         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 721
 722         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 723              clock.m1++) {
 724                 for (clock.m2 = limit->m2.min;
 725                      clock.m2 <= limit->m2.max; clock.m2++) {
 726                         if (clock.m2 >= clock.m1)
 727                                 break;
 728                         for (clock.n = limit->n.min;
 729                              clock.n <= limit->n.max; clock.n++) {
 730                                 for (clock.p1 = limit->p1.min;
 731                                         clock.p1 <= limit->p1.max; clock.p1++) {
 732                                         int this_err;
 733
 734                                         i9xx_calc_dpll_params(refclk, &clock);
 735                                         if (!intel_pll_is_valid(to_i915(dev),
 736                                                                 limit,
 737                                                                 &clock))
 738                                                 continue;
 739                                         if (match_clock &&
 740                                             clock.p != match_clock->p)
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err) {
 745                                                 *best_clock = clock;
 746                                                 err = this_err;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752
 753         return (err != target);
 754 }
 755
 756 /*
 757  * Returns a set of divisors for the desired target clock with the given
 758  * refclk, or FALSE.  The returned values represent the clock equation:
 759  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 760  *
 761  * Target and reference clocks are specified in kHz.
 762  *
 763  * If match_clock is provided, then best_clock P divider must match the P
 764  * divider from @match_clock used for LVDS downclocking.
 765  */
 766 static bool
 767 pnv_find_best_dpll(const struct intel_limit *limit,
 768                    struct intel_crtc_state *crtc_state,
 769                    int target, int refclk, struct dpll *match_clock,
 770                    struct dpll *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 773         struct dpll clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         pnv_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_pll_is_valid(to_i915(dev),
 792                                                                 limit,
 793                                                                 &clock))
 794                                                 continue;
 795                                         if (match_clock &&
 796                                             clock.p != match_clock->p)
 797                                                 continue;
 798
 799                                         this_err = abs(clock.dot - target);
 800                                         if (this_err < err) {
 801                                                 *best_clock = clock;
 802                                                 err = this_err;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return (err != target);
 810 }
 811
 812 /*
 813  * Returns a set of divisors for the desired target clock with the given
 814  * refclk, or FALSE.  The returned values represent the clock equation:
 815  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 816  *
 817  * Target and reference clocks are specified in kHz.
 818  *
 819  * If match_clock is provided, then best_clock P divider must match the P
 820  * divider from @match_clock used for LVDS downclocking.
 821  */
 822 static bool
 823 g4x_find_best_dpll(const struct intel_limit *limit,
 824                    struct intel_crtc_state *crtc_state,
 825                    int target, int refclk, struct dpll *match_clock,
 826                    struct dpll *best_clock)
 827 {
 828         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 829         struct dpll clock;
 830         int max_n;
 831         bool found = false;
 832         /* approximately equals target * 0.00585 */
 833         int err_most = (target >> 8) + (target >> 9);
 834
 835         memset(best_clock, 0, sizeof(*best_clock));
 836
 837         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 838
 839         max_n = limit->n.max;
 840         /* based on hardware requirement, prefer smaller n to precision */
 841         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 842                 /* based on hardware requirement, prefere larger m1,m2 */
 843                 for (clock.m1 = limit->m1.max;
 844                      clock.m1 >= limit->m1.min; clock.m1--) {
 845                         for (clock.m2 = limit->m2.max;
 846                              clock.m2 >= limit->m2.min; clock.m2--) {
 847                                 for (clock.p1 = limit->p1.max;
 848                                      clock.p1 >= limit->p1.min; clock.p1--) {
 849                                         int this_err;
 850
 851                                         i9xx_calc_dpll_params(refclk, &clock);
 852                                         if (!intel_pll_is_valid(to_i915(dev),
 853                                                                 limit,
 854                                                                 &clock))
 855                                                 continue;
 856
 857                                         this_err = abs(clock.dot - target);
 858                                         if (this_err < err_most) {
 859                                                 *best_clock = clock;
 860                                                 err_most = this_err;
 861                                                 max_n = clock.n;
 862                                                 found = true;
 863                                         }
 864                                 }
 865                         }
 866                 }
 867         }
 868         return found;
 869 }
 870
 871 /*
 872  * Check if the calculated PLL configuration is more optimal compared to the
 873  * best configuration and error found so far. Return the calculated error.
 874  */
 875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 876                                const struct dpll *calculated_clock,
 877                                const struct dpll *best_clock,
 878                                unsigned int best_error_ppm,
 879                                unsigned int *error_ppm)
 880 {
 881         /*
 882          * For CHV ignore the error and consider only the P value.
 883          * Prefer a bigger P value based on HW requirements.
 884          */
 885         if (IS_CHERRYVIEW(to_i915(dev))) {
 886                 *error_ppm = 0;
 887
 888                 return calculated_clock->p > best_clock->p;
 889         }
 890
 891         if (drm_WARN_ON_ONCE(dev, !target_freq))
 892                 return false;
 893
 894         *error_ppm = div_u64(1000000ULL *
 895                                 abs(target_freq - calculated_clock->dot),
 896                              target_freq);
 897         /*
 898          * Prefer a better P value over a better (smaller) error if the error
 899          * is small. Ensure this preference for future configurations too by
 900          * setting the error to 0.
 901          */
 902         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 903                 *error_ppm = 0;
 904
 905                 return true;
 906         }
 907
 908         return *error_ppm + 10 < best_error_ppm;
 909 }
 910
 911 /*
 912  * Returns a set of divisors for the desired target clock with the given
 913  * refclk, or FALSE.  The returned values represent the clock equation:
 914  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 915  */
 916 static bool
 917 vlv_find_best_dpll(const struct intel_limit *limit,
 918                    struct intel_crtc_state *crtc_state,
 919                    int target, int refclk, struct dpll *match_clock,
 920                    struct dpll *best_clock)
 921 {
 922         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 923         struct drm_device *dev = crtc->base.dev;
 924         struct dpll clock;
 925         unsigned int bestppm = 1000000;
 926         /* min update 19.2 MHz */
 927         int max_n = min(limit->n.max, refclk / 19200);
 928         bool found = false;
 929
 930         target *= 5; /* fast clock */
 931
 932         memset(best_clock, 0, sizeof(*best_clock));
 933
 934         /* based on hardware requirement, prefer smaller n to precision */
 935         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 936                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 937                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 938                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                                 clock.p = clock.p1 * clock.p2;
 940                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 941                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 942                                         unsigned int ppm;
 943
 944                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 945                                                                      refclk * clock.m1);
 946
 947                                         vlv_calc_dpll_params(refclk, &clock);
 948
 949                                         if (!intel_pll_is_valid(to_i915(dev),
 950                                                                 limit,
 951                                                                 &clock))
 952                                                 continue;
 953
 954                                         if (!vlv_PLL_is_optimal(dev, target,
 955                                                                 &clock,
 956                                                                 best_clock,
 957                                                                 bestppm, &ppm))
 958                                                 continue;
 959
 960                                         *best_clock = clock;
 961                                         bestppm = ppm;
 962                                         found = true;
 963                                 }
 964                         }
 965                 }
 966         }
 967
 968         return found;
 969 }
 970
 971 /*
 972  * Returns a set of divisors for the desired target clock with the given
 973  * refclk, or FALSE.  The returned values represent the clock equation:
 974  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 975  */
 976 static bool
 977 chv_find_best_dpll(const struct intel_limit *limit,
 978                    struct intel_crtc_state *crtc_state,
 979                    int target, int refclk, struct dpll *match_clock,
 980                    struct dpll *best_clock)
 981 {
 982         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 983         struct drm_device *dev = crtc->base.dev;
 984         unsigned int best_error_ppm;
 985         struct dpll clock;
 986         u64 m2;
 987         int found = false;
 988
 989         memset(best_clock, 0, sizeof(*best_clock));
 990         best_error_ppm = 1000000;
 991
 992         /*
 993          * Based on hardware doc, the n always set to 1, and m1 always
 994          * set to 2.  If requires to support 200Mhz refclk, we need to
 995          * revisit this because n may not 1 anymore.
 996          */
 997         clock.n = 1, clock.m1 = 2;
 998         target *= 5;    /* fast clock */
 999
1000         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001                 for (clock.p2 = limit->p2.p2_fast;
1002                                 clock.p2 >= limit->p2.p2_slow;
1003                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004                         unsigned int error_ppm;
1005
1006                         clock.p = clock.p1 * clock.p2;
1007
1008                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1009                                                    refclk * clock.m1);
1010
1011                         if (m2 > INT_MAX/clock.m1)
1012                                 continue;
1013
1014                         clock.m2 = m2;
1015
1016                         chv_calc_dpll_params(refclk, &clock);
1017
1018                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1019                                 continue;
1020
1021                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022                                                 best_error_ppm, &error_ppm))
1023                                 continue;
1024
1025                         *best_clock = clock;
1026                         best_error_ppm = error_ppm;
1027                         found = true;
1028                 }
1029         }
1030
1031         return found;
1032 }
1033
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035                         struct dpll *best_clock)
1036 {
1037         int refclk = 100000;
1038         const struct intel_limit *limit = &intel_limits_bxt;
1039
1040         return chv_find_best_dpll(limit, crtc_state,
1041                                   crtc_state->port_clock, refclk,
1042                                   NULL, best_clock);
1043 }
1044
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1046                                     enum pipe pipe)
1047 {
1048         i915_reg_t reg = PIPEDSL(pipe);
1049         u32 line1, line2;
1050         u32 line_mask;
1051
1052         if (IS_GEN(dev_priv, 2))
1053                 line_mask = DSL_LINEMASK_GEN2;
1054         else
1055                 line_mask = DSL_LINEMASK_GEN3;
1056
1057         line1 = intel_de_read(dev_priv, reg) & line_mask;
1058         msleep(5);
1059         line2 = intel_de_read(dev_priv, reg) & line_mask;
1060
1061         return line1 != line2;
1062 }
1063
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 {
1066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067         enum pipe pipe = crtc->pipe;
1068
1069         /* Wait for the display line to settle/start moving */
1070         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071                 drm_err(&dev_priv->drm,
1072                         "pipe %c scanline %s wait timed out\n",
1073                         pipe_name(pipe), onoff(state));
1074 }
1075
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1077 {
1078         wait_for_pipe_scanline_moving(crtc, false);
1079 }
1080
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1082 {
1083         wait_for_pipe_scanline_moving(crtc, true);
1084 }
1085
1086 static void
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1088 {
1089         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1091
1092         if (INTEL_GEN(dev_priv) >= 4) {
1093                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1095
1096                 /* Wait for the Pipe State to go off */
1097                 if (intel_de_wait_for_clear(dev_priv, reg,
1098                                             I965_PIPECONF_ACTIVE, 100))
1099                         drm_WARN(&dev_priv->drm, 1,
1100                                  "pipe_off wait timed out\n");
1101         } else {
1102                 intel_wait_for_pipe_scanline_stopped(crtc);
1103         }
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108                 enum pipe pipe, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         val = intel_de_read(dev_priv, DPLL(pipe));
1114         cur_state = !!(val & DPLL_VCO_ENABLE);
1115         I915_STATE_WARN(cur_state != state,
1116              "PLL state assertion failure (expected %s, current %s)\n",
1117                         onoff(state), onoff(cur_state));
1118 }
1119
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1122 {
1123         u32 val;
1124         bool cur_state;
1125
1126         vlv_cck_get(dev_priv);
1127         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128         vlv_cck_put(dev_priv);
1129
1130         cur_state = val & DSI_PLL_VCO_EN;
1131         I915_STATE_WARN(cur_state != state,
1132              "DSI PLL state assertion failure (expected %s, current %s)\n",
1133                         onoff(state), onoff(cur_state));
1134 }
1135
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137                           enum pipe pipe, bool state)
1138 {
1139         bool cur_state;
1140
1141         if (HAS_DDI(dev_priv)) {
1142                 /*
1143                  * DDI does not have a specific FDI_TX register.
1144                  *
1145                  * FDI is never fed from EDP transcoder
1146                  * so pipe->transcoder cast is fine here.
1147                  */
1148                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149                 u32 val = intel_de_read(dev_priv,
1150                                         TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1152         } else {
1153                 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154                 cur_state = !!(val & FDI_TX_ENABLE);
1155         }
1156         I915_STATE_WARN(cur_state != state,
1157              "FDI TX state assertion failure (expected %s, current %s)\n",
1158                         onoff(state), onoff(cur_state));
1159 }
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1162
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         u32 val;
1167         bool cur_state;
1168
1169         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170         cur_state = !!(val & FDI_RX_ENABLE);
1171         I915_STATE_WARN(cur_state != state,
1172              "FDI RX state assertion failure (expected %s, current %s)\n",
1173                         onoff(state), onoff(cur_state));
1174 }
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1177
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1179                                       enum pipe pipe)
1180 {
1181         u32 val;
1182
1183         /* ILK FDI PLL is always enabled */
1184         if (IS_GEN(dev_priv, 5))
1185                 return;
1186
1187         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188         if (HAS_DDI(dev_priv))
1189                 return;
1190
1191         val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1193 }
1194
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196                        enum pipe pipe, bool state)
1197 {
1198         u32 val;
1199         bool cur_state;
1200
1201         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203         I915_STATE_WARN(cur_state != state,
1204              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205                         onoff(state), onoff(cur_state));
1206 }
1207
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1209 {
1210         i915_reg_t pp_reg;
1211         u32 val;
1212         enum pipe panel_pipe = INVALID_PIPE;
1213         bool locked = true;
1214
1215         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1216                 return;
1217
1218         if (HAS_PCH_SPLIT(dev_priv)) {
1219                 u32 port_sel;
1220
1221                 pp_reg = PP_CONTROL(0);
1222                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1223
1224                 switch (port_sel) {
1225                 case PANEL_PORT_SELECT_LVDS:
1226                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPA:
1229                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPC:
1232                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1233                         break;
1234                 case PANEL_PORT_SELECT_DPD:
1235                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1236                         break;
1237                 default:
1238                         MISSING_CASE(port_sel);
1239                         break;
1240                 }
1241         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242                 /* presumably write lock depends on pipe, not port select */
1243                 pp_reg = PP_CONTROL(pipe);
1244                 panel_pipe = pipe;
1245         } else {
1246                 u32 port_sel;
1247
1248                 pp_reg = PP_CONTROL(0);
1249                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1250
1251                 drm_WARN_ON(&dev_priv->drm,
1252                             port_sel != PANEL_PORT_SELECT_LVDS);
1253                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1254         }
1255
1256         val = intel_de_read(dev_priv, pp_reg);
1257         if (!(val & PANEL_POWER_ON) ||
1258             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1259                 locked = false;
1260
1261         I915_STATE_WARN(panel_pipe == pipe && locked,
1262              "panel assertion failure, pipe %c regs locked\n",
1263              pipe_name(pipe));
1264 }
1265
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267                  enum transcoder cpu_transcoder, bool state)
1268 {
1269         bool cur_state;
1270         enum intel_display_power_domain power_domain;
1271         intel_wakeref_t wakeref;
1272
1273         /* we keep both pipes enabled on 830 */
1274         if (IS_I830(dev_priv))
1275                 state = true;
1276
1277         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1279         if (wakeref) {
1280                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281                 cur_state = !!(val & PIPECONF_ENABLE);
1282
1283                 intel_display_power_put(dev_priv, power_domain, wakeref);
1284         } else {
1285                 cur_state = false;
1286         }
1287
1288         I915_STATE_WARN(cur_state != state,
1289                         "transcoder %s assertion failure (expected %s, current %s)\n",
1290                         transcoder_name(cpu_transcoder),
1291                         onoff(state), onoff(cur_state));
1292 }
1293
1294 static void assert_plane(struct intel_plane *plane, bool state)
1295 {
1296         enum pipe pipe;
1297         bool cur_state;
1298
1299         cur_state = plane->get_hw_state(plane, &pipe);
1300
1301         I915_STATE_WARN(cur_state != state,
1302                         "%s assertion failure (expected %s, current %s)\n",
1303                         plane->base.name, onoff(state), onoff(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1308
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1310 {
1311         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312         struct intel_plane *plane;
1313
1314         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315                 assert_plane_disabled(plane);
1316 }
1317
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1319 {
1320         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321                 drm_crtc_vblank_put(crtc);
1322 }
1323
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1325                                     enum pipe pipe)
1326 {
1327         u32 val;
1328         bool enabled;
1329
1330         val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331         enabled = !!(val & TRANS_ENABLE);
1332         I915_STATE_WARN(enabled,
1333              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1334              pipe_name(pipe));
1335 }
1336
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338                                    enum pipe pipe, enum port port,
1339                                    i915_reg_t dp_reg)
1340 {
1341         enum pipe port_pipe;
1342         bool state;
1343
1344         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1345
1346         I915_STATE_WARN(state && port_pipe == pipe,
1347                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348                         port_name(port), pipe_name(pipe));
1349
1350         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351                         "IBX PCH DP %c still using transcoder B\n",
1352                         port_name(port));
1353 }
1354
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356                                      enum pipe pipe, enum port port,
1357                                      i915_reg_t hdmi_reg)
1358 {
1359         enum pipe port_pipe;
1360         bool state;
1361
1362         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1363
1364         I915_STATE_WARN(state && port_pipe == pipe,
1365                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366                         port_name(port), pipe_name(pipe));
1367
1368         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369                         "IBX PCH HDMI %c still using transcoder B\n",
1370                         port_name(port));
1371 }
1372
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1374                                       enum pipe pipe)
1375 {
1376         enum pipe port_pipe;
1377
1378         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1381
1382         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1383                         port_pipe == pipe,
1384                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1385                         pipe_name(pipe));
1386
1387         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1388                         port_pipe == pipe,
1389                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1390                         pipe_name(pipe));
1391
1392         /* PCH SDVOB multiplex with HDMIB */
1393         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1396 }
1397
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399                             const struct intel_crtc_state *pipe_config)
1400 {
1401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402         enum pipe pipe = crtc->pipe;
1403
1404         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405         intel_de_posting_read(dev_priv, DPLL(pipe));
1406         udelay(150);
1407
1408         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1410 }
1411
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413                            const struct intel_crtc_state *pipe_config)
1414 {
1415         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416         enum pipe pipe = crtc->pipe;
1417
1418         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1419
1420         /* PLL is protected by panel, make sure we can write it */
1421         assert_panel_unlocked(dev_priv, pipe);
1422
1423         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424                 _vlv_enable_pll(crtc, pipe_config);
1425
1426         intel_de_write(dev_priv, DPLL_MD(pipe),
1427                        pipe_config->dpll_hw_state.dpll_md);
1428         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1429 }
1430
1431
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433                             const struct intel_crtc_state *pipe_config)
1434 {
1435         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436         enum pipe pipe = crtc->pipe;
1437         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1438         u32 tmp;
1439
1440         vlv_dpio_get(dev_priv);
1441
1442         /* Enable back the 10bit clock to display controller */
1443         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444         tmp |= DPIO_DCLKP_EN;
1445         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1446
1447         vlv_dpio_put(dev_priv);
1448
1449         /*
1450          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1451          */
1452         udelay(1);
1453
1454         /* Enable PLL */
1455         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1456
1457         /* Check PLL is locked */
1458         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1460 }
1461
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463                            const struct intel_crtc_state *pipe_config)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466         enum pipe pipe = crtc->pipe;
1467
1468         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         assert_panel_unlocked(dev_priv, pipe);
1472
1473         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474                 _chv_enable_pll(crtc, pipe_config);
1475
1476         if (pipe != PIPE_A) {
1477                 /*
1478                  * WaPixelRepeatModeFixForC0:chv
1479                  *
1480                  * DPLLCMD is AWOL. Use chicken bits to propagate
1481                  * the value from DPLLBMD to either pipe B or C.
1482                  */
1483                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485                                pipe_config->dpll_hw_state.dpll_md);
1486                 intel_de_write(dev_priv, CBR4_VLV, 0);
1487                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1488
1489                 /*
1490                  * DPLLB VGA mode also seems to cause problems.
1491                  * We should always have it disabled.
1492                  */
1493                 drm_WARN_ON(&dev_priv->drm,
1494                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495                              DPLL_VGA_MODE_DIS) == 0);
1496         } else {
1497                 intel_de_write(dev_priv, DPLL_MD(pipe),
1498                                pipe_config->dpll_hw_state.dpll_md);
1499                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1500         }
1501 }
1502
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1504 {
1505         if (IS_I830(dev_priv))
1506                 return false;
1507
1508         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1509 }
1510
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512                             const struct intel_crtc_state *crtc_state)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         i915_reg_t reg = DPLL(crtc->pipe);
1516         u32 dpll = crtc_state->dpll_hw_state.dpll;
1517         int i;
1518
1519         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1520
1521         /* PLL is protected by panel, make sure we can write it */
1522         if (i9xx_has_pps(dev_priv))
1523                 assert_panel_unlocked(dev_priv, crtc->pipe);
1524
1525         /*
1526          * Apparently we need to have VGA mode enabled prior to changing
1527          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528          * dividers, even though the register value does change.
1529          */
1530         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531         intel_de_write(dev_priv, reg, dpll);
1532
1533         /* Wait for the clocks to stabilize. */
1534         intel_de_posting_read(dev_priv, reg);
1535         udelay(150);
1536
1537         if (INTEL_GEN(dev_priv) >= 4) {
1538                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539                                crtc_state->dpll_hw_state.dpll_md);
1540         } else {
1541                 /* The pixel multiplier can only be updated once the
1542                  * DPLL is enabled and the clocks are stable.
1543                  *
1544                  * So write it again.
1545                  */
1546                 intel_de_write(dev_priv, reg, dpll);
1547         }
1548
1549         /* We do this three times for luck */
1550         for (i = 0; i < 3; i++) {
1551                 intel_de_write(dev_priv, reg, dpll);
1552                 intel_de_posting_read(dev_priv, reg);
1553                 udelay(150); /* wait for warmup */
1554         }
1555 }
1556
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1558 {
1559         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562
1563         /* Don't disable pipe or pipe PLLs if needed */
1564         if (IS_I830(dev_priv))
1565                 return;
1566
1567         /* Make sure the pipe isn't still relying on us */
1568         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1569
1570         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571         intel_de_posting_read(dev_priv, DPLL(pipe));
1572 }
1573
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         /* Make sure the pipe isn't still relying on us */
1579         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1580
1581         val = DPLL_INTEGRATED_REF_CLK_VLV |
1582                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1583         if (pipe != PIPE_A)
1584                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1585
1586         intel_de_write(dev_priv, DPLL(pipe), val);
1587         intel_de_posting_read(dev_priv, DPLL(pipe));
1588 }
1589
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1591 {
1592         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1593         u32 val;
1594
1595         /* Make sure the pipe isn't still relying on us */
1596         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1597
1598         val = DPLL_SSC_REF_CLK_CHV |
1599                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1600         if (pipe != PIPE_A)
1601                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1602
1603         intel_de_write(dev_priv, DPLL(pipe), val);
1604         intel_de_posting_read(dev_priv, DPLL(pipe));
1605
1606         vlv_dpio_get(dev_priv);
1607
1608         /* Disable 10bit clock to display controller */
1609         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610         val &= ~DPIO_DCLKP_EN;
1611         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1612
1613         vlv_dpio_put(dev_priv);
1614 }
1615
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617                          struct intel_digital_port *dig_port,
1618                          unsigned int expected_mask)
1619 {
1620         u32 port_mask;
1621         i915_reg_t dpll_reg;
1622
1623         switch (dig_port->base.port) {
1624         case PORT_B:
1625                 port_mask = DPLL_PORTB_READY_MASK;
1626                 dpll_reg = DPLL(0);
1627                 break;
1628         case PORT_C:
1629                 port_mask = DPLL_PORTC_READY_MASK;
1630                 dpll_reg = DPLL(0);
1631                 expected_mask <<= 4;
1632                 break;
1633         case PORT_D:
1634                 port_mask = DPLL_PORTD_READY_MASK;
1635                 dpll_reg = DPIO_PHY_STATUS;
1636                 break;
1637         default:
1638                 BUG();
1639         }
1640
1641         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642                                        port_mask, expected_mask, 1000))
1643                 drm_WARN(&dev_priv->drm, 1,
1644                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645                          dig_port->base.base.base.id, dig_port->base.base.name,
1646                          intel_de_read(dev_priv, dpll_reg) & port_mask,
1647                          expected_mask);
1648 }
1649
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1651 {
1652         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654         enum pipe pipe = crtc->pipe;
1655         i915_reg_t reg;
1656         u32 val, pipeconf_val;
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (HAS_PCH_CPT(dev_priv)) {
1666                 reg = TRANS_CHICKEN2(pipe);
1667                 val = intel_de_read(dev_priv, reg);
1668                 /*
1669                  * Workaround: Set the timing override bit
1670                  * before enabling the pch transcoder.
1671                  */
1672                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673                 /* Configure frame start delay to match the CPU */
1674                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676                 intel_de_write(dev_priv, reg, val);
1677         }
1678
1679         reg = PCH_TRANSCONF(pipe);
1680         val = intel_de_read(dev_priv, reg);
1681         pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1682
1683         if (HAS_PCH_IBX(dev_priv)) {
1684                 /* Configure frame start delay to match the CPU */
1685                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686                 val |= TRANS_FRAME_START_DELAY(0);
1687
1688                 /*
1689                  * Make the BPC in transcoder be consistent with
1690                  * that in pipeconf reg. For HDMI we must use 8bpc
1691                  * here for both 8bpc and 12bpc.
1692                  */
1693                 val &= ~PIPECONF_BPC_MASK;
1694                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695                         val |= PIPECONF_8BPC;
1696                 else
1697                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1698         }
1699
1700         val &= ~TRANS_INTERLACE_MASK;
1701         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702                 if (HAS_PCH_IBX(dev_priv) &&
1703                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704                         val |= TRANS_LEGACY_INTERLACED_ILK;
1705                 else
1706                         val |= TRANS_INTERLACED;
1707         } else {
1708                 val |= TRANS_PROGRESSIVE;
1709         }
1710
1711         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1714                         pipe_name(pipe));
1715 }
1716
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718                                       enum transcoder cpu_transcoder)
1719 {
1720         u32 val, pipeconf_val;
1721
1722         /* FDI must be feeding us bits for PCH ports */
1723         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1725
1726         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727         /* Workaround: set timing override bit. */
1728         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729         /* Configure frame start delay to match the CPU */
1730         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1733
1734         val = TRANS_ENABLE;
1735         pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1736
1737         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738             PIPECONF_INTERLACED_ILK)
1739                 val |= TRANS_INTERLACED;
1740         else
1741                 val |= TRANS_PROGRESSIVE;
1742
1743         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745                                   TRANS_STATE_ENABLE, 100))
1746                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                        enum pipe pipe)
1751 {
1752         i915_reg_t reg;
1753         u32 val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = PCH_TRANSCONF(pipe);
1763         val = intel_de_read(dev_priv, reg);
1764         val &= ~TRANS_ENABLE;
1765         intel_de_write(dev_priv, reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1769                         pipe_name(pipe));
1770
1771         if (HAS_PCH_CPT(dev_priv)) {
1772                 /* Workaround: Clear the timing override chicken bit again. */
1773                 reg = TRANS_CHICKEN2(pipe);
1774                 val = intel_de_read(dev_priv, reg);
1775                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776                 intel_de_write(dev_priv, reg, val);
1777         }
1778 }
1779
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1781 {
1782         u32 val;
1783
1784         val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785         val &= ~TRANS_ENABLE;
1786         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787         /* wait for PCH transcoder off, transcoder state */
1788         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789                                     TRANS_STATE_ENABLE, 50))
1790                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1791
1792         /* Workaround: clear timing override bit. */
1793         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1796 }
1797
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1799 {
1800         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1801
1802         if (HAS_PCH_LPT(dev_priv))
1803                 return PIPE_A;
1804         else
1805                 return crtc->pipe;
1806 }
1807
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1809 {
1810         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811
1812         /*
1813          * On i965gm the hardware frame counter reads
1814          * zero when the TV encoder is enabled :(
1815          */
1816         if (IS_I965GM(dev_priv) &&
1817             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1818                 return 0;
1819
1820         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1821                 return 0xffffffff; /* full 32 bit counter */
1822         else if (INTEL_GEN(dev_priv) >= 3)
1823                 return 0xffffff; /* only 24 bits of frame count */
1824         else
1825                 return 0; /* Gen2 doesn't have a hardware frame counter */
1826 }
1827
1828 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1829 {
1830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831
1832         assert_vblank_disabled(&crtc->base);
1833         drm_crtc_set_max_vblank_count(&crtc->base,
1834                                       intel_crtc_max_vblank_count(crtc_state));
1835         drm_crtc_vblank_on(&crtc->base);
1836 }
1837
1838 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841
1842         drm_crtc_vblank_off(&crtc->base);
1843         assert_vblank_disabled(&crtc->base);
1844 }
1845
1846 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1847 {
1848         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1851         enum pipe pipe = crtc->pipe;
1852         i915_reg_t reg;
1853         u32 val;
1854
1855         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1856
1857         assert_planes_disabled(crtc);
1858
1859         /*
1860          * A pipe without a PLL won't actually be able to drive bits from
1861          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1862          * need the check.
1863          */
1864         if (HAS_GMCH(dev_priv)) {
1865                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1866                         assert_dsi_pll_enabled(dev_priv);
1867                 else
1868                         assert_pll_enabled(dev_priv, pipe);
1869         } else {
1870                 if (new_crtc_state->has_pch_encoder) {
1871                         /* if driving the PCH, we need FDI enabled */
1872                         assert_fdi_rx_pll_enabled(dev_priv,
1873                                                   intel_crtc_pch_transcoder(crtc));
1874                         assert_fdi_tx_pll_enabled(dev_priv,
1875                                                   (enum pipe) cpu_transcoder);
1876                 }
1877                 /* FIXME: assert CPU port conditions for SNB+ */
1878         }
1879
1880         trace_intel_pipe_enable(crtc);
1881
1882         reg = PIPECONF(cpu_transcoder);
1883         val = intel_de_read(dev_priv, reg);
1884         if (val & PIPECONF_ENABLE) {
1885                 /* we keep both pipes enabled on 830 */
1886                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1887                 return;
1888         }
1889
1890         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1891         intel_de_posting_read(dev_priv, reg);
1892
1893         /*
1894          * Until the pipe starts PIPEDSL reads will return a stale value,
1895          * which causes an apparent vblank timestamp jump when PIPEDSL
1896          * resets to its proper value. That also messes up the frame count
1897          * when it's derived from the timestamps. So let's wait for the
1898          * pipe to start properly before we call drm_crtc_vblank_on()
1899          */
1900         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1901                 intel_wait_for_pipe_scanline_moving(crtc);
1902 }
1903
1904 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1905 {
1906         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1907         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1908         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1909         enum pipe pipe = crtc->pipe;
1910         i915_reg_t reg;
1911         u32 val;
1912
1913         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1914
1915         /*
1916          * Make sure planes won't keep trying to pump pixels to us,
1917          * or we might hang the display.
1918          */
1919         assert_planes_disabled(crtc);
1920
1921         trace_intel_pipe_disable(crtc);
1922
1923         reg = PIPECONF(cpu_transcoder);
1924         val = intel_de_read(dev_priv, reg);
1925         if ((val & PIPECONF_ENABLE) == 0)
1926                 return;
1927
1928         /*
1929          * Double wide has implications for planes
1930          * so best keep it disabled when not needed.
1931          */
1932         if (old_crtc_state->double_wide)
1933                 val &= ~PIPECONF_DOUBLE_WIDE;
1934
1935         /* Don't disable pipe or pipe PLLs if needed */
1936         if (!IS_I830(dev_priv))
1937                 val &= ~PIPECONF_ENABLE;
1938
1939         intel_de_write(dev_priv, reg, val);
1940         if ((val & PIPECONF_ENABLE) == 0)
1941                 intel_wait_for_pipe_off(old_crtc_state);
1942 }
1943
1944 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1945 {
1946         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1947 }
1948
1949 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1950 {
1951         if (!is_ccs_modifier(fb->modifier))
1952                 return false;
1953
1954         return plane >= fb->format->num_planes / 2;
1955 }
1956
1957 static bool is_gen12_ccs_modifier(u64 modifier)
1958 {
1959         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1960                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1961
1962 }
1963
1964 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1965 {
1966         return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1967 }
1968
1969 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1970 {
1971         if (is_ccs_modifier(fb->modifier))
1972                 return is_ccs_plane(fb, plane);
1973
1974         return plane == 1;
1975 }
1976
1977 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1978 {
1979         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1980                     (main_plane && main_plane >= fb->format->num_planes / 2));
1981
1982         return fb->format->num_planes / 2 + main_plane;
1983 }
1984
1985 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1986 {
1987         drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1988                     ccs_plane < fb->format->num_planes / 2);
1989
1990         return ccs_plane - fb->format->num_planes / 2;
1991 }
1992
1993 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1994 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1995 {
1996         if (is_ccs_modifier(fb->modifier))
1997                 return main_to_ccs_plane(fb, main_plane);
1998
1999         return 1;
2000 }
2001
2002 bool
2003 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2004                                     uint64_t modifier)
2005 {
2006         return info->is_yuv &&
2007                info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2008 }
2009
2010 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2011                                    int color_plane)
2012 {
2013         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2014                color_plane == 1;
2015 }
2016
2017 static unsigned int
2018 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2019 {
2020         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2021         unsigned int cpp = fb->format->cpp[color_plane];
2022
2023         switch (fb->modifier) {
2024         case DRM_FORMAT_MOD_LINEAR:
2025                 return intel_tile_size(dev_priv);
2026         case I915_FORMAT_MOD_X_TILED:
2027                 if (IS_GEN(dev_priv, 2))
2028                         return 128;
2029                 else
2030                         return 512;
2031         case I915_FORMAT_MOD_Y_TILED_CCS:
2032                 if (is_ccs_plane(fb, color_plane))
2033                         return 128;
2034                 fallthrough;
2035         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2036         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2037                 if (is_ccs_plane(fb, color_plane))
2038                         return 64;
2039                 fallthrough;
2040         case I915_FORMAT_MOD_Y_TILED:
2041                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2042                         return 128;
2043                 else
2044                         return 512;
2045         case I915_FORMAT_MOD_Yf_TILED_CCS:
2046                 if (is_ccs_plane(fb, color_plane))
2047                         return 128;
2048                 fallthrough;
2049         case I915_FORMAT_MOD_Yf_TILED:
2050                 switch (cpp) {
2051                 case 1:
2052                         return 64;
2053                 case 2:
2054                 case 4:
2055                         return 128;
2056                 case 8:
2057                 case 16:
2058                         return 256;
2059                 default:
2060                         MISSING_CASE(cpp);
2061                         return cpp;
2062                 }
2063                 break;
2064         default:
2065                 MISSING_CASE(fb->modifier);
2066                 return cpp;
2067         }
2068 }
2069
2070 static unsigned int
2071 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2072 {
2073         if (is_gen12_ccs_plane(fb, color_plane))
2074                 return 1;
2075
2076         return intel_tile_size(to_i915(fb->dev)) /
2077                 intel_tile_width_bytes(fb, color_plane);
2078 }
2079
2080 /* Return the tile dimensions in pixel units */
2081 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2082                             unsigned int *tile_width,
2083                             unsigned int *tile_height)
2084 {
2085         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2086         unsigned int cpp = fb->format->cpp[color_plane];
2087
2088         *tile_width = tile_width_bytes / cpp;
2089         *tile_height = intel_tile_height(fb, color_plane);
2090 }
2091
2092 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2093                                         int color_plane)
2094 {
2095         unsigned int tile_width, tile_height;
2096
2097         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2098
2099         return fb->pitches[color_plane] * tile_height;
2100 }
2101
2102 unsigned int
2103 intel_fb_align_height(const struct drm_framebuffer *fb,
2104                       int color_plane, unsigned int height)
2105 {
2106         unsigned int tile_height = intel_tile_height(fb, color_plane);
2107
2108         return ALIGN(height, tile_height);
2109 }
2110
2111 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2112 {
2113         unsigned int size = 0;
2114         int i;
2115
2116         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2117                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2118
2119         return size;
2120 }
2121
2122 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2123 {
2124         unsigned int size = 0;
2125         int i;
2126
2127         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2128                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2129
2130         return size;
2131 }
2132
2133 static void
2134 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2135                         const struct drm_framebuffer *fb,
2136                         unsigned int rotation)
2137 {
2138         view->type = I915_GGTT_VIEW_NORMAL;
2139         if (drm_rotation_90_or_270(rotation)) {
2140                 view->type = I915_GGTT_VIEW_ROTATED;
2141                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2142         }
2143 }
2144
2145 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2146 {
2147         if (IS_I830(dev_priv))
2148                 return 16 * 1024;
2149         else if (IS_I85X(dev_priv))
2150                 return 256;
2151         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2152                 return 32;
2153         else
2154                 return 4 * 1024;
2155 }
2156
2157 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2158 {
2159         if (INTEL_GEN(dev_priv) >= 9)
2160                 return 256 * 1024;
2161         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2162                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2163                 return 128 * 1024;
2164         else if (INTEL_GEN(dev_priv) >= 4)
2165                 return 4 * 1024;
2166         else
2167                 return 0;
2168 }
2169
2170 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2171                                          int color_plane)
2172 {
2173         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2174
2175         /* AUX_DIST needs only 4K alignment */
2176         if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2177             is_ccs_plane(fb, color_plane))
2178                 return 4096;
2179
2180         switch (fb->modifier) {
2181         case DRM_FORMAT_MOD_LINEAR:
2182                 return intel_linear_alignment(dev_priv);
2183         case I915_FORMAT_MOD_X_TILED:
2184                 if (INTEL_GEN(dev_priv) >= 9)
2185                         return 256 * 1024;
2186                 return 0;
2187         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2188                 if (is_semiplanar_uv_plane(fb, color_plane))
2189                         return intel_tile_row_size(fb, color_plane);
2190                 fallthrough;
2191         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2192                 return 16 * 1024;
2193         case I915_FORMAT_MOD_Y_TILED_CCS:
2194         case I915_FORMAT_MOD_Yf_TILED_CCS:
2195         case I915_FORMAT_MOD_Y_TILED:
2196                 if (INTEL_GEN(dev_priv) >= 12 &&
2197                     is_semiplanar_uv_plane(fb, color_plane))
2198                         return intel_tile_row_size(fb, color_plane);
2199                 fallthrough;
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb->modifier);
2204                 return 0;
2205         }
2206 }
2207
2208 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2209 {
2210         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2211         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2212
2213         return INTEL_GEN(dev_priv) < 4 ||
2214                 (plane->has_fbc &&
2215                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2216 }
2217
2218 struct i915_vma *
2219 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2220                            const struct i915_ggtt_view *view,
2221                            bool uses_fence,
2222                            unsigned long *out_flags)
2223 {
2224         struct drm_device *dev = fb->dev;
2225         struct drm_i915_private *dev_priv = to_i915(dev);
2226         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2227         intel_wakeref_t wakeref;
2228         struct i915_vma *vma;
2229         unsigned int pinctl;
2230         u32 alignment;
2231
2232         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2233                 return ERR_PTR(-EINVAL);
2234
2235         alignment = intel_surf_alignment(fb, 0);
2236         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2237                 return ERR_PTR(-EINVAL);
2238
2239         /* Note that the w/a also requires 64 PTE of padding following the
2240          * bo. We currently fill all unused PTE with the shadow page and so
2241          * we should always have valid PTE following the scanout preventing
2242          * the VT-d warning.
2243          */
2244         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2245                 alignment = 256 * 1024;
2246
2247         /*
2248          * Global gtt pte registers are special registers which actually forward
2249          * writes to a chunk of system memory. Which means that there is no risk
2250          * that the register values disappear as soon as we call
2251          * intel_runtime_pm_put(), so it is correct to wrap only the
2252          * pin/unpin/fence and not more.
2253          */
2254         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2255
2256         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2257
2258         /*
2259          * Valleyview is definitely limited to scanning out the first
2260          * 512MiB. Lets presume this behaviour was inherited from the
2261          * g4x display engine and that all earlier gen are similarly
2262          * limited. Testing suggests that it is a little more
2263          * complicated than this. For example, Cherryview appears quite
2264          * happy to scanout from anywhere within its global aperture.
2265          */
2266         pinctl = 0;
2267         if (HAS_GMCH(dev_priv))
2268                 pinctl |= PIN_MAPPABLE;
2269
2270         vma = i915_gem_object_pin_to_display_plane(obj,
2271                                                    alignment, view, pinctl);
2272         if (IS_ERR(vma))
2273                 goto err;
2274
2275         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2276                 int ret;
2277
2278                 /*
2279                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2280                  * fence, whereas 965+ only requires a fence if using
2281                  * framebuffer compression.  For simplicity, we always, when
2282                  * possible, install a fence as the cost is not that onerous.
2283                  *
2284                  * If we fail to fence the tiled scanout, then either the
2285                  * modeset will reject the change (which is highly unlikely as
2286                  * the affected systems, all but one, do not have unmappable
2287                  * space) or we will not be able to enable full powersaving
2288                  * techniques (also likely not to apply due to various limits
2289                  * FBC and the like impose on the size of the buffer, which
2290                  * presumably we violated anyway with this unmappable buffer).
2291                  * Anyway, it is presumably better to stumble onwards with
2292                  * something and try to run the system in a "less than optimal"
2293                  * mode that matches the user configuration.
2294                  */
2295                 ret = i915_vma_pin_fence(vma);
2296                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2297                         i915_gem_object_unpin_from_display_plane(vma);
2298                         vma = ERR_PTR(ret);
2299                         goto err;
2300                 }
2301
2302                 if (ret == 0 && vma->fence)
2303                         *out_flags |= PLANE_HAS_FENCE;
2304         }
2305
2306         i915_vma_get(vma);
2307 err:
2308         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2309         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2310         return vma;
2311 }
2312
2313 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2314 {
2315         i915_gem_object_lock(vma->obj, NULL);
2316         if (flags & PLANE_HAS_FENCE)
2317                 i915_vma_unpin_fence(vma);
2318         i915_gem_object_unpin_from_display_plane(vma);
2319         i915_gem_object_unlock(vma->obj);
2320
2321         i915_vma_put(vma);
2322 }
2323
2324 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2325                           unsigned int rotation)
2326 {
2327         if (drm_rotation_90_or_270(rotation))
2328                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2329         else
2330                 return fb->pitches[color_plane];
2331 }
2332
2333 /*
2334  * Convert the x/y offsets into a linear offset.
2335  * Only valid with 0/180 degree rotation, which is fine since linear
2336  * offset is only used with linear buffers on pre-hsw and tiled buffers
2337  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2338  */
2339 u32 intel_fb_xy_to_linear(int x, int y,
2340                           const struct intel_plane_state *state,
2341                           int color_plane)
2342 {
2343         const struct drm_framebuffer *fb = state->hw.fb;
2344         unsigned int cpp = fb->format->cpp[color_plane];
2345         unsigned int pitch = state->color_plane[color_plane].stride;
2346
2347         return y * pitch + x * cpp;
2348 }
2349
2350 /*
2351  * Add the x/y offsets derived from fb->offsets[] to the user
2352  * specified plane src x/y offsets. The resulting x/y offsets
2353  * specify the start of scanout from the beginning of the gtt mapping.
2354  */
2355 void intel_add_fb_offsets(int *x, int *y,
2356                           const struct intel_plane_state *state,
2357                           int color_plane)
2358
2359 {
2360         *x += state->color_plane[color_plane].x;
2361         *y += state->color_plane[color_plane].y;
2362 }
2363
2364 static u32 intel_adjust_tile_offset(int *x, int *y,
2365                                     unsigned int tile_width,
2366                                     unsigned int tile_height,
2367                                     unsigned int tile_size,
2368                                     unsigned int pitch_tiles,
2369                                     u32 old_offset,
2370                                     u32 new_offset)
2371 {
2372         unsigned int pitch_pixels = pitch_tiles * tile_width;
2373         unsigned int tiles;
2374
2375         WARN_ON(old_offset & (tile_size - 1));
2376         WARN_ON(new_offset & (tile_size - 1));
2377         WARN_ON(new_offset > old_offset);
2378
2379         tiles = (old_offset - new_offset) / tile_size;
2380
2381         *y += tiles / pitch_tiles * tile_height;
2382         *x += tiles % pitch_tiles * tile_width;
2383
2384         /* minimize x in case it got needlessly big */
2385         *y += *x / pitch_pixels * tile_height;
2386         *x %= pitch_pixels;
2387
2388         return new_offset;
2389 }
2390
2391 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2392 {
2393         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2394                is_gen12_ccs_plane(fb, color_plane);
2395 }
2396
2397 static u32 intel_adjust_aligned_offset(int *x, int *y,
2398                                        const struct drm_framebuffer *fb,
2399                                        int color_plane,
2400                                        unsigned int rotation,
2401                                        unsigned int pitch,
2402                                        u32 old_offset, u32 new_offset)
2403 {
2404         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2405         unsigned int cpp = fb->format->cpp[color_plane];
2406
2407         drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2408
2409         if (!is_surface_linear(fb, color_plane)) {
2410                 unsigned int tile_size, tile_width, tile_height;
2411                 unsigned int pitch_tiles;
2412
2413                 tile_size = intel_tile_size(dev_priv);
2414                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2415
2416                 if (drm_rotation_90_or_270(rotation)) {
2417                         pitch_tiles = pitch / tile_height;
2418                         swap(tile_width, tile_height);
2419                 } else {
2420                         pitch_tiles = pitch / (tile_width * cpp);
2421                 }
2422
2423                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2424                                          tile_size, pitch_tiles,
2425                                          old_offset, new_offset);
2426         } else {
2427                 old_offset += *y * pitch + *x * cpp;
2428
2429                 *y = (old_offset - new_offset) / pitch;
2430                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2431         }
2432
2433         return new_offset;
2434 }
2435
2436 /*
2437  * Adjust the tile offset by moving the difference into
2438  * the x/y offsets.
2439  */
2440 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2441                                              const struct intel_plane_state *state,
2442                                              int color_plane,
2443                                              u32 old_offset, u32 new_offset)
2444 {
2445         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2446                                            state->hw.rotation,
2447                                            state->color_plane[color_plane].stride,
2448                                            old_offset, new_offset);
2449 }
2450
2451 /*
2452  * Computes the aligned offset to the base tile and adjusts
2453  * x, y. bytes per pixel is assumed to be a power-of-two.
2454  *
2455  * In the 90/270 rotated case, x and y are assumed
2456  * to be already rotated to match the rotated GTT view, and
2457  * pitch is the tile_height aligned framebuffer height.
2458  *
2459  * This function is used when computing the derived information
2460  * under intel_framebuffer, so using any of that information
2461  * here is not allowed. Anything under drm_framebuffer can be
2462  * used. This is why the user has to pass in the pitch since it
2463  * is specified in the rotated orientation.
2464  */
2465 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2466                                         int *x, int *y,
2467                                         const struct drm_framebuffer *fb,
2468                                         int color_plane,
2469                                         unsigned int pitch,
2470                                         unsigned int rotation,
2471                                         u32 alignment)
2472 {
2473         unsigned int cpp = fb->format->cpp[color_plane];
2474         u32 offset, offset_aligned;
2475
2476         if (!is_surface_linear(fb, color_plane)) {
2477                 unsigned int tile_size, tile_width, tile_height;
2478                 unsigned int tile_rows, tiles, pitch_tiles;
2479
2480                 tile_size = intel_tile_size(dev_priv);
2481                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2482
2483                 if (drm_rotation_90_or_270(rotation)) {
2484                         pitch_tiles = pitch / tile_height;
2485                         swap(tile_width, tile_height);
2486                 } else {
2487                         pitch_tiles = pitch / (tile_width * cpp);
2488                 }
2489
2490                 tile_rows = *y / tile_height;
2491                 *y %= tile_height;
2492
2493                 tiles = *x / tile_width;
2494                 *x %= tile_width;
2495
2496                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2497
2498                 offset_aligned = offset;
2499                 if (alignment)
2500                         offset_aligned = rounddown(offset_aligned, alignment);
2501
2502                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2503                                          tile_size, pitch_tiles,
2504                                          offset, offset_aligned);
2505         } else {
2506                 offset = *y * pitch + *x * cpp;
2507                 offset_aligned = offset;
2508                 if (alignment) {
2509                         offset_aligned = rounddown(offset_aligned, alignment);
2510                         *y = (offset % alignment) / pitch;
2511                         *x = ((offset % alignment) - *y * pitch) / cpp;
2512                 } else {
2513                         *y = *x = 0;
2514                 }
2515         }
2516
2517         return offset_aligned;
2518 }
2519
2520 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2521                                               const struct intel_plane_state *state,
2522                                               int color_plane)
2523 {
2524         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2525         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2526         const struct drm_framebuffer *fb = state->hw.fb;
2527         unsigned int rotation = state->hw.rotation;
2528         int pitch = state->color_plane[color_plane].stride;
2529         u32 alignment;
2530
2531         if (intel_plane->id == PLANE_CURSOR)
2532                 alignment = intel_cursor_alignment(dev_priv);
2533         else
2534                 alignment = intel_surf_alignment(fb, color_plane);
2535
2536         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2537                                             pitch, rotation, alignment);
2538 }
2539
2540 /* Convert the fb->offset[] into x/y offsets */
2541 static int intel_fb_offset_to_xy(int *x, int *y,
2542                                  const struct drm_framebuffer *fb,
2543                                  int color_plane)
2544 {
2545         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2546         unsigned int height;
2547         u32 alignment;
2548
2549         if (INTEL_GEN(dev_priv) >= 12 &&
2550             is_semiplanar_uv_plane(fb, color_plane))
2551                 alignment = intel_tile_row_size(fb, color_plane);
2552         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2553                 alignment = intel_tile_size(dev_priv);
2554         else
2555                 alignment = 0;
2556
2557         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2558                 drm_dbg_kms(&dev_priv->drm,
2559                             "Misaligned offset 0x%08x for color plane %d\n",
2560                             fb->offsets[color_plane], color_plane);
2561                 return -EINVAL;
2562         }
2563
2564         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2565         height = ALIGN(height, intel_tile_height(fb, color_plane));
2566
2567         /* Catch potential overflows early */
2568         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2569                             fb->offsets[color_plane])) {
2570                 drm_dbg_kms(&dev_priv->drm,
2571                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
2572                             fb->offsets[color_plane], fb->pitches[color_plane],
2573                             color_plane);
2574                 return -ERANGE;
2575         }
2576
2577         *x = 0;
2578         *y = 0;
2579
2580         intel_adjust_aligned_offset(x, y,
2581                                     fb, color_plane, DRM_MODE_ROTATE_0,
2582                                     fb->pitches[color_plane],
2583                                     fb->offsets[color_plane], 0);
2584
2585         return 0;
2586 }
2587
2588 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2589 {
2590         switch (fb_modifier) {
2591         case I915_FORMAT_MOD_X_TILED:
2592                 return I915_TILING_X;
2593         case I915_FORMAT_MOD_Y_TILED:
2594         case I915_FORMAT_MOD_Y_TILED_CCS:
2595         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2596         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2597                 return I915_TILING_Y;
2598         default:
2599                 return I915_TILING_NONE;
2600         }
2601 }
2602
2603 /*
2604  * From the Sky Lake PRM:
2605  * "The Color Control Surface (CCS) contains the compression status of
2606  *  the cache-line pairs. The compression state of the cache-line pair
2607  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2608  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2609  *  cache-line-pairs. CCS is always Y tiled."
2610  *
2611  * Since cache line pairs refers to horizontally adjacent cache lines,
2612  * each cache line in the CCS corresponds to an area of 32x16 cache
2613  * lines on the main surface. Since each pixel is 4 bytes, this gives
2614  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2615  * main surface.
2616  */
2617 static const struct drm_format_info skl_ccs_formats[] = {
2618         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2619           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2620         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2621           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2622         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2623           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2624         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2625           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2626 };
2627
2628 /*
2629  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2630  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2631  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2632  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2633  * the main surface.
2634  */
2635 static const struct drm_format_info gen12_ccs_formats[] = {
2636         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2637           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638           .hsub = 1, .vsub = 1, },
2639         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2640           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641           .hsub = 1, .vsub = 1, },
2642         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2643           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644           .hsub = 1, .vsub = 1, .has_alpha = true },
2645         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2646           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647           .hsub = 1, .vsub = 1, .has_alpha = true },
2648         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2649           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650           .hsub = 2, .vsub = 1, .is_yuv = true },
2651         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2652           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653           .hsub = 2, .vsub = 1, .is_yuv = true },
2654         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2655           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656           .hsub = 2, .vsub = 1, .is_yuv = true },
2657         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2658           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659           .hsub = 2, .vsub = 1, .is_yuv = true },
2660         { .format = DRM_FORMAT_NV12, .num_planes = 4,
2661           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2662           .hsub = 2, .vsub = 2, .is_yuv = true },
2663         { .format = DRM_FORMAT_P010, .num_planes = 4,
2664           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665           .hsub = 2, .vsub = 2, .is_yuv = true },
2666         { .format = DRM_FORMAT_P012, .num_planes = 4,
2667           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668           .hsub = 2, .vsub = 2, .is_yuv = true },
2669         { .format = DRM_FORMAT_P016, .num_planes = 4,
2670           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2671           .hsub = 2, .vsub = 2, .is_yuv = true },
2672 };
2673
2674 static const struct drm_format_info *
2675 lookup_format_info(const struct drm_format_info formats[],
2676                    int num_formats, u32 format)
2677 {
2678         int i;
2679
2680         for (i = 0; i < num_formats; i++) {
2681                 if (formats[i].format == format)
2682                         return &formats[i];
2683         }
2684
2685         return NULL;
2686 }
2687
2688 static const struct drm_format_info *
2689 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2690 {
2691         switch (cmd->modifier[0]) {
2692         case I915_FORMAT_MOD_Y_TILED_CCS:
2693         case I915_FORMAT_MOD_Yf_TILED_CCS:
2694                 return lookup_format_info(skl_ccs_formats,
2695                                           ARRAY_SIZE(skl_ccs_formats),
2696                                           cmd->pixel_format);
2697         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2698         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2699                 return lookup_format_info(gen12_ccs_formats,
2700                                           ARRAY_SIZE(gen12_ccs_formats),
2701                                           cmd->pixel_format);
2702         default:
2703                 return NULL;
2704         }
2705 }
2706
2707 bool is_ccs_modifier(u64 modifier)
2708 {
2709         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2710                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2711                modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2712                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2713 }
2714
2715 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2716 {
2717         return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2718                             512) * 64;
2719 }
2720
2721 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2722                               u32 pixel_format, u64 modifier)
2723 {
2724         struct intel_crtc *crtc;
2725         struct intel_plane *plane;
2726
2727         /*
2728          * We assume the primary plane for pipe A has
2729          * the highest stride limits of them all,
2730          * if in case pipe A is disabled, use the first pipe from pipe_mask.
2731          */
2732         crtc = intel_get_first_crtc(dev_priv);
2733         if (!crtc)
2734                 return 0;
2735
2736         plane = to_intel_plane(crtc->base.primary);
2737
2738         return plane->max_stride(plane, pixel_format, modifier,
2739                                  DRM_MODE_ROTATE_0);
2740 }
2741
2742 static
2743 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2744                         u32 pixel_format, u64 modifier)
2745 {
2746         /*
2747          * Arbitrary limit for gen4+ chosen to match the
2748          * render engine max stride.
2749          *
2750          * The new CCS hash mode makes remapping impossible
2751          */
2752         if (!is_ccs_modifier(modifier)) {
2753                 if (INTEL_GEN(dev_priv) >= 7)
2754                         return 256*1024;
2755                 else if (INTEL_GEN(dev_priv) >= 4)
2756                         return 128*1024;
2757         }
2758
2759         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2760 }
2761
2762 static u32
2763 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2764 {
2765         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2766         u32 tile_width;
2767
2768         if (is_surface_linear(fb, color_plane)) {
2769                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2770                                                            fb->format->format,
2771                                                            fb->modifier);
2772
2773                 /*
2774                  * To make remapping with linear generally feasible
2775                  * we need the stride to be page aligned.
2776                  */
2777                 if (fb->pitches[color_plane] > max_stride &&
2778                     !is_ccs_modifier(fb->modifier))
2779                         return intel_tile_size(dev_priv);
2780                 else
2781                         return 64;
2782         }
2783
2784         tile_width = intel_tile_width_bytes(fb, color_plane);
2785         if (is_ccs_modifier(fb->modifier)) {
2786                 /*
2787                  * Display WA #0531: skl,bxt,kbl,glk
2788                  *
2789                  * Render decompression and plane width > 3840
2790                  * combined with horizontal panning requires the
2791                  * plane stride to be a multiple of 4. We'll just
2792                  * require the entire fb to accommodate that to avoid
2793                  * potential runtime errors at plane configuration time.
2794                  */
2795                 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2796                         tile_width *= 4;
2797                 /*
2798                  * The main surface pitch must be padded to a multiple of four
2799                  * tile widths.
2800                  */
2801                 else if (INTEL_GEN(dev_priv) >= 12)
2802                         tile_width *= 4;
2803         }
2804         return tile_width;
2805 }
2806
2807 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2808 {
2809         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2810         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2811         const struct drm_framebuffer *fb = plane_state->hw.fb;
2812         int i;
2813
2814         /* We don't want to deal with remapping with cursors */
2815         if (plane->id == PLANE_CURSOR)
2816                 return false;
2817
2818         /*
2819          * The display engine limits already match/exceed the
2820          * render engine limits, so not much point in remapping.
2821          * Would also need to deal with the fence POT alignment
2822          * and gen2 2KiB GTT tile size.
2823          */
2824         if (INTEL_GEN(dev_priv) < 4)
2825                 return false;
2826
2827         /*
2828          * The new CCS hash mode isn't compatible with remapping as
2829          * the virtual address of the pages affects the compressed data.
2830          */
2831         if (is_ccs_modifier(fb->modifier))
2832                 return false;
2833
2834         /* Linear needs a page aligned stride for remapping */
2835         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2836                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2837
2838                 for (i = 0; i < fb->format->num_planes; i++) {
2839                         if (fb->pitches[i] & alignment)
2840                                 return false;
2841                 }
2842         }
2843
2844         return true;
2845 }
2846
2847 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2848 {
2849         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2850         const struct drm_framebuffer *fb = plane_state->hw.fb;
2851         unsigned int rotation = plane_state->hw.rotation;
2852         u32 stride, max_stride;
2853
2854         /*
2855          * No remapping for invisible planes since we don't have
2856          * an actual source viewport to remap.
2857          */
2858         if (!plane_state->uapi.visible)
2859                 return false;
2860
2861         if (!intel_plane_can_remap(plane_state))
2862                 return false;
2863
2864         /*
2865          * FIXME: aux plane limits on gen9+ are
2866          * unclear in Bspec, for now no checking.
2867          */
2868         stride = intel_fb_pitch(fb, 0, rotation);
2869         max_stride = plane->max_stride(plane, fb->format->format,
2870                                        fb->modifier, rotation);
2871
2872         return stride > max_stride;
2873 }
2874
2875 static void
2876 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2877                                const struct drm_framebuffer *fb,
2878                                int color_plane)
2879 {
2880         int main_plane;
2881
2882         if (color_plane == 0) {
2883                 *hsub = 1;
2884                 *vsub = 1;
2885
2886                 return;
2887         }
2888
2889         /*
2890          * TODO: Deduct the subsampling from the char block for all CCS
2891          * formats and planes.
2892          */
2893         if (!is_gen12_ccs_plane(fb, color_plane)) {
2894                 *hsub = fb->format->hsub;
2895                 *vsub = fb->format->vsub;
2896
2897                 return;
2898         }
2899
2900         main_plane = ccs_to_main_plane(fb, color_plane);
2901         *hsub = drm_format_info_block_width(fb->format, color_plane) /
2902                 drm_format_info_block_width(fb->format, main_plane);
2903
2904         /*
2905          * The min stride check in the core framebuffer_check() function
2906          * assumes that format->hsub applies to every plane except for the
2907          * first plane. That's incorrect for the CCS AUX plane of the first
2908          * plane, but for the above check to pass we must define the block
2909          * width with that subsampling applied to it. Adjust the width here
2910          * accordingly, so we can calculate the actual subsampling factor.
2911          */
2912         if (main_plane == 0)
2913                 *hsub *= fb->format->hsub;
2914
2915         *vsub = 32;
2916 }
2917 static int
2918 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2919 {
2920         struct drm_i915_private *i915 = to_i915(fb->dev);
2921         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2922         int main_plane;
2923         int hsub, vsub;
2924         int tile_width, tile_height;
2925         int ccs_x, ccs_y;
2926         int main_x, main_y;
2927
2928         if (!is_ccs_plane(fb, ccs_plane))
2929                 return 0;
2930
2931         intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2932         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2933
2934         tile_width *= hsub;
2935         tile_height *= vsub;
2936
2937         ccs_x = (x * hsub) % tile_width;
2938         ccs_y = (y * vsub) % tile_height;
2939
2940         main_plane = ccs_to_main_plane(fb, ccs_plane);
2941         main_x = intel_fb->normal[main_plane].x % tile_width;
2942         main_y = intel_fb->normal[main_plane].y % tile_height;
2943
2944         /*
2945          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2946          * x/y offsets must match between CCS and the main surface.
2947          */
2948         if (main_x != ccs_x || main_y != ccs_y) {
2949                 drm_dbg_kms(&i915->drm,
2950                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2951                               main_x, main_y,
2952                               ccs_x, ccs_y,
2953                               intel_fb->normal[main_plane].x,
2954                               intel_fb->normal[main_plane].y,
2955                               x, y);
2956                 return -EINVAL;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static void
2963 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2964 {
2965         int main_plane = is_ccs_plane(fb, color_plane) ?
2966                          ccs_to_main_plane(fb, color_plane) : 0;
2967         int main_hsub, main_vsub;
2968         int hsub, vsub;
2969
2970         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2971         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2972         *w = fb->width / main_hsub / hsub;
2973         *h = fb->height / main_vsub / vsub;
2974 }
2975
2976 /*
2977  * Setup the rotated view for an FB plane and return the size the GTT mapping
2978  * requires for this view.
2979  */
2980 static u32
2981 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2982                   u32 gtt_offset_rotated, int x, int y,
2983                   unsigned int width, unsigned int height,
2984                   unsigned int tile_size,
2985                   unsigned int tile_width, unsigned int tile_height,
2986                   struct drm_framebuffer *fb)
2987 {
2988         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2989         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2990         unsigned int pitch_tiles;
2991         struct drm_rect r;
2992
2993         /* Y or Yf modifiers required for 90/270 rotation */
2994         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2995             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2996                 return 0;
2997
2998         if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
2999                 return 0;
3000
3001         rot_info->plane[plane] = *plane_info;
3002
3003         intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3004
3005         /* rotate the x/y offsets to match the GTT view */
3006         drm_rect_init(&r, x, y, width, height);
3007         drm_rect_rotate(&r,
3008                         plane_info->width * tile_width,
3009                         plane_info->height * tile_height,
3010                         DRM_MODE_ROTATE_270);
3011         x = r.x1;
3012         y = r.y1;
3013
3014         /* rotate the tile dimensions to match the GTT view */
3015         pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3016         swap(tile_width, tile_height);
3017
3018         /*
3019          * We only keep the x/y offsets, so push all of the
3020          * gtt offset into the x/y offsets.
3021          */
3022         intel_adjust_tile_offset(&x, &y,
3023                                  tile_width, tile_height,
3024                                  tile_size, pitch_tiles,
3025                                  gtt_offset_rotated * tile_size, 0);
3026
3027         /*
3028          * First pixel of the framebuffer from
3029          * the start of the rotated gtt mapping.
3030          */
3031         intel_fb->rotated[plane].x = x;
3032         intel_fb->rotated[plane].y = y;
3033
3034         return plane_info->width * plane_info->height;
3035 }
3036
3037 static int
3038 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3039                    struct drm_framebuffer *fb)
3040 {
3041         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3042         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3043         u32 gtt_offset_rotated = 0;
3044         unsigned int max_size = 0;
3045         int i, num_planes = fb->format->num_planes;
3046         unsigned int tile_size = intel_tile_size(dev_priv);
3047
3048         for (i = 0; i < num_planes; i++) {
3049                 unsigned int width, height;
3050                 unsigned int cpp, size;
3051                 u32 offset;
3052                 int x, y;
3053                 int ret;
3054
3055                 cpp = fb->format->cpp[i];
3056                 intel_fb_plane_dims(&width, &height, fb, i);
3057
3058                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3059                 if (ret) {
3060                         drm_dbg_kms(&dev_priv->drm,
3061                                     "bad fb plane %d offset: 0x%x\n",
3062                                     i, fb->offsets[i]);
3063                         return ret;
3064                 }
3065
3066                 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3067                 if (ret)
3068                         return ret;
3069
3070                 /*
3071                  * The fence (if used) is aligned to the start of the object
3072                  * so having the framebuffer wrap around across the edge of the
3073                  * fenced region doesn't really work. We have no API to configure
3074                  * the fence start offset within the object (nor could we probably
3075                  * on gen2/3). So it's just easier if we just require that the
3076                  * fb layout agrees with the fence layout. We already check that the
3077                  * fb stride matches the fence stride elsewhere.
3078                  */
3079                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3080                     (x + width) * cpp > fb->pitches[i]) {
3081                         drm_dbg_kms(&dev_priv->drm,
3082                                     "bad fb plane %d offset: 0x%x\n",
3083                                      i, fb->offsets[i]);
3084                         return -EINVAL;
3085                 }
3086
3087                 /*
3088                  * First pixel of the framebuffer from
3089                  * the start of the normal gtt mapping.
3090                  */
3091                 intel_fb->normal[i].x = x;
3092                 intel_fb->normal[i].y = y;
3093
3094                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3095                                                       fb->pitches[i],
3096                                                       DRM_MODE_ROTATE_0,
3097                                                       tile_size);
3098                 offset /= tile_size;
3099
3100                 if (!is_surface_linear(fb, i)) {
3101                         struct intel_remapped_plane_info plane_info;
3102                         unsigned int tile_width, tile_height;
3103
3104                         intel_tile_dims(fb, i, &tile_width, &tile_height);
3105
3106                         plane_info.offset = offset;
3107                         plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3108                                                          tile_width * cpp);
3109                         plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3110                         plane_info.height = DIV_ROUND_UP(y + height,
3111                                                          tile_height);
3112
3113                         /* how many tiles does this plane need */
3114                         size = plane_info.stride * plane_info.height;
3115                         /*
3116                          * If the plane isn't horizontally tile aligned,
3117                          * we need one more tile.
3118                          */
3119                         if (x != 0)
3120                                 size++;
3121
3122                         gtt_offset_rotated +=
3123                                 setup_fb_rotation(i, &plane_info,
3124                                                   gtt_offset_rotated,
3125                                                   x, y, width, height,
3126                                                   tile_size,
3127                                                   tile_width, tile_height,
3128                                                   fb);
3129                 } else {
3130                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3131                                             x * cpp, tile_size);
3132                 }
3133
3134                 /* how many tiles in total needed in the bo */
3135                 max_size = max(max_size, offset + size);
3136         }
3137
3138         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3139                 drm_dbg_kms(&dev_priv->drm,
3140                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3141                             mul_u32_u32(max_size, tile_size), obj->base.size);
3142                 return -EINVAL;
3143         }
3144
3145         return 0;
3146 }
3147
3148 static void
3149 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3150 {
3151         struct drm_i915_private *dev_priv =
3152                 to_i915(plane_state->uapi.plane->dev);
3153         struct drm_framebuffer *fb = plane_state->hw.fb;
3154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3155         struct intel_rotation_info *info = &plane_state->view.rotated;
3156         unsigned int rotation = plane_state->hw.rotation;
3157         int i, num_planes = fb->format->num_planes;
3158         unsigned int tile_size = intel_tile_size(dev_priv);
3159         unsigned int src_x, src_y;
3160         unsigned int src_w, src_h;
3161         u32 gtt_offset = 0;
3162
3163         memset(&plane_state->view, 0, sizeof(plane_state->view));
3164         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3165                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3166
3167         src_x = plane_state->uapi.src.x1 >> 16;
3168         src_y = plane_state->uapi.src.y1 >> 16;
3169         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3170         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3171
3172         drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3173
3174         /* Make src coordinates relative to the viewport */
3175         drm_rect_translate(&plane_state->uapi.src,
3176                            -(src_x << 16), -(src_y << 16));
3177
3178         /* Rotate src coordinates to match rotated GTT view */
3179         if (drm_rotation_90_or_270(rotation))
3180                 drm_rect_rotate(&plane_state->uapi.src,
3181                                 src_w << 16, src_h << 16,
3182                                 DRM_MODE_ROTATE_270);
3183
3184         for (i = 0; i < num_planes; i++) {
3185                 unsigned int hsub = i ? fb->format->hsub : 1;
3186                 unsigned int vsub = i ? fb->format->vsub : 1;
3187                 unsigned int cpp = fb->format->cpp[i];
3188                 unsigned int tile_width, tile_height;
3189                 unsigned int width, height;
3190                 unsigned int pitch_tiles;
3191                 unsigned int x, y;
3192                 u32 offset;
3193
3194                 intel_tile_dims(fb, i, &tile_width, &tile_height);
3195
3196                 x = src_x / hsub;
3197                 y = src_y / vsub;
3198                 width = src_w / hsub;
3199                 height = src_h / vsub;
3200
3201                 /*
3202                  * First pixel of the src viewport from the
3203                  * start of the normal gtt mapping.
3204                  */
3205                 x += intel_fb->normal[i].x;
3206                 y += intel_fb->normal[i].y;
3207
3208                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3209                                                       fb, i, fb->pitches[i],
3210                                                       DRM_MODE_ROTATE_0, tile_size);
3211                 offset /= tile_size;
3212
3213                 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3214                 info->plane[i].offset = offset;
3215                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3216                                                      tile_width * cpp);
3217                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3218                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3219
3220                 if (drm_rotation_90_or_270(rotation)) {
3221                         struct drm_rect r;
3222
3223                         /* rotate the x/y offsets to match the GTT view */
3224                         drm_rect_init(&r, x, y, width, height);
3225                         drm_rect_rotate(&r,
3226                                         info->plane[i].width * tile_width,
3227                                         info->plane[i].height * tile_height,
3228                                         DRM_MODE_ROTATE_270);
3229                         x = r.x1;
3230                         y = r.y1;
3231
3232                         pitch_tiles = info->plane[i].height;
3233                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3234
3235                         /* rotate the tile dimensions to match the GTT view */
3236                         swap(tile_width, tile_height);
3237                 } else {
3238                         pitch_tiles = info->plane[i].width;
3239                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3240                 }
3241
3242                 /*
3243                  * We only keep the x/y offsets, so push all of the
3244                  * gtt offset into the x/y offsets.
3245                  */
3246                 intel_adjust_tile_offset(&x, &y,
3247                                          tile_width, tile_height,
3248                                          tile_size, pitch_tiles,
3249                                          gtt_offset * tile_size, 0);
3250
3251                 gtt_offset += info->plane[i].width * info->plane[i].height;
3252
3253                 plane_state->color_plane[i].offset = 0;
3254                 plane_state->color_plane[i].x = x;
3255                 plane_state->color_plane[i].y = y;
3256         }
3257 }
3258
3259 static int
3260 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3261 {
3262         const struct intel_framebuffer *fb =
3263                 to_intel_framebuffer(plane_state->hw.fb);
3264         unsigned int rotation = plane_state->hw.rotation;
3265         int i, num_planes;
3266
3267         if (!fb)
3268                 return 0;
3269
3270         num_planes = fb->base.format->num_planes;
3271
3272         if (intel_plane_needs_remap(plane_state)) {
3273                 intel_plane_remap_gtt(plane_state);
3274
3275                 /*
3276                  * Sometimes even remapping can't overcome
3277                  * the stride limitations :( Can happen with
3278                  * big plane sizes and suitably misaligned
3279                  * offsets.
3280                  */
3281                 return intel_plane_check_stride(plane_state);
3282         }
3283
3284         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3285
3286         for (i = 0; i < num_planes; i++) {
3287                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3288                 plane_state->color_plane[i].offset = 0;
3289
3290                 if (drm_rotation_90_or_270(rotation)) {
3291                         plane_state->color_plane[i].x = fb->rotated[i].x;
3292                         plane_state->color_plane[i].y = fb->rotated[i].y;
3293                 } else {
3294                         plane_state->color_plane[i].x = fb->normal[i].x;
3295                         plane_state->color_plane[i].y = fb->normal[i].y;
3296                 }
3297         }
3298
3299         /* Rotate src coordinates to match rotated GTT view */
3300         if (drm_rotation_90_or_270(rotation))
3301                 drm_rect_rotate(&plane_state->uapi.src,
3302                                 fb->base.width << 16, fb->base.height << 16,
3303                                 DRM_MODE_ROTATE_270);
3304
3305         return intel_plane_check_stride(plane_state);
3306 }
3307
3308 static int i9xx_format_to_fourcc(int format)
3309 {
3310         switch (format) {
3311         case DISPPLANE_8BPP:
3312                 return DRM_FORMAT_C8;
3313         case DISPPLANE_BGRA555:
3314                 return DRM_FORMAT_ARGB1555;
3315         case DISPPLANE_BGRX555:
3316                 return DRM_FORMAT_XRGB1555;
3317         case DISPPLANE_BGRX565:
3318                 return DRM_FORMAT_RGB565;
3319         default:
3320         case DISPPLANE_BGRX888:
3321                 return DRM_FORMAT_XRGB8888;
3322         case DISPPLANE_RGBX888:
3323                 return DRM_FORMAT_XBGR8888;
3324         case DISPPLANE_BGRA888:
3325                 return DRM_FORMAT_ARGB8888;
3326         case DISPPLANE_RGBA888:
3327                 return DRM_FORMAT_ABGR8888;
3328         case DISPPLANE_BGRX101010:
3329                 return DRM_FORMAT_XRGB2101010;
3330         case DISPPLANE_RGBX101010:
3331                 return DRM_FORMAT_XBGR2101010;
3332         case DISPPLANE_BGRA101010:
3333                 return DRM_FORMAT_ARGB2101010;
3334         case DISPPLANE_RGBA101010:
3335                 return DRM_FORMAT_ABGR2101010;
3336         case DISPPLANE_RGBX161616:
3337                 return DRM_FORMAT_XBGR16161616F;
3338         }
3339 }
3340
3341 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3342 {
3343         switch (format) {
3344         case PLANE_CTL_FORMAT_RGB_565:
3345                 return DRM_FORMAT_RGB565;
3346         case PLANE_CTL_FORMAT_NV12:
3347                 return DRM_FORMAT_NV12;
3348         case PLANE_CTL_FORMAT_XYUV:
3349                 return DRM_FORMAT_XYUV8888;
3350         case PLANE_CTL_FORMAT_P010:
3351                 return DRM_FORMAT_P010;
3352         case PLANE_CTL_FORMAT_P012:
3353                 return DRM_FORMAT_P012;
3354         case PLANE_CTL_FORMAT_P016:
3355                 return DRM_FORMAT_P016;
3356         case PLANE_CTL_FORMAT_Y210:
3357                 return DRM_FORMAT_Y210;
3358         case PLANE_CTL_FORMAT_Y212:
3359                 return DRM_FORMAT_Y212;
3360         case PLANE_CTL_FORMAT_Y216:
3361                 return DRM_FORMAT_Y216;
3362         case PLANE_CTL_FORMAT_Y410:
3363                 return DRM_FORMAT_XVYU2101010;
3364         case PLANE_CTL_FORMAT_Y412:
3365                 return DRM_FORMAT_XVYU12_16161616;
3366         case PLANE_CTL_FORMAT_Y416:
3367                 return DRM_FORMAT_XVYU16161616;
3368         default:
3369         case PLANE_CTL_FORMAT_XRGB_8888:
3370                 if (rgb_order) {
3371                         if (alpha)
3372                                 return DRM_FORMAT_ABGR8888;
3373                         else
3374                                 return DRM_FORMAT_XBGR8888;
3375                 } else {
3376                         if (alpha)
3377                                 return DRM_FORMAT_ARGB8888;
3378                         else
3379                                 return DRM_FORMAT_XRGB8888;
3380                 }
3381         case PLANE_CTL_FORMAT_XRGB_2101010:
3382                 if (rgb_order) {
3383                         if (alpha)
3384                                 return DRM_FORMAT_ABGR2101010;
3385                         else
3386                                 return DRM_FORMAT_XBGR2101010;
3387                 } else {
3388                         if (alpha)
3389                                 return DRM_FORMAT_ARGB2101010;
3390                         else
3391                                 return DRM_FORMAT_XRGB2101010;
3392                 }
3393         case PLANE_CTL_FORMAT_XRGB_16161616F:
3394                 if (rgb_order) {
3395                         if (alpha)
3396                                 return DRM_FORMAT_ABGR16161616F;
3397                         else
3398                                 return DRM_FORMAT_XBGR16161616F;
3399                 } else {
3400                         if (alpha)
3401                                 return DRM_FORMAT_ARGB16161616F;
3402                         else
3403                                 return DRM_FORMAT_XRGB16161616F;
3404                 }
3405         }
3406 }
3407
3408 static struct i915_vma *
3409 initial_plane_vma(struct drm_i915_private *i915,
3410                   struct intel_initial_plane_config *plane_config)
3411 {
3412         struct drm_i915_gem_object *obj;
3413         struct i915_vma *vma;
3414         u32 base, size;
3415
3416         if (plane_config->size == 0)
3417                 return NULL;
3418
3419         base = round_down(plane_config->base,
3420                           I915_GTT_MIN_ALIGNMENT);
3421         size = round_up(plane_config->base + plane_config->size,
3422                         I915_GTT_MIN_ALIGNMENT);
3423         size -= base;
3424
3425         /*
3426          * If the FB is too big, just don't use it since fbdev is not very
3427          * important and we should probably use that space with FBC or other
3428          * features.
3429          */
3430         if (size * 2 > i915->stolen_usable_size)
3431                 return NULL;
3432
3433         obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3434         if (IS_ERR(obj))
3435                 return NULL;
3436
3437         switch (plane_config->tiling) {
3438         case I915_TILING_NONE:
3439                 break;
3440         case I915_TILING_X:
3441         case I915_TILING_Y:
3442                 obj->tiling_and_stride =
3443                         plane_config->fb->base.pitches[0] |
3444                         plane_config->tiling;
3445                 break;
3446         default:
3447                 MISSING_CASE(plane_config->tiling);
3448                 goto err_obj;
3449         }
3450
3451         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3452         if (IS_ERR(vma))
3453                 goto err_obj;
3454
3455         if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3456                 goto err_obj;
3457
3458         if (i915_gem_object_is_tiled(obj) &&
3459             !i915_vma_is_map_and_fenceable(vma))
3460                 goto err_obj;
3461
3462         return vma;
3463
3464 err_obj:
3465         i915_gem_object_put(obj);
3466         return NULL;
3467 }
3468
3469 static bool
3470 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3471                               struct intel_initial_plane_config *plane_config)
3472 {
3473         struct drm_device *dev = crtc->base.dev;
3474         struct drm_i915_private *dev_priv = to_i915(dev);
3475         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3476         struct drm_framebuffer *fb = &plane_config->fb->base;
3477         struct i915_vma *vma;
3478
3479         switch (fb->modifier) {
3480         case DRM_FORMAT_MOD_LINEAR:
3481         case I915_FORMAT_MOD_X_TILED:
3482         case I915_FORMAT_MOD_Y_TILED:
3483                 break;
3484         default:
3485                 drm_dbg(&dev_priv->drm,
3486                         "Unsupported modifier for initial FB: 0x%llx\n",
3487                         fb->modifier);
3488                 return false;
3489         }
3490
3491         vma = initial_plane_vma(dev_priv, plane_config);
3492         if (!vma)
3493                 return false;
3494
3495         mode_cmd.pixel_format = fb->format->format;
3496         mode_cmd.width = fb->width;
3497         mode_cmd.height = fb->height;
3498         mode_cmd.pitches[0] = fb->pitches[0];
3499         mode_cmd.modifier[0] = fb->modifier;
3500         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3501
3502         if (intel_framebuffer_init(to_intel_framebuffer(fb),
3503                                    vma->obj, &mode_cmd)) {
3504                 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3505                 goto err_vma;
3506         }
3507
3508         plane_config->vma = vma;
3509         return true;
3510
3511 err_vma:
3512         i915_vma_put(vma);
3513         return false;
3514 }
3515
3516 static void
3517 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3518                         struct intel_plane_state *plane_state,
3519                         bool visible)
3520 {
3521         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3522
3523         plane_state->uapi.visible = visible;
3524
3525         if (visible)
3526                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3527         else
3528                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3529 }
3530
3531 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3532 {
3533         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3534         struct drm_plane *plane;
3535
3536         /*
3537          * Active_planes aliases if multiple "primary" or cursor planes
3538          * have been used on the same (or wrong) pipe. plane_mask uses
3539          * unique ids, hence we can use that to reconstruct active_planes.
3540          */
3541         crtc_state->active_planes = 0;
3542
3543         drm_for_each_plane_mask(plane, &dev_priv->drm,
3544                                 crtc_state->uapi.plane_mask)
3545                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3546 }
3547
3548 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3549                                          struct intel_plane *plane)
3550 {
3551         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3552         struct intel_crtc_state *crtc_state =
3553                 to_intel_crtc_state(crtc->base.state);
3554         struct intel_plane_state *plane_state =
3555                 to_intel_plane_state(plane->base.state);
3556
3557         drm_dbg_kms(&dev_priv->drm,
3558                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3559                     plane->base.base.id, plane->base.name,
3560                     crtc->base.base.id, crtc->base.name);
3561
3562         intel_set_plane_visible(crtc_state, plane_state, false);
3563         fixup_active_planes(crtc_state);
3564         crtc_state->data_rate[plane->id] = 0;
3565         crtc_state->min_cdclk[plane->id] = 0;
3566
3567         if (plane->id == PLANE_PRIMARY)
3568                 hsw_disable_ips(crtc_state);
3569
3570         /*
3571          * Vblank time updates from the shadow to live plane control register
3572          * are blocked if the memory self-refresh mode is active at that
3573          * moment. So to make sure the plane gets truly disabled, disable
3574          * first the self-refresh mode. The self-refresh enable bit in turn
3575          * will be checked/applied by the HW only at the next frame start
3576          * event which is after the vblank start event, so we need to have a
3577          * wait-for-vblank between disabling the plane and the pipe.
3578          */
3579         if (HAS_GMCH(dev_priv) &&
3580             intel_set_memory_cxsr(dev_priv, false))
3581                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3582
3583         /*
3584          * Gen2 reports pipe underruns whenever all planes are disabled.
3585          * So disable underrun reporting before all the planes get disabled.
3586          */
3587         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3588                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3589
3590         intel_disable_plane(plane, crtc_state);
3591 }
3592
3593 static struct intel_frontbuffer *
3594 to_intel_frontbuffer(struct drm_framebuffer *fb)
3595 {
3596         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3597 }
3598
3599 static void
3600 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3601                              struct intel_initial_plane_config *plane_config)
3602 {
3603         struct drm_device *dev = intel_crtc->base.dev;
3604         struct drm_i915_private *dev_priv = to_i915(dev);
3605         struct drm_crtc *c;
3606         struct drm_plane *primary = intel_crtc->base.primary;
3607         struct drm_plane_state *plane_state = primary->state;
3608         struct intel_plane *intel_plane = to_intel_plane(primary);
3609         struct intel_plane_state *intel_state =
3610                 to_intel_plane_state(plane_state);
3611         struct drm_framebuffer *fb;
3612         struct i915_vma *vma;
3613
3614         if (!plane_config->fb)
3615                 return;
3616
3617         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3618                 fb = &plane_config->fb->base;
3619                 vma = plane_config->vma;
3620                 goto valid_fb;
3621         }
3622
3623         /*
3624          * Failed to alloc the obj, check to see if we should share
3625          * an fb with another CRTC instead
3626          */
3627         for_each_crtc(dev, c) {
3628                 struct intel_plane_state *state;
3629
3630                 if (c == &intel_crtc->base)
3631                         continue;
3632
3633                 if (!to_intel_crtc(c)->active)
3634                         continue;
3635
3636                 state = to_intel_plane_state(c->primary->state);
3637                 if (!state->vma)
3638                         continue;
3639
3640                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3641                         fb = state->hw.fb;
3642                         vma = state->vma;
3643                         goto valid_fb;
3644                 }
3645         }
3646
3647         /*
3648          * We've failed to reconstruct the BIOS FB.  Current display state
3649          * indicates that the primary plane is visible, but has a NULL FB,
3650          * which will lead to problems later if we don't fix it up.  The
3651          * simplest solution is to just disable the primary plane now and
3652          * pretend the BIOS never had it enabled.
3653          */
3654         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3655
3656         return;
3657
3658 valid_fb:
3659         intel_state->hw.rotation = plane_config->rotation;
3660         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3661                                 intel_state->hw.rotation);
3662         intel_state->color_plane[0].stride =
3663                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3664
3665         __i915_vma_pin(vma);
3666         intel_state->vma = i915_vma_get(vma);
3667         if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3668                 if (vma->fence)
3669                         intel_state->flags |= PLANE_HAS_FENCE;
3670
3671         plane_state->src_x = 0;
3672         plane_state->src_y = 0;
3673         plane_state->src_w = fb->width << 16;
3674         plane_state->src_h = fb->height << 16;
3675
3676         plane_state->crtc_x = 0;
3677         plane_state->crtc_y = 0;
3678         plane_state->crtc_w = fb->width;
3679         plane_state->crtc_h = fb->height;
3680
3681         intel_state->uapi.src = drm_plane_state_src(plane_state);
3682         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3683
3684         if (plane_config->tiling)
3685                 dev_priv->preserve_bios_swizzle = true;
3686
3687         plane_state->fb = fb;
3688         drm_framebuffer_get(fb);
3689
3690         plane_state->crtc = &intel_crtc->base;
3691         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3692
3693         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3694
3695         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3696                   &to_intel_frontbuffer(fb)->bits);
3697 }
3698
3699 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3700                                int color_plane,
3701                                unsigned int rotation)
3702 {
3703         int cpp = fb->format->cpp[color_plane];
3704
3705         switch (fb->modifier) {
3706         case DRM_FORMAT_MOD_LINEAR:
3707         case I915_FORMAT_MOD_X_TILED:
3708                 /*
3709                  * Validated limit is 4k, but has 5k should
3710                  * work apart from the following features:
3711                  * - Ytile (already limited to 4k)
3712                  * - FP16 (already limited to 4k)
3713                  * - render compression (already limited to 4k)
3714                  * - KVMR sprite and cursor (don't care)
3715                  * - horizontal panning (TODO verify this)
3716                  * - pipe and plane scaling (TODO verify this)
3717                  */
3718                 if (cpp == 8)
3719                         return 4096;
3720                 else
3721                         return 5120;
3722         case I915_FORMAT_MOD_Y_TILED_CCS:
3723         case I915_FORMAT_MOD_Yf_TILED_CCS:
3724         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3725                 /* FIXME AUX plane? */
3726         case I915_FORMAT_MOD_Y_TILED:
3727         case I915_FORMAT_MOD_Yf_TILED:
3728                 if (cpp == 8)
3729                         return 2048;
3730                 else
3731                         return 4096;
3732         default:
3733                 MISSING_CASE(fb->modifier);
3734                 return 2048;
3735         }
3736 }
3737
3738 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3739                                int color_plane,
3740                                unsigned int rotation)
3741 {
3742         int cpp = fb->format->cpp[color_plane];
3743
3744         switch (fb->modifier) {
3745         case DRM_FORMAT_MOD_LINEAR:
3746         case I915_FORMAT_MOD_X_TILED:
3747                 if (cpp == 8)
3748                         return 4096;
3749                 else
3750                         return 5120;
3751         case I915_FORMAT_MOD_Y_TILED_CCS:
3752         case I915_FORMAT_MOD_Yf_TILED_CCS:
3753                 /* FIXME AUX plane? */
3754         case I915_FORMAT_MOD_Y_TILED:
3755         case I915_FORMAT_MOD_Yf_TILED:
3756                 if (cpp == 8)
3757                         return 2048;
3758                 else
3759                         return 5120;
3760         default:
3761                 MISSING_CASE(fb->modifier);
3762                 return 2048;
3763         }
3764 }
3765
3766 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3767 {
3768         /* Wa_14011264657, Wa_14011050563: gen11+ */
3769         switch (fb->format->format) {
3770         case DRM_FORMAT_C8:
3771                 return 18;
3772         case DRM_FORMAT_RGB565:
3773                 return 10;
3774         case DRM_FORMAT_XRGB8888:
3775         case DRM_FORMAT_XBGR8888:
3776         case DRM_FORMAT_ARGB8888:
3777         case DRM_FORMAT_ABGR8888:
3778         case DRM_FORMAT_XRGB2101010:
3779         case DRM_FORMAT_XBGR2101010:
3780         case DRM_FORMAT_ARGB2101010:
3781         case DRM_FORMAT_ABGR2101010:
3782         case DRM_FORMAT_XVYU2101010:
3783         case DRM_FORMAT_Y212:
3784         case DRM_FORMAT_Y216:
3785                 return 6;
3786         case DRM_FORMAT_NV12:
3787                 return 20;
3788         case DRM_FORMAT_P010:
3789         case DRM_FORMAT_P012:
3790         case DRM_FORMAT_P016:
3791                 return 12;
3792         case DRM_FORMAT_XRGB16161616F:
3793         case DRM_FORMAT_XBGR16161616F:
3794         case DRM_FORMAT_ARGB16161616F:
3795         case DRM_FORMAT_ABGR16161616F:
3796         case DRM_FORMAT_XVYU12_16161616:
3797         case DRM_FORMAT_XVYU16161616:
3798                 return 4;
3799         default:
3800                 return 1;
3801         }
3802 }
3803
3804 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3805                                int color_plane,
3806                                unsigned int rotation)
3807 {
3808         return 5120;
3809 }
3810
3811 static int skl_max_plane_height(void)
3812 {
3813         return 4096;
3814 }
3815
3816 static int icl_max_plane_height(void)
3817 {
3818         return 4320;
3819 }
3820
3821 static bool
3822 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3823                                int main_x, int main_y, u32 main_offset,
3824                                int ccs_plane)
3825 {
3826         const struct drm_framebuffer *fb = plane_state->hw.fb;
3827         int aux_x = plane_state->color_plane[ccs_plane].x;
3828         int aux_y = plane_state->color_plane[ccs_plane].y;
3829         u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3830         u32 alignment = intel_surf_alignment(fb, ccs_plane);
3831         int hsub;
3832         int vsub;
3833
3834         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3835         while (aux_offset >= main_offset && aux_y <= main_y) {
3836                 int x, y;
3837
3838                 if (aux_x == main_x && aux_y == main_y)
3839                         break;
3840
3841                 if (aux_offset == 0)
3842                         break;
3843
3844                 x = aux_x / hsub;
3845                 y = aux_y / vsub;
3846                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3847                                                                plane_state,
3848                                                                ccs_plane,
3849                                                                aux_offset,
3850                                                                aux_offset -
3851                                                                 alignment);
3852                 aux_x = x * hsub + aux_x % hsub;
3853                 aux_y = y * vsub + aux_y % vsub;
3854         }
3855
3856         if (aux_x != main_x || aux_y != main_y)
3857                 return false;
3858
3859         plane_state->color_plane[ccs_plane].offset = aux_offset;
3860         plane_state->color_plane[ccs_plane].x = aux_x;
3861         plane_state->color_plane[ccs_plane].y = aux_y;
3862
3863         return true;
3864 }
3865
3866 unsigned int
3867 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3868 {
3869         int x = 0, y = 0;
3870
3871         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3872                                           plane_state->color_plane[0].offset, 0);
3873
3874         return y;
3875 }
3876
3877 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3878 {
3879         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3880         const struct drm_framebuffer *fb = plane_state->hw.fb;
3881         unsigned int rotation = plane_state->hw.rotation;
3882         int x = plane_state->uapi.src.x1 >> 16;
3883         int y = plane_state->uapi.src.y1 >> 16;
3884         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3885         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3886         int max_width, min_width, max_height;
3887         u32 alignment, offset;
3888         int aux_plane = intel_main_to_aux_plane(fb, 0);
3889         u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3890
3891         if (INTEL_GEN(dev_priv) >= 11) {
3892                 max_width = icl_max_plane_width(fb, 0, rotation);
3893                 min_width = icl_min_plane_width(fb);
3894         } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3895                 max_width = glk_max_plane_width(fb, 0, rotation);
3896                 min_width = 1;
3897         } else {
3898                 max_width = skl_max_plane_width(fb, 0, rotation);
3899                 min_width = 1;
3900         }
3901
3902         if (INTEL_GEN(dev_priv) >= 11)
3903                 max_height = icl_max_plane_height();
3904         else
3905                 max_height = skl_max_plane_height();
3906
3907         if (w > max_width || w < min_width || h > max_height) {
3908                 drm_dbg_kms(&dev_priv->drm,
3909                             "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3910                             w, h, min_width, max_width, max_height);
3911                 return -EINVAL;
3912         }
3913
3914         intel_add_fb_offsets(&x, &y, plane_state, 0);
3915         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3916         alignment = intel_surf_alignment(fb, 0);
3917         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3918                 return -EINVAL;
3919
3920         /*
3921          * AUX surface offset is specified as the distance from the
3922          * main surface offset, and it must be non-negative. Make
3923          * sure that is what we will get.
3924          */
3925         if (offset > aux_offset)
3926                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3927                                                            offset, aux_offset & ~(alignment - 1));
3928
3929         /*
3930          * When using an X-tiled surface, the plane blows up
3931          * if the x offset + width exceed the stride.
3932          *
3933          * TODO: linear and Y-tiled seem fine, Yf untested,
3934          */
3935         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3936                 int cpp = fb->format->cpp[0];
3937
3938                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3939                         if (offset == 0) {
3940                                 drm_dbg_kms(&dev_priv->drm,
3941                                             "Unable to find suitable display surface offset due to X-tiling\n");
3942                                 return -EINVAL;
3943                         }
3944
3945                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3946                                                                    offset, offset - alignment);
3947                 }
3948         }
3949
3950         /*
3951          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3952          * they match with the main surface x/y offsets.
3953          */
3954         if (is_ccs_modifier(fb->modifier)) {
3955                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3956                                                        offset, aux_plane)) {
3957                         if (offset == 0)
3958                                 break;
3959
3960                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3961                                                                    offset, offset - alignment);
3962                 }
3963
3964                 if (x != plane_state->color_plane[aux_plane].x ||
3965                     y != plane_state->color_plane[aux_plane].y) {
3966                         drm_dbg_kms(&dev_priv->drm,
3967                                     "Unable to find suitable display surface offset due to CCS\n");
3968                         return -EINVAL;
3969                 }
3970         }
3971
3972         plane_state->color_plane[0].offset = offset;
3973         plane_state->color_plane[0].x = x;
3974         plane_state->color_plane[0].y = y;
3975
3976         /*
3977          * Put the final coordinates back so that the src
3978          * coordinate checks will see the right values.
3979          */
3980         drm_rect_translate_to(&plane_state->uapi.src,
3981                               x << 16, y << 16);
3982
3983         return 0;
3984 }
3985
3986 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3987 {
3988         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3989         const struct drm_framebuffer *fb = plane_state->hw.fb;
3990         unsigned int rotation = plane_state->hw.rotation;
3991         int uv_plane = 1;
3992         int max_width = skl_max_plane_width(fb, uv_plane, rotation);
3993         int max_height = 4096;
3994         int x = plane_state->uapi.src.x1 >> 17;
3995         int y = plane_state->uapi.src.y1 >> 17;
3996         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3997         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3998         u32 offset;
3999
4000         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4001         offset = intel_plane_compute_aligned_offset(&x, &y,
4002                                                     plane_state, uv_plane);
4003
4004         /* FIXME not quite sure how/if these apply to the chroma plane */
4005         if (w > max_width || h > max_height) {
4006                 drm_dbg_kms(&i915->drm,
4007                             "CbCr source size %dx%d too big (limit %dx%d)\n",
4008                             w, h, max_width, max_height);
4009                 return -EINVAL;
4010         }
4011
4012         if (is_ccs_modifier(fb->modifier)) {
4013                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4014                 int aux_offset = plane_state->color_plane[ccs_plane].offset;
4015                 int alignment = intel_surf_alignment(fb, uv_plane);
4016
4017                 if (offset > aux_offset)
4018                         offset = intel_plane_adjust_aligned_offset(&x, &y,
4019                                                                    plane_state,
4020                                                                    uv_plane,
4021                                                                    offset,
4022                                                                    aux_offset & ~(alignment - 1));
4023
4024                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4025                                                        offset, ccs_plane)) {
4026                         if (offset == 0)
4027                                 break;
4028
4029                         offset = intel_plane_adjust_aligned_offset(&x, &y,
4030                                                                    plane_state,
4031                                                                    uv_plane,
4032                                                                    offset, offset - alignment);
4033                 }
4034
4035                 if (x != plane_state->color_plane[ccs_plane].x ||
4036                     y != plane_state->color_plane[ccs_plane].y) {
4037                         drm_dbg_kms(&i915->drm,
4038                                     "Unable to find suitable display surface offset due to CCS\n");
4039                         return -EINVAL;
4040                 }
4041         }
4042
4043         plane_state->color_plane[uv_plane].offset = offset;
4044         plane_state->color_plane[uv_plane].x = x;
4045         plane_state->color_plane[uv_plane].y = y;
4046
4047         return 0;
4048 }
4049
4050 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4051 {
4052         const struct drm_framebuffer *fb = plane_state->hw.fb;
4053         int src_x = plane_state->uapi.src.x1 >> 16;
4054         int src_y = plane_state->uapi.src.y1 >> 16;
4055         u32 offset;
4056         int ccs_plane;
4057
4058         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4059                 int main_hsub, main_vsub;
4060                 int hsub, vsub;
4061                 int x, y;
4062
4063                 if (!is_ccs_plane(fb, ccs_plane))
4064                         continue;
4065
4066                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4067                                                ccs_to_main_plane(fb, ccs_plane));
4068                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4069
4070                 hsub *= main_hsub;
4071                 vsub *= main_vsub;
4072                 x = src_x / hsub;
4073                 y = src_y / vsub;
4074
4075                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4076
4077                 offset = intel_plane_compute_aligned_offset(&x, &y,
4078                                                             plane_state,
4079                                                             ccs_plane);
4080
4081                 plane_state->color_plane[ccs_plane].offset = offset;
4082                 plane_state->color_plane[ccs_plane].x = (x * hsub +
4083                                                          src_x % hsub) /
4084                                                         main_hsub;
4085                 plane_state->color_plane[ccs_plane].y = (y * vsub +
4086                                                          src_y % vsub) /
4087                                                         main_vsub;
4088         }
4089
4090         return 0;
4091 }
4092
4093 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4094 {
4095         const struct drm_framebuffer *fb = plane_state->hw.fb;
4096         int ret;
4097         bool needs_aux = false;
4098
4099         ret = intel_plane_compute_gtt(plane_state);
4100         if (ret)
4101                 return ret;
4102
4103         if (!plane_state->uapi.visible)
4104                 return 0;
4105
4106         /*
4107          * Handle the AUX surface first since the main surface setup depends on
4108          * it.
4109          */
4110         if (is_ccs_modifier(fb->modifier)) {
4111                 needs_aux = true;
4112                 ret = skl_check_ccs_aux_surface(plane_state);
4113                 if (ret)
4114                         return ret;
4115         }
4116
4117         if (intel_format_info_is_yuv_semiplanar(fb->format,
4118                                                 fb->modifier)) {
4119                 needs_aux = true;
4120                 ret = skl_check_nv12_aux_surface(plane_state);
4121                 if (ret)
4122                         return ret;
4123         }
4124
4125         if (!needs_aux) {
4126                 int i;
4127
4128                 for (i = 1; i < fb->format->num_planes; i++) {
4129                         plane_state->color_plane[i].offset = ~0xfff;
4130                         plane_state->color_plane[i].x = 0;
4131                         plane_state->color_plane[i].y = 0;
4132                 }
4133         }
4134
4135         ret = skl_check_main_surface(plane_state);
4136         if (ret)
4137                 return ret;
4138
4139         return 0;
4140 }
4141
4142 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4143                              const struct intel_plane_state *plane_state,
4144                              unsigned int *num, unsigned int *den)
4145 {
4146         const struct drm_framebuffer *fb = plane_state->hw.fb;
4147         unsigned int cpp = fb->format->cpp[0];
4148
4149         /*
4150          * g4x bspec says 64bpp pixel rate can't exceed 80%
4151          * of cdclk when the sprite plane is enabled on the
4152          * same pipe. ilk/snb bspec says 64bpp pixel rate is
4153          * never allowed to exceed 80% of cdclk. Let's just go
4154          * with the ilk/snb limit always.
4155          */
4156         if (cpp == 8) {
4157                 *num = 10;
4158                 *den = 8;
4159         } else {
4160                 *num = 1;
4161                 *den = 1;
4162         }
4163 }
4164
4165 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4166                                 const struct intel_plane_state *plane_state)
4167 {
4168         unsigned int pixel_rate;
4169         unsigned int num, den;
4170
4171         /*
4172          * Note that crtc_state->pixel_rate accounts for both
4173          * horizontal and vertical panel fitter downscaling factors.
4174          * Pre-HSW bspec tells us to only consider the horizontal
4175          * downscaling factor here. We ignore that and just consider
4176          * both for simplicity.
4177          */
4178         pixel_rate = crtc_state->pixel_rate;
4179
4180         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4181
4182         /* two pixels per clock with double wide pipe */
4183         if (crtc_state->double_wide)
4184                 den *= 2;
4185
4186         return DIV_ROUND_UP(pixel_rate * num, den);
4187 }
4188
4189 unsigned int
4190 i9xx_plane_max_stride(struct intel_plane *plane,
4191                       u32 pixel_format, u64 modifier,
4192                       unsigned int rotation)
4193 {
4194         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4195
4196         if (!HAS_GMCH(dev_priv)) {
4197                 return 32*1024;
4198         } else if (INTEL_GEN(dev_priv) >= 4) {
4199                 if (modifier == I915_FORMAT_MOD_X_TILED)
4200                         return 16*1024;
4201                 else
4202                         return 32*1024;
4203         } else if (INTEL_GEN(dev_priv) >= 3) {
4204                 if (modifier == I915_FORMAT_MOD_X_TILED)
4205                         return 8*1024;
4206                 else
4207                         return 16*1024;
4208         } else {
4209                 if (plane->i9xx_plane == PLANE_C)
4210                         return 4*1024;
4211                 else
4212                         return 8*1024;
4213         }
4214 }
4215
4216 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4217 {
4218         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4219         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4220         u32 dspcntr = 0;
4221
4222         if (crtc_state->gamma_enable)
4223                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4224
4225         if (crtc_state->csc_enable)
4226                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4227
4228         if (INTEL_GEN(dev_priv) < 5)
4229                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4230
4231         return dspcntr;
4232 }
4233
4234 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4235                           const struct intel_plane_state *plane_state)
4236 {
4237         struct drm_i915_private *dev_priv =
4238                 to_i915(plane_state->uapi.plane->dev);
4239         const struct drm_framebuffer *fb = plane_state->hw.fb;
4240         unsigned int rotation = plane_state->hw.rotation;
4241         u32 dspcntr;
4242
4243         dspcntr = DISPLAY_PLANE_ENABLE;
4244
4245         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4246             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4247                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4248
4249         switch (fb->format->format) {
4250         case DRM_FORMAT_C8:
4251                 dspcntr |= DISPPLANE_8BPP;
4252                 break;
4253         case DRM_FORMAT_XRGB1555:
4254                 dspcntr |= DISPPLANE_BGRX555;
4255                 break;
4256         case DRM_FORMAT_ARGB1555:
4257                 dspcntr |= DISPPLANE_BGRA555;
4258                 break;
4259         case DRM_FORMAT_RGB565:
4260                 dspcntr |= DISPPLANE_BGRX565;
4261                 break;
4262         case DRM_FORMAT_XRGB8888:
4263                 dspcntr |= DISPPLANE_BGRX888;
4264                 break;
4265         case DRM_FORMAT_XBGR8888:
4266                 dspcntr |= DISPPLANE_RGBX888;
4267                 break;
4268         case DRM_FORMAT_ARGB8888:
4269                 dspcntr |= DISPPLANE_BGRA888;
4270                 break;
4271         case DRM_FORMAT_ABGR8888:
4272                 dspcntr |= DISPPLANE_RGBA888;
4273                 break;
4274         case DRM_FORMAT_XRGB2101010:
4275                 dspcntr |= DISPPLANE_BGRX101010;
4276                 break;
4277         case DRM_FORMAT_XBGR2101010:
4278                 dspcntr |= DISPPLANE_RGBX101010;
4279                 break;
4280         case DRM_FORMAT_ARGB2101010:
4281                 dspcntr |= DISPPLANE_BGRA101010;
4282                 break;
4283         case DRM_FORMAT_ABGR2101010:
4284                 dspcntr |= DISPPLANE_RGBA101010;
4285                 break;
4286         case DRM_FORMAT_XBGR16161616F:
4287                 dspcntr |= DISPPLANE_RGBX161616;
4288                 break;
4289         default:
4290                 MISSING_CASE(fb->format->format);
4291                 return 0;
4292         }
4293
4294         if (INTEL_GEN(dev_priv) >= 4 &&
4295             fb->modifier == I915_FORMAT_MOD_X_TILED)
4296                 dspcntr |= DISPPLANE_TILED;
4297
4298         if (rotation & DRM_MODE_ROTATE_180)
4299                 dspcntr |= DISPPLANE_ROTATE_180;
4300
4301         if (rotation & DRM_MODE_REFLECT_X)
4302                 dspcntr |= DISPPLANE_MIRROR;
4303
4304         return dspcntr;
4305 }
4306
4307 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4308 {
4309         struct drm_i915_private *dev_priv =
4310                 to_i915(plane_state->uapi.plane->dev);
4311         const struct drm_framebuffer *fb = plane_state->hw.fb;
4312         int src_x, src_y, src_w;
4313         u32 offset;
4314         int ret;
4315
4316         ret = intel_plane_compute_gtt(plane_state);
4317         if (ret)
4318                 return ret;
4319
4320         if (!plane_state->uapi.visible)
4321                 return 0;
4322
4323         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4324         src_x = plane_state->uapi.src.x1 >> 16;
4325         src_y = plane_state->uapi.src.y1 >> 16;
4326
4327         /* Undocumented hardware limit on i965/g4x/vlv/chv */
4328         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4329                 return -EINVAL;
4330
4331         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4332
4333         if (INTEL_GEN(dev_priv) >= 4)
4334                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4335                                                             plane_state, 0);
4336         else
4337                 offset = 0;
4338
4339         /*
4340          * Put the final coordinates back so that the src
4341          * coordinate checks will see the right values.
4342          */
4343         drm_rect_translate_to(&plane_state->uapi.src,
4344                               src_x << 16, src_y << 16);
4345
4346         /* HSW/BDW do this automagically in hardware */
4347         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4348                 unsigned int rotation = plane_state->hw.rotation;
4349                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4350                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4351
4352                 if (rotation & DRM_MODE_ROTATE_180) {
4353                         src_x += src_w - 1;
4354                         src_y += src_h - 1;
4355                 } else if (rotation & DRM_MODE_REFLECT_X) {
4356                         src_x += src_w - 1;
4357                 }
4358         }
4359
4360         plane_state->color_plane[0].offset = offset;
4361         plane_state->color_plane[0].x = src_x;
4362         plane_state->color_plane[0].y = src_y;
4363
4364         return 0;
4365 }
4366
4367 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4368 {
4369         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4370         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4371
4372         if (IS_CHERRYVIEW(dev_priv))
4373                 return i9xx_plane == PLANE_B;
4374         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4375                 return false;
4376         else if (IS_GEN(dev_priv, 4))
4377                 return i9xx_plane == PLANE_C;
4378         else
4379                 return i9xx_plane == PLANE_B ||
4380                         i9xx_plane == PLANE_C;
4381 }
4382
4383 static int
4384 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4385                  struct intel_plane_state *plane_state)
4386 {
4387         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4388         int ret;
4389
4390         ret = chv_plane_check_rotation(plane_state);
4391         if (ret)
4392                 return ret;
4393
4394         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4395                                                   &crtc_state->uapi,
4396                                                   DRM_PLANE_HELPER_NO_SCALING,
4397                                                   DRM_PLANE_HELPER_NO_SCALING,
4398                                                   i9xx_plane_has_windowing(plane),
4399                                                   true);
4400         if (ret)
4401                 return ret;
4402
4403         ret = i9xx_check_plane_surface(plane_state);
4404         if (ret)
4405                 return ret;
4406
4407         if (!plane_state->uapi.visible)
4408                 return 0;
4409
4410         ret = intel_plane_check_src_coordinates(plane_state);
4411         if (ret)
4412                 return ret;
4413
4414         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4415
4416         return 0;
4417 }
4418
4419 static void i9xx_update_plane(struct intel_plane *plane,
4420                               const struct intel_crtc_state *crtc_state,
4421                               const struct intel_plane_state *plane_state)
4422 {
4423         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4424         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4425         u32 linear_offset;
4426         int x = plane_state->color_plane[0].x;
4427         int y = plane_state->color_plane[0].y;
4428         int crtc_x = plane_state->uapi.dst.x1;
4429         int crtc_y = plane_state->uapi.dst.y1;
4430         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4431         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4432         unsigned long irqflags;
4433         u32 dspaddr_offset;
4434         u32 dspcntr;
4435
4436         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4437
4438         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4439
4440         if (INTEL_GEN(dev_priv) >= 4)
4441                 dspaddr_offset = plane_state->color_plane[0].offset;
4442         else
4443                 dspaddr_offset = linear_offset;
4444
4445         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4446
4447         intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4448                           plane_state->color_plane[0].stride);
4449
4450         if (INTEL_GEN(dev_priv) < 4) {
4451                 /*
4452                  * PLANE_A doesn't actually have a full window
4453                  * generator but let's assume we still need to
4454                  * program whatever is there.
4455                  */
4456                 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4457                                   (crtc_y << 16) | crtc_x);
4458                 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4459                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4460         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4461                 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4462                                   (crtc_y << 16) | crtc_x);
4463                 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4464                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4465                 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4466         }
4467
4468         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4469                 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4470                                   (y << 16) | x);
4471         } else if (INTEL_GEN(dev_priv) >= 4) {
4472                 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4473                                   linear_offset);
4474                 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4475                                   (y << 16) | x);
4476         }
4477
4478         /*
4479          * The control register self-arms if the plane was previously
4480          * disabled. Try to make the plane enable atomic by writing
4481          * the control register just before the surface register.
4482          */
4483         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4484         if (INTEL_GEN(dev_priv) >= 4)
4485                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4486                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4487         else
4488                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4489                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4490
4491         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4492 }
4493
4494 static void i9xx_disable_plane(struct intel_plane *plane,
4495                                const struct intel_crtc_state *crtc_state)
4496 {
4497         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4498         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4499         unsigned long irqflags;
4500         u32 dspcntr;
4501
4502         /*
4503          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4504          * enable on ilk+ affect the pipe bottom color as
4505          * well, so we must configure them even if the plane
4506          * is disabled.
4507          *
4508          * On pre-g4x there is no way to gamma correct the
4509          * pipe bottom color but we'll keep on doing this
4510          * anyway so that the crtc state readout works correctly.
4511          */
4512         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4513
4514         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4515
4516         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4517         if (INTEL_GEN(dev_priv) >= 4)
4518                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4519         else
4520                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4521
4522         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4523 }
4524
4525 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4526                                     enum pipe *pipe)
4527 {
4528         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4529         enum intel_display_power_domain power_domain;
4530         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4531         intel_wakeref_t wakeref;
4532         bool ret;
4533         u32 val;
4534
4535         /*
4536          * Not 100% correct for planes that can move between pipes,
4537          * but that's only the case for gen2-4 which don't have any
4538          * display power wells.
4539          */
4540         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4541         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4542         if (!wakeref)
4543                 return false;
4544
4545         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4546
4547         ret = val & DISPLAY_PLANE_ENABLE;
4548
4549         if (INTEL_GEN(dev_priv) >= 5)
4550                 *pipe = plane->pipe;
4551         else
4552                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4553                         DISPPLANE_SEL_PIPE_SHIFT;
4554
4555         intel_display_power_put(dev_priv, power_domain, wakeref);
4556
4557         return ret;
4558 }
4559
4560 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4561 {
4562         struct drm_device *dev = intel_crtc->base.dev;
4563         struct drm_i915_private *dev_priv = to_i915(dev);
4564         unsigned long irqflags;
4565
4566         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4567
4568         intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4569         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4570         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4571
4572         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4573 }
4574
4575 /*
4576  * This function detaches (aka. unbinds) unused scalers in hardware
4577  */
4578 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4579 {
4580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4581         const struct intel_crtc_scaler_state *scaler_state =
4582                 &crtc_state->scaler_state;
4583         int i;
4584
4585         /* loop through and disable scalers that aren't in use */
4586         for (i = 0; i < intel_crtc->num_scalers; i++) {
4587                 if (!scaler_state->scalers[i].in_use)
4588                         skl_detach_scaler(intel_crtc, i);
4589         }
4590 }
4591
4592 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4593                                           int color_plane, unsigned int rotation)
4594 {
4595         /*
4596          * The stride is either expressed as a multiple of 64 bytes chunks for
4597          * linear buffers or in number of tiles for tiled buffers.
4598          */
4599         if (is_surface_linear(fb, color_plane))
4600                 return 64;
4601         else if (drm_rotation_90_or_270(rotation))
4602                 return intel_tile_height(fb, color_plane);
4603         else
4604                 return intel_tile_width_bytes(fb, color_plane);
4605 }
4606
4607 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4608                      int color_plane)
4609 {
4610         const struct drm_framebuffer *fb = plane_state->hw.fb;
4611         unsigned int rotation = plane_state->hw.rotation;
4612         u32 stride = plane_state->color_plane[color_plane].stride;
4613
4614         if (color_plane >= fb->format->num_planes)
4615                 return 0;
4616
4617         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4618 }
4619
4620 static u32 skl_plane_ctl_format(u32 pixel_format)
4621 {
4622         switch (pixel_format) {
4623         case DRM_FORMAT_C8:
4624                 return PLANE_CTL_FORMAT_INDEXED;
4625         case DRM_FORMAT_RGB565:
4626                 return PLANE_CTL_FORMAT_RGB_565;
4627         case DRM_FORMAT_XBGR8888:
4628         case DRM_FORMAT_ABGR8888:
4629                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4630         case DRM_FORMAT_XRGB8888:
4631         case DRM_FORMAT_ARGB8888:
4632                 return PLANE_CTL_FORMAT_XRGB_8888;
4633         case DRM_FORMAT_XBGR2101010:
4634         case DRM_FORMAT_ABGR2101010:
4635                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4636         case DRM_FORMAT_XRGB2101010:
4637         case DRM_FORMAT_ARGB2101010:
4638                 return PLANE_CTL_FORMAT_XRGB_2101010;
4639         case DRM_FORMAT_XBGR16161616F:
4640         case DRM_FORMAT_ABGR16161616F:
4641                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4642         case DRM_FORMAT_XRGB16161616F:
4643         case DRM_FORMAT_ARGB16161616F:
4644                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4645         case DRM_FORMAT_XYUV8888:
4646                 return PLANE_CTL_FORMAT_XYUV;
4647         case DRM_FORMAT_YUYV:
4648                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4649         case DRM_FORMAT_YVYU:
4650                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4651         case DRM_FORMAT_UYVY:
4652                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4653         case DRM_FORMAT_VYUY:
4654                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4655         case DRM_FORMAT_NV12:
4656                 return PLANE_CTL_FORMAT_NV12;
4657         case DRM_FORMAT_P010:
4658                 return PLANE_CTL_FORMAT_P010;
4659         case DRM_FORMAT_P012:
4660                 return PLANE_CTL_FORMAT_P012;
4661         case DRM_FORMAT_P016:
4662                 return PLANE_CTL_FORMAT_P016;
4663         case DRM_FORMAT_Y210:
4664                 return PLANE_CTL_FORMAT_Y210;
4665         case DRM_FORMAT_Y212:
4666                 return PLANE_CTL_FORMAT_Y212;
4667         case DRM_FORMAT_Y216:
4668                 return PLANE_CTL_FORMAT_Y216;
4669         case DRM_FORMAT_XVYU2101010:
4670                 return PLANE_CTL_FORMAT_Y410;
4671         case DRM_FORMAT_XVYU12_16161616:
4672                 return PLANE_CTL_FORMAT_Y412;
4673         case DRM_FORMAT_XVYU16161616:
4674                 return PLANE_CTL_FORMAT_Y416;
4675         default:
4676                 MISSING_CASE(pixel_format);
4677         }
4678
4679         return 0;
4680 }
4681
4682 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4683 {
4684         if (!plane_state->hw.fb->format->has_alpha)
4685                 return PLANE_CTL_ALPHA_DISABLE;
4686
4687         switch (plane_state->hw.pixel_blend_mode) {
4688         case DRM_MODE_BLEND_PIXEL_NONE:
4689                 return PLANE_CTL_ALPHA_DISABLE;
4690         case DRM_MODE_BLEND_PREMULTI:
4691                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4692         case DRM_MODE_BLEND_COVERAGE:
4693                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4694         default:
4695                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4696                 return PLANE_CTL_ALPHA_DISABLE;
4697         }
4698 }
4699
4700 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4701 {
4702         if (!plane_state->hw.fb->format->has_alpha)
4703                 return PLANE_COLOR_ALPHA_DISABLE;
4704
4705         switch (plane_state->hw.pixel_blend_mode) {
4706         case DRM_MODE_BLEND_PIXEL_NONE:
4707                 return PLANE_COLOR_ALPHA_DISABLE;
4708         case DRM_MODE_BLEND_PREMULTI:
4709                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4710         case DRM_MODE_BLEND_COVERAGE:
4711                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4712         default:
4713                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4714                 return PLANE_COLOR_ALPHA_DISABLE;
4715         }
4716 }
4717
4718 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4719 {
4720         switch (fb_modifier) {
4721         case DRM_FORMAT_MOD_LINEAR:
4722                 break;
4723         case I915_FORMAT_MOD_X_TILED:
4724                 return PLANE_CTL_TILED_X;
4725         case I915_FORMAT_MOD_Y_TILED:
4726                 return PLANE_CTL_TILED_Y;
4727         case I915_FORMAT_MOD_Y_TILED_CCS:
4728                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4729         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4730                 return PLANE_CTL_TILED_Y |
4731                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4732                        PLANE_CTL_CLEAR_COLOR_DISABLE;
4733         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4734                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4735         case I915_FORMAT_MOD_Yf_TILED:
4736                 return PLANE_CTL_TILED_YF;
4737         case I915_FORMAT_MOD_Yf_TILED_CCS:
4738                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4739         default:
4740                 MISSING_CASE(fb_modifier);
4741         }
4742
4743         return 0;
4744 }
4745
4746 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4747 {
4748         switch (rotate) {
4749         case DRM_MODE_ROTATE_0:
4750                 break;
4751         /*
4752          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4753          * while i915 HW rotation is clockwise, thats why this swapping.
4754          */
4755         case DRM_MODE_ROTATE_90:
4756                 return PLANE_CTL_ROTATE_270;
4757         case DRM_MODE_ROTATE_180:
4758                 return PLANE_CTL_ROTATE_180;
4759         case DRM_MODE_ROTATE_270:
4760                 return PLANE_CTL_ROTATE_90;
4761         default:
4762                 MISSING_CASE(rotate);
4763         }
4764
4765         return 0;
4766 }
4767
4768 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4769 {
4770         switch (reflect) {
4771         case 0:
4772                 break;
4773         case DRM_MODE_REFLECT_X:
4774                 return PLANE_CTL_FLIP_HORIZONTAL;
4775         case DRM_MODE_REFLECT_Y:
4776         default:
4777                 MISSING_CASE(reflect);
4778         }
4779
4780         return 0;
4781 }
4782
4783 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4784 {
4785         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4786         u32 plane_ctl = 0;
4787
4788         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4789                 return plane_ctl;
4790
4791         if (crtc_state->gamma_enable)
4792                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4793
4794         if (crtc_state->csc_enable)
4795                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4796
4797         return plane_ctl;
4798 }
4799
4800 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4801                   const struct intel_plane_state *plane_state)
4802 {
4803         struct drm_i915_private *dev_priv =
4804                 to_i915(plane_state->uapi.plane->dev);
4805         const struct drm_framebuffer *fb = plane_state->hw.fb;
4806         unsigned int rotation = plane_state->hw.rotation;
4807         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4808         u32 plane_ctl;
4809
4810         plane_ctl = PLANE_CTL_ENABLE;
4811
4812         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4813                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4814                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4815
4816                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4817                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4818
4819                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4820                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4821         }
4822
4823         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4824         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4825         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4826
4827         if (INTEL_GEN(dev_priv) >= 10)
4828                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4829                                                 DRM_MODE_REFLECT_MASK);
4830
4831         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4832                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4833         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4834                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4835
4836         return plane_ctl;
4837 }
4838
4839 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4840 {
4841         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4842         u32 plane_color_ctl = 0;
4843
4844         if (INTEL_GEN(dev_priv) >= 11)
4845                 return plane_color_ctl;
4846
4847         if (crtc_state->gamma_enable)
4848                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4849
4850         if (crtc_state->csc_enable)
4851                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4852
4853         return plane_color_ctl;
4854 }
4855
4856 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4857                         const struct intel_plane_state *plane_state)
4858 {
4859         struct drm_i915_private *dev_priv =
4860                 to_i915(plane_state->uapi.plane->dev);
4861         const struct drm_framebuffer *fb = plane_state->hw.fb;
4862         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4863         u32 plane_color_ctl = 0;
4864
4865         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4866         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4867
4868         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4869                 switch (plane_state->hw.color_encoding) {
4870                 case DRM_COLOR_YCBCR_BT709:
4871                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4872                         break;
4873                 case DRM_COLOR_YCBCR_BT2020:
4874                         plane_color_ctl |=
4875                                 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4876                         break;
4877                 default:
4878                         plane_color_ctl |=
4879                                 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4880                 }
4881                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4882                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4883         } else if (fb->format->is_yuv) {
4884                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4885         }
4886
4887         return plane_color_ctl;
4888 }
4889
4890 static int
4891 __intel_display_resume(struct drm_device *dev,
4892                        struct drm_atomic_state *state,
4893                        struct drm_modeset_acquire_ctx *ctx)
4894 {
4895         struct drm_crtc_state *crtc_state;
4896         struct drm_crtc *crtc;
4897         int i, ret;
4898
4899         intel_modeset_setup_hw_state(dev, ctx);
4900         intel_vga_redisable(to_i915(dev));
4901
4902         if (!state)
4903                 return 0;
4904
4905         /*
4906          * We've duplicated the state, pointers to the old state are invalid.
4907          *
4908          * Don't attempt to use the old state until we commit the duplicated state.
4909          */
4910         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4911                 /*
4912                  * Force recalculation even if we restore
4913                  * current state. With fast modeset this may not result
4914                  * in a modeset when the state is compatible.
4915                  */
4916                 crtc_state->mode_changed = true;
4917         }
4918
4919         /* ignore any reset values/BIOS leftovers in the WM registers */
4920         if (!HAS_GMCH(to_i915(dev)))
4921                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4922
4923         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4924
4925         drm_WARN_ON(dev, ret == -EDEADLK);
4926         return ret;
4927 }
4928
4929 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4930 {
4931         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4932                 intel_has_gpu_reset(&dev_priv->gt));
4933 }
4934
4935 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4936 {
4937         struct drm_device *dev = &dev_priv->drm;
4938         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4939         struct drm_atomic_state *state;
4940         int ret;
4941
4942         /* reset doesn't touch the display */
4943         if (!dev_priv->params.force_reset_modeset_test &&
4944             !gpu_reset_clobbers_display(dev_priv))
4945                 return;
4946
4947         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4948         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4949         smp_mb__after_atomic();
4950         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4951
4952         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4953                 drm_dbg_kms(&dev_priv->drm,
4954                             "Modeset potentially stuck, unbreaking through wedging\n");
4955                 intel_gt_set_wedged(&dev_priv->gt);
4956         }
4957
4958         /*
4959          * Need mode_config.mutex so that we don't
4960          * trample ongoing ->detect() and whatnot.
4961          */
4962         mutex_lock(&dev->mode_config.mutex);
4963         drm_modeset_acquire_init(ctx, 0);
4964         while (1) {
4965                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4966                 if (ret != -EDEADLK)
4967                         break;
4968
4969                 drm_modeset_backoff(ctx);
4970         }
4971         /*
4972          * Disabling the crtcs gracefully seems nicer. Also the
4973          * g33 docs say we should at least disable all the planes.
4974          */
4975         state = drm_atomic_helper_duplicate_state(dev, ctx);
4976         if (IS_ERR(state)) {
4977                 ret = PTR_ERR(state);
4978                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4979                         ret);
4980                 return;
4981         }
4982
4983         ret = drm_atomic_helper_disable_all(dev, ctx);
4984         if (ret) {
4985                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4986                         ret);
4987                 drm_atomic_state_put(state);
4988                 return;
4989         }
4990
4991         dev_priv->modeset_restore_state = state;
4992         state->acquire_ctx = ctx;
4993 }
4994
4995 void intel_finish_reset(struct drm_i915_private *dev_priv)
4996 {
4997         struct drm_device *dev = &dev_priv->drm;
4998         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4999         struct drm_atomic_state *state;
5000         int ret;
5001
5002         /* reset doesn't touch the display */
5003         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5004                 return;
5005
5006         state = fetch_and_zero(&dev_priv->modeset_restore_state);
5007         if (!state)
5008                 goto unlock;
5009
5010         /* reset doesn't touch the display */
5011         if (!gpu_reset_clobbers_display(dev_priv)) {
5012                 /* for testing only restore the display */
5013                 ret = __intel_display_resume(dev, state, ctx);
5014                 if (ret)
5015                         drm_err(&dev_priv->drm,
5016                                 "Restoring old state failed with %i\n", ret);
5017         } else {
5018                 /*
5019                  * The display has been reset as well,
5020                  * so need a full re-initialization.
5021                  */
5022                 intel_pps_unlock_regs_wa(dev_priv);
5023                 intel_modeset_init_hw(dev_priv);
5024                 intel_init_clock_gating(dev_priv);
5025
5026                 spin_lock_irq(&dev_priv->irq_lock);
5027                 if (dev_priv->display.hpd_irq_setup)
5028                         dev_priv->display.hpd_irq_setup(dev_priv);
5029                 spin_unlock_irq(&dev_priv->irq_lock);
5030
5031                 ret = __intel_display_resume(dev, state, ctx);
5032                 if (ret)
5033                         drm_err(&dev_priv->drm,
5034                                 "Restoring old state failed with %i\n", ret);
5035
5036                 intel_hpd_init(dev_priv);
5037         }
5038
5039         drm_atomic_state_put(state);
5040 unlock:
5041         drm_modeset_drop_locks(ctx);
5042         drm_modeset_acquire_fini(ctx);
5043         mutex_unlock(&dev->mode_config.mutex);
5044
5045         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5046 }
5047
5048 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5049 {
5050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5051         enum pipe pipe = crtc->pipe;
5052         u32 tmp;
5053
5054         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5055
5056         /*
5057          * Display WA #1153: icl
5058          * enable hardware to bypass the alpha math
5059          * and rounding for per-pixel values 00 and 0xff
5060          */
5061         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5062         /*
5063          * Display WA # 1605353570: icl
5064          * Set the pixel rounding bit to 1 for allowing
5065          * passthrough of Frame buffer pixels unmodified
5066          * across pipe
5067          */
5068         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5069         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5070 }
5071
5072 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5073 {
5074         struct drm_device *dev = crtc->base.dev;
5075         struct drm_i915_private *dev_priv = to_i915(dev);
5076         enum pipe pipe = crtc->pipe;
5077         i915_reg_t reg;
5078         u32 temp;
5079
5080         /* enable normal train */
5081         reg = FDI_TX_CTL(pipe);
5082         temp = intel_de_read(dev_priv, reg);
5083         if (IS_IVYBRIDGE(dev_priv)) {
5084                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5085                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5086         } else {
5087                 temp &= ~FDI_LINK_TRAIN_NONE;
5088                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5089         }
5090         intel_de_write(dev_priv, reg, temp);
5091
5092         reg = FDI_RX_CTL(pipe);
5093         temp = intel_de_read(dev_priv, reg);
5094         if (HAS_PCH_CPT(dev_priv)) {
5095                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5096                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5097         } else {
5098                 temp &= ~FDI_LINK_TRAIN_NONE;
5099                 temp |= FDI_LINK_TRAIN_NONE;
5100         }
5101         intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5102
5103         /* wait one idle pattern time */
5104         intel_de_posting_read(dev_priv, reg);
5105         udelay(1000);
5106
5107         /* IVB wants error correction enabled */
5108         if (IS_IVYBRIDGE(dev_priv))
5109                 intel_de_write(dev_priv, reg,
5110                                intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5111 }
5112
5113 /* The FDI link training functions for ILK/Ibexpeak. */
5114 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5115                                const struct intel_crtc_state *crtc_state)
5116 {
5117         struct drm_device *dev = crtc->base.dev;
5118         struct drm_i915_private *dev_priv = to_i915(dev);
5119         enum pipe pipe = crtc->pipe;
5120         i915_reg_t reg;
5121         u32 temp, tries;
5122
5123         /* FDI needs bits from pipe first */
5124         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5125
5126         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5127            for train result */
5128         reg = FDI_RX_IMR(pipe);
5129         temp = intel_de_read(dev_priv, reg);
5130         temp &= ~FDI_RX_SYMBOL_LOCK;
5131         temp &= ~FDI_RX_BIT_LOCK;
5132         intel_de_write(dev_priv, reg, temp);
5133         intel_de_read(dev_priv, reg);
5134         udelay(150);
5135
5136         /* enable CPU FDI TX and PCH FDI RX */
5137         reg = FDI_TX_CTL(pipe);
5138         temp = intel_de_read(dev_priv, reg);
5139         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5140         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5141         temp &= ~FDI_LINK_TRAIN_NONE;
5142         temp |= FDI_LINK_TRAIN_PATTERN_1;
5143         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5144
5145         reg = FDI_RX_CTL(pipe);
5146         temp = intel_de_read(dev_priv, reg);
5147         temp &= ~FDI_LINK_TRAIN_NONE;
5148         temp |= FDI_LINK_TRAIN_PATTERN_1;
5149         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5150
5151         intel_de_posting_read(dev_priv, reg);
5152         udelay(150);
5153
5154         /* Ironlake workaround, enable clock pointer after FDI enable*/
5155         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5156                        FDI_RX_PHASE_SYNC_POINTER_OVR);
5157         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5158                        FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5159
5160         reg = FDI_RX_IIR(pipe);
5161         for (tries = 0; tries < 5; tries++) {
5162                 temp = intel_de_read(dev_priv, reg);
5163                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5164
5165                 if ((temp & FDI_RX_BIT_LOCK)) {
5166                         drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5167                         intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5168                         break;
5169                 }
5170         }
5171         if (tries == 5)
5172                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5173
5174         /* Train 2 */
5175         reg = FDI_TX_CTL(pipe);
5176         temp = intel_de_read(dev_priv, reg);
5177         temp &= ~FDI_LINK_TRAIN_NONE;
5178         temp |= FDI_LINK_TRAIN_PATTERN_2;
5179         intel_de_write(dev_priv, reg, temp);
5180
5181         reg = FDI_RX_CTL(pipe);
5182         temp = intel_de_read(dev_priv, reg);
5183         temp &= ~FDI_LINK_TRAIN_NONE;
5184         temp |= FDI_LINK_TRAIN_PATTERN_2;
5185         intel_de_write(dev_priv, reg, temp);
5186
5187         intel_de_posting_read(dev_priv, reg);
5188         udelay(150);
5189
5190         reg = FDI_RX_IIR(pipe);
5191         for (tries = 0; tries < 5; tries++) {
5192                 temp = intel_de_read(dev_priv, reg);
5193                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5194
5195                 if (temp & FDI_RX_SYMBOL_LOCK) {
5196                         intel_de_write(dev_priv, reg,
5197                                        temp | FDI_RX_SYMBOL_LOCK);
5198                         drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5199                         break;
5200                 }
5201         }
5202         if (tries == 5)
5203                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5204
5205         drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5206
5207 }
5208
5209 static const int snb_b_fdi_train_param[] = {
5210         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5211         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5212         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5213         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5214 };
5215
5216 /* The FDI link training functions for SNB/Cougarpoint. */
5217 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5218                                 const struct intel_crtc_state *crtc_state)
5219 {
5220         struct drm_device *dev = crtc->base.dev;
5221         struct drm_i915_private *dev_priv = to_i915(dev);
5222         enum pipe pipe = crtc->pipe;
5223         i915_reg_t reg;
5224         u32 temp, i, retry;
5225
5226         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5227            for train result */
5228         reg = FDI_RX_IMR(pipe);
5229         temp = intel_de_read(dev_priv, reg);
5230         temp &= ~FDI_RX_SYMBOL_LOCK;
5231         temp &= ~FDI_RX_BIT_LOCK;
5232         intel_de_write(dev_priv, reg, temp);
5233
5234         intel_de_posting_read(dev_priv, reg);
5235         udelay(150);
5236
5237         /* enable CPU FDI TX and PCH FDI RX */
5238         reg = FDI_TX_CTL(pipe);
5239         temp = intel_de_read(dev_priv, reg);
5240         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5241         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5242         temp &= ~FDI_LINK_TRAIN_NONE;
5243         temp |= FDI_LINK_TRAIN_PATTERN_1;
5244         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5245         /* SNB-B */
5246         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5247         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5248
5249         intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5250                        FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5251
5252         reg = FDI_RX_CTL(pipe);
5253         temp = intel_de_read(dev_priv, reg);
5254         if (HAS_PCH_CPT(dev_priv)) {
5255                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5256                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5257         } else {
5258                 temp &= ~FDI_LINK_TRAIN_NONE;
5259                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5260         }
5261         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5262
5263         intel_de_posting_read(dev_priv, reg);
5264         udelay(150);
5265
5266         for (i = 0; i < 4; i++) {
5267                 reg = FDI_TX_CTL(pipe);
5268                 temp = intel_de_read(dev_priv, reg);
5269                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5270                 temp |= snb_b_fdi_train_param[i];
5271                 intel_de_write(dev_priv, reg, temp);
5272
5273                 intel_de_posting_read(dev_priv, reg);
5274                 udelay(500);
5275
5276                 for (retry = 0; retry < 5; retry++) {
5277                         reg = FDI_RX_IIR(pipe);
5278                         temp = intel_de_read(dev_priv, reg);
5279                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5280                         if (temp & FDI_RX_BIT_LOCK) {
5281                                 intel_de_write(dev_priv, reg,
5282                                                temp | FDI_RX_BIT_LOCK);
5283                                 drm_dbg_kms(&dev_priv->drm,
5284                                             "FDI train 1 done.\n");
5285                                 break;
5286                         }
5287                         udelay(50);
5288                 }
5289                 if (retry < 5)
5290                         break;
5291         }
5292         if (i == 4)
5293                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5294
5295         /* Train 2 */
5296         reg = FDI_TX_CTL(pipe);
5297         temp = intel_de_read(dev_priv, reg);
5298         temp &= ~FDI_LINK_TRAIN_NONE;
5299         temp |= FDI_LINK_TRAIN_PATTERN_2;
5300         if (IS_GEN(dev_priv, 6)) {
5301                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5302                 /* SNB-B */
5303                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5304         }
5305         intel_de_write(dev_priv, reg, temp);
5306
5307         reg = FDI_RX_CTL(pipe);
5308         temp = intel_de_read(dev_priv, reg);
5309         if (HAS_PCH_CPT(dev_priv)) {
5310                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5311                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5312         } else {
5313                 temp &= ~FDI_LINK_TRAIN_NONE;
5314                 temp |= FDI_LINK_TRAIN_PATTERN_2;
5315         }
5316         intel_de_write(dev_priv, reg, temp);
5317
5318         intel_de_posting_read(dev_priv, reg);
5319         udelay(150);
5320
5321         for (i = 0; i < 4; i++) {
5322                 reg = FDI_TX_CTL(pipe);
5323                 temp = intel_de_read(dev_priv, reg);
5324                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5325                 temp |= snb_b_fdi_train_param[i];
5326                 intel_de_write(dev_priv, reg, temp);
5327
5328                 intel_de_posting_read(dev_priv, reg);
5329                 udelay(500);
5330
5331                 for (retry = 0; retry < 5; retry++) {
5332                         reg = FDI_RX_IIR(pipe);
5333                         temp = intel_de_read(dev_priv, reg);
5334                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5335                         if (temp & FDI_RX_SYMBOL_LOCK) {
5336                                 intel_de_write(dev_priv, reg,
5337                                                temp | FDI_RX_SYMBOL_LOCK);
5338                                 drm_dbg_kms(&dev_priv->drm,
5339                                             "FDI train 2 done.\n");
5340                                 break;
5341                         }
5342                         udelay(50);
5343                 }
5344                 if (retry < 5)
5345                         break;
5346         }
5347         if (i == 4)
5348                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5349
5350         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5351 }
5352
5353 /* Manual link training for Ivy Bridge A0 parts */
5354 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5355                                       const struct intel_crtc_state *crtc_state)
5356 {
5357         struct drm_device *dev = crtc->base.dev;
5358         struct drm_i915_private *dev_priv = to_i915(dev);
5359         enum pipe pipe = crtc->pipe;
5360         i915_reg_t reg;
5361         u32 temp, i, j;
5362
5363         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5364            for train result */
5365         reg = FDI_RX_IMR(pipe);
5366         temp = intel_de_read(dev_priv, reg);
5367         temp &= ~FDI_RX_SYMBOL_LOCK;
5368         temp &= ~FDI_RX_BIT_LOCK;
5369         intel_de_write(dev_priv, reg, temp);
5370
5371         intel_de_posting_read(dev_priv, reg);
5372         udelay(150);
5373
5374         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5375                     intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5376
5377         /* Try each vswing and preemphasis setting twice before moving on */
5378         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5379                 /* disable first in case we need to retry */
5380                 reg = FDI_TX_CTL(pipe);
5381                 temp = intel_de_read(dev_priv, reg);
5382                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5383                 temp &= ~FDI_TX_ENABLE;
5384                 intel_de_write(dev_priv, reg, temp);
5385
5386                 reg = FDI_RX_CTL(pipe);
5387                 temp = intel_de_read(dev_priv, reg);
5388                 temp &= ~FDI_LINK_TRAIN_AUTO;
5389                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5390                 temp &= ~FDI_RX_ENABLE;
5391                 intel_de_write(dev_priv, reg, temp);
5392
5393                 /* enable CPU FDI TX and PCH FDI RX */
5394                 reg = FDI_TX_CTL(pipe);
5395                 temp = intel_de_read(dev_priv, reg);
5396                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5397                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5398                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5399                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5400                 temp |= snb_b_fdi_train_param[j/2];
5401                 temp |= FDI_COMPOSITE_SYNC;
5402                 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5403
5404                 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5405                                FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5406
5407                 reg = FDI_RX_CTL(pipe);
5408                 temp = intel_de_read(dev_priv, reg);
5409                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5410                 temp |= FDI_COMPOSITE_SYNC;
5411                 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5412
5413                 intel_de_posting_read(dev_priv, reg);
5414                 udelay(1); /* should be 0.5us */
5415
5416                 for (i = 0; i < 4; i++) {
5417                         reg = FDI_RX_IIR(pipe);
5418                         temp = intel_de_read(dev_priv, reg);
5419                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5420
5421                         if (temp & FDI_RX_BIT_LOCK ||
5422                             (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5423                                 intel_de_write(dev_priv, reg,
5424                                                temp | FDI_RX_BIT_LOCK);
5425                                 drm_dbg_kms(&dev_priv->drm,
5426                                             "FDI train 1 done, level %i.\n",
5427                                             i);
5428                                 break;
5429                         }
5430                         udelay(1); /* should be 0.5us */
5431                 }
5432                 if (i == 4) {
5433                         drm_dbg_kms(&dev_priv->drm,
5434                                     "FDI train 1 fail on vswing %d\n", j / 2);
5435                         continue;
5436                 }
5437
5438                 /* Train 2 */
5439                 reg = FDI_TX_CTL(pipe);
5440                 temp = intel_de_read(dev_priv, reg);
5441                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5442                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5443                 intel_de_write(dev_priv, reg, temp);
5444
5445                 reg = FDI_RX_CTL(pipe);
5446                 temp = intel_de_read(dev_priv, reg);
5447                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5448                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5449                 intel_de_write(dev_priv, reg, temp);
5450
5451                 intel_de_posting_read(dev_priv, reg);
5452                 udelay(2); /* should be 1.5us */
5453
5454                 for (i = 0; i < 4; i++) {
5455                         reg = FDI_RX_IIR(pipe);
5456                         temp = intel_de_read(dev_priv, reg);
5457                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5458
5459                         if (temp & FDI_RX_SYMBOL_LOCK ||
5460                             (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5461                                 intel_de_write(dev_priv, reg,
5462                                                temp | FDI_RX_SYMBOL_LOCK);
5463                                 drm_dbg_kms(&dev_priv->drm,
5464                                             "FDI train 2 done, level %i.\n",
5465                                             i);
5466                                 goto train_done;
5467                         }
5468                         udelay(2); /* should be 1.5us */
5469                 }
5470                 if (i == 4)
5471                         drm_dbg_kms(&dev_priv->drm,
5472                                     "FDI train 2 fail on vswing %d\n", j / 2);
5473         }
5474
5475 train_done:
5476         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5477 }
5478
5479 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5480 {
5481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5482         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5483         enum pipe pipe = intel_crtc->pipe;
5484         i915_reg_t reg;
5485         u32 temp;
5486
5487         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5488         reg = FDI_RX_CTL(pipe);
5489         temp = intel_de_read(dev_priv, reg);
5490         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5491         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5492         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5493         intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5494
5495         intel_de_posting_read(dev_priv, reg);
5496         udelay(200);
5497
5498         /* Switch from Rawclk to PCDclk */
5499         temp = intel_de_read(dev_priv, reg);
5500         intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5501
5502         intel_de_posting_read(dev_priv, reg);
5503         udelay(200);
5504
5505         /* Enable CPU FDI TX PLL, always on for Ironlake */
5506         reg = FDI_TX_CTL(pipe);
5507         temp = intel_de_read(dev_priv, reg);
5508         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5509                 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5510
5511                 intel_de_posting_read(dev_priv, reg);
5512                 udelay(100);
5513         }
5514 }
5515
5516 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5517 {
5518         struct drm_device *dev = intel_crtc->base.dev;
5519         struct drm_i915_private *dev_priv = to_i915(dev);
5520         enum pipe pipe = intel_crtc->pipe;
5521         i915_reg_t reg;
5522         u32 temp;
5523
5524         /* Switch from PCDclk to Rawclk */
5525         reg = FDI_RX_CTL(pipe);
5526         temp = intel_de_read(dev_priv, reg);
5527         intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5528
5529         /* Disable CPU FDI TX PLL */
5530         reg = FDI_TX_CTL(pipe);
5531         temp = intel_de_read(dev_priv, reg);
5532         intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5533
5534         intel_de_posting_read(dev_priv, reg);
5535         udelay(100);
5536
5537         reg = FDI_RX_CTL(pipe);
5538         temp = intel_de_read(dev_priv, reg);
5539         intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5540
5541         /* Wait for the clocks to turn off. */
5542         intel_de_posting_read(dev_priv, reg);
5543         udelay(100);
5544 }
5545
5546 static void ilk_fdi_disable(struct intel_crtc *crtc)
5547 {
5548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5549         enum pipe pipe = crtc->pipe;
5550         i915_reg_t reg;
5551         u32 temp;
5552
5553         /* disable CPU FDI tx and PCH FDI rx */
5554         reg = FDI_TX_CTL(pipe);
5555         temp = intel_de_read(dev_priv, reg);
5556         intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5557         intel_de_posting_read(dev_priv, reg);
5558
5559         reg = FDI_RX_CTL(pipe);
5560         temp = intel_de_read(dev_priv, reg);
5561         temp &= ~(0x7 << 16);
5562         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5563         intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5564
5565         intel_de_posting_read(dev_priv, reg);
5566         udelay(100);
5567
5568         /* Ironlake workaround, disable clock pointer after downing FDI */
5569         if (HAS_PCH_IBX(dev_priv))
5570                 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5571                                FDI_RX_PHASE_SYNC_POINTER_OVR);
5572
5573         /* still set train pattern 1 */
5574         reg = FDI_TX_CTL(pipe);
5575         temp = intel_de_read(dev_priv, reg);
5576         temp &= ~FDI_LINK_TRAIN_NONE;
5577         temp |= FDI_LINK_TRAIN_PATTERN_1;
5578         intel_de_write(dev_priv, reg, temp);
5579
5580         reg = FDI_RX_CTL(pipe);
5581         temp = intel_de_read(dev_priv, reg);
5582         if (HAS_PCH_CPT(dev_priv)) {
5583                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5584                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5585         } else {
5586                 temp &= ~FDI_LINK_TRAIN_NONE;
5587                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5588         }
5589         /* BPC in FDI rx is consistent with that in PIPECONF */
5590         temp &= ~(0x07 << 16);
5591         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5592         intel_de_write(dev_priv, reg, temp);
5593
5594         intel_de_posting_read(dev_priv, reg);
5595         udelay(100);
5596 }
5597
5598 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5599 {
5600         struct drm_crtc *crtc;
5601         bool cleanup_done;
5602
5603         drm_for_each_crtc(crtc, &dev_priv->drm) {
5604                 struct drm_crtc_commit *commit;
5605                 spin_lock(&crtc->commit_lock);
5606                 commit = list_first_entry_or_null(&crtc->commit_list,
5607                                                   struct drm_crtc_commit, commit_entry);
5608                 cleanup_done = commit ?
5609                         try_wait_for_completion(&commit->cleanup_done) : true;
5610                 spin_unlock(&crtc->commit_lock);
5611
5612                 if (cleanup_done)
5613                         continue;
5614
5615                 drm_crtc_wait_one_vblank(crtc);
5616
5617                 return true;
5618         }
5619
5620         return false;
5621 }
5622
5623 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5624 {
5625         u32 temp;
5626
5627         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5628
5629         mutex_lock(&dev_priv->sb_lock);
5630
5631         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5632         temp |= SBI_SSCCTL_DISABLE;
5633         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5634
5635         mutex_unlock(&dev_priv->sb_lock);
5636 }
5637
5638 /* Program iCLKIP clock to the desired frequency */
5639 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5640 {
5641         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5642         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5643         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5644         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5645         u32 temp;
5646
5647         lpt_disable_iclkip(dev_priv);
5648
5649         /* The iCLK virtual clock root frequency is in MHz,
5650          * but the adjusted_mode->crtc_clock in in KHz. To get the
5651          * divisors, it is necessary to divide one by another, so we
5652          * convert the virtual clock precision to KHz here for higher
5653          * precision.
5654          */
5655         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5656                 u32 iclk_virtual_root_freq = 172800 * 1000;
5657                 u32 iclk_pi_range = 64;
5658                 u32 desired_divisor;
5659
5660                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5661                                                     clock << auxdiv);
5662                 divsel = (desired_divisor / iclk_pi_range) - 2;
5663                 phaseinc = desired_divisor % iclk_pi_range;
5664
5665                 /*
5666                  * Near 20MHz is a corner case which is
5667                  * out of range for the 7-bit divisor
5668                  */
5669                 if (divsel <= 0x7f)
5670                         break;
5671         }
5672
5673         /* This should not happen with any sane values */
5674         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5675                     ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5676         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5677                     ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5678
5679         drm_dbg_kms(&dev_priv->drm,
5680                     "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5681                     clock, auxdiv, divsel, phasedir, phaseinc);
5682
5683         mutex_lock(&dev_priv->sb_lock);
5684
5685         /* Program SSCDIVINTPHASE6 */
5686         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5687         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5688         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5689         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5690         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5691         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5692         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5693         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5694
5695         /* Program SSCAUXDIV */
5696         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5697         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5698         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5699         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5700
5701         /* Enable modulator and associated divider */
5702         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5703         temp &= ~SBI_SSCCTL_DISABLE;
5704         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5705
5706         mutex_unlock(&dev_priv->sb_lock);
5707
5708         /* Wait for initialization time */
5709         udelay(24);
5710
5711         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5712 }
5713
5714 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5715 {
5716         u32 divsel, phaseinc, auxdiv;
5717         u32 iclk_virtual_root_freq = 172800 * 1000;
5718         u32 iclk_pi_range = 64;
5719         u32 desired_divisor;
5720         u32 temp;
5721
5722         if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5723                 return 0;
5724
5725         mutex_lock(&dev_priv->sb_lock);
5726
5727         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5728         if (temp & SBI_SSCCTL_DISABLE) {
5729                 mutex_unlock(&dev_priv->sb_lock);
5730                 return 0;
5731         }
5732
5733         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5734         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5735                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5736         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5737                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5738
5739         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5740         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5741                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5742
5743         mutex_unlock(&dev_priv->sb_lock);
5744
5745         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5746
5747         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5748                                  desired_divisor << auxdiv);
5749 }
5750
5751 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5752                                            enum pipe pch_transcoder)
5753 {
5754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5756         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5757
5758         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5759                        intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5760         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5761                        intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5762         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5763                        intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5764
5765         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5766                        intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5767         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5768                        intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5769         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5770                        intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5771         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5772                        intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5773 }
5774
5775 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5776 {
5777         u32 temp;
5778
5779         temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5780         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5781                 return;
5782
5783         drm_WARN_ON(&dev_priv->drm,
5784                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5785                     FDI_RX_ENABLE);
5786         drm_WARN_ON(&dev_priv->drm,
5787                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5788                     FDI_RX_ENABLE);
5789
5790         temp &= ~FDI_BC_BIFURCATION_SELECT;
5791         if (enable)
5792                 temp |= FDI_BC_BIFURCATION_SELECT;
5793
5794         drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5795                     enable ? "en" : "dis");
5796         intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5797         intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5798 }
5799
5800 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5801 {
5802         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5803         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5804
5805         switch (crtc->pipe) {
5806         case PIPE_A:
5807                 break;
5808         case PIPE_B:
5809                 if (crtc_state->fdi_lanes > 2)
5810                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5811                 else
5812                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5813
5814                 break;
5815         case PIPE_C:
5816                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5817
5818                 break;
5819         default:
5820                 BUG();
5821         }
5822 }
5823
5824 /*
5825  * Finds the encoder associated with the given CRTC. This can only be
5826  * used when we know that the CRTC isn't feeding multiple encoders!
5827  */
5828 static struct intel_encoder *
5829 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5830                            const struct intel_crtc_state *crtc_state)
5831 {
5832         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5833         const struct drm_connector_state *connector_state;
5834         const struct drm_connector *connector;
5835         struct intel_encoder *encoder = NULL;
5836         int num_encoders = 0;
5837         int i;
5838
5839         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5840                 if (connector_state->crtc != &crtc->base)
5841                         continue;
5842
5843                 encoder = to_intel_encoder(connector_state->best_encoder);
5844                 num_encoders++;
5845         }
5846
5847         drm_WARN(encoder->base.dev, num_encoders != 1,
5848                  "%d encoders for pipe %c\n",
5849                  num_encoders, pipe_name(crtc->pipe));
5850
5851         return encoder;
5852 }
5853
5854 /*
5855  * Enable PCH resources required for PCH ports:
5856  *   - PCH PLLs
5857  *   - FDI training & RX/TX
5858  *   - update transcoder timings
5859  *   - DP transcoding bits
5860  *   - transcoder
5861  */
5862 static void ilk_pch_enable(const struct intel_atomic_state *state,
5863                            const struct intel_crtc_state *crtc_state)
5864 {
5865         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5866         struct drm_device *dev = crtc->base.dev;
5867         struct drm_i915_private *dev_priv = to_i915(dev);
5868         enum pipe pipe = crtc->pipe;
5869         u32 temp;
5870
5871         assert_pch_transcoder_disabled(dev_priv, pipe);
5872
5873         if (IS_IVYBRIDGE(dev_priv))
5874                 ivb_update_fdi_bc_bifurcation(crtc_state);
5875
5876         /* Write the TU size bits before fdi link training, so that error
5877          * detection works. */
5878         intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5879                        intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5880
5881         /* For PCH output, training FDI link */
5882         dev_priv->display.fdi_link_train(crtc, crtc_state);
5883
5884         /* We need to program the right clock selection before writing the pixel
5885          * mutliplier into the DPLL. */
5886         if (HAS_PCH_CPT(dev_priv)) {
5887                 u32 sel;
5888
5889                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5890                 temp |= TRANS_DPLL_ENABLE(pipe);
5891                 sel = TRANS_DPLLB_SEL(pipe);
5892                 if (crtc_state->shared_dpll ==
5893                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5894                         temp |= sel;
5895                 else
5896                         temp &= ~sel;
5897                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5898         }
5899
5900         /* XXX: pch pll's can be enabled any time before we enable the PCH
5901          * transcoder, and we actually should do this to not upset any PCH
5902          * transcoder that already use the clock when we share it.
5903          *
5904          * Note that enable_shared_dpll tries to do the right thing, but
5905          * get_shared_dpll unconditionally resets the pll - we need that to have
5906          * the right LVDS enable sequence. */
5907         intel_enable_shared_dpll(crtc_state);
5908
5909         /* set transcoder timing, panel must allow it */
5910         assert_panel_unlocked(dev_priv, pipe);
5911         ilk_pch_transcoder_set_timings(crtc_state, pipe);
5912
5913         intel_fdi_normal_train(crtc);
5914
5915         /* For PCH DP, enable TRANS_DP_CTL */
5916         if (HAS_PCH_CPT(dev_priv) &&
5917             intel_crtc_has_dp_encoder(crtc_state)) {
5918                 const struct drm_display_mode *adjusted_mode =
5919                         &crtc_state->hw.adjusted_mode;
5920                 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5921                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5922                 enum port port;
5923
5924                 temp = intel_de_read(dev_priv, reg);
5925                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5926                           TRANS_DP_SYNC_MASK |
5927                           TRANS_DP_BPC_MASK);
5928                 temp |= TRANS_DP_OUTPUT_ENABLE;
5929                 temp |= bpc << 9; /* same format but at 11:9 */
5930
5931                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5932                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5933                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5934                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5935
5936                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5937                 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5938                 temp |= TRANS_DP_PORT_SEL(port);
5939
5940                 intel_de_write(dev_priv, reg, temp);
5941         }
5942
5943         ilk_enable_pch_transcoder(crtc_state);
5944 }
5945
5946 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5947 {
5948         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5949         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5950         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5951
5952         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5953
5954         lpt_program_iclkip(crtc_state);
5955
5956         /* Set transcoder timing. */
5957         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5958
5959         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5960 }
5961
5962 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5963                                enum pipe pipe)
5964 {
5965         i915_reg_t dslreg = PIPEDSL(pipe);
5966         u32 temp;
5967
5968         temp = intel_de_read(dev_priv, dslreg);
5969         udelay(500);
5970         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5971                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5972                         drm_err(&dev_priv->drm,
5973                                 "mode set failed: pipe %c stuck\n",
5974                                 pipe_name(pipe));
5975         }
5976 }
5977
5978 /*
5979  * The hardware phase 0.0 refers to the center of the pixel.
5980  * We want to start from the top/left edge which is phase
5981  * -0.5. That matches how the hardware calculates the scaling
5982  * factors (from top-left of the first pixel to bottom-right
5983  * of the last pixel, as opposed to the pixel centers).
5984  *
5985  * For 4:2:0 subsampled chroma planes we obviously have to
5986  * adjust that so that the chroma sample position lands in
5987  * the right spot.
5988  *
5989  * Note that for packed YCbCr 4:2:2 formats there is no way to
5990  * control chroma siting. The hardware simply replicates the
5991  * chroma samples for both of the luma samples, and thus we don't
5992  * actually get the expected MPEG2 chroma siting convention :(
5993  * The same behaviour is observed on pre-SKL platforms as well.
5994  *
5995  * Theory behind the formula (note that we ignore sub-pixel
5996  * source coordinates):
5997  * s = source sample position
5998  * d = destination sample position
5999  *
6000  * Downscaling 4:1:
6001  * -0.5
6002  * | 0.0
6003  * | |     1.5 (initial phase)
6004  * | |     |
6005  * v v     v
6006  * | s | s | s | s |
6007  * |       d       |
6008  *
6009  * Upscaling 1:4:
6010  * -0.5
6011  * | -0.375 (initial phase)
6012  * | |     0.0
6013  * | |     |
6014  * v v     v
6015  * |       s       |
6016  * | d | d | d | d |
6017  */
6018 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6019 {
6020         int phase = -0x8000;
6021         u16 trip = 0;
6022
6023         if (chroma_cosited)
6024                 phase += (sub - 1) * 0x8000 / sub;
6025
6026         phase += scale / (2 * sub);
6027
6028         /*
6029          * Hardware initial phase limited to [-0.5:1.5].
6030          * Since the max hardware scale factor is 3.0, we
6031          * should never actually excdeed 1.0 here.
6032          */
6033         WARN_ON(phase < -0x8000 || phase > 0x18000);
6034
6035         if (phase < 0)
6036                 phase = 0x10000 + phase;
6037         else
6038                 trip = PS_PHASE_TRIP;
6039
6040         return ((phase >> 2) & PS_PHASE_MASK) | trip;
6041 }
6042
6043 #define SKL_MIN_SRC_W 8
6044 #define SKL_MAX_SRC_W 4096
6045 #define SKL_MIN_SRC_H 8
6046 #define SKL_MAX_SRC_H 4096
6047 #define SKL_MIN_DST_W 8
6048 #define SKL_MAX_DST_W 4096
6049 #define SKL_MIN_DST_H 8
6050 #define SKL_MAX_DST_H 4096
6051 #define ICL_MAX_SRC_W 5120
6052 #define ICL_MAX_SRC_H 4096
6053 #define ICL_MAX_DST_W 5120
6054 #define ICL_MAX_DST_H 4096
6055 #define SKL_MIN_YUV_420_SRC_W 16
6056 #define SKL_MIN_YUV_420_SRC_H 16
6057
6058 static int
6059 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6060                   unsigned int scaler_user, int *scaler_id,
6061                   int src_w, int src_h, int dst_w, int dst_h,
6062                   const struct drm_format_info *format,
6063                   u64 modifier, bool need_scaler)
6064 {
6065         struct intel_crtc_scaler_state *scaler_state =
6066                 &crtc_state->scaler_state;
6067         struct intel_crtc *intel_crtc =
6068                 to_intel_crtc(crtc_state->uapi.crtc);
6069         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6070         const struct drm_display_mode *adjusted_mode =
6071                 &crtc_state->hw.adjusted_mode;
6072
6073         /*
6074          * Src coordinates are already rotated by 270 degrees for
6075          * the 90/270 degree plane rotation cases (to match the
6076          * GTT mapping), hence no need to account for rotation here.
6077          */
6078         if (src_w != dst_w || src_h != dst_h)
6079                 need_scaler = true;
6080
6081         /*
6082          * Scaling/fitting not supported in IF-ID mode in GEN9+
6083          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6084          * Once NV12 is enabled, handle it here while allocating scaler
6085          * for NV12.
6086          */
6087         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6088             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6089                 drm_dbg_kms(&dev_priv->drm,
6090                             "Pipe/Plane scaling not supported with IF-ID mode\n");
6091                 return -EINVAL;
6092         }
6093
6094         /*
6095          * if plane is being disabled or scaler is no more required or force detach
6096          *  - free scaler binded to this plane/crtc
6097          *  - in order to do this, update crtc->scaler_usage
6098          *
6099          * Here scaler state in crtc_state is set free so that
6100          * scaler can be assigned to other user. Actual register
6101          * update to free the scaler is done in plane/panel-fit programming.
6102          * For this purpose crtc/plane_state->scaler_id isn't reset here.
6103          */
6104         if (force_detach || !need_scaler) {
6105                 if (*scaler_id >= 0) {
6106                         scaler_state->scaler_users &= ~(1 << scaler_user);
6107                         scaler_state->scalers[*scaler_id].in_use = 0;
6108
6109                         drm_dbg_kms(&dev_priv->drm,
6110                                     "scaler_user index %u.%u: "
6111                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
6112                                     intel_crtc->pipe, scaler_user, *scaler_id,
6113                                     scaler_state->scaler_users);
6114                         *scaler_id = -1;
6115                 }
6116                 return 0;
6117         }
6118
6119         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6120             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6121                 drm_dbg_kms(&dev_priv->drm,
6122                             "Planar YUV: src dimensions not met\n");
6123                 return -EINVAL;
6124         }
6125
6126         /* range checks */
6127         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6128             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6129             (INTEL_GEN(dev_priv) >= 11 &&
6130              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6131               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6132             (INTEL_GEN(dev_priv) < 11 &&
6133              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6134               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6135                 drm_dbg_kms(&dev_priv->drm,
6136                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
6137                             "size is out of scaler range\n",
6138                             intel_crtc->pipe, scaler_user, src_w, src_h,
6139                             dst_w, dst_h);
6140                 return -EINVAL;
6141         }
6142
6143         /* mark this plane as a scaler user in crtc_state */
6144         scaler_state->scaler_users |= (1 << scaler_user);
6145         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6146                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6147                     intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6148                     scaler_state->scaler_users);
6149
6150         return 0;
6151 }
6152
6153 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6154 {
6155         const struct drm_display_mode *adjusted_mode =
6156                 &crtc_state->hw.adjusted_mode;
6157         int width, height;
6158
6159         if (crtc_state->pch_pfit.enabled) {
6160                 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6161                 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6162         } else {
6163                 width = adjusted_mode->crtc_hdisplay;
6164                 height = adjusted_mode->crtc_vdisplay;
6165         }
6166
6167         return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6168                                  SKL_CRTC_INDEX,
6169                                  &crtc_state->scaler_state.scaler_id,
6170                                  crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6171                                  width, height, NULL, 0,
6172                                  crtc_state->pch_pfit.enabled);
6173 }
6174
6175 /**
6176  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6177  * @crtc_state: crtc's scaler state
6178  * @plane_state: atomic plane state to update
6179  *
6180  * Return
6181  *     0 - scaler_usage updated successfully
6182  *    error - requested scaling cannot be supported or other error condition
6183  */
6184 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6185                                    struct intel_plane_state *plane_state)
6186 {
6187         struct intel_plane *intel_plane =
6188                 to_intel_plane(plane_state->uapi.plane);
6189         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6190         struct drm_framebuffer *fb = plane_state->hw.fb;
6191         int ret;
6192         bool force_detach = !fb || !plane_state->uapi.visible;
6193         bool need_scaler = false;
6194
6195         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6196         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6197             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6198                 need_scaler = true;
6199
6200         ret = skl_update_scaler(crtc_state, force_detach,
6201                                 drm_plane_index(&intel_plane->base),
6202                                 &plane_state->scaler_id,
6203                                 drm_rect_width(&plane_state->uapi.src) >> 16,
6204                                 drm_rect_height(&plane_state->uapi.src) >> 16,
6205                                 drm_rect_width(&plane_state->uapi.dst),
6206                                 drm_rect_height(&plane_state->uapi.dst),
6207                                 fb ? fb->format : NULL,
6208                                 fb ? fb->modifier : 0,
6209                                 need_scaler);
6210
6211         if (ret || plane_state->scaler_id < 0)
6212                 return ret;
6213
6214         /* check colorkey */
6215         if (plane_state->ckey.flags) {
6216                 drm_dbg_kms(&dev_priv->drm,
6217                             "[PLANE:%d:%s] scaling with color key not allowed",
6218                             intel_plane->base.base.id,
6219                             intel_plane->base.name);
6220                 return -EINVAL;
6221         }
6222
6223         /* Check src format */
6224         switch (fb->format->format) {
6225         case DRM_FORMAT_RGB565:
6226         case DRM_FORMAT_XBGR8888:
6227         case DRM_FORMAT_XRGB8888:
6228         case DRM_FORMAT_ABGR8888:
6229         case DRM_FORMAT_ARGB8888:
6230         case DRM_FORMAT_XRGB2101010:
6231         case DRM_FORMAT_XBGR2101010:
6232         case DRM_FORMAT_ARGB2101010:
6233         case DRM_FORMAT_ABGR2101010:
6234         case DRM_FORMAT_YUYV:
6235         case DRM_FORMAT_YVYU:
6236         case DRM_FORMAT_UYVY:
6237         case DRM_FORMAT_VYUY:
6238         case DRM_FORMAT_NV12:
6239         case DRM_FORMAT_XYUV8888:
6240         case DRM_FORMAT_P010:
6241         case DRM_FORMAT_P012:
6242         case DRM_FORMAT_P016:
6243         case DRM_FORMAT_Y210:
6244         case DRM_FORMAT_Y212:
6245         case DRM_FORMAT_Y216:
6246         case DRM_FORMAT_XVYU2101010:
6247         case DRM_FORMAT_XVYU12_16161616:
6248         case DRM_FORMAT_XVYU16161616:
6249                 break;
6250         case DRM_FORMAT_XBGR16161616F:
6251         case DRM_FORMAT_ABGR16161616F:
6252         case DRM_FORMAT_XRGB16161616F:
6253         case DRM_FORMAT_ARGB16161616F:
6254                 if (INTEL_GEN(dev_priv) >= 11)
6255                         break;
6256                 fallthrough;
6257         default:
6258                 drm_dbg_kms(&dev_priv->drm,
6259                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6260                             intel_plane->base.base.id, intel_plane->base.name,
6261                             fb->base.id, fb->format->format);
6262                 return -EINVAL;
6263         }
6264
6265         return 0;
6266 }
6267
6268 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6269 {
6270         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6271         int i;
6272
6273         for (i = 0; i < crtc->num_scalers; i++)
6274                 skl_detach_scaler(crtc, i);
6275 }
6276
6277 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6278 {
6279         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6280         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6281         const struct intel_crtc_scaler_state *scaler_state =
6282                 &crtc_state->scaler_state;
6283         struct drm_rect src = {
6284                 .x2 = crtc_state->pipe_src_w << 16,
6285                 .y2 = crtc_state->pipe_src_h << 16,
6286         };
6287         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6288         u16 uv_rgb_hphase, uv_rgb_vphase;
6289         enum pipe pipe = crtc->pipe;
6290         int width = drm_rect_width(dst);
6291         int height = drm_rect_height(dst);
6292         int x = dst->x1;
6293         int y = dst->y1;
6294         int hscale, vscale;
6295         unsigned long irqflags;
6296         int id;
6297
6298         if (!crtc_state->pch_pfit.enabled)
6299                 return;
6300
6301         if (drm_WARN_ON(&dev_priv->drm,
6302                         crtc_state->scaler_state.scaler_id < 0))
6303                 return;
6304
6305         hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6306         vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6307
6308         uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6309         uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6310
6311         id = scaler_state->scaler_id;
6312
6313         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6314
6315         intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6316                           PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6317         intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6318                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6319         intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6320                           PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6321         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6322                           x << 16 | y);
6323         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6324                           width << 16 | height);
6325
6326         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6327 }
6328
6329 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6330 {
6331         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6332         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6333         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6334         enum pipe pipe = crtc->pipe;
6335         int width = drm_rect_width(dst);
6336         int height = drm_rect_height(dst);
6337         int x = dst->x1;
6338         int y = dst->y1;
6339
6340         if (!crtc_state->pch_pfit.enabled)
6341                 return;
6342
6343         /* Force use of hard-coded filter coefficients
6344          * as some pre-programmed values are broken,
6345          * e.g. x201.
6346          */
6347         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6348                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6349                                PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6350         else
6351                 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6352                                PF_FILTER_MED_3x3);
6353         intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6354         intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6355 }
6356
6357 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6358 {
6359         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6360         struct drm_device *dev = crtc->base.dev;
6361         struct drm_i915_private *dev_priv = to_i915(dev);
6362
6363         if (!crtc_state->ips_enabled)
6364                 return;
6365
6366         /*
6367          * We can only enable IPS after we enable a plane and wait for a vblank
6368          * This function is called from post_plane_update, which is run after
6369          * a vblank wait.
6370          */
6371         drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6372
6373         if (IS_BROADWELL(dev_priv)) {
6374                 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6375                                                          IPS_ENABLE | IPS_PCODE_CONTROL));
6376                 /* Quoting Art Runyan: "its not safe to expect any particular
6377                  * value in IPS_CTL bit 31 after enabling IPS through the
6378                  * mailbox." Moreover, the mailbox may return a bogus state,
6379                  * so we need to just enable it and continue on.
6380                  */
6381         } else {
6382                 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6383                 /* The bit only becomes 1 in the next vblank, so this wait here
6384                  * is essentially intel_wait_for_vblank. If we don't have this
6385                  * and don't wait for vblanks until the end of crtc_enable, then
6386                  * the HW state readout code will complain that the expected
6387                  * IPS_CTL value is not the one we read. */
6388                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6389                         drm_err(&dev_priv->drm,
6390                                 "Timed out waiting for IPS enable\n");
6391         }
6392 }
6393
6394 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6395 {
6396         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6397         struct drm_device *dev = crtc->base.dev;
6398         struct drm_i915_private *dev_priv = to_i915(dev);
6399
6400         if (!crtc_state->ips_enabled)
6401                 return;
6402
6403         if (IS_BROADWELL(dev_priv)) {
6404                 drm_WARN_ON(dev,
6405                             sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6406                 /*
6407                  * Wait for PCODE to finish disabling IPS. The BSpec specified
6408                  * 42ms timeout value leads to occasional timeouts so use 100ms
6409                  * instead.
6410                  */
6411                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6412                         drm_err(&dev_priv->drm,
6413                                 "Timed out waiting for IPS disable\n");
6414         } else {
6415                 intel_de_write(dev_priv, IPS_CTL, 0);
6416                 intel_de_posting_read(dev_priv, IPS_CTL);
6417         }
6418
6419         /* We need to wait for a vblank before we can disable the plane. */
6420         intel_wait_for_vblank(dev_priv, crtc->pipe);
6421 }
6422
6423 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6424 {
6425         if (intel_crtc->overlay)
6426                 (void) intel_overlay_switch_off(intel_crtc->overlay);
6427
6428         /* Let userspace switch the overlay on again. In most cases userspace
6429          * has to recompute where to put it anyway.
6430          */
6431 }
6432
6433 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6434                                        const struct intel_crtc_state *new_crtc_state)
6435 {
6436         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6437         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6438
6439         if (!old_crtc_state->ips_enabled)
6440                 return false;
6441
6442         if (needs_modeset(new_crtc_state))
6443                 return true;
6444
6445         /*
6446          * Workaround : Do not read or write the pipe palette/gamma data while
6447          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6448          *
6449          * Disable IPS before we program the LUT.
6450          */
6451         if (IS_HASWELL(dev_priv) &&
6452             (new_crtc_state->uapi.color_mgmt_changed ||
6453              new_crtc_state->update_pipe) &&
6454             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6455                 return true;
6456
6457         return !new_crtc_state->ips_enabled;
6458 }
6459
6460 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6461                                        const struct intel_crtc_state *new_crtc_state)
6462 {
6463         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6465
6466         if (!new_crtc_state->ips_enabled)
6467                 return false;
6468
6469         if (needs_modeset(new_crtc_state))
6470                 return true;
6471
6472         /*
6473          * Workaround : Do not read or write the pipe palette/gamma data while
6474          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6475          *
6476          * Re-enable IPS after the LUT has been programmed.
6477          */
6478         if (IS_HASWELL(dev_priv) &&
6479             (new_crtc_state->uapi.color_mgmt_changed ||
6480              new_crtc_state->update_pipe) &&
6481             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6482                 return true;
6483
6484         /*
6485          * We can't read out IPS on broadwell, assume the worst and
6486          * forcibly enable IPS on the first fastset.
6487          */
6488         if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6489                 return true;
6490
6491         return !old_crtc_state->ips_enabled;
6492 }
6493
6494 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6495 {
6496         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6497
6498         if (!crtc_state->nv12_planes)
6499                 return false;
6500
6501         /* WA Display #0827: Gen9:all */
6502         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6503                 return true;
6504
6505         return false;
6506 }
6507
6508 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6509 {
6510         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6511
6512         /* Wa_2006604312:icl,ehl */
6513         if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6514                 return true;
6515
6516         return false;
6517 }
6518
6519 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6520                             const struct intel_crtc_state *new_crtc_state)
6521 {
6522         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6523                 new_crtc_state->active_planes;
6524 }
6525
6526 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6527                              const struct intel_crtc_state *new_crtc_state)
6528 {
6529         return old_crtc_state->active_planes &&
6530                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6531 }
6532
6533 static void intel_post_plane_update(struct intel_atomic_state *state,
6534                                     struct intel_crtc *crtc)
6535 {
6536         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6537         const struct intel_crtc_state *old_crtc_state =
6538                 intel_atomic_get_old_crtc_state(state, crtc);
6539         const struct intel_crtc_state *new_crtc_state =
6540                 intel_atomic_get_new_crtc_state(state, crtc);
6541         enum pipe pipe = crtc->pipe;
6542
6543         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6544
6545         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6546                 intel_update_watermarks(crtc);
6547
6548         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6549                 hsw_enable_ips(new_crtc_state);
6550
6551         intel_fbc_post_update(state, crtc);
6552
6553         if (needs_nv12_wa(old_crtc_state) &&
6554             !needs_nv12_wa(new_crtc_state))
6555                 skl_wa_827(dev_priv, pipe, false);
6556
6557         if (needs_scalerclk_wa(old_crtc_state) &&
6558             !needs_scalerclk_wa(new_crtc_state))
6559                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6560 }
6561
6562 static void intel_pre_plane_update(struct intel_atomic_state *state,
6563                                    struct intel_crtc *crtc)
6564 {
6565         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6566         const struct intel_crtc_state *old_crtc_state =
6567                 intel_atomic_get_old_crtc_state(state, crtc);
6568         const struct intel_crtc_state *new_crtc_state =
6569                 intel_atomic_get_new_crtc_state(state, crtc);
6570         enum pipe pipe = crtc->pipe;
6571
6572         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6573                 hsw_disable_ips(old_crtc_state);
6574
6575         if (intel_fbc_pre_update(state, crtc))
6576                 intel_wait_for_vblank(dev_priv, pipe);
6577
6578         /* Display WA 827 */
6579         if (!needs_nv12_wa(old_crtc_state) &&
6580             needs_nv12_wa(new_crtc_state))
6581                 skl_wa_827(dev_priv, pipe, true);
6582
6583         /* Wa_2006604312:icl,ehl */
6584         if (!needs_scalerclk_wa(old_crtc_state) &&
6585             needs_scalerclk_wa(new_crtc_state))
6586                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6587
6588         /*
6589          * Vblank time updates from the shadow to live plane control register
6590          * are blocked if the memory self-refresh mode is active at that
6591          * moment. So to make sure the plane gets truly disabled, disable
6592          * first the self-refresh mode. The self-refresh enable bit in turn
6593          * will be checked/applied by the HW only at the next frame start
6594          * event which is after the vblank start event, so we need to have a
6595          * wait-for-vblank between disabling the plane and the pipe.
6596          */
6597         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6598             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6599                 intel_wait_for_vblank(dev_priv, pipe);
6600
6601         /*
6602          * IVB workaround: must disable low power watermarks for at least
6603          * one frame before enabling scaling.  LP watermarks can be re-enabled
6604          * when scaling is disabled.
6605          *
6606          * WaCxSRDisabledForSpriteScaling:ivb
6607          */
6608         if (old_crtc_state->hw.active &&
6609             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6610                 intel_wait_for_vblank(dev_priv, pipe);
6611
6612         /*
6613          * If we're doing a modeset we don't need to do any
6614          * pre-vblank watermark programming here.
6615          */
6616         if (!needs_modeset(new_crtc_state)) {
6617                 /*
6618                  * For platforms that support atomic watermarks, program the
6619                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6620                  * will be the intermediate values that are safe for both pre- and
6621                  * post- vblank; when vblank happens, the 'active' values will be set
6622                  * to the final 'target' values and we'll do this again to get the
6623                  * optimal watermarks.  For gen9+ platforms, the values we program here
6624                  * will be the final target values which will get automatically latched
6625                  * at vblank time; no further programming will be necessary.
6626                  *
6627                  * If a platform hasn't been transitioned to atomic watermarks yet,
6628                  * we'll continue to update watermarks the old way, if flags tell
6629                  * us to.
6630                  */
6631                 if (dev_priv->display.initial_watermarks)
6632                         dev_priv->display.initial_watermarks(state, crtc);
6633                 else if (new_crtc_state->update_wm_pre)
6634                         intel_update_watermarks(crtc);
6635         }
6636
6637         /*
6638          * Gen2 reports pipe underruns whenever all planes are disabled.
6639          * So disable underrun reporting before all the planes get disabled.
6640          *
6641          * We do this after .initial_watermarks() so that we have a
6642          * chance of catching underruns with the intermediate watermarks
6643          * vs. the old plane configuration.
6644          */
6645         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6646                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6647 }
6648
6649 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6650                                       struct intel_crtc *crtc)
6651 {
6652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6653         const struct intel_crtc_state *new_crtc_state =
6654                 intel_atomic_get_new_crtc_state(state, crtc);
6655         unsigned int update_mask = new_crtc_state->update_planes;
6656         const struct intel_plane_state *old_plane_state;
6657         struct intel_plane *plane;
6658         unsigned fb_bits = 0;
6659         int i;
6660
6661         intel_crtc_dpms_overlay_disable(crtc);
6662
6663         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6664                 if (crtc->pipe != plane->pipe ||
6665                     !(update_mask & BIT(plane->id)))
6666                         continue;
6667
6668                 intel_disable_plane(plane, new_crtc_state);
6669
6670                 if (old_plane_state->uapi.visible)
6671                         fb_bits |= plane->frontbuffer_bit;
6672         }
6673
6674         intel_frontbuffer_flip(dev_priv, fb_bits);
6675 }
6676
6677 /*
6678  * intel_connector_primary_encoder - get the primary encoder for a connector
6679  * @connector: connector for which to return the encoder
6680  *
6681  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6682  * all connectors to their encoder, except for DP-MST connectors which have
6683  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6684  * pointed to by as many DP-MST connectors as there are pipes.
6685  */
6686 static struct intel_encoder *
6687 intel_connector_primary_encoder(struct intel_connector *connector)
6688 {
6689         struct intel_encoder *encoder;
6690
6691         if (connector->mst_port)
6692                 return &dp_to_dig_port(connector->mst_port)->base;
6693
6694         encoder = intel_attached_encoder(connector);
6695         drm_WARN_ON(connector->base.dev, !encoder);
6696
6697         return encoder;
6698 }
6699
6700 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6701 {
6702         struct drm_connector_state *new_conn_state;
6703         struct drm_connector *connector;
6704         int i;
6705
6706         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6707                                         i) {
6708                 struct intel_connector *intel_connector;
6709                 struct intel_encoder *encoder;
6710                 struct intel_crtc *crtc;
6711
6712                 if (!intel_connector_needs_modeset(state, connector))
6713                         continue;
6714
6715                 intel_connector = to_intel_connector(connector);
6716                 encoder = intel_connector_primary_encoder(intel_connector);
6717                 if (!encoder->update_prepare)
6718                         continue;
6719
6720                 crtc = new_conn_state->crtc ?
6721                         to_intel_crtc(new_conn_state->crtc) : NULL;
6722                 encoder->update_prepare(state, encoder, crtc);
6723         }
6724 }
6725
6726 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6727 {
6728         struct drm_connector_state *new_conn_state;
6729         struct drm_connector *connector;
6730         int i;
6731
6732         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6733                                         i) {
6734                 struct intel_connector *intel_connector;
6735                 struct intel_encoder *encoder;
6736                 struct intel_crtc *crtc;
6737
6738                 if (!intel_connector_needs_modeset(state, connector))
6739                         continue;
6740
6741                 intel_connector = to_intel_connector(connector);
6742                 encoder = intel_connector_primary_encoder(intel_connector);
6743                 if (!encoder->update_complete)
6744                         continue;
6745
6746                 crtc = new_conn_state->crtc ?
6747                         to_intel_crtc(new_conn_state->crtc) : NULL;
6748                 encoder->update_complete(state, encoder, crtc);
6749         }
6750 }
6751
6752 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6753                                           struct intel_crtc *crtc)
6754 {
6755         const struct intel_crtc_state *crtc_state =
6756                 intel_atomic_get_new_crtc_state(state, crtc);
6757         const struct drm_connector_state *conn_state;
6758         struct drm_connector *conn;
6759         int i;
6760
6761         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6762                 struct intel_encoder *encoder =
6763                         to_intel_encoder(conn_state->best_encoder);
6764
6765                 if (conn_state->crtc != &crtc->base)
6766                         continue;
6767
6768                 if (encoder->pre_pll_enable)
6769                         encoder->pre_pll_enable(state, encoder,
6770                                                 crtc_state, conn_state);
6771         }
6772 }
6773
6774 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6775                                       struct intel_crtc *crtc)
6776 {
6777         const struct intel_crtc_state *crtc_state =
6778                 intel_atomic_get_new_crtc_state(state, crtc);
6779         const struct drm_connector_state *conn_state;
6780         struct drm_connector *conn;
6781         int i;
6782
6783         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6784                 struct intel_encoder *encoder =
6785                         to_intel_encoder(conn_state->best_encoder);
6786
6787                 if (conn_state->crtc != &crtc->base)
6788                         continue;
6789
6790                 if (encoder->pre_enable)
6791                         encoder->pre_enable(state, encoder,
6792                                             crtc_state, conn_state);
6793         }
6794 }
6795
6796 static void intel_encoders_enable(struct intel_atomic_state *state,
6797                                   struct intel_crtc *crtc)
6798 {
6799         const struct intel_crtc_state *crtc_state =
6800                 intel_atomic_get_new_crtc_state(state, crtc);
6801         const struct drm_connector_state *conn_state;
6802         struct drm_connector *conn;
6803         int i;
6804
6805         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6806                 struct intel_encoder *encoder =
6807                         to_intel_encoder(conn_state->best_encoder);
6808
6809                 if (conn_state->crtc != &crtc->base)
6810                         continue;
6811
6812                 if (encoder->enable)
6813                         encoder->enable(state, encoder,
6814                                         crtc_state, conn_state);
6815                 intel_opregion_notify_encoder(encoder, true);
6816         }
6817 }
6818
6819 static void intel_encoders_disable(struct intel_atomic_state *state,
6820                                    struct intel_crtc *crtc)
6821 {
6822         const struct intel_crtc_state *old_crtc_state =
6823                 intel_atomic_get_old_crtc_state(state, crtc);
6824         const struct drm_connector_state *old_conn_state;
6825         struct drm_connector *conn;
6826         int i;
6827
6828         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6829                 struct intel_encoder *encoder =
6830                         to_intel_encoder(old_conn_state->best_encoder);
6831
6832                 if (old_conn_state->crtc != &crtc->base)
6833                         continue;
6834
6835                 intel_opregion_notify_encoder(encoder, false);
6836                 if (encoder->disable)
6837                         encoder->disable(state, encoder,
6838                                          old_crtc_state, old_conn_state);
6839         }
6840 }
6841
6842 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6843                                         struct intel_crtc *crtc)
6844 {
6845         const struct intel_crtc_state *old_crtc_state =
6846                 intel_atomic_get_old_crtc_state(state, crtc);
6847         const struct drm_connector_state *old_conn_state;
6848         struct drm_connector *conn;
6849         int i;
6850
6851         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6852                 struct intel_encoder *encoder =
6853                         to_intel_encoder(old_conn_state->best_encoder);
6854
6855                 if (old_conn_state->crtc != &crtc->base)
6856                         continue;
6857
6858                 if (encoder->post_disable)
6859                         encoder->post_disable(state, encoder,
6860                                               old_crtc_state, old_conn_state);
6861         }
6862 }
6863
6864 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6865                                             struct intel_crtc *crtc)
6866 {
6867         const struct intel_crtc_state *old_crtc_state =
6868                 intel_atomic_get_old_crtc_state(state, crtc);
6869         const struct drm_connector_state *old_conn_state;
6870         struct drm_connector *conn;
6871         int i;
6872
6873         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6874                 struct intel_encoder *encoder =
6875                         to_intel_encoder(old_conn_state->best_encoder);
6876
6877                 if (old_conn_state->crtc != &crtc->base)
6878                         continue;
6879
6880                 if (encoder->post_pll_disable)
6881                         encoder->post_pll_disable(state, encoder,
6882                                                   old_crtc_state, old_conn_state);
6883         }
6884 }
6885
6886 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6887                                        struct intel_crtc *crtc)
6888 {
6889         const struct intel_crtc_state *crtc_state =
6890                 intel_atomic_get_new_crtc_state(state, crtc);
6891         const struct drm_connector_state *conn_state;
6892         struct drm_connector *conn;
6893         int i;
6894
6895         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6896                 struct intel_encoder *encoder =
6897                         to_intel_encoder(conn_state->best_encoder);
6898
6899                 if (conn_state->crtc != &crtc->base)
6900                         continue;
6901
6902                 if (encoder->update_pipe)
6903                         encoder->update_pipe(state, encoder,
6904                                              crtc_state, conn_state);
6905         }
6906 }
6907
6908 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6909 {
6910         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6911         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6912
6913         plane->disable_plane(plane, crtc_state);
6914 }
6915
6916 static void ilk_crtc_enable(struct intel_atomic_state *state,
6917                             struct intel_crtc *crtc)
6918 {
6919         const struct intel_crtc_state *new_crtc_state =
6920                 intel_atomic_get_new_crtc_state(state, crtc);
6921         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6922         enum pipe pipe = crtc->pipe;
6923
6924         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6925                 return;
6926
6927         /*
6928          * Sometimes spurious CPU pipe underruns happen during FDI
6929          * training, at least with VGA+HDMI cloning. Suppress them.
6930          *
6931          * On ILK we get an occasional spurious CPU pipe underruns
6932          * between eDP port A enable and vdd enable. Also PCH port
6933          * enable seems to result in the occasional CPU pipe underrun.
6934          *
6935          * Spurious PCH underruns also occur during PCH enabling.
6936          */
6937         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6938         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6939
6940         if (new_crtc_state->has_pch_encoder)
6941                 intel_prepare_shared_dpll(new_crtc_state);
6942
6943         if (intel_crtc_has_dp_encoder(new_crtc_state))
6944                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6945
6946         intel_set_pipe_timings(new_crtc_state);
6947         intel_set_pipe_src_size(new_crtc_state);
6948
6949         if (new_crtc_state->has_pch_encoder)
6950                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6951                                              &new_crtc_state->fdi_m_n, NULL);
6952
6953         ilk_set_pipeconf(new_crtc_state);
6954
6955         crtc->active = true;
6956
6957         intel_encoders_pre_enable(state, crtc);
6958
6959         if (new_crtc_state->has_pch_encoder) {
6960                 /* Note: FDI PLL enabling _must_ be done before we enable the
6961                  * cpu pipes, hence this is separate from all the other fdi/pch
6962                  * enabling. */
6963                 ilk_fdi_pll_enable(new_crtc_state);
6964         } else {
6965                 assert_fdi_tx_disabled(dev_priv, pipe);
6966                 assert_fdi_rx_disabled(dev_priv, pipe);
6967         }
6968
6969         ilk_pfit_enable(new_crtc_state);
6970
6971         /*
6972          * On ILK+ LUT must be loaded before the pipe is running but with
6973          * clocks enabled
6974          */
6975         intel_color_load_luts(new_crtc_state);
6976         intel_color_commit(new_crtc_state);
6977         /* update DSPCNTR to configure gamma for pipe bottom color */
6978         intel_disable_primary_plane(new_crtc_state);
6979
6980         if (dev_priv->display.initial_watermarks)
6981                 dev_priv->display.initial_watermarks(state, crtc);
6982         intel_enable_pipe(new_crtc_state);
6983
6984         if (new_crtc_state->has_pch_encoder)
6985                 ilk_pch_enable(state, new_crtc_state);
6986
6987         intel_crtc_vblank_on(new_crtc_state);
6988
6989         intel_encoders_enable(state, crtc);
6990
6991         if (HAS_PCH_CPT(dev_priv))
6992                 cpt_verify_modeset(dev_priv, pipe);
6993
6994         /*
6995          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6996          * And a second vblank wait is needed at least on ILK with
6997          * some interlaced HDMI modes. Let's do the double wait always
6998          * in case there are more corner cases we don't know about.
6999          */
7000         if (new_crtc_state->has_pch_encoder) {
7001                 intel_wait_for_vblank(dev_priv, pipe);
7002                 intel_wait_for_vblank(dev_priv, pipe);
7003         }
7004         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7005         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7006 }
7007
7008 /* IPS only exists on ULT machines and is tied to pipe A. */
7009 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7010 {
7011         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7012 }
7013
7014 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7015                                             enum pipe pipe, bool apply)
7016 {
7017         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7018         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7019
7020         if (apply)
7021                 val |= mask;
7022         else
7023                 val &= ~mask;
7024
7025         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7026 }
7027
7028 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7029 {
7030         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7031         enum pipe pipe = crtc->pipe;
7032         u32 val;
7033
7034         val = MBUS_DBOX_A_CREDIT(2);
7035
7036         if (INTEL_GEN(dev_priv) >= 12) {
7037                 val |= MBUS_DBOX_BW_CREDIT(2);
7038                 val |= MBUS_DBOX_B_CREDIT(12);
7039         } else {
7040                 val |= MBUS_DBOX_BW_CREDIT(1);
7041                 val |= MBUS_DBOX_B_CREDIT(8);
7042         }
7043
7044         intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7045 }
7046
7047 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7048 {
7049         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7051
7052         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7053                        HSW_LINETIME(crtc_state->linetime) |
7054                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
7055 }
7056
7057 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7058 {
7059         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7060         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7061         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7062         u32 val;
7063
7064         val = intel_de_read(dev_priv, reg);
7065         val &= ~HSW_FRAME_START_DELAY_MASK;
7066         val |= HSW_FRAME_START_DELAY(0);
7067         intel_de_write(dev_priv, reg, val);
7068 }
7069
7070 static void hsw_crtc_enable(struct intel_atomic_state *state,
7071                             struct intel_crtc *crtc)
7072 {
7073         const struct intel_crtc_state *new_crtc_state =
7074                 intel_atomic_get_new_crtc_state(state, crtc);
7075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7076         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7077         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7078         bool psl_clkgate_wa;
7079
7080         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7081                 return;
7082
7083         intel_encoders_pre_pll_enable(state, crtc);
7084
7085         if (new_crtc_state->shared_dpll)
7086                 intel_enable_shared_dpll(new_crtc_state);
7087
7088         intel_encoders_pre_enable(state, crtc);
7089
7090         if (!transcoder_is_dsi(cpu_transcoder))
7091                 intel_set_pipe_timings(new_crtc_state);
7092
7093         intel_set_pipe_src_size(new_crtc_state);
7094
7095         if (cpu_transcoder != TRANSCODER_EDP &&
7096             !transcoder_is_dsi(cpu_transcoder))
7097                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7098                                new_crtc_state->pixel_multiplier - 1);
7099
7100         if (new_crtc_state->has_pch_encoder)
7101                 intel_cpu_transcoder_set_m_n(new_crtc_state,
7102                                              &new_crtc_state->fdi_m_n, NULL);
7103
7104         if (!transcoder_is_dsi(cpu_transcoder)) {
7105                 hsw_set_frame_start_delay(new_crtc_state);
7106                 hsw_set_pipeconf(new_crtc_state);
7107         }
7108
7109         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7110                 bdw_set_pipemisc(new_crtc_state);
7111
7112         crtc->active = true;
7113
7114         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7115         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7116                 new_crtc_state->pch_pfit.enabled;
7117         if (psl_clkgate_wa)
7118                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7119
7120         if (INTEL_GEN(dev_priv) >= 9)
7121                 skl_pfit_enable(new_crtc_state);
7122         else
7123                 ilk_pfit_enable(new_crtc_state);
7124
7125         /*
7126          * On ILK+ LUT must be loaded before the pipe is running but with
7127          * clocks enabled
7128          */
7129         intel_color_load_luts(new_crtc_state);
7130         intel_color_commit(new_crtc_state);
7131         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7132         if (INTEL_GEN(dev_priv) < 9)
7133                 intel_disable_primary_plane(new_crtc_state);
7134
7135         hsw_set_linetime_wm(new_crtc_state);
7136
7137         if (INTEL_GEN(dev_priv) >= 11)
7138                 icl_set_pipe_chicken(crtc);
7139
7140         if (dev_priv->display.initial_watermarks)
7141                 dev_priv->display.initial_watermarks(state, crtc);
7142
7143         if (INTEL_GEN(dev_priv) >= 11)
7144                 icl_pipe_mbus_enable(crtc);
7145
7146         intel_encoders_enable(state, crtc);
7147
7148         if (psl_clkgate_wa) {
7149                 intel_wait_for_vblank(dev_priv, pipe);
7150                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7151         }
7152
7153         /* If we change the relative order between pipe/planes enabling, we need
7154          * to change the workaround. */
7155         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7156         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7157                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7158                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7159         }
7160 }
7161
7162 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7163 {
7164         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7165         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7166         enum pipe pipe = crtc->pipe;
7167
7168         /* To avoid upsetting the power well on haswell only disable the pfit if
7169          * it's in use. The hw state code will make sure we get this right. */
7170         if (!old_crtc_state->pch_pfit.enabled)
7171                 return;
7172
7173         intel_de_write(dev_priv, PF_CTL(pipe), 0);
7174         intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7175         intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7176 }
7177
7178 static void ilk_crtc_disable(struct intel_atomic_state *state,
7179                              struct intel_crtc *crtc)
7180 {
7181         const struct intel_crtc_state *old_crtc_state =
7182                 intel_atomic_get_old_crtc_state(state, crtc);
7183         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7184         enum pipe pipe = crtc->pipe;
7185
7186         /*
7187          * Sometimes spurious CPU pipe underruns happen when the
7188          * pipe is already disabled, but FDI RX/TX is still enabled.
7189          * Happens at least with VGA+HDMI cloning. Suppress them.
7190          */
7191         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7192         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7193
7194         intel_encoders_disable(state, crtc);
7195
7196         intel_crtc_vblank_off(old_crtc_state);
7197
7198         intel_disable_pipe(old_crtc_state);
7199
7200         ilk_pfit_disable(old_crtc_state);
7201
7202         if (old_crtc_state->has_pch_encoder)
7203                 ilk_fdi_disable(crtc);
7204
7205         intel_encoders_post_disable(state, crtc);
7206
7207         if (old_crtc_state->has_pch_encoder) {
7208                 ilk_disable_pch_transcoder(dev_priv, pipe);
7209
7210                 if (HAS_PCH_CPT(dev_priv)) {
7211                         i915_reg_t reg;
7212                         u32 temp;
7213
7214                         /* disable TRANS_DP_CTL */
7215                         reg = TRANS_DP_CTL(pipe);
7216                         temp = intel_de_read(dev_priv, reg);
7217                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7218                                   TRANS_DP_PORT_SEL_MASK);
7219                         temp |= TRANS_DP_PORT_SEL_NONE;
7220                         intel_de_write(dev_priv, reg, temp);
7221
7222                         /* disable DPLL_SEL */
7223                         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7224                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7225                         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7226                 }
7227
7228                 ilk_fdi_pll_disable(crtc);
7229         }
7230
7231         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7232         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7233 }
7234
7235 static void hsw_crtc_disable(struct intel_atomic_state *state,
7236                              struct intel_crtc *crtc)
7237 {
7238         /*
7239          * FIXME collapse everything to one hook.
7240          * Need care with mst->ddi interactions.
7241          */
7242         intel_encoders_disable(state, crtc);
7243         intel_encoders_post_disable(state, crtc);
7244 }
7245
7246 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7247 {
7248         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7249         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7250
7251         if (!crtc_state->gmch_pfit.control)
7252                 return;
7253
7254         /*
7255          * The panel fitter should only be adjusted whilst the pipe is disabled,
7256          * according to register description and PRM.
7257          */
7258         drm_WARN_ON(&dev_priv->drm,
7259                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7260         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7261
7262         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7263                        crtc_state->gmch_pfit.pgm_ratios);
7264         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7265
7266         /* Border color in case we don't scale up to the full screen. Black by
7267          * default, change to something else for debugging. */
7268         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7269 }
7270
7271 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7272 {
7273         if (phy == PHY_NONE)
7274                 return false;
7275         else if (IS_ROCKETLAKE(dev_priv))
7276                 return phy <= PHY_D;
7277         else if (IS_ELKHARTLAKE(dev_priv))
7278                 return phy <= PHY_C;
7279         else if (INTEL_GEN(dev_priv) >= 11)
7280                 return phy <= PHY_B;
7281         else
7282                 return false;
7283 }
7284
7285 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7286 {
7287         if (IS_ROCKETLAKE(dev_priv))
7288                 return false;
7289         else if (INTEL_GEN(dev_priv) >= 12)
7290                 return phy >= PHY_D && phy <= PHY_I;
7291         else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7292                 return phy >= PHY_C && phy <= PHY_F;
7293         else
7294                 return false;
7295 }
7296
7297 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7298 {
7299         if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7300                 return (enum phy)port - 1;
7301         else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7302                 return PHY_A;
7303
7304         return (enum phy)port;
7305 }
7306
7307 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7308 {
7309         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7310                 return PORT_TC_NONE;
7311
7312         if (INTEL_GEN(dev_priv) >= 12)
7313                 return port - PORT_D;
7314
7315         return port - PORT_C;
7316 }
7317
7318 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7319 {
7320         switch (port) {
7321         case PORT_A:
7322                 return POWER_DOMAIN_PORT_DDI_A_LANES;
7323         case PORT_B:
7324                 return POWER_DOMAIN_PORT_DDI_B_LANES;
7325         case PORT_C:
7326                 return POWER_DOMAIN_PORT_DDI_C_LANES;
7327         case PORT_D:
7328                 return POWER_DOMAIN_PORT_DDI_D_LANES;
7329         case PORT_E:
7330                 return POWER_DOMAIN_PORT_DDI_E_LANES;
7331         case PORT_F:
7332                 return POWER_DOMAIN_PORT_DDI_F_LANES;
7333         case PORT_G:
7334                 return POWER_DOMAIN_PORT_DDI_G_LANES;
7335         case PORT_H:
7336                 return POWER_DOMAIN_PORT_DDI_H_LANES;
7337         case PORT_I:
7338                 return POWER_DOMAIN_PORT_DDI_I_LANES;
7339         default:
7340                 MISSING_CASE(port);
7341                 return POWER_DOMAIN_PORT_OTHER;
7342         }
7343 }
7344
7345 enum intel_display_power_domain
7346 intel_aux_power_domain(struct intel_digital_port *dig_port)
7347 {
7348         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7349         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7350
7351         if (intel_phy_is_tc(dev_priv, phy) &&
7352             dig_port->tc_mode == TC_PORT_TBT_ALT) {
7353                 switch (dig_port->aux_ch) {
7354                 case AUX_CH_C:
7355                         return POWER_DOMAIN_AUX_C_TBT;
7356                 case AUX_CH_D:
7357                         return POWER_DOMAIN_AUX_D_TBT;
7358                 case AUX_CH_E:
7359                         return POWER_DOMAIN_AUX_E_TBT;
7360                 case AUX_CH_F:
7361                         return POWER_DOMAIN_AUX_F_TBT;
7362                 case AUX_CH_G:
7363                         return POWER_DOMAIN_AUX_G_TBT;
7364                 case AUX_CH_H:
7365                         return POWER_DOMAIN_AUX_H_TBT;
7366                 case AUX_CH_I:
7367                         return POWER_DOMAIN_AUX_I_TBT;
7368                 default:
7369                         MISSING_CASE(dig_port->aux_ch);
7370                         return POWER_DOMAIN_AUX_C_TBT;
7371                 }
7372         }
7373
7374         return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7375 }
7376
7377 /*
7378  * Converts aux_ch to power_domain without caring about TBT ports for that use
7379  * intel_aux_power_domain()
7380  */
7381 enum intel_display_power_domain
7382 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7383 {
7384         switch (aux_ch) {
7385         case AUX_CH_A:
7386                 return POWER_DOMAIN_AUX_A;
7387         case AUX_CH_B:
7388                 return POWER_DOMAIN_AUX_B;
7389         case AUX_CH_C:
7390                 return POWER_DOMAIN_AUX_C;
7391         case AUX_CH_D:
7392                 return POWER_DOMAIN_AUX_D;
7393         case AUX_CH_E:
7394                 return POWER_DOMAIN_AUX_E;
7395         case AUX_CH_F:
7396                 return POWER_DOMAIN_AUX_F;
7397         case AUX_CH_G:
7398                 return POWER_DOMAIN_AUX_G;
7399         case AUX_CH_H:
7400                 return POWER_DOMAIN_AUX_H;
7401         case AUX_CH_I:
7402                 return POWER_DOMAIN_AUX_I;
7403         default:
7404                 MISSING_CASE(aux_ch);
7405                 return POWER_DOMAIN_AUX_A;
7406         }
7407 }
7408
7409 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7410 {
7411         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7412         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7413         struct drm_encoder *encoder;
7414         enum pipe pipe = crtc->pipe;
7415         u64 mask;
7416         enum transcoder transcoder = crtc_state->cpu_transcoder;
7417
7418         if (!crtc_state->hw.active)
7419                 return 0;
7420
7421         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7422         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7423         if (crtc_state->pch_pfit.enabled ||
7424             crtc_state->pch_pfit.force_thru)
7425                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7426
7427         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7428                                   crtc_state->uapi.encoder_mask) {
7429                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7430
7431                 mask |= BIT_ULL(intel_encoder->power_domain);
7432         }
7433
7434         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7435                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7436
7437         if (crtc_state->shared_dpll)
7438                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7439
7440         return mask;
7441 }
7442
7443 static u64
7444 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7445 {
7446         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7447         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7448         enum intel_display_power_domain domain;
7449         u64 domains, new_domains, old_domains;
7450
7451         old_domains = crtc->enabled_power_domains;
7452         crtc->enabled_power_domains = new_domains =
7453                 get_crtc_power_domains(crtc_state);
7454
7455         domains = new_domains & ~old_domains;
7456
7457         for_each_power_domain(domain, domains)
7458                 intel_display_power_get(dev_priv, domain);
7459
7460         return old_domains & ~new_domains;
7461 }
7462
7463 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7464                                       u64 domains)
7465 {
7466         enum intel_display_power_domain domain;
7467
7468         for_each_power_domain(domain, domains)
7469                 intel_display_power_put_unchecked(dev_priv, domain);
7470 }
7471
7472 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7473                                    struct intel_crtc *crtc)
7474 {
7475         const struct intel_crtc_state *new_crtc_state =
7476                 intel_atomic_get_new_crtc_state(state, crtc);
7477         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7478         enum pipe pipe = crtc->pipe;
7479
7480         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7481                 return;
7482
7483         if (intel_crtc_has_dp_encoder(new_crtc_state))
7484                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7485
7486         intel_set_pipe_timings(new_crtc_state);
7487         intel_set_pipe_src_size(new_crtc_state);
7488
7489         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7490                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7491                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7492         }
7493
7494         i9xx_set_pipeconf(new_crtc_state);
7495
7496         crtc->active = true;
7497
7498         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7499
7500         intel_encoders_pre_pll_enable(state, crtc);
7501
7502         if (IS_CHERRYVIEW(dev_priv)) {
7503                 chv_prepare_pll(crtc, new_crtc_state);
7504                 chv_enable_pll(crtc, new_crtc_state);
7505         } else {
7506                 vlv_prepare_pll(crtc, new_crtc_state);
7507                 vlv_enable_pll(crtc, new_crtc_state);
7508         }
7509
7510         intel_encoders_pre_enable(state, crtc);
7511
7512         i9xx_pfit_enable(new_crtc_state);
7513
7514         intel_color_load_luts(new_crtc_state);
7515         intel_color_commit(new_crtc_state);
7516         /* update DSPCNTR to configure gamma for pipe bottom color */
7517         intel_disable_primary_plane(new_crtc_state);
7518
7519         dev_priv->display.initial_watermarks(state, crtc);
7520         intel_enable_pipe(new_crtc_state);
7521
7522         intel_crtc_vblank_on(new_crtc_state);
7523
7524         intel_encoders_enable(state, crtc);
7525 }
7526
7527 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7528 {
7529         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7530         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7531
7532         intel_de_write(dev_priv, FP0(crtc->pipe),
7533                        crtc_state->dpll_hw_state.fp0);
7534         intel_de_write(dev_priv, FP1(crtc->pipe),
7535                        crtc_state->dpll_hw_state.fp1);
7536 }
7537
7538 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7539                              struct intel_crtc *crtc)
7540 {
7541         const struct intel_crtc_state *new_crtc_state =
7542                 intel_atomic_get_new_crtc_state(state, crtc);
7543         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7544         enum pipe pipe = crtc->pipe;
7545
7546         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7547                 return;
7548
7549         i9xx_set_pll_dividers(new_crtc_state);
7550
7551         if (intel_crtc_has_dp_encoder(new_crtc_state))
7552                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7553
7554         intel_set_pipe_timings(new_crtc_state);
7555         intel_set_pipe_src_size(new_crtc_state);
7556
7557         i9xx_set_pipeconf(new_crtc_state);
7558
7559         crtc->active = true;
7560
7561         if (!IS_GEN(dev_priv, 2))
7562                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7563
7564         intel_encoders_pre_enable(state, crtc);
7565
7566         i9xx_enable_pll(crtc, new_crtc_state);
7567
7568         i9xx_pfit_enable(new_crtc_state);
7569
7570         intel_color_load_luts(new_crtc_state);
7571         intel_color_commit(new_crtc_state);
7572         /* update DSPCNTR to configure gamma for pipe bottom color */
7573         intel_disable_primary_plane(new_crtc_state);
7574
7575         if (dev_priv->display.initial_watermarks)
7576                 dev_priv->display.initial_watermarks(state, crtc);
7577         else
7578                 intel_update_watermarks(crtc);
7579         intel_enable_pipe(new_crtc_state);
7580
7581         intel_crtc_vblank_on(new_crtc_state);
7582
7583         intel_encoders_enable(state, crtc);
7584
7585         /* prevents spurious underruns */
7586         if (IS_GEN(dev_priv, 2))
7587                 intel_wait_for_vblank(dev_priv, pipe);
7588 }
7589
7590 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7591 {
7592         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7594
7595         if (!old_crtc_state->gmch_pfit.control)
7596                 return;
7597
7598         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7599
7600         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7601                     intel_de_read(dev_priv, PFIT_CONTROL));
7602         intel_de_write(dev_priv, PFIT_CONTROL, 0);
7603 }
7604
7605 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7606                               struct intel_crtc *crtc)
7607 {
7608         struct intel_crtc_state *old_crtc_state =
7609                 intel_atomic_get_old_crtc_state(state, crtc);
7610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7611         enum pipe pipe = crtc->pipe;
7612
7613         /*
7614          * On gen2 planes are double buffered but the pipe isn't, so we must
7615          * wait for planes to fully turn off before disabling the pipe.
7616          */
7617         if (IS_GEN(dev_priv, 2))
7618                 intel_wait_for_vblank(dev_priv, pipe);
7619
7620         intel_encoders_disable(state, crtc);
7621
7622         intel_crtc_vblank_off(old_crtc_state);
7623
7624         intel_disable_pipe(old_crtc_state);
7625
7626         i9xx_pfit_disable(old_crtc_state);
7627
7628         intel_encoders_post_disable(state, crtc);
7629
7630         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7631                 if (IS_CHERRYVIEW(dev_priv))
7632                         chv_disable_pll(dev_priv, pipe);
7633                 else if (IS_VALLEYVIEW(dev_priv))
7634                         vlv_disable_pll(dev_priv, pipe);
7635                 else
7636                         i9xx_disable_pll(old_crtc_state);
7637         }
7638
7639         intel_encoders_post_pll_disable(state, crtc);
7640
7641         if (!IS_GEN(dev_priv, 2))
7642                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7643
7644         if (!dev_priv->display.initial_watermarks)
7645                 intel_update_watermarks(crtc);
7646
7647         /* clock the pipe down to 640x480@60 to potentially save power */
7648         if (IS_I830(dev_priv))
7649                 i830_enable_pipe(dev_priv, pipe);
7650 }
7651
7652 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7653                                         struct drm_modeset_acquire_ctx *ctx)
7654 {
7655         struct intel_encoder *encoder;
7656         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7657         struct intel_bw_state *bw_state =
7658                 to_intel_bw_state(dev_priv->bw_obj.state);
7659         struct intel_cdclk_state *cdclk_state =
7660                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7661         struct intel_dbuf_state *dbuf_state =
7662                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7663         struct intel_crtc_state *crtc_state =
7664                 to_intel_crtc_state(crtc->base.state);
7665         enum intel_display_power_domain domain;
7666         struct intel_plane *plane;
7667         struct drm_atomic_state *state;
7668         struct intel_crtc_state *temp_crtc_state;
7669         enum pipe pipe = crtc->pipe;
7670         u64 domains;
7671         int ret;
7672
7673         if (!crtc_state->hw.active)
7674                 return;
7675
7676         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7677                 const struct intel_plane_state *plane_state =
7678                         to_intel_plane_state(plane->base.state);
7679
7680                 if (plane_state->uapi.visible)
7681                         intel_plane_disable_noatomic(crtc, plane);
7682         }
7683
7684         state = drm_atomic_state_alloc(&dev_priv->drm);
7685         if (!state) {
7686                 drm_dbg_kms(&dev_priv->drm,
7687                             "failed to disable [CRTC:%d:%s], out of memory",
7688                             crtc->base.base.id, crtc->base.name);
7689                 return;
7690         }
7691
7692         state->acquire_ctx = ctx;
7693
7694         /* Everything's already locked, -EDEADLK can't happen. */
7695         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7696         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7697
7698         drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7699
7700         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7701
7702         drm_atomic_state_put(state);
7703
7704         drm_dbg_kms(&dev_priv->drm,
7705                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7706                     crtc->base.base.id, crtc->base.name);
7707
7708         crtc->active = false;
7709         crtc->base.enabled = false;
7710
7711         drm_WARN_ON(&dev_priv->drm,
7712                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7713         crtc_state->uapi.active = false;
7714         crtc_state->uapi.connector_mask = 0;
7715         crtc_state->uapi.encoder_mask = 0;
7716         intel_crtc_free_hw_state(crtc_state);
7717         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7718
7719         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7720                 encoder->base.crtc = NULL;
7721
7722         intel_fbc_disable(crtc);
7723         intel_update_watermarks(crtc);
7724         intel_disable_shared_dpll(crtc_state);
7725
7726         domains = crtc->enabled_power_domains;
7727         for_each_power_domain(domain, domains)
7728                 intel_display_power_put_unchecked(dev_priv, domain);
7729         crtc->enabled_power_domains = 0;
7730
7731         dev_priv->active_pipes &= ~BIT(pipe);
7732         cdclk_state->min_cdclk[pipe] = 0;
7733         cdclk_state->min_voltage_level[pipe] = 0;
7734         cdclk_state->active_pipes &= ~BIT(pipe);
7735
7736         dbuf_state->active_pipes &= ~BIT(pipe);
7737
7738         bw_state->data_rate[pipe] = 0;
7739         bw_state->num_active_planes[pipe] = 0;
7740 }
7741
7742 /*
7743  * turn all crtc's off, but do not adjust state
7744  * This has to be paired with a call to intel_modeset_setup_hw_state.
7745  */
7746 int intel_display_suspend(struct drm_device *dev)
7747 {
7748         struct drm_i915_private *dev_priv = to_i915(dev);
7749         struct drm_atomic_state *state;
7750         int ret;
7751
7752         state = drm_atomic_helper_suspend(dev);
7753         ret = PTR_ERR_OR_ZERO(state);
7754         if (ret)
7755                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7756                         ret);
7757         else
7758                 dev_priv->modeset_restore_state = state;
7759         return ret;
7760 }
7761
7762 void intel_encoder_destroy(struct drm_encoder *encoder)
7763 {
7764         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7765
7766         drm_encoder_cleanup(encoder);
7767         kfree(intel_encoder);
7768 }
7769
7770 /* Cross check the actual hw state with our own modeset state tracking (and it's
7771  * internal consistency). */
7772 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7773                                          struct drm_connector_state *conn_state)
7774 {
7775         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7776         struct drm_i915_private *i915 = to_i915(connector->base.dev);
7777
7778         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7779                     connector->base.base.id, connector->base.name);
7780
7781         if (connector->get_hw_state(connector)) {
7782                 struct intel_encoder *encoder = intel_attached_encoder(connector);
7783
7784                 I915_STATE_WARN(!crtc_state,
7785                          "connector enabled without attached crtc\n");
7786
7787                 if (!crtc_state)
7788                         return;
7789
7790                 I915_STATE_WARN(!crtc_state->hw.active,
7791                                 "connector is active, but attached crtc isn't\n");
7792
7793                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7794                         return;
7795
7796                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7797                         "atomic encoder doesn't match attached encoder\n");
7798
7799                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7800                         "attached encoder crtc differs from connector crtc\n");
7801         } else {
7802                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7803                                 "attached crtc is active, but connector isn't\n");
7804                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7805                         "best encoder set without crtc!\n");
7806         }
7807 }
7808
7809 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7810 {
7811         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7812                 return crtc_state->fdi_lanes;
7813
7814         return 0;
7815 }
7816
7817 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7818                                struct intel_crtc_state *pipe_config)
7819 {
7820         struct drm_i915_private *dev_priv = to_i915(dev);
7821         struct drm_atomic_state *state = pipe_config->uapi.state;
7822         struct intel_crtc *other_crtc;
7823         struct intel_crtc_state *other_crtc_state;
7824
7825         drm_dbg_kms(&dev_priv->drm,
7826                     "checking fdi config on pipe %c, lanes %i\n",
7827                     pipe_name(pipe), pipe_config->fdi_lanes);
7828         if (pipe_config->fdi_lanes > 4) {
7829                 drm_dbg_kms(&dev_priv->drm,
7830                             "invalid fdi lane config on pipe %c: %i lanes\n",
7831                             pipe_name(pipe), pipe_config->fdi_lanes);
7832                 return -EINVAL;
7833         }
7834
7835         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7836                 if (pipe_config->fdi_lanes > 2) {
7837                         drm_dbg_kms(&dev_priv->drm,
7838                                     "only 2 lanes on haswell, required: %i lanes\n",
7839                                     pipe_config->fdi_lanes);
7840                         return -EINVAL;
7841                 } else {
7842                         return 0;
7843                 }
7844         }
7845
7846         if (INTEL_NUM_PIPES(dev_priv) == 2)
7847                 return 0;
7848
7849         /* Ivybridge 3 pipe is really complicated */
7850         switch (pipe) {
7851         case PIPE_A:
7852                 return 0;
7853         case PIPE_B:
7854                 if (pipe_config->fdi_lanes <= 2)
7855                         return 0;
7856
7857                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7858                 other_crtc_state =
7859                         intel_atomic_get_crtc_state(state, other_crtc);
7860                 if (IS_ERR(other_crtc_state))
7861                         return PTR_ERR(other_crtc_state);
7862
7863                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7864                         drm_dbg_kms(&dev_priv->drm,
7865                                     "invalid shared fdi lane config on pipe %c: %i lanes\n",
7866                                     pipe_name(pipe), pipe_config->fdi_lanes);
7867                         return -EINVAL;
7868                 }
7869                 return 0;
7870         case PIPE_C:
7871                 if (pipe_config->fdi_lanes > 2) {
7872                         drm_dbg_kms(&dev_priv->drm,
7873                                     "only 2 lanes on pipe %c: required %i lanes\n",
7874                                     pipe_name(pipe), pipe_config->fdi_lanes);
7875                         return -EINVAL;
7876                 }
7877
7878                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7879                 other_crtc_state =
7880                         intel_atomic_get_crtc_state(state, other_crtc);
7881                 if (IS_ERR(other_crtc_state))
7882                         return PTR_ERR(other_crtc_state);
7883
7884                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7885                         drm_dbg_kms(&dev_priv->drm,
7886                                     "fdi link B uses too many lanes to enable link C\n");
7887                         return -EINVAL;
7888                 }
7889                 return 0;
7890         default:
7891                 BUG();
7892         }
7893 }
7894
7895 #define RETRY 1
7896 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7897                                   struct intel_crtc_state *pipe_config)
7898 {
7899         struct drm_device *dev = intel_crtc->base.dev;
7900         struct drm_i915_private *i915 = to_i915(dev);
7901         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7902         int lane, link_bw, fdi_dotclock, ret;
7903         bool needs_recompute = false;
7904
7905 retry:
7906         /* FDI is a binary signal running at ~2.7GHz, encoding
7907          * each output octet as 10 bits. The actual frequency
7908          * is stored as a divider into a 100MHz clock, and the
7909          * mode pixel clock is stored in units of 1KHz.
7910          * Hence the bw of each lane in terms of the mode signal
7911          * is:
7912          */
7913         link_bw = intel_fdi_link_freq(i915, pipe_config);
7914
7915         fdi_dotclock = adjusted_mode->crtc_clock;
7916
7917         lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7918                                       pipe_config->pipe_bpp);
7919
7920         pipe_config->fdi_lanes = lane;
7921
7922         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7923                                link_bw, &pipe_config->fdi_m_n, false, false);
7924
7925         ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7926         if (ret == -EDEADLK)
7927                 return ret;
7928
7929         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7930                 pipe_config->pipe_bpp -= 2*3;
7931                 drm_dbg_kms(&i915->drm,
7932                             "fdi link bw constraint, reducing pipe bpp to %i\n",
7933                             pipe_config->pipe_bpp);
7934                 needs_recompute = true;
7935                 pipe_config->bw_constrained = true;
7936
7937                 goto retry;
7938         }
7939
7940         if (needs_recompute)
7941                 return RETRY;
7942
7943         return ret;
7944 }
7945
7946 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7947 {
7948         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7949         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7950
7951         /* IPS only exists on ULT machines and is tied to pipe A. */
7952         if (!hsw_crtc_supports_ips(crtc))
7953                 return false;
7954
7955         if (!dev_priv->params.enable_ips)
7956                 return false;
7957
7958         if (crtc_state->pipe_bpp > 24)
7959                 return false;
7960
7961         /*
7962          * We compare against max which means we must take
7963          * the increased cdclk requirement into account when
7964          * calculating the new cdclk.
7965          *
7966          * Should measure whether using a lower cdclk w/o IPS
7967          */
7968         if (IS_BROADWELL(dev_priv) &&
7969             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7970                 return false;
7971
7972         return true;
7973 }
7974
7975 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7976 {
7977         struct drm_i915_private *dev_priv =
7978                 to_i915(crtc_state->uapi.crtc->dev);
7979         struct intel_atomic_state *state =
7980                 to_intel_atomic_state(crtc_state->uapi.state);
7981
7982         crtc_state->ips_enabled = false;
7983
7984         if (!hsw_crtc_state_ips_capable(crtc_state))
7985                 return 0;
7986
7987         /*
7988          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7989          * enabled and disabled dynamically based on package C states,
7990          * user space can't make reliable use of the CRCs, so let's just
7991          * completely disable it.
7992          */
7993         if (crtc_state->crc_enabled)
7994                 return 0;
7995
7996         /* IPS should be fine as long as at least one plane is enabled. */
7997         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7998                 return 0;
7999
8000         if (IS_BROADWELL(dev_priv)) {
8001                 const struct intel_cdclk_state *cdclk_state;
8002
8003                 cdclk_state = intel_atomic_get_cdclk_state(state);
8004                 if (IS_ERR(cdclk_state))
8005                         return PTR_ERR(cdclk_state);
8006
8007                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8008                 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8009                         return 0;
8010         }
8011
8012         crtc_state->ips_enabled = true;
8013
8014         return 0;
8015 }
8016
8017 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8018 {
8019         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8020
8021         /* GDG double wide on either pipe, otherwise pipe A only */
8022         return INTEL_GEN(dev_priv) < 4 &&
8023                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8024 }
8025
8026 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8027 {
8028         u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8029         unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8030
8031         /*
8032          * We only use IF-ID interlacing. If we ever use
8033          * PF-ID we'll need to adjust the pixel_rate here.
8034          */
8035
8036         if (!crtc_state->pch_pfit.enabled)
8037                 return pixel_rate;
8038
8039         pipe_w = crtc_state->pipe_src_w;
8040         pipe_h = crtc_state->pipe_src_h;
8041
8042         pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8043         pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8044
8045         if (pipe_w < pfit_w)
8046                 pipe_w = pfit_w;
8047         if (pipe_h < pfit_h)
8048                 pipe_h = pfit_h;
8049
8050         if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8051                         !pfit_w || !pfit_h))
8052                 return pixel_rate;
8053
8054         return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8055                        pfit_w * pfit_h);
8056 }
8057
8058 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8059 {
8060         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8061
8062         if (HAS_GMCH(dev_priv))
8063                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8064                 crtc_state->pixel_rate =
8065                         crtc_state->hw.adjusted_mode.crtc_clock;
8066         else
8067                 crtc_state->pixel_rate =
8068                         ilk_pipe_pixel_rate(crtc_state);
8069 }
8070
8071 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8072                                      struct intel_crtc_state *pipe_config)
8073 {
8074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8075         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8076         int clock_limit = dev_priv->max_dotclk_freq;
8077
8078         if (INTEL_GEN(dev_priv) < 4) {
8079                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8080
8081                 /*
8082                  * Enable double wide mode when the dot clock
8083                  * is > 90% of the (display) core speed.
8084                  */
8085                 if (intel_crtc_supports_double_wide(crtc) &&
8086                     adjusted_mode->crtc_clock > clock_limit) {
8087                         clock_limit = dev_priv->max_dotclk_freq;
8088                         pipe_config->double_wide = true;
8089                 }
8090         }
8091
8092         if (adjusted_mode->crtc_clock > clock_limit) {
8093                 drm_dbg_kms(&dev_priv->drm,
8094                             "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8095                             adjusted_mode->crtc_clock, clock_limit,
8096                             yesno(pipe_config->double_wide));
8097                 return -EINVAL;
8098         }
8099
8100         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8101              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8102              pipe_config->hw.ctm) {
8103                 /*
8104                  * There is only one pipe CSC unit per pipe, and we need that
8105                  * for output conversion from RGB->YCBCR. So if CTM is already
8106                  * applied we can't support YCBCR420 output.
8107                  */
8108                 drm_dbg_kms(&dev_priv->drm,
8109                             "YCBCR420 and CTM together are not possible\n");
8110                 return -EINVAL;
8111         }
8112
8113         /*
8114          * Pipe horizontal size must be even in:
8115          * - DVO ganged mode
8116          * - LVDS dual channel mode
8117          * - Double wide pipe
8118          */
8119         if (pipe_config->pipe_src_w & 1) {
8120                 if (pipe_config->double_wide) {
8121                         drm_dbg_kms(&dev_priv->drm,
8122                                     "Odd pipe source width not supported with double wide pipe\n");
8123                         return -EINVAL;
8124                 }
8125
8126                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8127                     intel_is_dual_link_lvds(dev_priv)) {
8128                         drm_dbg_kms(&dev_priv->drm,
8129                                     "Odd pipe source width not supported with dual link LVDS\n");
8130                         return -EINVAL;
8131                 }
8132         }
8133
8134         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8135          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8136          */
8137         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8138                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8139                 return -EINVAL;
8140
8141         intel_crtc_compute_pixel_rate(pipe_config);
8142
8143         if (pipe_config->has_pch_encoder)
8144                 return ilk_fdi_compute_config(crtc, pipe_config);
8145
8146         return 0;
8147 }
8148
8149 static void
8150 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8151 {
8152         while (*num > DATA_LINK_M_N_MASK ||
8153                *den > DATA_LINK_M_N_MASK) {
8154                 *num >>= 1;
8155                 *den >>= 1;
8156         }
8157 }
8158
8159 static void compute_m_n(unsigned int m, unsigned int n,
8160                         u32 *ret_m, u32 *ret_n,
8161                         bool constant_n)
8162 {
8163         /*
8164          * Several DP dongles in particular seem to be fussy about
8165          * too large link M/N values. Give N value as 0x8000 that
8166          * should be acceptable by specific devices. 0x8000 is the
8167          * specified fixed N value for asynchronous clock mode,
8168          * which the devices expect also in synchronous clock mode.
8169          */
8170         if (constant_n)
8171                 *ret_n = DP_LINK_CONSTANT_N_VALUE;
8172         else
8173                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8174
8175         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8176         intel_reduce_m_n_ratio(ret_m, ret_n);
8177 }
8178
8179 void
8180 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8181                        int pixel_clock, int link_clock,
8182                        struct intel_link_m_n *m_n,
8183                        bool constant_n, bool fec_enable)
8184 {
8185         u32 data_clock = bits_per_pixel * pixel_clock;
8186
8187         if (fec_enable)
8188                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8189
8190         m_n->tu = 64;
8191         compute_m_n(data_clock,
8192                     link_clock * nlanes * 8,
8193                     &m_n->gmch_m, &m_n->gmch_n,
8194                     constant_n);
8195
8196         compute_m_n(pixel_clock, link_clock,
8197                     &m_n->link_m, &m_n->link_n,
8198                     constant_n);
8199 }
8200
8201 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8202 {
8203         /*
8204          * There may be no VBT; and if the BIOS enabled SSC we can
8205          * just keep using it to avoid unnecessary flicker.  Whereas if the
8206          * BIOS isn't using it, don't assume it will work even if the VBT
8207          * indicates as much.
8208          */
8209         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8210                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8211                                                        PCH_DREF_CONTROL) &
8212                         DREF_SSC1_ENABLE;
8213
8214                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8215                         drm_dbg_kms(&dev_priv->drm,
8216                                     "SSC %s by BIOS, overriding VBT which says %s\n",
8217                                     enableddisabled(bios_lvds_use_ssc),
8218                                     enableddisabled(dev_priv->vbt.lvds_use_ssc));
8219                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8220                 }
8221         }
8222 }
8223
8224 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8225 {
8226         if (dev_priv->params.panel_use_ssc >= 0)
8227                 return dev_priv->params.panel_use_ssc != 0;
8228         return dev_priv->vbt.lvds_use_ssc
8229                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8230 }
8231
8232 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8233 {
8234         return (1 << dpll->n) << 16 | dpll->m2;
8235 }
8236
8237 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8238 {
8239         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8240 }
8241
8242 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8243                                      struct intel_crtc_state *crtc_state,
8244                                      struct dpll *reduced_clock)
8245 {
8246         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8247         u32 fp, fp2 = 0;
8248
8249         if (IS_PINEVIEW(dev_priv)) {
8250                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8251                 if (reduced_clock)
8252                         fp2 = pnv_dpll_compute_fp(reduced_clock);
8253         } else {
8254                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8255                 if (reduced_clock)
8256                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
8257         }
8258
8259         crtc_state->dpll_hw_state.fp0 = fp;
8260
8261         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8262             reduced_clock) {
8263                 crtc_state->dpll_hw_state.fp1 = fp2;
8264         } else {
8265                 crtc_state->dpll_hw_state.fp1 = fp;
8266         }
8267 }
8268
8269 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8270                 pipe)
8271 {
8272         u32 reg_val;
8273
8274         /*
8275          * PLLB opamp always calibrates to max value of 0x3f, force enable it
8276          * and set it to a reasonable value instead.
8277          */
8278         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8279         reg_val &= 0xffffff00;
8280         reg_val |= 0x00000030;
8281         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8282
8283         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8284         reg_val &= 0x00ffffff;
8285         reg_val |= 0x8c000000;
8286         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8287
8288         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8289         reg_val &= 0xffffff00;
8290         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8291
8292         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8293         reg_val &= 0x00ffffff;
8294         reg_val |= 0xb0000000;
8295         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8296 }
8297
8298 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8299                                          const struct intel_link_m_n *m_n)
8300 {
8301         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8302         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8303         enum pipe pipe = crtc->pipe;
8304
8305         intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8306                        TU_SIZE(m_n->tu) | m_n->gmch_m);
8307         intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8308         intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8309         intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8310 }
8311
8312 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8313                                  enum transcoder transcoder)
8314 {
8315         if (IS_HASWELL(dev_priv))
8316                 return transcoder == TRANSCODER_EDP;
8317
8318         /*
8319          * Strictly speaking some registers are available before
8320          * gen7, but we only support DRRS on gen7+
8321          */
8322         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8323 }
8324
8325 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8326                                          const struct intel_link_m_n *m_n,
8327                                          const struct intel_link_m_n *m2_n2)
8328 {
8329         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8330         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8331         enum pipe pipe = crtc->pipe;
8332         enum transcoder transcoder = crtc_state->cpu_transcoder;
8333
8334         if (INTEL_GEN(dev_priv) >= 5) {
8335                 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8336                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8337                 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8338                                m_n->gmch_n);
8339                 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8340                                m_n->link_m);
8341                 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8342                                m_n->link_n);
8343                 /*
8344                  *  M2_N2 registers are set only if DRRS is supported
8345                  * (to make sure the registers are not unnecessarily accessed).
8346                  */
8347                 if (m2_n2 && crtc_state->has_drrs &&
8348                     transcoder_has_m2_n2(dev_priv, transcoder)) {
8349                         intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8350                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8351                         intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8352                                        m2_n2->gmch_n);
8353                         intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8354                                        m2_n2->link_m);
8355                         intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8356                                        m2_n2->link_n);
8357                 }
8358         } else {
8359                 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8360                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8361                 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8362                 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8363                 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8364         }
8365 }
8366
8367 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8368 {
8369         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8370         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8371
8372         if (m_n == M1_N1) {
8373                 dp_m_n = &crtc_state->dp_m_n;
8374                 dp_m2_n2 = &crtc_state->dp_m2_n2;
8375         } else if (m_n == M2_N2) {
8376
8377                 /*
8378                  * M2_N2 registers are not supported. Hence m2_n2 divider value
8379                  * needs to be programmed into M1_N1.
8380                  */
8381                 dp_m_n = &crtc_state->dp_m2_n2;
8382         } else {
8383                 drm_err(&i915->drm, "Unsupported divider value\n");
8384                 return;
8385         }
8386
8387         if (crtc_state->has_pch_encoder)
8388                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8389         else
8390                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8391 }
8392
8393 static void vlv_compute_dpll(struct intel_crtc *crtc,
8394                              struct intel_crtc_state *pipe_config)
8395 {
8396         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8397                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8398         if (crtc->pipe != PIPE_A)
8399                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8400
8401         /* DPLL not used with DSI, but still need the rest set up */
8402         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8403                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8404                         DPLL_EXT_BUFFER_ENABLE_VLV;
8405
8406         pipe_config->dpll_hw_state.dpll_md =
8407                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8408 }
8409
8410 static void chv_compute_dpll(struct intel_crtc *crtc,
8411                              struct intel_crtc_state *pipe_config)
8412 {
8413         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8414                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8415         if (crtc->pipe != PIPE_A)
8416                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8417
8418         /* DPLL not used with DSI, but still need the rest set up */
8419         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8420                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8421
8422         pipe_config->dpll_hw_state.dpll_md =
8423                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8424 }
8425
8426 static void vlv_prepare_pll(struct intel_crtc *crtc,
8427                             const struct intel_crtc_state *pipe_config)
8428 {
8429         struct drm_device *dev = crtc->base.dev;
8430         struct drm_i915_private *dev_priv = to_i915(dev);
8431         enum pipe pipe = crtc->pipe;
8432         u32 mdiv;
8433         u32 bestn, bestm1, bestm2, bestp1, bestp2;
8434         u32 coreclk, reg_val;
8435
8436         /* Enable Refclk */
8437         intel_de_write(dev_priv, DPLL(pipe),
8438                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8439
8440         /* No need to actually set up the DPLL with DSI */
8441         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8442                 return;
8443
8444         vlv_dpio_get(dev_priv);
8445
8446         bestn = pipe_config->dpll.n;
8447         bestm1 = pipe_config->dpll.m1;
8448         bestm2 = pipe_config->dpll.m2;
8449         bestp1 = pipe_config->dpll.p1;
8450         bestp2 = pipe_config->dpll.p2;
8451
8452         /* See eDP HDMI DPIO driver vbios notes doc */
8453
8454         /* PLL B needs special handling */
8455         if (pipe == PIPE_B)
8456                 vlv_pllb_recal_opamp(dev_priv, pipe);
8457
8458         /* Set up Tx target for periodic Rcomp update */
8459         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8460
8461         /* Disable target IRef on PLL */
8462         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8463         reg_val &= 0x00ffffff;
8464         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8465
8466         /* Disable fast lock */
8467         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8468
8469         /* Set idtafcrecal before PLL is enabled */
8470         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8471         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8472         mdiv |= ((bestn << DPIO_N_SHIFT));
8473         mdiv |= (1 << DPIO_K_SHIFT);
8474
8475         /*
8476          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8477          * but we don't support that).
8478          * Note: don't use the DAC post divider as it seems unstable.
8479          */
8480         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8481         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8482
8483         mdiv |= DPIO_ENABLE_CALIBRATION;
8484         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8485
8486         /* Set HBR and RBR LPF coefficients */
8487         if (pipe_config->port_clock == 162000 ||
8488             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8489             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8490                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8491                                  0x009f0003);
8492         else
8493                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8494                                  0x00d0000f);
8495
8496         if (intel_crtc_has_dp_encoder(pipe_config)) {
8497                 /* Use SSC source */
8498                 if (pipe == PIPE_A)
8499                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8500                                          0x0df40000);
8501                 else
8502                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8503                                          0x0df70000);
8504         } else { /* HDMI or VGA */
8505                 /* Use bend source */
8506                 if (pipe == PIPE_A)
8507                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8508                                          0x0df70000);
8509                 else
8510                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8511                                          0x0df40000);
8512         }
8513
8514         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8515         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8516         if (intel_crtc_has_dp_encoder(pipe_config))
8517                 coreclk |= 0x01000000;
8518         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8519
8520         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8521
8522         vlv_dpio_put(dev_priv);
8523 }
8524
8525 static void chv_prepare_pll(struct intel_crtc *crtc,
8526                             const struct intel_crtc_state *pipe_config)
8527 {
8528         struct drm_device *dev = crtc->base.dev;
8529         struct drm_i915_private *dev_priv = to_i915(dev);
8530         enum pipe pipe = crtc->pipe;
8531         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8532         u32 loopfilter, tribuf_calcntr;
8533         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8534         u32 dpio_val;
8535         int vco;
8536
8537         /* Enable Refclk and SSC */
8538         intel_de_write(dev_priv, DPLL(pipe),
8539                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8540
8541         /* No need to actually set up the DPLL with DSI */
8542         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8543                 return;
8544
8545         bestn = pipe_config->dpll.n;
8546         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8547         bestm1 = pipe_config->dpll.m1;
8548         bestm2 = pipe_config->dpll.m2 >> 22;
8549         bestp1 = pipe_config->dpll.p1;
8550         bestp2 = pipe_config->dpll.p2;
8551         vco = pipe_config->dpll.vco;
8552         dpio_val = 0;
8553         loopfilter = 0;
8554
8555         vlv_dpio_get(dev_priv);
8556
8557         /* p1 and p2 divider */
8558         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8559                         5 << DPIO_CHV_S1_DIV_SHIFT |
8560                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8561                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8562                         1 << DPIO_CHV_K_DIV_SHIFT);
8563
8564         /* Feedback post-divider - m2 */
8565         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8566
8567         /* Feedback refclk divider - n and m1 */
8568         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8569                         DPIO_CHV_M1_DIV_BY_2 |
8570                         1 << DPIO_CHV_N_DIV_SHIFT);
8571
8572         /* M2 fraction division */
8573         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8574
8575         /* M2 fraction division enable */
8576         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8577         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8578         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8579         if (bestm2_frac)
8580                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8581         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8582
8583         /* Program digital lock detect threshold */
8584         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8585         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8586                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8587         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8588         if (!bestm2_frac)
8589                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8590         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8591
8592         /* Loop filter */
8593         if (vco == 5400000) {
8594                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8595                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8596                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8597                 tribuf_calcntr = 0x9;
8598         } else if (vco <= 6200000) {
8599                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8600                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8601                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8602                 tribuf_calcntr = 0x9;
8603         } else if (vco <= 6480000) {
8604                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8605                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8606                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8607                 tribuf_calcntr = 0x8;
8608         } else {
8609                 /* Not supported. Apply the same limits as in the max case */
8610                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8611                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8612                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8613                 tribuf_calcntr = 0;
8614         }
8615         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8616
8617         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8618         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8619         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8620         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8621
8622         /* AFC Recal */
8623         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8624                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8625                         DPIO_AFC_RECAL);
8626
8627         vlv_dpio_put(dev_priv);
8628 }
8629
8630 /**
8631  * vlv_force_pll_on - forcibly enable just the PLL
8632  * @dev_priv: i915 private structure
8633  * @pipe: pipe PLL to enable
8634  * @dpll: PLL configuration
8635  *
8636  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8637  * in cases where we need the PLL enabled even when @pipe is not going to
8638  * be enabled.
8639  */
8640 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8641                      const struct dpll *dpll)
8642 {
8643         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8644         struct intel_crtc_state *pipe_config;
8645
8646         pipe_config = intel_crtc_state_alloc(crtc);
8647         if (!pipe_config)
8648                 return -ENOMEM;
8649
8650         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8651         pipe_config->pixel_multiplier = 1;
8652         pipe_config->dpll = *dpll;
8653
8654         if (IS_CHERRYVIEW(dev_priv)) {
8655                 chv_compute_dpll(crtc, pipe_config);
8656                 chv_prepare_pll(crtc, pipe_config);
8657                 chv_enable_pll(crtc, pipe_config);
8658         } else {
8659                 vlv_compute_dpll(crtc, pipe_config);
8660                 vlv_prepare_pll(crtc, pipe_config);
8661                 vlv_enable_pll(crtc, pipe_config);
8662         }
8663
8664         kfree(pipe_config);
8665
8666         return 0;
8667 }
8668
8669 /**
8670  * vlv_force_pll_off - forcibly disable just the PLL
8671  * @dev_priv: i915 private structure
8672  * @pipe: pipe PLL to disable
8673  *
8674  * Disable the PLL for @pipe. To be used in cases where we need
8675  * the PLL enabled even when @pipe is not going to be enabled.
8676  */
8677 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8678 {
8679         if (IS_CHERRYVIEW(dev_priv))
8680                 chv_disable_pll(dev_priv, pipe);
8681         else
8682                 vlv_disable_pll(dev_priv, pipe);
8683 }
8684
8685 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8686                               struct intel_crtc_state *crtc_state,
8687                               struct dpll *reduced_clock)
8688 {
8689         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8690         u32 dpll;
8691         struct dpll *clock = &crtc_state->dpll;
8692
8693         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8694
8695         dpll = DPLL_VGA_MODE_DIS;
8696
8697         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8698                 dpll |= DPLLB_MODE_LVDS;
8699         else
8700                 dpll |= DPLLB_MODE_DAC_SERIAL;
8701
8702         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8703             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8704                 dpll |= (crtc_state->pixel_multiplier - 1)
8705                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8706         }
8707
8708         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8709             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8710                 dpll |= DPLL_SDVO_HIGH_SPEED;
8711
8712         if (intel_crtc_has_dp_encoder(crtc_state))
8713                 dpll |= DPLL_SDVO_HIGH_SPEED;
8714
8715         /* compute bitmask from p1 value */
8716         if (IS_PINEVIEW(dev_priv))
8717                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8718         else {
8719                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8720                 if (IS_G4X(dev_priv) && reduced_clock)
8721                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8722         }
8723         switch (clock->p2) {
8724         case 5:
8725                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8726                 break;
8727         case 7:
8728                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8729                 break;
8730         case 10:
8731                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8732                 break;
8733         case 14:
8734                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8735                 break;
8736         }
8737         if (INTEL_GEN(dev_priv) >= 4)
8738                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8739
8740         if (crtc_state->sdvo_tv_clock)
8741                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8742         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8743                  intel_panel_use_ssc(dev_priv))
8744                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8745         else
8746                 dpll |= PLL_REF_INPUT_DREFCLK;
8747
8748         dpll |= DPLL_VCO_ENABLE;
8749         crtc_state->dpll_hw_state.dpll = dpll;
8750
8751         if (INTEL_GEN(dev_priv) >= 4) {
8752                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8753                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8754                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8755         }
8756 }
8757
8758 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8759                               struct intel_crtc_state *crtc_state,
8760                               struct dpll *reduced_clock)
8761 {
8762         struct drm_device *dev = crtc->base.dev;
8763         struct drm_i915_private *dev_priv = to_i915(dev);
8764         u32 dpll;
8765         struct dpll *clock = &crtc_state->dpll;
8766
8767         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8768
8769         dpll = DPLL_VGA_MODE_DIS;
8770
8771         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8772                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8773         } else {
8774                 if (clock->p1 == 2)
8775                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8776                 else
8777                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8778                 if (clock->p2 == 4)
8779                         dpll |= PLL_P2_DIVIDE_BY_4;
8780         }
8781
8782         /*
8783          * Bspec:
8784          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8785          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8786          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8787          *  Enable) must be set to “1” in both the DPLL A Control Register
8788          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8789          *
8790          * For simplicity We simply keep both bits always enabled in
8791          * both DPLLS. The spec says we should disable the DVO 2X clock
8792          * when not needed, but this seems to work fine in practice.
8793          */
8794         if (IS_I830(dev_priv) ||
8795             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8796                 dpll |= DPLL_DVO_2X_MODE;
8797
8798         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8799             intel_panel_use_ssc(dev_priv))
8800                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8801         else
8802                 dpll |= PLL_REF_INPUT_DREFCLK;
8803
8804         dpll |= DPLL_VCO_ENABLE;
8805         crtc_state->dpll_hw_state.dpll = dpll;
8806 }
8807
8808 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8809 {
8810         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8811         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8812         enum pipe pipe = crtc->pipe;
8813         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8814         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8815         u32 crtc_vtotal, crtc_vblank_end;
8816         int vsyncshift = 0;
8817
8818         /* We need to be careful not to changed the adjusted mode, for otherwise
8819          * the hw state checker will get angry at the mismatch. */
8820         crtc_vtotal = adjusted_mode->crtc_vtotal;
8821         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8822
8823         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8824                 /* the chip adds 2 halflines automatically */
8825                 crtc_vtotal -= 1;
8826                 crtc_vblank_end -= 1;
8827
8828                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8829                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8830                 else
8831                         vsyncshift = adjusted_mode->crtc_hsync_start -
8832                                 adjusted_mode->crtc_htotal / 2;
8833                 if (vsyncshift < 0)
8834                         vsyncshift += adjusted_mode->crtc_htotal;
8835         }
8836
8837         if (INTEL_GEN(dev_priv) > 3)
8838                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8839                                vsyncshift);
8840
8841         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8842                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8843         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8844                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8845         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8846                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8847
8848         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8849                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8850         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8851                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8852         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8853                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8854
8855         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8856          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8857          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8858          * bits. */
8859         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8860             (pipe == PIPE_B || pipe == PIPE_C))
8861                 intel_de_write(dev_priv, VTOTAL(pipe),
8862                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8863
8864 }
8865
8866 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8867 {
8868         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8869         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8870         enum pipe pipe = crtc->pipe;
8871
8872         /* pipesrc controls the size that is scaled from, which should
8873          * always be the user's requested size.
8874          */
8875         intel_de_write(dev_priv, PIPESRC(pipe),
8876                        ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8877 }
8878
8879 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8880 {
8881         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8882         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8883
8884         if (IS_GEN(dev_priv, 2))
8885                 return false;
8886
8887         if (INTEL_GEN(dev_priv) >= 9 ||
8888             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8889                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8890         else
8891                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8892 }
8893
8894 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8895                                    struct intel_crtc_state *pipe_config)
8896 {
8897         struct drm_device *dev = crtc->base.dev;
8898         struct drm_i915_private *dev_priv = to_i915(dev);
8899         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8900         u32 tmp;
8901
8902         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8903         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8904         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8905
8906         if (!transcoder_is_dsi(cpu_transcoder)) {
8907                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8908                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8909                                                         (tmp & 0xffff) + 1;
8910                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8911                                                 ((tmp >> 16) & 0xffff) + 1;
8912         }
8913         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8914         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8915         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8916
8917         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8918         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8919         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8920
8921         if (!transcoder_is_dsi(cpu_transcoder)) {
8922                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8923                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8924                                                         (tmp & 0xffff) + 1;
8925                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8926                                                 ((tmp >> 16) & 0xffff) + 1;
8927         }
8928         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8929         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8930         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8931
8932         if (intel_pipe_is_interlaced(pipe_config)) {
8933                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8934                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8935                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8936         }
8937 }
8938
8939 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8940                                     struct intel_crtc_state *pipe_config)
8941 {
8942         struct drm_device *dev = crtc->base.dev;
8943         struct drm_i915_private *dev_priv = to_i915(dev);
8944         u32 tmp;
8945
8946         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8947         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8948         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8949
8950         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8951         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8952 }
8953
8954 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8955                                  struct intel_crtc_state *pipe_config)
8956 {
8957         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8958         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8959         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8960         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8961
8962         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8963         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8964         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8965         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8966
8967         mode->flags = pipe_config->hw.adjusted_mode.flags;
8968         mode->type = DRM_MODE_TYPE_DRIVER;
8969
8970         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8971
8972         drm_mode_set_name(mode);
8973 }
8974
8975 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8976 {
8977         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8978         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8979         u32 pipeconf;
8980
8981         pipeconf = 0;
8982
8983         /* we keep both pipes enabled on 830 */
8984         if (IS_I830(dev_priv))
8985                 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8986
8987         if (crtc_state->double_wide)
8988                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8989
8990         /* only g4x and later have fancy bpc/dither controls */
8991         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8992             IS_CHERRYVIEW(dev_priv)) {
8993                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8994                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8995                         pipeconf |= PIPECONF_DITHER_EN |
8996                                     PIPECONF_DITHER_TYPE_SP;
8997
8998                 switch (crtc_state->pipe_bpp) {
8999                 case 18:
9000                         pipeconf |= PIPECONF_6BPC;
9001                         break;
9002                 case 24:
9003                         pipeconf |= PIPECONF_8BPC;
9004                         break;
9005                 case 30:
9006                         pipeconf |= PIPECONF_10BPC;
9007                         break;
9008                 default:
9009                         /* Case prevented by intel_choose_pipe_bpp_dither. */
9010                         BUG();
9011                 }
9012         }
9013
9014         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9015                 if (INTEL_GEN(dev_priv) < 4 ||
9016                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9017                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9018                 else
9019                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9020         } else {
9021                 pipeconf |= PIPECONF_PROGRESSIVE;
9022         }
9023
9024         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9025              crtc_state->limited_color_range)
9026                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9027
9028         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9029
9030         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9031
9032         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9033         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9034 }
9035
9036 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9037                                    struct intel_crtc_state *crtc_state)
9038 {
9039         struct drm_device *dev = crtc->base.dev;
9040         struct drm_i915_private *dev_priv = to_i915(dev);
9041         const struct intel_limit *limit;
9042         int refclk = 48000;
9043
9044         memset(&crtc_state->dpll_hw_state, 0,
9045                sizeof(crtc_state->dpll_hw_state));
9046
9047         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9048                 if (intel_panel_use_ssc(dev_priv)) {
9049                         refclk = dev_priv->vbt.lvds_ssc_freq;
9050                         drm_dbg_kms(&dev_priv->drm,
9051                                     "using SSC reference clock of %d kHz\n",
9052                                     refclk);
9053                 }
9054
9055                 limit = &intel_limits_i8xx_lvds;
9056         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9057                 limit = &intel_limits_i8xx_dvo;
9058         } else {
9059                 limit = &intel_limits_i8xx_dac;
9060         }
9061
9062         if (!crtc_state->clock_set &&
9063             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9064                                  refclk, NULL, &crtc_state->dpll)) {
9065                 drm_err(&dev_priv->drm,
9066                         "Couldn't find PLL settings for mode!\n");
9067                 return -EINVAL;
9068         }
9069
9070         i8xx_compute_dpll(crtc, crtc_state, NULL);
9071
9072         return 0;
9073 }
9074
9075 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9076                                   struct intel_crtc_state *crtc_state)
9077 {
9078         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9079         const struct intel_limit *limit;
9080         int refclk = 96000;
9081
9082         memset(&crtc_state->dpll_hw_state, 0,
9083                sizeof(crtc_state->dpll_hw_state));
9084
9085         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9086                 if (intel_panel_use_ssc(dev_priv)) {
9087                         refclk = dev_priv->vbt.lvds_ssc_freq;
9088                         drm_dbg_kms(&dev_priv->drm,
9089                                     "using SSC reference clock of %d kHz\n",
9090                                     refclk);
9091                 }
9092
9093                 if (intel_is_dual_link_lvds(dev_priv))
9094                         limit = &intel_limits_g4x_dual_channel_lvds;
9095                 else
9096                         limit = &intel_limits_g4x_single_channel_lvds;
9097         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9098                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9099                 limit = &intel_limits_g4x_hdmi;
9100         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9101                 limit = &intel_limits_g4x_sdvo;
9102         } else {
9103                 /* The option is for other outputs */
9104                 limit = &intel_limits_i9xx_sdvo;
9105         }
9106
9107         if (!crtc_state->clock_set &&
9108             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9109                                 refclk, NULL, &crtc_state->dpll)) {
9110                 drm_err(&dev_priv->drm,
9111                         "Couldn't find PLL settings for mode!\n");
9112                 return -EINVAL;
9113         }
9114
9115         i9xx_compute_dpll(crtc, crtc_state, NULL);
9116
9117         return 0;
9118 }
9119
9120 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9121                                   struct intel_crtc_state *crtc_state)
9122 {
9123         struct drm_device *dev = crtc->base.dev;
9124         struct drm_i915_private *dev_priv = to_i915(dev);
9125         const struct intel_limit *limit;
9126         int refclk = 96000;
9127
9128         memset(&crtc_state->dpll_hw_state, 0,
9129                sizeof(crtc_state->dpll_hw_state));
9130
9131         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9132                 if (intel_panel_use_ssc(dev_priv)) {
9133                         refclk = dev_priv->vbt.lvds_ssc_freq;
9134                         drm_dbg_kms(&dev_priv->drm,
9135                                     "using SSC reference clock of %d kHz\n",
9136                                     refclk);
9137                 }
9138
9139                 limit = &pnv_limits_lvds;
9140         } else {
9141                 limit = &pnv_limits_sdvo;
9142         }
9143
9144         if (!crtc_state->clock_set &&
9145             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9146                                 refclk, NULL, &crtc_state->dpll)) {
9147                 drm_err(&dev_priv->drm,
9148                         "Couldn't find PLL settings for mode!\n");
9149                 return -EINVAL;
9150         }
9151
9152         i9xx_compute_dpll(crtc, crtc_state, NULL);
9153
9154         return 0;
9155 }
9156
9157 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9158                                    struct intel_crtc_state *crtc_state)
9159 {
9160         struct drm_device *dev = crtc->base.dev;
9161         struct drm_i915_private *dev_priv = to_i915(dev);
9162         const struct intel_limit *limit;
9163         int refclk = 96000;
9164
9165         memset(&crtc_state->dpll_hw_state, 0,
9166                sizeof(crtc_state->dpll_hw_state));
9167
9168         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9169                 if (intel_panel_use_ssc(dev_priv)) {
9170                         refclk = dev_priv->vbt.lvds_ssc_freq;
9171                         drm_dbg_kms(&dev_priv->drm,
9172                                     "using SSC reference clock of %d kHz\n",
9173                                     refclk);
9174                 }
9175
9176                 limit = &intel_limits_i9xx_lvds;
9177         } else {
9178                 limit = &intel_limits_i9xx_sdvo;
9179         }
9180
9181         if (!crtc_state->clock_set &&
9182             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9183                                  refclk, NULL, &crtc_state->dpll)) {
9184                 drm_err(&dev_priv->drm,
9185                         "Couldn't find PLL settings for mode!\n");
9186                 return -EINVAL;
9187         }
9188
9189         i9xx_compute_dpll(crtc, crtc_state, NULL);
9190
9191         return 0;
9192 }
9193
9194 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9195                                   struct intel_crtc_state *crtc_state)
9196 {
9197         int refclk = 100000;
9198         const struct intel_limit *limit = &intel_limits_chv;
9199         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9200
9201         memset(&crtc_state->dpll_hw_state, 0,
9202                sizeof(crtc_state->dpll_hw_state));
9203
9204         if (!crtc_state->clock_set &&
9205             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9206                                 refclk, NULL, &crtc_state->dpll)) {
9207                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9208                 return -EINVAL;
9209         }
9210
9211         chv_compute_dpll(crtc, crtc_state);
9212
9213         return 0;
9214 }
9215
9216 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9217                                   struct intel_crtc_state *crtc_state)
9218 {
9219         int refclk = 100000;
9220         const struct intel_limit *limit = &intel_limits_vlv;
9221         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9222
9223         memset(&crtc_state->dpll_hw_state, 0,
9224                sizeof(crtc_state->dpll_hw_state));
9225
9226         if (!crtc_state->clock_set &&
9227             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9228                                 refclk, NULL, &crtc_state->dpll)) {
9229                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
9230                 return -EINVAL;
9231         }
9232
9233         vlv_compute_dpll(crtc, crtc_state);
9234
9235         return 0;
9236 }
9237
9238 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9239 {
9240         if (IS_I830(dev_priv))
9241                 return false;
9242
9243         return INTEL_GEN(dev_priv) >= 4 ||
9244                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9245 }
9246
9247 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9248 {
9249         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9250         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9251         u32 tmp;
9252
9253         if (!i9xx_has_pfit(dev_priv))
9254                 return;
9255
9256         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9257         if (!(tmp & PFIT_ENABLE))
9258                 return;
9259
9260         /* Check whether the pfit is attached to our pipe. */
9261         if (INTEL_GEN(dev_priv) < 4) {
9262                 if (crtc->pipe != PIPE_B)
9263                         return;
9264         } else {
9265                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9266                         return;
9267         }
9268
9269         crtc_state->gmch_pfit.control = tmp;
9270         crtc_state->gmch_pfit.pgm_ratios =
9271                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9272 }
9273
9274 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9275                                struct intel_crtc_state *pipe_config)
9276 {
9277         struct drm_device *dev = crtc->base.dev;
9278         struct drm_i915_private *dev_priv = to_i915(dev);
9279         enum pipe pipe = crtc->pipe;
9280         struct dpll clock;
9281         u32 mdiv;
9282         int refclk = 100000;
9283
9284         /* In case of DSI, DPLL will not be used */
9285         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9286                 return;
9287
9288         vlv_dpio_get(dev_priv);
9289         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9290         vlv_dpio_put(dev_priv);
9291
9292         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9293         clock.m2 = mdiv & DPIO_M2DIV_MASK;
9294         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9295         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9296         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9297
9298         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9299 }
9300
9301 static void
9302 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9303                               struct intel_initial_plane_config *plane_config)
9304 {
9305         struct drm_device *dev = crtc->base.dev;
9306         struct drm_i915_private *dev_priv = to_i915(dev);
9307         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9308         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9309         enum pipe pipe;
9310         u32 val, base, offset;
9311         int fourcc, pixel_format;
9312         unsigned int aligned_height;
9313         struct drm_framebuffer *fb;
9314         struct intel_framebuffer *intel_fb;
9315
9316         if (!plane->get_hw_state(plane, &pipe))
9317                 return;
9318
9319         drm_WARN_ON(dev, pipe != crtc->pipe);
9320
9321         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9322         if (!intel_fb) {
9323                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9324                 return;
9325         }
9326
9327         fb = &intel_fb->base;
9328
9329         fb->dev = dev;
9330
9331         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9332
9333         if (INTEL_GEN(dev_priv) >= 4) {
9334                 if (val & DISPPLANE_TILED) {
9335                         plane_config->tiling = I915_TILING_X;
9336                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9337                 }
9338
9339                 if (val & DISPPLANE_ROTATE_180)
9340                         plane_config->rotation = DRM_MODE_ROTATE_180;
9341         }
9342
9343         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9344             val & DISPPLANE_MIRROR)
9345                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9346
9347         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9348         fourcc = i9xx_format_to_fourcc(pixel_format);
9349         fb->format = drm_format_info(fourcc);
9350
9351         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9352                 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9353                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9354         } else if (INTEL_GEN(dev_priv) >= 4) {
9355                 if (plane_config->tiling)
9356                         offset = intel_de_read(dev_priv,
9357                                                DSPTILEOFF(i9xx_plane));
9358                 else
9359                         offset = intel_de_read(dev_priv,
9360                                                DSPLINOFF(i9xx_plane));
9361                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9362         } else {
9363                 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9364         }
9365         plane_config->base = base;
9366
9367         val = intel_de_read(dev_priv, PIPESRC(pipe));
9368         fb->width = ((val >> 16) & 0xfff) + 1;
9369         fb->height = ((val >> 0) & 0xfff) + 1;
9370
9371         val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9372         fb->pitches[0] = val & 0xffffffc0;
9373
9374         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9375
9376         plane_config->size = fb->pitches[0] * aligned_height;
9377
9378         drm_dbg_kms(&dev_priv->drm,
9379                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9380                     crtc->base.name, plane->base.name, fb->width, fb->height,
9381                     fb->format->cpp[0] * 8, base, fb->pitches[0],
9382                     plane_config->size);
9383
9384         plane_config->fb = intel_fb;
9385 }
9386
9387 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9388                                struct intel_crtc_state *pipe_config)
9389 {
9390         struct drm_device *dev = crtc->base.dev;
9391         struct drm_i915_private *dev_priv = to_i915(dev);
9392         enum pipe pipe = crtc->pipe;
9393         enum dpio_channel port = vlv_pipe_to_channel(pipe);
9394         struct dpll clock;
9395         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9396         int refclk = 100000;
9397
9398         /* In case of DSI, DPLL will not be used */
9399         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9400                 return;
9401
9402         vlv_dpio_get(dev_priv);
9403         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9404         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9405         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9406         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9407         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9408         vlv_dpio_put(dev_priv);
9409
9410         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9411         clock.m2 = (pll_dw0 & 0xff) << 22;
9412         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9413                 clock.m2 |= pll_dw2 & 0x3fffff;
9414         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9415         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9416         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9417
9418         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9419 }
9420
9421 static enum intel_output_format
9422 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9423 {
9424         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9425         u32 tmp;
9426
9427         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9428
9429         if (tmp & PIPEMISC_YUV420_ENABLE) {
9430                 /* We support 4:2:0 in full blend mode only */
9431                 drm_WARN_ON(&dev_priv->drm,
9432                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9433
9434                 return INTEL_OUTPUT_FORMAT_YCBCR420;
9435         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9436                 return INTEL_OUTPUT_FORMAT_YCBCR444;
9437         } else {
9438                 return INTEL_OUTPUT_FORMAT_RGB;
9439         }
9440 }
9441
9442 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9443 {
9444         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9445         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9446         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9447         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9448         u32 tmp;
9449
9450         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9451
9452         if (tmp & DISPPLANE_GAMMA_ENABLE)
9453                 crtc_state->gamma_enable = true;
9454
9455         if (!HAS_GMCH(dev_priv) &&
9456             tmp & DISPPLANE_PIPE_CSC_ENABLE)
9457                 crtc_state->csc_enable = true;
9458 }
9459
9460 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9461                                  struct intel_crtc_state *pipe_config)
9462 {
9463         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9464         enum intel_display_power_domain power_domain;
9465         intel_wakeref_t wakeref;
9466         u32 tmp;
9467         bool ret;
9468
9469         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9470         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9471         if (!wakeref)
9472                 return false;
9473
9474         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9475         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9476         pipe_config->shared_dpll = NULL;
9477
9478         ret = false;
9479
9480         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9481         if (!(tmp & PIPECONF_ENABLE))
9482                 goto out;
9483
9484         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9485             IS_CHERRYVIEW(dev_priv)) {
9486                 switch (tmp & PIPECONF_BPC_MASK) {
9487                 case PIPECONF_6BPC:
9488                         pipe_config->pipe_bpp = 18;
9489                         break;
9490                 case PIPECONF_8BPC:
9491                         pipe_config->pipe_bpp = 24;
9492                         break;
9493                 case PIPECONF_10BPC:
9494                         pipe_config->pipe_bpp = 30;
9495                         break;
9496                 default:
9497                         break;
9498                 }
9499         }
9500
9501         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9502             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9503                 pipe_config->limited_color_range = true;
9504
9505         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9506                 PIPECONF_GAMMA_MODE_SHIFT;
9507
9508         if (IS_CHERRYVIEW(dev_priv))
9509                 pipe_config->cgm_mode = intel_de_read(dev_priv,
9510                                                       CGM_PIPE_MODE(crtc->pipe));
9511
9512         i9xx_get_pipe_color_config(pipe_config);
9513         intel_color_get_config(pipe_config);
9514
9515         if (INTEL_GEN(dev_priv) < 4)
9516                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9517
9518         intel_get_pipe_timings(crtc, pipe_config);
9519         intel_get_pipe_src_size(crtc, pipe_config);
9520
9521         i9xx_get_pfit_config(pipe_config);
9522
9523         if (INTEL_GEN(dev_priv) >= 4) {
9524                 /* No way to read it out on pipes B and C */
9525                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9526                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9527                 else
9528                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9529                 pipe_config->pixel_multiplier =
9530                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9531                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9532                 pipe_config->dpll_hw_state.dpll_md = tmp;
9533         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9534                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9535                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9536                 pipe_config->pixel_multiplier =
9537                         ((tmp & SDVO_MULTIPLIER_MASK)
9538                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9539         } else {
9540                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9541                  * port and will be fixed up in the encoder->get_config
9542                  * function. */
9543                 pipe_config->pixel_multiplier = 1;
9544         }
9545         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9546                                                         DPLL(crtc->pipe));
9547         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9548                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9549                                                                FP0(crtc->pipe));
9550                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9551                                                                FP1(crtc->pipe));
9552         } else {
9553                 /* Mask out read-only status bits. */
9554                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9555                                                      DPLL_PORTC_READY_MASK |
9556                                                      DPLL_PORTB_READY_MASK);
9557         }
9558
9559         if (IS_CHERRYVIEW(dev_priv))
9560                 chv_crtc_clock_get(crtc, pipe_config);
9561         else if (IS_VALLEYVIEW(dev_priv))
9562                 vlv_crtc_clock_get(crtc, pipe_config);
9563         else
9564                 i9xx_crtc_clock_get(crtc, pipe_config);
9565
9566         /*
9567          * Normally the dotclock is filled in by the encoder .get_config()
9568          * but in case the pipe is enabled w/o any ports we need a sane
9569          * default.
9570          */
9571         pipe_config->hw.adjusted_mode.crtc_clock =
9572                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9573
9574         ret = true;
9575
9576 out:
9577         intel_display_power_put(dev_priv, power_domain, wakeref);
9578
9579         return ret;
9580 }
9581
9582 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9583 {
9584         struct intel_encoder *encoder;
9585         int i;
9586         u32 val, final;
9587         bool has_lvds = false;
9588         bool has_cpu_edp = false;
9589         bool has_panel = false;
9590         bool has_ck505 = false;
9591         bool can_ssc = false;
9592         bool using_ssc_source = false;
9593
9594         /* We need to take the global config into account */
9595         for_each_intel_encoder(&dev_priv->drm, encoder) {
9596                 switch (encoder->type) {
9597                 case INTEL_OUTPUT_LVDS:
9598                         has_panel = true;
9599                         has_lvds = true;
9600                         break;
9601                 case INTEL_OUTPUT_EDP:
9602                         has_panel = true;
9603                         if (encoder->port == PORT_A)
9604                                 has_cpu_edp = true;
9605                         break;
9606                 default:
9607                         break;
9608                 }
9609         }
9610
9611         if (HAS_PCH_IBX(dev_priv)) {
9612                 has_ck505 = dev_priv->vbt.display_clock_mode;
9613                 can_ssc = has_ck505;
9614         } else {
9615                 has_ck505 = false;
9616                 can_ssc = true;
9617         }
9618
9619         /* Check if any DPLLs are using the SSC source */
9620         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9621                 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9622
9623                 if (!(temp & DPLL_VCO_ENABLE))
9624                         continue;
9625
9626                 if ((temp & PLL_REF_INPUT_MASK) ==
9627                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9628                         using_ssc_source = true;
9629                         break;
9630                 }
9631         }
9632
9633         drm_dbg_kms(&dev_priv->drm,
9634                     "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9635                     has_panel, has_lvds, has_ck505, using_ssc_source);
9636
9637         /* Ironlake: try to setup display ref clock before DPLL
9638          * enabling. This is only under driver's control after
9639          * PCH B stepping, previous chipset stepping should be
9640          * ignoring this setting.
9641          */
9642         val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9643
9644         /* As we must carefully and slowly disable/enable each source in turn,
9645          * compute the final state we want first and check if we need to
9646          * make any changes at all.
9647          */
9648         final = val;
9649         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9650         if (has_ck505)
9651                 final |= DREF_NONSPREAD_CK505_ENABLE;
9652         else
9653                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9654
9655         final &= ~DREF_SSC_SOURCE_MASK;
9656         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9657         final &= ~DREF_SSC1_ENABLE;
9658
9659         if (has_panel) {
9660                 final |= DREF_SSC_SOURCE_ENABLE;
9661
9662                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9663                         final |= DREF_SSC1_ENABLE;
9664
9665                 if (has_cpu_edp) {
9666                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9667                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9668                         else
9669                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9670                 } else
9671                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9672         } else if (using_ssc_source) {
9673                 final |= DREF_SSC_SOURCE_ENABLE;
9674                 final |= DREF_SSC1_ENABLE;
9675         }
9676
9677         if (final == val)
9678                 return;
9679
9680         /* Always enable nonspread source */
9681         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9682
9683         if (has_ck505)
9684                 val |= DREF_NONSPREAD_CK505_ENABLE;
9685         else
9686                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9687
9688         if (has_panel) {
9689                 val &= ~DREF_SSC_SOURCE_MASK;
9690                 val |= DREF_SSC_SOURCE_ENABLE;
9691
9692                 /* SSC must be turned on before enabling the CPU output  */
9693                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9694                         drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9695                         val |= DREF_SSC1_ENABLE;
9696                 } else
9697                         val &= ~DREF_SSC1_ENABLE;
9698
9699                 /* Get SSC going before enabling the outputs */
9700                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9701                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9702                 udelay(200);
9703
9704                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9705
9706                 /* Enable CPU source on CPU attached eDP */
9707                 if (has_cpu_edp) {
9708                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9709                                 drm_dbg_kms(&dev_priv->drm,
9710                                             "Using SSC on eDP\n");
9711                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9712                         } else
9713                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9714                 } else
9715                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9716
9717                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9718                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9719                 udelay(200);
9720         } else {
9721                 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9722
9723                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9724
9725                 /* Turn off CPU output */
9726                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9727
9728                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9729                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9730                 udelay(200);
9731
9732                 if (!using_ssc_source) {
9733                         drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9734
9735                         /* Turn off the SSC source */
9736                         val &= ~DREF_SSC_SOURCE_MASK;
9737                         val |= DREF_SSC_SOURCE_DISABLE;
9738
9739                         /* Turn off SSC1 */
9740                         val &= ~DREF_SSC1_ENABLE;
9741
9742                         intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9743                         intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9744                         udelay(200);
9745                 }
9746         }
9747
9748         BUG_ON(val != final);
9749 }
9750
9751 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9752 {
9753         u32 tmp;
9754
9755         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9756         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9757         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9758
9759         if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9760                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9761                 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9762
9763         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9764         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9765         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9766
9767         if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9768                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9769                 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9770 }
9771
9772 /* WaMPhyProgramming:hsw */
9773 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9774 {
9775         u32 tmp;
9776
9777         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9778         tmp &= ~(0xFF << 24);
9779         tmp |= (0x12 << 24);
9780         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9781
9782         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9783         tmp |= (1 << 11);
9784         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9785
9786         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9787         tmp |= (1 << 11);
9788         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9789
9790         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9791         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9792         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9793
9794         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9795         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9796         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9797
9798         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9799         tmp &= ~(7 << 13);
9800         tmp |= (5 << 13);
9801         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9802
9803         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9804         tmp &= ~(7 << 13);
9805         tmp |= (5 << 13);
9806         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9807
9808         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9809         tmp &= ~0xFF;
9810         tmp |= 0x1C;
9811         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9812
9813         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9814         tmp &= ~0xFF;
9815         tmp |= 0x1C;
9816         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9817
9818         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9819         tmp &= ~(0xFF << 16);
9820         tmp |= (0x1C << 16);
9821         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9822
9823         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9824         tmp &= ~(0xFF << 16);
9825         tmp |= (0x1C << 16);
9826         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9827
9828         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9829         tmp |= (1 << 27);
9830         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9831
9832         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9833         tmp |= (1 << 27);
9834         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9835
9836         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9837         tmp &= ~(0xF << 28);
9838         tmp |= (4 << 28);
9839         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9840
9841         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9842         tmp &= ~(0xF << 28);
9843         tmp |= (4 << 28);
9844         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9845 }
9846
9847 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9848  * Programming" based on the parameters passed:
9849  * - Sequence to enable CLKOUT_DP
9850  * - Sequence to enable CLKOUT_DP without spread
9851  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9852  */
9853 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9854                                  bool with_spread, bool with_fdi)
9855 {
9856         u32 reg, tmp;
9857
9858         if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9859                      "FDI requires downspread\n"))
9860                 with_spread = true;
9861         if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9862                      with_fdi, "LP PCH doesn't have FDI\n"))
9863                 with_fdi = false;
9864
9865         mutex_lock(&dev_priv->sb_lock);
9866
9867         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9868         tmp &= ~SBI_SSCCTL_DISABLE;
9869         tmp |= SBI_SSCCTL_PATHALT;
9870         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9871
9872         udelay(24);
9873
9874         if (with_spread) {
9875                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9876                 tmp &= ~SBI_SSCCTL_PATHALT;
9877                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9878
9879                 if (with_fdi) {
9880                         lpt_reset_fdi_mphy(dev_priv);
9881                         lpt_program_fdi_mphy(dev_priv);
9882                 }
9883         }
9884
9885         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9886         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9887         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9888         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9889
9890         mutex_unlock(&dev_priv->sb_lock);
9891 }
9892
9893 /* Sequence to disable CLKOUT_DP */
9894 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9895 {
9896         u32 reg, tmp;
9897
9898         mutex_lock(&dev_priv->sb_lock);
9899
9900         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9901         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9902         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9903         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9904
9905         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9906         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9907                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9908                         tmp |= SBI_SSCCTL_PATHALT;
9909                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9910                         udelay(32);
9911                 }
9912                 tmp |= SBI_SSCCTL_DISABLE;
9913                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9914         }
9915
9916         mutex_unlock(&dev_priv->sb_lock);
9917 }
9918
9919 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9920
9921 static const u16 sscdivintphase[] = {
9922         [BEND_IDX( 50)] = 0x3B23,
9923         [BEND_IDX( 45)] = 0x3B23,
9924         [BEND_IDX( 40)] = 0x3C23,
9925         [BEND_IDX( 35)] = 0x3C23,
9926         [BEND_IDX( 30)] = 0x3D23,
9927         [BEND_IDX( 25)] = 0x3D23,
9928         [BEND_IDX( 20)] = 0x3E23,
9929         [BEND_IDX( 15)] = 0x3E23,
9930         [BEND_IDX( 10)] = 0x3F23,
9931         [BEND_IDX(  5)] = 0x3F23,
9932         [BEND_IDX(  0)] = 0x0025,
9933         [BEND_IDX( -5)] = 0x0025,
9934         [BEND_IDX(-10)] = 0x0125,
9935         [BEND_IDX(-15)] = 0x0125,
9936         [BEND_IDX(-20)] = 0x0225,
9937         [BEND_IDX(-25)] = 0x0225,
9938         [BEND_IDX(-30)] = 0x0325,
9939         [BEND_IDX(-35)] = 0x0325,
9940         [BEND_IDX(-40)] = 0x0425,
9941         [BEND_IDX(-45)] = 0x0425,
9942         [BEND_IDX(-50)] = 0x0525,
9943 };
9944
9945 /*
9946  * Bend CLKOUT_DP
9947  * steps -50 to 50 inclusive, in steps of 5
9948  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9949  * change in clock period = -(steps / 10) * 5.787 ps
9950  */
9951 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9952 {
9953         u32 tmp;
9954         int idx = BEND_IDX(steps);
9955
9956         if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9957                 return;
9958
9959         if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9960                 return;
9961
9962         mutex_lock(&dev_priv->sb_lock);
9963
9964         if (steps % 10 != 0)
9965                 tmp = 0xAAAAAAAB;
9966         else
9967                 tmp = 0x00000000;
9968         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9969
9970         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9971         tmp &= 0xffff0000;
9972         tmp |= sscdivintphase[idx];
9973         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9974
9975         mutex_unlock(&dev_priv->sb_lock);
9976 }
9977
9978 #undef BEND_IDX
9979
9980 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9981 {
9982         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9983         u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9984
9985         if ((ctl & SPLL_PLL_ENABLE) == 0)
9986                 return false;
9987
9988         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9989             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9990                 return true;
9991
9992         if (IS_BROADWELL(dev_priv) &&
9993             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9994                 return true;
9995
9996         return false;
9997 }
9998
9999 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10000                                enum intel_dpll_id id)
10001 {
10002         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10003         u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10004
10005         if ((ctl & WRPLL_PLL_ENABLE) == 0)
10006                 return false;
10007
10008         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10009                 return true;
10010
10011         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10012             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10013             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10014                 return true;
10015
10016         return false;
10017 }
10018
10019 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10020 {
10021         struct intel_encoder *encoder;
10022         bool has_fdi = false;
10023
10024         for_each_intel_encoder(&dev_priv->drm, encoder) {
10025                 switch (encoder->type) {
10026                 case INTEL_OUTPUT_ANALOG:
10027                         has_fdi = true;
10028                         break;
10029                 default:
10030                         break;
10031                 }
10032         }
10033
10034         /*
10035          * The BIOS may have decided to use the PCH SSC
10036          * reference so we must not disable it until the
10037          * relevant PLLs have stopped relying on it. We'll
10038          * just leave the PCH SSC reference enabled in case
10039          * any active PLL is using it. It will get disabled
10040          * after runtime suspend if we don't have FDI.
10041          *
10042          * TODO: Move the whole reference clock handling
10043          * to the modeset sequence proper so that we can
10044          * actually enable/disable/reconfigure these things
10045          * safely. To do that we need to introduce a real
10046          * clock hierarchy. That would also allow us to do
10047          * clock bending finally.
10048          */
10049         dev_priv->pch_ssc_use = 0;
10050
10051         if (spll_uses_pch_ssc(dev_priv)) {
10052                 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10053                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10054         }
10055
10056         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10057                 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10058                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10059         }
10060
10061         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10062                 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10063                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10064         }
10065
10066         if (dev_priv->pch_ssc_use)
10067                 return;
10068
10069         if (has_fdi) {
10070                 lpt_bend_clkout_dp(dev_priv, 0);
10071                 lpt_enable_clkout_dp(dev_priv, true, true);
10072         } else {
10073                 lpt_disable_clkout_dp(dev_priv);
10074         }
10075 }
10076
10077 /*
10078  * Initialize reference clocks when the driver loads
10079  */
10080 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10081 {
10082         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10083                 ilk_init_pch_refclk(dev_priv);
10084         else if (HAS_PCH_LPT(dev_priv))
10085                 lpt_init_pch_refclk(dev_priv);
10086 }
10087
10088 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10089 {
10090         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10091         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10092         enum pipe pipe = crtc->pipe;
10093         u32 val;
10094
10095         val = 0;
10096
10097         switch (crtc_state->pipe_bpp) {
10098         case 18:
10099                 val |= PIPECONF_6BPC;
10100                 break;
10101         case 24:
10102                 val |= PIPECONF_8BPC;
10103                 break;
10104         case 30:
10105                 val |= PIPECONF_10BPC;
10106                 break;
10107         case 36:
10108                 val |= PIPECONF_12BPC;
10109                 break;
10110         default:
10111                 /* Case prevented by intel_choose_pipe_bpp_dither. */
10112                 BUG();
10113         }
10114
10115         if (crtc_state->dither)
10116                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10117
10118         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10119                 val |= PIPECONF_INTERLACED_ILK;
10120         else
10121                 val |= PIPECONF_PROGRESSIVE;
10122
10123         /*
10124          * This would end up with an odd purple hue over
10125          * the entire display. Make sure we don't do it.
10126          */
10127         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10128                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10129
10130         if (crtc_state->limited_color_range &&
10131             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10132                 val |= PIPECONF_COLOR_RANGE_SELECT;
10133
10134         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10135                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10136
10137         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10138
10139         val |= PIPECONF_FRAME_START_DELAY(0);
10140
10141         intel_de_write(dev_priv, PIPECONF(pipe), val);
10142         intel_de_posting_read(dev_priv, PIPECONF(pipe));
10143 }
10144
10145 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10146 {
10147         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10148         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10149         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10150         u32 val = 0;
10151
10152         if (IS_HASWELL(dev_priv) && crtc_state->dither)
10153                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10154
10155         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10156                 val |= PIPECONF_INTERLACED_ILK;
10157         else
10158                 val |= PIPECONF_PROGRESSIVE;
10159
10160         if (IS_HASWELL(dev_priv) &&
10161             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10162                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10163
10164         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10165         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10166 }
10167
10168 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10169 {
10170         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10171         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10172         u32 val = 0;
10173
10174         switch (crtc_state->pipe_bpp) {
10175         case 18:
10176                 val |= PIPEMISC_DITHER_6_BPC;
10177                 break;
10178         case 24:
10179                 val |= PIPEMISC_DITHER_8_BPC;
10180                 break;
10181         case 30:
10182                 val |= PIPEMISC_DITHER_10_BPC;
10183                 break;
10184         case 36:
10185                 val |= PIPEMISC_DITHER_12_BPC;
10186                 break;
10187         default:
10188                 MISSING_CASE(crtc_state->pipe_bpp);
10189                 break;
10190         }
10191
10192         if (crtc_state->dither)
10193                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10194
10195         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10196             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10197                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10198
10199         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10200                 val |= PIPEMISC_YUV420_ENABLE |
10201                         PIPEMISC_YUV420_MODE_FULL_BLEND;
10202
10203         if (INTEL_GEN(dev_priv) >= 11 &&
10204             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10205                                            BIT(PLANE_CURSOR))) == 0)
10206                 val |= PIPEMISC_HDR_MODE_PRECISION;
10207
10208         if (INTEL_GEN(dev_priv) >= 12)
10209                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10210
10211         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10212 }
10213
10214 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10215 {
10216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10217         u32 tmp;
10218
10219         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10220
10221         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10222         case PIPEMISC_DITHER_6_BPC:
10223                 return 18;
10224         case PIPEMISC_DITHER_8_BPC:
10225                 return 24;
10226         case PIPEMISC_DITHER_10_BPC:
10227                 return 30;
10228         case PIPEMISC_DITHER_12_BPC:
10229                 return 36;
10230         default:
10231                 MISSING_CASE(tmp);
10232                 return 0;
10233         }
10234 }
10235
10236 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10237 {
10238         /*
10239          * Account for spread spectrum to avoid
10240          * oversubscribing the link. Max center spread
10241          * is 2.5%; use 5% for safety's sake.
10242          */
10243         u32 bps = target_clock * bpp * 21 / 20;
10244         return DIV_ROUND_UP(bps, link_bw * 8);
10245 }
10246
10247 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10248 {
10249         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10250 }
10251
10252 static void ilk_compute_dpll(struct intel_crtc *crtc,
10253                              struct intel_crtc_state *crtc_state,
10254                              struct dpll *reduced_clock)
10255 {
10256         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10257         u32 dpll, fp, fp2;
10258         int factor;
10259
10260         /* Enable autotuning of the PLL clock (if permissible) */
10261         factor = 21;
10262         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10263                 if ((intel_panel_use_ssc(dev_priv) &&
10264                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
10265                     (HAS_PCH_IBX(dev_priv) &&
10266                      intel_is_dual_link_lvds(dev_priv)))
10267                         factor = 25;
10268         } else if (crtc_state->sdvo_tv_clock) {
10269                 factor = 20;
10270         }
10271
10272         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10273
10274         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10275                 fp |= FP_CB_TUNE;
10276
10277         if (reduced_clock) {
10278                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10279
10280                 if (reduced_clock->m < factor * reduced_clock->n)
10281                         fp2 |= FP_CB_TUNE;
10282         } else {
10283                 fp2 = fp;
10284         }
10285
10286         dpll = 0;
10287
10288         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10289                 dpll |= DPLLB_MODE_LVDS;
10290         else
10291                 dpll |= DPLLB_MODE_DAC_SERIAL;
10292
10293         dpll |= (crtc_state->pixel_multiplier - 1)
10294                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10295
10296         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10297             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10298                 dpll |= DPLL_SDVO_HIGH_SPEED;
10299
10300         if (intel_crtc_has_dp_encoder(crtc_state))
10301                 dpll |= DPLL_SDVO_HIGH_SPEED;
10302
10303         /*
10304          * The high speed IO clock is only really required for
10305          * SDVO/HDMI/DP, but we also enable it for CRT to make it
10306          * possible to share the DPLL between CRT and HDMI. Enabling
10307          * the clock needlessly does no real harm, except use up a
10308          * bit of power potentially.
10309          *
10310          * We'll limit this to IVB with 3 pipes, since it has only two
10311          * DPLLs and so DPLL sharing is the only way to get three pipes
10312          * driving PCH ports at the same time. On SNB we could do this,
10313          * and potentially avoid enabling the second DPLL, but it's not
10314          * clear if it''s a win or loss power wise. No point in doing
10315          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10316          */
10317         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10318             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10319                 dpll |= DPLL_SDVO_HIGH_SPEED;
10320
10321         /* compute bitmask from p1 value */
10322         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10323         /* also FPA1 */
10324         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10325
10326         switch (crtc_state->dpll.p2) {
10327         case 5:
10328                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10329                 break;
10330         case 7:
10331                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10332                 break;
10333         case 10:
10334                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10335                 break;
10336         case 14:
10337                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10338                 break;
10339         }
10340
10341         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10342             intel_panel_use_ssc(dev_priv))
10343                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10344         else
10345                 dpll |= PLL_REF_INPUT_DREFCLK;
10346
10347         dpll |= DPLL_VCO_ENABLE;
10348
10349         crtc_state->dpll_hw_state.dpll = dpll;
10350         crtc_state->dpll_hw_state.fp0 = fp;
10351         crtc_state->dpll_hw_state.fp1 = fp2;
10352 }
10353
10354 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10355                                   struct intel_crtc_state *crtc_state)
10356 {
10357         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10358         struct intel_atomic_state *state =
10359                 to_intel_atomic_state(crtc_state->uapi.state);
10360         const struct intel_limit *limit;
10361         int refclk = 120000;
10362
10363         memset(&crtc_state->dpll_hw_state, 0,
10364                sizeof(crtc_state->dpll_hw_state));
10365
10366         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10367         if (!crtc_state->has_pch_encoder)
10368                 return 0;
10369
10370         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10371                 if (intel_panel_use_ssc(dev_priv)) {
10372                         drm_dbg_kms(&dev_priv->drm,
10373                                     "using SSC reference clock of %d kHz\n",
10374                                     dev_priv->vbt.lvds_ssc_freq);
10375                         refclk = dev_priv->vbt.lvds_ssc_freq;
10376                 }
10377
10378                 if (intel_is_dual_link_lvds(dev_priv)) {
10379                         if (refclk == 100000)
10380                                 limit = &ilk_limits_dual_lvds_100m;
10381                         else
10382                                 limit = &ilk_limits_dual_lvds;
10383                 } else {
10384                         if (refclk == 100000)
10385                                 limit = &ilk_limits_single_lvds_100m;
10386                         else
10387                                 limit = &ilk_limits_single_lvds;
10388                 }
10389         } else {
10390                 limit = &ilk_limits_dac;
10391         }
10392
10393         if (!crtc_state->clock_set &&
10394             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10395                                 refclk, NULL, &crtc_state->dpll)) {
10396                 drm_err(&dev_priv->drm,
10397                         "Couldn't find PLL settings for mode!\n");
10398                 return -EINVAL;
10399         }
10400
10401         ilk_compute_dpll(crtc, crtc_state, NULL);
10402
10403         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10404                 drm_dbg_kms(&dev_priv->drm,
10405                             "failed to find PLL for pipe %c\n",
10406                             pipe_name(crtc->pipe));
10407                 return -EINVAL;
10408         }
10409
10410         return 0;
10411 }
10412
10413 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10414                                          struct intel_link_m_n *m_n)
10415 {
10416         struct drm_device *dev = crtc->base.dev;
10417         struct drm_i915_private *dev_priv = to_i915(dev);
10418         enum pipe pipe = crtc->pipe;
10419
10420         m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10421         m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10422         m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10423                 & ~TU_SIZE_MASK;
10424         m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10425         m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10426                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10427 }
10428
10429 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10430                                          enum transcoder transcoder,
10431                                          struct intel_link_m_n *m_n,
10432                                          struct intel_link_m_n *m2_n2)
10433 {
10434         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10435         enum pipe pipe = crtc->pipe;
10436
10437         if (INTEL_GEN(dev_priv) >= 5) {
10438                 m_n->link_m = intel_de_read(dev_priv,
10439                                             PIPE_LINK_M1(transcoder));
10440                 m_n->link_n = intel_de_read(dev_priv,
10441                                             PIPE_LINK_N1(transcoder));
10442                 m_n->gmch_m = intel_de_read(dev_priv,
10443                                             PIPE_DATA_M1(transcoder))
10444                         & ~TU_SIZE_MASK;
10445                 m_n->gmch_n = intel_de_read(dev_priv,
10446                                             PIPE_DATA_N1(transcoder));
10447                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10448                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10449
10450                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10451                         m2_n2->link_m = intel_de_read(dev_priv,
10452                                                       PIPE_LINK_M2(transcoder));
10453                         m2_n2->link_n = intel_de_read(dev_priv,
10454                                                              PIPE_LINK_N2(transcoder));
10455                         m2_n2->gmch_m = intel_de_read(dev_priv,
10456                                                              PIPE_DATA_M2(transcoder))
10457                                         & ~TU_SIZE_MASK;
10458                         m2_n2->gmch_n = intel_de_read(dev_priv,
10459                                                              PIPE_DATA_N2(transcoder));
10460                         m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10461                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10462                 }
10463         } else {
10464                 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10465                 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10466                 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10467                         & ~TU_SIZE_MASK;
10468                 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10469                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10470                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10471         }
10472 }
10473
10474 void intel_dp_get_m_n(struct intel_crtc *crtc,
10475                       struct intel_crtc_state *pipe_config)
10476 {
10477         if (pipe_config->has_pch_encoder)
10478                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10479         else
10480                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10481                                              &pipe_config->dp_m_n,
10482                                              &pipe_config->dp_m2_n2);
10483 }
10484
10485 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10486                                    struct intel_crtc_state *pipe_config)
10487 {
10488         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10489                                      &pipe_config->fdi_m_n, NULL);
10490 }
10491
10492 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10493                                   u32 pos, u32 size)
10494 {
10495         drm_rect_init(&crtc_state->pch_pfit.dst,
10496                       pos >> 16, pos & 0xffff,
10497                       size >> 16, size & 0xffff);
10498 }
10499
10500 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10501 {
10502         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10503         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10504         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10505         int id = -1;
10506         int i;
10507
10508         /* find scaler attached to this pipe */
10509         for (i = 0; i < crtc->num_scalers; i++) {
10510                 u32 ctl, pos, size;
10511
10512                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10513                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10514                         continue;
10515
10516                 id = i;
10517                 crtc_state->pch_pfit.enabled = true;
10518
10519                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10520                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10521
10522                 ilk_get_pfit_pos_size(crtc_state, pos, size);
10523
10524                 scaler_state->scalers[i].in_use = true;
10525                 break;
10526         }
10527
10528         scaler_state->scaler_id = id;
10529         if (id >= 0)
10530                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10531         else
10532                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10533 }
10534
10535 static void
10536 skl_get_initial_plane_config(struct intel_crtc *crtc,
10537                              struct intel_initial_plane_config *plane_config)
10538 {
10539         struct drm_device *dev = crtc->base.dev;
10540         struct drm_i915_private *dev_priv = to_i915(dev);
10541         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10542         enum plane_id plane_id = plane->id;
10543         enum pipe pipe;
10544         u32 val, base, offset, stride_mult, tiling, alpha;
10545         int fourcc, pixel_format;
10546         unsigned int aligned_height;
10547         struct drm_framebuffer *fb;
10548         struct intel_framebuffer *intel_fb;
10549
10550         if (!plane->get_hw_state(plane, &pipe))
10551                 return;
10552
10553         drm_WARN_ON(dev, pipe != crtc->pipe);
10554
10555         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10556         if (!intel_fb) {
10557                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10558                 return;
10559         }
10560
10561         fb = &intel_fb->base;
10562
10563         fb->dev = dev;
10564
10565         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10566
10567         if (INTEL_GEN(dev_priv) >= 11)
10568                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10569         else
10570                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10571
10572         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10573                 alpha = intel_de_read(dev_priv,
10574                                       PLANE_COLOR_CTL(pipe, plane_id));
10575                 alpha &= PLANE_COLOR_ALPHA_MASK;
10576         } else {
10577                 alpha = val & PLANE_CTL_ALPHA_MASK;
10578         }
10579
10580         fourcc = skl_format_to_fourcc(pixel_format,
10581                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10582         fb->format = drm_format_info(fourcc);
10583
10584         tiling = val & PLANE_CTL_TILED_MASK;
10585         switch (tiling) {
10586         case PLANE_CTL_TILED_LINEAR:
10587                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10588                 break;
10589         case PLANE_CTL_TILED_X:
10590                 plane_config->tiling = I915_TILING_X;
10591                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10592                 break;
10593         case PLANE_CTL_TILED_Y:
10594                 plane_config->tiling = I915_TILING_Y;
10595                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10596                         fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10597                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10598                                 I915_FORMAT_MOD_Y_TILED_CCS;
10599                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10600                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10601                 else
10602                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10603                 break;
10604         case PLANE_CTL_TILED_YF:
10605                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10606                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10607                 else
10608                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10609                 break;
10610         default:
10611                 MISSING_CASE(tiling);
10612                 goto error;
10613         }
10614
10615         /*
10616          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10617          * while i915 HW rotation is clockwise, thats why this swapping.
10618          */
10619         switch (val & PLANE_CTL_ROTATE_MASK) {
10620         case PLANE_CTL_ROTATE_0:
10621                 plane_config->rotation = DRM_MODE_ROTATE_0;
10622                 break;
10623         case PLANE_CTL_ROTATE_90:
10624                 plane_config->rotation = DRM_MODE_ROTATE_270;
10625                 break;
10626         case PLANE_CTL_ROTATE_180:
10627                 plane_config->rotation = DRM_MODE_ROTATE_180;
10628                 break;
10629         case PLANE_CTL_ROTATE_270:
10630                 plane_config->rotation = DRM_MODE_ROTATE_90;
10631                 break;
10632         }
10633
10634         if (INTEL_GEN(dev_priv) >= 10 &&
10635             val & PLANE_CTL_FLIP_HORIZONTAL)
10636                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10637
10638         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10639         plane_config->base = base;
10640
10641         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10642
10643         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10644         fb->height = ((val >> 16) & 0xffff) + 1;
10645         fb->width = ((val >> 0) & 0xffff) + 1;
10646
10647         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10648         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10649         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10650
10651         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10652
10653         plane_config->size = fb->pitches[0] * aligned_height;
10654
10655         drm_dbg_kms(&dev_priv->drm,
10656                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10657                     crtc->base.name, plane->base.name, fb->width, fb->height,
10658                     fb->format->cpp[0] * 8, base, fb->pitches[0],
10659                     plane_config->size);
10660
10661         plane_config->fb = intel_fb;
10662         return;
10663
10664 error:
10665         kfree(intel_fb);
10666 }
10667
10668 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10669 {
10670         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10671         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10672         u32 ctl, pos, size;
10673
10674         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10675         if ((ctl & PF_ENABLE) == 0)
10676                 return;
10677
10678         crtc_state->pch_pfit.enabled = true;
10679
10680         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10681         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10682
10683         ilk_get_pfit_pos_size(crtc_state, pos, size);
10684
10685         /*
10686          * We currently do not free assignements of panel fitters on
10687          * ivb/hsw (since we don't use the higher upscaling modes which
10688          * differentiates them) so just WARN about this case for now.
10689          */
10690         drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10691                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10692 }
10693
10694 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10695                                 struct intel_crtc_state *pipe_config)
10696 {
10697         struct drm_device *dev = crtc->base.dev;
10698         struct drm_i915_private *dev_priv = to_i915(dev);
10699         enum intel_display_power_domain power_domain;
10700         intel_wakeref_t wakeref;
10701         u32 tmp;
10702         bool ret;
10703
10704         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10705         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10706         if (!wakeref)
10707                 return false;
10708
10709         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10710         pipe_config->shared_dpll = NULL;
10711
10712         ret = false;
10713         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10714         if (!(tmp & PIPECONF_ENABLE))
10715                 goto out;
10716
10717         switch (tmp & PIPECONF_BPC_MASK) {
10718         case PIPECONF_6BPC:
10719                 pipe_config->pipe_bpp = 18;
10720                 break;
10721         case PIPECONF_8BPC:
10722                 pipe_config->pipe_bpp = 24;
10723                 break;
10724         case PIPECONF_10BPC:
10725                 pipe_config->pipe_bpp = 30;
10726                 break;
10727         case PIPECONF_12BPC:
10728                 pipe_config->pipe_bpp = 36;
10729                 break;
10730         default:
10731                 break;
10732         }
10733
10734         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10735                 pipe_config->limited_color_range = true;
10736
10737         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10738         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10739         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10740                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10741                 break;
10742         default:
10743                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10744                 break;
10745         }
10746
10747         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10748                 PIPECONF_GAMMA_MODE_SHIFT;
10749
10750         pipe_config->csc_mode = intel_de_read(dev_priv,
10751                                               PIPE_CSC_MODE(crtc->pipe));
10752
10753         i9xx_get_pipe_color_config(pipe_config);
10754         intel_color_get_config(pipe_config);
10755
10756         if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10757                 struct intel_shared_dpll *pll;
10758                 enum intel_dpll_id pll_id;
10759
10760                 pipe_config->has_pch_encoder = true;
10761
10762                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10763                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10764                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10765
10766                 ilk_get_fdi_m_n_config(crtc, pipe_config);
10767
10768                 if (HAS_PCH_IBX(dev_priv)) {
10769                         /*
10770                          * The pipe->pch transcoder and pch transcoder->pll
10771                          * mapping is fixed.
10772                          */
10773                         pll_id = (enum intel_dpll_id) crtc->pipe;
10774                 } else {
10775                         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10776                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10777                                 pll_id = DPLL_ID_PCH_PLL_B;
10778                         else
10779                                 pll_id= DPLL_ID_PCH_PLL_A;
10780                 }
10781
10782                 pipe_config->shared_dpll =
10783                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10784                 pll = pipe_config->shared_dpll;
10785
10786                 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10787                                                  &pipe_config->dpll_hw_state));
10788
10789                 tmp = pipe_config->dpll_hw_state.dpll;
10790                 pipe_config->pixel_multiplier =
10791                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10792                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10793
10794                 ilk_pch_clock_get(crtc, pipe_config);
10795         } else {
10796                 pipe_config->pixel_multiplier = 1;
10797         }
10798
10799         intel_get_pipe_timings(crtc, pipe_config);
10800         intel_get_pipe_src_size(crtc, pipe_config);
10801
10802         ilk_get_pfit_config(pipe_config);
10803
10804         ret = true;
10805
10806 out:
10807         intel_display_power_put(dev_priv, power_domain, wakeref);
10808
10809         return ret;
10810 }
10811
10812 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10813                                   struct intel_crtc_state *crtc_state)
10814 {
10815         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10816         struct intel_atomic_state *state =
10817                 to_intel_atomic_state(crtc_state->uapi.state);
10818
10819         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10820             INTEL_GEN(dev_priv) >= 11) {
10821                 struct intel_encoder *encoder =
10822                         intel_get_crtc_new_encoder(state, crtc_state);
10823
10824                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10825                         drm_dbg_kms(&dev_priv->drm,
10826                                     "failed to find PLL for pipe %c\n",
10827                                     pipe_name(crtc->pipe));
10828                         return -EINVAL;
10829                 }
10830         }
10831
10832         return 0;
10833 }
10834
10835 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10836                             struct intel_crtc_state *pipe_config)
10837 {
10838         enum intel_dpll_id id;
10839         u32 temp;
10840
10841         temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10842         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10843
10844         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10845                 return;
10846
10847         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10848 }
10849
10850 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10851                             struct intel_crtc_state *pipe_config)
10852 {
10853         enum phy phy = intel_port_to_phy(dev_priv, port);
10854         enum icl_port_dpll_id port_dpll_id;
10855         enum intel_dpll_id id;
10856         u32 temp;
10857
10858         if (intel_phy_is_combo(dev_priv, phy)) {
10859                 u32 mask, shift;
10860
10861                 if (IS_ROCKETLAKE(dev_priv)) {
10862                         mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10863                         shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10864                 } else {
10865                         mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10866                         shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10867                 }
10868
10869                 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10870                 id = temp >> shift;
10871                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10872         } else if (intel_phy_is_tc(dev_priv, phy)) {
10873                 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10874
10875                 if (clk_sel == DDI_CLK_SEL_MG) {
10876                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10877                                                                     port));
10878                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10879                 } else {
10880                         drm_WARN_ON(&dev_priv->drm,
10881                                     clk_sel < DDI_CLK_SEL_TBT_162);
10882                         id = DPLL_ID_ICL_TBTPLL;
10883                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10884                 }
10885         } else {
10886                 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10887                 return;
10888         }
10889
10890         pipe_config->icl_port_dplls[port_dpll_id].pll =
10891                 intel_get_shared_dpll_by_id(dev_priv, id);
10892
10893         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10894 }
10895
10896 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10897                                 enum port port,
10898                                 struct intel_crtc_state *pipe_config)
10899 {
10900         enum intel_dpll_id id;
10901
10902         switch (port) {
10903         case PORT_A:
10904                 id = DPLL_ID_SKL_DPLL0;
10905                 break;
10906         case PORT_B:
10907                 id = DPLL_ID_SKL_DPLL1;
10908                 break;
10909         case PORT_C:
10910                 id = DPLL_ID_SKL_DPLL2;
10911                 break;
10912         default:
10913                 drm_err(&dev_priv->drm, "Incorrect port type\n");
10914                 return;
10915         }
10916
10917         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10918 }
10919
10920 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10921                             struct intel_crtc_state *pipe_config)
10922 {
10923         enum intel_dpll_id id;
10924         u32 temp;
10925
10926         temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10927         id = temp >> (port * 3 + 1);
10928
10929         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10930                 return;
10931
10932         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10933 }
10934
10935 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10936                             struct intel_crtc_state *pipe_config)
10937 {
10938         enum intel_dpll_id id;
10939         u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10940
10941         switch (ddi_pll_sel) {
10942         case PORT_CLK_SEL_WRPLL1:
10943                 id = DPLL_ID_WRPLL1;
10944                 break;
10945         case PORT_CLK_SEL_WRPLL2:
10946                 id = DPLL_ID_WRPLL2;
10947                 break;
10948         case PORT_CLK_SEL_SPLL:
10949                 id = DPLL_ID_SPLL;
10950                 break;
10951         case PORT_CLK_SEL_LCPLL_810:
10952                 id = DPLL_ID_LCPLL_810;
10953                 break;
10954         case PORT_CLK_SEL_LCPLL_1350:
10955                 id = DPLL_ID_LCPLL_1350;
10956                 break;
10957         case PORT_CLK_SEL_LCPLL_2700:
10958                 id = DPLL_ID_LCPLL_2700;
10959                 break;
10960         default:
10961                 MISSING_CASE(ddi_pll_sel);
10962                 fallthrough;
10963         case PORT_CLK_SEL_NONE:
10964                 return;
10965         }
10966
10967         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10968 }
10969
10970 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10971                                      struct intel_crtc_state *pipe_config,
10972                                      u64 *power_domain_mask,
10973                                      intel_wakeref_t *wakerefs)
10974 {
10975         struct drm_device *dev = crtc->base.dev;
10976         struct drm_i915_private *dev_priv = to_i915(dev);
10977         enum intel_display_power_domain power_domain;
10978         unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
10979         unsigned long enabled_panel_transcoders = 0;
10980         enum transcoder panel_transcoder;
10981         intel_wakeref_t wf;
10982         u32 tmp;
10983
10984         if (INTEL_GEN(dev_priv) >= 11)
10985                 panel_transcoder_mask |=
10986                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10987
10988         /*
10989          * The pipe->transcoder mapping is fixed with the exception of the eDP
10990          * and DSI transcoders handled below.
10991          */
10992         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10993
10994         /*
10995          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10996          * consistency and less surprising code; it's in always on power).
10997          */
10998         for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
10999                                        panel_transcoder_mask) {
11000                 bool force_thru = false;
11001                 enum pipe trans_pipe;
11002
11003                 tmp = intel_de_read(dev_priv,
11004                                     TRANS_DDI_FUNC_CTL(panel_transcoder));
11005                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11006                         continue;
11007
11008                 /*
11009                  * Log all enabled ones, only use the first one.
11010                  *
11011                  * FIXME: This won't work for two separate DSI displays.
11012                  */
11013                 enabled_panel_transcoders |= BIT(panel_transcoder);
11014                 if (enabled_panel_transcoders != BIT(panel_transcoder))
11015                         continue;
11016
11017                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11018                 default:
11019                         drm_WARN(dev, 1,
11020                                  "unknown pipe linked to transcoder %s\n",
11021                                  transcoder_name(panel_transcoder));
11022                         fallthrough;
11023                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11024                         force_thru = true;
11025                         fallthrough;
11026                 case TRANS_DDI_EDP_INPUT_A_ON:
11027                         trans_pipe = PIPE_A;
11028                         break;
11029                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11030                         trans_pipe = PIPE_B;
11031                         break;
11032                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11033                         trans_pipe = PIPE_C;
11034                         break;
11035                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11036                         trans_pipe = PIPE_D;
11037                         break;
11038                 }
11039
11040                 if (trans_pipe == crtc->pipe) {
11041                         pipe_config->cpu_transcoder = panel_transcoder;
11042                         pipe_config->pch_pfit.force_thru = force_thru;
11043                 }
11044         }
11045
11046         /*
11047          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11048          */
11049         drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11050                     enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11051
11052         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11053         drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11054
11055         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11056         if (!wf)
11057                 return false;
11058
11059         wakerefs[power_domain] = wf;
11060         *power_domain_mask |= BIT_ULL(power_domain);
11061
11062         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11063
11064         return tmp & PIPECONF_ENABLE;
11065 }
11066
11067 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11068                                          struct intel_crtc_state *pipe_config,
11069                                          u64 *power_domain_mask,
11070                                          intel_wakeref_t *wakerefs)
11071 {
11072         struct drm_device *dev = crtc->base.dev;
11073         struct drm_i915_private *dev_priv = to_i915(dev);
11074         enum intel_display_power_domain power_domain;
11075         enum transcoder cpu_transcoder;
11076         intel_wakeref_t wf;
11077         enum port port;
11078         u32 tmp;
11079
11080         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11081                 if (port == PORT_A)
11082                         cpu_transcoder = TRANSCODER_DSI_A;
11083                 else
11084                         cpu_transcoder = TRANSCODER_DSI_C;
11085
11086                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11087                 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11088
11089                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11090                 if (!wf)
11091                         continue;
11092
11093                 wakerefs[power_domain] = wf;
11094                 *power_domain_mask |= BIT_ULL(power_domain);
11095
11096                 /*
11097                  * The PLL needs to be enabled with a valid divider
11098                  * configuration, otherwise accessing DSI registers will hang
11099                  * the machine. See BSpec North Display Engine
11100                  * registers/MIPI[BXT]. We can break out here early, since we
11101                  * need the same DSI PLL to be enabled for both DSI ports.
11102                  */
11103                 if (!bxt_dsi_pll_is_enabled(dev_priv))
11104                         break;
11105
11106                 /* XXX: this works for video mode only */
11107                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11108                 if (!(tmp & DPI_ENABLE))
11109                         continue;
11110
11111                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11112                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11113                         continue;
11114
11115                 pipe_config->cpu_transcoder = cpu_transcoder;
11116                 break;
11117         }
11118
11119         return transcoder_is_dsi(pipe_config->cpu_transcoder);
11120 }
11121
11122 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11123                                    struct intel_crtc_state *pipe_config)
11124 {
11125         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11126         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11127         struct intel_shared_dpll *pll;
11128         enum port port;
11129         u32 tmp;
11130
11131         if (transcoder_is_dsi(cpu_transcoder)) {
11132                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11133                                                 PORT_A : PORT_B;
11134         } else {
11135                 tmp = intel_de_read(dev_priv,
11136                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
11137                 if (INTEL_GEN(dev_priv) >= 12)
11138                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11139                 else
11140                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11141         }
11142
11143         if (INTEL_GEN(dev_priv) >= 11)
11144                 icl_get_ddi_pll(dev_priv, port, pipe_config);
11145         else if (IS_CANNONLAKE(dev_priv))
11146                 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11147         else if (IS_GEN9_BC(dev_priv))
11148                 skl_get_ddi_pll(dev_priv, port, pipe_config);
11149         else if (IS_GEN9_LP(dev_priv))
11150                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11151         else
11152                 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11153
11154         pll = pipe_config->shared_dpll;
11155         if (pll) {
11156                 drm_WARN_ON(&dev_priv->drm,
11157                             !pll->info->funcs->get_hw_state(dev_priv, pll,
11158                                                 &pipe_config->dpll_hw_state));
11159         }
11160
11161         /*
11162          * Haswell has only FDI/PCH transcoder A. It is which is connected to
11163          * DDI E. So just check whether this pipe is wired to DDI E and whether
11164          * the PCH transcoder is on.
11165          */
11166         if (INTEL_GEN(dev_priv) < 9 &&
11167             (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11168                 pipe_config->has_pch_encoder = true;
11169
11170                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11171                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11172                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
11173
11174                 ilk_get_fdi_m_n_config(crtc, pipe_config);
11175         }
11176 }
11177
11178 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11179                                 struct intel_crtc_state *pipe_config)
11180 {
11181         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11182         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11183         enum intel_display_power_domain power_domain;
11184         u64 power_domain_mask;
11185         bool active;
11186         u32 tmp;
11187
11188         pipe_config->master_transcoder = INVALID_TRANSCODER;
11189
11190         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11191         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11192         if (!wf)
11193                 return false;
11194
11195         wakerefs[power_domain] = wf;
11196         power_domain_mask = BIT_ULL(power_domain);
11197
11198         pipe_config->shared_dpll = NULL;
11199
11200         active = hsw_get_transcoder_state(crtc, pipe_config,
11201                                           &power_domain_mask, wakerefs);
11202
11203         if (IS_GEN9_LP(dev_priv) &&
11204             bxt_get_dsi_transcoder_state(crtc, pipe_config,
11205                                          &power_domain_mask, wakerefs)) {
11206                 drm_WARN_ON(&dev_priv->drm, active);
11207                 active = true;
11208         }
11209
11210         if (!active)
11211                 goto out;
11212
11213         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11214             INTEL_GEN(dev_priv) >= 11) {
11215                 hsw_get_ddi_port_state(crtc, pipe_config);
11216                 intel_get_pipe_timings(crtc, pipe_config);
11217         }
11218
11219         intel_get_pipe_src_size(crtc, pipe_config);
11220
11221         if (IS_HASWELL(dev_priv)) {
11222                 u32 tmp = intel_de_read(dev_priv,
11223                                         PIPECONF(pipe_config->cpu_transcoder));
11224
11225                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11226                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11227                 else
11228                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11229         } else {
11230                 pipe_config->output_format =
11231                         bdw_get_pipemisc_output_format(crtc);
11232
11233                 /*
11234                  * Currently there is no interface defined to
11235                  * check user preference between RGB/YCBCR444
11236                  * or YCBCR420. So the only possible case for
11237                  * YCBCR444 usage is driving YCBCR420 output
11238                  * with LSPCON, when pipe is configured for
11239                  * YCBCR444 output and LSPCON takes care of
11240                  * downsampling it.
11241                  */
11242                 pipe_config->lspcon_downsampling =
11243                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11244         }
11245
11246         pipe_config->gamma_mode = intel_de_read(dev_priv,
11247                                                 GAMMA_MODE(crtc->pipe));
11248
11249         pipe_config->csc_mode = intel_de_read(dev_priv,
11250                                               PIPE_CSC_MODE(crtc->pipe));
11251
11252         if (INTEL_GEN(dev_priv) >= 9) {
11253                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11254
11255                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11256                         pipe_config->gamma_enable = true;
11257
11258                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11259                         pipe_config->csc_enable = true;
11260         } else {
11261                 i9xx_get_pipe_color_config(pipe_config);
11262         }
11263
11264         intel_color_get_config(pipe_config);
11265
11266         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11267         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11268         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11269                 pipe_config->ips_linetime =
11270                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11271
11272         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11273         drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11274
11275         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11276         if (wf) {
11277                 wakerefs[power_domain] = wf;
11278                 power_domain_mask |= BIT_ULL(power_domain);
11279
11280                 if (INTEL_GEN(dev_priv) >= 9)
11281                         skl_get_pfit_config(pipe_config);
11282                 else
11283                         ilk_get_pfit_config(pipe_config);
11284         }
11285
11286         if (hsw_crtc_supports_ips(crtc)) {
11287                 if (IS_HASWELL(dev_priv))
11288                         pipe_config->ips_enabled = intel_de_read(dev_priv,
11289                                                                  IPS_CTL) & IPS_ENABLE;
11290                 else {
11291                         /*
11292                          * We cannot readout IPS state on broadwell, set to
11293                          * true so we can set it to a defined state on first
11294                          * commit.
11295                          */
11296                         pipe_config->ips_enabled = true;
11297                 }
11298         }
11299
11300         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11301             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11302                 pipe_config->pixel_multiplier =
11303                         intel_de_read(dev_priv,
11304                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11305         } else {
11306                 pipe_config->pixel_multiplier = 1;
11307         }
11308
11309 out:
11310         for_each_power_domain(power_domain, power_domain_mask)
11311                 intel_display_power_put(dev_priv,
11312                                         power_domain, wakerefs[power_domain]);
11313
11314         return active;
11315 }
11316
11317 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11318 {
11319         struct drm_i915_private *dev_priv =
11320                 to_i915(plane_state->uapi.plane->dev);
11321         const struct drm_framebuffer *fb = plane_state->hw.fb;
11322         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11323         u32 base;
11324
11325         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11326                 base = sg_dma_address(obj->mm.pages->sgl);
11327         else
11328                 base = intel_plane_ggtt_offset(plane_state);
11329
11330         return base + plane_state->color_plane[0].offset;
11331 }
11332
11333 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11334 {
11335         int x = plane_state->uapi.dst.x1;
11336         int y = plane_state->uapi.dst.y1;
11337         u32 pos = 0;
11338
11339         if (x < 0) {
11340                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11341                 x = -x;
11342         }
11343         pos |= x << CURSOR_X_SHIFT;
11344
11345         if (y < 0) {
11346                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11347                 y = -y;
11348         }
11349         pos |= y << CURSOR_Y_SHIFT;
11350
11351         return pos;
11352 }
11353
11354 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11355 {
11356         const struct drm_mode_config *config =
11357                 &plane_state->uapi.plane->dev->mode_config;
11358         int width = drm_rect_width(&plane_state->uapi.dst);
11359         int height = drm_rect_height(&plane_state->uapi.dst);
11360
11361         return width > 0 && width <= config->cursor_width &&
11362                 height > 0 && height <= config->cursor_height;
11363 }
11364
11365 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11366 {
11367         struct drm_i915_private *dev_priv =
11368                 to_i915(plane_state->uapi.plane->dev);
11369         unsigned int rotation = plane_state->hw.rotation;
11370         int src_x, src_y;
11371         u32 offset;
11372         int ret;
11373
11374         ret = intel_plane_compute_gtt(plane_state);
11375         if (ret)
11376                 return ret;
11377
11378         if (!plane_state->uapi.visible)
11379                 return 0;
11380
11381         src_x = plane_state->uapi.src.x1 >> 16;
11382         src_y = plane_state->uapi.src.y1 >> 16;
11383
11384         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11385         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11386                                                     plane_state, 0);
11387
11388         if (src_x != 0 || src_y != 0) {
11389                 drm_dbg_kms(&dev_priv->drm,
11390                             "Arbitrary cursor panning not supported\n");
11391                 return -EINVAL;
11392         }
11393
11394         /*
11395          * Put the final coordinates back so that the src
11396          * coordinate checks will see the right values.
11397          */
11398         drm_rect_translate_to(&plane_state->uapi.src,
11399                               src_x << 16, src_y << 16);
11400
11401         /* ILK+ do this automagically in hardware */
11402         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11403                 const struct drm_framebuffer *fb = plane_state->hw.fb;
11404                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11405                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11406
11407                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11408         }
11409
11410         plane_state->color_plane[0].offset = offset;
11411         plane_state->color_plane[0].x = src_x;
11412         plane_state->color_plane[0].y = src_y;
11413
11414         return 0;
11415 }
11416
11417 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11418                               struct intel_plane_state *plane_state)
11419 {
11420         const struct drm_framebuffer *fb = plane_state->hw.fb;
11421         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11422         int ret;
11423
11424         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11425                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11426                 return -EINVAL;
11427         }
11428
11429         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11430                                                   &crtc_state->uapi,
11431                                                   DRM_PLANE_HELPER_NO_SCALING,
11432                                                   DRM_PLANE_HELPER_NO_SCALING,
11433                                                   true, true);
11434         if (ret)
11435                 return ret;
11436
11437         /* Use the unclipped src/dst rectangles, which we program to hw */
11438         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11439         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11440
11441         ret = intel_cursor_check_surface(plane_state);
11442         if (ret)
11443                 return ret;
11444
11445         if (!plane_state->uapi.visible)
11446                 return 0;
11447
11448         ret = intel_plane_check_src_coordinates(plane_state);
11449         if (ret)
11450                 return ret;
11451
11452         return 0;
11453 }
11454
11455 static unsigned int
11456 i845_cursor_max_stride(struct intel_plane *plane,
11457                        u32 pixel_format, u64 modifier,
11458                        unsigned int rotation)
11459 {
11460         return 2048;
11461 }
11462
11463 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11464 {
11465         u32 cntl = 0;
11466
11467         if (crtc_state->gamma_enable)
11468                 cntl |= CURSOR_GAMMA_ENABLE;
11469
11470         return cntl;
11471 }
11472
11473 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11474                            const struct intel_plane_state *plane_state)
11475 {
11476         return CURSOR_ENABLE |
11477                 CURSOR_FORMAT_ARGB |
11478                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11479 }
11480
11481 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11482 {
11483         int width = drm_rect_width(&plane_state->uapi.dst);
11484
11485         /*
11486          * 845g/865g are only limited by the width of their cursors,
11487          * the height is arbitrary up to the precision of the register.
11488          */
11489         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11490 }
11491
11492 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11493                              struct intel_plane_state *plane_state)
11494 {
11495         const struct drm_framebuffer *fb = plane_state->hw.fb;
11496         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11497         int ret;
11498
11499         ret = intel_check_cursor(crtc_state, plane_state);
11500         if (ret)
11501                 return ret;
11502
11503         /* if we want to turn off the cursor ignore width and height */
11504         if (!fb)
11505                 return 0;
11506
11507         /* Check for which cursor types we support */
11508         if (!i845_cursor_size_ok(plane_state)) {
11509                 drm_dbg_kms(&i915->drm,
11510                             "Cursor dimension %dx%d not supported\n",
11511                             drm_rect_width(&plane_state->uapi.dst),
11512                             drm_rect_height(&plane_state->uapi.dst));
11513                 return -EINVAL;
11514         }
11515
11516         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11517                     plane_state->color_plane[0].stride != fb->pitches[0]);
11518
11519         switch (fb->pitches[0]) {
11520         case 256:
11521         case 512:
11522         case 1024:
11523         case 2048:
11524                 break;
11525         default:
11526                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11527                              fb->pitches[0]);
11528                 return -EINVAL;
11529         }
11530
11531         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11532
11533         return 0;
11534 }
11535
11536 static void i845_update_cursor(struct intel_plane *plane,
11537                                const struct intel_crtc_state *crtc_state,
11538                                const struct intel_plane_state *plane_state)
11539 {
11540         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11541         u32 cntl = 0, base = 0, pos = 0, size = 0;
11542         unsigned long irqflags;
11543
11544         if (plane_state && plane_state->uapi.visible) {
11545                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11546                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11547
11548                 cntl = plane_state->ctl |
11549                         i845_cursor_ctl_crtc(crtc_state);
11550
11551                 size = (height << 12) | width;
11552
11553                 base = intel_cursor_base(plane_state);
11554                 pos = intel_cursor_position(plane_state);
11555         }
11556
11557         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11558
11559         /* On these chipsets we can only modify the base/size/stride
11560          * whilst the cursor is disabled.
11561          */
11562         if (plane->cursor.base != base ||
11563             plane->cursor.size != size ||
11564             plane->cursor.cntl != cntl) {
11565                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11566                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11567                 intel_de_write_fw(dev_priv, CURSIZE, size);
11568                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11569                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11570
11571                 plane->cursor.base = base;
11572                 plane->cursor.size = size;
11573                 plane->cursor.cntl = cntl;
11574         } else {
11575                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11576         }
11577
11578         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11579 }
11580
11581 static void i845_disable_cursor(struct intel_plane *plane,
11582                                 const struct intel_crtc_state *crtc_state)
11583 {
11584         i845_update_cursor(plane, crtc_state, NULL);
11585 }
11586
11587 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11588                                      enum pipe *pipe)
11589 {
11590         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11591         enum intel_display_power_domain power_domain;
11592         intel_wakeref_t wakeref;
11593         bool ret;
11594
11595         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11596         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11597         if (!wakeref)
11598                 return false;
11599
11600         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11601
11602         *pipe = PIPE_A;
11603
11604         intel_display_power_put(dev_priv, power_domain, wakeref);
11605
11606         return ret;
11607 }
11608
11609 static unsigned int
11610 i9xx_cursor_max_stride(struct intel_plane *plane,
11611                        u32 pixel_format, u64 modifier,
11612                        unsigned int rotation)
11613 {
11614         return plane->base.dev->mode_config.cursor_width * 4;
11615 }
11616
11617 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11618 {
11619         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11621         u32 cntl = 0;
11622
11623         if (INTEL_GEN(dev_priv) >= 11)
11624                 return cntl;
11625
11626         if (crtc_state->gamma_enable)
11627                 cntl = MCURSOR_GAMMA_ENABLE;
11628
11629         if (crtc_state->csc_enable)
11630                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11631
11632         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11633                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11634
11635         return cntl;
11636 }
11637
11638 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11639                            const struct intel_plane_state *plane_state)
11640 {
11641         struct drm_i915_private *dev_priv =
11642                 to_i915(plane_state->uapi.plane->dev);
11643         u32 cntl = 0;
11644
11645         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11646                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11647
11648         switch (drm_rect_width(&plane_state->uapi.dst)) {
11649         case 64:
11650                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11651                 break;
11652         case 128:
11653                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11654                 break;
11655         case 256:
11656                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11657                 break;
11658         default:
11659                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11660                 return 0;
11661         }
11662
11663         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11664                 cntl |= MCURSOR_ROTATE_180;
11665
11666         return cntl;
11667 }
11668
11669 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11670 {
11671         struct drm_i915_private *dev_priv =
11672                 to_i915(plane_state->uapi.plane->dev);
11673         int width = drm_rect_width(&plane_state->uapi.dst);
11674         int height = drm_rect_height(&plane_state->uapi.dst);
11675
11676         if (!intel_cursor_size_ok(plane_state))
11677                 return false;
11678
11679         /* Cursor width is limited to a few power-of-two sizes */
11680         switch (width) {
11681         case 256:
11682         case 128:
11683         case 64:
11684                 break;
11685         default:
11686                 return false;
11687         }
11688
11689         /*
11690          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11691          * height from 8 lines up to the cursor width, when the
11692          * cursor is not rotated. Everything else requires square
11693          * cursors.
11694          */
11695         if (HAS_CUR_FBC(dev_priv) &&
11696             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11697                 if (height < 8 || height > width)
11698                         return false;
11699         } else {
11700                 if (height != width)
11701                         return false;
11702         }
11703
11704         return true;
11705 }
11706
11707 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11708                              struct intel_plane_state *plane_state)
11709 {
11710         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11711         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11712         const struct drm_framebuffer *fb = plane_state->hw.fb;
11713         enum pipe pipe = plane->pipe;
11714         int ret;
11715
11716         ret = intel_check_cursor(crtc_state, plane_state);
11717         if (ret)
11718                 return ret;
11719
11720         /* if we want to turn off the cursor ignore width and height */
11721         if (!fb)
11722                 return 0;
11723
11724         /* Check for which cursor types we support */
11725         if (!i9xx_cursor_size_ok(plane_state)) {
11726                 drm_dbg(&dev_priv->drm,
11727                         "Cursor dimension %dx%d not supported\n",
11728                         drm_rect_width(&plane_state->uapi.dst),
11729                         drm_rect_height(&plane_state->uapi.dst));
11730                 return -EINVAL;
11731         }
11732
11733         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11734                     plane_state->color_plane[0].stride != fb->pitches[0]);
11735
11736         if (fb->pitches[0] !=
11737             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11738                 drm_dbg_kms(&dev_priv->drm,
11739                             "Invalid cursor stride (%u) (cursor width %d)\n",
11740                             fb->pitches[0],
11741                             drm_rect_width(&plane_state->uapi.dst));
11742                 return -EINVAL;
11743         }
11744
11745         /*
11746          * There's something wrong with the cursor on CHV pipe C.
11747          * If it straddles the left edge of the screen then
11748          * moving it away from the edge or disabling it often
11749          * results in a pipe underrun, and often that can lead to
11750          * dead pipe (constant underrun reported, and it scans
11751          * out just a solid color). To recover from that, the
11752          * display power well must be turned off and on again.
11753          * Refuse the put the cursor into that compromised position.
11754          */
11755         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11756             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11757                 drm_dbg_kms(&dev_priv->drm,
11758                             "CHV cursor C not allowed to straddle the left screen edge\n");
11759                 return -EINVAL;
11760         }
11761
11762         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11763
11764         return 0;
11765 }
11766
11767 static void i9xx_update_cursor(struct intel_plane *plane,
11768                                const struct intel_crtc_state *crtc_state,
11769                                const struct intel_plane_state *plane_state)
11770 {
11771         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11772         enum pipe pipe = plane->pipe;
11773         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11774         unsigned long irqflags;
11775
11776         if (plane_state && plane_state->uapi.visible) {
11777                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11778                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11779
11780                 cntl = plane_state->ctl |
11781                         i9xx_cursor_ctl_crtc(crtc_state);
11782
11783                 if (width != height)
11784                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11785
11786                 base = intel_cursor_base(plane_state);
11787                 pos = intel_cursor_position(plane_state);
11788         }
11789
11790         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11791
11792         /*
11793          * On some platforms writing CURCNTR first will also
11794          * cause CURPOS to be armed by the CURBASE write.
11795          * Without the CURCNTR write the CURPOS write would
11796          * arm itself. Thus we always update CURCNTR before
11797          * CURPOS.
11798          *
11799          * On other platforms CURPOS always requires the
11800          * CURBASE write to arm the update. Additonally
11801          * a write to any of the cursor register will cancel
11802          * an already armed cursor update. Thus leaving out
11803          * the CURBASE write after CURPOS could lead to a
11804          * cursor that doesn't appear to move, or even change
11805          * shape. Thus we always write CURBASE.
11806          *
11807          * The other registers are armed by by the CURBASE write
11808          * except when the plane is getting enabled at which time
11809          * the CURCNTR write arms the update.
11810          */
11811
11812         if (INTEL_GEN(dev_priv) >= 9)
11813                 skl_write_cursor_wm(plane, crtc_state);
11814
11815         if (plane->cursor.base != base ||
11816             plane->cursor.size != fbc_ctl ||
11817             plane->cursor.cntl != cntl) {
11818                 if (HAS_CUR_FBC(dev_priv))
11819                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11820                                           fbc_ctl);
11821                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11822                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11823                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11824
11825                 plane->cursor.base = base;
11826                 plane->cursor.size = fbc_ctl;
11827                 plane->cursor.cntl = cntl;
11828         } else {
11829                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11830                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11831         }
11832
11833         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11834 }
11835
11836 static void i9xx_disable_cursor(struct intel_plane *plane,
11837                                 const struct intel_crtc_state *crtc_state)
11838 {
11839         i9xx_update_cursor(plane, crtc_state, NULL);
11840 }
11841
11842 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11843                                      enum pipe *pipe)
11844 {
11845         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11846         enum intel_display_power_domain power_domain;
11847         intel_wakeref_t wakeref;
11848         bool ret;
11849         u32 val;
11850
11851         /*
11852          * Not 100% correct for planes that can move between pipes,
11853          * but that's only the case for gen2-3 which don't have any
11854          * display power wells.
11855          */
11856         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11857         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11858         if (!wakeref)
11859                 return false;
11860
11861         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11862
11863         ret = val & MCURSOR_MODE;
11864
11865         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11866                 *pipe = plane->pipe;
11867         else
11868                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11869                         MCURSOR_PIPE_SELECT_SHIFT;
11870
11871         intel_display_power_put(dev_priv, power_domain, wakeref);
11872
11873         return ret;
11874 }
11875
11876 /* VESA 640x480x72Hz mode to set on the pipe */
11877 static const struct drm_display_mode load_detect_mode = {
11878         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11879                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11880 };
11881
11882 struct drm_framebuffer *
11883 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11884                          struct drm_mode_fb_cmd2 *mode_cmd)
11885 {
11886         struct intel_framebuffer *intel_fb;
11887         int ret;
11888
11889         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11890         if (!intel_fb)
11891                 return ERR_PTR(-ENOMEM);
11892
11893         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11894         if (ret)
11895                 goto err;
11896
11897         return &intel_fb->base;
11898
11899 err:
11900         kfree(intel_fb);
11901         return ERR_PTR(ret);
11902 }
11903
11904 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11905                                         struct drm_crtc *crtc)
11906 {
11907         struct drm_plane *plane;
11908         struct drm_plane_state *plane_state;
11909         int ret, i;
11910
11911         ret = drm_atomic_add_affected_planes(state, crtc);
11912         if (ret)
11913                 return ret;
11914
11915         for_each_new_plane_in_state(state, plane, plane_state, i) {
11916                 if (plane_state->crtc != crtc)
11917                         continue;
11918
11919                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11920                 if (ret)
11921                         return ret;
11922
11923                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11924         }
11925
11926         return 0;
11927 }
11928
11929 int intel_get_load_detect_pipe(struct drm_connector *connector,
11930                                struct intel_load_detect_pipe *old,
11931                                struct drm_modeset_acquire_ctx *ctx)
11932 {
11933         struct intel_crtc *intel_crtc;
11934         struct intel_encoder *intel_encoder =
11935                 intel_attached_encoder(to_intel_connector(connector));
11936         struct drm_crtc *possible_crtc;
11937         struct drm_encoder *encoder = &intel_encoder->base;
11938         struct drm_crtc *crtc = NULL;
11939         struct drm_device *dev = encoder->dev;
11940         struct drm_i915_private *dev_priv = to_i915(dev);
11941         struct drm_mode_config *config = &dev->mode_config;
11942         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11943         struct drm_connector_state *connector_state;
11944         struct intel_crtc_state *crtc_state;
11945         int ret, i = -1;
11946
11947         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11948                     connector->base.id, connector->name,
11949                     encoder->base.id, encoder->name);
11950
11951         old->restore_state = NULL;
11952
11953         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11954
11955         /*
11956          * Algorithm gets a little messy:
11957          *
11958          *   - if the connector already has an assigned crtc, use it (but make
11959          *     sure it's on first)
11960          *
11961          *   - try to find the first unused crtc that can drive this connector,
11962          *     and use that if we find one
11963          */
11964
11965         /* See if we already have a CRTC for this connector */
11966         if (connector->state->crtc) {
11967                 crtc = connector->state->crtc;
11968
11969                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11970                 if (ret)
11971                         goto fail;
11972
11973                 /* Make sure the crtc and connector are running */
11974                 goto found;
11975         }
11976
11977         /* Find an unused one (if possible) */
11978         for_each_crtc(dev, possible_crtc) {
11979                 i++;
11980                 if (!(encoder->possible_crtcs & (1 << i)))
11981                         continue;
11982
11983                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11984                 if (ret)
11985                         goto fail;
11986
11987                 if (possible_crtc->state->enable) {
11988                         drm_modeset_unlock(&possible_crtc->mutex);
11989                         continue;
11990                 }
11991
11992                 crtc = possible_crtc;
11993                 break;
11994         }
11995
11996         /*
11997          * If we didn't find an unused CRTC, don't use any.
11998          */
11999         if (!crtc) {
12000                 drm_dbg_kms(&dev_priv->drm,
12001                             "no pipe available for load-detect\n");
12002                 ret = -ENODEV;
12003                 goto fail;
12004         }
12005
12006 found:
12007         intel_crtc = to_intel_crtc(crtc);
12008
12009         state = drm_atomic_state_alloc(dev);
12010         restore_state = drm_atomic_state_alloc(dev);
12011         if (!state || !restore_state) {
12012                 ret = -ENOMEM;
12013                 goto fail;
12014         }
12015
12016         state->acquire_ctx = ctx;
12017         restore_state->acquire_ctx = ctx;
12018
12019         connector_state = drm_atomic_get_connector_state(state, connector);
12020         if (IS_ERR(connector_state)) {
12021                 ret = PTR_ERR(connector_state);
12022                 goto fail;
12023         }
12024
12025         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12026         if (ret)
12027                 goto fail;
12028
12029         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12030         if (IS_ERR(crtc_state)) {
12031                 ret = PTR_ERR(crtc_state);
12032                 goto fail;
12033         }
12034
12035         crtc_state->uapi.active = true;
12036
12037         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12038                                            &load_detect_mode);
12039         if (ret)
12040                 goto fail;
12041
12042         ret = intel_modeset_disable_planes(state, crtc);
12043         if (ret)
12044                 goto fail;
12045
12046         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12047         if (!ret)
12048                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12049         if (!ret)
12050                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12051         if (ret) {
12052                 drm_dbg_kms(&dev_priv->drm,
12053                             "Failed to create a copy of old state to restore: %i\n",
12054                             ret);
12055                 goto fail;
12056         }
12057
12058         ret = drm_atomic_commit(state);
12059         if (ret) {
12060                 drm_dbg_kms(&dev_priv->drm,
12061                             "failed to set mode on load-detect pipe\n");
12062                 goto fail;
12063         }
12064
12065         old->restore_state = restore_state;
12066         drm_atomic_state_put(state);
12067
12068         /* let the connector get through one full cycle before testing */
12069         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12070         return true;
12071
12072 fail:
12073         if (state) {
12074                 drm_atomic_state_put(state);
12075                 state = NULL;
12076         }
12077         if (restore_state) {
12078                 drm_atomic_state_put(restore_state);
12079                 restore_state = NULL;
12080         }
12081
12082         if (ret == -EDEADLK)
12083                 return ret;
12084
12085         return false;
12086 }
12087
12088 void intel_release_load_detect_pipe(struct drm_connector *connector,
12089                                     struct intel_load_detect_pipe *old,
12090                                     struct drm_modeset_acquire_ctx *ctx)
12091 {
12092         struct intel_encoder *intel_encoder =
12093                 intel_attached_encoder(to_intel_connector(connector));
12094         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12095         struct drm_encoder *encoder = &intel_encoder->base;
12096         struct drm_atomic_state *state = old->restore_state;
12097         int ret;
12098
12099         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12100                     connector->base.id, connector->name,
12101                     encoder->base.id, encoder->name);
12102
12103         if (!state)
12104                 return;
12105
12106         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12107         if (ret)
12108                 drm_dbg_kms(&i915->drm,
12109                             "Couldn't release load detect pipe: %i\n", ret);
12110         drm_atomic_state_put(state);
12111 }
12112
12113 static int i9xx_pll_refclk(struct drm_device *dev,
12114                            const struct intel_crtc_state *pipe_config)
12115 {
12116         struct drm_i915_private *dev_priv = to_i915(dev);
12117         u32 dpll = pipe_config->dpll_hw_state.dpll;
12118
12119         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12120                 return dev_priv->vbt.lvds_ssc_freq;
12121         else if (HAS_PCH_SPLIT(dev_priv))
12122                 return 120000;
12123         else if (!IS_GEN(dev_priv, 2))
12124                 return 96000;
12125         else
12126                 return 48000;
12127 }
12128
12129 /* Returns the clock of the currently programmed mode of the given pipe. */
12130 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12131                                 struct intel_crtc_state *pipe_config)
12132 {
12133         struct drm_device *dev = crtc->base.dev;
12134         struct drm_i915_private *dev_priv = to_i915(dev);
12135         enum pipe pipe = crtc->pipe;
12136         u32 dpll = pipe_config->dpll_hw_state.dpll;
12137         u32 fp;
12138         struct dpll clock;
12139         int port_clock;
12140         int refclk = i9xx_pll_refclk(dev, pipe_config);
12141
12142         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12143                 fp = pipe_config->dpll_hw_state.fp0;
12144         else
12145                 fp = pipe_config->dpll_hw_state.fp1;
12146
12147         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12148         if (IS_PINEVIEW(dev_priv)) {
12149                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12150                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12151         } else {
12152                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12153                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12154         }
12155
12156         if (!IS_GEN(dev_priv, 2)) {
12157                 if (IS_PINEVIEW(dev_priv))
12158                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12159                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12160                 else
12161                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12162                                DPLL_FPA01_P1_POST_DIV_SHIFT);
12163
12164                 switch (dpll & DPLL_MODE_MASK) {
12165                 case DPLLB_MODE_DAC_SERIAL:
12166                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12167                                 5 : 10;
12168                         break;
12169                 case DPLLB_MODE_LVDS:
12170                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12171                                 7 : 14;
12172                         break;
12173                 default:
12174                         drm_dbg_kms(&dev_priv->drm,
12175                                     "Unknown DPLL mode %08x in programmed "
12176                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
12177                         return;
12178                 }
12179
12180                 if (IS_PINEVIEW(dev_priv))
12181                         port_clock = pnv_calc_dpll_params(refclk, &clock);
12182                 else
12183                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
12184         } else {
12185                 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12186                                                                  LVDS);
12187                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12188
12189                 if (is_lvds) {
12190                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12191                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
12192
12193                         if (lvds & LVDS_CLKB_POWER_UP)
12194                                 clock.p2 = 7;
12195                         else
12196                                 clock.p2 = 14;
12197                 } else {
12198                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
12199                                 clock.p1 = 2;
12200                         else {
12201                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12202                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12203                         }
12204                         if (dpll & PLL_P2_DIVIDE_BY_4)
12205                                 clock.p2 = 4;
12206                         else
12207                                 clock.p2 = 2;
12208                 }
12209
12210                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12211         }
12212
12213         /*
12214          * This value includes pixel_multiplier. We will use
12215          * port_clock to compute adjusted_mode.crtc_clock in the
12216          * encoder's get_config() function.
12217          */
12218         pipe_config->port_clock = port_clock;
12219 }
12220
12221 int intel_dotclock_calculate(int link_freq,
12222                              const struct intel_link_m_n *m_n)
12223 {
12224         /*
12225          * The calculation for the data clock is:
12226          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12227          * But we want to avoid losing precison if possible, so:
12228          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12229          *
12230          * and the link clock is simpler:
12231          * link_clock = (m * link_clock) / n
12232          */
12233
12234         if (!m_n->link_n)
12235                 return 0;
12236
12237         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12238 }
12239
12240 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12241                               struct intel_crtc_state *pipe_config)
12242 {
12243         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12244
12245         /* read out port_clock from the DPLL */
12246         i9xx_crtc_clock_get(crtc, pipe_config);
12247
12248         /*
12249          * In case there is an active pipe without active ports,
12250          * we may need some idea for the dotclock anyway.
12251          * Calculate one based on the FDI configuration.
12252          */
12253         pipe_config->hw.adjusted_mode.crtc_clock =
12254                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12255                                          &pipe_config->fdi_m_n);
12256 }
12257
12258 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12259                                    struct intel_crtc *crtc)
12260 {
12261         memset(crtc_state, 0, sizeof(*crtc_state));
12262
12263         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12264
12265         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12266         crtc_state->master_transcoder = INVALID_TRANSCODER;
12267         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12268         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12269         crtc_state->scaler_state.scaler_id = -1;
12270         crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12271 }
12272
12273 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12274 {
12275         struct intel_crtc_state *crtc_state;
12276
12277         crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12278
12279         if (crtc_state)
12280                 intel_crtc_state_reset(crtc_state, crtc);
12281
12282         return crtc_state;
12283 }
12284
12285 /* Returns the currently programmed mode of the given encoder. */
12286 struct drm_display_mode *
12287 intel_encoder_current_mode(struct intel_encoder *encoder)
12288 {
12289         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12290         struct intel_crtc_state *crtc_state;
12291         struct drm_display_mode *mode;
12292         struct intel_crtc *crtc;
12293         enum pipe pipe;
12294
12295         if (!encoder->get_hw_state(encoder, &pipe))
12296                 return NULL;
12297
12298         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12299
12300         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12301         if (!mode)
12302                 return NULL;
12303
12304         crtc_state = intel_crtc_state_alloc(crtc);
12305         if (!crtc_state) {
12306                 kfree(mode);
12307                 return NULL;
12308         }
12309
12310         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12311                 kfree(crtc_state);
12312                 kfree(mode);
12313                 return NULL;
12314         }
12315
12316         encoder->get_config(encoder, crtc_state);
12317
12318         intel_mode_from_pipe_config(mode, crtc_state);
12319
12320         kfree(crtc_state);
12321
12322         return mode;
12323 }
12324
12325 static void intel_crtc_destroy(struct drm_crtc *crtc)
12326 {
12327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12328
12329         drm_crtc_cleanup(crtc);
12330         kfree(intel_crtc);
12331 }
12332
12333 /**
12334  * intel_wm_need_update - Check whether watermarks need updating
12335  * @cur: current plane state
12336  * @new: new plane state
12337  *
12338  * Check current plane state versus the new one to determine whether
12339  * watermarks need to be recalculated.
12340  *
12341  * Returns true or false.
12342  */
12343 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12344                                  struct intel_plane_state *new)
12345 {
12346         /* Update watermarks on tiling or size changes. */
12347         if (new->uapi.visible != cur->uapi.visible)
12348                 return true;
12349
12350         if (!cur->hw.fb || !new->hw.fb)
12351                 return false;
12352
12353         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12354             cur->hw.rotation != new->hw.rotation ||
12355             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12356             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12357             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12358             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12359                 return true;
12360
12361         return false;
12362 }
12363
12364 static bool needs_scaling(const struct intel_plane_state *state)
12365 {
12366         int src_w = drm_rect_width(&state->uapi.src) >> 16;
12367         int src_h = drm_rect_height(&state->uapi.src) >> 16;
12368         int dst_w = drm_rect_width(&state->uapi.dst);
12369         int dst_h = drm_rect_height(&state->uapi.dst);
12370
12371         return (src_w != dst_w || src_h != dst_h);
12372 }
12373
12374 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12375                                     struct intel_crtc_state *crtc_state,
12376                                     const struct intel_plane_state *old_plane_state,
12377                                     struct intel_plane_state *plane_state)
12378 {
12379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12380         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12381         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12382         bool mode_changed = needs_modeset(crtc_state);
12383         bool was_crtc_enabled = old_crtc_state->hw.active;
12384         bool is_crtc_enabled = crtc_state->hw.active;
12385         bool turn_off, turn_on, visible, was_visible;
12386         int ret;
12387
12388         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12389                 ret = skl_update_scaler_plane(crtc_state, plane_state);
12390                 if (ret)
12391                         return ret;
12392         }
12393
12394         was_visible = old_plane_state->uapi.visible;
12395         visible = plane_state->uapi.visible;
12396
12397         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12398                 was_visible = false;
12399
12400         /*
12401          * Visibility is calculated as if the crtc was on, but
12402          * after scaler setup everything depends on it being off
12403          * when the crtc isn't active.
12404          *
12405          * FIXME this is wrong for watermarks. Watermarks should also
12406          * be computed as if the pipe would be active. Perhaps move
12407          * per-plane wm computation to the .check_plane() hook, and
12408          * only combine the results from all planes in the current place?
12409          */
12410         if (!is_crtc_enabled) {
12411                 intel_plane_set_invisible(crtc_state, plane_state);
12412                 visible = false;
12413         }
12414
12415         if (!was_visible && !visible)
12416                 return 0;
12417
12418         turn_off = was_visible && (!visible || mode_changed);
12419         turn_on = visible && (!was_visible || mode_changed);
12420
12421         drm_dbg_atomic(&dev_priv->drm,
12422                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12423                        crtc->base.base.id, crtc->base.name,
12424                        plane->base.base.id, plane->base.name,
12425                        was_visible, visible,
12426                        turn_off, turn_on, mode_changed);
12427
12428         if (turn_on) {
12429                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12430                         crtc_state->update_wm_pre = true;
12431
12432                 /* must disable cxsr around plane enable/disable */
12433                 if (plane->id != PLANE_CURSOR)
12434                         crtc_state->disable_cxsr = true;
12435         } else if (turn_off) {
12436                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12437                         crtc_state->update_wm_post = true;
12438
12439                 /* must disable cxsr around plane enable/disable */
12440                 if (plane->id != PLANE_CURSOR)
12441                         crtc_state->disable_cxsr = true;
12442         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12443                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12444                         /* FIXME bollocks */
12445                         crtc_state->update_wm_pre = true;
12446                         crtc_state->update_wm_post = true;
12447                 }
12448         }
12449
12450         if (visible || was_visible)
12451                 crtc_state->fb_bits |= plane->frontbuffer_bit;
12452
12453         /*
12454          * ILK/SNB DVSACNTR/Sprite Enable
12455          * IVB SPR_CTL/Sprite Enable
12456          * "When in Self Refresh Big FIFO mode, a write to enable the
12457          *  plane will be internally buffered and delayed while Big FIFO
12458          *  mode is exiting."
12459          *
12460          * Which means that enabling the sprite can take an extra frame
12461          * when we start in big FIFO mode (LP1+). Thus we need to drop
12462          * down to LP0 and wait for vblank in order to make sure the
12463          * sprite gets enabled on the next vblank after the register write.
12464          * Doing otherwise would risk enabling the sprite one frame after
12465          * we've already signalled flip completion. We can resume LP1+
12466          * once the sprite has been enabled.
12467          *
12468          *
12469          * WaCxSRDisabledForSpriteScaling:ivb
12470          * IVB SPR_SCALE/Scaling Enable
12471          * "Low Power watermarks must be disabled for at least one
12472          *  frame before enabling sprite scaling, and kept disabled
12473          *  until sprite scaling is disabled."
12474          *
12475          * ILK/SNB DVSASCALE/Scaling Enable
12476          * "When in Self Refresh Big FIFO mode, scaling enable will be
12477          *  masked off while Big FIFO mode is exiting."
12478          *
12479          * Despite the w/a only being listed for IVB we assume that
12480          * the ILK/SNB note has similar ramifications, hence we apply
12481          * the w/a on all three platforms.
12482          *
12483          * With experimental results seems this is needed also for primary
12484          * plane, not only sprite plane.
12485          */
12486         if (plane->id != PLANE_CURSOR &&
12487             (IS_GEN_RANGE(dev_priv, 5, 6) ||
12488              IS_IVYBRIDGE(dev_priv)) &&
12489             (turn_on || (!needs_scaling(old_plane_state) &&
12490                          needs_scaling(plane_state))))
12491                 crtc_state->disable_lp_wm = true;
12492
12493         return 0;
12494 }
12495
12496 static bool encoders_cloneable(const struct intel_encoder *a,
12497                                const struct intel_encoder *b)
12498 {
12499         /* masks could be asymmetric, so check both ways */
12500         return a == b || (a->cloneable & (1 << b->type) &&
12501                           b->cloneable & (1 << a->type));
12502 }
12503
12504 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12505                                          struct intel_crtc *crtc,
12506                                          struct intel_encoder *encoder)
12507 {
12508         struct intel_encoder *source_encoder;
12509         struct drm_connector *connector;
12510         struct drm_connector_state *connector_state;
12511         int i;
12512
12513         for_each_new_connector_in_state(state, connector, connector_state, i) {
12514                 if (connector_state->crtc != &crtc->base)
12515                         continue;
12516
12517                 source_encoder =
12518                         to_intel_encoder(connector_state->best_encoder);
12519                 if (!encoders_cloneable(encoder, source_encoder))
12520                         return false;
12521         }
12522
12523         return true;
12524 }
12525
12526 static int icl_add_linked_planes(struct intel_atomic_state *state)
12527 {
12528         struct intel_plane *plane, *linked;
12529         struct intel_plane_state *plane_state, *linked_plane_state;
12530         int i;
12531
12532         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12533                 linked = plane_state->planar_linked_plane;
12534
12535                 if (!linked)
12536                         continue;
12537
12538                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12539                 if (IS_ERR(linked_plane_state))
12540                         return PTR_ERR(linked_plane_state);
12541
12542                 drm_WARN_ON(state->base.dev,
12543                             linked_plane_state->planar_linked_plane != plane);
12544                 drm_WARN_ON(state->base.dev,
12545                             linked_plane_state->planar_slave == plane_state->planar_slave);
12546         }
12547
12548         return 0;
12549 }
12550
12551 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12552 {
12553         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12554         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12555         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12556         struct intel_plane *plane, *linked;
12557         struct intel_plane_state *plane_state;
12558         int i;
12559
12560         if (INTEL_GEN(dev_priv) < 11)
12561                 return 0;
12562
12563         /*
12564          * Destroy all old plane links and make the slave plane invisible
12565          * in the crtc_state->active_planes mask.
12566          */
12567         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12568                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12569                         continue;
12570
12571                 plane_state->planar_linked_plane = NULL;
12572                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12573                         crtc_state->active_planes &= ~BIT(plane->id);
12574                         crtc_state->update_planes |= BIT(plane->id);
12575                 }
12576
12577                 plane_state->planar_slave = false;
12578         }
12579
12580         if (!crtc_state->nv12_planes)
12581                 return 0;
12582
12583         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12584                 struct intel_plane_state *linked_state = NULL;
12585
12586                 if (plane->pipe != crtc->pipe ||
12587                     !(crtc_state->nv12_planes & BIT(plane->id)))
12588                         continue;
12589
12590                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12591                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12592                                 continue;
12593
12594                         if (crtc_state->active_planes & BIT(linked->id))
12595                                 continue;
12596
12597                         linked_state = intel_atomic_get_plane_state(state, linked);
12598                         if (IS_ERR(linked_state))
12599                                 return PTR_ERR(linked_state);
12600
12601                         break;
12602                 }
12603
12604                 if (!linked_state) {
12605                         drm_dbg_kms(&dev_priv->drm,
12606                                     "Need %d free Y planes for planar YUV\n",
12607                                     hweight8(crtc_state->nv12_planes));
12608
12609                         return -EINVAL;
12610                 }
12611
12612                 plane_state->planar_linked_plane = linked;
12613
12614                 linked_state->planar_slave = true;
12615                 linked_state->planar_linked_plane = plane;
12616                 crtc_state->active_planes |= BIT(linked->id);
12617                 crtc_state->update_planes |= BIT(linked->id);
12618                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12619                             linked->base.name, plane->base.name);
12620
12621                 /* Copy parameters to slave plane */
12622                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12623                 linked_state->color_ctl = plane_state->color_ctl;
12624                 linked_state->view = plane_state->view;
12625                 memcpy(linked_state->color_plane, plane_state->color_plane,
12626                        sizeof(linked_state->color_plane));
12627
12628                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12629                 linked_state->uapi.src = plane_state->uapi.src;
12630                 linked_state->uapi.dst = plane_state->uapi.dst;
12631
12632                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12633                         if (linked->id == PLANE_SPRITE5)
12634                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12635                         else if (linked->id == PLANE_SPRITE4)
12636                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12637                         else if (linked->id == PLANE_SPRITE3)
12638                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12639                         else if (linked->id == PLANE_SPRITE2)
12640                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12641                         else
12642                                 MISSING_CASE(linked->id);
12643                 }
12644         }
12645
12646         return 0;
12647 }
12648
12649 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12650 {
12651         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12652         struct intel_atomic_state *state =
12653                 to_intel_atomic_state(new_crtc_state->uapi.state);
12654         const struct intel_crtc_state *old_crtc_state =
12655                 intel_atomic_get_old_crtc_state(state, crtc);
12656
12657         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12658 }
12659
12660 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12661 {
12662         const struct drm_display_mode *adjusted_mode =
12663                 &crtc_state->hw.adjusted_mode;
12664         int linetime_wm;
12665
12666         if (!crtc_state->hw.enable)
12667                 return 0;
12668
12669         linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12670                                         adjusted_mode->crtc_clock);
12671
12672         return min(linetime_wm, 0x1ff);
12673 }
12674
12675 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12676                                const struct intel_cdclk_state *cdclk_state)
12677 {
12678         const struct drm_display_mode *adjusted_mode =
12679                 &crtc_state->hw.adjusted_mode;
12680         int linetime_wm;
12681
12682         if (!crtc_state->hw.enable)
12683                 return 0;
12684
12685         linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12686                                         cdclk_state->logical.cdclk);
12687
12688         return min(linetime_wm, 0x1ff);
12689 }
12690
12691 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12692 {
12693         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12695         const struct drm_display_mode *adjusted_mode =
12696                 &crtc_state->hw.adjusted_mode;
12697         int linetime_wm;
12698
12699         if (!crtc_state->hw.enable)
12700                 return 0;
12701
12702         linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12703                                    crtc_state->pixel_rate);
12704
12705         /* Display WA #1135: BXT:ALL GLK:ALL */
12706         if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12707                 linetime_wm /= 2;
12708
12709         return min(linetime_wm, 0x1ff);
12710 }
12711
12712 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12713                                    struct intel_crtc *crtc)
12714 {
12715         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12716         struct intel_crtc_state *crtc_state =
12717                 intel_atomic_get_new_crtc_state(state, crtc);
12718         const struct intel_cdclk_state *cdclk_state;
12719
12720         if (INTEL_GEN(dev_priv) >= 9)
12721                 crtc_state->linetime = skl_linetime_wm(crtc_state);
12722         else
12723                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12724
12725         if (!hsw_crtc_supports_ips(crtc))
12726                 return 0;
12727
12728         cdclk_state = intel_atomic_get_cdclk_state(state);
12729         if (IS_ERR(cdclk_state))
12730                 return PTR_ERR(cdclk_state);
12731
12732         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12733                                                        cdclk_state);
12734
12735         return 0;
12736 }
12737
12738 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12739                                    struct intel_crtc *crtc)
12740 {
12741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12742         struct intel_crtc_state *crtc_state =
12743                 intel_atomic_get_new_crtc_state(state, crtc);
12744         bool mode_changed = needs_modeset(crtc_state);
12745         int ret;
12746
12747         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12748             mode_changed && !crtc_state->hw.active)
12749                 crtc_state->update_wm_post = true;
12750
12751         if (mode_changed && crtc_state->hw.enable &&
12752             dev_priv->display.crtc_compute_clock &&
12753             !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12754                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12755                 if (ret)
12756                         return ret;
12757         }
12758
12759         /*
12760          * May need to update pipe gamma enable bits
12761          * when C8 planes are getting enabled/disabled.
12762          */
12763         if (c8_planes_changed(crtc_state))
12764                 crtc_state->uapi.color_mgmt_changed = true;
12765
12766         if (mode_changed || crtc_state->update_pipe ||
12767             crtc_state->uapi.color_mgmt_changed) {
12768                 ret = intel_color_check(crtc_state);
12769                 if (ret)
12770                         return ret;
12771         }
12772
12773         if (dev_priv->display.compute_pipe_wm) {
12774                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12775                 if (ret) {
12776                         drm_dbg_kms(&dev_priv->drm,
12777                                     "Target pipe watermarks are invalid\n");
12778                         return ret;
12779                 }
12780         }
12781
12782         if (dev_priv->display.compute_intermediate_wm) {
12783                 if (drm_WARN_ON(&dev_priv->drm,
12784                                 !dev_priv->display.compute_pipe_wm))
12785                         return 0;
12786
12787                 /*
12788                  * Calculate 'intermediate' watermarks that satisfy both the
12789                  * old state and the new state.  We can program these
12790                  * immediately.
12791                  */
12792                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12793                 if (ret) {
12794                         drm_dbg_kms(&dev_priv->drm,
12795                                     "No valid intermediate pipe watermarks are possible\n");
12796                         return ret;
12797                 }
12798         }
12799
12800         if (INTEL_GEN(dev_priv) >= 9) {
12801                 if (mode_changed || crtc_state->update_pipe) {
12802                         ret = skl_update_scaler_crtc(crtc_state);
12803                         if (ret)
12804                                 return ret;
12805                 }
12806
12807                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12808                 if (ret)
12809                         return ret;
12810         }
12811
12812         if (HAS_IPS(dev_priv)) {
12813                 ret = hsw_compute_ips_config(crtc_state);
12814                 if (ret)
12815                         return ret;
12816         }
12817
12818         if (INTEL_GEN(dev_priv) >= 9 ||
12819             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12820                 ret = hsw_compute_linetime_wm(state, crtc);
12821                 if (ret)
12822                         return ret;
12823
12824         }
12825
12826         if (!mode_changed)
12827                 intel_psr2_sel_fetch_update(state, crtc);
12828
12829         return 0;
12830 }
12831
12832 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12833 {
12834         struct intel_connector *connector;
12835         struct drm_connector_list_iter conn_iter;
12836
12837         drm_connector_list_iter_begin(dev, &conn_iter);
12838         for_each_intel_connector_iter(connector, &conn_iter) {
12839                 if (connector->base.state->crtc)
12840                         drm_connector_put(&connector->base);
12841
12842                 if (connector->base.encoder) {
12843                         connector->base.state->best_encoder =
12844                                 connector->base.encoder;
12845                         connector->base.state->crtc =
12846                                 connector->base.encoder->crtc;
12847
12848                         drm_connector_get(&connector->base);
12849                 } else {
12850                         connector->base.state->best_encoder = NULL;
12851                         connector->base.state->crtc = NULL;
12852                 }
12853         }
12854         drm_connector_list_iter_end(&conn_iter);
12855 }
12856
12857 static int
12858 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12859                       struct intel_crtc_state *pipe_config)
12860 {
12861         struct drm_connector *connector = conn_state->connector;
12862         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12863         const struct drm_display_info *info = &connector->display_info;
12864         int bpp;
12865
12866         switch (conn_state->max_bpc) {
12867         case 6 ... 7:
12868                 bpp = 6 * 3;
12869                 break;
12870         case 8 ... 9:
12871                 bpp = 8 * 3;
12872                 break;
12873         case 10 ... 11:
12874                 bpp = 10 * 3;
12875                 break;
12876         case 12:
12877                 bpp = 12 * 3;
12878                 break;
12879         default:
12880                 return -EINVAL;
12881         }
12882
12883         if (bpp < pipe_config->pipe_bpp) {
12884                 drm_dbg_kms(&i915->drm,
12885                             "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12886                             "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12887                             connector->base.id, connector->name,
12888                             bpp, 3 * info->bpc,
12889                             3 * conn_state->max_requested_bpc,
12890                             pipe_config->pipe_bpp);
12891
12892                 pipe_config->pipe_bpp = bpp;
12893         }
12894
12895         return 0;
12896 }
12897
12898 static int
12899 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12900                           struct intel_crtc_state *pipe_config)
12901 {
12902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12903         struct drm_atomic_state *state = pipe_config->uapi.state;
12904         struct drm_connector *connector;
12905         struct drm_connector_state *connector_state;
12906         int bpp, i;
12907
12908         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12909             IS_CHERRYVIEW(dev_priv)))
12910                 bpp = 10*3;
12911         else if (INTEL_GEN(dev_priv) >= 5)
12912                 bpp = 12*3;
12913         else
12914                 bpp = 8*3;
12915
12916         pipe_config->pipe_bpp = bpp;
12917
12918         /* Clamp display bpp to connector max bpp */
12919         for_each_new_connector_in_state(state, connector, connector_state, i) {
12920                 int ret;
12921
12922                 if (connector_state->crtc != &crtc->base)
12923                         continue;
12924
12925                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12926                 if (ret)
12927                         return ret;
12928         }
12929
12930         return 0;
12931 }
12932
12933 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
12934                                     const struct drm_display_mode *mode)
12935 {
12936         drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
12937                     "type: 0x%x flags: 0x%x\n",
12938                     mode->crtc_clock,
12939                     mode->crtc_hdisplay, mode->crtc_hsync_start,
12940                     mode->crtc_hsync_end, mode->crtc_htotal,
12941                     mode->crtc_vdisplay, mode->crtc_vsync_start,
12942                     mode->crtc_vsync_end, mode->crtc_vtotal,
12943                     mode->type, mode->flags);
12944 }
12945
12946 static void
12947 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12948                       const char *id, unsigned int lane_count,
12949                       const struct intel_link_m_n *m_n)
12950 {
12951         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12952
12953         drm_dbg_kms(&i915->drm,
12954                     "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12955                     id, lane_count,
12956                     m_n->gmch_m, m_n->gmch_n,
12957                     m_n->link_m, m_n->link_n, m_n->tu);
12958 }
12959
12960 static void
12961 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12962                      const union hdmi_infoframe *frame)
12963 {
12964         if (!drm_debug_enabled(DRM_UT_KMS))
12965                 return;
12966
12967         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12968 }
12969
12970 static void
12971 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
12972                       const struct drm_dp_vsc_sdp *vsc)
12973 {
12974         if (!drm_debug_enabled(DRM_UT_KMS))
12975                 return;
12976
12977         drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
12978 }
12979
12980 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12981
12982 static const char * const output_type_str[] = {
12983         OUTPUT_TYPE(UNUSED),
12984         OUTPUT_TYPE(ANALOG),
12985         OUTPUT_TYPE(DVO),
12986         OUTPUT_TYPE(SDVO),
12987         OUTPUT_TYPE(LVDS),
12988         OUTPUT_TYPE(TVOUT),
12989         OUTPUT_TYPE(HDMI),
12990         OUTPUT_TYPE(DP),
12991         OUTPUT_TYPE(EDP),
12992         OUTPUT_TYPE(DSI),
12993         OUTPUT_TYPE(DDI),
12994         OUTPUT_TYPE(DP_MST),
12995 };
12996
12997 #undef OUTPUT_TYPE
12998
12999 static void snprintf_output_types(char *buf, size_t len,
13000                                   unsigned int output_types)
13001 {
13002         char *str = buf;
13003         int i;
13004
13005         str[0] = '\0';
13006
13007         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13008                 int r;
13009
13010                 if ((output_types & BIT(i)) == 0)
13011                         continue;
13012
13013                 r = snprintf(str, len, "%s%s",
13014                              str != buf ? "," : "", output_type_str[i]);
13015                 if (r >= len)
13016                         break;
13017                 str += r;
13018                 len -= r;
13019
13020                 output_types &= ~BIT(i);
13021         }
13022
13023         WARN_ON_ONCE(output_types != 0);
13024 }
13025
13026 static const char * const output_format_str[] = {
13027         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13028         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13029         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13030         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13031 };
13032
13033 static const char *output_formats(enum intel_output_format format)
13034 {
13035         if (format >= ARRAY_SIZE(output_format_str))
13036                 format = INTEL_OUTPUT_FORMAT_INVALID;
13037         return output_format_str[format];
13038 }
13039
13040 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13041 {
13042         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13043         struct drm_i915_private *i915 = to_i915(plane->base.dev);
13044         const struct drm_framebuffer *fb = plane_state->hw.fb;
13045         struct drm_format_name_buf format_name;
13046
13047         if (!fb) {
13048                 drm_dbg_kms(&i915->drm,
13049                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13050                             plane->base.base.id, plane->base.name,
13051                             yesno(plane_state->uapi.visible));
13052                 return;
13053         }
13054
13055         drm_dbg_kms(&i915->drm,
13056                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13057                     plane->base.base.id, plane->base.name,
13058                     fb->base.id, fb->width, fb->height,
13059                     drm_get_format_name(fb->format->format, &format_name),
13060                     yesno(plane_state->uapi.visible));
13061         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13062                     plane_state->hw.rotation, plane_state->scaler_id);
13063         if (plane_state->uapi.visible)
13064                 drm_dbg_kms(&i915->drm,
13065                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13066                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
13067                             DRM_RECT_ARG(&plane_state->uapi.dst));
13068 }
13069
13070 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13071                                    struct intel_atomic_state *state,
13072                                    const char *context)
13073 {
13074         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13076         const struct intel_plane_state *plane_state;
13077         struct intel_plane *plane;
13078         char buf[64];
13079         int i;
13080
13081         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13082                     crtc->base.base.id, crtc->base.name,
13083                     yesno(pipe_config->hw.enable), context);
13084
13085         if (!pipe_config->hw.enable)
13086                 goto dump_planes;
13087
13088         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13089         drm_dbg_kms(&dev_priv->drm,
13090                     "active: %s, output_types: %s (0x%x), output format: %s\n",
13091                     yesno(pipe_config->hw.active),
13092                     buf, pipe_config->output_types,
13093                     output_formats(pipe_config->output_format));
13094
13095         drm_dbg_kms(&dev_priv->drm,
13096                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13097                     transcoder_name(pipe_config->cpu_transcoder),
13098                     pipe_config->pipe_bpp, pipe_config->dither);
13099
13100         drm_dbg_kms(&dev_priv->drm,
13101                     "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13102                     transcoder_name(pipe_config->master_transcoder),
13103                     pipe_config->sync_mode_slaves_mask);
13104
13105         if (pipe_config->has_pch_encoder)
13106                 intel_dump_m_n_config(pipe_config, "fdi",
13107                                       pipe_config->fdi_lanes,
13108                                       &pipe_config->fdi_m_n);
13109
13110         if (intel_crtc_has_dp_encoder(pipe_config)) {
13111                 intel_dump_m_n_config(pipe_config, "dp m_n",
13112                                 pipe_config->lane_count, &pipe_config->dp_m_n);
13113                 if (pipe_config->has_drrs)
13114                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
13115                                               pipe_config->lane_count,
13116                                               &pipe_config->dp_m2_n2);
13117         }
13118
13119         drm_dbg_kms(&dev_priv->drm,
13120                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13121                     pipe_config->has_audio, pipe_config->has_infoframe,
13122                     pipe_config->infoframes.enable);
13123
13124         if (pipe_config->infoframes.enable &
13125             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13126                 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13127                             pipe_config->infoframes.gcp);
13128         if (pipe_config->infoframes.enable &
13129             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13130                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13131         if (pipe_config->infoframes.enable &
13132             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13133                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13134         if (pipe_config->infoframes.enable &
13135             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13136                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13137         if (pipe_config->infoframes.enable &
13138             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13139                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13140         if (pipe_config->infoframes.enable &
13141             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13142                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13143         if (pipe_config->infoframes.enable &
13144             intel_hdmi_infoframe_enable(DP_SDP_VSC))
13145                 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13146
13147         drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13148         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13149         drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13150         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13151         intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13152         drm_dbg_kms(&dev_priv->drm,
13153                     "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13154                     pipe_config->port_clock,
13155                     pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13156                     pipe_config->pixel_rate);
13157
13158         drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13159                     pipe_config->linetime, pipe_config->ips_linetime);
13160
13161         if (INTEL_GEN(dev_priv) >= 9)
13162                 drm_dbg_kms(&dev_priv->drm,
13163                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13164                             crtc->num_scalers,
13165                             pipe_config->scaler_state.scaler_users,
13166                             pipe_config->scaler_state.scaler_id);
13167
13168         if (HAS_GMCH(dev_priv))
13169                 drm_dbg_kms(&dev_priv->drm,
13170                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13171                             pipe_config->gmch_pfit.control,
13172                             pipe_config->gmch_pfit.pgm_ratios,
13173                             pipe_config->gmch_pfit.lvds_border_bits);
13174         else
13175                 drm_dbg_kms(&dev_priv->drm,
13176                             "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13177                             DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13178                             enableddisabled(pipe_config->pch_pfit.enabled),
13179                             yesno(pipe_config->pch_pfit.force_thru));
13180
13181         drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13182                     pipe_config->ips_enabled, pipe_config->double_wide);
13183
13184         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13185
13186         if (IS_CHERRYVIEW(dev_priv))
13187                 drm_dbg_kms(&dev_priv->drm,
13188                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13189                             pipe_config->cgm_mode, pipe_config->gamma_mode,
13190                             pipe_config->gamma_enable, pipe_config->csc_enable);
13191         else
13192                 drm_dbg_kms(&dev_priv->drm,
13193                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13194                             pipe_config->csc_mode, pipe_config->gamma_mode,
13195                             pipe_config->gamma_enable, pipe_config->csc_enable);
13196
13197         drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13198                     transcoder_name(pipe_config->mst_master_transcoder));
13199
13200 dump_planes:
13201         if (!state)
13202                 return;
13203
13204         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13205                 if (plane->pipe == crtc->pipe)
13206                         intel_dump_plane_state(plane_state);
13207         }
13208 }
13209
13210 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13211 {
13212         struct drm_device *dev = state->base.dev;
13213         struct drm_connector *connector;
13214         struct drm_connector_list_iter conn_iter;
13215         unsigned int used_ports = 0;
13216         unsigned int used_mst_ports = 0;
13217         bool ret = true;
13218
13219         /*
13220          * We're going to peek into connector->state,
13221          * hence connection_mutex must be held.
13222          */
13223         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13224
13225         /*
13226          * Walk the connector list instead of the encoder
13227          * list to detect the problem on ddi platforms
13228          * where there's just one encoder per digital port.
13229          */
13230         drm_connector_list_iter_begin(dev, &conn_iter);
13231         drm_for_each_connector_iter(connector, &conn_iter) {
13232                 struct drm_connector_state *connector_state;
13233                 struct intel_encoder *encoder;
13234
13235                 connector_state =
13236                         drm_atomic_get_new_connector_state(&state->base,
13237                                                            connector);
13238                 if (!connector_state)
13239                         connector_state = connector->state;
13240
13241                 if (!connector_state->best_encoder)
13242                         continue;
13243
13244                 encoder = to_intel_encoder(connector_state->best_encoder);
13245
13246                 drm_WARN_ON(dev, !connector_state->crtc);
13247
13248                 switch (encoder->type) {
13249                 case INTEL_OUTPUT_DDI:
13250                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13251                                 break;
13252                         fallthrough;
13253                 case INTEL_OUTPUT_DP:
13254                 case INTEL_OUTPUT_HDMI:
13255                 case INTEL_OUTPUT_EDP:
13256                         /* the same port mustn't appear more than once */
13257                         if (used_ports & BIT(encoder->port))
13258                                 ret = false;
13259
13260                         used_ports |= BIT(encoder->port);
13261                         break;
13262                 case INTEL_OUTPUT_DP_MST:
13263                         used_mst_ports |=
13264                                 1 << encoder->port;
13265                         break;
13266                 default:
13267                         break;
13268                 }
13269         }
13270         drm_connector_list_iter_end(&conn_iter);
13271
13272         /* can't mix MST and SST/HDMI on the same port */
13273         if (used_ports & used_mst_ports)
13274                 return false;
13275
13276         return ret;
13277 }
13278
13279 static void
13280 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13281 {
13282         intel_crtc_copy_color_blobs(crtc_state);
13283 }
13284
13285 static void
13286 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13287 {
13288         crtc_state->hw.enable = crtc_state->uapi.enable;
13289         crtc_state->hw.active = crtc_state->uapi.active;
13290         crtc_state->hw.mode = crtc_state->uapi.mode;
13291         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13292         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13293 }
13294
13295 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13296 {
13297         crtc_state->uapi.enable = crtc_state->hw.enable;
13298         crtc_state->uapi.active = crtc_state->hw.active;
13299         drm_WARN_ON(crtc_state->uapi.crtc->dev,
13300                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13301
13302         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13303
13304         /* copy color blobs to uapi */
13305         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13306                                   crtc_state->hw.degamma_lut);
13307         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13308                                   crtc_state->hw.gamma_lut);
13309         drm_property_replace_blob(&crtc_state->uapi.ctm,
13310                                   crtc_state->hw.ctm);
13311 }
13312
13313 static int
13314 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13315 {
13316         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13317         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13318         struct intel_crtc_state *saved_state;
13319
13320         saved_state = intel_crtc_state_alloc(crtc);
13321         if (!saved_state)
13322                 return -ENOMEM;
13323
13324         /* free the old crtc_state->hw members */
13325         intel_crtc_free_hw_state(crtc_state);
13326
13327         /* FIXME: before the switch to atomic started, a new pipe_config was
13328          * kzalloc'd. Code that depends on any field being zero should be
13329          * fixed, so that the crtc_state can be safely duplicated. For now,
13330          * only fields that are know to not cause problems are preserved. */
13331
13332         saved_state->uapi = crtc_state->uapi;
13333         saved_state->scaler_state = crtc_state->scaler_state;
13334         saved_state->shared_dpll = crtc_state->shared_dpll;
13335         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13336         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13337                sizeof(saved_state->icl_port_dplls));
13338         saved_state->crc_enabled = crtc_state->crc_enabled;
13339         if (IS_G4X(dev_priv) ||
13340             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13341                 saved_state->wm = crtc_state->wm;
13342
13343         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13344         kfree(saved_state);
13345
13346         intel_crtc_copy_uapi_to_hw_state(crtc_state);
13347
13348         return 0;
13349 }
13350
13351 static int
13352 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13353 {
13354         struct drm_crtc *crtc = pipe_config->uapi.crtc;
13355         struct drm_atomic_state *state = pipe_config->uapi.state;
13356         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13357         struct drm_connector *connector;
13358         struct drm_connector_state *connector_state;
13359         int base_bpp, ret, i;
13360         bool retry = true;
13361
13362         pipe_config->cpu_transcoder =
13363                 (enum transcoder) to_intel_crtc(crtc)->pipe;
13364
13365         /*
13366          * Sanitize sync polarity flags based on requested ones. If neither
13367          * positive or negative polarity is requested, treat this as meaning
13368          * negative polarity.
13369          */
13370         if (!(pipe_config->hw.adjusted_mode.flags &
13371               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13372                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13373
13374         if (!(pipe_config->hw.adjusted_mode.flags &
13375               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13376                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13377
13378         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13379                                         pipe_config);
13380         if (ret)
13381                 return ret;
13382
13383         base_bpp = pipe_config->pipe_bpp;
13384
13385         /*
13386          * Determine the real pipe dimensions. Note that stereo modes can
13387          * increase the actual pipe size due to the frame doubling and
13388          * insertion of additional space for blanks between the frame. This
13389          * is stored in the crtc timings. We use the requested mode to do this
13390          * computation to clearly distinguish it from the adjusted mode, which
13391          * can be changed by the connectors in the below retry loop.
13392          */
13393         drm_mode_get_hv_timing(&pipe_config->hw.mode,
13394                                &pipe_config->pipe_src_w,
13395                                &pipe_config->pipe_src_h);
13396
13397         for_each_new_connector_in_state(state, connector, connector_state, i) {
13398                 struct intel_encoder *encoder =
13399                         to_intel_encoder(connector_state->best_encoder);
13400
13401                 if (connector_state->crtc != crtc)
13402                         continue;
13403
13404                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13405                         drm_dbg_kms(&i915->drm,
13406                                     "rejecting invalid cloning configuration\n");
13407                         return -EINVAL;
13408                 }
13409
13410                 /*
13411                  * Determine output_types before calling the .compute_config()
13412                  * hooks so that the hooks can use this information safely.
13413                  */
13414                 if (encoder->compute_output_type)
13415                         pipe_config->output_types |=
13416                                 BIT(encoder->compute_output_type(encoder, pipe_config,
13417                                                                  connector_state));
13418                 else
13419                         pipe_config->output_types |= BIT(encoder->type);
13420         }
13421
13422 encoder_retry:
13423         /* Ensure the port clock defaults are reset when retrying. */
13424         pipe_config->port_clock = 0;
13425         pipe_config->pixel_multiplier = 1;
13426
13427         /* Fill in default crtc timings, allow encoders to overwrite them. */
13428         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13429                               CRTC_STEREO_DOUBLE);
13430
13431         /* Pass our mode to the connectors and the CRTC to give them a chance to
13432          * adjust it according to limitations or connector properties, and also
13433          * a chance to reject the mode entirely.
13434          */
13435         for_each_new_connector_in_state(state, connector, connector_state, i) {
13436                 struct intel_encoder *encoder =
13437                         to_intel_encoder(connector_state->best_encoder);
13438
13439                 if (connector_state->crtc != crtc)
13440                         continue;
13441
13442                 ret = encoder->compute_config(encoder, pipe_config,
13443                                               connector_state);
13444                 if (ret < 0) {
13445                         if (ret != -EDEADLK)
13446                                 drm_dbg_kms(&i915->drm,
13447                                             "Encoder config failure: %d\n",
13448                                             ret);
13449                         return ret;
13450                 }
13451         }
13452
13453         /* Set default port clock if not overwritten by the encoder. Needs to be
13454          * done afterwards in case the encoder adjusts the mode. */
13455         if (!pipe_config->port_clock)
13456                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13457                         * pipe_config->pixel_multiplier;
13458
13459         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13460         if (ret == -EDEADLK)
13461                 return ret;
13462         if (ret < 0) {
13463                 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13464                 return ret;
13465         }
13466
13467         if (ret == RETRY) {
13468                 if (drm_WARN(&i915->drm, !retry,
13469                              "loop in pipe configuration computation\n"))
13470                         return -EINVAL;
13471
13472                 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13473                 retry = false;
13474                 goto encoder_retry;
13475         }
13476
13477         /* Dithering seems to not pass-through bits correctly when it should, so
13478          * only enable it on 6bpc panels and when its not a compliance
13479          * test requesting 6bpc video pattern.
13480          */
13481         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13482                 !pipe_config->dither_force_disable;
13483         drm_dbg_kms(&i915->drm,
13484                     "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13485                     base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13486
13487         return 0;
13488 }
13489
13490 static int
13491 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13492 {
13493         struct intel_atomic_state *state =
13494                 to_intel_atomic_state(crtc_state->uapi.state);
13495         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13496         struct drm_connector_state *conn_state;
13497         struct drm_connector *connector;
13498         int i;
13499
13500         for_each_new_connector_in_state(&state->base, connector,
13501                                         conn_state, i) {
13502                 struct intel_encoder *encoder =
13503                         to_intel_encoder(conn_state->best_encoder);
13504                 int ret;
13505
13506                 if (conn_state->crtc != &crtc->base ||
13507                     !encoder->compute_config_late)
13508                         continue;
13509
13510                 ret = encoder->compute_config_late(encoder, crtc_state,
13511                                                    conn_state);
13512                 if (ret)
13513                         return ret;
13514         }
13515
13516         return 0;
13517 }
13518
13519 bool intel_fuzzy_clock_check(int clock1, int clock2)
13520 {
13521         int diff;
13522
13523         if (clock1 == clock2)
13524                 return true;
13525
13526         if (!clock1 || !clock2)
13527                 return false;
13528
13529         diff = abs(clock1 - clock2);
13530
13531         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13532                 return true;
13533
13534         return false;
13535 }
13536
13537 static bool
13538 intel_compare_m_n(unsigned int m, unsigned int n,
13539                   unsigned int m2, unsigned int n2,
13540                   bool exact)
13541 {
13542         if (m == m2 && n == n2)
13543                 return true;
13544
13545         if (exact || !m || !n || !m2 || !n2)
13546                 return false;
13547
13548         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13549
13550         if (n > n2) {
13551                 while (n > n2) {
13552                         m2 <<= 1;
13553                         n2 <<= 1;
13554                 }
13555         } else if (n < n2) {
13556                 while (n < n2) {
13557                         m <<= 1;
13558                         n <<= 1;
13559                 }
13560         }
13561
13562         if (n != n2)
13563                 return false;
13564
13565         return intel_fuzzy_clock_check(m, m2);
13566 }
13567
13568 static bool
13569 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13570                        const struct intel_link_m_n *m2_n2,
13571                        bool exact)
13572 {
13573         return m_n->tu == m2_n2->tu &&
13574                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13575                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13576                 intel_compare_m_n(m_n->link_m, m_n->link_n,
13577                                   m2_n2->link_m, m2_n2->link_n, exact);
13578 }
13579
13580 static bool
13581 intel_compare_infoframe(const union hdmi_infoframe *a,
13582                         const union hdmi_infoframe *b)
13583 {
13584         return memcmp(a, b, sizeof(*a)) == 0;
13585 }
13586
13587 static bool
13588 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13589                          const struct drm_dp_vsc_sdp *b)
13590 {
13591         return memcmp(a, b, sizeof(*a)) == 0;
13592 }
13593
13594 static void
13595 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13596                                bool fastset, const char *name,
13597                                const union hdmi_infoframe *a,
13598                                const union hdmi_infoframe *b)
13599 {
13600         if (fastset) {
13601                 if (!drm_debug_enabled(DRM_UT_KMS))
13602                         return;
13603
13604                 drm_dbg_kms(&dev_priv->drm,
13605                             "fastset mismatch in %s infoframe\n", name);
13606                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13607                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13608                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13609                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13610         } else {
13611                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13612                 drm_err(&dev_priv->drm, "expected:\n");
13613                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13614                 drm_err(&dev_priv->drm, "found:\n");
13615                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13616         }
13617 }
13618
13619 static void
13620 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13621                                 bool fastset, const char *name,
13622                                 const struct drm_dp_vsc_sdp *a,
13623                                 const struct drm_dp_vsc_sdp *b)
13624 {
13625         if (fastset) {
13626                 if (!drm_debug_enabled(DRM_UT_KMS))
13627                         return;
13628
13629                 drm_dbg_kms(&dev_priv->drm,
13630                             "fastset mismatch in %s dp sdp\n", name);
13631                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13632                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13633                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13634                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13635         } else {
13636                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13637                 drm_err(&dev_priv->drm, "expected:\n");
13638                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13639                 drm_err(&dev_priv->drm, "found:\n");
13640                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13641         }
13642 }
13643
13644 static void __printf(4, 5)
13645 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13646                      const char *name, const char *format, ...)
13647 {
13648         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13649         struct va_format vaf;
13650         va_list args;
13651
13652         va_start(args, format);
13653         vaf.fmt = format;
13654         vaf.va = &args;
13655
13656         if (fastset)
13657                 drm_dbg_kms(&i915->drm,
13658                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13659                             crtc->base.base.id, crtc->base.name, name, &vaf);
13660         else
13661                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13662                         crtc->base.base.id, crtc->base.name, name, &vaf);
13663
13664         va_end(args);
13665 }
13666
13667 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13668 {
13669         if (dev_priv->params.fastboot != -1)
13670                 return dev_priv->params.fastboot;
13671
13672         /* Enable fastboot by default on Skylake and newer */
13673         if (INTEL_GEN(dev_priv) >= 9)
13674                 return true;
13675
13676         /* Enable fastboot by default on VLV and CHV */
13677         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13678                 return true;
13679
13680         /* Disabled by default on all others */
13681         return false;
13682 }
13683
13684 static bool
13685 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13686                           const struct intel_crtc_state *pipe_config,
13687                           bool fastset)
13688 {
13689         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13690         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13691         bool ret = true;
13692         u32 bp_gamma = 0;
13693         bool fixup_inherited = fastset &&
13694                 current_config->inherited && !pipe_config->inherited;
13695
13696         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13697                 drm_dbg_kms(&dev_priv->drm,
13698                             "initial modeset and fastboot not set\n");
13699                 ret = false;
13700         }
13701
13702 #define PIPE_CONF_CHECK_X(name) do { \
13703         if (current_config->name != pipe_config->name) { \
13704                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13705                                      "(expected 0x%08x, found 0x%08x)", \
13706                                      current_config->name, \
13707                                      pipe_config->name); \
13708                 ret = false; \
13709         } \
13710 } while (0)
13711
13712 #define PIPE_CONF_CHECK_I(name) do { \
13713         if (current_config->name != pipe_config->name) { \
13714                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13715                                      "(expected %i, found %i)", \
13716                                      current_config->name, \
13717                                      pipe_config->name); \
13718                 ret = false; \
13719         } \
13720 } while (0)
13721
13722 #define PIPE_CONF_CHECK_BOOL(name) do { \
13723         if (current_config->name != pipe_config->name) { \
13724                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13725                                      "(expected %s, found %s)", \
13726                                      yesno(current_config->name), \
13727                                      yesno(pipe_config->name)); \
13728                 ret = false; \
13729         } \
13730 } while (0)
13731
13732 /*
13733  * Checks state where we only read out the enabling, but not the entire
13734  * state itself (like full infoframes or ELD for audio). These states
13735  * require a full modeset on bootup to fix up.
13736  */
13737 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13738         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13739                 PIPE_CONF_CHECK_BOOL(name); \
13740         } else { \
13741                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13742                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13743                                      yesno(current_config->name), \
13744                                      yesno(pipe_config->name)); \
13745                 ret = false; \
13746         } \
13747 } while (0)
13748
13749 #define PIPE_CONF_CHECK_P(name) do { \
13750         if (current_config->name != pipe_config->name) { \
13751                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13752                                      "(expected %p, found %p)", \
13753                                      current_config->name, \
13754                                      pipe_config->name); \
13755                 ret = false; \
13756         } \
13757 } while (0)
13758
13759 #define PIPE_CONF_CHECK_M_N(name) do { \
13760         if (!intel_compare_link_m_n(&current_config->name, \
13761                                     &pipe_config->name,\
13762                                     !fastset)) { \
13763                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13764                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13765                                      "found tu %i, gmch %i/%i link %i/%i)", \
13766                                      current_config->name.tu, \
13767                                      current_config->name.gmch_m, \
13768                                      current_config->name.gmch_n, \
13769                                      current_config->name.link_m, \
13770                                      current_config->name.link_n, \
13771                                      pipe_config->name.tu, \
13772                                      pipe_config->name.gmch_m, \
13773                                      pipe_config->name.gmch_n, \
13774                                      pipe_config->name.link_m, \
13775                                      pipe_config->name.link_n); \
13776                 ret = false; \
13777         } \
13778 } while (0)
13779
13780 /* This is required for BDW+ where there is only one set of registers for
13781  * switching between high and low RR.
13782  * This macro can be used whenever a comparison has to be made between one
13783  * hw state and multiple sw state variables.
13784  */
13785 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13786         if (!intel_compare_link_m_n(&current_config->name, \
13787                                     &pipe_config->name, !fastset) && \
13788             !intel_compare_link_m_n(&current_config->alt_name, \
13789                                     &pipe_config->name, !fastset)) { \
13790                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13791                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13792                                      "or tu %i gmch %i/%i link %i/%i, " \
13793                                      "found tu %i, gmch %i/%i link %i/%i)", \
13794                                      current_config->name.tu, \
13795                                      current_config->name.gmch_m, \
13796                                      current_config->name.gmch_n, \
13797                                      current_config->name.link_m, \
13798                                      current_config->name.link_n, \
13799                                      current_config->alt_name.tu, \
13800                                      current_config->alt_name.gmch_m, \
13801                                      current_config->alt_name.gmch_n, \
13802                                      current_config->alt_name.link_m, \
13803                                      current_config->alt_name.link_n, \
13804                                      pipe_config->name.tu, \
13805                                      pipe_config->name.gmch_m, \
13806                                      pipe_config->name.gmch_n, \
13807                                      pipe_config->name.link_m, \
13808                                      pipe_config->name.link_n); \
13809                 ret = false; \
13810         } \
13811 } while (0)
13812
13813 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13814         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13815                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13816                                      "(%x) (expected %i, found %i)", \
13817                                      (mask), \
13818                                      current_config->name & (mask), \
13819                                      pipe_config->name & (mask)); \
13820                 ret = false; \
13821         } \
13822 } while (0)
13823
13824 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13825         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13826                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13827                                      "(expected %i, found %i)", \
13828                                      current_config->name, \
13829                                      pipe_config->name); \
13830                 ret = false; \
13831         } \
13832 } while (0)
13833
13834 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13835         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13836                                      &pipe_config->infoframes.name)) { \
13837                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13838                                                &current_config->infoframes.name, \
13839                                                &pipe_config->infoframes.name); \
13840                 ret = false; \
13841         } \
13842 } while (0)
13843
13844 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13845         if (!current_config->has_psr && !pipe_config->has_psr && \
13846             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
13847                                       &pipe_config->infoframes.name)) { \
13848                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13849                                                 &current_config->infoframes.name, \
13850                                                 &pipe_config->infoframes.name); \
13851                 ret = false; \
13852         } \
13853 } while (0)
13854
13855 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13856         if (current_config->name1 != pipe_config->name1) { \
13857                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13858                                 "(expected %i, found %i, won't compare lut values)", \
13859                                 current_config->name1, \
13860                                 pipe_config->name1); \
13861                 ret = false;\
13862         } else { \
13863                 if (!intel_color_lut_equal(current_config->name2, \
13864                                         pipe_config->name2, pipe_config->name1, \
13865                                         bit_precision)) { \
13866                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13867                                         "hw_state doesn't match sw_state"); \
13868                         ret = false; \
13869                 } \
13870         } \
13871 } while (0)
13872
13873 #define PIPE_CONF_QUIRK(quirk) \
13874         ((current_config->quirks | pipe_config->quirks) & (quirk))
13875
13876         PIPE_CONF_CHECK_I(cpu_transcoder);
13877
13878         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13879         PIPE_CONF_CHECK_I(fdi_lanes);
13880         PIPE_CONF_CHECK_M_N(fdi_m_n);
13881
13882         PIPE_CONF_CHECK_I(lane_count);
13883         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13884
13885         if (INTEL_GEN(dev_priv) < 8) {
13886                 PIPE_CONF_CHECK_M_N(dp_m_n);
13887
13888                 if (current_config->has_drrs)
13889                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13890         } else
13891                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13892
13893         PIPE_CONF_CHECK_X(output_types);
13894
13895         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13896         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13897         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13898         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13899         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13900         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13901
13902         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13903         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13904         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13905         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13906         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13907         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13908
13909         PIPE_CONF_CHECK_I(pixel_multiplier);
13910         PIPE_CONF_CHECK_I(output_format);
13911         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13912         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13913             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13914                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13915
13916         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13917         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13918         PIPE_CONF_CHECK_BOOL(has_infoframe);
13919         PIPE_CONF_CHECK_BOOL(fec_enable);
13920
13921         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13922
13923         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13924                               DRM_MODE_FLAG_INTERLACE);
13925
13926         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13927                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13928                                       DRM_MODE_FLAG_PHSYNC);
13929                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13930                                       DRM_MODE_FLAG_NHSYNC);
13931                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13932                                       DRM_MODE_FLAG_PVSYNC);
13933                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13934                                       DRM_MODE_FLAG_NVSYNC);
13935         }
13936
13937         PIPE_CONF_CHECK_X(gmch_pfit.control);
13938         /* pfit ratios are autocomputed by the hw on gen4+ */
13939         if (INTEL_GEN(dev_priv) < 4)
13940                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13941         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13942
13943         /*
13944          * Changing the EDP transcoder input mux
13945          * (A_ONOFF vs. A_ON) requires a full modeset.
13946          */
13947         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13948
13949         if (!fastset) {
13950                 PIPE_CONF_CHECK_I(pipe_src_w);
13951                 PIPE_CONF_CHECK_I(pipe_src_h);
13952
13953                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13954                 if (current_config->pch_pfit.enabled) {
13955                         PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
13956                         PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
13957                         PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
13958                         PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
13959                 }
13960
13961                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13962                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13963
13964                 PIPE_CONF_CHECK_X(gamma_mode);
13965                 if (IS_CHERRYVIEW(dev_priv))
13966                         PIPE_CONF_CHECK_X(cgm_mode);
13967                 else
13968                         PIPE_CONF_CHECK_X(csc_mode);
13969                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13970                 PIPE_CONF_CHECK_BOOL(csc_enable);
13971
13972                 PIPE_CONF_CHECK_I(linetime);
13973                 PIPE_CONF_CHECK_I(ips_linetime);
13974
13975                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13976                 if (bp_gamma)
13977                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13978         }
13979
13980         PIPE_CONF_CHECK_BOOL(double_wide);
13981
13982         PIPE_CONF_CHECK_P(shared_dpll);
13983         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13984         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13985         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13986         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13987         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13988         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13989         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13990         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13991         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13992         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13993         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13994         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13995         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13996         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13997         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13998         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13999         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14000         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14001         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14002         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14003         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14004         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14005         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14006         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14007         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14008         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14009         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14010         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14011         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14012         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14013         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14014
14015         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14016         PIPE_CONF_CHECK_X(dsi_pll.div);
14017
14018         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14019                 PIPE_CONF_CHECK_I(pipe_bpp);
14020
14021         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14022         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14023
14024         PIPE_CONF_CHECK_I(min_voltage_level);
14025
14026         PIPE_CONF_CHECK_X(infoframes.enable);
14027         PIPE_CONF_CHECK_X(infoframes.gcp);
14028         PIPE_CONF_CHECK_INFOFRAME(avi);
14029         PIPE_CONF_CHECK_INFOFRAME(spd);
14030         PIPE_CONF_CHECK_INFOFRAME(hdmi);
14031         PIPE_CONF_CHECK_INFOFRAME(drm);
14032         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14033
14034         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14035         PIPE_CONF_CHECK_I(master_transcoder);
14036
14037         PIPE_CONF_CHECK_I(dsc.compression_enable);
14038         PIPE_CONF_CHECK_I(dsc.dsc_split);
14039         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14040
14041         PIPE_CONF_CHECK_I(mst_master_transcoder);
14042
14043 #undef PIPE_CONF_CHECK_X
14044 #undef PIPE_CONF_CHECK_I
14045 #undef PIPE_CONF_CHECK_BOOL
14046 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14047 #undef PIPE_CONF_CHECK_P
14048 #undef PIPE_CONF_CHECK_FLAGS
14049 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14050 #undef PIPE_CONF_CHECK_COLOR_LUT
14051 #undef PIPE_CONF_QUIRK
14052
14053         return ret;
14054 }
14055
14056 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14057                                            const struct intel_crtc_state *pipe_config)
14058 {
14059         if (pipe_config->has_pch_encoder) {
14060                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14061                                                             &pipe_config->fdi_m_n);
14062                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14063
14064                 /*
14065                  * FDI already provided one idea for the dotclock.
14066                  * Yell if the encoder disagrees.
14067                  */
14068                 drm_WARN(&dev_priv->drm,
14069                          !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14070                          "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14071                          fdi_dotclock, dotclock);
14072         }
14073 }
14074
14075 static void verify_wm_state(struct intel_crtc *crtc,
14076                             struct intel_crtc_state *new_crtc_state)
14077 {
14078         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14079         struct skl_hw_state {
14080                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14081                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14082                 struct skl_pipe_wm wm;
14083         } *hw;
14084         struct skl_pipe_wm *sw_wm;
14085         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14086         u8 hw_enabled_slices;
14087         const enum pipe pipe = crtc->pipe;
14088         int plane, level, max_level = ilk_wm_max_level(dev_priv);
14089
14090         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14091                 return;
14092
14093         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14094         if (!hw)
14095                 return;
14096
14097         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14098         sw_wm = &new_crtc_state->wm.skl.optimal;
14099
14100         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14101
14102         hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14103
14104         if (INTEL_GEN(dev_priv) >= 11 &&
14105             hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14106                 drm_err(&dev_priv->drm,
14107                         "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14108                         dev_priv->dbuf.enabled_slices,
14109                         hw_enabled_slices);
14110
14111         /* planes */
14112         for_each_universal_plane(dev_priv, pipe, plane) {
14113                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14114
14115                 hw_plane_wm = &hw->wm.planes[plane];
14116                 sw_plane_wm = &sw_wm->planes[plane];
14117
14118                 /* Watermarks */
14119                 for (level = 0; level <= max_level; level++) {
14120                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14121                                                 &sw_plane_wm->wm[level]) ||
14122                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14123                                                                &sw_plane_wm->sagv_wm0)))
14124                                 continue;
14125
14126                         drm_err(&dev_priv->drm,
14127                                 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14128                                 pipe_name(pipe), plane + 1, level,
14129                                 sw_plane_wm->wm[level].plane_en,
14130                                 sw_plane_wm->wm[level].plane_res_b,
14131                                 sw_plane_wm->wm[level].plane_res_l,
14132                                 hw_plane_wm->wm[level].plane_en,
14133                                 hw_plane_wm->wm[level].plane_res_b,
14134                                 hw_plane_wm->wm[level].plane_res_l);
14135                 }
14136
14137                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14138                                          &sw_plane_wm->trans_wm)) {
14139                         drm_err(&dev_priv->drm,
14140                                 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14141                                 pipe_name(pipe), plane + 1,
14142                                 sw_plane_wm->trans_wm.plane_en,
14143                                 sw_plane_wm->trans_wm.plane_res_b,
14144                                 sw_plane_wm->trans_wm.plane_res_l,
14145                                 hw_plane_wm->trans_wm.plane_en,
14146                                 hw_plane_wm->trans_wm.plane_res_b,
14147                                 hw_plane_wm->trans_wm.plane_res_l);
14148                 }
14149
14150                 /* DDB */
14151                 hw_ddb_entry = &hw->ddb_y[plane];
14152                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14153
14154                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14155                         drm_err(&dev_priv->drm,
14156                                 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14157                                 pipe_name(pipe), plane + 1,
14158                                 sw_ddb_entry->start, sw_ddb_entry->end,
14159                                 hw_ddb_entry->start, hw_ddb_entry->end);
14160                 }
14161         }
14162
14163         /*
14164          * cursor
14165          * If the cursor plane isn't active, we may not have updated it's ddb
14166          * allocation. In that case since the ddb allocation will be updated
14167          * once the plane becomes visible, we can skip this check
14168          */
14169         if (1) {
14170                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14171
14172                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14173                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14174
14175                 /* Watermarks */
14176                 for (level = 0; level <= max_level; level++) {
14177                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14178                                                 &sw_plane_wm->wm[level]) ||
14179                             (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14180                                                                &sw_plane_wm->sagv_wm0)))
14181                                 continue;
14182
14183                         drm_err(&dev_priv->drm,
14184                                 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14185                                 pipe_name(pipe), level,
14186                                 sw_plane_wm->wm[level].plane_en,
14187                                 sw_plane_wm->wm[level].plane_res_b,
14188                                 sw_plane_wm->wm[level].plane_res_l,
14189                                 hw_plane_wm->wm[level].plane_en,
14190                                 hw_plane_wm->wm[level].plane_res_b,
14191                                 hw_plane_wm->wm[level].plane_res_l);
14192                 }
14193
14194                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14195                                          &sw_plane_wm->trans_wm)) {
14196                         drm_err(&dev_priv->drm,
14197                                 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14198                                 pipe_name(pipe),
14199                                 sw_plane_wm->trans_wm.plane_en,
14200                                 sw_plane_wm->trans_wm.plane_res_b,
14201                                 sw_plane_wm->trans_wm.plane_res_l,
14202                                 hw_plane_wm->trans_wm.plane_en,
14203                                 hw_plane_wm->trans_wm.plane_res_b,
14204                                 hw_plane_wm->trans_wm.plane_res_l);
14205                 }
14206
14207                 /* DDB */
14208                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14209                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14210
14211                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14212                         drm_err(&dev_priv->drm,
14213                                 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14214                                 pipe_name(pipe),
14215                                 sw_ddb_entry->start, sw_ddb_entry->end,
14216                                 hw_ddb_entry->start, hw_ddb_entry->end);
14217                 }
14218         }
14219
14220         kfree(hw);
14221 }
14222
14223 static void
14224 verify_connector_state(struct intel_atomic_state *state,
14225                        struct intel_crtc *crtc)
14226 {
14227         struct drm_connector *connector;
14228         struct drm_connector_state *new_conn_state;
14229         int i;
14230
14231         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14232                 struct drm_encoder *encoder = connector->encoder;
14233                 struct intel_crtc_state *crtc_state = NULL;
14234
14235                 if (new_conn_state->crtc != &crtc->base)
14236                         continue;
14237
14238                 if (crtc)
14239                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14240
14241                 intel_connector_verify_state(crtc_state, new_conn_state);
14242
14243                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14244                      "connector's atomic encoder doesn't match legacy encoder\n");
14245         }
14246 }
14247
14248 static void
14249 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14250 {
14251         struct intel_encoder *encoder;
14252         struct drm_connector *connector;
14253         struct drm_connector_state *old_conn_state, *new_conn_state;
14254         int i;
14255
14256         for_each_intel_encoder(&dev_priv->drm, encoder) {
14257                 bool enabled = false, found = false;
14258                 enum pipe pipe;
14259
14260                 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14261                             encoder->base.base.id,
14262                             encoder->base.name);
14263
14264                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14265                                                    new_conn_state, i) {
14266                         if (old_conn_state->best_encoder == &encoder->base)
14267                                 found = true;
14268
14269                         if (new_conn_state->best_encoder != &encoder->base)
14270                                 continue;
14271                         found = enabled = true;
14272
14273                         I915_STATE_WARN(new_conn_state->crtc !=
14274                                         encoder->base.crtc,
14275                              "connector's crtc doesn't match encoder crtc\n");
14276                 }
14277
14278                 if (!found)
14279                         continue;
14280
14281                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14282                      "encoder's enabled state mismatch "
14283                      "(expected %i, found %i)\n",
14284                      !!encoder->base.crtc, enabled);
14285
14286                 if (!encoder->base.crtc) {
14287                         bool active;
14288
14289                         active = encoder->get_hw_state(encoder, &pipe);
14290                         I915_STATE_WARN(active,
14291                              "encoder detached but still enabled on pipe %c.\n",
14292                              pipe_name(pipe));
14293                 }
14294         }
14295 }
14296
14297 static void
14298 verify_crtc_state(struct intel_crtc *crtc,
14299                   struct intel_crtc_state *old_crtc_state,
14300                   struct intel_crtc_state *new_crtc_state)
14301 {
14302         struct drm_device *dev = crtc->base.dev;
14303         struct drm_i915_private *dev_priv = to_i915(dev);
14304         struct intel_encoder *encoder;
14305         struct intel_crtc_state *pipe_config = old_crtc_state;
14306         struct drm_atomic_state *state = old_crtc_state->uapi.state;
14307
14308         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14309         intel_crtc_free_hw_state(old_crtc_state);
14310         intel_crtc_state_reset(old_crtc_state, crtc);
14311         old_crtc_state->uapi.state = state;
14312
14313         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14314                     crtc->base.name);
14315
14316         pipe_config->hw.enable = new_crtc_state->hw.enable;
14317
14318         pipe_config->hw.active =
14319                 dev_priv->display.get_pipe_config(crtc, pipe_config);
14320
14321         /* we keep both pipes enabled on 830 */
14322         if (IS_I830(dev_priv) && pipe_config->hw.active)
14323                 pipe_config->hw.active = new_crtc_state->hw.active;
14324
14325         I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14326                         "crtc active state doesn't match with hw state "
14327                         "(expected %i, found %i)\n",
14328                         new_crtc_state->hw.active, pipe_config->hw.active);
14329
14330         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14331                         "transitional active state does not match atomic hw state "
14332                         "(expected %i, found %i)\n",
14333                         new_crtc_state->hw.active, crtc->active);
14334
14335         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14336                 enum pipe pipe;
14337                 bool active;
14338
14339                 active = encoder->get_hw_state(encoder, &pipe);
14340                 I915_STATE_WARN(active != new_crtc_state->hw.active,
14341                                 "[ENCODER:%i] active %i with crtc active %i\n",
14342                                 encoder->base.base.id, active,
14343                                 new_crtc_state->hw.active);
14344
14345                 I915_STATE_WARN(active && crtc->pipe != pipe,
14346                                 "Encoder connected to wrong pipe %c\n",
14347                                 pipe_name(pipe));
14348
14349                 if (active)
14350                         encoder->get_config(encoder, pipe_config);
14351         }
14352
14353         intel_crtc_compute_pixel_rate(pipe_config);
14354
14355         if (!new_crtc_state->hw.active)
14356                 return;
14357
14358         intel_pipe_config_sanity_check(dev_priv, pipe_config);
14359
14360         if (!intel_pipe_config_compare(new_crtc_state,
14361                                        pipe_config, false)) {
14362                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14363                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14364                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14365         }
14366 }
14367
14368 static void
14369 intel_verify_planes(struct intel_atomic_state *state)
14370 {
14371         struct intel_plane *plane;
14372         const struct intel_plane_state *plane_state;
14373         int i;
14374
14375         for_each_new_intel_plane_in_state(state, plane,
14376                                           plane_state, i)
14377                 assert_plane(plane, plane_state->planar_slave ||
14378                              plane_state->uapi.visible);
14379 }
14380
14381 static void
14382 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14383                          struct intel_shared_dpll *pll,
14384                          struct intel_crtc *crtc,
14385                          struct intel_crtc_state *new_crtc_state)
14386 {
14387         struct intel_dpll_hw_state dpll_hw_state;
14388         unsigned int crtc_mask;
14389         bool active;
14390
14391         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14392
14393         drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14394
14395         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14396
14397         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14398                 I915_STATE_WARN(!pll->on && pll->active_mask,
14399                      "pll in active use but not on in sw tracking\n");
14400                 I915_STATE_WARN(pll->on && !pll->active_mask,
14401                      "pll is on but not used by any active crtc\n");
14402                 I915_STATE_WARN(pll->on != active,
14403                      "pll on state mismatch (expected %i, found %i)\n",
14404                      pll->on, active);
14405         }
14406
14407         if (!crtc) {
14408                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14409                                 "more active pll users than references: %x vs %x\n",
14410                                 pll->active_mask, pll->state.crtc_mask);
14411
14412                 return;
14413         }
14414
14415         crtc_mask = drm_crtc_mask(&crtc->base);
14416
14417         if (new_crtc_state->hw.active)
14418                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14419                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14420                                 pipe_name(crtc->pipe), pll->active_mask);
14421         else
14422                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14423                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14424                                 pipe_name(crtc->pipe), pll->active_mask);
14425
14426         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14427                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14428                         crtc_mask, pll->state.crtc_mask);
14429
14430         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14431                                           &dpll_hw_state,
14432                                           sizeof(dpll_hw_state)),
14433                         "pll hw state mismatch\n");
14434 }
14435
14436 static void
14437 verify_shared_dpll_state(struct intel_crtc *crtc,
14438                          struct intel_crtc_state *old_crtc_state,
14439                          struct intel_crtc_state *new_crtc_state)
14440 {
14441         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14442
14443         if (new_crtc_state->shared_dpll)
14444                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14445
14446         if (old_crtc_state->shared_dpll &&
14447             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14448                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14449                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14450
14451                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14452                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14453                                 pipe_name(crtc->pipe));
14454                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14455                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14456                                 pipe_name(crtc->pipe));
14457         }
14458 }
14459
14460 static void
14461 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14462                           struct intel_atomic_state *state,
14463                           struct intel_crtc_state *old_crtc_state,
14464                           struct intel_crtc_state *new_crtc_state)
14465 {
14466         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14467                 return;
14468
14469         verify_wm_state(crtc, new_crtc_state);
14470         verify_connector_state(state, crtc);
14471         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14472         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14473 }
14474
14475 static void
14476 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14477 {
14478         int i;
14479
14480         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14481                 verify_single_dpll_state(dev_priv,
14482                                          &dev_priv->dpll.shared_dplls[i],
14483                                          NULL, NULL);
14484 }
14485
14486 static void
14487 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14488                               struct intel_atomic_state *state)
14489 {
14490         verify_encoder_state(dev_priv, state);
14491         verify_connector_state(state, NULL);
14492         verify_disabled_dpll_state(dev_priv);
14493 }
14494
14495 static void
14496 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14497 {
14498         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14499         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14500         const struct drm_display_mode *adjusted_mode =
14501                 &crtc_state->hw.adjusted_mode;
14502
14503         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14504
14505         crtc->mode_flags = crtc_state->mode_flags;
14506
14507         /*
14508          * The scanline counter increments at the leading edge of hsync.
14509          *
14510          * On most platforms it starts counting from vtotal-1 on the
14511          * first active line. That means the scanline counter value is
14512          * always one less than what we would expect. Ie. just after
14513          * start of vblank, which also occurs at start of hsync (on the
14514          * last active line), the scanline counter will read vblank_start-1.
14515          *
14516          * On gen2 the scanline counter starts counting from 1 instead
14517          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14518          * to keep the value positive), instead of adding one.
14519          *
14520          * On HSW+ the behaviour of the scanline counter depends on the output
14521          * type. For DP ports it behaves like most other platforms, but on HDMI
14522          * there's an extra 1 line difference. So we need to add two instead of
14523          * one to the value.
14524          *
14525          * On VLV/CHV DSI the scanline counter would appear to increment
14526          * approx. 1/3 of a scanline before start of vblank. Unfortunately
14527          * that means we can't tell whether we're in vblank or not while
14528          * we're on that particular line. We must still set scanline_offset
14529          * to 1 so that the vblank timestamps come out correct when we query
14530          * the scanline counter from within the vblank interrupt handler.
14531          * However if queried just before the start of vblank we'll get an
14532          * answer that's slightly in the future.
14533          */
14534         if (IS_GEN(dev_priv, 2)) {
14535                 int vtotal;
14536
14537                 vtotal = adjusted_mode->crtc_vtotal;
14538                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14539                         vtotal /= 2;
14540
14541                 crtc->scanline_offset = vtotal - 1;
14542         } else if (HAS_DDI(dev_priv) &&
14543                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14544                 crtc->scanline_offset = 2;
14545         } else {
14546                 crtc->scanline_offset = 1;
14547         }
14548 }
14549
14550 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14551 {
14552         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14553         struct intel_crtc_state *new_crtc_state;
14554         struct intel_crtc *crtc;
14555         int i;
14556
14557         if (!dev_priv->display.crtc_compute_clock)
14558                 return;
14559
14560         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14561                 if (!needs_modeset(new_crtc_state))
14562                         continue;
14563
14564                 intel_release_shared_dplls(state, crtc);
14565         }
14566 }
14567
14568 /*
14569  * This implements the workaround described in the "notes" section of the mode
14570  * set sequence documentation. When going from no pipes or single pipe to
14571  * multiple pipes, and planes are enabled after the pipe, we need to wait at
14572  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14573  */
14574 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14575 {
14576         struct intel_crtc_state *crtc_state;
14577         struct intel_crtc *crtc;
14578         struct intel_crtc_state *first_crtc_state = NULL;
14579         struct intel_crtc_state *other_crtc_state = NULL;
14580         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14581         int i;
14582
14583         /* look at all crtc's that are going to be enabled in during modeset */
14584         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14585                 if (!crtc_state->hw.active ||
14586                     !needs_modeset(crtc_state))
14587                         continue;
14588
14589                 if (first_crtc_state) {
14590                         other_crtc_state = crtc_state;
14591                         break;
14592                 } else {
14593                         first_crtc_state = crtc_state;
14594                         first_pipe = crtc->pipe;
14595                 }
14596         }
14597
14598         /* No workaround needed? */
14599         if (!first_crtc_state)
14600                 return 0;
14601
14602         /* w/a possibly needed, check how many crtc's are already enabled. */
14603         for_each_intel_crtc(state->base.dev, crtc) {
14604                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14605                 if (IS_ERR(crtc_state))
14606                         return PTR_ERR(crtc_state);
14607
14608                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14609
14610                 if (!crtc_state->hw.active ||
14611                     needs_modeset(crtc_state))
14612                         continue;
14613
14614                 /* 2 or more enabled crtcs means no need for w/a */
14615                 if (enabled_pipe != INVALID_PIPE)
14616                         return 0;
14617
14618                 enabled_pipe = crtc->pipe;
14619         }
14620
14621         if (enabled_pipe != INVALID_PIPE)
14622                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14623         else if (other_crtc_state)
14624                 other_crtc_state->hsw_workaround_pipe = first_pipe;
14625
14626         return 0;
14627 }
14628
14629 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14630                            u8 active_pipes)
14631 {
14632         const struct intel_crtc_state *crtc_state;
14633         struct intel_crtc *crtc;
14634         int i;
14635
14636         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14637                 if (crtc_state->hw.active)
14638                         active_pipes |= BIT(crtc->pipe);
14639                 else
14640                         active_pipes &= ~BIT(crtc->pipe);
14641         }
14642
14643         return active_pipes;
14644 }
14645
14646 static int intel_modeset_checks(struct intel_atomic_state *state)
14647 {
14648         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14649
14650         state->modeset = true;
14651
14652         if (IS_HASWELL(dev_priv))
14653                 return hsw_mode_set_planes_workaround(state);
14654
14655         return 0;
14656 }
14657
14658 /*
14659  * Handle calculation of various watermark data at the end of the atomic check
14660  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14661  * handlers to ensure that all derived state has been updated.
14662  */
14663 static int calc_watermark_data(struct intel_atomic_state *state)
14664 {
14665         struct drm_device *dev = state->base.dev;
14666         struct drm_i915_private *dev_priv = to_i915(dev);
14667
14668         /* Is there platform-specific watermark information to calculate? */
14669         if (dev_priv->display.compute_global_watermarks)
14670                 return dev_priv->display.compute_global_watermarks(state);
14671
14672         return 0;
14673 }
14674
14675 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14676                                      struct intel_crtc_state *new_crtc_state)
14677 {
14678         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14679                 return;
14680
14681         new_crtc_state->uapi.mode_changed = false;
14682         new_crtc_state->update_pipe = true;
14683 }
14684
14685 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14686                                     struct intel_crtc_state *new_crtc_state)
14687 {
14688         /*
14689          * If we're not doing the full modeset we want to
14690          * keep the current M/N values as they may be
14691          * sufficiently different to the computed values
14692          * to cause problems.
14693          *
14694          * FIXME: should really copy more fuzzy state here
14695          */
14696         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14697         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14698         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14699         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14700 }
14701
14702 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14703                                           struct intel_crtc *crtc,
14704                                           u8 plane_ids_mask)
14705 {
14706         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14707         struct intel_plane *plane;
14708
14709         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14710                 struct intel_plane_state *plane_state;
14711
14712                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14713                         continue;
14714
14715                 plane_state = intel_atomic_get_plane_state(state, plane);
14716                 if (IS_ERR(plane_state))
14717                         return PTR_ERR(plane_state);
14718         }
14719
14720         return 0;
14721 }
14722
14723 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14724 {
14725         /* See {hsw,vlv,ivb}_plane_ratio() */
14726         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14727                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14728                 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14729 }
14730
14731 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14732 {
14733         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14734         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14735         struct intel_plane_state *plane_state;
14736         struct intel_plane *plane;
14737         struct intel_crtc *crtc;
14738         int i, ret;
14739
14740         ret = icl_add_linked_planes(state);
14741         if (ret)
14742                 return ret;
14743
14744         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14745                 ret = intel_plane_atomic_check(state, plane);
14746                 if (ret) {
14747                         drm_dbg_atomic(&dev_priv->drm,
14748                                        "[PLANE:%d:%s] atomic driver check failed\n",
14749                                        plane->base.base.id, plane->base.name);
14750                         return ret;
14751                 }
14752         }
14753
14754         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14755                                             new_crtc_state, i) {
14756                 u8 old_active_planes, new_active_planes;
14757
14758                 ret = icl_check_nv12_planes(new_crtc_state);
14759                 if (ret)
14760                         return ret;
14761
14762                 /*
14763                  * On some platforms the number of active planes affects
14764                  * the planes' minimum cdclk calculation. Add such planes
14765                  * to the state before we compute the minimum cdclk.
14766                  */
14767                 if (!active_planes_affects_min_cdclk(dev_priv))
14768                         continue;
14769
14770                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14771                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14772
14773                 /*
14774                  * Not only the number of planes, but if the plane configuration had
14775                  * changed might already mean we need to recompute min CDCLK,
14776                  * because different planes might consume different amount of Dbuf bandwidth
14777                  * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14778                  */
14779                 if (old_active_planes == new_active_planes)
14780                         continue;
14781
14782                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14783                 if (ret)
14784                         return ret;
14785         }
14786
14787         return 0;
14788 }
14789
14790 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14791                                     bool *need_cdclk_calc)
14792 {
14793         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14794         const struct intel_cdclk_state *old_cdclk_state;
14795         const struct intel_cdclk_state *new_cdclk_state;
14796         struct intel_plane_state *plane_state;
14797         struct intel_bw_state *new_bw_state;
14798         struct intel_plane *plane;
14799         int min_cdclk = 0;
14800         enum pipe pipe;
14801         int ret;
14802         int i;
14803         /*
14804          * active_planes bitmask has been updated, and potentially
14805          * affected planes are part of the state. We can now
14806          * compute the minimum cdclk for each plane.
14807          */
14808         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14809                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14810                 if (ret)
14811                         return ret;
14812         }
14813
14814         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14815         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14816
14817         if (new_cdclk_state &&
14818             old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14819                 *need_cdclk_calc = true;
14820
14821         ret = dev_priv->display.bw_calc_min_cdclk(state);
14822         if (ret)
14823                 return ret;
14824
14825         new_bw_state = intel_atomic_get_new_bw_state(state);
14826
14827         if (!new_cdclk_state || !new_bw_state)
14828                 return 0;
14829
14830         for_each_pipe(dev_priv, pipe) {
14831                 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14832
14833                 /*
14834                  * Currently do this change only if we need to increase
14835                  */
14836                 if (new_bw_state->min_cdclk > min_cdclk)
14837                         *need_cdclk_calc = true;
14838         }
14839
14840         return 0;
14841 }
14842
14843 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14844 {
14845         struct intel_crtc_state *crtc_state;
14846         struct intel_crtc *crtc;
14847         int i;
14848
14849         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14850                 int ret = intel_crtc_atomic_check(state, crtc);
14851                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14852                 if (ret) {
14853                         drm_dbg_atomic(&i915->drm,
14854                                        "[CRTC:%d:%s] atomic driver check failed\n",
14855                                        crtc->base.base.id, crtc->base.name);
14856                         return ret;
14857                 }
14858         }
14859
14860         return 0;
14861 }
14862
14863 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14864                                                u8 transcoders)
14865 {
14866         const struct intel_crtc_state *new_crtc_state;
14867         struct intel_crtc *crtc;
14868         int i;
14869
14870         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14871                 if (new_crtc_state->hw.enable &&
14872                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14873                     needs_modeset(new_crtc_state))
14874                         return true;
14875         }
14876
14877         return false;
14878 }
14879
14880 /**
14881  * intel_atomic_check - validate state object
14882  * @dev: drm device
14883  * @_state: state to validate
14884  */
14885 static int intel_atomic_check(struct drm_device *dev,
14886                               struct drm_atomic_state *_state)
14887 {
14888         struct drm_i915_private *dev_priv = to_i915(dev);
14889         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14890         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14891         struct intel_crtc *crtc;
14892         int ret, i;
14893         bool any_ms = false;
14894
14895         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14896                                             new_crtc_state, i) {
14897                 if (new_crtc_state->inherited != old_crtc_state->inherited)
14898                         new_crtc_state->uapi.mode_changed = true;
14899         }
14900
14901         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14902         if (ret)
14903                 goto fail;
14904
14905         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14906                                             new_crtc_state, i) {
14907                 if (!needs_modeset(new_crtc_state)) {
14908                         /* Light copy */
14909                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14910
14911                         continue;
14912                 }
14913
14914                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14915                 if (ret)
14916                         goto fail;
14917
14918                 if (!new_crtc_state->hw.enable)
14919                         continue;
14920
14921                 ret = intel_modeset_pipe_config(new_crtc_state);
14922                 if (ret)
14923                         goto fail;
14924         }
14925
14926         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14927                                             new_crtc_state, i) {
14928                 if (!needs_modeset(new_crtc_state))
14929                         continue;
14930
14931                 ret = intel_modeset_pipe_config_late(new_crtc_state);
14932                 if (ret)
14933                         goto fail;
14934
14935                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14936         }
14937
14938         /**
14939          * Check if fastset is allowed by external dependencies like other
14940          * pipes and transcoders.
14941          *
14942          * Right now it only forces a fullmodeset when the MST master
14943          * transcoder did not changed but the pipe of the master transcoder
14944          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14945          * in case of port synced crtcs, if one of the synced crtcs
14946          * needs a full modeset, all other synced crtcs should be
14947          * forced a full modeset.
14948          */
14949         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14950                 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14951                         continue;
14952
14953                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14954                         enum transcoder master = new_crtc_state->mst_master_transcoder;
14955
14956                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14957                                 new_crtc_state->uapi.mode_changed = true;
14958                                 new_crtc_state->update_pipe = false;
14959                         }
14960                 }
14961
14962                 if (is_trans_port_sync_mode(new_crtc_state)) {
14963                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
14964
14965                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14966                                 trans |= BIT(new_crtc_state->master_transcoder);
14967
14968                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
14969                                 new_crtc_state->uapi.mode_changed = true;
14970                                 new_crtc_state->update_pipe = false;
14971                         }
14972                 }
14973         }
14974
14975         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14976                                             new_crtc_state, i) {
14977                 if (needs_modeset(new_crtc_state)) {
14978                         any_ms = true;
14979                         continue;
14980                 }
14981
14982                 if (!new_crtc_state->update_pipe)
14983                         continue;
14984
14985                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14986         }
14987
14988         if (any_ms && !check_digital_port_conflicts(state)) {
14989                 drm_dbg_kms(&dev_priv->drm,
14990                             "rejecting conflicting digital port configuration\n");
14991                 ret = -EINVAL;
14992                 goto fail;
14993         }
14994
14995         ret = drm_dp_mst_atomic_check(&state->base);
14996         if (ret)
14997                 goto fail;
14998
14999         ret = intel_atomic_check_planes(state);
15000         if (ret)
15001                 goto fail;
15002
15003         /*
15004          * distrust_bios_wm will force a full dbuf recomputation
15005          * but the hardware state will only get updated accordingly
15006          * if state->modeset==true. Hence distrust_bios_wm==true &&
15007          * state->modeset==false is an invalid combination which
15008          * would cause the hardware and software dbuf state to get
15009          * out of sync. We must prevent that.
15010          *
15011          * FIXME clean up this mess and introduce better
15012          * state tracking for dbuf.
15013          */
15014         if (dev_priv->wm.distrust_bios_wm)
15015                 any_ms = true;
15016
15017         intel_fbc_choose_crtc(dev_priv, state);
15018         ret = calc_watermark_data(state);
15019         if (ret)
15020                 goto fail;
15021
15022         ret = intel_bw_atomic_check(state);
15023         if (ret)
15024                 goto fail;
15025
15026         ret = intel_atomic_check_cdclk(state, &any_ms);
15027         if (ret)
15028                 goto fail;
15029
15030         if (any_ms) {
15031                 ret = intel_modeset_checks(state);
15032                 if (ret)
15033                         goto fail;
15034
15035                 ret = intel_modeset_calc_cdclk(state);
15036                 if (ret)
15037                         return ret;
15038
15039                 intel_modeset_clear_plls(state);
15040         }
15041
15042         ret = intel_atomic_check_crtcs(state);
15043         if (ret)
15044                 goto fail;
15045
15046         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15047                                             new_crtc_state, i) {
15048                 if (!needs_modeset(new_crtc_state) &&
15049                     !new_crtc_state->update_pipe)
15050                         continue;
15051
15052                 intel_dump_pipe_config(new_crtc_state, state,
15053                                        needs_modeset(new_crtc_state) ?
15054                                        "[modeset]" : "[fastset]");
15055         }
15056
15057         return 0;
15058
15059  fail:
15060         if (ret == -EDEADLK)
15061                 return ret;
15062
15063         /*
15064          * FIXME would probably be nice to know which crtc specifically
15065          * caused the failure, in cases where we can pinpoint it.
15066          */
15067         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15068                                             new_crtc_state, i)
15069                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15070
15071         return ret;
15072 }
15073
15074 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15075 {
15076         struct intel_crtc_state *crtc_state;
15077         struct intel_crtc *crtc;
15078         int i, ret;
15079
15080         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15081         if (ret < 0)
15082                 return ret;
15083
15084         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15085                 bool mode_changed = needs_modeset(crtc_state);
15086
15087                 if (mode_changed || crtc_state->update_pipe ||
15088                     crtc_state->uapi.color_mgmt_changed) {
15089                         intel_dsb_prepare(crtc_state);
15090                 }
15091         }
15092
15093         return 0;
15094 }
15095
15096 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15097 {
15098         struct drm_device *dev = crtc->base.dev;
15099         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15100
15101         if (!vblank->max_vblank_count)
15102                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15103
15104         return crtc->base.funcs->get_vblank_counter(&crtc->base);
15105 }
15106
15107 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15108                                   struct intel_crtc_state *crtc_state)
15109 {
15110         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15111
15112         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15113                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15114
15115         if (crtc_state->has_pch_encoder) {
15116                 enum pipe pch_transcoder =
15117                         intel_crtc_pch_transcoder(crtc);
15118
15119                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15120         }
15121 }
15122
15123 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15124                                const struct intel_crtc_state *new_crtc_state)
15125 {
15126         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15127         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15128
15129         /*
15130          * Update pipe size and adjust fitter if needed: the reason for this is
15131          * that in compute_mode_changes we check the native mode (not the pfit
15132          * mode) to see if we can flip rather than do a full mode set. In the
15133          * fastboot case, we'll flip, but if we don't update the pipesrc and
15134          * pfit state, we'll end up with a big fb scanned out into the wrong
15135          * sized surface.
15136          */
15137         intel_set_pipe_src_size(new_crtc_state);
15138
15139         /* on skylake this is done by detaching scalers */
15140         if (INTEL_GEN(dev_priv) >= 9) {
15141                 skl_detach_scalers(new_crtc_state);
15142
15143                 if (new_crtc_state->pch_pfit.enabled)
15144                         skl_pfit_enable(new_crtc_state);
15145         } else if (HAS_PCH_SPLIT(dev_priv)) {
15146                 if (new_crtc_state->pch_pfit.enabled)
15147                         ilk_pfit_enable(new_crtc_state);
15148                 else if (old_crtc_state->pch_pfit.enabled)
15149                         ilk_pfit_disable(old_crtc_state);
15150         }
15151
15152         /*
15153          * The register is supposedly single buffered so perhaps
15154          * not 100% correct to do this here. But SKL+ calculate
15155          * this based on the adjust pixel rate so pfit changes do
15156          * affect it and so it must be updated for fastsets.
15157          * HSW/BDW only really need this here for fastboot, after
15158          * that the value should not change without a full modeset.
15159          */
15160         if (INTEL_GEN(dev_priv) >= 9 ||
15161             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15162                 hsw_set_linetime_wm(new_crtc_state);
15163
15164         if (INTEL_GEN(dev_priv) >= 11)
15165                 icl_set_pipe_chicken(crtc);
15166 }
15167
15168 static void commit_pipe_config(struct intel_atomic_state *state,
15169                                struct intel_crtc *crtc)
15170 {
15171         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15172         const struct intel_crtc_state *old_crtc_state =
15173                 intel_atomic_get_old_crtc_state(state, crtc);
15174         const struct intel_crtc_state *new_crtc_state =
15175                 intel_atomic_get_new_crtc_state(state, crtc);
15176         bool modeset = needs_modeset(new_crtc_state);
15177
15178         /*
15179          * During modesets pipe configuration was programmed as the
15180          * CRTC was enabled.
15181          */
15182         if (!modeset) {
15183                 if (new_crtc_state->uapi.color_mgmt_changed ||
15184                     new_crtc_state->update_pipe)
15185                         intel_color_commit(new_crtc_state);
15186
15187                 if (INTEL_GEN(dev_priv) >= 9)
15188                         skl_detach_scalers(new_crtc_state);
15189
15190                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15191                         bdw_set_pipemisc(new_crtc_state);
15192
15193                 if (new_crtc_state->update_pipe)
15194                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
15195
15196                 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15197         }
15198
15199         if (dev_priv->display.atomic_update_watermarks)
15200                 dev_priv->display.atomic_update_watermarks(state, crtc);
15201 }
15202
15203 static void intel_enable_crtc(struct intel_atomic_state *state,
15204                               struct intel_crtc *crtc)
15205 {
15206         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15207         const struct intel_crtc_state *new_crtc_state =
15208                 intel_atomic_get_new_crtc_state(state, crtc);
15209
15210         if (!needs_modeset(new_crtc_state))
15211                 return;
15212
15213         intel_crtc_update_active_timings(new_crtc_state);
15214
15215         dev_priv->display.crtc_enable(state, crtc);
15216
15217         /* vblanks work again, re-enable pipe CRC. */
15218         intel_crtc_enable_pipe_crc(crtc);
15219 }
15220
15221 static void intel_update_crtc(struct intel_atomic_state *state,
15222                               struct intel_crtc *crtc)
15223 {
15224         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15225         const struct intel_crtc_state *old_crtc_state =
15226                 intel_atomic_get_old_crtc_state(state, crtc);
15227         struct intel_crtc_state *new_crtc_state =
15228                 intel_atomic_get_new_crtc_state(state, crtc);
15229         bool modeset = needs_modeset(new_crtc_state);
15230
15231         if (!modeset) {
15232                 if (new_crtc_state->preload_luts &&
15233                     (new_crtc_state->uapi.color_mgmt_changed ||
15234                      new_crtc_state->update_pipe))
15235                         intel_color_load_luts(new_crtc_state);
15236
15237                 intel_pre_plane_update(state, crtc);
15238
15239                 if (new_crtc_state->update_pipe)
15240                         intel_encoders_update_pipe(state, crtc);
15241         }
15242
15243         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15244                 intel_fbc_disable(crtc);
15245         else
15246                 intel_fbc_enable(state, crtc);
15247
15248         /* Perform vblank evasion around commit operation */
15249         intel_pipe_update_start(new_crtc_state);
15250
15251         commit_pipe_config(state, crtc);
15252
15253         if (INTEL_GEN(dev_priv) >= 9)
15254                 skl_update_planes_on_crtc(state, crtc);
15255         else
15256                 i9xx_update_planes_on_crtc(state, crtc);
15257
15258         intel_pipe_update_end(new_crtc_state);
15259
15260         /*
15261          * We usually enable FIFO underrun interrupts as part of the
15262          * CRTC enable sequence during modesets.  But when we inherit a
15263          * valid pipe configuration from the BIOS we need to take care
15264          * of enabling them on the CRTC's first fastset.
15265          */
15266         if (new_crtc_state->update_pipe && !modeset &&
15267             old_crtc_state->inherited)
15268                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15269 }
15270
15271
15272 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15273                                           struct intel_crtc_state *old_crtc_state,
15274                                           struct intel_crtc_state *new_crtc_state,
15275                                           struct intel_crtc *crtc)
15276 {
15277         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15278
15279         intel_crtc_disable_planes(state, crtc);
15280
15281         /*
15282          * We need to disable pipe CRC before disabling the pipe,
15283          * or we race against vblank off.
15284          */
15285         intel_crtc_disable_pipe_crc(crtc);
15286
15287         dev_priv->display.crtc_disable(state, crtc);
15288         crtc->active = false;
15289         intel_fbc_disable(crtc);
15290         intel_disable_shared_dpll(old_crtc_state);
15291
15292         /* FIXME unify this for all platforms */
15293         if (!new_crtc_state->hw.active &&
15294             !HAS_GMCH(dev_priv) &&
15295             dev_priv->display.initial_watermarks)
15296                 dev_priv->display.initial_watermarks(state, crtc);
15297 }
15298
15299 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15300 {
15301         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15302         struct intel_crtc *crtc;
15303         u32 handled = 0;
15304         int i;
15305
15306         /* Only disable port sync and MST slaves */
15307         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15308                                             new_crtc_state, i) {
15309                 if (!needs_modeset(new_crtc_state))
15310                         continue;
15311
15312                 if (!old_crtc_state->hw.active)
15313                         continue;
15314
15315                 /* In case of Transcoder port Sync master slave CRTCs can be
15316                  * assigned in any order and we need to make sure that
15317                  * slave CRTCs are disabled first and then master CRTC since
15318                  * Slave vblanks are masked till Master Vblanks.
15319                  */
15320                 if (!is_trans_port_sync_slave(old_crtc_state) &&
15321                     !intel_dp_mst_is_slave_trans(old_crtc_state))
15322                         continue;
15323
15324                 intel_pre_plane_update(state, crtc);
15325                 intel_old_crtc_state_disables(state, old_crtc_state,
15326                                               new_crtc_state, crtc);
15327                 handled |= BIT(crtc->pipe);
15328         }
15329
15330         /* Disable everything else left on */
15331         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15332                                             new_crtc_state, i) {
15333                 if (!needs_modeset(new_crtc_state) ||
15334                     (handled & BIT(crtc->pipe)))
15335                         continue;
15336
15337                 intel_pre_plane_update(state, crtc);
15338                 if (old_crtc_state->hw.active)
15339                         intel_old_crtc_state_disables(state, old_crtc_state,
15340                                                       new_crtc_state, crtc);
15341         }
15342 }
15343
15344 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15345 {
15346         struct intel_crtc_state *new_crtc_state;
15347         struct intel_crtc *crtc;
15348         int i;
15349
15350         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15351                 if (!new_crtc_state->hw.active)
15352                         continue;
15353
15354                 intel_enable_crtc(state, crtc);
15355                 intel_update_crtc(state, crtc);
15356         }
15357 }
15358
15359 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15360 {
15361         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15362         struct intel_crtc *crtc;
15363         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15364         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15365         u8 update_pipes = 0, modeset_pipes = 0;
15366         int i;
15367
15368         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15369                 enum pipe pipe = crtc->pipe;
15370
15371                 if (!new_crtc_state->hw.active)
15372                         continue;
15373
15374                 /* ignore allocations for crtc's that have been turned off. */
15375                 if (!needs_modeset(new_crtc_state)) {
15376                         entries[pipe] = old_crtc_state->wm.skl.ddb;
15377                         update_pipes |= BIT(pipe);
15378                 } else {
15379                         modeset_pipes |= BIT(pipe);
15380                 }
15381         }
15382
15383         /*
15384          * Whenever the number of active pipes changes, we need to make sure we
15385          * update the pipes in the right order so that their ddb allocations
15386          * never overlap with each other between CRTC updates. Otherwise we'll
15387          * cause pipe underruns and other bad stuff.
15388          *
15389          * So first lets enable all pipes that do not need a fullmodeset as
15390          * those don't have any external dependency.
15391          */
15392         while (update_pipes) {
15393                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15394                                                     new_crtc_state, i) {
15395                         enum pipe pipe = crtc->pipe;
15396
15397                         if ((update_pipes & BIT(pipe)) == 0)
15398                                 continue;
15399
15400                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15401                                                         entries, I915_MAX_PIPES, pipe))
15402                                 continue;
15403
15404                         entries[pipe] = new_crtc_state->wm.skl.ddb;
15405                         update_pipes &= ~BIT(pipe);
15406
15407                         intel_update_crtc(state, crtc);
15408
15409                         /*
15410                          * If this is an already active pipe, it's DDB changed,
15411                          * and this isn't the last pipe that needs updating
15412                          * then we need to wait for a vblank to pass for the
15413                          * new ddb allocation to take effect.
15414                          */
15415                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15416                                                  &old_crtc_state->wm.skl.ddb) &&
15417                             (update_pipes | modeset_pipes))
15418                                 intel_wait_for_vblank(dev_priv, pipe);
15419                 }
15420         }
15421
15422         update_pipes = modeset_pipes;
15423
15424         /*
15425          * Enable all pipes that needs a modeset and do not depends on other
15426          * pipes
15427          */
15428         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15429                 enum pipe pipe = crtc->pipe;
15430
15431                 if ((modeset_pipes & BIT(pipe)) == 0)
15432                         continue;
15433
15434                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15435                     is_trans_port_sync_master(new_crtc_state))
15436                         continue;
15437
15438                 modeset_pipes &= ~BIT(pipe);
15439
15440                 intel_enable_crtc(state, crtc);
15441         }
15442
15443         /*
15444          * Then we enable all remaining pipes that depend on other
15445          * pipes: MST slaves and port sync masters.
15446          */
15447         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15448                 enum pipe pipe = crtc->pipe;
15449
15450                 if ((modeset_pipes & BIT(pipe)) == 0)
15451                         continue;
15452
15453                 modeset_pipes &= ~BIT(pipe);
15454
15455                 intel_enable_crtc(state, crtc);
15456         }
15457
15458         /*
15459          * Finally we do the plane updates/etc. for all pipes that got enabled.
15460          */
15461         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15462                 enum pipe pipe = crtc->pipe;
15463
15464                 if ((update_pipes & BIT(pipe)) == 0)
15465                         continue;
15466
15467                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15468                                                                         entries, I915_MAX_PIPES, pipe));
15469
15470                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15471                 update_pipes &= ~BIT(pipe);
15472
15473                 intel_update_crtc(state, crtc);
15474         }
15475
15476         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15477         drm_WARN_ON(&dev_priv->drm, update_pipes);
15478 }
15479
15480 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15481 {
15482         struct intel_atomic_state *state, *next;
15483         struct llist_node *freed;
15484
15485         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15486         llist_for_each_entry_safe(state, next, freed, freed)
15487                 drm_atomic_state_put(&state->base);
15488 }
15489
15490 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15491 {
15492         struct drm_i915_private *dev_priv =
15493                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15494
15495         intel_atomic_helper_free_state(dev_priv);
15496 }
15497
15498 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15499 {
15500         struct wait_queue_entry wait_fence, wait_reset;
15501         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15502
15503         init_wait_entry(&wait_fence, 0);
15504         init_wait_entry(&wait_reset, 0);
15505         for (;;) {
15506                 prepare_to_wait(&intel_state->commit_ready.wait,
15507                                 &wait_fence, TASK_UNINTERRUPTIBLE);
15508                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15509                                               I915_RESET_MODESET),
15510                                 &wait_reset, TASK_UNINTERRUPTIBLE);
15511
15512
15513                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15514                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15515                         break;
15516
15517                 schedule();
15518         }
15519         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15520         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15521                                   I915_RESET_MODESET),
15522                     &wait_reset);
15523 }
15524
15525 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15526 {
15527         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15528         struct intel_crtc *crtc;
15529         int i;
15530
15531         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15532                                             new_crtc_state, i)
15533                 intel_dsb_cleanup(old_crtc_state);
15534 }
15535
15536 static void intel_atomic_cleanup_work(struct work_struct *work)
15537 {
15538         struct intel_atomic_state *state =
15539                 container_of(work, struct intel_atomic_state, base.commit_work);
15540         struct drm_i915_private *i915 = to_i915(state->base.dev);
15541
15542         intel_cleanup_dsbs(state);
15543         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15544         drm_atomic_helper_commit_cleanup_done(&state->base);
15545         drm_atomic_state_put(&state->base);
15546
15547         intel_atomic_helper_free_state(i915);
15548 }
15549
15550 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15551 {
15552         struct drm_device *dev = state->base.dev;
15553         struct drm_i915_private *dev_priv = to_i915(dev);
15554         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15555         struct intel_crtc *crtc;
15556         u64 put_domains[I915_MAX_PIPES] = {};
15557         intel_wakeref_t wakeref = 0;
15558         int i;
15559
15560         intel_atomic_commit_fence_wait(state);
15561
15562         drm_atomic_helper_wait_for_dependencies(&state->base);
15563
15564         if (state->modeset)
15565                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15566
15567         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15568                                             new_crtc_state, i) {
15569                 if (needs_modeset(new_crtc_state) ||
15570                     new_crtc_state->update_pipe) {
15571
15572                         put_domains[crtc->pipe] =
15573                                 modeset_get_crtc_power_domains(new_crtc_state);
15574                 }
15575         }
15576
15577         intel_commit_modeset_disables(state);
15578
15579         /* FIXME: Eventually get rid of our crtc->config pointer */
15580         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15581                 crtc->config = new_crtc_state;
15582
15583         if (state->modeset) {
15584                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15585
15586                 intel_set_cdclk_pre_plane_update(state);
15587
15588                 intel_modeset_verify_disabled(dev_priv, state);
15589         }
15590
15591         intel_sagv_pre_plane_update(state);
15592
15593         /* Complete the events for pipes that have now been disabled */
15594         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15595                 bool modeset = needs_modeset(new_crtc_state);
15596
15597                 /* Complete events for now disable pipes here. */
15598                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15599                         spin_lock_irq(&dev->event_lock);
15600                         drm_crtc_send_vblank_event(&crtc->base,
15601                                                    new_crtc_state->uapi.event);
15602                         spin_unlock_irq(&dev->event_lock);
15603
15604                         new_crtc_state->uapi.event = NULL;
15605                 }
15606         }
15607
15608         if (state->modeset)
15609                 intel_encoders_update_prepare(state);
15610
15611         intel_dbuf_pre_plane_update(state);
15612
15613         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15614         dev_priv->display.commit_modeset_enables(state);
15615
15616         if (state->modeset) {
15617                 intel_encoders_update_complete(state);
15618
15619                 intel_set_cdclk_post_plane_update(state);
15620         }
15621
15622         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15623          * already, but still need the state for the delayed optimization. To
15624          * fix this:
15625          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15626          * - schedule that vblank worker _before_ calling hw_done
15627          * - at the start of commit_tail, cancel it _synchrously
15628          * - switch over to the vblank wait helper in the core after that since
15629          *   we don't need out special handling any more.
15630          */
15631         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15632
15633         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15634                 if (new_crtc_state->hw.active &&
15635                     !needs_modeset(new_crtc_state) &&
15636                     !new_crtc_state->preload_luts &&
15637                     (new_crtc_state->uapi.color_mgmt_changed ||
15638                      new_crtc_state->update_pipe))
15639                         intel_color_load_luts(new_crtc_state);
15640         }
15641
15642         /*
15643          * Now that the vblank has passed, we can go ahead and program the
15644          * optimal watermarks on platforms that need two-step watermark
15645          * programming.
15646          *
15647          * TODO: Move this (and other cleanup) to an async worker eventually.
15648          */
15649         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15650                                             new_crtc_state, i) {
15651                 /*
15652                  * Gen2 reports pipe underruns whenever all planes are disabled.
15653                  * So re-enable underrun reporting after some planes get enabled.
15654                  *
15655                  * We do this before .optimize_watermarks() so that we have a
15656                  * chance of catching underruns with the intermediate watermarks
15657                  * vs. the new plane configuration.
15658                  */
15659                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15660                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15661
15662                 if (dev_priv->display.optimize_watermarks)
15663                         dev_priv->display.optimize_watermarks(state, crtc);
15664         }
15665
15666         intel_dbuf_post_plane_update(state);
15667
15668         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15669                 intel_post_plane_update(state, crtc);
15670
15671                 if (put_domains[i])
15672                         modeset_put_power_domains(dev_priv, put_domains[i]);
15673
15674                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15675
15676                 /*
15677                  * DSB cleanup is done in cleanup_work aligning with framebuffer
15678                  * cleanup. So copy and reset the dsb structure to sync with
15679                  * commit_done and later do dsb cleanup in cleanup_work.
15680                  */
15681                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15682         }
15683
15684         /* Underruns don't always raise interrupts, so check manually */
15685         intel_check_cpu_fifo_underruns(dev_priv);
15686         intel_check_pch_fifo_underruns(dev_priv);
15687
15688         if (state->modeset)
15689                 intel_verify_planes(state);
15690
15691         intel_sagv_post_plane_update(state);
15692
15693         drm_atomic_helper_commit_hw_done(&state->base);
15694
15695         if (state->modeset) {
15696                 /* As one of the primary mmio accessors, KMS has a high
15697                  * likelihood of triggering bugs in unclaimed access. After we
15698                  * finish modesetting, see if an error has been flagged, and if
15699                  * so enable debugging for the next modeset - and hope we catch
15700                  * the culprit.
15701                  */
15702                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15703                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15704         }
15705         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15706
15707         /*
15708          * Defer the cleanup of the old state to a separate worker to not
15709          * impede the current task (userspace for blocking modesets) that
15710          * are executed inline. For out-of-line asynchronous modesets/flips,
15711          * deferring to a new worker seems overkill, but we would place a
15712          * schedule point (cond_resched()) here anyway to keep latencies
15713          * down.
15714          */
15715         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15716         queue_work(system_highpri_wq, &state->base.commit_work);
15717 }
15718
15719 static void intel_atomic_commit_work(struct work_struct *work)
15720 {
15721         struct intel_atomic_state *state =
15722                 container_of(work, struct intel_atomic_state, base.commit_work);
15723
15724         intel_atomic_commit_tail(state);
15725 }
15726
15727 static int __i915_sw_fence_call
15728 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15729                           enum i915_sw_fence_notify notify)
15730 {
15731         struct intel_atomic_state *state =
15732                 container_of(fence, struct intel_atomic_state, commit_ready);
15733
15734         switch (notify) {
15735         case FENCE_COMPLETE:
15736                 /* we do blocking waits in the worker, nothing to do here */
15737                 break;
15738         case FENCE_FREE:
15739                 {
15740                         struct intel_atomic_helper *helper =
15741                                 &to_i915(state->base.dev)->atomic_helper;
15742
15743                         if (llist_add(&state->freed, &helper->free_list))
15744                                 schedule_work(&helper->free_work);
15745                         break;
15746                 }
15747         }
15748
15749         return NOTIFY_DONE;
15750 }
15751
15752 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15753 {
15754         struct intel_plane_state *old_plane_state, *new_plane_state;
15755         struct intel_plane *plane;
15756         int i;
15757
15758         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15759                                              new_plane_state, i)
15760                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15761                                         to_intel_frontbuffer(new_plane_state->hw.fb),
15762                                         plane->frontbuffer_bit);
15763 }
15764
15765 static int intel_atomic_commit(struct drm_device *dev,
15766                                struct drm_atomic_state *_state,
15767                                bool nonblock)
15768 {
15769         struct intel_atomic_state *state = to_intel_atomic_state(_state);
15770         struct drm_i915_private *dev_priv = to_i915(dev);
15771         int ret = 0;
15772
15773         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15774
15775         drm_atomic_state_get(&state->base);
15776         i915_sw_fence_init(&state->commit_ready,
15777                            intel_atomic_commit_ready);
15778
15779         /*
15780          * The intel_legacy_cursor_update() fast path takes care
15781          * of avoiding the vblank waits for simple cursor
15782          * movement and flips. For cursor on/off and size changes,
15783          * we want to perform the vblank waits so that watermark
15784          * updates happen during the correct frames. Gen9+ have
15785          * double buffered watermarks and so shouldn't need this.
15786          *
15787          * Unset state->legacy_cursor_update before the call to
15788          * drm_atomic_helper_setup_commit() because otherwise
15789          * drm_atomic_helper_wait_for_flip_done() is a noop and
15790          * we get FIFO underruns because we didn't wait
15791          * for vblank.
15792          *
15793          * FIXME doing watermarks and fb cleanup from a vblank worker
15794          * (assuming we had any) would solve these problems.
15795          */
15796         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15797                 struct intel_crtc_state *new_crtc_state;
15798                 struct intel_crtc *crtc;
15799                 int i;
15800
15801                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15802                         if (new_crtc_state->wm.need_postvbl_update ||
15803                             new_crtc_state->update_wm_post)
15804                                 state->base.legacy_cursor_update = false;
15805         }
15806
15807         ret = intel_atomic_prepare_commit(state);
15808         if (ret) {
15809                 drm_dbg_atomic(&dev_priv->drm,
15810                                "Preparing state failed with %i\n", ret);
15811                 i915_sw_fence_commit(&state->commit_ready);
15812                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15813                 return ret;
15814         }
15815
15816         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15817         if (!ret)
15818                 ret = drm_atomic_helper_swap_state(&state->base, true);
15819         if (!ret)
15820                 intel_atomic_swap_global_state(state);
15821
15822         if (ret) {
15823                 struct intel_crtc_state *new_crtc_state;
15824                 struct intel_crtc *crtc;
15825                 int i;
15826
15827                 i915_sw_fence_commit(&state->commit_ready);
15828
15829                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15830                         intel_dsb_cleanup(new_crtc_state);
15831
15832                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15833                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15834                 return ret;
15835         }
15836         dev_priv->wm.distrust_bios_wm = false;
15837         intel_shared_dpll_swap_state(state);
15838         intel_atomic_track_fbs(state);
15839
15840         drm_atomic_state_get(&state->base);
15841         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15842
15843         i915_sw_fence_commit(&state->commit_ready);
15844         if (nonblock && state->modeset) {
15845                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15846         } else if (nonblock) {
15847                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15848         } else {
15849                 if (state->modeset)
15850                         flush_workqueue(dev_priv->modeset_wq);
15851                 intel_atomic_commit_tail(state);
15852         }
15853
15854         return 0;
15855 }
15856
15857 struct wait_rps_boost {
15858         struct wait_queue_entry wait;
15859
15860         struct drm_crtc *crtc;
15861         struct i915_request *request;
15862 };
15863
15864 static int do_rps_boost(struct wait_queue_entry *_wait,
15865                         unsigned mode, int sync, void *key)
15866 {
15867         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15868         struct i915_request *rq = wait->request;
15869
15870         /*
15871          * If we missed the vblank, but the request is already running it
15872          * is reasonable to assume that it will complete before the next
15873          * vblank without our intervention, so leave RPS alone.
15874          */
15875         if (!i915_request_started(rq))
15876                 intel_rps_boost(rq);
15877         i915_request_put(rq);
15878
15879         drm_crtc_vblank_put(wait->crtc);
15880
15881         list_del(&wait->wait.entry);
15882         kfree(wait);
15883         return 1;
15884 }
15885
15886 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15887                                        struct dma_fence *fence)
15888 {
15889         struct wait_rps_boost *wait;
15890
15891         if (!dma_fence_is_i915(fence))
15892                 return;
15893
15894         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15895                 return;
15896
15897         if (drm_crtc_vblank_get(crtc))
15898                 return;
15899
15900         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15901         if (!wait) {
15902                 drm_crtc_vblank_put(crtc);
15903                 return;
15904         }
15905
15906         wait->request = to_request(dma_fence_get(fence));
15907         wait->crtc = crtc;
15908
15909         wait->wait.func = do_rps_boost;
15910         wait->wait.flags = 0;
15911
15912         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15913 }
15914
15915 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15916 {
15917         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15918         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15919         struct drm_framebuffer *fb = plane_state->hw.fb;
15920         struct i915_vma *vma;
15921
15922         if (plane->id == PLANE_CURSOR &&
15923             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15924                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15925                 const int align = intel_cursor_alignment(dev_priv);
15926                 int err;
15927
15928                 err = i915_gem_object_attach_phys(obj, align);
15929                 if (err)
15930                         return err;
15931         }
15932
15933         vma = intel_pin_and_fence_fb_obj(fb,
15934                                          &plane_state->view,
15935                                          intel_plane_uses_fence(plane_state),
15936                                          &plane_state->flags);
15937         if (IS_ERR(vma))
15938                 return PTR_ERR(vma);
15939
15940         plane_state->vma = vma;
15941
15942         return 0;
15943 }
15944
15945 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15946 {
15947         struct i915_vma *vma;
15948
15949         vma = fetch_and_zero(&old_plane_state->vma);
15950         if (vma)
15951                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15952 }
15953
15954 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15955 {
15956         struct i915_sched_attr attr = {
15957                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15958         };
15959
15960         i915_gem_object_wait_priority(obj, 0, &attr);
15961 }
15962
15963 /**
15964  * intel_prepare_plane_fb - Prepare fb for usage on plane
15965  * @_plane: drm plane to prepare for
15966  * @_new_plane_state: the plane state being prepared
15967  *
15968  * Prepares a framebuffer for usage on a display plane.  Generally this
15969  * involves pinning the underlying object and updating the frontbuffer tracking
15970  * bits.  Some older platforms need special physical address handling for
15971  * cursor planes.
15972  *
15973  * Returns 0 on success, negative error code on failure.
15974  */
15975 int
15976 intel_prepare_plane_fb(struct drm_plane *_plane,
15977                        struct drm_plane_state *_new_plane_state)
15978 {
15979         struct intel_plane *plane = to_intel_plane(_plane);
15980         struct intel_plane_state *new_plane_state =
15981                 to_intel_plane_state(_new_plane_state);
15982         struct intel_atomic_state *state =
15983                 to_intel_atomic_state(new_plane_state->uapi.state);
15984         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15985         const struct intel_plane_state *old_plane_state =
15986                 intel_atomic_get_old_plane_state(state, plane);
15987         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15988         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15989         int ret;
15990
15991         if (old_obj) {
15992                 const struct intel_crtc_state *crtc_state =
15993                         intel_atomic_get_new_crtc_state(state,
15994                                                         to_intel_crtc(old_plane_state->hw.crtc));
15995
15996                 /* Big Hammer, we also need to ensure that any pending
15997                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15998                  * current scanout is retired before unpinning the old
15999                  * framebuffer. Note that we rely on userspace rendering
16000                  * into the buffer attached to the pipe they are waiting
16001                  * on. If not, userspace generates a GPU hang with IPEHR
16002                  * point to the MI_WAIT_FOR_EVENT.
16003                  *
16004                  * This should only fail upon a hung GPU, in which case we
16005                  * can safely continue.
16006                  */
16007                 if (needs_modeset(crtc_state)) {
16008                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
16009                                                               old_obj->base.resv, NULL,
16010                                                               false, 0,
16011                                                               GFP_KERNEL);
16012                         if (ret < 0)
16013                                 return ret;
16014                 }
16015         }
16016
16017         if (new_plane_state->uapi.fence) { /* explicit fencing */
16018                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16019                                                     new_plane_state->uapi.fence,
16020                                                     i915_fence_timeout(dev_priv),
16021                                                     GFP_KERNEL);
16022                 if (ret < 0)
16023                         return ret;
16024         }
16025
16026         if (!obj)
16027                 return 0;
16028
16029         ret = i915_gem_object_pin_pages(obj);
16030         if (ret)
16031                 return ret;
16032
16033         ret = intel_plane_pin_fb(new_plane_state);
16034
16035         i915_gem_object_unpin_pages(obj);
16036         if (ret)
16037                 return ret;
16038
16039         fb_obj_bump_render_priority(obj);
16040         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16041
16042         if (!new_plane_state->uapi.fence) { /* implicit fencing */
16043                 struct dma_fence *fence;
16044
16045                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16046                                                       obj->base.resv, NULL,
16047                                                       false,
16048                                                       i915_fence_timeout(dev_priv),
16049                                                       GFP_KERNEL);
16050                 if (ret < 0)
16051                         goto unpin_fb;
16052
16053                 fence = dma_resv_get_excl_rcu(obj->base.resv);
16054                 if (fence) {
16055                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16056                                                    fence);
16057                         dma_fence_put(fence);
16058                 }
16059         } else {
16060                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16061                                            new_plane_state->uapi.fence);
16062         }
16063
16064         /*
16065          * We declare pageflips to be interactive and so merit a small bias
16066          * towards upclocking to deliver the frame on time. By only changing
16067          * the RPS thresholds to sample more regularly and aim for higher
16068          * clocks we can hopefully deliver low power workloads (like kodi)
16069          * that are not quite steady state without resorting to forcing
16070          * maximum clocks following a vblank miss (see do_rps_boost()).
16071          */
16072         if (!state->rps_interactive) {
16073                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16074                 state->rps_interactive = true;
16075         }
16076
16077         return 0;
16078
16079 unpin_fb:
16080         intel_plane_unpin_fb(new_plane_state);
16081
16082         return ret;
16083 }
16084
16085 /**
16086  * intel_cleanup_plane_fb - Cleans up an fb after plane use
16087  * @plane: drm plane to clean up for
16088  * @_old_plane_state: the state from the previous modeset
16089  *
16090  * Cleans up a framebuffer that has just been removed from a plane.
16091  */
16092 void
16093 intel_cleanup_plane_fb(struct drm_plane *plane,
16094                        struct drm_plane_state *_old_plane_state)
16095 {
16096         struct intel_plane_state *old_plane_state =
16097                 to_intel_plane_state(_old_plane_state);
16098         struct intel_atomic_state *state =
16099                 to_intel_atomic_state(old_plane_state->uapi.state);
16100         struct drm_i915_private *dev_priv = to_i915(plane->dev);
16101         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16102
16103         if (!obj)
16104                 return;
16105
16106         if (state->rps_interactive) {
16107                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16108                 state->rps_interactive = false;
16109         }
16110
16111         /* Should only be called after a successful intel_prepare_plane_fb()! */
16112         intel_plane_unpin_fb(old_plane_state);
16113 }
16114
16115 /**
16116  * intel_plane_destroy - destroy a plane
16117  * @plane: plane to destroy
16118  *
16119  * Common destruction function for all types of planes (primary, cursor,
16120  * sprite).
16121  */
16122 void intel_plane_destroy(struct drm_plane *plane)
16123 {
16124         drm_plane_cleanup(plane);
16125         kfree(to_intel_plane(plane));
16126 }
16127
16128 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16129                                             u32 format, u64 modifier)
16130 {
16131         switch (modifier) {
16132         case DRM_FORMAT_MOD_LINEAR:
16133         case I915_FORMAT_MOD_X_TILED:
16134                 break;
16135         default:
16136                 return false;
16137         }
16138
16139         switch (format) {
16140         case DRM_FORMAT_C8:
16141         case DRM_FORMAT_RGB565:
16142         case DRM_FORMAT_XRGB1555:
16143         case DRM_FORMAT_XRGB8888:
16144                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16145                         modifier == I915_FORMAT_MOD_X_TILED;
16146         default:
16147                 return false;
16148         }
16149 }
16150
16151 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16152                                             u32 format, u64 modifier)
16153 {
16154         switch (modifier) {
16155         case DRM_FORMAT_MOD_LINEAR:
16156         case I915_FORMAT_MOD_X_TILED:
16157                 break;
16158         default:
16159                 return false;
16160         }
16161
16162         switch (format) {
16163         case DRM_FORMAT_C8:
16164         case DRM_FORMAT_RGB565:
16165         case DRM_FORMAT_XRGB8888:
16166         case DRM_FORMAT_XBGR8888:
16167         case DRM_FORMAT_ARGB8888:
16168         case DRM_FORMAT_ABGR8888:
16169         case DRM_FORMAT_XRGB2101010:
16170         case DRM_FORMAT_XBGR2101010:
16171         case DRM_FORMAT_ARGB2101010:
16172         case DRM_FORMAT_ABGR2101010:
16173         case DRM_FORMAT_XBGR16161616F:
16174                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16175                         modifier == I915_FORMAT_MOD_X_TILED;
16176         default:
16177                 return false;
16178         }
16179 }
16180
16181 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16182                                               u32 format, u64 modifier)
16183 {
16184         return modifier == DRM_FORMAT_MOD_LINEAR &&
16185                 format == DRM_FORMAT_ARGB8888;
16186 }
16187
16188 static const struct drm_plane_funcs i965_plane_funcs = {
16189         .update_plane = drm_atomic_helper_update_plane,
16190         .disable_plane = drm_atomic_helper_disable_plane,
16191         .destroy = intel_plane_destroy,
16192         .atomic_duplicate_state = intel_plane_duplicate_state,
16193         .atomic_destroy_state = intel_plane_destroy_state,
16194         .format_mod_supported = i965_plane_format_mod_supported,
16195 };
16196
16197 static const struct drm_plane_funcs i8xx_plane_funcs = {
16198         .update_plane = drm_atomic_helper_update_plane,
16199         .disable_plane = drm_atomic_helper_disable_plane,
16200         .destroy = intel_plane_destroy,
16201         .atomic_duplicate_state = intel_plane_duplicate_state,
16202         .atomic_destroy_state = intel_plane_destroy_state,
16203         .format_mod_supported = i8xx_plane_format_mod_supported,
16204 };
16205
16206 static int
16207 intel_legacy_cursor_update(struct drm_plane *_plane,
16208                            struct drm_crtc *_crtc,
16209                            struct drm_framebuffer *fb,
16210                            int crtc_x, int crtc_y,
16211                            unsigned int crtc_w, unsigned int crtc_h,
16212                            u32 src_x, u32 src_y,
16213                            u32 src_w, u32 src_h,
16214                            struct drm_modeset_acquire_ctx *ctx)
16215 {
16216         struct intel_plane *plane = to_intel_plane(_plane);
16217         struct intel_crtc *crtc = to_intel_crtc(_crtc);
16218         struct intel_plane_state *old_plane_state =
16219                 to_intel_plane_state(plane->base.state);
16220         struct intel_plane_state *new_plane_state;
16221         struct intel_crtc_state *crtc_state =
16222                 to_intel_crtc_state(crtc->base.state);
16223         struct intel_crtc_state *new_crtc_state;
16224         int ret;
16225
16226         /*
16227          * When crtc is inactive or there is a modeset pending,
16228          * wait for it to complete in the slowpath
16229          */
16230         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16231             crtc_state->update_pipe)
16232                 goto slow;
16233
16234         /*
16235          * Don't do an async update if there is an outstanding commit modifying
16236          * the plane.  This prevents our async update's changes from getting
16237          * overridden by a previous synchronous update's state.
16238          */
16239         if (old_plane_state->uapi.commit &&
16240             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16241                 goto slow;
16242
16243         /*
16244          * If any parameters change that may affect watermarks,
16245          * take the slowpath. Only changing fb or position should be
16246          * in the fastpath.
16247          */
16248         if (old_plane_state->uapi.crtc != &crtc->base ||
16249             old_plane_state->uapi.src_w != src_w ||
16250             old_plane_state->uapi.src_h != src_h ||
16251             old_plane_state->uapi.crtc_w != crtc_w ||
16252             old_plane_state->uapi.crtc_h != crtc_h ||
16253             !old_plane_state->uapi.fb != !fb)
16254                 goto slow;
16255
16256         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16257         if (!new_plane_state)
16258                 return -ENOMEM;
16259
16260         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16261         if (!new_crtc_state) {
16262                 ret = -ENOMEM;
16263                 goto out_free;
16264         }
16265
16266         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16267
16268         new_plane_state->uapi.src_x = src_x;
16269         new_plane_state->uapi.src_y = src_y;
16270         new_plane_state->uapi.src_w = src_w;
16271         new_plane_state->uapi.src_h = src_h;
16272         new_plane_state->uapi.crtc_x = crtc_x;
16273         new_plane_state->uapi.crtc_y = crtc_y;
16274         new_plane_state->uapi.crtc_w = crtc_w;
16275         new_plane_state->uapi.crtc_h = crtc_h;
16276
16277         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16278
16279         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16280                                                   old_plane_state, new_plane_state);
16281         if (ret)
16282                 goto out_free;
16283
16284         ret = intel_plane_pin_fb(new_plane_state);
16285         if (ret)
16286                 goto out_free;
16287
16288         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16289                                 ORIGIN_FLIP);
16290         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16291                                 to_intel_frontbuffer(new_plane_state->hw.fb),
16292                                 plane->frontbuffer_bit);
16293
16294         /* Swap plane state */
16295         plane->base.state = &new_plane_state->uapi;
16296
16297         /*
16298          * We cannot swap crtc_state as it may be in use by an atomic commit or
16299          * page flip that's running simultaneously. If we swap crtc_state and
16300          * destroy the old state, we will cause a use-after-free there.
16301          *
16302          * Only update active_planes, which is needed for our internal
16303          * bookkeeping. Either value will do the right thing when updating
16304          * planes atomically. If the cursor was part of the atomic update then
16305          * we would have taken the slowpath.
16306          */
16307         crtc_state->active_planes = new_crtc_state->active_planes;
16308
16309         if (new_plane_state->uapi.visible)
16310                 intel_update_plane(plane, crtc_state, new_plane_state);
16311         else
16312                 intel_disable_plane(plane, crtc_state);
16313
16314         intel_plane_unpin_fb(old_plane_state);
16315
16316 out_free:
16317         if (new_crtc_state)
16318                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16319         if (ret)
16320                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16321         else
16322                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16323         return ret;
16324
16325 slow:
16326         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16327                                               crtc_x, crtc_y, crtc_w, crtc_h,
16328                                               src_x, src_y, src_w, src_h, ctx);
16329 }
16330
16331 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16332         .update_plane = intel_legacy_cursor_update,
16333         .disable_plane = drm_atomic_helper_disable_plane,
16334         .destroy = intel_plane_destroy,
16335         .atomic_duplicate_state = intel_plane_duplicate_state,
16336         .atomic_destroy_state = intel_plane_destroy_state,
16337         .format_mod_supported = intel_cursor_format_mod_supported,
16338 };
16339
16340 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16341                                enum i9xx_plane_id i9xx_plane)
16342 {
16343         if (!HAS_FBC(dev_priv))
16344                 return false;
16345
16346         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16347                 return i9xx_plane == PLANE_A; /* tied to pipe A */
16348         else if (IS_IVYBRIDGE(dev_priv))
16349                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16350                         i9xx_plane == PLANE_C;
16351         else if (INTEL_GEN(dev_priv) >= 4)
16352                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16353         else
16354                 return i9xx_plane == PLANE_A;
16355 }
16356
16357 static struct intel_plane *
16358 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16359 {
16360         struct intel_plane *plane;
16361         const struct drm_plane_funcs *plane_funcs;
16362         unsigned int supported_rotations;
16363         const u32 *formats;
16364         int num_formats;
16365         int ret, zpos;
16366
16367         if (INTEL_GEN(dev_priv) >= 9)
16368                 return skl_universal_plane_create(dev_priv, pipe,
16369                                                   PLANE_PRIMARY);
16370
16371         plane = intel_plane_alloc();
16372         if (IS_ERR(plane))
16373                 return plane;
16374
16375         plane->pipe = pipe;
16376         /*
16377          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16378          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16379          */
16380         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16381             INTEL_NUM_PIPES(dev_priv) == 2)
16382                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16383         else
16384                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16385         plane->id = PLANE_PRIMARY;
16386         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16387
16388         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16389         if (plane->has_fbc) {
16390                 struct intel_fbc *fbc = &dev_priv->fbc;
16391
16392                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16393         }
16394
16395         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16396                 formats = vlv_primary_formats;
16397                 num_formats = ARRAY_SIZE(vlv_primary_formats);
16398         } else if (INTEL_GEN(dev_priv) >= 4) {
16399                 /*
16400                  * WaFP16GammaEnabling:ivb
16401                  * "Workaround : When using the 64-bit format, the plane
16402                  *  output on each color channel has one quarter amplitude.
16403                  *  It can be brought up to full amplitude by using pipe
16404                  *  gamma correction or pipe color space conversion to
16405                  *  multiply the plane output by four."
16406                  *
16407                  * There is no dedicated plane gamma for the primary plane,
16408                  * and using the pipe gamma/csc could conflict with other
16409                  * planes, so we choose not to expose fp16 on IVB primary
16410                  * planes. HSW primary planes no longer have this problem.
16411                  */
16412                 if (IS_IVYBRIDGE(dev_priv)) {
16413                         formats = ivb_primary_formats;
16414                         num_formats = ARRAY_SIZE(ivb_primary_formats);
16415                 } else {
16416                         formats = i965_primary_formats;
16417                         num_formats = ARRAY_SIZE(i965_primary_formats);
16418                 }
16419         } else {
16420                 formats = i8xx_primary_formats;
16421                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16422         }
16423
16424         if (INTEL_GEN(dev_priv) >= 4)
16425                 plane_funcs = &i965_plane_funcs;
16426         else
16427                 plane_funcs = &i8xx_plane_funcs;
16428
16429         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16430                 plane->min_cdclk = vlv_plane_min_cdclk;
16431         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16432                 plane->min_cdclk = hsw_plane_min_cdclk;
16433         else if (IS_IVYBRIDGE(dev_priv))
16434                 plane->min_cdclk = ivb_plane_min_cdclk;
16435         else
16436                 plane->min_cdclk = i9xx_plane_min_cdclk;
16437
16438         plane->max_stride = i9xx_plane_max_stride;
16439         plane->update_plane = i9xx_update_plane;
16440         plane->disable_plane = i9xx_disable_plane;
16441         plane->get_hw_state = i9xx_plane_get_hw_state;
16442         plane->check_plane = i9xx_plane_check;
16443
16444         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16445                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16446                                                0, plane_funcs,
16447                                                formats, num_formats,
16448                                                i9xx_format_modifiers,
16449                                                DRM_PLANE_TYPE_PRIMARY,
16450                                                "primary %c", pipe_name(pipe));
16451         else
16452                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16453                                                0, plane_funcs,
16454                                                formats, num_formats,
16455                                                i9xx_format_modifiers,
16456                                                DRM_PLANE_TYPE_PRIMARY,
16457                                                "plane %c",
16458                                                plane_name(plane->i9xx_plane));
16459         if (ret)
16460                 goto fail;
16461
16462         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16463                 supported_rotations =
16464                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16465                         DRM_MODE_REFLECT_X;
16466         } else if (INTEL_GEN(dev_priv) >= 4) {
16467                 supported_rotations =
16468                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16469         } else {
16470                 supported_rotations = DRM_MODE_ROTATE_0;
16471         }
16472
16473         if (INTEL_GEN(dev_priv) >= 4)
16474                 drm_plane_create_rotation_property(&plane->base,
16475                                                    DRM_MODE_ROTATE_0,
16476                                                    supported_rotations);
16477
16478         zpos = 0;
16479         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16480
16481         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16482
16483         return plane;
16484
16485 fail:
16486         intel_plane_free(plane);
16487
16488         return ERR_PTR(ret);
16489 }
16490
16491 static struct intel_plane *
16492 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16493                           enum pipe pipe)
16494 {
16495         struct intel_plane *cursor;
16496         int ret, zpos;
16497
16498         cursor = intel_plane_alloc();
16499         if (IS_ERR(cursor))
16500                 return cursor;
16501
16502         cursor->pipe = pipe;
16503         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16504         cursor->id = PLANE_CURSOR;
16505         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16506
16507         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16508                 cursor->max_stride = i845_cursor_max_stride;
16509                 cursor->update_plane = i845_update_cursor;
16510                 cursor->disable_plane = i845_disable_cursor;
16511                 cursor->get_hw_state = i845_cursor_get_hw_state;
16512                 cursor->check_plane = i845_check_cursor;
16513         } else {
16514                 cursor->max_stride = i9xx_cursor_max_stride;
16515                 cursor->update_plane = i9xx_update_cursor;
16516                 cursor->disable_plane = i9xx_disable_cursor;
16517                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16518                 cursor->check_plane = i9xx_check_cursor;
16519         }
16520
16521         cursor->cursor.base = ~0;
16522         cursor->cursor.cntl = ~0;
16523
16524         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16525                 cursor->cursor.size = ~0;
16526
16527         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16528                                        0, &intel_cursor_plane_funcs,
16529                                        intel_cursor_formats,
16530                                        ARRAY_SIZE(intel_cursor_formats),
16531                                        cursor_format_modifiers,
16532                                        DRM_PLANE_TYPE_CURSOR,
16533                                        "cursor %c", pipe_name(pipe));
16534         if (ret)
16535                 goto fail;
16536
16537         if (INTEL_GEN(dev_priv) >= 4)
16538                 drm_plane_create_rotation_property(&cursor->base,
16539                                                    DRM_MODE_ROTATE_0,
16540                                                    DRM_MODE_ROTATE_0 |
16541                                                    DRM_MODE_ROTATE_180);
16542
16543         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16544         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16545
16546         if (INTEL_GEN(dev_priv) >= 12)
16547                 drm_plane_enable_fb_damage_clips(&cursor->base);
16548
16549         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16550
16551         return cursor;
16552
16553 fail:
16554         intel_plane_free(cursor);
16555
16556         return ERR_PTR(ret);
16557 }
16558
16559 #define INTEL_CRTC_FUNCS \
16560         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16561         .set_config = drm_atomic_helper_set_config, \
16562         .destroy = intel_crtc_destroy, \
16563         .page_flip = drm_atomic_helper_page_flip, \
16564         .atomic_duplicate_state = intel_crtc_duplicate_state, \
16565         .atomic_destroy_state = intel_crtc_destroy_state, \
16566         .set_crc_source = intel_crtc_set_crc_source, \
16567         .verify_crc_source = intel_crtc_verify_crc_source, \
16568         .get_crc_sources = intel_crtc_get_crc_sources
16569
16570 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16571         INTEL_CRTC_FUNCS,
16572
16573         .get_vblank_counter = g4x_get_vblank_counter,
16574         .enable_vblank = bdw_enable_vblank,
16575         .disable_vblank = bdw_disable_vblank,
16576         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16577 };
16578
16579 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16580         INTEL_CRTC_FUNCS,
16581
16582         .get_vblank_counter = g4x_get_vblank_counter,
16583         .enable_vblank = ilk_enable_vblank,
16584         .disable_vblank = ilk_disable_vblank,
16585         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16586 };
16587
16588 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16589         INTEL_CRTC_FUNCS,
16590
16591         .get_vblank_counter = g4x_get_vblank_counter,
16592         .enable_vblank = i965_enable_vblank,
16593         .disable_vblank = i965_disable_vblank,
16594         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16595 };
16596
16597 static const struct drm_crtc_funcs i965_crtc_funcs = {
16598         INTEL_CRTC_FUNCS,
16599
16600         .get_vblank_counter = i915_get_vblank_counter,
16601         .enable_vblank = i965_enable_vblank,
16602         .disable_vblank = i965_disable_vblank,
16603         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16604 };
16605
16606 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16607         INTEL_CRTC_FUNCS,
16608
16609         .get_vblank_counter = i915_get_vblank_counter,
16610         .enable_vblank = i915gm_enable_vblank,
16611         .disable_vblank = i915gm_disable_vblank,
16612         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16613 };
16614
16615 static const struct drm_crtc_funcs i915_crtc_funcs = {
16616         INTEL_CRTC_FUNCS,
16617
16618         .get_vblank_counter = i915_get_vblank_counter,
16619         .enable_vblank = i8xx_enable_vblank,
16620         .disable_vblank = i8xx_disable_vblank,
16621         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16622 };
16623
16624 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16625         INTEL_CRTC_FUNCS,
16626
16627         /* no hw vblank counter */
16628         .enable_vblank = i8xx_enable_vblank,
16629         .disable_vblank = i8xx_disable_vblank,
16630         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16631 };
16632
16633 static struct intel_crtc *intel_crtc_alloc(void)
16634 {
16635         struct intel_crtc_state *crtc_state;
16636         struct intel_crtc *crtc;
16637
16638         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16639         if (!crtc)
16640                 return ERR_PTR(-ENOMEM);
16641
16642         crtc_state = intel_crtc_state_alloc(crtc);
16643         if (!crtc_state) {
16644                 kfree(crtc);
16645                 return ERR_PTR(-ENOMEM);
16646         }
16647
16648         crtc->base.state = &crtc_state->uapi;
16649         crtc->config = crtc_state;
16650
16651         return crtc;
16652 }
16653
16654 static void intel_crtc_free(struct intel_crtc *crtc)
16655 {
16656         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16657         kfree(crtc);
16658 }
16659
16660 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16661 {
16662         struct intel_plane *plane;
16663
16664         for_each_intel_plane(&dev_priv->drm, plane) {
16665                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16666                                                                   plane->pipe);
16667
16668                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16669         }
16670 }
16671
16672 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16673 {
16674         struct intel_plane *primary, *cursor;
16675         const struct drm_crtc_funcs *funcs;
16676         struct intel_crtc *crtc;
16677         int sprite, ret;
16678
16679         crtc = intel_crtc_alloc();
16680         if (IS_ERR(crtc))
16681                 return PTR_ERR(crtc);
16682
16683         crtc->pipe = pipe;
16684         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16685
16686         primary = intel_primary_plane_create(dev_priv, pipe);
16687         if (IS_ERR(primary)) {
16688                 ret = PTR_ERR(primary);
16689                 goto fail;
16690         }
16691         crtc->plane_ids_mask |= BIT(primary->id);
16692
16693         for_each_sprite(dev_priv, pipe, sprite) {
16694                 struct intel_plane *plane;
16695
16696                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16697                 if (IS_ERR(plane)) {
16698                         ret = PTR_ERR(plane);
16699                         goto fail;
16700                 }
16701                 crtc->plane_ids_mask |= BIT(plane->id);
16702         }
16703
16704         cursor = intel_cursor_plane_create(dev_priv, pipe);
16705         if (IS_ERR(cursor)) {
16706                 ret = PTR_ERR(cursor);
16707                 goto fail;
16708         }
16709         crtc->plane_ids_mask |= BIT(cursor->id);
16710
16711         if (HAS_GMCH(dev_priv)) {
16712                 if (IS_CHERRYVIEW(dev_priv) ||
16713                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16714                         funcs = &g4x_crtc_funcs;
16715                 else if (IS_GEN(dev_priv, 4))
16716                         funcs = &i965_crtc_funcs;
16717                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16718                         funcs = &i915gm_crtc_funcs;
16719                 else if (IS_GEN(dev_priv, 3))
16720                         funcs = &i915_crtc_funcs;
16721                 else
16722                         funcs = &i8xx_crtc_funcs;
16723         } else {
16724                 if (INTEL_GEN(dev_priv) >= 8)
16725                         funcs = &bdw_crtc_funcs;
16726                 else
16727                         funcs = &ilk_crtc_funcs;
16728         }
16729
16730         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16731                                         &primary->base, &cursor->base,
16732                                         funcs, "pipe %c", pipe_name(pipe));
16733         if (ret)
16734                 goto fail;
16735
16736         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16737                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16738         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16739
16740         if (INTEL_GEN(dev_priv) < 9) {
16741                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16742
16743                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16744                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16745                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16746         }
16747
16748         intel_color_init(crtc);
16749
16750         intel_crtc_crc_init(crtc);
16751
16752         drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16753
16754         return 0;
16755
16756 fail:
16757         intel_crtc_free(crtc);
16758
16759         return ret;
16760 }
16761
16762 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16763                                       struct drm_file *file)
16764 {
16765         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16766         struct drm_crtc *drmmode_crtc;
16767         struct intel_crtc *crtc;
16768
16769         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16770         if (!drmmode_crtc)
16771                 return -ENOENT;
16772
16773         crtc = to_intel_crtc(drmmode_crtc);
16774         pipe_from_crtc_id->pipe = crtc->pipe;
16775
16776         return 0;
16777 }
16778
16779 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16780 {
16781         struct drm_device *dev = encoder->base.dev;
16782         struct intel_encoder *source_encoder;
16783         u32 possible_clones = 0;
16784
16785         for_each_intel_encoder(dev, source_encoder) {
16786                 if (encoders_cloneable(encoder, source_encoder))
16787                         possible_clones |= drm_encoder_mask(&source_encoder->base);
16788         }
16789
16790         return possible_clones;
16791 }
16792
16793 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16794 {
16795         struct drm_device *dev = encoder->base.dev;
16796         struct intel_crtc *crtc;
16797         u32 possible_crtcs = 0;
16798
16799         for_each_intel_crtc(dev, crtc) {
16800                 if (encoder->pipe_mask & BIT(crtc->pipe))
16801                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16802         }
16803
16804         return possible_crtcs;
16805 }
16806
16807 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16808 {
16809         if (!IS_MOBILE(dev_priv))
16810                 return false;
16811
16812         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16813                 return false;
16814
16815         if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16816                 return false;
16817
16818         return true;
16819 }
16820
16821 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16822 {
16823         if (INTEL_GEN(dev_priv) >= 9)
16824                 return false;
16825
16826         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16827                 return false;
16828
16829         if (HAS_PCH_LPT_H(dev_priv) &&
16830             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16831                 return false;
16832
16833         /* DDI E can't be used if DDI A requires 4 lanes */
16834         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16835                 return false;
16836
16837         if (!dev_priv->vbt.int_crt_support)
16838                 return false;
16839
16840         return true;
16841 }
16842
16843 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16844 {
16845         int pps_num;
16846         int pps_idx;
16847
16848         if (HAS_DDI(dev_priv))
16849                 return;
16850         /*
16851          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16852          * everywhere where registers can be write protected.
16853          */
16854         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16855                 pps_num = 2;
16856         else
16857                 pps_num = 1;
16858
16859         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16860                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16861
16862                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16863                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16864         }
16865 }
16866
16867 static void intel_pps_init(struct drm_i915_private *dev_priv)
16868 {
16869         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16870                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16871         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16872                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16873         else
16874                 dev_priv->pps_mmio_base = PPS_BASE;
16875
16876         intel_pps_unlock_regs_wa(dev_priv);
16877 }
16878
16879 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16880 {
16881         struct intel_encoder *encoder;
16882         bool dpd_is_edp = false;
16883
16884         intel_pps_init(dev_priv);
16885
16886         if (!HAS_DISPLAY(dev_priv))
16887                 return;
16888
16889         if (IS_ROCKETLAKE(dev_priv)) {
16890                 intel_ddi_init(dev_priv, PORT_A);
16891                 intel_ddi_init(dev_priv, PORT_B);
16892                 intel_ddi_init(dev_priv, PORT_D);       /* DDI TC1 */
16893                 intel_ddi_init(dev_priv, PORT_E);       /* DDI TC2 */
16894         } else if (INTEL_GEN(dev_priv) >= 12) {
16895                 intel_ddi_init(dev_priv, PORT_A);
16896                 intel_ddi_init(dev_priv, PORT_B);
16897                 intel_ddi_init(dev_priv, PORT_D);
16898                 intel_ddi_init(dev_priv, PORT_E);
16899                 intel_ddi_init(dev_priv, PORT_F);
16900                 intel_ddi_init(dev_priv, PORT_G);
16901                 intel_ddi_init(dev_priv, PORT_H);
16902                 intel_ddi_init(dev_priv, PORT_I);
16903                 icl_dsi_init(dev_priv);
16904         } else if (IS_ELKHARTLAKE(dev_priv)) {
16905                 intel_ddi_init(dev_priv, PORT_A);
16906                 intel_ddi_init(dev_priv, PORT_B);
16907                 intel_ddi_init(dev_priv, PORT_C);
16908                 intel_ddi_init(dev_priv, PORT_D);
16909                 icl_dsi_init(dev_priv);
16910         } else if (IS_GEN(dev_priv, 11)) {
16911                 intel_ddi_init(dev_priv, PORT_A);
16912                 intel_ddi_init(dev_priv, PORT_B);
16913                 intel_ddi_init(dev_priv, PORT_C);
16914                 intel_ddi_init(dev_priv, PORT_D);
16915                 intel_ddi_init(dev_priv, PORT_E);
16916                 /*
16917                  * On some ICL SKUs port F is not present. No strap bits for
16918                  * this, so rely on VBT.
16919                  * Work around broken VBTs on SKUs known to have no port F.
16920                  */
16921                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16922                     intel_bios_is_port_present(dev_priv, PORT_F))
16923                         intel_ddi_init(dev_priv, PORT_F);
16924
16925                 icl_dsi_init(dev_priv);
16926         } else if (IS_GEN9_LP(dev_priv)) {
16927                 /*
16928                  * FIXME: Broxton doesn't support port detection via the
16929                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16930                  * detect the ports.
16931                  */
16932                 intel_ddi_init(dev_priv, PORT_A);
16933                 intel_ddi_init(dev_priv, PORT_B);
16934                 intel_ddi_init(dev_priv, PORT_C);
16935
16936                 vlv_dsi_init(dev_priv);
16937         } else if (HAS_DDI(dev_priv)) {
16938                 int found;
16939
16940                 if (intel_ddi_crt_present(dev_priv))
16941                         intel_crt_init(dev_priv);
16942
16943                 /*
16944                  * Haswell uses DDI functions to detect digital outputs.
16945                  * On SKL pre-D0 the strap isn't connected, so we assume
16946                  * it's there.
16947                  */
16948                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16949                 /* WaIgnoreDDIAStrap: skl */
16950                 if (found || IS_GEN9_BC(dev_priv))
16951                         intel_ddi_init(dev_priv, PORT_A);
16952
16953                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16954                  * register */
16955                 found = intel_de_read(dev_priv, SFUSE_STRAP);
16956
16957                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16958                         intel_ddi_init(dev_priv, PORT_B);
16959                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16960                         intel_ddi_init(dev_priv, PORT_C);
16961                 if (found & SFUSE_STRAP_DDID_DETECTED)
16962                         intel_ddi_init(dev_priv, PORT_D);
16963                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16964                         intel_ddi_init(dev_priv, PORT_F);
16965                 /*
16966                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16967                  */
16968                 if (IS_GEN9_BC(dev_priv) &&
16969                     intel_bios_is_port_present(dev_priv, PORT_E))
16970                         intel_ddi_init(dev_priv, PORT_E);
16971
16972         } else if (HAS_PCH_SPLIT(dev_priv)) {
16973                 int found;
16974
16975                 /*
16976                  * intel_edp_init_connector() depends on this completing first,
16977                  * to prevent the registration of both eDP and LVDS and the
16978                  * incorrect sharing of the PPS.
16979                  */
16980                 intel_lvds_init(dev_priv);
16981                 intel_crt_init(dev_priv);
16982
16983                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16984
16985                 if (ilk_has_edp_a(dev_priv))
16986                         intel_dp_init(dev_priv, DP_A, PORT_A);
16987
16988                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16989                         /* PCH SDVOB multiplex with HDMIB */
16990                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16991                         if (!found)
16992                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16993                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16994                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16995                 }
16996
16997                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
16998                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16999
17000                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17001                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17002
17003                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17004                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17005
17006                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17007                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17008         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17009                 bool has_edp, has_port;
17010
17011                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17012                         intel_crt_init(dev_priv);
17013
17014                 /*
17015                  * The DP_DETECTED bit is the latched state of the DDC
17016                  * SDA pin at boot. However since eDP doesn't require DDC
17017                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
17018                  * eDP ports may have been muxed to an alternate function.
17019                  * Thus we can't rely on the DP_DETECTED bit alone to detect
17020                  * eDP ports. Consult the VBT as well as DP_DETECTED to
17021                  * detect eDP ports.
17022                  *
17023                  * Sadly the straps seem to be missing sometimes even for HDMI
17024                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17025                  * and VBT for the presence of the port. Additionally we can't
17026                  * trust the port type the VBT declares as we've seen at least
17027                  * HDMI ports that the VBT claim are DP or eDP.
17028                  */
17029                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17030                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17031                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17032                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17033                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17034                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17035
17036                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17037                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17038                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17039                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17040                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17041                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17042
17043                 if (IS_CHERRYVIEW(dev_priv)) {
17044                         /*
17045                          * eDP not supported on port D,
17046                          * so no need to worry about it
17047                          */
17048                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17049                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17050                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17051                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17052                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17053                 }
17054
17055                 vlv_dsi_init(dev_priv);
17056         } else if (IS_PINEVIEW(dev_priv)) {
17057                 intel_lvds_init(dev_priv);
17058                 intel_crt_init(dev_priv);
17059         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17060                 bool found = false;
17061
17062                 if (IS_MOBILE(dev_priv))
17063                         intel_lvds_init(dev_priv);
17064
17065                 intel_crt_init(dev_priv);
17066
17067                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17068                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17069                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17070                         if (!found && IS_G4X(dev_priv)) {
17071                                 drm_dbg_kms(&dev_priv->drm,
17072                                             "probing HDMI on SDVOB\n");
17073                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17074                         }
17075
17076                         if (!found && IS_G4X(dev_priv))
17077                                 intel_dp_init(dev_priv, DP_B, PORT_B);
17078                 }
17079
17080                 /* Before G4X SDVOC doesn't have its own detect register */
17081
17082                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17083                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17084                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17085                 }
17086
17087                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17088
17089                         if (IS_G4X(dev_priv)) {
17090                                 drm_dbg_kms(&dev_priv->drm,
17091                                             "probing HDMI on SDVOC\n");
17092                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17093                         }
17094                         if (IS_G4X(dev_priv))
17095                                 intel_dp_init(dev_priv, DP_C, PORT_C);
17096                 }
17097
17098                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17099                         intel_dp_init(dev_priv, DP_D, PORT_D);
17100
17101                 if (SUPPORTS_TV(dev_priv))
17102                         intel_tv_init(dev_priv);
17103         } else if (IS_GEN(dev_priv, 2)) {
17104                 if (IS_I85X(dev_priv))
17105                         intel_lvds_init(dev_priv);
17106
17107                 intel_crt_init(dev_priv);
17108                 intel_dvo_init(dev_priv);
17109         }
17110
17111         intel_psr_init(dev_priv);
17112
17113         for_each_intel_encoder(&dev_priv->drm, encoder) {
17114                 encoder->base.possible_crtcs =
17115                         intel_encoder_possible_crtcs(encoder);
17116                 encoder->base.possible_clones =
17117                         intel_encoder_possible_clones(encoder);
17118         }
17119
17120         intel_init_pch_refclk(dev_priv);
17121
17122         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17123 }
17124
17125 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17126 {
17127         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17128
17129         drm_framebuffer_cleanup(fb);
17130         intel_frontbuffer_put(intel_fb->frontbuffer);
17131
17132         kfree(intel_fb);
17133 }
17134
17135 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17136                                                 struct drm_file *file,
17137                                                 unsigned int *handle)
17138 {
17139         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17140         struct drm_i915_private *i915 = to_i915(obj->base.dev);
17141
17142         if (obj->userptr.mm) {
17143                 drm_dbg(&i915->drm,
17144                         "attempting to use a userptr for a framebuffer, denied\n");
17145                 return -EINVAL;
17146         }
17147
17148         return drm_gem_handle_create(file, &obj->base, handle);
17149 }
17150
17151 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17152                                         struct drm_file *file,
17153                                         unsigned flags, unsigned color,
17154                                         struct drm_clip_rect *clips,
17155                                         unsigned num_clips)
17156 {
17157         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17158
17159         i915_gem_object_flush_if_display(obj);
17160         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17161
17162         return 0;
17163 }
17164
17165 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17166         .destroy = intel_user_framebuffer_destroy,
17167         .create_handle = intel_user_framebuffer_create_handle,
17168         .dirty = intel_user_framebuffer_dirty,
17169 };
17170
17171 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17172                                   struct drm_i915_gem_object *obj,
17173                                   struct drm_mode_fb_cmd2 *mode_cmd)
17174 {
17175         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17176         struct drm_framebuffer *fb = &intel_fb->base;
17177         u32 max_stride;
17178         unsigned int tiling, stride;
17179         int ret = -EINVAL;
17180         int i;
17181
17182         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17183         if (!intel_fb->frontbuffer)
17184                 return -ENOMEM;
17185
17186         i915_gem_object_lock(obj, NULL);
17187         tiling = i915_gem_object_get_tiling(obj);
17188         stride = i915_gem_object_get_stride(obj);
17189         i915_gem_object_unlock(obj);
17190
17191         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17192                 /*
17193                  * If there's a fence, enforce that
17194                  * the fb modifier and tiling mode match.
17195                  */
17196                 if (tiling != I915_TILING_NONE &&
17197                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17198                         drm_dbg_kms(&dev_priv->drm,
17199                                     "tiling_mode doesn't match fb modifier\n");
17200                         goto err;
17201                 }
17202         } else {
17203                 if (tiling == I915_TILING_X) {
17204                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17205                 } else if (tiling == I915_TILING_Y) {
17206                         drm_dbg_kms(&dev_priv->drm,
17207                                     "No Y tiling for legacy addfb\n");
17208                         goto err;
17209                 }
17210         }
17211
17212         if (!drm_any_plane_has_format(&dev_priv->drm,
17213                                       mode_cmd->pixel_format,
17214                                       mode_cmd->modifier[0])) {
17215                 struct drm_format_name_buf format_name;
17216
17217                 drm_dbg_kms(&dev_priv->drm,
17218                             "unsupported pixel format %s / modifier 0x%llx\n",
17219                             drm_get_format_name(mode_cmd->pixel_format,
17220                                                 &format_name),
17221                             mode_cmd->modifier[0]);
17222                 goto err;
17223         }
17224
17225         /*
17226          * gen2/3 display engine uses the fence if present,
17227          * so the tiling mode must match the fb modifier exactly.
17228          */
17229         if (INTEL_GEN(dev_priv) < 4 &&
17230             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17231                 drm_dbg_kms(&dev_priv->drm,
17232                             "tiling_mode must match fb modifier exactly on gen2/3\n");
17233                 goto err;
17234         }
17235
17236         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17237                                          mode_cmd->modifier[0]);
17238         if (mode_cmd->pitches[0] > max_stride) {
17239                 drm_dbg_kms(&dev_priv->drm,
17240                             "%s pitch (%u) must be at most %d\n",
17241                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17242                             "tiled" : "linear",
17243                             mode_cmd->pitches[0], max_stride);
17244                 goto err;
17245         }
17246
17247         /*
17248          * If there's a fence, enforce that
17249          * the fb pitch and fence stride match.
17250          */
17251         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17252                 drm_dbg_kms(&dev_priv->drm,
17253                             "pitch (%d) must match tiling stride (%d)\n",
17254                             mode_cmd->pitches[0], stride);
17255                 goto err;
17256         }
17257
17258         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17259         if (mode_cmd->offsets[0] != 0) {
17260                 drm_dbg_kms(&dev_priv->drm,
17261                             "plane 0 offset (0x%08x) must be 0\n",
17262                             mode_cmd->offsets[0]);
17263                 goto err;
17264         }
17265
17266         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17267
17268         for (i = 0; i < fb->format->num_planes; i++) {
17269                 u32 stride_alignment;
17270
17271                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17272                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17273                                     i);
17274                         goto err;
17275                 }
17276
17277                 stride_alignment = intel_fb_stride_alignment(fb, i);
17278                 if (fb->pitches[i] & (stride_alignment - 1)) {
17279                         drm_dbg_kms(&dev_priv->drm,
17280                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
17281                                     i, fb->pitches[i], stride_alignment);
17282                         goto err;
17283                 }
17284
17285                 if (is_gen12_ccs_plane(fb, i)) {
17286                         int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17287
17288                         if (fb->pitches[i] != ccs_aux_stride) {
17289                                 drm_dbg_kms(&dev_priv->drm,
17290                                             "ccs aux plane %d pitch (%d) must be %d\n",
17291                                             i,
17292                                             fb->pitches[i], ccs_aux_stride);
17293                                 goto err;
17294                         }
17295                 }
17296
17297                 fb->obj[i] = &obj->base;
17298         }
17299
17300         ret = intel_fill_fb_info(dev_priv, fb);
17301         if (ret)
17302                 goto err;
17303
17304         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17305         if (ret) {
17306                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17307                 goto err;
17308         }
17309
17310         return 0;
17311
17312 err:
17313         intel_frontbuffer_put(intel_fb->frontbuffer);
17314         return ret;
17315 }
17316
17317 static struct drm_framebuffer *
17318 intel_user_framebuffer_create(struct drm_device *dev,
17319                               struct drm_file *filp,
17320                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
17321 {
17322         struct drm_framebuffer *fb;
17323         struct drm_i915_gem_object *obj;
17324         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17325
17326         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17327         if (!obj)
17328                 return ERR_PTR(-ENOENT);
17329
17330         fb = intel_framebuffer_create(obj, &mode_cmd);
17331         i915_gem_object_put(obj);
17332
17333         return fb;
17334 }
17335
17336 static enum drm_mode_status
17337 intel_mode_valid(struct drm_device *dev,
17338                  const struct drm_display_mode *mode)
17339 {
17340         struct drm_i915_private *dev_priv = to_i915(dev);
17341         int hdisplay_max, htotal_max;
17342         int vdisplay_max, vtotal_max;
17343
17344         /*
17345          * Can't reject DBLSCAN here because Xorg ddxen can add piles
17346          * of DBLSCAN modes to the output's mode list when they detect
17347          * the scaling mode property on the connector. And they don't
17348          * ask the kernel to validate those modes in any way until
17349          * modeset time at which point the client gets a protocol error.
17350          * So in order to not upset those clients we silently ignore the
17351          * DBLSCAN flag on such connectors. For other connectors we will
17352          * reject modes with the DBLSCAN flag in encoder->compute_config().
17353          * And we always reject DBLSCAN modes in connector->mode_valid()
17354          * as we never want such modes on the connector's mode list.
17355          */
17356
17357         if (mode->vscan > 1)
17358                 return MODE_NO_VSCAN;
17359
17360         if (mode->flags & DRM_MODE_FLAG_HSKEW)
17361                 return MODE_H_ILLEGAL;
17362
17363         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17364                            DRM_MODE_FLAG_NCSYNC |
17365                            DRM_MODE_FLAG_PCSYNC))
17366                 return MODE_HSYNC;
17367
17368         if (mode->flags & (DRM_MODE_FLAG_BCAST |
17369                            DRM_MODE_FLAG_PIXMUX |
17370                            DRM_MODE_FLAG_CLKDIV2))
17371                 return MODE_BAD;
17372
17373         /* Transcoder timing limits */
17374         if (INTEL_GEN(dev_priv) >= 11) {
17375                 hdisplay_max = 16384;
17376                 vdisplay_max = 8192;
17377                 htotal_max = 16384;
17378                 vtotal_max = 8192;
17379         } else if (INTEL_GEN(dev_priv) >= 9 ||
17380                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17381                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17382                 vdisplay_max = 4096;
17383                 htotal_max = 8192;
17384                 vtotal_max = 8192;
17385         } else if (INTEL_GEN(dev_priv) >= 3) {
17386                 hdisplay_max = 4096;
17387                 vdisplay_max = 4096;
17388                 htotal_max = 8192;
17389                 vtotal_max = 8192;
17390         } else {
17391                 hdisplay_max = 2048;
17392                 vdisplay_max = 2048;
17393                 htotal_max = 4096;
17394                 vtotal_max = 4096;
17395         }
17396
17397         if (mode->hdisplay > hdisplay_max ||
17398             mode->hsync_start > htotal_max ||
17399             mode->hsync_end > htotal_max ||
17400             mode->htotal > htotal_max)
17401                 return MODE_H_ILLEGAL;
17402
17403         if (mode->vdisplay > vdisplay_max ||
17404             mode->vsync_start > vtotal_max ||
17405             mode->vsync_end > vtotal_max ||
17406             mode->vtotal > vtotal_max)
17407                 return MODE_V_ILLEGAL;
17408
17409         if (INTEL_GEN(dev_priv) >= 5) {
17410                 if (mode->hdisplay < 64 ||
17411                     mode->htotal - mode->hdisplay < 32)
17412                         return MODE_H_ILLEGAL;
17413
17414                 if (mode->vtotal - mode->vdisplay < 5)
17415                         return MODE_V_ILLEGAL;
17416         } else {
17417                 if (mode->htotal - mode->hdisplay < 32)
17418                         return MODE_H_ILLEGAL;
17419
17420                 if (mode->vtotal - mode->vdisplay < 3)
17421                         return MODE_V_ILLEGAL;
17422         }
17423
17424         return MODE_OK;
17425 }
17426
17427 enum drm_mode_status
17428 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17429                                 const struct drm_display_mode *mode)
17430 {
17431         int plane_width_max, plane_height_max;
17432
17433         /*
17434          * intel_mode_valid() should be
17435          * sufficient on older platforms.
17436          */
17437         if (INTEL_GEN(dev_priv) < 9)
17438                 return MODE_OK;
17439
17440         /*
17441          * Most people will probably want a fullscreen
17442          * plane so let's not advertize modes that are
17443          * too big for that.
17444          */
17445         if (INTEL_GEN(dev_priv) >= 11) {
17446                 plane_width_max = 5120;
17447                 plane_height_max = 4320;
17448         } else {
17449                 plane_width_max = 5120;
17450                 plane_height_max = 4096;
17451         }
17452
17453         if (mode->hdisplay > plane_width_max)
17454                 return MODE_H_ILLEGAL;
17455
17456         if (mode->vdisplay > plane_height_max)
17457                 return MODE_V_ILLEGAL;
17458
17459         return MODE_OK;
17460 }
17461
17462 static const struct drm_mode_config_funcs intel_mode_funcs = {
17463         .fb_create = intel_user_framebuffer_create,
17464         .get_format_info = intel_get_format_info,
17465         .output_poll_changed = intel_fbdev_output_poll_changed,
17466         .mode_valid = intel_mode_valid,
17467         .atomic_check = intel_atomic_check,
17468         .atomic_commit = intel_atomic_commit,
17469         .atomic_state_alloc = intel_atomic_state_alloc,
17470         .atomic_state_clear = intel_atomic_state_clear,
17471         .atomic_state_free = intel_atomic_state_free,
17472 };
17473
17474 /**
17475  * intel_init_display_hooks - initialize the display modesetting hooks
17476  * @dev_priv: device private
17477  */
17478 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17479 {
17480         intel_init_cdclk_hooks(dev_priv);
17481
17482         if (INTEL_GEN(dev_priv) >= 9) {
17483                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17484                 dev_priv->display.get_initial_plane_config =
17485                         skl_get_initial_plane_config;
17486                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17487                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17488                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17489         } else if (HAS_DDI(dev_priv)) {
17490                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17491                 dev_priv->display.get_initial_plane_config =
17492                         i9xx_get_initial_plane_config;
17493                 dev_priv->display.crtc_compute_clock =
17494                         hsw_crtc_compute_clock;
17495                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17496                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17497         } else if (HAS_PCH_SPLIT(dev_priv)) {
17498                 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17499                 dev_priv->display.get_initial_plane_config =
17500                         i9xx_get_initial_plane_config;
17501                 dev_priv->display.crtc_compute_clock =
17502                         ilk_crtc_compute_clock;
17503                 dev_priv->display.crtc_enable = ilk_crtc_enable;
17504                 dev_priv->display.crtc_disable = ilk_crtc_disable;
17505         } else if (IS_CHERRYVIEW(dev_priv)) {
17506                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17507                 dev_priv->display.get_initial_plane_config =
17508                         i9xx_get_initial_plane_config;
17509                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17510                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17511                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17512         } else if (IS_VALLEYVIEW(dev_priv)) {
17513                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17514                 dev_priv->display.get_initial_plane_config =
17515                         i9xx_get_initial_plane_config;
17516                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17517                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17518                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17519         } else if (IS_G4X(dev_priv)) {
17520                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17521                 dev_priv->display.get_initial_plane_config =
17522                         i9xx_get_initial_plane_config;
17523                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17524                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17525                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17526         } else if (IS_PINEVIEW(dev_priv)) {
17527                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17528                 dev_priv->display.get_initial_plane_config =
17529                         i9xx_get_initial_plane_config;
17530                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17531                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17532                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17533         } else if (!IS_GEN(dev_priv, 2)) {
17534                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17535                 dev_priv->display.get_initial_plane_config =
17536                         i9xx_get_initial_plane_config;
17537                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17538                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17539                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17540         } else {
17541                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17542                 dev_priv->display.get_initial_plane_config =
17543                         i9xx_get_initial_plane_config;
17544                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17545                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17546                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17547         }
17548
17549         if (IS_GEN(dev_priv, 5)) {
17550                 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17551         } else if (IS_GEN(dev_priv, 6)) {
17552                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17553         } else if (IS_IVYBRIDGE(dev_priv)) {
17554                 /* FIXME: detect B0+ stepping and use auto training */
17555                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17556         }
17557
17558         if (INTEL_GEN(dev_priv) >= 9)
17559                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17560         else
17561                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17562
17563 }
17564
17565 void intel_modeset_init_hw(struct drm_i915_private *i915)
17566 {
17567         struct intel_cdclk_state *cdclk_state =
17568                 to_intel_cdclk_state(i915->cdclk.obj.state);
17569         struct intel_dbuf_state *dbuf_state =
17570                 to_intel_dbuf_state(i915->dbuf.obj.state);
17571
17572         intel_update_cdclk(i915);
17573         intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17574         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17575
17576         dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17577 }
17578
17579 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17580 {
17581         struct drm_plane *plane;
17582         struct intel_crtc *crtc;
17583
17584         for_each_intel_crtc(state->dev, crtc) {
17585                 struct intel_crtc_state *crtc_state;
17586
17587                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17588                 if (IS_ERR(crtc_state))
17589                         return PTR_ERR(crtc_state);
17590
17591                 if (crtc_state->hw.active) {
17592                         /*
17593                          * Preserve the inherited flag to avoid
17594                          * taking the full modeset path.
17595                          */
17596                         crtc_state->inherited = true;
17597                 }
17598         }
17599
17600         drm_for_each_plane(plane, state->dev) {
17601                 struct drm_plane_state *plane_state;
17602
17603                 plane_state = drm_atomic_get_plane_state(state, plane);
17604                 if (IS_ERR(plane_state))
17605                         return PTR_ERR(plane_state);
17606         }
17607
17608         return 0;
17609 }
17610
17611 /*
17612  * Calculate what we think the watermarks should be for the state we've read
17613  * out of the hardware and then immediately program those watermarks so that
17614  * we ensure the hardware settings match our internal state.
17615  *
17616  * We can calculate what we think WM's should be by creating a duplicate of the
17617  * current state (which was constructed during hardware readout) and running it
17618  * through the atomic check code to calculate new watermark values in the
17619  * state object.
17620  */
17621 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17622 {
17623         struct drm_atomic_state *state;
17624         struct intel_atomic_state *intel_state;
17625         struct intel_crtc *crtc;
17626         struct intel_crtc_state *crtc_state;
17627         struct drm_modeset_acquire_ctx ctx;
17628         int ret;
17629         int i;
17630
17631         /* Only supported on platforms that use atomic watermark design */
17632         if (!dev_priv->display.optimize_watermarks)
17633                 return;
17634
17635         state = drm_atomic_state_alloc(&dev_priv->drm);
17636         if (drm_WARN_ON(&dev_priv->drm, !state))
17637                 return;
17638
17639         intel_state = to_intel_atomic_state(state);
17640
17641         drm_modeset_acquire_init(&ctx, 0);
17642
17643 retry:
17644         state->acquire_ctx = &ctx;
17645
17646         /*
17647          * Hardware readout is the only time we don't want to calculate
17648          * intermediate watermarks (since we don't trust the current
17649          * watermarks).
17650          */
17651         if (!HAS_GMCH(dev_priv))
17652                 intel_state->skip_intermediate_wm = true;
17653
17654         ret = sanitize_watermarks_add_affected(state);
17655         if (ret)
17656                 goto fail;
17657
17658         ret = intel_atomic_check(&dev_priv->drm, state);
17659         if (ret)
17660                 goto fail;
17661
17662         /* Write calculated watermark values back */
17663         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17664                 crtc_state->wm.need_postvbl_update = true;
17665                 dev_priv->display.optimize_watermarks(intel_state, crtc);
17666
17667                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17668         }
17669
17670 fail:
17671         if (ret == -EDEADLK) {
17672                 drm_atomic_state_clear(state);
17673                 drm_modeset_backoff(&ctx);
17674                 goto retry;
17675         }
17676
17677         /*
17678          * If we fail here, it means that the hardware appears to be
17679          * programmed in a way that shouldn't be possible, given our
17680          * understanding of watermark requirements.  This might mean a
17681          * mistake in the hardware readout code or a mistake in the
17682          * watermark calculations for a given platform.  Raise a WARN
17683          * so that this is noticeable.
17684          *
17685          * If this actually happens, we'll have to just leave the
17686          * BIOS-programmed watermarks untouched and hope for the best.
17687          */
17688         drm_WARN(&dev_priv->drm, ret,
17689                  "Could not determine valid watermarks for inherited state\n");
17690
17691         drm_atomic_state_put(state);
17692
17693         drm_modeset_drop_locks(&ctx);
17694         drm_modeset_acquire_fini(&ctx);
17695 }
17696
17697 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17698 {
17699         if (IS_GEN(dev_priv, 5)) {
17700                 u32 fdi_pll_clk =
17701                         intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17702
17703                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17704         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17705                 dev_priv->fdi_pll_freq = 270000;
17706         } else {
17707                 return;
17708         }
17709
17710         drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17711 }
17712
17713 static int intel_initial_commit(struct drm_device *dev)
17714 {
17715         struct drm_atomic_state *state = NULL;
17716         struct drm_modeset_acquire_ctx ctx;
17717         struct intel_crtc *crtc;
17718         int ret = 0;
17719
17720         state = drm_atomic_state_alloc(dev);
17721         if (!state)
17722                 return -ENOMEM;
17723
17724         drm_modeset_acquire_init(&ctx, 0);
17725
17726 retry:
17727         state->acquire_ctx = &ctx;
17728
17729         for_each_intel_crtc(dev, crtc) {
17730                 struct intel_crtc_state *crtc_state =
17731                         intel_atomic_get_crtc_state(state, crtc);
17732
17733                 if (IS_ERR(crtc_state)) {
17734                         ret = PTR_ERR(crtc_state);
17735                         goto out;
17736                 }
17737
17738                 if (crtc_state->hw.active) {
17739                         /*
17740                          * We've not yet detected sink capabilities
17741                          * (audio,infoframes,etc.) and thus we don't want to
17742                          * force a full state recomputation yet. We want that to
17743                          * happen only for the first real commit from userspace.
17744                          * So preserve the inherited flag for the time being.
17745                          */
17746                         crtc_state->inherited = true;
17747
17748                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
17749                         if (ret)
17750                                 goto out;
17751
17752                         /*
17753                          * FIXME hack to force a LUT update to avoid the
17754                          * plane update forcing the pipe gamma on without
17755                          * having a proper LUT loaded. Remove once we
17756                          * have readout for pipe gamma enable.
17757                          */
17758                         crtc_state->uapi.color_mgmt_changed = true;
17759
17760                         /*
17761                          * FIXME hack to force full modeset when DSC is being
17762                          * used.
17763                          *
17764                          * As long as we do not have full state readout and
17765                          * config comparison of crtc_state->dsc, we have no way
17766                          * to ensure reliable fastset. Remove once we have
17767                          * readout for DSC.
17768                          */
17769                         if (crtc_state->dsc.compression_enable) {
17770                                 ret = drm_atomic_add_affected_connectors(state,
17771                                                                          &crtc->base);
17772                                 if (ret)
17773                                         goto out;
17774                                 crtc_state->uapi.mode_changed = true;
17775                                 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17776                         }
17777                 }
17778         }
17779
17780         ret = drm_atomic_commit(state);
17781
17782 out:
17783         if (ret == -EDEADLK) {
17784                 drm_atomic_state_clear(state);
17785                 drm_modeset_backoff(&ctx);
17786                 goto retry;
17787         }
17788
17789         drm_atomic_state_put(state);
17790
17791         drm_modeset_drop_locks(&ctx);
17792         drm_modeset_acquire_fini(&ctx);
17793
17794         return ret;
17795 }
17796
17797 static void intel_mode_config_init(struct drm_i915_private *i915)
17798 {
17799         struct drm_mode_config *mode_config = &i915->drm.mode_config;
17800
17801         drm_mode_config_init(&i915->drm);
17802         INIT_LIST_HEAD(&i915->global_obj_list);
17803
17804         mode_config->min_width = 0;
17805         mode_config->min_height = 0;
17806
17807         mode_config->preferred_depth = 24;
17808         mode_config->prefer_shadow = 1;
17809
17810         mode_config->allow_fb_modifiers = true;
17811
17812         mode_config->funcs = &intel_mode_funcs;
17813
17814         /*
17815          * Maximum framebuffer dimensions, chosen to match
17816          * the maximum render engine surface size on gen4+.
17817          */
17818         if (INTEL_GEN(i915) >= 7) {
17819                 mode_config->max_width = 16384;
17820                 mode_config->max_height = 16384;
17821         } else if (INTEL_GEN(i915) >= 4) {
17822                 mode_config->max_width = 8192;
17823                 mode_config->max_height = 8192;
17824         } else if (IS_GEN(i915, 3)) {
17825                 mode_config->max_width = 4096;
17826                 mode_config->max_height = 4096;
17827         } else {
17828                 mode_config->max_width = 2048;
17829                 mode_config->max_height = 2048;
17830         }
17831
17832         if (IS_I845G(i915) || IS_I865G(i915)) {
17833                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17834                 mode_config->cursor_height = 1023;
17835         } else if (IS_I830(i915) || IS_I85X(i915) ||
17836                    IS_I915G(i915) || IS_I915GM(i915)) {
17837                 mode_config->cursor_width = 64;
17838                 mode_config->cursor_height = 64;
17839         } else {
17840                 mode_config->cursor_width = 256;
17841                 mode_config->cursor_height = 256;
17842         }
17843 }
17844
17845 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17846 {
17847         intel_atomic_global_obj_cleanup(i915);
17848         drm_mode_config_cleanup(&i915->drm);
17849 }
17850
17851 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17852 {
17853         if (plane_config->fb) {
17854                 struct drm_framebuffer *fb = &plane_config->fb->base;
17855
17856                 /* We may only have the stub and not a full framebuffer */
17857                 if (drm_framebuffer_read_refcount(fb))
17858                         drm_framebuffer_put(fb);
17859                 else
17860                         kfree(fb);
17861         }
17862
17863         if (plane_config->vma)
17864                 i915_vma_put(plane_config->vma);
17865 }
17866
17867 /* part #1: call before irq install */
17868 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17869 {
17870         int ret;
17871
17872         if (i915_inject_probe_failure(i915))
17873                 return -ENODEV;
17874
17875         if (HAS_DISPLAY(i915)) {
17876                 ret = drm_vblank_init(&i915->drm,
17877                                       INTEL_NUM_PIPES(i915));
17878                 if (ret)
17879                         return ret;
17880         }
17881
17882         intel_bios_init(i915);
17883
17884         ret = intel_vga_register(i915);
17885         if (ret)
17886                 goto cleanup_bios;
17887
17888         /* FIXME: completely on the wrong abstraction layer */
17889         intel_power_domains_init_hw(i915, false);
17890
17891         intel_csr_ucode_init(i915);
17892
17893         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17894         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17895                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17896
17897         intel_mode_config_init(i915);
17898
17899         ret = intel_cdclk_init(i915);
17900         if (ret)
17901                 goto cleanup_vga_client_pw_domain_csr;
17902
17903         ret = intel_dbuf_init(i915);
17904         if (ret)
17905                 goto cleanup_vga_client_pw_domain_csr;
17906
17907         ret = intel_bw_init(i915);
17908         if (ret)
17909                 goto cleanup_vga_client_pw_domain_csr;
17910
17911         init_llist_head(&i915->atomic_helper.free_list);
17912         INIT_WORK(&i915->atomic_helper.free_work,
17913                   intel_atomic_helper_free_state_worker);
17914
17915         intel_init_quirks(i915);
17916
17917         intel_fbc_init(i915);
17918
17919         return 0;
17920
17921 cleanup_vga_client_pw_domain_csr:
17922         intel_csr_ucode_fini(i915);
17923         intel_power_domains_driver_remove(i915);
17924         intel_vga_unregister(i915);
17925 cleanup_bios:
17926         intel_bios_driver_remove(i915);
17927
17928         return ret;
17929 }
17930
17931 /* part #2: call after irq install, but before gem init */
17932 int intel_modeset_init_nogem(struct drm_i915_private *i915)
17933 {
17934         struct drm_device *dev = &i915->drm;
17935         enum pipe pipe;
17936         struct intel_crtc *crtc;
17937         int ret;
17938
17939         intel_init_pm(i915);
17940
17941         intel_panel_sanitize_ssc(i915);
17942
17943         intel_gmbus_setup(i915);
17944
17945         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17946                     INTEL_NUM_PIPES(i915),
17947                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17948
17949         if (HAS_DISPLAY(i915)) {
17950                 for_each_pipe(i915, pipe) {
17951                         ret = intel_crtc_init(i915, pipe);
17952                         if (ret) {
17953                                 intel_mode_config_cleanup(i915);
17954                                 return ret;
17955                         }
17956                 }
17957         }
17958
17959         intel_plane_possible_crtcs_init(i915);
17960         intel_shared_dpll_init(dev);
17961         intel_update_fdi_pll_freq(i915);
17962
17963         intel_update_czclk(i915);
17964         intel_modeset_init_hw(i915);
17965
17966         intel_hdcp_component_init(i915);
17967
17968         if (i915->max_cdclk_freq == 0)
17969                 intel_update_max_cdclk(i915);
17970
17971         /*
17972          * If the platform has HTI, we need to find out whether it has reserved
17973          * any display resources before we create our display outputs.
17974          */
17975         if (INTEL_INFO(i915)->display.has_hti)
17976                 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
17977
17978         /* Just disable it once at startup */
17979         intel_vga_disable(i915);
17980         intel_setup_outputs(i915);
17981
17982         drm_modeset_lock_all(dev);
17983         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17984         drm_modeset_unlock_all(dev);
17985
17986         for_each_intel_crtc(dev, crtc) {
17987                 struct intel_initial_plane_config plane_config = {};
17988
17989                 if (!crtc->active)
17990                         continue;
17991
17992                 /*
17993                  * Note that reserving the BIOS fb up front prevents us
17994                  * from stuffing other stolen allocations like the ring
17995                  * on top.  This prevents some ugliness at boot time, and
17996                  * can even allow for smooth boot transitions if the BIOS
17997                  * fb is large enough for the active pipe configuration.
17998                  */
17999                 i915->display.get_initial_plane_config(crtc, &plane_config);
18000
18001                 /*
18002                  * If the fb is shared between multiple heads, we'll
18003                  * just get the first one.
18004                  */
18005                 intel_find_initial_plane_obj(crtc, &plane_config);
18006
18007                 plane_config_fini(&plane_config);
18008         }
18009
18010         /*
18011          * Make sure hardware watermarks really match the state we read out.
18012          * Note that we need to do this after reconstructing the BIOS fb's
18013          * since the watermark calculation done here will use pstate->fb.
18014          */
18015         if (!HAS_GMCH(i915))
18016                 sanitize_watermarks(i915);
18017
18018         /*
18019          * Force all active planes to recompute their states. So that on
18020          * mode_setcrtc after probe, all the intel_plane_state variables
18021          * are already calculated and there is no assert_plane warnings
18022          * during bootup.
18023          */
18024         ret = intel_initial_commit(dev);
18025         if (ret)
18026                 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18027
18028         return 0;
18029 }
18030
18031 /* part #3: call after gem init */
18032 int intel_modeset_init(struct drm_i915_private *i915)
18033 {
18034         int ret;
18035
18036         intel_overlay_setup(i915);
18037
18038         if (!HAS_DISPLAY(i915))
18039                 return 0;
18040
18041         ret = intel_fbdev_init(&i915->drm);
18042         if (ret)
18043                 return ret;
18044
18045         /* Only enable hotplug handling once the fbdev is fully set up. */
18046         intel_hpd_init(i915);
18047
18048         intel_init_ipc(i915);
18049
18050         intel_psr_set_force_mode_changed(i915->psr.dp);
18051
18052         return 0;
18053 }
18054
18055 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18056 {
18057         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18058         /* 640x480@60Hz, ~25175 kHz */
18059         struct dpll clock = {
18060                 .m1 = 18,
18061                 .m2 = 7,
18062                 .p1 = 13,
18063                 .p2 = 4,
18064                 .n = 2,
18065         };
18066         u32 dpll, fp;
18067         int i;
18068
18069         drm_WARN_ON(&dev_priv->drm,
18070                     i9xx_calc_dpll_params(48000, &clock) != 25154);
18071
18072         drm_dbg_kms(&dev_priv->drm,
18073                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18074                     pipe_name(pipe), clock.vco, clock.dot);
18075
18076         fp = i9xx_dpll_compute_fp(&clock);
18077         dpll = DPLL_DVO_2X_MODE |
18078                 DPLL_VGA_MODE_DIS |
18079                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18080                 PLL_P2_DIVIDE_BY_4 |
18081                 PLL_REF_INPUT_DREFCLK |
18082                 DPLL_VCO_ENABLE;
18083
18084         intel_de_write(dev_priv, FP0(pipe), fp);
18085         intel_de_write(dev_priv, FP1(pipe), fp);
18086
18087         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18088         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18089         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18090         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18091         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18092         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18093         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18094
18095         /*
18096          * Apparently we need to have VGA mode enabled prior to changing
18097          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18098          * dividers, even though the register value does change.
18099          */
18100         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18101         intel_de_write(dev_priv, DPLL(pipe), dpll);
18102
18103         /* Wait for the clocks to stabilize. */
18104         intel_de_posting_read(dev_priv, DPLL(pipe));
18105         udelay(150);
18106
18107         /* The pixel multiplier can only be updated once the
18108          * DPLL is enabled and the clocks are stable.
18109          *
18110          * So write it again.
18111          */
18112         intel_de_write(dev_priv, DPLL(pipe), dpll);
18113
18114         /* We do this three times for luck */
18115         for (i = 0; i < 3 ; i++) {
18116                 intel_de_write(dev_priv, DPLL(pipe), dpll);
18117                 intel_de_posting_read(dev_priv, DPLL(pipe));
18118                 udelay(150); /* wait for warmup */
18119         }
18120
18121         intel_de_write(dev_priv, PIPECONF(pipe),
18122                        PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18123         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18124
18125         intel_wait_for_pipe_scanline_moving(crtc);
18126 }
18127
18128 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18129 {
18130         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18131
18132         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18133                     pipe_name(pipe));
18134
18135         drm_WARN_ON(&dev_priv->drm,
18136                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18137                     DISPLAY_PLANE_ENABLE);
18138         drm_WARN_ON(&dev_priv->drm,
18139                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18140                     DISPLAY_PLANE_ENABLE);
18141         drm_WARN_ON(&dev_priv->drm,
18142                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18143                     DISPLAY_PLANE_ENABLE);
18144         drm_WARN_ON(&dev_priv->drm,
18145                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18146         drm_WARN_ON(&dev_priv->drm,
18147                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18148
18149         intel_de_write(dev_priv, PIPECONF(pipe), 0);
18150         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18151
18152         intel_wait_for_pipe_scanline_stopped(crtc);
18153
18154         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18155         intel_de_posting_read(dev_priv, DPLL(pipe));
18156 }
18157
18158 static void
18159 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18160 {
18161         struct intel_crtc *crtc;
18162
18163         if (INTEL_GEN(dev_priv) >= 4)
18164                 return;
18165
18166         for_each_intel_crtc(&dev_priv->drm, crtc) {
18167                 struct intel_plane *plane =
18168                         to_intel_plane(crtc->base.primary);
18169                 struct intel_crtc *plane_crtc;
18170                 enum pipe pipe;
18171
18172                 if (!plane->get_hw_state(plane, &pipe))
18173                         continue;
18174
18175                 if (pipe == crtc->pipe)
18176                         continue;
18177
18178                 drm_dbg_kms(&dev_priv->drm,
18179                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18180                             plane->base.base.id, plane->base.name);
18181
18182                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18183                 intel_plane_disable_noatomic(plane_crtc, plane);
18184         }
18185 }
18186
18187 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18188 {
18189         struct drm_device *dev = crtc->base.dev;
18190         struct intel_encoder *encoder;
18191
18192         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18193                 return true;
18194
18195         return false;
18196 }
18197
18198 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18199 {
18200         struct drm_device *dev = encoder->base.dev;
18201         struct intel_connector *connector;
18202
18203         for_each_connector_on_encoder(dev, &encoder->base, connector)
18204                 return connector;
18205
18206         return NULL;
18207 }
18208
18209 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18210                               enum pipe pch_transcoder)
18211 {
18212         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18213                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18214 }
18215
18216 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18217 {
18218         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18219         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18220         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18221
18222         if (INTEL_GEN(dev_priv) >= 9 ||
18223             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18224                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18225                 u32 val;
18226
18227                 if (transcoder_is_dsi(cpu_transcoder))
18228                         return;
18229
18230                 val = intel_de_read(dev_priv, reg);
18231                 val &= ~HSW_FRAME_START_DELAY_MASK;
18232                 val |= HSW_FRAME_START_DELAY(0);
18233                 intel_de_write(dev_priv, reg, val);
18234         } else {
18235                 i915_reg_t reg = PIPECONF(cpu_transcoder);
18236                 u32 val;
18237
18238                 val = intel_de_read(dev_priv, reg);
18239                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18240                 val |= PIPECONF_FRAME_START_DELAY(0);
18241                 intel_de_write(dev_priv, reg, val);
18242         }
18243
18244         if (!crtc_state->has_pch_encoder)
18245                 return;
18246
18247         if (HAS_PCH_IBX(dev_priv)) {
18248                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18249                 u32 val;
18250
18251                 val = intel_de_read(dev_priv, reg);
18252                 val &= ~TRANS_FRAME_START_DELAY_MASK;
18253                 val |= TRANS_FRAME_START_DELAY(0);
18254                 intel_de_write(dev_priv, reg, val);
18255         } else {
18256                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18257                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18258                 u32 val;
18259
18260                 val = intel_de_read(dev_priv, reg);
18261                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18262                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18263                 intel_de_write(dev_priv, reg, val);
18264         }
18265 }
18266
18267 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18268                                 struct drm_modeset_acquire_ctx *ctx)
18269 {
18270         struct drm_device *dev = crtc->base.dev;
18271         struct drm_i915_private *dev_priv = to_i915(dev);
18272         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18273
18274         if (crtc_state->hw.active) {
18275                 struct intel_plane *plane;
18276
18277                 /* Clear any frame start delays used for debugging left by the BIOS */
18278                 intel_sanitize_frame_start_delay(crtc_state);
18279
18280                 /* Disable everything but the primary plane */
18281                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18282                         const struct intel_plane_state *plane_state =
18283                                 to_intel_plane_state(plane->base.state);
18284
18285                         if (plane_state->uapi.visible &&
18286                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18287                                 intel_plane_disable_noatomic(crtc, plane);
18288                 }
18289
18290                 /*
18291                  * Disable any background color set by the BIOS, but enable the
18292                  * gamma and CSC to match how we program our planes.
18293                  */
18294                 if (INTEL_GEN(dev_priv) >= 9)
18295                         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18296                                        SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18297         }
18298
18299         /* Adjust the state of the output pipe according to whether we
18300          * have active connectors/encoders. */
18301         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18302                 intel_crtc_disable_noatomic(crtc, ctx);
18303
18304         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18305                 /*
18306                  * We start out with underrun reporting disabled to avoid races.
18307                  * For correct bookkeeping mark this on active crtcs.
18308                  *
18309                  * Also on gmch platforms we dont have any hardware bits to
18310                  * disable the underrun reporting. Which means we need to start
18311                  * out with underrun reporting disabled also on inactive pipes,
18312                  * since otherwise we'll complain about the garbage we read when
18313                  * e.g. coming up after runtime pm.
18314                  *
18315                  * No protection against concurrent access is required - at
18316                  * worst a fifo underrun happens which also sets this to false.
18317                  */
18318                 crtc->cpu_fifo_underrun_disabled = true;
18319                 /*
18320                  * We track the PCH trancoder underrun reporting state
18321                  * within the crtc. With crtc for pipe A housing the underrun
18322                  * reporting state for PCH transcoder A, crtc for pipe B housing
18323                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18324                  * and marking underrun reporting as disabled for the non-existing
18325                  * PCH transcoders B and C would prevent enabling the south
18326                  * error interrupt (see cpt_can_enable_serr_int()).
18327                  */
18328                 if (has_pch_trancoder(dev_priv, crtc->pipe))
18329                         crtc->pch_fifo_underrun_disabled = true;
18330         }
18331 }
18332
18333 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18334 {
18335         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18336
18337         /*
18338          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18339          * the hardware when a high res displays plugged in. DPLL P
18340          * divider is zero, and the pipe timings are bonkers. We'll
18341          * try to disable everything in that case.
18342          *
18343          * FIXME would be nice to be able to sanitize this state
18344          * without several WARNs, but for now let's take the easy
18345          * road.
18346          */
18347         return IS_GEN(dev_priv, 6) &&
18348                 crtc_state->hw.active &&
18349                 crtc_state->shared_dpll &&
18350                 crtc_state->port_clock == 0;
18351 }
18352
18353 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18354 {
18355         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18356         struct intel_connector *connector;
18357         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18358         struct intel_crtc_state *crtc_state = crtc ?
18359                 to_intel_crtc_state(crtc->base.state) : NULL;
18360
18361         /* We need to check both for a crtc link (meaning that the
18362          * encoder is active and trying to read from a pipe) and the
18363          * pipe itself being active. */
18364         bool has_active_crtc = crtc_state &&
18365                 crtc_state->hw.active;
18366
18367         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18368                 drm_dbg_kms(&dev_priv->drm,
18369                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18370                             pipe_name(crtc->pipe));
18371                 has_active_crtc = false;
18372         }
18373
18374         connector = intel_encoder_find_connector(encoder);
18375         if (connector && !has_active_crtc) {
18376                 drm_dbg_kms(&dev_priv->drm,
18377                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18378                             encoder->base.base.id,
18379                             encoder->base.name);
18380
18381                 /* Connector is active, but has no active pipe. This is
18382                  * fallout from our resume register restoring. Disable
18383                  * the encoder manually again. */
18384                 if (crtc_state) {
18385                         struct drm_encoder *best_encoder;
18386
18387                         drm_dbg_kms(&dev_priv->drm,
18388                                     "[ENCODER:%d:%s] manually disabled\n",
18389                                     encoder->base.base.id,
18390                                     encoder->base.name);
18391
18392                         /* avoid oopsing in case the hooks consult best_encoder */
18393                         best_encoder = connector->base.state->best_encoder;
18394                         connector->base.state->best_encoder = &encoder->base;
18395
18396                         /* FIXME NULL atomic state passed! */
18397                         if (encoder->disable)
18398                                 encoder->disable(NULL, encoder, crtc_state,
18399                                                  connector->base.state);
18400                         if (encoder->post_disable)
18401                                 encoder->post_disable(NULL, encoder, crtc_state,
18402                                                       connector->base.state);
18403
18404                         connector->base.state->best_encoder = best_encoder;
18405                 }
18406                 encoder->base.crtc = NULL;
18407
18408                 /* Inconsistent output/port/pipe state happens presumably due to
18409                  * a bug in one of the get_hw_state functions. Or someplace else
18410                  * in our code, like the register restore mess on resume. Clamp
18411                  * things to off as a safer default. */
18412
18413                 connector->base.dpms = DRM_MODE_DPMS_OFF;
18414                 connector->base.encoder = NULL;
18415         }
18416
18417         /* notify opregion of the sanitized encoder state */
18418         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18419
18420         if (INTEL_GEN(dev_priv) >= 11)
18421                 icl_sanitize_encoder_pll_mapping(encoder);
18422 }
18423
18424 /* FIXME read out full plane state for all planes */
18425 static void readout_plane_state(struct drm_i915_private *dev_priv)
18426 {
18427         struct intel_plane *plane;
18428         struct intel_crtc *crtc;
18429
18430         for_each_intel_plane(&dev_priv->drm, plane) {
18431                 struct intel_plane_state *plane_state =
18432                         to_intel_plane_state(plane->base.state);
18433                 struct intel_crtc_state *crtc_state;
18434                 enum pipe pipe = PIPE_A;
18435                 bool visible;
18436
18437                 visible = plane->get_hw_state(plane, &pipe);
18438
18439                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18440                 crtc_state = to_intel_crtc_state(crtc->base.state);
18441
18442                 intel_set_plane_visible(crtc_state, plane_state, visible);
18443
18444                 drm_dbg_kms(&dev_priv->drm,
18445                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18446                             plane->base.base.id, plane->base.name,
18447                             enableddisabled(visible), pipe_name(pipe));
18448         }
18449
18450         for_each_intel_crtc(&dev_priv->drm, crtc) {
18451                 struct intel_crtc_state *crtc_state =
18452                         to_intel_crtc_state(crtc->base.state);
18453
18454                 fixup_active_planes(crtc_state);
18455         }
18456 }
18457
18458 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18459 {
18460         struct drm_i915_private *dev_priv = to_i915(dev);
18461         struct intel_cdclk_state *cdclk_state =
18462                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18463         struct intel_dbuf_state *dbuf_state =
18464                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18465         enum pipe pipe;
18466         struct intel_crtc *crtc;
18467         struct intel_encoder *encoder;
18468         struct intel_connector *connector;
18469         struct drm_connector_list_iter conn_iter;
18470         u8 active_pipes = 0;
18471
18472         for_each_intel_crtc(dev, crtc) {
18473                 struct intel_crtc_state *crtc_state =
18474                         to_intel_crtc_state(crtc->base.state);
18475
18476                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18477                 intel_crtc_free_hw_state(crtc_state);
18478                 intel_crtc_state_reset(crtc_state, crtc);
18479
18480                 crtc_state->hw.active = crtc_state->hw.enable =
18481                         dev_priv->display.get_pipe_config(crtc, crtc_state);
18482
18483                 crtc->base.enabled = crtc_state->hw.enable;
18484                 crtc->active = crtc_state->hw.active;
18485
18486                 if (crtc_state->hw.active)
18487                         active_pipes |= BIT(crtc->pipe);
18488
18489                 drm_dbg_kms(&dev_priv->drm,
18490                             "[CRTC:%d:%s] hw state readout: %s\n",
18491                             crtc->base.base.id, crtc->base.name,
18492                             enableddisabled(crtc_state->hw.active));
18493         }
18494
18495         dev_priv->active_pipes = cdclk_state->active_pipes =
18496                 dbuf_state->active_pipes = active_pipes;
18497
18498         readout_plane_state(dev_priv);
18499
18500         intel_dpll_readout_hw_state(dev_priv);
18501
18502         for_each_intel_encoder(dev, encoder) {
18503                 pipe = 0;
18504
18505                 if (encoder->get_hw_state(encoder, &pipe)) {
18506                         struct intel_crtc_state *crtc_state;
18507
18508                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18509                         crtc_state = to_intel_crtc_state(crtc->base.state);
18510
18511                         encoder->base.crtc = &crtc->base;
18512                         encoder->get_config(encoder, crtc_state);
18513                 } else {
18514                         encoder->base.crtc = NULL;
18515                 }
18516
18517                 drm_dbg_kms(&dev_priv->drm,
18518                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18519                             encoder->base.base.id, encoder->base.name,
18520                             enableddisabled(encoder->base.crtc),
18521                             pipe_name(pipe));
18522         }
18523
18524         drm_connector_list_iter_begin(dev, &conn_iter);
18525         for_each_intel_connector_iter(connector, &conn_iter) {
18526                 if (connector->get_hw_state(connector)) {
18527                         struct intel_crtc_state *crtc_state;
18528                         struct intel_crtc *crtc;
18529
18530                         connector->base.dpms = DRM_MODE_DPMS_ON;
18531
18532                         encoder = intel_attached_encoder(connector);
18533                         connector->base.encoder = &encoder->base;
18534
18535                         crtc = to_intel_crtc(encoder->base.crtc);
18536                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18537
18538                         if (crtc_state && crtc_state->hw.active) {
18539                                 /*
18540                                  * This has to be done during hardware readout
18541                                  * because anything calling .crtc_disable may
18542                                  * rely on the connector_mask being accurate.
18543                                  */
18544                                 crtc_state->uapi.connector_mask |=
18545                                         drm_connector_mask(&connector->base);
18546                                 crtc_state->uapi.encoder_mask |=
18547                                         drm_encoder_mask(&encoder->base);
18548                         }
18549                 } else {
18550                         connector->base.dpms = DRM_MODE_DPMS_OFF;
18551                         connector->base.encoder = NULL;
18552                 }
18553                 drm_dbg_kms(&dev_priv->drm,
18554                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
18555                             connector->base.base.id, connector->base.name,
18556                             enableddisabled(connector->base.encoder));
18557         }
18558         drm_connector_list_iter_end(&conn_iter);
18559
18560         for_each_intel_crtc(dev, crtc) {
18561                 struct intel_bw_state *bw_state =
18562                         to_intel_bw_state(dev_priv->bw_obj.state);
18563                 struct intel_crtc_state *crtc_state =
18564                         to_intel_crtc_state(crtc->base.state);
18565                 struct intel_plane *plane;
18566                 int min_cdclk = 0;
18567
18568                 if (crtc_state->hw.active) {
18569                         struct drm_display_mode *mode = &crtc_state->hw.mode;
18570
18571                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18572                                                     crtc_state);
18573
18574                         *mode = crtc_state->hw.adjusted_mode;
18575                         mode->hdisplay = crtc_state->pipe_src_w;
18576                         mode->vdisplay = crtc_state->pipe_src_h;
18577
18578                         /*
18579                          * The initial mode needs to be set in order to keep
18580                          * the atomic core happy. It wants a valid mode if the
18581                          * crtc's enabled, so we do the above call.
18582                          *
18583                          * But we don't set all the derived state fully, hence
18584                          * set a flag to indicate that a full recalculation is
18585                          * needed on the next commit.
18586                          */
18587                         crtc_state->inherited = true;
18588
18589                         intel_crtc_compute_pixel_rate(crtc_state);
18590
18591                         intel_crtc_update_active_timings(crtc_state);
18592
18593                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
18594                 }
18595
18596                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18597                         const struct intel_plane_state *plane_state =
18598                                 to_intel_plane_state(plane->base.state);
18599
18600                         /*
18601                          * FIXME don't have the fb yet, so can't
18602                          * use intel_plane_data_rate() :(
18603                          */
18604                         if (plane_state->uapi.visible)
18605                                 crtc_state->data_rate[plane->id] =
18606                                         4 * crtc_state->pixel_rate;
18607                         /*
18608                          * FIXME don't have the fb yet, so can't
18609                          * use plane->min_cdclk() :(
18610                          */
18611                         if (plane_state->uapi.visible && plane->min_cdclk) {
18612                                 if (crtc_state->double_wide ||
18613                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18614                                         crtc_state->min_cdclk[plane->id] =
18615                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18616                                 else
18617                                         crtc_state->min_cdclk[plane->id] =
18618                                                 crtc_state->pixel_rate;
18619                         }
18620                         drm_dbg_kms(&dev_priv->drm,
18621                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
18622                                     plane->base.base.id, plane->base.name,
18623                                     crtc_state->min_cdclk[plane->id]);
18624                 }
18625
18626                 if (crtc_state->hw.active) {
18627                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18628                         if (drm_WARN_ON(dev, min_cdclk < 0))
18629                                 min_cdclk = 0;
18630                 }
18631
18632                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18633                 cdclk_state->min_voltage_level[crtc->pipe] =
18634                         crtc_state->min_voltage_level;
18635
18636                 intel_bw_crtc_update(bw_state, crtc_state);
18637
18638                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18639         }
18640 }
18641
18642 static void
18643 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18644 {
18645         struct intel_encoder *encoder;
18646
18647         for_each_intel_encoder(&dev_priv->drm, encoder) {
18648                 struct intel_crtc_state *crtc_state;
18649
18650                 if (!encoder->get_power_domains)
18651                         continue;
18652
18653                 /*
18654                  * MST-primary and inactive encoders don't have a crtc state
18655                  * and neither of these require any power domain references.
18656                  */
18657                 if (!encoder->base.crtc)
18658                         continue;
18659
18660                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18661                 encoder->get_power_domains(encoder, crtc_state);
18662         }
18663 }
18664
18665 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18666 {
18667         /*
18668          * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18669          * Also known as Wa_14010480278.
18670          */
18671         if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18672                 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18673                                intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18674
18675         if (IS_HASWELL(dev_priv)) {
18676                 /*
18677                  * WaRsPkgCStateDisplayPMReq:hsw
18678                  * System hang if this isn't done before disabling all planes!
18679                  */
18680                 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18681                                intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18682         }
18683 }
18684
18685 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18686                                        enum port port, i915_reg_t hdmi_reg)
18687 {
18688         u32 val = intel_de_read(dev_priv, hdmi_reg);
18689
18690         if (val & SDVO_ENABLE ||
18691             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18692                 return;
18693
18694         drm_dbg_kms(&dev_priv->drm,
18695                     "Sanitizing transcoder select for HDMI %c\n",
18696                     port_name(port));
18697
18698         val &= ~SDVO_PIPE_SEL_MASK;
18699         val |= SDVO_PIPE_SEL(PIPE_A);
18700
18701         intel_de_write(dev_priv, hdmi_reg, val);
18702 }
18703
18704 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18705                                      enum port port, i915_reg_t dp_reg)
18706 {
18707         u32 val = intel_de_read(dev_priv, dp_reg);
18708
18709         if (val & DP_PORT_EN ||
18710             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18711                 return;
18712
18713         drm_dbg_kms(&dev_priv->drm,
18714                     "Sanitizing transcoder select for DP %c\n",
18715                     port_name(port));
18716
18717         val &= ~DP_PIPE_SEL_MASK;
18718         val |= DP_PIPE_SEL(PIPE_A);
18719
18720         intel_de_write(dev_priv, dp_reg, val);
18721 }
18722
18723 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18724 {
18725         /*
18726          * The BIOS may select transcoder B on some of the PCH
18727          * ports even it doesn't enable the port. This would trip
18728          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18729          * Sanitize the transcoder select bits to prevent that. We
18730          * assume that the BIOS never actually enabled the port,
18731          * because if it did we'd actually have to toggle the port
18732          * on and back off to make the transcoder A select stick
18733          * (see. intel_dp_link_down(), intel_disable_hdmi(),
18734          * intel_disable_sdvo()).
18735          */
18736         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18737         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18738         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18739
18740         /* PCH SDVOB multiplex with HDMIB */
18741         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18742         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18743         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18744 }
18745
18746 /* Scan out the current hw modeset state,
18747  * and sanitizes it to the current state
18748  */
18749 static void
18750 intel_modeset_setup_hw_state(struct drm_device *dev,
18751                              struct drm_modeset_acquire_ctx *ctx)
18752 {
18753         struct drm_i915_private *dev_priv = to_i915(dev);
18754         struct intel_encoder *encoder;
18755         struct intel_crtc *crtc;
18756         intel_wakeref_t wakeref;
18757
18758         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18759
18760         intel_early_display_was(dev_priv);
18761         intel_modeset_readout_hw_state(dev);
18762
18763         /* HW state is read out, now we need to sanitize this mess. */
18764
18765         /* Sanitize the TypeC port mode upfront, encoders depend on this */
18766         for_each_intel_encoder(dev, encoder) {
18767                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18768
18769                 /* We need to sanitize only the MST primary port. */
18770                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18771                     intel_phy_is_tc(dev_priv, phy))
18772                         intel_tc_port_sanitize(enc_to_dig_port(encoder));
18773         }
18774
18775         get_encoder_power_domains(dev_priv);
18776
18777         if (HAS_PCH_IBX(dev_priv))
18778                 ibx_sanitize_pch_ports(dev_priv);
18779
18780         /*
18781          * intel_sanitize_plane_mapping() may need to do vblank
18782          * waits, so we need vblank interrupts restored beforehand.
18783          */
18784         for_each_intel_crtc(&dev_priv->drm, crtc) {
18785                 struct intel_crtc_state *crtc_state =
18786                         to_intel_crtc_state(crtc->base.state);
18787
18788                 drm_crtc_vblank_reset(&crtc->base);
18789
18790                 if (crtc_state->hw.active)
18791                         intel_crtc_vblank_on(crtc_state);
18792         }
18793
18794         intel_sanitize_plane_mapping(dev_priv);
18795
18796         for_each_intel_encoder(dev, encoder)
18797                 intel_sanitize_encoder(encoder);
18798
18799         for_each_intel_crtc(&dev_priv->drm, crtc) {
18800                 struct intel_crtc_state *crtc_state =
18801                         to_intel_crtc_state(crtc->base.state);
18802
18803                 intel_sanitize_crtc(crtc, ctx);
18804                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18805         }
18806
18807         intel_modeset_update_connector_atomic_state(dev);
18808
18809         intel_dpll_sanitize_state(dev_priv);
18810
18811         if (IS_G4X(dev_priv)) {
18812                 g4x_wm_get_hw_state(dev_priv);
18813                 g4x_wm_sanitize(dev_priv);
18814         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18815                 vlv_wm_get_hw_state(dev_priv);
18816                 vlv_wm_sanitize(dev_priv);
18817         } else if (INTEL_GEN(dev_priv) >= 9) {
18818                 skl_wm_get_hw_state(dev_priv);
18819         } else if (HAS_PCH_SPLIT(dev_priv)) {
18820                 ilk_wm_get_hw_state(dev_priv);
18821         }
18822
18823         for_each_intel_crtc(dev, crtc) {
18824                 struct intel_crtc_state *crtc_state =
18825                         to_intel_crtc_state(crtc->base.state);
18826                 u64 put_domains;
18827
18828                 put_domains = modeset_get_crtc_power_domains(crtc_state);
18829                 if (drm_WARN_ON(dev, put_domains))
18830                         modeset_put_power_domains(dev_priv, put_domains);
18831         }
18832
18833         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18834 }
18835
18836 void intel_display_resume(struct drm_device *dev)
18837 {
18838         struct drm_i915_private *dev_priv = to_i915(dev);
18839         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18840         struct drm_modeset_acquire_ctx ctx;
18841         int ret;
18842
18843         dev_priv->modeset_restore_state = NULL;
18844         if (state)
18845                 state->acquire_ctx = &ctx;
18846
18847         drm_modeset_acquire_init(&ctx, 0);
18848
18849         while (1) {
18850                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18851                 if (ret != -EDEADLK)
18852                         break;
18853
18854                 drm_modeset_backoff(&ctx);
18855         }
18856
18857         if (!ret)
18858                 ret = __intel_display_resume(dev, state, &ctx);
18859
18860         intel_enable_ipc(dev_priv);
18861         drm_modeset_drop_locks(&ctx);
18862         drm_modeset_acquire_fini(&ctx);
18863
18864         if (ret)
18865                 drm_err(&dev_priv->drm,
18866                         "Restoring old state failed with %i\n", ret);
18867         if (state)
18868                 drm_atomic_state_put(state);
18869 }
18870
18871 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18872 {
18873         struct intel_connector *connector;
18874         struct drm_connector_list_iter conn_iter;
18875
18876         /* Kill all the work that may have been queued by hpd. */
18877         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18878         for_each_intel_connector_iter(connector, &conn_iter) {
18879                 if (connector->modeset_retry_work.func)
18880                         cancel_work_sync(&connector->modeset_retry_work);
18881                 if (connector->hdcp.shim) {
18882                         cancel_delayed_work_sync(&connector->hdcp.check_work);
18883                         cancel_work_sync(&connector->hdcp.prop_work);
18884                 }
18885         }
18886         drm_connector_list_iter_end(&conn_iter);
18887 }
18888
18889 /* part #1: call before irq uninstall */
18890 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18891 {
18892         flush_workqueue(i915->flip_wq);
18893         flush_workqueue(i915->modeset_wq);
18894
18895         flush_work(&i915->atomic_helper.free_work);
18896         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18897 }
18898
18899 /* part #2: call after irq uninstall */
18900 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18901 {
18902         /*
18903          * Due to the hpd irq storm handling the hotplug work can re-arm the
18904          * poll handlers. Hence disable polling after hpd handling is shut down.
18905          */
18906         intel_hpd_poll_fini(i915);
18907
18908         /*
18909          * MST topology needs to be suspended so we don't have any calls to
18910          * fbdev after it's finalized. MST will be destroyed later as part of
18911          * drm_mode_config_cleanup()
18912          */
18913         intel_dp_mst_suspend(i915);
18914
18915         /* poll work can call into fbdev, hence clean that up afterwards */
18916         intel_fbdev_fini(i915);
18917
18918         intel_unregister_dsm_handler();
18919
18920         intel_fbc_global_disable(i915);
18921
18922         /* flush any delayed tasks or pending work */
18923         flush_scheduled_work();
18924
18925         intel_hdcp_component_fini(i915);
18926
18927         intel_mode_config_cleanup(i915);
18928
18929         intel_overlay_cleanup(i915);
18930
18931         intel_gmbus_teardown(i915);
18932
18933         destroy_workqueue(i915->flip_wq);
18934         destroy_workqueue(i915->modeset_wq);
18935
18936         intel_fbc_cleanup_cfb(i915);
18937 }
18938
18939 /* part #3: call after gem init */
18940 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
18941 {
18942         intel_csr_ucode_fini(i915);
18943
18944         intel_power_domains_driver_remove(i915);
18945
18946         intel_vga_unregister(i915);
18947
18948         intel_bios_driver_remove(i915);
18949 }
18950
18951 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18952
18953 struct intel_display_error_state {
18954
18955         u32 power_well_driver;
18956
18957         struct intel_cursor_error_state {
18958                 u32 control;
18959                 u32 position;
18960                 u32 base;
18961                 u32 size;
18962         } cursor[I915_MAX_PIPES];
18963
18964         struct intel_pipe_error_state {
18965                 bool power_domain_on;
18966                 u32 source;
18967                 u32 stat;
18968         } pipe[I915_MAX_PIPES];
18969
18970         struct intel_plane_error_state {
18971                 u32 control;
18972                 u32 stride;
18973                 u32 size;
18974                 u32 pos;
18975                 u32 addr;
18976                 u32 surface;
18977                 u32 tile_offset;
18978         } plane[I915_MAX_PIPES];
18979
18980         struct intel_transcoder_error_state {
18981                 bool available;
18982                 bool power_domain_on;
18983                 enum transcoder cpu_transcoder;
18984
18985                 u32 conf;
18986
18987                 u32 htotal;
18988                 u32 hblank;
18989                 u32 hsync;
18990                 u32 vtotal;
18991                 u32 vblank;
18992                 u32 vsync;
18993         } transcoder[5];
18994 };
18995
18996 struct intel_display_error_state *
18997 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18998 {
18999         struct intel_display_error_state *error;
19000         int transcoders[] = {
19001                 TRANSCODER_A,
19002                 TRANSCODER_B,
19003                 TRANSCODER_C,
19004                 TRANSCODER_D,
19005                 TRANSCODER_EDP,
19006         };
19007         int i;
19008
19009         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19010
19011         if (!HAS_DISPLAY(dev_priv))
19012                 return NULL;
19013
19014         error = kzalloc(sizeof(*error), GFP_ATOMIC);
19015         if (error == NULL)
19016                 return NULL;
19017
19018         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19019                 error->power_well_driver = intel_de_read(dev_priv,
19020                                                          HSW_PWR_WELL_CTL2);
19021
19022         for_each_pipe(dev_priv, i) {
19023                 error->pipe[i].power_domain_on =
19024                         __intel_display_power_is_enabled(dev_priv,
19025                                                          POWER_DOMAIN_PIPE(i));
19026                 if (!error->pipe[i].power_domain_on)
19027                         continue;
19028
19029                 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19030                 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19031                 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19032
19033                 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19034                 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19035                 if (INTEL_GEN(dev_priv) <= 3) {
19036                         error->plane[i].size = intel_de_read(dev_priv,
19037                                                              DSPSIZE(i));
19038                         error->plane[i].pos = intel_de_read(dev_priv,
19039                                                             DSPPOS(i));
19040                 }
19041                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19042                         error->plane[i].addr = intel_de_read(dev_priv,
19043                                                              DSPADDR(i));
19044                 if (INTEL_GEN(dev_priv) >= 4) {
19045                         error->plane[i].surface = intel_de_read(dev_priv,
19046                                                                 DSPSURF(i));
19047                         error->plane[i].tile_offset = intel_de_read(dev_priv,
19048                                                                     DSPTILEOFF(i));
19049                 }
19050
19051                 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19052
19053                 if (HAS_GMCH(dev_priv))
19054                         error->pipe[i].stat = intel_de_read(dev_priv,
19055                                                             PIPESTAT(i));
19056         }
19057
19058         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19059                 enum transcoder cpu_transcoder = transcoders[i];
19060
19061                 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19062                         continue;
19063
19064                 error->transcoder[i].available = true;
19065                 error->transcoder[i].power_domain_on =
19066                         __intel_display_power_is_enabled(dev_priv,
19067                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19068                 if (!error->transcoder[i].power_domain_on)
19069                         continue;
19070
19071                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19072
19073                 error->transcoder[i].conf = intel_de_read(dev_priv,
19074                                                           PIPECONF(cpu_transcoder));
19075                 error->transcoder[i].htotal = intel_de_read(dev_priv,
19076                                                             HTOTAL(cpu_transcoder));
19077                 error->transcoder[i].hblank = intel_de_read(dev_priv,
19078                                                             HBLANK(cpu_transcoder));
19079                 error->transcoder[i].hsync = intel_de_read(dev_priv,
19080                                                            HSYNC(cpu_transcoder));
19081                 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19082                                                             VTOTAL(cpu_transcoder));
19083                 error->transcoder[i].vblank = intel_de_read(dev_priv,
19084                                                             VBLANK(cpu_transcoder));
19085                 error->transcoder[i].vsync = intel_de_read(dev_priv,
19086                                                            VSYNC(cpu_transcoder));
19087         }
19088
19089         return error;
19090 }
19091
19092 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19093
19094 void
19095 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19096                                 struct intel_display_error_state *error)
19097 {
19098         struct drm_i915_private *dev_priv = m->i915;
19099         int i;
19100
19101         if (!error)
19102                 return;
19103
19104         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19105         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19106                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19107                            error->power_well_driver);
19108         for_each_pipe(dev_priv, i) {
19109                 err_printf(m, "Pipe [%d]:\n", i);
19110                 err_printf(m, "  Power: %s\n",
19111                            onoff(error->pipe[i].power_domain_on));
19112                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
19113                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
19114
19115                 err_printf(m, "Plane [%d]:\n", i);
19116                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
19117                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
19118                 if (INTEL_GEN(dev_priv) <= 3) {
19119                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
19120                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
19121                 }
19122                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19123                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
19124                 if (INTEL_GEN(dev_priv) >= 4) {
19125                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
19126                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
19127                 }
19128
19129                 err_printf(m, "Cursor [%d]:\n", i);
19130                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
19131                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
19132                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
19133         }
19134
19135         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19136                 if (!error->transcoder[i].available)
19137                         continue;
19138
19139                 err_printf(m, "CPU transcoder: %s\n",
19140                            transcoder_name(error->transcoder[i].cpu_transcoder));
19141                 err_printf(m, "  Power: %s\n",
19142                            onoff(error->transcoder[i].power_domain_on));
19143                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
19144                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
19145                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
19146                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
19147                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
19148                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
19149                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
19150         }
19151 }
19152
19153 #endif