drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <drm/i915_drm.h>
  45
  46 #include "display/intel_crt.h"
  47 #include "display/intel_ddi.h"
  48 #include "display/intel_dp.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 149                                    struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 168                                     struct intel_crtc_state *crtc_state);
 169 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
 170 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 171 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
 172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 173                                          struct drm_modeset_acquire_ctx *ctx);
 174
 175 struct intel_limit {
 176         struct {
 177                 int min, max;
 178         } dot, vco, n, m, m1, m2, p, p1;
 179
 180         struct {
 181                 int dot_limit;
 182                 int p2_slow, p2_fast;
 183         } p2;
 184 };
 185
 186 /* returns HPLL frequency in kHz */
 187 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 188 {
 189         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 190
 191         /* Obtain SKU information */
 192         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 193                 CCK_FUSE_HPLL_FREQ_MASK;
 194
 195         return vco_freq[hpll_freq] * 1000;
 196 }
 197
 198 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 199                       const char *name, u32 reg, int ref_freq)
 200 {
 201         u32 val;
 202         int divider;
 203
 204         val = vlv_cck_read(dev_priv, reg);
 205         divider = val & CCK_FREQUENCY_VALUES;
 206
 207         WARN((val & CCK_FREQUENCY_STATUS) !=
 208              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 209              "%s change in progress\n", name);
 210
 211         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 212 }
 213
 214 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 215                            const char *name, u32 reg)
 216 {
 217         int hpll;
 218
 219         vlv_cck_get(dev_priv);
 220
 221         if (dev_priv->hpll_freq == 0)
 222                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 223
 224         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 225
 226         vlv_cck_put(dev_priv);
 227
 228         return hpll;
 229 }
 230
 231 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 232 {
 233         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 234                 return;
 235
 236         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 237                                                       CCK_CZ_CLOCK_CONTROL);
 238
 239         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 240 }
 241
 242 static inline u32 /* units of 100MHz */
 243 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 244                     const struct intel_crtc_state *pipe_config)
 245 {
 246         if (HAS_DDI(dev_priv))
 247                 return pipe_config->port_clock; /* SPLL */
 248         else
 249                 return dev_priv->fdi_pll_freq;
 250 }
 251
 252 static const struct intel_limit intel_limits_i8xx_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 2, .max = 33 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 4, .p2_fast = 2 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i8xx_dvo = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 908000, .max = 1512000 },
 268         .n = { .min = 2, .max = 16 },
 269         .m = { .min = 96, .max = 140 },
 270         .m1 = { .min = 18, .max = 26 },
 271         .m2 = { .min = 6, .max = 16 },
 272         .p = { .min = 4, .max = 128 },
 273         .p1 = { .min = 2, .max = 33 },
 274         .p2 = { .dot_limit = 165000,
 275                 .p2_slow = 4, .p2_fast = 4 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i8xx_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 908000, .max = 1512000 },
 281         .n = { .min = 2, .max = 16 },
 282         .m = { .min = 96, .max = 140 },
 283         .m1 = { .min = 18, .max = 26 },
 284         .m2 = { .min = 6, .max = 16 },
 285         .p = { .min = 4, .max = 128 },
 286         .p1 = { .min = 1, .max = 6 },
 287         .p2 = { .dot_limit = 165000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291 static const struct intel_limit intel_limits_i9xx_sdvo = {
 292         .dot = { .min = 20000, .max = 400000 },
 293         .vco = { .min = 1400000, .max = 2800000 },
 294         .n = { .min = 1, .max = 6 },
 295         .m = { .min = 70, .max = 120 },
 296         .m1 = { .min = 8, .max = 18 },
 297         .m2 = { .min = 3, .max = 7 },
 298         .p = { .min = 5, .max = 80 },
 299         .p1 = { .min = 1, .max = 8 },
 300         .p2 = { .dot_limit = 200000,
 301                 .p2_slow = 10, .p2_fast = 5 },
 302 };
 303
 304 static const struct intel_limit intel_limits_i9xx_lvds = {
 305         .dot = { .min = 20000, .max = 400000 },
 306         .vco = { .min = 1400000, .max = 2800000 },
 307         .n = { .min = 1, .max = 6 },
 308         .m = { .min = 70, .max = 120 },
 309         .m1 = { .min = 8, .max = 18 },
 310         .m2 = { .min = 3, .max = 7 },
 311         .p = { .min = 7, .max = 98 },
 312         .p1 = { .min = 1, .max = 8 },
 313         .p2 = { .dot_limit = 112000,
 314                 .p2_slow = 14, .p2_fast = 7 },
 315 };
 316
 317
 318 static const struct intel_limit intel_limits_g4x_sdvo = {
 319         .dot = { .min = 25000, .max = 270000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 17, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 10, .max = 30 },
 326         .p1 = { .min = 1, .max = 3},
 327         .p2 = { .dot_limit = 270000,
 328                 .p2_slow = 10,
 329                 .p2_fast = 10
 330         },
 331 };
 332
 333 static const struct intel_limit intel_limits_g4x_hdmi = {
 334         .dot = { .min = 22000, .max = 400000 },
 335         .vco = { .min = 1750000, .max = 3500000},
 336         .n = { .min = 1, .max = 4 },
 337         .m = { .min = 104, .max = 138 },
 338         .m1 = { .min = 16, .max = 23 },
 339         .m2 = { .min = 5, .max = 11 },
 340         .p = { .min = 5, .max = 80 },
 341         .p1 = { .min = 1, .max = 8},
 342         .p2 = { .dot_limit = 165000,
 343                 .p2_slow = 10, .p2_fast = 5 },
 344 };
 345
 346 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 347         .dot = { .min = 20000, .max = 115000 },
 348         .vco = { .min = 1750000, .max = 3500000 },
 349         .n = { .min = 1, .max = 3 },
 350         .m = { .min = 104, .max = 138 },
 351         .m1 = { .min = 17, .max = 23 },
 352         .m2 = { .min = 5, .max = 11 },
 353         .p = { .min = 28, .max = 112 },
 354         .p1 = { .min = 2, .max = 8 },
 355         .p2 = { .dot_limit = 0,
 356                 .p2_slow = 14, .p2_fast = 14
 357         },
 358 };
 359
 360 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 361         .dot = { .min = 80000, .max = 224000 },
 362         .vco = { .min = 1750000, .max = 3500000 },
 363         .n = { .min = 1, .max = 3 },
 364         .m = { .min = 104, .max = 138 },
 365         .m1 = { .min = 17, .max = 23 },
 366         .m2 = { .min = 5, .max = 11 },
 367         .p = { .min = 14, .max = 42 },
 368         .p1 = { .min = 2, .max = 6 },
 369         .p2 = { .dot_limit = 0,
 370                 .p2_slow = 7, .p2_fast = 7
 371         },
 372 };
 373
 374 static const struct intel_limit intel_limits_pineview_sdvo = {
 375         .dot = { .min = 20000, .max = 400000},
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         /* Pineview's Ncounter is a ring counter */
 378         .n = { .min = 3, .max = 6 },
 379         .m = { .min = 2, .max = 256 },
 380         /* Pineview only has one combined m divider, which we treat as m2. */
 381         .m1 = { .min = 0, .max = 0 },
 382         .m2 = { .min = 0, .max = 254 },
 383         .p = { .min = 5, .max = 80 },
 384         .p1 = { .min = 1, .max = 8 },
 385         .p2 = { .dot_limit = 200000,
 386                 .p2_slow = 10, .p2_fast = 5 },
 387 };
 388
 389 static const struct intel_limit intel_limits_pineview_lvds = {
 390         .dot = { .min = 20000, .max = 400000 },
 391         .vco = { .min = 1700000, .max = 3500000 },
 392         .n = { .min = 3, .max = 6 },
 393         .m = { .min = 2, .max = 256 },
 394         .m1 = { .min = 0, .max = 0 },
 395         .m2 = { .min = 0, .max = 254 },
 396         .p = { .min = 7, .max = 112 },
 397         .p1 = { .min = 1, .max = 8 },
 398         .p2 = { .dot_limit = 112000,
 399                 .p2_slow = 14, .p2_fast = 14 },
 400 };
 401
 402 /* Ironlake / Sandybridge
 403  *
 404  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 405  * the range value for them is (actual_value - 2).
 406  */
 407 static const struct intel_limit intel_limits_ironlake_dac = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 5 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 5, .max = 80 },
 415         .p1 = { .min = 1, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 10, .p2_fast = 5 },
 418 };
 419
 420 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 421         .dot = { .min = 25000, .max = 350000 },
 422         .vco = { .min = 1760000, .max = 3510000 },
 423         .n = { .min = 1, .max = 3 },
 424         .m = { .min = 79, .max = 118 },
 425         .m1 = { .min = 12, .max = 22 },
 426         .m2 = { .min = 5, .max = 9 },
 427         .p = { .min = 28, .max = 112 },
 428         .p1 = { .min = 2, .max = 8 },
 429         .p2 = { .dot_limit = 225000,
 430                 .p2_slow = 14, .p2_fast = 14 },
 431 };
 432
 433 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 434         .dot = { .min = 25000, .max = 350000 },
 435         .vco = { .min = 1760000, .max = 3510000 },
 436         .n = { .min = 1, .max = 3 },
 437         .m = { .min = 79, .max = 127 },
 438         .m1 = { .min = 12, .max = 22 },
 439         .m2 = { .min = 5, .max = 9 },
 440         .p = { .min = 14, .max = 56 },
 441         .p1 = { .min = 2, .max = 8 },
 442         .p2 = { .dot_limit = 225000,
 443                 .p2_slow = 7, .p2_fast = 7 },
 444 };
 445
 446 /* LVDS 100mhz refclk limits. */
 447 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 448         .dot = { .min = 25000, .max = 350000 },
 449         .vco = { .min = 1760000, .max = 3510000 },
 450         .n = { .min = 1, .max = 2 },
 451         .m = { .min = 79, .max = 126 },
 452         .m1 = { .min = 12, .max = 22 },
 453         .m2 = { .min = 5, .max = 9 },
 454         .p = { .min = 28, .max = 112 },
 455         .p1 = { .min = 2, .max = 8 },
 456         .p2 = { .dot_limit = 225000,
 457                 .p2_slow = 14, .p2_fast = 14 },
 458 };
 459
 460 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 461         .dot = { .min = 25000, .max = 350000 },
 462         .vco = { .min = 1760000, .max = 3510000 },
 463         .n = { .min = 1, .max = 3 },
 464         .m = { .min = 79, .max = 126 },
 465         .m1 = { .min = 12, .max = 22 },
 466         .m2 = { .min = 5, .max = 9 },
 467         .p = { .min = 14, .max = 42 },
 468         .p1 = { .min = 2, .max = 6 },
 469         .p2 = { .dot_limit = 225000,
 470                 .p2_slow = 7, .p2_fast = 7 },
 471 };
 472
 473 static const struct intel_limit intel_limits_vlv = {
 474          /*
 475           * These are the data rate limits (measured in fast clocks)
 476           * since those are the strictest limits we have. The fast
 477           * clock and actual rate limits are more relaxed, so checking
 478           * them would make no difference.
 479           */
 480         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 481         .vco = { .min = 4000000, .max = 6000000 },
 482         .n = { .min = 1, .max = 7 },
 483         .m1 = { .min = 2, .max = 3 },
 484         .m2 = { .min = 11, .max = 156 },
 485         .p1 = { .min = 2, .max = 3 },
 486         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 487 };
 488
 489 static const struct intel_limit intel_limits_chv = {
 490         /*
 491          * These are the data rate limits (measured in fast clocks)
 492          * since those are the strictest limits we have.  The fast
 493          * clock and actual rate limits are more relaxed, so checking
 494          * them would make no difference.
 495          */
 496         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 497         .vco = { .min = 4800000, .max = 6480000 },
 498         .n = { .min = 1, .max = 1 },
 499         .m1 = { .min = 2, .max = 2 },
 500         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 501         .p1 = { .min = 2, .max = 4 },
 502         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 503 };
 504
 505 static const struct intel_limit intel_limits_bxt = {
 506         /* FIXME: find real dot limits */
 507         .dot = { .min = 0, .max = INT_MAX },
 508         .vco = { .min = 4800000, .max = 6700000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         /* FIXME: find real m2 limits */
 512         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 513         .p1 = { .min = 2, .max = 4 },
 514         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 515 };
 516
 517 /* WA Display #0827: Gen9:all */
 518 static void
 519 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 520 {
 521         if (enable)
 522                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 523                            I915_READ(CLKGATE_DIS_PSL(pipe)) |
 524                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 525         else
 526                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 527                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 528                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 529 }
 530
 531 /* Wa_2006604312:icl */
 532 static void
 533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 534                        bool enable)
 535 {
 536         if (enable)
 537                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 538                            I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 539         else
 540                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 541                            I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 542 }
 543
 544 static bool
 545 needs_modeset(const struct intel_crtc_state *state)
 546 {
 547         return drm_atomic_crtc_needs_modeset(&state->uapi);
 548 }
 549
 550 bool
 551 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 552 {
 553         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 554                 crtc_state->sync_mode_slaves_mask);
 555 }
 556
 557 static bool
 558 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 559 {
 560         return (crtc_state->master_transcoder == INVALID_TRANSCODER &&
 561                 crtc_state->sync_mode_slaves_mask);
 562 }
 563
 564 static bool
 565 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 566 {
 567         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 568 }
 569
 570 /*
 571  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 572  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 573  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 574  * The helpers' return value is the rate of the clock that is fed to the
 575  * display engine's pipe which can be the above fast dot clock rate or a
 576  * divided-down version of it.
 577  */
 578 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 579 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 580 {
 581         clock->m = clock->m2 + 2;
 582         clock->p = clock->p1 * clock->p2;
 583         if (WARN_ON(clock->n == 0 || clock->p == 0))
 584                 return 0;
 585         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 586         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 587
 588         return clock->dot;
 589 }
 590
 591 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 592 {
 593         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 594 }
 595
 596 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 597 {
 598         clock->m = i9xx_dpll_compute_m(clock);
 599         clock->p = clock->p1 * clock->p2;
 600         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 601                 return 0;
 602         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 603         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 604
 605         return clock->dot;
 606 }
 607
 608 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 609 {
 610         clock->m = clock->m1 * clock->m2;
 611         clock->p = clock->p1 * clock->p2;
 612         if (WARN_ON(clock->n == 0 || clock->p == 0))
 613                 return 0;
 614         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 615         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 616
 617         return clock->dot / 5;
 618 }
 619
 620 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 621 {
 622         clock->m = clock->m1 * clock->m2;
 623         clock->p = clock->p1 * clock->p2;
 624         if (WARN_ON(clock->n == 0 || clock->p == 0))
 625                 return 0;
 626         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 627                                            clock->n << 22);
 628         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 629
 630         return clock->dot / 5;
 631 }
 632
 633 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 634
 635 /*
 636  * Returns whether the given set of divisors are valid for a given refclk with
 637  * the given connectors.
 638  */
 639 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 640                                const struct intel_limit *limit,
 641                                const struct dpll *clock)
 642 {
 643         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 644                 INTELPllInvalid("n out of range\n");
 645         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 646                 INTELPllInvalid("p1 out of range\n");
 647         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 648                 INTELPllInvalid("m2 out of range\n");
 649         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 650                 INTELPllInvalid("m1 out of range\n");
 651
 652         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 653             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 654                 if (clock->m1 <= clock->m2)
 655                         INTELPllInvalid("m1 <= m2\n");
 656
 657         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 658             !IS_GEN9_LP(dev_priv)) {
 659                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 660                         INTELPllInvalid("p out of range\n");
 661                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 662                         INTELPllInvalid("m out of range\n");
 663         }
 664
 665         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 666                 INTELPllInvalid("vco out of range\n");
 667         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 668          * connector, etc., rather than just a single range.
 669          */
 670         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 671                 INTELPllInvalid("dot out of range\n");
 672
 673         return true;
 674 }
 675
 676 static int
 677 i9xx_select_p2_div(const struct intel_limit *limit,
 678                    const struct intel_crtc_state *crtc_state,
 679                    int target)
 680 {
 681         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 682
 683         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 684                 /*
 685                  * For LVDS just rely on its current settings for dual-channel.
 686                  * We haven't figured out how to reliably set up different
 687                  * single/dual channel state, if we even can.
 688                  */
 689                 if (intel_is_dual_link_lvds(dev_priv))
 690                         return limit->p2.p2_fast;
 691                 else
 692                         return limit->p2.p2_slow;
 693         } else {
 694                 if (target < limit->p2.dot_limit)
 695                         return limit->p2.p2_slow;
 696                 else
 697                         return limit->p2.p2_fast;
 698         }
 699 }
 700
 701 /*
 702  * Returns a set of divisors for the desired target clock with the given
 703  * refclk, or FALSE.  The returned values represent the clock equation:
 704  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 705  *
 706  * Target and reference clocks are specified in kHz.
 707  *
 708  * If match_clock is provided, then best_clock P divider must match the P
 709  * divider from @match_clock used for LVDS downclocking.
 710  */
 711 static bool
 712 i9xx_find_best_dpll(const struct intel_limit *limit,
 713                     struct intel_crtc_state *crtc_state,
 714                     int target, int refclk, struct dpll *match_clock,
 715                     struct dpll *best_clock)
 716 {
 717         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 718         struct dpll clock;
 719         int err = target;
 720
 721         memset(best_clock, 0, sizeof(*best_clock));
 722
 723         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 724
 725         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 726              clock.m1++) {
 727                 for (clock.m2 = limit->m2.min;
 728                      clock.m2 <= limit->m2.max; clock.m2++) {
 729                         if (clock.m2 >= clock.m1)
 730                                 break;
 731                         for (clock.n = limit->n.min;
 732                              clock.n <= limit->n.max; clock.n++) {
 733                                 for (clock.p1 = limit->p1.min;
 734                                         clock.p1 <= limit->p1.max; clock.p1++) {
 735                                         int this_err;
 736
 737                                         i9xx_calc_dpll_params(refclk, &clock);
 738                                         if (!intel_PLL_is_valid(to_i915(dev),
 739                                                                 limit,
 740                                                                 &clock))
 741                                                 continue;
 742                                         if (match_clock &&
 743                                             clock.p != match_clock->p)
 744                                                 continue;
 745
 746                                         this_err = abs(clock.dot - target);
 747                                         if (this_err < err) {
 748                                                 *best_clock = clock;
 749                                                 err = this_err;
 750                                         }
 751                                 }
 752                         }
 753                 }
 754         }
 755
 756         return (err != target);
 757 }
 758
 759 /*
 760  * Returns a set of divisors for the desired target clock with the given
 761  * refclk, or FALSE.  The returned values represent the clock equation:
 762  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 763  *
 764  * Target and reference clocks are specified in kHz.
 765  *
 766  * If match_clock is provided, then best_clock P divider must match the P
 767  * divider from @match_clock used for LVDS downclocking.
 768  */
 769 static bool
 770 pnv_find_best_dpll(const struct intel_limit *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, struct dpll *match_clock,
 773                    struct dpll *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 776         struct dpll clock;
 777         int err = target;
 778
 779         memset(best_clock, 0, sizeof(*best_clock));
 780
 781         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 782
 783         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 784              clock.m1++) {
 785                 for (clock.m2 = limit->m2.min;
 786                      clock.m2 <= limit->m2.max; clock.m2++) {
 787                         for (clock.n = limit->n.min;
 788                              clock.n <= limit->n.max; clock.n++) {
 789                                 for (clock.p1 = limit->p1.min;
 790                                         clock.p1 <= limit->p1.max; clock.p1++) {
 791                                         int this_err;
 792
 793                                         pnv_calc_dpll_params(refclk, &clock);
 794                                         if (!intel_PLL_is_valid(to_i915(dev),
 795                                                                 limit,
 796                                                                 &clock))
 797                                                 continue;
 798                                         if (match_clock &&
 799                                             clock.p != match_clock->p)
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err) {
 804                                                 *best_clock = clock;
 805                                                 err = this_err;
 806                                         }
 807                                 }
 808                         }
 809                 }
 810         }
 811
 812         return (err != target);
 813 }
 814
 815 /*
 816  * Returns a set of divisors for the desired target clock with the given
 817  * refclk, or FALSE.  The returned values represent the clock equation:
 818  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 819  *
 820  * Target and reference clocks are specified in kHz.
 821  *
 822  * If match_clock is provided, then best_clock P divider must match the P
 823  * divider from @match_clock used for LVDS downclocking.
 824  */
 825 static bool
 826 g4x_find_best_dpll(const struct intel_limit *limit,
 827                    struct intel_crtc_state *crtc_state,
 828                    int target, int refclk, struct dpll *match_clock,
 829                    struct dpll *best_clock)
 830 {
 831         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 832         struct dpll clock;
 833         int max_n;
 834         bool found = false;
 835         /* approximately equals target * 0.00585 */
 836         int err_most = (target >> 8) + (target >> 9);
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         max_n = limit->n.max;
 843         /* based on hardware requirement, prefer smaller n to precision */
 844         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 845                 /* based on hardware requirement, prefere larger m1,m2 */
 846                 for (clock.m1 = limit->m1.max;
 847                      clock.m1 >= limit->m1.min; clock.m1--) {
 848                         for (clock.m2 = limit->m2.max;
 849                              clock.m2 >= limit->m2.min; clock.m2--) {
 850                                 for (clock.p1 = limit->p1.max;
 851                                      clock.p1 >= limit->p1.min; clock.p1--) {
 852                                         int this_err;
 853
 854                                         i9xx_calc_dpll_params(refclk, &clock);
 855                                         if (!intel_PLL_is_valid(to_i915(dev),
 856                                                                 limit,
 857                                                                 &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err_most) {
 862                                                 *best_clock = clock;
 863                                                 err_most = this_err;
 864                                                 max_n = clock.n;
 865                                                 found = true;
 866                                         }
 867                                 }
 868                         }
 869                 }
 870         }
 871         return found;
 872 }
 873
 874 /*
 875  * Check if the calculated PLL configuration is more optimal compared to the
 876  * best configuration and error found so far. Return the calculated error.
 877  */
 878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 879                                const struct dpll *calculated_clock,
 880                                const struct dpll *best_clock,
 881                                unsigned int best_error_ppm,
 882                                unsigned int *error_ppm)
 883 {
 884         /*
 885          * For CHV ignore the error and consider only the P value.
 886          * Prefer a bigger P value based on HW requirements.
 887          */
 888         if (IS_CHERRYVIEW(to_i915(dev))) {
 889                 *error_ppm = 0;
 890
 891                 return calculated_clock->p > best_clock->p;
 892         }
 893
 894         if (WARN_ON_ONCE(!target_freq))
 895                 return false;
 896
 897         *error_ppm = div_u64(1000000ULL *
 898                                 abs(target_freq - calculated_clock->dot),
 899                              target_freq);
 900         /*
 901          * Prefer a better P value over a better (smaller) error if the error
 902          * is small. Ensure this preference for future configurations too by
 903          * setting the error to 0.
 904          */
 905         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 906                 *error_ppm = 0;
 907
 908                 return true;
 909         }
 910
 911         return *error_ppm + 10 < best_error_ppm;
 912 }
 913
 914 /*
 915  * Returns a set of divisors for the desired target clock with the given
 916  * refclk, or FALSE.  The returned values represent the clock equation:
 917  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 918  */
 919 static bool
 920 vlv_find_best_dpll(const struct intel_limit *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, struct dpll *match_clock,
 923                    struct dpll *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         struct dpll clock;
 928         unsigned int bestppm = 1000000;
 929         /* min update 19.2 MHz */
 930         int max_n = min(limit->n.max, refclk / 19200);
 931         bool found = false;
 932
 933         target *= 5; /* fast clock */
 934
 935         memset(best_clock, 0, sizeof(*best_clock));
 936
 937         /* based on hardware requirement, prefer smaller n to precision */
 938         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 939                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 940                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 941                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                                 clock.p = clock.p1 * clock.p2;
 943                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 944                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 945                                         unsigned int ppm;
 946
 947                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 948                                                                      refclk * clock.m1);
 949
 950                                         vlv_calc_dpll_params(refclk, &clock);
 951
 952                                         if (!intel_PLL_is_valid(to_i915(dev),
 953                                                                 limit,
 954                                                                 &clock))
 955                                                 continue;
 956
 957                                         if (!vlv_PLL_is_optimal(dev, target,
 958                                                                 &clock,
 959                                                                 best_clock,
 960                                                                 bestppm, &ppm))
 961                                                 continue;
 962
 963                                         *best_clock = clock;
 964                                         bestppm = ppm;
 965                                         found = true;
 966                                 }
 967                         }
 968                 }
 969         }
 970
 971         return found;
 972 }
 973
 974 /*
 975  * Returns a set of divisors for the desired target clock with the given
 976  * refclk, or FALSE.  The returned values represent the clock equation:
 977  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 978  */
 979 static bool
 980 chv_find_best_dpll(const struct intel_limit *limit,
 981                    struct intel_crtc_state *crtc_state,
 982                    int target, int refclk, struct dpll *match_clock,
 983                    struct dpll *best_clock)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 986         struct drm_device *dev = crtc->base.dev;
 987         unsigned int best_error_ppm;
 988         struct dpll clock;
 989         u64 m2;
 990         int found = false;
 991
 992         memset(best_clock, 0, sizeof(*best_clock));
 993         best_error_ppm = 1000000;
 994
 995         /*
 996          * Based on hardware doc, the n always set to 1, and m1 always
 997          * set to 2.  If requires to support 200Mhz refclk, we need to
 998          * revisit this because n may not 1 anymore.
 999          */
1000         clock.n = 1, clock.m1 = 2;
1001         target *= 5;    /* fast clock */
1002
1003         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004                 for (clock.p2 = limit->p2.p2_fast;
1005                                 clock.p2 >= limit->p2.p2_slow;
1006                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007                         unsigned int error_ppm;
1008
1009                         clock.p = clock.p1 * clock.p2;
1010
1011                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1012                                                    refclk * clock.m1);
1013
1014                         if (m2 > INT_MAX/clock.m1)
1015                                 continue;
1016
1017                         clock.m2 = m2;
1018
1019                         chv_calc_dpll_params(refclk, &clock);
1020
1021                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1022                                 continue;
1023
1024                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025                                                 best_error_ppm, &error_ppm))
1026                                 continue;
1027
1028                         *best_clock = clock;
1029                         best_error_ppm = error_ppm;
1030                         found = true;
1031                 }
1032         }
1033
1034         return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1038                         struct dpll *best_clock)
1039 {
1040         int refclk = 100000;
1041         const struct intel_limit *limit = &intel_limits_bxt;
1042
1043         return chv_find_best_dpll(limit, crtc_state,
1044                                   crtc_state->port_clock, refclk,
1045                                   NULL, best_clock);
1046 }
1047
1048 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1049                                     enum pipe pipe)
1050 {
1051         i915_reg_t reg = PIPEDSL(pipe);
1052         u32 line1, line2;
1053         u32 line_mask;
1054
1055         if (IS_GEN(dev_priv, 2))
1056                 line_mask = DSL_LINEMASK_GEN2;
1057         else
1058                 line_mask = DSL_LINEMASK_GEN3;
1059
1060         line1 = I915_READ(reg) & line_mask;
1061         msleep(5);
1062         line2 = I915_READ(reg) & line_mask;
1063
1064         return line1 != line2;
1065 }
1066
1067 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1068 {
1069         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1070         enum pipe pipe = crtc->pipe;
1071
1072         /* Wait for the display line to settle/start moving */
1073         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1074                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1075                           pipe_name(pipe), onoff(state));
1076 }
1077
1078 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1079 {
1080         wait_for_pipe_scanline_moving(crtc, false);
1081 }
1082
1083 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1084 {
1085         wait_for_pipe_scanline_moving(crtc, true);
1086 }
1087
1088 static void
1089 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1090 {
1091         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1092         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1093
1094         if (INTEL_GEN(dev_priv) >= 4) {
1095                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1096                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1097
1098                 /* Wait for the Pipe State to go off */
1099                 if (intel_de_wait_for_clear(dev_priv, reg,
1100                                             I965_PIPECONF_ACTIVE, 100))
1101                         WARN(1, "pipe_off wait timed out\n");
1102         } else {
1103                 intel_wait_for_pipe_scanline_stopped(crtc);
1104         }
1105 }
1106
1107 /* Only for pre-ILK configs */
1108 void assert_pll(struct drm_i915_private *dev_priv,
1109                 enum pipe pipe, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113
1114         val = I915_READ(DPLL(pipe));
1115         cur_state = !!(val & DPLL_VCO_ENABLE);
1116         I915_STATE_WARN(cur_state != state,
1117              "PLL state assertion failure (expected %s, current %s)\n",
1118                         onoff(state), onoff(cur_state));
1119 }
1120
1121 /* XXX: the dsi pll is shared between MIPI DSI ports */
1122 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1123 {
1124         u32 val;
1125         bool cur_state;
1126
1127         vlv_cck_get(dev_priv);
1128         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1129         vlv_cck_put(dev_priv);
1130
1131         cur_state = val & DSI_PLL_VCO_EN;
1132         I915_STATE_WARN(cur_state != state,
1133              "DSI PLL state assertion failure (expected %s, current %s)\n",
1134                         onoff(state), onoff(cur_state));
1135 }
1136
1137 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1138                           enum pipe pipe, bool state)
1139 {
1140         bool cur_state;
1141
1142         if (HAS_DDI(dev_priv)) {
1143                 /*
1144                  * DDI does not have a specific FDI_TX register.
1145                  *
1146                  * FDI is never fed from EDP transcoder
1147                  * so pipe->transcoder cast is fine here.
1148                  */
1149                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1150                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1152         } else {
1153                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1154                 cur_state = !!(val & FDI_TX_ENABLE);
1155         }
1156         I915_STATE_WARN(cur_state != state,
1157              "FDI TX state assertion failure (expected %s, current %s)\n",
1158                         onoff(state), onoff(cur_state));
1159 }
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1162
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         u32 val;
1167         bool cur_state;
1168
1169         val = I915_READ(FDI_RX_CTL(pipe));
1170         cur_state = !!(val & FDI_RX_ENABLE);
1171         I915_STATE_WARN(cur_state != state,
1172              "FDI RX state assertion failure (expected %s, current %s)\n",
1173                         onoff(state), onoff(cur_state));
1174 }
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1177
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1179                                       enum pipe pipe)
1180 {
1181         u32 val;
1182
1183         /* ILK FDI PLL is always enabled */
1184         if (IS_GEN(dev_priv, 5))
1185                 return;
1186
1187         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188         if (HAS_DDI(dev_priv))
1189                 return;
1190
1191         val = I915_READ(FDI_TX_CTL(pipe));
1192         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1193 }
1194
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196                        enum pipe pipe, bool state)
1197 {
1198         u32 val;
1199         bool cur_state;
1200
1201         val = I915_READ(FDI_RX_CTL(pipe));
1202         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203         I915_STATE_WARN(cur_state != state,
1204              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205                         onoff(state), onoff(cur_state));
1206 }
1207
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1209 {
1210         i915_reg_t pp_reg;
1211         u32 val;
1212         enum pipe panel_pipe = INVALID_PIPE;
1213         bool locked = true;
1214
1215         if (WARN_ON(HAS_DDI(dev_priv)))
1216                 return;
1217
1218         if (HAS_PCH_SPLIT(dev_priv)) {
1219                 u32 port_sel;
1220
1221                 pp_reg = PP_CONTROL(0);
1222                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1223
1224                 switch (port_sel) {
1225                 case PANEL_PORT_SELECT_LVDS:
1226                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPA:
1229                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1230                         break;
1231                 case PANEL_PORT_SELECT_DPC:
1232                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1233                         break;
1234                 case PANEL_PORT_SELECT_DPD:
1235                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1236                         break;
1237                 default:
1238                         MISSING_CASE(port_sel);
1239                         break;
1240                 }
1241         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242                 /* presumably write lock depends on pipe, not port select */
1243                 pp_reg = PP_CONTROL(pipe);
1244                 panel_pipe = pipe;
1245         } else {
1246                 u32 port_sel;
1247
1248                 pp_reg = PP_CONTROL(0);
1249                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1250
1251                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1252                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1253         }
1254
1255         val = I915_READ(pp_reg);
1256         if (!(val & PANEL_POWER_ON) ||
1257             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1258                 locked = false;
1259
1260         I915_STATE_WARN(panel_pipe == pipe && locked,
1261              "panel assertion failure, pipe %c regs locked\n",
1262              pipe_name(pipe));
1263 }
1264
1265 void assert_pipe(struct drm_i915_private *dev_priv,
1266                  enum transcoder cpu_transcoder, bool state)
1267 {
1268         bool cur_state;
1269         enum intel_display_power_domain power_domain;
1270         intel_wakeref_t wakeref;
1271
1272         /* we keep both pipes enabled on 830 */
1273         if (IS_I830(dev_priv))
1274                 state = true;
1275
1276         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1277         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1278         if (wakeref) {
1279                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1280                 cur_state = !!(val & PIPECONF_ENABLE);
1281
1282                 intel_display_power_put(dev_priv, power_domain, wakeref);
1283         } else {
1284                 cur_state = false;
1285         }
1286
1287         I915_STATE_WARN(cur_state != state,
1288                         "transcoder %s assertion failure (expected %s, current %s)\n",
1289                         transcoder_name(cpu_transcoder),
1290                         onoff(state), onoff(cur_state));
1291 }
1292
1293 static void assert_plane(struct intel_plane *plane, bool state)
1294 {
1295         enum pipe pipe;
1296         bool cur_state;
1297
1298         cur_state = plane->get_hw_state(plane, &pipe);
1299
1300         I915_STATE_WARN(cur_state != state,
1301                         "%s assertion failure (expected %s, current %s)\n",
1302                         plane->base.name, onoff(state), onoff(cur_state));
1303 }
1304
1305 #define assert_plane_enabled(p) assert_plane(p, true)
1306 #define assert_plane_disabled(p) assert_plane(p, false)
1307
1308 static void assert_planes_disabled(struct intel_crtc *crtc)
1309 {
1310         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1311         struct intel_plane *plane;
1312
1313         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1314                 assert_plane_disabled(plane);
1315 }
1316
1317 static void assert_vblank_disabled(struct drm_crtc *crtc)
1318 {
1319         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1320                 drm_crtc_vblank_put(crtc);
1321 }
1322
1323 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1324                                     enum pipe pipe)
1325 {
1326         u32 val;
1327         bool enabled;
1328
1329         val = I915_READ(PCH_TRANSCONF(pipe));
1330         enabled = !!(val & TRANS_ENABLE);
1331         I915_STATE_WARN(enabled,
1332              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333              pipe_name(pipe));
1334 }
1335
1336 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1337                                    enum pipe pipe, enum port port,
1338                                    i915_reg_t dp_reg)
1339 {
1340         enum pipe port_pipe;
1341         bool state;
1342
1343         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1344
1345         I915_STATE_WARN(state && port_pipe == pipe,
1346                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1347                         port_name(port), pipe_name(pipe));
1348
1349         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1350                         "IBX PCH DP %c still using transcoder B\n",
1351                         port_name(port));
1352 }
1353
1354 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1355                                      enum pipe pipe, enum port port,
1356                                      i915_reg_t hdmi_reg)
1357 {
1358         enum pipe port_pipe;
1359         bool state;
1360
1361         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1362
1363         I915_STATE_WARN(state && port_pipe == pipe,
1364                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1365                         port_name(port), pipe_name(pipe));
1366
1367         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1368                         "IBX PCH HDMI %c still using transcoder B\n",
1369                         port_name(port));
1370 }
1371
1372 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1373                                       enum pipe pipe)
1374 {
1375         enum pipe port_pipe;
1376
1377         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1378         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1379         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1380
1381         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1382                         port_pipe == pipe,
1383                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1384                         pipe_name(pipe));
1385
1386         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1387                         port_pipe == pipe,
1388                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1389                         pipe_name(pipe));
1390
1391         /* PCH SDVOB multiplex with HDMIB */
1392         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1393         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1394         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1395 }
1396
1397 static void _vlv_enable_pll(struct intel_crtc *crtc,
1398                             const struct intel_crtc_state *pipe_config)
1399 {
1400         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1401         enum pipe pipe = crtc->pipe;
1402
1403         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1404         POSTING_READ(DPLL(pipe));
1405         udelay(150);
1406
1407         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1408                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1409 }
1410
1411 static void vlv_enable_pll(struct intel_crtc *crtc,
1412                            const struct intel_crtc_state *pipe_config)
1413 {
1414         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1415         enum pipe pipe = crtc->pipe;
1416
1417         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1418
1419         /* PLL is protected by panel, make sure we can write it */
1420         assert_panel_unlocked(dev_priv, pipe);
1421
1422         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1423                 _vlv_enable_pll(crtc, pipe_config);
1424
1425         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1426         POSTING_READ(DPLL_MD(pipe));
1427 }
1428
1429
1430 static void _chv_enable_pll(struct intel_crtc *crtc,
1431                             const struct intel_crtc_state *pipe_config)
1432 {
1433         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1434         enum pipe pipe = crtc->pipe;
1435         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1436         u32 tmp;
1437
1438         vlv_dpio_get(dev_priv);
1439
1440         /* Enable back the 10bit clock to display controller */
1441         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1442         tmp |= DPIO_DCLKP_EN;
1443         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1444
1445         vlv_dpio_put(dev_priv);
1446
1447         /*
1448          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1449          */
1450         udelay(1);
1451
1452         /* Enable PLL */
1453         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1454
1455         /* Check PLL is locked */
1456         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1457                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1458 }
1459
1460 static void chv_enable_pll(struct intel_crtc *crtc,
1461                            const struct intel_crtc_state *pipe_config)
1462 {
1463         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1464         enum pipe pipe = crtc->pipe;
1465
1466         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1467
1468         /* PLL is protected by panel, make sure we can write it */
1469         assert_panel_unlocked(dev_priv, pipe);
1470
1471         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1472                 _chv_enable_pll(crtc, pipe_config);
1473
1474         if (pipe != PIPE_A) {
1475                 /*
1476                  * WaPixelRepeatModeFixForC0:chv
1477                  *
1478                  * DPLLCMD is AWOL. Use chicken bits to propagate
1479                  * the value from DPLLBMD to either pipe B or C.
1480                  */
1481                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1482                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1483                 I915_WRITE(CBR4_VLV, 0);
1484                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1485
1486                 /*
1487                  * DPLLB VGA mode also seems to cause problems.
1488                  * We should always have it disabled.
1489                  */
1490                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1491         } else {
1492                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1493                 POSTING_READ(DPLL_MD(pipe));
1494         }
1495 }
1496
1497 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1498 {
1499         if (IS_I830(dev_priv))
1500                 return false;
1501
1502         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1503 }
1504
1505 static void i9xx_enable_pll(struct intel_crtc *crtc,
1506                             const struct intel_crtc_state *crtc_state)
1507 {
1508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1509         i915_reg_t reg = DPLL(crtc->pipe);
1510         u32 dpll = crtc_state->dpll_hw_state.dpll;
1511         int i;
1512
1513         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1514
1515         /* PLL is protected by panel, make sure we can write it */
1516         if (i9xx_has_pps(dev_priv))
1517                 assert_panel_unlocked(dev_priv, crtc->pipe);
1518
1519         /*
1520          * Apparently we need to have VGA mode enabled prior to changing
1521          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1522          * dividers, even though the register value does change.
1523          */
1524         I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1525         I915_WRITE(reg, dpll);
1526
1527         /* Wait for the clocks to stabilize. */
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (INTEL_GEN(dev_priv) >= 4) {
1532                 I915_WRITE(DPLL_MD(crtc->pipe),
1533                            crtc_state->dpll_hw_state.dpll_md);
1534         } else {
1535                 /* The pixel multiplier can only be updated once the
1536                  * DPLL is enabled and the clocks are stable.
1537                  *
1538                  * So write it again.
1539                  */
1540                 I915_WRITE(reg, dpll);
1541         }
1542
1543         /* We do this three times for luck */
1544         for (i = 0; i < 3; i++) {
1545                 I915_WRITE(reg, dpll);
1546                 POSTING_READ(reg);
1547                 udelay(150); /* wait for warmup */
1548         }
1549 }
1550
1551 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1552 {
1553         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1554         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1555         enum pipe pipe = crtc->pipe;
1556
1557         /* Don't disable pipe or pipe PLLs if needed */
1558         if (IS_I830(dev_priv))
1559                 return;
1560
1561         /* Make sure the pipe isn't still relying on us */
1562         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1563
1564         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1565         POSTING_READ(DPLL(pipe));
1566 }
1567
1568 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1569 {
1570         u32 val;
1571
1572         /* Make sure the pipe isn't still relying on us */
1573         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1574
1575         val = DPLL_INTEGRATED_REF_CLK_VLV |
1576                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1577         if (pipe != PIPE_A)
1578                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1579
1580         I915_WRITE(DPLL(pipe), val);
1581         POSTING_READ(DPLL(pipe));
1582 }
1583
1584 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1585 {
1586         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1587         u32 val;
1588
1589         /* Make sure the pipe isn't still relying on us */
1590         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1591
1592         val = DPLL_SSC_REF_CLK_CHV |
1593                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1594         if (pipe != PIPE_A)
1595                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1596
1597         I915_WRITE(DPLL(pipe), val);
1598         POSTING_READ(DPLL(pipe));
1599
1600         vlv_dpio_get(dev_priv);
1601
1602         /* Disable 10bit clock to display controller */
1603         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1604         val &= ~DPIO_DCLKP_EN;
1605         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1606
1607         vlv_dpio_put(dev_priv);
1608 }
1609
1610 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1611                          struct intel_digital_port *dport,
1612                          unsigned int expected_mask)
1613 {
1614         u32 port_mask;
1615         i915_reg_t dpll_reg;
1616
1617         switch (dport->base.port) {
1618         case PORT_B:
1619                 port_mask = DPLL_PORTB_READY_MASK;
1620                 dpll_reg = DPLL(0);
1621                 break;
1622         case PORT_C:
1623                 port_mask = DPLL_PORTC_READY_MASK;
1624                 dpll_reg = DPLL(0);
1625                 expected_mask <<= 4;
1626                 break;
1627         case PORT_D:
1628                 port_mask = DPLL_PORTD_READY_MASK;
1629                 dpll_reg = DPIO_PHY_STATUS;
1630                 break;
1631         default:
1632                 BUG();
1633         }
1634
1635         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1636                                        port_mask, expected_mask, 1000))
1637                 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1638                      dport->base.base.base.id, dport->base.base.name,
1639                      I915_READ(dpll_reg) & port_mask, expected_mask);
1640 }
1641
1642 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1643 {
1644         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1645         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1646         enum pipe pipe = crtc->pipe;
1647         i915_reg_t reg;
1648         u32 val, pipeconf_val;
1649
1650         /* Make sure PCH DPLL is enabled */
1651         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1652
1653         /* FDI must be feeding us bits for PCH ports */
1654         assert_fdi_tx_enabled(dev_priv, pipe);
1655         assert_fdi_rx_enabled(dev_priv, pipe);
1656
1657         if (HAS_PCH_CPT(dev_priv)) {
1658                 reg = TRANS_CHICKEN2(pipe);
1659                 val = I915_READ(reg);
1660                 /*
1661                  * Workaround: Set the timing override bit
1662                  * before enabling the pch transcoder.
1663                  */
1664                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1665                 /* Configure frame start delay to match the CPU */
1666                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1667                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1668                 I915_WRITE(reg, val);
1669         }
1670
1671         reg = PCH_TRANSCONF(pipe);
1672         val = I915_READ(reg);
1673         pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675         if (HAS_PCH_IBX(dev_priv)) {
1676                 /* Configure frame start delay to match the CPU */
1677                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1678                 val |= TRANS_FRAME_START_DELAY(0);
1679
1680                 /*
1681                  * Make the BPC in transcoder be consistent with
1682                  * that in pipeconf reg. For HDMI we must use 8bpc
1683                  * here for both 8bpc and 12bpc.
1684                  */
1685                 val &= ~PIPECONF_BPC_MASK;
1686                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1687                         val |= PIPECONF_8BPC;
1688                 else
1689                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1690         }
1691
1692         val &= ~TRANS_INTERLACE_MASK;
1693         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1694                 if (HAS_PCH_IBX(dev_priv) &&
1695                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1696                         val |= TRANS_LEGACY_INTERLACED_ILK;
1697                 else
1698                         val |= TRANS_INTERLACED;
1699         } else {
1700                 val |= TRANS_PROGRESSIVE;
1701         }
1702
1703         I915_WRITE(reg, val | TRANS_ENABLE);
1704         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1705                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1706 }
1707
1708 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1709                                       enum transcoder cpu_transcoder)
1710 {
1711         u32 val, pipeconf_val;
1712
1713         /* FDI must be feeding us bits for PCH ports */
1714         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1716
1717         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1718         /* Workaround: set timing override bit. */
1719         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720         /* Configure frame start delay to match the CPU */
1721         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1722         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1723         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1724
1725         val = TRANS_ENABLE;
1726         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1727
1728         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1729             PIPECONF_INTERLACED_ILK)
1730                 val |= TRANS_INTERLACED;
1731         else
1732                 val |= TRANS_PROGRESSIVE;
1733
1734         I915_WRITE(LPT_TRANSCONF, val);
1735         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1736                                   TRANS_STATE_ENABLE, 100))
1737                 DRM_ERROR("Failed to enable PCH transcoder\n");
1738 }
1739
1740 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1741                                             enum pipe pipe)
1742 {
1743         i915_reg_t reg;
1744         u32 val;
1745
1746         /* FDI relies on the transcoder */
1747         assert_fdi_tx_disabled(dev_priv, pipe);
1748         assert_fdi_rx_disabled(dev_priv, pipe);
1749
1750         /* Ports must be off as well */
1751         assert_pch_ports_disabled(dev_priv, pipe);
1752
1753         reg = PCH_TRANSCONF(pipe);
1754         val = I915_READ(reg);
1755         val &= ~TRANS_ENABLE;
1756         I915_WRITE(reg, val);
1757         /* wait for PCH transcoder off, transcoder state */
1758         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1759                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1760
1761         if (HAS_PCH_CPT(dev_priv)) {
1762                 /* Workaround: Clear the timing override chicken bit again. */
1763                 reg = TRANS_CHICKEN2(pipe);
1764                 val = I915_READ(reg);
1765                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1766                 I915_WRITE(reg, val);
1767         }
1768 }
1769
1770 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1771 {
1772         u32 val;
1773
1774         val = I915_READ(LPT_TRANSCONF);
1775         val &= ~TRANS_ENABLE;
1776         I915_WRITE(LPT_TRANSCONF, val);
1777         /* wait for PCH transcoder off, transcoder state */
1778         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1779                                     TRANS_STATE_ENABLE, 50))
1780                 DRM_ERROR("Failed to disable PCH transcoder\n");
1781
1782         /* Workaround: clear timing override bit. */
1783         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1785         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786 }
1787
1788 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1789 {
1790         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1791
1792         if (HAS_PCH_LPT(dev_priv))
1793                 return PIPE_A;
1794         else
1795                 return crtc->pipe;
1796 }
1797
1798 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1799 {
1800         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1801
1802         /*
1803          * On i965gm the hardware frame counter reads
1804          * zero when the TV encoder is enabled :(
1805          */
1806         if (IS_I965GM(dev_priv) &&
1807             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1808                 return 0;
1809
1810         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1811                 return 0xffffffff; /* full 32 bit counter */
1812         else if (INTEL_GEN(dev_priv) >= 3)
1813                 return 0xffffff; /* only 24 bits of frame count */
1814         else
1815                 return 0; /* Gen2 doesn't have a hardware frame counter */
1816 }
1817
1818 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1819 {
1820         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1821
1822         assert_vblank_disabled(&crtc->base);
1823         drm_crtc_set_max_vblank_count(&crtc->base,
1824                                       intel_crtc_max_vblank_count(crtc_state));
1825         drm_crtc_vblank_on(&crtc->base);
1826 }
1827
1828 static void intel_crtc_vblank_off(struct intel_crtc *crtc)
1829 {
1830         drm_crtc_vblank_off(&crtc->base);
1831         assert_vblank_disabled(&crtc->base);
1832 }
1833
1834 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1835 {
1836         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1837         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1838         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1839         enum pipe pipe = crtc->pipe;
1840         i915_reg_t reg;
1841         u32 val;
1842
1843         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1844
1845         assert_planes_disabled(crtc);
1846
1847         /*
1848          * A pipe without a PLL won't actually be able to drive bits from
1849          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1850          * need the check.
1851          */
1852         if (HAS_GMCH(dev_priv)) {
1853                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1854                         assert_dsi_pll_enabled(dev_priv);
1855                 else
1856                         assert_pll_enabled(dev_priv, pipe);
1857         } else {
1858                 if (new_crtc_state->has_pch_encoder) {
1859                         /* if driving the PCH, we need FDI enabled */
1860                         assert_fdi_rx_pll_enabled(dev_priv,
1861                                                   intel_crtc_pch_transcoder(crtc));
1862                         assert_fdi_tx_pll_enabled(dev_priv,
1863                                                   (enum pipe) cpu_transcoder);
1864                 }
1865                 /* FIXME: assert CPU port conditions for SNB+ */
1866         }
1867
1868         trace_intel_pipe_enable(crtc);
1869
1870         reg = PIPECONF(cpu_transcoder);
1871         val = I915_READ(reg);
1872         if (val & PIPECONF_ENABLE) {
1873                 /* we keep both pipes enabled on 830 */
1874                 WARN_ON(!IS_I830(dev_priv));
1875                 return;
1876         }
1877
1878         I915_WRITE(reg, val | PIPECONF_ENABLE);
1879         POSTING_READ(reg);
1880
1881         /*
1882          * Until the pipe starts PIPEDSL reads will return a stale value,
1883          * which causes an apparent vblank timestamp jump when PIPEDSL
1884          * resets to its proper value. That also messes up the frame count
1885          * when it's derived from the timestamps. So let's wait for the
1886          * pipe to start properly before we call drm_crtc_vblank_on()
1887          */
1888         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1889                 intel_wait_for_pipe_scanline_moving(crtc);
1890 }
1891
1892 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1893 {
1894         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1895         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1897         enum pipe pipe = crtc->pipe;
1898         i915_reg_t reg;
1899         u32 val;
1900
1901         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1902
1903         /*
1904          * Make sure planes won't keep trying to pump pixels to us,
1905          * or we might hang the display.
1906          */
1907         assert_planes_disabled(crtc);
1908
1909         trace_intel_pipe_disable(crtc);
1910
1911         reg = PIPECONF(cpu_transcoder);
1912         val = I915_READ(reg);
1913         if ((val & PIPECONF_ENABLE) == 0)
1914                 return;
1915
1916         /*
1917          * Double wide has implications for planes
1918          * so best keep it disabled when not needed.
1919          */
1920         if (old_crtc_state->double_wide)
1921                 val &= ~PIPECONF_DOUBLE_WIDE;
1922
1923         /* Don't disable pipe or pipe PLLs if needed */
1924         if (!IS_I830(dev_priv))
1925                 val &= ~PIPECONF_ENABLE;
1926
1927         I915_WRITE(reg, val);
1928         if ((val & PIPECONF_ENABLE) == 0)
1929                 intel_wait_for_pipe_off(old_crtc_state);
1930 }
1931
1932 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1933 {
1934         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1935 }
1936
1937 static unsigned int
1938 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1939 {
1940         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1941         unsigned int cpp = fb->format->cpp[color_plane];
1942
1943         switch (fb->modifier) {
1944         case DRM_FORMAT_MOD_LINEAR:
1945                 return intel_tile_size(dev_priv);
1946         case I915_FORMAT_MOD_X_TILED:
1947                 if (IS_GEN(dev_priv, 2))
1948                         return 128;
1949                 else
1950                         return 512;
1951         case I915_FORMAT_MOD_Y_TILED_CCS:
1952                 if (color_plane == 1)
1953                         return 128;
1954                 /* fall through */
1955         case I915_FORMAT_MOD_Y_TILED:
1956                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1957                         return 128;
1958                 else
1959                         return 512;
1960         case I915_FORMAT_MOD_Yf_TILED_CCS:
1961                 if (color_plane == 1)
1962                         return 128;
1963                 /* fall through */
1964         case I915_FORMAT_MOD_Yf_TILED:
1965                 switch (cpp) {
1966                 case 1:
1967                         return 64;
1968                 case 2:
1969                 case 4:
1970                         return 128;
1971                 case 8:
1972                 case 16:
1973                         return 256;
1974                 default:
1975                         MISSING_CASE(cpp);
1976                         return cpp;
1977                 }
1978                 break;
1979         default:
1980                 MISSING_CASE(fb->modifier);
1981                 return cpp;
1982         }
1983 }
1984
1985 static unsigned int
1986 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1987 {
1988         return intel_tile_size(to_i915(fb->dev)) /
1989                 intel_tile_width_bytes(fb, color_plane);
1990 }
1991
1992 /* Return the tile dimensions in pixel units */
1993 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1994                             unsigned int *tile_width,
1995                             unsigned int *tile_height)
1996 {
1997         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1998         unsigned int cpp = fb->format->cpp[color_plane];
1999
2000         *tile_width = tile_width_bytes / cpp;
2001         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2002 }
2003
2004 unsigned int
2005 intel_fb_align_height(const struct drm_framebuffer *fb,
2006                       int color_plane, unsigned int height)
2007 {
2008         unsigned int tile_height = intel_tile_height(fb, color_plane);
2009
2010         return ALIGN(height, tile_height);
2011 }
2012
2013 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2014 {
2015         unsigned int size = 0;
2016         int i;
2017
2018         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2019                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2020
2021         return size;
2022 }
2023
2024 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2025 {
2026         unsigned int size = 0;
2027         int i;
2028
2029         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2030                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2031
2032         return size;
2033 }
2034
2035 static void
2036 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2037                         const struct drm_framebuffer *fb,
2038                         unsigned int rotation)
2039 {
2040         view->type = I915_GGTT_VIEW_NORMAL;
2041         if (drm_rotation_90_or_270(rotation)) {
2042                 view->type = I915_GGTT_VIEW_ROTATED;
2043                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2044         }
2045 }
2046
2047 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2048 {
2049         if (IS_I830(dev_priv))
2050                 return 16 * 1024;
2051         else if (IS_I85X(dev_priv))
2052                 return 256;
2053         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2054                 return 32;
2055         else
2056                 return 4 * 1024;
2057 }
2058
2059 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2060 {
2061         if (INTEL_GEN(dev_priv) >= 9)
2062                 return 256 * 1024;
2063         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2064                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2065                 return 128 * 1024;
2066         else if (INTEL_GEN(dev_priv) >= 4)
2067                 return 4 * 1024;
2068         else
2069                 return 0;
2070 }
2071
2072 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2073                                          int color_plane)
2074 {
2075         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2076
2077         /* AUX_DIST needs only 4K alignment */
2078         if (color_plane == 1)
2079                 return 4096;
2080
2081         switch (fb->modifier) {
2082         case DRM_FORMAT_MOD_LINEAR:
2083                 return intel_linear_alignment(dev_priv);
2084         case I915_FORMAT_MOD_X_TILED:
2085                 if (INTEL_GEN(dev_priv) >= 9)
2086                         return 256 * 1024;
2087                 return 0;
2088         case I915_FORMAT_MOD_Y_TILED_CCS:
2089         case I915_FORMAT_MOD_Yf_TILED_CCS:
2090         case I915_FORMAT_MOD_Y_TILED:
2091         case I915_FORMAT_MOD_Yf_TILED:
2092                 return 1 * 1024 * 1024;
2093         default:
2094                 MISSING_CASE(fb->modifier);
2095                 return 0;
2096         }
2097 }
2098
2099 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2100 {
2101         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2102         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2103
2104         return INTEL_GEN(dev_priv) < 4 ||
2105                 (plane->has_fbc &&
2106                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2107 }
2108
2109 struct i915_vma *
2110 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2111                            const struct i915_ggtt_view *view,
2112                            bool uses_fence,
2113                            unsigned long *out_flags)
2114 {
2115         struct drm_device *dev = fb->dev;
2116         struct drm_i915_private *dev_priv = to_i915(dev);
2117         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2118         intel_wakeref_t wakeref;
2119         struct i915_vma *vma;
2120         unsigned int pinctl;
2121         u32 alignment;
2122
2123         if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2124                 return ERR_PTR(-EINVAL);
2125
2126         alignment = intel_surf_alignment(fb, 0);
2127
2128         /* Note that the w/a also requires 64 PTE of padding following the
2129          * bo. We currently fill all unused PTE with the shadow page and so
2130          * we should always have valid PTE following the scanout preventing
2131          * the VT-d warning.
2132          */
2133         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2134                 alignment = 256 * 1024;
2135
2136         /*
2137          * Global gtt pte registers are special registers which actually forward
2138          * writes to a chunk of system memory. Which means that there is no risk
2139          * that the register values disappear as soon as we call
2140          * intel_runtime_pm_put(), so it is correct to wrap only the
2141          * pin/unpin/fence and not more.
2142          */
2143         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2144
2145         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2146
2147         /*
2148          * Valleyview is definitely limited to scanning out the first
2149          * 512MiB. Lets presume this behaviour was inherited from the
2150          * g4x display engine and that all earlier gen are similarly
2151          * limited. Testing suggests that it is a little more
2152          * complicated than this. For example, Cherryview appears quite
2153          * happy to scanout from anywhere within its global aperture.
2154          */
2155         pinctl = 0;
2156         if (HAS_GMCH(dev_priv))
2157                 pinctl |= PIN_MAPPABLE;
2158
2159         vma = i915_gem_object_pin_to_display_plane(obj,
2160                                                    alignment, view, pinctl);
2161         if (IS_ERR(vma))
2162                 goto err;
2163
2164         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2165                 int ret;
2166
2167                 /*
2168                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2169                  * fence, whereas 965+ only requires a fence if using
2170                  * framebuffer compression.  For simplicity, we always, when
2171                  * possible, install a fence as the cost is not that onerous.
2172                  *
2173                  * If we fail to fence the tiled scanout, then either the
2174                  * modeset will reject the change (which is highly unlikely as
2175                  * the affected systems, all but one, do not have unmappable
2176                  * space) or we will not be able to enable full powersaving
2177                  * techniques (also likely not to apply due to various limits
2178                  * FBC and the like impose on the size of the buffer, which
2179                  * presumably we violated anyway with this unmappable buffer).
2180                  * Anyway, it is presumably better to stumble onwards with
2181                  * something and try to run the system in a "less than optimal"
2182                  * mode that matches the user configuration.
2183                  */
2184                 ret = i915_vma_pin_fence(vma);
2185                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2186                         i915_gem_object_unpin_from_display_plane(vma);
2187                         vma = ERR_PTR(ret);
2188                         goto err;
2189                 }
2190
2191                 if (ret == 0 && vma->fence)
2192                         *out_flags |= PLANE_HAS_FENCE;
2193         }
2194
2195         i915_vma_get(vma);
2196 err:
2197         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2198         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2199         return vma;
2200 }
2201
2202 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2203 {
2204         i915_gem_object_lock(vma->obj);
2205         if (flags & PLANE_HAS_FENCE)
2206                 i915_vma_unpin_fence(vma);
2207         i915_gem_object_unpin_from_display_plane(vma);
2208         i915_gem_object_unlock(vma->obj);
2209
2210         i915_vma_put(vma);
2211 }
2212
2213 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2214                           unsigned int rotation)
2215 {
2216         if (drm_rotation_90_or_270(rotation))
2217                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2218         else
2219                 return fb->pitches[color_plane];
2220 }
2221
2222 /*
2223  * Convert the x/y offsets into a linear offset.
2224  * Only valid with 0/180 degree rotation, which is fine since linear
2225  * offset is only used with linear buffers on pre-hsw and tiled buffers
2226  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2227  */
2228 u32 intel_fb_xy_to_linear(int x, int y,
2229                           const struct intel_plane_state *state,
2230                           int color_plane)
2231 {
2232         const struct drm_framebuffer *fb = state->hw.fb;
2233         unsigned int cpp = fb->format->cpp[color_plane];
2234         unsigned int pitch = state->color_plane[color_plane].stride;
2235
2236         return y * pitch + x * cpp;
2237 }
2238
2239 /*
2240  * Add the x/y offsets derived from fb->offsets[] to the user
2241  * specified plane src x/y offsets. The resulting x/y offsets
2242  * specify the start of scanout from the beginning of the gtt mapping.
2243  */
2244 void intel_add_fb_offsets(int *x, int *y,
2245                           const struct intel_plane_state *state,
2246                           int color_plane)
2247
2248 {
2249         *x += state->color_plane[color_plane].x;
2250         *y += state->color_plane[color_plane].y;
2251 }
2252
2253 static u32 intel_adjust_tile_offset(int *x, int *y,
2254                                     unsigned int tile_width,
2255                                     unsigned int tile_height,
2256                                     unsigned int tile_size,
2257                                     unsigned int pitch_tiles,
2258                                     u32 old_offset,
2259                                     u32 new_offset)
2260 {
2261         unsigned int pitch_pixels = pitch_tiles * tile_width;
2262         unsigned int tiles;
2263
2264         WARN_ON(old_offset & (tile_size - 1));
2265         WARN_ON(new_offset & (tile_size - 1));
2266         WARN_ON(new_offset > old_offset);
2267
2268         tiles = (old_offset - new_offset) / tile_size;
2269
2270         *y += tiles / pitch_tiles * tile_height;
2271         *x += tiles % pitch_tiles * tile_width;
2272
2273         /* minimize x in case it got needlessly big */
2274         *y += *x / pitch_pixels * tile_height;
2275         *x %= pitch_pixels;
2276
2277         return new_offset;
2278 }
2279
2280 static bool is_surface_linear(u64 modifier, int color_plane)
2281 {
2282         return modifier == DRM_FORMAT_MOD_LINEAR;
2283 }
2284
2285 static u32 intel_adjust_aligned_offset(int *x, int *y,
2286                                        const struct drm_framebuffer *fb,
2287                                        int color_plane,
2288                                        unsigned int rotation,
2289                                        unsigned int pitch,
2290                                        u32 old_offset, u32 new_offset)
2291 {
2292         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2293         unsigned int cpp = fb->format->cpp[color_plane];
2294
2295         WARN_ON(new_offset > old_offset);
2296
2297         if (!is_surface_linear(fb->modifier, color_plane)) {
2298                 unsigned int tile_size, tile_width, tile_height;
2299                 unsigned int pitch_tiles;
2300
2301                 tile_size = intel_tile_size(dev_priv);
2302                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2303
2304                 if (drm_rotation_90_or_270(rotation)) {
2305                         pitch_tiles = pitch / tile_height;
2306                         swap(tile_width, tile_height);
2307                 } else {
2308                         pitch_tiles = pitch / (tile_width * cpp);
2309                 }
2310
2311                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2312                                          tile_size, pitch_tiles,
2313                                          old_offset, new_offset);
2314         } else {
2315                 old_offset += *y * pitch + *x * cpp;
2316
2317                 *y = (old_offset - new_offset) / pitch;
2318                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2319         }
2320
2321         return new_offset;
2322 }
2323
2324 /*
2325  * Adjust the tile offset by moving the difference into
2326  * the x/y offsets.
2327  */
2328 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2329                                              const struct intel_plane_state *state,
2330                                              int color_plane,
2331                                              u32 old_offset, u32 new_offset)
2332 {
2333         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2334                                            state->hw.rotation,
2335                                            state->color_plane[color_plane].stride,
2336                                            old_offset, new_offset);
2337 }
2338
2339 /*
2340  * Computes the aligned offset to the base tile and adjusts
2341  * x, y. bytes per pixel is assumed to be a power-of-two.
2342  *
2343  * In the 90/270 rotated case, x and y are assumed
2344  * to be already rotated to match the rotated GTT view, and
2345  * pitch is the tile_height aligned framebuffer height.
2346  *
2347  * This function is used when computing the derived information
2348  * under intel_framebuffer, so using any of that information
2349  * here is not allowed. Anything under drm_framebuffer can be
2350  * used. This is why the user has to pass in the pitch since it
2351  * is specified in the rotated orientation.
2352  */
2353 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2354                                         int *x, int *y,
2355                                         const struct drm_framebuffer *fb,
2356                                         int color_plane,
2357                                         unsigned int pitch,
2358                                         unsigned int rotation,
2359                                         u32 alignment)
2360 {
2361         unsigned int cpp = fb->format->cpp[color_plane];
2362         u32 offset, offset_aligned;
2363
2364         if (alignment)
2365                 alignment--;
2366
2367         if (!is_surface_linear(fb->modifier, color_plane)) {
2368                 unsigned int tile_size, tile_width, tile_height;
2369                 unsigned int tile_rows, tiles, pitch_tiles;
2370
2371                 tile_size = intel_tile_size(dev_priv);
2372                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2373
2374                 if (drm_rotation_90_or_270(rotation)) {
2375                         pitch_tiles = pitch / tile_height;
2376                         swap(tile_width, tile_height);
2377                 } else {
2378                         pitch_tiles = pitch / (tile_width * cpp);
2379                 }
2380
2381                 tile_rows = *y / tile_height;
2382                 *y %= tile_height;
2383
2384                 tiles = *x / tile_width;
2385                 *x %= tile_width;
2386
2387                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2388                 offset_aligned = offset & ~alignment;
2389
2390                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2391                                          tile_size, pitch_tiles,
2392                                          offset, offset_aligned);
2393         } else {
2394                 offset = *y * pitch + *x * cpp;
2395                 offset_aligned = offset & ~alignment;
2396
2397                 *y = (offset & alignment) / pitch;
2398                 *x = ((offset & alignment) - *y * pitch) / cpp;
2399         }
2400
2401         return offset_aligned;
2402 }
2403
2404 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2405                                               const struct intel_plane_state *state,
2406                                               int color_plane)
2407 {
2408         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2409         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2410         const struct drm_framebuffer *fb = state->hw.fb;
2411         unsigned int rotation = state->hw.rotation;
2412         int pitch = state->color_plane[color_plane].stride;
2413         u32 alignment;
2414
2415         if (intel_plane->id == PLANE_CURSOR)
2416                 alignment = intel_cursor_alignment(dev_priv);
2417         else
2418                 alignment = intel_surf_alignment(fb, color_plane);
2419
2420         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2421                                             pitch, rotation, alignment);
2422 }
2423
2424 /* Convert the fb->offset[] into x/y offsets */
2425 static int intel_fb_offset_to_xy(int *x, int *y,
2426                                  const struct drm_framebuffer *fb,
2427                                  int color_plane)
2428 {
2429         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2430         unsigned int height;
2431
2432         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2433             fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2434                 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2435                               fb->offsets[color_plane], color_plane);
2436                 return -EINVAL;
2437         }
2438
2439         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2440         height = ALIGN(height, intel_tile_height(fb, color_plane));
2441
2442         /* Catch potential overflows early */
2443         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2444                             fb->offsets[color_plane])) {
2445                 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2446                               fb->offsets[color_plane], fb->pitches[color_plane],
2447                               color_plane);
2448                 return -ERANGE;
2449         }
2450
2451         *x = 0;
2452         *y = 0;
2453
2454         intel_adjust_aligned_offset(x, y,
2455                                     fb, color_plane, DRM_MODE_ROTATE_0,
2456                                     fb->pitches[color_plane],
2457                                     fb->offsets[color_plane], 0);
2458
2459         return 0;
2460 }
2461
2462 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2463 {
2464         switch (fb_modifier) {
2465         case I915_FORMAT_MOD_X_TILED:
2466                 return I915_TILING_X;
2467         case I915_FORMAT_MOD_Y_TILED:
2468         case I915_FORMAT_MOD_Y_TILED_CCS:
2469                 return I915_TILING_Y;
2470         default:
2471                 return I915_TILING_NONE;
2472         }
2473 }
2474
2475 /*
2476  * From the Sky Lake PRM:
2477  * "The Color Control Surface (CCS) contains the compression status of
2478  *  the cache-line pairs. The compression state of the cache-line pair
2479  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2480  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2481  *  cache-line-pairs. CCS is always Y tiled."
2482  *
2483  * Since cache line pairs refers to horizontally adjacent cache lines,
2484  * each cache line in the CCS corresponds to an area of 32x16 cache
2485  * lines on the main surface. Since each pixel is 4 bytes, this gives
2486  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2487  * main surface.
2488  */
2489 static const struct drm_format_info ccs_formats[] = {
2490         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2491           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2493           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2494         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2495           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2496         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2497           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2498 };
2499
2500 static const struct drm_format_info *
2501 lookup_format_info(const struct drm_format_info formats[],
2502                    int num_formats, u32 format)
2503 {
2504         int i;
2505
2506         for (i = 0; i < num_formats; i++) {
2507                 if (formats[i].format == format)
2508                         return &formats[i];
2509         }
2510
2511         return NULL;
2512 }
2513
2514 static const struct drm_format_info *
2515 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2516 {
2517         switch (cmd->modifier[0]) {
2518         case I915_FORMAT_MOD_Y_TILED_CCS:
2519         case I915_FORMAT_MOD_Yf_TILED_CCS:
2520                 return lookup_format_info(ccs_formats,
2521                                           ARRAY_SIZE(ccs_formats),
2522                                           cmd->pixel_format);
2523         default:
2524                 return NULL;
2525         }
2526 }
2527
2528 bool is_ccs_modifier(u64 modifier)
2529 {
2530         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2531                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2532 }
2533
2534 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2535                               u32 pixel_format, u64 modifier)
2536 {
2537         struct intel_crtc *crtc;
2538         struct intel_plane *plane;
2539
2540         /*
2541          * We assume the primary plane for pipe A has
2542          * the highest stride limits of them all.
2543          */
2544         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2545         if (!crtc)
2546                 return 0;
2547
2548         plane = to_intel_plane(crtc->base.primary);
2549
2550         return plane->max_stride(plane, pixel_format, modifier,
2551                                  DRM_MODE_ROTATE_0);
2552 }
2553
2554 static
2555 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2556                         u32 pixel_format, u64 modifier)
2557 {
2558         /*
2559          * Arbitrary limit for gen4+ chosen to match the
2560          * render engine max stride.
2561          *
2562          * The new CCS hash mode makes remapping impossible
2563          */
2564         if (!is_ccs_modifier(modifier)) {
2565                 if (INTEL_GEN(dev_priv) >= 7)
2566                         return 256*1024;
2567                 else if (INTEL_GEN(dev_priv) >= 4)
2568                         return 128*1024;
2569         }
2570
2571         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2572 }
2573
2574 static u32
2575 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2576 {
2577         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2578
2579         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2580                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2581                                                            fb->format->format,
2582                                                            fb->modifier);
2583
2584                 /*
2585                  * To make remapping with linear generally feasible
2586                  * we need the stride to be page aligned.
2587                  */
2588                 if (fb->pitches[color_plane] > max_stride)
2589                         return intel_tile_size(dev_priv);
2590                 else
2591                         return 64;
2592         } else {
2593                 return intel_tile_width_bytes(fb, color_plane);
2594         }
2595 }
2596
2597 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2598 {
2599         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2600         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2601         const struct drm_framebuffer *fb = plane_state->hw.fb;
2602         int i;
2603
2604         /* We don't want to deal with remapping with cursors */
2605         if (plane->id == PLANE_CURSOR)
2606                 return false;
2607
2608         /*
2609          * The display engine limits already match/exceed the
2610          * render engine limits, so not much point in remapping.
2611          * Would also need to deal with the fence POT alignment
2612          * and gen2 2KiB GTT tile size.
2613          */
2614         if (INTEL_GEN(dev_priv) < 4)
2615                 return false;
2616
2617         /*
2618          * The new CCS hash mode isn't compatible with remapping as
2619          * the virtual address of the pages affects the compressed data.
2620          */
2621         if (is_ccs_modifier(fb->modifier))
2622                 return false;
2623
2624         /* Linear needs a page aligned stride for remapping */
2625         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2626                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2627
2628                 for (i = 0; i < fb->format->num_planes; i++) {
2629                         if (fb->pitches[i] & alignment)
2630                                 return false;
2631                 }
2632         }
2633
2634         return true;
2635 }
2636
2637 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2638 {
2639         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2640         const struct drm_framebuffer *fb = plane_state->hw.fb;
2641         unsigned int rotation = plane_state->hw.rotation;
2642         u32 stride, max_stride;
2643
2644         /*
2645          * No remapping for invisible planes since we don't have
2646          * an actual source viewport to remap.
2647          */
2648         if (!plane_state->uapi.visible)
2649                 return false;
2650
2651         if (!intel_plane_can_remap(plane_state))
2652                 return false;
2653
2654         /*
2655          * FIXME: aux plane limits on gen9+ are
2656          * unclear in Bspec, for now no checking.
2657          */
2658         stride = intel_fb_pitch(fb, 0, rotation);
2659         max_stride = plane->max_stride(plane, fb->format->format,
2660                                        fb->modifier, rotation);
2661
2662         return stride > max_stride;
2663 }
2664
2665 static int
2666 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2667                    struct drm_framebuffer *fb)
2668 {
2669         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2670         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2671         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2672         u32 gtt_offset_rotated = 0;
2673         unsigned int max_size = 0;
2674         int i, num_planes = fb->format->num_planes;
2675         unsigned int tile_size = intel_tile_size(dev_priv);
2676
2677         for (i = 0; i < num_planes; i++) {
2678                 unsigned int width, height;
2679                 unsigned int cpp, size;
2680                 u32 offset;
2681                 int x, y;
2682                 int ret;
2683
2684                 cpp = fb->format->cpp[i];
2685                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2686                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2687
2688                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2689                 if (ret) {
2690                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2691                                       i, fb->offsets[i]);
2692                         return ret;
2693                 }
2694
2695                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2696                         int hsub = fb->format->hsub;
2697                         int vsub = fb->format->vsub;
2698                         int tile_width, tile_height;
2699                         int main_x, main_y;
2700                         int ccs_x, ccs_y;
2701
2702                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2703                         tile_width *= hsub;
2704                         tile_height *= vsub;
2705
2706                         ccs_x = (x * hsub) % tile_width;
2707                         ccs_y = (y * vsub) % tile_height;
2708                         main_x = intel_fb->normal[0].x % tile_width;
2709                         main_y = intel_fb->normal[0].y % tile_height;
2710
2711                         /*
2712                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2713                          * x/y offsets must match between CCS and the main surface.
2714                          */
2715                         if (main_x != ccs_x || main_y != ccs_y) {
2716                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2717                                               main_x, main_y,
2718                                               ccs_x, ccs_y,
2719                                               intel_fb->normal[0].x,
2720                                               intel_fb->normal[0].y,
2721                                               x, y);
2722                                 return -EINVAL;
2723                         }
2724                 }
2725
2726                 /*
2727                  * The fence (if used) is aligned to the start of the object
2728                  * so having the framebuffer wrap around across the edge of the
2729                  * fenced region doesn't really work. We have no API to configure
2730                  * the fence start offset within the object (nor could we probably
2731                  * on gen2/3). So it's just easier if we just require that the
2732                  * fb layout agrees with the fence layout. We already check that the
2733                  * fb stride matches the fence stride elsewhere.
2734                  */
2735                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2736                     (x + width) * cpp > fb->pitches[i]) {
2737                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2738                                       i, fb->offsets[i]);
2739                         return -EINVAL;
2740                 }
2741
2742                 /*
2743                  * First pixel of the framebuffer from
2744                  * the start of the normal gtt mapping.
2745                  */
2746                 intel_fb->normal[i].x = x;
2747                 intel_fb->normal[i].y = y;
2748
2749                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2750                                                       fb->pitches[i],
2751                                                       DRM_MODE_ROTATE_0,
2752                                                       tile_size);
2753                 offset /= tile_size;
2754
2755                 if (!is_surface_linear(fb->modifier, i)) {
2756                         unsigned int tile_width, tile_height;
2757                         unsigned int pitch_tiles;
2758                         struct drm_rect r;
2759
2760                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2761
2762                         rot_info->plane[i].offset = offset;
2763                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2764                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2765                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2766
2767                         intel_fb->rotated[i].pitch =
2768                                 rot_info->plane[i].height * tile_height;
2769
2770                         /* how many tiles does this plane need */
2771                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2772                         /*
2773                          * If the plane isn't horizontally tile aligned,
2774                          * we need one more tile.
2775                          */
2776                         if (x != 0)
2777                                 size++;
2778
2779                         /* rotate the x/y offsets to match the GTT view */
2780                         drm_rect_init(&r, x, y, width, height);
2781                         drm_rect_rotate(&r,
2782                                         rot_info->plane[i].width * tile_width,
2783                                         rot_info->plane[i].height * tile_height,
2784                                         DRM_MODE_ROTATE_270);
2785                         x = r.x1;
2786                         y = r.y1;
2787
2788                         /* rotate the tile dimensions to match the GTT view */
2789                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2790                         swap(tile_width, tile_height);
2791
2792                         /*
2793                          * We only keep the x/y offsets, so push all of the
2794                          * gtt offset into the x/y offsets.
2795                          */
2796                         intel_adjust_tile_offset(&x, &y,
2797                                                  tile_width, tile_height,
2798                                                  tile_size, pitch_tiles,
2799                                                  gtt_offset_rotated * tile_size, 0);
2800
2801                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2802
2803                         /*
2804                          * First pixel of the framebuffer from
2805                          * the start of the rotated gtt mapping.
2806                          */
2807                         intel_fb->rotated[i].x = x;
2808                         intel_fb->rotated[i].y = y;
2809                 } else {
2810                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2811                                             x * cpp, tile_size);
2812                 }
2813
2814                 /* how many tiles in total needed in the bo */
2815                 max_size = max(max_size, offset + size);
2816         }
2817
2818         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2819                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2820                               mul_u32_u32(max_size, tile_size), obj->base.size);
2821                 return -EINVAL;
2822         }
2823
2824         return 0;
2825 }
2826
2827 static void
2828 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2829 {
2830         struct drm_i915_private *dev_priv =
2831                 to_i915(plane_state->uapi.plane->dev);
2832         struct drm_framebuffer *fb = plane_state->hw.fb;
2833         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2834         struct intel_rotation_info *info = &plane_state->view.rotated;
2835         unsigned int rotation = plane_state->hw.rotation;
2836         int i, num_planes = fb->format->num_planes;
2837         unsigned int tile_size = intel_tile_size(dev_priv);
2838         unsigned int src_x, src_y;
2839         unsigned int src_w, src_h;
2840         u32 gtt_offset = 0;
2841
2842         memset(&plane_state->view, 0, sizeof(plane_state->view));
2843         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2844                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2845
2846         src_x = plane_state->uapi.src.x1 >> 16;
2847         src_y = plane_state->uapi.src.y1 >> 16;
2848         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2849         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
2850
2851         WARN_ON(is_ccs_modifier(fb->modifier));
2852
2853         /* Make src coordinates relative to the viewport */
2854         drm_rect_translate(&plane_state->uapi.src,
2855                            -(src_x << 16), -(src_y << 16));
2856
2857         /* Rotate src coordinates to match rotated GTT view */
2858         if (drm_rotation_90_or_270(rotation))
2859                 drm_rect_rotate(&plane_state->uapi.src,
2860                                 src_w << 16, src_h << 16,
2861                                 DRM_MODE_ROTATE_270);
2862
2863         for (i = 0; i < num_planes; i++) {
2864                 unsigned int hsub = i ? fb->format->hsub : 1;
2865                 unsigned int vsub = i ? fb->format->vsub : 1;
2866                 unsigned int cpp = fb->format->cpp[i];
2867                 unsigned int tile_width, tile_height;
2868                 unsigned int width, height;
2869                 unsigned int pitch_tiles;
2870                 unsigned int x, y;
2871                 u32 offset;
2872
2873                 intel_tile_dims(fb, i, &tile_width, &tile_height);
2874
2875                 x = src_x / hsub;
2876                 y = src_y / vsub;
2877                 width = src_w / hsub;
2878                 height = src_h / vsub;
2879
2880                 /*
2881                  * First pixel of the src viewport from the
2882                  * start of the normal gtt mapping.
2883                  */
2884                 x += intel_fb->normal[i].x;
2885                 y += intel_fb->normal[i].y;
2886
2887                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2888                                                       fb, i, fb->pitches[i],
2889                                                       DRM_MODE_ROTATE_0, tile_size);
2890                 offset /= tile_size;
2891
2892                 info->plane[i].offset = offset;
2893                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2894                                                      tile_width * cpp);
2895                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2896                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2897
2898                 if (drm_rotation_90_or_270(rotation)) {
2899                         struct drm_rect r;
2900
2901                         /* rotate the x/y offsets to match the GTT view */
2902                         drm_rect_init(&r, x, y, width, height);
2903                         drm_rect_rotate(&r,
2904                                         info->plane[i].width * tile_width,
2905                                         info->plane[i].height * tile_height,
2906                                         DRM_MODE_ROTATE_270);
2907                         x = r.x1;
2908                         y = r.y1;
2909
2910                         pitch_tiles = info->plane[i].height;
2911                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2912
2913                         /* rotate the tile dimensions to match the GTT view */
2914                         swap(tile_width, tile_height);
2915                 } else {
2916                         pitch_tiles = info->plane[i].width;
2917                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2918                 }
2919
2920                 /*
2921                  * We only keep the x/y offsets, so push all of the
2922                  * gtt offset into the x/y offsets.
2923                  */
2924                 intel_adjust_tile_offset(&x, &y,
2925                                          tile_width, tile_height,
2926                                          tile_size, pitch_tiles,
2927                                          gtt_offset * tile_size, 0);
2928
2929                 gtt_offset += info->plane[i].width * info->plane[i].height;
2930
2931                 plane_state->color_plane[i].offset = 0;
2932                 plane_state->color_plane[i].x = x;
2933                 plane_state->color_plane[i].y = y;
2934         }
2935 }
2936
2937 static int
2938 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2939 {
2940         const struct intel_framebuffer *fb =
2941                 to_intel_framebuffer(plane_state->hw.fb);
2942         unsigned int rotation = plane_state->hw.rotation;
2943         int i, num_planes;
2944
2945         if (!fb)
2946                 return 0;
2947
2948         num_planes = fb->base.format->num_planes;
2949
2950         if (intel_plane_needs_remap(plane_state)) {
2951                 intel_plane_remap_gtt(plane_state);
2952
2953                 /*
2954                  * Sometimes even remapping can't overcome
2955                  * the stride limitations :( Can happen with
2956                  * big plane sizes and suitably misaligned
2957                  * offsets.
2958                  */
2959                 return intel_plane_check_stride(plane_state);
2960         }
2961
2962         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2963
2964         for (i = 0; i < num_planes; i++) {
2965                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2966                 plane_state->color_plane[i].offset = 0;
2967
2968                 if (drm_rotation_90_or_270(rotation)) {
2969                         plane_state->color_plane[i].x = fb->rotated[i].x;
2970                         plane_state->color_plane[i].y = fb->rotated[i].y;
2971                 } else {
2972                         plane_state->color_plane[i].x = fb->normal[i].x;
2973                         plane_state->color_plane[i].y = fb->normal[i].y;
2974                 }
2975         }
2976
2977         /* Rotate src coordinates to match rotated GTT view */
2978         if (drm_rotation_90_or_270(rotation))
2979                 drm_rect_rotate(&plane_state->uapi.src,
2980                                 fb->base.width << 16, fb->base.height << 16,
2981                                 DRM_MODE_ROTATE_270);
2982
2983         return intel_plane_check_stride(plane_state);
2984 }
2985
2986 static int i9xx_format_to_fourcc(int format)
2987 {
2988         switch (format) {
2989         case DISPPLANE_8BPP:
2990                 return DRM_FORMAT_C8;
2991         case DISPPLANE_BGRA555:
2992                 return DRM_FORMAT_ARGB1555;
2993         case DISPPLANE_BGRX555:
2994                 return DRM_FORMAT_XRGB1555;
2995         case DISPPLANE_BGRX565:
2996                 return DRM_FORMAT_RGB565;
2997         default:
2998         case DISPPLANE_BGRX888:
2999                 return DRM_FORMAT_XRGB8888;
3000         case DISPPLANE_RGBX888:
3001                 return DRM_FORMAT_XBGR8888;
3002         case DISPPLANE_BGRA888:
3003                 return DRM_FORMAT_ARGB8888;
3004         case DISPPLANE_RGBA888:
3005                 return DRM_FORMAT_ABGR8888;
3006         case DISPPLANE_BGRX101010:
3007                 return DRM_FORMAT_XRGB2101010;
3008         case DISPPLANE_RGBX101010:
3009                 return DRM_FORMAT_XBGR2101010;
3010         case DISPPLANE_BGRA101010:
3011                 return DRM_FORMAT_ARGB2101010;
3012         case DISPPLANE_RGBA101010:
3013                 return DRM_FORMAT_ABGR2101010;
3014         case DISPPLANE_RGBX161616:
3015                 return DRM_FORMAT_XBGR16161616F;
3016         }
3017 }
3018
3019 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3020 {
3021         switch (format) {
3022         case PLANE_CTL_FORMAT_RGB_565:
3023                 return DRM_FORMAT_RGB565;
3024         case PLANE_CTL_FORMAT_NV12:
3025                 return DRM_FORMAT_NV12;
3026         case PLANE_CTL_FORMAT_P010:
3027                 return DRM_FORMAT_P010;
3028         case PLANE_CTL_FORMAT_P012:
3029                 return DRM_FORMAT_P012;
3030         case PLANE_CTL_FORMAT_P016:
3031                 return DRM_FORMAT_P016;
3032         case PLANE_CTL_FORMAT_Y210:
3033                 return DRM_FORMAT_Y210;
3034         case PLANE_CTL_FORMAT_Y212:
3035                 return DRM_FORMAT_Y212;
3036         case PLANE_CTL_FORMAT_Y216:
3037                 return DRM_FORMAT_Y216;
3038         case PLANE_CTL_FORMAT_Y410:
3039                 return DRM_FORMAT_XVYU2101010;
3040         case PLANE_CTL_FORMAT_Y412:
3041                 return DRM_FORMAT_XVYU12_16161616;
3042         case PLANE_CTL_FORMAT_Y416:
3043                 return DRM_FORMAT_XVYU16161616;
3044         default:
3045         case PLANE_CTL_FORMAT_XRGB_8888:
3046                 if (rgb_order) {
3047                         if (alpha)
3048                                 return DRM_FORMAT_ABGR8888;
3049                         else
3050                                 return DRM_FORMAT_XBGR8888;
3051                 } else {
3052                         if (alpha)
3053                                 return DRM_FORMAT_ARGB8888;
3054                         else
3055                                 return DRM_FORMAT_XRGB8888;
3056                 }
3057         case PLANE_CTL_FORMAT_XRGB_2101010:
3058                 if (rgb_order) {
3059                         if (alpha)
3060                                 return DRM_FORMAT_ABGR2101010;
3061                         else
3062                                 return DRM_FORMAT_XBGR2101010;
3063                 } else {
3064                         if (alpha)
3065                                 return DRM_FORMAT_ARGB2101010;
3066                         else
3067                                 return DRM_FORMAT_XRGB2101010;
3068                 }
3069         case PLANE_CTL_FORMAT_XRGB_16161616F:
3070                 if (rgb_order) {
3071                         if (alpha)
3072                                 return DRM_FORMAT_ABGR16161616F;
3073                         else
3074                                 return DRM_FORMAT_XBGR16161616F;
3075                 } else {
3076                         if (alpha)
3077                                 return DRM_FORMAT_ARGB16161616F;
3078                         else
3079                                 return DRM_FORMAT_XRGB16161616F;
3080                 }
3081         }
3082 }
3083
3084 static bool
3085 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3086                               struct intel_initial_plane_config *plane_config)
3087 {
3088         struct drm_device *dev = crtc->base.dev;
3089         struct drm_i915_private *dev_priv = to_i915(dev);
3090         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3091         struct drm_framebuffer *fb = &plane_config->fb->base;
3092         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3093         u32 size_aligned = round_up(plane_config->base + plane_config->size,
3094                                     PAGE_SIZE);
3095         struct drm_i915_gem_object *obj;
3096         bool ret = false;
3097
3098         size_aligned -= base_aligned;
3099
3100         if (plane_config->size == 0)
3101                 return false;
3102
3103         /* If the FB is too big, just don't use it since fbdev is not very
3104          * important and we should probably use that space with FBC or other
3105          * features. */
3106         if (size_aligned * 2 > dev_priv->stolen_usable_size)
3107                 return false;
3108
3109         switch (fb->modifier) {
3110         case DRM_FORMAT_MOD_LINEAR:
3111         case I915_FORMAT_MOD_X_TILED:
3112         case I915_FORMAT_MOD_Y_TILED:
3113                 break;
3114         default:
3115                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3116                                  fb->modifier);
3117                 return false;
3118         }
3119
3120         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3121                                                              base_aligned,
3122                                                              base_aligned,
3123                                                              size_aligned);
3124         if (IS_ERR(obj))
3125                 return false;
3126
3127         switch (plane_config->tiling) {
3128         case I915_TILING_NONE:
3129                 break;
3130         case I915_TILING_X:
3131         case I915_TILING_Y:
3132                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3133                 break;
3134         default:
3135                 MISSING_CASE(plane_config->tiling);
3136                 goto out;
3137         }
3138
3139         mode_cmd.pixel_format = fb->format->format;
3140         mode_cmd.width = fb->width;
3141         mode_cmd.height = fb->height;
3142         mode_cmd.pitches[0] = fb->pitches[0];
3143         mode_cmd.modifier[0] = fb->modifier;
3144         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3145
3146         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3147                 DRM_DEBUG_KMS("intel fb init failed\n");
3148                 goto out;
3149         }
3150
3151
3152         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3153         ret = true;
3154 out:
3155         i915_gem_object_put(obj);
3156         return ret;
3157 }
3158
3159 static void
3160 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3161                         struct intel_plane_state *plane_state,
3162                         bool visible)
3163 {
3164         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3165
3166         plane_state->uapi.visible = visible;
3167
3168         if (visible)
3169                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3170         else
3171                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3172 }
3173
3174 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3175 {
3176         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3177         struct drm_plane *plane;
3178
3179         /*
3180          * Active_planes aliases if multiple "primary" or cursor planes
3181          * have been used on the same (or wrong) pipe. plane_mask uses
3182          * unique ids, hence we can use that to reconstruct active_planes.
3183          */
3184         crtc_state->active_planes = 0;
3185
3186         drm_for_each_plane_mask(plane, &dev_priv->drm,
3187                                 crtc_state->uapi.plane_mask)
3188                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3189 }
3190
3191 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3192                                          struct intel_plane *plane)
3193 {
3194         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195         struct intel_crtc_state *crtc_state =
3196                 to_intel_crtc_state(crtc->base.state);
3197         struct intel_plane_state *plane_state =
3198                 to_intel_plane_state(plane->base.state);
3199
3200         DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3201                       plane->base.base.id, plane->base.name,
3202                       crtc->base.base.id, crtc->base.name);
3203
3204         intel_set_plane_visible(crtc_state, plane_state, false);
3205         fixup_active_planes(crtc_state);
3206         crtc_state->data_rate[plane->id] = 0;
3207         crtc_state->min_cdclk[plane->id] = 0;
3208
3209         if (plane->id == PLANE_PRIMARY)
3210                 hsw_disable_ips(crtc_state);
3211
3212         /*
3213          * Vblank time updates from the shadow to live plane control register
3214          * are blocked if the memory self-refresh mode is active at that
3215          * moment. So to make sure the plane gets truly disabled, disable
3216          * first the self-refresh mode. The self-refresh enable bit in turn
3217          * will be checked/applied by the HW only at the next frame start
3218          * event which is after the vblank start event, so we need to have a
3219          * wait-for-vblank between disabling the plane and the pipe.
3220          */
3221         if (HAS_GMCH(dev_priv) &&
3222             intel_set_memory_cxsr(dev_priv, false))
3223                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3224
3225         /*
3226          * Gen2 reports pipe underruns whenever all planes are disabled.
3227          * So disable underrun reporting before all the planes get disabled.
3228          */
3229         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3230                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3231
3232         intel_disable_plane(plane, crtc_state);
3233 }
3234
3235 static struct intel_frontbuffer *
3236 to_intel_frontbuffer(struct drm_framebuffer *fb)
3237 {
3238         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3239 }
3240
3241 static void
3242 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3243                              struct intel_initial_plane_config *plane_config)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247         struct drm_crtc *c;
3248         struct drm_plane *primary = intel_crtc->base.primary;
3249         struct drm_plane_state *plane_state = primary->state;
3250         struct intel_plane *intel_plane = to_intel_plane(primary);
3251         struct intel_plane_state *intel_state =
3252                 to_intel_plane_state(plane_state);
3253         struct drm_framebuffer *fb;
3254
3255         if (!plane_config->fb)
3256                 return;
3257
3258         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3259                 fb = &plane_config->fb->base;
3260                 goto valid_fb;
3261         }
3262
3263         kfree(plane_config->fb);
3264
3265         /*
3266          * Failed to alloc the obj, check to see if we should share
3267          * an fb with another CRTC instead
3268          */
3269         for_each_crtc(dev, c) {
3270                 struct intel_plane_state *state;
3271
3272                 if (c == &intel_crtc->base)
3273                         continue;
3274
3275                 if (!to_intel_crtc(c)->active)
3276                         continue;
3277
3278                 state = to_intel_plane_state(c->primary->state);
3279                 if (!state->vma)
3280                         continue;
3281
3282                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3283                         fb = state->hw.fb;
3284                         drm_framebuffer_get(fb);
3285                         goto valid_fb;
3286                 }
3287         }
3288
3289         /*
3290          * We've failed to reconstruct the BIOS FB.  Current display state
3291          * indicates that the primary plane is visible, but has a NULL FB,
3292          * which will lead to problems later if we don't fix it up.  The
3293          * simplest solution is to just disable the primary plane now and
3294          * pretend the BIOS never had it enabled.
3295          */
3296         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3297
3298         return;
3299
3300 valid_fb:
3301         intel_state->hw.rotation = plane_config->rotation;
3302         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3303                                 intel_state->hw.rotation);
3304         intel_state->color_plane[0].stride =
3305                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3306
3307         intel_state->vma =
3308                 intel_pin_and_fence_fb_obj(fb,
3309                                            &intel_state->view,
3310                                            intel_plane_uses_fence(intel_state),
3311                                            &intel_state->flags);
3312         if (IS_ERR(intel_state->vma)) {
3313                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3314                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
3315
3316                 intel_state->vma = NULL;
3317                 drm_framebuffer_put(fb);
3318                 return;
3319         }
3320
3321         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3322
3323         plane_state->src_x = 0;
3324         plane_state->src_y = 0;
3325         plane_state->src_w = fb->width << 16;
3326         plane_state->src_h = fb->height << 16;
3327
3328         plane_state->crtc_x = 0;
3329         plane_state->crtc_y = 0;
3330         plane_state->crtc_w = fb->width;
3331         plane_state->crtc_h = fb->height;
3332
3333         intel_state->uapi.src = drm_plane_state_src(plane_state);
3334         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3335
3336         if (plane_config->tiling)
3337                 dev_priv->preserve_bios_swizzle = true;
3338
3339         plane_state->fb = fb;
3340         plane_state->crtc = &intel_crtc->base;
3341         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3342
3343         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3344                   &to_intel_frontbuffer(fb)->bits);
3345 }
3346
3347 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3348                                int color_plane,
3349                                unsigned int rotation)
3350 {
3351         int cpp = fb->format->cpp[color_plane];
3352
3353         switch (fb->modifier) {
3354         case DRM_FORMAT_MOD_LINEAR:
3355         case I915_FORMAT_MOD_X_TILED:
3356                 /*
3357                  * Validated limit is 4k, but has 5k should
3358                  * work apart from the following features:
3359                  * - Ytile (already limited to 4k)
3360                  * - FP16 (already limited to 4k)
3361                  * - render compression (already limited to 4k)
3362                  * - KVMR sprite and cursor (don't care)
3363                  * - horizontal panning (TODO verify this)
3364                  * - pipe and plane scaling (TODO verify this)
3365                  */
3366                 if (cpp == 8)
3367                         return 4096;
3368                 else
3369                         return 5120;
3370         case I915_FORMAT_MOD_Y_TILED_CCS:
3371         case I915_FORMAT_MOD_Yf_TILED_CCS:
3372                 /* FIXME AUX plane? */
3373         case I915_FORMAT_MOD_Y_TILED:
3374         case I915_FORMAT_MOD_Yf_TILED:
3375                 if (cpp == 8)
3376                         return 2048;
3377                 else
3378                         return 4096;
3379         default:
3380                 MISSING_CASE(fb->modifier);
3381                 return 2048;
3382         }
3383 }
3384
3385 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3386                                int color_plane,
3387                                unsigned int rotation)
3388 {
3389         int cpp = fb->format->cpp[color_plane];
3390
3391         switch (fb->modifier) {
3392         case DRM_FORMAT_MOD_LINEAR:
3393         case I915_FORMAT_MOD_X_TILED:
3394                 if (cpp == 8)
3395                         return 4096;
3396                 else
3397                         return 5120;
3398         case I915_FORMAT_MOD_Y_TILED_CCS:
3399         case I915_FORMAT_MOD_Yf_TILED_CCS:
3400                 /* FIXME AUX plane? */
3401         case I915_FORMAT_MOD_Y_TILED:
3402         case I915_FORMAT_MOD_Yf_TILED:
3403                 if (cpp == 8)
3404                         return 2048;
3405                 else
3406                         return 5120;
3407         default:
3408                 MISSING_CASE(fb->modifier);
3409                 return 2048;
3410         }
3411 }
3412
3413 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3414                                int color_plane,
3415                                unsigned int rotation)
3416 {
3417         return 5120;
3418 }
3419
3420 static int skl_max_plane_height(void)
3421 {
3422         return 4096;
3423 }
3424
3425 static int icl_max_plane_height(void)
3426 {
3427         return 4320;
3428 }
3429
3430 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3431                                            int main_x, int main_y, u32 main_offset)
3432 {
3433         const struct drm_framebuffer *fb = plane_state->hw.fb;
3434         int hsub = fb->format->hsub;
3435         int vsub = fb->format->vsub;
3436         int aux_x = plane_state->color_plane[1].x;
3437         int aux_y = plane_state->color_plane[1].y;
3438         u32 aux_offset = plane_state->color_plane[1].offset;
3439         u32 alignment = intel_surf_alignment(fb, 1);
3440
3441         while (aux_offset >= main_offset && aux_y <= main_y) {
3442                 int x, y;
3443
3444                 if (aux_x == main_x && aux_y == main_y)
3445                         break;
3446
3447                 if (aux_offset == 0)
3448                         break;
3449
3450                 x = aux_x / hsub;
3451                 y = aux_y / vsub;
3452                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3453                                                                aux_offset, aux_offset - alignment);
3454                 aux_x = x * hsub + aux_x % hsub;
3455                 aux_y = y * vsub + aux_y % vsub;
3456         }
3457
3458         if (aux_x != main_x || aux_y != main_y)
3459                 return false;
3460
3461         plane_state->color_plane[1].offset = aux_offset;
3462         plane_state->color_plane[1].x = aux_x;
3463         plane_state->color_plane[1].y = aux_y;
3464
3465         return true;
3466 }
3467
3468 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3469 {
3470         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3471         const struct drm_framebuffer *fb = plane_state->hw.fb;
3472         unsigned int rotation = plane_state->hw.rotation;
3473         int x = plane_state->uapi.src.x1 >> 16;
3474         int y = plane_state->uapi.src.y1 >> 16;
3475         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3476         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3477         int max_width;
3478         int max_height;
3479         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3480
3481         if (INTEL_GEN(dev_priv) >= 11)
3482                 max_width = icl_max_plane_width(fb, 0, rotation);
3483         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3484                 max_width = glk_max_plane_width(fb, 0, rotation);
3485         else
3486                 max_width = skl_max_plane_width(fb, 0, rotation);
3487
3488         if (INTEL_GEN(dev_priv) >= 11)
3489                 max_height = icl_max_plane_height();
3490         else
3491                 max_height = skl_max_plane_height();
3492
3493         if (w > max_width || h > max_height) {
3494                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3495                               w, h, max_width, max_height);
3496                 return -EINVAL;
3497         }
3498
3499         intel_add_fb_offsets(&x, &y, plane_state, 0);
3500         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3501         alignment = intel_surf_alignment(fb, 0);
3502
3503         /*
3504          * AUX surface offset is specified as the distance from the
3505          * main surface offset, and it must be non-negative. Make
3506          * sure that is what we will get.
3507          */
3508         if (offset > aux_offset)
3509                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3510                                                            offset, aux_offset & ~(alignment - 1));
3511
3512         /*
3513          * When using an X-tiled surface, the plane blows up
3514          * if the x offset + width exceed the stride.
3515          *
3516          * TODO: linear and Y-tiled seem fine, Yf untested,
3517          */
3518         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3519                 int cpp = fb->format->cpp[0];
3520
3521                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3522                         if (offset == 0) {
3523                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3524                                 return -EINVAL;
3525                         }
3526
3527                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3528                                                                    offset, offset - alignment);
3529                 }
3530         }
3531
3532         /*
3533          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3534          * they match with the main surface x/y offsets.
3535          */
3536         if (is_ccs_modifier(fb->modifier)) {
3537                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3538                         if (offset == 0)
3539                                 break;
3540
3541                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3542                                                                    offset, offset - alignment);
3543                 }
3544
3545                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3546                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3547                         return -EINVAL;
3548                 }
3549         }
3550
3551         plane_state->color_plane[0].offset = offset;
3552         plane_state->color_plane[0].x = x;
3553         plane_state->color_plane[0].y = y;
3554
3555         /*
3556          * Put the final coordinates back so that the src
3557          * coordinate checks will see the right values.
3558          */
3559         drm_rect_translate_to(&plane_state->uapi.src,
3560                               x << 16, y << 16);
3561
3562         return 0;
3563 }
3564
3565 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3566 {
3567         const struct drm_framebuffer *fb = plane_state->hw.fb;
3568         unsigned int rotation = plane_state->hw.rotation;
3569         int max_width = skl_max_plane_width(fb, 1, rotation);
3570         int max_height = 4096;
3571         int x = plane_state->uapi.src.x1 >> 17;
3572         int y = plane_state->uapi.src.y1 >> 17;
3573         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3574         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3575         u32 offset;
3576
3577         intel_add_fb_offsets(&x, &y, plane_state, 1);
3578         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3579
3580         /* FIXME not quite sure how/if these apply to the chroma plane */
3581         if (w > max_width || h > max_height) {
3582                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3583                               w, h, max_width, max_height);
3584                 return -EINVAL;
3585         }
3586
3587         plane_state->color_plane[1].offset = offset;
3588         plane_state->color_plane[1].x = x;
3589         plane_state->color_plane[1].y = y;
3590
3591         return 0;
3592 }
3593
3594 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3595 {
3596         const struct drm_framebuffer *fb = plane_state->hw.fb;
3597         int src_x = plane_state->uapi.src.x1 >> 16;
3598         int src_y = plane_state->uapi.src.y1 >> 16;
3599         int hsub = fb->format->hsub;
3600         int vsub = fb->format->vsub;
3601         int x = src_x / hsub;
3602         int y = src_y / vsub;
3603         u32 offset;
3604
3605         intel_add_fb_offsets(&x, &y, plane_state, 1);
3606         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3607
3608         plane_state->color_plane[1].offset = offset;
3609         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3610         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3611
3612         return 0;
3613 }
3614
3615 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3616 {
3617         const struct drm_framebuffer *fb = plane_state->hw.fb;
3618         int ret;
3619
3620         ret = intel_plane_compute_gtt(plane_state);
3621         if (ret)
3622                 return ret;
3623
3624         if (!plane_state->uapi.visible)
3625                 return 0;
3626
3627         /*
3628          * Handle the AUX surface first since
3629          * the main surface setup depends on it.
3630          */
3631         if (drm_format_info_is_yuv_semiplanar(fb->format)) {
3632                 ret = skl_check_nv12_aux_surface(plane_state);
3633                 if (ret)
3634                         return ret;
3635         } else if (is_ccs_modifier(fb->modifier)) {
3636                 ret = skl_check_ccs_aux_surface(plane_state);
3637                 if (ret)
3638                         return ret;
3639         } else {
3640                 plane_state->color_plane[1].offset = ~0xfff;
3641                 plane_state->color_plane[1].x = 0;
3642                 plane_state->color_plane[1].y = 0;
3643         }
3644
3645         ret = skl_check_main_surface(plane_state);
3646         if (ret)
3647                 return ret;
3648
3649         return 0;
3650 }
3651
3652 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
3653                              const struct intel_plane_state *plane_state,
3654                              unsigned int *num, unsigned int *den)
3655 {
3656         const struct drm_framebuffer *fb = plane_state->hw.fb;
3657         unsigned int cpp = fb->format->cpp[0];
3658
3659         /*
3660          * g4x bspec says 64bpp pixel rate can't exceed 80%
3661          * of cdclk when the sprite plane is enabled on the
3662          * same pipe. ilk/snb bspec says 64bpp pixel rate is
3663          * never allowed to exceed 80% of cdclk. Let's just go
3664          * with the ilk/snb limit always.
3665          */
3666         if (cpp == 8) {
3667                 *num = 10;
3668                 *den = 8;
3669         } else {
3670                 *num = 1;
3671                 *den = 1;
3672         }
3673 }
3674
3675 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
3676                                 const struct intel_plane_state *plane_state)
3677 {
3678         unsigned int pixel_rate;
3679         unsigned int num, den;
3680
3681         /*
3682          * Note that crtc_state->pixel_rate accounts for both
3683          * horizontal and vertical panel fitter downscaling factors.
3684          * Pre-HSW bspec tells us to only consider the horizontal
3685          * downscaling factor here. We ignore that and just consider
3686          * both for simplicity.
3687          */
3688         pixel_rate = crtc_state->pixel_rate;
3689
3690         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
3691
3692         /* two pixels per clock with double wide pipe */
3693         if (crtc_state->double_wide)
3694                 den *= 2;
3695
3696         return DIV_ROUND_UP(pixel_rate * num, den);
3697 }
3698
3699 unsigned int
3700 i9xx_plane_max_stride(struct intel_plane *plane,
3701                       u32 pixel_format, u64 modifier,
3702                       unsigned int rotation)
3703 {
3704         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3705
3706         if (!HAS_GMCH(dev_priv)) {
3707                 return 32*1024;
3708         } else if (INTEL_GEN(dev_priv) >= 4) {
3709                 if (modifier == I915_FORMAT_MOD_X_TILED)
3710                         return 16*1024;
3711                 else
3712                         return 32*1024;
3713         } else if (INTEL_GEN(dev_priv) >= 3) {
3714                 if (modifier == I915_FORMAT_MOD_X_TILED)
3715                         return 8*1024;
3716                 else
3717                         return 16*1024;
3718         } else {
3719                 if (plane->i9xx_plane == PLANE_C)
3720                         return 4*1024;
3721                 else
3722                         return 8*1024;
3723         }
3724 }
3725
3726 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3727 {
3728         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3730         u32 dspcntr = 0;
3731
3732         if (crtc_state->gamma_enable)
3733                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3734
3735         if (crtc_state->csc_enable)
3736                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3737
3738         if (INTEL_GEN(dev_priv) < 5)
3739                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3740
3741         return dspcntr;
3742 }
3743
3744 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3745                           const struct intel_plane_state *plane_state)
3746 {
3747         struct drm_i915_private *dev_priv =
3748                 to_i915(plane_state->uapi.plane->dev);
3749         const struct drm_framebuffer *fb = plane_state->hw.fb;
3750         unsigned int rotation = plane_state->hw.rotation;
3751         u32 dspcntr;
3752
3753         dspcntr = DISPLAY_PLANE_ENABLE;
3754
3755         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3756             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3757                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3758
3759         switch (fb->format->format) {
3760         case DRM_FORMAT_C8:
3761                 dspcntr |= DISPPLANE_8BPP;
3762                 break;
3763         case DRM_FORMAT_XRGB1555:
3764                 dspcntr |= DISPPLANE_BGRX555;
3765                 break;
3766         case DRM_FORMAT_ARGB1555:
3767                 dspcntr |= DISPPLANE_BGRA555;
3768                 break;
3769         case DRM_FORMAT_RGB565:
3770                 dspcntr |= DISPPLANE_BGRX565;
3771                 break;
3772         case DRM_FORMAT_XRGB8888:
3773                 dspcntr |= DISPPLANE_BGRX888;
3774                 break;
3775         case DRM_FORMAT_XBGR8888:
3776                 dspcntr |= DISPPLANE_RGBX888;
3777                 break;
3778         case DRM_FORMAT_ARGB8888:
3779                 dspcntr |= DISPPLANE_BGRA888;
3780                 break;
3781         case DRM_FORMAT_ABGR8888:
3782                 dspcntr |= DISPPLANE_RGBA888;
3783                 break;
3784         case DRM_FORMAT_XRGB2101010:
3785                 dspcntr |= DISPPLANE_BGRX101010;
3786                 break;
3787         case DRM_FORMAT_XBGR2101010:
3788                 dspcntr |= DISPPLANE_RGBX101010;
3789                 break;
3790         case DRM_FORMAT_ARGB2101010:
3791                 dspcntr |= DISPPLANE_BGRA101010;
3792                 break;
3793         case DRM_FORMAT_ABGR2101010:
3794                 dspcntr |= DISPPLANE_RGBA101010;
3795                 break;
3796         case DRM_FORMAT_XBGR16161616F:
3797                 dspcntr |= DISPPLANE_RGBX161616;
3798                 break;
3799         default:
3800                 MISSING_CASE(fb->format->format);
3801                 return 0;
3802         }
3803
3804         if (INTEL_GEN(dev_priv) >= 4 &&
3805             fb->modifier == I915_FORMAT_MOD_X_TILED)
3806                 dspcntr |= DISPPLANE_TILED;
3807
3808         if (rotation & DRM_MODE_ROTATE_180)
3809                 dspcntr |= DISPPLANE_ROTATE_180;
3810
3811         if (rotation & DRM_MODE_REFLECT_X)
3812                 dspcntr |= DISPPLANE_MIRROR;
3813
3814         return dspcntr;
3815 }
3816
3817 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3818 {
3819         struct drm_i915_private *dev_priv =
3820                 to_i915(plane_state->uapi.plane->dev);
3821         const struct drm_framebuffer *fb = plane_state->hw.fb;
3822         int src_x, src_y, src_w;
3823         u32 offset;
3824         int ret;
3825
3826         ret = intel_plane_compute_gtt(plane_state);
3827         if (ret)
3828                 return ret;
3829
3830         if (!plane_state->uapi.visible)
3831                 return 0;
3832
3833         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3834         src_x = plane_state->uapi.src.x1 >> 16;
3835         src_y = plane_state->uapi.src.y1 >> 16;
3836
3837         /* Undocumented hardware limit on i965/g4x/vlv/chv */
3838         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
3839                 return -EINVAL;
3840
3841         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3842
3843         if (INTEL_GEN(dev_priv) >= 4)
3844                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3845                                                             plane_state, 0);
3846         else
3847                 offset = 0;
3848
3849         /*
3850          * Put the final coordinates back so that the src
3851          * coordinate checks will see the right values.
3852          */
3853         drm_rect_translate_to(&plane_state->uapi.src,
3854                               src_x << 16, src_y << 16);
3855
3856         /* HSW/BDW do this automagically in hardware */
3857         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3858                 unsigned int rotation = plane_state->hw.rotation;
3859                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3860                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3861
3862                 if (rotation & DRM_MODE_ROTATE_180) {
3863                         src_x += src_w - 1;
3864                         src_y += src_h - 1;
3865                 } else if (rotation & DRM_MODE_REFLECT_X) {
3866                         src_x += src_w - 1;
3867                 }
3868         }
3869
3870         plane_state->color_plane[0].offset = offset;
3871         plane_state->color_plane[0].x = src_x;
3872         plane_state->color_plane[0].y = src_y;
3873
3874         return 0;
3875 }
3876
3877 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3878 {
3879         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3880         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3881
3882         if (IS_CHERRYVIEW(dev_priv))
3883                 return i9xx_plane == PLANE_B;
3884         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3885                 return false;
3886         else if (IS_GEN(dev_priv, 4))
3887                 return i9xx_plane == PLANE_C;
3888         else
3889                 return i9xx_plane == PLANE_B ||
3890                         i9xx_plane == PLANE_C;
3891 }
3892
3893 static int
3894 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3895                  struct intel_plane_state *plane_state)
3896 {
3897         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3898         int ret;
3899
3900         ret = chv_plane_check_rotation(plane_state);
3901         if (ret)
3902                 return ret;
3903
3904         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
3905                                                   &crtc_state->uapi,
3906                                                   DRM_PLANE_HELPER_NO_SCALING,
3907                                                   DRM_PLANE_HELPER_NO_SCALING,
3908                                                   i9xx_plane_has_windowing(plane),
3909                                                   true);
3910         if (ret)
3911                 return ret;
3912
3913         ret = i9xx_check_plane_surface(plane_state);
3914         if (ret)
3915                 return ret;
3916
3917         if (!plane_state->uapi.visible)
3918                 return 0;
3919
3920         ret = intel_plane_check_src_coordinates(plane_state);
3921         if (ret)
3922                 return ret;
3923
3924         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3925
3926         return 0;
3927 }
3928
3929 static void i9xx_update_plane(struct intel_plane *plane,
3930                               const struct intel_crtc_state *crtc_state,
3931                               const struct intel_plane_state *plane_state)
3932 {
3933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3934         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3935         u32 linear_offset;
3936         int x = plane_state->color_plane[0].x;
3937         int y = plane_state->color_plane[0].y;
3938         int crtc_x = plane_state->uapi.dst.x1;
3939         int crtc_y = plane_state->uapi.dst.y1;
3940         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
3941         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
3942         unsigned long irqflags;
3943         u32 dspaddr_offset;
3944         u32 dspcntr;
3945
3946         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3947
3948         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3949
3950         if (INTEL_GEN(dev_priv) >= 4)
3951                 dspaddr_offset = plane_state->color_plane[0].offset;
3952         else
3953                 dspaddr_offset = linear_offset;
3954
3955         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3956
3957         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3958
3959         if (INTEL_GEN(dev_priv) < 4) {
3960                 /*
3961                  * PLANE_A doesn't actually have a full window
3962                  * generator but let's assume we still need to
3963                  * program whatever is there.
3964                  */
3965                 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3966                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3967                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3968         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3969                 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3970                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3971                               ((crtc_h - 1) << 16) | (crtc_w - 1));
3972                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3973         }
3974
3975         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3976                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3977         } else if (INTEL_GEN(dev_priv) >= 4) {
3978                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3979                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3980         }
3981
3982         /*
3983          * The control register self-arms if the plane was previously
3984          * disabled. Try to make the plane enable atomic by writing
3985          * the control register just before the surface register.
3986          */
3987         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3988         if (INTEL_GEN(dev_priv) >= 4)
3989                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3990                               intel_plane_ggtt_offset(plane_state) +
3991                               dspaddr_offset);
3992         else
3993                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3994                               intel_plane_ggtt_offset(plane_state) +
3995                               dspaddr_offset);
3996
3997         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3998 }
3999
4000 static void i9xx_disable_plane(struct intel_plane *plane,
4001                                const struct intel_crtc_state *crtc_state)
4002 {
4003         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4004         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4005         unsigned long irqflags;
4006         u32 dspcntr;
4007
4008         /*
4009          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4010          * enable on ilk+ affect the pipe bottom color as
4011          * well, so we must configure them even if the plane
4012          * is disabled.
4013          *
4014          * On pre-g4x there is no way to gamma correct the
4015          * pipe bottom color but we'll keep on doing this
4016          * anyway so that the crtc state readout works correctly.
4017          */
4018         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4019
4020         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4021
4022         I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
4023         if (INTEL_GEN(dev_priv) >= 4)
4024                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
4025         else
4026                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
4027
4028         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4029 }
4030
4031 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4032                                     enum pipe *pipe)
4033 {
4034         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4035         enum intel_display_power_domain power_domain;
4036         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4037         intel_wakeref_t wakeref;
4038         bool ret;
4039         u32 val;
4040
4041         /*
4042          * Not 100% correct for planes that can move between pipes,
4043          * but that's only the case for gen2-4 which don't have any
4044          * display power wells.
4045          */
4046         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4047         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4048         if (!wakeref)
4049                 return false;
4050
4051         val = I915_READ(DSPCNTR(i9xx_plane));
4052
4053         ret = val & DISPLAY_PLANE_ENABLE;
4054
4055         if (INTEL_GEN(dev_priv) >= 5)
4056                 *pipe = plane->pipe;
4057         else
4058                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4059                         DISPPLANE_SEL_PIPE_SHIFT;
4060
4061         intel_display_power_put(dev_priv, power_domain, wakeref);
4062
4063         return ret;
4064 }
4065
4066 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069         struct drm_i915_private *dev_priv = to_i915(dev);
4070
4071         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4072         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4073         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4074 }
4075
4076 /*
4077  * This function detaches (aka. unbinds) unused scalers in hardware
4078  */
4079 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4080 {
4081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4082         const struct intel_crtc_scaler_state *scaler_state =
4083                 &crtc_state->scaler_state;
4084         int i;
4085
4086         /* loop through and disable scalers that aren't in use */
4087         for (i = 0; i < intel_crtc->num_scalers; i++) {
4088                 if (!scaler_state->scalers[i].in_use)
4089                         skl_detach_scaler(intel_crtc, i);
4090         }
4091 }
4092
4093 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4094                                           int color_plane, unsigned int rotation)
4095 {
4096         /*
4097          * The stride is either expressed as a multiple of 64 bytes chunks for
4098          * linear buffers or in number of tiles for tiled buffers.
4099          */
4100         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
4101                 return 64;
4102         else if (drm_rotation_90_or_270(rotation))
4103                 return intel_tile_height(fb, color_plane);
4104         else
4105                 return intel_tile_width_bytes(fb, color_plane);
4106 }
4107
4108 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4109                      int color_plane)
4110 {
4111         const struct drm_framebuffer *fb = plane_state->hw.fb;
4112         unsigned int rotation = plane_state->hw.rotation;
4113         u32 stride = plane_state->color_plane[color_plane].stride;
4114
4115         if (color_plane >= fb->format->num_planes)
4116                 return 0;
4117
4118         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4119 }
4120
4121 static u32 skl_plane_ctl_format(u32 pixel_format)
4122 {
4123         switch (pixel_format) {
4124         case DRM_FORMAT_C8:
4125                 return PLANE_CTL_FORMAT_INDEXED;
4126         case DRM_FORMAT_RGB565:
4127                 return PLANE_CTL_FORMAT_RGB_565;
4128         case DRM_FORMAT_XBGR8888:
4129         case DRM_FORMAT_ABGR8888:
4130                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4131         case DRM_FORMAT_XRGB8888:
4132         case DRM_FORMAT_ARGB8888:
4133                 return PLANE_CTL_FORMAT_XRGB_8888;
4134         case DRM_FORMAT_XBGR2101010:
4135         case DRM_FORMAT_ABGR2101010:
4136                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4137         case DRM_FORMAT_XRGB2101010:
4138         case DRM_FORMAT_ARGB2101010:
4139                 return PLANE_CTL_FORMAT_XRGB_2101010;
4140         case DRM_FORMAT_XBGR16161616F:
4141         case DRM_FORMAT_ABGR16161616F:
4142                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4143         case DRM_FORMAT_XRGB16161616F:
4144         case DRM_FORMAT_ARGB16161616F:
4145                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4146         case DRM_FORMAT_YUYV:
4147                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4148         case DRM_FORMAT_YVYU:
4149                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4150         case DRM_FORMAT_UYVY:
4151                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4152         case DRM_FORMAT_VYUY:
4153                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4154         case DRM_FORMAT_NV12:
4155                 return PLANE_CTL_FORMAT_NV12;
4156         case DRM_FORMAT_P010:
4157                 return PLANE_CTL_FORMAT_P010;
4158         case DRM_FORMAT_P012:
4159                 return PLANE_CTL_FORMAT_P012;
4160         case DRM_FORMAT_P016:
4161                 return PLANE_CTL_FORMAT_P016;
4162         case DRM_FORMAT_Y210:
4163                 return PLANE_CTL_FORMAT_Y210;
4164         case DRM_FORMAT_Y212:
4165                 return PLANE_CTL_FORMAT_Y212;
4166         case DRM_FORMAT_Y216:
4167                 return PLANE_CTL_FORMAT_Y216;
4168         case DRM_FORMAT_XVYU2101010:
4169                 return PLANE_CTL_FORMAT_Y410;
4170         case DRM_FORMAT_XVYU12_16161616:
4171                 return PLANE_CTL_FORMAT_Y412;
4172         case DRM_FORMAT_XVYU16161616:
4173                 return PLANE_CTL_FORMAT_Y416;
4174         default:
4175                 MISSING_CASE(pixel_format);
4176         }
4177
4178         return 0;
4179 }
4180
4181 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4182 {
4183         if (!plane_state->hw.fb->format->has_alpha)
4184                 return PLANE_CTL_ALPHA_DISABLE;
4185
4186         switch (plane_state->hw.pixel_blend_mode) {
4187         case DRM_MODE_BLEND_PIXEL_NONE:
4188                 return PLANE_CTL_ALPHA_DISABLE;
4189         case DRM_MODE_BLEND_PREMULTI:
4190                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4191         case DRM_MODE_BLEND_COVERAGE:
4192                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4193         default:
4194                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4195                 return PLANE_CTL_ALPHA_DISABLE;
4196         }
4197 }
4198
4199 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4200 {
4201         if (!plane_state->hw.fb->format->has_alpha)
4202                 return PLANE_COLOR_ALPHA_DISABLE;
4203
4204         switch (plane_state->hw.pixel_blend_mode) {
4205         case DRM_MODE_BLEND_PIXEL_NONE:
4206                 return PLANE_COLOR_ALPHA_DISABLE;
4207         case DRM_MODE_BLEND_PREMULTI:
4208                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4209         case DRM_MODE_BLEND_COVERAGE:
4210                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4211         default:
4212                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4213                 return PLANE_COLOR_ALPHA_DISABLE;
4214         }
4215 }
4216
4217 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4218 {
4219         switch (fb_modifier) {
4220         case DRM_FORMAT_MOD_LINEAR:
4221                 break;
4222         case I915_FORMAT_MOD_X_TILED:
4223                 return PLANE_CTL_TILED_X;
4224         case I915_FORMAT_MOD_Y_TILED:
4225                 return PLANE_CTL_TILED_Y;
4226         case I915_FORMAT_MOD_Y_TILED_CCS:
4227                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4228         case I915_FORMAT_MOD_Yf_TILED:
4229                 return PLANE_CTL_TILED_YF;
4230         case I915_FORMAT_MOD_Yf_TILED_CCS:
4231                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4232         default:
4233                 MISSING_CASE(fb_modifier);
4234         }
4235
4236         return 0;
4237 }
4238
4239 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4240 {
4241         switch (rotate) {
4242         case DRM_MODE_ROTATE_0:
4243                 break;
4244         /*
4245          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4246          * while i915 HW rotation is clockwise, thats why this swapping.
4247          */
4248         case DRM_MODE_ROTATE_90:
4249                 return PLANE_CTL_ROTATE_270;
4250         case DRM_MODE_ROTATE_180:
4251                 return PLANE_CTL_ROTATE_180;
4252         case DRM_MODE_ROTATE_270:
4253                 return PLANE_CTL_ROTATE_90;
4254         default:
4255                 MISSING_CASE(rotate);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4262 {
4263         switch (reflect) {
4264         case 0:
4265                 break;
4266         case DRM_MODE_REFLECT_X:
4267                 return PLANE_CTL_FLIP_HORIZONTAL;
4268         case DRM_MODE_REFLECT_Y:
4269         default:
4270                 MISSING_CASE(reflect);
4271         }
4272
4273         return 0;
4274 }
4275
4276 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4277 {
4278         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4279         u32 plane_ctl = 0;
4280
4281         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4282                 return plane_ctl;
4283
4284         if (crtc_state->gamma_enable)
4285                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4286
4287         if (crtc_state->csc_enable)
4288                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4289
4290         return plane_ctl;
4291 }
4292
4293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4294                   const struct intel_plane_state *plane_state)
4295 {
4296         struct drm_i915_private *dev_priv =
4297                 to_i915(plane_state->uapi.plane->dev);
4298         const struct drm_framebuffer *fb = plane_state->hw.fb;
4299         unsigned int rotation = plane_state->hw.rotation;
4300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4301         u32 plane_ctl;
4302
4303         plane_ctl = PLANE_CTL_ENABLE;
4304
4305         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4306                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4307                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4308
4309                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4310                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4311
4312                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4313                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4314         }
4315
4316         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4317         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4318         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4319
4320         if (INTEL_GEN(dev_priv) >= 10)
4321                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4322                                                 DRM_MODE_REFLECT_MASK);
4323
4324         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4325                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4326         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4327                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4328
4329         return plane_ctl;
4330 }
4331
4332 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4335         u32 plane_color_ctl = 0;
4336
4337         if (INTEL_GEN(dev_priv) >= 11)
4338                 return plane_color_ctl;
4339
4340         if (crtc_state->gamma_enable)
4341                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4342
4343         if (crtc_state->csc_enable)
4344                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4345
4346         return plane_color_ctl;
4347 }
4348
4349 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4350                         const struct intel_plane_state *plane_state)
4351 {
4352         struct drm_i915_private *dev_priv =
4353                 to_i915(plane_state->uapi.plane->dev);
4354         const struct drm_framebuffer *fb = plane_state->hw.fb;
4355         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4356         u32 plane_color_ctl = 0;
4357
4358         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4359         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4360
4361         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4362                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4363                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4364                 else
4365                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4366
4367                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4368                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4369         } else if (fb->format->is_yuv) {
4370                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4371         }
4372
4373         return plane_color_ctl;
4374 }
4375
4376 static int
4377 __intel_display_resume(struct drm_device *dev,
4378                        struct drm_atomic_state *state,
4379                        struct drm_modeset_acquire_ctx *ctx)
4380 {
4381         struct drm_crtc_state *crtc_state;
4382         struct drm_crtc *crtc;
4383         int i, ret;
4384
4385         intel_modeset_setup_hw_state(dev, ctx);
4386         intel_vga_redisable(to_i915(dev));
4387
4388         if (!state)
4389                 return 0;
4390
4391         /*
4392          * We've duplicated the state, pointers to the old state are invalid.
4393          *
4394          * Don't attempt to use the old state until we commit the duplicated state.
4395          */
4396         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4397                 /*
4398                  * Force recalculation even if we restore
4399                  * current state. With fast modeset this may not result
4400                  * in a modeset when the state is compatible.
4401                  */
4402                 crtc_state->mode_changed = true;
4403         }
4404
4405         /* ignore any reset values/BIOS leftovers in the WM registers */
4406         if (!HAS_GMCH(to_i915(dev)))
4407                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4408
4409         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4410
4411         WARN_ON(ret == -EDEADLK);
4412         return ret;
4413 }
4414
4415 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4416 {
4417         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4418                 intel_has_gpu_reset(&dev_priv->gt));
4419 }
4420
4421 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4422 {
4423         struct drm_device *dev = &dev_priv->drm;
4424         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4425         struct drm_atomic_state *state;
4426         int ret;
4427
4428         /* reset doesn't touch the display */
4429         if (!i915_modparams.force_reset_modeset_test &&
4430             !gpu_reset_clobbers_display(dev_priv))
4431                 return;
4432
4433         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4434         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4435         smp_mb__after_atomic();
4436         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4437
4438         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4439                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4440                 intel_gt_set_wedged(&dev_priv->gt);
4441         }
4442
4443         /*
4444          * Need mode_config.mutex so that we don't
4445          * trample ongoing ->detect() and whatnot.
4446          */
4447         mutex_lock(&dev->mode_config.mutex);
4448         drm_modeset_acquire_init(ctx, 0);
4449         while (1) {
4450                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4451                 if (ret != -EDEADLK)
4452                         break;
4453
4454                 drm_modeset_backoff(ctx);
4455         }
4456         /*
4457          * Disabling the crtcs gracefully seems nicer. Also the
4458          * g33 docs say we should at least disable all the planes.
4459          */
4460         state = drm_atomic_helper_duplicate_state(dev, ctx);
4461         if (IS_ERR(state)) {
4462                 ret = PTR_ERR(state);
4463                 DRM_ERROR("Duplicating state failed with %i\n", ret);
4464                 return;
4465         }
4466
4467         ret = drm_atomic_helper_disable_all(dev, ctx);
4468         if (ret) {
4469                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4470                 drm_atomic_state_put(state);
4471                 return;
4472         }
4473
4474         dev_priv->modeset_restore_state = state;
4475         state->acquire_ctx = ctx;
4476 }
4477
4478 void intel_finish_reset(struct drm_i915_private *dev_priv)
4479 {
4480         struct drm_device *dev = &dev_priv->drm;
4481         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4482         struct drm_atomic_state *state;
4483         int ret;
4484
4485         /* reset doesn't touch the display */
4486         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4487                 return;
4488
4489         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4490         if (!state)
4491                 goto unlock;
4492
4493         /* reset doesn't touch the display */
4494         if (!gpu_reset_clobbers_display(dev_priv)) {
4495                 /* for testing only restore the display */
4496                 ret = __intel_display_resume(dev, state, ctx);
4497                 if (ret)
4498                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4499         } else {
4500                 /*
4501                  * The display has been reset as well,
4502                  * so need a full re-initialization.
4503                  */
4504                 intel_pps_unlock_regs_wa(dev_priv);
4505                 intel_modeset_init_hw(dev_priv);
4506                 intel_init_clock_gating(dev_priv);
4507
4508                 spin_lock_irq(&dev_priv->irq_lock);
4509                 if (dev_priv->display.hpd_irq_setup)
4510                         dev_priv->display.hpd_irq_setup(dev_priv);
4511                 spin_unlock_irq(&dev_priv->irq_lock);
4512
4513                 ret = __intel_display_resume(dev, state, ctx);
4514                 if (ret)
4515                         DRM_ERROR("Restoring old state failed with %i\n", ret);
4516
4517                 intel_hpd_init(dev_priv);
4518         }
4519
4520         drm_atomic_state_put(state);
4521 unlock:
4522         drm_modeset_drop_locks(ctx);
4523         drm_modeset_acquire_fini(ctx);
4524         mutex_unlock(&dev->mode_config.mutex);
4525
4526         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4527 }
4528
4529 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4530 {
4531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4532         enum pipe pipe = crtc->pipe;
4533         u32 tmp;
4534
4535         tmp = I915_READ(PIPE_CHICKEN(pipe));
4536
4537         /*
4538          * Display WA #1153: icl
4539          * enable hardware to bypass the alpha math
4540          * and rounding for per-pixel values 00 and 0xff
4541          */
4542         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4543         /*
4544          * Display WA # 1605353570: icl
4545          * Set the pixel rounding bit to 1 for allowing
4546          * passthrough of Frame buffer pixels unmodified
4547          * across pipe
4548          */
4549         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4550         I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4551 }
4552
4553 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
4554 {
4555         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4556         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4557         u32 trans_ddi_func_ctl2_val;
4558         u8 master_select;
4559
4560         /*
4561          * Configure the master select and enable Transcoder Port Sync for
4562          * Slave CRTCs transcoder.
4563          */
4564         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
4565                 return;
4566
4567         if (crtc_state->master_transcoder == TRANSCODER_EDP)
4568                 master_select = 0;
4569         else
4570                 master_select = crtc_state->master_transcoder + 1;
4571
4572         /* Set the master select bits for Tranascoder Port Sync */
4573         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
4574                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
4575                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
4576         /* Enable Transcoder Port Sync */
4577         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
4578
4579         I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
4580                    trans_ddi_func_ctl2_val);
4581 }
4582
4583 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
4584 {
4585         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4587         i915_reg_t reg;
4588         u32 trans_ddi_func_ctl2_val;
4589
4590         if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
4591                 return;
4592
4593         DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
4594                       transcoder_name(old_crtc_state->cpu_transcoder));
4595
4596         reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
4597         trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
4598                                     PORT_SYNC_MODE_MASTER_SELECT_MASK);
4599         I915_WRITE(reg, trans_ddi_func_ctl2_val);
4600 }
4601
4602 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = to_i915(dev);
4606         enum pipe pipe = crtc->pipe;
4607         i915_reg_t reg;
4608         u32 temp;
4609
4610         /* enable normal train */
4611         reg = FDI_TX_CTL(pipe);
4612         temp = I915_READ(reg);
4613         if (IS_IVYBRIDGE(dev_priv)) {
4614                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4615                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4616         } else {
4617                 temp &= ~FDI_LINK_TRAIN_NONE;
4618                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4619         }
4620         I915_WRITE(reg, temp);
4621
4622         reg = FDI_RX_CTL(pipe);
4623         temp = I915_READ(reg);
4624         if (HAS_PCH_CPT(dev_priv)) {
4625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4626                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4627         } else {
4628                 temp &= ~FDI_LINK_TRAIN_NONE;
4629                 temp |= FDI_LINK_TRAIN_NONE;
4630         }
4631         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4632
4633         /* wait one idle pattern time */
4634         POSTING_READ(reg);
4635         udelay(1000);
4636
4637         /* IVB wants error correction enabled */
4638         if (IS_IVYBRIDGE(dev_priv))
4639                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4640                            FDI_FE_ERRC_ENABLE);
4641 }
4642
4643 /* The FDI link training functions for ILK/Ibexpeak. */
4644 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4645                                     const struct intel_crtc_state *crtc_state)
4646 {
4647         struct drm_device *dev = crtc->base.dev;
4648         struct drm_i915_private *dev_priv = to_i915(dev);
4649         enum pipe pipe = crtc->pipe;
4650         i915_reg_t reg;
4651         u32 temp, tries;
4652
4653         /* FDI needs bits from pipe first */
4654         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
4655
4656         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4657            for train result */
4658         reg = FDI_RX_IMR(pipe);
4659         temp = I915_READ(reg);
4660         temp &= ~FDI_RX_SYMBOL_LOCK;
4661         temp &= ~FDI_RX_BIT_LOCK;
4662         I915_WRITE(reg, temp);
4663         I915_READ(reg);
4664         udelay(150);
4665
4666         /* enable CPU FDI TX and PCH FDI RX */
4667         reg = FDI_TX_CTL(pipe);
4668         temp = I915_READ(reg);
4669         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4670         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4671         temp &= ~FDI_LINK_TRAIN_NONE;
4672         temp |= FDI_LINK_TRAIN_PATTERN_1;
4673         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4674
4675         reg = FDI_RX_CTL(pipe);
4676         temp = I915_READ(reg);
4677         temp &= ~FDI_LINK_TRAIN_NONE;
4678         temp |= FDI_LINK_TRAIN_PATTERN_1;
4679         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4680
4681         POSTING_READ(reg);
4682         udelay(150);
4683
4684         /* Ironlake workaround, enable clock pointer after FDI enable*/
4685         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4686         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4687                    FDI_RX_PHASE_SYNC_POINTER_EN);
4688
4689         reg = FDI_RX_IIR(pipe);
4690         for (tries = 0; tries < 5; tries++) {
4691                 temp = I915_READ(reg);
4692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4693
4694                 if ((temp & FDI_RX_BIT_LOCK)) {
4695                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4697                         break;
4698                 }
4699         }
4700         if (tries == 5)
4701                 DRM_ERROR("FDI train 1 fail!\n");
4702
4703         /* Train 2 */
4704         reg = FDI_TX_CTL(pipe);
4705         temp = I915_READ(reg);
4706         temp &= ~FDI_LINK_TRAIN_NONE;
4707         temp |= FDI_LINK_TRAIN_PATTERN_2;
4708         I915_WRITE(reg, temp);
4709
4710         reg = FDI_RX_CTL(pipe);
4711         temp = I915_READ(reg);
4712         temp &= ~FDI_LINK_TRAIN_NONE;
4713         temp |= FDI_LINK_TRAIN_PATTERN_2;
4714         I915_WRITE(reg, temp);
4715
4716         POSTING_READ(reg);
4717         udelay(150);
4718
4719         reg = FDI_RX_IIR(pipe);
4720         for (tries = 0; tries < 5; tries++) {
4721                 temp = I915_READ(reg);
4722                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4723
4724                 if (temp & FDI_RX_SYMBOL_LOCK) {
4725                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4726                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4727                         break;
4728                 }
4729         }
4730         if (tries == 5)
4731                 DRM_ERROR("FDI train 2 fail!\n");
4732
4733         DRM_DEBUG_KMS("FDI train done\n");
4734
4735 }
4736
4737 static const int snb_b_fdi_train_param[] = {
4738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4742 };
4743
4744 /* The FDI link training functions for SNB/Cougarpoint. */
4745 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4746                                 const struct intel_crtc_state *crtc_state)
4747 {
4748         struct drm_device *dev = crtc->base.dev;
4749         struct drm_i915_private *dev_priv = to_i915(dev);
4750         enum pipe pipe = crtc->pipe;
4751         i915_reg_t reg;
4752         u32 temp, i, retry;
4753
4754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4755            for train result */
4756         reg = FDI_RX_IMR(pipe);
4757         temp = I915_READ(reg);
4758         temp &= ~FDI_RX_SYMBOL_LOCK;
4759         temp &= ~FDI_RX_BIT_LOCK;
4760         I915_WRITE(reg, temp);
4761
4762         POSTING_READ(reg);
4763         udelay(150);
4764
4765         /* enable CPU FDI TX and PCH FDI RX */
4766         reg = FDI_TX_CTL(pipe);
4767         temp = I915_READ(reg);
4768         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4769         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4770         temp &= ~FDI_LINK_TRAIN_NONE;
4771         temp |= FDI_LINK_TRAIN_PATTERN_1;
4772         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4773         /* SNB-B */
4774         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4775         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4776
4777         I915_WRITE(FDI_RX_MISC(pipe),
4778                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4779
4780         reg = FDI_RX_CTL(pipe);
4781         temp = I915_READ(reg);
4782         if (HAS_PCH_CPT(dev_priv)) {
4783                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4784                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4785         } else {
4786                 temp &= ~FDI_LINK_TRAIN_NONE;
4787                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4788         }
4789         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4790
4791         POSTING_READ(reg);
4792         udelay(150);
4793
4794         for (i = 0; i < 4; i++) {
4795                 reg = FDI_TX_CTL(pipe);
4796                 temp = I915_READ(reg);
4797                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4798                 temp |= snb_b_fdi_train_param[i];
4799                 I915_WRITE(reg, temp);
4800
4801                 POSTING_READ(reg);
4802                 udelay(500);
4803
4804                 for (retry = 0; retry < 5; retry++) {
4805                         reg = FDI_RX_IIR(pipe);
4806                         temp = I915_READ(reg);
4807                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4808                         if (temp & FDI_RX_BIT_LOCK) {
4809                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4810                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4811                                 break;
4812                         }
4813                         udelay(50);
4814                 }
4815                 if (retry < 5)
4816                         break;
4817         }
4818         if (i == 4)
4819                 DRM_ERROR("FDI train 1 fail!\n");
4820
4821         /* Train 2 */
4822         reg = FDI_TX_CTL(pipe);
4823         temp = I915_READ(reg);
4824         temp &= ~FDI_LINK_TRAIN_NONE;
4825         temp |= FDI_LINK_TRAIN_PATTERN_2;
4826         if (IS_GEN(dev_priv, 6)) {
4827                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4828                 /* SNB-B */
4829                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4830         }
4831         I915_WRITE(reg, temp);
4832
4833         reg = FDI_RX_CTL(pipe);
4834         temp = I915_READ(reg);
4835         if (HAS_PCH_CPT(dev_priv)) {
4836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4837                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4838         } else {
4839                 temp &= ~FDI_LINK_TRAIN_NONE;
4840                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4841         }
4842         I915_WRITE(reg, temp);
4843
4844         POSTING_READ(reg);
4845         udelay(150);
4846
4847         for (i = 0; i < 4; i++) {
4848                 reg = FDI_TX_CTL(pipe);
4849                 temp = I915_READ(reg);
4850                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4851                 temp |= snb_b_fdi_train_param[i];
4852                 I915_WRITE(reg, temp);
4853
4854                 POSTING_READ(reg);
4855                 udelay(500);
4856
4857                 for (retry = 0; retry < 5; retry++) {
4858                         reg = FDI_RX_IIR(pipe);
4859                         temp = I915_READ(reg);
4860                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4861                         if (temp & FDI_RX_SYMBOL_LOCK) {
4862                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4863                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4864                                 break;
4865                         }
4866                         udelay(50);
4867                 }
4868                 if (retry < 5)
4869                         break;
4870         }
4871         if (i == 4)
4872                 DRM_ERROR("FDI train 2 fail!\n");
4873
4874         DRM_DEBUG_KMS("FDI train done.\n");
4875 }
4876
4877 /* Manual link training for Ivy Bridge A0 parts */
4878 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4879                                       const struct intel_crtc_state *crtc_state)
4880 {
4881         struct drm_device *dev = crtc->base.dev;
4882         struct drm_i915_private *dev_priv = to_i915(dev);
4883         enum pipe pipe = crtc->pipe;
4884         i915_reg_t reg;
4885         u32 temp, i, j;
4886
4887         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4888            for train result */
4889         reg = FDI_RX_IMR(pipe);
4890         temp = I915_READ(reg);
4891         temp &= ~FDI_RX_SYMBOL_LOCK;
4892         temp &= ~FDI_RX_BIT_LOCK;
4893         I915_WRITE(reg, temp);
4894
4895         POSTING_READ(reg);
4896         udelay(150);
4897
4898         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4899                       I915_READ(FDI_RX_IIR(pipe)));
4900
4901         /* Try each vswing and preemphasis setting twice before moving on */
4902         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4903                 /* disable first in case we need to retry */
4904                 reg = FDI_TX_CTL(pipe);
4905                 temp = I915_READ(reg);
4906                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4907                 temp &= ~FDI_TX_ENABLE;
4908                 I915_WRITE(reg, temp);
4909
4910                 reg = FDI_RX_CTL(pipe);
4911                 temp = I915_READ(reg);
4912                 temp &= ~FDI_LINK_TRAIN_AUTO;
4913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4914                 temp &= ~FDI_RX_ENABLE;
4915                 I915_WRITE(reg, temp);
4916
4917                 /* enable CPU FDI TX and PCH FDI RX */
4918                 reg = FDI_TX_CTL(pipe);
4919                 temp = I915_READ(reg);
4920                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4921                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4922                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4923                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4924                 temp |= snb_b_fdi_train_param[j/2];
4925                 temp |= FDI_COMPOSITE_SYNC;
4926                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4927
4928                 I915_WRITE(FDI_RX_MISC(pipe),
4929                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4930
4931                 reg = FDI_RX_CTL(pipe);
4932                 temp = I915_READ(reg);
4933                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4934                 temp |= FDI_COMPOSITE_SYNC;
4935                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4936
4937                 POSTING_READ(reg);
4938                 udelay(1); /* should be 0.5us */
4939
4940                 for (i = 0; i < 4; i++) {
4941                         reg = FDI_RX_IIR(pipe);
4942                         temp = I915_READ(reg);
4943                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4944
4945                         if (temp & FDI_RX_BIT_LOCK ||
4946                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4948                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4949                                               i);
4950                                 break;
4951                         }
4952                         udelay(1); /* should be 0.5us */
4953                 }
4954                 if (i == 4) {
4955                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4956                         continue;
4957                 }
4958
4959                 /* Train 2 */
4960                 reg = FDI_TX_CTL(pipe);
4961                 temp = I915_READ(reg);
4962                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4963                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4964                 I915_WRITE(reg, temp);
4965
4966                 reg = FDI_RX_CTL(pipe);
4967                 temp = I915_READ(reg);
4968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4969                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4970                 I915_WRITE(reg, temp);
4971
4972                 POSTING_READ(reg);
4973                 udelay(2); /* should be 1.5us */
4974
4975                 for (i = 0; i < 4; i++) {
4976                         reg = FDI_RX_IIR(pipe);
4977                         temp = I915_READ(reg);
4978                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4979
4980                         if (temp & FDI_RX_SYMBOL_LOCK ||
4981                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4982                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4983                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4984                                               i);
4985                                 goto train_done;
4986                         }
4987                         udelay(2); /* should be 1.5us */
4988                 }
4989                 if (i == 4)
4990                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4991         }
4992
4993 train_done:
4994         DRM_DEBUG_KMS("FDI train done.\n");
4995 }
4996
4997 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4998 {
4999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5000         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5001         enum pipe pipe = intel_crtc->pipe;
5002         i915_reg_t reg;
5003         u32 temp;
5004
5005         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5006         reg = FDI_RX_CTL(pipe);
5007         temp = I915_READ(reg);
5008         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5009         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5010         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5011         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
5012
5013         POSTING_READ(reg);
5014         udelay(200);
5015
5016         /* Switch from Rawclk to PCDclk */
5017         temp = I915_READ(reg);
5018         I915_WRITE(reg, temp | FDI_PCDCLK);
5019
5020         POSTING_READ(reg);
5021         udelay(200);
5022
5023         /* Enable CPU FDI TX PLL, always on for Ironlake */
5024         reg = FDI_TX_CTL(pipe);
5025         temp = I915_READ(reg);
5026         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5027                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5028
5029                 POSTING_READ(reg);
5030                 udelay(100);
5031         }
5032 }
5033
5034 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
5035 {
5036         struct drm_device *dev = intel_crtc->base.dev;
5037         struct drm_i915_private *dev_priv = to_i915(dev);
5038         enum pipe pipe = intel_crtc->pipe;
5039         i915_reg_t reg;
5040         u32 temp;
5041
5042         /* Switch from PCDclk to Rawclk */
5043         reg = FDI_RX_CTL(pipe);
5044         temp = I915_READ(reg);
5045         I915_WRITE(reg, temp & ~FDI_PCDCLK);
5046
5047         /* Disable CPU FDI TX PLL */
5048         reg = FDI_TX_CTL(pipe);
5049         temp = I915_READ(reg);
5050         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
5051
5052         POSTING_READ(reg);
5053         udelay(100);
5054
5055         reg = FDI_RX_CTL(pipe);
5056         temp = I915_READ(reg);
5057         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
5058
5059         /* Wait for the clocks to turn off. */
5060         POSTING_READ(reg);
5061         udelay(100);
5062 }
5063
5064 static void ironlake_fdi_disable(struct intel_crtc *crtc)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5067         enum pipe pipe = crtc->pipe;
5068         i915_reg_t reg;
5069         u32 temp;
5070
5071         /* disable CPU FDI tx and PCH FDI rx */
5072         reg = FDI_TX_CTL(pipe);
5073         temp = I915_READ(reg);
5074         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
5075         POSTING_READ(reg);
5076
5077         reg = FDI_RX_CTL(pipe);
5078         temp = I915_READ(reg);
5079         temp &= ~(0x7 << 16);
5080         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5081         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
5082
5083         POSTING_READ(reg);
5084         udelay(100);
5085
5086         /* Ironlake workaround, disable clock pointer after downing FDI */
5087         if (HAS_PCH_IBX(dev_priv))
5088                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
5089
5090         /* still set train pattern 1 */
5091         reg = FDI_TX_CTL(pipe);
5092         temp = I915_READ(reg);
5093         temp &= ~FDI_LINK_TRAIN_NONE;
5094         temp |= FDI_LINK_TRAIN_PATTERN_1;
5095         I915_WRITE(reg, temp);
5096
5097         reg = FDI_RX_CTL(pipe);
5098         temp = I915_READ(reg);
5099         if (HAS_PCH_CPT(dev_priv)) {
5100                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5101                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5102         } else {
5103                 temp &= ~FDI_LINK_TRAIN_NONE;
5104                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5105         }
5106         /* BPC in FDI rx is consistent with that in PIPECONF */
5107         temp &= ~(0x07 << 16);
5108         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5109         I915_WRITE(reg, temp);
5110
5111         POSTING_READ(reg);
5112         udelay(100);
5113 }
5114
5115 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5116 {
5117         struct drm_crtc *crtc;
5118         bool cleanup_done;
5119
5120         drm_for_each_crtc(crtc, &dev_priv->drm) {
5121                 struct drm_crtc_commit *commit;
5122                 spin_lock(&crtc->commit_lock);
5123                 commit = list_first_entry_or_null(&crtc->commit_list,
5124                                                   struct drm_crtc_commit, commit_entry);
5125                 cleanup_done = commit ?
5126                         try_wait_for_completion(&commit->cleanup_done) : true;
5127                 spin_unlock(&crtc->commit_lock);
5128
5129                 if (cleanup_done)
5130                         continue;
5131
5132                 drm_crtc_wait_one_vblank(crtc);
5133
5134                 return true;
5135         }
5136
5137         return false;
5138 }
5139
5140 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5141 {
5142         u32 temp;
5143
5144         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
5145
5146         mutex_lock(&dev_priv->sb_lock);
5147
5148         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5149         temp |= SBI_SSCCTL_DISABLE;
5150         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5151
5152         mutex_unlock(&dev_priv->sb_lock);
5153 }
5154
5155 /* Program iCLKIP clock to the desired frequency */
5156 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5157 {
5158         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5159         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5160         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5161         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5162         u32 temp;
5163
5164         lpt_disable_iclkip(dev_priv);
5165
5166         /* The iCLK virtual clock root frequency is in MHz,
5167          * but the adjusted_mode->crtc_clock in in KHz. To get the
5168          * divisors, it is necessary to divide one by another, so we
5169          * convert the virtual clock precision to KHz here for higher
5170          * precision.
5171          */
5172         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5173                 u32 iclk_virtual_root_freq = 172800 * 1000;
5174                 u32 iclk_pi_range = 64;
5175                 u32 desired_divisor;
5176
5177                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5178                                                     clock << auxdiv);
5179                 divsel = (desired_divisor / iclk_pi_range) - 2;
5180                 phaseinc = desired_divisor % iclk_pi_range;
5181
5182                 /*
5183                  * Near 20MHz is a corner case which is
5184                  * out of range for the 7-bit divisor
5185                  */
5186                 if (divsel <= 0x7f)
5187                         break;
5188         }
5189
5190         /* This should not happen with any sane values */
5191         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5192                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5193         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5194                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5195
5196         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5197                         clock,
5198                         auxdiv,
5199                         divsel,
5200                         phasedir,
5201                         phaseinc);
5202
5203         mutex_lock(&dev_priv->sb_lock);
5204
5205         /* Program SSCDIVINTPHASE6 */
5206         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5207         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5208         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5209         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5210         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5211         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5212         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5213         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5214
5215         /* Program SSCAUXDIV */
5216         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5217         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5218         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5219         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5220
5221         /* Enable modulator and associated divider */
5222         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5223         temp &= ~SBI_SSCCTL_DISABLE;
5224         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5225
5226         mutex_unlock(&dev_priv->sb_lock);
5227
5228         /* Wait for initialization time */
5229         udelay(24);
5230
5231         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5232 }
5233
5234 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5235 {
5236         u32 divsel, phaseinc, auxdiv;
5237         u32 iclk_virtual_root_freq = 172800 * 1000;
5238         u32 iclk_pi_range = 64;
5239         u32 desired_divisor;
5240         u32 temp;
5241
5242         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5243                 return 0;
5244
5245         mutex_lock(&dev_priv->sb_lock);
5246
5247         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5248         if (temp & SBI_SSCCTL_DISABLE) {
5249                 mutex_unlock(&dev_priv->sb_lock);
5250                 return 0;
5251         }
5252
5253         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5254         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5255                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5256         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5257                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5258
5259         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5260         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5261                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5262
5263         mutex_unlock(&dev_priv->sb_lock);
5264
5265         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5266
5267         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5268                                  desired_divisor << auxdiv);
5269 }
5270
5271 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5272                                                 enum pipe pch_transcoder)
5273 {
5274         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5276         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5277
5278         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5279                    I915_READ(HTOTAL(cpu_transcoder)));
5280         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5281                    I915_READ(HBLANK(cpu_transcoder)));
5282         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5283                    I915_READ(HSYNC(cpu_transcoder)));
5284
5285         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5286                    I915_READ(VTOTAL(cpu_transcoder)));
5287         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5288                    I915_READ(VBLANK(cpu_transcoder)));
5289         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5290                    I915_READ(VSYNC(cpu_transcoder)));
5291         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5292                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
5293 }
5294
5295 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5296 {
5297         u32 temp;
5298
5299         temp = I915_READ(SOUTH_CHICKEN1);
5300         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5301                 return;
5302
5303         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5304         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5305
5306         temp &= ~FDI_BC_BIFURCATION_SELECT;
5307         if (enable)
5308                 temp |= FDI_BC_BIFURCATION_SELECT;
5309
5310         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5311         I915_WRITE(SOUTH_CHICKEN1, temp);
5312         POSTING_READ(SOUTH_CHICKEN1);
5313 }
5314
5315 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5316 {
5317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5319
5320         switch (crtc->pipe) {
5321         case PIPE_A:
5322                 break;
5323         case PIPE_B:
5324                 if (crtc_state->fdi_lanes > 2)
5325                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5326                 else
5327                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5328
5329                 break;
5330         case PIPE_C:
5331                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5332
5333                 break;
5334         default:
5335                 BUG();
5336         }
5337 }
5338
5339 /*
5340  * Finds the encoder associated with the given CRTC. This can only be
5341  * used when we know that the CRTC isn't feeding multiple encoders!
5342  */
5343 static struct intel_encoder *
5344 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5345                            const struct intel_crtc_state *crtc_state)
5346 {
5347         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5348         const struct drm_connector_state *connector_state;
5349         const struct drm_connector *connector;
5350         struct intel_encoder *encoder = NULL;
5351         int num_encoders = 0;
5352         int i;
5353
5354         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5355                 if (connector_state->crtc != &crtc->base)
5356                         continue;
5357
5358                 encoder = to_intel_encoder(connector_state->best_encoder);
5359                 num_encoders++;
5360         }
5361
5362         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5363              num_encoders, pipe_name(crtc->pipe));
5364
5365         return encoder;
5366 }
5367
5368 /*
5369  * Enable PCH resources required for PCH ports:
5370  *   - PCH PLLs
5371  *   - FDI training & RX/TX
5372  *   - update transcoder timings
5373  *   - DP transcoding bits
5374  *   - transcoder
5375  */
5376 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5377                                 const struct intel_crtc_state *crtc_state)
5378 {
5379         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = to_i915(dev);
5382         enum pipe pipe = crtc->pipe;
5383         u32 temp;
5384
5385         assert_pch_transcoder_disabled(dev_priv, pipe);
5386
5387         if (IS_IVYBRIDGE(dev_priv))
5388                 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5389
5390         /* Write the TU size bits before fdi link training, so that error
5391          * detection works. */
5392         I915_WRITE(FDI_RX_TUSIZE1(pipe),
5393                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5394
5395         /* For PCH output, training FDI link */
5396         dev_priv->display.fdi_link_train(crtc, crtc_state);
5397
5398         /* We need to program the right clock selection before writing the pixel
5399          * mutliplier into the DPLL. */
5400         if (HAS_PCH_CPT(dev_priv)) {
5401                 u32 sel;
5402
5403                 temp = I915_READ(PCH_DPLL_SEL);
5404                 temp |= TRANS_DPLL_ENABLE(pipe);
5405                 sel = TRANS_DPLLB_SEL(pipe);
5406                 if (crtc_state->shared_dpll ==
5407                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5408                         temp |= sel;
5409                 else
5410                         temp &= ~sel;
5411                 I915_WRITE(PCH_DPLL_SEL, temp);
5412         }
5413
5414         /* XXX: pch pll's can be enabled any time before we enable the PCH
5415          * transcoder, and we actually should do this to not upset any PCH
5416          * transcoder that already use the clock when we share it.
5417          *
5418          * Note that enable_shared_dpll tries to do the right thing, but
5419          * get_shared_dpll unconditionally resets the pll - we need that to have
5420          * the right LVDS enable sequence. */
5421         intel_enable_shared_dpll(crtc_state);
5422
5423         /* set transcoder timing, panel must allow it */
5424         assert_panel_unlocked(dev_priv, pipe);
5425         ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5426
5427         intel_fdi_normal_train(crtc);
5428
5429         /* For PCH DP, enable TRANS_DP_CTL */
5430         if (HAS_PCH_CPT(dev_priv) &&
5431             intel_crtc_has_dp_encoder(crtc_state)) {
5432                 const struct drm_display_mode *adjusted_mode =
5433                         &crtc_state->hw.adjusted_mode;
5434                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5435                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5436                 enum port port;
5437
5438                 temp = I915_READ(reg);
5439                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5440                           TRANS_DP_SYNC_MASK |
5441                           TRANS_DP_BPC_MASK);
5442                 temp |= TRANS_DP_OUTPUT_ENABLE;
5443                 temp |= bpc << 9; /* same format but at 11:9 */
5444
5445                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5446                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5447                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5448                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5449
5450                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5451                 WARN_ON(port < PORT_B || port > PORT_D);
5452                 temp |= TRANS_DP_PORT_SEL(port);
5453
5454                 I915_WRITE(reg, temp);
5455         }
5456
5457         ironlake_enable_pch_transcoder(crtc_state);
5458 }
5459
5460 static void lpt_pch_enable(const struct intel_atomic_state *state,
5461                            const struct intel_crtc_state *crtc_state)
5462 {
5463         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5465         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5466
5467         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5468
5469         lpt_program_iclkip(crtc_state);
5470
5471         /* Set transcoder timing. */
5472         ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5473
5474         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5475 }
5476
5477 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5478                                enum pipe pipe)
5479 {
5480         i915_reg_t dslreg = PIPEDSL(pipe);
5481         u32 temp;
5482
5483         temp = I915_READ(dslreg);
5484         udelay(500);
5485         if (wait_for(I915_READ(dslreg) != temp, 5)) {
5486                 if (wait_for(I915_READ(dslreg) != temp, 5))
5487                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5488         }
5489 }
5490
5491 /*
5492  * The hardware phase 0.0 refers to the center of the pixel.
5493  * We want to start from the top/left edge which is phase
5494  * -0.5. That matches how the hardware calculates the scaling
5495  * factors (from top-left of the first pixel to bottom-right
5496  * of the last pixel, as opposed to the pixel centers).
5497  *
5498  * For 4:2:0 subsampled chroma planes we obviously have to
5499  * adjust that so that the chroma sample position lands in
5500  * the right spot.
5501  *
5502  * Note that for packed YCbCr 4:2:2 formats there is no way to
5503  * control chroma siting. The hardware simply replicates the
5504  * chroma samples for both of the luma samples, and thus we don't
5505  * actually get the expected MPEG2 chroma siting convention :(
5506  * The same behaviour is observed on pre-SKL platforms as well.
5507  *
5508  * Theory behind the formula (note that we ignore sub-pixel
5509  * source coordinates):
5510  * s = source sample position
5511  * d = destination sample position
5512  *
5513  * Downscaling 4:1:
5514  * -0.5
5515  * | 0.0
5516  * | |     1.5 (initial phase)
5517  * | |     |
5518  * v v     v
5519  * | s | s | s | s |
5520  * |       d       |
5521  *
5522  * Upscaling 1:4:
5523  * -0.5
5524  * | -0.375 (initial phase)
5525  * | |     0.0
5526  * | |     |
5527  * v v     v
5528  * |       s       |
5529  * | d | d | d | d |
5530  */
5531 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5532 {
5533         int phase = -0x8000;
5534         u16 trip = 0;
5535
5536         if (chroma_cosited)
5537                 phase += (sub - 1) * 0x8000 / sub;
5538
5539         phase += scale / (2 * sub);
5540
5541         /*
5542          * Hardware initial phase limited to [-0.5:1.5].
5543          * Since the max hardware scale factor is 3.0, we
5544          * should never actually excdeed 1.0 here.
5545          */
5546         WARN_ON(phase < -0x8000 || phase > 0x18000);
5547
5548         if (phase < 0)
5549                 phase = 0x10000 + phase;
5550         else
5551                 trip = PS_PHASE_TRIP;
5552
5553         return ((phase >> 2) & PS_PHASE_MASK) | trip;
5554 }
5555
5556 #define SKL_MIN_SRC_W 8
5557 #define SKL_MAX_SRC_W 4096
5558 #define SKL_MIN_SRC_H 8
5559 #define SKL_MAX_SRC_H 4096
5560 #define SKL_MIN_DST_W 8
5561 #define SKL_MAX_DST_W 4096
5562 #define SKL_MIN_DST_H 8
5563 #define SKL_MAX_DST_H 4096
5564 #define ICL_MAX_SRC_W 5120
5565 #define ICL_MAX_SRC_H 4096
5566 #define ICL_MAX_DST_W 5120
5567 #define ICL_MAX_DST_H 4096
5568 #define SKL_MIN_YUV_420_SRC_W 16
5569 #define SKL_MIN_YUV_420_SRC_H 16
5570
5571 static int
5572 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5573                   unsigned int scaler_user, int *scaler_id,
5574                   int src_w, int src_h, int dst_w, int dst_h,
5575                   const struct drm_format_info *format, bool need_scaler)
5576 {
5577         struct intel_crtc_scaler_state *scaler_state =
5578                 &crtc_state->scaler_state;
5579         struct intel_crtc *intel_crtc =
5580                 to_intel_crtc(crtc_state->uapi.crtc);
5581         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5582         const struct drm_display_mode *adjusted_mode =
5583                 &crtc_state->hw.adjusted_mode;
5584
5585         /*
5586          * Src coordinates are already rotated by 270 degrees for
5587          * the 90/270 degree plane rotation cases (to match the
5588          * GTT mapping), hence no need to account for rotation here.
5589          */
5590         if (src_w != dst_w || src_h != dst_h)
5591                 need_scaler = true;
5592
5593         /*
5594          * Scaling/fitting not supported in IF-ID mode in GEN9+
5595          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5596          * Once NV12 is enabled, handle it here while allocating scaler
5597          * for NV12.
5598          */
5599         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
5600             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5601                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5602                 return -EINVAL;
5603         }
5604
5605         /*
5606          * if plane is being disabled or scaler is no more required or force detach
5607          *  - free scaler binded to this plane/crtc
5608          *  - in order to do this, update crtc->scaler_usage
5609          *
5610          * Here scaler state in crtc_state is set free so that
5611          * scaler can be assigned to other user. Actual register
5612          * update to free the scaler is done in plane/panel-fit programming.
5613          * For this purpose crtc/plane_state->scaler_id isn't reset here.
5614          */
5615         if (force_detach || !need_scaler) {
5616                 if (*scaler_id >= 0) {
5617                         scaler_state->scaler_users &= ~(1 << scaler_user);
5618                         scaler_state->scalers[*scaler_id].in_use = 0;
5619
5620                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5621                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5622                                 intel_crtc->pipe, scaler_user, *scaler_id,
5623                                 scaler_state->scaler_users);
5624                         *scaler_id = -1;
5625                 }
5626                 return 0;
5627         }
5628
5629         if (format && drm_format_info_is_yuv_semiplanar(format) &&
5630             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5631                 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5632                 return -EINVAL;
5633         }
5634
5635         /* range checks */
5636         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5637             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5638             (INTEL_GEN(dev_priv) >= 11 &&
5639              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5640               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5641             (INTEL_GEN(dev_priv) < 11 &&
5642              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5643               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5644                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5645                         "size is out of scaler range\n",
5646                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5647                 return -EINVAL;
5648         }
5649
5650         /* mark this plane as a scaler user in crtc_state */
5651         scaler_state->scaler_users |= (1 << scaler_user);
5652         DRM_DEBUG_KMS("scaler_user index %u.%u: "
5653                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5654                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5655                 scaler_state->scaler_users);
5656
5657         return 0;
5658 }
5659
5660 /**
5661  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5662  *
5663  * @state: crtc's scaler state
5664  *
5665  * Return
5666  *     0 - scaler_usage updated successfully
5667  *    error - requested scaling cannot be supported or other error condition
5668  */
5669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5670 {
5671         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
5672         bool need_scaler = false;
5673
5674         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5675                 need_scaler = true;
5676
5677         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
5678                                  &state->scaler_state.scaler_id,
5679                                  state->pipe_src_w, state->pipe_src_h,
5680                                  adjusted_mode->crtc_hdisplay,
5681                                  adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5682 }
5683
5684 /**
5685  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5686  * @crtc_state: crtc's scaler state
5687  * @plane_state: atomic plane state to update
5688  *
5689  * Return
5690  *     0 - scaler_usage updated successfully
5691  *    error - requested scaling cannot be supported or other error condition
5692  */
5693 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5694                                    struct intel_plane_state *plane_state)
5695 {
5696         struct intel_plane *intel_plane =
5697                 to_intel_plane(plane_state->uapi.plane);
5698         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5699         struct drm_framebuffer *fb = plane_state->hw.fb;
5700         int ret;
5701         bool force_detach = !fb || !plane_state->uapi.visible;
5702         bool need_scaler = false;
5703
5704         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5705         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5706             fb && drm_format_info_is_yuv_semiplanar(fb->format))
5707                 need_scaler = true;
5708
5709         ret = skl_update_scaler(crtc_state, force_detach,
5710                                 drm_plane_index(&intel_plane->base),
5711                                 &plane_state->scaler_id,
5712                                 drm_rect_width(&plane_state->uapi.src) >> 16,
5713                                 drm_rect_height(&plane_state->uapi.src) >> 16,
5714                                 drm_rect_width(&plane_state->uapi.dst),
5715                                 drm_rect_height(&plane_state->uapi.dst),
5716                                 fb ? fb->format : NULL, need_scaler);
5717
5718         if (ret || plane_state->scaler_id < 0)
5719                 return ret;
5720
5721         /* check colorkey */
5722         if (plane_state->ckey.flags) {
5723                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5724                               intel_plane->base.base.id,
5725                               intel_plane->base.name);
5726                 return -EINVAL;
5727         }
5728
5729         /* Check src format */
5730         switch (fb->format->format) {
5731         case DRM_FORMAT_RGB565:
5732         case DRM_FORMAT_XBGR8888:
5733         case DRM_FORMAT_XRGB8888:
5734         case DRM_FORMAT_ABGR8888:
5735         case DRM_FORMAT_ARGB8888:
5736         case DRM_FORMAT_XRGB2101010:
5737         case DRM_FORMAT_XBGR2101010:
5738         case DRM_FORMAT_ARGB2101010:
5739         case DRM_FORMAT_ABGR2101010:
5740         case DRM_FORMAT_YUYV:
5741         case DRM_FORMAT_YVYU:
5742         case DRM_FORMAT_UYVY:
5743         case DRM_FORMAT_VYUY:
5744         case DRM_FORMAT_NV12:
5745         case DRM_FORMAT_P010:
5746         case DRM_FORMAT_P012:
5747         case DRM_FORMAT_P016:
5748         case DRM_FORMAT_Y210:
5749         case DRM_FORMAT_Y212:
5750         case DRM_FORMAT_Y216:
5751         case DRM_FORMAT_XVYU2101010:
5752         case DRM_FORMAT_XVYU12_16161616:
5753         case DRM_FORMAT_XVYU16161616:
5754                 break;
5755         case DRM_FORMAT_XBGR16161616F:
5756         case DRM_FORMAT_ABGR16161616F:
5757         case DRM_FORMAT_XRGB16161616F:
5758         case DRM_FORMAT_ARGB16161616F:
5759                 if (INTEL_GEN(dev_priv) >= 11)
5760                         break;
5761                 /* fall through */
5762         default:
5763                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5764                               intel_plane->base.base.id, intel_plane->base.name,
5765                               fb->base.id, fb->format->format);
5766                 return -EINVAL;
5767         }
5768
5769         return 0;
5770 }
5771
5772 static void skylake_scaler_disable(struct intel_crtc *crtc)
5773 {
5774         int i;
5775
5776         for (i = 0; i < crtc->num_scalers; i++)
5777                 skl_detach_scaler(crtc, i);
5778 }
5779
5780 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5781 {
5782         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5784         enum pipe pipe = crtc->pipe;
5785         const struct intel_crtc_scaler_state *scaler_state =
5786                 &crtc_state->scaler_state;
5787
5788         if (crtc_state->pch_pfit.enabled) {
5789                 u16 uv_rgb_hphase, uv_rgb_vphase;
5790                 int pfit_w, pfit_h, hscale, vscale;
5791                 int id;
5792
5793                 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5794                         return;
5795
5796                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5797                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5798
5799                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5800                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5801
5802                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5803                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5804
5805                 id = scaler_state->scaler_id;
5806                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5807                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5808                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5809                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5810                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5811                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5812                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5813                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5814         }
5815 }
5816
5817 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5818 {
5819         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5821         enum pipe pipe = crtc->pipe;
5822
5823         if (crtc_state->pch_pfit.enabled) {
5824                 /* Force use of hard-coded filter coefficients
5825                  * as some pre-programmed values are broken,
5826                  * e.g. x201.
5827                  */
5828                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5829                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5830                                                  PF_PIPE_SEL_IVB(pipe));
5831                 else
5832                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5833                 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5834                 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5835         }
5836 }
5837
5838 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5839 {
5840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5841         struct drm_device *dev = crtc->base.dev;
5842         struct drm_i915_private *dev_priv = to_i915(dev);
5843
5844         if (!crtc_state->ips_enabled)
5845                 return;
5846
5847         /*
5848          * We can only enable IPS after we enable a plane and wait for a vblank
5849          * This function is called from post_plane_update, which is run after
5850          * a vblank wait.
5851          */
5852         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5853
5854         if (IS_BROADWELL(dev_priv)) {
5855                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5856                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5857                 /* Quoting Art Runyan: "its not safe to expect any particular
5858                  * value in IPS_CTL bit 31 after enabling IPS through the
5859                  * mailbox." Moreover, the mailbox may return a bogus state,
5860                  * so we need to just enable it and continue on.
5861                  */
5862         } else {
5863                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5864                 /* The bit only becomes 1 in the next vblank, so this wait here
5865                  * is essentially intel_wait_for_vblank. If we don't have this
5866                  * and don't wait for vblanks until the end of crtc_enable, then
5867                  * the HW state readout code will complain that the expected
5868                  * IPS_CTL value is not the one we read. */
5869                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5870                         DRM_ERROR("Timed out waiting for IPS enable\n");
5871         }
5872 }
5873
5874 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5875 {
5876         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = to_i915(dev);
5879
5880         if (!crtc_state->ips_enabled)
5881                 return;
5882
5883         if (IS_BROADWELL(dev_priv)) {
5884                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5885                 /*
5886                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5887                  * 42ms timeout value leads to occasional timeouts so use 100ms
5888                  * instead.
5889                  */
5890                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5891                         DRM_ERROR("Timed out waiting for IPS disable\n");
5892         } else {
5893                 I915_WRITE(IPS_CTL, 0);
5894                 POSTING_READ(IPS_CTL);
5895         }
5896
5897         /* We need to wait for a vblank before we can disable the plane. */
5898         intel_wait_for_vblank(dev_priv, crtc->pipe);
5899 }
5900
5901 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5902 {
5903         if (intel_crtc->overlay)
5904                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5905
5906         /* Let userspace switch the overlay on again. In most cases userspace
5907          * has to recompute where to put it anyway.
5908          */
5909 }
5910
5911 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5912                                        const struct intel_crtc_state *new_crtc_state)
5913 {
5914         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5915         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5916
5917         if (!old_crtc_state->ips_enabled)
5918                 return false;
5919
5920         if (needs_modeset(new_crtc_state))
5921                 return true;
5922
5923         /*
5924          * Workaround : Do not read or write the pipe palette/gamma data while
5925          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5926          *
5927          * Disable IPS before we program the LUT.
5928          */
5929         if (IS_HASWELL(dev_priv) &&
5930             (new_crtc_state->uapi.color_mgmt_changed ||
5931              new_crtc_state->update_pipe) &&
5932             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5933                 return true;
5934
5935         return !new_crtc_state->ips_enabled;
5936 }
5937
5938 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5939                                        const struct intel_crtc_state *new_crtc_state)
5940 {
5941         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5942         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5943
5944         if (!new_crtc_state->ips_enabled)
5945                 return false;
5946
5947         if (needs_modeset(new_crtc_state))
5948                 return true;
5949
5950         /*
5951          * Workaround : Do not read or write the pipe palette/gamma data while
5952          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5953          *
5954          * Re-enable IPS after the LUT has been programmed.
5955          */
5956         if (IS_HASWELL(dev_priv) &&
5957             (new_crtc_state->uapi.color_mgmt_changed ||
5958              new_crtc_state->update_pipe) &&
5959             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5960                 return true;
5961
5962         /*
5963          * We can't read out IPS on broadwell, assume the worst and
5964          * forcibly enable IPS on the first fastset.
5965          */
5966         if (new_crtc_state->update_pipe &&
5967             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5968                 return true;
5969
5970         return !old_crtc_state->ips_enabled;
5971 }
5972
5973 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
5974 {
5975         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5976
5977         if (!crtc_state->nv12_planes)
5978                 return false;
5979
5980         /* WA Display #0827: Gen9:all */
5981         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5982                 return true;
5983
5984         return false;
5985 }
5986
5987 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
5988 {
5989         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5990
5991         /* Wa_2006604312:icl */
5992         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5993                 return true;
5994
5995         return false;
5996 }
5997
5998 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
5999                             const struct intel_crtc_state *new_crtc_state)
6000 {
6001         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6002                 new_crtc_state->active_planes;
6003 }
6004
6005 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6006                              const struct intel_crtc_state *new_crtc_state)
6007 {
6008         return old_crtc_state->active_planes &&
6009                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6010 }
6011
6012 static void intel_post_plane_update(struct intel_atomic_state *state,
6013                                     struct intel_crtc *crtc)
6014 {
6015         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6016         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6017         const struct intel_crtc_state *old_crtc_state =
6018                 intel_atomic_get_old_crtc_state(state, crtc);
6019         const struct intel_crtc_state *new_crtc_state =
6020                 intel_atomic_get_new_crtc_state(state, crtc);
6021         const struct intel_plane_state *new_primary_state =
6022                 intel_atomic_get_new_plane_state(state, primary);
6023         enum pipe pipe = crtc->pipe;
6024
6025         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6026
6027         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6028                 intel_update_watermarks(crtc);
6029
6030         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6031                 hsw_enable_ips(new_crtc_state);
6032
6033         if (new_primary_state)
6034                 intel_fbc_post_update(crtc);
6035
6036         if (needs_nv12_wa(old_crtc_state) &&
6037             !needs_nv12_wa(new_crtc_state))
6038                 skl_wa_827(dev_priv, pipe, false);
6039
6040         if (needs_scalerclk_wa(old_crtc_state) &&
6041             !needs_scalerclk_wa(new_crtc_state))
6042                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6043 }
6044
6045 static void intel_pre_plane_update(struct intel_atomic_state *state,
6046                                    struct intel_crtc *crtc)
6047 {
6048         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6049         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
6050         const struct intel_crtc_state *old_crtc_state =
6051                 intel_atomic_get_old_crtc_state(state, crtc);
6052         const struct intel_crtc_state *new_crtc_state =
6053                 intel_atomic_get_new_crtc_state(state, crtc);
6054         const struct intel_plane_state *new_primary_state =
6055                 intel_atomic_get_new_plane_state(state, primary);
6056         enum pipe pipe = crtc->pipe;
6057
6058         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6059                 hsw_disable_ips(old_crtc_state);
6060
6061         if (new_primary_state &&
6062             intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state))
6063                 intel_wait_for_vblank(dev_priv, pipe);
6064
6065         if (new_primary_state)
6066                 intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state);
6067
6068         /* Display WA 827 */
6069         if (!needs_nv12_wa(old_crtc_state) &&
6070             needs_nv12_wa(new_crtc_state))
6071                 skl_wa_827(dev_priv, pipe, true);
6072
6073         /* Wa_2006604312:icl */
6074         if (!needs_scalerclk_wa(old_crtc_state) &&
6075             needs_scalerclk_wa(new_crtc_state))
6076                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6077
6078         /*
6079          * Vblank time updates from the shadow to live plane control register
6080          * are blocked if the memory self-refresh mode is active at that
6081          * moment. So to make sure the plane gets truly disabled, disable
6082          * first the self-refresh mode. The self-refresh enable bit in turn
6083          * will be checked/applied by the HW only at the next frame start
6084          * event which is after the vblank start event, so we need to have a
6085          * wait-for-vblank between disabling the plane and the pipe.
6086          */
6087         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6088             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6089                 intel_wait_for_vblank(dev_priv, pipe);
6090
6091         /*
6092          * IVB workaround: must disable low power watermarks for at least
6093          * one frame before enabling scaling.  LP watermarks can be re-enabled
6094          * when scaling is disabled.
6095          *
6096          * WaCxSRDisabledForSpriteScaling:ivb
6097          */
6098         if (old_crtc_state->hw.active &&
6099             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6100                 intel_wait_for_vblank(dev_priv, pipe);
6101
6102         /*
6103          * If we're doing a modeset we don't need to do any
6104          * pre-vblank watermark programming here.
6105          */
6106         if (!needs_modeset(new_crtc_state)) {
6107                 /*
6108                  * For platforms that support atomic watermarks, program the
6109                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6110                  * will be the intermediate values that are safe for both pre- and
6111                  * post- vblank; when vblank happens, the 'active' values will be set
6112                  * to the final 'target' values and we'll do this again to get the
6113                  * optimal watermarks.  For gen9+ platforms, the values we program here
6114                  * will be the final target values which will get automatically latched
6115                  * at vblank time; no further programming will be necessary.
6116                  *
6117                  * If a platform hasn't been transitioned to atomic watermarks yet,
6118                  * we'll continue to update watermarks the old way, if flags tell
6119                  * us to.
6120                  */
6121                 if (dev_priv->display.initial_watermarks)
6122                         dev_priv->display.initial_watermarks(state, crtc);
6123                 else if (new_crtc_state->update_wm_pre)
6124                         intel_update_watermarks(crtc);
6125         }
6126
6127         /*
6128          * Gen2 reports pipe underruns whenever all planes are disabled.
6129          * So disable underrun reporting before all the planes get disabled.
6130          *
6131          * We do this after .initial_watermarks() so that we have a
6132          * chance of catching underruns with the intermediate watermarks
6133          * vs. the old plane configuration.
6134          */
6135         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6136                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6137 }
6138
6139 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6140                                       struct intel_crtc *crtc)
6141 {
6142         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6143         const struct intel_crtc_state *new_crtc_state =
6144                 intel_atomic_get_new_crtc_state(state, crtc);
6145         unsigned int update_mask = new_crtc_state->update_planes;
6146         const struct intel_plane_state *old_plane_state;
6147         struct intel_plane *plane;
6148         unsigned fb_bits = 0;
6149         int i;
6150
6151         intel_crtc_dpms_overlay_disable(crtc);
6152
6153         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6154                 if (crtc->pipe != plane->pipe ||
6155                     !(update_mask & BIT(plane->id)))
6156                         continue;
6157
6158                 intel_disable_plane(plane, new_crtc_state);
6159
6160                 if (old_plane_state->uapi.visible)
6161                         fb_bits |= plane->frontbuffer_bit;
6162         }
6163
6164         intel_frontbuffer_flip(dev_priv, fb_bits);
6165 }
6166
6167 /*
6168  * intel_connector_primary_encoder - get the primary encoder for a connector
6169  * @connector: connector for which to return the encoder
6170  *
6171  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6172  * all connectors to their encoder, except for DP-MST connectors which have
6173  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6174  * pointed to by as many DP-MST connectors as there are pipes.
6175  */
6176 static struct intel_encoder *
6177 intel_connector_primary_encoder(struct intel_connector *connector)
6178 {
6179         struct intel_encoder *encoder;
6180
6181         if (connector->mst_port)
6182                 return &dp_to_dig_port(connector->mst_port)->base;
6183
6184         encoder = intel_attached_encoder(&connector->base);
6185         WARN_ON(!encoder);
6186
6187         return encoder;
6188 }
6189
6190 static bool
6191 intel_connector_needs_modeset(struct intel_atomic_state *state,
6192                               const struct drm_connector_state *old_conn_state,
6193                               const struct drm_connector_state *new_conn_state)
6194 {
6195         struct intel_crtc *old_crtc = old_conn_state->crtc ?
6196                                       to_intel_crtc(old_conn_state->crtc) : NULL;
6197         struct intel_crtc *new_crtc = new_conn_state->crtc ?
6198                                       to_intel_crtc(new_conn_state->crtc) : NULL;
6199
6200         return new_crtc != old_crtc ||
6201                (new_crtc &&
6202                 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6203 }
6204
6205 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6206 {
6207         struct drm_connector_state *old_conn_state;
6208         struct drm_connector_state *new_conn_state;
6209         struct drm_connector *conn;
6210         int i;
6211
6212         for_each_oldnew_connector_in_state(&state->base, conn,
6213                                            old_conn_state, new_conn_state, i) {
6214                 struct intel_encoder *encoder;
6215                 struct intel_crtc *crtc;
6216
6217                 if (!intel_connector_needs_modeset(state,
6218                                                    old_conn_state,
6219                                                    new_conn_state))
6220                         continue;
6221
6222                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6223                 if (!encoder->update_prepare)
6224                         continue;
6225
6226                 crtc = new_conn_state->crtc ?
6227                         to_intel_crtc(new_conn_state->crtc) : NULL;
6228                 encoder->update_prepare(state, encoder, crtc);
6229         }
6230 }
6231
6232 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6233 {
6234         struct drm_connector_state *old_conn_state;
6235         struct drm_connector_state *new_conn_state;
6236         struct drm_connector *conn;
6237         int i;
6238
6239         for_each_oldnew_connector_in_state(&state->base, conn,
6240                                            old_conn_state, new_conn_state, i) {
6241                 struct intel_encoder *encoder;
6242                 struct intel_crtc *crtc;
6243
6244                 if (!intel_connector_needs_modeset(state,
6245                                                    old_conn_state,
6246                                                    new_conn_state))
6247                         continue;
6248
6249                 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6250                 if (!encoder->update_complete)
6251                         continue;
6252
6253                 crtc = new_conn_state->crtc ?
6254                         to_intel_crtc(new_conn_state->crtc) : NULL;
6255                 encoder->update_complete(state, encoder, crtc);
6256         }
6257 }
6258
6259 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6260                                           struct intel_crtc *crtc)
6261 {
6262         const struct intel_crtc_state *crtc_state =
6263                 intel_atomic_get_new_crtc_state(state, crtc);
6264         const struct drm_connector_state *conn_state;
6265         struct drm_connector *conn;
6266         int i;
6267
6268         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6269                 struct intel_encoder *encoder =
6270                         to_intel_encoder(conn_state->best_encoder);
6271
6272                 if (conn_state->crtc != &crtc->base)
6273                         continue;
6274
6275                 if (encoder->pre_pll_enable)
6276                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6277         }
6278 }
6279
6280 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6281                                       struct intel_crtc *crtc)
6282 {
6283         const struct intel_crtc_state *crtc_state =
6284                 intel_atomic_get_new_crtc_state(state, crtc);
6285         const struct drm_connector_state *conn_state;
6286         struct drm_connector *conn;
6287         int i;
6288
6289         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6290                 struct intel_encoder *encoder =
6291                         to_intel_encoder(conn_state->best_encoder);
6292
6293                 if (conn_state->crtc != &crtc->base)
6294                         continue;
6295
6296                 if (encoder->pre_enable)
6297                         encoder->pre_enable(encoder, crtc_state, conn_state);
6298         }
6299 }
6300
6301 static void intel_encoders_enable(struct intel_atomic_state *state,
6302                                   struct intel_crtc *crtc)
6303 {
6304         const struct intel_crtc_state *crtc_state =
6305                 intel_atomic_get_new_crtc_state(state, crtc);
6306         const struct drm_connector_state *conn_state;
6307         struct drm_connector *conn;
6308         int i;
6309
6310         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6311                 struct intel_encoder *encoder =
6312                         to_intel_encoder(conn_state->best_encoder);
6313
6314                 if (conn_state->crtc != &crtc->base)
6315                         continue;
6316
6317                 if (encoder->enable)
6318                         encoder->enable(encoder, crtc_state, conn_state);
6319                 intel_opregion_notify_encoder(encoder, true);
6320         }
6321 }
6322
6323 static void intel_encoders_disable(struct intel_atomic_state *state,
6324                                    struct intel_crtc *crtc)
6325 {
6326         const struct intel_crtc_state *old_crtc_state =
6327                 intel_atomic_get_old_crtc_state(state, crtc);
6328         const struct drm_connector_state *old_conn_state;
6329         struct drm_connector *conn;
6330         int i;
6331
6332         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6333                 struct intel_encoder *encoder =
6334                         to_intel_encoder(old_conn_state->best_encoder);
6335
6336                 if (old_conn_state->crtc != &crtc->base)
6337                         continue;
6338
6339                 intel_opregion_notify_encoder(encoder, false);
6340                 if (encoder->disable)
6341                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6342         }
6343 }
6344
6345 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6346                                         struct intel_crtc *crtc)
6347 {
6348         const struct intel_crtc_state *old_crtc_state =
6349                 intel_atomic_get_old_crtc_state(state, crtc);
6350         const struct drm_connector_state *old_conn_state;
6351         struct drm_connector *conn;
6352         int i;
6353
6354         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6355                 struct intel_encoder *encoder =
6356                         to_intel_encoder(old_conn_state->best_encoder);
6357
6358                 if (old_conn_state->crtc != &crtc->base)
6359                         continue;
6360
6361                 if (encoder->post_disable)
6362                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6363         }
6364 }
6365
6366 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6367                                             struct intel_crtc *crtc)
6368 {
6369         const struct intel_crtc_state *old_crtc_state =
6370                 intel_atomic_get_old_crtc_state(state, crtc);
6371         const struct drm_connector_state *old_conn_state;
6372         struct drm_connector *conn;
6373         int i;
6374
6375         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6376                 struct intel_encoder *encoder =
6377                         to_intel_encoder(old_conn_state->best_encoder);
6378
6379                 if (old_conn_state->crtc != &crtc->base)
6380                         continue;
6381
6382                 if (encoder->post_pll_disable)
6383                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6384         }
6385 }
6386
6387 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6388                                        struct intel_crtc *crtc)
6389 {
6390         const struct intel_crtc_state *crtc_state =
6391                 intel_atomic_get_new_crtc_state(state, crtc);
6392         const struct drm_connector_state *conn_state;
6393         struct drm_connector *conn;
6394         int i;
6395
6396         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6397                 struct intel_encoder *encoder =
6398                         to_intel_encoder(conn_state->best_encoder);
6399
6400                 if (conn_state->crtc != &crtc->base)
6401                         continue;
6402
6403                 if (encoder->update_pipe)
6404                         encoder->update_pipe(encoder, crtc_state, conn_state);
6405         }
6406 }
6407
6408 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6409 {
6410         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6411         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6412
6413         plane->disable_plane(plane, crtc_state);
6414 }
6415
6416 static void ironlake_crtc_enable(struct intel_atomic_state *state,
6417                                  struct intel_crtc *crtc)
6418 {
6419         const struct intel_crtc_state *new_crtc_state =
6420                 intel_atomic_get_new_crtc_state(state, crtc);
6421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6422         enum pipe pipe = crtc->pipe;
6423
6424         if (WARN_ON(crtc->active))
6425                 return;
6426
6427         /*
6428          * Sometimes spurious CPU pipe underruns happen during FDI
6429          * training, at least with VGA+HDMI cloning. Suppress them.
6430          *
6431          * On ILK we get an occasional spurious CPU pipe underruns
6432          * between eDP port A enable and vdd enable. Also PCH port
6433          * enable seems to result in the occasional CPU pipe underrun.
6434          *
6435          * Spurious PCH underruns also occur during PCH enabling.
6436          */
6437         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6438         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6439
6440         if (new_crtc_state->has_pch_encoder)
6441                 intel_prepare_shared_dpll(new_crtc_state);
6442
6443         if (intel_crtc_has_dp_encoder(new_crtc_state))
6444                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6445
6446         intel_set_pipe_timings(new_crtc_state);
6447         intel_set_pipe_src_size(new_crtc_state);
6448
6449         if (new_crtc_state->has_pch_encoder)
6450                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6451                                              &new_crtc_state->fdi_m_n, NULL);
6452
6453         ironlake_set_pipeconf(new_crtc_state);
6454
6455         crtc->active = true;
6456
6457         intel_encoders_pre_enable(state, crtc);
6458
6459         if (new_crtc_state->has_pch_encoder) {
6460                 /* Note: FDI PLL enabling _must_ be done before we enable the
6461                  * cpu pipes, hence this is separate from all the other fdi/pch
6462                  * enabling. */
6463                 ironlake_fdi_pll_enable(new_crtc_state);
6464         } else {
6465                 assert_fdi_tx_disabled(dev_priv, pipe);
6466                 assert_fdi_rx_disabled(dev_priv, pipe);
6467         }
6468
6469         ironlake_pfit_enable(new_crtc_state);
6470
6471         /*
6472          * On ILK+ LUT must be loaded before the pipe is running but with
6473          * clocks enabled
6474          */
6475         intel_color_load_luts(new_crtc_state);
6476         intel_color_commit(new_crtc_state);
6477         /* update DSPCNTR to configure gamma for pipe bottom color */
6478         intel_disable_primary_plane(new_crtc_state);
6479
6480         if (dev_priv->display.initial_watermarks)
6481                 dev_priv->display.initial_watermarks(state, crtc);
6482         intel_enable_pipe(new_crtc_state);
6483
6484         if (new_crtc_state->has_pch_encoder)
6485                 ironlake_pch_enable(state, new_crtc_state);
6486
6487         intel_crtc_vblank_on(new_crtc_state);
6488
6489         intel_encoders_enable(state, crtc);
6490
6491         if (HAS_PCH_CPT(dev_priv))
6492                 cpt_verify_modeset(dev_priv, pipe);
6493
6494         /*
6495          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6496          * And a second vblank wait is needed at least on ILK with
6497          * some interlaced HDMI modes. Let's do the double wait always
6498          * in case there are more corner cases we don't know about.
6499          */
6500         if (new_crtc_state->has_pch_encoder) {
6501                 intel_wait_for_vblank(dev_priv, pipe);
6502                 intel_wait_for_vblank(dev_priv, pipe);
6503         }
6504         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6505         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6506 }
6507
6508 /* IPS only exists on ULT machines and is tied to pipe A. */
6509 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6510 {
6511         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6512 }
6513
6514 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6515                                             enum pipe pipe, bool apply)
6516 {
6517         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6518         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6519
6520         if (apply)
6521                 val |= mask;
6522         else
6523                 val &= ~mask;
6524
6525         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6526 }
6527
6528 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6529 {
6530         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6531         enum pipe pipe = crtc->pipe;
6532         u32 val;
6533
6534         val = MBUS_DBOX_A_CREDIT(2);
6535
6536         if (INTEL_GEN(dev_priv) >= 12) {
6537                 val |= MBUS_DBOX_BW_CREDIT(2);
6538                 val |= MBUS_DBOX_B_CREDIT(12);
6539         } else {
6540                 val |= MBUS_DBOX_BW_CREDIT(1);
6541                 val |= MBUS_DBOX_B_CREDIT(8);
6542         }
6543
6544         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6545 }
6546
6547 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
6548 {
6549         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6550         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6551         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
6552         u32 val;
6553
6554         val = I915_READ(reg);
6555         val &= ~HSW_FRAME_START_DELAY_MASK;
6556         val |= HSW_FRAME_START_DELAY(0);
6557         I915_WRITE(reg, val);
6558 }
6559
6560 static void haswell_crtc_enable(struct intel_atomic_state *state,
6561                                 struct intel_crtc *crtc)
6562 {
6563         const struct intel_crtc_state *new_crtc_state =
6564                 intel_atomic_get_new_crtc_state(state, crtc);
6565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6566         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
6567         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
6568         bool psl_clkgate_wa;
6569
6570         if (WARN_ON(crtc->active))
6571                 return;
6572
6573         intel_encoders_pre_pll_enable(state, crtc);
6574
6575         if (new_crtc_state->shared_dpll)
6576                 intel_enable_shared_dpll(new_crtc_state);
6577
6578         intel_encoders_pre_enable(state, crtc);
6579
6580         if (intel_crtc_has_dp_encoder(new_crtc_state))
6581                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6582
6583         if (!transcoder_is_dsi(cpu_transcoder))
6584                 intel_set_pipe_timings(new_crtc_state);
6585
6586         if (INTEL_GEN(dev_priv) >= 11)
6587                 icl_enable_trans_port_sync(new_crtc_state);
6588
6589         intel_set_pipe_src_size(new_crtc_state);
6590
6591         if (cpu_transcoder != TRANSCODER_EDP &&
6592             !transcoder_is_dsi(cpu_transcoder))
6593                 I915_WRITE(PIPE_MULT(cpu_transcoder),
6594                            new_crtc_state->pixel_multiplier - 1);
6595
6596         if (new_crtc_state->has_pch_encoder)
6597                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6598                                              &new_crtc_state->fdi_m_n, NULL);
6599
6600         if (!transcoder_is_dsi(cpu_transcoder)) {
6601                 hsw_set_frame_start_delay(new_crtc_state);
6602                 haswell_set_pipeconf(new_crtc_state);
6603         }
6604
6605         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6606                 bdw_set_pipemisc(new_crtc_state);
6607
6608         crtc->active = true;
6609
6610         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6611         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6612                 new_crtc_state->pch_pfit.enabled;
6613         if (psl_clkgate_wa)
6614                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6615
6616         if (INTEL_GEN(dev_priv) >= 9)
6617                 skylake_pfit_enable(new_crtc_state);
6618         else
6619                 ironlake_pfit_enable(new_crtc_state);
6620
6621         /*
6622          * On ILK+ LUT must be loaded before the pipe is running but with
6623          * clocks enabled
6624          */
6625         intel_color_load_luts(new_crtc_state);
6626         intel_color_commit(new_crtc_state);
6627         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6628         if (INTEL_GEN(dev_priv) < 9)
6629                 intel_disable_primary_plane(new_crtc_state);
6630
6631         if (INTEL_GEN(dev_priv) >= 11)
6632                 icl_set_pipe_chicken(crtc);
6633
6634         if (!transcoder_is_dsi(cpu_transcoder))
6635                 intel_ddi_enable_transcoder_func(new_crtc_state);
6636
6637         if (dev_priv->display.initial_watermarks)
6638                 dev_priv->display.initial_watermarks(state, crtc);
6639
6640         if (INTEL_GEN(dev_priv) >= 11)
6641                 icl_pipe_mbus_enable(crtc);
6642
6643         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6644         if (!transcoder_is_dsi(cpu_transcoder))
6645                 intel_enable_pipe(new_crtc_state);
6646
6647         if (new_crtc_state->has_pch_encoder)
6648                 lpt_pch_enable(state, new_crtc_state);
6649
6650         intel_crtc_vblank_on(new_crtc_state);
6651
6652         intel_encoders_enable(state, crtc);
6653
6654         if (psl_clkgate_wa) {
6655                 intel_wait_for_vblank(dev_priv, pipe);
6656                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6657         }
6658
6659         /* If we change the relative order between pipe/planes enabling, we need
6660          * to change the workaround. */
6661         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
6662         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6663                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6664                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6665         }
6666 }
6667
6668 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6669 {
6670         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6671         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6672         enum pipe pipe = crtc->pipe;
6673
6674         /* To avoid upsetting the power well on haswell only disable the pfit if
6675          * it's in use. The hw state code will make sure we get this right. */
6676         if (old_crtc_state->pch_pfit.enabled) {
6677                 I915_WRITE(PF_CTL(pipe), 0);
6678                 I915_WRITE(PF_WIN_POS(pipe), 0);
6679                 I915_WRITE(PF_WIN_SZ(pipe), 0);
6680         }
6681 }
6682
6683 static void ironlake_crtc_disable(struct intel_atomic_state *state,
6684                                   struct intel_crtc *crtc)
6685 {
6686         const struct intel_crtc_state *old_crtc_state =
6687                 intel_atomic_get_old_crtc_state(state, crtc);
6688         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6689         enum pipe pipe = crtc->pipe;
6690
6691         /*
6692          * Sometimes spurious CPU pipe underruns happen when the
6693          * pipe is already disabled, but FDI RX/TX is still enabled.
6694          * Happens at least with VGA+HDMI cloning. Suppress them.
6695          */
6696         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6697         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6698
6699         intel_encoders_disable(state, crtc);
6700
6701         intel_crtc_vblank_off(crtc);
6702
6703         intel_disable_pipe(old_crtc_state);
6704
6705         ironlake_pfit_disable(old_crtc_state);
6706
6707         if (old_crtc_state->has_pch_encoder)
6708                 ironlake_fdi_disable(crtc);
6709
6710         intel_encoders_post_disable(state, crtc);
6711
6712         if (old_crtc_state->has_pch_encoder) {
6713                 ironlake_disable_pch_transcoder(dev_priv, pipe);
6714
6715                 if (HAS_PCH_CPT(dev_priv)) {
6716                         i915_reg_t reg;
6717                         u32 temp;
6718
6719                         /* disable TRANS_DP_CTL */
6720                         reg = TRANS_DP_CTL(pipe);
6721                         temp = I915_READ(reg);
6722                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6723                                   TRANS_DP_PORT_SEL_MASK);
6724                         temp |= TRANS_DP_PORT_SEL_NONE;
6725                         I915_WRITE(reg, temp);
6726
6727                         /* disable DPLL_SEL */
6728                         temp = I915_READ(PCH_DPLL_SEL);
6729                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6730                         I915_WRITE(PCH_DPLL_SEL, temp);
6731                 }
6732
6733                 ironlake_fdi_pll_disable(crtc);
6734         }
6735
6736         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6737         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6738 }
6739
6740 static void haswell_crtc_disable(struct intel_atomic_state *state,
6741                                  struct intel_crtc *crtc)
6742 {
6743         const struct intel_crtc_state *old_crtc_state =
6744                 intel_atomic_get_old_crtc_state(state, crtc);
6745         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6746         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6747
6748         intel_encoders_disable(state, crtc);
6749
6750         intel_crtc_vblank_off(crtc);
6751
6752         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6753         if (!transcoder_is_dsi(cpu_transcoder))
6754                 intel_disable_pipe(old_crtc_state);
6755
6756         if (INTEL_GEN(dev_priv) >= 11)
6757                 icl_disable_transcoder_port_sync(old_crtc_state);
6758
6759         if (!transcoder_is_dsi(cpu_transcoder))
6760                 intel_ddi_disable_transcoder_func(old_crtc_state);
6761
6762         intel_dsc_disable(old_crtc_state);
6763
6764         if (INTEL_GEN(dev_priv) >= 9)
6765                 skylake_scaler_disable(crtc);
6766         else
6767                 ironlake_pfit_disable(old_crtc_state);
6768
6769         intel_encoders_post_disable(state, crtc);
6770
6771         intel_encoders_post_pll_disable(state, crtc);
6772 }
6773
6774 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6775 {
6776         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6777         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6778
6779         if (!crtc_state->gmch_pfit.control)
6780                 return;
6781
6782         /*
6783          * The panel fitter should only be adjusted whilst the pipe is disabled,
6784          * according to register description and PRM.
6785          */
6786         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6787         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
6788
6789         I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6790         I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6791
6792         /* Border color in case we don't scale up to the full screen. Black by
6793          * default, change to something else for debugging. */
6794         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6795 }
6796
6797 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6798 {
6799         if (phy == PHY_NONE)
6800                 return false;
6801
6802         if (IS_ELKHARTLAKE(dev_priv))
6803                 return phy <= PHY_C;
6804
6805         if (INTEL_GEN(dev_priv) >= 11)
6806                 return phy <= PHY_B;
6807
6808         return false;
6809 }
6810
6811 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6812 {
6813         if (INTEL_GEN(dev_priv) >= 12)
6814                 return phy >= PHY_D && phy <= PHY_I;
6815
6816         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6817                 return phy >= PHY_C && phy <= PHY_F;
6818
6819         return false;
6820 }
6821
6822 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6823 {
6824         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6825                 return PHY_A;
6826
6827         return (enum phy)port;
6828 }
6829
6830 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6831 {
6832         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6833                 return PORT_TC_NONE;
6834
6835         if (INTEL_GEN(dev_priv) >= 12)
6836                 return port - PORT_D;
6837
6838         return port - PORT_C;
6839 }
6840
6841 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6842 {
6843         switch (port) {
6844         case PORT_A:
6845                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6846         case PORT_B:
6847                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6848         case PORT_C:
6849                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6850         case PORT_D:
6851                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6852         case PORT_E:
6853                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6854         case PORT_F:
6855                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6856         case PORT_G:
6857                 return POWER_DOMAIN_PORT_DDI_G_LANES;
6858         default:
6859                 MISSING_CASE(port);
6860                 return POWER_DOMAIN_PORT_OTHER;
6861         }
6862 }
6863
6864 enum intel_display_power_domain
6865 intel_aux_power_domain(struct intel_digital_port *dig_port)
6866 {
6867         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6868         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6869
6870         if (intel_phy_is_tc(dev_priv, phy) &&
6871             dig_port->tc_mode == TC_PORT_TBT_ALT) {
6872                 switch (dig_port->aux_ch) {
6873                 case AUX_CH_C:
6874                         return POWER_DOMAIN_AUX_C_TBT;
6875                 case AUX_CH_D:
6876                         return POWER_DOMAIN_AUX_D_TBT;
6877                 case AUX_CH_E:
6878                         return POWER_DOMAIN_AUX_E_TBT;
6879                 case AUX_CH_F:
6880                         return POWER_DOMAIN_AUX_F_TBT;
6881                 case AUX_CH_G:
6882                         return POWER_DOMAIN_AUX_G_TBT;
6883                 default:
6884                         MISSING_CASE(dig_port->aux_ch);
6885                         return POWER_DOMAIN_AUX_C_TBT;
6886                 }
6887         }
6888
6889         switch (dig_port->aux_ch) {
6890         case AUX_CH_A:
6891                 return POWER_DOMAIN_AUX_A;
6892         case AUX_CH_B:
6893                 return POWER_DOMAIN_AUX_B;
6894         case AUX_CH_C:
6895                 return POWER_DOMAIN_AUX_C;
6896         case AUX_CH_D:
6897                 return POWER_DOMAIN_AUX_D;
6898         case AUX_CH_E:
6899                 return POWER_DOMAIN_AUX_E;
6900         case AUX_CH_F:
6901                 return POWER_DOMAIN_AUX_F;
6902         case AUX_CH_G:
6903                 return POWER_DOMAIN_AUX_G;
6904         default:
6905                 MISSING_CASE(dig_port->aux_ch);
6906                 return POWER_DOMAIN_AUX_A;
6907         }
6908 }
6909
6910 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6911 {
6912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6913         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6914         struct drm_encoder *encoder;
6915         enum pipe pipe = crtc->pipe;
6916         u64 mask;
6917         enum transcoder transcoder = crtc_state->cpu_transcoder;
6918
6919         if (!crtc_state->hw.active)
6920                 return 0;
6921
6922         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6923         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6924         if (crtc_state->pch_pfit.enabled ||
6925             crtc_state->pch_pfit.force_thru)
6926                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6927
6928         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6929                                   crtc_state->uapi.encoder_mask) {
6930                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6931
6932                 mask |= BIT_ULL(intel_encoder->power_domain);
6933         }
6934
6935         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6936                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6937
6938         if (crtc_state->shared_dpll)
6939                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6940
6941         return mask;
6942 }
6943
6944 static u64
6945 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6946 {
6947         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6948         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6949         enum intel_display_power_domain domain;
6950         u64 domains, new_domains, old_domains;
6951
6952         old_domains = crtc->enabled_power_domains;
6953         crtc->enabled_power_domains = new_domains =
6954                 get_crtc_power_domains(crtc_state);
6955
6956         domains = new_domains & ~old_domains;
6957
6958         for_each_power_domain(domain, domains)
6959                 intel_display_power_get(dev_priv, domain);
6960
6961         return old_domains & ~new_domains;
6962 }
6963
6964 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6965                                       u64 domains)
6966 {
6967         enum intel_display_power_domain domain;
6968
6969         for_each_power_domain(domain, domains)
6970                 intel_display_power_put_unchecked(dev_priv, domain);
6971 }
6972
6973 static void valleyview_crtc_enable(struct intel_atomic_state *state,
6974                                    struct intel_crtc *crtc)
6975 {
6976         const struct intel_crtc_state *new_crtc_state =
6977                 intel_atomic_get_new_crtc_state(state, crtc);
6978         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6979         enum pipe pipe = crtc->pipe;
6980
6981         if (WARN_ON(crtc->active))
6982                 return;
6983
6984         if (intel_crtc_has_dp_encoder(new_crtc_state))
6985                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6986
6987         intel_set_pipe_timings(new_crtc_state);
6988         intel_set_pipe_src_size(new_crtc_state);
6989
6990         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6991                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6992                 I915_WRITE(CHV_CANVAS(pipe), 0);
6993         }
6994
6995         i9xx_set_pipeconf(new_crtc_state);
6996
6997         crtc->active = true;
6998
6999         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7000
7001         intel_encoders_pre_pll_enable(state, crtc);
7002
7003         if (IS_CHERRYVIEW(dev_priv)) {
7004                 chv_prepare_pll(crtc, new_crtc_state);
7005                 chv_enable_pll(crtc, new_crtc_state);
7006         } else {
7007                 vlv_prepare_pll(crtc, new_crtc_state);
7008                 vlv_enable_pll(crtc, new_crtc_state);
7009         }
7010
7011         intel_encoders_pre_enable(state, crtc);
7012
7013         i9xx_pfit_enable(new_crtc_state);
7014
7015         intel_color_load_luts(new_crtc_state);
7016         intel_color_commit(new_crtc_state);
7017         /* update DSPCNTR to configure gamma for pipe bottom color */
7018         intel_disable_primary_plane(new_crtc_state);
7019
7020         dev_priv->display.initial_watermarks(state, crtc);
7021         intel_enable_pipe(new_crtc_state);
7022
7023         intel_crtc_vblank_on(new_crtc_state);
7024
7025         intel_encoders_enable(state, crtc);
7026 }
7027
7028 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7029 {
7030         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7031         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7032
7033         I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
7034         I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
7035 }
7036
7037 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7038                              struct intel_crtc *crtc)
7039 {
7040         const struct intel_crtc_state *new_crtc_state =
7041                 intel_atomic_get_new_crtc_state(state, crtc);
7042         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7043         enum pipe pipe = crtc->pipe;
7044
7045         if (WARN_ON(crtc->active))
7046                 return;
7047
7048         i9xx_set_pll_dividers(new_crtc_state);
7049
7050         if (intel_crtc_has_dp_encoder(new_crtc_state))
7051                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7052
7053         intel_set_pipe_timings(new_crtc_state);
7054         intel_set_pipe_src_size(new_crtc_state);
7055
7056         i9xx_set_pipeconf(new_crtc_state);
7057
7058         crtc->active = true;
7059
7060         if (!IS_GEN(dev_priv, 2))
7061                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7062
7063         intel_encoders_pre_enable(state, crtc);
7064
7065         i9xx_enable_pll(crtc, new_crtc_state);
7066
7067         i9xx_pfit_enable(new_crtc_state);
7068
7069         intel_color_load_luts(new_crtc_state);
7070         intel_color_commit(new_crtc_state);
7071         /* update DSPCNTR to configure gamma for pipe bottom color */
7072         intel_disable_primary_plane(new_crtc_state);
7073
7074         if (dev_priv->display.initial_watermarks)
7075                 dev_priv->display.initial_watermarks(state, crtc);
7076         else
7077                 intel_update_watermarks(crtc);
7078         intel_enable_pipe(new_crtc_state);
7079
7080         intel_crtc_vblank_on(new_crtc_state);
7081
7082         intel_encoders_enable(state, crtc);
7083 }
7084
7085 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7086 {
7087         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7088         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7089
7090         if (!old_crtc_state->gmch_pfit.control)
7091                 return;
7092
7093         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7094
7095         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
7096                       I915_READ(PFIT_CONTROL));
7097         I915_WRITE(PFIT_CONTROL, 0);
7098 }
7099
7100 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7101                               struct intel_crtc *crtc)
7102 {
7103         struct intel_crtc_state *old_crtc_state =
7104                 intel_atomic_get_old_crtc_state(state, crtc);
7105         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7106         enum pipe pipe = crtc->pipe;
7107
7108         /*
7109          * On gen2 planes are double buffered but the pipe isn't, so we must
7110          * wait for planes to fully turn off before disabling the pipe.
7111          */
7112         if (IS_GEN(dev_priv, 2))
7113                 intel_wait_for_vblank(dev_priv, pipe);
7114
7115         intel_encoders_disable(state, crtc);
7116
7117         intel_crtc_vblank_off(crtc);
7118
7119         intel_disable_pipe(old_crtc_state);
7120
7121         i9xx_pfit_disable(old_crtc_state);
7122
7123         intel_encoders_post_disable(state, crtc);
7124
7125         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7126                 if (IS_CHERRYVIEW(dev_priv))
7127                         chv_disable_pll(dev_priv, pipe);
7128                 else if (IS_VALLEYVIEW(dev_priv))
7129                         vlv_disable_pll(dev_priv, pipe);
7130                 else
7131                         i9xx_disable_pll(old_crtc_state);
7132         }
7133
7134         intel_encoders_post_pll_disable(state, crtc);
7135
7136         if (!IS_GEN(dev_priv, 2))
7137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7138
7139         if (!dev_priv->display.initial_watermarks)
7140                 intel_update_watermarks(crtc);
7141
7142         /* clock the pipe down to 640x480@60 to potentially save power */
7143         if (IS_I830(dev_priv))
7144                 i830_enable_pipe(dev_priv, pipe);
7145 }
7146
7147 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7148                                         struct drm_modeset_acquire_ctx *ctx)
7149 {
7150         struct intel_encoder *encoder;
7151         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7152         struct intel_bw_state *bw_state =
7153                 to_intel_bw_state(dev_priv->bw_obj.state);
7154         struct intel_crtc_state *crtc_state =
7155                 to_intel_crtc_state(crtc->base.state);
7156         enum intel_display_power_domain domain;
7157         struct intel_plane *plane;
7158         struct drm_atomic_state *state;
7159         struct intel_crtc_state *temp_crtc_state;
7160         enum pipe pipe = crtc->pipe;
7161         u64 domains;
7162         int ret;
7163
7164         if (!crtc_state->hw.active)
7165                 return;
7166
7167         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7168                 const struct intel_plane_state *plane_state =
7169                         to_intel_plane_state(plane->base.state);
7170
7171                 if (plane_state->uapi.visible)
7172                         intel_plane_disable_noatomic(crtc, plane);
7173         }
7174
7175         state = drm_atomic_state_alloc(&dev_priv->drm);
7176         if (!state) {
7177                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7178                               crtc->base.base.id, crtc->base.name);
7179                 return;
7180         }
7181
7182         state->acquire_ctx = ctx;
7183
7184         /* Everything's already locked, -EDEADLK can't happen. */
7185         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7186         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7187
7188         WARN_ON(IS_ERR(temp_crtc_state) || ret);
7189
7190         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7191
7192         drm_atomic_state_put(state);
7193
7194         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7195                       crtc->base.base.id, crtc->base.name);
7196
7197         crtc->active = false;
7198         crtc->base.enabled = false;
7199
7200         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7201         crtc_state->uapi.active = false;
7202         crtc_state->uapi.connector_mask = 0;
7203         crtc_state->uapi.encoder_mask = 0;
7204         intel_crtc_free_hw_state(crtc_state);
7205         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7206
7207         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7208                 encoder->base.crtc = NULL;
7209
7210         intel_fbc_disable(crtc);
7211         intel_update_watermarks(crtc);
7212         intel_disable_shared_dpll(crtc_state);
7213
7214         domains = crtc->enabled_power_domains;
7215         for_each_power_domain(domain, domains)
7216                 intel_display_power_put_unchecked(dev_priv, domain);
7217         crtc->enabled_power_domains = 0;
7218
7219         dev_priv->active_pipes &= ~BIT(pipe);
7220         dev_priv->min_cdclk[pipe] = 0;
7221         dev_priv->min_voltage_level[pipe] = 0;
7222
7223         bw_state->data_rate[pipe] = 0;
7224         bw_state->num_active_planes[pipe] = 0;
7225 }
7226
7227 /*
7228  * turn all crtc's off, but do not adjust state
7229  * This has to be paired with a call to intel_modeset_setup_hw_state.
7230  */
7231 int intel_display_suspend(struct drm_device *dev)
7232 {
7233         struct drm_i915_private *dev_priv = to_i915(dev);
7234         struct drm_atomic_state *state;
7235         int ret;
7236
7237         state = drm_atomic_helper_suspend(dev);
7238         ret = PTR_ERR_OR_ZERO(state);
7239         if (ret)
7240                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7241         else
7242                 dev_priv->modeset_restore_state = state;
7243         return ret;
7244 }
7245
7246 void intel_encoder_destroy(struct drm_encoder *encoder)
7247 {
7248         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7249
7250         drm_encoder_cleanup(encoder);
7251         kfree(intel_encoder);
7252 }
7253
7254 /* Cross check the actual hw state with our own modeset state tracking (and it's
7255  * internal consistency). */
7256 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7257                                          struct drm_connector_state *conn_state)
7258 {
7259         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7260
7261         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7262                       connector->base.base.id,
7263                       connector->base.name);
7264
7265         if (connector->get_hw_state(connector)) {
7266                 struct intel_encoder *encoder = connector->encoder;
7267
7268                 I915_STATE_WARN(!crtc_state,
7269                          "connector enabled without attached crtc\n");
7270
7271                 if (!crtc_state)
7272                         return;
7273
7274                 I915_STATE_WARN(!crtc_state->hw.active,
7275                                 "connector is active, but attached crtc isn't\n");
7276
7277                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7278                         return;
7279
7280                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7281                         "atomic encoder doesn't match attached encoder\n");
7282
7283                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7284                         "attached encoder crtc differs from connector crtc\n");
7285         } else {
7286                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7287                                 "attached crtc is active, but connector isn't\n");
7288                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7289                         "best encoder set without crtc!\n");
7290         }
7291 }
7292
7293 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7294 {
7295         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7296                 return crtc_state->fdi_lanes;
7297
7298         return 0;
7299 }
7300
7301 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7302                                      struct intel_crtc_state *pipe_config)
7303 {
7304         struct drm_i915_private *dev_priv = to_i915(dev);
7305         struct drm_atomic_state *state = pipe_config->uapi.state;
7306         struct intel_crtc *other_crtc;
7307         struct intel_crtc_state *other_crtc_state;
7308
7309         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7310                       pipe_name(pipe), pipe_config->fdi_lanes);
7311         if (pipe_config->fdi_lanes > 4) {
7312                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7313                               pipe_name(pipe), pipe_config->fdi_lanes);
7314                 return -EINVAL;
7315         }
7316
7317         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7318                 if (pipe_config->fdi_lanes > 2) {
7319                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7320                                       pipe_config->fdi_lanes);
7321                         return -EINVAL;
7322                 } else {
7323                         return 0;
7324                 }
7325         }
7326
7327         if (INTEL_NUM_PIPES(dev_priv) == 2)
7328                 return 0;
7329
7330         /* Ivybridge 3 pipe is really complicated */
7331         switch (pipe) {
7332         case PIPE_A:
7333                 return 0;
7334         case PIPE_B:
7335                 if (pipe_config->fdi_lanes <= 2)
7336                         return 0;
7337
7338                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7339                 other_crtc_state =
7340                         intel_atomic_get_crtc_state(state, other_crtc);
7341                 if (IS_ERR(other_crtc_state))
7342                         return PTR_ERR(other_crtc_state);
7343
7344                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7345                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7346                                       pipe_name(pipe), pipe_config->fdi_lanes);
7347                         return -EINVAL;
7348                 }
7349                 return 0;
7350         case PIPE_C:
7351                 if (pipe_config->fdi_lanes > 2) {
7352                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7353                                       pipe_name(pipe), pipe_config->fdi_lanes);
7354                         return -EINVAL;
7355                 }
7356
7357                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7358                 other_crtc_state =
7359                         intel_atomic_get_crtc_state(state, other_crtc);
7360                 if (IS_ERR(other_crtc_state))
7361                         return PTR_ERR(other_crtc_state);
7362
7363                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7364                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7365                         return -EINVAL;
7366                 }
7367                 return 0;
7368         default:
7369                 BUG();
7370         }
7371 }
7372
7373 #define RETRY 1
7374 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7375                                        struct intel_crtc_state *pipe_config)
7376 {
7377         struct drm_device *dev = intel_crtc->base.dev;
7378         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7379         int lane, link_bw, fdi_dotclock, ret;
7380         bool needs_recompute = false;
7381
7382 retry:
7383         /* FDI is a binary signal running at ~2.7GHz, encoding
7384          * each output octet as 10 bits. The actual frequency
7385          * is stored as a divider into a 100MHz clock, and the
7386          * mode pixel clock is stored in units of 1KHz.
7387          * Hence the bw of each lane in terms of the mode signal
7388          * is:
7389          */
7390         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7391
7392         fdi_dotclock = adjusted_mode->crtc_clock;
7393
7394         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7395                                            pipe_config->pipe_bpp);
7396
7397         pipe_config->fdi_lanes = lane;
7398
7399         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7400                                link_bw, &pipe_config->fdi_m_n, false, false);
7401
7402         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7403         if (ret == -EDEADLK)
7404                 return ret;
7405
7406         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7407                 pipe_config->pipe_bpp -= 2*3;
7408                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7409                               pipe_config->pipe_bpp);
7410                 needs_recompute = true;
7411                 pipe_config->bw_constrained = true;
7412
7413                 goto retry;
7414         }
7415
7416         if (needs_recompute)
7417                 return RETRY;
7418
7419         return ret;
7420 }
7421
7422 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7423 {
7424         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7425         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7426
7427         /* IPS only exists on ULT machines and is tied to pipe A. */
7428         if (!hsw_crtc_supports_ips(crtc))
7429                 return false;
7430
7431         if (!i915_modparams.enable_ips)
7432                 return false;
7433
7434         if (crtc_state->pipe_bpp > 24)
7435                 return false;
7436
7437         /*
7438          * We compare against max which means we must take
7439          * the increased cdclk requirement into account when
7440          * calculating the new cdclk.
7441          *
7442          * Should measure whether using a lower cdclk w/o IPS
7443          */
7444         if (IS_BROADWELL(dev_priv) &&
7445             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7446                 return false;
7447
7448         return true;
7449 }
7450
7451 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7452 {
7453         struct drm_i915_private *dev_priv =
7454                 to_i915(crtc_state->uapi.crtc->dev);
7455         struct intel_atomic_state *intel_state =
7456                 to_intel_atomic_state(crtc_state->uapi.state);
7457
7458         if (!hsw_crtc_state_ips_capable(crtc_state))
7459                 return false;
7460
7461         /*
7462          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7463          * enabled and disabled dynamically based on package C states,
7464          * user space can't make reliable use of the CRCs, so let's just
7465          * completely disable it.
7466          */
7467         if (crtc_state->crc_enabled)
7468                 return false;
7469
7470         /* IPS should be fine as long as at least one plane is enabled. */
7471         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7472                 return false;
7473
7474         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7475         if (IS_BROADWELL(dev_priv) &&
7476             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7477                 return false;
7478
7479         return true;
7480 }
7481
7482 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7483 {
7484         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7485
7486         /* GDG double wide on either pipe, otherwise pipe A only */
7487         return INTEL_GEN(dev_priv) < 4 &&
7488                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7489 }
7490
7491 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7492 {
7493         u32 pixel_rate;
7494
7495         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7496
7497         /*
7498          * We only use IF-ID interlacing. If we ever use
7499          * PF-ID we'll need to adjust the pixel_rate here.
7500          */
7501
7502         if (pipe_config->pch_pfit.enabled) {
7503                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7504                 u32 pfit_size = pipe_config->pch_pfit.size;
7505
7506                 pipe_w = pipe_config->pipe_src_w;
7507                 pipe_h = pipe_config->pipe_src_h;
7508
7509                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7510                 pfit_h = pfit_size & 0xFFFF;
7511                 if (pipe_w < pfit_w)
7512                         pipe_w = pfit_w;
7513                 if (pipe_h < pfit_h)
7514                         pipe_h = pfit_h;
7515
7516                 if (WARN_ON(!pfit_w || !pfit_h))
7517                         return pixel_rate;
7518
7519                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7520                                      pfit_w * pfit_h);
7521         }
7522
7523         return pixel_rate;
7524 }
7525
7526 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7527 {
7528         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7529
7530         if (HAS_GMCH(dev_priv))
7531                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7532                 crtc_state->pixel_rate =
7533                         crtc_state->hw.adjusted_mode.crtc_clock;
7534         else
7535                 crtc_state->pixel_rate =
7536                         ilk_pipe_pixel_rate(crtc_state);
7537 }
7538
7539 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7540                                      struct intel_crtc_state *pipe_config)
7541 {
7542         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7543         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7544         int clock_limit = dev_priv->max_dotclk_freq;
7545
7546         if (INTEL_GEN(dev_priv) < 4) {
7547                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7548
7549                 /*
7550                  * Enable double wide mode when the dot clock
7551                  * is > 90% of the (display) core speed.
7552                  */
7553                 if (intel_crtc_supports_double_wide(crtc) &&
7554                     adjusted_mode->crtc_clock > clock_limit) {
7555                         clock_limit = dev_priv->max_dotclk_freq;
7556                         pipe_config->double_wide = true;
7557                 }
7558         }
7559
7560         if (adjusted_mode->crtc_clock > clock_limit) {
7561                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7562                               adjusted_mode->crtc_clock, clock_limit,
7563                               yesno(pipe_config->double_wide));
7564                 return -EINVAL;
7565         }
7566
7567         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7568              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7569              pipe_config->hw.ctm) {
7570                 /*
7571                  * There is only one pipe CSC unit per pipe, and we need that
7572                  * for output conversion from RGB->YCBCR. So if CTM is already
7573                  * applied we can't support YCBCR420 output.
7574                  */
7575                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7576                 return -EINVAL;
7577         }
7578
7579         /*
7580          * Pipe horizontal size must be even in:
7581          * - DVO ganged mode
7582          * - LVDS dual channel mode
7583          * - Double wide pipe
7584          */
7585         if (pipe_config->pipe_src_w & 1) {
7586                 if (pipe_config->double_wide) {
7587                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7588                         return -EINVAL;
7589                 }
7590
7591                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7592                     intel_is_dual_link_lvds(dev_priv)) {
7593                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7594                         return -EINVAL;
7595                 }
7596         }
7597
7598         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7599          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7600          */
7601         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7602                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7603                 return -EINVAL;
7604
7605         intel_crtc_compute_pixel_rate(pipe_config);
7606
7607         if (pipe_config->has_pch_encoder)
7608                 return ironlake_fdi_compute_config(crtc, pipe_config);
7609
7610         return 0;
7611 }
7612
7613 static void
7614 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7615 {
7616         while (*num > DATA_LINK_M_N_MASK ||
7617                *den > DATA_LINK_M_N_MASK) {
7618                 *num >>= 1;
7619                 *den >>= 1;
7620         }
7621 }
7622
7623 static void compute_m_n(unsigned int m, unsigned int n,
7624                         u32 *ret_m, u32 *ret_n,
7625                         bool constant_n)
7626 {
7627         /*
7628          * Several DP dongles in particular seem to be fussy about
7629          * too large link M/N values. Give N value as 0x8000 that
7630          * should be acceptable by specific devices. 0x8000 is the
7631          * specified fixed N value for asynchronous clock mode,
7632          * which the devices expect also in synchronous clock mode.
7633          */
7634         if (constant_n)
7635                 *ret_n = 0x8000;
7636         else
7637                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7638
7639         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7640         intel_reduce_m_n_ratio(ret_m, ret_n);
7641 }
7642
7643 void
7644 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7645                        int pixel_clock, int link_clock,
7646                        struct intel_link_m_n *m_n,
7647                        bool constant_n, bool fec_enable)
7648 {
7649         u32 data_clock = bits_per_pixel * pixel_clock;
7650
7651         if (fec_enable)
7652                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
7653
7654         m_n->tu = 64;
7655         compute_m_n(data_clock,
7656                     link_clock * nlanes * 8,
7657                     &m_n->gmch_m, &m_n->gmch_n,
7658                     constant_n);
7659
7660         compute_m_n(pixel_clock, link_clock,
7661                     &m_n->link_m, &m_n->link_n,
7662                     constant_n);
7663 }
7664
7665 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
7666 {
7667         /*
7668          * There may be no VBT; and if the BIOS enabled SSC we can
7669          * just keep using it to avoid unnecessary flicker.  Whereas if the
7670          * BIOS isn't using it, don't assume it will work even if the VBT
7671          * indicates as much.
7672          */
7673         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7674                 bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) &
7675                         DREF_SSC1_ENABLE;
7676
7677                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
7678                         DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n",
7679                                       enableddisabled(bios_lvds_use_ssc),
7680                                       enableddisabled(dev_priv->vbt.lvds_use_ssc));
7681                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
7682                 }
7683         }
7684 }
7685
7686 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7687 {
7688         if (i915_modparams.panel_use_ssc >= 0)
7689                 return i915_modparams.panel_use_ssc != 0;
7690         return dev_priv->vbt.lvds_use_ssc
7691                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7692 }
7693
7694 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7695 {
7696         return (1 << dpll->n) << 16 | dpll->m2;
7697 }
7698
7699 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7700 {
7701         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7702 }
7703
7704 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7705                                      struct intel_crtc_state *crtc_state,
7706                                      struct dpll *reduced_clock)
7707 {
7708         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7709         u32 fp, fp2 = 0;
7710
7711         if (IS_PINEVIEW(dev_priv)) {
7712                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7713                 if (reduced_clock)
7714                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7715         } else {
7716                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7717                 if (reduced_clock)
7718                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7719         }
7720
7721         crtc_state->dpll_hw_state.fp0 = fp;
7722
7723         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7724             reduced_clock) {
7725                 crtc_state->dpll_hw_state.fp1 = fp2;
7726         } else {
7727                 crtc_state->dpll_hw_state.fp1 = fp;
7728         }
7729 }
7730
7731 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7732                 pipe)
7733 {
7734         u32 reg_val;
7735
7736         /*
7737          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7738          * and set it to a reasonable value instead.
7739          */
7740         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7741         reg_val &= 0xffffff00;
7742         reg_val |= 0x00000030;
7743         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7744
7745         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7746         reg_val &= 0x00ffffff;
7747         reg_val |= 0x8c000000;
7748         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7749
7750         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7751         reg_val &= 0xffffff00;
7752         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7753
7754         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7755         reg_val &= 0x00ffffff;
7756         reg_val |= 0xb0000000;
7757         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7758 }
7759
7760 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7761                                          const struct intel_link_m_n *m_n)
7762 {
7763         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7764         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7765         enum pipe pipe = crtc->pipe;
7766
7767         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7768         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7769         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7770         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7771 }
7772
7773 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7774                                  enum transcoder transcoder)
7775 {
7776         if (IS_HASWELL(dev_priv))
7777                 return transcoder == TRANSCODER_EDP;
7778
7779         /*
7780          * Strictly speaking some registers are available before
7781          * gen7, but we only support DRRS on gen7+
7782          */
7783         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7784 }
7785
7786 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7787                                          const struct intel_link_m_n *m_n,
7788                                          const struct intel_link_m_n *m2_n2)
7789 {
7790         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7791         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7792         enum pipe pipe = crtc->pipe;
7793         enum transcoder transcoder = crtc_state->cpu_transcoder;
7794
7795         if (INTEL_GEN(dev_priv) >= 5) {
7796                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7797                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7798                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7799                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7800                 /*
7801                  *  M2_N2 registers are set only if DRRS is supported
7802                  * (to make sure the registers are not unnecessarily accessed).
7803                  */
7804                 if (m2_n2 && crtc_state->has_drrs &&
7805                     transcoder_has_m2_n2(dev_priv, transcoder)) {
7806                         I915_WRITE(PIPE_DATA_M2(transcoder),
7807                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7808                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7809                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7810                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7811                 }
7812         } else {
7813                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7814                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7815                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7816                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7817         }
7818 }
7819
7820 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7821 {
7822         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7823
7824         if (m_n == M1_N1) {
7825                 dp_m_n = &crtc_state->dp_m_n;
7826                 dp_m2_n2 = &crtc_state->dp_m2_n2;
7827         } else if (m_n == M2_N2) {
7828
7829                 /*
7830                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7831                  * needs to be programmed into M1_N1.
7832                  */
7833                 dp_m_n = &crtc_state->dp_m2_n2;
7834         } else {
7835                 DRM_ERROR("Unsupported divider value\n");
7836                 return;
7837         }
7838
7839         if (crtc_state->has_pch_encoder)
7840                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7841         else
7842                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7843 }
7844
7845 static void vlv_compute_dpll(struct intel_crtc *crtc,
7846                              struct intel_crtc_state *pipe_config)
7847 {
7848         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7849                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7850         if (crtc->pipe != PIPE_A)
7851                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7852
7853         /* DPLL not used with DSI, but still need the rest set up */
7854         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7855                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7856                         DPLL_EXT_BUFFER_ENABLE_VLV;
7857
7858         pipe_config->dpll_hw_state.dpll_md =
7859                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7860 }
7861
7862 static void chv_compute_dpll(struct intel_crtc *crtc,
7863                              struct intel_crtc_state *pipe_config)
7864 {
7865         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7866                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7867         if (crtc->pipe != PIPE_A)
7868                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7869
7870         /* DPLL not used with DSI, but still need the rest set up */
7871         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7872                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7873
7874         pipe_config->dpll_hw_state.dpll_md =
7875                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7876 }
7877
7878 static void vlv_prepare_pll(struct intel_crtc *crtc,
7879                             const struct intel_crtc_state *pipe_config)
7880 {
7881         struct drm_device *dev = crtc->base.dev;
7882         struct drm_i915_private *dev_priv = to_i915(dev);
7883         enum pipe pipe = crtc->pipe;
7884         u32 mdiv;
7885         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7886         u32 coreclk, reg_val;
7887
7888         /* Enable Refclk */
7889         I915_WRITE(DPLL(pipe),
7890                    pipe_config->dpll_hw_state.dpll &
7891                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7892
7893         /* No need to actually set up the DPLL with DSI */
7894         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7895                 return;
7896
7897         vlv_dpio_get(dev_priv);
7898
7899         bestn = pipe_config->dpll.n;
7900         bestm1 = pipe_config->dpll.m1;
7901         bestm2 = pipe_config->dpll.m2;
7902         bestp1 = pipe_config->dpll.p1;
7903         bestp2 = pipe_config->dpll.p2;
7904
7905         /* See eDP HDMI DPIO driver vbios notes doc */
7906
7907         /* PLL B needs special handling */
7908         if (pipe == PIPE_B)
7909                 vlv_pllb_recal_opamp(dev_priv, pipe);
7910
7911         /* Set up Tx target for periodic Rcomp update */
7912         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7913
7914         /* Disable target IRef on PLL */
7915         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7916         reg_val &= 0x00ffffff;
7917         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7918
7919         /* Disable fast lock */
7920         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7921
7922         /* Set idtafcrecal before PLL is enabled */
7923         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7924         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7925         mdiv |= ((bestn << DPIO_N_SHIFT));
7926         mdiv |= (1 << DPIO_K_SHIFT);
7927
7928         /*
7929          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7930          * but we don't support that).
7931          * Note: don't use the DAC post divider as it seems unstable.
7932          */
7933         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7934         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7935
7936         mdiv |= DPIO_ENABLE_CALIBRATION;
7937         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7938
7939         /* Set HBR and RBR LPF coefficients */
7940         if (pipe_config->port_clock == 162000 ||
7941             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7942             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7943                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7944                                  0x009f0003);
7945         else
7946                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7947                                  0x00d0000f);
7948
7949         if (intel_crtc_has_dp_encoder(pipe_config)) {
7950                 /* Use SSC source */
7951                 if (pipe == PIPE_A)
7952                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7953                                          0x0df40000);
7954                 else
7955                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7956                                          0x0df70000);
7957         } else { /* HDMI or VGA */
7958                 /* Use bend source */
7959                 if (pipe == PIPE_A)
7960                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7961                                          0x0df70000);
7962                 else
7963                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7964                                          0x0df40000);
7965         }
7966
7967         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7968         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7969         if (intel_crtc_has_dp_encoder(pipe_config))
7970                 coreclk |= 0x01000000;
7971         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7972
7973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7974
7975         vlv_dpio_put(dev_priv);
7976 }
7977
7978 static void chv_prepare_pll(struct intel_crtc *crtc,
7979                             const struct intel_crtc_state *pipe_config)
7980 {
7981         struct drm_device *dev = crtc->base.dev;
7982         struct drm_i915_private *dev_priv = to_i915(dev);
7983         enum pipe pipe = crtc->pipe;
7984         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7985         u32 loopfilter, tribuf_calcntr;
7986         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7987         u32 dpio_val;
7988         int vco;
7989
7990         /* Enable Refclk and SSC */
7991         I915_WRITE(DPLL(pipe),
7992                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7993
7994         /* No need to actually set up the DPLL with DSI */
7995         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7996                 return;
7997
7998         bestn = pipe_config->dpll.n;
7999         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8000         bestm1 = pipe_config->dpll.m1;
8001         bestm2 = pipe_config->dpll.m2 >> 22;
8002         bestp1 = pipe_config->dpll.p1;
8003         bestp2 = pipe_config->dpll.p2;
8004         vco = pipe_config->dpll.vco;
8005         dpio_val = 0;
8006         loopfilter = 0;
8007
8008         vlv_dpio_get(dev_priv);
8009
8010         /* p1 and p2 divider */
8011         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8012                         5 << DPIO_CHV_S1_DIV_SHIFT |
8013                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8014                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8015                         1 << DPIO_CHV_K_DIV_SHIFT);
8016
8017         /* Feedback post-divider - m2 */
8018         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8019
8020         /* Feedback refclk divider - n and m1 */
8021         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8022                         DPIO_CHV_M1_DIV_BY_2 |
8023                         1 << DPIO_CHV_N_DIV_SHIFT);
8024
8025         /* M2 fraction division */
8026         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8027
8028         /* M2 fraction division enable */
8029         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8030         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8031         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8032         if (bestm2_frac)
8033                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8034         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8035
8036         /* Program digital lock detect threshold */
8037         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8038         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8039                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8040         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8041         if (!bestm2_frac)
8042                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8043         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8044
8045         /* Loop filter */
8046         if (vco == 5400000) {
8047                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8048                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8049                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8050                 tribuf_calcntr = 0x9;
8051         } else if (vco <= 6200000) {
8052                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8053                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8054                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8055                 tribuf_calcntr = 0x9;
8056         } else if (vco <= 6480000) {
8057                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8058                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8059                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8060                 tribuf_calcntr = 0x8;
8061         } else {
8062                 /* Not supported. Apply the same limits as in the max case */
8063                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8064                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8065                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8066                 tribuf_calcntr = 0;
8067         }
8068         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8069
8070         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8071         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8072         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8073         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8074
8075         /* AFC Recal */
8076         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8077                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8078                         DPIO_AFC_RECAL);
8079
8080         vlv_dpio_put(dev_priv);
8081 }
8082
8083 /**
8084  * vlv_force_pll_on - forcibly enable just the PLL
8085  * @dev_priv: i915 private structure
8086  * @pipe: pipe PLL to enable
8087  * @dpll: PLL configuration
8088  *
8089  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8090  * in cases where we need the PLL enabled even when @pipe is not going to
8091  * be enabled.
8092  */
8093 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8094                      const struct dpll *dpll)
8095 {
8096         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8097         struct intel_crtc_state *pipe_config;
8098
8099         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8100         if (!pipe_config)
8101                 return -ENOMEM;
8102
8103         pipe_config->uapi.crtc = &crtc->base;
8104         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8105         pipe_config->pixel_multiplier = 1;
8106         pipe_config->dpll = *dpll;
8107
8108         if (IS_CHERRYVIEW(dev_priv)) {
8109                 chv_compute_dpll(crtc, pipe_config);
8110                 chv_prepare_pll(crtc, pipe_config);
8111                 chv_enable_pll(crtc, pipe_config);
8112         } else {
8113                 vlv_compute_dpll(crtc, pipe_config);
8114                 vlv_prepare_pll(crtc, pipe_config);
8115                 vlv_enable_pll(crtc, pipe_config);
8116         }
8117
8118         kfree(pipe_config);
8119
8120         return 0;
8121 }
8122
8123 /**
8124  * vlv_force_pll_off - forcibly disable just the PLL
8125  * @dev_priv: i915 private structure
8126  * @pipe: pipe PLL to disable
8127  *
8128  * Disable the PLL for @pipe. To be used in cases where we need
8129  * the PLL enabled even when @pipe is not going to be enabled.
8130  */
8131 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8132 {
8133         if (IS_CHERRYVIEW(dev_priv))
8134                 chv_disable_pll(dev_priv, pipe);
8135         else
8136                 vlv_disable_pll(dev_priv, pipe);
8137 }
8138
8139 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8140                               struct intel_crtc_state *crtc_state,
8141                               struct dpll *reduced_clock)
8142 {
8143         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8144         u32 dpll;
8145         struct dpll *clock = &crtc_state->dpll;
8146
8147         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8148
8149         dpll = DPLL_VGA_MODE_DIS;
8150
8151         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8152                 dpll |= DPLLB_MODE_LVDS;
8153         else
8154                 dpll |= DPLLB_MODE_DAC_SERIAL;
8155
8156         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8157             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8158                 dpll |= (crtc_state->pixel_multiplier - 1)
8159                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8160         }
8161
8162         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8163             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8164                 dpll |= DPLL_SDVO_HIGH_SPEED;
8165
8166         if (intel_crtc_has_dp_encoder(crtc_state))
8167                 dpll |= DPLL_SDVO_HIGH_SPEED;
8168
8169         /* compute bitmask from p1 value */
8170         if (IS_PINEVIEW(dev_priv))
8171                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8172         else {
8173                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8174                 if (IS_G4X(dev_priv) && reduced_clock)
8175                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8176         }
8177         switch (clock->p2) {
8178         case 5:
8179                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8180                 break;
8181         case 7:
8182                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8183                 break;
8184         case 10:
8185                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8186                 break;
8187         case 14:
8188                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8189                 break;
8190         }
8191         if (INTEL_GEN(dev_priv) >= 4)
8192                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8193
8194         if (crtc_state->sdvo_tv_clock)
8195                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8196         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8197                  intel_panel_use_ssc(dev_priv))
8198                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8199         else
8200                 dpll |= PLL_REF_INPUT_DREFCLK;
8201
8202         dpll |= DPLL_VCO_ENABLE;
8203         crtc_state->dpll_hw_state.dpll = dpll;
8204
8205         if (INTEL_GEN(dev_priv) >= 4) {
8206                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8207                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8208                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8209         }
8210 }
8211
8212 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8213                               struct intel_crtc_state *crtc_state,
8214                               struct dpll *reduced_clock)
8215 {
8216         struct drm_device *dev = crtc->base.dev;
8217         struct drm_i915_private *dev_priv = to_i915(dev);
8218         u32 dpll;
8219         struct dpll *clock = &crtc_state->dpll;
8220
8221         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8222
8223         dpll = DPLL_VGA_MODE_DIS;
8224
8225         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8226                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8227         } else {
8228                 if (clock->p1 == 2)
8229                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8230                 else
8231                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232                 if (clock->p2 == 4)
8233                         dpll |= PLL_P2_DIVIDE_BY_4;
8234         }
8235
8236         /*
8237          * Bspec:
8238          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8239          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8240          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8241          *  Enable) must be set to “1” in both the DPLL A Control Register
8242          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8243          *
8244          * For simplicity We simply keep both bits always enabled in
8245          * both DPLLS. The spec says we should disable the DVO 2X clock
8246          * when not needed, but this seems to work fine in practice.
8247          */
8248         if (IS_I830(dev_priv) ||
8249             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8250                 dpll |= DPLL_DVO_2X_MODE;
8251
8252         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8253             intel_panel_use_ssc(dev_priv))
8254                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8255         else
8256                 dpll |= PLL_REF_INPUT_DREFCLK;
8257
8258         dpll |= DPLL_VCO_ENABLE;
8259         crtc_state->dpll_hw_state.dpll = dpll;
8260 }
8261
8262 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8263 {
8264         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8265         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8266         enum pipe pipe = crtc->pipe;
8267         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8268         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8269         u32 crtc_vtotal, crtc_vblank_end;
8270         int vsyncshift = 0;
8271
8272         /* We need to be careful not to changed the adjusted mode, for otherwise
8273          * the hw state checker will get angry at the mismatch. */
8274         crtc_vtotal = adjusted_mode->crtc_vtotal;
8275         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8276
8277         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8278                 /* the chip adds 2 halflines automatically */
8279                 crtc_vtotal -= 1;
8280                 crtc_vblank_end -= 1;
8281
8282                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8283                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8284                 else
8285                         vsyncshift = adjusted_mode->crtc_hsync_start -
8286                                 adjusted_mode->crtc_htotal / 2;
8287                 if (vsyncshift < 0)
8288                         vsyncshift += adjusted_mode->crtc_htotal;
8289         }
8290
8291         if (INTEL_GEN(dev_priv) > 3)
8292                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8293
8294         I915_WRITE(HTOTAL(cpu_transcoder),
8295                    (adjusted_mode->crtc_hdisplay - 1) |
8296                    ((adjusted_mode->crtc_htotal - 1) << 16));
8297         I915_WRITE(HBLANK(cpu_transcoder),
8298                    (adjusted_mode->crtc_hblank_start - 1) |
8299                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8300         I915_WRITE(HSYNC(cpu_transcoder),
8301                    (adjusted_mode->crtc_hsync_start - 1) |
8302                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8303
8304         I915_WRITE(VTOTAL(cpu_transcoder),
8305                    (adjusted_mode->crtc_vdisplay - 1) |
8306                    ((crtc_vtotal - 1) << 16));
8307         I915_WRITE(VBLANK(cpu_transcoder),
8308                    (adjusted_mode->crtc_vblank_start - 1) |
8309                    ((crtc_vblank_end - 1) << 16));
8310         I915_WRITE(VSYNC(cpu_transcoder),
8311                    (adjusted_mode->crtc_vsync_start - 1) |
8312                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8313
8314         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8315          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8316          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8317          * bits. */
8318         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8319             (pipe == PIPE_B || pipe == PIPE_C))
8320                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8321
8322 }
8323
8324 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8325 {
8326         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8327         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8328         enum pipe pipe = crtc->pipe;
8329
8330         /* pipesrc controls the size that is scaled from, which should
8331          * always be the user's requested size.
8332          */
8333         I915_WRITE(PIPESRC(pipe),
8334                    ((crtc_state->pipe_src_w - 1) << 16) |
8335                    (crtc_state->pipe_src_h - 1));
8336 }
8337
8338 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8339 {
8340         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8341         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8342
8343         if (IS_GEN(dev_priv, 2))
8344                 return false;
8345
8346         if (INTEL_GEN(dev_priv) >= 9 ||
8347             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8348                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8349         else
8350                 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8351 }
8352
8353 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8354                                    struct intel_crtc_state *pipe_config)
8355 {
8356         struct drm_device *dev = crtc->base.dev;
8357         struct drm_i915_private *dev_priv = to_i915(dev);
8358         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8359         u32 tmp;
8360
8361         tmp = I915_READ(HTOTAL(cpu_transcoder));
8362         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8363         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8364
8365         if (!transcoder_is_dsi(cpu_transcoder)) {
8366                 tmp = I915_READ(HBLANK(cpu_transcoder));
8367                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8368                                                         (tmp & 0xffff) + 1;
8369                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8370                                                 ((tmp >> 16) & 0xffff) + 1;
8371         }
8372         tmp = I915_READ(HSYNC(cpu_transcoder));
8373         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8374         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8375
8376         tmp = I915_READ(VTOTAL(cpu_transcoder));
8377         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8378         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8379
8380         if (!transcoder_is_dsi(cpu_transcoder)) {
8381                 tmp = I915_READ(VBLANK(cpu_transcoder));
8382                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8383                                                         (tmp & 0xffff) + 1;
8384                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8385                                                 ((tmp >> 16) & 0xffff) + 1;
8386         }
8387         tmp = I915_READ(VSYNC(cpu_transcoder));
8388         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8389         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8390
8391         if (intel_pipe_is_interlaced(pipe_config)) {
8392                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8393                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8394                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8395         }
8396 }
8397
8398 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8399                                     struct intel_crtc_state *pipe_config)
8400 {
8401         struct drm_device *dev = crtc->base.dev;
8402         struct drm_i915_private *dev_priv = to_i915(dev);
8403         u32 tmp;
8404
8405         tmp = I915_READ(PIPESRC(crtc->pipe));
8406         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8407         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8408
8409         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8410         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8411 }
8412
8413 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8414                                  struct intel_crtc_state *pipe_config)
8415 {
8416         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8417         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8418         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8419         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8420
8421         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8422         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8423         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8424         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8425
8426         mode->flags = pipe_config->hw.adjusted_mode.flags;
8427         mode->type = DRM_MODE_TYPE_DRIVER;
8428
8429         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8430
8431         mode->hsync = drm_mode_hsync(mode);
8432         mode->vrefresh = drm_mode_vrefresh(mode);
8433         drm_mode_set_name(mode);
8434 }
8435
8436 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8437 {
8438         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8439         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8440         u32 pipeconf;
8441
8442         pipeconf = 0;
8443
8444         /* we keep both pipes enabled on 830 */
8445         if (IS_I830(dev_priv))
8446                 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8447
8448         if (crtc_state->double_wide)
8449                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8450
8451         /* only g4x and later have fancy bpc/dither controls */
8452         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8453             IS_CHERRYVIEW(dev_priv)) {
8454                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8455                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8456                         pipeconf |= PIPECONF_DITHER_EN |
8457                                     PIPECONF_DITHER_TYPE_SP;
8458
8459                 switch (crtc_state->pipe_bpp) {
8460                 case 18:
8461                         pipeconf |= PIPECONF_6BPC;
8462                         break;
8463                 case 24:
8464                         pipeconf |= PIPECONF_8BPC;
8465                         break;
8466                 case 30:
8467                         pipeconf |= PIPECONF_10BPC;
8468                         break;
8469                 default:
8470                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8471                         BUG();
8472                 }
8473         }
8474
8475         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8476                 if (INTEL_GEN(dev_priv) < 4 ||
8477                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8478                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8479                 else
8480                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8481         } else {
8482                 pipeconf |= PIPECONF_PROGRESSIVE;
8483         }
8484
8485         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8486              crtc_state->limited_color_range)
8487                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8488
8489         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8490
8491         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8492
8493         I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8494         POSTING_READ(PIPECONF(crtc->pipe));
8495 }
8496
8497 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8498                                    struct intel_crtc_state *crtc_state)
8499 {
8500         struct drm_device *dev = crtc->base.dev;
8501         struct drm_i915_private *dev_priv = to_i915(dev);
8502         const struct intel_limit *limit;
8503         int refclk = 48000;
8504
8505         memset(&crtc_state->dpll_hw_state, 0,
8506                sizeof(crtc_state->dpll_hw_state));
8507
8508         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8509                 if (intel_panel_use_ssc(dev_priv)) {
8510                         refclk = dev_priv->vbt.lvds_ssc_freq;
8511                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8512                 }
8513
8514                 limit = &intel_limits_i8xx_lvds;
8515         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8516                 limit = &intel_limits_i8xx_dvo;
8517         } else {
8518                 limit = &intel_limits_i8xx_dac;
8519         }
8520
8521         if (!crtc_state->clock_set &&
8522             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8523                                  refclk, NULL, &crtc_state->dpll)) {
8524                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8525                 return -EINVAL;
8526         }
8527
8528         i8xx_compute_dpll(crtc, crtc_state, NULL);
8529
8530         return 0;
8531 }
8532
8533 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8534                                   struct intel_crtc_state *crtc_state)
8535 {
8536         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8537         const struct intel_limit *limit;
8538         int refclk = 96000;
8539
8540         memset(&crtc_state->dpll_hw_state, 0,
8541                sizeof(crtc_state->dpll_hw_state));
8542
8543         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8544                 if (intel_panel_use_ssc(dev_priv)) {
8545                         refclk = dev_priv->vbt.lvds_ssc_freq;
8546                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8547                 }
8548
8549                 if (intel_is_dual_link_lvds(dev_priv))
8550                         limit = &intel_limits_g4x_dual_channel_lvds;
8551                 else
8552                         limit = &intel_limits_g4x_single_channel_lvds;
8553         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8554                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8555                 limit = &intel_limits_g4x_hdmi;
8556         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8557                 limit = &intel_limits_g4x_sdvo;
8558         } else {
8559                 /* The option is for other outputs */
8560                 limit = &intel_limits_i9xx_sdvo;
8561         }
8562
8563         if (!crtc_state->clock_set &&
8564             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8565                                 refclk, NULL, &crtc_state->dpll)) {
8566                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8567                 return -EINVAL;
8568         }
8569
8570         i9xx_compute_dpll(crtc, crtc_state, NULL);
8571
8572         return 0;
8573 }
8574
8575 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8576                                   struct intel_crtc_state *crtc_state)
8577 {
8578         struct drm_device *dev = crtc->base.dev;
8579         struct drm_i915_private *dev_priv = to_i915(dev);
8580         const struct intel_limit *limit;
8581         int refclk = 96000;
8582
8583         memset(&crtc_state->dpll_hw_state, 0,
8584                sizeof(crtc_state->dpll_hw_state));
8585
8586         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8587                 if (intel_panel_use_ssc(dev_priv)) {
8588                         refclk = dev_priv->vbt.lvds_ssc_freq;
8589                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8590                 }
8591
8592                 limit = &intel_limits_pineview_lvds;
8593         } else {
8594                 limit = &intel_limits_pineview_sdvo;
8595         }
8596
8597         if (!crtc_state->clock_set &&
8598             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8599                                 refclk, NULL, &crtc_state->dpll)) {
8600                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8601                 return -EINVAL;
8602         }
8603
8604         i9xx_compute_dpll(crtc, crtc_state, NULL);
8605
8606         return 0;
8607 }
8608
8609 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8610                                    struct intel_crtc_state *crtc_state)
8611 {
8612         struct drm_device *dev = crtc->base.dev;
8613         struct drm_i915_private *dev_priv = to_i915(dev);
8614         const struct intel_limit *limit;
8615         int refclk = 96000;
8616
8617         memset(&crtc_state->dpll_hw_state, 0,
8618                sizeof(crtc_state->dpll_hw_state));
8619
8620         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8621                 if (intel_panel_use_ssc(dev_priv)) {
8622                         refclk = dev_priv->vbt.lvds_ssc_freq;
8623                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8624                 }
8625
8626                 limit = &intel_limits_i9xx_lvds;
8627         } else {
8628                 limit = &intel_limits_i9xx_sdvo;
8629         }
8630
8631         if (!crtc_state->clock_set &&
8632             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8633                                  refclk, NULL, &crtc_state->dpll)) {
8634                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8635                 return -EINVAL;
8636         }
8637
8638         i9xx_compute_dpll(crtc, crtc_state, NULL);
8639
8640         return 0;
8641 }
8642
8643 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8644                                   struct intel_crtc_state *crtc_state)
8645 {
8646         int refclk = 100000;
8647         const struct intel_limit *limit = &intel_limits_chv;
8648
8649         memset(&crtc_state->dpll_hw_state, 0,
8650                sizeof(crtc_state->dpll_hw_state));
8651
8652         if (!crtc_state->clock_set &&
8653             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8654                                 refclk, NULL, &crtc_state->dpll)) {
8655                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8656                 return -EINVAL;
8657         }
8658
8659         chv_compute_dpll(crtc, crtc_state);
8660
8661         return 0;
8662 }
8663
8664 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8665                                   struct intel_crtc_state *crtc_state)
8666 {
8667         int refclk = 100000;
8668         const struct intel_limit *limit = &intel_limits_vlv;
8669
8670         memset(&crtc_state->dpll_hw_state, 0,
8671                sizeof(crtc_state->dpll_hw_state));
8672
8673         if (!crtc_state->clock_set &&
8674             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8675                                 refclk, NULL, &crtc_state->dpll)) {
8676                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8677                 return -EINVAL;
8678         }
8679
8680         vlv_compute_dpll(crtc, crtc_state);
8681
8682         return 0;
8683 }
8684
8685 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8686 {
8687         if (IS_I830(dev_priv))
8688                 return false;
8689
8690         return INTEL_GEN(dev_priv) >= 4 ||
8691                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8692 }
8693
8694 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8695                                  struct intel_crtc_state *pipe_config)
8696 {
8697         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8698         u32 tmp;
8699
8700         if (!i9xx_has_pfit(dev_priv))
8701                 return;
8702
8703         tmp = I915_READ(PFIT_CONTROL);
8704         if (!(tmp & PFIT_ENABLE))
8705                 return;
8706
8707         /* Check whether the pfit is attached to our pipe. */
8708         if (INTEL_GEN(dev_priv) < 4) {
8709                 if (crtc->pipe != PIPE_B)
8710                         return;
8711         } else {
8712                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8713                         return;
8714         }
8715
8716         pipe_config->gmch_pfit.control = tmp;
8717         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8718 }
8719
8720 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8721                                struct intel_crtc_state *pipe_config)
8722 {
8723         struct drm_device *dev = crtc->base.dev;
8724         struct drm_i915_private *dev_priv = to_i915(dev);
8725         enum pipe pipe = crtc->pipe;
8726         struct dpll clock;
8727         u32 mdiv;
8728         int refclk = 100000;
8729
8730         /* In case of DSI, DPLL will not be used */
8731         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8732                 return;
8733
8734         vlv_dpio_get(dev_priv);
8735         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8736         vlv_dpio_put(dev_priv);
8737
8738         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8739         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8740         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8741         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8742         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8743
8744         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8745 }
8746
8747 static void
8748 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8749                               struct intel_initial_plane_config *plane_config)
8750 {
8751         struct drm_device *dev = crtc->base.dev;
8752         struct drm_i915_private *dev_priv = to_i915(dev);
8753         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8754         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8755         enum pipe pipe;
8756         u32 val, base, offset;
8757         int fourcc, pixel_format;
8758         unsigned int aligned_height;
8759         struct drm_framebuffer *fb;
8760         struct intel_framebuffer *intel_fb;
8761
8762         if (!plane->get_hw_state(plane, &pipe))
8763                 return;
8764
8765         WARN_ON(pipe != crtc->pipe);
8766
8767         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8768         if (!intel_fb) {
8769                 DRM_DEBUG_KMS("failed to alloc fb\n");
8770                 return;
8771         }
8772
8773         fb = &intel_fb->base;
8774
8775         fb->dev = dev;
8776
8777         val = I915_READ(DSPCNTR(i9xx_plane));
8778
8779         if (INTEL_GEN(dev_priv) >= 4) {
8780                 if (val & DISPPLANE_TILED) {
8781                         plane_config->tiling = I915_TILING_X;
8782                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8783                 }
8784
8785                 if (val & DISPPLANE_ROTATE_180)
8786                         plane_config->rotation = DRM_MODE_ROTATE_180;
8787         }
8788
8789         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8790             val & DISPPLANE_MIRROR)
8791                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8792
8793         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8794         fourcc = i9xx_format_to_fourcc(pixel_format);
8795         fb->format = drm_format_info(fourcc);
8796
8797         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8798                 offset = I915_READ(DSPOFFSET(i9xx_plane));
8799                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8800         } else if (INTEL_GEN(dev_priv) >= 4) {
8801                 if (plane_config->tiling)
8802                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
8803                 else
8804                         offset = I915_READ(DSPLINOFF(i9xx_plane));
8805                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8806         } else {
8807                 base = I915_READ(DSPADDR(i9xx_plane));
8808         }
8809         plane_config->base = base;
8810
8811         val = I915_READ(PIPESRC(pipe));
8812         fb->width = ((val >> 16) & 0xfff) + 1;
8813         fb->height = ((val >> 0) & 0xfff) + 1;
8814
8815         val = I915_READ(DSPSTRIDE(i9xx_plane));
8816         fb->pitches[0] = val & 0xffffffc0;
8817
8818         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8819
8820         plane_config->size = fb->pitches[0] * aligned_height;
8821
8822         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8823                       crtc->base.name, plane->base.name, fb->width, fb->height,
8824                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8825                       plane_config->size);
8826
8827         plane_config->fb = intel_fb;
8828 }
8829
8830 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8831                                struct intel_crtc_state *pipe_config)
8832 {
8833         struct drm_device *dev = crtc->base.dev;
8834         struct drm_i915_private *dev_priv = to_i915(dev);
8835         enum pipe pipe = crtc->pipe;
8836         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8837         struct dpll clock;
8838         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8839         int refclk = 100000;
8840
8841         /* In case of DSI, DPLL will not be used */
8842         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8843                 return;
8844
8845         vlv_dpio_get(dev_priv);
8846         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8847         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8848         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8849         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8850         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8851         vlv_dpio_put(dev_priv);
8852
8853         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8854         clock.m2 = (pll_dw0 & 0xff) << 22;
8855         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8856                 clock.m2 |= pll_dw2 & 0x3fffff;
8857         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8858         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8859         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8860
8861         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8862 }
8863
8864 static enum intel_output_format
8865 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
8866 {
8867         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8868         u32 tmp;
8869
8870         tmp = I915_READ(PIPEMISC(crtc->pipe));
8871
8872         if (tmp & PIPEMISC_YUV420_ENABLE) {
8873                 /* We support 4:2:0 in full blend mode only */
8874                 WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
8875
8876                 return INTEL_OUTPUT_FORMAT_YCBCR420;
8877         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8878                 return INTEL_OUTPUT_FORMAT_YCBCR444;
8879         } else {
8880                 return INTEL_OUTPUT_FORMAT_RGB;
8881         }
8882 }
8883
8884 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8885 {
8886         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8887         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8889         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8890         u32 tmp;
8891
8892         tmp = I915_READ(DSPCNTR(i9xx_plane));
8893
8894         if (tmp & DISPPLANE_GAMMA_ENABLE)
8895                 crtc_state->gamma_enable = true;
8896
8897         if (!HAS_GMCH(dev_priv) &&
8898             tmp & DISPPLANE_PIPE_CSC_ENABLE)
8899                 crtc_state->csc_enable = true;
8900 }
8901
8902 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8903                                  struct intel_crtc_state *pipe_config)
8904 {
8905         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8906         enum intel_display_power_domain power_domain;
8907         intel_wakeref_t wakeref;
8908         u32 tmp;
8909         bool ret;
8910
8911         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8912         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8913         if (!wakeref)
8914                 return false;
8915
8916         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8917         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8918         pipe_config->shared_dpll = NULL;
8919         pipe_config->master_transcoder = INVALID_TRANSCODER;
8920
8921         ret = false;
8922
8923         tmp = I915_READ(PIPECONF(crtc->pipe));
8924         if (!(tmp & PIPECONF_ENABLE))
8925                 goto out;
8926
8927         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8928             IS_CHERRYVIEW(dev_priv)) {
8929                 switch (tmp & PIPECONF_BPC_MASK) {
8930                 case PIPECONF_6BPC:
8931                         pipe_config->pipe_bpp = 18;
8932                         break;
8933                 case PIPECONF_8BPC:
8934                         pipe_config->pipe_bpp = 24;
8935                         break;
8936                 case PIPECONF_10BPC:
8937                         pipe_config->pipe_bpp = 30;
8938                         break;
8939                 default:
8940                         break;
8941                 }
8942         }
8943
8944         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8945             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8946                 pipe_config->limited_color_range = true;
8947
8948         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8949                 PIPECONF_GAMMA_MODE_SHIFT;
8950
8951         if (IS_CHERRYVIEW(dev_priv))
8952                 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8953
8954         i9xx_get_pipe_color_config(pipe_config);
8955         intel_color_get_config(pipe_config);
8956
8957         if (INTEL_GEN(dev_priv) < 4)
8958                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8959
8960         intel_get_pipe_timings(crtc, pipe_config);
8961         intel_get_pipe_src_size(crtc, pipe_config);
8962
8963         i9xx_get_pfit_config(crtc, pipe_config);
8964
8965         if (INTEL_GEN(dev_priv) >= 4) {
8966                 /* No way to read it out on pipes B and C */
8967                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8968                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8969                 else
8970                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8971                 pipe_config->pixel_multiplier =
8972                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8973                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8974                 pipe_config->dpll_hw_state.dpll_md = tmp;
8975         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8976                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8977                 tmp = I915_READ(DPLL(crtc->pipe));
8978                 pipe_config->pixel_multiplier =
8979                         ((tmp & SDVO_MULTIPLIER_MASK)
8980                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8981         } else {
8982                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8983                  * port and will be fixed up in the encoder->get_config
8984                  * function. */
8985                 pipe_config->pixel_multiplier = 1;
8986         }
8987         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8988         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8989                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8990                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8991         } else {
8992                 /* Mask out read-only status bits. */
8993                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8994                                                      DPLL_PORTC_READY_MASK |
8995                                                      DPLL_PORTB_READY_MASK);
8996         }
8997
8998         if (IS_CHERRYVIEW(dev_priv))
8999                 chv_crtc_clock_get(crtc, pipe_config);
9000         else if (IS_VALLEYVIEW(dev_priv))
9001                 vlv_crtc_clock_get(crtc, pipe_config);
9002         else
9003                 i9xx_crtc_clock_get(crtc, pipe_config);
9004
9005         /*
9006          * Normally the dotclock is filled in by the encoder .get_config()
9007          * but in case the pipe is enabled w/o any ports we need a sane
9008          * default.
9009          */
9010         pipe_config->hw.adjusted_mode.crtc_clock =
9011                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9012
9013         ret = true;
9014
9015 out:
9016         intel_display_power_put(dev_priv, power_domain, wakeref);
9017
9018         return ret;
9019 }
9020
9021 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
9022 {
9023         struct intel_encoder *encoder;
9024         int i;
9025         u32 val, final;
9026         bool has_lvds = false;
9027         bool has_cpu_edp = false;
9028         bool has_panel = false;
9029         bool has_ck505 = false;
9030         bool can_ssc = false;
9031         bool using_ssc_source = false;
9032
9033         /* We need to take the global config into account */
9034         for_each_intel_encoder(&dev_priv->drm, encoder) {
9035                 switch (encoder->type) {
9036                 case INTEL_OUTPUT_LVDS:
9037                         has_panel = true;
9038                         has_lvds = true;
9039                         break;
9040                 case INTEL_OUTPUT_EDP:
9041                         has_panel = true;
9042                         if (encoder->port == PORT_A)
9043                                 has_cpu_edp = true;
9044                         break;
9045                 default:
9046                         break;
9047                 }
9048         }
9049
9050         if (HAS_PCH_IBX(dev_priv)) {
9051                 has_ck505 = dev_priv->vbt.display_clock_mode;
9052                 can_ssc = has_ck505;
9053         } else {
9054                 has_ck505 = false;
9055                 can_ssc = true;
9056         }
9057
9058         /* Check if any DPLLs are using the SSC source */
9059         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9060                 u32 temp = I915_READ(PCH_DPLL(i));
9061
9062                 if (!(temp & DPLL_VCO_ENABLE))
9063                         continue;
9064
9065                 if ((temp & PLL_REF_INPUT_MASK) ==
9066                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9067                         using_ssc_source = true;
9068                         break;
9069                 }
9070         }
9071
9072         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9073                       has_panel, has_lvds, has_ck505, using_ssc_source);
9074
9075         /* Ironlake: try to setup display ref clock before DPLL
9076          * enabling. This is only under driver's control after
9077          * PCH B stepping, previous chipset stepping should be
9078          * ignoring this setting.
9079          */
9080         val = I915_READ(PCH_DREF_CONTROL);
9081
9082         /* As we must carefully and slowly disable/enable each source in turn,
9083          * compute the final state we want first and check if we need to
9084          * make any changes at all.
9085          */
9086         final = val;
9087         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9088         if (has_ck505)
9089                 final |= DREF_NONSPREAD_CK505_ENABLE;
9090         else
9091                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9092
9093         final &= ~DREF_SSC_SOURCE_MASK;
9094         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9095         final &= ~DREF_SSC1_ENABLE;
9096
9097         if (has_panel) {
9098                 final |= DREF_SSC_SOURCE_ENABLE;
9099
9100                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9101                         final |= DREF_SSC1_ENABLE;
9102
9103                 if (has_cpu_edp) {
9104                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9105                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9106                         else
9107                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9108                 } else
9109                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9110         } else if (using_ssc_source) {
9111                 final |= DREF_SSC_SOURCE_ENABLE;
9112                 final |= DREF_SSC1_ENABLE;
9113         }
9114
9115         if (final == val)
9116                 return;
9117
9118         /* Always enable nonspread source */
9119         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9120
9121         if (has_ck505)
9122                 val |= DREF_NONSPREAD_CK505_ENABLE;
9123         else
9124                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9125
9126         if (has_panel) {
9127                 val &= ~DREF_SSC_SOURCE_MASK;
9128                 val |= DREF_SSC_SOURCE_ENABLE;
9129
9130                 /* SSC must be turned on before enabling the CPU output  */
9131                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9132                         DRM_DEBUG_KMS("Using SSC on panel\n");
9133                         val |= DREF_SSC1_ENABLE;
9134                 } else
9135                         val &= ~DREF_SSC1_ENABLE;
9136
9137                 /* Get SSC going before enabling the outputs */
9138                 I915_WRITE(PCH_DREF_CONTROL, val);
9139                 POSTING_READ(PCH_DREF_CONTROL);
9140                 udelay(200);
9141
9142                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9143
9144                 /* Enable CPU source on CPU attached eDP */
9145                 if (has_cpu_edp) {
9146                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9147                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
9148                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9149                         } else
9150                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9151                 } else
9152                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9153
9154                 I915_WRITE(PCH_DREF_CONTROL, val);
9155                 POSTING_READ(PCH_DREF_CONTROL);
9156                 udelay(200);
9157         } else {
9158                 DRM_DEBUG_KMS("Disabling CPU source output\n");
9159
9160                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9161
9162                 /* Turn off CPU output */
9163                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9164
9165                 I915_WRITE(PCH_DREF_CONTROL, val);
9166                 POSTING_READ(PCH_DREF_CONTROL);
9167                 udelay(200);
9168
9169                 if (!using_ssc_source) {
9170                         DRM_DEBUG_KMS("Disabling SSC source\n");
9171
9172                         /* Turn off the SSC source */
9173                         val &= ~DREF_SSC_SOURCE_MASK;
9174                         val |= DREF_SSC_SOURCE_DISABLE;
9175
9176                         /* Turn off SSC1 */
9177                         val &= ~DREF_SSC1_ENABLE;
9178
9179                         I915_WRITE(PCH_DREF_CONTROL, val);
9180                         POSTING_READ(PCH_DREF_CONTROL);
9181                         udelay(200);
9182                 }
9183         }
9184
9185         BUG_ON(val != final);
9186 }
9187
9188 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9189 {
9190         u32 tmp;
9191
9192         tmp = I915_READ(SOUTH_CHICKEN2);
9193         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9194         I915_WRITE(SOUTH_CHICKEN2, tmp);
9195
9196         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9197                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9198                 DRM_ERROR("FDI mPHY reset assert timeout\n");
9199
9200         tmp = I915_READ(SOUTH_CHICKEN2);
9201         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9202         I915_WRITE(SOUTH_CHICKEN2, tmp);
9203
9204         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9205                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9206                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9207 }
9208
9209 /* WaMPhyProgramming:hsw */
9210 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9211 {
9212         u32 tmp;
9213
9214         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9215         tmp &= ~(0xFF << 24);
9216         tmp |= (0x12 << 24);
9217         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9218
9219         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9220         tmp |= (1 << 11);
9221         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9222
9223         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9224         tmp |= (1 << 11);
9225         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9226
9227         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9228         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9229         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9230
9231         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9232         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9233         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9234
9235         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9236         tmp &= ~(7 << 13);
9237         tmp |= (5 << 13);
9238         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9239
9240         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9241         tmp &= ~(7 << 13);
9242         tmp |= (5 << 13);
9243         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9244
9245         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9246         tmp &= ~0xFF;
9247         tmp |= 0x1C;
9248         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9249
9250         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9251         tmp &= ~0xFF;
9252         tmp |= 0x1C;
9253         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9254
9255         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9256         tmp &= ~(0xFF << 16);
9257         tmp |= (0x1C << 16);
9258         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9259
9260         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9261         tmp &= ~(0xFF << 16);
9262         tmp |= (0x1C << 16);
9263         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9264
9265         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9266         tmp |= (1 << 27);
9267         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9268
9269         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9270         tmp |= (1 << 27);
9271         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9272
9273         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9274         tmp &= ~(0xF << 28);
9275         tmp |= (4 << 28);
9276         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9277
9278         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9279         tmp &= ~(0xF << 28);
9280         tmp |= (4 << 28);
9281         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9282 }
9283
9284 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9285  * Programming" based on the parameters passed:
9286  * - Sequence to enable CLKOUT_DP
9287  * - Sequence to enable CLKOUT_DP without spread
9288  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9289  */
9290 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9291                                  bool with_spread, bool with_fdi)
9292 {
9293         u32 reg, tmp;
9294
9295         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9296                 with_spread = true;
9297         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9298             with_fdi, "LP PCH doesn't have FDI\n"))
9299                 with_fdi = false;
9300
9301         mutex_lock(&dev_priv->sb_lock);
9302
9303         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9304         tmp &= ~SBI_SSCCTL_DISABLE;
9305         tmp |= SBI_SSCCTL_PATHALT;
9306         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9307
9308         udelay(24);
9309
9310         if (with_spread) {
9311                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9312                 tmp &= ~SBI_SSCCTL_PATHALT;
9313                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9314
9315                 if (with_fdi) {
9316                         lpt_reset_fdi_mphy(dev_priv);
9317                         lpt_program_fdi_mphy(dev_priv);
9318                 }
9319         }
9320
9321         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9322         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9323         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9324         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9325
9326         mutex_unlock(&dev_priv->sb_lock);
9327 }
9328
9329 /* Sequence to disable CLKOUT_DP */
9330 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9331 {
9332         u32 reg, tmp;
9333
9334         mutex_lock(&dev_priv->sb_lock);
9335
9336         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9337         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9338         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9339         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9340
9341         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9342         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9343                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9344                         tmp |= SBI_SSCCTL_PATHALT;
9345                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9346                         udelay(32);
9347                 }
9348                 tmp |= SBI_SSCCTL_DISABLE;
9349                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9350         }
9351
9352         mutex_unlock(&dev_priv->sb_lock);
9353 }
9354
9355 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9356
9357 static const u16 sscdivintphase[] = {
9358         [BEND_IDX( 50)] = 0x3B23,
9359         [BEND_IDX( 45)] = 0x3B23,
9360         [BEND_IDX( 40)] = 0x3C23,
9361         [BEND_IDX( 35)] = 0x3C23,
9362         [BEND_IDX( 30)] = 0x3D23,
9363         [BEND_IDX( 25)] = 0x3D23,
9364         [BEND_IDX( 20)] = 0x3E23,
9365         [BEND_IDX( 15)] = 0x3E23,
9366         [BEND_IDX( 10)] = 0x3F23,
9367         [BEND_IDX(  5)] = 0x3F23,
9368         [BEND_IDX(  0)] = 0x0025,
9369         [BEND_IDX( -5)] = 0x0025,
9370         [BEND_IDX(-10)] = 0x0125,
9371         [BEND_IDX(-15)] = 0x0125,
9372         [BEND_IDX(-20)] = 0x0225,
9373         [BEND_IDX(-25)] = 0x0225,
9374         [BEND_IDX(-30)] = 0x0325,
9375         [BEND_IDX(-35)] = 0x0325,
9376         [BEND_IDX(-40)] = 0x0425,
9377         [BEND_IDX(-45)] = 0x0425,
9378         [BEND_IDX(-50)] = 0x0525,
9379 };
9380
9381 /*
9382  * Bend CLKOUT_DP
9383  * steps -50 to 50 inclusive, in steps of 5
9384  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9385  * change in clock period = -(steps / 10) * 5.787 ps
9386  */
9387 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9388 {
9389         u32 tmp;
9390         int idx = BEND_IDX(steps);
9391
9392         if (WARN_ON(steps % 5 != 0))
9393                 return;
9394
9395         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9396                 return;
9397
9398         mutex_lock(&dev_priv->sb_lock);
9399
9400         if (steps % 10 != 0)
9401                 tmp = 0xAAAAAAAB;
9402         else
9403                 tmp = 0x00000000;
9404         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9405
9406         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9407         tmp &= 0xffff0000;
9408         tmp |= sscdivintphase[idx];
9409         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9410
9411         mutex_unlock(&dev_priv->sb_lock);
9412 }
9413
9414 #undef BEND_IDX
9415
9416 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9417 {
9418         u32 fuse_strap = I915_READ(FUSE_STRAP);
9419         u32 ctl = I915_READ(SPLL_CTL);
9420
9421         if ((ctl & SPLL_PLL_ENABLE) == 0)
9422                 return false;
9423
9424         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9425             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9426                 return true;
9427
9428         if (IS_BROADWELL(dev_priv) &&
9429             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9430                 return true;
9431
9432         return false;
9433 }
9434
9435 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9436                                enum intel_dpll_id id)
9437 {
9438         u32 fuse_strap = I915_READ(FUSE_STRAP);
9439         u32 ctl = I915_READ(WRPLL_CTL(id));
9440
9441         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9442                 return false;
9443
9444         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9445                 return true;
9446
9447         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9448             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9449             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9450                 return true;
9451
9452         return false;
9453 }
9454
9455 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9456 {
9457         struct intel_encoder *encoder;
9458         bool has_fdi = false;
9459
9460         for_each_intel_encoder(&dev_priv->drm, encoder) {
9461                 switch (encoder->type) {
9462                 case INTEL_OUTPUT_ANALOG:
9463                         has_fdi = true;
9464                         break;
9465                 default:
9466                         break;
9467                 }
9468         }
9469
9470         /*
9471          * The BIOS may have decided to use the PCH SSC
9472          * reference so we must not disable it until the
9473          * relevant PLLs have stopped relying on it. We'll
9474          * just leave the PCH SSC reference enabled in case
9475          * any active PLL is using it. It will get disabled
9476          * after runtime suspend if we don't have FDI.
9477          *
9478          * TODO: Move the whole reference clock handling
9479          * to the modeset sequence proper so that we can
9480          * actually enable/disable/reconfigure these things
9481          * safely. To do that we need to introduce a real
9482          * clock hierarchy. That would also allow us to do
9483          * clock bending finally.
9484          */
9485         dev_priv->pch_ssc_use = 0;
9486
9487         if (spll_uses_pch_ssc(dev_priv)) {
9488                 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9489                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9490         }
9491
9492         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9493                 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9494                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9495         }
9496
9497         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9498                 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9499                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9500         }
9501
9502         if (dev_priv->pch_ssc_use)
9503                 return;
9504
9505         if (has_fdi) {
9506                 lpt_bend_clkout_dp(dev_priv, 0);
9507                 lpt_enable_clkout_dp(dev_priv, true, true);
9508         } else {
9509                 lpt_disable_clkout_dp(dev_priv);
9510         }
9511 }
9512
9513 /*
9514  * Initialize reference clocks when the driver loads
9515  */
9516 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9517 {
9518         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9519                 ironlake_init_pch_refclk(dev_priv);
9520         else if (HAS_PCH_LPT(dev_priv))
9521                 lpt_init_pch_refclk(dev_priv);
9522 }
9523
9524 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9525 {
9526         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9528         enum pipe pipe = crtc->pipe;
9529         u32 val;
9530
9531         val = 0;
9532
9533         switch (crtc_state->pipe_bpp) {
9534         case 18:
9535                 val |= PIPECONF_6BPC;
9536                 break;
9537         case 24:
9538                 val |= PIPECONF_8BPC;
9539                 break;
9540         case 30:
9541                 val |= PIPECONF_10BPC;
9542                 break;
9543         case 36:
9544                 val |= PIPECONF_12BPC;
9545                 break;
9546         default:
9547                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9548                 BUG();
9549         }
9550
9551         if (crtc_state->dither)
9552                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9553
9554         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9555                 val |= PIPECONF_INTERLACED_ILK;
9556         else
9557                 val |= PIPECONF_PROGRESSIVE;
9558
9559         /*
9560          * This would end up with an odd purple hue over
9561          * the entire display. Make sure we don't do it.
9562          */
9563         WARN_ON(crtc_state->limited_color_range &&
9564                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
9565
9566         if (crtc_state->limited_color_range)
9567                 val |= PIPECONF_COLOR_RANGE_SELECT;
9568
9569         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9570                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
9571
9572         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9573
9574         val |= PIPECONF_FRAME_START_DELAY(0);
9575
9576         I915_WRITE(PIPECONF(pipe), val);
9577         POSTING_READ(PIPECONF(pipe));
9578 }
9579
9580 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9581 {
9582         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9583         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9584         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9585         u32 val = 0;
9586
9587         if (IS_HASWELL(dev_priv) && crtc_state->dither)
9588                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9589
9590         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9591                 val |= PIPECONF_INTERLACED_ILK;
9592         else
9593                 val |= PIPECONF_PROGRESSIVE;
9594
9595         if (IS_HASWELL(dev_priv) &&
9596             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
9597                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
9598
9599         I915_WRITE(PIPECONF(cpu_transcoder), val);
9600         POSTING_READ(PIPECONF(cpu_transcoder));
9601 }
9602
9603 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9604 {
9605         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9606         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9607         u32 val = 0;
9608
9609         switch (crtc_state->pipe_bpp) {
9610         case 18:
9611                 val |= PIPEMISC_DITHER_6_BPC;
9612                 break;
9613         case 24:
9614                 val |= PIPEMISC_DITHER_8_BPC;
9615                 break;
9616         case 30:
9617                 val |= PIPEMISC_DITHER_10_BPC;
9618                 break;
9619         case 36:
9620                 val |= PIPEMISC_DITHER_12_BPC;
9621                 break;
9622         default:
9623                 MISSING_CASE(crtc_state->pipe_bpp);
9624                 break;
9625         }
9626
9627         if (crtc_state->dither)
9628                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9629
9630         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9631             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9632                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9633
9634         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9635                 val |= PIPEMISC_YUV420_ENABLE |
9636                         PIPEMISC_YUV420_MODE_FULL_BLEND;
9637
9638         if (INTEL_GEN(dev_priv) >= 11 &&
9639             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9640                                            BIT(PLANE_CURSOR))) == 0)
9641                 val |= PIPEMISC_HDR_MODE_PRECISION;
9642
9643         I915_WRITE(PIPEMISC(crtc->pipe), val);
9644 }
9645
9646 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9647 {
9648         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9649         u32 tmp;
9650
9651         tmp = I915_READ(PIPEMISC(crtc->pipe));
9652
9653         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9654         case PIPEMISC_DITHER_6_BPC:
9655                 return 18;
9656         case PIPEMISC_DITHER_8_BPC:
9657                 return 24;
9658         case PIPEMISC_DITHER_10_BPC:
9659                 return 30;
9660         case PIPEMISC_DITHER_12_BPC:
9661                 return 36;
9662         default:
9663                 MISSING_CASE(tmp);
9664                 return 0;
9665         }
9666 }
9667
9668 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9669 {
9670         /*
9671          * Account for spread spectrum to avoid
9672          * oversubscribing the link. Max center spread
9673          * is 2.5%; use 5% for safety's sake.
9674          */
9675         u32 bps = target_clock * bpp * 21 / 20;
9676         return DIV_ROUND_UP(bps, link_bw * 8);
9677 }
9678
9679 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9680 {
9681         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9682 }
9683
9684 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9685                                   struct intel_crtc_state *crtc_state,
9686                                   struct dpll *reduced_clock)
9687 {
9688         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9689         u32 dpll, fp, fp2;
9690         int factor;
9691
9692         /* Enable autotuning of the PLL clock (if permissible) */
9693         factor = 21;
9694         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9695                 if ((intel_panel_use_ssc(dev_priv) &&
9696                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9697                     (HAS_PCH_IBX(dev_priv) &&
9698                      intel_is_dual_link_lvds(dev_priv)))
9699                         factor = 25;
9700         } else if (crtc_state->sdvo_tv_clock) {
9701                 factor = 20;
9702         }
9703
9704         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9705
9706         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9707                 fp |= FP_CB_TUNE;
9708
9709         if (reduced_clock) {
9710                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9711
9712                 if (reduced_clock->m < factor * reduced_clock->n)
9713                         fp2 |= FP_CB_TUNE;
9714         } else {
9715                 fp2 = fp;
9716         }
9717
9718         dpll = 0;
9719
9720         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9721                 dpll |= DPLLB_MODE_LVDS;
9722         else
9723                 dpll |= DPLLB_MODE_DAC_SERIAL;
9724
9725         dpll |= (crtc_state->pixel_multiplier - 1)
9726                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9727
9728         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9729             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9730                 dpll |= DPLL_SDVO_HIGH_SPEED;
9731
9732         if (intel_crtc_has_dp_encoder(crtc_state))
9733                 dpll |= DPLL_SDVO_HIGH_SPEED;
9734
9735         /*
9736          * The high speed IO clock is only really required for
9737          * SDVO/HDMI/DP, but we also enable it for CRT to make it
9738          * possible to share the DPLL between CRT and HDMI. Enabling
9739          * the clock needlessly does no real harm, except use up a
9740          * bit of power potentially.
9741          *
9742          * We'll limit this to IVB with 3 pipes, since it has only two
9743          * DPLLs and so DPLL sharing is the only way to get three pipes
9744          * driving PCH ports at the same time. On SNB we could do this,
9745          * and potentially avoid enabling the second DPLL, but it's not
9746          * clear if it''s a win or loss power wise. No point in doing
9747          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9748          */
9749         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
9750             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9751                 dpll |= DPLL_SDVO_HIGH_SPEED;
9752
9753         /* compute bitmask from p1 value */
9754         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9755         /* also FPA1 */
9756         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9757
9758         switch (crtc_state->dpll.p2) {
9759         case 5:
9760                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9761                 break;
9762         case 7:
9763                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9764                 break;
9765         case 10:
9766                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9767                 break;
9768         case 14:
9769                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9770                 break;
9771         }
9772
9773         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9774             intel_panel_use_ssc(dev_priv))
9775                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9776         else
9777                 dpll |= PLL_REF_INPUT_DREFCLK;
9778
9779         dpll |= DPLL_VCO_ENABLE;
9780
9781         crtc_state->dpll_hw_state.dpll = dpll;
9782         crtc_state->dpll_hw_state.fp0 = fp;
9783         crtc_state->dpll_hw_state.fp1 = fp2;
9784 }
9785
9786 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9787                                        struct intel_crtc_state *crtc_state)
9788 {
9789         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9790         struct intel_atomic_state *state =
9791                 to_intel_atomic_state(crtc_state->uapi.state);
9792         const struct intel_limit *limit;
9793         int refclk = 120000;
9794
9795         memset(&crtc_state->dpll_hw_state, 0,
9796                sizeof(crtc_state->dpll_hw_state));
9797
9798         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9799         if (!crtc_state->has_pch_encoder)
9800                 return 0;
9801
9802         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9803                 if (intel_panel_use_ssc(dev_priv)) {
9804                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9805                                       dev_priv->vbt.lvds_ssc_freq);
9806                         refclk = dev_priv->vbt.lvds_ssc_freq;
9807                 }
9808
9809                 if (intel_is_dual_link_lvds(dev_priv)) {
9810                         if (refclk == 100000)
9811                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9812                         else
9813                                 limit = &intel_limits_ironlake_dual_lvds;
9814                 } else {
9815                         if (refclk == 100000)
9816                                 limit = &intel_limits_ironlake_single_lvds_100m;
9817                         else
9818                                 limit = &intel_limits_ironlake_single_lvds;
9819                 }
9820         } else {
9821                 limit = &intel_limits_ironlake_dac;
9822         }
9823
9824         if (!crtc_state->clock_set &&
9825             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9826                                 refclk, NULL, &crtc_state->dpll)) {
9827                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9828                 return -EINVAL;
9829         }
9830
9831         ironlake_compute_dpll(crtc, crtc_state, NULL);
9832
9833         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9834                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9835                               pipe_name(crtc->pipe));
9836                 return -EINVAL;
9837         }
9838
9839         return 0;
9840 }
9841
9842 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9843                                          struct intel_link_m_n *m_n)
9844 {
9845         struct drm_device *dev = crtc->base.dev;
9846         struct drm_i915_private *dev_priv = to_i915(dev);
9847         enum pipe pipe = crtc->pipe;
9848
9849         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9850         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9851         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9852                 & ~TU_SIZE_MASK;
9853         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9854         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9855                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9856 }
9857
9858 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9859                                          enum transcoder transcoder,
9860                                          struct intel_link_m_n *m_n,
9861                                          struct intel_link_m_n *m2_n2)
9862 {
9863         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9864         enum pipe pipe = crtc->pipe;
9865
9866         if (INTEL_GEN(dev_priv) >= 5) {
9867                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9868                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9869                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9870                         & ~TU_SIZE_MASK;
9871                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9872                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9873                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9874
9875                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9876                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9877                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9878                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9879                                         & ~TU_SIZE_MASK;
9880                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9881                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9882                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9883                 }
9884         } else {
9885                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9886                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9887                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9888                         & ~TU_SIZE_MASK;
9889                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9890                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9891                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9892         }
9893 }
9894
9895 void intel_dp_get_m_n(struct intel_crtc *crtc,
9896                       struct intel_crtc_state *pipe_config)
9897 {
9898         if (pipe_config->has_pch_encoder)
9899                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9900         else
9901                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9902                                              &pipe_config->dp_m_n,
9903                                              &pipe_config->dp_m2_n2);
9904 }
9905
9906 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9907                                         struct intel_crtc_state *pipe_config)
9908 {
9909         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9910                                      &pipe_config->fdi_m_n, NULL);
9911 }
9912
9913 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9914                                     struct intel_crtc_state *pipe_config)
9915 {
9916         struct drm_device *dev = crtc->base.dev;
9917         struct drm_i915_private *dev_priv = to_i915(dev);
9918         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9919         u32 ps_ctrl = 0;
9920         int id = -1;
9921         int i;
9922
9923         /* find scaler attached to this pipe */
9924         for (i = 0; i < crtc->num_scalers; i++) {
9925                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9926                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9927                         id = i;
9928                         pipe_config->pch_pfit.enabled = true;
9929                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9930                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9931                         scaler_state->scalers[i].in_use = true;
9932                         break;
9933                 }
9934         }
9935
9936         scaler_state->scaler_id = id;
9937         if (id >= 0) {
9938                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9939         } else {
9940                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9941         }
9942 }
9943
9944 static void
9945 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9946                                  struct intel_initial_plane_config *plane_config)
9947 {
9948         struct drm_device *dev = crtc->base.dev;
9949         struct drm_i915_private *dev_priv = to_i915(dev);
9950         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9951         enum plane_id plane_id = plane->id;
9952         enum pipe pipe;
9953         u32 val, base, offset, stride_mult, tiling, alpha;
9954         int fourcc, pixel_format;
9955         unsigned int aligned_height;
9956         struct drm_framebuffer *fb;
9957         struct intel_framebuffer *intel_fb;
9958
9959         if (!plane->get_hw_state(plane, &pipe))
9960                 return;
9961
9962         WARN_ON(pipe != crtc->pipe);
9963
9964         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9965         if (!intel_fb) {
9966                 DRM_DEBUG_KMS("failed to alloc fb\n");
9967                 return;
9968         }
9969
9970         fb = &intel_fb->base;
9971
9972         fb->dev = dev;
9973
9974         val = I915_READ(PLANE_CTL(pipe, plane_id));
9975
9976         if (INTEL_GEN(dev_priv) >= 11)
9977                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9978         else
9979                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9980
9981         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9982                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9983                 alpha &= PLANE_COLOR_ALPHA_MASK;
9984         } else {
9985                 alpha = val & PLANE_CTL_ALPHA_MASK;
9986         }
9987
9988         fourcc = skl_format_to_fourcc(pixel_format,
9989                                       val & PLANE_CTL_ORDER_RGBX, alpha);
9990         fb->format = drm_format_info(fourcc);
9991
9992         tiling = val & PLANE_CTL_TILED_MASK;
9993         switch (tiling) {
9994         case PLANE_CTL_TILED_LINEAR:
9995                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9996                 break;
9997         case PLANE_CTL_TILED_X:
9998                 plane_config->tiling = I915_TILING_X;
9999                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10000                 break;
10001         case PLANE_CTL_TILED_Y:
10002                 plane_config->tiling = I915_TILING_Y;
10003                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10004                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
10005                 else
10006                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10007                 break;
10008         case PLANE_CTL_TILED_YF:
10009                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10010                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10011                 else
10012                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10013                 break;
10014         default:
10015                 MISSING_CASE(tiling);
10016                 goto error;
10017         }
10018
10019         /*
10020          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10021          * while i915 HW rotation is clockwise, thats why this swapping.
10022          */
10023         switch (val & PLANE_CTL_ROTATE_MASK) {
10024         case PLANE_CTL_ROTATE_0:
10025                 plane_config->rotation = DRM_MODE_ROTATE_0;
10026                 break;
10027         case PLANE_CTL_ROTATE_90:
10028                 plane_config->rotation = DRM_MODE_ROTATE_270;
10029                 break;
10030         case PLANE_CTL_ROTATE_180:
10031                 plane_config->rotation = DRM_MODE_ROTATE_180;
10032                 break;
10033         case PLANE_CTL_ROTATE_270:
10034                 plane_config->rotation = DRM_MODE_ROTATE_90;
10035                 break;
10036         }
10037
10038         if (INTEL_GEN(dev_priv) >= 10 &&
10039             val & PLANE_CTL_FLIP_HORIZONTAL)
10040                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10041
10042         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10043         plane_config->base = base;
10044
10045         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
10046
10047         val = I915_READ(PLANE_SIZE(pipe, plane_id));
10048         fb->height = ((val >> 16) & 0xffff) + 1;
10049         fb->width = ((val >> 0) & 0xffff) + 1;
10050
10051         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
10052         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10053         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10054
10055         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10056
10057         plane_config->size = fb->pitches[0] * aligned_height;
10058
10059         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10060                       crtc->base.name, plane->base.name, fb->width, fb->height,
10061                       fb->format->cpp[0] * 8, base, fb->pitches[0],
10062                       plane_config->size);
10063
10064         plane_config->fb = intel_fb;
10065         return;
10066
10067 error:
10068         kfree(intel_fb);
10069 }
10070
10071 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
10072                                      struct intel_crtc_state *pipe_config)
10073 {
10074         struct drm_device *dev = crtc->base.dev;
10075         struct drm_i915_private *dev_priv = to_i915(dev);
10076         u32 tmp;
10077
10078         tmp = I915_READ(PF_CTL(crtc->pipe));
10079
10080         if (tmp & PF_ENABLE) {
10081                 pipe_config->pch_pfit.enabled = true;
10082                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
10083                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
10084
10085                 /* We currently do not free assignements of panel fitters on
10086                  * ivb/hsw (since we don't use the higher upscaling modes which
10087                  * differentiates them) so just WARN about this case for now. */
10088                 if (IS_GEN(dev_priv, 7)) {
10089                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
10090                                 PF_PIPE_SEL_IVB(crtc->pipe));
10091                 }
10092         }
10093 }
10094
10095 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
10096                                      struct intel_crtc_state *pipe_config)
10097 {
10098         struct drm_device *dev = crtc->base.dev;
10099         struct drm_i915_private *dev_priv = to_i915(dev);
10100         enum intel_display_power_domain power_domain;
10101         intel_wakeref_t wakeref;
10102         u32 tmp;
10103         bool ret;
10104
10105         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10106         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10107         if (!wakeref)
10108                 return false;
10109
10110         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10111         pipe_config->shared_dpll = NULL;
10112         pipe_config->master_transcoder = INVALID_TRANSCODER;
10113
10114         ret = false;
10115         tmp = I915_READ(PIPECONF(crtc->pipe));
10116         if (!(tmp & PIPECONF_ENABLE))
10117                 goto out;
10118
10119         switch (tmp & PIPECONF_BPC_MASK) {
10120         case PIPECONF_6BPC:
10121                 pipe_config->pipe_bpp = 18;
10122                 break;
10123         case PIPECONF_8BPC:
10124                 pipe_config->pipe_bpp = 24;
10125                 break;
10126         case PIPECONF_10BPC:
10127                 pipe_config->pipe_bpp = 30;
10128                 break;
10129         case PIPECONF_12BPC:
10130                 pipe_config->pipe_bpp = 36;
10131                 break;
10132         default:
10133                 break;
10134         }
10135
10136         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10137                 pipe_config->limited_color_range = true;
10138
10139         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10140         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10141         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10142                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10143                 break;
10144         default:
10145                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10146                 break;
10147         }
10148
10149         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10150                 PIPECONF_GAMMA_MODE_SHIFT;
10151
10152         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10153
10154         i9xx_get_pipe_color_config(pipe_config);
10155         intel_color_get_config(pipe_config);
10156
10157         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10158                 struct intel_shared_dpll *pll;
10159                 enum intel_dpll_id pll_id;
10160
10161                 pipe_config->has_pch_encoder = true;
10162
10163                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
10164                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10165                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10166
10167                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10168
10169                 if (HAS_PCH_IBX(dev_priv)) {
10170                         /*
10171                          * The pipe->pch transcoder and pch transcoder->pll
10172                          * mapping is fixed.
10173                          */
10174                         pll_id = (enum intel_dpll_id) crtc->pipe;
10175                 } else {
10176                         tmp = I915_READ(PCH_DPLL_SEL);
10177                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10178                                 pll_id = DPLL_ID_PCH_PLL_B;
10179                         else
10180                                 pll_id= DPLL_ID_PCH_PLL_A;
10181                 }
10182
10183                 pipe_config->shared_dpll =
10184                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10185                 pll = pipe_config->shared_dpll;
10186
10187                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10188                                                 &pipe_config->dpll_hw_state));
10189
10190                 tmp = pipe_config->dpll_hw_state.dpll;
10191                 pipe_config->pixel_multiplier =
10192                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10193                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10194
10195                 ironlake_pch_clock_get(crtc, pipe_config);
10196         } else {
10197                 pipe_config->pixel_multiplier = 1;
10198         }
10199
10200         intel_get_pipe_timings(crtc, pipe_config);
10201         intel_get_pipe_src_size(crtc, pipe_config);
10202
10203         ironlake_get_pfit_config(crtc, pipe_config);
10204
10205         ret = true;
10206
10207 out:
10208         intel_display_power_put(dev_priv, power_domain, wakeref);
10209
10210         return ret;
10211 }
10212 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10213                                       struct intel_crtc_state *crtc_state)
10214 {
10215         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10216         struct intel_atomic_state *state =
10217                 to_intel_atomic_state(crtc_state->uapi.state);
10218
10219         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10220             INTEL_GEN(dev_priv) >= 11) {
10221                 struct intel_encoder *encoder =
10222                         intel_get_crtc_new_encoder(state, crtc_state);
10223
10224                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10225                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10226                                       pipe_name(crtc->pipe));
10227                         return -EINVAL;
10228                 }
10229         }
10230
10231         return 0;
10232 }
10233
10234 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10235                                    enum port port,
10236                                    struct intel_crtc_state *pipe_config)
10237 {
10238         enum intel_dpll_id id;
10239         u32 temp;
10240
10241         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10242         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10243
10244         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10245                 return;
10246
10247         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10248 }
10249
10250 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10251                                 enum port port,
10252                                 struct intel_crtc_state *pipe_config)
10253 {
10254         enum phy phy = intel_port_to_phy(dev_priv, port);
10255         enum icl_port_dpll_id port_dpll_id;
10256         enum intel_dpll_id id;
10257         u32 temp;
10258
10259         if (intel_phy_is_combo(dev_priv, phy)) {
10260                 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10261                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10262                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10263                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10264         } else if (intel_phy_is_tc(dev_priv, phy)) {
10265                 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10266
10267                 if (clk_sel == DDI_CLK_SEL_MG) {
10268                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10269                                                                     port));
10270                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10271                 } else {
10272                         WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10273                         id = DPLL_ID_ICL_TBTPLL;
10274                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10275                 }
10276         } else {
10277                 WARN(1, "Invalid port %x\n", port);
10278                 return;
10279         }
10280
10281         pipe_config->icl_port_dplls[port_dpll_id].pll =
10282                 intel_get_shared_dpll_by_id(dev_priv, id);
10283
10284         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10285 }
10286
10287 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10288                                 enum port port,
10289                                 struct intel_crtc_state *pipe_config)
10290 {
10291         enum intel_dpll_id id;
10292
10293         switch (port) {
10294         case PORT_A:
10295                 id = DPLL_ID_SKL_DPLL0;
10296                 break;
10297         case PORT_B:
10298                 id = DPLL_ID_SKL_DPLL1;
10299                 break;
10300         case PORT_C:
10301                 id = DPLL_ID_SKL_DPLL2;
10302                 break;
10303         default:
10304                 DRM_ERROR("Incorrect port type\n");
10305                 return;
10306         }
10307
10308         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10309 }
10310
10311 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10312                                 enum port port,
10313                                 struct intel_crtc_state *pipe_config)
10314 {
10315         enum intel_dpll_id id;
10316         u32 temp;
10317
10318         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10319         id = temp >> (port * 3 + 1);
10320
10321         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10322                 return;
10323
10324         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10325 }
10326
10327 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10328                                 enum port port,
10329                                 struct intel_crtc_state *pipe_config)
10330 {
10331         enum intel_dpll_id id;
10332         u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10333
10334         switch (ddi_pll_sel) {
10335         case PORT_CLK_SEL_WRPLL1:
10336                 id = DPLL_ID_WRPLL1;
10337                 break;
10338         case PORT_CLK_SEL_WRPLL2:
10339                 id = DPLL_ID_WRPLL2;
10340                 break;
10341         case PORT_CLK_SEL_SPLL:
10342                 id = DPLL_ID_SPLL;
10343                 break;
10344         case PORT_CLK_SEL_LCPLL_810:
10345                 id = DPLL_ID_LCPLL_810;
10346                 break;
10347         case PORT_CLK_SEL_LCPLL_1350:
10348                 id = DPLL_ID_LCPLL_1350;
10349                 break;
10350         case PORT_CLK_SEL_LCPLL_2700:
10351                 id = DPLL_ID_LCPLL_2700;
10352                 break;
10353         default:
10354                 MISSING_CASE(ddi_pll_sel);
10355                 /* fall through */
10356         case PORT_CLK_SEL_NONE:
10357                 return;
10358         }
10359
10360         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10361 }
10362
10363 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10364                                      struct intel_crtc_state *pipe_config,
10365                                      u64 *power_domain_mask,
10366                                      intel_wakeref_t *wakerefs)
10367 {
10368         struct drm_device *dev = crtc->base.dev;
10369         struct drm_i915_private *dev_priv = to_i915(dev);
10370         enum intel_display_power_domain power_domain;
10371         unsigned long panel_transcoder_mask = 0;
10372         unsigned long enabled_panel_transcoders = 0;
10373         enum transcoder panel_transcoder;
10374         intel_wakeref_t wf;
10375         u32 tmp;
10376
10377         if (INTEL_GEN(dev_priv) >= 11)
10378                 panel_transcoder_mask |=
10379                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10380
10381         if (HAS_TRANSCODER_EDP(dev_priv))
10382                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10383
10384         /*
10385          * The pipe->transcoder mapping is fixed with the exception of the eDP
10386          * and DSI transcoders handled below.
10387          */
10388         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10389
10390         /*
10391          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10392          * consistency and less surprising code; it's in always on power).
10393          */
10394         for_each_set_bit(panel_transcoder,
10395                          &panel_transcoder_mask,
10396                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10397                 bool force_thru = false;
10398                 enum pipe trans_pipe;
10399
10400                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10401                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10402                         continue;
10403
10404                 /*
10405                  * Log all enabled ones, only use the first one.
10406                  *
10407                  * FIXME: This won't work for two separate DSI displays.
10408                  */
10409                 enabled_panel_transcoders |= BIT(panel_transcoder);
10410                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10411                         continue;
10412
10413                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10414                 default:
10415                         WARN(1, "unknown pipe linked to transcoder %s\n",
10416                              transcoder_name(panel_transcoder));
10417                         /* fall through */
10418                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10419                         force_thru = true;
10420                         /* fall through */
10421                 case TRANS_DDI_EDP_INPUT_A_ON:
10422                         trans_pipe = PIPE_A;
10423                         break;
10424                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10425                         trans_pipe = PIPE_B;
10426                         break;
10427                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10428                         trans_pipe = PIPE_C;
10429                         break;
10430                 }
10431
10432                 if (trans_pipe == crtc->pipe) {
10433                         pipe_config->cpu_transcoder = panel_transcoder;
10434                         pipe_config->pch_pfit.force_thru = force_thru;
10435                 }
10436         }
10437
10438         /*
10439          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10440          */
10441         WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10442                 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10443
10444         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10445         WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10446
10447         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10448         if (!wf)
10449                 return false;
10450
10451         wakerefs[power_domain] = wf;
10452         *power_domain_mask |= BIT_ULL(power_domain);
10453
10454         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10455
10456         return tmp & PIPECONF_ENABLE;
10457 }
10458
10459 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10460                                          struct intel_crtc_state *pipe_config,
10461                                          u64 *power_domain_mask,
10462                                          intel_wakeref_t *wakerefs)
10463 {
10464         struct drm_device *dev = crtc->base.dev;
10465         struct drm_i915_private *dev_priv = to_i915(dev);
10466         enum intel_display_power_domain power_domain;
10467         enum transcoder cpu_transcoder;
10468         intel_wakeref_t wf;
10469         enum port port;
10470         u32 tmp;
10471
10472         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10473                 if (port == PORT_A)
10474                         cpu_transcoder = TRANSCODER_DSI_A;
10475                 else
10476                         cpu_transcoder = TRANSCODER_DSI_C;
10477
10478                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10479                 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10480
10481                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10482                 if (!wf)
10483                         continue;
10484
10485                 wakerefs[power_domain] = wf;
10486                 *power_domain_mask |= BIT_ULL(power_domain);
10487
10488                 /*
10489                  * The PLL needs to be enabled with a valid divider
10490                  * configuration, otherwise accessing DSI registers will hang
10491                  * the machine. See BSpec North Display Engine
10492                  * registers/MIPI[BXT]. We can break out here early, since we
10493                  * need the same DSI PLL to be enabled for both DSI ports.
10494                  */
10495                 if (!bxt_dsi_pll_is_enabled(dev_priv))
10496                         break;
10497
10498                 /* XXX: this works for video mode only */
10499                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10500                 if (!(tmp & DPI_ENABLE))
10501                         continue;
10502
10503                 tmp = I915_READ(MIPI_CTRL(port));
10504                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10505                         continue;
10506
10507                 pipe_config->cpu_transcoder = cpu_transcoder;
10508                 break;
10509         }
10510
10511         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10512 }
10513
10514 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10515                                        struct intel_crtc_state *pipe_config)
10516 {
10517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10518         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
10519         struct intel_shared_dpll *pll;
10520         enum port port;
10521         u32 tmp;
10522
10523         if (transcoder_is_dsi(cpu_transcoder)) {
10524                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
10525                                                 PORT_A : PORT_B;
10526         } else {
10527                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
10528                 if (INTEL_GEN(dev_priv) >= 12)
10529                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10530                 else
10531                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10532         }
10533
10534         if (INTEL_GEN(dev_priv) >= 11)
10535                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10536         else if (IS_CANNONLAKE(dev_priv))
10537                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10538         else if (IS_GEN9_BC(dev_priv))
10539                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10540         else if (IS_GEN9_LP(dev_priv))
10541                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10542         else
10543                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10544
10545         pll = pipe_config->shared_dpll;
10546         if (pll) {
10547                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10548                                                 &pipe_config->dpll_hw_state));
10549         }
10550
10551         /*
10552          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10553          * DDI E. So just check whether this pipe is wired to DDI E and whether
10554          * the PCH transcoder is on.
10555          */
10556         if (INTEL_GEN(dev_priv) < 9 &&
10557             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10558                 pipe_config->has_pch_encoder = true;
10559
10560                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10561                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10562                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10563
10564                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10565         }
10566 }
10567
10568 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
10569                                                  enum transcoder cpu_transcoder)
10570 {
10571         u32 trans_port_sync, master_select;
10572
10573         trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
10574
10575         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
10576                 return INVALID_TRANSCODER;
10577
10578         master_select = trans_port_sync &
10579                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
10580         if (master_select == 0)
10581                 return TRANSCODER_EDP;
10582         else
10583                 return master_select - 1;
10584 }
10585
10586 static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
10587 {
10588         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
10589         u32 transcoders;
10590         enum transcoder cpu_transcoder;
10591
10592         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
10593                                                                   crtc_state->cpu_transcoder);
10594
10595         transcoders = BIT(TRANSCODER_A) |
10596                 BIT(TRANSCODER_B) |
10597                 BIT(TRANSCODER_C) |
10598                 BIT(TRANSCODER_D);
10599         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
10600                 enum intel_display_power_domain power_domain;
10601                 intel_wakeref_t trans_wakeref;
10602
10603                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10604                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
10605                                                                    power_domain);
10606
10607                 if (!trans_wakeref)
10608                         continue;
10609
10610                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
10611                     crtc_state->cpu_transcoder)
10612                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
10613
10614                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
10615         }
10616
10617         WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
10618                 crtc_state->sync_mode_slaves_mask);
10619 }
10620
10621 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10622                                     struct intel_crtc_state *pipe_config)
10623 {
10624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10625         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10626         enum intel_display_power_domain power_domain;
10627         u64 power_domain_mask;
10628         bool active;
10629
10630         intel_crtc_init_scalers(crtc, pipe_config);
10631
10632         pipe_config->master_transcoder = INVALID_TRANSCODER;
10633
10634         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10635         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10636         if (!wf)
10637                 return false;
10638
10639         wakerefs[power_domain] = wf;
10640         power_domain_mask = BIT_ULL(power_domain);
10641
10642         pipe_config->shared_dpll = NULL;
10643
10644         active = hsw_get_transcoder_state(crtc, pipe_config,
10645                                           &power_domain_mask, wakerefs);
10646
10647         if (IS_GEN9_LP(dev_priv) &&
10648             bxt_get_dsi_transcoder_state(crtc, pipe_config,
10649                                          &power_domain_mask, wakerefs)) {
10650                 WARN_ON(active);
10651                 active = true;
10652         }
10653
10654         if (!active)
10655                 goto out;
10656
10657         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10658             INTEL_GEN(dev_priv) >= 11) {
10659                 haswell_get_ddi_port_state(crtc, pipe_config);
10660                 intel_get_pipe_timings(crtc, pipe_config);
10661         }
10662
10663         intel_get_pipe_src_size(crtc, pipe_config);
10664
10665         if (IS_HASWELL(dev_priv)) {
10666                 u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10667
10668                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
10669                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10670                 else
10671                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10672         } else {
10673                 pipe_config->output_format =
10674                         bdw_get_pipemisc_output_format(crtc);
10675
10676                 /*
10677                  * Currently there is no interface defined to
10678                  * check user preference between RGB/YCBCR444
10679                  * or YCBCR420. So the only possible case for
10680                  * YCBCR444 usage is driving YCBCR420 output
10681                  * with LSPCON, when pipe is configured for
10682                  * YCBCR444 output and LSPCON takes care of
10683                  * downsampling it.
10684                  */
10685                 pipe_config->lspcon_downsampling =
10686                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
10687         }
10688
10689         pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10690
10691         pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10692
10693         if (INTEL_GEN(dev_priv) >= 9) {
10694                 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10695
10696                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10697                         pipe_config->gamma_enable = true;
10698
10699                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10700                         pipe_config->csc_enable = true;
10701         } else {
10702                 i9xx_get_pipe_color_config(pipe_config);
10703         }
10704
10705         intel_color_get_config(pipe_config);
10706
10707         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10708         WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10709
10710         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10711         if (wf) {
10712                 wakerefs[power_domain] = wf;
10713                 power_domain_mask |= BIT_ULL(power_domain);
10714
10715                 if (INTEL_GEN(dev_priv) >= 9)
10716                         skylake_get_pfit_config(crtc, pipe_config);
10717                 else
10718                         ironlake_get_pfit_config(crtc, pipe_config);
10719         }
10720
10721         if (hsw_crtc_supports_ips(crtc)) {
10722                 if (IS_HASWELL(dev_priv))
10723                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10724                 else {
10725                         /*
10726                          * We cannot readout IPS state on broadwell, set to
10727                          * true so we can set it to a defined state on first
10728                          * commit.
10729                          */
10730                         pipe_config->ips_enabled = true;
10731                 }
10732         }
10733
10734         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10735             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10736                 pipe_config->pixel_multiplier =
10737                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10738         } else {
10739                 pipe_config->pixel_multiplier = 1;
10740         }
10741
10742         if (INTEL_GEN(dev_priv) >= 11 &&
10743             !transcoder_is_dsi(pipe_config->cpu_transcoder))
10744                 icelake_get_trans_port_sync_config(pipe_config);
10745
10746 out:
10747         for_each_power_domain(power_domain, power_domain_mask)
10748                 intel_display_power_put(dev_priv,
10749                                         power_domain, wakerefs[power_domain]);
10750
10751         return active;
10752 }
10753
10754 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10755 {
10756         struct drm_i915_private *dev_priv =
10757                 to_i915(plane_state->uapi.plane->dev);
10758         const struct drm_framebuffer *fb = plane_state->hw.fb;
10759         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10760         u32 base;
10761
10762         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10763                 base = obj->phys_handle->busaddr;
10764         else
10765                 base = intel_plane_ggtt_offset(plane_state);
10766
10767         return base + plane_state->color_plane[0].offset;
10768 }
10769
10770 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10771 {
10772         int x = plane_state->uapi.dst.x1;
10773         int y = plane_state->uapi.dst.y1;
10774         u32 pos = 0;
10775
10776         if (x < 0) {
10777                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10778                 x = -x;
10779         }
10780         pos |= x << CURSOR_X_SHIFT;
10781
10782         if (y < 0) {
10783                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10784                 y = -y;
10785         }
10786         pos |= y << CURSOR_Y_SHIFT;
10787
10788         return pos;
10789 }
10790
10791 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10792 {
10793         const struct drm_mode_config *config =
10794                 &plane_state->uapi.plane->dev->mode_config;
10795         int width = drm_rect_width(&plane_state->uapi.dst);
10796         int height = drm_rect_height(&plane_state->uapi.dst);
10797
10798         return width > 0 && width <= config->cursor_width &&
10799                 height > 0 && height <= config->cursor_height;
10800 }
10801
10802 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10803 {
10804         struct drm_i915_private *dev_priv =
10805                 to_i915(plane_state->uapi.plane->dev);
10806         unsigned int rotation = plane_state->hw.rotation;
10807         int src_x, src_y;
10808         u32 offset;
10809         int ret;
10810
10811         ret = intel_plane_compute_gtt(plane_state);
10812         if (ret)
10813                 return ret;
10814
10815         if (!plane_state->uapi.visible)
10816                 return 0;
10817
10818         src_x = plane_state->uapi.src.x1 >> 16;
10819         src_y = plane_state->uapi.src.y1 >> 16;
10820
10821         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10822         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10823                                                     plane_state, 0);
10824
10825         if (src_x != 0 || src_y != 0) {
10826                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10827                 return -EINVAL;
10828         }
10829
10830         /*
10831          * Put the final coordinates back so that the src
10832          * coordinate checks will see the right values.
10833          */
10834         drm_rect_translate_to(&plane_state->uapi.src,
10835                               src_x << 16, src_y << 16);
10836
10837         /* ILK+ do this automagically in hardware */
10838         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
10839                 const struct drm_framebuffer *fb = plane_state->hw.fb;
10840                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
10841                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
10842
10843                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
10844         }
10845
10846         plane_state->color_plane[0].offset = offset;
10847         plane_state->color_plane[0].x = src_x;
10848         plane_state->color_plane[0].y = src_y;
10849
10850         return 0;
10851 }
10852
10853 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10854                               struct intel_plane_state *plane_state)
10855 {
10856         const struct drm_framebuffer *fb = plane_state->hw.fb;
10857         int ret;
10858
10859         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10860                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10861                 return -EINVAL;
10862         }
10863
10864         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
10865                                                   &crtc_state->uapi,
10866                                                   DRM_PLANE_HELPER_NO_SCALING,
10867                                                   DRM_PLANE_HELPER_NO_SCALING,
10868                                                   true, true);
10869         if (ret)
10870                 return ret;
10871
10872         /* Use the unclipped src/dst rectangles, which we program to hw */
10873         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
10874         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
10875
10876         ret = intel_cursor_check_surface(plane_state);
10877         if (ret)
10878                 return ret;
10879
10880         if (!plane_state->uapi.visible)
10881                 return 0;
10882
10883         ret = intel_plane_check_src_coordinates(plane_state);
10884         if (ret)
10885                 return ret;
10886
10887         return 0;
10888 }
10889
10890 static unsigned int
10891 i845_cursor_max_stride(struct intel_plane *plane,
10892                        u32 pixel_format, u64 modifier,
10893                        unsigned int rotation)
10894 {
10895         return 2048;
10896 }
10897
10898 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10899 {
10900         u32 cntl = 0;
10901
10902         if (crtc_state->gamma_enable)
10903                 cntl |= CURSOR_GAMMA_ENABLE;
10904
10905         return cntl;
10906 }
10907
10908 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10909                            const struct intel_plane_state *plane_state)
10910 {
10911         return CURSOR_ENABLE |
10912                 CURSOR_FORMAT_ARGB |
10913                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10914 }
10915
10916 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10917 {
10918         int width = drm_rect_width(&plane_state->uapi.dst);
10919
10920         /*
10921          * 845g/865g are only limited by the width of their cursors,
10922          * the height is arbitrary up to the precision of the register.
10923          */
10924         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10925 }
10926
10927 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10928                              struct intel_plane_state *plane_state)
10929 {
10930         const struct drm_framebuffer *fb = plane_state->hw.fb;
10931         int ret;
10932
10933         ret = intel_check_cursor(crtc_state, plane_state);
10934         if (ret)
10935                 return ret;
10936
10937         /* if we want to turn off the cursor ignore width and height */
10938         if (!fb)
10939                 return 0;
10940
10941         /* Check for which cursor types we support */
10942         if (!i845_cursor_size_ok(plane_state)) {
10943                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10944                           drm_rect_width(&plane_state->uapi.dst),
10945                           drm_rect_height(&plane_state->uapi.dst));
10946                 return -EINVAL;
10947         }
10948
10949         WARN_ON(plane_state->uapi.visible &&
10950                 plane_state->color_plane[0].stride != fb->pitches[0]);
10951
10952         switch (fb->pitches[0]) {
10953         case 256:
10954         case 512:
10955         case 1024:
10956         case 2048:
10957                 break;
10958         default:
10959                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10960                               fb->pitches[0]);
10961                 return -EINVAL;
10962         }
10963
10964         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10965
10966         return 0;
10967 }
10968
10969 static void i845_update_cursor(struct intel_plane *plane,
10970                                const struct intel_crtc_state *crtc_state,
10971                                const struct intel_plane_state *plane_state)
10972 {
10973         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10974         u32 cntl = 0, base = 0, pos = 0, size = 0;
10975         unsigned long irqflags;
10976
10977         if (plane_state && plane_state->uapi.visible) {
10978                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
10979                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
10980
10981                 cntl = plane_state->ctl |
10982                         i845_cursor_ctl_crtc(crtc_state);
10983
10984                 size = (height << 12) | width;
10985
10986                 base = intel_cursor_base(plane_state);
10987                 pos = intel_cursor_position(plane_state);
10988         }
10989
10990         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10991
10992         /* On these chipsets we can only modify the base/size/stride
10993          * whilst the cursor is disabled.
10994          */
10995         if (plane->cursor.base != base ||
10996             plane->cursor.size != size ||
10997             plane->cursor.cntl != cntl) {
10998                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10999                 I915_WRITE_FW(CURBASE(PIPE_A), base);
11000                 I915_WRITE_FW(CURSIZE, size);
11001                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11002                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11003
11004                 plane->cursor.base = base;
11005                 plane->cursor.size = size;
11006                 plane->cursor.cntl = cntl;
11007         } else {
11008                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
11009         }
11010
11011         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11012 }
11013
11014 static void i845_disable_cursor(struct intel_plane *plane,
11015                                 const struct intel_crtc_state *crtc_state)
11016 {
11017         i845_update_cursor(plane, crtc_state, NULL);
11018 }
11019
11020 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11021                                      enum pipe *pipe)
11022 {
11023         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11024         enum intel_display_power_domain power_domain;
11025         intel_wakeref_t wakeref;
11026         bool ret;
11027
11028         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11029         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11030         if (!wakeref)
11031                 return false;
11032
11033         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11034
11035         *pipe = PIPE_A;
11036
11037         intel_display_power_put(dev_priv, power_domain, wakeref);
11038
11039         return ret;
11040 }
11041
11042 static unsigned int
11043 i9xx_cursor_max_stride(struct intel_plane *plane,
11044                        u32 pixel_format, u64 modifier,
11045                        unsigned int rotation)
11046 {
11047         return plane->base.dev->mode_config.cursor_width * 4;
11048 }
11049
11050 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11051 {
11052         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11053         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11054         u32 cntl = 0;
11055
11056         if (INTEL_GEN(dev_priv) >= 11)
11057                 return cntl;
11058
11059         if (crtc_state->gamma_enable)
11060                 cntl = MCURSOR_GAMMA_ENABLE;
11061
11062         if (crtc_state->csc_enable)
11063                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11064
11065         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11066                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11067
11068         return cntl;
11069 }
11070
11071 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11072                            const struct intel_plane_state *plane_state)
11073 {
11074         struct drm_i915_private *dev_priv =
11075                 to_i915(plane_state->uapi.plane->dev);
11076         u32 cntl = 0;
11077
11078         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11079                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11080
11081         switch (drm_rect_width(&plane_state->uapi.dst)) {
11082         case 64:
11083                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11084                 break;
11085         case 128:
11086                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11087                 break;
11088         case 256:
11089                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11090                 break;
11091         default:
11092                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11093                 return 0;
11094         }
11095
11096         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11097                 cntl |= MCURSOR_ROTATE_180;
11098
11099         return cntl;
11100 }
11101
11102 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11103 {
11104         struct drm_i915_private *dev_priv =
11105                 to_i915(plane_state->uapi.plane->dev);
11106         int width = drm_rect_width(&plane_state->uapi.dst);
11107         int height = drm_rect_height(&plane_state->uapi.dst);
11108
11109         if (!intel_cursor_size_ok(plane_state))
11110                 return false;
11111
11112         /* Cursor width is limited to a few power-of-two sizes */
11113         switch (width) {
11114         case 256:
11115         case 128:
11116         case 64:
11117                 break;
11118         default:
11119                 return false;
11120         }
11121
11122         /*
11123          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11124          * height from 8 lines up to the cursor width, when the
11125          * cursor is not rotated. Everything else requires square
11126          * cursors.
11127          */
11128         if (HAS_CUR_FBC(dev_priv) &&
11129             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11130                 if (height < 8 || height > width)
11131                         return false;
11132         } else {
11133                 if (height != width)
11134                         return false;
11135         }
11136
11137         return true;
11138 }
11139
11140 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11141                              struct intel_plane_state *plane_state)
11142 {
11143         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11144         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11145         const struct drm_framebuffer *fb = plane_state->hw.fb;
11146         enum pipe pipe = plane->pipe;
11147         int ret;
11148
11149         ret = intel_check_cursor(crtc_state, plane_state);
11150         if (ret)
11151                 return ret;
11152
11153         /* if we want to turn off the cursor ignore width and height */
11154         if (!fb)
11155                 return 0;
11156
11157         /* Check for which cursor types we support */
11158         if (!i9xx_cursor_size_ok(plane_state)) {
11159                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
11160                           drm_rect_width(&plane_state->uapi.dst),
11161                           drm_rect_height(&plane_state->uapi.dst));
11162                 return -EINVAL;
11163         }
11164
11165         WARN_ON(plane_state->uapi.visible &&
11166                 plane_state->color_plane[0].stride != fb->pitches[0]);
11167
11168         if (fb->pitches[0] !=
11169             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11170                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
11171                               fb->pitches[0],
11172                               drm_rect_width(&plane_state->uapi.dst));
11173                 return -EINVAL;
11174         }
11175
11176         /*
11177          * There's something wrong with the cursor on CHV pipe C.
11178          * If it straddles the left edge of the screen then
11179          * moving it away from the edge or disabling it often
11180          * results in a pipe underrun, and often that can lead to
11181          * dead pipe (constant underrun reported, and it scans
11182          * out just a solid color). To recover from that, the
11183          * display power well must be turned off and on again.
11184          * Refuse the put the cursor into that compromised position.
11185          */
11186         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11187             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11188                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
11189                 return -EINVAL;
11190         }
11191
11192         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11193
11194         return 0;
11195 }
11196
11197 static void i9xx_update_cursor(struct intel_plane *plane,
11198                                const struct intel_crtc_state *crtc_state,
11199                                const struct intel_plane_state *plane_state)
11200 {
11201         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11202         enum pipe pipe = plane->pipe;
11203         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11204         unsigned long irqflags;
11205
11206         if (plane_state && plane_state->uapi.visible) {
11207                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11208                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11209
11210                 cntl = plane_state->ctl |
11211                         i9xx_cursor_ctl_crtc(crtc_state);
11212
11213                 if (width != height)
11214                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11215
11216                 base = intel_cursor_base(plane_state);
11217                 pos = intel_cursor_position(plane_state);
11218         }
11219
11220         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11221
11222         /*
11223          * On some platforms writing CURCNTR first will also
11224          * cause CURPOS to be armed by the CURBASE write.
11225          * Without the CURCNTR write the CURPOS write would
11226          * arm itself. Thus we always update CURCNTR before
11227          * CURPOS.
11228          *
11229          * On other platforms CURPOS always requires the
11230          * CURBASE write to arm the update. Additonally
11231          * a write to any of the cursor register will cancel
11232          * an already armed cursor update. Thus leaving out
11233          * the CURBASE write after CURPOS could lead to a
11234          * cursor that doesn't appear to move, or even change
11235          * shape. Thus we always write CURBASE.
11236          *
11237          * The other registers are armed by by the CURBASE write
11238          * except when the plane is getting enabled at which time
11239          * the CURCNTR write arms the update.
11240          */
11241
11242         if (INTEL_GEN(dev_priv) >= 9)
11243                 skl_write_cursor_wm(plane, crtc_state);
11244
11245         if (plane->cursor.base != base ||
11246             plane->cursor.size != fbc_ctl ||
11247             plane->cursor.cntl != cntl) {
11248                 if (HAS_CUR_FBC(dev_priv))
11249                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
11250                 I915_WRITE_FW(CURCNTR(pipe), cntl);
11251                 I915_WRITE_FW(CURPOS(pipe), pos);
11252                 I915_WRITE_FW(CURBASE(pipe), base);
11253
11254                 plane->cursor.base = base;
11255                 plane->cursor.size = fbc_ctl;
11256                 plane->cursor.cntl = cntl;
11257         } else {
11258                 I915_WRITE_FW(CURPOS(pipe), pos);
11259                 I915_WRITE_FW(CURBASE(pipe), base);
11260         }
11261
11262         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11263 }
11264
11265 static void i9xx_disable_cursor(struct intel_plane *plane,
11266                                 const struct intel_crtc_state *crtc_state)
11267 {
11268         i9xx_update_cursor(plane, crtc_state, NULL);
11269 }
11270
11271 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11272                                      enum pipe *pipe)
11273 {
11274         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11275         enum intel_display_power_domain power_domain;
11276         intel_wakeref_t wakeref;
11277         bool ret;
11278         u32 val;
11279
11280         /*
11281          * Not 100% correct for planes that can move between pipes,
11282          * but that's only the case for gen2-3 which don't have any
11283          * display power wells.
11284          */
11285         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11286         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11287         if (!wakeref)
11288                 return false;
11289
11290         val = I915_READ(CURCNTR(plane->pipe));
11291
11292         ret = val & MCURSOR_MODE;
11293
11294         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11295                 *pipe = plane->pipe;
11296         else
11297                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11298                         MCURSOR_PIPE_SELECT_SHIFT;
11299
11300         intel_display_power_put(dev_priv, power_domain, wakeref);
11301
11302         return ret;
11303 }
11304
11305 /* VESA 640x480x72Hz mode to set on the pipe */
11306 static const struct drm_display_mode load_detect_mode = {
11307         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11308                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11309 };
11310
11311 struct drm_framebuffer *
11312 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11313                          struct drm_mode_fb_cmd2 *mode_cmd)
11314 {
11315         struct intel_framebuffer *intel_fb;
11316         int ret;
11317
11318         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11319         if (!intel_fb)
11320                 return ERR_PTR(-ENOMEM);
11321
11322         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11323         if (ret)
11324                 goto err;
11325
11326         return &intel_fb->base;
11327
11328 err:
11329         kfree(intel_fb);
11330         return ERR_PTR(ret);
11331 }
11332
11333 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11334                                         struct drm_crtc *crtc)
11335 {
11336         struct drm_plane *plane;
11337         struct drm_plane_state *plane_state;
11338         int ret, i;
11339
11340         ret = drm_atomic_add_affected_planes(state, crtc);
11341         if (ret)
11342                 return ret;
11343
11344         for_each_new_plane_in_state(state, plane, plane_state, i) {
11345                 if (plane_state->crtc != crtc)
11346                         continue;
11347
11348                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11349                 if (ret)
11350                         return ret;
11351
11352                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11353         }
11354
11355         return 0;
11356 }
11357
11358 int intel_get_load_detect_pipe(struct drm_connector *connector,
11359                                struct intel_load_detect_pipe *old,
11360                                struct drm_modeset_acquire_ctx *ctx)
11361 {
11362         struct intel_crtc *intel_crtc;
11363         struct intel_encoder *intel_encoder =
11364                 intel_attached_encoder(connector);
11365         struct drm_crtc *possible_crtc;
11366         struct drm_encoder *encoder = &intel_encoder->base;
11367         struct drm_crtc *crtc = NULL;
11368         struct drm_device *dev = encoder->dev;
11369         struct drm_i915_private *dev_priv = to_i915(dev);
11370         struct drm_mode_config *config = &dev->mode_config;
11371         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11372         struct drm_connector_state *connector_state;
11373         struct intel_crtc_state *crtc_state;
11374         int ret, i = -1;
11375
11376         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11377                       connector->base.id, connector->name,
11378                       encoder->base.id, encoder->name);
11379
11380         old->restore_state = NULL;
11381
11382         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11383
11384         /*
11385          * Algorithm gets a little messy:
11386          *
11387          *   - if the connector already has an assigned crtc, use it (but make
11388          *     sure it's on first)
11389          *
11390          *   - try to find the first unused crtc that can drive this connector,
11391          *     and use that if we find one
11392          */
11393
11394         /* See if we already have a CRTC for this connector */
11395         if (connector->state->crtc) {
11396                 crtc = connector->state->crtc;
11397
11398                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11399                 if (ret)
11400                         goto fail;
11401
11402                 /* Make sure the crtc and connector are running */
11403                 goto found;
11404         }
11405
11406         /* Find an unused one (if possible) */
11407         for_each_crtc(dev, possible_crtc) {
11408                 i++;
11409                 if (!(encoder->possible_crtcs & (1 << i)))
11410                         continue;
11411
11412                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11413                 if (ret)
11414                         goto fail;
11415
11416                 if (possible_crtc->state->enable) {
11417                         drm_modeset_unlock(&possible_crtc->mutex);
11418                         continue;
11419                 }
11420
11421                 crtc = possible_crtc;
11422                 break;
11423         }
11424
11425         /*
11426          * If we didn't find an unused CRTC, don't use any.
11427          */
11428         if (!crtc) {
11429                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11430                 ret = -ENODEV;
11431                 goto fail;
11432         }
11433
11434 found:
11435         intel_crtc = to_intel_crtc(crtc);
11436
11437         state = drm_atomic_state_alloc(dev);
11438         restore_state = drm_atomic_state_alloc(dev);
11439         if (!state || !restore_state) {
11440                 ret = -ENOMEM;
11441                 goto fail;
11442         }
11443
11444         state->acquire_ctx = ctx;
11445         restore_state->acquire_ctx = ctx;
11446
11447         connector_state = drm_atomic_get_connector_state(state, connector);
11448         if (IS_ERR(connector_state)) {
11449                 ret = PTR_ERR(connector_state);
11450                 goto fail;
11451         }
11452
11453         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11454         if (ret)
11455                 goto fail;
11456
11457         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11458         if (IS_ERR(crtc_state)) {
11459                 ret = PTR_ERR(crtc_state);
11460                 goto fail;
11461         }
11462
11463         crtc_state->uapi.active = true;
11464
11465         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
11466                                            &load_detect_mode);
11467         if (ret)
11468                 goto fail;
11469
11470         ret = intel_modeset_disable_planes(state, crtc);
11471         if (ret)
11472                 goto fail;
11473
11474         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11475         if (!ret)
11476                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11477         if (!ret)
11478                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11479         if (ret) {
11480                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11481                 goto fail;
11482         }
11483
11484         ret = drm_atomic_commit(state);
11485         if (ret) {
11486                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11487                 goto fail;
11488         }
11489
11490         old->restore_state = restore_state;
11491         drm_atomic_state_put(state);
11492
11493         /* let the connector get through one full cycle before testing */
11494         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11495         return true;
11496
11497 fail:
11498         if (state) {
11499                 drm_atomic_state_put(state);
11500                 state = NULL;
11501         }
11502         if (restore_state) {
11503                 drm_atomic_state_put(restore_state);
11504                 restore_state = NULL;
11505         }
11506
11507         if (ret == -EDEADLK)
11508                 return ret;
11509
11510         return false;
11511 }
11512
11513 void intel_release_load_detect_pipe(struct drm_connector *connector,
11514                                     struct intel_load_detect_pipe *old,
11515                                     struct drm_modeset_acquire_ctx *ctx)
11516 {
11517         struct intel_encoder *intel_encoder =
11518                 intel_attached_encoder(connector);
11519         struct drm_encoder *encoder = &intel_encoder->base;
11520         struct drm_atomic_state *state = old->restore_state;
11521         int ret;
11522
11523         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11524                       connector->base.id, connector->name,
11525                       encoder->base.id, encoder->name);
11526
11527         if (!state)
11528                 return;
11529
11530         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11531         if (ret)
11532                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11533         drm_atomic_state_put(state);
11534 }
11535
11536 static int i9xx_pll_refclk(struct drm_device *dev,
11537                            const struct intel_crtc_state *pipe_config)
11538 {
11539         struct drm_i915_private *dev_priv = to_i915(dev);
11540         u32 dpll = pipe_config->dpll_hw_state.dpll;
11541
11542         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11543                 return dev_priv->vbt.lvds_ssc_freq;
11544         else if (HAS_PCH_SPLIT(dev_priv))
11545                 return 120000;
11546         else if (!IS_GEN(dev_priv, 2))
11547                 return 96000;
11548         else
11549                 return 48000;
11550 }
11551
11552 /* Returns the clock of the currently programmed mode of the given pipe. */
11553 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11554                                 struct intel_crtc_state *pipe_config)
11555 {
11556         struct drm_device *dev = crtc->base.dev;
11557         struct drm_i915_private *dev_priv = to_i915(dev);
11558         enum pipe pipe = crtc->pipe;
11559         u32 dpll = pipe_config->dpll_hw_state.dpll;
11560         u32 fp;
11561         struct dpll clock;
11562         int port_clock;
11563         int refclk = i9xx_pll_refclk(dev, pipe_config);
11564
11565         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11566                 fp = pipe_config->dpll_hw_state.fp0;
11567         else
11568                 fp = pipe_config->dpll_hw_state.fp1;
11569
11570         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11571         if (IS_PINEVIEW(dev_priv)) {
11572                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11573                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11574         } else {
11575                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11576                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11577         }
11578
11579         if (!IS_GEN(dev_priv, 2)) {
11580                 if (IS_PINEVIEW(dev_priv))
11581                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11582                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11583                 else
11584                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11585                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11586
11587                 switch (dpll & DPLL_MODE_MASK) {
11588                 case DPLLB_MODE_DAC_SERIAL:
11589                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11590                                 5 : 10;
11591                         break;
11592                 case DPLLB_MODE_LVDS:
11593                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11594                                 7 : 14;
11595                         break;
11596                 default:
11597                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11598                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11599                         return;
11600                 }
11601
11602                 if (IS_PINEVIEW(dev_priv))
11603                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11604                 else
11605                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11606         } else {
11607                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11608                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11609
11610                 if (is_lvds) {
11611                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11612                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11613
11614                         if (lvds & LVDS_CLKB_POWER_UP)
11615                                 clock.p2 = 7;
11616                         else
11617                                 clock.p2 = 14;
11618                 } else {
11619                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11620                                 clock.p1 = 2;
11621                         else {
11622                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11623                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11624                         }
11625                         if (dpll & PLL_P2_DIVIDE_BY_4)
11626                                 clock.p2 = 4;
11627                         else
11628                                 clock.p2 = 2;
11629                 }
11630
11631                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11632         }
11633
11634         /*
11635          * This value includes pixel_multiplier. We will use
11636          * port_clock to compute adjusted_mode.crtc_clock in the
11637          * encoder's get_config() function.
11638          */
11639         pipe_config->port_clock = port_clock;
11640 }
11641
11642 int intel_dotclock_calculate(int link_freq,
11643                              const struct intel_link_m_n *m_n)
11644 {
11645         /*
11646          * The calculation for the data clock is:
11647          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11648          * But we want to avoid losing precison if possible, so:
11649          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11650          *
11651          * and the link clock is simpler:
11652          * link_clock = (m * link_clock) / n
11653          */
11654
11655         if (!m_n->link_n)
11656                 return 0;
11657
11658         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11659 }
11660
11661 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11662                                    struct intel_crtc_state *pipe_config)
11663 {
11664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11665
11666         /* read out port_clock from the DPLL */
11667         i9xx_crtc_clock_get(crtc, pipe_config);
11668
11669         /*
11670          * In case there is an active pipe without active ports,
11671          * we may need some idea for the dotclock anyway.
11672          * Calculate one based on the FDI configuration.
11673          */
11674         pipe_config->hw.adjusted_mode.crtc_clock =
11675                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11676                                          &pipe_config->fdi_m_n);
11677 }
11678
11679 /* Returns the currently programmed mode of the given encoder. */
11680 struct drm_display_mode *
11681 intel_encoder_current_mode(struct intel_encoder *encoder)
11682 {
11683         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11684         struct intel_crtc_state *crtc_state;
11685         struct drm_display_mode *mode;
11686         struct intel_crtc *crtc;
11687         enum pipe pipe;
11688
11689         if (!encoder->get_hw_state(encoder, &pipe))
11690                 return NULL;
11691
11692         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11693
11694         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11695         if (!mode)
11696                 return NULL;
11697
11698         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11699         if (!crtc_state) {
11700                 kfree(mode);
11701                 return NULL;
11702         }
11703
11704         crtc_state->uapi.crtc = &crtc->base;
11705
11706         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11707                 kfree(crtc_state);
11708                 kfree(mode);
11709                 return NULL;
11710         }
11711
11712         encoder->get_config(encoder, crtc_state);
11713
11714         intel_mode_from_pipe_config(mode, crtc_state);
11715
11716         kfree(crtc_state);
11717
11718         return mode;
11719 }
11720
11721 static void intel_crtc_destroy(struct drm_crtc *crtc)
11722 {
11723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11724
11725         drm_crtc_cleanup(crtc);
11726         kfree(intel_crtc);
11727 }
11728
11729 /**
11730  * intel_wm_need_update - Check whether watermarks need updating
11731  * @cur: current plane state
11732  * @new: new plane state
11733  *
11734  * Check current plane state versus the new one to determine whether
11735  * watermarks need to be recalculated.
11736  *
11737  * Returns true or false.
11738  */
11739 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11740                                  struct intel_plane_state *new)
11741 {
11742         /* Update watermarks on tiling or size changes. */
11743         if (new->uapi.visible != cur->uapi.visible)
11744                 return true;
11745
11746         if (!cur->hw.fb || !new->hw.fb)
11747                 return false;
11748
11749         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
11750             cur->hw.rotation != new->hw.rotation ||
11751             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
11752             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
11753             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
11754             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
11755                 return true;
11756
11757         return false;
11758 }
11759
11760 static bool needs_scaling(const struct intel_plane_state *state)
11761 {
11762         int src_w = drm_rect_width(&state->uapi.src) >> 16;
11763         int src_h = drm_rect_height(&state->uapi.src) >> 16;
11764         int dst_w = drm_rect_width(&state->uapi.dst);
11765         int dst_h = drm_rect_height(&state->uapi.dst);
11766
11767         return (src_w != dst_w || src_h != dst_h);
11768 }
11769
11770 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11771                                     struct intel_crtc_state *crtc_state,
11772                                     const struct intel_plane_state *old_plane_state,
11773                                     struct intel_plane_state *plane_state)
11774 {
11775         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11776         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11777         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11778         bool mode_changed = needs_modeset(crtc_state);
11779         bool was_crtc_enabled = old_crtc_state->hw.active;
11780         bool is_crtc_enabled = crtc_state->hw.active;
11781         bool turn_off, turn_on, visible, was_visible;
11782         int ret;
11783
11784         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11785                 ret = skl_update_scaler_plane(crtc_state, plane_state);
11786                 if (ret)
11787                         return ret;
11788         }
11789
11790         was_visible = old_plane_state->uapi.visible;
11791         visible = plane_state->uapi.visible;
11792
11793         if (!was_crtc_enabled && WARN_ON(was_visible))
11794                 was_visible = false;
11795
11796         /*
11797          * Visibility is calculated as if the crtc was on, but
11798          * after scaler setup everything depends on it being off
11799          * when the crtc isn't active.
11800          *
11801          * FIXME this is wrong for watermarks. Watermarks should also
11802          * be computed as if the pipe would be active. Perhaps move
11803          * per-plane wm computation to the .check_plane() hook, and
11804          * only combine the results from all planes in the current place?
11805          */
11806         if (!is_crtc_enabled) {
11807                 plane_state->uapi.visible = visible = false;
11808                 crtc_state->active_planes &= ~BIT(plane->id);
11809                 crtc_state->data_rate[plane->id] = 0;
11810                 crtc_state->min_cdclk[plane->id] = 0;
11811         }
11812
11813         if (!was_visible && !visible)
11814                 return 0;
11815
11816         turn_off = was_visible && (!visible || mode_changed);
11817         turn_on = visible && (!was_visible || mode_changed);
11818
11819         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11820                          crtc->base.base.id, crtc->base.name,
11821                          plane->base.base.id, plane->base.name,
11822                          was_visible, visible,
11823                          turn_off, turn_on, mode_changed);
11824
11825         if (turn_on) {
11826                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11827                         crtc_state->update_wm_pre = true;
11828
11829                 /* must disable cxsr around plane enable/disable */
11830                 if (plane->id != PLANE_CURSOR)
11831                         crtc_state->disable_cxsr = true;
11832         } else if (turn_off) {
11833                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11834                         crtc_state->update_wm_post = true;
11835
11836                 /* must disable cxsr around plane enable/disable */
11837                 if (plane->id != PLANE_CURSOR)
11838                         crtc_state->disable_cxsr = true;
11839         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11840                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11841                         /* FIXME bollocks */
11842                         crtc_state->update_wm_pre = true;
11843                         crtc_state->update_wm_post = true;
11844                 }
11845         }
11846
11847         if (visible || was_visible)
11848                 crtc_state->fb_bits |= plane->frontbuffer_bit;
11849
11850         /*
11851          * ILK/SNB DVSACNTR/Sprite Enable
11852          * IVB SPR_CTL/Sprite Enable
11853          * "When in Self Refresh Big FIFO mode, a write to enable the
11854          *  plane will be internally buffered and delayed while Big FIFO
11855          *  mode is exiting."
11856          *
11857          * Which means that enabling the sprite can take an extra frame
11858          * when we start in big FIFO mode (LP1+). Thus we need to drop
11859          * down to LP0 and wait for vblank in order to make sure the
11860          * sprite gets enabled on the next vblank after the register write.
11861          * Doing otherwise would risk enabling the sprite one frame after
11862          * we've already signalled flip completion. We can resume LP1+
11863          * once the sprite has been enabled.
11864          *
11865          *
11866          * WaCxSRDisabledForSpriteScaling:ivb
11867          * IVB SPR_SCALE/Scaling Enable
11868          * "Low Power watermarks must be disabled for at least one
11869          *  frame before enabling sprite scaling, and kept disabled
11870          *  until sprite scaling is disabled."
11871          *
11872          * ILK/SNB DVSASCALE/Scaling Enable
11873          * "When in Self Refresh Big FIFO mode, scaling enable will be
11874          *  masked off while Big FIFO mode is exiting."
11875          *
11876          * Despite the w/a only being listed for IVB we assume that
11877          * the ILK/SNB note has similar ramifications, hence we apply
11878          * the w/a on all three platforms.
11879          *
11880          * With experimental results seems this is needed also for primary
11881          * plane, not only sprite plane.
11882          */
11883         if (plane->id != PLANE_CURSOR &&
11884             (IS_GEN_RANGE(dev_priv, 5, 6) ||
11885              IS_IVYBRIDGE(dev_priv)) &&
11886             (turn_on || (!needs_scaling(old_plane_state) &&
11887                          needs_scaling(plane_state))))
11888                 crtc_state->disable_lp_wm = true;
11889
11890         return 0;
11891 }
11892
11893 static bool encoders_cloneable(const struct intel_encoder *a,
11894                                const struct intel_encoder *b)
11895 {
11896         /* masks could be asymmetric, so check both ways */
11897         return a == b || (a->cloneable & (1 << b->type) &&
11898                           b->cloneable & (1 << a->type));
11899 }
11900
11901 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11902                                          struct intel_crtc *crtc,
11903                                          struct intel_encoder *encoder)
11904 {
11905         struct intel_encoder *source_encoder;
11906         struct drm_connector *connector;
11907         struct drm_connector_state *connector_state;
11908         int i;
11909
11910         for_each_new_connector_in_state(state, connector, connector_state, i) {
11911                 if (connector_state->crtc != &crtc->base)
11912                         continue;
11913
11914                 source_encoder =
11915                         to_intel_encoder(connector_state->best_encoder);
11916                 if (!encoders_cloneable(encoder, source_encoder))
11917                         return false;
11918         }
11919
11920         return true;
11921 }
11922
11923 static int icl_add_linked_planes(struct intel_atomic_state *state)
11924 {
11925         struct intel_plane *plane, *linked;
11926         struct intel_plane_state *plane_state, *linked_plane_state;
11927         int i;
11928
11929         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11930                 linked = plane_state->planar_linked_plane;
11931
11932                 if (!linked)
11933                         continue;
11934
11935                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11936                 if (IS_ERR(linked_plane_state))
11937                         return PTR_ERR(linked_plane_state);
11938
11939                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
11940                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
11941         }
11942
11943         return 0;
11944 }
11945
11946 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11947 {
11948         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11949         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11950         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
11951         struct intel_plane *plane, *linked;
11952         struct intel_plane_state *plane_state;
11953         int i;
11954
11955         if (INTEL_GEN(dev_priv) < 11)
11956                 return 0;
11957
11958         /*
11959          * Destroy all old plane links and make the slave plane invisible
11960          * in the crtc_state->active_planes mask.
11961          */
11962         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11963                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
11964                         continue;
11965
11966                 plane_state->planar_linked_plane = NULL;
11967                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
11968                         crtc_state->active_planes &= ~BIT(plane->id);
11969                         crtc_state->update_planes |= BIT(plane->id);
11970                 }
11971
11972                 plane_state->planar_slave = false;
11973         }
11974
11975         if (!crtc_state->nv12_planes)
11976                 return 0;
11977
11978         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11979                 struct intel_plane_state *linked_state = NULL;
11980
11981                 if (plane->pipe != crtc->pipe ||
11982                     !(crtc_state->nv12_planes & BIT(plane->id)))
11983                         continue;
11984
11985                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11986                         if (!icl_is_nv12_y_plane(linked->id))
11987                                 continue;
11988
11989                         if (crtc_state->active_planes & BIT(linked->id))
11990                                 continue;
11991
11992                         linked_state = intel_atomic_get_plane_state(state, linked);
11993                         if (IS_ERR(linked_state))
11994                                 return PTR_ERR(linked_state);
11995
11996                         break;
11997                 }
11998
11999                 if (!linked_state) {
12000                         DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
12001                                       hweight8(crtc_state->nv12_planes));
12002
12003                         return -EINVAL;
12004                 }
12005
12006                 plane_state->planar_linked_plane = linked;
12007
12008                 linked_state->planar_slave = true;
12009                 linked_state->planar_linked_plane = plane;
12010                 crtc_state->active_planes |= BIT(linked->id);
12011                 crtc_state->update_planes |= BIT(linked->id);
12012                 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
12013
12014                 /* Copy parameters to slave plane */
12015                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12016                 linked_state->color_ctl = plane_state->color_ctl;
12017                 linked_state->color_plane[0] = plane_state->color_plane[0];
12018
12019                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12020                 linked_state->uapi.src = plane_state->uapi.src;
12021                 linked_state->uapi.dst = plane_state->uapi.dst;
12022
12023                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12024                         if (linked->id == PLANE_SPRITE5)
12025                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12026                         else if (linked->id == PLANE_SPRITE4)
12027                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12028                         else
12029                                 MISSING_CASE(linked->id);
12030                 }
12031         }
12032
12033         return 0;
12034 }
12035
12036 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12037 {
12038         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12039         struct intel_atomic_state *state =
12040                 to_intel_atomic_state(new_crtc_state->uapi.state);
12041         const struct intel_crtc_state *old_crtc_state =
12042                 intel_atomic_get_old_crtc_state(state, crtc);
12043
12044         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12045 }
12046
12047 static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
12048 {
12049         struct drm_crtc *crtc = crtc_state->uapi.crtc;
12050         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12051         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12052         struct drm_connector *master_connector, *connector;
12053         struct drm_connector_state *connector_state;
12054         struct drm_connector_list_iter conn_iter;
12055         struct drm_crtc *master_crtc = NULL;
12056         struct drm_crtc_state *master_crtc_state;
12057         struct intel_crtc_state *master_pipe_config;
12058         int i, tile_group_id;
12059
12060         if (INTEL_GEN(dev_priv) < 11)
12061                 return 0;
12062
12063         /*
12064          * In case of tiled displays there could be one or more slaves but there is
12065          * only one master. Lets make the CRTC used by the connector corresponding
12066          * to the last horizonal and last vertical tile a master/genlock CRTC.
12067          * All the other CRTCs corresponding to other tiles of the same Tile group
12068          * are the slave CRTCs and hold a pointer to their genlock CRTC.
12069          */
12070         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
12071                 if (connector_state->crtc != crtc)
12072                         continue;
12073                 if (!connector->has_tile)
12074                         continue;
12075                 if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
12076                     crtc_state->hw.mode.vdisplay != connector->tile_v_size)
12077                         return 0;
12078                 if (connector->tile_h_loc == connector->num_h_tile - 1 &&
12079                     connector->tile_v_loc == connector->num_v_tile - 1)
12080                         continue;
12081                 crtc_state->sync_mode_slaves_mask = 0;
12082                 tile_group_id = connector->tile_group->id;
12083                 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
12084                 drm_for_each_connector_iter(master_connector, &conn_iter) {
12085                         struct drm_connector_state *master_conn_state = NULL;
12086
12087                         if (!master_connector->has_tile)
12088                                 continue;
12089                         if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
12090                             master_connector->tile_v_loc != master_connector->num_v_tile - 1)
12091                                 continue;
12092                         if (master_connector->tile_group->id != tile_group_id)
12093                                 continue;
12094
12095                         master_conn_state = drm_atomic_get_connector_state(&state->base,
12096                                                                            master_connector);
12097                         if (IS_ERR(master_conn_state)) {
12098                                 drm_connector_list_iter_end(&conn_iter);
12099                                 return PTR_ERR(master_conn_state);
12100                         }
12101                         if (master_conn_state->crtc) {
12102                                 master_crtc = master_conn_state->crtc;
12103                                 break;
12104                         }
12105                 }
12106                 drm_connector_list_iter_end(&conn_iter);
12107
12108                 if (!master_crtc) {
12109                         DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
12110                                       connector_state->crtc->base.id);
12111                         return -EINVAL;
12112                 }
12113
12114                 master_crtc_state = drm_atomic_get_crtc_state(&state->base,
12115                                                               master_crtc);
12116                 if (IS_ERR(master_crtc_state))
12117                         return PTR_ERR(master_crtc_state);
12118
12119                 master_pipe_config = to_intel_crtc_state(master_crtc_state);
12120                 crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
12121                 master_pipe_config->sync_mode_slaves_mask |=
12122                         BIT(crtc_state->cpu_transcoder);
12123                 DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
12124                               transcoder_name(crtc_state->master_transcoder),
12125                               crtc_state->uapi.crtc->base.id,
12126                               master_pipe_config->sync_mode_slaves_mask);
12127         }
12128
12129         return 0;
12130 }
12131
12132 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12133                                    struct intel_crtc *crtc)
12134 {
12135         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12136         struct intel_crtc_state *crtc_state =
12137                 intel_atomic_get_new_crtc_state(state, crtc);
12138         bool mode_changed = needs_modeset(crtc_state);
12139         int ret;
12140
12141         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12142             mode_changed && !crtc_state->hw.active)
12143                 crtc_state->update_wm_post = true;
12144
12145         if (mode_changed && crtc_state->hw.enable &&
12146             dev_priv->display.crtc_compute_clock &&
12147             !WARN_ON(crtc_state->shared_dpll)) {
12148                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12149                 if (ret)
12150                         return ret;
12151         }
12152
12153         /*
12154          * May need to update pipe gamma enable bits
12155          * when C8 planes are getting enabled/disabled.
12156          */
12157         if (c8_planes_changed(crtc_state))
12158                 crtc_state->uapi.color_mgmt_changed = true;
12159
12160         if (mode_changed || crtc_state->update_pipe ||
12161             crtc_state->uapi.color_mgmt_changed) {
12162                 ret = intel_color_check(crtc_state);
12163                 if (ret)
12164                         return ret;
12165         }
12166
12167         ret = 0;
12168         if (dev_priv->display.compute_pipe_wm) {
12169                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12170                 if (ret) {
12171                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12172                         return ret;
12173                 }
12174         }
12175
12176         if (dev_priv->display.compute_intermediate_wm) {
12177                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12178                         return 0;
12179
12180                 /*
12181                  * Calculate 'intermediate' watermarks that satisfy both the
12182                  * old state and the new state.  We can program these
12183                  * immediately.
12184                  */
12185                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12186                 if (ret) {
12187                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12188                         return ret;
12189                 }
12190         }
12191
12192         if (INTEL_GEN(dev_priv) >= 9) {
12193                 if (mode_changed || crtc_state->update_pipe)
12194                         ret = skl_update_scaler_crtc(crtc_state);
12195                 if (!ret)
12196                         ret = intel_atomic_setup_scalers(dev_priv, crtc,
12197                                                          crtc_state);
12198         }
12199
12200         if (HAS_IPS(dev_priv))
12201                 crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
12202
12203         return ret;
12204 }
12205
12206 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12207 {
12208         struct intel_connector *connector;
12209         struct drm_connector_list_iter conn_iter;
12210
12211         drm_connector_list_iter_begin(dev, &conn_iter);
12212         for_each_intel_connector_iter(connector, &conn_iter) {
12213                 if (connector->base.state->crtc)
12214                         drm_connector_put(&connector->base);
12215
12216                 if (connector->base.encoder) {
12217                         connector->base.state->best_encoder =
12218                                 connector->base.encoder;
12219                         connector->base.state->crtc =
12220                                 connector->base.encoder->crtc;
12221
12222                         drm_connector_get(&connector->base);
12223                 } else {
12224                         connector->base.state->best_encoder = NULL;
12225                         connector->base.state->crtc = NULL;
12226                 }
12227         }
12228         drm_connector_list_iter_end(&conn_iter);
12229 }
12230
12231 static int
12232 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12233                       struct intel_crtc_state *pipe_config)
12234 {
12235         struct drm_connector *connector = conn_state->connector;
12236         const struct drm_display_info *info = &connector->display_info;
12237         int bpp;
12238
12239         switch (conn_state->max_bpc) {
12240         case 6 ... 7:
12241                 bpp = 6 * 3;
12242                 break;
12243         case 8 ... 9:
12244                 bpp = 8 * 3;
12245                 break;
12246         case 10 ... 11:
12247                 bpp = 10 * 3;
12248                 break;
12249         case 12:
12250                 bpp = 12 * 3;
12251                 break;
12252         default:
12253                 return -EINVAL;
12254         }
12255
12256         if (bpp < pipe_config->pipe_bpp) {
12257                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12258                               "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12259                               connector->base.id, connector->name,
12260                               bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
12261                               pipe_config->pipe_bpp);
12262
12263                 pipe_config->pipe_bpp = bpp;
12264         }
12265
12266         return 0;
12267 }
12268
12269 static int
12270 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12271                           struct intel_crtc_state *pipe_config)
12272 {
12273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12274         struct drm_atomic_state *state = pipe_config->uapi.state;
12275         struct drm_connector *connector;
12276         struct drm_connector_state *connector_state;
12277         int bpp, i;
12278
12279         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12280             IS_CHERRYVIEW(dev_priv)))
12281                 bpp = 10*3;
12282         else if (INTEL_GEN(dev_priv) >= 5)
12283                 bpp = 12*3;
12284         else
12285                 bpp = 8*3;
12286
12287         pipe_config->pipe_bpp = bpp;
12288
12289         /* Clamp display bpp to connector max bpp */
12290         for_each_new_connector_in_state(state, connector, connector_state, i) {
12291                 int ret;
12292
12293                 if (connector_state->crtc != &crtc->base)
12294                         continue;
12295
12296                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12297                 if (ret)
12298                         return ret;
12299         }
12300
12301         return 0;
12302 }
12303
12304 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12305 {
12306         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12307                       "type: 0x%x flags: 0x%x\n",
12308                       mode->crtc_clock,
12309                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12310                       mode->crtc_hsync_end, mode->crtc_htotal,
12311                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12312                       mode->crtc_vsync_end, mode->crtc_vtotal,
12313                       mode->type, mode->flags);
12314 }
12315
12316 static inline void
12317 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12318                       const char *id, unsigned int lane_count,
12319                       const struct intel_link_m_n *m_n)
12320 {
12321         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12322                       id, lane_count,
12323                       m_n->gmch_m, m_n->gmch_n,
12324                       m_n->link_m, m_n->link_n, m_n->tu);
12325 }
12326
12327 static void
12328 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12329                      const union hdmi_infoframe *frame)
12330 {
12331         if ((drm_debug & DRM_UT_KMS) == 0)
12332                 return;
12333
12334         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12335 }
12336
12337 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12338
12339 static const char * const output_type_str[] = {
12340         OUTPUT_TYPE(UNUSED),
12341         OUTPUT_TYPE(ANALOG),
12342         OUTPUT_TYPE(DVO),
12343         OUTPUT_TYPE(SDVO),
12344         OUTPUT_TYPE(LVDS),
12345         OUTPUT_TYPE(TVOUT),
12346         OUTPUT_TYPE(HDMI),
12347         OUTPUT_TYPE(DP),
12348         OUTPUT_TYPE(EDP),
12349         OUTPUT_TYPE(DSI),
12350         OUTPUT_TYPE(DDI),
12351         OUTPUT_TYPE(DP_MST),
12352 };
12353
12354 #undef OUTPUT_TYPE
12355
12356 static void snprintf_output_types(char *buf, size_t len,
12357                                   unsigned int output_types)
12358 {
12359         char *str = buf;
12360         int i;
12361
12362         str[0] = '\0';
12363
12364         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12365                 int r;
12366
12367                 if ((output_types & BIT(i)) == 0)
12368                         continue;
12369
12370                 r = snprintf(str, len, "%s%s",
12371                              str != buf ? "," : "", output_type_str[i]);
12372                 if (r >= len)
12373                         break;
12374                 str += r;
12375                 len -= r;
12376
12377                 output_types &= ~BIT(i);
12378         }
12379
12380         WARN_ON_ONCE(output_types != 0);
12381 }
12382
12383 static const char * const output_format_str[] = {
12384         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12385         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12386         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12387         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12388 };
12389
12390 static const char *output_formats(enum intel_output_format format)
12391 {
12392         if (format >= ARRAY_SIZE(output_format_str))
12393                 format = INTEL_OUTPUT_FORMAT_INVALID;
12394         return output_format_str[format];
12395 }
12396
12397 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12398 {
12399         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12400         const struct drm_framebuffer *fb = plane_state->hw.fb;
12401         struct drm_format_name_buf format_name;
12402
12403         if (!fb) {
12404                 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12405                               plane->base.base.id, plane->base.name,
12406                               yesno(plane_state->uapi.visible));
12407                 return;
12408         }
12409
12410         DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12411                       plane->base.base.id, plane->base.name,
12412                       fb->base.id, fb->width, fb->height,
12413                       drm_get_format_name(fb->format->format, &format_name),
12414                       yesno(plane_state->uapi.visible));
12415         DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12416                       plane_state->hw.rotation, plane_state->scaler_id);
12417         if (plane_state->uapi.visible)
12418                 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12419                               DRM_RECT_FP_ARG(&plane_state->uapi.src),
12420                               DRM_RECT_ARG(&plane_state->uapi.dst));
12421 }
12422
12423 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12424                                    struct intel_atomic_state *state,
12425                                    const char *context)
12426 {
12427         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12428         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12429         const struct intel_plane_state *plane_state;
12430         struct intel_plane *plane;
12431         char buf[64];
12432         int i;
12433
12434         DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12435                       crtc->base.base.id, crtc->base.name,
12436                       yesno(pipe_config->hw.enable), context);
12437
12438         if (!pipe_config->hw.enable)
12439                 goto dump_planes;
12440
12441         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12442         DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12443                       yesno(pipe_config->hw.active),
12444                       buf, pipe_config->output_types,
12445                       output_formats(pipe_config->output_format));
12446
12447         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12448                       transcoder_name(pipe_config->cpu_transcoder),
12449                       pipe_config->pipe_bpp, pipe_config->dither);
12450
12451         if (pipe_config->has_pch_encoder)
12452                 intel_dump_m_n_config(pipe_config, "fdi",
12453                                       pipe_config->fdi_lanes,
12454                                       &pipe_config->fdi_m_n);
12455
12456         if (intel_crtc_has_dp_encoder(pipe_config)) {
12457                 intel_dump_m_n_config(pipe_config, "dp m_n",
12458                                 pipe_config->lane_count, &pipe_config->dp_m_n);
12459                 if (pipe_config->has_drrs)
12460                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
12461                                               pipe_config->lane_count,
12462                                               &pipe_config->dp_m2_n2);
12463         }
12464
12465         DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12466                       pipe_config->has_audio, pipe_config->has_infoframe,
12467                       pipe_config->infoframes.enable);
12468
12469         if (pipe_config->infoframes.enable &
12470             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12471                 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12472         if (pipe_config->infoframes.enable &
12473             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12474                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12475         if (pipe_config->infoframes.enable &
12476             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12477                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12478         if (pipe_config->infoframes.enable &
12479             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12480                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12481
12482         DRM_DEBUG_KMS("requested mode:\n");
12483         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
12484         DRM_DEBUG_KMS("adjusted mode:\n");
12485         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
12486         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
12487         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12488                       pipe_config->port_clock,
12489                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12490                       pipe_config->pixel_rate);
12491
12492         if (INTEL_GEN(dev_priv) >= 9)
12493                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12494                               crtc->num_scalers,
12495                               pipe_config->scaler_state.scaler_users,
12496                               pipe_config->scaler_state.scaler_id);
12497
12498         if (HAS_GMCH(dev_priv))
12499                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12500                               pipe_config->gmch_pfit.control,
12501                               pipe_config->gmch_pfit.pgm_ratios,
12502                               pipe_config->gmch_pfit.lvds_border_bits);
12503         else
12504                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12505                               pipe_config->pch_pfit.pos,
12506                               pipe_config->pch_pfit.size,
12507                               enableddisabled(pipe_config->pch_pfit.enabled),
12508                               yesno(pipe_config->pch_pfit.force_thru));
12509
12510         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12511                       pipe_config->ips_enabled, pipe_config->double_wide);
12512
12513         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12514
12515         if (IS_CHERRYVIEW(dev_priv))
12516                 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12517                               pipe_config->cgm_mode, pipe_config->gamma_mode,
12518                               pipe_config->gamma_enable, pipe_config->csc_enable);
12519         else
12520                 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12521                               pipe_config->csc_mode, pipe_config->gamma_mode,
12522                               pipe_config->gamma_enable, pipe_config->csc_enable);
12523
12524 dump_planes:
12525         if (!state)
12526                 return;
12527
12528         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12529                 if (plane->pipe == crtc->pipe)
12530                         intel_dump_plane_state(plane_state);
12531         }
12532 }
12533
12534 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12535 {
12536         struct drm_device *dev = state->base.dev;
12537         struct drm_connector *connector;
12538         struct drm_connector_list_iter conn_iter;
12539         unsigned int used_ports = 0;
12540         unsigned int used_mst_ports = 0;
12541         bool ret = true;
12542
12543         /*
12544          * We're going to peek into connector->state,
12545          * hence connection_mutex must be held.
12546          */
12547         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
12548
12549         /*
12550          * Walk the connector list instead of the encoder
12551          * list to detect the problem on ddi platforms
12552          * where there's just one encoder per digital port.
12553          */
12554         drm_connector_list_iter_begin(dev, &conn_iter);
12555         drm_for_each_connector_iter(connector, &conn_iter) {
12556                 struct drm_connector_state *connector_state;
12557                 struct intel_encoder *encoder;
12558
12559                 connector_state =
12560                         drm_atomic_get_new_connector_state(&state->base,
12561                                                            connector);
12562                 if (!connector_state)
12563                         connector_state = connector->state;
12564
12565                 if (!connector_state->best_encoder)
12566                         continue;
12567
12568                 encoder = to_intel_encoder(connector_state->best_encoder);
12569
12570                 WARN_ON(!connector_state->crtc);
12571
12572                 switch (encoder->type) {
12573                         unsigned int port_mask;
12574                 case INTEL_OUTPUT_DDI:
12575                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
12576                                 break;
12577                         /* else, fall through */
12578                 case INTEL_OUTPUT_DP:
12579                 case INTEL_OUTPUT_HDMI:
12580                 case INTEL_OUTPUT_EDP:
12581                         port_mask = 1 << encoder->port;
12582
12583                         /* the same port mustn't appear more than once */
12584                         if (used_ports & port_mask)
12585                                 ret = false;
12586
12587                         used_ports |= port_mask;
12588                         break;
12589                 case INTEL_OUTPUT_DP_MST:
12590                         used_mst_ports |=
12591                                 1 << encoder->port;
12592                         break;
12593                 default:
12594                         break;
12595                 }
12596         }
12597         drm_connector_list_iter_end(&conn_iter);
12598
12599         /* can't mix MST and SST/HDMI on the same port */
12600         if (used_ports & used_mst_ports)
12601                 return false;
12602
12603         return ret;
12604 }
12605
12606 static void
12607 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
12608 {
12609         intel_crtc_copy_color_blobs(crtc_state);
12610 }
12611
12612 static void
12613 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
12614 {
12615         crtc_state->hw.enable = crtc_state->uapi.enable;
12616         crtc_state->hw.active = crtc_state->uapi.active;
12617         crtc_state->hw.mode = crtc_state->uapi.mode;
12618         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
12619         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
12620 }
12621
12622 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
12623 {
12624         crtc_state->uapi.enable = crtc_state->hw.enable;
12625         crtc_state->uapi.active = crtc_state->hw.active;
12626         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
12627
12628         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
12629
12630         /* copy color blobs to uapi */
12631         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
12632                                   crtc_state->hw.degamma_lut);
12633         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
12634                                   crtc_state->hw.gamma_lut);
12635         drm_property_replace_blob(&crtc_state->uapi.ctm,
12636                                   crtc_state->hw.ctm);
12637 }
12638
12639 static int
12640 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
12641 {
12642         struct drm_i915_private *dev_priv =
12643                 to_i915(crtc_state->uapi.crtc->dev);
12644         struct intel_crtc_state *saved_state;
12645
12646         saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12647         if (!saved_state)
12648                 return -ENOMEM;
12649
12650         /* free the old crtc_state->hw members */
12651         intel_crtc_free_hw_state(crtc_state);
12652
12653         /* FIXME: before the switch to atomic started, a new pipe_config was
12654          * kzalloc'd. Code that depends on any field being zero should be
12655          * fixed, so that the crtc_state can be safely duplicated. For now,
12656          * only fields that are know to not cause problems are preserved. */
12657
12658         saved_state->uapi = crtc_state->uapi;
12659         saved_state->scaler_state = crtc_state->scaler_state;
12660         saved_state->shared_dpll = crtc_state->shared_dpll;
12661         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12662         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12663                sizeof(saved_state->icl_port_dplls));
12664         saved_state->crc_enabled = crtc_state->crc_enabled;
12665         if (IS_G4X(dev_priv) ||
12666             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12667                 saved_state->wm = crtc_state->wm;
12668         /*
12669          * Save the slave bitmask which gets filled for master crtc state during
12670          * slave atomic check call.
12671          */
12672         if (is_trans_port_sync_master(crtc_state))
12673                 saved_state->sync_mode_slaves_mask =
12674                         crtc_state->sync_mode_slaves_mask;
12675
12676         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
12677         kfree(saved_state);
12678
12679         intel_crtc_copy_uapi_to_hw_state(crtc_state);
12680
12681         return 0;
12682 }
12683
12684 static int
12685 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12686 {
12687         struct drm_crtc *crtc = pipe_config->uapi.crtc;
12688         struct drm_atomic_state *state = pipe_config->uapi.state;
12689         struct intel_encoder *encoder;
12690         struct drm_connector *connector;
12691         struct drm_connector_state *connector_state;
12692         int base_bpp, ret;
12693         int i;
12694         bool retry = true;
12695
12696         pipe_config->cpu_transcoder =
12697                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12698
12699         /*
12700          * Sanitize sync polarity flags based on requested ones. If neither
12701          * positive or negative polarity is requested, treat this as meaning
12702          * negative polarity.
12703          */
12704         if (!(pipe_config->hw.adjusted_mode.flags &
12705               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12706                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12707
12708         if (!(pipe_config->hw.adjusted_mode.flags &
12709               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12710                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12711
12712         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12713                                         pipe_config);
12714         if (ret)
12715                 return ret;
12716
12717         base_bpp = pipe_config->pipe_bpp;
12718
12719         /*
12720          * Determine the real pipe dimensions. Note that stereo modes can
12721          * increase the actual pipe size due to the frame doubling and
12722          * insertion of additional space for blanks between the frame. This
12723          * is stored in the crtc timings. We use the requested mode to do this
12724          * computation to clearly distinguish it from the adjusted mode, which
12725          * can be changed by the connectors in the below retry loop.
12726          */
12727         drm_mode_get_hv_timing(&pipe_config->hw.mode,
12728                                &pipe_config->pipe_src_w,
12729                                &pipe_config->pipe_src_h);
12730
12731         for_each_new_connector_in_state(state, connector, connector_state, i) {
12732                 if (connector_state->crtc != crtc)
12733                         continue;
12734
12735                 encoder = to_intel_encoder(connector_state->best_encoder);
12736
12737                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12738                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12739                         return -EINVAL;
12740                 }
12741
12742                 /*
12743                  * Determine output_types before calling the .compute_config()
12744                  * hooks so that the hooks can use this information safely.
12745                  */
12746                 if (encoder->compute_output_type)
12747                         pipe_config->output_types |=
12748                                 BIT(encoder->compute_output_type(encoder, pipe_config,
12749                                                                  connector_state));
12750                 else
12751                         pipe_config->output_types |= BIT(encoder->type);
12752         }
12753
12754 encoder_retry:
12755         /* Ensure the port clock defaults are reset when retrying. */
12756         pipe_config->port_clock = 0;
12757         pipe_config->pixel_multiplier = 1;
12758
12759         /* Fill in default crtc timings, allow encoders to overwrite them. */
12760         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
12761                               CRTC_STEREO_DOUBLE);
12762
12763         /* Set the crtc_state defaults for trans_port_sync */
12764         pipe_config->master_transcoder = INVALID_TRANSCODER;
12765         ret = icl_add_sync_mode_crtcs(pipe_config);
12766         if (ret) {
12767                 DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
12768                               ret);
12769                 return ret;
12770         }
12771
12772         /* Pass our mode to the connectors and the CRTC to give them a chance to
12773          * adjust it according to limitations or connector properties, and also
12774          * a chance to reject the mode entirely.
12775          */
12776         for_each_new_connector_in_state(state, connector, connector_state, i) {
12777                 if (connector_state->crtc != crtc)
12778                         continue;
12779
12780                 encoder = to_intel_encoder(connector_state->best_encoder);
12781                 ret = encoder->compute_config(encoder, pipe_config,
12782                                               connector_state);
12783                 if (ret < 0) {
12784                         if (ret != -EDEADLK)
12785                                 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12786                                               ret);
12787                         return ret;
12788                 }
12789         }
12790
12791         /* Set default port clock if not overwritten by the encoder. Needs to be
12792          * done afterwards in case the encoder adjusts the mode. */
12793         if (!pipe_config->port_clock)
12794                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
12795                         * pipe_config->pixel_multiplier;
12796
12797         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12798         if (ret == -EDEADLK)
12799                 return ret;
12800         if (ret < 0) {
12801                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12802                 return ret;
12803         }
12804
12805         if (ret == RETRY) {
12806                 if (WARN(!retry, "loop in pipe configuration computation\n"))
12807                         return -EINVAL;
12808
12809                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12810                 retry = false;
12811                 goto encoder_retry;
12812         }
12813
12814         /* Dithering seems to not pass-through bits correctly when it should, so
12815          * only enable it on 6bpc panels and when its not a compliance
12816          * test requesting 6bpc video pattern.
12817          */
12818         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12819                 !pipe_config->dither_force_disable;
12820         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12821                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12822
12823         /*
12824          * Make drm_calc_timestamping_constants in
12825          * drm_atomic_helper_update_legacy_modeset_state() happy
12826          */
12827         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
12828
12829         return 0;
12830 }
12831
12832 bool intel_fuzzy_clock_check(int clock1, int clock2)
12833 {
12834         int diff;
12835
12836         if (clock1 == clock2)
12837                 return true;
12838
12839         if (!clock1 || !clock2)
12840                 return false;
12841
12842         diff = abs(clock1 - clock2);
12843
12844         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12845                 return true;
12846
12847         return false;
12848 }
12849
12850 static bool
12851 intel_compare_m_n(unsigned int m, unsigned int n,
12852                   unsigned int m2, unsigned int n2,
12853                   bool exact)
12854 {
12855         if (m == m2 && n == n2)
12856                 return true;
12857
12858         if (exact || !m || !n || !m2 || !n2)
12859                 return false;
12860
12861         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12862
12863         if (n > n2) {
12864                 while (n > n2) {
12865                         m2 <<= 1;
12866                         n2 <<= 1;
12867                 }
12868         } else if (n < n2) {
12869                 while (n < n2) {
12870                         m <<= 1;
12871                         n <<= 1;
12872                 }
12873         }
12874
12875         if (n != n2)
12876                 return false;
12877
12878         return intel_fuzzy_clock_check(m, m2);
12879 }
12880
12881 static bool
12882 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12883                        const struct intel_link_m_n *m2_n2,
12884                        bool exact)
12885 {
12886         return m_n->tu == m2_n2->tu &&
12887                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12888                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12889                 intel_compare_m_n(m_n->link_m, m_n->link_n,
12890                                   m2_n2->link_m, m2_n2->link_n, exact);
12891 }
12892
12893 static bool
12894 intel_compare_infoframe(const union hdmi_infoframe *a,
12895                         const union hdmi_infoframe *b)
12896 {
12897         return memcmp(a, b, sizeof(*a)) == 0;
12898 }
12899
12900 static void
12901 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12902                                bool fastset, const char *name,
12903                                const union hdmi_infoframe *a,
12904                                const union hdmi_infoframe *b)
12905 {
12906         if (fastset) {
12907                 if ((drm_debug & DRM_UT_KMS) == 0)
12908                         return;
12909
12910                 DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name);
12911                 DRM_DEBUG_KMS("expected:\n");
12912                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12913                 DRM_DEBUG_KMS("found:\n");
12914                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12915         } else {
12916                 DRM_ERROR("mismatch in %s infoframe\n", name);
12917                 DRM_ERROR("expected:\n");
12918                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12919                 DRM_ERROR("found:\n");
12920                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12921         }
12922 }
12923
12924 static void __printf(4, 5)
12925 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
12926                      const char *name, const char *format, ...)
12927 {
12928         struct va_format vaf;
12929         va_list args;
12930
12931         va_start(args, format);
12932         vaf.fmt = format;
12933         vaf.va = &args;
12934
12935         if (fastset)
12936                 DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n",
12937                               crtc->base.base.id, crtc->base.name, name, &vaf);
12938         else
12939                 DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n",
12940                           crtc->base.base.id, crtc->base.name, name, &vaf);
12941
12942         va_end(args);
12943 }
12944
12945 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12946 {
12947         if (i915_modparams.fastboot != -1)
12948                 return i915_modparams.fastboot;
12949
12950         /* Enable fastboot by default on Skylake and newer */
12951         if (INTEL_GEN(dev_priv) >= 9)
12952                 return true;
12953
12954         /* Enable fastboot by default on VLV and CHV */
12955         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12956                 return true;
12957
12958         /* Disabled by default on all others */
12959         return false;
12960 }
12961
12962 static bool
12963 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12964                           const struct intel_crtc_state *pipe_config,
12965                           bool fastset)
12966 {
12967         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
12968         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
12969         bool ret = true;
12970         u32 bp_gamma = 0;
12971         bool fixup_inherited = fastset &&
12972                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12973                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
12974
12975         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12976                 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12977                 ret = false;
12978         }
12979
12980 #define PIPE_CONF_CHECK_X(name) do { \
12981         if (current_config->name != pipe_config->name) { \
12982                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12983                                      "(expected 0x%08x, found 0x%08x)", \
12984                                      current_config->name, \
12985                                      pipe_config->name); \
12986                 ret = false; \
12987         } \
12988 } while (0)
12989
12990 #define PIPE_CONF_CHECK_I(name) do { \
12991         if (current_config->name != pipe_config->name) { \
12992                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
12993                                      "(expected %i, found %i)", \
12994                                      current_config->name, \
12995                                      pipe_config->name); \
12996                 ret = false; \
12997         } \
12998 } while (0)
12999
13000 #define PIPE_CONF_CHECK_BOOL(name) do { \
13001         if (current_config->name != pipe_config->name) { \
13002                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13003                                      "(expected %s, found %s)", \
13004                                      yesno(current_config->name), \
13005                                      yesno(pipe_config->name)); \
13006                 ret = false; \
13007         } \
13008 } while (0)
13009
13010 /*
13011  * Checks state where we only read out the enabling, but not the entire
13012  * state itself (like full infoframes or ELD for audio). These states
13013  * require a full modeset on bootup to fix up.
13014  */
13015 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13016         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13017                 PIPE_CONF_CHECK_BOOL(name); \
13018         } else { \
13019                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13020                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13021                                      yesno(current_config->name), \
13022                                      yesno(pipe_config->name)); \
13023                 ret = false; \
13024         } \
13025 } while (0)
13026
13027 #define PIPE_CONF_CHECK_P(name) do { \
13028         if (current_config->name != pipe_config->name) { \
13029                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13030                                      "(expected %p, found %p)", \
13031                                      current_config->name, \
13032                                      pipe_config->name); \
13033                 ret = false; \
13034         } \
13035 } while (0)
13036
13037 #define PIPE_CONF_CHECK_M_N(name) do { \
13038         if (!intel_compare_link_m_n(&current_config->name, \
13039                                     &pipe_config->name,\
13040                                     !fastset)) { \
13041                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13042                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13043                                      "found tu %i, gmch %i/%i link %i/%i)", \
13044                                      current_config->name.tu, \
13045                                      current_config->name.gmch_m, \
13046                                      current_config->name.gmch_n, \
13047                                      current_config->name.link_m, \
13048                                      current_config->name.link_n, \
13049                                      pipe_config->name.tu, \
13050                                      pipe_config->name.gmch_m, \
13051                                      pipe_config->name.gmch_n, \
13052                                      pipe_config->name.link_m, \
13053                                      pipe_config->name.link_n); \
13054                 ret = false; \
13055         } \
13056 } while (0)
13057
13058 /* This is required for BDW+ where there is only one set of registers for
13059  * switching between high and low RR.
13060  * This macro can be used whenever a comparison has to be made between one
13061  * hw state and multiple sw state variables.
13062  */
13063 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13064         if (!intel_compare_link_m_n(&current_config->name, \
13065                                     &pipe_config->name, !fastset) && \
13066             !intel_compare_link_m_n(&current_config->alt_name, \
13067                                     &pipe_config->name, !fastset)) { \
13068                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13069                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13070                                      "or tu %i gmch %i/%i link %i/%i, " \
13071                                      "found tu %i, gmch %i/%i link %i/%i)", \
13072                                      current_config->name.tu, \
13073                                      current_config->name.gmch_m, \
13074                                      current_config->name.gmch_n, \
13075                                      current_config->name.link_m, \
13076                                      current_config->name.link_n, \
13077                                      current_config->alt_name.tu, \
13078                                      current_config->alt_name.gmch_m, \
13079                                      current_config->alt_name.gmch_n, \
13080                                      current_config->alt_name.link_m, \
13081                                      current_config->alt_name.link_n, \
13082                                      pipe_config->name.tu, \
13083                                      pipe_config->name.gmch_m, \
13084                                      pipe_config->name.gmch_n, \
13085                                      pipe_config->name.link_m, \
13086                                      pipe_config->name.link_n); \
13087                 ret = false; \
13088         } \
13089 } while (0)
13090
13091 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13092         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13093                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13094                                      "(%x) (expected %i, found %i)", \
13095                                      (mask), \
13096                                      current_config->name & (mask), \
13097                                      pipe_config->name & (mask)); \
13098                 ret = false; \
13099         } \
13100 } while (0)
13101
13102 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13103         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13104                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13105                                      "(expected %i, found %i)", \
13106                                      current_config->name, \
13107                                      pipe_config->name); \
13108                 ret = false; \
13109         } \
13110 } while (0)
13111
13112 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13113         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13114                                      &pipe_config->infoframes.name)) { \
13115                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13116                                                &current_config->infoframes.name, \
13117                                                &pipe_config->infoframes.name); \
13118                 ret = false; \
13119         } \
13120 } while (0)
13121
13122 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13123         if (current_config->name1 != pipe_config->name1) { \
13124                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13125                                 "(expected %i, found %i, won't compare lut values)", \
13126                                 current_config->name1, \
13127                                 pipe_config->name1); \
13128                 ret = false;\
13129         } else { \
13130                 if (!intel_color_lut_equal(current_config->name2, \
13131                                         pipe_config->name2, pipe_config->name1, \
13132                                         bit_precision)) { \
13133                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13134                                         "hw_state doesn't match sw_state"); \
13135                         ret = false; \
13136                 } \
13137         } \
13138 } while (0)
13139
13140 #define PIPE_CONF_QUIRK(quirk) \
13141         ((current_config->quirks | pipe_config->quirks) & (quirk))
13142
13143         PIPE_CONF_CHECK_I(cpu_transcoder);
13144
13145         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13146         PIPE_CONF_CHECK_I(fdi_lanes);
13147         PIPE_CONF_CHECK_M_N(fdi_m_n);
13148
13149         PIPE_CONF_CHECK_I(lane_count);
13150         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13151
13152         if (INTEL_GEN(dev_priv) < 8) {
13153                 PIPE_CONF_CHECK_M_N(dp_m_n);
13154
13155                 if (current_config->has_drrs)
13156                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13157         } else
13158                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13159
13160         PIPE_CONF_CHECK_X(output_types);
13161
13162         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13163         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13164         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13165         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13166         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13167         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13168
13169         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13170         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13171         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13172         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13173         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13174         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13175
13176         PIPE_CONF_CHECK_I(pixel_multiplier);
13177         PIPE_CONF_CHECK_I(output_format);
13178         PIPE_CONF_CHECK_I(dc3co_exitline);
13179         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13180         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13181             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13182                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13183
13184         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13185         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13186         PIPE_CONF_CHECK_BOOL(has_infoframe);
13187         PIPE_CONF_CHECK_BOOL(fec_enable);
13188
13189         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13190
13191         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13192                               DRM_MODE_FLAG_INTERLACE);
13193
13194         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13195                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13196                                       DRM_MODE_FLAG_PHSYNC);
13197                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13198                                       DRM_MODE_FLAG_NHSYNC);
13199                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13200                                       DRM_MODE_FLAG_PVSYNC);
13201                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13202                                       DRM_MODE_FLAG_NVSYNC);
13203         }
13204
13205         PIPE_CONF_CHECK_X(gmch_pfit.control);
13206         /* pfit ratios are autocomputed by the hw on gen4+ */
13207         if (INTEL_GEN(dev_priv) < 4)
13208                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13209         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13210
13211         /*
13212          * Changing the EDP transcoder input mux
13213          * (A_ONOFF vs. A_ON) requires a full modeset.
13214          */
13215         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13216
13217         if (!fastset) {
13218                 PIPE_CONF_CHECK_I(pipe_src_w);
13219                 PIPE_CONF_CHECK_I(pipe_src_h);
13220
13221                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13222                 if (current_config->pch_pfit.enabled) {
13223                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13224                         PIPE_CONF_CHECK_X(pch_pfit.size);
13225                 }
13226
13227                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13228                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13229
13230                 PIPE_CONF_CHECK_X(gamma_mode);
13231                 if (IS_CHERRYVIEW(dev_priv))
13232                         PIPE_CONF_CHECK_X(cgm_mode);
13233                 else
13234                         PIPE_CONF_CHECK_X(csc_mode);
13235                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13236                 PIPE_CONF_CHECK_BOOL(csc_enable);
13237
13238                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13239                 if (bp_gamma)
13240                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13241
13242         }
13243
13244         PIPE_CONF_CHECK_BOOL(double_wide);
13245
13246         PIPE_CONF_CHECK_P(shared_dpll);
13247         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13248         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13249         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13250         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13251         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13252         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13253         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13254         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13255         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13256         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13257         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13258         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13259         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13260         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13261         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13262         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13263         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13264         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13265         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13266         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13267         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13268         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13269         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13270         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13271         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13272         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13273         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13274         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13275         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13276         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13277         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13278
13279         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13280         PIPE_CONF_CHECK_X(dsi_pll.div);
13281
13282         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13283                 PIPE_CONF_CHECK_I(pipe_bpp);
13284
13285         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13286         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13287
13288         PIPE_CONF_CHECK_I(min_voltage_level);
13289
13290         PIPE_CONF_CHECK_X(infoframes.enable);
13291         PIPE_CONF_CHECK_X(infoframes.gcp);
13292         PIPE_CONF_CHECK_INFOFRAME(avi);
13293         PIPE_CONF_CHECK_INFOFRAME(spd);
13294         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13295         PIPE_CONF_CHECK_INFOFRAME(drm);
13296
13297         PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
13298         PIPE_CONF_CHECK_I(master_transcoder);
13299
13300         PIPE_CONF_CHECK_I(dsc.compression_enable);
13301         PIPE_CONF_CHECK_I(dsc.dsc_split);
13302         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
13303
13304 #undef PIPE_CONF_CHECK_X
13305 #undef PIPE_CONF_CHECK_I
13306 #undef PIPE_CONF_CHECK_BOOL
13307 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13308 #undef PIPE_CONF_CHECK_P
13309 #undef PIPE_CONF_CHECK_FLAGS
13310 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13311 #undef PIPE_CONF_CHECK_COLOR_LUT
13312 #undef PIPE_CONF_QUIRK
13313
13314         return ret;
13315 }
13316
13317 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13318                                            const struct intel_crtc_state *pipe_config)
13319 {
13320         if (pipe_config->has_pch_encoder) {
13321                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13322                                                             &pipe_config->fdi_m_n);
13323                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13324
13325                 /*
13326                  * FDI already provided one idea for the dotclock.
13327                  * Yell if the encoder disagrees.
13328                  */
13329                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13330                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13331                      fdi_dotclock, dotclock);
13332         }
13333 }
13334
13335 static void verify_wm_state(struct intel_crtc *crtc,
13336                             struct intel_crtc_state *new_crtc_state)
13337 {
13338         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13339         struct skl_hw_state {
13340                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13341                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13342                 struct skl_ddb_allocation ddb;
13343                 struct skl_pipe_wm wm;
13344         } *hw;
13345         struct skl_ddb_allocation *sw_ddb;
13346         struct skl_pipe_wm *sw_wm;
13347         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13348         const enum pipe pipe = crtc->pipe;
13349         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13350
13351         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13352                 return;
13353
13354         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13355         if (!hw)
13356                 return;
13357
13358         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13359         sw_wm = &new_crtc_state->wm.skl.optimal;
13360
13361         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13362
13363         skl_ddb_get_hw_state(dev_priv, &hw->ddb);
13364         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13365
13366         if (INTEL_GEN(dev_priv) >= 11 &&
13367             hw->ddb.enabled_slices != sw_ddb->enabled_slices)
13368                 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
13369                           sw_ddb->enabled_slices,
13370                           hw->ddb.enabled_slices);
13371
13372         /* planes */
13373         for_each_universal_plane(dev_priv, pipe, plane) {
13374                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13375
13376                 hw_plane_wm = &hw->wm.planes[plane];
13377                 sw_plane_wm = &sw_wm->planes[plane];
13378
13379                 /* Watermarks */
13380                 for (level = 0; level <= max_level; level++) {
13381                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13382                                                 &sw_plane_wm->wm[level]))
13383                                 continue;
13384
13385                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13386                                   pipe_name(pipe), plane + 1, level,
13387                                   sw_plane_wm->wm[level].plane_en,
13388                                   sw_plane_wm->wm[level].plane_res_b,
13389                                   sw_plane_wm->wm[level].plane_res_l,
13390                                   hw_plane_wm->wm[level].plane_en,
13391                                   hw_plane_wm->wm[level].plane_res_b,
13392                                   hw_plane_wm->wm[level].plane_res_l);
13393                 }
13394
13395                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13396                                          &sw_plane_wm->trans_wm)) {
13397                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13398                                   pipe_name(pipe), plane + 1,
13399                                   sw_plane_wm->trans_wm.plane_en,
13400                                   sw_plane_wm->trans_wm.plane_res_b,
13401                                   sw_plane_wm->trans_wm.plane_res_l,
13402                                   hw_plane_wm->trans_wm.plane_en,
13403                                   hw_plane_wm->trans_wm.plane_res_b,
13404                                   hw_plane_wm->trans_wm.plane_res_l);
13405                 }
13406
13407                 /* DDB */
13408                 hw_ddb_entry = &hw->ddb_y[plane];
13409                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
13410
13411                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13412                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13413                                   pipe_name(pipe), plane + 1,
13414                                   sw_ddb_entry->start, sw_ddb_entry->end,
13415                                   hw_ddb_entry->start, hw_ddb_entry->end);
13416                 }
13417         }
13418
13419         /*
13420          * cursor
13421          * If the cursor plane isn't active, we may not have updated it's ddb
13422          * allocation. In that case since the ddb allocation will be updated
13423          * once the plane becomes visible, we can skip this check
13424          */
13425         if (1) {
13426                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
13427
13428                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
13429                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
13430
13431                 /* Watermarks */
13432                 for (level = 0; level <= max_level; level++) {
13433                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
13434                                                 &sw_plane_wm->wm[level]))
13435                                 continue;
13436
13437                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13438                                   pipe_name(pipe), level,
13439                                   sw_plane_wm->wm[level].plane_en,
13440                                   sw_plane_wm->wm[level].plane_res_b,
13441                                   sw_plane_wm->wm[level].plane_res_l,
13442                                   hw_plane_wm->wm[level].plane_en,
13443                                   hw_plane_wm->wm[level].plane_res_b,
13444                                   hw_plane_wm->wm[level].plane_res_l);
13445                 }
13446
13447                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13448                                          &sw_plane_wm->trans_wm)) {
13449                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13450                                   pipe_name(pipe),
13451                                   sw_plane_wm->trans_wm.plane_en,
13452                                   sw_plane_wm->trans_wm.plane_res_b,
13453                                   sw_plane_wm->trans_wm.plane_res_l,
13454                                   hw_plane_wm->trans_wm.plane_en,
13455                                   hw_plane_wm->trans_wm.plane_res_b,
13456                                   hw_plane_wm->trans_wm.plane_res_l);
13457                 }
13458
13459                 /* DDB */
13460                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13461                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13462
13463                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13464                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13465                                   pipe_name(pipe),
13466                                   sw_ddb_entry->start, sw_ddb_entry->end,
13467                                   hw_ddb_entry->start, hw_ddb_entry->end);
13468                 }
13469         }
13470
13471         kfree(hw);
13472 }
13473
13474 static void
13475 verify_connector_state(struct intel_atomic_state *state,
13476                        struct intel_crtc *crtc)
13477 {
13478         struct drm_connector *connector;
13479         struct drm_connector_state *new_conn_state;
13480         int i;
13481
13482         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13483                 struct drm_encoder *encoder = connector->encoder;
13484                 struct intel_crtc_state *crtc_state = NULL;
13485
13486                 if (new_conn_state->crtc != &crtc->base)
13487                         continue;
13488
13489                 if (crtc)
13490                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13491
13492                 intel_connector_verify_state(crtc_state, new_conn_state);
13493
13494                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13495                      "connector's atomic encoder doesn't match legacy encoder\n");
13496         }
13497 }
13498
13499 static void
13500 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13501 {
13502         struct intel_encoder *encoder;
13503         struct drm_connector *connector;
13504         struct drm_connector_state *old_conn_state, *new_conn_state;
13505         int i;
13506
13507         for_each_intel_encoder(&dev_priv->drm, encoder) {
13508                 bool enabled = false, found = false;
13509                 enum pipe pipe;
13510
13511                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13512                               encoder->base.base.id,
13513                               encoder->base.name);
13514
13515                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13516                                                    new_conn_state, i) {
13517                         if (old_conn_state->best_encoder == &encoder->base)
13518                                 found = true;
13519
13520                         if (new_conn_state->best_encoder != &encoder->base)
13521                                 continue;
13522                         found = enabled = true;
13523
13524                         I915_STATE_WARN(new_conn_state->crtc !=
13525                                         encoder->base.crtc,
13526                              "connector's crtc doesn't match encoder crtc\n");
13527                 }
13528
13529                 if (!found)
13530                         continue;
13531
13532                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13533                      "encoder's enabled state mismatch "
13534                      "(expected %i, found %i)\n",
13535                      !!encoder->base.crtc, enabled);
13536
13537                 if (!encoder->base.crtc) {
13538                         bool active;
13539
13540                         active = encoder->get_hw_state(encoder, &pipe);
13541                         I915_STATE_WARN(active,
13542                              "encoder detached but still enabled on pipe %c.\n",
13543                              pipe_name(pipe));
13544                 }
13545         }
13546 }
13547
13548 static void
13549 verify_crtc_state(struct intel_crtc *crtc,
13550                   struct intel_crtc_state *old_crtc_state,
13551                   struct intel_crtc_state *new_crtc_state)
13552 {
13553         struct drm_device *dev = crtc->base.dev;
13554         struct drm_i915_private *dev_priv = to_i915(dev);
13555         struct intel_encoder *encoder;
13556         struct intel_crtc_state *pipe_config;
13557         struct drm_atomic_state *state;
13558         bool active;
13559
13560         state = old_crtc_state->uapi.state;
13561         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
13562         intel_crtc_free_hw_state(old_crtc_state);
13563
13564         pipe_config = old_crtc_state;
13565         memset(pipe_config, 0, sizeof(*pipe_config));
13566         pipe_config->uapi.crtc = &crtc->base;
13567         pipe_config->uapi.state = state;
13568
13569         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13570
13571         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13572
13573         /* we keep both pipes enabled on 830 */
13574         if (IS_I830(dev_priv))
13575                 active = new_crtc_state->hw.active;
13576
13577         I915_STATE_WARN(new_crtc_state->hw.active != active,
13578                         "crtc active state doesn't match with hw state "
13579                         "(expected %i, found %i)\n",
13580                         new_crtc_state->hw.active, active);
13581
13582         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
13583                         "transitional active state does not match atomic hw state "
13584                         "(expected %i, found %i)\n",
13585                         new_crtc_state->hw.active, crtc->active);
13586
13587         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13588                 enum pipe pipe;
13589
13590                 active = encoder->get_hw_state(encoder, &pipe);
13591                 I915_STATE_WARN(active != new_crtc_state->hw.active,
13592                                 "[ENCODER:%i] active %i with crtc active %i\n",
13593                                 encoder->base.base.id, active,
13594                                 new_crtc_state->hw.active);
13595
13596                 I915_STATE_WARN(active && crtc->pipe != pipe,
13597                                 "Encoder connected to wrong pipe %c\n",
13598                                 pipe_name(pipe));
13599
13600                 if (active)
13601                         encoder->get_config(encoder, pipe_config);
13602         }
13603
13604         intel_crtc_compute_pixel_rate(pipe_config);
13605
13606         if (!new_crtc_state->hw.active)
13607                 return;
13608
13609         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13610
13611         if (!intel_pipe_config_compare(new_crtc_state,
13612                                        pipe_config, false)) {
13613                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13614                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13615                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13616         }
13617 }
13618
13619 static void
13620 intel_verify_planes(struct intel_atomic_state *state)
13621 {
13622         struct intel_plane *plane;
13623         const struct intel_plane_state *plane_state;
13624         int i;
13625
13626         for_each_new_intel_plane_in_state(state, plane,
13627                                           plane_state, i)
13628                 assert_plane(plane, plane_state->planar_slave ||
13629                              plane_state->uapi.visible);
13630 }
13631
13632 static void
13633 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13634                          struct intel_shared_dpll *pll,
13635                          struct intel_crtc *crtc,
13636                          struct intel_crtc_state *new_crtc_state)
13637 {
13638         struct intel_dpll_hw_state dpll_hw_state;
13639         unsigned int crtc_mask;
13640         bool active;
13641
13642         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13643
13644         DRM_DEBUG_KMS("%s\n", pll->info->name);
13645
13646         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13647
13648         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13649                 I915_STATE_WARN(!pll->on && pll->active_mask,
13650                      "pll in active use but not on in sw tracking\n");
13651                 I915_STATE_WARN(pll->on && !pll->active_mask,
13652                      "pll is on but not used by any active crtc\n");
13653                 I915_STATE_WARN(pll->on != active,
13654                      "pll on state mismatch (expected %i, found %i)\n",
13655                      pll->on, active);
13656         }
13657
13658         if (!crtc) {
13659                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13660                                 "more active pll users than references: %x vs %x\n",
13661                                 pll->active_mask, pll->state.crtc_mask);
13662
13663                 return;
13664         }
13665
13666         crtc_mask = drm_crtc_mask(&crtc->base);
13667
13668         if (new_crtc_state->hw.active)
13669                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13670                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13671                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13672         else
13673                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13674                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13675                                 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13676
13677         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13678                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13679                         crtc_mask, pll->state.crtc_mask);
13680
13681         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13682                                           &dpll_hw_state,
13683                                           sizeof(dpll_hw_state)),
13684                         "pll hw state mismatch\n");
13685 }
13686
13687 static void
13688 verify_shared_dpll_state(struct intel_crtc *crtc,
13689                          struct intel_crtc_state *old_crtc_state,
13690                          struct intel_crtc_state *new_crtc_state)
13691 {
13692         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13693
13694         if (new_crtc_state->shared_dpll)
13695                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13696
13697         if (old_crtc_state->shared_dpll &&
13698             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13699                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13700                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13701
13702                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13703                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13704                                 pipe_name(drm_crtc_index(&crtc->base)));
13705                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13706                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13707                                 pipe_name(drm_crtc_index(&crtc->base)));
13708         }
13709 }
13710
13711 static void
13712 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13713                           struct intel_atomic_state *state,
13714                           struct intel_crtc_state *old_crtc_state,
13715                           struct intel_crtc_state *new_crtc_state)
13716 {
13717         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13718                 return;
13719
13720         verify_wm_state(crtc, new_crtc_state);
13721         verify_connector_state(state, crtc);
13722         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13723         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13724 }
13725
13726 static void
13727 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13728 {
13729         int i;
13730
13731         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13732                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13733 }
13734
13735 static void
13736 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13737                               struct intel_atomic_state *state)
13738 {
13739         verify_encoder_state(dev_priv, state);
13740         verify_connector_state(state, NULL);
13741         verify_disabled_dpll_state(dev_priv);
13742 }
13743
13744 static void
13745 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
13746 {
13747         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13749         const struct drm_display_mode *adjusted_mode =
13750                 &crtc_state->hw.adjusted_mode;
13751
13752         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
13753
13754         /*
13755          * The scanline counter increments at the leading edge of hsync.
13756          *
13757          * On most platforms it starts counting from vtotal-1 on the
13758          * first active line. That means the scanline counter value is
13759          * always one less than what we would expect. Ie. just after
13760          * start of vblank, which also occurs at start of hsync (on the
13761          * last active line), the scanline counter will read vblank_start-1.
13762          *
13763          * On gen2 the scanline counter starts counting from 1 instead
13764          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13765          * to keep the value positive), instead of adding one.
13766          *
13767          * On HSW+ the behaviour of the scanline counter depends on the output
13768          * type. For DP ports it behaves like most other platforms, but on HDMI
13769          * there's an extra 1 line difference. So we need to add two instead of
13770          * one to the value.
13771          *
13772          * On VLV/CHV DSI the scanline counter would appear to increment
13773          * approx. 1/3 of a scanline before start of vblank. Unfortunately
13774          * that means we can't tell whether we're in vblank or not while
13775          * we're on that particular line. We must still set scanline_offset
13776          * to 1 so that the vblank timestamps come out correct when we query
13777          * the scanline counter from within the vblank interrupt handler.
13778          * However if queried just before the start of vblank we'll get an
13779          * answer that's slightly in the future.
13780          */
13781         if (IS_GEN(dev_priv, 2)) {
13782                 int vtotal;
13783
13784                 vtotal = adjusted_mode->crtc_vtotal;
13785                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13786                         vtotal /= 2;
13787
13788                 crtc->scanline_offset = vtotal - 1;
13789         } else if (HAS_DDI(dev_priv) &&
13790                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13791                 crtc->scanline_offset = 2;
13792         } else {
13793                 crtc->scanline_offset = 1;
13794         }
13795 }
13796
13797 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13798 {
13799         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13800         struct intel_crtc_state *new_crtc_state;
13801         struct intel_crtc *crtc;
13802         int i;
13803
13804         if (!dev_priv->display.crtc_compute_clock)
13805                 return;
13806
13807         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13808                 if (!needs_modeset(new_crtc_state))
13809                         continue;
13810
13811                 intel_release_shared_dplls(state, crtc);
13812         }
13813 }
13814
13815 /*
13816  * This implements the workaround described in the "notes" section of the mode
13817  * set sequence documentation. When going from no pipes or single pipe to
13818  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13819  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13820  */
13821 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13822 {
13823         struct intel_crtc_state *crtc_state;
13824         struct intel_crtc *crtc;
13825         struct intel_crtc_state *first_crtc_state = NULL;
13826         struct intel_crtc_state *other_crtc_state = NULL;
13827         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13828         int i;
13829
13830         /* look at all crtc's that are going to be enabled in during modeset */
13831         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13832                 if (!crtc_state->hw.active ||
13833                     !needs_modeset(crtc_state))
13834                         continue;
13835
13836                 if (first_crtc_state) {
13837                         other_crtc_state = crtc_state;
13838                         break;
13839                 } else {
13840                         first_crtc_state = crtc_state;
13841                         first_pipe = crtc->pipe;
13842                 }
13843         }
13844
13845         /* No workaround needed? */
13846         if (!first_crtc_state)
13847                 return 0;
13848
13849         /* w/a possibly needed, check how many crtc's are already enabled. */
13850         for_each_intel_crtc(state->base.dev, crtc) {
13851                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13852                 if (IS_ERR(crtc_state))
13853                         return PTR_ERR(crtc_state);
13854
13855                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13856
13857                 if (!crtc_state->hw.active ||
13858                     needs_modeset(crtc_state))
13859                         continue;
13860
13861                 /* 2 or more enabled crtcs means no need for w/a */
13862                 if (enabled_pipe != INVALID_PIPE)
13863                         return 0;
13864
13865                 enabled_pipe = crtc->pipe;
13866         }
13867
13868         if (enabled_pipe != INVALID_PIPE)
13869                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13870         else if (other_crtc_state)
13871                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13872
13873         return 0;
13874 }
13875
13876 static int intel_modeset_checks(struct intel_atomic_state *state)
13877 {
13878         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13879         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13880         struct intel_crtc *crtc;
13881         int ret, i;
13882
13883         /* keep the current setting */
13884         if (!state->cdclk.force_min_cdclk_changed)
13885                 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13886
13887         state->modeset = true;
13888         state->active_pipes = dev_priv->active_pipes;
13889         state->cdclk.logical = dev_priv->cdclk.logical;
13890         state->cdclk.actual = dev_priv->cdclk.actual;
13891
13892         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13893                                             new_crtc_state, i) {
13894                 if (new_crtc_state->hw.active)
13895                         state->active_pipes |= BIT(crtc->pipe);
13896                 else
13897                         state->active_pipes &= ~BIT(crtc->pipe);
13898
13899                 if (old_crtc_state->hw.active != new_crtc_state->hw.active)
13900                         state->active_pipe_changes |= BIT(crtc->pipe);
13901         }
13902
13903         if (state->active_pipe_changes) {
13904                 ret = intel_atomic_lock_global_state(state);
13905                 if (ret)
13906                         return ret;
13907         }
13908
13909         ret = intel_modeset_calc_cdclk(state);
13910         if (ret)
13911                 return ret;
13912
13913         intel_modeset_clear_plls(state);
13914
13915         if (IS_HASWELL(dev_priv))
13916                 return haswell_mode_set_planes_workaround(state);
13917
13918         return 0;
13919 }
13920
13921 /*
13922  * Handle calculation of various watermark data at the end of the atomic check
13923  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13924  * handlers to ensure that all derived state has been updated.
13925  */
13926 static int calc_watermark_data(struct intel_atomic_state *state)
13927 {
13928         struct drm_device *dev = state->base.dev;
13929         struct drm_i915_private *dev_priv = to_i915(dev);
13930
13931         /* Is there platform-specific watermark information to calculate? */
13932         if (dev_priv->display.compute_global_watermarks)
13933                 return dev_priv->display.compute_global_watermarks(state);
13934
13935         return 0;
13936 }
13937
13938 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13939                                      struct intel_crtc_state *new_crtc_state)
13940 {
13941         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13942                 return;
13943
13944         new_crtc_state->uapi.mode_changed = false;
13945         new_crtc_state->update_pipe = true;
13946
13947         /*
13948          * If we're not doing the full modeset we want to
13949          * keep the current M/N values as they may be
13950          * sufficiently different to the computed values
13951          * to cause problems.
13952          *
13953          * FIXME: should really copy more fuzzy state here
13954          */
13955         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13956         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13957         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13958         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13959 }
13960
13961 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
13962                                           struct intel_crtc *crtc,
13963                                           u8 plane_ids_mask)
13964 {
13965         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13966         struct intel_plane *plane;
13967
13968         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13969                 struct intel_plane_state *plane_state;
13970
13971                 if ((plane_ids_mask & BIT(plane->id)) == 0)
13972                         continue;
13973
13974                 plane_state = intel_atomic_get_plane_state(state, plane);
13975                 if (IS_ERR(plane_state))
13976                         return PTR_ERR(plane_state);
13977         }
13978
13979         return 0;
13980 }
13981
13982 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
13983 {
13984         /* See {hsw,vlv,ivb}_plane_ratio() */
13985         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
13986                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13987                 IS_IVYBRIDGE(dev_priv);
13988 }
13989
13990 static int intel_atomic_check_planes(struct intel_atomic_state *state,
13991                                      bool *need_modeset)
13992 {
13993         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13994         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13995         struct intel_plane_state *plane_state;
13996         struct intel_plane *plane;
13997         struct intel_crtc *crtc;
13998         int i, ret;
13999
14000         ret = icl_add_linked_planes(state);
14001         if (ret)
14002                 return ret;
14003
14004         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14005                 ret = intel_plane_atomic_check(state, plane);
14006                 if (ret) {
14007                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
14008                                          plane->base.base.id, plane->base.name);
14009                         return ret;
14010                 }
14011         }
14012
14013         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14014                                             new_crtc_state, i) {
14015                 u8 old_active_planes, new_active_planes;
14016
14017                 ret = icl_check_nv12_planes(new_crtc_state);
14018                 if (ret)
14019                         return ret;
14020
14021                 /*
14022                  * On some platforms the number of active planes affects
14023                  * the planes' minimum cdclk calculation. Add such planes
14024                  * to the state before we compute the minimum cdclk.
14025                  */
14026                 if (!active_planes_affects_min_cdclk(dev_priv))
14027                         continue;
14028
14029                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14030                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14031
14032                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14033                         continue;
14034
14035                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14036                 if (ret)
14037                         return ret;
14038         }
14039
14040         /*
14041          * active_planes bitmask has been updated, and potentially
14042          * affected planes are part of the state. We can now
14043          * compute the minimum cdclk for each plane.
14044          */
14045         for_each_new_intel_plane_in_state(state, plane, plane_state, i)
14046                 *need_modeset |= intel_plane_calc_min_cdclk(state, plane);
14047
14048         return 0;
14049 }
14050
14051 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14052 {
14053         struct intel_crtc_state *crtc_state;
14054         struct intel_crtc *crtc;
14055         int i;
14056
14057         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14058                 int ret = intel_crtc_atomic_check(state, crtc);
14059                 if (ret) {
14060                         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
14061                                          crtc->base.base.id, crtc->base.name);
14062                         return ret;
14063                 }
14064         }
14065
14066         return 0;
14067 }
14068
14069 /**
14070  * intel_atomic_check - validate state object
14071  * @dev: drm device
14072  * @_state: state to validate
14073  */
14074 static int intel_atomic_check(struct drm_device *dev,
14075                               struct drm_atomic_state *_state)
14076 {
14077         struct drm_i915_private *dev_priv = to_i915(dev);
14078         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14079         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14080         struct intel_crtc *crtc;
14081         int ret, i;
14082         bool any_ms = false;
14083
14084         /* Catch I915_MODE_FLAG_INHERITED */
14085         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14086                                             new_crtc_state, i) {
14087                 if (new_crtc_state->hw.mode.private_flags !=
14088                     old_crtc_state->hw.mode.private_flags)
14089                         new_crtc_state->uapi.mode_changed = true;
14090         }
14091
14092         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14093         if (ret)
14094                 goto fail;
14095
14096         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14097                                             new_crtc_state, i) {
14098                 if (!needs_modeset(new_crtc_state)) {
14099                         /* Light copy */
14100                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14101
14102                         continue;
14103                 }
14104
14105                 if (!new_crtc_state->uapi.enable) {
14106                         intel_crtc_copy_uapi_to_hw_state(new_crtc_state);
14107
14108                         any_ms = true;
14109                         continue;
14110                 }
14111
14112                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14113                 if (ret)
14114                         goto fail;
14115
14116                 ret = intel_modeset_pipe_config(new_crtc_state);
14117                 if (ret)
14118                         goto fail;
14119
14120                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14121
14122                 if (needs_modeset(new_crtc_state))
14123                         any_ms = true;
14124         }
14125
14126         if (any_ms && !check_digital_port_conflicts(state)) {
14127                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14128                 ret = EINVAL;
14129                 goto fail;
14130         }
14131
14132         ret = drm_dp_mst_atomic_check(&state->base);
14133         if (ret)
14134                 goto fail;
14135
14136         any_ms |= state->cdclk.force_min_cdclk_changed;
14137
14138         ret = intel_atomic_check_planes(state, &any_ms);
14139         if (ret)
14140                 goto fail;
14141
14142         if (any_ms) {
14143                 ret = intel_modeset_checks(state);
14144                 if (ret)
14145                         goto fail;
14146         } else {
14147                 state->cdclk.logical = dev_priv->cdclk.logical;
14148         }
14149
14150         ret = intel_atomic_check_crtcs(state);
14151         if (ret)
14152                 goto fail;
14153
14154         intel_fbc_choose_crtc(dev_priv, state);
14155         ret = calc_watermark_data(state);
14156         if (ret)
14157                 goto fail;
14158
14159         ret = intel_bw_atomic_check(state);
14160         if (ret)
14161                 goto fail;
14162
14163         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14164                                             new_crtc_state, i) {
14165                 if (!needs_modeset(new_crtc_state) &&
14166                     !new_crtc_state->update_pipe)
14167                         continue;
14168
14169                 intel_dump_pipe_config(new_crtc_state, state,
14170                                        needs_modeset(new_crtc_state) ?
14171                                        "[modeset]" : "[fastset]");
14172         }
14173
14174         return 0;
14175
14176  fail:
14177         if (ret == -EDEADLK)
14178                 return ret;
14179
14180         /*
14181          * FIXME would probably be nice to know which crtc specifically
14182          * caused the failure, in cases where we can pinpoint it.
14183          */
14184         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14185                                             new_crtc_state, i)
14186                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14187
14188         return ret;
14189 }
14190
14191 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14192 {
14193         return drm_atomic_helper_prepare_planes(state->base.dev,
14194                                                 &state->base);
14195 }
14196
14197 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14198 {
14199         struct drm_device *dev = crtc->base.dev;
14200         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14201
14202         if (!vblank->max_vblank_count)
14203                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14204
14205         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14206 }
14207
14208 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14209                                   struct intel_crtc_state *crtc_state)
14210 {
14211         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14212
14213         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
14214                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14215
14216         if (crtc_state->has_pch_encoder) {
14217                 enum pipe pch_transcoder =
14218                         intel_crtc_pch_transcoder(crtc);
14219
14220                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14221         }
14222 }
14223
14224 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14225                                const struct intel_crtc_state *new_crtc_state)
14226 {
14227         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14228         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14229
14230         /*
14231          * Update pipe size and adjust fitter if needed: the reason for this is
14232          * that in compute_mode_changes we check the native mode (not the pfit
14233          * mode) to see if we can flip rather than do a full mode set. In the
14234          * fastboot case, we'll flip, but if we don't update the pipesrc and
14235          * pfit state, we'll end up with a big fb scanned out into the wrong
14236          * sized surface.
14237          */
14238         intel_set_pipe_src_size(new_crtc_state);
14239
14240         /* on skylake this is done by detaching scalers */
14241         if (INTEL_GEN(dev_priv) >= 9) {
14242                 skl_detach_scalers(new_crtc_state);
14243
14244                 if (new_crtc_state->pch_pfit.enabled)
14245                         skylake_pfit_enable(new_crtc_state);
14246         } else if (HAS_PCH_SPLIT(dev_priv)) {
14247                 if (new_crtc_state->pch_pfit.enabled)
14248                         ironlake_pfit_enable(new_crtc_state);
14249                 else if (old_crtc_state->pch_pfit.enabled)
14250                         ironlake_pfit_disable(old_crtc_state);
14251         }
14252
14253         if (INTEL_GEN(dev_priv) >= 11)
14254                 icl_set_pipe_chicken(crtc);
14255 }
14256
14257 static void commit_pipe_config(struct intel_atomic_state *state,
14258                                struct intel_crtc_state *old_crtc_state,
14259                                struct intel_crtc_state *new_crtc_state)
14260 {
14261         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14262         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14263         bool modeset = needs_modeset(new_crtc_state);
14264
14265         /*
14266          * During modesets pipe configuration was programmed as the
14267          * CRTC was enabled.
14268          */
14269         if (!modeset) {
14270                 if (new_crtc_state->uapi.color_mgmt_changed ||
14271                     new_crtc_state->update_pipe)
14272                         intel_color_commit(new_crtc_state);
14273
14274                 if (INTEL_GEN(dev_priv) >= 9)
14275                         skl_detach_scalers(new_crtc_state);
14276
14277                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14278                         bdw_set_pipemisc(new_crtc_state);
14279
14280                 if (new_crtc_state->update_pipe)
14281                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
14282         }
14283
14284         if (dev_priv->display.atomic_update_watermarks)
14285                 dev_priv->display.atomic_update_watermarks(state, crtc);
14286 }
14287
14288 static void intel_update_crtc(struct intel_crtc *crtc,
14289                               struct intel_atomic_state *state,
14290                               struct intel_crtc_state *old_crtc_state,
14291                               struct intel_crtc_state *new_crtc_state)
14292 {
14293         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14294         bool modeset = needs_modeset(new_crtc_state);
14295         struct intel_plane_state *new_plane_state =
14296                 intel_atomic_get_new_plane_state(state,
14297                                                  to_intel_plane(crtc->base.primary));
14298
14299         if (modeset) {
14300                 intel_crtc_update_active_timings(new_crtc_state);
14301
14302                 dev_priv->display.crtc_enable(state, crtc);
14303
14304                 /* vblanks work again, re-enable pipe CRC. */
14305                 intel_crtc_enable_pipe_crc(crtc);
14306         } else {
14307                 if (new_crtc_state->preload_luts &&
14308                     (new_crtc_state->uapi.color_mgmt_changed ||
14309                      new_crtc_state->update_pipe))
14310                         intel_color_load_luts(new_crtc_state);
14311
14312                 intel_pre_plane_update(state, crtc);
14313
14314                 if (new_crtc_state->update_pipe)
14315                         intel_encoders_update_pipe(state, crtc);
14316         }
14317
14318         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14319                 intel_fbc_disable(crtc);
14320         else if (new_plane_state)
14321                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14322
14323         /* Perform vblank evasion around commit operation */
14324         intel_pipe_update_start(new_crtc_state);
14325
14326         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14327
14328         if (INTEL_GEN(dev_priv) >= 9)
14329                 skl_update_planes_on_crtc(state, crtc);
14330         else
14331                 i9xx_update_planes_on_crtc(state, crtc);
14332
14333         intel_pipe_update_end(new_crtc_state);
14334
14335         /*
14336          * We usually enable FIFO underrun interrupts as part of the
14337          * CRTC enable sequence during modesets.  But when we inherit a
14338          * valid pipe configuration from the BIOS we need to take care
14339          * of enabling them on the CRTC's first fastset.
14340          */
14341         if (new_crtc_state->update_pipe && !modeset &&
14342             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14343                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14344 }
14345
14346 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
14347 {
14348         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
14349         enum transcoder slave_transcoder;
14350
14351         WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
14352
14353         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
14354         return intel_get_crtc_for_pipe(dev_priv,
14355                                        (enum pipe)slave_transcoder);
14356 }
14357
14358 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
14359                                           struct intel_crtc_state *old_crtc_state,
14360                                           struct intel_crtc_state *new_crtc_state,
14361                                           struct intel_crtc *crtc)
14362 {
14363         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14364
14365         intel_crtc_disable_planes(state, crtc);
14366
14367         /*
14368          * We need to disable pipe CRC before disabling the pipe,
14369          * or we race against vblank off.
14370          */
14371         intel_crtc_disable_pipe_crc(crtc);
14372
14373         dev_priv->display.crtc_disable(state, crtc);
14374         crtc->active = false;
14375         intel_fbc_disable(crtc);
14376         intel_disable_shared_dpll(old_crtc_state);
14377
14378         /* FIXME unify this for all platforms */
14379         if (!new_crtc_state->hw.active &&
14380             !HAS_GMCH(dev_priv) &&
14381             dev_priv->display.initial_watermarks)
14382                 dev_priv->display.initial_watermarks(state, crtc);
14383 }
14384
14385 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
14386 {
14387         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14388         struct intel_crtc *crtc;
14389         u32 handled = 0;
14390         int i;
14391
14392         /* Only disable port sync slaves */
14393         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14394                                             new_crtc_state, i) {
14395                 if (!needs_modeset(new_crtc_state))
14396                         continue;
14397
14398                 if (!old_crtc_state->hw.active)
14399                         continue;
14400
14401                 /* In case of Transcoder port Sync master slave CRTCs can be
14402                  * assigned in any order and we need to make sure that
14403                  * slave CRTCs are disabled first and then master CRTC since
14404                  * Slave vblanks are masked till Master Vblanks.
14405                  */
14406                 if (!is_trans_port_sync_slave(old_crtc_state))
14407                         continue;
14408
14409                 intel_pre_plane_update(state, crtc);
14410                 intel_old_crtc_state_disables(state, old_crtc_state,
14411                                               new_crtc_state, crtc);
14412                 handled |= BIT(crtc->pipe);
14413         }
14414
14415         /* Disable everything else left on */
14416         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14417                                             new_crtc_state, i) {
14418                 if (!needs_modeset(new_crtc_state) ||
14419                     (handled & BIT(crtc->pipe)))
14420                         continue;
14421
14422                 intel_pre_plane_update(state, crtc);
14423                 if (old_crtc_state->hw.active)
14424                         intel_old_crtc_state_disables(state, old_crtc_state,
14425                                                       new_crtc_state, crtc);
14426         }
14427 }
14428
14429 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
14430 {
14431         struct intel_crtc *crtc;
14432         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14433         int i;
14434
14435         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14436                 if (!new_crtc_state->hw.active)
14437                         continue;
14438
14439                 intel_update_crtc(crtc, state, old_crtc_state,
14440                                   new_crtc_state);
14441         }
14442 }
14443
14444 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
14445                                               struct intel_atomic_state *state,
14446                                               struct intel_crtc_state *new_crtc_state)
14447 {
14448         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14449
14450         intel_crtc_update_active_timings(new_crtc_state);
14451         dev_priv->display.crtc_enable(state, crtc);
14452         intel_crtc_enable_pipe_crc(crtc);
14453 }
14454
14455 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
14456                                        struct intel_atomic_state *state)
14457 {
14458         struct drm_connector *uninitialized_var(conn);
14459         struct drm_connector_state *conn_state;
14460         struct intel_dp *intel_dp;
14461         int i;
14462
14463         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
14464                 if (conn_state->crtc == &crtc->base)
14465                         break;
14466         }
14467         intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
14468         intel_dp_stop_link_train(intel_dp);
14469 }
14470
14471 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
14472                                            struct intel_atomic_state *state)
14473 {
14474         struct intel_crtc_state *new_crtc_state =
14475                 intel_atomic_get_new_crtc_state(state, crtc);
14476         struct intel_crtc_state *old_crtc_state =
14477                 intel_atomic_get_old_crtc_state(state, crtc);
14478         struct intel_plane_state *new_plane_state =
14479                 intel_atomic_get_new_plane_state(state,
14480                                                  to_intel_plane(crtc->base.primary));
14481         bool modeset = needs_modeset(new_crtc_state);
14482
14483         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
14484                 intel_fbc_disable(crtc);
14485         else if (new_plane_state)
14486                 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
14487
14488         /* Perform vblank evasion around commit operation */
14489         intel_pipe_update_start(new_crtc_state);
14490         commit_pipe_config(state, old_crtc_state, new_crtc_state);
14491         skl_update_planes_on_crtc(state, crtc);
14492         intel_pipe_update_end(new_crtc_state);
14493
14494         /*
14495          * We usually enable FIFO underrun interrupts as part of the
14496          * CRTC enable sequence during modesets.  But when we inherit a
14497          * valid pipe configuration from the BIOS we need to take care
14498          * of enabling them on the CRTC's first fastset.
14499          */
14500         if (new_crtc_state->update_pipe && !modeset &&
14501             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
14502                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14503 }
14504
14505 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
14506                                                struct intel_atomic_state *state,
14507                                                struct intel_crtc_state *old_crtc_state,
14508                                                struct intel_crtc_state *new_crtc_state)
14509 {
14510         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
14511         struct intel_crtc_state *new_slave_crtc_state =
14512                 intel_atomic_get_new_crtc_state(state, slave_crtc);
14513         struct intel_crtc_state *old_slave_crtc_state =
14514                 intel_atomic_get_old_crtc_state(state, slave_crtc);
14515
14516         WARN_ON(!slave_crtc || !new_slave_crtc_state ||
14517                 !old_slave_crtc_state);
14518
14519         DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
14520                       crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
14521                       slave_crtc->base.name);
14522
14523         /* Enable seq for slave with with DP_TP_CTL left Idle until the
14524          * master is ready
14525          */
14526         intel_crtc_enable_trans_port_sync(slave_crtc,
14527                                           state,
14528                                           new_slave_crtc_state);
14529
14530         /* Enable seq for master with with DP_TP_CTL left Idle */
14531         intel_crtc_enable_trans_port_sync(crtc,
14532                                           state,
14533                                           new_crtc_state);
14534
14535         /* Set Slave's DP_TP_CTL to Normal */
14536         intel_set_dp_tp_ctl_normal(slave_crtc,
14537                                    state);
14538
14539         /* Set Master's DP_TP_CTL To Normal */
14540         usleep_range(200, 400);
14541         intel_set_dp_tp_ctl_normal(crtc,
14542                                    state);
14543
14544         /* Now do the post crtc enable for all master and slaves */
14545         intel_post_crtc_enable_updates(slave_crtc,
14546                                        state);
14547         intel_post_crtc_enable_updates(crtc,
14548                                        state);
14549 }
14550
14551 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
14552 {
14553         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14554         struct intel_crtc *crtc;
14555         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14556         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
14557         u8 required_slices = state->wm_results.ddb.enabled_slices;
14558         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
14559         u8 dirty_pipes = 0;
14560         int i;
14561
14562         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14563                 /* ignore allocations for crtc's that have been turned off. */
14564                 if (!needs_modeset(new_crtc_state) && new_crtc_state->hw.active)
14565                         entries[i] = old_crtc_state->wm.skl.ddb;
14566                 if (new_crtc_state->hw.active)
14567                         dirty_pipes |= BIT(crtc->pipe);
14568         }
14569
14570         /* If 2nd DBuf slice required, enable it here */
14571         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
14572                 icl_dbuf_slices_update(dev_priv, required_slices);
14573
14574         /*
14575          * Whenever the number of active pipes changes, we need to make sure we
14576          * update the pipes in the right order so that their ddb allocations
14577          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14578          * cause pipe underruns and other bad stuff.
14579          */
14580         while (dirty_pipes) {
14581                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14582                                                     new_crtc_state, i) {
14583                         enum pipe pipe = crtc->pipe;
14584                         bool modeset = needs_modeset(new_crtc_state);
14585
14586                         if ((dirty_pipes & BIT(pipe)) == 0)
14587                                 continue;
14588
14589                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
14590                                                         entries,
14591                                                         INTEL_NUM_PIPES(dev_priv), i))
14592                                 continue;
14593
14594                         entries[i] = new_crtc_state->wm.skl.ddb;
14595                         dirty_pipes &= ~BIT(pipe);
14596
14597                         if (modeset && is_trans_port_sync_mode(new_crtc_state)) {
14598                                 if (is_trans_port_sync_master(new_crtc_state))
14599                                         intel_update_trans_port_sync_crtcs(crtc,
14600                                                                            state,
14601                                                                            old_crtc_state,
14602                                                                            new_crtc_state);
14603                                 else
14604                                         continue;
14605                         } else {
14606                                 intel_update_crtc(crtc, state, old_crtc_state,
14607                                                   new_crtc_state);
14608                         }
14609
14610                         /*
14611                          * If this is an already active pipe, it's DDB changed,
14612                          * and this isn't the last pipe that needs updating
14613                          * then we need to wait for a vblank to pass for the
14614                          * new ddb allocation to take effect.
14615                          */
14616                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
14617                                                  &old_crtc_state->wm.skl.ddb) &&
14618                             !modeset && dirty_pipes)
14619                                 intel_wait_for_vblank(dev_priv, pipe);
14620                 }
14621         }
14622
14623         /* If 2nd DBuf slice is no more required disable it */
14624         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
14625                 icl_dbuf_slices_update(dev_priv, required_slices);
14626 }
14627
14628 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14629 {
14630         struct intel_atomic_state *state, *next;
14631         struct llist_node *freed;
14632
14633         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14634         llist_for_each_entry_safe(state, next, freed, freed)
14635                 drm_atomic_state_put(&state->base);
14636 }
14637
14638 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14639 {
14640         struct drm_i915_private *dev_priv =
14641                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14642
14643         intel_atomic_helper_free_state(dev_priv);
14644 }
14645
14646 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
14647 {
14648         struct wait_queue_entry wait_fence, wait_reset;
14649         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
14650
14651         init_wait_entry(&wait_fence, 0);
14652         init_wait_entry(&wait_reset, 0);
14653         for (;;) {
14654                 prepare_to_wait(&intel_state->commit_ready.wait,
14655                                 &wait_fence, TASK_UNINTERRUPTIBLE);
14656                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14657                                               I915_RESET_MODESET),
14658                                 &wait_reset, TASK_UNINTERRUPTIBLE);
14659
14660
14661                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
14662                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
14663                         break;
14664
14665                 schedule();
14666         }
14667         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
14668         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
14669                                   I915_RESET_MODESET),
14670                     &wait_reset);
14671 }
14672
14673 static void intel_atomic_cleanup_work(struct work_struct *work)
14674 {
14675         struct drm_atomic_state *state =
14676                 container_of(work, struct drm_atomic_state, commit_work);
14677         struct drm_i915_private *i915 = to_i915(state->dev);
14678
14679         drm_atomic_helper_cleanup_planes(&i915->drm, state);
14680         drm_atomic_helper_commit_cleanup_done(state);
14681         drm_atomic_state_put(state);
14682
14683         intel_atomic_helper_free_state(i915);
14684 }
14685
14686 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
14687 {
14688         struct drm_device *dev = state->base.dev;
14689         struct drm_i915_private *dev_priv = to_i915(dev);
14690         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
14691         struct intel_crtc *crtc;
14692         u64 put_domains[I915_MAX_PIPES] = {};
14693         intel_wakeref_t wakeref = 0;
14694         int i;
14695
14696         intel_atomic_commit_fence_wait(state);
14697
14698         drm_atomic_helper_wait_for_dependencies(&state->base);
14699
14700         if (state->modeset)
14701                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14702
14703         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14704                                             new_crtc_state, i) {
14705                 if (needs_modeset(new_crtc_state) ||
14706                     new_crtc_state->update_pipe) {
14707
14708                         put_domains[crtc->pipe] =
14709                                 modeset_get_crtc_power_domains(new_crtc_state);
14710                 }
14711         }
14712
14713         intel_commit_modeset_disables(state);
14714
14715         /* FIXME: Eventually get rid of our crtc->config pointer */
14716         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14717                 crtc->config = new_crtc_state;
14718
14719         if (state->modeset) {
14720                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14721
14722                 intel_set_cdclk_pre_plane_update(dev_priv,
14723                                                  &state->cdclk.actual,
14724                                                  &dev_priv->cdclk.actual,
14725                                                  state->cdclk.pipe);
14726
14727                 /*
14728                  * SKL workaround: bspec recommends we disable the SAGV when we
14729                  * have more then one pipe enabled
14730                  */
14731                 if (!intel_can_enable_sagv(state))
14732                         intel_disable_sagv(dev_priv);
14733
14734                 intel_modeset_verify_disabled(dev_priv, state);
14735         }
14736
14737         /* Complete the events for pipes that have now been disabled */
14738         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14739                 bool modeset = needs_modeset(new_crtc_state);
14740
14741                 /* Complete events for now disable pipes here. */
14742                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
14743                         spin_lock_irq(&dev->event_lock);
14744                         drm_crtc_send_vblank_event(&crtc->base,
14745                                                    new_crtc_state->uapi.event);
14746                         spin_unlock_irq(&dev->event_lock);
14747
14748                         new_crtc_state->uapi.event = NULL;
14749                 }
14750         }
14751
14752         if (state->modeset)
14753                 intel_encoders_update_prepare(state);
14754
14755         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14756         dev_priv->display.commit_modeset_enables(state);
14757
14758         if (state->modeset) {
14759                 intel_encoders_update_complete(state);
14760
14761                 intel_set_cdclk_post_plane_update(dev_priv,
14762                                                   &state->cdclk.actual,
14763                                                   &dev_priv->cdclk.actual,
14764                                                   state->cdclk.pipe);
14765         }
14766
14767         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14768          * already, but still need the state for the delayed optimization. To
14769          * fix this:
14770          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14771          * - schedule that vblank worker _before_ calling hw_done
14772          * - at the start of commit_tail, cancel it _synchrously
14773          * - switch over to the vblank wait helper in the core after that since
14774          *   we don't need out special handling any more.
14775          */
14776         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14777
14778         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14779                 if (new_crtc_state->hw.active &&
14780                     !needs_modeset(new_crtc_state) &&
14781                     !new_crtc_state->preload_luts &&
14782                     (new_crtc_state->uapi.color_mgmt_changed ||
14783                      new_crtc_state->update_pipe))
14784                         intel_color_load_luts(new_crtc_state);
14785         }
14786
14787         /*
14788          * Now that the vblank has passed, we can go ahead and program the
14789          * optimal watermarks on platforms that need two-step watermark
14790          * programming.
14791          *
14792          * TODO: Move this (and other cleanup) to an async worker eventually.
14793          */
14794         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14795                                             new_crtc_state, i) {
14796                 /*
14797                  * Gen2 reports pipe underruns whenever all planes are disabled.
14798                  * So re-enable underrun reporting after some planes get enabled.
14799                  *
14800                  * We do this before .optimize_watermarks() so that we have a
14801                  * chance of catching underruns with the intermediate watermarks
14802                  * vs. the new plane configuration.
14803                  */
14804                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
14805                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14806
14807                 if (dev_priv->display.optimize_watermarks)
14808                         dev_priv->display.optimize_watermarks(state, crtc);
14809         }
14810
14811         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14812                 intel_post_plane_update(state, crtc);
14813
14814                 if (put_domains[i])
14815                         modeset_put_power_domains(dev_priv, put_domains[i]);
14816
14817                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14818         }
14819
14820         /* Underruns don't always raise interrupts, so check manually */
14821         intel_check_cpu_fifo_underruns(dev_priv);
14822         intel_check_pch_fifo_underruns(dev_priv);
14823
14824         if (state->modeset)
14825                 intel_verify_planes(state);
14826
14827         if (state->modeset && intel_can_enable_sagv(state))
14828                 intel_enable_sagv(dev_priv);
14829
14830         drm_atomic_helper_commit_hw_done(&state->base);
14831
14832         if (state->modeset) {
14833                 /* As one of the primary mmio accessors, KMS has a high
14834                  * likelihood of triggering bugs in unclaimed access. After we
14835                  * finish modesetting, see if an error has been flagged, and if
14836                  * so enable debugging for the next modeset - and hope we catch
14837                  * the culprit.
14838                  */
14839                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14840                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14841         }
14842         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14843
14844         /*
14845          * Defer the cleanup of the old state to a separate worker to not
14846          * impede the current task (userspace for blocking modesets) that
14847          * are executed inline. For out-of-line asynchronous modesets/flips,
14848          * deferring to a new worker seems overkill, but we would place a
14849          * schedule point (cond_resched()) here anyway to keep latencies
14850          * down.
14851          */
14852         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14853         queue_work(system_highpri_wq, &state->base.commit_work);
14854 }
14855
14856 static void intel_atomic_commit_work(struct work_struct *work)
14857 {
14858         struct intel_atomic_state *state =
14859                 container_of(work, struct intel_atomic_state, base.commit_work);
14860
14861         intel_atomic_commit_tail(state);
14862 }
14863
14864 static int __i915_sw_fence_call
14865 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14866                           enum i915_sw_fence_notify notify)
14867 {
14868         struct intel_atomic_state *state =
14869                 container_of(fence, struct intel_atomic_state, commit_ready);
14870
14871         switch (notify) {
14872         case FENCE_COMPLETE:
14873                 /* we do blocking waits in the worker, nothing to do here */
14874                 break;
14875         case FENCE_FREE:
14876                 {
14877                         struct intel_atomic_helper *helper =
14878                                 &to_i915(state->base.dev)->atomic_helper;
14879
14880                         if (llist_add(&state->freed, &helper->free_list))
14881                                 schedule_work(&helper->free_work);
14882                         break;
14883                 }
14884         }
14885
14886         return NOTIFY_DONE;
14887 }
14888
14889 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14890 {
14891         struct intel_plane_state *old_plane_state, *new_plane_state;
14892         struct intel_plane *plane;
14893         int i;
14894
14895         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14896                                              new_plane_state, i)
14897                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
14898                                         to_intel_frontbuffer(new_plane_state->hw.fb),
14899                                         plane->frontbuffer_bit);
14900 }
14901
14902 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
14903 {
14904         struct intel_crtc *crtc;
14905
14906         for_each_intel_crtc(&dev_priv->drm, crtc)
14907                 drm_modeset_lock_assert_held(&crtc->base.mutex);
14908 }
14909
14910 static int intel_atomic_commit(struct drm_device *dev,
14911                                struct drm_atomic_state *_state,
14912                                bool nonblock)
14913 {
14914         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14915         struct drm_i915_private *dev_priv = to_i915(dev);
14916         int ret = 0;
14917
14918         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14919
14920         drm_atomic_state_get(&state->base);
14921         i915_sw_fence_init(&state->commit_ready,
14922                            intel_atomic_commit_ready);
14923
14924         /*
14925          * The intel_legacy_cursor_update() fast path takes care
14926          * of avoiding the vblank waits for simple cursor
14927          * movement and flips. For cursor on/off and size changes,
14928          * we want to perform the vblank waits so that watermark
14929          * updates happen during the correct frames. Gen9+ have
14930          * double buffered watermarks and so shouldn't need this.
14931          *
14932          * Unset state->legacy_cursor_update before the call to
14933          * drm_atomic_helper_setup_commit() because otherwise
14934          * drm_atomic_helper_wait_for_flip_done() is a noop and
14935          * we get FIFO underruns because we didn't wait
14936          * for vblank.
14937          *
14938          * FIXME doing watermarks and fb cleanup from a vblank worker
14939          * (assuming we had any) would solve these problems.
14940          */
14941         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14942                 struct intel_crtc_state *new_crtc_state;
14943                 struct intel_crtc *crtc;
14944                 int i;
14945
14946                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14947                         if (new_crtc_state->wm.need_postvbl_update ||
14948                             new_crtc_state->update_wm_post)
14949                                 state->base.legacy_cursor_update = false;
14950         }
14951
14952         ret = intel_atomic_prepare_commit(state);
14953         if (ret) {
14954                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14955                 i915_sw_fence_commit(&state->commit_ready);
14956                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14957                 return ret;
14958         }
14959
14960         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14961         if (!ret)
14962                 ret = drm_atomic_helper_swap_state(&state->base, true);
14963
14964         if (ret) {
14965                 i915_sw_fence_commit(&state->commit_ready);
14966
14967                 drm_atomic_helper_cleanup_planes(dev, &state->base);
14968                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14969                 return ret;
14970         }
14971         dev_priv->wm.distrust_bios_wm = false;
14972         intel_shared_dpll_swap_state(state);
14973         intel_atomic_track_fbs(state);
14974
14975         if (state->global_state_changed) {
14976                 assert_global_state_locked(dev_priv);
14977
14978                 memcpy(dev_priv->min_cdclk, state->min_cdclk,
14979                        sizeof(state->min_cdclk));
14980                 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14981                        sizeof(state->min_voltage_level));
14982                 dev_priv->active_pipes = state->active_pipes;
14983                 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14984
14985                 intel_cdclk_swap_state(state);
14986         }
14987
14988         drm_atomic_state_get(&state->base);
14989         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
14990
14991         i915_sw_fence_commit(&state->commit_ready);
14992         if (nonblock && state->modeset) {
14993                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
14994         } else if (nonblock) {
14995                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
14996         } else {
14997                 if (state->modeset)
14998                         flush_workqueue(dev_priv->modeset_wq);
14999                 intel_atomic_commit_tail(state);
15000         }
15001
15002         return 0;
15003 }
15004
15005 struct wait_rps_boost {
15006         struct wait_queue_entry wait;
15007
15008         struct drm_crtc *crtc;
15009         struct i915_request *request;
15010 };
15011
15012 static int do_rps_boost(struct wait_queue_entry *_wait,
15013                         unsigned mode, int sync, void *key)
15014 {
15015         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15016         struct i915_request *rq = wait->request;
15017
15018         /*
15019          * If we missed the vblank, but the request is already running it
15020          * is reasonable to assume that it will complete before the next
15021          * vblank without our intervention, so leave RPS alone.
15022          */
15023         if (!i915_request_started(rq))
15024                 intel_rps_boost(rq);
15025         i915_request_put(rq);
15026
15027         drm_crtc_vblank_put(wait->crtc);
15028
15029         list_del(&wait->wait.entry);
15030         kfree(wait);
15031         return 1;
15032 }
15033
15034 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15035                                        struct dma_fence *fence)
15036 {
15037         struct wait_rps_boost *wait;
15038
15039         if (!dma_fence_is_i915(fence))
15040                 return;
15041
15042         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15043                 return;
15044
15045         if (drm_crtc_vblank_get(crtc))
15046                 return;
15047
15048         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15049         if (!wait) {
15050                 drm_crtc_vblank_put(crtc);
15051                 return;
15052         }
15053
15054         wait->request = to_request(dma_fence_get(fence));
15055         wait->crtc = crtc;
15056
15057         wait->wait.func = do_rps_boost;
15058         wait->wait.flags = 0;
15059
15060         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15061 }
15062
15063 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15064 {
15065         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15066         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15067         struct drm_framebuffer *fb = plane_state->hw.fb;
15068         struct i915_vma *vma;
15069
15070         if (plane->id == PLANE_CURSOR &&
15071             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15072                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15073                 const int align = intel_cursor_alignment(dev_priv);
15074                 int err;
15075
15076                 err = i915_gem_object_attach_phys(obj, align);
15077                 if (err)
15078                         return err;
15079         }
15080
15081         vma = intel_pin_and_fence_fb_obj(fb,
15082                                          &plane_state->view,
15083                                          intel_plane_uses_fence(plane_state),
15084                                          &plane_state->flags);
15085         if (IS_ERR(vma))
15086                 return PTR_ERR(vma);
15087
15088         plane_state->vma = vma;
15089
15090         return 0;
15091 }
15092
15093 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15094 {
15095         struct i915_vma *vma;
15096
15097         vma = fetch_and_zero(&old_plane_state->vma);
15098         if (vma)
15099                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15100 }
15101
15102 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15103 {
15104         struct i915_sched_attr attr = {
15105                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15106         };
15107
15108         i915_gem_object_wait_priority(obj, 0, &attr);
15109 }
15110
15111 /**
15112  * intel_prepare_plane_fb - Prepare fb for usage on plane
15113  * @plane: drm plane to prepare for
15114  * @_new_plane_state: the plane state being prepared
15115  *
15116  * Prepares a framebuffer for usage on a display plane.  Generally this
15117  * involves pinning the underlying object and updating the frontbuffer tracking
15118  * bits.  Some older platforms need special physical address handling for
15119  * cursor planes.
15120  *
15121  * Returns 0 on success, negative error code on failure.
15122  */
15123 int
15124 intel_prepare_plane_fb(struct drm_plane *plane,
15125                        struct drm_plane_state *_new_plane_state)
15126 {
15127         struct intel_plane_state *new_plane_state =
15128                 to_intel_plane_state(_new_plane_state);
15129         struct intel_atomic_state *intel_state =
15130                 to_intel_atomic_state(new_plane_state->uapi.state);
15131         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15132         struct drm_framebuffer *fb = new_plane_state->hw.fb;
15133         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15134         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
15135         int ret;
15136
15137         if (old_obj) {
15138                 struct intel_crtc_state *crtc_state =
15139                         intel_atomic_get_new_crtc_state(intel_state,
15140                                                         to_intel_crtc(plane->state->crtc));
15141
15142                 /* Big Hammer, we also need to ensure that any pending
15143                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15144                  * current scanout is retired before unpinning the old
15145                  * framebuffer. Note that we rely on userspace rendering
15146                  * into the buffer attached to the pipe they are waiting
15147                  * on. If not, userspace generates a GPU hang with IPEHR
15148                  * point to the MI_WAIT_FOR_EVENT.
15149                  *
15150                  * This should only fail upon a hung GPU, in which case we
15151                  * can safely continue.
15152                  */
15153                 if (needs_modeset(crtc_state)) {
15154                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15155                                                               old_obj->base.resv, NULL,
15156                                                               false, 0,
15157                                                               GFP_KERNEL);
15158                         if (ret < 0)
15159                                 return ret;
15160                 }
15161         }
15162
15163         if (new_plane_state->uapi.fence) { /* explicit fencing */
15164                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
15165                                                     new_plane_state->uapi.fence,
15166                                                     I915_FENCE_TIMEOUT,
15167                                                     GFP_KERNEL);
15168                 if (ret < 0)
15169                         return ret;
15170         }
15171
15172         if (!obj)
15173                 return 0;
15174
15175         ret = i915_gem_object_pin_pages(obj);
15176         if (ret)
15177                 return ret;
15178
15179         ret = intel_plane_pin_fb(new_plane_state);
15180
15181         i915_gem_object_unpin_pages(obj);
15182         if (ret)
15183                 return ret;
15184
15185         fb_obj_bump_render_priority(obj);
15186         intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
15187
15188         if (!new_plane_state->uapi.fence) { /* implicit fencing */
15189                 struct dma_fence *fence;
15190
15191                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
15192                                                       obj->base.resv, NULL,
15193                                                       false, I915_FENCE_TIMEOUT,
15194                                                       GFP_KERNEL);
15195                 if (ret < 0)
15196                         return ret;
15197
15198                 fence = dma_resv_get_excl_rcu(obj->base.resv);
15199                 if (fence) {
15200                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15201                                                    fence);
15202                         dma_fence_put(fence);
15203                 }
15204         } else {
15205                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
15206                                            new_plane_state->uapi.fence);
15207         }
15208
15209         /*
15210          * We declare pageflips to be interactive and so merit a small bias
15211          * towards upclocking to deliver the frame on time. By only changing
15212          * the RPS thresholds to sample more regularly and aim for higher
15213          * clocks we can hopefully deliver low power workloads (like kodi)
15214          * that are not quite steady state without resorting to forcing
15215          * maximum clocks following a vblank miss (see do_rps_boost()).
15216          */
15217         if (!intel_state->rps_interactive) {
15218                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
15219                 intel_state->rps_interactive = true;
15220         }
15221
15222         return 0;
15223 }
15224
15225 /**
15226  * intel_cleanup_plane_fb - Cleans up an fb after plane use
15227  * @plane: drm plane to clean up for
15228  * @_old_plane_state: the state from the previous modeset
15229  *
15230  * Cleans up a framebuffer that has just been removed from a plane.
15231  */
15232 void
15233 intel_cleanup_plane_fb(struct drm_plane *plane,
15234                        struct drm_plane_state *_old_plane_state)
15235 {
15236         struct intel_plane_state *old_plane_state =
15237                 to_intel_plane_state(_old_plane_state);
15238         struct intel_atomic_state *intel_state =
15239                 to_intel_atomic_state(old_plane_state->uapi.state);
15240         struct drm_i915_private *dev_priv = to_i915(plane->dev);
15241
15242         if (intel_state->rps_interactive) {
15243                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
15244                 intel_state->rps_interactive = false;
15245         }
15246
15247         /* Should only be called after a successful intel_prepare_plane_fb()! */
15248         intel_plane_unpin_fb(old_plane_state);
15249 }
15250
15251 /**
15252  * intel_plane_destroy - destroy a plane
15253  * @plane: plane to destroy
15254  *
15255  * Common destruction function for all types of planes (primary, cursor,
15256  * sprite).
15257  */
15258 void intel_plane_destroy(struct drm_plane *plane)
15259 {
15260         drm_plane_cleanup(plane);
15261         kfree(to_intel_plane(plane));
15262 }
15263
15264 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
15265                                             u32 format, u64 modifier)
15266 {
15267         switch (modifier) {
15268         case DRM_FORMAT_MOD_LINEAR:
15269         case I915_FORMAT_MOD_X_TILED:
15270                 break;
15271         default:
15272                 return false;
15273         }
15274
15275         switch (format) {
15276         case DRM_FORMAT_C8:
15277         case DRM_FORMAT_RGB565:
15278         case DRM_FORMAT_XRGB1555:
15279         case DRM_FORMAT_XRGB8888:
15280                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15281                         modifier == I915_FORMAT_MOD_X_TILED;
15282         default:
15283                 return false;
15284         }
15285 }
15286
15287 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
15288                                             u32 format, u64 modifier)
15289 {
15290         switch (modifier) {
15291         case DRM_FORMAT_MOD_LINEAR:
15292         case I915_FORMAT_MOD_X_TILED:
15293                 break;
15294         default:
15295                 return false;
15296         }
15297
15298         switch (format) {
15299         case DRM_FORMAT_C8:
15300         case DRM_FORMAT_RGB565:
15301         case DRM_FORMAT_XRGB8888:
15302         case DRM_FORMAT_XBGR8888:
15303         case DRM_FORMAT_ARGB8888:
15304         case DRM_FORMAT_ABGR8888:
15305         case DRM_FORMAT_XRGB2101010:
15306         case DRM_FORMAT_XBGR2101010:
15307         case DRM_FORMAT_ARGB2101010:
15308         case DRM_FORMAT_ABGR2101010:
15309         case DRM_FORMAT_XBGR16161616F:
15310                 return modifier == DRM_FORMAT_MOD_LINEAR ||
15311                         modifier == I915_FORMAT_MOD_X_TILED;
15312         default:
15313                 return false;
15314         }
15315 }
15316
15317 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
15318                                               u32 format, u64 modifier)
15319 {
15320         return modifier == DRM_FORMAT_MOD_LINEAR &&
15321                 format == DRM_FORMAT_ARGB8888;
15322 }
15323
15324 static const struct drm_plane_funcs i965_plane_funcs = {
15325         .update_plane = drm_atomic_helper_update_plane,
15326         .disable_plane = drm_atomic_helper_disable_plane,
15327         .destroy = intel_plane_destroy,
15328         .atomic_duplicate_state = intel_plane_duplicate_state,
15329         .atomic_destroy_state = intel_plane_destroy_state,
15330         .format_mod_supported = i965_plane_format_mod_supported,
15331 };
15332
15333 static const struct drm_plane_funcs i8xx_plane_funcs = {
15334         .update_plane = drm_atomic_helper_update_plane,
15335         .disable_plane = drm_atomic_helper_disable_plane,
15336         .destroy = intel_plane_destroy,
15337         .atomic_duplicate_state = intel_plane_duplicate_state,
15338         .atomic_destroy_state = intel_plane_destroy_state,
15339         .format_mod_supported = i8xx_plane_format_mod_supported,
15340 };
15341
15342 static int
15343 intel_legacy_cursor_update(struct drm_plane *_plane,
15344                            struct drm_crtc *_crtc,
15345                            struct drm_framebuffer *fb,
15346                            int crtc_x, int crtc_y,
15347                            unsigned int crtc_w, unsigned int crtc_h,
15348                            u32 src_x, u32 src_y,
15349                            u32 src_w, u32 src_h,
15350                            struct drm_modeset_acquire_ctx *ctx)
15351 {
15352         struct intel_plane *plane = to_intel_plane(_plane);
15353         struct intel_crtc *crtc = to_intel_crtc(_crtc);
15354         struct intel_plane_state *old_plane_state =
15355                 to_intel_plane_state(plane->base.state);
15356         struct intel_plane_state *new_plane_state;
15357         struct intel_crtc_state *crtc_state =
15358                 to_intel_crtc_state(crtc->base.state);
15359         struct intel_crtc_state *new_crtc_state;
15360         int ret;
15361
15362         /*
15363          * When crtc is inactive or there is a modeset pending,
15364          * wait for it to complete in the slowpath
15365          */
15366         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
15367             crtc_state->update_pipe)
15368                 goto slow;
15369
15370         /*
15371          * Don't do an async update if there is an outstanding commit modifying
15372          * the plane.  This prevents our async update's changes from getting
15373          * overridden by a previous synchronous update's state.
15374          */
15375         if (old_plane_state->uapi.commit &&
15376             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
15377                 goto slow;
15378
15379         /*
15380          * If any parameters change that may affect watermarks,
15381          * take the slowpath. Only changing fb or position should be
15382          * in the fastpath.
15383          */
15384         if (old_plane_state->uapi.crtc != &crtc->base ||
15385             old_plane_state->uapi.src_w != src_w ||
15386             old_plane_state->uapi.src_h != src_h ||
15387             old_plane_state->uapi.crtc_w != crtc_w ||
15388             old_plane_state->uapi.crtc_h != crtc_h ||
15389             !old_plane_state->uapi.fb != !fb)
15390                 goto slow;
15391
15392         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
15393         if (!new_plane_state)
15394                 return -ENOMEM;
15395
15396         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
15397         if (!new_crtc_state) {
15398                 ret = -ENOMEM;
15399                 goto out_free;
15400         }
15401
15402         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
15403
15404         new_plane_state->uapi.src_x = src_x;
15405         new_plane_state->uapi.src_y = src_y;
15406         new_plane_state->uapi.src_w = src_w;
15407         new_plane_state->uapi.src_h = src_h;
15408         new_plane_state->uapi.crtc_x = crtc_x;
15409         new_plane_state->uapi.crtc_y = crtc_y;
15410         new_plane_state->uapi.crtc_w = crtc_w;
15411         new_plane_state->uapi.crtc_h = crtc_h;
15412
15413         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
15414                                                   old_plane_state, new_plane_state);
15415         if (ret)
15416                 goto out_free;
15417
15418         ret = intel_plane_pin_fb(new_plane_state);
15419         if (ret)
15420                 goto out_free;
15421
15422         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
15423                                 ORIGIN_FLIP);
15424         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15425                                 to_intel_frontbuffer(new_plane_state->hw.fb),
15426                                 plane->frontbuffer_bit);
15427
15428         /* Swap plane state */
15429         plane->base.state = &new_plane_state->uapi;
15430
15431         /*
15432          * We cannot swap crtc_state as it may be in use by an atomic commit or
15433          * page flip that's running simultaneously. If we swap crtc_state and
15434          * destroy the old state, we will cause a use-after-free there.
15435          *
15436          * Only update active_planes, which is needed for our internal
15437          * bookkeeping. Either value will do the right thing when updating
15438          * planes atomically. If the cursor was part of the atomic update then
15439          * we would have taken the slowpath.
15440          */
15441         crtc_state->active_planes = new_crtc_state->active_planes;
15442
15443         if (new_plane_state->uapi.visible)
15444                 intel_update_plane(plane, crtc_state, new_plane_state);
15445         else
15446                 intel_disable_plane(plane, crtc_state);
15447
15448         intel_plane_unpin_fb(old_plane_state);
15449
15450 out_free:
15451         if (new_crtc_state)
15452                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
15453         if (ret)
15454                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
15455         else
15456                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
15457         return ret;
15458
15459 slow:
15460         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
15461                                               crtc_x, crtc_y, crtc_w, crtc_h,
15462                                               src_x, src_y, src_w, src_h, ctx);
15463 }
15464
15465 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
15466         .update_plane = intel_legacy_cursor_update,
15467         .disable_plane = drm_atomic_helper_disable_plane,
15468         .destroy = intel_plane_destroy,
15469         .atomic_duplicate_state = intel_plane_duplicate_state,
15470         .atomic_destroy_state = intel_plane_destroy_state,
15471         .format_mod_supported = intel_cursor_format_mod_supported,
15472 };
15473
15474 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
15475                                enum i9xx_plane_id i9xx_plane)
15476 {
15477         if (!HAS_FBC(dev_priv))
15478                 return false;
15479
15480         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15481                 return i9xx_plane == PLANE_A; /* tied to pipe A */
15482         else if (IS_IVYBRIDGE(dev_priv))
15483                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
15484                         i9xx_plane == PLANE_C;
15485         else if (INTEL_GEN(dev_priv) >= 4)
15486                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
15487         else
15488                 return i9xx_plane == PLANE_A;
15489 }
15490
15491 static struct intel_plane *
15492 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
15493 {
15494         struct intel_plane *plane;
15495         const struct drm_plane_funcs *plane_funcs;
15496         unsigned int supported_rotations;
15497         unsigned int possible_crtcs;
15498         const u32 *formats;
15499         int num_formats;
15500         int ret, zpos;
15501
15502         if (INTEL_GEN(dev_priv) >= 9)
15503                 return skl_universal_plane_create(dev_priv, pipe,
15504                                                   PLANE_PRIMARY);
15505
15506         plane = intel_plane_alloc();
15507         if (IS_ERR(plane))
15508                 return plane;
15509
15510         plane->pipe = pipe;
15511         /*
15512          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15513          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15514          */
15515         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
15516                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
15517         else
15518                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
15519         plane->id = PLANE_PRIMARY;
15520         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
15521
15522         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
15523         if (plane->has_fbc) {
15524                 struct intel_fbc *fbc = &dev_priv->fbc;
15525
15526                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
15527         }
15528
15529         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15530                 formats = vlv_primary_formats;
15531                 num_formats = ARRAY_SIZE(vlv_primary_formats);
15532         } else if (INTEL_GEN(dev_priv) >= 4) {
15533                 /*
15534                  * WaFP16GammaEnabling:ivb
15535                  * "Workaround : When using the 64-bit format, the plane
15536                  *  output on each color channel has one quarter amplitude.
15537                  *  It can be brought up to full amplitude by using pipe
15538                  *  gamma correction or pipe color space conversion to
15539                  *  multiply the plane output by four."
15540                  *
15541                  * There is no dedicated plane gamma for the primary plane,
15542                  * and using the pipe gamma/csc could conflict with other
15543                  * planes, so we choose not to expose fp16 on IVB primary
15544                  * planes. HSW primary planes no longer have this problem.
15545                  */
15546                 if (IS_IVYBRIDGE(dev_priv)) {
15547                         formats = ivb_primary_formats;
15548                         num_formats = ARRAY_SIZE(ivb_primary_formats);
15549                 } else {
15550                         formats = i965_primary_formats;
15551                         num_formats = ARRAY_SIZE(i965_primary_formats);
15552                 }
15553         } else {
15554                 formats = i8xx_primary_formats;
15555                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
15556         }
15557
15558         if (INTEL_GEN(dev_priv) >= 4)
15559                 plane_funcs = &i965_plane_funcs;
15560         else
15561                 plane_funcs = &i8xx_plane_funcs;
15562
15563         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15564                 plane->min_cdclk = vlv_plane_min_cdclk;
15565         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15566                 plane->min_cdclk = hsw_plane_min_cdclk;
15567         else if (IS_IVYBRIDGE(dev_priv))
15568                 plane->min_cdclk = ivb_plane_min_cdclk;
15569         else
15570                 plane->min_cdclk = i9xx_plane_min_cdclk;
15571
15572         plane->max_stride = i9xx_plane_max_stride;
15573         plane->update_plane = i9xx_update_plane;
15574         plane->disable_plane = i9xx_disable_plane;
15575         plane->get_hw_state = i9xx_plane_get_hw_state;
15576         plane->check_plane = i9xx_plane_check;
15577
15578         possible_crtcs = BIT(pipe);
15579
15580         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
15581                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15582                                                possible_crtcs, plane_funcs,
15583                                                formats, num_formats,
15584                                                i9xx_format_modifiers,
15585                                                DRM_PLANE_TYPE_PRIMARY,
15586                                                "primary %c", pipe_name(pipe));
15587         else
15588                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
15589                                                possible_crtcs, plane_funcs,
15590                                                formats, num_formats,
15591                                                i9xx_format_modifiers,
15592                                                DRM_PLANE_TYPE_PRIMARY,
15593                                                "plane %c",
15594                                                plane_name(plane->i9xx_plane));
15595         if (ret)
15596                 goto fail;
15597
15598         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
15599                 supported_rotations =
15600                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
15601                         DRM_MODE_REFLECT_X;
15602         } else if (INTEL_GEN(dev_priv) >= 4) {
15603                 supported_rotations =
15604                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
15605         } else {
15606                 supported_rotations = DRM_MODE_ROTATE_0;
15607         }
15608
15609         if (INTEL_GEN(dev_priv) >= 4)
15610                 drm_plane_create_rotation_property(&plane->base,
15611                                                    DRM_MODE_ROTATE_0,
15612                                                    supported_rotations);
15613
15614         zpos = 0;
15615         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
15616
15617         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
15618
15619         return plane;
15620
15621 fail:
15622         intel_plane_free(plane);
15623
15624         return ERR_PTR(ret);
15625 }
15626
15627 static struct intel_plane *
15628 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
15629                           enum pipe pipe)
15630 {
15631         unsigned int possible_crtcs;
15632         struct intel_plane *cursor;
15633         int ret, zpos;
15634
15635         cursor = intel_plane_alloc();
15636         if (IS_ERR(cursor))
15637                 return cursor;
15638
15639         cursor->pipe = pipe;
15640         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15641         cursor->id = PLANE_CURSOR;
15642         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15643
15644         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15645                 cursor->max_stride = i845_cursor_max_stride;
15646                 cursor->update_plane = i845_update_cursor;
15647                 cursor->disable_plane = i845_disable_cursor;
15648                 cursor->get_hw_state = i845_cursor_get_hw_state;
15649                 cursor->check_plane = i845_check_cursor;
15650         } else {
15651                 cursor->max_stride = i9xx_cursor_max_stride;
15652                 cursor->update_plane = i9xx_update_cursor;
15653                 cursor->disable_plane = i9xx_disable_cursor;
15654                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15655                 cursor->check_plane = i9xx_check_cursor;
15656         }
15657
15658         cursor->cursor.base = ~0;
15659         cursor->cursor.cntl = ~0;
15660
15661         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15662                 cursor->cursor.size = ~0;
15663
15664         possible_crtcs = BIT(pipe);
15665
15666         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15667                                        possible_crtcs, &intel_cursor_plane_funcs,
15668                                        intel_cursor_formats,
15669                                        ARRAY_SIZE(intel_cursor_formats),
15670                                        cursor_format_modifiers,
15671                                        DRM_PLANE_TYPE_CURSOR,
15672                                        "cursor %c", pipe_name(pipe));
15673         if (ret)
15674                 goto fail;
15675
15676         if (INTEL_GEN(dev_priv) >= 4)
15677                 drm_plane_create_rotation_property(&cursor->base,
15678                                                    DRM_MODE_ROTATE_0,
15679                                                    DRM_MODE_ROTATE_0 |
15680                                                    DRM_MODE_ROTATE_180);
15681
15682         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15683         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15684
15685         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15686
15687         return cursor;
15688
15689 fail:
15690         intel_plane_free(cursor);
15691
15692         return ERR_PTR(ret);
15693 }
15694
15695 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15696                                     struct intel_crtc_state *crtc_state)
15697 {
15698         struct intel_crtc_scaler_state *scaler_state =
15699                 &crtc_state->scaler_state;
15700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15701         int i;
15702
15703         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15704         if (!crtc->num_scalers)
15705                 return;
15706
15707         for (i = 0; i < crtc->num_scalers; i++) {
15708                 struct intel_scaler *scaler = &scaler_state->scalers[i];
15709
15710                 scaler->in_use = 0;
15711                 scaler->mode = 0;
15712         }
15713
15714         scaler_state->scaler_id = -1;
15715 }
15716
15717 #define INTEL_CRTC_FUNCS \
15718         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15719         .set_config = drm_atomic_helper_set_config, \
15720         .destroy = intel_crtc_destroy, \
15721         .page_flip = drm_atomic_helper_page_flip, \
15722         .atomic_duplicate_state = intel_crtc_duplicate_state, \
15723         .atomic_destroy_state = intel_crtc_destroy_state, \
15724         .set_crc_source = intel_crtc_set_crc_source, \
15725         .verify_crc_source = intel_crtc_verify_crc_source, \
15726         .get_crc_sources = intel_crtc_get_crc_sources
15727
15728 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15729         INTEL_CRTC_FUNCS,
15730
15731         .get_vblank_counter = g4x_get_vblank_counter,
15732         .enable_vblank = bdw_enable_vblank,
15733         .disable_vblank = bdw_disable_vblank,
15734 };
15735
15736 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15737         INTEL_CRTC_FUNCS,
15738
15739         .get_vblank_counter = g4x_get_vblank_counter,
15740         .enable_vblank = ilk_enable_vblank,
15741         .disable_vblank = ilk_disable_vblank,
15742 };
15743
15744 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15745         INTEL_CRTC_FUNCS,
15746
15747         .get_vblank_counter = g4x_get_vblank_counter,
15748         .enable_vblank = i965_enable_vblank,
15749         .disable_vblank = i965_disable_vblank,
15750 };
15751
15752 static const struct drm_crtc_funcs i965_crtc_funcs = {
15753         INTEL_CRTC_FUNCS,
15754
15755         .get_vblank_counter = i915_get_vblank_counter,
15756         .enable_vblank = i965_enable_vblank,
15757         .disable_vblank = i965_disable_vblank,
15758 };
15759
15760 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
15761         INTEL_CRTC_FUNCS,
15762
15763         .get_vblank_counter = i915_get_vblank_counter,
15764         .enable_vblank = i915gm_enable_vblank,
15765         .disable_vblank = i915gm_disable_vblank,
15766 };
15767
15768 static const struct drm_crtc_funcs i915_crtc_funcs = {
15769         INTEL_CRTC_FUNCS,
15770
15771         .get_vblank_counter = i915_get_vblank_counter,
15772         .enable_vblank = i8xx_enable_vblank,
15773         .disable_vblank = i8xx_disable_vblank,
15774 };
15775
15776 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15777         INTEL_CRTC_FUNCS,
15778
15779         /* no hw vblank counter */
15780         .enable_vblank = i8xx_enable_vblank,
15781         .disable_vblank = i8xx_disable_vblank,
15782 };
15783
15784 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15785 {
15786         const struct drm_crtc_funcs *funcs;
15787         struct intel_crtc *intel_crtc;
15788         struct intel_crtc_state *crtc_state = NULL;
15789         struct intel_plane *primary = NULL;
15790         struct intel_plane *cursor = NULL;
15791         int sprite, ret;
15792
15793         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15794         if (!intel_crtc)
15795                 return -ENOMEM;
15796
15797         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15798         if (!crtc_state) {
15799                 ret = -ENOMEM;
15800                 goto fail;
15801         }
15802         __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
15803         intel_crtc->config = crtc_state;
15804
15805         primary = intel_primary_plane_create(dev_priv, pipe);
15806         if (IS_ERR(primary)) {
15807                 ret = PTR_ERR(primary);
15808                 goto fail;
15809         }
15810         intel_crtc->plane_ids_mask |= BIT(primary->id);
15811
15812         for_each_sprite(dev_priv, pipe, sprite) {
15813                 struct intel_plane *plane;
15814
15815                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15816                 if (IS_ERR(plane)) {
15817                         ret = PTR_ERR(plane);
15818                         goto fail;
15819                 }
15820                 intel_crtc->plane_ids_mask |= BIT(plane->id);
15821         }
15822
15823         cursor = intel_cursor_plane_create(dev_priv, pipe);
15824         if (IS_ERR(cursor)) {
15825                 ret = PTR_ERR(cursor);
15826                 goto fail;
15827         }
15828         intel_crtc->plane_ids_mask |= BIT(cursor->id);
15829
15830         if (HAS_GMCH(dev_priv)) {
15831                 if (IS_CHERRYVIEW(dev_priv) ||
15832                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15833                         funcs = &g4x_crtc_funcs;
15834                 else if (IS_GEN(dev_priv, 4))
15835                         funcs = &i965_crtc_funcs;
15836                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
15837                         funcs = &i915gm_crtc_funcs;
15838                 else if (IS_GEN(dev_priv, 3))
15839                         funcs = &i915_crtc_funcs;
15840                 else
15841                         funcs = &i8xx_crtc_funcs;
15842         } else {
15843                 if (INTEL_GEN(dev_priv) >= 8)
15844                         funcs = &bdw_crtc_funcs;
15845                 else
15846                         funcs = &ilk_crtc_funcs;
15847         }
15848
15849         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15850                                         &primary->base, &cursor->base,
15851                                         funcs, "pipe %c", pipe_name(pipe));
15852         if (ret)
15853                 goto fail;
15854
15855         intel_crtc->pipe = pipe;
15856
15857         /* initialize shared scalers */
15858         intel_crtc_init_scalers(intel_crtc, crtc_state);
15859
15860         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15861                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15862         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15863
15864         if (INTEL_GEN(dev_priv) < 9) {
15865                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15866
15867                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15868                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15869                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15870         }
15871
15872         intel_color_init(intel_crtc);
15873
15874         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15875
15876         return 0;
15877
15878 fail:
15879         /*
15880          * drm_mode_config_cleanup() will free up any
15881          * crtcs/planes already initialized.
15882          */
15883         kfree(crtc_state);
15884         kfree(intel_crtc);
15885
15886         return ret;
15887 }
15888
15889 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15890                                       struct drm_file *file)
15891 {
15892         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15893         struct drm_crtc *drmmode_crtc;
15894         struct intel_crtc *crtc;
15895
15896         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15897         if (!drmmode_crtc)
15898                 return -ENOENT;
15899
15900         crtc = to_intel_crtc(drmmode_crtc);
15901         pipe_from_crtc_id->pipe = crtc->pipe;
15902
15903         return 0;
15904 }
15905
15906 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
15907 {
15908         struct drm_device *dev = encoder->base.dev;
15909         struct intel_encoder *source_encoder;
15910         u32 possible_clones = 0;
15911
15912         for_each_intel_encoder(dev, source_encoder) {
15913                 if (encoders_cloneable(encoder, source_encoder))
15914                         possible_clones |= drm_encoder_mask(&source_encoder->base);
15915         }
15916
15917         return possible_clones;
15918 }
15919
15920 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
15921 {
15922         struct drm_device *dev = encoder->base.dev;
15923         struct intel_crtc *crtc;
15924         u32 possible_crtcs = 0;
15925
15926         for_each_intel_crtc(dev, crtc) {
15927                 if (encoder->pipe_mask & BIT(crtc->pipe))
15928                         possible_crtcs |= drm_crtc_mask(&crtc->base);
15929         }
15930
15931         return possible_crtcs;
15932 }
15933
15934 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15935 {
15936         if (!IS_MOBILE(dev_priv))
15937                 return false;
15938
15939         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15940                 return false;
15941
15942         if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15943                 return false;
15944
15945         return true;
15946 }
15947
15948 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15949 {
15950         if (INTEL_GEN(dev_priv) >= 9)
15951                 return false;
15952
15953         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15954                 return false;
15955
15956         if (HAS_PCH_LPT_H(dev_priv) &&
15957             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15958                 return false;
15959
15960         /* DDI E can't be used if DDI A requires 4 lanes */
15961         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15962                 return false;
15963
15964         if (!dev_priv->vbt.int_crt_support)
15965                 return false;
15966
15967         return true;
15968 }
15969
15970 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15971 {
15972         int pps_num;
15973         int pps_idx;
15974
15975         if (HAS_DDI(dev_priv))
15976                 return;
15977         /*
15978          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15979          * everywhere where registers can be write protected.
15980          */
15981         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15982                 pps_num = 2;
15983         else
15984                 pps_num = 1;
15985
15986         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15987                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15988
15989                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15990                 I915_WRITE(PP_CONTROL(pps_idx), val);
15991         }
15992 }
15993
15994 static void intel_pps_init(struct drm_i915_private *dev_priv)
15995 {
15996         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15997                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15998         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15999                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16000         else
16001                 dev_priv->pps_mmio_base = PPS_BASE;
16002
16003         intel_pps_unlock_regs_wa(dev_priv);
16004 }
16005
16006 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16007 {
16008         struct intel_encoder *encoder;
16009         bool dpd_is_edp = false;
16010
16011         intel_pps_init(dev_priv);
16012
16013         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16014                 return;
16015
16016         if (INTEL_GEN(dev_priv) >= 12) {
16017                 intel_ddi_init(dev_priv, PORT_A);
16018                 intel_ddi_init(dev_priv, PORT_B);
16019                 intel_ddi_init(dev_priv, PORT_D);
16020                 intel_ddi_init(dev_priv, PORT_E);
16021                 intel_ddi_init(dev_priv, PORT_F);
16022                 intel_ddi_init(dev_priv, PORT_G);
16023                 intel_ddi_init(dev_priv, PORT_H);
16024                 intel_ddi_init(dev_priv, PORT_I);
16025                 icl_dsi_init(dev_priv);
16026         } else if (IS_ELKHARTLAKE(dev_priv)) {
16027                 intel_ddi_init(dev_priv, PORT_A);
16028                 intel_ddi_init(dev_priv, PORT_B);
16029                 intel_ddi_init(dev_priv, PORT_C);
16030                 intel_ddi_init(dev_priv, PORT_D);
16031                 icl_dsi_init(dev_priv);
16032         } else if (IS_GEN(dev_priv, 11)) {
16033                 intel_ddi_init(dev_priv, PORT_A);
16034                 intel_ddi_init(dev_priv, PORT_B);
16035                 intel_ddi_init(dev_priv, PORT_C);
16036                 intel_ddi_init(dev_priv, PORT_D);
16037                 intel_ddi_init(dev_priv, PORT_E);
16038                 /*
16039                  * On some ICL SKUs port F is not present. No strap bits for
16040                  * this, so rely on VBT.
16041                  * Work around broken VBTs on SKUs known to have no port F.
16042                  */
16043                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16044                     intel_bios_is_port_present(dev_priv, PORT_F))
16045                         intel_ddi_init(dev_priv, PORT_F);
16046
16047                 icl_dsi_init(dev_priv);
16048         } else if (IS_GEN9_LP(dev_priv)) {
16049                 /*
16050                  * FIXME: Broxton doesn't support port detection via the
16051                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16052                  * detect the ports.
16053                  */
16054                 intel_ddi_init(dev_priv, PORT_A);
16055                 intel_ddi_init(dev_priv, PORT_B);
16056                 intel_ddi_init(dev_priv, PORT_C);
16057
16058                 vlv_dsi_init(dev_priv);
16059         } else if (HAS_DDI(dev_priv)) {
16060                 int found;
16061
16062                 if (intel_ddi_crt_present(dev_priv))
16063                         intel_crt_init(dev_priv);
16064
16065                 /*
16066                  * Haswell uses DDI functions to detect digital outputs.
16067                  * On SKL pre-D0 the strap isn't connected, so we assume
16068                  * it's there.
16069                  */
16070                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16071                 /* WaIgnoreDDIAStrap: skl */
16072                 if (found || IS_GEN9_BC(dev_priv))
16073                         intel_ddi_init(dev_priv, PORT_A);
16074
16075                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16076                  * register */
16077                 found = I915_READ(SFUSE_STRAP);
16078
16079                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16080                         intel_ddi_init(dev_priv, PORT_B);
16081                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16082                         intel_ddi_init(dev_priv, PORT_C);
16083                 if (found & SFUSE_STRAP_DDID_DETECTED)
16084                         intel_ddi_init(dev_priv, PORT_D);
16085                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16086                         intel_ddi_init(dev_priv, PORT_F);
16087                 /*
16088                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16089                  */
16090                 if (IS_GEN9_BC(dev_priv) &&
16091                     intel_bios_is_port_present(dev_priv, PORT_E))
16092                         intel_ddi_init(dev_priv, PORT_E);
16093
16094         } else if (HAS_PCH_SPLIT(dev_priv)) {
16095                 int found;
16096
16097                 /*
16098                  * intel_edp_init_connector() depends on this completing first,
16099                  * to prevent the registration of both eDP and LVDS and the
16100                  * incorrect sharing of the PPS.
16101                  */
16102                 intel_lvds_init(dev_priv);
16103                 intel_crt_init(dev_priv);
16104
16105                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16106
16107                 if (ilk_has_edp_a(dev_priv))
16108                         intel_dp_init(dev_priv, DP_A, PORT_A);
16109
16110                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
16111                         /* PCH SDVOB multiplex with HDMIB */
16112                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16113                         if (!found)
16114                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16115                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
16116                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16117                 }
16118
16119                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
16120                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16121
16122                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
16123                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16124
16125                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
16126                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16127
16128                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
16129                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16130         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16131                 bool has_edp, has_port;
16132
16133                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16134                         intel_crt_init(dev_priv);
16135
16136                 /*
16137                  * The DP_DETECTED bit is the latched state of the DDC
16138                  * SDA pin at boot. However since eDP doesn't require DDC
16139                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16140                  * eDP ports may have been muxed to an alternate function.
16141                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16142                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16143                  * detect eDP ports.
16144                  *
16145                  * Sadly the straps seem to be missing sometimes even for HDMI
16146                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16147                  * and VBT for the presence of the port. Additionally we can't
16148                  * trust the port type the VBT declares as we've seen at least
16149                  * HDMI ports that the VBT claim are DP or eDP.
16150                  */
16151                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16152                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16153                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
16154                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16155                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16156                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16157
16158                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16159                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16160                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
16161                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16162                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16163                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16164
16165                 if (IS_CHERRYVIEW(dev_priv)) {
16166                         /*
16167                          * eDP not supported on port D,
16168                          * so no need to worry about it
16169                          */
16170                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
16171                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
16172                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
16173                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
16174                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
16175                 }
16176
16177                 vlv_dsi_init(dev_priv);
16178         } else if (IS_PINEVIEW(dev_priv)) {
16179                 intel_lvds_init(dev_priv);
16180                 intel_crt_init(dev_priv);
16181         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
16182                 bool found = false;
16183
16184                 if (IS_MOBILE(dev_priv))
16185                         intel_lvds_init(dev_priv);
16186
16187                 intel_crt_init(dev_priv);
16188
16189                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16190                         DRM_DEBUG_KMS("probing SDVOB\n");
16191                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
16192                         if (!found && IS_G4X(dev_priv)) {
16193                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
16194                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
16195                         }
16196
16197                         if (!found && IS_G4X(dev_priv))
16198                                 intel_dp_init(dev_priv, DP_B, PORT_B);
16199                 }
16200
16201                 /* Before G4X SDVOC doesn't have its own detect register */
16202
16203                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
16204                         DRM_DEBUG_KMS("probing SDVOC\n");
16205                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
16206                 }
16207
16208                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
16209
16210                         if (IS_G4X(dev_priv)) {
16211                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
16212                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
16213                         }
16214                         if (IS_G4X(dev_priv))
16215                                 intel_dp_init(dev_priv, DP_C, PORT_C);
16216                 }
16217
16218                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
16219                         intel_dp_init(dev_priv, DP_D, PORT_D);
16220
16221                 if (SUPPORTS_TV(dev_priv))
16222                         intel_tv_init(dev_priv);
16223         } else if (IS_GEN(dev_priv, 2)) {
16224                 if (IS_I85X(dev_priv))
16225                         intel_lvds_init(dev_priv);
16226
16227                 intel_crt_init(dev_priv);
16228                 intel_dvo_init(dev_priv);
16229         }
16230
16231         intel_psr_init(dev_priv);
16232
16233         for_each_intel_encoder(&dev_priv->drm, encoder) {
16234                 encoder->base.possible_crtcs =
16235                         intel_encoder_possible_crtcs(encoder);
16236                 encoder->base.possible_clones =
16237                         intel_encoder_possible_clones(encoder);
16238         }
16239
16240         intel_init_pch_refclk(dev_priv);
16241
16242         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
16243 }
16244
16245 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
16246 {
16247         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
16248
16249         drm_framebuffer_cleanup(fb);
16250         intel_frontbuffer_put(intel_fb->frontbuffer);
16251
16252         kfree(intel_fb);
16253 }
16254
16255 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
16256                                                 struct drm_file *file,
16257                                                 unsigned int *handle)
16258 {
16259         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16260
16261         if (obj->userptr.mm) {
16262                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
16263                 return -EINVAL;
16264         }
16265
16266         return drm_gem_handle_create(file, &obj->base, handle);
16267 }
16268
16269 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
16270                                         struct drm_file *file,
16271                                         unsigned flags, unsigned color,
16272                                         struct drm_clip_rect *clips,
16273                                         unsigned num_clips)
16274 {
16275         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16276
16277         i915_gem_object_flush_if_display(obj);
16278         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
16279
16280         return 0;
16281 }
16282
16283 static const struct drm_framebuffer_funcs intel_fb_funcs = {
16284         .destroy = intel_user_framebuffer_destroy,
16285         .create_handle = intel_user_framebuffer_create_handle,
16286         .dirty = intel_user_framebuffer_dirty,
16287 };
16288
16289 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
16290                                   struct drm_i915_gem_object *obj,
16291                                   struct drm_mode_fb_cmd2 *mode_cmd)
16292 {
16293         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
16294         struct drm_framebuffer *fb = &intel_fb->base;
16295         u32 max_stride;
16296         unsigned int tiling, stride;
16297         int ret = -EINVAL;
16298         int i;
16299
16300         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
16301         if (!intel_fb->frontbuffer)
16302                 return -ENOMEM;
16303
16304         i915_gem_object_lock(obj);
16305         tiling = i915_gem_object_get_tiling(obj);
16306         stride = i915_gem_object_get_stride(obj);
16307         i915_gem_object_unlock(obj);
16308
16309         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
16310                 /*
16311                  * If there's a fence, enforce that
16312                  * the fb modifier and tiling mode match.
16313                  */
16314                 if (tiling != I915_TILING_NONE &&
16315                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16316                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
16317                         goto err;
16318                 }
16319         } else {
16320                 if (tiling == I915_TILING_X) {
16321                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
16322                 } else if (tiling == I915_TILING_Y) {
16323                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
16324                         goto err;
16325                 }
16326         }
16327
16328         if (!drm_any_plane_has_format(&dev_priv->drm,
16329                                       mode_cmd->pixel_format,
16330                                       mode_cmd->modifier[0])) {
16331                 struct drm_format_name_buf format_name;
16332
16333                 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
16334                               drm_get_format_name(mode_cmd->pixel_format,
16335                                                   &format_name),
16336                               mode_cmd->modifier[0]);
16337                 goto err;
16338         }
16339
16340         /*
16341          * gen2/3 display engine uses the fence if present,
16342          * so the tiling mode must match the fb modifier exactly.
16343          */
16344         if (INTEL_GEN(dev_priv) < 4 &&
16345             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
16346                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
16347                 goto err;
16348         }
16349
16350         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
16351                                          mode_cmd->modifier[0]);
16352         if (mode_cmd->pitches[0] > max_stride) {
16353                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
16354                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
16355                               "tiled" : "linear",
16356                               mode_cmd->pitches[0], max_stride);
16357                 goto err;
16358         }
16359
16360         /*
16361          * If there's a fence, enforce that
16362          * the fb pitch and fence stride match.
16363          */
16364         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
16365                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
16366                               mode_cmd->pitches[0], stride);
16367                 goto err;
16368         }
16369
16370         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16371         if (mode_cmd->offsets[0] != 0)
16372                 goto err;
16373
16374         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
16375
16376         for (i = 0; i < fb->format->num_planes; i++) {
16377                 u32 stride_alignment;
16378
16379                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
16380                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
16381                         goto err;
16382                 }
16383
16384                 stride_alignment = intel_fb_stride_alignment(fb, i);
16385
16386                 /*
16387                  * Display WA #0531: skl,bxt,kbl,glk
16388                  *
16389                  * Render decompression and plane width > 3840
16390                  * combined with horizontal panning requires the
16391                  * plane stride to be a multiple of 4. We'll just
16392                  * require the entire fb to accommodate that to avoid
16393                  * potential runtime errors at plane configuration time.
16394                  */
16395                 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
16396                     is_ccs_modifier(fb->modifier))
16397                         stride_alignment *= 4;
16398
16399                 if (fb->pitches[i] & (stride_alignment - 1)) {
16400                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
16401                                       i, fb->pitches[i], stride_alignment);
16402                         goto err;
16403                 }
16404
16405                 fb->obj[i] = &obj->base;
16406         }
16407
16408         ret = intel_fill_fb_info(dev_priv, fb);
16409         if (ret)
16410                 goto err;
16411
16412         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
16413         if (ret) {
16414                 DRM_ERROR("framebuffer init failed %d\n", ret);
16415                 goto err;
16416         }
16417
16418         return 0;
16419
16420 err:
16421         intel_frontbuffer_put(intel_fb->frontbuffer);
16422         return ret;
16423 }
16424
16425 static struct drm_framebuffer *
16426 intel_user_framebuffer_create(struct drm_device *dev,
16427                               struct drm_file *filp,
16428                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
16429 {
16430         struct drm_framebuffer *fb;
16431         struct drm_i915_gem_object *obj;
16432         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
16433
16434         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
16435         if (!obj)
16436                 return ERR_PTR(-ENOENT);
16437
16438         fb = intel_framebuffer_create(obj, &mode_cmd);
16439         i915_gem_object_put(obj);
16440
16441         return fb;
16442 }
16443
16444 static void intel_atomic_state_free(struct drm_atomic_state *state)
16445 {
16446         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
16447
16448         drm_atomic_state_default_release(state);
16449
16450         i915_sw_fence_fini(&intel_state->commit_ready);
16451
16452         kfree(state);
16453 }
16454
16455 static enum drm_mode_status
16456 intel_mode_valid(struct drm_device *dev,
16457                  const struct drm_display_mode *mode)
16458 {
16459         struct drm_i915_private *dev_priv = to_i915(dev);
16460         int hdisplay_max, htotal_max;
16461         int vdisplay_max, vtotal_max;
16462
16463         /*
16464          * Can't reject DBLSCAN here because Xorg ddxen can add piles
16465          * of DBLSCAN modes to the output's mode list when they detect
16466          * the scaling mode property on the connector. And they don't
16467          * ask the kernel to validate those modes in any way until
16468          * modeset time at which point the client gets a protocol error.
16469          * So in order to not upset those clients we silently ignore the
16470          * DBLSCAN flag on such connectors. For other connectors we will
16471          * reject modes with the DBLSCAN flag in encoder->compute_config().
16472          * And we always reject DBLSCAN modes in connector->mode_valid()
16473          * as we never want such modes on the connector's mode list.
16474          */
16475
16476         if (mode->vscan > 1)
16477                 return MODE_NO_VSCAN;
16478
16479         if (mode->flags & DRM_MODE_FLAG_HSKEW)
16480                 return MODE_H_ILLEGAL;
16481
16482         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
16483                            DRM_MODE_FLAG_NCSYNC |
16484                            DRM_MODE_FLAG_PCSYNC))
16485                 return MODE_HSYNC;
16486
16487         if (mode->flags & (DRM_MODE_FLAG_BCAST |
16488                            DRM_MODE_FLAG_PIXMUX |
16489                            DRM_MODE_FLAG_CLKDIV2))
16490                 return MODE_BAD;
16491
16492         /* Transcoder timing limits */
16493         if (INTEL_GEN(dev_priv) >= 11) {
16494                 hdisplay_max = 16384;
16495                 vdisplay_max = 8192;
16496                 htotal_max = 16384;
16497                 vtotal_max = 8192;
16498         } else if (INTEL_GEN(dev_priv) >= 9 ||
16499                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
16500                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
16501                 vdisplay_max = 4096;
16502                 htotal_max = 8192;
16503                 vtotal_max = 8192;
16504         } else if (INTEL_GEN(dev_priv) >= 3) {
16505                 hdisplay_max = 4096;
16506                 vdisplay_max = 4096;
16507                 htotal_max = 8192;
16508                 vtotal_max = 8192;
16509         } else {
16510                 hdisplay_max = 2048;
16511                 vdisplay_max = 2048;
16512                 htotal_max = 4096;
16513                 vtotal_max = 4096;
16514         }
16515
16516         if (mode->hdisplay > hdisplay_max ||
16517             mode->hsync_start > htotal_max ||
16518             mode->hsync_end > htotal_max ||
16519             mode->htotal > htotal_max)
16520                 return MODE_H_ILLEGAL;
16521
16522         if (mode->vdisplay > vdisplay_max ||
16523             mode->vsync_start > vtotal_max ||
16524             mode->vsync_end > vtotal_max ||
16525             mode->vtotal > vtotal_max)
16526                 return MODE_V_ILLEGAL;
16527
16528         if (INTEL_GEN(dev_priv) >= 5) {
16529                 if (mode->hdisplay < 64 ||
16530                     mode->htotal - mode->hdisplay < 32)
16531                         return MODE_H_ILLEGAL;
16532
16533                 if (mode->vtotal - mode->vdisplay < 5)
16534                         return MODE_V_ILLEGAL;
16535         } else {
16536                 if (mode->htotal - mode->hdisplay < 32)
16537                         return MODE_H_ILLEGAL;
16538
16539                 if (mode->vtotal - mode->vdisplay < 3)
16540                         return MODE_V_ILLEGAL;
16541         }
16542
16543         return MODE_OK;
16544 }
16545
16546 enum drm_mode_status
16547 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
16548                                 const struct drm_display_mode *mode)
16549 {
16550         int plane_width_max, plane_height_max;
16551
16552         /*
16553          * intel_mode_valid() should be
16554          * sufficient on older platforms.
16555          */
16556         if (INTEL_GEN(dev_priv) < 9)
16557                 return MODE_OK;
16558
16559         /*
16560          * Most people will probably want a fullscreen
16561          * plane so let's not advertize modes that are
16562          * too big for that.
16563          */
16564         if (INTEL_GEN(dev_priv) >= 11) {
16565                 plane_width_max = 5120;
16566                 plane_height_max = 4320;
16567         } else {
16568                 plane_width_max = 5120;
16569                 plane_height_max = 4096;
16570         }
16571
16572         if (mode->hdisplay > plane_width_max)
16573                 return MODE_H_ILLEGAL;
16574
16575         if (mode->vdisplay > plane_height_max)
16576                 return MODE_V_ILLEGAL;
16577
16578         return MODE_OK;
16579 }
16580
16581 static const struct drm_mode_config_funcs intel_mode_funcs = {
16582         .fb_create = intel_user_framebuffer_create,
16583         .get_format_info = intel_get_format_info,
16584         .output_poll_changed = intel_fbdev_output_poll_changed,
16585         .mode_valid = intel_mode_valid,
16586         .atomic_check = intel_atomic_check,
16587         .atomic_commit = intel_atomic_commit,
16588         .atomic_state_alloc = intel_atomic_state_alloc,
16589         .atomic_state_clear = intel_atomic_state_clear,
16590         .atomic_state_free = intel_atomic_state_free,
16591 };
16592
16593 /**
16594  * intel_init_display_hooks - initialize the display modesetting hooks
16595  * @dev_priv: device private
16596  */
16597 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
16598 {
16599         intel_init_cdclk_hooks(dev_priv);
16600
16601         if (INTEL_GEN(dev_priv) >= 9) {
16602                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16603                 dev_priv->display.get_initial_plane_config =
16604                         skylake_get_initial_plane_config;
16605                 dev_priv->display.crtc_compute_clock =
16606                         haswell_crtc_compute_clock;
16607                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16608                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16609         } else if (HAS_DDI(dev_priv)) {
16610                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
16611                 dev_priv->display.get_initial_plane_config =
16612                         i9xx_get_initial_plane_config;
16613                 dev_priv->display.crtc_compute_clock =
16614                         haswell_crtc_compute_clock;
16615                 dev_priv->display.crtc_enable = haswell_crtc_enable;
16616                 dev_priv->display.crtc_disable = haswell_crtc_disable;
16617         } else if (HAS_PCH_SPLIT(dev_priv)) {
16618                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
16619                 dev_priv->display.get_initial_plane_config =
16620                         i9xx_get_initial_plane_config;
16621                 dev_priv->display.crtc_compute_clock =
16622                         ironlake_crtc_compute_clock;
16623                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
16624                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
16625         } else if (IS_CHERRYVIEW(dev_priv)) {
16626                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16627                 dev_priv->display.get_initial_plane_config =
16628                         i9xx_get_initial_plane_config;
16629                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
16630                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16631                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16632         } else if (IS_VALLEYVIEW(dev_priv)) {
16633                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16634                 dev_priv->display.get_initial_plane_config =
16635                         i9xx_get_initial_plane_config;
16636                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
16637                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
16638                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16639         } else if (IS_G4X(dev_priv)) {
16640                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16641                 dev_priv->display.get_initial_plane_config =
16642                         i9xx_get_initial_plane_config;
16643                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
16644                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16645                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16646         } else if (IS_PINEVIEW(dev_priv)) {
16647                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16648                 dev_priv->display.get_initial_plane_config =
16649                         i9xx_get_initial_plane_config;
16650                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
16651                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16652                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16653         } else if (!IS_GEN(dev_priv, 2)) {
16654                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16655                 dev_priv->display.get_initial_plane_config =
16656                         i9xx_get_initial_plane_config;
16657                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
16658                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16659                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16660         } else {
16661                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
16662                 dev_priv->display.get_initial_plane_config =
16663                         i9xx_get_initial_plane_config;
16664                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
16665                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
16666                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
16667         }
16668
16669         if (IS_GEN(dev_priv, 5)) {
16670                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16671         } else if (IS_GEN(dev_priv, 6)) {
16672                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16673         } else if (IS_IVYBRIDGE(dev_priv)) {
16674                 /* FIXME: detect B0+ stepping and use auto training */
16675                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16676         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16677                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16678         }
16679
16680         if (INTEL_GEN(dev_priv) >= 9)
16681                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
16682         else
16683                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
16684
16685 }
16686
16687 void intel_modeset_init_hw(struct drm_i915_private *i915)
16688 {
16689         intel_update_cdclk(i915);
16690         intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
16691         i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
16692 }
16693
16694 /*
16695  * Calculate what we think the watermarks should be for the state we've read
16696  * out of the hardware and then immediately program those watermarks so that
16697  * we ensure the hardware settings match our internal state.
16698  *
16699  * We can calculate what we think WM's should be by creating a duplicate of the
16700  * current state (which was constructed during hardware readout) and running it
16701  * through the atomic check code to calculate new watermark values in the
16702  * state object.
16703  */
16704 static void sanitize_watermarks(struct drm_device *dev)
16705 {
16706         struct drm_i915_private *dev_priv = to_i915(dev);
16707         struct drm_atomic_state *state;
16708         struct intel_atomic_state *intel_state;
16709         struct intel_crtc *crtc;
16710         struct intel_crtc_state *crtc_state;
16711         struct drm_modeset_acquire_ctx ctx;
16712         int ret;
16713         int i;
16714
16715         /* Only supported on platforms that use atomic watermark design */
16716         if (!dev_priv->display.optimize_watermarks)
16717                 return;
16718
16719         /*
16720          * We need to hold connection_mutex before calling duplicate_state so
16721          * that the connector loop is protected.
16722          */
16723         drm_modeset_acquire_init(&ctx, 0);
16724 retry:
16725         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16726         if (ret == -EDEADLK) {
16727                 drm_modeset_backoff(&ctx);
16728                 goto retry;
16729         } else if (WARN_ON(ret)) {
16730                 goto fail;
16731         }
16732
16733         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16734         if (WARN_ON(IS_ERR(state)))
16735                 goto fail;
16736
16737         intel_state = to_intel_atomic_state(state);
16738
16739         /*
16740          * Hardware readout is the only time we don't want to calculate
16741          * intermediate watermarks (since we don't trust the current
16742          * watermarks).
16743          */
16744         if (!HAS_GMCH(dev_priv))
16745                 intel_state->skip_intermediate_wm = true;
16746
16747         ret = intel_atomic_check(dev, state);
16748         if (ret) {
16749                 /*
16750                  * If we fail here, it means that the hardware appears to be
16751                  * programmed in a way that shouldn't be possible, given our
16752                  * understanding of watermark requirements.  This might mean a
16753                  * mistake in the hardware readout code or a mistake in the
16754                  * watermark calculations for a given platform.  Raise a WARN
16755                  * so that this is noticeable.
16756                  *
16757                  * If this actually happens, we'll have to just leave the
16758                  * BIOS-programmed watermarks untouched and hope for the best.
16759                  */
16760                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16761                 goto put_state;
16762         }
16763
16764         /* Write calculated watermark values back */
16765         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16766                 crtc_state->wm.need_postvbl_update = true;
16767                 dev_priv->display.optimize_watermarks(intel_state, crtc);
16768
16769                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16770         }
16771
16772 put_state:
16773         drm_atomic_state_put(state);
16774 fail:
16775         drm_modeset_drop_locks(&ctx);
16776         drm_modeset_acquire_fini(&ctx);
16777 }
16778
16779 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16780 {
16781         if (IS_GEN(dev_priv, 5)) {
16782                 u32 fdi_pll_clk =
16783                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16784
16785                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16786         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16787                 dev_priv->fdi_pll_freq = 270000;
16788         } else {
16789                 return;
16790         }
16791
16792         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16793 }
16794
16795 static int intel_initial_commit(struct drm_device *dev)
16796 {
16797         struct drm_atomic_state *state = NULL;
16798         struct drm_modeset_acquire_ctx ctx;
16799         struct intel_crtc *crtc;
16800         int ret = 0;
16801
16802         state = drm_atomic_state_alloc(dev);
16803         if (!state)
16804                 return -ENOMEM;
16805
16806         drm_modeset_acquire_init(&ctx, 0);
16807
16808 retry:
16809         state->acquire_ctx = &ctx;
16810
16811         for_each_intel_crtc(dev, crtc) {
16812                 struct intel_crtc_state *crtc_state =
16813                         intel_atomic_get_crtc_state(state, crtc);
16814
16815                 if (IS_ERR(crtc_state)) {
16816                         ret = PTR_ERR(crtc_state);
16817                         goto out;
16818                 }
16819
16820                 if (crtc_state->hw.active) {
16821                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
16822                         if (ret)
16823                                 goto out;
16824
16825                         /*
16826                          * FIXME hack to force a LUT update to avoid the
16827                          * plane update forcing the pipe gamma on without
16828                          * having a proper LUT loaded. Remove once we
16829                          * have readout for pipe gamma enable.
16830                          */
16831                         crtc_state->uapi.color_mgmt_changed = true;
16832                 }
16833         }
16834
16835         ret = drm_atomic_commit(state);
16836
16837 out:
16838         if (ret == -EDEADLK) {
16839                 drm_atomic_state_clear(state);
16840                 drm_modeset_backoff(&ctx);
16841                 goto retry;
16842         }
16843
16844         drm_atomic_state_put(state);
16845
16846         drm_modeset_drop_locks(&ctx);
16847         drm_modeset_acquire_fini(&ctx);
16848
16849         return ret;
16850 }
16851
16852 static void intel_mode_config_init(struct drm_i915_private *i915)
16853 {
16854         struct drm_mode_config *mode_config = &i915->drm.mode_config;
16855
16856         drm_mode_config_init(&i915->drm);
16857
16858         mode_config->min_width = 0;
16859         mode_config->min_height = 0;
16860
16861         mode_config->preferred_depth = 24;
16862         mode_config->prefer_shadow = 1;
16863
16864         mode_config->allow_fb_modifiers = true;
16865
16866         mode_config->funcs = &intel_mode_funcs;
16867
16868         /*
16869          * Maximum framebuffer dimensions, chosen to match
16870          * the maximum render engine surface size on gen4+.
16871          */
16872         if (INTEL_GEN(i915) >= 7) {
16873                 mode_config->max_width = 16384;
16874                 mode_config->max_height = 16384;
16875         } else if (INTEL_GEN(i915) >= 4) {
16876                 mode_config->max_width = 8192;
16877                 mode_config->max_height = 8192;
16878         } else if (IS_GEN(i915, 3)) {
16879                 mode_config->max_width = 4096;
16880                 mode_config->max_height = 4096;
16881         } else {
16882                 mode_config->max_width = 2048;
16883                 mode_config->max_height = 2048;
16884         }
16885
16886         if (IS_I845G(i915) || IS_I865G(i915)) {
16887                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
16888                 mode_config->cursor_height = 1023;
16889         } else if (IS_GEN(i915, 2)) {
16890                 mode_config->cursor_width = 64;
16891                 mode_config->cursor_height = 64;
16892         } else {
16893                 mode_config->cursor_width = 256;
16894                 mode_config->cursor_height = 256;
16895         }
16896 }
16897
16898 int intel_modeset_init(struct drm_i915_private *i915)
16899 {
16900         struct drm_device *dev = &i915->drm;
16901         enum pipe pipe;
16902         struct intel_crtc *crtc;
16903         int ret;
16904
16905         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16906         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16907                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16908
16909         intel_mode_config_init(i915);
16910
16911         ret = intel_bw_init(i915);
16912         if (ret)
16913                 return ret;
16914
16915         init_llist_head(&i915->atomic_helper.free_list);
16916         INIT_WORK(&i915->atomic_helper.free_work,
16917                   intel_atomic_helper_free_state_worker);
16918
16919         intel_init_quirks(i915);
16920
16921         intel_fbc_init(i915);
16922
16923         intel_init_pm(i915);
16924
16925         intel_panel_sanitize_ssc(i915);
16926
16927         intel_gmbus_setup(i915);
16928
16929         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16930                       INTEL_NUM_PIPES(i915),
16931                       INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
16932
16933         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
16934                 for_each_pipe(i915, pipe) {
16935                         ret = intel_crtc_init(i915, pipe);
16936                         if (ret) {
16937                                 drm_mode_config_cleanup(dev);
16938                                 return ret;
16939                         }
16940                 }
16941         }
16942
16943         intel_shared_dpll_init(dev);
16944         intel_update_fdi_pll_freq(i915);
16945
16946         intel_update_czclk(i915);
16947         intel_modeset_init_hw(i915);
16948
16949         intel_hdcp_component_init(i915);
16950
16951         if (i915->max_cdclk_freq == 0)
16952                 intel_update_max_cdclk(i915);
16953
16954         /* Just disable it once at startup */
16955         intel_vga_disable(i915);
16956         intel_setup_outputs(i915);
16957
16958         drm_modeset_lock_all(dev);
16959         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16960         drm_modeset_unlock_all(dev);
16961
16962         for_each_intel_crtc(dev, crtc) {
16963                 struct intel_initial_plane_config plane_config = {};
16964
16965                 if (!crtc->active)
16966                         continue;
16967
16968                 /*
16969                  * Note that reserving the BIOS fb up front prevents us
16970                  * from stuffing other stolen allocations like the ring
16971                  * on top.  This prevents some ugliness at boot time, and
16972                  * can even allow for smooth boot transitions if the BIOS
16973                  * fb is large enough for the active pipe configuration.
16974                  */
16975                 i915->display.get_initial_plane_config(crtc, &plane_config);
16976
16977                 /*
16978                  * If the fb is shared between multiple heads, we'll
16979                  * just get the first one.
16980                  */
16981                 intel_find_initial_plane_obj(crtc, &plane_config);
16982         }
16983
16984         /*
16985          * Make sure hardware watermarks really match the state we read out.
16986          * Note that we need to do this after reconstructing the BIOS fb's
16987          * since the watermark calculation done here will use pstate->fb.
16988          */
16989         if (!HAS_GMCH(i915))
16990                 sanitize_watermarks(dev);
16991
16992         /*
16993          * Force all active planes to recompute their states. So that on
16994          * mode_setcrtc after probe, all the intel_plane_state variables
16995          * are already calculated and there is no assert_plane warnings
16996          * during bootup.
16997          */
16998         ret = intel_initial_commit(dev);
16999         if (ret)
17000                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
17001
17002         return 0;
17003 }
17004
17005 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17006 {
17007         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17008         /* 640x480@60Hz, ~25175 kHz */
17009         struct dpll clock = {
17010                 .m1 = 18,
17011                 .m2 = 7,
17012                 .p1 = 13,
17013                 .p2 = 4,
17014                 .n = 2,
17015         };
17016         u32 dpll, fp;
17017         int i;
17018
17019         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
17020
17021         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17022                       pipe_name(pipe), clock.vco, clock.dot);
17023
17024         fp = i9xx_dpll_compute_fp(&clock);
17025         dpll = DPLL_DVO_2X_MODE |
17026                 DPLL_VGA_MODE_DIS |
17027                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17028                 PLL_P2_DIVIDE_BY_4 |
17029                 PLL_REF_INPUT_DREFCLK |
17030                 DPLL_VCO_ENABLE;
17031
17032         I915_WRITE(FP0(pipe), fp);
17033         I915_WRITE(FP1(pipe), fp);
17034
17035         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17036         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17037         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17038         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17039         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17040         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17041         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17042
17043         /*
17044          * Apparently we need to have VGA mode enabled prior to changing
17045          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17046          * dividers, even though the register value does change.
17047          */
17048         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17049         I915_WRITE(DPLL(pipe), dpll);
17050
17051         /* Wait for the clocks to stabilize. */
17052         POSTING_READ(DPLL(pipe));
17053         udelay(150);
17054
17055         /* The pixel multiplier can only be updated once the
17056          * DPLL is enabled and the clocks are stable.
17057          *
17058          * So write it again.
17059          */
17060         I915_WRITE(DPLL(pipe), dpll);
17061
17062         /* We do this three times for luck */
17063         for (i = 0; i < 3 ; i++) {
17064                 I915_WRITE(DPLL(pipe), dpll);
17065                 POSTING_READ(DPLL(pipe));
17066                 udelay(150); /* wait for warmup */
17067         }
17068
17069         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17070         POSTING_READ(PIPECONF(pipe));
17071
17072         intel_wait_for_pipe_scanline_moving(crtc);
17073 }
17074
17075 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17076 {
17077         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17078
17079         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
17080                       pipe_name(pipe));
17081
17082         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
17083         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
17084         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
17085         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
17086         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
17087
17088         I915_WRITE(PIPECONF(pipe), 0);
17089         POSTING_READ(PIPECONF(pipe));
17090
17091         intel_wait_for_pipe_scanline_stopped(crtc);
17092
17093         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
17094         POSTING_READ(DPLL(pipe));
17095 }
17096
17097 static void
17098 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
17099 {
17100         struct intel_crtc *crtc;
17101
17102         if (INTEL_GEN(dev_priv) >= 4)
17103                 return;
17104
17105         for_each_intel_crtc(&dev_priv->drm, crtc) {
17106                 struct intel_plane *plane =
17107                         to_intel_plane(crtc->base.primary);
17108                 struct intel_crtc *plane_crtc;
17109                 enum pipe pipe;
17110
17111                 if (!plane->get_hw_state(plane, &pipe))
17112                         continue;
17113
17114                 if (pipe == crtc->pipe)
17115                         continue;
17116
17117                 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
17118                               plane->base.base.id, plane->base.name);
17119
17120                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17121                 intel_plane_disable_noatomic(plane_crtc, plane);
17122         }
17123 }
17124
17125 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
17126 {
17127         struct drm_device *dev = crtc->base.dev;
17128         struct intel_encoder *encoder;
17129
17130         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
17131                 return true;
17132
17133         return false;
17134 }
17135
17136 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
17137 {
17138         struct drm_device *dev = encoder->base.dev;
17139         struct intel_connector *connector;
17140
17141         for_each_connector_on_encoder(dev, &encoder->base, connector)
17142                 return connector;
17143
17144         return NULL;
17145 }
17146
17147 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
17148                               enum pipe pch_transcoder)
17149 {
17150         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
17151                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
17152 }
17153
17154 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
17155 {
17156         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
17157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
17158         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
17159
17160         if (INTEL_GEN(dev_priv) >= 9 ||
17161             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17162                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
17163                 u32 val;
17164
17165                 if (transcoder_is_dsi(cpu_transcoder))
17166                         return;
17167
17168                 val = I915_READ(reg);
17169                 val &= ~HSW_FRAME_START_DELAY_MASK;
17170                 val |= HSW_FRAME_START_DELAY(0);
17171                 I915_WRITE(reg, val);
17172         } else {
17173                 i915_reg_t reg = PIPECONF(cpu_transcoder);
17174                 u32 val;
17175
17176                 val = I915_READ(reg);
17177                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
17178                 val |= PIPECONF_FRAME_START_DELAY(0);
17179                 I915_WRITE(reg, val);
17180         }
17181
17182         if (!crtc_state->has_pch_encoder)
17183                 return;
17184
17185         if (HAS_PCH_IBX(dev_priv)) {
17186                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
17187                 u32 val;
17188
17189                 val = I915_READ(reg);
17190                 val &= ~TRANS_FRAME_START_DELAY_MASK;
17191                 val |= TRANS_FRAME_START_DELAY(0);
17192                 I915_WRITE(reg, val);
17193         } else {
17194                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
17195                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
17196                 u32 val;
17197
17198                 val = I915_READ(reg);
17199                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
17200                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
17201                 I915_WRITE(reg, val);
17202         }
17203 }
17204
17205 static void intel_sanitize_crtc(struct intel_crtc *crtc,
17206                                 struct drm_modeset_acquire_ctx *ctx)
17207 {
17208         struct drm_device *dev = crtc->base.dev;
17209         struct drm_i915_private *dev_priv = to_i915(dev);
17210         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
17211
17212         if (crtc_state->hw.active) {
17213                 struct intel_plane *plane;
17214
17215                 /* Clear any frame start delays used for debugging left by the BIOS */
17216                 intel_sanitize_frame_start_delay(crtc_state);
17217
17218                 /* Disable everything but the primary plane */
17219                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
17220                         const struct intel_plane_state *plane_state =
17221                                 to_intel_plane_state(plane->base.state);
17222
17223                         if (plane_state->uapi.visible &&
17224                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
17225                                 intel_plane_disable_noatomic(crtc, plane);
17226                 }
17227
17228                 /*
17229                  * Disable any background color set by the BIOS, but enable the
17230                  * gamma and CSC to match how we program our planes.
17231                  */
17232                 if (INTEL_GEN(dev_priv) >= 9)
17233                         I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
17234                                    SKL_BOTTOM_COLOR_GAMMA_ENABLE |
17235                                    SKL_BOTTOM_COLOR_CSC_ENABLE);
17236         }
17237
17238         /* Adjust the state of the output pipe according to whether we
17239          * have active connectors/encoders. */
17240         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
17241                 intel_crtc_disable_noatomic(crtc, ctx);
17242
17243         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
17244                 /*
17245                  * We start out with underrun reporting disabled to avoid races.
17246                  * For correct bookkeeping mark this on active crtcs.
17247                  *
17248                  * Also on gmch platforms we dont have any hardware bits to
17249                  * disable the underrun reporting. Which means we need to start
17250                  * out with underrun reporting disabled also on inactive pipes,
17251                  * since otherwise we'll complain about the garbage we read when
17252                  * e.g. coming up after runtime pm.
17253                  *
17254                  * No protection against concurrent access is required - at
17255                  * worst a fifo underrun happens which also sets this to false.
17256                  */
17257                 crtc->cpu_fifo_underrun_disabled = true;
17258                 /*
17259                  * We track the PCH trancoder underrun reporting state
17260                  * within the crtc. With crtc for pipe A housing the underrun
17261                  * reporting state for PCH transcoder A, crtc for pipe B housing
17262                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
17263                  * and marking underrun reporting as disabled for the non-existing
17264                  * PCH transcoders B and C would prevent enabling the south
17265                  * error interrupt (see cpt_can_enable_serr_int()).
17266                  */
17267                 if (has_pch_trancoder(dev_priv, crtc->pipe))
17268                         crtc->pch_fifo_underrun_disabled = true;
17269         }
17270 }
17271
17272 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
17273 {
17274         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
17275
17276         /*
17277          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
17278          * the hardware when a high res displays plugged in. DPLL P
17279          * divider is zero, and the pipe timings are bonkers. We'll
17280          * try to disable everything in that case.
17281          *
17282          * FIXME would be nice to be able to sanitize this state
17283          * without several WARNs, but for now let's take the easy
17284          * road.
17285          */
17286         return IS_GEN(dev_priv, 6) &&
17287                 crtc_state->hw.active &&
17288                 crtc_state->shared_dpll &&
17289                 crtc_state->port_clock == 0;
17290 }
17291
17292 static void intel_sanitize_encoder(struct intel_encoder *encoder)
17293 {
17294         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
17295         struct intel_connector *connector;
17296         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
17297         struct intel_crtc_state *crtc_state = crtc ?
17298                 to_intel_crtc_state(crtc->base.state) : NULL;
17299
17300         /* We need to check both for a crtc link (meaning that the
17301          * encoder is active and trying to read from a pipe) and the
17302          * pipe itself being active. */
17303         bool has_active_crtc = crtc_state &&
17304                 crtc_state->hw.active;
17305
17306         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
17307                 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
17308                               pipe_name(crtc->pipe));
17309                 has_active_crtc = false;
17310         }
17311
17312         connector = intel_encoder_find_connector(encoder);
17313         if (connector && !has_active_crtc) {
17314                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
17315                               encoder->base.base.id,
17316                               encoder->base.name);
17317
17318                 /* Connector is active, but has no active pipe. This is
17319                  * fallout from our resume register restoring. Disable
17320                  * the encoder manually again. */
17321                 if (crtc_state) {
17322                         struct drm_encoder *best_encoder;
17323
17324                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
17325                                       encoder->base.base.id,
17326                                       encoder->base.name);
17327
17328                         /* avoid oopsing in case the hooks consult best_encoder */
17329                         best_encoder = connector->base.state->best_encoder;
17330                         connector->base.state->best_encoder = &encoder->base;
17331
17332                         if (encoder->disable)
17333                                 encoder->disable(encoder, crtc_state,
17334                                                  connector->base.state);
17335                         if (encoder->post_disable)
17336                                 encoder->post_disable(encoder, crtc_state,
17337                                                       connector->base.state);
17338
17339                         connector->base.state->best_encoder = best_encoder;
17340                 }
17341                 encoder->base.crtc = NULL;
17342
17343                 /* Inconsistent output/port/pipe state happens presumably due to
17344                  * a bug in one of the get_hw_state functions. Or someplace else
17345                  * in our code, like the register restore mess on resume. Clamp
17346                  * things to off as a safer default. */
17347
17348                 connector->base.dpms = DRM_MODE_DPMS_OFF;
17349                 connector->base.encoder = NULL;
17350         }
17351
17352         /* notify opregion of the sanitized encoder state */
17353         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
17354
17355         if (INTEL_GEN(dev_priv) >= 11)
17356                 icl_sanitize_encoder_pll_mapping(encoder);
17357 }
17358
17359 /* FIXME read out full plane state for all planes */
17360 static void readout_plane_state(struct drm_i915_private *dev_priv)
17361 {
17362         struct intel_plane *plane;
17363         struct intel_crtc *crtc;
17364
17365         for_each_intel_plane(&dev_priv->drm, plane) {
17366                 struct intel_plane_state *plane_state =
17367                         to_intel_plane_state(plane->base.state);
17368                 struct intel_crtc_state *crtc_state;
17369                 enum pipe pipe = PIPE_A;
17370                 bool visible;
17371
17372                 visible = plane->get_hw_state(plane, &pipe);
17373
17374                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17375                 crtc_state = to_intel_crtc_state(crtc->base.state);
17376
17377                 intel_set_plane_visible(crtc_state, plane_state, visible);
17378
17379                 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
17380                               plane->base.base.id, plane->base.name,
17381                               enableddisabled(visible), pipe_name(pipe));
17382         }
17383
17384         for_each_intel_crtc(&dev_priv->drm, crtc) {
17385                 struct intel_crtc_state *crtc_state =
17386                         to_intel_crtc_state(crtc->base.state);
17387
17388                 fixup_active_planes(crtc_state);
17389         }
17390 }
17391
17392 static void intel_modeset_readout_hw_state(struct drm_device *dev)
17393 {
17394         struct drm_i915_private *dev_priv = to_i915(dev);
17395         enum pipe pipe;
17396         struct intel_crtc *crtc;
17397         struct intel_encoder *encoder;
17398         struct intel_connector *connector;
17399         struct drm_connector_list_iter conn_iter;
17400         int i;
17401
17402         dev_priv->active_pipes = 0;
17403
17404         for_each_intel_crtc(dev, crtc) {
17405                 struct intel_crtc_state *crtc_state =
17406                         to_intel_crtc_state(crtc->base.state);
17407
17408                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
17409                 intel_crtc_free_hw_state(crtc_state);
17410                 memset(crtc_state, 0, sizeof(*crtc_state));
17411                 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
17412
17413                 crtc_state->hw.active = crtc_state->hw.enable =
17414                         dev_priv->display.get_pipe_config(crtc, crtc_state);
17415
17416                 crtc->base.enabled = crtc_state->hw.enable;
17417                 crtc->active = crtc_state->hw.active;
17418
17419                 if (crtc_state->hw.active)
17420                         dev_priv->active_pipes |= BIT(crtc->pipe);
17421
17422                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17423                               crtc->base.base.id, crtc->base.name,
17424                               enableddisabled(crtc_state->hw.active));
17425         }
17426
17427         readout_plane_state(dev_priv);
17428
17429         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17430                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17431
17432                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
17433                                                         &pll->state.hw_state);
17434
17435                 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
17436                     pll->info->id == DPLL_ID_EHL_DPLL4) {
17437                         pll->wakeref = intel_display_power_get(dev_priv,
17438                                                                POWER_DOMAIN_DPLL_DC_OFF);
17439                 }
17440
17441                 pll->state.crtc_mask = 0;
17442                 for_each_intel_crtc(dev, crtc) {
17443                         struct intel_crtc_state *crtc_state =
17444                                 to_intel_crtc_state(crtc->base.state);
17445
17446                         if (crtc_state->hw.active &&
17447                             crtc_state->shared_dpll == pll)
17448                                 pll->state.crtc_mask |= 1 << crtc->pipe;
17449                 }
17450                 pll->active_mask = pll->state.crtc_mask;
17451
17452                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17453                               pll->info->name, pll->state.crtc_mask, pll->on);
17454         }
17455
17456         for_each_intel_encoder(dev, encoder) {
17457                 pipe = 0;
17458
17459                 if (encoder->get_hw_state(encoder, &pipe)) {
17460                         struct intel_crtc_state *crtc_state;
17461
17462                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17463                         crtc_state = to_intel_crtc_state(crtc->base.state);
17464
17465                         encoder->base.crtc = &crtc->base;
17466                         encoder->get_config(encoder, crtc_state);
17467                 } else {
17468                         encoder->base.crtc = NULL;
17469                 }
17470
17471                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17472                               encoder->base.base.id, encoder->base.name,
17473                               enableddisabled(encoder->base.crtc),
17474                               pipe_name(pipe));
17475         }
17476
17477         drm_connector_list_iter_begin(dev, &conn_iter);
17478         for_each_intel_connector_iter(connector, &conn_iter) {
17479                 if (connector->get_hw_state(connector)) {
17480                         struct intel_crtc_state *crtc_state;
17481                         struct intel_crtc *crtc;
17482
17483                         connector->base.dpms = DRM_MODE_DPMS_ON;
17484
17485                         encoder = connector->encoder;
17486                         connector->base.encoder = &encoder->base;
17487
17488                         crtc = to_intel_crtc(encoder->base.crtc);
17489                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
17490
17491                         if (crtc_state && crtc_state->hw.active) {
17492                                 /*
17493                                  * This has to be done during hardware readout
17494                                  * because anything calling .crtc_disable may
17495                                  * rely on the connector_mask being accurate.
17496                                  */
17497                                 crtc_state->uapi.connector_mask |=
17498                                         drm_connector_mask(&connector->base);
17499                                 crtc_state->uapi.encoder_mask |=
17500                                         drm_encoder_mask(&encoder->base);
17501                         }
17502                 } else {
17503                         connector->base.dpms = DRM_MODE_DPMS_OFF;
17504                         connector->base.encoder = NULL;
17505                 }
17506                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17507                               connector->base.base.id, connector->base.name,
17508                               enableddisabled(connector->base.encoder));
17509         }
17510         drm_connector_list_iter_end(&conn_iter);
17511
17512         for_each_intel_crtc(dev, crtc) {
17513                 struct intel_bw_state *bw_state =
17514                         to_intel_bw_state(dev_priv->bw_obj.state);
17515                 struct intel_crtc_state *crtc_state =
17516                         to_intel_crtc_state(crtc->base.state);
17517                 struct intel_plane *plane;
17518                 int min_cdclk = 0;
17519
17520                 if (crtc_state->hw.active) {
17521                         struct drm_display_mode *mode = &crtc_state->hw.mode;
17522
17523                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
17524                                                     crtc_state);
17525
17526                         *mode = crtc_state->hw.adjusted_mode;
17527                         mode->hdisplay = crtc_state->pipe_src_w;
17528                         mode->vdisplay = crtc_state->pipe_src_h;
17529
17530                         /*
17531                          * The initial mode needs to be set in order to keep
17532                          * the atomic core happy. It wants a valid mode if the
17533                          * crtc's enabled, so we do the above call.
17534                          *
17535                          * But we don't set all the derived state fully, hence
17536                          * set a flag to indicate that a full recalculation is
17537                          * needed on the next commit.
17538                          */
17539                         mode->private_flags = I915_MODE_FLAG_INHERITED;
17540
17541                         intel_crtc_compute_pixel_rate(crtc_state);
17542
17543                         intel_crtc_update_active_timings(crtc_state);
17544
17545                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
17546                 }
17547
17548                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
17549                         const struct intel_plane_state *plane_state =
17550                                 to_intel_plane_state(plane->base.state);
17551
17552                         /*
17553                          * FIXME don't have the fb yet, so can't
17554                          * use intel_plane_data_rate() :(
17555                          */
17556                         if (plane_state->uapi.visible)
17557                                 crtc_state->data_rate[plane->id] =
17558                                         4 * crtc_state->pixel_rate;
17559                         /*
17560                          * FIXME don't have the fb yet, so can't
17561                          * use plane->min_cdclk() :(
17562                          */
17563                         if (plane_state->uapi.visible && plane->min_cdclk) {
17564                                 if (crtc_state->double_wide ||
17565                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
17566                                         crtc_state->min_cdclk[plane->id] =
17567                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
17568                                 else
17569                                         crtc_state->min_cdclk[plane->id] =
17570                                                 crtc_state->pixel_rate;
17571                         }
17572                         DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n",
17573                                       plane->base.base.id, plane->base.name,
17574                                       crtc_state->min_cdclk[plane->id]);
17575                 }
17576
17577                 if (crtc_state->hw.active) {
17578                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
17579                         if (WARN_ON(min_cdclk < 0))
17580                                 min_cdclk = 0;
17581                 }
17582
17583                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
17584                 dev_priv->min_voltage_level[crtc->pipe] =
17585                         crtc_state->min_voltage_level;
17586
17587                 intel_bw_crtc_update(bw_state, crtc_state);
17588
17589                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
17590         }
17591 }
17592
17593 static void
17594 get_encoder_power_domains(struct drm_i915_private *dev_priv)
17595 {
17596         struct intel_encoder *encoder;
17597
17598         for_each_intel_encoder(&dev_priv->drm, encoder) {
17599                 struct intel_crtc_state *crtc_state;
17600
17601                 if (!encoder->get_power_domains)
17602                         continue;
17603
17604                 /*
17605                  * MST-primary and inactive encoders don't have a crtc state
17606                  * and neither of these require any power domain references.
17607                  */
17608                 if (!encoder->base.crtc)
17609                         continue;
17610
17611                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
17612                 encoder->get_power_domains(encoder, crtc_state);
17613         }
17614 }
17615
17616 static void intel_early_display_was(struct drm_i915_private *dev_priv)
17617 {
17618         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
17619         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
17620                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
17621                            DARBF_GATING_DIS);
17622
17623         if (IS_HASWELL(dev_priv)) {
17624                 /*
17625                  * WaRsPkgCStateDisplayPMReq:hsw
17626                  * System hang if this isn't done before disabling all planes!
17627                  */
17628                 I915_WRITE(CHICKEN_PAR1_1,
17629                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
17630         }
17631 }
17632
17633 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
17634                                        enum port port, i915_reg_t hdmi_reg)
17635 {
17636         u32 val = I915_READ(hdmi_reg);
17637
17638         if (val & SDVO_ENABLE ||
17639             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
17640                 return;
17641
17642         DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
17643                       port_name(port));
17644
17645         val &= ~SDVO_PIPE_SEL_MASK;
17646         val |= SDVO_PIPE_SEL(PIPE_A);
17647
17648         I915_WRITE(hdmi_reg, val);
17649 }
17650
17651 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
17652                                      enum port port, i915_reg_t dp_reg)
17653 {
17654         u32 val = I915_READ(dp_reg);
17655
17656         if (val & DP_PORT_EN ||
17657             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
17658                 return;
17659
17660         DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
17661                       port_name(port));
17662
17663         val &= ~DP_PIPE_SEL_MASK;
17664         val |= DP_PIPE_SEL(PIPE_A);
17665
17666         I915_WRITE(dp_reg, val);
17667 }
17668
17669 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
17670 {
17671         /*
17672          * The BIOS may select transcoder B on some of the PCH
17673          * ports even it doesn't enable the port. This would trip
17674          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
17675          * Sanitize the transcoder select bits to prevent that. We
17676          * assume that the BIOS never actually enabled the port,
17677          * because if it did we'd actually have to toggle the port
17678          * on and back off to make the transcoder A select stick
17679          * (see. intel_dp_link_down(), intel_disable_hdmi(),
17680          * intel_disable_sdvo()).
17681          */
17682         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
17683         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
17684         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
17685
17686         /* PCH SDVOB multiplex with HDMIB */
17687         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
17688         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
17689         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
17690 }
17691
17692 /* Scan out the current hw modeset state,
17693  * and sanitizes it to the current state
17694  */
17695 static void
17696 intel_modeset_setup_hw_state(struct drm_device *dev,
17697                              struct drm_modeset_acquire_ctx *ctx)
17698 {
17699         struct drm_i915_private *dev_priv = to_i915(dev);
17700         struct intel_encoder *encoder;
17701         struct intel_crtc *crtc;
17702         intel_wakeref_t wakeref;
17703         int i;
17704
17705         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17706
17707         intel_early_display_was(dev_priv);
17708         intel_modeset_readout_hw_state(dev);
17709
17710         /* HW state is read out, now we need to sanitize this mess. */
17711
17712         /* Sanitize the TypeC port mode upfront, encoders depend on this */
17713         for_each_intel_encoder(dev, encoder) {
17714                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17715
17716                 /* We need to sanitize only the MST primary port. */
17717                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17718                     intel_phy_is_tc(dev_priv, phy))
17719                         intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17720         }
17721
17722         get_encoder_power_domains(dev_priv);
17723
17724         if (HAS_PCH_IBX(dev_priv))
17725                 ibx_sanitize_pch_ports(dev_priv);
17726
17727         /*
17728          * intel_sanitize_plane_mapping() may need to do vblank
17729          * waits, so we need vblank interrupts restored beforehand.
17730          */
17731         for_each_intel_crtc(&dev_priv->drm, crtc) {
17732                 struct intel_crtc_state *crtc_state =
17733                         to_intel_crtc_state(crtc->base.state);
17734
17735                 drm_crtc_vblank_reset(&crtc->base);
17736
17737                 if (crtc_state->hw.active)
17738                         intel_crtc_vblank_on(crtc_state);
17739         }
17740
17741         intel_sanitize_plane_mapping(dev_priv);
17742
17743         for_each_intel_encoder(dev, encoder)
17744                 intel_sanitize_encoder(encoder);
17745
17746         for_each_intel_crtc(&dev_priv->drm, crtc) {
17747                 struct intel_crtc_state *crtc_state =
17748                         to_intel_crtc_state(crtc->base.state);
17749
17750                 intel_sanitize_crtc(crtc, ctx);
17751                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17752         }
17753
17754         intel_modeset_update_connector_atomic_state(dev);
17755
17756         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17757                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17758
17759                 if (!pll->on || pll->active_mask)
17760                         continue;
17761
17762                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17763                               pll->info->name);
17764
17765                 pll->info->funcs->disable(dev_priv, pll);
17766                 pll->on = false;
17767         }
17768
17769         if (IS_G4X(dev_priv)) {
17770                 g4x_wm_get_hw_state(dev_priv);
17771                 g4x_wm_sanitize(dev_priv);
17772         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17773                 vlv_wm_get_hw_state(dev_priv);
17774                 vlv_wm_sanitize(dev_priv);
17775         } else if (INTEL_GEN(dev_priv) >= 9) {
17776                 skl_wm_get_hw_state(dev_priv);
17777         } else if (HAS_PCH_SPLIT(dev_priv)) {
17778                 ilk_wm_get_hw_state(dev_priv);
17779         }
17780
17781         for_each_intel_crtc(dev, crtc) {
17782                 struct intel_crtc_state *crtc_state =
17783                         to_intel_crtc_state(crtc->base.state);
17784                 u64 put_domains;
17785
17786                 put_domains = modeset_get_crtc_power_domains(crtc_state);
17787                 if (WARN_ON(put_domains))
17788                         modeset_put_power_domains(dev_priv, put_domains);
17789         }
17790
17791         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17792 }
17793
17794 void intel_display_resume(struct drm_device *dev)
17795 {
17796         struct drm_i915_private *dev_priv = to_i915(dev);
17797         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17798         struct drm_modeset_acquire_ctx ctx;
17799         int ret;
17800
17801         dev_priv->modeset_restore_state = NULL;
17802         if (state)
17803                 state->acquire_ctx = &ctx;
17804
17805         drm_modeset_acquire_init(&ctx, 0);
17806
17807         while (1) {
17808                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17809                 if (ret != -EDEADLK)
17810                         break;
17811
17812                 drm_modeset_backoff(&ctx);
17813         }
17814
17815         if (!ret)
17816                 ret = __intel_display_resume(dev, state, &ctx);
17817
17818         intel_enable_ipc(dev_priv);
17819         drm_modeset_drop_locks(&ctx);
17820         drm_modeset_acquire_fini(&ctx);
17821
17822         if (ret)
17823                 DRM_ERROR("Restoring old state failed with %i\n", ret);
17824         if (state)
17825                 drm_atomic_state_put(state);
17826 }
17827
17828 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
17829 {
17830         struct intel_connector *connector;
17831         struct drm_connector_list_iter conn_iter;
17832
17833         /* Kill all the work that may have been queued by hpd. */
17834         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
17835         for_each_intel_connector_iter(connector, &conn_iter) {
17836                 if (connector->modeset_retry_work.func)
17837                         cancel_work_sync(&connector->modeset_retry_work);
17838                 if (connector->hdcp.shim) {
17839                         cancel_delayed_work_sync(&connector->hdcp.check_work);
17840                         cancel_work_sync(&connector->hdcp.prop_work);
17841                 }
17842         }
17843         drm_connector_list_iter_end(&conn_iter);
17844 }
17845
17846 void intel_modeset_driver_remove(struct drm_i915_private *i915)
17847 {
17848         flush_workqueue(i915->flip_wq);
17849         flush_workqueue(i915->modeset_wq);
17850
17851         flush_work(&i915->atomic_helper.free_work);
17852         WARN_ON(!llist_empty(&i915->atomic_helper.free_list));
17853
17854         /*
17855          * Interrupts and polling as the first thing to avoid creating havoc.
17856          * Too much stuff here (turning of connectors, ...) would
17857          * experience fancy races otherwise.
17858          */
17859         intel_irq_uninstall(i915);
17860
17861         /*
17862          * Due to the hpd irq storm handling the hotplug work can re-arm the
17863          * poll handlers. Hence disable polling after hpd handling is shut down.
17864          */
17865         intel_hpd_poll_fini(i915);
17866
17867         /*
17868          * MST topology needs to be suspended so we don't have any calls to
17869          * fbdev after it's finalized. MST will be destroyed later as part of
17870          * drm_mode_config_cleanup()
17871          */
17872         intel_dp_mst_suspend(i915);
17873
17874         /* poll work can call into fbdev, hence clean that up afterwards */
17875         intel_fbdev_fini(i915);
17876
17877         intel_unregister_dsm_handler();
17878
17879         intel_fbc_global_disable(i915);
17880
17881         /* flush any delayed tasks or pending work */
17882         flush_scheduled_work();
17883
17884         intel_hdcp_component_fini(i915);
17885
17886         drm_mode_config_cleanup(&i915->drm);
17887
17888         intel_overlay_cleanup(i915);
17889
17890         intel_gmbus_teardown(i915);
17891
17892         destroy_workqueue(i915->flip_wq);
17893         destroy_workqueue(i915->modeset_wq);
17894
17895         intel_fbc_cleanup_cfb(i915);
17896 }
17897
17898 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17899
17900 struct intel_display_error_state {
17901
17902         u32 power_well_driver;
17903
17904         struct intel_cursor_error_state {
17905                 u32 control;
17906                 u32 position;
17907                 u32 base;
17908                 u32 size;
17909         } cursor[I915_MAX_PIPES];
17910
17911         struct intel_pipe_error_state {
17912                 bool power_domain_on;
17913                 u32 source;
17914                 u32 stat;
17915         } pipe[I915_MAX_PIPES];
17916
17917         struct intel_plane_error_state {
17918                 u32 control;
17919                 u32 stride;
17920                 u32 size;
17921                 u32 pos;
17922                 u32 addr;
17923                 u32 surface;
17924                 u32 tile_offset;
17925         } plane[I915_MAX_PIPES];
17926
17927         struct intel_transcoder_error_state {
17928                 bool available;
17929                 bool power_domain_on;
17930                 enum transcoder cpu_transcoder;
17931
17932                 u32 conf;
17933
17934                 u32 htotal;
17935                 u32 hblank;
17936                 u32 hsync;
17937                 u32 vtotal;
17938                 u32 vblank;
17939                 u32 vsync;
17940         } transcoder[5];
17941 };
17942
17943 struct intel_display_error_state *
17944 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17945 {
17946         struct intel_display_error_state *error;
17947         int transcoders[] = {
17948                 TRANSCODER_A,
17949                 TRANSCODER_B,
17950                 TRANSCODER_C,
17951                 TRANSCODER_D,
17952                 TRANSCODER_EDP,
17953         };
17954         int i;
17955
17956         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17957
17958         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
17959                 return NULL;
17960
17961         error = kzalloc(sizeof(*error), GFP_ATOMIC);
17962         if (error == NULL)
17963                 return NULL;
17964
17965         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17966                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17967
17968         for_each_pipe(dev_priv, i) {
17969                 error->pipe[i].power_domain_on =
17970                         __intel_display_power_is_enabled(dev_priv,
17971                                                          POWER_DOMAIN_PIPE(i));
17972                 if (!error->pipe[i].power_domain_on)
17973                         continue;
17974
17975                 error->cursor[i].control = I915_READ(CURCNTR(i));
17976                 error->cursor[i].position = I915_READ(CURPOS(i));
17977                 error->cursor[i].base = I915_READ(CURBASE(i));
17978
17979                 error->plane[i].control = I915_READ(DSPCNTR(i));
17980                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17981                 if (INTEL_GEN(dev_priv) <= 3) {
17982                         error->plane[i].size = I915_READ(DSPSIZE(i));
17983                         error->plane[i].pos = I915_READ(DSPPOS(i));
17984                 }
17985                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17986                         error->plane[i].addr = I915_READ(DSPADDR(i));
17987                 if (INTEL_GEN(dev_priv) >= 4) {
17988                         error->plane[i].surface = I915_READ(DSPSURF(i));
17989                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17990                 }
17991
17992                 error->pipe[i].source = I915_READ(PIPESRC(i));
17993
17994                 if (HAS_GMCH(dev_priv))
17995                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
17996         }
17997
17998         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17999                 enum transcoder cpu_transcoder = transcoders[i];
18000
18001                 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
18002                         continue;
18003
18004                 error->transcoder[i].available = true;
18005                 error->transcoder[i].power_domain_on =
18006                         __intel_display_power_is_enabled(dev_priv,
18007                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18008                 if (!error->transcoder[i].power_domain_on)
18009                         continue;
18010
18011                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18012
18013                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
18014                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
18015                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
18016                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
18017                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
18018                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
18019                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
18020         }
18021
18022         return error;
18023 }
18024
18025 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18026
18027 void
18028 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18029                                 struct intel_display_error_state *error)
18030 {
18031         struct drm_i915_private *dev_priv = m->i915;
18032         int i;
18033
18034         if (!error)
18035                 return;
18036
18037         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18038         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18039                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18040                            error->power_well_driver);
18041         for_each_pipe(dev_priv, i) {
18042                 err_printf(m, "Pipe [%d]:\n", i);
18043                 err_printf(m, "  Power: %s\n",
18044                            onoff(error->pipe[i].power_domain_on));
18045                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18046                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18047
18048                 err_printf(m, "Plane [%d]:\n", i);
18049                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18050                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18051                 if (INTEL_GEN(dev_priv) <= 3) {
18052                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18053                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18054                 }
18055                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18056                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18057                 if (INTEL_GEN(dev_priv) >= 4) {
18058                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18059                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18060                 }
18061
18062                 err_printf(m, "Cursor [%d]:\n", i);
18063                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18064                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18065                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18066         }
18067
18068         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18069                 if (!error->transcoder[i].available)
18070                         continue;
18071
18072                 err_printf(m, "CPU transcoder: %s\n",
18073                            transcoder_name(error->transcoder[i].cpu_transcoder));
18074                 err_printf(m, "  Power: %s\n",
18075                            onoff(error->transcoder[i].power_domain_on));
18076                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
18077                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
18078                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
18079                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
18080                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
18081                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
18082                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
18083         }
18084 }
18085
18086 #endif