2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <acpi/video.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/intel-iommu.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/dma-resv.h>
34 #include <linux/slab.h>
35 #include <linux/string_helpers.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/drm_atomic.h>
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_atomic_uapi.h>
42 #include <drm/drm_damage_helper.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_fourcc.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_privacy_screen_consumer.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/drm_rect.h>
50 #include "display/intel_audio.h"
51 #include "display/intel_crt.h"
52 #include "display/intel_ddi.h"
53 #include "display/intel_display_debugfs.h"
54 #include "display/intel_display_power.h"
55 #include "display/intel_dp.h"
56 #include "display/intel_dp_mst.h"
57 #include "display/intel_dpll.h"
58 #include "display/intel_dpll_mgr.h"
59 #include "display/intel_drrs.h"
60 #include "display/intel_dsi.h"
61 #include "display/intel_dvo.h"
62 #include "display/intel_fb.h"
63 #include "display/intel_gmbus.h"
64 #include "display/intel_hdmi.h"
65 #include "display/intel_lvds.h"
66 #include "display/intel_sdvo.h"
67 #include "display/intel_snps_phy.h"
68 #include "display/intel_tv.h"
69 #include "display/intel_vdsc.h"
70 #include "display/intel_vrr.h"
72 #include "gem/i915_gem_lmem.h"
73 #include "gem/i915_gem_object.h"
75 #include "gt/gen8_ppgtt.h"
81 #include "i915_utils.h"
83 #include "intel_acpi.h"
84 #include "intel_atomic.h"
85 #include "intel_atomic_plane.h"
87 #include "intel_cdclk.h"
88 #include "intel_color.h"
89 #include "intel_crtc.h"
90 #include "intel_crtc_state_dump.h"
92 #include "intel_display_types.h"
93 #include "intel_dmc.h"
94 #include "intel_dp_link_training.h"
95 #include "intel_dpt.h"
96 #include "intel_fbc.h"
97 #include "intel_fbdev.h"
98 #include "intel_fdi.h"
99 #include "intel_fifo_underrun.h"
100 #include "intel_frontbuffer.h"
101 #include "intel_hdcp.h"
102 #include "intel_hotplug.h"
103 #include "intel_modeset_verify.h"
104 #include "intel_modeset_setup.h"
105 #include "intel_overlay.h"
106 #include "intel_panel.h"
107 #include "intel_pch_display.h"
108 #include "intel_pch_refclk.h"
109 #include "intel_pcode.h"
110 #include "intel_pipe_crc.h"
111 #include "intel_plane_initial.h"
112 #include "intel_pm.h"
113 #include "intel_pps.h"
114 #include "intel_psr.h"
115 #include "intel_quirks.h"
116 #include "intel_sprite.h"
117 #include "intel_tc.h"
118 #include "intel_vga.h"
119 #include "i9xx_plane.h"
120 #include "skl_scaler.h"
121 #include "skl_universal_plane.h"
123 #include "vlv_dsi_pll.h"
124 #include "vlv_dsi_regs.h"
125 #include "vlv_sideband.h"
127 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
128 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
129 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
130 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
131 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
134 * intel_update_watermarks - update FIFO watermark values based on current modes
135 * @dev_priv: i915 device
137 * Calculate watermark values for the various WM regs based on current mode
138 * and plane configuration.
140 * There are several cases to deal with here:
141 * - normal (i.e. non-self-refresh)
142 * - self-refresh (SR) mode
143 * - lines are large relative to FIFO size (buffer can hold up to 2)
144 * - lines are small relative to FIFO size (buffer can hold more than 2
145 * lines), so need to account for TLB latency
147 * The normal calculation is:
148 * watermark = dotclock * bytes per pixel * latency
149 * where latency is platform & configuration dependent (we assume pessimal
152 * The SR calculation is:
153 * watermark = (trunc(latency/line time)+1) * surface width *
156 * line time = htotal / dotclock
157 * surface width = hdisplay for normal plane and 64 for cursor
158 * and latency is assumed to be high, as above.
160 * The final value programmed to the register should always be rounded up,
161 * and include an extra 2 entries to account for clock crossings.
163 * We don't use the sprite, so we can ignore that. And on Crestline we have
164 * to set the non-SR watermarks to 8.
166 void intel_update_watermarks(struct drm_i915_private *dev_priv)
168 if (dev_priv->wm_disp->update_wm)
169 dev_priv->wm_disp->update_wm(dev_priv);
172 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
173 struct intel_crtc *crtc)
175 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
176 if (dev_priv->wm_disp->compute_pipe_wm)
177 return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
181 static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
182 struct intel_crtc *crtc)
184 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
185 if (!dev_priv->wm_disp->compute_intermediate_wm)
187 if (drm_WARN_ON(&dev_priv->drm,
188 !dev_priv->wm_disp->compute_pipe_wm))
190 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
193 static bool intel_initial_watermarks(struct intel_atomic_state *state,
194 struct intel_crtc *crtc)
196 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
197 if (dev_priv->wm_disp->initial_watermarks) {
198 dev_priv->wm_disp->initial_watermarks(state, crtc);
204 static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
205 struct intel_crtc *crtc)
207 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
208 if (dev_priv->wm_disp->atomic_update_watermarks)
209 dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
212 static void intel_optimize_watermarks(struct intel_atomic_state *state,
213 struct intel_crtc *crtc)
215 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
216 if (dev_priv->wm_disp->optimize_watermarks)
217 dev_priv->wm_disp->optimize_watermarks(state, crtc);
220 static int intel_compute_global_watermarks(struct intel_atomic_state *state)
222 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
223 if (dev_priv->wm_disp->compute_global_watermarks)
224 return dev_priv->wm_disp->compute_global_watermarks(state);
228 /* returns HPLL frequency in kHz */
229 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
231 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
233 /* Obtain SKU information */
234 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
235 CCK_FUSE_HPLL_FREQ_MASK;
237 return vco_freq[hpll_freq] * 1000;
240 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
241 const char *name, u32 reg, int ref_freq)
246 val = vlv_cck_read(dev_priv, reg);
247 divider = val & CCK_FREQUENCY_VALUES;
249 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
250 (divider << CCK_FREQUENCY_STATUS_SHIFT),
251 "%s change in progress\n", name);
253 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
256 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
257 const char *name, u32 reg)
261 vlv_cck_get(dev_priv);
263 if (dev_priv->hpll_freq == 0)
264 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
266 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
268 vlv_cck_put(dev_priv);
273 static void intel_update_czclk(struct drm_i915_private *dev_priv)
275 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
278 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
279 CCK_CZ_CLOCK_CONTROL);
281 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
282 dev_priv->czclk_freq);
285 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
287 return (crtc_state->active_planes &
288 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
291 /* WA Display #0827: Gen9:all */
293 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
296 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
297 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
299 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
300 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
303 /* Wa_2006604312:icl,ehl */
305 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
309 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
310 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
312 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
313 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
316 /* Wa_1604331009:icl,jsl,ehl */
318 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
321 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
322 enable ? CURSOR_GATING_DIS : 0);
326 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
328 return crtc_state->master_transcoder != INVALID_TRANSCODER;
332 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
334 return crtc_state->sync_mode_slaves_mask != 0;
338 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
340 return is_trans_port_sync_master(crtc_state) ||
341 is_trans_port_sync_slave(crtc_state);
344 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
346 return ffs(crtc_state->bigjoiner_pipes) - 1;
349 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
351 if (crtc_state->bigjoiner_pipes)
352 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
357 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
361 return crtc_state->bigjoiner_pipes &&
362 crtc->pipe != bigjoiner_master_pipe(crtc_state);
365 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
369 return crtc_state->bigjoiner_pipes &&
370 crtc->pipe == bigjoiner_master_pipe(crtc_state);
373 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
375 return hweight8(crtc_state->bigjoiner_pipes);
378 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
380 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
382 if (intel_crtc_is_bigjoiner_slave(crtc_state))
383 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
385 return to_intel_crtc(crtc_state->uapi.crtc);
388 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
391 i915_reg_t reg = PIPEDSL(pipe);
394 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
396 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
398 return line1 != line2;
401 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
404 enum pipe pipe = crtc->pipe;
406 /* Wait for the display line to settle/start moving */
407 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
408 drm_err(&dev_priv->drm,
409 "pipe %c scanline %s wait timed out\n",
410 pipe_name(pipe), str_on_off(state));
413 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
415 wait_for_pipe_scanline_moving(crtc, false);
418 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
420 wait_for_pipe_scanline_moving(crtc, true);
424 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
426 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
429 if (DISPLAY_VER(dev_priv) >= 4) {
430 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
432 /* Wait for the Pipe State to go off */
433 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
434 PIPECONF_STATE_ENABLE, 100))
435 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
437 intel_wait_for_pipe_scanline_stopped(crtc);
441 void assert_transcoder(struct drm_i915_private *dev_priv,
442 enum transcoder cpu_transcoder, bool state)
445 enum intel_display_power_domain power_domain;
446 intel_wakeref_t wakeref;
448 /* we keep both pipes enabled on 830 */
449 if (IS_I830(dev_priv))
452 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
453 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
455 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
456 cur_state = !!(val & PIPECONF_ENABLE);
458 intel_display_power_put(dev_priv, power_domain, wakeref);
463 I915_STATE_WARN(cur_state != state,
464 "transcoder %s assertion failure (expected %s, current %s)\n",
465 transcoder_name(cpu_transcoder),
466 str_on_off(state), str_on_off(cur_state));
469 static void assert_plane(struct intel_plane *plane, bool state)
474 cur_state = plane->get_hw_state(plane, &pipe);
476 I915_STATE_WARN(cur_state != state,
477 "%s assertion failure (expected %s, current %s)\n",
478 plane->base.name, str_on_off(state),
479 str_on_off(cur_state));
482 #define assert_plane_enabled(p) assert_plane(p, true)
483 #define assert_plane_disabled(p) assert_plane(p, false)
485 static void assert_planes_disabled(struct intel_crtc *crtc)
487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
488 struct intel_plane *plane;
490 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
491 assert_plane_disabled(plane);
494 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
495 struct intel_digital_port *dig_port,
496 unsigned int expected_mask)
501 switch (dig_port->base.port) {
503 MISSING_CASE(dig_port->base.port);
506 port_mask = DPLL_PORTB_READY_MASK;
510 port_mask = DPLL_PORTC_READY_MASK;
515 port_mask = DPLL_PORTD_READY_MASK;
516 dpll_reg = DPIO_PHY_STATUS;
520 if (intel_de_wait_for_register(dev_priv, dpll_reg,
521 port_mask, expected_mask, 1000))
522 drm_WARN(&dev_priv->drm, 1,
523 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
524 dig_port->base.base.base.id, dig_port->base.base.name,
525 intel_de_read(dev_priv, dpll_reg) & port_mask,
529 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
531 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
533 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
534 enum pipe pipe = crtc->pipe;
538 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
540 assert_planes_disabled(crtc);
543 * A pipe without a PLL won't actually be able to drive bits from
544 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
547 if (HAS_GMCH(dev_priv)) {
548 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
549 assert_dsi_pll_enabled(dev_priv);
551 assert_pll_enabled(dev_priv, pipe);
553 if (new_crtc_state->has_pch_encoder) {
554 /* if driving the PCH, we need FDI enabled */
555 assert_fdi_rx_pll_enabled(dev_priv,
556 intel_crtc_pch_transcoder(crtc));
557 assert_fdi_tx_pll_enabled(dev_priv,
558 (enum pipe) cpu_transcoder);
560 /* FIXME: assert CPU port conditions for SNB+ */
563 /* Wa_22012358565:adl-p */
564 if (DISPLAY_VER(dev_priv) == 13)
565 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
566 0, PIPE_ARB_USE_PROG_SLOTS);
568 reg = PIPECONF(cpu_transcoder);
569 val = intel_de_read(dev_priv, reg);
570 if (val & PIPECONF_ENABLE) {
571 /* we keep both pipes enabled on 830 */
572 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
576 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
577 intel_de_posting_read(dev_priv, reg);
580 * Until the pipe starts PIPEDSL reads will return a stale value,
581 * which causes an apparent vblank timestamp jump when PIPEDSL
582 * resets to its proper value. That also messes up the frame count
583 * when it's derived from the timestamps. So let's wait for the
584 * pipe to start properly before we call drm_crtc_vblank_on()
586 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
587 intel_wait_for_pipe_scanline_moving(crtc);
590 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
592 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
594 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
595 enum pipe pipe = crtc->pipe;
599 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
602 * Make sure planes won't keep trying to pump pixels to us,
603 * or we might hang the display.
605 assert_planes_disabled(crtc);
607 reg = PIPECONF(cpu_transcoder);
608 val = intel_de_read(dev_priv, reg);
609 if ((val & PIPECONF_ENABLE) == 0)
613 * Double wide has implications for planes
614 * so best keep it disabled when not needed.
616 if (old_crtc_state->double_wide)
617 val &= ~PIPECONF_DOUBLE_WIDE;
619 /* Don't disable pipe or pipe PLLs if needed */
620 if (!IS_I830(dev_priv))
621 val &= ~PIPECONF_ENABLE;
623 if (DISPLAY_VER(dev_priv) >= 12)
624 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
625 FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
627 intel_de_write(dev_priv, reg, val);
628 if ((val & PIPECONF_ENABLE) == 0)
629 intel_wait_for_pipe_off(old_crtc_state);
632 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
634 unsigned int size = 0;
637 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
638 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
643 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
645 unsigned int size = 0;
648 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
649 unsigned int plane_size;
651 if (rem_info->plane[i].linear)
652 plane_size = rem_info->plane[i].size;
654 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
659 if (rem_info->plane_alignment)
660 size = ALIGN(size, rem_info->plane_alignment);
668 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
670 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
671 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
673 return DISPLAY_VER(dev_priv) < 4 ||
675 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
679 * Convert the x/y offsets into a linear offset.
680 * Only valid with 0/180 degree rotation, which is fine since linear
681 * offset is only used with linear buffers on pre-hsw and tiled buffers
682 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
684 u32 intel_fb_xy_to_linear(int x, int y,
685 const struct intel_plane_state *state,
688 const struct drm_framebuffer *fb = state->hw.fb;
689 unsigned int cpp = fb->format->cpp[color_plane];
690 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
692 return y * pitch + x * cpp;
696 * Add the x/y offsets derived from fb->offsets[] to the user
697 * specified plane src x/y offsets. The resulting x/y offsets
698 * specify the start of scanout from the beginning of the gtt mapping.
700 void intel_add_fb_offsets(int *x, int *y,
701 const struct intel_plane_state *state,
705 *x += state->view.color_plane[color_plane].x;
706 *y += state->view.color_plane[color_plane].y;
709 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
710 u32 pixel_format, u64 modifier)
712 struct intel_crtc *crtc;
713 struct intel_plane *plane;
715 if (!HAS_DISPLAY(dev_priv))
719 * We assume the primary plane for pipe A has
720 * the highest stride limits of them all,
721 * if in case pipe A is disabled, use the first pipe from pipe_mask.
723 crtc = intel_first_crtc(dev_priv);
727 plane = to_intel_plane(crtc->base.primary);
729 return plane->max_stride(plane, pixel_format, modifier,
733 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
734 struct intel_plane_state *plane_state,
737 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
739 plane_state->uapi.visible = visible;
742 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
744 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
747 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
749 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
750 struct drm_plane *plane;
753 * Active_planes aliases if multiple "primary" or cursor planes
754 * have been used on the same (or wrong) pipe. plane_mask uses
755 * unique ids, hence we can use that to reconstruct active_planes.
757 crtc_state->enabled_planes = 0;
758 crtc_state->active_planes = 0;
760 drm_for_each_plane_mask(plane, &dev_priv->drm,
761 crtc_state->uapi.plane_mask) {
762 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
763 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
767 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
768 struct intel_plane *plane)
770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
771 struct intel_crtc_state *crtc_state =
772 to_intel_crtc_state(crtc->base.state);
773 struct intel_plane_state *plane_state =
774 to_intel_plane_state(plane->base.state);
776 drm_dbg_kms(&dev_priv->drm,
777 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
778 plane->base.base.id, plane->base.name,
779 crtc->base.base.id, crtc->base.name);
781 intel_set_plane_visible(crtc_state, plane_state, false);
782 intel_plane_fixup_bitmasks(crtc_state);
783 crtc_state->data_rate[plane->id] = 0;
784 crtc_state->data_rate_y[plane->id] = 0;
785 crtc_state->rel_data_rate[plane->id] = 0;
786 crtc_state->rel_data_rate_y[plane->id] = 0;
787 crtc_state->min_cdclk[plane->id] = 0;
789 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
790 hsw_ips_disable(crtc_state)) {
791 crtc_state->ips_enabled = false;
792 intel_crtc_wait_for_next_vblank(crtc);
796 * Vblank time updates from the shadow to live plane control register
797 * are blocked if the memory self-refresh mode is active at that
798 * moment. So to make sure the plane gets truly disabled, disable
799 * first the self-refresh mode. The self-refresh enable bit in turn
800 * will be checked/applied by the HW only at the next frame start
801 * event which is after the vblank start event, so we need to have a
802 * wait-for-vblank between disabling the plane and the pipe.
804 if (HAS_GMCH(dev_priv) &&
805 intel_set_memory_cxsr(dev_priv, false))
806 intel_crtc_wait_for_next_vblank(crtc);
809 * Gen2 reports pipe underruns whenever all planes are disabled.
810 * So disable underrun reporting before all the planes get disabled.
812 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
813 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
815 intel_plane_disable_arm(plane, crtc_state);
816 intel_crtc_wait_for_next_vblank(crtc);
820 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
824 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
825 plane_state->view.color_plane[0].offset, 0);
831 __intel_display_resume(struct drm_i915_private *i915,
832 struct drm_atomic_state *state,
833 struct drm_modeset_acquire_ctx *ctx)
835 struct drm_crtc_state *crtc_state;
836 struct drm_crtc *crtc;
839 intel_modeset_setup_hw_state(i915, ctx);
840 intel_vga_redisable(i915);
846 * We've duplicated the state, pointers to the old state are invalid.
848 * Don't attempt to use the old state until we commit the duplicated state.
850 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
852 * Force recalculation even if we restore
853 * current state. With fast modeset this may not result
854 * in a modeset when the state is compatible.
856 crtc_state->mode_changed = true;
859 /* ignore any reset values/BIOS leftovers in the WM registers */
861 to_intel_atomic_state(state)->skip_intermediate_wm = true;
863 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
865 drm_WARN_ON(&i915->drm, ret == -EDEADLK);
870 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
872 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
873 intel_has_gpu_reset(to_gt(dev_priv)));
876 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
878 struct drm_device *dev = &dev_priv->drm;
879 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
880 struct drm_atomic_state *state;
883 if (!HAS_DISPLAY(dev_priv))
886 /* reset doesn't touch the display */
887 if (!dev_priv->params.force_reset_modeset_test &&
888 !gpu_reset_clobbers_display(dev_priv))
891 /* We have a modeset vs reset deadlock, defensively unbreak it. */
892 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
893 smp_mb__after_atomic();
894 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
896 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
897 drm_dbg_kms(&dev_priv->drm,
898 "Modeset potentially stuck, unbreaking through wedging\n");
899 intel_gt_set_wedged(to_gt(dev_priv));
903 * Need mode_config.mutex so that we don't
904 * trample ongoing ->detect() and whatnot.
906 mutex_lock(&dev->mode_config.mutex);
907 drm_modeset_acquire_init(ctx, 0);
909 ret = drm_modeset_lock_all_ctx(dev, ctx);
913 drm_modeset_backoff(ctx);
916 * Disabling the crtcs gracefully seems nicer. Also the
917 * g33 docs say we should at least disable all the planes.
919 state = drm_atomic_helper_duplicate_state(dev, ctx);
921 ret = PTR_ERR(state);
922 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
927 ret = drm_atomic_helper_disable_all(dev, ctx);
929 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
931 drm_atomic_state_put(state);
935 dev_priv->modeset_restore_state = state;
936 state->acquire_ctx = ctx;
939 void intel_display_finish_reset(struct drm_i915_private *i915)
941 struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
942 struct drm_atomic_state *state;
945 if (!HAS_DISPLAY(i915))
948 /* reset doesn't touch the display */
949 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
952 state = fetch_and_zero(&i915->modeset_restore_state);
956 /* reset doesn't touch the display */
957 if (!gpu_reset_clobbers_display(i915)) {
958 /* for testing only restore the display */
959 ret = __intel_display_resume(i915, state, ctx);
962 "Restoring old state failed with %i\n", ret);
965 * The display has been reset as well,
966 * so need a full re-initialization.
968 intel_pps_unlock_regs_wa(i915);
969 intel_modeset_init_hw(i915);
970 intel_init_clock_gating(i915);
971 intel_hpd_init(i915);
973 ret = __intel_display_resume(i915, state, ctx);
976 "Restoring old state failed with %i\n", ret);
978 intel_hpd_poll_disable(i915);
981 drm_atomic_state_put(state);
983 drm_modeset_drop_locks(ctx);
984 drm_modeset_acquire_fini(ctx);
985 mutex_unlock(&i915->drm.mode_config.mutex);
987 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
990 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
994 enum pipe pipe = crtc->pipe;
997 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
1000 * Display WA #1153: icl
1001 * enable hardware to bypass the alpha math
1002 * and rounding for per-pixel values 00 and 0xff
1004 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
1006 * Display WA # 1605353570: icl
1007 * Set the pixel rounding bit to 1 for allowing
1008 * passthrough of Frame buffer pixels unmodified
1011 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
1014 * Underrun recovery must always be disabled on display 13+.
1015 * DG2 chicken bit meaning is inverted compared to other platforms.
1017 if (IS_DG2(dev_priv))
1018 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
1019 else if (DISPLAY_VER(dev_priv) >= 13)
1020 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
1022 /* Wa_14010547955:dg2 */
1023 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
1024 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
1026 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
1029 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
1031 struct drm_crtc *crtc;
1034 drm_for_each_crtc(crtc, &dev_priv->drm) {
1035 struct drm_crtc_commit *commit;
1036 spin_lock(&crtc->commit_lock);
1037 commit = list_first_entry_or_null(&crtc->commit_list,
1038 struct drm_crtc_commit, commit_entry);
1039 cleanup_done = commit ?
1040 try_wait_for_completion(&commit->cleanup_done) : true;
1041 spin_unlock(&crtc->commit_lock);
1046 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
1055 * Finds the encoder associated with the given CRTC. This can only be
1056 * used when we know that the CRTC isn't feeding multiple encoders!
1058 struct intel_encoder *
1059 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
1060 const struct intel_crtc_state *crtc_state)
1062 const struct drm_connector_state *connector_state;
1063 const struct drm_connector *connector;
1064 struct intel_encoder *encoder = NULL;
1065 struct intel_crtc *master_crtc;
1066 int num_encoders = 0;
1069 master_crtc = intel_master_crtc(crtc_state);
1071 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
1072 if (connector_state->crtc != &master_crtc->base)
1075 encoder = to_intel_encoder(connector_state->best_encoder);
1079 drm_WARN(encoder->base.dev, num_encoders != 1,
1080 "%d encoders for pipe %c\n",
1081 num_encoders, pipe_name(master_crtc->pipe));
1086 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
1089 i915_reg_t dslreg = PIPEDSL(pipe);
1092 temp = intel_de_read(dev_priv, dslreg);
1094 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
1095 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
1096 drm_err(&dev_priv->drm,
1097 "mode set failed: pipe %c stuck\n",
1102 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
1104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1106 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
1107 enum pipe pipe = crtc->pipe;
1108 int width = drm_rect_width(dst);
1109 int height = drm_rect_height(dst);
1113 if (!crtc_state->pch_pfit.enabled)
1116 /* Force use of hard-coded filter coefficients
1117 * as some pre-programmed values are broken,
1120 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
1121 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1122 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
1124 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1126 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
1127 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
1130 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
1133 (void) intel_overlay_switch_off(crtc->overlay);
1135 /* Let userspace switch the overlay on again. In most cases userspace
1136 * has to recompute where to put it anyway.
1140 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1142 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1144 if (!crtc_state->nv12_planes)
1147 /* WA Display #0827: Gen9:all */
1148 if (DISPLAY_VER(dev_priv) == 9)
1154 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1156 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1158 /* Wa_2006604312:icl,ehl */
1159 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1165 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1167 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1169 /* Wa_1604331009:icl,jsl,ehl */
1170 if (is_hdr_mode(crtc_state) &&
1171 crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1172 DISPLAY_VER(dev_priv) == 11)
1178 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1179 enum pipe pipe, bool enable)
1181 if (DISPLAY_VER(i915) == 9) {
1183 * "Plane N strech max must be programmed to 11b (x1)
1184 * when Async flips are enabled on that plane."
1186 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1187 SKL_PLANE1_STRETCH_MAX_MASK,
1188 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1190 /* Also needed on HSW/BDW albeit undocumented */
1191 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1192 HSW_PRI_STRETCH_MAX_MASK,
1193 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1197 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1201 return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1202 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1205 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1206 const struct intel_crtc_state *new_crtc_state)
1208 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1209 new_crtc_state->active_planes;
1212 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1213 const struct intel_crtc_state *new_crtc_state)
1215 return old_crtc_state->active_planes &&
1216 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1219 static void intel_post_plane_update(struct intel_atomic_state *state,
1220 struct intel_crtc *crtc)
1222 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1223 const struct intel_crtc_state *old_crtc_state =
1224 intel_atomic_get_old_crtc_state(state, crtc);
1225 const struct intel_crtc_state *new_crtc_state =
1226 intel_atomic_get_new_crtc_state(state, crtc);
1227 enum pipe pipe = crtc->pipe;
1229 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1231 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1232 intel_update_watermarks(dev_priv);
1234 hsw_ips_post_update(state, crtc);
1235 intel_fbc_post_update(state, crtc);
1237 if (needs_async_flip_vtd_wa(old_crtc_state) &&
1238 !needs_async_flip_vtd_wa(new_crtc_state))
1239 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1241 if (needs_nv12_wa(old_crtc_state) &&
1242 !needs_nv12_wa(new_crtc_state))
1243 skl_wa_827(dev_priv, pipe, false);
1245 if (needs_scalerclk_wa(old_crtc_state) &&
1246 !needs_scalerclk_wa(new_crtc_state))
1247 icl_wa_scalerclkgating(dev_priv, pipe, false);
1249 if (needs_cursorclk_wa(old_crtc_state) &&
1250 !needs_cursorclk_wa(new_crtc_state))
1251 icl_wa_cursorclkgating(dev_priv, pipe, false);
1253 intel_drrs_activate(new_crtc_state);
1256 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1257 struct intel_crtc *crtc)
1259 const struct intel_crtc_state *crtc_state =
1260 intel_atomic_get_new_crtc_state(state, crtc);
1261 u8 update_planes = crtc_state->update_planes;
1262 const struct intel_plane_state *plane_state;
1263 struct intel_plane *plane;
1266 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1267 if (plane->pipe == crtc->pipe &&
1268 update_planes & BIT(plane->id))
1269 plane->enable_flip_done(plane);
1273 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1274 struct intel_crtc *crtc)
1276 const struct intel_crtc_state *crtc_state =
1277 intel_atomic_get_new_crtc_state(state, crtc);
1278 u8 update_planes = crtc_state->update_planes;
1279 const struct intel_plane_state *plane_state;
1280 struct intel_plane *plane;
1283 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1284 if (plane->pipe == crtc->pipe &&
1285 update_planes & BIT(plane->id))
1286 plane->disable_flip_done(plane);
1290 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1291 struct intel_crtc *crtc)
1293 const struct intel_crtc_state *old_crtc_state =
1294 intel_atomic_get_old_crtc_state(state, crtc);
1295 const struct intel_crtc_state *new_crtc_state =
1296 intel_atomic_get_new_crtc_state(state, crtc);
1297 u8 update_planes = new_crtc_state->update_planes;
1298 const struct intel_plane_state *old_plane_state;
1299 struct intel_plane *plane;
1300 bool need_vbl_wait = false;
1303 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1304 if (plane->need_async_flip_disable_wa &&
1305 plane->pipe == crtc->pipe &&
1306 update_planes & BIT(plane->id)) {
1308 * Apart from the async flip bit we want to
1309 * preserve the old state for the plane.
1311 plane->async_flip(plane, old_crtc_state,
1312 old_plane_state, false);
1313 need_vbl_wait = true;
1318 intel_crtc_wait_for_next_vblank(crtc);
1321 static void intel_pre_plane_update(struct intel_atomic_state *state,
1322 struct intel_crtc *crtc)
1324 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1325 const struct intel_crtc_state *old_crtc_state =
1326 intel_atomic_get_old_crtc_state(state, crtc);
1327 const struct intel_crtc_state *new_crtc_state =
1328 intel_atomic_get_new_crtc_state(state, crtc);
1329 enum pipe pipe = crtc->pipe;
1331 intel_drrs_deactivate(old_crtc_state);
1333 intel_psr_pre_plane_update(state, crtc);
1335 if (hsw_ips_pre_update(state, crtc))
1336 intel_crtc_wait_for_next_vblank(crtc);
1338 if (intel_fbc_pre_update(state, crtc))
1339 intel_crtc_wait_for_next_vblank(crtc);
1341 if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1342 needs_async_flip_vtd_wa(new_crtc_state))
1343 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1345 /* Display WA 827 */
1346 if (!needs_nv12_wa(old_crtc_state) &&
1347 needs_nv12_wa(new_crtc_state))
1348 skl_wa_827(dev_priv, pipe, true);
1350 /* Wa_2006604312:icl,ehl */
1351 if (!needs_scalerclk_wa(old_crtc_state) &&
1352 needs_scalerclk_wa(new_crtc_state))
1353 icl_wa_scalerclkgating(dev_priv, pipe, true);
1355 /* Wa_1604331009:icl,jsl,ehl */
1356 if (!needs_cursorclk_wa(old_crtc_state) &&
1357 needs_cursorclk_wa(new_crtc_state))
1358 icl_wa_cursorclkgating(dev_priv, pipe, true);
1361 * Vblank time updates from the shadow to live plane control register
1362 * are blocked if the memory self-refresh mode is active at that
1363 * moment. So to make sure the plane gets truly disabled, disable
1364 * first the self-refresh mode. The self-refresh enable bit in turn
1365 * will be checked/applied by the HW only at the next frame start
1366 * event which is after the vblank start event, so we need to have a
1367 * wait-for-vblank between disabling the plane and the pipe.
1369 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1370 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1371 intel_crtc_wait_for_next_vblank(crtc);
1374 * IVB workaround: must disable low power watermarks for at least
1375 * one frame before enabling scaling. LP watermarks can be re-enabled
1376 * when scaling is disabled.
1378 * WaCxSRDisabledForSpriteScaling:ivb
1380 if (old_crtc_state->hw.active &&
1381 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1382 intel_crtc_wait_for_next_vblank(crtc);
1385 * If we're doing a modeset we don't need to do any
1386 * pre-vblank watermark programming here.
1388 if (!intel_crtc_needs_modeset(new_crtc_state)) {
1390 * For platforms that support atomic watermarks, program the
1391 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1392 * will be the intermediate values that are safe for both pre- and
1393 * post- vblank; when vblank happens, the 'active' values will be set
1394 * to the final 'target' values and we'll do this again to get the
1395 * optimal watermarks. For gen9+ platforms, the values we program here
1396 * will be the final target values which will get automatically latched
1397 * at vblank time; no further programming will be necessary.
1399 * If a platform hasn't been transitioned to atomic watermarks yet,
1400 * we'll continue to update watermarks the old way, if flags tell
1403 if (!intel_initial_watermarks(state, crtc))
1404 if (new_crtc_state->update_wm_pre)
1405 intel_update_watermarks(dev_priv);
1409 * Gen2 reports pipe underruns whenever all planes are disabled.
1410 * So disable underrun reporting before all the planes get disabled.
1412 * We do this after .initial_watermarks() so that we have a
1413 * chance of catching underruns with the intermediate watermarks
1414 * vs. the old plane configuration.
1416 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1417 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1420 * WA for platforms where async address update enable bit
1421 * is double buffered and only latched at start of vblank.
1423 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
1424 intel_crtc_async_flip_disable_wa(state, crtc);
1427 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1428 struct intel_crtc *crtc)
1430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1431 const struct intel_crtc_state *new_crtc_state =
1432 intel_atomic_get_new_crtc_state(state, crtc);
1433 unsigned int update_mask = new_crtc_state->update_planes;
1434 const struct intel_plane_state *old_plane_state;
1435 struct intel_plane *plane;
1436 unsigned fb_bits = 0;
1439 intel_crtc_dpms_overlay_disable(crtc);
1441 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1442 if (crtc->pipe != plane->pipe ||
1443 !(update_mask & BIT(plane->id)))
1446 intel_plane_disable_arm(plane, new_crtc_state);
1448 if (old_plane_state->uapi.visible)
1449 fb_bits |= plane->frontbuffer_bit;
1452 intel_frontbuffer_flip(dev_priv, fb_bits);
1456 * intel_connector_primary_encoder - get the primary encoder for a connector
1457 * @connector: connector for which to return the encoder
1459 * Returns the primary encoder for a connector. There is a 1:1 mapping from
1460 * all connectors to their encoder, except for DP-MST connectors which have
1461 * both a virtual and a primary encoder. These DP-MST primary encoders can be
1462 * pointed to by as many DP-MST connectors as there are pipes.
1464 static struct intel_encoder *
1465 intel_connector_primary_encoder(struct intel_connector *connector)
1467 struct intel_encoder *encoder;
1469 if (connector->mst_port)
1470 return &dp_to_dig_port(connector->mst_port)->base;
1472 encoder = intel_attached_encoder(connector);
1473 drm_WARN_ON(connector->base.dev, !encoder);
1478 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1480 struct drm_i915_private *i915 = to_i915(state->base.dev);
1481 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1482 struct intel_crtc *crtc;
1483 struct drm_connector_state *new_conn_state;
1484 struct drm_connector *connector;
1488 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1489 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1491 if (i915->dpll.mgr) {
1492 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1493 if (intel_crtc_needs_modeset(new_crtc_state))
1496 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1497 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1501 if (!state->modeset)
1504 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1506 struct intel_connector *intel_connector;
1507 struct intel_encoder *encoder;
1508 struct intel_crtc *crtc;
1510 if (!intel_connector_needs_modeset(state, connector))
1513 intel_connector = to_intel_connector(connector);
1514 encoder = intel_connector_primary_encoder(intel_connector);
1515 if (!encoder->update_prepare)
1518 crtc = new_conn_state->crtc ?
1519 to_intel_crtc(new_conn_state->crtc) : NULL;
1520 encoder->update_prepare(state, encoder, crtc);
1524 static void intel_encoders_update_complete(struct intel_atomic_state *state)
1526 struct drm_connector_state *new_conn_state;
1527 struct drm_connector *connector;
1530 if (!state->modeset)
1533 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1535 struct intel_connector *intel_connector;
1536 struct intel_encoder *encoder;
1537 struct intel_crtc *crtc;
1539 if (!intel_connector_needs_modeset(state, connector))
1542 intel_connector = to_intel_connector(connector);
1543 encoder = intel_connector_primary_encoder(intel_connector);
1544 if (!encoder->update_complete)
1547 crtc = new_conn_state->crtc ?
1548 to_intel_crtc(new_conn_state->crtc) : NULL;
1549 encoder->update_complete(state, encoder, crtc);
1553 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1554 struct intel_crtc *crtc)
1556 const struct intel_crtc_state *crtc_state =
1557 intel_atomic_get_new_crtc_state(state, crtc);
1558 const struct drm_connector_state *conn_state;
1559 struct drm_connector *conn;
1562 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1563 struct intel_encoder *encoder =
1564 to_intel_encoder(conn_state->best_encoder);
1566 if (conn_state->crtc != &crtc->base)
1569 if (encoder->pre_pll_enable)
1570 encoder->pre_pll_enable(state, encoder,
1571 crtc_state, conn_state);
1575 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1576 struct intel_crtc *crtc)
1578 const struct intel_crtc_state *crtc_state =
1579 intel_atomic_get_new_crtc_state(state, crtc);
1580 const struct drm_connector_state *conn_state;
1581 struct drm_connector *conn;
1584 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1585 struct intel_encoder *encoder =
1586 to_intel_encoder(conn_state->best_encoder);
1588 if (conn_state->crtc != &crtc->base)
1591 if (encoder->pre_enable)
1592 encoder->pre_enable(state, encoder,
1593 crtc_state, conn_state);
1597 static void intel_encoders_enable(struct intel_atomic_state *state,
1598 struct intel_crtc *crtc)
1600 const struct intel_crtc_state *crtc_state =
1601 intel_atomic_get_new_crtc_state(state, crtc);
1602 const struct drm_connector_state *conn_state;
1603 struct drm_connector *conn;
1606 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1607 struct intel_encoder *encoder =
1608 to_intel_encoder(conn_state->best_encoder);
1610 if (conn_state->crtc != &crtc->base)
1613 if (encoder->enable)
1614 encoder->enable(state, encoder,
1615 crtc_state, conn_state);
1616 intel_opregion_notify_encoder(encoder, true);
1620 static void intel_encoders_disable(struct intel_atomic_state *state,
1621 struct intel_crtc *crtc)
1623 const struct intel_crtc_state *old_crtc_state =
1624 intel_atomic_get_old_crtc_state(state, crtc);
1625 const struct drm_connector_state *old_conn_state;
1626 struct drm_connector *conn;
1629 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1630 struct intel_encoder *encoder =
1631 to_intel_encoder(old_conn_state->best_encoder);
1633 if (old_conn_state->crtc != &crtc->base)
1636 intel_opregion_notify_encoder(encoder, false);
1637 if (encoder->disable)
1638 encoder->disable(state, encoder,
1639 old_crtc_state, old_conn_state);
1643 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1644 struct intel_crtc *crtc)
1646 const struct intel_crtc_state *old_crtc_state =
1647 intel_atomic_get_old_crtc_state(state, crtc);
1648 const struct drm_connector_state *old_conn_state;
1649 struct drm_connector *conn;
1652 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1653 struct intel_encoder *encoder =
1654 to_intel_encoder(old_conn_state->best_encoder);
1656 if (old_conn_state->crtc != &crtc->base)
1659 if (encoder->post_disable)
1660 encoder->post_disable(state, encoder,
1661 old_crtc_state, old_conn_state);
1665 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1666 struct intel_crtc *crtc)
1668 const struct intel_crtc_state *old_crtc_state =
1669 intel_atomic_get_old_crtc_state(state, crtc);
1670 const struct drm_connector_state *old_conn_state;
1671 struct drm_connector *conn;
1674 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1675 struct intel_encoder *encoder =
1676 to_intel_encoder(old_conn_state->best_encoder);
1678 if (old_conn_state->crtc != &crtc->base)
1681 if (encoder->post_pll_disable)
1682 encoder->post_pll_disable(state, encoder,
1683 old_crtc_state, old_conn_state);
1687 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1688 struct intel_crtc *crtc)
1690 const struct intel_crtc_state *crtc_state =
1691 intel_atomic_get_new_crtc_state(state, crtc);
1692 const struct drm_connector_state *conn_state;
1693 struct drm_connector *conn;
1696 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1697 struct intel_encoder *encoder =
1698 to_intel_encoder(conn_state->best_encoder);
1700 if (conn_state->crtc != &crtc->base)
1703 if (encoder->update_pipe)
1704 encoder->update_pipe(state, encoder,
1705 crtc_state, conn_state);
1709 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1712 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1714 plane->disable_arm(plane, crtc_state);
1717 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1720 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1722 if (crtc_state->has_pch_encoder) {
1723 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1724 &crtc_state->fdi_m_n);
1725 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1726 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1727 &crtc_state->dp_m_n);
1728 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1729 &crtc_state->dp_m2_n2);
1732 intel_set_transcoder_timings(crtc_state);
1734 ilk_set_pipeconf(crtc_state);
1737 static void ilk_crtc_enable(struct intel_atomic_state *state,
1738 struct intel_crtc *crtc)
1740 const struct intel_crtc_state *new_crtc_state =
1741 intel_atomic_get_new_crtc_state(state, crtc);
1742 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1743 enum pipe pipe = crtc->pipe;
1745 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1749 * Sometimes spurious CPU pipe underruns happen during FDI
1750 * training, at least with VGA+HDMI cloning. Suppress them.
1752 * On ILK we get an occasional spurious CPU pipe underruns
1753 * between eDP port A enable and vdd enable. Also PCH port
1754 * enable seems to result in the occasional CPU pipe underrun.
1756 * Spurious PCH underruns also occur during PCH enabling.
1758 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1759 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1761 ilk_configure_cpu_transcoder(new_crtc_state);
1763 intel_set_pipe_src_size(new_crtc_state);
1765 crtc->active = true;
1767 intel_encoders_pre_enable(state, crtc);
1769 if (new_crtc_state->has_pch_encoder) {
1770 ilk_pch_pre_enable(state, crtc);
1772 assert_fdi_tx_disabled(dev_priv, pipe);
1773 assert_fdi_rx_disabled(dev_priv, pipe);
1776 ilk_pfit_enable(new_crtc_state);
1779 * On ILK+ LUT must be loaded before the pipe is running but with
1782 intel_color_load_luts(new_crtc_state);
1783 intel_color_commit_noarm(new_crtc_state);
1784 intel_color_commit_arm(new_crtc_state);
1785 /* update DSPCNTR to configure gamma for pipe bottom color */
1786 intel_disable_primary_plane(new_crtc_state);
1788 intel_initial_watermarks(state, crtc);
1789 intel_enable_transcoder(new_crtc_state);
1791 if (new_crtc_state->has_pch_encoder)
1792 ilk_pch_enable(state, crtc);
1794 intel_crtc_vblank_on(new_crtc_state);
1796 intel_encoders_enable(state, crtc);
1798 if (HAS_PCH_CPT(dev_priv))
1799 cpt_verify_modeset(dev_priv, pipe);
1802 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1803 * And a second vblank wait is needed at least on ILK with
1804 * some interlaced HDMI modes. Let's do the double wait always
1805 * in case there are more corner cases we don't know about.
1807 if (new_crtc_state->has_pch_encoder) {
1808 intel_crtc_wait_for_next_vblank(crtc);
1809 intel_crtc_wait_for_next_vblank(crtc);
1811 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1812 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1815 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1816 enum pipe pipe, bool apply)
1818 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1819 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1826 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1829 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1834 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1835 HSW_LINETIME(crtc_state->linetime) |
1836 HSW_IPS_LINETIME(crtc_state->ips_linetime));
1839 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1843 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
1846 val = intel_de_read(dev_priv, reg);
1847 val &= ~HSW_FRAME_START_DELAY_MASK;
1848 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
1849 intel_de_write(dev_priv, reg, val);
1852 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1853 const struct intel_crtc_state *crtc_state)
1855 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1858 * Enable sequence steps 1-7 on bigjoiner master
1860 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1861 intel_encoders_pre_pll_enable(state, master_crtc);
1863 if (crtc_state->shared_dpll)
1864 intel_enable_shared_dpll(crtc_state);
1866 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1867 intel_encoders_pre_enable(state, master_crtc);
1870 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1876 if (crtc_state->has_pch_encoder) {
1877 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1878 &crtc_state->fdi_m_n);
1879 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1880 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1881 &crtc_state->dp_m_n);
1882 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1883 &crtc_state->dp_m2_n2);
1886 intel_set_transcoder_timings(crtc_state);
1888 if (cpu_transcoder != TRANSCODER_EDP)
1889 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
1890 crtc_state->pixel_multiplier - 1);
1892 hsw_set_frame_start_delay(crtc_state);
1894 hsw_set_transconf(crtc_state);
1897 static void hsw_crtc_enable(struct intel_atomic_state *state,
1898 struct intel_crtc *crtc)
1900 const struct intel_crtc_state *new_crtc_state =
1901 intel_atomic_get_new_crtc_state(state, crtc);
1902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1903 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1904 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1905 bool psl_clkgate_wa;
1907 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1910 if (!new_crtc_state->bigjoiner_pipes) {
1911 intel_encoders_pre_pll_enable(state, crtc);
1913 if (new_crtc_state->shared_dpll)
1914 intel_enable_shared_dpll(new_crtc_state);
1916 intel_encoders_pre_enable(state, crtc);
1918 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1921 intel_dsc_enable(new_crtc_state);
1923 if (DISPLAY_VER(dev_priv) >= 13)
1924 intel_uncompressed_joiner_enable(new_crtc_state);
1926 intel_set_pipe_src_size(new_crtc_state);
1927 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1928 bdw_set_pipemisc(new_crtc_state);
1930 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1931 !transcoder_is_dsi(cpu_transcoder))
1932 hsw_configure_cpu_transcoder(new_crtc_state);
1934 crtc->active = true;
1936 /* Display WA #1180: WaDisableScalarClockGating: glk */
1937 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1938 new_crtc_state->pch_pfit.enabled;
1940 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1942 if (DISPLAY_VER(dev_priv) >= 9)
1943 skl_pfit_enable(new_crtc_state);
1945 ilk_pfit_enable(new_crtc_state);
1948 * On ILK+ LUT must be loaded before the pipe is running but with
1951 intel_color_load_luts(new_crtc_state);
1952 intel_color_commit_noarm(new_crtc_state);
1953 intel_color_commit_arm(new_crtc_state);
1954 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1955 if (DISPLAY_VER(dev_priv) < 9)
1956 intel_disable_primary_plane(new_crtc_state);
1958 hsw_set_linetime_wm(new_crtc_state);
1960 if (DISPLAY_VER(dev_priv) >= 11)
1961 icl_set_pipe_chicken(new_crtc_state);
1963 intel_initial_watermarks(state, crtc);
1965 if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1966 intel_crtc_vblank_on(new_crtc_state);
1968 intel_encoders_enable(state, crtc);
1970 if (psl_clkgate_wa) {
1971 intel_crtc_wait_for_next_vblank(crtc);
1972 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1975 /* If we change the relative order between pipe/planes enabling, we need
1976 * to change the workaround. */
1977 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1978 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1979 struct intel_crtc *wa_crtc;
1981 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1983 intel_crtc_wait_for_next_vblank(wa_crtc);
1984 intel_crtc_wait_for_next_vblank(wa_crtc);
1988 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1990 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1992 enum pipe pipe = crtc->pipe;
1994 /* To avoid upsetting the power well on haswell only disable the pfit if
1995 * it's in use. The hw state code will make sure we get this right. */
1996 if (!old_crtc_state->pch_pfit.enabled)
1999 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
2000 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
2001 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
2004 static void ilk_crtc_disable(struct intel_atomic_state *state,
2005 struct intel_crtc *crtc)
2007 const struct intel_crtc_state *old_crtc_state =
2008 intel_atomic_get_old_crtc_state(state, crtc);
2009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2010 enum pipe pipe = crtc->pipe;
2013 * Sometimes spurious CPU pipe underruns happen when the
2014 * pipe is already disabled, but FDI RX/TX is still enabled.
2015 * Happens at least with VGA+HDMI cloning. Suppress them.
2017 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2018 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2020 intel_encoders_disable(state, crtc);
2022 intel_crtc_vblank_off(old_crtc_state);
2024 intel_disable_transcoder(old_crtc_state);
2026 ilk_pfit_disable(old_crtc_state);
2028 if (old_crtc_state->has_pch_encoder)
2029 ilk_pch_disable(state, crtc);
2031 intel_encoders_post_disable(state, crtc);
2033 if (old_crtc_state->has_pch_encoder)
2034 ilk_pch_post_disable(state, crtc);
2036 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2037 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
2040 static void hsw_crtc_disable(struct intel_atomic_state *state,
2041 struct intel_crtc *crtc)
2043 const struct intel_crtc_state *old_crtc_state =
2044 intel_atomic_get_old_crtc_state(state, crtc);
2047 * FIXME collapse everything to one hook.
2048 * Need care with mst->ddi interactions.
2050 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
2051 intel_encoders_disable(state, crtc);
2052 intel_encoders_post_disable(state, crtc);
2056 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
2058 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2059 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2061 if (!crtc_state->gmch_pfit.control)
2065 * The panel fitter should only be adjusted whilst the pipe is disabled,
2066 * according to register description and PRM.
2068 drm_WARN_ON(&dev_priv->drm,
2069 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
2070 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2072 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
2073 crtc_state->gmch_pfit.pgm_ratios);
2074 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
2076 /* Border color in case we don't scale up to the full screen. Black by
2077 * default, change to something else for debugging. */
2078 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
2081 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
2083 if (phy == PHY_NONE)
2085 else if (IS_ALDERLAKE_S(dev_priv))
2086 return phy <= PHY_E;
2087 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
2088 return phy <= PHY_D;
2089 else if (IS_JSL_EHL(dev_priv))
2090 return phy <= PHY_C;
2091 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
2092 return phy <= PHY_B;
2095 * DG2 outputs labelled as "combo PHY" in the bspec use
2096 * SNPS PHYs with completely different programming,
2097 * hence we always return false here.
2102 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
2104 if (IS_DG2(dev_priv))
2105 /* DG2's "TC1" output uses a SNPS PHY */
2107 else if (IS_ALDERLAKE_P(dev_priv))
2108 return phy >= PHY_F && phy <= PHY_I;
2109 else if (IS_TIGERLAKE(dev_priv))
2110 return phy >= PHY_D && phy <= PHY_I;
2111 else if (IS_ICELAKE(dev_priv))
2112 return phy >= PHY_C && phy <= PHY_F;
2117 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
2119 if (phy == PHY_NONE)
2121 else if (IS_DG2(dev_priv))
2123 * All four "combo" ports and the TC1 port (PHY E) use
2126 return phy <= PHY_E;
2131 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
2133 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
2134 return PHY_D + port - PORT_D_XELPD;
2135 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
2136 return PHY_F + port - PORT_TC1;
2137 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
2138 return PHY_B + port - PORT_TC1;
2139 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
2140 return PHY_C + port - PORT_TC1;
2141 else if (IS_JSL_EHL(i915) && port == PORT_D)
2144 return PHY_A + port - PORT_A;
2147 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
2149 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
2150 return TC_PORT_NONE;
2152 if (DISPLAY_VER(dev_priv) >= 12)
2153 return TC_PORT_1 + port - PORT_TC1;
2155 return TC_PORT_1 + port - PORT_C;
2158 enum intel_display_power_domain
2159 intel_aux_power_domain(struct intel_digital_port *dig_port)
2161 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2163 if (intel_tc_port_in_tbt_alt_mode(dig_port))
2164 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2166 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2169 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2170 struct intel_power_domain_mask *mask)
2172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2174 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2175 struct drm_encoder *encoder;
2176 enum pipe pipe = crtc->pipe;
2178 bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2180 if (!crtc_state->hw.active)
2183 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2184 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2185 if (crtc_state->pch_pfit.enabled ||
2186 crtc_state->pch_pfit.force_thru)
2187 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2189 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2190 crtc_state->uapi.encoder_mask) {
2191 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2193 set_bit(intel_encoder->power_domain, mask->bits);
2196 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2197 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2199 if (crtc_state->shared_dpll)
2200 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2202 if (crtc_state->dsc.compression_enable)
2203 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2206 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2207 struct intel_power_domain_mask *old_domains)
2209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2211 enum intel_display_power_domain domain;
2212 struct intel_power_domain_mask domains, new_domains;
2214 get_crtc_power_domains(crtc_state, &domains);
2216 bitmap_andnot(new_domains.bits,
2218 crtc->enabled_power_domains.mask.bits,
2220 bitmap_andnot(old_domains->bits,
2221 crtc->enabled_power_domains.mask.bits,
2225 for_each_power_domain(domain, &new_domains)
2226 intel_display_power_get_in_set(dev_priv,
2227 &crtc->enabled_power_domains,
2231 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2232 struct intel_power_domain_mask *domains)
2234 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2235 &crtc->enabled_power_domains,
2239 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2241 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2242 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2244 if (intel_crtc_has_dp_encoder(crtc_state)) {
2245 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2246 &crtc_state->dp_m_n);
2247 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2248 &crtc_state->dp_m2_n2);
2251 intel_set_transcoder_timings(crtc_state);
2253 i9xx_set_pipeconf(crtc_state);
2256 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2257 struct intel_crtc *crtc)
2259 const struct intel_crtc_state *new_crtc_state =
2260 intel_atomic_get_new_crtc_state(state, crtc);
2261 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2262 enum pipe pipe = crtc->pipe;
2264 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2267 i9xx_configure_cpu_transcoder(new_crtc_state);
2269 intel_set_pipe_src_size(new_crtc_state);
2271 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2272 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2273 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2276 crtc->active = true;
2278 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2280 intel_encoders_pre_pll_enable(state, crtc);
2282 if (IS_CHERRYVIEW(dev_priv))
2283 chv_enable_pll(new_crtc_state);
2285 vlv_enable_pll(new_crtc_state);
2287 intel_encoders_pre_enable(state, crtc);
2289 i9xx_pfit_enable(new_crtc_state);
2291 intel_color_load_luts(new_crtc_state);
2292 intel_color_commit_noarm(new_crtc_state);
2293 intel_color_commit_arm(new_crtc_state);
2294 /* update DSPCNTR to configure gamma for pipe bottom color */
2295 intel_disable_primary_plane(new_crtc_state);
2297 intel_initial_watermarks(state, crtc);
2298 intel_enable_transcoder(new_crtc_state);
2300 intel_crtc_vblank_on(new_crtc_state);
2302 intel_encoders_enable(state, crtc);
2305 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2306 struct intel_crtc *crtc)
2308 const struct intel_crtc_state *new_crtc_state =
2309 intel_atomic_get_new_crtc_state(state, crtc);
2310 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2311 enum pipe pipe = crtc->pipe;
2313 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2316 i9xx_configure_cpu_transcoder(new_crtc_state);
2318 intel_set_pipe_src_size(new_crtc_state);
2320 crtc->active = true;
2322 if (DISPLAY_VER(dev_priv) != 2)
2323 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2325 intel_encoders_pre_enable(state, crtc);
2327 i9xx_enable_pll(new_crtc_state);
2329 i9xx_pfit_enable(new_crtc_state);
2331 intel_color_load_luts(new_crtc_state);
2332 intel_color_commit_noarm(new_crtc_state);
2333 intel_color_commit_arm(new_crtc_state);
2334 /* update DSPCNTR to configure gamma for pipe bottom color */
2335 intel_disable_primary_plane(new_crtc_state);
2337 if (!intel_initial_watermarks(state, crtc))
2338 intel_update_watermarks(dev_priv);
2339 intel_enable_transcoder(new_crtc_state);
2341 intel_crtc_vblank_on(new_crtc_state);
2343 intel_encoders_enable(state, crtc);
2345 /* prevents spurious underruns */
2346 if (DISPLAY_VER(dev_priv) == 2)
2347 intel_crtc_wait_for_next_vblank(crtc);
2350 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2352 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2355 if (!old_crtc_state->gmch_pfit.control)
2358 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2360 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2361 intel_de_read(dev_priv, PFIT_CONTROL));
2362 intel_de_write(dev_priv, PFIT_CONTROL, 0);
2365 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2366 struct intel_crtc *crtc)
2368 struct intel_crtc_state *old_crtc_state =
2369 intel_atomic_get_old_crtc_state(state, crtc);
2370 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2371 enum pipe pipe = crtc->pipe;
2374 * On gen2 planes are double buffered but the pipe isn't, so we must
2375 * wait for planes to fully turn off before disabling the pipe.
2377 if (DISPLAY_VER(dev_priv) == 2)
2378 intel_crtc_wait_for_next_vblank(crtc);
2380 intel_encoders_disable(state, crtc);
2382 intel_crtc_vblank_off(old_crtc_state);
2384 intel_disable_transcoder(old_crtc_state);
2386 i9xx_pfit_disable(old_crtc_state);
2388 intel_encoders_post_disable(state, crtc);
2390 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2391 if (IS_CHERRYVIEW(dev_priv))
2392 chv_disable_pll(dev_priv, pipe);
2393 else if (IS_VALLEYVIEW(dev_priv))
2394 vlv_disable_pll(dev_priv, pipe);
2396 i9xx_disable_pll(old_crtc_state);
2399 intel_encoders_post_pll_disable(state, crtc);
2401 if (DISPLAY_VER(dev_priv) != 2)
2402 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2404 if (!dev_priv->wm_disp->initial_watermarks)
2405 intel_update_watermarks(dev_priv);
2407 /* clock the pipe down to 640x480@60 to potentially save power */
2408 if (IS_I830(dev_priv))
2409 i830_enable_pipe(dev_priv, pipe);
2414 * turn all crtc's off, but do not adjust state
2415 * This has to be paired with a call to intel_modeset_setup_hw_state.
2417 int intel_display_suspend(struct drm_device *dev)
2419 struct drm_i915_private *dev_priv = to_i915(dev);
2420 struct drm_atomic_state *state;
2423 if (!HAS_DISPLAY(dev_priv))
2426 state = drm_atomic_helper_suspend(dev);
2427 ret = PTR_ERR_OR_ZERO(state);
2429 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2432 dev_priv->modeset_restore_state = state;
2436 void intel_encoder_destroy(struct drm_encoder *encoder)
2438 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2440 drm_encoder_cleanup(encoder);
2441 kfree(intel_encoder);
2444 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2446 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2448 /* GDG double wide on either pipe, otherwise pipe A only */
2449 return DISPLAY_VER(dev_priv) < 4 &&
2450 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2453 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2455 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2456 struct drm_rect src;
2459 * We only use IF-ID interlacing. If we ever use
2460 * PF-ID we'll need to adjust the pixel_rate here.
2463 if (!crtc_state->pch_pfit.enabled)
2466 drm_rect_init(&src, 0, 0,
2467 drm_rect_width(&crtc_state->pipe_src) << 16,
2468 drm_rect_height(&crtc_state->pipe_src) << 16);
2470 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2474 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2475 const struct drm_display_mode *timings)
2477 mode->hdisplay = timings->crtc_hdisplay;
2478 mode->htotal = timings->crtc_htotal;
2479 mode->hsync_start = timings->crtc_hsync_start;
2480 mode->hsync_end = timings->crtc_hsync_end;
2482 mode->vdisplay = timings->crtc_vdisplay;
2483 mode->vtotal = timings->crtc_vtotal;
2484 mode->vsync_start = timings->crtc_vsync_start;
2485 mode->vsync_end = timings->crtc_vsync_end;
2487 mode->flags = timings->flags;
2488 mode->type = DRM_MODE_TYPE_DRIVER;
2490 mode->clock = timings->crtc_clock;
2492 drm_mode_set_name(mode);
2495 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2497 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2499 if (HAS_GMCH(dev_priv))
2500 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2501 crtc_state->pixel_rate =
2502 crtc_state->hw.pipe_mode.crtc_clock;
2504 crtc_state->pixel_rate =
2505 ilk_pipe_pixel_rate(crtc_state);
2508 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2509 struct drm_display_mode *mode)
2511 int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2516 mode->crtc_clock /= num_pipes;
2517 mode->crtc_hdisplay /= num_pipes;
2518 mode->crtc_hblank_start /= num_pipes;
2519 mode->crtc_hblank_end /= num_pipes;
2520 mode->crtc_hsync_start /= num_pipes;
2521 mode->crtc_hsync_end /= num_pipes;
2522 mode->crtc_htotal /= num_pipes;
2525 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2526 struct drm_display_mode *mode)
2528 int overlap = crtc_state->splitter.pixel_overlap;
2529 int n = crtc_state->splitter.link_count;
2531 if (!crtc_state->splitter.enable)
2535 * eDP MSO uses segment timings from EDID for transcoder
2536 * timings, but full mode for everything else.
2538 * h_full = (h_segment - pixel_overlap) * link_count
2540 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2541 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2542 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2543 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2544 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2545 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2546 mode->crtc_clock *= n;
2549 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2551 struct drm_display_mode *mode = &crtc_state->hw.mode;
2552 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2553 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2556 * Start with the adjusted_mode crtc timings, which
2557 * have been filled with the transcoder timings.
2559 drm_mode_copy(pipe_mode, adjusted_mode);
2561 /* Expand MSO per-segment transcoder timings to full */
2562 intel_splitter_adjust_timings(crtc_state, pipe_mode);
2565 * We want the full numbers in adjusted_mode normal timings,
2566 * adjusted_mode crtc timings are left with the raw transcoder
2569 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2571 /* Populate the "user" mode with full numbers */
2572 drm_mode_copy(mode, pipe_mode);
2573 intel_mode_from_crtc_timings(mode, mode);
2574 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2575 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2576 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2578 /* Derive per-pipe timings in case bigjoiner is used */
2579 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2580 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2582 intel_crtc_compute_pixel_rate(crtc_state);
2585 void intel_encoder_get_config(struct intel_encoder *encoder,
2586 struct intel_crtc_state *crtc_state)
2588 encoder->get_config(encoder, crtc_state);
2590 intel_crtc_readout_derived_state(crtc_state);
2593 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2595 int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2601 width = drm_rect_width(&crtc_state->pipe_src);
2602 height = drm_rect_height(&crtc_state->pipe_src);
2604 drm_rect_init(&crtc_state->pipe_src, 0, 0,
2605 width / num_pipes, height);
2608 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2610 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2611 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2613 intel_bigjoiner_compute_pipe_src(crtc_state);
2616 * Pipe horizontal size must be even in:
2618 * - LVDS dual channel mode
2619 * - Double wide pipe
2621 if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2622 if (crtc_state->double_wide) {
2623 drm_dbg_kms(&i915->drm,
2624 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2625 crtc->base.base.id, crtc->base.name);
2629 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2630 intel_is_dual_link_lvds(i915)) {
2631 drm_dbg_kms(&i915->drm,
2632 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2633 crtc->base.base.id, crtc->base.name);
2641 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2644 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2645 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2646 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2647 int clock_limit = i915->max_dotclk_freq;
2650 * Start with the adjusted_mode crtc timings, which
2651 * have been filled with the transcoder timings.
2653 drm_mode_copy(pipe_mode, adjusted_mode);
2655 /* Expand MSO per-segment transcoder timings to full */
2656 intel_splitter_adjust_timings(crtc_state, pipe_mode);
2658 /* Derive per-pipe timings in case bigjoiner is used */
2659 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2660 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2662 if (DISPLAY_VER(i915) < 4) {
2663 clock_limit = i915->max_cdclk_freq * 9 / 10;
2666 * Enable double wide mode when the dot clock
2667 * is > 90% of the (display) core speed.
2669 if (intel_crtc_supports_double_wide(crtc) &&
2670 pipe_mode->crtc_clock > clock_limit) {
2671 clock_limit = i915->max_dotclk_freq;
2672 crtc_state->double_wide = true;
2676 if (pipe_mode->crtc_clock > clock_limit) {
2677 drm_dbg_kms(&i915->drm,
2678 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2679 crtc->base.base.id, crtc->base.name,
2680 pipe_mode->crtc_clock, clock_limit,
2681 str_yes_no(crtc_state->double_wide));
2688 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2689 struct intel_crtc *crtc)
2691 struct intel_crtc_state *crtc_state =
2692 intel_atomic_get_new_crtc_state(state, crtc);
2695 ret = intel_crtc_compute_pipe_src(crtc_state);
2699 ret = intel_crtc_compute_pipe_mode(crtc_state);
2703 intel_crtc_compute_pixel_rate(crtc_state);
2705 if (crtc_state->has_pch_encoder)
2706 return ilk_fdi_compute_config(crtc, crtc_state);
2712 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2714 while (*num > DATA_LINK_M_N_MASK ||
2715 *den > DATA_LINK_M_N_MASK) {
2721 static void compute_m_n(unsigned int m, unsigned int n,
2722 u32 *ret_m, u32 *ret_n,
2726 * Several DP dongles in particular seem to be fussy about
2727 * too large link M/N values. Give N value as 0x8000 that
2728 * should be acceptable by specific devices. 0x8000 is the
2729 * specified fixed N value for asynchronous clock mode,
2730 * which the devices expect also in synchronous clock mode.
2733 *ret_n = DP_LINK_CONSTANT_N_VALUE;
2735 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2737 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2738 intel_reduce_m_n_ratio(ret_m, ret_n);
2742 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2743 int pixel_clock, int link_clock,
2744 struct intel_link_m_n *m_n,
2745 bool constant_n, bool fec_enable)
2747 u32 data_clock = bits_per_pixel * pixel_clock;
2750 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2753 compute_m_n(data_clock,
2754 link_clock * nlanes * 8,
2755 &m_n->data_m, &m_n->data_n,
2758 compute_m_n(pixel_clock, link_clock,
2759 &m_n->link_m, &m_n->link_n,
2763 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2766 * There may be no VBT; and if the BIOS enabled SSC we can
2767 * just keep using it to avoid unnecessary flicker. Whereas if the
2768 * BIOS isn't using it, don't assume it will work even if the VBT
2769 * indicates as much.
2771 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2772 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2776 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2777 drm_dbg_kms(&dev_priv->drm,
2778 "SSC %s by BIOS, overriding VBT which says %s\n",
2779 str_enabled_disabled(bios_lvds_use_ssc),
2780 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc));
2781 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2786 void intel_zero_m_n(struct intel_link_m_n *m_n)
2788 /* corresponds to 0 register value */
2789 memset(m_n, 0, sizeof(*m_n));
2793 void intel_set_m_n(struct drm_i915_private *i915,
2794 const struct intel_link_m_n *m_n,
2795 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2796 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2798 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2799 intel_de_write(i915, data_n_reg, m_n->data_n);
2800 intel_de_write(i915, link_m_reg, m_n->link_m);
2802 * On BDW+ writing LINK_N arms the double buffered update
2803 * of all the M/N registers, so it must be written last.
2805 intel_de_write(i915, link_n_reg, m_n->link_n);
2808 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2809 enum transcoder transcoder)
2811 if (IS_HASWELL(dev_priv))
2812 return transcoder == TRANSCODER_EDP;
2814 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2817 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2818 enum transcoder transcoder,
2819 const struct intel_link_m_n *m_n)
2821 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2822 enum pipe pipe = crtc->pipe;
2824 if (DISPLAY_VER(dev_priv) >= 5)
2825 intel_set_m_n(dev_priv, m_n,
2826 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2827 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2829 intel_set_m_n(dev_priv, m_n,
2830 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2831 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2834 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2835 enum transcoder transcoder,
2836 const struct intel_link_m_n *m_n)
2838 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2840 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2843 intel_set_m_n(dev_priv, m_n,
2844 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2845 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2848 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2852 enum pipe pipe = crtc->pipe;
2853 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2854 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2855 u32 crtc_vtotal, crtc_vblank_end;
2858 /* We need to be careful not to changed the adjusted mode, for otherwise
2859 * the hw state checker will get angry at the mismatch. */
2860 crtc_vtotal = adjusted_mode->crtc_vtotal;
2861 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2863 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2864 /* the chip adds 2 halflines automatically */
2866 crtc_vblank_end -= 1;
2868 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2869 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2871 vsyncshift = adjusted_mode->crtc_hsync_start -
2872 adjusted_mode->crtc_htotal / 2;
2874 vsyncshift += adjusted_mode->crtc_htotal;
2877 if (DISPLAY_VER(dev_priv) > 3)
2878 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
2881 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
2882 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
2883 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
2884 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
2885 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
2886 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
2888 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
2889 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
2890 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
2891 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
2892 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
2893 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
2895 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2896 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2897 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2899 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2900 (pipe == PIPE_B || pipe == PIPE_C))
2901 intel_de_write(dev_priv, VTOTAL(pipe),
2902 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2906 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2908 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2910 int width = drm_rect_width(&crtc_state->pipe_src);
2911 int height = drm_rect_height(&crtc_state->pipe_src);
2912 enum pipe pipe = crtc->pipe;
2914 /* pipesrc controls the size that is scaled from, which should
2915 * always be the user's requested size.
2917 intel_de_write(dev_priv, PIPESRC(pipe),
2918 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2921 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2923 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2924 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2926 if (DISPLAY_VER(dev_priv) == 2)
2929 if (DISPLAY_VER(dev_priv) >= 9 ||
2930 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2931 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
2933 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
2936 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2937 struct intel_crtc_state *pipe_config)
2939 struct drm_device *dev = crtc->base.dev;
2940 struct drm_i915_private *dev_priv = to_i915(dev);
2941 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2944 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
2945 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
2946 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
2948 if (!transcoder_is_dsi(cpu_transcoder)) {
2949 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
2950 pipe_config->hw.adjusted_mode.crtc_hblank_start =
2952 pipe_config->hw.adjusted_mode.crtc_hblank_end =
2953 ((tmp >> 16) & 0xffff) + 1;
2955 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
2956 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
2957 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
2959 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
2960 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
2961 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
2963 if (!transcoder_is_dsi(cpu_transcoder)) {
2964 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
2965 pipe_config->hw.adjusted_mode.crtc_vblank_start =
2967 pipe_config->hw.adjusted_mode.crtc_vblank_end =
2968 ((tmp >> 16) & 0xffff) + 1;
2970 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
2971 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
2972 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
2974 if (intel_pipe_is_interlaced(pipe_config)) {
2975 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2976 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
2977 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
2981 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2984 int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2985 enum pipe master_pipe, pipe = crtc->pipe;
2991 master_pipe = bigjoiner_master_pipe(crtc_state);
2992 width = drm_rect_width(&crtc_state->pipe_src);
2994 drm_rect_translate_to(&crtc_state->pipe_src,
2995 (pipe - master_pipe) * width, 0);
2998 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2999 struct intel_crtc_state *pipe_config)
3001 struct drm_device *dev = crtc->base.dev;
3002 struct drm_i915_private *dev_priv = to_i915(dev);
3005 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
3007 drm_rect_init(&pipe_config->pipe_src, 0, 0,
3008 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
3009 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
3011 intel_bigjoiner_adjust_pipe_src(pipe_config);
3014 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3016 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3017 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3021 * - We keep both pipes enabled on 830
3022 * - During modeset the pipe is still disabled and must remain so
3023 * - During fastset the pipe is already enabled and must remain so
3025 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3026 pipeconf |= PIPECONF_ENABLE;
3028 if (crtc_state->double_wide)
3029 pipeconf |= PIPECONF_DOUBLE_WIDE;
3031 /* only g4x and later have fancy bpc/dither controls */
3032 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3033 IS_CHERRYVIEW(dev_priv)) {
3034 /* Bspec claims that we can't use dithering for 30bpp pipes. */
3035 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
3036 pipeconf |= PIPECONF_DITHER_EN |
3037 PIPECONF_DITHER_TYPE_SP;
3039 switch (crtc_state->pipe_bpp) {
3041 /* Case prevented by intel_choose_pipe_bpp_dither. */
3042 MISSING_CASE(crtc_state->pipe_bpp);
3045 pipeconf |= PIPECONF_BPC_6;
3048 pipeconf |= PIPECONF_BPC_8;
3051 pipeconf |= PIPECONF_BPC_10;
3056 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3057 if (DISPLAY_VER(dev_priv) < 4 ||
3058 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3059 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3061 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
3063 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
3066 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3067 crtc_state->limited_color_range)
3068 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
3070 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3072 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3074 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
3075 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
3078 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
3080 if (IS_I830(dev_priv))
3083 return DISPLAY_VER(dev_priv) >= 4 ||
3084 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
3087 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
3089 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3093 if (!i9xx_has_pfit(dev_priv))
3096 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
3097 if (!(tmp & PFIT_ENABLE))
3100 /* Check whether the pfit is attached to our pipe. */
3101 if (DISPLAY_VER(dev_priv) < 4) {
3102 if (crtc->pipe != PIPE_B)
3105 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
3109 crtc_state->gmch_pfit.control = tmp;
3110 crtc_state->gmch_pfit.pgm_ratios =
3111 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
3114 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
3115 struct intel_crtc_state *pipe_config)
3117 struct drm_device *dev = crtc->base.dev;
3118 struct drm_i915_private *dev_priv = to_i915(dev);
3119 enum pipe pipe = crtc->pipe;
3122 int refclk = 100000;
3124 /* In case of DSI, DPLL will not be used */
3125 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3128 vlv_dpio_get(dev_priv);
3129 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
3130 vlv_dpio_put(dev_priv);
3132 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
3133 clock.m2 = mdiv & DPIO_M2DIV_MASK;
3134 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
3135 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
3136 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
3138 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
3141 static void chv_crtc_clock_get(struct intel_crtc *crtc,
3142 struct intel_crtc_state *pipe_config)
3144 struct drm_device *dev = crtc->base.dev;
3145 struct drm_i915_private *dev_priv = to_i915(dev);
3146 enum pipe pipe = crtc->pipe;
3147 enum dpio_channel port = vlv_pipe_to_channel(pipe);
3149 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
3150 int refclk = 100000;
3152 /* In case of DSI, DPLL will not be used */
3153 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3156 vlv_dpio_get(dev_priv);
3157 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
3158 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
3159 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
3160 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
3161 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
3162 vlv_dpio_put(dev_priv);
3164 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3165 clock.m2 = (pll_dw0 & 0xff) << 22;
3166 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3167 clock.m2 |= pll_dw2 & 0x3fffff;
3168 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3169 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3170 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3172 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3175 static enum intel_output_format
3176 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
3178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3183 if (tmp & PIPEMISC_YUV420_ENABLE) {
3184 /* We support 4:2:0 in full blend mode only */
3185 drm_WARN_ON(&dev_priv->drm,
3186 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
3188 return INTEL_OUTPUT_FORMAT_YCBCR420;
3189 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
3190 return INTEL_OUTPUT_FORMAT_YCBCR444;
3192 return INTEL_OUTPUT_FORMAT_RGB;
3196 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3199 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3201 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3204 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3206 if (tmp & DISP_PIPE_GAMMA_ENABLE)
3207 crtc_state->gamma_enable = true;
3209 if (!HAS_GMCH(dev_priv) &&
3210 tmp & DISP_PIPE_CSC_ENABLE)
3211 crtc_state->csc_enable = true;
3214 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3215 struct intel_crtc_state *pipe_config)
3217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3218 enum intel_display_power_domain power_domain;
3219 intel_wakeref_t wakeref;
3223 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3224 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3228 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3229 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3230 pipe_config->shared_dpll = NULL;
3234 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3235 if (!(tmp & PIPECONF_ENABLE))
3238 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3239 IS_CHERRYVIEW(dev_priv)) {
3240 switch (tmp & PIPECONF_BPC_MASK) {
3241 case PIPECONF_BPC_6:
3242 pipe_config->pipe_bpp = 18;
3244 case PIPECONF_BPC_8:
3245 pipe_config->pipe_bpp = 24;
3247 case PIPECONF_BPC_10:
3248 pipe_config->pipe_bpp = 30;
3256 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3257 (tmp & PIPECONF_COLOR_RANGE_SELECT))
3258 pipe_config->limited_color_range = true;
3260 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
3262 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3264 if (IS_CHERRYVIEW(dev_priv))
3265 pipe_config->cgm_mode = intel_de_read(dev_priv,
3266 CGM_PIPE_MODE(crtc->pipe));
3268 i9xx_get_pipe_color_config(pipe_config);
3269 intel_color_get_config(pipe_config);
3271 if (DISPLAY_VER(dev_priv) < 4)
3272 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
3274 intel_get_transcoder_timings(crtc, pipe_config);
3275 intel_get_pipe_src_size(crtc, pipe_config);
3277 i9xx_get_pfit_config(pipe_config);
3279 if (DISPLAY_VER(dev_priv) >= 4) {
3280 /* No way to read it out on pipes B and C */
3281 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3282 tmp = dev_priv->chv_dpll_md[crtc->pipe];
3284 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3285 pipe_config->pixel_multiplier =
3286 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3287 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3288 pipe_config->dpll_hw_state.dpll_md = tmp;
3289 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3290 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3291 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3292 pipe_config->pixel_multiplier =
3293 ((tmp & SDVO_MULTIPLIER_MASK)
3294 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3296 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3297 * port and will be fixed up in the encoder->get_config
3299 pipe_config->pixel_multiplier = 1;
3301 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3303 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3304 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3306 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3309 /* Mask out read-only status bits. */
3310 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3311 DPLL_PORTC_READY_MASK |
3312 DPLL_PORTB_READY_MASK);
3315 if (IS_CHERRYVIEW(dev_priv))
3316 chv_crtc_clock_get(crtc, pipe_config);
3317 else if (IS_VALLEYVIEW(dev_priv))
3318 vlv_crtc_clock_get(crtc, pipe_config);
3320 i9xx_crtc_clock_get(crtc, pipe_config);
3323 * Normally the dotclock is filled in by the encoder .get_config()
3324 * but in case the pipe is enabled w/o any ports we need a sane
3327 pipe_config->hw.adjusted_mode.crtc_clock =
3328 pipe_config->port_clock / pipe_config->pixel_multiplier;
3333 intel_display_power_put(dev_priv, power_domain, wakeref);
3338 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3340 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3342 enum pipe pipe = crtc->pipe;
3346 * - During modeset the pipe is still disabled and must remain so
3347 * - During fastset the pipe is already enabled and must remain so
3349 if (!intel_crtc_needs_modeset(crtc_state))
3350 val |= PIPECONF_ENABLE;
3352 switch (crtc_state->pipe_bpp) {
3354 /* Case prevented by intel_choose_pipe_bpp_dither. */
3355 MISSING_CASE(crtc_state->pipe_bpp);
3358 val |= PIPECONF_BPC_6;
3361 val |= PIPECONF_BPC_8;
3364 val |= PIPECONF_BPC_10;
3367 val |= PIPECONF_BPC_12;
3371 if (crtc_state->dither)
3372 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3374 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3375 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3377 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3380 * This would end up with an odd purple hue over
3381 * the entire display. Make sure we don't do it.
3383 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3384 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3386 if (crtc_state->limited_color_range &&
3387 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3388 val |= PIPECONF_COLOR_RANGE_SELECT;
3390 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3391 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
3393 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3395 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3396 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3398 intel_de_write(dev_priv, PIPECONF(pipe), val);
3399 intel_de_posting_read(dev_priv, PIPECONF(pipe));
3402 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3404 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3406 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3410 * - During modeset the pipe is still disabled and must remain so
3411 * - During fastset the pipe is already enabled and must remain so
3413 if (!intel_crtc_needs_modeset(crtc_state))
3414 val |= PIPECONF_ENABLE;
3416 if (IS_HASWELL(dev_priv) && crtc_state->dither)
3417 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3419 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3420 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3422 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3424 if (IS_HASWELL(dev_priv) &&
3425 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3426 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
3428 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
3429 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
3432 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
3434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3438 switch (crtc_state->pipe_bpp) {
3440 val |= PIPEMISC_BPC_6;
3443 val |= PIPEMISC_BPC_8;
3446 val |= PIPEMISC_BPC_10;
3449 /* Port output 12BPC defined for ADLP+ */
3450 if (DISPLAY_VER(dev_priv) > 12)
3451 val |= PIPEMISC_BPC_12_ADLP;
3454 MISSING_CASE(crtc_state->pipe_bpp);
3458 if (crtc_state->dither)
3459 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
3461 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3462 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3463 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
3465 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3466 val |= PIPEMISC_YUV420_ENABLE |
3467 PIPEMISC_YUV420_MODE_FULL_BLEND;
3469 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3470 val |= PIPEMISC_HDR_MODE_PRECISION;
3472 if (DISPLAY_VER(dev_priv) >= 12)
3473 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
3475 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
3478 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
3480 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3483 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3485 switch (tmp & PIPEMISC_BPC_MASK) {
3486 case PIPEMISC_BPC_6:
3488 case PIPEMISC_BPC_8:
3490 case PIPEMISC_BPC_10:
3493 * PORT OUTPUT 12 BPC defined for ADLP+.
3496 * For previous platforms with DSI interface, bits 5:7
3497 * are used for storing pipe_bpp irrespective of dithering.
3498 * Since the value of 12 BPC is not defined for these bits
3499 * on older platforms, need to find a workaround for 12 BPC
3500 * MIPI DSI HW readout.
3502 case PIPEMISC_BPC_12_ADLP:
3503 if (DISPLAY_VER(dev_priv) > 12)
3512 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3515 * Account for spread spectrum to avoid
3516 * oversubscribing the link. Max center spread
3517 * is 2.5%; use 5% for safety's sake.
3519 u32 bps = target_clock * bpp * 21 / 20;
3520 return DIV_ROUND_UP(bps, link_bw * 8);
3523 void intel_get_m_n(struct drm_i915_private *i915,
3524 struct intel_link_m_n *m_n,
3525 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3526 i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3528 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3529 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3530 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3531 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3532 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3535 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3536 enum transcoder transcoder,
3537 struct intel_link_m_n *m_n)
3539 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3540 enum pipe pipe = crtc->pipe;
3542 if (DISPLAY_VER(dev_priv) >= 5)
3543 intel_get_m_n(dev_priv, m_n,
3544 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3545 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3547 intel_get_m_n(dev_priv, m_n,
3548 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3549 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3552 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3553 enum transcoder transcoder,
3554 struct intel_link_m_n *m_n)
3556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3558 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3561 intel_get_m_n(dev_priv, m_n,
3562 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3563 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3566 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3569 drm_rect_init(&crtc_state->pch_pfit.dst,
3570 pos >> 16, pos & 0xffff,
3571 size >> 16, size & 0xffff);
3574 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3577 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3578 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3582 /* find scaler attached to this pipe */
3583 for (i = 0; i < crtc->num_scalers; i++) {
3586 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3587 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3591 crtc_state->pch_pfit.enabled = true;
3593 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3594 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3596 ilk_get_pfit_pos_size(crtc_state, pos, size);
3598 scaler_state->scalers[i].in_use = true;
3602 scaler_state->scaler_id = id;
3604 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3606 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3609 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3615 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3616 if ((ctl & PF_ENABLE) == 0)
3619 crtc_state->pch_pfit.enabled = true;
3621 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3622 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3624 ilk_get_pfit_pos_size(crtc_state, pos, size);
3627 * We currently do not free assignements of panel fitters on
3628 * ivb/hsw (since we don't use the higher upscaling modes which
3629 * differentiates them) so just WARN about this case for now.
3631 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3632 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3635 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3636 struct intel_crtc_state *pipe_config)
3638 struct drm_device *dev = crtc->base.dev;
3639 struct drm_i915_private *dev_priv = to_i915(dev);
3640 enum intel_display_power_domain power_domain;
3641 intel_wakeref_t wakeref;
3645 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3646 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3650 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3651 pipe_config->shared_dpll = NULL;
3654 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3655 if (!(tmp & PIPECONF_ENABLE))
3658 switch (tmp & PIPECONF_BPC_MASK) {
3659 case PIPECONF_BPC_6:
3660 pipe_config->pipe_bpp = 18;
3662 case PIPECONF_BPC_8:
3663 pipe_config->pipe_bpp = 24;
3665 case PIPECONF_BPC_10:
3666 pipe_config->pipe_bpp = 30;
3668 case PIPECONF_BPC_12:
3669 pipe_config->pipe_bpp = 36;
3675 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
3676 pipe_config->limited_color_range = true;
3678 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
3679 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
3680 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
3681 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3684 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3688 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
3690 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3692 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
3694 pipe_config->csc_mode = intel_de_read(dev_priv,
3695 PIPE_CSC_MODE(crtc->pipe));
3697 i9xx_get_pipe_color_config(pipe_config);
3698 intel_color_get_config(pipe_config);
3700 pipe_config->pixel_multiplier = 1;
3702 ilk_pch_get_config(pipe_config);
3704 intel_get_transcoder_timings(crtc, pipe_config);
3705 intel_get_pipe_src_size(crtc, pipe_config);
3707 ilk_get_pfit_config(pipe_config);
3712 intel_display_power_put(dev_priv, power_domain, wakeref);
3717 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3719 if (DISPLAY_VER(i915) >= 12)
3720 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3721 else if (DISPLAY_VER(i915) >= 11)
3722 return BIT(PIPE_B) | BIT(PIPE_C);
3727 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3728 enum transcoder cpu_transcoder)
3730 enum intel_display_power_domain power_domain;
3731 intel_wakeref_t wakeref;
3734 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3736 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3737 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3739 return tmp & TRANS_DDI_FUNC_ENABLE;
3742 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3743 u8 *master_pipes, u8 *slave_pipes)
3745 struct intel_crtc *crtc;
3750 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3751 bigjoiner_pipes(dev_priv)) {
3752 enum intel_display_power_domain power_domain;
3753 enum pipe pipe = crtc->pipe;
3754 intel_wakeref_t wakeref;
3756 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3757 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3758 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3760 if (!(tmp & BIG_JOINER_ENABLE))
3763 if (tmp & MASTER_BIG_JOINER_ENABLE)
3764 *master_pipes |= BIT(pipe);
3766 *slave_pipes |= BIT(pipe);
3769 if (DISPLAY_VER(dev_priv) < 13)
3772 power_domain = POWER_DOMAIN_PIPE(pipe);
3773 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3774 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3776 if (tmp & UNCOMPRESSED_JOINER_MASTER)
3777 *master_pipes |= BIT(pipe);
3778 if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3779 *slave_pipes |= BIT(pipe);
3783 /* Bigjoiner pipes should always be consecutive master and slave */
3784 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3785 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3786 *master_pipes, *slave_pipes);
3789 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3791 if ((slave_pipes & BIT(pipe)) == 0)
3794 /* ignore everything above our pipe */
3795 master_pipes &= ~GENMASK(7, pipe);
3797 /* highest remaining bit should be our master pipe */
3798 return fls(master_pipes) - 1;
3801 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3803 enum pipe master_pipe, next_master_pipe;
3805 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3807 if ((master_pipes & BIT(master_pipe)) == 0)
3810 /* ignore our master pipe and everything below it */
3811 master_pipes &= ~GENMASK(master_pipe, 0);
3812 /* make sure a high bit is set for the ffs() */
3813 master_pipes |= BIT(7);
3814 /* lowest remaining bit should be the next master pipe */
3815 next_master_pipe = ffs(master_pipes) - 1;
3817 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3820 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3822 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3824 if (DISPLAY_VER(i915) >= 11)
3825 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3827 return panel_transcoder_mask;
3830 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3832 struct drm_device *dev = crtc->base.dev;
3833 struct drm_i915_private *dev_priv = to_i915(dev);
3834 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3835 enum transcoder cpu_transcoder;
3836 u8 master_pipes, slave_pipes;
3837 u8 enabled_transcoders = 0;
3840 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3841 * consistency and less surprising code; it's in always on power).
3843 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3844 panel_transcoder_mask) {
3845 enum intel_display_power_domain power_domain;
3846 intel_wakeref_t wakeref;
3847 enum pipe trans_pipe;
3850 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3851 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3852 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3854 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3857 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3860 "unknown pipe linked to transcoder %s\n",
3861 transcoder_name(cpu_transcoder));
3863 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3864 case TRANS_DDI_EDP_INPUT_A_ON:
3865 trans_pipe = PIPE_A;
3867 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3868 trans_pipe = PIPE_B;
3870 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3871 trans_pipe = PIPE_C;
3873 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3874 trans_pipe = PIPE_D;
3878 if (trans_pipe == crtc->pipe)
3879 enabled_transcoders |= BIT(cpu_transcoder);
3882 /* single pipe or bigjoiner master */
3883 cpu_transcoder = (enum transcoder) crtc->pipe;
3884 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3885 enabled_transcoders |= BIT(cpu_transcoder);
3887 /* bigjoiner slave -> consider the master pipe's transcoder as well */
3888 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3889 if (slave_pipes & BIT(crtc->pipe)) {
3890 cpu_transcoder = (enum transcoder)
3891 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3892 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3893 enabled_transcoders |= BIT(cpu_transcoder);
3896 return enabled_transcoders;
3899 static bool has_edp_transcoders(u8 enabled_transcoders)
3901 return enabled_transcoders & BIT(TRANSCODER_EDP);
3904 static bool has_dsi_transcoders(u8 enabled_transcoders)
3906 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3907 BIT(TRANSCODER_DSI_1));
3910 static bool has_pipe_transcoders(u8 enabled_transcoders)
3912 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3913 BIT(TRANSCODER_DSI_0) |
3914 BIT(TRANSCODER_DSI_1));
3917 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3918 u8 enabled_transcoders)
3920 /* Only one type of transcoder please */
3921 drm_WARN_ON(&i915->drm,
3922 has_edp_transcoders(enabled_transcoders) +
3923 has_dsi_transcoders(enabled_transcoders) +
3924 has_pipe_transcoders(enabled_transcoders) > 1);
3926 /* Only DSI transcoders can be ganged */
3927 drm_WARN_ON(&i915->drm,
3928 !has_dsi_transcoders(enabled_transcoders) &&
3929 !is_power_of_2(enabled_transcoders));
3932 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3933 struct intel_crtc_state *pipe_config,
3934 struct intel_display_power_domain_set *power_domain_set)
3936 struct drm_device *dev = crtc->base.dev;
3937 struct drm_i915_private *dev_priv = to_i915(dev);
3938 unsigned long enabled_transcoders;
3941 enabled_transcoders = hsw_enabled_transcoders(crtc);
3942 if (!enabled_transcoders)
3945 assert_enabled_transcoders(dev_priv, enabled_transcoders);
3948 * With the exception of DSI we should only ever have
3949 * a single enabled transcoder. With DSI let's just
3950 * pick the first one.
3952 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3954 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3955 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3958 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3959 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3961 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3962 pipe_config->pch_pfit.force_thru = true;
3965 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
3967 return tmp & PIPECONF_ENABLE;
3970 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3971 struct intel_crtc_state *pipe_config,
3972 struct intel_display_power_domain_set *power_domain_set)
3974 struct drm_device *dev = crtc->base.dev;
3975 struct drm_i915_private *dev_priv = to_i915(dev);
3976 enum transcoder cpu_transcoder;
3980 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3982 cpu_transcoder = TRANSCODER_DSI_A;
3984 cpu_transcoder = TRANSCODER_DSI_C;
3986 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3987 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3991 * The PLL needs to be enabled with a valid divider
3992 * configuration, otherwise accessing DSI registers will hang
3993 * the machine. See BSpec North Display Engine
3994 * registers/MIPI[BXT]. We can break out here early, since we
3995 * need the same DSI PLL to be enabled for both DSI ports.
3997 if (!bxt_dsi_pll_is_enabled(dev_priv))
4000 /* XXX: this works for video mode only */
4001 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
4002 if (!(tmp & DPI_ENABLE))
4005 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
4006 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
4009 pipe_config->cpu_transcoder = cpu_transcoder;
4013 return transcoder_is_dsi(pipe_config->cpu_transcoder);
4016 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
4018 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4019 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4020 u8 master_pipes, slave_pipes;
4021 enum pipe pipe = crtc->pipe;
4023 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
4025 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
4028 crtc_state->bigjoiner_pipes =
4029 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
4030 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
4033 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
4034 struct intel_crtc_state *pipe_config)
4036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4037 struct intel_display_power_domain_set power_domain_set = { };
4041 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4042 POWER_DOMAIN_PIPE(crtc->pipe)))
4045 pipe_config->shared_dpll = NULL;
4047 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
4049 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4050 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
4051 drm_WARN_ON(&dev_priv->drm, active);
4058 intel_dsc_get_config(pipe_config);
4059 intel_bigjoiner_get_config(pipe_config);
4061 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
4062 DISPLAY_VER(dev_priv) >= 11)
4063 intel_get_transcoder_timings(crtc, pipe_config);
4065 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
4066 intel_vrr_get_config(crtc, pipe_config);
4068 intel_get_pipe_src_size(crtc, pipe_config);
4070 if (IS_HASWELL(dev_priv)) {
4071 u32 tmp = intel_de_read(dev_priv,
4072 PIPECONF(pipe_config->cpu_transcoder));
4074 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
4075 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
4077 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4079 pipe_config->output_format =
4080 bdw_get_pipemisc_output_format(crtc);
4083 pipe_config->gamma_mode = intel_de_read(dev_priv,
4084 GAMMA_MODE(crtc->pipe));
4086 pipe_config->csc_mode = intel_de_read(dev_priv,
4087 PIPE_CSC_MODE(crtc->pipe));
4089 if (DISPLAY_VER(dev_priv) >= 9) {
4090 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
4092 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
4093 pipe_config->gamma_enable = true;
4095 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
4096 pipe_config->csc_enable = true;
4098 i9xx_get_pipe_color_config(pipe_config);
4101 intel_color_get_config(pipe_config);
4103 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
4104 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
4105 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4106 pipe_config->ips_linetime =
4107 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
4109 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4110 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4111 if (DISPLAY_VER(dev_priv) >= 9)
4112 skl_get_pfit_config(pipe_config);
4114 ilk_get_pfit_config(pipe_config);
4117 hsw_ips_get_config(pipe_config);
4119 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4120 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4121 pipe_config->pixel_multiplier =
4122 intel_de_read(dev_priv,
4123 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
4125 pipe_config->pixel_multiplier = 1;
4128 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4129 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
4131 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4133 /* no idea if this is correct */
4134 pipe_config->framestart_delay = 1;
4138 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
4143 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4146 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4148 if (!i915->display->get_pipe_config(crtc, crtc_state))
4151 crtc_state->hw.active = true;
4153 intel_crtc_readout_derived_state(crtc_state);
4158 /* VESA 640x480x72Hz mode to set on the pipe */
4159 static const struct drm_display_mode load_detect_mode = {
4160 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4161 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4164 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4165 struct drm_crtc *crtc)
4167 struct drm_plane *plane;
4168 struct drm_plane_state *plane_state;
4171 ret = drm_atomic_add_affected_planes(state, crtc);
4175 for_each_new_plane_in_state(state, plane, plane_state, i) {
4176 if (plane_state->crtc != crtc)
4179 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4183 drm_atomic_set_fb_for_plane(plane_state, NULL);
4189 int intel_get_load_detect_pipe(struct drm_connector *connector,
4190 struct intel_load_detect_pipe *old,
4191 struct drm_modeset_acquire_ctx *ctx)
4193 struct intel_encoder *encoder =
4194 intel_attached_encoder(to_intel_connector(connector));
4195 struct intel_crtc *possible_crtc;
4196 struct intel_crtc *crtc = NULL;
4197 struct drm_device *dev = encoder->base.dev;
4198 struct drm_i915_private *dev_priv = to_i915(dev);
4199 struct drm_mode_config *config = &dev->mode_config;
4200 struct drm_atomic_state *state = NULL, *restore_state = NULL;
4201 struct drm_connector_state *connector_state;
4202 struct intel_crtc_state *crtc_state;
4205 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4206 connector->base.id, connector->name,
4207 encoder->base.base.id, encoder->base.name);
4209 old->restore_state = NULL;
4211 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4214 * Algorithm gets a little messy:
4216 * - if the connector already has an assigned crtc, use it (but make
4217 * sure it's on first)
4219 * - try to find the first unused crtc that can drive this connector,
4220 * and use that if we find one
4223 /* See if we already have a CRTC for this connector */
4224 if (connector->state->crtc) {
4225 crtc = to_intel_crtc(connector->state->crtc);
4227 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4231 /* Make sure the crtc and connector are running */
4235 /* Find an unused one (if possible) */
4236 for_each_intel_crtc(dev, possible_crtc) {
4237 if (!(encoder->base.possible_crtcs &
4238 drm_crtc_mask(&possible_crtc->base)))
4241 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4245 if (possible_crtc->base.state->enable) {
4246 drm_modeset_unlock(&possible_crtc->base.mutex);
4250 crtc = possible_crtc;
4255 * If we didn't find an unused CRTC, don't use any.
4258 drm_dbg_kms(&dev_priv->drm,
4259 "no pipe available for load-detect\n");
4265 state = drm_atomic_state_alloc(dev);
4266 restore_state = drm_atomic_state_alloc(dev);
4267 if (!state || !restore_state) {
4272 state->acquire_ctx = ctx;
4273 restore_state->acquire_ctx = ctx;
4275 connector_state = drm_atomic_get_connector_state(state, connector);
4276 if (IS_ERR(connector_state)) {
4277 ret = PTR_ERR(connector_state);
4281 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4285 crtc_state = intel_atomic_get_crtc_state(state, crtc);
4286 if (IS_ERR(crtc_state)) {
4287 ret = PTR_ERR(crtc_state);
4291 crtc_state->uapi.active = true;
4293 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4298 ret = intel_modeset_disable_planes(state, &crtc->base);
4302 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4304 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4306 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4308 drm_dbg_kms(&dev_priv->drm,
4309 "Failed to create a copy of old state to restore: %i\n",
4314 ret = drm_atomic_commit(state);
4316 drm_dbg_kms(&dev_priv->drm,
4317 "failed to set mode on load-detect pipe\n");
4321 old->restore_state = restore_state;
4322 drm_atomic_state_put(state);
4324 /* let the connector get through one full cycle before testing */
4325 intel_crtc_wait_for_next_vblank(crtc);
4331 drm_atomic_state_put(state);
4334 if (restore_state) {
4335 drm_atomic_state_put(restore_state);
4336 restore_state = NULL;
4339 if (ret == -EDEADLK)
4345 void intel_release_load_detect_pipe(struct drm_connector *connector,
4346 struct intel_load_detect_pipe *old,
4347 struct drm_modeset_acquire_ctx *ctx)
4349 struct intel_encoder *intel_encoder =
4350 intel_attached_encoder(to_intel_connector(connector));
4351 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4352 struct drm_encoder *encoder = &intel_encoder->base;
4353 struct drm_atomic_state *state = old->restore_state;
4356 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4357 connector->base.id, connector->name,
4358 encoder->base.id, encoder->name);
4363 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4365 drm_dbg_kms(&i915->drm,
4366 "Couldn't release load detect pipe: %i\n", ret);
4367 drm_atomic_state_put(state);
4370 static int i9xx_pll_refclk(struct drm_device *dev,
4371 const struct intel_crtc_state *pipe_config)
4373 struct drm_i915_private *dev_priv = to_i915(dev);
4374 u32 dpll = pipe_config->dpll_hw_state.dpll;
4376 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4377 return dev_priv->vbt.lvds_ssc_freq;
4378 else if (HAS_PCH_SPLIT(dev_priv))
4380 else if (DISPLAY_VER(dev_priv) != 2)
4386 /* Returns the clock of the currently programmed mode of the given pipe. */
4387 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4388 struct intel_crtc_state *pipe_config)
4390 struct drm_device *dev = crtc->base.dev;
4391 struct drm_i915_private *dev_priv = to_i915(dev);
4392 u32 dpll = pipe_config->dpll_hw_state.dpll;
4396 int refclk = i9xx_pll_refclk(dev, pipe_config);
4398 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4399 fp = pipe_config->dpll_hw_state.fp0;
4401 fp = pipe_config->dpll_hw_state.fp1;
4403 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4404 if (IS_PINEVIEW(dev_priv)) {
4405 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4406 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4408 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4409 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4412 if (DISPLAY_VER(dev_priv) != 2) {
4413 if (IS_PINEVIEW(dev_priv))
4414 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4415 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4417 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4418 DPLL_FPA01_P1_POST_DIV_SHIFT);
4420 switch (dpll & DPLL_MODE_MASK) {
4421 case DPLLB_MODE_DAC_SERIAL:
4422 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4425 case DPLLB_MODE_LVDS:
4426 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4430 drm_dbg_kms(&dev_priv->drm,
4431 "Unknown DPLL mode %08x in programmed "
4432 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4436 if (IS_PINEVIEW(dev_priv))
4437 port_clock = pnv_calc_dpll_params(refclk, &clock);
4439 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4441 enum pipe lvds_pipe;
4443 if (IS_I85X(dev_priv) &&
4444 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4445 lvds_pipe == crtc->pipe) {
4446 u32 lvds = intel_de_read(dev_priv, LVDS);
4448 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4449 DPLL_FPA01_P1_POST_DIV_SHIFT);
4451 if (lvds & LVDS_CLKB_POWER_UP)
4456 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4459 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4460 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4462 if (dpll & PLL_P2_DIVIDE_BY_4)
4468 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4472 * This value includes pixel_multiplier. We will use
4473 * port_clock to compute adjusted_mode.crtc_clock in the
4474 * encoder's get_config() function.
4476 pipe_config->port_clock = port_clock;
4479 int intel_dotclock_calculate(int link_freq,
4480 const struct intel_link_m_n *m_n)
4483 * The calculation for the data clock is:
4484 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4485 * But we want to avoid losing precison if possible, so:
4486 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4488 * and the link clock is simpler:
4489 * link_clock = (m * link_clock) / n
4495 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
4498 /* Returns the currently programmed mode of the given encoder. */
4499 struct drm_display_mode *
4500 intel_encoder_current_mode(struct intel_encoder *encoder)
4502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4503 struct intel_crtc_state *crtc_state;
4504 struct drm_display_mode *mode;
4505 struct intel_crtc *crtc;
4508 if (!encoder->get_hw_state(encoder, &pipe))
4511 crtc = intel_crtc_for_pipe(dev_priv, pipe);
4513 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4517 crtc_state = intel_crtc_state_alloc(crtc);
4523 if (!intel_crtc_get_pipe_config(crtc_state)) {
4529 intel_encoder_get_config(encoder, crtc_state);
4531 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4538 static bool encoders_cloneable(const struct intel_encoder *a,
4539 const struct intel_encoder *b)
4541 /* masks could be asymmetric, so check both ways */
4542 return a == b || (a->cloneable & (1 << b->type) &&
4543 b->cloneable & (1 << a->type));
4546 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4547 struct intel_crtc *crtc,
4548 struct intel_encoder *encoder)
4550 struct intel_encoder *source_encoder;
4551 struct drm_connector *connector;
4552 struct drm_connector_state *connector_state;
4555 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4556 if (connector_state->crtc != &crtc->base)
4560 to_intel_encoder(connector_state->best_encoder);
4561 if (!encoders_cloneable(encoder, source_encoder))
4568 static int icl_add_linked_planes(struct intel_atomic_state *state)
4570 struct intel_plane *plane, *linked;
4571 struct intel_plane_state *plane_state, *linked_plane_state;
4574 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4575 linked = plane_state->planar_linked_plane;
4580 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4581 if (IS_ERR(linked_plane_state))
4582 return PTR_ERR(linked_plane_state);
4584 drm_WARN_ON(state->base.dev,
4585 linked_plane_state->planar_linked_plane != plane);
4586 drm_WARN_ON(state->base.dev,
4587 linked_plane_state->planar_slave == plane_state->planar_slave);
4593 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4595 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4597 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4598 struct intel_plane *plane, *linked;
4599 struct intel_plane_state *plane_state;
4602 if (DISPLAY_VER(dev_priv) < 11)
4606 * Destroy all old plane links and make the slave plane invisible
4607 * in the crtc_state->active_planes mask.
4609 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4610 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4613 plane_state->planar_linked_plane = NULL;
4614 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4615 crtc_state->enabled_planes &= ~BIT(plane->id);
4616 crtc_state->active_planes &= ~BIT(plane->id);
4617 crtc_state->update_planes |= BIT(plane->id);
4618 crtc_state->data_rate[plane->id] = 0;
4619 crtc_state->rel_data_rate[plane->id] = 0;
4622 plane_state->planar_slave = false;
4625 if (!crtc_state->nv12_planes)
4628 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4629 struct intel_plane_state *linked_state = NULL;
4631 if (plane->pipe != crtc->pipe ||
4632 !(crtc_state->nv12_planes & BIT(plane->id)))
4635 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4636 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4639 if (crtc_state->active_planes & BIT(linked->id))
4642 linked_state = intel_atomic_get_plane_state(state, linked);
4643 if (IS_ERR(linked_state))
4644 return PTR_ERR(linked_state);
4649 if (!linked_state) {
4650 drm_dbg_kms(&dev_priv->drm,
4651 "Need %d free Y planes for planar YUV\n",
4652 hweight8(crtc_state->nv12_planes));
4657 plane_state->planar_linked_plane = linked;
4659 linked_state->planar_slave = true;
4660 linked_state->planar_linked_plane = plane;
4661 crtc_state->enabled_planes |= BIT(linked->id);
4662 crtc_state->active_planes |= BIT(linked->id);
4663 crtc_state->update_planes |= BIT(linked->id);
4664 crtc_state->data_rate[linked->id] =
4665 crtc_state->data_rate_y[plane->id];
4666 crtc_state->rel_data_rate[linked->id] =
4667 crtc_state->rel_data_rate_y[plane->id];
4668 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4669 linked->base.name, plane->base.name);
4671 /* Copy parameters to slave plane */
4672 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4673 linked_state->color_ctl = plane_state->color_ctl;
4674 linked_state->view = plane_state->view;
4675 linked_state->decrypt = plane_state->decrypt;
4677 intel_plane_copy_hw_state(linked_state, plane_state);
4678 linked_state->uapi.src = plane_state->uapi.src;
4679 linked_state->uapi.dst = plane_state->uapi.dst;
4681 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4682 if (linked->id == PLANE_SPRITE5)
4683 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4684 else if (linked->id == PLANE_SPRITE4)
4685 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4686 else if (linked->id == PLANE_SPRITE3)
4687 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4688 else if (linked->id == PLANE_SPRITE2)
4689 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4691 MISSING_CASE(linked->id);
4698 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4700 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4701 struct intel_atomic_state *state =
4702 to_intel_atomic_state(new_crtc_state->uapi.state);
4703 const struct intel_crtc_state *old_crtc_state =
4704 intel_atomic_get_old_crtc_state(state, crtc);
4706 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4709 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4711 const struct drm_display_mode *pipe_mode =
4712 &crtc_state->hw.pipe_mode;
4715 if (!crtc_state->hw.enable)
4718 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4719 pipe_mode->crtc_clock);
4721 return min(linetime_wm, 0x1ff);
4724 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4725 const struct intel_cdclk_state *cdclk_state)
4727 const struct drm_display_mode *pipe_mode =
4728 &crtc_state->hw.pipe_mode;
4731 if (!crtc_state->hw.enable)
4734 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4735 cdclk_state->logical.cdclk);
4737 return min(linetime_wm, 0x1ff);
4740 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4744 const struct drm_display_mode *pipe_mode =
4745 &crtc_state->hw.pipe_mode;
4748 if (!crtc_state->hw.enable)
4751 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4752 crtc_state->pixel_rate);
4754 /* Display WA #1135: BXT:ALL GLK:ALL */
4755 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4756 dev_priv->ipc_enabled)
4759 return min(linetime_wm, 0x1ff);
4762 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4763 struct intel_crtc *crtc)
4765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4766 struct intel_crtc_state *crtc_state =
4767 intel_atomic_get_new_crtc_state(state, crtc);
4768 const struct intel_cdclk_state *cdclk_state;
4770 if (DISPLAY_VER(dev_priv) >= 9)
4771 crtc_state->linetime = skl_linetime_wm(crtc_state);
4773 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4775 if (!hsw_crtc_supports_ips(crtc))
4778 cdclk_state = intel_atomic_get_cdclk_state(state);
4779 if (IS_ERR(cdclk_state))
4780 return PTR_ERR(cdclk_state);
4782 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4788 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4789 struct intel_crtc *crtc)
4791 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4792 struct intel_crtc_state *crtc_state =
4793 intel_atomic_get_new_crtc_state(state, crtc);
4794 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
4797 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4798 mode_changed && !crtc_state->hw.active)
4799 crtc_state->update_wm_post = true;
4802 ret = intel_dpll_crtc_compute_clock(state, crtc);
4806 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4812 * May need to update pipe gamma enable bits
4813 * when C8 planes are getting enabled/disabled.
4815 if (c8_planes_changed(crtc_state))
4816 crtc_state->uapi.color_mgmt_changed = true;
4818 if (mode_changed || crtc_state->update_pipe ||
4819 crtc_state->uapi.color_mgmt_changed) {
4820 ret = intel_color_check(crtc_state);
4825 ret = intel_compute_pipe_wm(state, crtc);
4827 drm_dbg_kms(&dev_priv->drm,
4828 "Target pipe watermarks are invalid\n");
4833 * Calculate 'intermediate' watermarks that satisfy both the
4834 * old state and the new state. We can program these
4837 ret = intel_compute_intermediate_wm(state, crtc);
4839 drm_dbg_kms(&dev_priv->drm,
4840 "No valid intermediate pipe watermarks are possible\n");
4844 if (DISPLAY_VER(dev_priv) >= 9) {
4845 if (mode_changed || crtc_state->update_pipe) {
4846 ret = skl_update_scaler_crtc(crtc_state);
4851 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4856 if (HAS_IPS(dev_priv)) {
4857 ret = hsw_ips_compute_config(state, crtc);
4862 if (DISPLAY_VER(dev_priv) >= 9 ||
4863 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4864 ret = hsw_compute_linetime_wm(state, crtc);
4870 ret = intel_psr2_sel_fetch_update(state, crtc);
4878 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4879 struct intel_crtc_state *crtc_state)
4881 struct drm_connector *connector = conn_state->connector;
4882 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4883 const struct drm_display_info *info = &connector->display_info;
4886 switch (conn_state->max_bpc) {
4900 MISSING_CASE(conn_state->max_bpc);
4904 if (bpp < crtc_state->pipe_bpp) {
4905 drm_dbg_kms(&i915->drm,
4906 "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4907 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4908 connector->base.id, connector->name,
4910 3 * conn_state->max_requested_bpc,
4911 crtc_state->pipe_bpp);
4913 crtc_state->pipe_bpp = bpp;
4920 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4921 struct intel_crtc *crtc)
4923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4924 struct intel_crtc_state *crtc_state =
4925 intel_atomic_get_new_crtc_state(state, crtc);
4926 struct drm_connector *connector;
4927 struct drm_connector_state *connector_state;
4930 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4931 IS_CHERRYVIEW(dev_priv)))
4933 else if (DISPLAY_VER(dev_priv) >= 5)
4938 crtc_state->pipe_bpp = bpp;
4940 /* Clamp display bpp to connector max bpp */
4941 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4944 if (connector_state->crtc != &crtc->base)
4947 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4955 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4957 struct drm_device *dev = state->base.dev;
4958 struct drm_connector *connector;
4959 struct drm_connector_list_iter conn_iter;
4960 unsigned int used_ports = 0;
4961 unsigned int used_mst_ports = 0;
4965 * We're going to peek into connector->state,
4966 * hence connection_mutex must be held.
4968 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4971 * Walk the connector list instead of the encoder
4972 * list to detect the problem on ddi platforms
4973 * where there's just one encoder per digital port.
4975 drm_connector_list_iter_begin(dev, &conn_iter);
4976 drm_for_each_connector_iter(connector, &conn_iter) {
4977 struct drm_connector_state *connector_state;
4978 struct intel_encoder *encoder;
4981 drm_atomic_get_new_connector_state(&state->base,
4983 if (!connector_state)
4984 connector_state = connector->state;
4986 if (!connector_state->best_encoder)
4989 encoder = to_intel_encoder(connector_state->best_encoder);
4991 drm_WARN_ON(dev, !connector_state->crtc);
4993 switch (encoder->type) {
4994 case INTEL_OUTPUT_DDI:
4995 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4998 case INTEL_OUTPUT_DP:
4999 case INTEL_OUTPUT_HDMI:
5000 case INTEL_OUTPUT_EDP:
5001 /* the same port mustn't appear more than once */
5002 if (used_ports & BIT(encoder->port))
5005 used_ports |= BIT(encoder->port);
5007 case INTEL_OUTPUT_DP_MST:
5015 drm_connector_list_iter_end(&conn_iter);
5017 /* can't mix MST and SST/HDMI on the same port */
5018 if (used_ports & used_mst_ports)
5025 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
5026 struct intel_crtc *crtc)
5028 struct intel_crtc_state *crtc_state =
5029 intel_atomic_get_new_crtc_state(state, crtc);
5031 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5033 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
5034 crtc_state->uapi.degamma_lut);
5035 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
5036 crtc_state->uapi.gamma_lut);
5037 drm_property_replace_blob(&crtc_state->hw.ctm,
5038 crtc_state->uapi.ctm);
5042 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
5043 struct intel_crtc *crtc)
5045 struct intel_crtc_state *crtc_state =
5046 intel_atomic_get_new_crtc_state(state, crtc);
5048 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5050 crtc_state->hw.enable = crtc_state->uapi.enable;
5051 crtc_state->hw.active = crtc_state->uapi.active;
5052 drm_mode_copy(&crtc_state->hw.mode,
5053 &crtc_state->uapi.mode);
5054 drm_mode_copy(&crtc_state->hw.adjusted_mode,
5055 &crtc_state->uapi.adjusted_mode);
5056 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
5058 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
5062 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
5063 struct intel_crtc *slave_crtc)
5065 struct intel_crtc_state *slave_crtc_state =
5066 intel_atomic_get_new_crtc_state(state, slave_crtc);
5067 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5068 const struct intel_crtc_state *master_crtc_state =
5069 intel_atomic_get_new_crtc_state(state, master_crtc);
5071 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
5072 master_crtc_state->hw.degamma_lut);
5073 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
5074 master_crtc_state->hw.gamma_lut);
5075 drm_property_replace_blob(&slave_crtc_state->hw.ctm,
5076 master_crtc_state->hw.ctm);
5078 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
5082 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
5083 struct intel_crtc *slave_crtc)
5085 struct intel_crtc_state *slave_crtc_state =
5086 intel_atomic_get_new_crtc_state(state, slave_crtc);
5087 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5088 const struct intel_crtc_state *master_crtc_state =
5089 intel_atomic_get_new_crtc_state(state, master_crtc);
5090 struct intel_crtc_state *saved_state;
5092 WARN_ON(master_crtc_state->bigjoiner_pipes !=
5093 slave_crtc_state->bigjoiner_pipes);
5095 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
5099 /* preserve some things from the slave's original crtc state */
5100 saved_state->uapi = slave_crtc_state->uapi;
5101 saved_state->scaler_state = slave_crtc_state->scaler_state;
5102 saved_state->shared_dpll = slave_crtc_state->shared_dpll;
5103 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
5104 saved_state->crc_enabled = slave_crtc_state->crc_enabled;
5106 intel_crtc_free_hw_state(slave_crtc_state);
5107 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
5110 /* Re-init hw state */
5111 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
5112 slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
5113 slave_crtc_state->hw.active = master_crtc_state->hw.active;
5114 drm_mode_copy(&slave_crtc_state->hw.mode,
5115 &master_crtc_state->hw.mode);
5116 drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
5117 &master_crtc_state->hw.pipe_mode);
5118 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
5119 &master_crtc_state->hw.adjusted_mode);
5120 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
5122 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
5124 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
5125 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
5126 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
5128 WARN_ON(master_crtc_state->bigjoiner_pipes !=
5129 slave_crtc_state->bigjoiner_pipes);
5135 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
5136 struct intel_crtc *crtc)
5138 struct intel_crtc_state *crtc_state =
5139 intel_atomic_get_new_crtc_state(state, crtc);
5140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5141 struct intel_crtc_state *saved_state;
5143 saved_state = intel_crtc_state_alloc(crtc);
5147 /* free the old crtc_state->hw members */
5148 intel_crtc_free_hw_state(crtc_state);
5150 /* FIXME: before the switch to atomic started, a new pipe_config was
5151 * kzalloc'd. Code that depends on any field being zero should be
5152 * fixed, so that the crtc_state can be safely duplicated. For now,
5153 * only fields that are know to not cause problems are preserved. */
5155 saved_state->uapi = crtc_state->uapi;
5156 saved_state->scaler_state = crtc_state->scaler_state;
5157 saved_state->shared_dpll = crtc_state->shared_dpll;
5158 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5159 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5160 sizeof(saved_state->icl_port_dplls));
5161 saved_state->crc_enabled = crtc_state->crc_enabled;
5162 if (IS_G4X(dev_priv) ||
5163 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5164 saved_state->wm = crtc_state->wm;
5166 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5169 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5175 intel_modeset_pipe_config(struct intel_atomic_state *state,
5176 struct intel_crtc *crtc)
5178 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5179 struct intel_crtc_state *crtc_state =
5180 intel_atomic_get_new_crtc_state(state, crtc);
5181 struct drm_connector *connector;
5182 struct drm_connector_state *connector_state;
5183 int pipe_src_w, pipe_src_h;
5184 int base_bpp, ret, i;
5187 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5189 crtc_state->framestart_delay = 1;
5192 * Sanitize sync polarity flags based on requested ones. If neither
5193 * positive or negative polarity is requested, treat this as meaning
5194 * negative polarity.
5196 if (!(crtc_state->hw.adjusted_mode.flags &
5197 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5198 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5200 if (!(crtc_state->hw.adjusted_mode.flags &
5201 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5202 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5204 ret = compute_baseline_pipe_bpp(state, crtc);
5208 base_bpp = crtc_state->pipe_bpp;
5211 * Determine the real pipe dimensions. Note that stereo modes can
5212 * increase the actual pipe size due to the frame doubling and
5213 * insertion of additional space for blanks between the frame. This
5214 * is stored in the crtc timings. We use the requested mode to do this
5215 * computation to clearly distinguish it from the adjusted mode, which
5216 * can be changed by the connectors in the below retry loop.
5218 drm_mode_get_hv_timing(&crtc_state->hw.mode,
5219 &pipe_src_w, &pipe_src_h);
5220 drm_rect_init(&crtc_state->pipe_src, 0, 0,
5221 pipe_src_w, pipe_src_h);
5223 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5224 struct intel_encoder *encoder =
5225 to_intel_encoder(connector_state->best_encoder);
5227 if (connector_state->crtc != &crtc->base)
5230 if (!check_single_encoder_cloning(state, crtc, encoder)) {
5231 drm_dbg_kms(&i915->drm,
5232 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5233 encoder->base.base.id, encoder->base.name);
5238 * Determine output_types before calling the .compute_config()
5239 * hooks so that the hooks can use this information safely.
5241 if (encoder->compute_output_type)
5242 crtc_state->output_types |=
5243 BIT(encoder->compute_output_type(encoder, crtc_state,
5246 crtc_state->output_types |= BIT(encoder->type);
5250 /* Ensure the port clock defaults are reset when retrying. */
5251 crtc_state->port_clock = 0;
5252 crtc_state->pixel_multiplier = 1;
5254 /* Fill in default crtc timings, allow encoders to overwrite them. */
5255 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5256 CRTC_STEREO_DOUBLE);
5258 /* Pass our mode to the connectors and the CRTC to give them a chance to
5259 * adjust it according to limitations or connector properties, and also
5260 * a chance to reject the mode entirely.
5262 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5263 struct intel_encoder *encoder =
5264 to_intel_encoder(connector_state->best_encoder);
5266 if (connector_state->crtc != &crtc->base)
5269 ret = encoder->compute_config(encoder, crtc_state,
5271 if (ret == -EDEADLK)
5274 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5275 encoder->base.base.id, encoder->base.name, ret);
5280 /* Set default port clock if not overwritten by the encoder. Needs to be
5281 * done afterwards in case the encoder adjusts the mode. */
5282 if (!crtc_state->port_clock)
5283 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5284 * crtc_state->pixel_multiplier;
5286 ret = intel_crtc_compute_config(state, crtc);
5287 if (ret == -EDEADLK)
5289 if (ret == -EAGAIN) {
5290 if (drm_WARN(&i915->drm, !retry,
5291 "[CRTC:%d:%s] loop in pipe configuration computation\n",
5292 crtc->base.base.id, crtc->base.name))
5295 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5296 crtc->base.base.id, crtc->base.name);
5301 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5302 crtc->base.base.id, crtc->base.name, ret);
5306 /* Dithering seems to not pass-through bits correctly when it should, so
5307 * only enable it on 6bpc panels and when its not a compliance
5308 * test requesting 6bpc video pattern.
5310 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5311 !crtc_state->dither_force_disable;
5312 drm_dbg_kms(&i915->drm,
5313 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5314 crtc->base.base.id, crtc->base.name,
5315 base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5321 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5322 struct intel_crtc *crtc)
5324 struct intel_crtc_state *crtc_state =
5325 intel_atomic_get_new_crtc_state(state, crtc);
5326 struct drm_connector_state *conn_state;
5327 struct drm_connector *connector;
5330 intel_bigjoiner_adjust_pipe_src(crtc_state);
5332 for_each_new_connector_in_state(&state->base, connector,
5334 struct intel_encoder *encoder =
5335 to_intel_encoder(conn_state->best_encoder);
5338 if (conn_state->crtc != &crtc->base ||
5339 !encoder->compute_config_late)
5342 ret = encoder->compute_config_late(encoder, crtc_state,
5351 bool intel_fuzzy_clock_check(int clock1, int clock2)
5355 if (clock1 == clock2)
5358 if (!clock1 || !clock2)
5361 diff = abs(clock1 - clock2);
5363 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5370 intel_compare_m_n(unsigned int m, unsigned int n,
5371 unsigned int m2, unsigned int n2,
5374 if (m == m2 && n == n2)
5377 if (exact || !m || !n || !m2 || !n2)
5380 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
5387 } else if (n < n2) {
5397 return intel_fuzzy_clock_check(m, m2);
5401 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5402 const struct intel_link_m_n *m2_n2,
5405 return m_n->tu == m2_n2->tu &&
5406 intel_compare_m_n(m_n->data_m, m_n->data_n,
5407 m2_n2->data_m, m2_n2->data_n, exact) &&
5408 intel_compare_m_n(m_n->link_m, m_n->link_n,
5409 m2_n2->link_m, m2_n2->link_n, exact);
5413 intel_compare_infoframe(const union hdmi_infoframe *a,
5414 const union hdmi_infoframe *b)
5416 return memcmp(a, b, sizeof(*a)) == 0;
5420 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5421 const struct drm_dp_vsc_sdp *b)
5423 return memcmp(a, b, sizeof(*a)) == 0;
5427 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5428 bool fastset, const char *name,
5429 const union hdmi_infoframe *a,
5430 const union hdmi_infoframe *b)
5433 if (!drm_debug_enabled(DRM_UT_KMS))
5436 drm_dbg_kms(&dev_priv->drm,
5437 "fastset mismatch in %s infoframe\n", name);
5438 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5439 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5440 drm_dbg_kms(&dev_priv->drm, "found:\n");
5441 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5443 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5444 drm_err(&dev_priv->drm, "expected:\n");
5445 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5446 drm_err(&dev_priv->drm, "found:\n");
5447 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5452 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5453 bool fastset, const char *name,
5454 const struct drm_dp_vsc_sdp *a,
5455 const struct drm_dp_vsc_sdp *b)
5458 if (!drm_debug_enabled(DRM_UT_KMS))
5461 drm_dbg_kms(&dev_priv->drm,
5462 "fastset mismatch in %s dp sdp\n", name);
5463 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5464 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5465 drm_dbg_kms(&dev_priv->drm, "found:\n");
5466 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5468 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5469 drm_err(&dev_priv->drm, "expected:\n");
5470 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5471 drm_err(&dev_priv->drm, "found:\n");
5472 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5476 static void __printf(4, 5)
5477 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5478 const char *name, const char *format, ...)
5480 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5481 struct va_format vaf;
5484 va_start(args, format);
5489 drm_dbg_kms(&i915->drm,
5490 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5491 crtc->base.base.id, crtc->base.name, name, &vaf);
5493 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5494 crtc->base.base.id, crtc->base.name, name, &vaf);
5499 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5501 if (dev_priv->params.fastboot != -1)
5502 return dev_priv->params.fastboot;
5504 /* Enable fastboot by default on Skylake and newer */
5505 if (DISPLAY_VER(dev_priv) >= 9)
5508 /* Enable fastboot by default on VLV and CHV */
5509 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5512 /* Disabled by default on all others */
5517 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5518 const struct intel_crtc_state *pipe_config,
5521 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5522 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5525 bool fixup_inherited = fastset &&
5526 current_config->inherited && !pipe_config->inherited;
5528 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5529 drm_dbg_kms(&dev_priv->drm,
5530 "initial modeset and fastboot not set\n");
5534 #define PIPE_CONF_CHECK_X(name) do { \
5535 if (current_config->name != pipe_config->name) { \
5536 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5537 "(expected 0x%08x, found 0x%08x)", \
5538 current_config->name, \
5539 pipe_config->name); \
5544 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5545 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5546 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5547 "(expected 0x%08x, found 0x%08x)", \
5548 current_config->name & (mask), \
5549 pipe_config->name & (mask)); \
5554 #define PIPE_CONF_CHECK_I(name) do { \
5555 if (current_config->name != pipe_config->name) { \
5556 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5557 "(expected %i, found %i)", \
5558 current_config->name, \
5559 pipe_config->name); \
5564 #define PIPE_CONF_CHECK_BOOL(name) do { \
5565 if (current_config->name != pipe_config->name) { \
5566 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5567 "(expected %s, found %s)", \
5568 str_yes_no(current_config->name), \
5569 str_yes_no(pipe_config->name)); \
5575 * Checks state where we only read out the enabling, but not the entire
5576 * state itself (like full infoframes or ELD for audio). These states
5577 * require a full modeset on bootup to fix up.
5579 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5580 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5581 PIPE_CONF_CHECK_BOOL(name); \
5583 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5584 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5585 str_yes_no(current_config->name), \
5586 str_yes_no(pipe_config->name)); \
5591 #define PIPE_CONF_CHECK_P(name) do { \
5592 if (current_config->name != pipe_config->name) { \
5593 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5594 "(expected %p, found %p)", \
5595 current_config->name, \
5596 pipe_config->name); \
5601 #define PIPE_CONF_CHECK_M_N(name) do { \
5602 if (!intel_compare_link_m_n(¤t_config->name, \
5603 &pipe_config->name,\
5605 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5606 "(expected tu %i data %i/%i link %i/%i, " \
5607 "found tu %i, data %i/%i link %i/%i)", \
5608 current_config->name.tu, \
5609 current_config->name.data_m, \
5610 current_config->name.data_n, \
5611 current_config->name.link_m, \
5612 current_config->name.link_n, \
5613 pipe_config->name.tu, \
5614 pipe_config->name.data_m, \
5615 pipe_config->name.data_n, \
5616 pipe_config->name.link_m, \
5617 pipe_config->name.link_n); \
5622 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5623 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5624 PIPE_CONF_CHECK_I(name.crtc_htotal); \
5625 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5626 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5627 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5628 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5629 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5630 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5631 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5632 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5633 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5634 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5637 #define PIPE_CONF_CHECK_RECT(name) do { \
5638 PIPE_CONF_CHECK_I(name.x1); \
5639 PIPE_CONF_CHECK_I(name.x2); \
5640 PIPE_CONF_CHECK_I(name.y1); \
5641 PIPE_CONF_CHECK_I(name.y2); \
5644 /* This is required for BDW+ where there is only one set of registers for
5645 * switching between high and low RR.
5646 * This macro can be used whenever a comparison has to be made between one
5647 * hw state and multiple sw state variables.
5649 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
5650 if (!intel_compare_link_m_n(¤t_config->name, \
5651 &pipe_config->name, !fastset) && \
5652 !intel_compare_link_m_n(¤t_config->alt_name, \
5653 &pipe_config->name, !fastset)) { \
5654 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5655 "(expected tu %i data %i/%i link %i/%i, " \
5656 "or tu %i data %i/%i link %i/%i, " \
5657 "found tu %i, data %i/%i link %i/%i)", \
5658 current_config->name.tu, \
5659 current_config->name.data_m, \
5660 current_config->name.data_n, \
5661 current_config->name.link_m, \
5662 current_config->name.link_n, \
5663 current_config->alt_name.tu, \
5664 current_config->alt_name.data_m, \
5665 current_config->alt_name.data_n, \
5666 current_config->alt_name.link_m, \
5667 current_config->alt_name.link_n, \
5668 pipe_config->name.tu, \
5669 pipe_config->name.data_m, \
5670 pipe_config->name.data_n, \
5671 pipe_config->name.link_m, \
5672 pipe_config->name.link_n); \
5677 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5678 if ((current_config->name ^ pipe_config->name) & (mask)) { \
5679 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5680 "(%x) (expected %i, found %i)", \
5682 current_config->name & (mask), \
5683 pipe_config->name & (mask)); \
5688 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
5689 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
5690 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5691 "(expected %i, found %i)", \
5692 current_config->name, \
5693 pipe_config->name); \
5698 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5699 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
5700 &pipe_config->infoframes.name)) { \
5701 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5702 ¤t_config->infoframes.name, \
5703 &pipe_config->infoframes.name); \
5708 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5709 if (!current_config->has_psr && !pipe_config->has_psr && \
5710 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
5711 &pipe_config->infoframes.name)) { \
5712 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5713 ¤t_config->infoframes.name, \
5714 &pipe_config->infoframes.name); \
5719 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
5720 if (current_config->name1 != pipe_config->name1) { \
5721 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
5722 "(expected %i, found %i, won't compare lut values)", \
5723 current_config->name1, \
5724 pipe_config->name1); \
5727 if (!intel_color_lut_equal(current_config->name2, \
5728 pipe_config->name2, pipe_config->name1, \
5730 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
5731 "hw_state doesn't match sw_state"); \
5737 #define PIPE_CONF_QUIRK(quirk) \
5738 ((current_config->quirks | pipe_config->quirks) & (quirk))
5740 PIPE_CONF_CHECK_I(hw.enable);
5741 PIPE_CONF_CHECK_I(hw.active);
5743 PIPE_CONF_CHECK_I(cpu_transcoder);
5744 PIPE_CONF_CHECK_I(mst_master_transcoder);
5746 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5747 PIPE_CONF_CHECK_I(fdi_lanes);
5748 PIPE_CONF_CHECK_M_N(fdi_m_n);
5750 PIPE_CONF_CHECK_I(lane_count);
5751 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5753 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
5754 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
5756 PIPE_CONF_CHECK_M_N(dp_m_n);
5757 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5760 PIPE_CONF_CHECK_X(output_types);
5762 PIPE_CONF_CHECK_I(framestart_delay);
5763 PIPE_CONF_CHECK_I(msa_timing_delay);
5765 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5766 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5768 PIPE_CONF_CHECK_I(pixel_multiplier);
5770 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5771 DRM_MODE_FLAG_INTERLACE);
5773 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5774 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5775 DRM_MODE_FLAG_PHSYNC);
5776 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5777 DRM_MODE_FLAG_NHSYNC);
5778 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5779 DRM_MODE_FLAG_PVSYNC);
5780 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5781 DRM_MODE_FLAG_NVSYNC);
5784 PIPE_CONF_CHECK_I(output_format);
5785 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5786 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5787 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5788 PIPE_CONF_CHECK_BOOL(limited_color_range);
5790 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5791 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5792 PIPE_CONF_CHECK_BOOL(has_infoframe);
5793 PIPE_CONF_CHECK_BOOL(fec_enable);
5795 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5797 PIPE_CONF_CHECK_X(gmch_pfit.control);
5798 /* pfit ratios are autocomputed by the hw on gen4+ */
5799 if (DISPLAY_VER(dev_priv) < 4)
5800 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5801 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5804 * Changing the EDP transcoder input mux
5805 * (A_ONOFF vs. A_ON) requires a full modeset.
5807 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5810 PIPE_CONF_CHECK_RECT(pipe_src);
5812 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5813 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5815 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5816 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
5818 PIPE_CONF_CHECK_X(gamma_mode);
5819 if (IS_CHERRYVIEW(dev_priv))
5820 PIPE_CONF_CHECK_X(cgm_mode);
5822 PIPE_CONF_CHECK_X(csc_mode);
5823 PIPE_CONF_CHECK_BOOL(gamma_enable);
5824 PIPE_CONF_CHECK_BOOL(csc_enable);
5826 PIPE_CONF_CHECK_I(linetime);
5827 PIPE_CONF_CHECK_I(ips_linetime);
5829 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
5831 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
5833 if (current_config->active_planes) {
5834 PIPE_CONF_CHECK_BOOL(has_psr);
5835 PIPE_CONF_CHECK_BOOL(has_psr2);
5836 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5837 PIPE_CONF_CHECK_I(dc3co_exitline);
5841 PIPE_CONF_CHECK_BOOL(double_wide);
5843 if (dev_priv->dpll.mgr) {
5844 PIPE_CONF_CHECK_P(shared_dpll);
5846 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5847 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5848 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5849 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5850 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5851 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5852 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5853 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5854 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5855 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5856 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5857 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5858 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5859 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5860 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5861 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5862 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5863 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5864 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5865 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5866 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5867 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5868 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5869 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5870 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5871 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5872 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5873 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5874 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5875 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5876 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5877 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5880 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5881 PIPE_CONF_CHECK_X(dsi_pll.div);
5883 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5884 PIPE_CONF_CHECK_I(pipe_bpp);
5886 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
5887 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
5888 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5890 PIPE_CONF_CHECK_I(min_voltage_level);
5892 if (current_config->has_psr || pipe_config->has_psr)
5893 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5894 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5896 PIPE_CONF_CHECK_X(infoframes.enable);
5898 PIPE_CONF_CHECK_X(infoframes.gcp);
5899 PIPE_CONF_CHECK_INFOFRAME(avi);
5900 PIPE_CONF_CHECK_INFOFRAME(spd);
5901 PIPE_CONF_CHECK_INFOFRAME(hdmi);
5902 PIPE_CONF_CHECK_INFOFRAME(drm);
5903 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5905 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5906 PIPE_CONF_CHECK_I(master_transcoder);
5907 PIPE_CONF_CHECK_X(bigjoiner_pipes);
5909 PIPE_CONF_CHECK_I(dsc.compression_enable);
5910 PIPE_CONF_CHECK_I(dsc.dsc_split);
5911 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5913 PIPE_CONF_CHECK_BOOL(splitter.enable);
5914 PIPE_CONF_CHECK_I(splitter.link_count);
5915 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5917 PIPE_CONF_CHECK_BOOL(vrr.enable);
5918 PIPE_CONF_CHECK_I(vrr.vmin);
5919 PIPE_CONF_CHECK_I(vrr.vmax);
5920 PIPE_CONF_CHECK_I(vrr.flipline);
5921 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5922 PIPE_CONF_CHECK_I(vrr.guardband);
5924 #undef PIPE_CONF_CHECK_X
5925 #undef PIPE_CONF_CHECK_I
5926 #undef PIPE_CONF_CHECK_BOOL
5927 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5928 #undef PIPE_CONF_CHECK_P
5929 #undef PIPE_CONF_CHECK_FLAGS
5930 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
5931 #undef PIPE_CONF_CHECK_COLOR_LUT
5932 #undef PIPE_CONF_CHECK_TIMINGS
5933 #undef PIPE_CONF_CHECK_RECT
5934 #undef PIPE_CONF_QUIRK
5940 intel_verify_planes(struct intel_atomic_state *state)
5942 struct intel_plane *plane;
5943 const struct intel_plane_state *plane_state;
5946 for_each_new_intel_plane_in_state(state, plane,
5948 assert_plane(plane, plane_state->planar_slave ||
5949 plane_state->uapi.visible);
5952 int intel_modeset_all_pipes(struct intel_atomic_state *state)
5954 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5955 struct intel_crtc *crtc;
5958 * Add all pipes to the state, and force
5959 * a modeset on all the active ones.
5961 for_each_intel_crtc(&dev_priv->drm, crtc) {
5962 struct intel_crtc_state *crtc_state;
5965 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5966 if (IS_ERR(crtc_state))
5967 return PTR_ERR(crtc_state);
5969 if (!crtc_state->hw.active ||
5970 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
5973 crtc_state->uapi.mode_changed = true;
5975 ret = drm_atomic_add_affected_connectors(&state->base,
5980 ret = intel_atomic_add_affected_planes(state, crtc);
5984 crtc_state->update_planes |= crtc_state->active_planes;
5990 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
5992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5994 struct drm_display_mode adjusted_mode;
5996 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
5998 if (crtc_state->vrr.enable) {
5999 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
6000 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
6001 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
6002 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
6005 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
6007 crtc->mode_flags = crtc_state->mode_flags;
6010 * The scanline counter increments at the leading edge of hsync.
6012 * On most platforms it starts counting from vtotal-1 on the
6013 * first active line. That means the scanline counter value is
6014 * always one less than what we would expect. Ie. just after
6015 * start of vblank, which also occurs at start of hsync (on the
6016 * last active line), the scanline counter will read vblank_start-1.
6018 * On gen2 the scanline counter starts counting from 1 instead
6019 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
6020 * to keep the value positive), instead of adding one.
6022 * On HSW+ the behaviour of the scanline counter depends on the output
6023 * type. For DP ports it behaves like most other platforms, but on HDMI
6024 * there's an extra 1 line difference. So we need to add two instead of
6027 * On VLV/CHV DSI the scanline counter would appear to increment
6028 * approx. 1/3 of a scanline before start of vblank. Unfortunately
6029 * that means we can't tell whether we're in vblank or not while
6030 * we're on that particular line. We must still set scanline_offset
6031 * to 1 so that the vblank timestamps come out correct when we query
6032 * the scanline counter from within the vblank interrupt handler.
6033 * However if queried just before the start of vblank we'll get an
6034 * answer that's slightly in the future.
6036 if (DISPLAY_VER(dev_priv) == 2) {
6039 vtotal = adjusted_mode.crtc_vtotal;
6040 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6043 crtc->scanline_offset = vtotal - 1;
6044 } else if (HAS_DDI(dev_priv) &&
6045 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
6046 crtc->scanline_offset = 2;
6048 crtc->scanline_offset = 1;
6052 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
6054 struct intel_crtc_state *new_crtc_state;
6055 struct intel_crtc *crtc;
6058 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6059 if (!intel_crtc_needs_modeset(new_crtc_state))
6062 intel_release_shared_dplls(state, crtc);
6067 * This implements the workaround described in the "notes" section of the mode
6068 * set sequence documentation. When going from no pipes or single pipe to
6069 * multiple pipes, and planes are enabled after the pipe, we need to wait at
6070 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
6072 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
6074 struct intel_crtc_state *crtc_state;
6075 struct intel_crtc *crtc;
6076 struct intel_crtc_state *first_crtc_state = NULL;
6077 struct intel_crtc_state *other_crtc_state = NULL;
6078 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
6081 /* look at all crtc's that are going to be enabled in during modeset */
6082 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6083 if (!crtc_state->hw.active ||
6084 !intel_crtc_needs_modeset(crtc_state))
6087 if (first_crtc_state) {
6088 other_crtc_state = crtc_state;
6091 first_crtc_state = crtc_state;
6092 first_pipe = crtc->pipe;
6096 /* No workaround needed? */
6097 if (!first_crtc_state)
6100 /* w/a possibly needed, check how many crtc's are already enabled. */
6101 for_each_intel_crtc(state->base.dev, crtc) {
6102 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6103 if (IS_ERR(crtc_state))
6104 return PTR_ERR(crtc_state);
6106 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
6108 if (!crtc_state->hw.active ||
6109 intel_crtc_needs_modeset(crtc_state))
6112 /* 2 or more enabled crtcs means no need for w/a */
6113 if (enabled_pipe != INVALID_PIPE)
6116 enabled_pipe = crtc->pipe;
6119 if (enabled_pipe != INVALID_PIPE)
6120 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
6121 else if (other_crtc_state)
6122 other_crtc_state->hsw_workaround_pipe = first_pipe;
6127 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
6130 const struct intel_crtc_state *crtc_state;
6131 struct intel_crtc *crtc;
6134 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6135 if (crtc_state->hw.active)
6136 active_pipes |= BIT(crtc->pipe);
6138 active_pipes &= ~BIT(crtc->pipe);
6141 return active_pipes;
6144 static int intel_modeset_checks(struct intel_atomic_state *state)
6146 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6148 state->modeset = true;
6150 if (IS_HASWELL(dev_priv))
6151 return hsw_mode_set_planes_workaround(state);
6156 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
6157 struct intel_crtc_state *new_crtc_state)
6159 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
6162 new_crtc_state->uapi.mode_changed = false;
6163 new_crtc_state->update_pipe = true;
6166 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
6167 struct intel_crtc_state *new_crtc_state)
6170 * If we're not doing the full modeset we want to
6171 * keep the current M/N values as they may be
6172 * sufficiently different to the computed values
6173 * to cause problems.
6175 * FIXME: should really copy more fuzzy state here
6177 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
6178 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
6179 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
6180 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
6183 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
6184 struct intel_crtc *crtc,
6187 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6188 struct intel_plane *plane;
6190 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6191 struct intel_plane_state *plane_state;
6193 if ((plane_ids_mask & BIT(plane->id)) == 0)
6196 plane_state = intel_atomic_get_plane_state(state, plane);
6197 if (IS_ERR(plane_state))
6198 return PTR_ERR(plane_state);
6204 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
6205 struct intel_crtc *crtc)
6207 const struct intel_crtc_state *old_crtc_state =
6208 intel_atomic_get_old_crtc_state(state, crtc);
6209 const struct intel_crtc_state *new_crtc_state =
6210 intel_atomic_get_new_crtc_state(state, crtc);
6212 return intel_crtc_add_planes_to_state(state, crtc,
6213 old_crtc_state->enabled_planes |
6214 new_crtc_state->enabled_planes);
6217 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
6219 /* See {hsw,vlv,ivb}_plane_ratio() */
6220 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
6221 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6222 IS_IVYBRIDGE(dev_priv);
6225 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
6226 struct intel_crtc *crtc,
6227 struct intel_crtc *other)
6229 const struct intel_plane_state *plane_state;
6230 struct intel_plane *plane;
6234 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6235 if (plane->pipe == crtc->pipe)
6236 plane_ids |= BIT(plane->id);
6239 return intel_crtc_add_planes_to_state(state, other, plane_ids);
6242 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6244 struct drm_i915_private *i915 = to_i915(state->base.dev);
6245 const struct intel_crtc_state *crtc_state;
6246 struct intel_crtc *crtc;
6249 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6250 struct intel_crtc *other;
6252 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6253 crtc_state->bigjoiner_pipes) {
6259 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6268 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6270 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6271 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6272 struct intel_plane_state *plane_state;
6273 struct intel_plane *plane;
6274 struct intel_crtc *crtc;
6277 ret = icl_add_linked_planes(state);
6281 ret = intel_bigjoiner_add_affected_planes(state);
6285 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6286 ret = intel_plane_atomic_check(state, plane);
6288 drm_dbg_atomic(&dev_priv->drm,
6289 "[PLANE:%d:%s] atomic driver check failed\n",
6290 plane->base.base.id, plane->base.name);
6295 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6296 new_crtc_state, i) {
6297 u8 old_active_planes, new_active_planes;
6299 ret = icl_check_nv12_planes(new_crtc_state);
6304 * On some platforms the number of active planes affects
6305 * the planes' minimum cdclk calculation. Add such planes
6306 * to the state before we compute the minimum cdclk.
6308 if (!active_planes_affects_min_cdclk(dev_priv))
6311 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6312 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6314 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6317 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6325 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6327 struct intel_crtc_state *crtc_state;
6328 struct intel_crtc *crtc;
6331 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6332 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6335 ret = intel_crtc_atomic_check(state, crtc);
6337 drm_dbg_atomic(&i915->drm,
6338 "[CRTC:%d:%s] atomic driver check failed\n",
6339 crtc->base.base.id, crtc->base.name);
6347 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6350 const struct intel_crtc_state *new_crtc_state;
6351 struct intel_crtc *crtc;
6354 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6355 if (new_crtc_state->hw.enable &&
6356 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6357 intel_crtc_needs_modeset(new_crtc_state))
6364 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6367 const struct intel_crtc_state *new_crtc_state;
6368 struct intel_crtc *crtc;
6371 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6372 if (new_crtc_state->hw.enable &&
6373 pipes & BIT(crtc->pipe) &&
6374 intel_crtc_needs_modeset(new_crtc_state))
6381 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6382 struct intel_crtc *master_crtc)
6384 struct drm_i915_private *i915 = to_i915(state->base.dev);
6385 struct intel_crtc_state *master_crtc_state =
6386 intel_atomic_get_new_crtc_state(state, master_crtc);
6387 struct intel_crtc *slave_crtc;
6389 if (!master_crtc_state->bigjoiner_pipes)
6393 if (drm_WARN_ON(&i915->drm,
6394 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6397 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6398 drm_dbg_kms(&i915->drm,
6399 "[CRTC:%d:%s] Cannot act as big joiner master "
6400 "(need 0x%x as pipes, only 0x%x possible)\n",
6401 master_crtc->base.base.id, master_crtc->base.name,
6402 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6406 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6407 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6408 struct intel_crtc_state *slave_crtc_state;
6411 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6412 if (IS_ERR(slave_crtc_state))
6413 return PTR_ERR(slave_crtc_state);
6415 /* master being enabled, slave was already configured? */
6416 if (slave_crtc_state->uapi.enable) {
6417 drm_dbg_kms(&i915->drm,
6418 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6419 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6420 slave_crtc->base.base.id, slave_crtc->base.name,
6421 master_crtc->base.base.id, master_crtc->base.name);
6426 * The state copy logic assumes the master crtc gets processed
6427 * before the slave crtc during the main compute_config loop.
6428 * This works because the crtcs are created in pipe order,
6429 * and the hardware requires master pipe < slave pipe as well.
6430 * Should that change we need to rethink the logic.
6432 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6433 drm_crtc_index(&slave_crtc->base)))
6436 drm_dbg_kms(&i915->drm,
6437 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6438 slave_crtc->base.base.id, slave_crtc->base.name,
6439 master_crtc->base.base.id, master_crtc->base.name);
6441 slave_crtc_state->bigjoiner_pipes =
6442 master_crtc_state->bigjoiner_pipes;
6444 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6452 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6453 struct intel_crtc *master_crtc)
6455 struct drm_i915_private *i915 = to_i915(state->base.dev);
6456 struct intel_crtc_state *master_crtc_state =
6457 intel_atomic_get_new_crtc_state(state, master_crtc);
6458 struct intel_crtc *slave_crtc;
6460 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6461 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6462 struct intel_crtc_state *slave_crtc_state =
6463 intel_atomic_get_new_crtc_state(state, slave_crtc);
6465 slave_crtc_state->bigjoiner_pipes = 0;
6467 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6470 master_crtc_state->bigjoiner_pipes = 0;
6474 * DOC: asynchronous flip implementation
6476 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6477 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6478 * Correspondingly, support is currently added for primary plane only.
6480 * Async flip can only change the plane surface address, so anything else
6481 * changing is rejected from the intel_async_flip_check_hw() function.
6482 * Once this check is cleared, flip done interrupt is enabled using
6483 * the intel_crtc_enable_flip_done() function.
6485 * As soon as the surface address register is written, flip done interrupt is
6486 * generated and the requested events are sent to the usersapce in the interrupt
6487 * handler itself. The timestamp and sequence sent during the flip done event
6488 * correspond to the last vblank and have no relation to the actual time when
6489 * the flip done event was sent.
6491 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6492 struct intel_crtc *crtc)
6494 struct drm_i915_private *i915 = to_i915(state->base.dev);
6495 const struct intel_crtc_state *new_crtc_state =
6496 intel_atomic_get_new_crtc_state(state, crtc);
6497 const struct intel_plane_state *old_plane_state;
6498 struct intel_plane_state *new_plane_state;
6499 struct intel_plane *plane;
6502 if (!new_crtc_state->uapi.async_flip)
6505 if (!new_crtc_state->uapi.active) {
6506 drm_dbg_kms(&i915->drm,
6507 "[CRTC:%d:%s] not active\n",
6508 crtc->base.base.id, crtc->base.name);
6512 if (intel_crtc_needs_modeset(new_crtc_state)) {
6513 drm_dbg_kms(&i915->drm,
6514 "[CRTC:%d:%s] modeset required\n",
6515 crtc->base.base.id, crtc->base.name);
6519 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6520 new_plane_state, i) {
6521 if (plane->pipe != crtc->pipe)
6525 * TODO: Async flip is only supported through the page flip IOCTL
6526 * as of now. So support currently added for primary plane only.
6527 * Support for other planes on platforms on which supports
6528 * this(vlv/chv and icl+) should be added when async flip is
6529 * enabled in the atomic IOCTL path.
6531 if (!plane->async_flip) {
6532 drm_dbg_kms(&i915->drm,
6533 "[PLANE:%d:%s] async flip not supported\n",
6534 plane->base.base.id, plane->base.name);
6538 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6539 drm_dbg_kms(&i915->drm,
6540 "[PLANE:%d:%s] no old or new framebuffer\n",
6541 plane->base.base.id, plane->base.name);
6549 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6551 struct drm_i915_private *i915 = to_i915(state->base.dev);
6552 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6553 const struct intel_plane_state *new_plane_state, *old_plane_state;
6554 struct intel_plane *plane;
6557 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6558 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6560 if (!new_crtc_state->uapi.async_flip)
6563 if (!new_crtc_state->hw.active) {
6564 drm_dbg_kms(&i915->drm,
6565 "[CRTC:%d:%s] not active\n",
6566 crtc->base.base.id, crtc->base.name);
6570 if (intel_crtc_needs_modeset(new_crtc_state)) {
6571 drm_dbg_kms(&i915->drm,
6572 "[CRTC:%d:%s] modeset required\n",
6573 crtc->base.base.id, crtc->base.name);
6577 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6578 drm_dbg_kms(&i915->drm,
6579 "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6580 crtc->base.base.id, crtc->base.name);
6584 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6585 new_plane_state, i) {
6586 if (plane->pipe != crtc->pipe)
6590 * Only async flip capable planes should be in the state
6591 * if we're really about to ask the hardware to perform
6592 * an async flip. We should never get this far otherwise.
6594 if (drm_WARN_ON(&i915->drm,
6595 new_crtc_state->do_async_flip && !plane->async_flip))
6599 * Only check async flip capable planes other planes
6600 * may be involved in the initial commit due to
6601 * the wm0/ddb optimization.
6603 * TODO maybe should track which planes actually
6604 * were requested to do the async flip...
6606 if (!plane->async_flip)
6610 * FIXME: This check is kept generic for all platforms.
6611 * Need to verify this for all gen9 platforms to enable
6612 * this selectively if required.
6614 switch (new_plane_state->hw.fb->modifier) {
6615 case I915_FORMAT_MOD_X_TILED:
6616 case I915_FORMAT_MOD_Y_TILED:
6617 case I915_FORMAT_MOD_Yf_TILED:
6618 case I915_FORMAT_MOD_4_TILED:
6621 drm_dbg_kms(&i915->drm,
6622 "[PLANE:%d:%s] Modifier does not support async flips\n",
6623 plane->base.base.id, plane->base.name);
6627 if (new_plane_state->hw.fb->format->num_planes > 1) {
6628 drm_dbg_kms(&i915->drm,
6629 "[PLANE:%d:%s] Planar formats do not support async flips\n",
6630 plane->base.base.id, plane->base.name);
6634 if (old_plane_state->view.color_plane[0].mapping_stride !=
6635 new_plane_state->view.color_plane[0].mapping_stride) {
6636 drm_dbg_kms(&i915->drm,
6637 "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6638 plane->base.base.id, plane->base.name);
6642 if (old_plane_state->hw.fb->modifier !=
6643 new_plane_state->hw.fb->modifier) {
6644 drm_dbg_kms(&i915->drm,
6645 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6646 plane->base.base.id, plane->base.name);
6650 if (old_plane_state->hw.fb->format !=
6651 new_plane_state->hw.fb->format) {
6652 drm_dbg_kms(&i915->drm,
6653 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6654 plane->base.base.id, plane->base.name);
6658 if (old_plane_state->hw.rotation !=
6659 new_plane_state->hw.rotation) {
6660 drm_dbg_kms(&i915->drm,
6661 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6662 plane->base.base.id, plane->base.name);
6666 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6667 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6668 drm_dbg_kms(&i915->drm,
6669 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6670 plane->base.base.id, plane->base.name);
6674 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6675 drm_dbg_kms(&i915->drm,
6676 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6677 plane->base.base.id, plane->base.name);
6681 if (old_plane_state->hw.pixel_blend_mode !=
6682 new_plane_state->hw.pixel_blend_mode) {
6683 drm_dbg_kms(&i915->drm,
6684 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6685 plane->base.base.id, plane->base.name);
6689 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6690 drm_dbg_kms(&i915->drm,
6691 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6692 plane->base.base.id, plane->base.name);
6696 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6697 drm_dbg_kms(&i915->drm,
6698 "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6699 plane->base.base.id, plane->base.name);
6703 /* plane decryption is allow to change only in synchronous flips */
6704 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6705 drm_dbg_kms(&i915->drm,
6706 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6707 plane->base.base.id, plane->base.name);
6715 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6717 struct drm_i915_private *i915 = to_i915(state->base.dev);
6718 struct intel_crtc_state *crtc_state;
6719 struct intel_crtc *crtc;
6720 u8 affected_pipes = 0;
6721 u8 modeset_pipes = 0;
6724 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6725 affected_pipes |= crtc_state->bigjoiner_pipes;
6726 if (intel_crtc_needs_modeset(crtc_state))
6727 modeset_pipes |= crtc_state->bigjoiner_pipes;
6730 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6731 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6732 if (IS_ERR(crtc_state))
6733 return PTR_ERR(crtc_state);
6736 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6739 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6741 crtc_state->uapi.mode_changed = true;
6743 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6747 ret = intel_atomic_add_affected_planes(state, crtc);
6752 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6753 /* Kill old bigjoiner link, we may re-establish afterwards */
6754 if (intel_crtc_needs_modeset(crtc_state) &&
6755 intel_crtc_is_bigjoiner_master(crtc_state))
6756 kill_bigjoiner_slave(state, crtc);
6763 * intel_atomic_check - validate state object
6765 * @_state: state to validate
6767 static int intel_atomic_check(struct drm_device *dev,
6768 struct drm_atomic_state *_state)
6770 struct drm_i915_private *dev_priv = to_i915(dev);
6771 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6772 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6773 struct intel_crtc *crtc;
6775 bool any_ms = false;
6777 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6778 new_crtc_state, i) {
6779 if (new_crtc_state->inherited != old_crtc_state->inherited)
6780 new_crtc_state->uapi.mode_changed = true;
6782 if (new_crtc_state->uapi.scaling_filter !=
6783 old_crtc_state->uapi.scaling_filter)
6784 new_crtc_state->uapi.mode_changed = true;
6787 intel_vrr_check_modeset(state);
6789 ret = drm_atomic_helper_check_modeset(dev, &state->base);
6793 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6794 ret = intel_async_flip_check_uapi(state, crtc);
6799 ret = intel_bigjoiner_add_affected_crtcs(state);
6803 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6804 new_crtc_state, i) {
6805 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6806 if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6807 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6809 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6813 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6814 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6818 ret = intel_crtc_prepare_cleared_state(state, crtc);
6822 if (!new_crtc_state->hw.enable)
6825 ret = intel_modeset_pipe_config(state, crtc);
6829 ret = intel_atomic_check_bigjoiner(state, crtc);
6834 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6835 new_crtc_state, i) {
6836 if (!intel_crtc_needs_modeset(new_crtc_state))
6839 ret = intel_modeset_pipe_config_late(state, crtc);
6843 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6847 * Check if fastset is allowed by external dependencies like other
6848 * pipes and transcoders.
6850 * Right now it only forces a fullmodeset when the MST master
6851 * transcoder did not changed but the pipe of the master transcoder
6852 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6853 * in case of port synced crtcs, if one of the synced crtcs
6854 * needs a full modeset, all other synced crtcs should be
6855 * forced a full modeset.
6857 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6858 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6861 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6862 enum transcoder master = new_crtc_state->mst_master_transcoder;
6864 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6865 new_crtc_state->uapi.mode_changed = true;
6866 new_crtc_state->update_pipe = false;
6870 if (is_trans_port_sync_mode(new_crtc_state)) {
6871 u8 trans = new_crtc_state->sync_mode_slaves_mask;
6873 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6874 trans |= BIT(new_crtc_state->master_transcoder);
6876 if (intel_cpu_transcoders_need_modeset(state, trans)) {
6877 new_crtc_state->uapi.mode_changed = true;
6878 new_crtc_state->update_pipe = false;
6882 if (new_crtc_state->bigjoiner_pipes) {
6883 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6884 new_crtc_state->uapi.mode_changed = true;
6885 new_crtc_state->update_pipe = false;
6890 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6891 new_crtc_state, i) {
6892 if (intel_crtc_needs_modeset(new_crtc_state)) {
6897 if (!new_crtc_state->update_pipe)
6900 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
6903 if (any_ms && !check_digital_port_conflicts(state)) {
6904 drm_dbg_kms(&dev_priv->drm,
6905 "rejecting conflicting digital port configuration\n");
6910 ret = drm_dp_mst_atomic_check(&state->base);
6914 ret = intel_atomic_check_planes(state);
6918 ret = intel_compute_global_watermarks(state);
6922 ret = intel_bw_atomic_check(state);
6926 ret = intel_cdclk_atomic_check(state, &any_ms);
6930 if (intel_any_crtc_needs_modeset(state))
6934 ret = intel_modeset_checks(state);
6938 ret = intel_modeset_calc_cdclk(state);
6942 intel_modeset_clear_plls(state);
6945 ret = intel_atomic_check_crtcs(state);
6949 ret = intel_fbc_atomic_check(state);
6953 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6954 new_crtc_state, i) {
6955 ret = intel_async_flip_check_hw(state, crtc);
6959 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6960 !new_crtc_state->update_pipe)
6963 intel_crtc_state_dump(new_crtc_state, state,
6964 intel_crtc_needs_modeset(new_crtc_state) ?
6965 "modeset" : "fastset");
6971 if (ret == -EDEADLK)
6975 * FIXME would probably be nice to know which crtc specifically
6976 * caused the failure, in cases where we can pinpoint it.
6978 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6980 intel_crtc_state_dump(new_crtc_state, state, "failed");
6985 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6987 struct intel_crtc_state *crtc_state;
6988 struct intel_crtc *crtc;
6991 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6995 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6996 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6998 if (mode_changed || crtc_state->update_pipe ||
6999 crtc_state->uapi.color_mgmt_changed) {
7000 intel_dsb_prepare(crtc_state);
7007 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
7008 struct intel_crtc_state *crtc_state)
7010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7012 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
7013 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7015 if (crtc_state->has_pch_encoder) {
7016 enum pipe pch_transcoder =
7017 intel_crtc_pch_transcoder(crtc);
7019 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
7023 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
7024 const struct intel_crtc_state *new_crtc_state)
7026 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7027 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7030 * Update pipe size and adjust fitter if needed: the reason for this is
7031 * that in compute_mode_changes we check the native mode (not the pfit
7032 * mode) to see if we can flip rather than do a full mode set. In the
7033 * fastboot case, we'll flip, but if we don't update the pipesrc and
7034 * pfit state, we'll end up with a big fb scanned out into the wrong
7037 intel_set_pipe_src_size(new_crtc_state);
7039 /* on skylake this is done by detaching scalers */
7040 if (DISPLAY_VER(dev_priv) >= 9) {
7041 if (new_crtc_state->pch_pfit.enabled)
7042 skl_pfit_enable(new_crtc_state);
7043 } else if (HAS_PCH_SPLIT(dev_priv)) {
7044 if (new_crtc_state->pch_pfit.enabled)
7045 ilk_pfit_enable(new_crtc_state);
7046 else if (old_crtc_state->pch_pfit.enabled)
7047 ilk_pfit_disable(old_crtc_state);
7051 * The register is supposedly single buffered so perhaps
7052 * not 100% correct to do this here. But SKL+ calculate
7053 * this based on the adjust pixel rate so pfit changes do
7054 * affect it and so it must be updated for fastsets.
7055 * HSW/BDW only really need this here for fastboot, after
7056 * that the value should not change without a full modeset.
7058 if (DISPLAY_VER(dev_priv) >= 9 ||
7059 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7060 hsw_set_linetime_wm(new_crtc_state);
7063 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
7064 struct intel_crtc *crtc)
7066 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7067 const struct intel_crtc_state *old_crtc_state =
7068 intel_atomic_get_old_crtc_state(state, crtc);
7069 const struct intel_crtc_state *new_crtc_state =
7070 intel_atomic_get_new_crtc_state(state, crtc);
7071 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7074 * During modesets pipe configuration was programmed as the
7078 if (new_crtc_state->uapi.color_mgmt_changed ||
7079 new_crtc_state->update_pipe)
7080 intel_color_commit_arm(new_crtc_state);
7082 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7083 bdw_set_pipemisc(new_crtc_state);
7085 if (new_crtc_state->update_pipe)
7086 intel_pipe_fastset(old_crtc_state, new_crtc_state);
7089 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
7091 intel_atomic_update_watermarks(state, crtc);
7094 static void commit_pipe_post_planes(struct intel_atomic_state *state,
7095 struct intel_crtc *crtc)
7097 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7098 const struct intel_crtc_state *new_crtc_state =
7099 intel_atomic_get_new_crtc_state(state, crtc);
7102 * Disable the scaler(s) after the plane(s) so that we don't
7103 * get a catastrophic underrun even if the two operations
7104 * end up happening in two different frames.
7106 if (DISPLAY_VER(dev_priv) >= 9 &&
7107 !intel_crtc_needs_modeset(new_crtc_state))
7108 skl_detach_scalers(new_crtc_state);
7111 static void intel_enable_crtc(struct intel_atomic_state *state,
7112 struct intel_crtc *crtc)
7114 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7115 const struct intel_crtc_state *new_crtc_state =
7116 intel_atomic_get_new_crtc_state(state, crtc);
7118 if (!intel_crtc_needs_modeset(new_crtc_state))
7121 intel_crtc_update_active_timings(new_crtc_state);
7123 dev_priv->display->crtc_enable(state, crtc);
7125 if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7128 /* vblanks work again, re-enable pipe CRC. */
7129 intel_crtc_enable_pipe_crc(crtc);
7132 static void intel_update_crtc(struct intel_atomic_state *state,
7133 struct intel_crtc *crtc)
7135 struct drm_i915_private *i915 = to_i915(state->base.dev);
7136 const struct intel_crtc_state *old_crtc_state =
7137 intel_atomic_get_old_crtc_state(state, crtc);
7138 struct intel_crtc_state *new_crtc_state =
7139 intel_atomic_get_new_crtc_state(state, crtc);
7140 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7143 if (new_crtc_state->preload_luts &&
7144 (new_crtc_state->uapi.color_mgmt_changed ||
7145 new_crtc_state->update_pipe))
7146 intel_color_load_luts(new_crtc_state);
7148 intel_pre_plane_update(state, crtc);
7150 if (new_crtc_state->update_pipe)
7151 intel_encoders_update_pipe(state, crtc);
7153 if (DISPLAY_VER(i915) >= 11 &&
7154 new_crtc_state->update_pipe)
7155 icl_set_pipe_chicken(new_crtc_state);
7158 intel_fbc_update(state, crtc);
7161 (new_crtc_state->uapi.color_mgmt_changed ||
7162 new_crtc_state->update_pipe))
7163 intel_color_commit_noarm(new_crtc_state);
7165 intel_crtc_planes_update_noarm(state, crtc);
7167 /* Perform vblank evasion around commit operation */
7168 intel_pipe_update_start(new_crtc_state);
7170 commit_pipe_pre_planes(state, crtc);
7172 intel_crtc_planes_update_arm(state, crtc);
7174 commit_pipe_post_planes(state, crtc);
7176 intel_pipe_update_end(new_crtc_state);
7179 * We usually enable FIFO underrun interrupts as part of the
7180 * CRTC enable sequence during modesets. But when we inherit a
7181 * valid pipe configuration from the BIOS we need to take care
7182 * of enabling them on the CRTC's first fastset.
7184 if (new_crtc_state->update_pipe && !modeset &&
7185 old_crtc_state->inherited)
7186 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
7189 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
7190 struct intel_crtc_state *old_crtc_state,
7191 struct intel_crtc_state *new_crtc_state,
7192 struct intel_crtc *crtc)
7194 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7197 * We need to disable pipe CRC before disabling the pipe,
7198 * or we race against vblank off.
7200 intel_crtc_disable_pipe_crc(crtc);
7202 dev_priv->display->crtc_disable(state, crtc);
7203 crtc->active = false;
7204 intel_fbc_disable(crtc);
7205 intel_disable_shared_dpll(old_crtc_state);
7207 /* FIXME unify this for all platforms */
7208 if (!new_crtc_state->hw.active &&
7209 !HAS_GMCH(dev_priv))
7210 intel_initial_watermarks(state, crtc);
7213 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
7215 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7216 struct intel_crtc *crtc;
7220 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7221 new_crtc_state, i) {
7222 if (!intel_crtc_needs_modeset(new_crtc_state))
7225 if (!old_crtc_state->hw.active)
7228 intel_pre_plane_update(state, crtc);
7229 intel_crtc_disable_planes(state, crtc);
7232 /* Only disable port sync and MST slaves */
7233 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7234 new_crtc_state, i) {
7235 if (!intel_crtc_needs_modeset(new_crtc_state))
7238 if (!old_crtc_state->hw.active)
7241 /* In case of Transcoder port Sync master slave CRTCs can be
7242 * assigned in any order and we need to make sure that
7243 * slave CRTCs are disabled first and then master CRTC since
7244 * Slave vblanks are masked till Master Vblanks.
7246 if (!is_trans_port_sync_slave(old_crtc_state) &&
7247 !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7248 !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7251 intel_old_crtc_state_disables(state, old_crtc_state,
7252 new_crtc_state, crtc);
7253 handled |= BIT(crtc->pipe);
7256 /* Disable everything else left on */
7257 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7258 new_crtc_state, i) {
7259 if (!intel_crtc_needs_modeset(new_crtc_state) ||
7260 (handled & BIT(crtc->pipe)))
7263 if (!old_crtc_state->hw.active)
7266 intel_old_crtc_state_disables(state, old_crtc_state,
7267 new_crtc_state, crtc);
7271 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7273 struct intel_crtc_state *new_crtc_state;
7274 struct intel_crtc *crtc;
7277 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7278 if (!new_crtc_state->hw.active)
7281 intel_enable_crtc(state, crtc);
7282 intel_update_crtc(state, crtc);
7286 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7288 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7289 struct intel_crtc *crtc;
7290 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7291 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7292 u8 update_pipes = 0, modeset_pipes = 0;
7295 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7296 enum pipe pipe = crtc->pipe;
7298 if (!new_crtc_state->hw.active)
7301 /* ignore allocations for crtc's that have been turned off. */
7302 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7303 entries[pipe] = old_crtc_state->wm.skl.ddb;
7304 update_pipes |= BIT(pipe);
7306 modeset_pipes |= BIT(pipe);
7311 * Whenever the number of active pipes changes, we need to make sure we
7312 * update the pipes in the right order so that their ddb allocations
7313 * never overlap with each other between CRTC updates. Otherwise we'll
7314 * cause pipe underruns and other bad stuff.
7316 * So first lets enable all pipes that do not need a fullmodeset as
7317 * those don't have any external dependency.
7319 while (update_pipes) {
7320 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7321 new_crtc_state, i) {
7322 enum pipe pipe = crtc->pipe;
7324 if ((update_pipes & BIT(pipe)) == 0)
7327 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7328 entries, I915_MAX_PIPES, pipe))
7331 entries[pipe] = new_crtc_state->wm.skl.ddb;
7332 update_pipes &= ~BIT(pipe);
7334 intel_update_crtc(state, crtc);
7337 * If this is an already active pipe, it's DDB changed,
7338 * and this isn't the last pipe that needs updating
7339 * then we need to wait for a vblank to pass for the
7340 * new ddb allocation to take effect.
7342 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7343 &old_crtc_state->wm.skl.ddb) &&
7344 (update_pipes | modeset_pipes))
7345 intel_crtc_wait_for_next_vblank(crtc);
7349 update_pipes = modeset_pipes;
7352 * Enable all pipes that needs a modeset and do not depends on other
7355 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7356 enum pipe pipe = crtc->pipe;
7358 if ((modeset_pipes & BIT(pipe)) == 0)
7361 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7362 is_trans_port_sync_master(new_crtc_state) ||
7363 intel_crtc_is_bigjoiner_master(new_crtc_state))
7366 modeset_pipes &= ~BIT(pipe);
7368 intel_enable_crtc(state, crtc);
7372 * Then we enable all remaining pipes that depend on other
7373 * pipes: MST slaves and port sync masters, big joiner master
7375 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7376 enum pipe pipe = crtc->pipe;
7378 if ((modeset_pipes & BIT(pipe)) == 0)
7381 modeset_pipes &= ~BIT(pipe);
7383 intel_enable_crtc(state, crtc);
7387 * Finally we do the plane updates/etc. for all pipes that got enabled.
7389 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7390 enum pipe pipe = crtc->pipe;
7392 if ((update_pipes & BIT(pipe)) == 0)
7395 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7396 entries, I915_MAX_PIPES, pipe));
7398 entries[pipe] = new_crtc_state->wm.skl.ddb;
7399 update_pipes &= ~BIT(pipe);
7401 intel_update_crtc(state, crtc);
7404 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7405 drm_WARN_ON(&dev_priv->drm, update_pipes);
7408 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7410 struct intel_atomic_state *state, *next;
7411 struct llist_node *freed;
7413 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
7414 llist_for_each_entry_safe(state, next, freed, freed)
7415 drm_atomic_state_put(&state->base);
7418 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7420 struct drm_i915_private *dev_priv =
7421 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
7423 intel_atomic_helper_free_state(dev_priv);
7426 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7428 struct wait_queue_entry wait_fence, wait_reset;
7429 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7431 init_wait_entry(&wait_fence, 0);
7432 init_wait_entry(&wait_reset, 0);
7434 prepare_to_wait(&intel_state->commit_ready.wait,
7435 &wait_fence, TASK_UNINTERRUPTIBLE);
7436 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7437 I915_RESET_MODESET),
7438 &wait_reset, TASK_UNINTERRUPTIBLE);
7441 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7442 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7447 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7448 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7449 I915_RESET_MODESET),
7453 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
7455 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7456 struct intel_crtc *crtc;
7459 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7461 intel_dsb_cleanup(old_crtc_state);
7464 static void intel_atomic_cleanup_work(struct work_struct *work)
7466 struct intel_atomic_state *state =
7467 container_of(work, struct intel_atomic_state, base.commit_work);
7468 struct drm_i915_private *i915 = to_i915(state->base.dev);
7470 intel_cleanup_dsbs(state);
7471 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7472 drm_atomic_helper_commit_cleanup_done(&state->base);
7473 drm_atomic_state_put(&state->base);
7475 intel_atomic_helper_free_state(i915);
7478 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7480 struct drm_i915_private *i915 = to_i915(state->base.dev);
7481 struct intel_plane *plane;
7482 struct intel_plane_state *plane_state;
7485 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7486 struct drm_framebuffer *fb = plane_state->hw.fb;
7493 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7498 * The layout of the fast clear color value expected by HW
7499 * (the DRM ABI requiring this value to be located in fb at
7500 * offset 0 of cc plane, plane #2 previous generations or
7501 * plane #1 for flat ccs):
7502 * - 4 x 4 bytes per-channel value
7503 * (in surface type specific float/int format provided by the fb user)
7504 * - 8 bytes native color value used by the display
7505 * (converted/written by GPU during a fast clear operation using the
7506 * above per-channel values)
7508 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7509 * caller made sure that the object is synced wrt. the related color clear value
7512 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7513 fb->offsets[cc_plane] + 16,
7514 &plane_state->ccval,
7515 sizeof(plane_state->ccval));
7516 /* The above could only fail if the FB obj has an unexpected backing store type. */
7517 drm_WARN_ON(&i915->drm, ret);
7521 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7523 struct drm_device *dev = state->base.dev;
7524 struct drm_i915_private *dev_priv = to_i915(dev);
7525 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7526 struct intel_crtc *crtc;
7527 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7528 intel_wakeref_t wakeref = 0;
7531 intel_atomic_commit_fence_wait(state);
7533 drm_atomic_helper_wait_for_dependencies(&state->base);
7536 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
7538 intel_atomic_prepare_plane_clear_colors(state);
7540 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7541 new_crtc_state, i) {
7542 if (intel_crtc_needs_modeset(new_crtc_state) ||
7543 new_crtc_state->update_pipe) {
7544 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7548 intel_commit_modeset_disables(state);
7550 /* FIXME: Eventually get rid of our crtc->config pointer */
7551 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7552 crtc->config = new_crtc_state;
7554 if (state->modeset) {
7555 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7557 intel_set_cdclk_pre_plane_update(state);
7559 intel_modeset_verify_disabled(dev_priv, state);
7562 intel_sagv_pre_plane_update(state);
7564 /* Complete the events for pipes that have now been disabled */
7565 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7566 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7568 /* Complete events for now disable pipes here. */
7569 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7570 spin_lock_irq(&dev->event_lock);
7571 drm_crtc_send_vblank_event(&crtc->base,
7572 new_crtc_state->uapi.event);
7573 spin_unlock_irq(&dev->event_lock);
7575 new_crtc_state->uapi.event = NULL;
7579 intel_encoders_update_prepare(state);
7581 intel_dbuf_pre_plane_update(state);
7582 intel_mbus_dbox_update(state);
7584 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7585 if (new_crtc_state->do_async_flip)
7586 intel_crtc_enable_flip_done(state, crtc);
7589 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7590 dev_priv->display->commit_modeset_enables(state);
7592 intel_encoders_update_complete(state);
7595 intel_set_cdclk_post_plane_update(state);
7597 intel_wait_for_vblank_workers(state);
7599 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7600 * already, but still need the state for the delayed optimization. To
7602 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7603 * - schedule that vblank worker _before_ calling hw_done
7604 * - at the start of commit_tail, cancel it _synchrously
7605 * - switch over to the vblank wait helper in the core after that since
7606 * we don't need out special handling any more.
7608 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7610 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7611 if (new_crtc_state->do_async_flip)
7612 intel_crtc_disable_flip_done(state, crtc);
7616 * Now that the vblank has passed, we can go ahead and program the
7617 * optimal watermarks on platforms that need two-step watermark
7620 * TODO: Move this (and other cleanup) to an async worker eventually.
7622 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7623 new_crtc_state, i) {
7625 * Gen2 reports pipe underruns whenever all planes are disabled.
7626 * So re-enable underrun reporting after some planes get enabled.
7628 * We do this before .optimize_watermarks() so that we have a
7629 * chance of catching underruns with the intermediate watermarks
7630 * vs. the new plane configuration.
7632 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7633 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7635 intel_optimize_watermarks(state, crtc);
7638 intel_dbuf_post_plane_update(state);
7639 intel_psr_post_plane_update(state);
7641 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7642 intel_post_plane_update(state, crtc);
7644 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7646 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7649 * DSB cleanup is done in cleanup_work aligning with framebuffer
7650 * cleanup. So copy and reset the dsb structure to sync with
7651 * commit_done and later do dsb cleanup in cleanup_work.
7653 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7656 /* Underruns don't always raise interrupts, so check manually */
7657 intel_check_cpu_fifo_underruns(dev_priv);
7658 intel_check_pch_fifo_underruns(dev_priv);
7661 intel_verify_planes(state);
7663 intel_sagv_post_plane_update(state);
7665 drm_atomic_helper_commit_hw_done(&state->base);
7667 if (state->modeset) {
7668 /* As one of the primary mmio accessors, KMS has a high
7669 * likelihood of triggering bugs in unclaimed access. After we
7670 * finish modesetting, see if an error has been flagged, and if
7671 * so enable debugging for the next modeset - and hope we catch
7674 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7675 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
7677 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7680 * Defer the cleanup of the old state to a separate worker to not
7681 * impede the current task (userspace for blocking modesets) that
7682 * are executed inline. For out-of-line asynchronous modesets/flips,
7683 * deferring to a new worker seems overkill, but we would place a
7684 * schedule point (cond_resched()) here anyway to keep latencies
7687 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7688 queue_work(system_highpri_wq, &state->base.commit_work);
7691 static void intel_atomic_commit_work(struct work_struct *work)
7693 struct intel_atomic_state *state =
7694 container_of(work, struct intel_atomic_state, base.commit_work);
7696 intel_atomic_commit_tail(state);
7700 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7701 enum i915_sw_fence_notify notify)
7703 struct intel_atomic_state *state =
7704 container_of(fence, struct intel_atomic_state, commit_ready);
7707 case FENCE_COMPLETE:
7708 /* we do blocking waits in the worker, nothing to do here */
7712 struct intel_atomic_helper *helper =
7713 &to_i915(state->base.dev)->atomic_helper;
7715 if (llist_add(&state->freed, &helper->free_list))
7716 schedule_work(&helper->free_work);
7724 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7726 struct intel_plane_state *old_plane_state, *new_plane_state;
7727 struct intel_plane *plane;
7730 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7732 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7733 to_intel_frontbuffer(new_plane_state->hw.fb),
7734 plane->frontbuffer_bit);
7737 static int intel_atomic_commit(struct drm_device *dev,
7738 struct drm_atomic_state *_state,
7741 struct intel_atomic_state *state = to_intel_atomic_state(_state);
7742 struct drm_i915_private *dev_priv = to_i915(dev);
7745 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7747 drm_atomic_state_get(&state->base);
7748 i915_sw_fence_init(&state->commit_ready,
7749 intel_atomic_commit_ready);
7752 * The intel_legacy_cursor_update() fast path takes care
7753 * of avoiding the vblank waits for simple cursor
7754 * movement and flips. For cursor on/off and size changes,
7755 * we want to perform the vblank waits so that watermark
7756 * updates happen during the correct frames. Gen9+ have
7757 * double buffered watermarks and so shouldn't need this.
7759 * Unset state->legacy_cursor_update before the call to
7760 * drm_atomic_helper_setup_commit() because otherwise
7761 * drm_atomic_helper_wait_for_flip_done() is a noop and
7762 * we get FIFO underruns because we didn't wait
7765 * FIXME doing watermarks and fb cleanup from a vblank worker
7766 * (assuming we had any) would solve these problems.
7768 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7769 struct intel_crtc_state *new_crtc_state;
7770 struct intel_crtc *crtc;
7773 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7774 if (new_crtc_state->wm.need_postvbl_update ||
7775 new_crtc_state->update_wm_post)
7776 state->base.legacy_cursor_update = false;
7779 ret = intel_atomic_prepare_commit(state);
7781 drm_dbg_atomic(&dev_priv->drm,
7782 "Preparing state failed with %i\n", ret);
7783 i915_sw_fence_commit(&state->commit_ready);
7784 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7788 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7790 ret = drm_atomic_helper_swap_state(&state->base, true);
7792 intel_atomic_swap_global_state(state);
7795 struct intel_crtc_state *new_crtc_state;
7796 struct intel_crtc *crtc;
7799 i915_sw_fence_commit(&state->commit_ready);
7801 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7802 intel_dsb_cleanup(new_crtc_state);
7804 drm_atomic_helper_cleanup_planes(dev, &state->base);
7805 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7808 intel_shared_dpll_swap_state(state);
7809 intel_atomic_track_fbs(state);
7811 drm_atomic_state_get(&state->base);
7812 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7814 i915_sw_fence_commit(&state->commit_ready);
7815 if (nonblock && state->modeset) {
7816 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
7817 } else if (nonblock) {
7818 queue_work(dev_priv->flip_wq, &state->base.commit_work);
7821 flush_workqueue(dev_priv->modeset_wq);
7822 intel_atomic_commit_tail(state);
7829 * intel_plane_destroy - destroy a plane
7830 * @plane: plane to destroy
7832 * Common destruction function for all types of planes (primary, cursor,
7835 void intel_plane_destroy(struct drm_plane *plane)
7837 drm_plane_cleanup(plane);
7838 kfree(to_intel_plane(plane));
7841 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7843 struct intel_plane *plane;
7845 for_each_intel_plane(&dev_priv->drm, plane) {
7846 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7849 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7854 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7855 struct drm_file *file)
7857 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7858 struct drm_crtc *drmmode_crtc;
7859 struct intel_crtc *crtc;
7861 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7865 crtc = to_intel_crtc(drmmode_crtc);
7866 pipe_from_crtc_id->pipe = crtc->pipe;
7871 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7873 struct drm_device *dev = encoder->base.dev;
7874 struct intel_encoder *source_encoder;
7875 u32 possible_clones = 0;
7877 for_each_intel_encoder(dev, source_encoder) {
7878 if (encoders_cloneable(encoder, source_encoder))
7879 possible_clones |= drm_encoder_mask(&source_encoder->base);
7882 return possible_clones;
7885 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7887 struct drm_device *dev = encoder->base.dev;
7888 struct intel_crtc *crtc;
7889 u32 possible_crtcs = 0;
7891 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7892 possible_crtcs |= drm_crtc_mask(&crtc->base);
7894 return possible_crtcs;
7897 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7899 if (!IS_MOBILE(dev_priv))
7902 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7905 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7911 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7913 if (DISPLAY_VER(dev_priv) >= 9)
7916 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7919 if (HAS_PCH_LPT_H(dev_priv) &&
7920 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7923 /* DDI E can't be used if DDI A requires 4 lanes */
7924 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7927 if (!dev_priv->vbt.int_crt_support)
7933 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7935 struct intel_encoder *encoder;
7936 bool dpd_is_edp = false;
7938 intel_pps_unlock_regs_wa(dev_priv);
7940 if (!HAS_DISPLAY(dev_priv))
7943 if (IS_DG2(dev_priv)) {
7944 intel_ddi_init(dev_priv, PORT_A);
7945 intel_ddi_init(dev_priv, PORT_B);
7946 intel_ddi_init(dev_priv, PORT_C);
7947 intel_ddi_init(dev_priv, PORT_D_XELPD);
7948 intel_ddi_init(dev_priv, PORT_TC1);
7949 } else if (IS_ALDERLAKE_P(dev_priv)) {
7950 intel_ddi_init(dev_priv, PORT_A);
7951 intel_ddi_init(dev_priv, PORT_B);
7952 intel_ddi_init(dev_priv, PORT_TC1);
7953 intel_ddi_init(dev_priv, PORT_TC2);
7954 intel_ddi_init(dev_priv, PORT_TC3);
7955 intel_ddi_init(dev_priv, PORT_TC4);
7956 icl_dsi_init(dev_priv);
7957 } else if (IS_ALDERLAKE_S(dev_priv)) {
7958 intel_ddi_init(dev_priv, PORT_A);
7959 intel_ddi_init(dev_priv, PORT_TC1);
7960 intel_ddi_init(dev_priv, PORT_TC2);
7961 intel_ddi_init(dev_priv, PORT_TC3);
7962 intel_ddi_init(dev_priv, PORT_TC4);
7963 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7964 intel_ddi_init(dev_priv, PORT_A);
7965 intel_ddi_init(dev_priv, PORT_B);
7966 intel_ddi_init(dev_priv, PORT_TC1);
7967 intel_ddi_init(dev_priv, PORT_TC2);
7968 } else if (DISPLAY_VER(dev_priv) >= 12) {
7969 intel_ddi_init(dev_priv, PORT_A);
7970 intel_ddi_init(dev_priv, PORT_B);
7971 intel_ddi_init(dev_priv, PORT_TC1);
7972 intel_ddi_init(dev_priv, PORT_TC2);
7973 intel_ddi_init(dev_priv, PORT_TC3);
7974 intel_ddi_init(dev_priv, PORT_TC4);
7975 intel_ddi_init(dev_priv, PORT_TC5);
7976 intel_ddi_init(dev_priv, PORT_TC6);
7977 icl_dsi_init(dev_priv);
7978 } else if (IS_JSL_EHL(dev_priv)) {
7979 intel_ddi_init(dev_priv, PORT_A);
7980 intel_ddi_init(dev_priv, PORT_B);
7981 intel_ddi_init(dev_priv, PORT_C);
7982 intel_ddi_init(dev_priv, PORT_D);
7983 icl_dsi_init(dev_priv);
7984 } else if (DISPLAY_VER(dev_priv) == 11) {
7985 intel_ddi_init(dev_priv, PORT_A);
7986 intel_ddi_init(dev_priv, PORT_B);
7987 intel_ddi_init(dev_priv, PORT_C);
7988 intel_ddi_init(dev_priv, PORT_D);
7989 intel_ddi_init(dev_priv, PORT_E);
7990 intel_ddi_init(dev_priv, PORT_F);
7991 icl_dsi_init(dev_priv);
7992 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7993 intel_ddi_init(dev_priv, PORT_A);
7994 intel_ddi_init(dev_priv, PORT_B);
7995 intel_ddi_init(dev_priv, PORT_C);
7996 vlv_dsi_init(dev_priv);
7997 } else if (DISPLAY_VER(dev_priv) >= 9) {
7998 intel_ddi_init(dev_priv, PORT_A);
7999 intel_ddi_init(dev_priv, PORT_B);
8000 intel_ddi_init(dev_priv, PORT_C);
8001 intel_ddi_init(dev_priv, PORT_D);
8002 intel_ddi_init(dev_priv, PORT_E);
8003 } else if (HAS_DDI(dev_priv)) {
8006 if (intel_ddi_crt_present(dev_priv))
8007 intel_crt_init(dev_priv);
8009 /* Haswell uses DDI functions to detect digital outputs. */
8010 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
8012 intel_ddi_init(dev_priv, PORT_A);
8014 found = intel_de_read(dev_priv, SFUSE_STRAP);
8015 if (found & SFUSE_STRAP_DDIB_DETECTED)
8016 intel_ddi_init(dev_priv, PORT_B);
8017 if (found & SFUSE_STRAP_DDIC_DETECTED)
8018 intel_ddi_init(dev_priv, PORT_C);
8019 if (found & SFUSE_STRAP_DDID_DETECTED)
8020 intel_ddi_init(dev_priv, PORT_D);
8021 if (found & SFUSE_STRAP_DDIF_DETECTED)
8022 intel_ddi_init(dev_priv, PORT_F);
8023 } else if (HAS_PCH_SPLIT(dev_priv)) {
8027 * intel_edp_init_connector() depends on this completing first,
8028 * to prevent the registration of both eDP and LVDS and the
8029 * incorrect sharing of the PPS.
8031 intel_lvds_init(dev_priv);
8032 intel_crt_init(dev_priv);
8034 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8036 if (ilk_has_edp_a(dev_priv))
8037 g4x_dp_init(dev_priv, DP_A, PORT_A);
8039 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
8040 /* PCH SDVOB multiplex with HDMIB */
8041 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
8043 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
8044 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
8045 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
8048 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
8049 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
8051 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
8052 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
8054 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
8055 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
8057 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
8058 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
8059 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8060 bool has_edp, has_port;
8062 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
8063 intel_crt_init(dev_priv);
8066 * The DP_DETECTED bit is the latched state of the DDC
8067 * SDA pin at boot. However since eDP doesn't require DDC
8068 * (no way to plug in a DP->HDMI dongle) the DDC pins for
8069 * eDP ports may have been muxed to an alternate function.
8070 * Thus we can't rely on the DP_DETECTED bit alone to detect
8071 * eDP ports. Consult the VBT as well as DP_DETECTED to
8074 * Sadly the straps seem to be missing sometimes even for HDMI
8075 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
8076 * and VBT for the presence of the port. Additionally we can't
8077 * trust the port type the VBT declares as we've seen at least
8078 * HDMI ports that the VBT claim are DP or eDP.
8080 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8081 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
8082 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8083 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8084 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8085 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8087 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8088 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
8089 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8090 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
8091 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
8092 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
8094 if (IS_CHERRYVIEW(dev_priv)) {
8096 * eDP not supported on port D,
8097 * so no need to worry about it
8099 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
8100 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
8101 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
8102 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
8103 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
8106 vlv_dsi_init(dev_priv);
8107 } else if (IS_PINEVIEW(dev_priv)) {
8108 intel_lvds_init(dev_priv);
8109 intel_crt_init(dev_priv);
8110 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8113 if (IS_MOBILE(dev_priv))
8114 intel_lvds_init(dev_priv);
8116 intel_crt_init(dev_priv);
8118 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8119 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
8120 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
8121 if (!found && IS_G4X(dev_priv)) {
8122 drm_dbg_kms(&dev_priv->drm,
8123 "probing HDMI on SDVOB\n");
8124 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
8127 if (!found && IS_G4X(dev_priv))
8128 g4x_dp_init(dev_priv, DP_B, PORT_B);
8131 /* Before G4X SDVOC doesn't have its own detect register */
8133 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8134 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
8135 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
8138 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
8140 if (IS_G4X(dev_priv)) {
8141 drm_dbg_kms(&dev_priv->drm,
8142 "probing HDMI on SDVOC\n");
8143 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
8145 if (IS_G4X(dev_priv))
8146 g4x_dp_init(dev_priv, DP_C, PORT_C);
8149 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8150 g4x_dp_init(dev_priv, DP_D, PORT_D);
8152 if (SUPPORTS_TV(dev_priv))
8153 intel_tv_init(dev_priv);
8154 } else if (DISPLAY_VER(dev_priv) == 2) {
8155 if (IS_I85X(dev_priv))
8156 intel_lvds_init(dev_priv);
8158 intel_crt_init(dev_priv);
8159 intel_dvo_init(dev_priv);
8162 for_each_intel_encoder(&dev_priv->drm, encoder) {
8163 encoder->base.possible_crtcs =
8164 intel_encoder_possible_crtcs(encoder);
8165 encoder->base.possible_clones =
8166 intel_encoder_possible_clones(encoder);
8169 intel_init_pch_refclk(dev_priv);
8171 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
8174 static enum drm_mode_status
8175 intel_mode_valid(struct drm_device *dev,
8176 const struct drm_display_mode *mode)
8178 struct drm_i915_private *dev_priv = to_i915(dev);
8179 int hdisplay_max, htotal_max;
8180 int vdisplay_max, vtotal_max;
8183 * Can't reject DBLSCAN here because Xorg ddxen can add piles
8184 * of DBLSCAN modes to the output's mode list when they detect
8185 * the scaling mode property on the connector. And they don't
8186 * ask the kernel to validate those modes in any way until
8187 * modeset time at which point the client gets a protocol error.
8188 * So in order to not upset those clients we silently ignore the
8189 * DBLSCAN flag on such connectors. For other connectors we will
8190 * reject modes with the DBLSCAN flag in encoder->compute_config().
8191 * And we always reject DBLSCAN modes in connector->mode_valid()
8192 * as we never want such modes on the connector's mode list.
8195 if (mode->vscan > 1)
8196 return MODE_NO_VSCAN;
8198 if (mode->flags & DRM_MODE_FLAG_HSKEW)
8199 return MODE_H_ILLEGAL;
8201 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8202 DRM_MODE_FLAG_NCSYNC |
8203 DRM_MODE_FLAG_PCSYNC))
8206 if (mode->flags & (DRM_MODE_FLAG_BCAST |
8207 DRM_MODE_FLAG_PIXMUX |
8208 DRM_MODE_FLAG_CLKDIV2))
8211 /* Transcoder timing limits */
8212 if (DISPLAY_VER(dev_priv) >= 11) {
8213 hdisplay_max = 16384;
8214 vdisplay_max = 8192;
8217 } else if (DISPLAY_VER(dev_priv) >= 9 ||
8218 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8219 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8220 vdisplay_max = 4096;
8223 } else if (DISPLAY_VER(dev_priv) >= 3) {
8224 hdisplay_max = 4096;
8225 vdisplay_max = 4096;
8229 hdisplay_max = 2048;
8230 vdisplay_max = 2048;
8235 if (mode->hdisplay > hdisplay_max ||
8236 mode->hsync_start > htotal_max ||
8237 mode->hsync_end > htotal_max ||
8238 mode->htotal > htotal_max)
8239 return MODE_H_ILLEGAL;
8241 if (mode->vdisplay > vdisplay_max ||
8242 mode->vsync_start > vtotal_max ||
8243 mode->vsync_end > vtotal_max ||
8244 mode->vtotal > vtotal_max)
8245 return MODE_V_ILLEGAL;
8247 if (DISPLAY_VER(dev_priv) >= 5) {
8248 if (mode->hdisplay < 64 ||
8249 mode->htotal - mode->hdisplay < 32)
8250 return MODE_H_ILLEGAL;
8252 if (mode->vtotal - mode->vdisplay < 5)
8253 return MODE_V_ILLEGAL;
8255 if (mode->htotal - mode->hdisplay < 32)
8256 return MODE_H_ILLEGAL;
8258 if (mode->vtotal - mode->vdisplay < 3)
8259 return MODE_V_ILLEGAL;
8263 * Cantiga+ cannot handle modes with a hsync front porch of 0.
8264 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8266 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8267 mode->hsync_start == mode->hdisplay)
8268 return MODE_H_ILLEGAL;
8273 enum drm_mode_status
8274 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8275 const struct drm_display_mode *mode,
8278 int plane_width_max, plane_height_max;
8281 * intel_mode_valid() should be
8282 * sufficient on older platforms.
8284 if (DISPLAY_VER(dev_priv) < 9)
8288 * Most people will probably want a fullscreen
8289 * plane so let's not advertize modes that are
8292 if (DISPLAY_VER(dev_priv) >= 11) {
8293 plane_width_max = 5120 << bigjoiner;
8294 plane_height_max = 4320;
8296 plane_width_max = 5120;
8297 plane_height_max = 4096;
8300 if (mode->hdisplay > plane_width_max)
8301 return MODE_H_ILLEGAL;
8303 if (mode->vdisplay > plane_height_max)
8304 return MODE_V_ILLEGAL;
8309 static const struct drm_mode_config_funcs intel_mode_funcs = {
8310 .fb_create = intel_user_framebuffer_create,
8311 .get_format_info = intel_fb_get_format_info,
8312 .output_poll_changed = intel_fbdev_output_poll_changed,
8313 .mode_valid = intel_mode_valid,
8314 .atomic_check = intel_atomic_check,
8315 .atomic_commit = intel_atomic_commit,
8316 .atomic_state_alloc = intel_atomic_state_alloc,
8317 .atomic_state_clear = intel_atomic_state_clear,
8318 .atomic_state_free = intel_atomic_state_free,
8321 static const struct drm_i915_display_funcs skl_display_funcs = {
8322 .get_pipe_config = hsw_get_pipe_config,
8323 .crtc_enable = hsw_crtc_enable,
8324 .crtc_disable = hsw_crtc_disable,
8325 .commit_modeset_enables = skl_commit_modeset_enables,
8326 .get_initial_plane_config = skl_get_initial_plane_config,
8329 static const struct drm_i915_display_funcs ddi_display_funcs = {
8330 .get_pipe_config = hsw_get_pipe_config,
8331 .crtc_enable = hsw_crtc_enable,
8332 .crtc_disable = hsw_crtc_disable,
8333 .commit_modeset_enables = intel_commit_modeset_enables,
8334 .get_initial_plane_config = i9xx_get_initial_plane_config,
8337 static const struct drm_i915_display_funcs pch_split_display_funcs = {
8338 .get_pipe_config = ilk_get_pipe_config,
8339 .crtc_enable = ilk_crtc_enable,
8340 .crtc_disable = ilk_crtc_disable,
8341 .commit_modeset_enables = intel_commit_modeset_enables,
8342 .get_initial_plane_config = i9xx_get_initial_plane_config,
8345 static const struct drm_i915_display_funcs vlv_display_funcs = {
8346 .get_pipe_config = i9xx_get_pipe_config,
8347 .crtc_enable = valleyview_crtc_enable,
8348 .crtc_disable = i9xx_crtc_disable,
8349 .commit_modeset_enables = intel_commit_modeset_enables,
8350 .get_initial_plane_config = i9xx_get_initial_plane_config,
8353 static const struct drm_i915_display_funcs i9xx_display_funcs = {
8354 .get_pipe_config = i9xx_get_pipe_config,
8355 .crtc_enable = i9xx_crtc_enable,
8356 .crtc_disable = i9xx_crtc_disable,
8357 .commit_modeset_enables = intel_commit_modeset_enables,
8358 .get_initial_plane_config = i9xx_get_initial_plane_config,
8362 * intel_init_display_hooks - initialize the display modesetting hooks
8363 * @dev_priv: device private
8365 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8367 if (!HAS_DISPLAY(dev_priv))
8370 intel_init_cdclk_hooks(dev_priv);
8371 intel_audio_hooks_init(dev_priv);
8373 intel_dpll_init_clock_hook(dev_priv);
8375 if (DISPLAY_VER(dev_priv) >= 9) {
8376 dev_priv->display = &skl_display_funcs;
8377 } else if (HAS_DDI(dev_priv)) {
8378 dev_priv->display = &ddi_display_funcs;
8379 } else if (HAS_PCH_SPLIT(dev_priv)) {
8380 dev_priv->display = &pch_split_display_funcs;
8381 } else if (IS_CHERRYVIEW(dev_priv) ||
8382 IS_VALLEYVIEW(dev_priv)) {
8383 dev_priv->display = &vlv_display_funcs;
8385 dev_priv->display = &i9xx_display_funcs;
8388 intel_fdi_init_hook(dev_priv);
8391 void intel_modeset_init_hw(struct drm_i915_private *i915)
8393 struct intel_cdclk_state *cdclk_state;
8395 if (!HAS_DISPLAY(i915))
8398 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
8400 intel_update_cdclk(i915);
8401 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
8402 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
8405 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
8407 struct drm_plane *plane;
8408 struct intel_crtc *crtc;
8410 for_each_intel_crtc(state->dev, crtc) {
8411 struct intel_crtc_state *crtc_state;
8413 crtc_state = intel_atomic_get_crtc_state(state, crtc);
8414 if (IS_ERR(crtc_state))
8415 return PTR_ERR(crtc_state);
8417 if (crtc_state->hw.active) {
8419 * Preserve the inherited flag to avoid
8420 * taking the full modeset path.
8422 crtc_state->inherited = true;
8426 drm_for_each_plane(plane, state->dev) {
8427 struct drm_plane_state *plane_state;
8429 plane_state = drm_atomic_get_plane_state(state, plane);
8430 if (IS_ERR(plane_state))
8431 return PTR_ERR(plane_state);
8438 * Calculate what we think the watermarks should be for the state we've read
8439 * out of the hardware and then immediately program those watermarks so that
8440 * we ensure the hardware settings match our internal state.
8442 * We can calculate what we think WM's should be by creating a duplicate of the
8443 * current state (which was constructed during hardware readout) and running it
8444 * through the atomic check code to calculate new watermark values in the
8447 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
8449 struct drm_atomic_state *state;
8450 struct intel_atomic_state *intel_state;
8451 struct intel_crtc *crtc;
8452 struct intel_crtc_state *crtc_state;
8453 struct drm_modeset_acquire_ctx ctx;
8457 /* Only supported on platforms that use atomic watermark design */
8458 if (!dev_priv->wm_disp->optimize_watermarks)
8461 state = drm_atomic_state_alloc(&dev_priv->drm);
8462 if (drm_WARN_ON(&dev_priv->drm, !state))
8465 intel_state = to_intel_atomic_state(state);
8467 drm_modeset_acquire_init(&ctx, 0);
8470 state->acquire_ctx = &ctx;
8473 * Hardware readout is the only time we don't want to calculate
8474 * intermediate watermarks (since we don't trust the current
8477 if (!HAS_GMCH(dev_priv))
8478 intel_state->skip_intermediate_wm = true;
8480 ret = sanitize_watermarks_add_affected(state);
8484 ret = intel_atomic_check(&dev_priv->drm, state);
8488 /* Write calculated watermark values back */
8489 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
8490 crtc_state->wm.need_postvbl_update = true;
8491 intel_optimize_watermarks(intel_state, crtc);
8493 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
8497 if (ret == -EDEADLK) {
8498 drm_atomic_state_clear(state);
8499 drm_modeset_backoff(&ctx);
8504 * If we fail here, it means that the hardware appears to be
8505 * programmed in a way that shouldn't be possible, given our
8506 * understanding of watermark requirements. This might mean a
8507 * mistake in the hardware readout code or a mistake in the
8508 * watermark calculations for a given platform. Raise a WARN
8509 * so that this is noticeable.
8511 * If this actually happens, we'll have to just leave the
8512 * BIOS-programmed watermarks untouched and hope for the best.
8514 drm_WARN(&dev_priv->drm, ret,
8515 "Could not determine valid watermarks for inherited state\n");
8517 drm_atomic_state_put(state);
8519 drm_modeset_drop_locks(&ctx);
8520 drm_modeset_acquire_fini(&ctx);
8523 static int intel_initial_commit(struct drm_device *dev)
8525 struct drm_atomic_state *state = NULL;
8526 struct drm_modeset_acquire_ctx ctx;
8527 struct intel_crtc *crtc;
8530 state = drm_atomic_state_alloc(dev);
8534 drm_modeset_acquire_init(&ctx, 0);
8537 state->acquire_ctx = &ctx;
8539 for_each_intel_crtc(dev, crtc) {
8540 struct intel_crtc_state *crtc_state =
8541 intel_atomic_get_crtc_state(state, crtc);
8543 if (IS_ERR(crtc_state)) {
8544 ret = PTR_ERR(crtc_state);
8548 if (crtc_state->hw.active) {
8549 struct intel_encoder *encoder;
8552 * We've not yet detected sink capabilities
8553 * (audio,infoframes,etc.) and thus we don't want to
8554 * force a full state recomputation yet. We want that to
8555 * happen only for the first real commit from userspace.
8556 * So preserve the inherited flag for the time being.
8558 crtc_state->inherited = true;
8560 ret = drm_atomic_add_affected_planes(state, &crtc->base);
8565 * FIXME hack to force a LUT update to avoid the
8566 * plane update forcing the pipe gamma on without
8567 * having a proper LUT loaded. Remove once we
8568 * have readout for pipe gamma enable.
8570 crtc_state->uapi.color_mgmt_changed = true;
8572 for_each_intel_encoder_mask(dev, encoder,
8573 crtc_state->uapi.encoder_mask) {
8574 if (encoder->initial_fastset_check &&
8575 !encoder->initial_fastset_check(encoder, crtc_state)) {
8576 ret = drm_atomic_add_affected_connectors(state,
8585 ret = drm_atomic_commit(state);
8588 if (ret == -EDEADLK) {
8589 drm_atomic_state_clear(state);
8590 drm_modeset_backoff(&ctx);
8594 drm_atomic_state_put(state);
8596 drm_modeset_drop_locks(&ctx);
8597 drm_modeset_acquire_fini(&ctx);
8602 static void intel_mode_config_init(struct drm_i915_private *i915)
8604 struct drm_mode_config *mode_config = &i915->drm.mode_config;
8606 drm_mode_config_init(&i915->drm);
8607 INIT_LIST_HEAD(&i915->global_obj_list);
8609 mode_config->min_width = 0;
8610 mode_config->min_height = 0;
8612 mode_config->preferred_depth = 24;
8613 mode_config->prefer_shadow = 1;
8615 mode_config->funcs = &intel_mode_funcs;
8617 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8620 * Maximum framebuffer dimensions, chosen to match
8621 * the maximum render engine surface size on gen4+.
8623 if (DISPLAY_VER(i915) >= 7) {
8624 mode_config->max_width = 16384;
8625 mode_config->max_height = 16384;
8626 } else if (DISPLAY_VER(i915) >= 4) {
8627 mode_config->max_width = 8192;
8628 mode_config->max_height = 8192;
8629 } else if (DISPLAY_VER(i915) == 3) {
8630 mode_config->max_width = 4096;
8631 mode_config->max_height = 4096;
8633 mode_config->max_width = 2048;
8634 mode_config->max_height = 2048;
8637 if (IS_I845G(i915) || IS_I865G(i915)) {
8638 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8639 mode_config->cursor_height = 1023;
8640 } else if (IS_I830(i915) || IS_I85X(i915) ||
8641 IS_I915G(i915) || IS_I915GM(i915)) {
8642 mode_config->cursor_width = 64;
8643 mode_config->cursor_height = 64;
8645 mode_config->cursor_width = 256;
8646 mode_config->cursor_height = 256;
8650 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8652 intel_atomic_global_obj_cleanup(i915);
8653 drm_mode_config_cleanup(&i915->drm);
8656 /* part #1: call before irq install */
8657 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8661 if (i915_inject_probe_failure(i915))
8664 if (HAS_DISPLAY(i915)) {
8665 ret = drm_vblank_init(&i915->drm,
8666 INTEL_NUM_PIPES(i915));
8671 intel_bios_init(i915);
8673 ret = intel_vga_register(i915);
8677 /* FIXME: completely on the wrong abstraction layer */
8678 intel_power_domains_init_hw(i915, false);
8680 if (!HAS_DISPLAY(i915))
8683 intel_dmc_ucode_init(i915);
8685 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
8686 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8687 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8689 i915->window2_delay = 0; /* No DSB so no window2 delay */
8691 intel_mode_config_init(i915);
8693 ret = intel_cdclk_init(i915);
8695 goto cleanup_vga_client_pw_domain_dmc;
8697 ret = intel_dbuf_init(i915);
8699 goto cleanup_vga_client_pw_domain_dmc;
8701 ret = intel_bw_init(i915);
8703 goto cleanup_vga_client_pw_domain_dmc;
8705 init_llist_head(&i915->atomic_helper.free_list);
8706 INIT_WORK(&i915->atomic_helper.free_work,
8707 intel_atomic_helper_free_state_worker);
8709 intel_init_quirks(i915);
8711 intel_fbc_init(i915);
8715 cleanup_vga_client_pw_domain_dmc:
8716 intel_dmc_ucode_fini(i915);
8717 intel_power_domains_driver_remove(i915);
8718 intel_vga_unregister(i915);
8720 intel_bios_driver_remove(i915);
8725 /* part #2: call after irq install, but before gem init */
8726 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8728 struct drm_device *dev = &i915->drm;
8730 struct intel_crtc *crtc;
8733 if (!HAS_DISPLAY(i915))
8736 intel_init_pm(i915);
8738 intel_panel_sanitize_ssc(i915);
8740 intel_pps_setup(i915);
8742 intel_gmbus_setup(i915);
8744 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8745 INTEL_NUM_PIPES(i915),
8746 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8748 for_each_pipe(i915, pipe) {
8749 ret = intel_crtc_init(i915, pipe);
8751 intel_mode_config_cleanup(i915);
8756 intel_plane_possible_crtcs_init(i915);
8757 intel_shared_dpll_init(i915);
8758 intel_fdi_pll_freq_update(i915);
8760 intel_update_czclk(i915);
8761 intel_modeset_init_hw(i915);
8762 intel_dpll_update_ref_clks(i915);
8764 intel_hdcp_component_init(i915);
8766 if (i915->max_cdclk_freq == 0)
8767 intel_update_max_cdclk(i915);
8770 * If the platform has HTI, we need to find out whether it has reserved
8771 * any display resources before we create our display outputs.
8773 if (INTEL_INFO(i915)->display.has_hti)
8774 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
8776 /* Just disable it once at startup */
8777 intel_vga_disable(i915);
8778 intel_setup_outputs(i915);
8780 drm_modeset_lock_all(dev);
8781 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8782 intel_acpi_assign_connector_fwnodes(i915);
8783 drm_modeset_unlock_all(dev);
8785 for_each_intel_crtc(dev, crtc) {
8786 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8788 intel_crtc_initial_plane_config(crtc);
8792 * Make sure hardware watermarks really match the state we read out.
8793 * Note that we need to do this after reconstructing the BIOS fb's
8794 * since the watermark calculation done here will use pstate->fb.
8796 if (!HAS_GMCH(i915))
8797 sanitize_watermarks(i915);
8802 /* part #3: call after gem init */
8803 int intel_modeset_init(struct drm_i915_private *i915)
8807 if (!HAS_DISPLAY(i915))
8811 * Force all active planes to recompute their states. So that on
8812 * mode_setcrtc after probe, all the intel_plane_state variables
8813 * are already calculated and there is no assert_plane warnings
8816 ret = intel_initial_commit(&i915->drm);
8818 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8820 intel_overlay_setup(i915);
8822 ret = intel_fbdev_init(&i915->drm);
8826 /* Only enable hotplug handling once the fbdev is fully set up. */
8827 intel_hpd_init(i915);
8828 intel_hpd_poll_disable(i915);
8830 intel_init_ipc(i915);
8835 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8837 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8838 /* 640x480@60Hz, ~25175 kHz */
8839 struct dpll clock = {
8849 drm_WARN_ON(&dev_priv->drm,
8850 i9xx_calc_dpll_params(48000, &clock) != 25154);
8852 drm_dbg_kms(&dev_priv->drm,
8853 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8854 pipe_name(pipe), clock.vco, clock.dot);
8856 fp = i9xx_dpll_compute_fp(&clock);
8857 dpll = DPLL_DVO_2X_MODE |
8859 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8860 PLL_P2_DIVIDE_BY_4 |
8861 PLL_REF_INPUT_DREFCLK |
8864 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
8865 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
8866 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
8867 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
8868 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
8869 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
8870 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
8872 intel_de_write(dev_priv, FP0(pipe), fp);
8873 intel_de_write(dev_priv, FP1(pipe), fp);
8876 * Apparently we need to have VGA mode enabled prior to changing
8877 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8878 * dividers, even though the register value does change.
8880 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8881 intel_de_write(dev_priv, DPLL(pipe), dpll);
8883 /* Wait for the clocks to stabilize. */
8884 intel_de_posting_read(dev_priv, DPLL(pipe));
8887 /* The pixel multiplier can only be updated once the
8888 * DPLL is enabled and the clocks are stable.
8890 * So write it again.
8892 intel_de_write(dev_priv, DPLL(pipe), dpll);
8894 /* We do this three times for luck */
8895 for (i = 0; i < 3 ; i++) {
8896 intel_de_write(dev_priv, DPLL(pipe), dpll);
8897 intel_de_posting_read(dev_priv, DPLL(pipe));
8898 udelay(150); /* wait for warmup */
8901 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
8902 intel_de_posting_read(dev_priv, PIPECONF(pipe));
8904 intel_wait_for_pipe_scanline_moving(crtc);
8907 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8909 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8911 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8914 drm_WARN_ON(&dev_priv->drm,
8915 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8916 drm_WARN_ON(&dev_priv->drm,
8917 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8918 drm_WARN_ON(&dev_priv->drm,
8919 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8920 drm_WARN_ON(&dev_priv->drm,
8921 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8922 drm_WARN_ON(&dev_priv->drm,
8923 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8925 intel_de_write(dev_priv, PIPECONF(pipe), 0);
8926 intel_de_posting_read(dev_priv, PIPECONF(pipe));
8928 intel_wait_for_pipe_scanline_stopped(crtc);
8930 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8931 intel_de_posting_read(dev_priv, DPLL(pipe));
8934 void intel_display_resume(struct drm_device *dev)
8936 struct drm_i915_private *i915 = to_i915(dev);
8937 struct drm_atomic_state *state = i915->modeset_restore_state;
8938 struct drm_modeset_acquire_ctx ctx;
8941 if (!HAS_DISPLAY(i915))
8944 i915->modeset_restore_state = NULL;
8946 state->acquire_ctx = &ctx;
8948 drm_modeset_acquire_init(&ctx, 0);
8951 ret = drm_modeset_lock_all_ctx(dev, &ctx);
8952 if (ret != -EDEADLK)
8955 drm_modeset_backoff(&ctx);
8959 ret = __intel_display_resume(i915, state, &ctx);
8961 intel_enable_ipc(i915);
8962 drm_modeset_drop_locks(&ctx);
8963 drm_modeset_acquire_fini(&ctx);
8967 "Restoring old state failed with %i\n", ret);
8969 drm_atomic_state_put(state);
8972 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8974 struct intel_connector *connector;
8975 struct drm_connector_list_iter conn_iter;
8977 /* Kill all the work that may have been queued by hpd. */
8978 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8979 for_each_intel_connector_iter(connector, &conn_iter) {
8980 if (connector->modeset_retry_work.func)
8981 cancel_work_sync(&connector->modeset_retry_work);
8982 if (connector->hdcp.shim) {
8983 cancel_delayed_work_sync(&connector->hdcp.check_work);
8984 cancel_work_sync(&connector->hdcp.prop_work);
8987 drm_connector_list_iter_end(&conn_iter);
8990 /* part #1: call before irq uninstall */
8991 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8993 if (!HAS_DISPLAY(i915))
8996 flush_workqueue(i915->flip_wq);
8997 flush_workqueue(i915->modeset_wq);
8999 flush_work(&i915->atomic_helper.free_work);
9000 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
9003 /* part #2: call after irq uninstall */
9004 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
9006 if (!HAS_DISPLAY(i915))
9010 * Due to the hpd irq storm handling the hotplug work can re-arm the
9011 * poll handlers. Hence disable polling after hpd handling is shut down.
9013 intel_hpd_poll_fini(i915);
9016 * MST topology needs to be suspended so we don't have any calls to
9017 * fbdev after it's finalized. MST will be destroyed later as part of
9018 * drm_mode_config_cleanup()
9020 intel_dp_mst_suspend(i915);
9022 /* poll work can call into fbdev, hence clean that up afterwards */
9023 intel_fbdev_fini(i915);
9025 intel_unregister_dsm_handler();
9027 /* flush any delayed tasks or pending work */
9028 flush_scheduled_work();
9030 intel_hdcp_component_fini(i915);
9032 intel_mode_config_cleanup(i915);
9034 intel_overlay_cleanup(i915);
9036 intel_gmbus_teardown(i915);
9038 destroy_workqueue(i915->flip_wq);
9039 destroy_workqueue(i915->modeset_wq);
9041 intel_fbc_cleanup(i915);
9044 /* part #3: call after gem init */
9045 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
9047 intel_dmc_ucode_fini(i915);
9049 intel_power_domains_driver_remove(i915);
9051 intel_vga_unregister(i915);
9053 intel_bios_driver_remove(i915);
9056 bool intel_modeset_probe_defer(struct pci_dev *pdev)
9058 struct drm_privacy_screen *privacy_screen;
9061 * apple-gmux is needed on dual GPU MacBook Pro
9062 * to probe the panel if we're the inactive GPU.
9064 if (vga_switcheroo_client_probe_defer(pdev))
9067 /* If the LCD panel has a privacy-screen, wait for it */
9068 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
9069 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
9072 drm_privacy_screen_put(privacy_screen);
9077 void intel_display_driver_register(struct drm_i915_private *i915)
9079 if (!HAS_DISPLAY(i915))
9082 intel_display_debugfs_register(i915);
9084 /* Must be done after probing outputs */
9085 intel_opregion_register(i915);
9086 acpi_video_register();
9088 intel_audio_init(i915);
9091 * Some ports require correctly set-up hpd registers for
9092 * detection to work properly (leading to ghost connected
9093 * connector status), e.g. VGA on gm45. Hence we can only set
9094 * up the initial fbdev config after hpd irqs are fully
9095 * enabled. We do it last so that the async config cannot run
9096 * before the connectors are registered.
9098 intel_fbdev_initial_config_async(&i915->drm);
9101 * We need to coordinate the hotplugs with the asynchronous
9102 * fbdev configuration, for which we use the
9103 * fbdev->async_cookie.
9105 drm_kms_helper_poll_init(&i915->drm);
9108 void intel_display_driver_unregister(struct drm_i915_private *i915)
9110 if (!HAS_DISPLAY(i915))
9113 intel_fbdev_unregister(i915);
9114 intel_audio_deinit(i915);
9117 * After flushing the fbdev (incl. a late async config which
9118 * will have delayed queuing of a hotplug event), then flush
9119 * the hotplug events.
9121 drm_kms_helper_poll_fini(&i915->drm);
9122 drm_atomic_helper_shutdown(&i915->drm);
9124 acpi_video_unregister();
9125 intel_opregion_unregister(i915);
9128 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
9130 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);