2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812 u32 mode_flags = crtc->mode_flags;
1815 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
1816 * have updated at the beginning of TE, if we want to use
1817 * the hw counter, then we would find it updated in only
1818 * the next TE, hence switching to sw counter.
1820 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
1824 * On i965gm the hardware frame counter reads
1825 * zero when the TV encoder is enabled :(
1827 if (IS_I965GM(dev_priv) &&
1828 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1831 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1832 return 0xffffffff; /* full 32 bit counter */
1833 else if (INTEL_GEN(dev_priv) >= 3)
1834 return 0xffffff; /* only 24 bits of frame count */
1836 return 0; /* Gen2 doesn't have a hardware frame counter */
1839 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1843 assert_vblank_disabled(&crtc->base);
1844 drm_crtc_set_max_vblank_count(&crtc->base,
1845 intel_crtc_max_vblank_count(crtc_state));
1846 drm_crtc_vblank_on(&crtc->base);
1849 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1853 drm_crtc_vblank_off(&crtc->base);
1854 assert_vblank_disabled(&crtc->base);
1857 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1862 enum pipe pipe = crtc->pipe;
1866 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1868 assert_planes_disabled(crtc);
1871 * A pipe without a PLL won't actually be able to drive bits from
1872 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1875 if (HAS_GMCH(dev_priv)) {
1876 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1877 assert_dsi_pll_enabled(dev_priv);
1879 assert_pll_enabled(dev_priv, pipe);
1881 if (new_crtc_state->has_pch_encoder) {
1882 /* if driving the PCH, we need FDI enabled */
1883 assert_fdi_rx_pll_enabled(dev_priv,
1884 intel_crtc_pch_transcoder(crtc));
1885 assert_fdi_tx_pll_enabled(dev_priv,
1886 (enum pipe) cpu_transcoder);
1888 /* FIXME: assert CPU port conditions for SNB+ */
1891 trace_intel_pipe_enable(crtc);
1893 reg = PIPECONF(cpu_transcoder);
1894 val = intel_de_read(dev_priv, reg);
1895 if (val & PIPECONF_ENABLE) {
1896 /* we keep both pipes enabled on 830 */
1897 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1901 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1902 intel_de_posting_read(dev_priv, reg);
1905 * Until the pipe starts PIPEDSL reads will return a stale value,
1906 * which causes an apparent vblank timestamp jump when PIPEDSL
1907 * resets to its proper value. That also messes up the frame count
1908 * when it's derived from the timestamps. So let's wait for the
1909 * pipe to start properly before we call drm_crtc_vblank_on()
1911 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1912 intel_wait_for_pipe_scanline_moving(crtc);
1915 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1919 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1920 enum pipe pipe = crtc->pipe;
1924 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1927 * Make sure planes won't keep trying to pump pixels to us,
1928 * or we might hang the display.
1930 assert_planes_disabled(crtc);
1932 trace_intel_pipe_disable(crtc);
1934 reg = PIPECONF(cpu_transcoder);
1935 val = intel_de_read(dev_priv, reg);
1936 if ((val & PIPECONF_ENABLE) == 0)
1940 * Double wide has implications for planes
1941 * so best keep it disabled when not needed.
1943 if (old_crtc_state->double_wide)
1944 val &= ~PIPECONF_DOUBLE_WIDE;
1946 /* Don't disable pipe or pipe PLLs if needed */
1947 if (!IS_I830(dev_priv))
1948 val &= ~PIPECONF_ENABLE;
1950 intel_de_write(dev_priv, reg, val);
1951 if ((val & PIPECONF_ENABLE) == 0)
1952 intel_wait_for_pipe_off(old_crtc_state);
1955 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1960 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 if (!is_ccs_modifier(fb->modifier))
1965 return plane >= fb->format->num_planes / 2;
1968 static bool is_gen12_ccs_modifier(u64 modifier)
1970 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1971 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1975 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1977 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1980 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1982 if (is_ccs_modifier(fb->modifier))
1983 return is_ccs_plane(fb, plane);
1988 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1990 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1991 (main_plane && main_plane >= fb->format->num_planes / 2));
1993 return fb->format->num_planes / 2 + main_plane;
1996 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1998 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1999 ccs_plane < fb->format->num_planes / 2);
2001 return ccs_plane - fb->format->num_planes / 2;
2004 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
2006 struct drm_i915_private *i915 = to_i915(fb->dev);
2008 if (is_ccs_modifier(fb->modifier))
2009 return main_to_ccs_plane(fb, main_plane);
2010 else if (INTEL_GEN(i915) < 11 &&
2011 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
2018 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2021 return info->is_yuv &&
2022 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2025 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2028 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2033 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2035 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 unsigned int cpp = fb->format->cpp[color_plane];
2038 switch (fb->modifier) {
2039 case DRM_FORMAT_MOD_LINEAR:
2040 return intel_tile_size(dev_priv);
2041 case I915_FORMAT_MOD_X_TILED:
2042 if (IS_GEN(dev_priv, 2))
2046 case I915_FORMAT_MOD_Y_TILED_CCS:
2047 if (is_ccs_plane(fb, color_plane))
2050 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2051 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2052 if (is_ccs_plane(fb, color_plane))
2055 case I915_FORMAT_MOD_Y_TILED:
2056 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 if (is_ccs_plane(fb, color_plane))
2064 case I915_FORMAT_MOD_Yf_TILED:
2080 MISSING_CASE(fb->modifier);
2086 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2088 if (is_gen12_ccs_plane(fb, color_plane))
2091 return intel_tile_size(to_i915(fb->dev)) /
2092 intel_tile_width_bytes(fb, color_plane);
2095 /* Return the tile dimensions in pixel units */
2096 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2097 unsigned int *tile_width,
2098 unsigned int *tile_height)
2100 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2101 unsigned int cpp = fb->format->cpp[color_plane];
2103 *tile_width = tile_width_bytes / cpp;
2104 *tile_height = intel_tile_height(fb, color_plane);
2107 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2110 unsigned int tile_width, tile_height;
2112 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2114 return fb->pitches[color_plane] * tile_height;
2118 intel_fb_align_height(const struct drm_framebuffer *fb,
2119 int color_plane, unsigned int height)
2121 unsigned int tile_height = intel_tile_height(fb, color_plane);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2137 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2139 unsigned int size = 0;
2142 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2143 size += rem_info->plane[i].width * rem_info->plane[i].height;
2149 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2150 const struct drm_framebuffer *fb,
2151 unsigned int rotation)
2153 view->type = I915_GGTT_VIEW_NORMAL;
2154 if (drm_rotation_90_or_270(rotation)) {
2155 view->type = I915_GGTT_VIEW_ROTATED;
2156 view->rotated = to_intel_framebuffer(fb)->rot_info;
2160 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2162 if (IS_I830(dev_priv))
2164 else if (IS_I85X(dev_priv))
2166 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2172 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2174 if (INTEL_GEN(dev_priv) >= 9)
2176 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2177 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2179 else if (INTEL_GEN(dev_priv) >= 4)
2185 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2188 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2190 /* AUX_DIST needs only 4K alignment */
2191 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2192 is_ccs_plane(fb, color_plane))
2195 switch (fb->modifier) {
2196 case DRM_FORMAT_MOD_LINEAR:
2197 return intel_linear_alignment(dev_priv);
2198 case I915_FORMAT_MOD_X_TILED:
2199 if (INTEL_GEN(dev_priv) >= 9)
2202 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2203 if (is_semiplanar_uv_plane(fb, color_plane))
2204 return intel_tile_row_size(fb, color_plane);
2206 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2208 case I915_FORMAT_MOD_Y_TILED_CCS:
2209 case I915_FORMAT_MOD_Yf_TILED_CCS:
2210 case I915_FORMAT_MOD_Y_TILED:
2211 if (INTEL_GEN(dev_priv) >= 12 &&
2212 is_semiplanar_uv_plane(fb, color_plane))
2213 return intel_tile_row_size(fb, color_plane);
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2218 MISSING_CASE(fb->modifier);
2223 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2226 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2228 return INTEL_GEN(dev_priv) < 4 ||
2230 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2234 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2235 const struct i915_ggtt_view *view,
2237 unsigned long *out_flags)
2239 struct drm_device *dev = fb->dev;
2240 struct drm_i915_private *dev_priv = to_i915(dev);
2241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2242 intel_wakeref_t wakeref;
2243 struct i915_vma *vma;
2244 unsigned int pinctl;
2247 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2248 return ERR_PTR(-EINVAL);
2250 alignment = intel_surf_alignment(fb, 0);
2251 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2252 return ERR_PTR(-EINVAL);
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2259 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2269 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2271 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2274 * Valleyview is definitely limited to scanning out the first
2275 * 512MiB. Lets presume this behaviour was inherited from the
2276 * g4x display engine and that all earlier gen are similarly
2277 * limited. Testing suggests that it is a little more
2278 * complicated than this. For example, Cherryview appears quite
2279 * happy to scanout from anywhere within its global aperture.
2282 if (HAS_GMCH(dev_priv))
2283 pinctl |= PIN_MAPPABLE;
2285 vma = i915_gem_object_pin_to_display_plane(obj,
2286 alignment, view, pinctl);
2290 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2294 * Install a fence for tiled scan-out. Pre-i965 always needs a
2295 * fence, whereas 965+ only requires a fence if using
2296 * framebuffer compression. For simplicity, we always, when
2297 * possible, install a fence as the cost is not that onerous.
2299 * If we fail to fence the tiled scanout, then either the
2300 * modeset will reject the change (which is highly unlikely as
2301 * the affected systems, all but one, do not have unmappable
2302 * space) or we will not be able to enable full powersaving
2303 * techniques (also likely not to apply due to various limits
2304 * FBC and the like impose on the size of the buffer, which
2305 * presumably we violated anyway with this unmappable buffer).
2306 * Anyway, it is presumably better to stumble onwards with
2307 * something and try to run the system in a "less than optimal"
2308 * mode that matches the user configuration.
2310 ret = i915_vma_pin_fence(vma);
2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2312 i915_gem_object_unpin_from_display_plane(vma);
2317 if (ret == 0 && vma->fence)
2318 *out_flags |= PLANE_HAS_FENCE;
2323 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2324 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2330 i915_gem_object_lock(vma->obj, NULL);
2331 if (flags & PLANE_HAS_FENCE)
2332 i915_vma_unpin_fence(vma);
2333 i915_gem_object_unpin_from_display_plane(vma);
2334 i915_gem_object_unlock(vma->obj);
2339 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2340 unsigned int rotation)
2342 if (drm_rotation_90_or_270(rotation))
2343 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2345 return fb->pitches[color_plane];
2349 * Convert the x/y offsets into a linear offset.
2350 * Only valid with 0/180 degree rotation, which is fine since linear
2351 * offset is only used with linear buffers on pre-hsw and tiled buffers
2352 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2354 u32 intel_fb_xy_to_linear(int x, int y,
2355 const struct intel_plane_state *state,
2358 const struct drm_framebuffer *fb = state->hw.fb;
2359 unsigned int cpp = fb->format->cpp[color_plane];
2360 unsigned int pitch = state->color_plane[color_plane].stride;
2362 return y * pitch + x * cpp;
2366 * Add the x/y offsets derived from fb->offsets[] to the user
2367 * specified plane src x/y offsets. The resulting x/y offsets
2368 * specify the start of scanout from the beginning of the gtt mapping.
2370 void intel_add_fb_offsets(int *x, int *y,
2371 const struct intel_plane_state *state,
2375 *x += state->color_plane[color_plane].x;
2376 *y += state->color_plane[color_plane].y;
2379 static u32 intel_adjust_tile_offset(int *x, int *y,
2380 unsigned int tile_width,
2381 unsigned int tile_height,
2382 unsigned int tile_size,
2383 unsigned int pitch_tiles,
2387 unsigned int pitch_pixels = pitch_tiles * tile_width;
2390 WARN_ON(old_offset & (tile_size - 1));
2391 WARN_ON(new_offset & (tile_size - 1));
2392 WARN_ON(new_offset > old_offset);
2394 tiles = (old_offset - new_offset) / tile_size;
2396 *y += tiles / pitch_tiles * tile_height;
2397 *x += tiles % pitch_tiles * tile_width;
2399 /* minimize x in case it got needlessly big */
2400 *y += *x / pitch_pixels * tile_height;
2406 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2408 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2409 is_gen12_ccs_plane(fb, color_plane);
2412 static u32 intel_adjust_aligned_offset(int *x, int *y,
2413 const struct drm_framebuffer *fb,
2415 unsigned int rotation,
2417 u32 old_offset, u32 new_offset)
2419 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2420 unsigned int cpp = fb->format->cpp[color_plane];
2422 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2424 if (!is_surface_linear(fb, color_plane)) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int pitch_tiles;
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2431 if (drm_rotation_90_or_270(rotation)) {
2432 pitch_tiles = pitch / tile_height;
2433 swap(tile_width, tile_height);
2435 pitch_tiles = pitch / (tile_width * cpp);
2438 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 old_offset, new_offset);
2442 old_offset += *y * pitch + *x * cpp;
2444 *y = (old_offset - new_offset) / pitch;
2445 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2452 * Adjust the tile offset by moving the difference into
2455 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2456 const struct intel_plane_state *state,
2458 u32 old_offset, u32 new_offset)
2460 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2462 state->color_plane[color_plane].stride,
2463 old_offset, new_offset);
2467 * Computes the aligned offset to the base tile and adjusts
2468 * x, y. bytes per pixel is assumed to be a power-of-two.
2470 * In the 90/270 rotated case, x and y are assumed
2471 * to be already rotated to match the rotated GTT view, and
2472 * pitch is the tile_height aligned framebuffer height.
2474 * This function is used when computing the derived information
2475 * under intel_framebuffer, so using any of that information
2476 * here is not allowed. Anything under drm_framebuffer can be
2477 * used. This is why the user has to pass in the pitch since it
2478 * is specified in the rotated orientation.
2480 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2482 const struct drm_framebuffer *fb,
2485 unsigned int rotation,
2488 unsigned int cpp = fb->format->cpp[color_plane];
2489 u32 offset, offset_aligned;
2491 if (!is_surface_linear(fb, color_plane)) {
2492 unsigned int tile_size, tile_width, tile_height;
2493 unsigned int tile_rows, tiles, pitch_tiles;
2495 tile_size = intel_tile_size(dev_priv);
2496 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2498 if (drm_rotation_90_or_270(rotation)) {
2499 pitch_tiles = pitch / tile_height;
2500 swap(tile_width, tile_height);
2502 pitch_tiles = pitch / (tile_width * cpp);
2505 tile_rows = *y / tile_height;
2508 tiles = *x / tile_width;
2511 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2513 offset_aligned = offset;
2515 offset_aligned = rounddown(offset_aligned, alignment);
2517 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2518 tile_size, pitch_tiles,
2519 offset, offset_aligned);
2521 offset = *y * pitch + *x * cpp;
2522 offset_aligned = offset;
2524 offset_aligned = rounddown(offset_aligned, alignment);
2525 *y = (offset % alignment) / pitch;
2526 *x = ((offset % alignment) - *y * pitch) / cpp;
2532 return offset_aligned;
2535 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2536 const struct intel_plane_state *state,
2539 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2540 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2541 const struct drm_framebuffer *fb = state->hw.fb;
2542 unsigned int rotation = state->hw.rotation;
2543 int pitch = state->color_plane[color_plane].stride;
2546 if (intel_plane->id == PLANE_CURSOR)
2547 alignment = intel_cursor_alignment(dev_priv);
2549 alignment = intel_surf_alignment(fb, color_plane);
2551 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2552 pitch, rotation, alignment);
2555 /* Convert the fb->offset[] into x/y offsets */
2556 static int intel_fb_offset_to_xy(int *x, int *y,
2557 const struct drm_framebuffer *fb,
2560 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561 unsigned int height;
2564 if (INTEL_GEN(dev_priv) >= 12 &&
2565 is_semiplanar_uv_plane(fb, color_plane))
2566 alignment = intel_tile_row_size(fb, color_plane);
2567 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2568 alignment = intel_tile_size(dev_priv);
2572 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2573 drm_dbg_kms(&dev_priv->drm,
2574 "Misaligned offset 0x%08x for color plane %d\n",
2575 fb->offsets[color_plane], color_plane);
2579 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2580 height = ALIGN(height, intel_tile_height(fb, color_plane));
2582 /* Catch potential overflows early */
2583 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2584 fb->offsets[color_plane])) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2587 fb->offsets[color_plane], fb->pitches[color_plane],
2595 intel_adjust_aligned_offset(x, y,
2596 fb, color_plane, DRM_MODE_ROTATE_0,
2597 fb->pitches[color_plane],
2598 fb->offsets[color_plane], 0);
2603 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2605 switch (fb_modifier) {
2606 case I915_FORMAT_MOD_X_TILED:
2607 return I915_TILING_X;
2608 case I915_FORMAT_MOD_Y_TILED:
2609 case I915_FORMAT_MOD_Y_TILED_CCS:
2610 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2611 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2612 return I915_TILING_Y;
2614 return I915_TILING_NONE;
2619 * From the Sky Lake PRM:
2620 * "The Color Control Surface (CCS) contains the compression status of
2621 * the cache-line pairs. The compression state of the cache-line pair
2622 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2623 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2624 * cache-line-pairs. CCS is always Y tiled."
2626 * Since cache line pairs refers to horizontally adjacent cache lines,
2627 * each cache line in the CCS corresponds to an area of 32x16 cache
2628 * lines on the main surface. Since each pixel is 4 bytes, this gives
2629 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2632 static const struct drm_format_info skl_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2635 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2636 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2637 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2638 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2639 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2640 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2644 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2645 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2646 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2647 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2650 static const struct drm_format_info gen12_ccs_formats[] = {
2651 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2652 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 1, .vsub = 1, },
2654 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2655 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 1, .vsub = 1, },
2657 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2658 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 1, .vsub = 1, .has_alpha = true },
2660 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2661 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2662 .hsub = 1, .vsub = 1, .has_alpha = true },
2663 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2664 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2665 .hsub = 2, .vsub = 1, .is_yuv = true },
2666 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2667 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2668 .hsub = 2, .vsub = 1, .is_yuv = true },
2669 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2670 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2671 .hsub = 2, .vsub = 1, .is_yuv = true },
2672 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2673 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2674 .hsub = 2, .vsub = 1, .is_yuv = true },
2675 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2676 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2677 .hsub = 2, .vsub = 2, .is_yuv = true },
2678 { .format = DRM_FORMAT_P010, .num_planes = 4,
2679 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2680 .hsub = 2, .vsub = 2, .is_yuv = true },
2681 { .format = DRM_FORMAT_P012, .num_planes = 4,
2682 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2683 .hsub = 2, .vsub = 2, .is_yuv = true },
2684 { .format = DRM_FORMAT_P016, .num_planes = 4,
2685 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2686 .hsub = 2, .vsub = 2, .is_yuv = true },
2689 static const struct drm_format_info *
2690 lookup_format_info(const struct drm_format_info formats[],
2691 int num_formats, u32 format)
2695 for (i = 0; i < num_formats; i++) {
2696 if (formats[i].format == format)
2703 static const struct drm_format_info *
2704 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2706 switch (cmd->modifier[0]) {
2707 case I915_FORMAT_MOD_Y_TILED_CCS:
2708 case I915_FORMAT_MOD_Yf_TILED_CCS:
2709 return lookup_format_info(skl_ccs_formats,
2710 ARRAY_SIZE(skl_ccs_formats),
2712 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2713 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2714 return lookup_format_info(gen12_ccs_formats,
2715 ARRAY_SIZE(gen12_ccs_formats),
2722 bool is_ccs_modifier(u64 modifier)
2724 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2725 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2726 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2727 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2730 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2732 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2736 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2737 u32 pixel_format, u64 modifier)
2739 struct intel_crtc *crtc;
2740 struct intel_plane *plane;
2743 * We assume the primary plane for pipe A has
2744 * the highest stride limits of them all,
2745 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2747 crtc = intel_get_first_crtc(dev_priv);
2751 plane = to_intel_plane(crtc->base.primary);
2753 return plane->max_stride(plane, pixel_format, modifier,
2758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2759 u32 pixel_format, u64 modifier)
2762 * Arbitrary limit for gen4+ chosen to match the
2763 * render engine max stride.
2765 * The new CCS hash mode makes remapping impossible
2767 if (!is_ccs_modifier(modifier)) {
2768 if (INTEL_GEN(dev_priv) >= 7)
2770 else if (INTEL_GEN(dev_priv) >= 4)
2774 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2778 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2780 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2783 if (is_surface_linear(fb, color_plane)) {
2784 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2789 * To make remapping with linear generally feasible
2790 * we need the stride to be page aligned.
2792 if (fb->pitches[color_plane] > max_stride &&
2793 !is_ccs_modifier(fb->modifier))
2794 return intel_tile_size(dev_priv);
2799 tile_width = intel_tile_width_bytes(fb, color_plane);
2800 if (is_ccs_modifier(fb->modifier)) {
2802 * Display WA #0531: skl,bxt,kbl,glk
2804 * Render decompression and plane width > 3840
2805 * combined with horizontal panning requires the
2806 * plane stride to be a multiple of 4. We'll just
2807 * require the entire fb to accommodate that to avoid
2808 * potential runtime errors at plane configuration time.
2810 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2813 * The main surface pitch must be padded to a multiple of four
2816 else if (INTEL_GEN(dev_priv) >= 12)
2822 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2824 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2825 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2826 const struct drm_framebuffer *fb = plane_state->hw.fb;
2829 /* We don't want to deal with remapping with cursors */
2830 if (plane->id == PLANE_CURSOR)
2834 * The display engine limits already match/exceed the
2835 * render engine limits, so not much point in remapping.
2836 * Would also need to deal with the fence POT alignment
2837 * and gen2 2KiB GTT tile size.
2839 if (INTEL_GEN(dev_priv) < 4)
2843 * The new CCS hash mode isn't compatible with remapping as
2844 * the virtual address of the pages affects the compressed data.
2846 if (is_ccs_modifier(fb->modifier))
2849 /* Linear needs a page aligned stride for remapping */
2850 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2851 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2853 for (i = 0; i < fb->format->num_planes; i++) {
2854 if (fb->pitches[i] & alignment)
2862 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2864 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2865 const struct drm_framebuffer *fb = plane_state->hw.fb;
2866 unsigned int rotation = plane_state->hw.rotation;
2867 u32 stride, max_stride;
2870 * No remapping for invisible planes since we don't have
2871 * an actual source viewport to remap.
2873 if (!plane_state->uapi.visible)
2876 if (!intel_plane_can_remap(plane_state))
2880 * FIXME: aux plane limits on gen9+ are
2881 * unclear in Bspec, for now no checking.
2883 stride = intel_fb_pitch(fb, 0, rotation);
2884 max_stride = plane->max_stride(plane, fb->format->format,
2885 fb->modifier, rotation);
2887 return stride > max_stride;
2891 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2892 const struct drm_framebuffer *fb,
2897 if (color_plane == 0) {
2905 * TODO: Deduct the subsampling from the char block for all CCS
2906 * formats and planes.
2908 if (!is_gen12_ccs_plane(fb, color_plane)) {
2909 *hsub = fb->format->hsub;
2910 *vsub = fb->format->vsub;
2915 main_plane = ccs_to_main_plane(fb, color_plane);
2916 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2917 drm_format_info_block_width(fb->format, main_plane);
2920 * The min stride check in the core framebuffer_check() function
2921 * assumes that format->hsub applies to every plane except for the
2922 * first plane. That's incorrect for the CCS AUX plane of the first
2923 * plane, but for the above check to pass we must define the block
2924 * width with that subsampling applied to it. Adjust the width here
2925 * accordingly, so we can calculate the actual subsampling factor.
2927 if (main_plane == 0)
2928 *hsub *= fb->format->hsub;
2933 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2935 struct drm_i915_private *i915 = to_i915(fb->dev);
2936 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2939 int tile_width, tile_height;
2943 if (!is_ccs_plane(fb, ccs_plane))
2946 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2947 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2950 tile_height *= vsub;
2952 ccs_x = (x * hsub) % tile_width;
2953 ccs_y = (y * vsub) % tile_height;
2955 main_plane = ccs_to_main_plane(fb, ccs_plane);
2956 main_x = intel_fb->normal[main_plane].x % tile_width;
2957 main_y = intel_fb->normal[main_plane].y % tile_height;
2960 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2961 * x/y offsets must match between CCS and the main surface.
2963 if (main_x != ccs_x || main_y != ccs_y) {
2964 drm_dbg_kms(&i915->drm,
2965 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2968 intel_fb->normal[main_plane].x,
2969 intel_fb->normal[main_plane].y,
2978 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2980 int main_plane = is_ccs_plane(fb, color_plane) ?
2981 ccs_to_main_plane(fb, color_plane) : 0;
2982 int main_hsub, main_vsub;
2985 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2986 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2987 *w = fb->width / main_hsub / hsub;
2988 *h = fb->height / main_vsub / vsub;
2992 * Setup the rotated view for an FB plane and return the size the GTT mapping
2993 * requires for this view.
2996 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2997 u32 gtt_offset_rotated, int x, int y,
2998 unsigned int width, unsigned int height,
2999 unsigned int tile_size,
3000 unsigned int tile_width, unsigned int tile_height,
3001 struct drm_framebuffer *fb)
3003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3004 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
3005 unsigned int pitch_tiles;
3008 /* Y or Yf modifiers required for 90/270 rotation */
3009 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3010 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3013 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3016 rot_info->plane[plane] = *plane_info;
3018 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3020 /* rotate the x/y offsets to match the GTT view */
3021 drm_rect_init(&r, x, y, width, height);
3023 plane_info->width * tile_width,
3024 plane_info->height * tile_height,
3025 DRM_MODE_ROTATE_270);
3029 /* rotate the tile dimensions to match the GTT view */
3030 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3031 swap(tile_width, tile_height);
3034 * We only keep the x/y offsets, so push all of the
3035 * gtt offset into the x/y offsets.
3037 intel_adjust_tile_offset(&x, &y,
3038 tile_width, tile_height,
3039 tile_size, pitch_tiles,
3040 gtt_offset_rotated * tile_size, 0);
3043 * First pixel of the framebuffer from
3044 * the start of the rotated gtt mapping.
3046 intel_fb->rotated[plane].x = x;
3047 intel_fb->rotated[plane].y = y;
3049 return plane_info->width * plane_info->height;
3053 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3054 struct drm_framebuffer *fb)
3056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3058 u32 gtt_offset_rotated = 0;
3059 unsigned int max_size = 0;
3060 int i, num_planes = fb->format->num_planes;
3061 unsigned int tile_size = intel_tile_size(dev_priv);
3063 for (i = 0; i < num_planes; i++) {
3064 unsigned int width, height;
3065 unsigned int cpp, size;
3070 cpp = fb->format->cpp[i];
3071 intel_fb_plane_dims(&width, &height, fb, i);
3073 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3075 drm_dbg_kms(&dev_priv->drm,
3076 "bad fb plane %d offset: 0x%x\n",
3081 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3086 * The fence (if used) is aligned to the start of the object
3087 * so having the framebuffer wrap around across the edge of the
3088 * fenced region doesn't really work. We have no API to configure
3089 * the fence start offset within the object (nor could we probably
3090 * on gen2/3). So it's just easier if we just require that the
3091 * fb layout agrees with the fence layout. We already check that the
3092 * fb stride matches the fence stride elsewhere.
3094 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3095 (x + width) * cpp > fb->pitches[i]) {
3096 drm_dbg_kms(&dev_priv->drm,
3097 "bad fb plane %d offset: 0x%x\n",
3103 * First pixel of the framebuffer from
3104 * the start of the normal gtt mapping.
3106 intel_fb->normal[i].x = x;
3107 intel_fb->normal[i].y = y;
3109 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3113 offset /= tile_size;
3115 if (!is_surface_linear(fb, i)) {
3116 struct intel_remapped_plane_info plane_info;
3117 unsigned int tile_width, tile_height;
3119 intel_tile_dims(fb, i, &tile_width, &tile_height);
3121 plane_info.offset = offset;
3122 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3124 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3125 plane_info.height = DIV_ROUND_UP(y + height,
3128 /* how many tiles does this plane need */
3129 size = plane_info.stride * plane_info.height;
3131 * If the plane isn't horizontally tile aligned,
3132 * we need one more tile.
3137 gtt_offset_rotated +=
3138 setup_fb_rotation(i, &plane_info,
3140 x, y, width, height,
3142 tile_width, tile_height,
3145 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3146 x * cpp, tile_size);
3149 /* how many tiles in total needed in the bo */
3150 max_size = max(max_size, offset + size);
3153 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3154 drm_dbg_kms(&dev_priv->drm,
3155 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3156 mul_u32_u32(max_size, tile_size), obj->base.size);
3164 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3166 struct drm_i915_private *dev_priv =
3167 to_i915(plane_state->uapi.plane->dev);
3168 struct drm_framebuffer *fb = plane_state->hw.fb;
3169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3170 struct intel_rotation_info *info = &plane_state->view.rotated;
3171 unsigned int rotation = plane_state->hw.rotation;
3172 int i, num_planes = fb->format->num_planes;
3173 unsigned int tile_size = intel_tile_size(dev_priv);
3174 unsigned int src_x, src_y;
3175 unsigned int src_w, src_h;
3178 memset(&plane_state->view, 0, sizeof(plane_state->view));
3179 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3180 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3182 src_x = plane_state->uapi.src.x1 >> 16;
3183 src_y = plane_state->uapi.src.y1 >> 16;
3184 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3185 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3187 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3189 /* Make src coordinates relative to the viewport */
3190 drm_rect_translate(&plane_state->uapi.src,
3191 -(src_x << 16), -(src_y << 16));
3193 /* Rotate src coordinates to match rotated GTT view */
3194 if (drm_rotation_90_or_270(rotation))
3195 drm_rect_rotate(&plane_state->uapi.src,
3196 src_w << 16, src_h << 16,
3197 DRM_MODE_ROTATE_270);
3199 for (i = 0; i < num_planes; i++) {
3200 unsigned int hsub = i ? fb->format->hsub : 1;
3201 unsigned int vsub = i ? fb->format->vsub : 1;
3202 unsigned int cpp = fb->format->cpp[i];
3203 unsigned int tile_width, tile_height;
3204 unsigned int width, height;
3205 unsigned int pitch_tiles;
3209 intel_tile_dims(fb, i, &tile_width, &tile_height);
3213 width = src_w / hsub;
3214 height = src_h / vsub;
3217 * First pixel of the src viewport from the
3218 * start of the normal gtt mapping.
3220 x += intel_fb->normal[i].x;
3221 y += intel_fb->normal[i].y;
3223 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3224 fb, i, fb->pitches[i],
3225 DRM_MODE_ROTATE_0, tile_size);
3226 offset /= tile_size;
3228 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3229 info->plane[i].offset = offset;
3230 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3232 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3233 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3235 if (drm_rotation_90_or_270(rotation)) {
3238 /* rotate the x/y offsets to match the GTT view */
3239 drm_rect_init(&r, x, y, width, height);
3241 info->plane[i].width * tile_width,
3242 info->plane[i].height * tile_height,
3243 DRM_MODE_ROTATE_270);
3247 pitch_tiles = info->plane[i].height;
3248 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3250 /* rotate the tile dimensions to match the GTT view */
3251 swap(tile_width, tile_height);
3253 pitch_tiles = info->plane[i].width;
3254 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3258 * We only keep the x/y offsets, so push all of the
3259 * gtt offset into the x/y offsets.
3261 intel_adjust_tile_offset(&x, &y,
3262 tile_width, tile_height,
3263 tile_size, pitch_tiles,
3264 gtt_offset * tile_size, 0);
3266 gtt_offset += info->plane[i].width * info->plane[i].height;
3268 plane_state->color_plane[i].offset = 0;
3269 plane_state->color_plane[i].x = x;
3270 plane_state->color_plane[i].y = y;
3275 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3277 const struct intel_framebuffer *fb =
3278 to_intel_framebuffer(plane_state->hw.fb);
3279 unsigned int rotation = plane_state->hw.rotation;
3285 num_planes = fb->base.format->num_planes;
3287 if (intel_plane_needs_remap(plane_state)) {
3288 intel_plane_remap_gtt(plane_state);
3291 * Sometimes even remapping can't overcome
3292 * the stride limitations :( Can happen with
3293 * big plane sizes and suitably misaligned
3296 return intel_plane_check_stride(plane_state);
3299 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3301 for (i = 0; i < num_planes; i++) {
3302 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3303 plane_state->color_plane[i].offset = 0;
3305 if (drm_rotation_90_or_270(rotation)) {
3306 plane_state->color_plane[i].x = fb->rotated[i].x;
3307 plane_state->color_plane[i].y = fb->rotated[i].y;
3309 plane_state->color_plane[i].x = fb->normal[i].x;
3310 plane_state->color_plane[i].y = fb->normal[i].y;
3314 /* Rotate src coordinates to match rotated GTT view */
3315 if (drm_rotation_90_or_270(rotation))
3316 drm_rect_rotate(&plane_state->uapi.src,
3317 fb->base.width << 16, fb->base.height << 16,
3318 DRM_MODE_ROTATE_270);
3320 return intel_plane_check_stride(plane_state);
3323 static int i9xx_format_to_fourcc(int format)
3326 case DISPPLANE_8BPP:
3327 return DRM_FORMAT_C8;
3328 case DISPPLANE_BGRA555:
3329 return DRM_FORMAT_ARGB1555;
3330 case DISPPLANE_BGRX555:
3331 return DRM_FORMAT_XRGB1555;
3332 case DISPPLANE_BGRX565:
3333 return DRM_FORMAT_RGB565;
3335 case DISPPLANE_BGRX888:
3336 return DRM_FORMAT_XRGB8888;
3337 case DISPPLANE_RGBX888:
3338 return DRM_FORMAT_XBGR8888;
3339 case DISPPLANE_BGRA888:
3340 return DRM_FORMAT_ARGB8888;
3341 case DISPPLANE_RGBA888:
3342 return DRM_FORMAT_ABGR8888;
3343 case DISPPLANE_BGRX101010:
3344 return DRM_FORMAT_XRGB2101010;
3345 case DISPPLANE_RGBX101010:
3346 return DRM_FORMAT_XBGR2101010;
3347 case DISPPLANE_BGRA101010:
3348 return DRM_FORMAT_ARGB2101010;
3349 case DISPPLANE_RGBA101010:
3350 return DRM_FORMAT_ABGR2101010;
3351 case DISPPLANE_RGBX161616:
3352 return DRM_FORMAT_XBGR16161616F;
3356 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3359 case PLANE_CTL_FORMAT_RGB_565:
3360 return DRM_FORMAT_RGB565;
3361 case PLANE_CTL_FORMAT_NV12:
3362 return DRM_FORMAT_NV12;
3363 case PLANE_CTL_FORMAT_XYUV:
3364 return DRM_FORMAT_XYUV8888;
3365 case PLANE_CTL_FORMAT_P010:
3366 return DRM_FORMAT_P010;
3367 case PLANE_CTL_FORMAT_P012:
3368 return DRM_FORMAT_P012;
3369 case PLANE_CTL_FORMAT_P016:
3370 return DRM_FORMAT_P016;
3371 case PLANE_CTL_FORMAT_Y210:
3372 return DRM_FORMAT_Y210;
3373 case PLANE_CTL_FORMAT_Y212:
3374 return DRM_FORMAT_Y212;
3375 case PLANE_CTL_FORMAT_Y216:
3376 return DRM_FORMAT_Y216;
3377 case PLANE_CTL_FORMAT_Y410:
3378 return DRM_FORMAT_XVYU2101010;
3379 case PLANE_CTL_FORMAT_Y412:
3380 return DRM_FORMAT_XVYU12_16161616;
3381 case PLANE_CTL_FORMAT_Y416:
3382 return DRM_FORMAT_XVYU16161616;
3384 case PLANE_CTL_FORMAT_XRGB_8888:
3387 return DRM_FORMAT_ABGR8888;
3389 return DRM_FORMAT_XBGR8888;
3392 return DRM_FORMAT_ARGB8888;
3394 return DRM_FORMAT_XRGB8888;
3396 case PLANE_CTL_FORMAT_XRGB_2101010:
3399 return DRM_FORMAT_ABGR2101010;
3401 return DRM_FORMAT_XBGR2101010;
3404 return DRM_FORMAT_ARGB2101010;
3406 return DRM_FORMAT_XRGB2101010;
3408 case PLANE_CTL_FORMAT_XRGB_16161616F:
3411 return DRM_FORMAT_ABGR16161616F;
3413 return DRM_FORMAT_XBGR16161616F;
3416 return DRM_FORMAT_ARGB16161616F;
3418 return DRM_FORMAT_XRGB16161616F;
3423 static struct i915_vma *
3424 initial_plane_vma(struct drm_i915_private *i915,
3425 struct intel_initial_plane_config *plane_config)
3427 struct drm_i915_gem_object *obj;
3428 struct i915_vma *vma;
3431 if (plane_config->size == 0)
3434 base = round_down(plane_config->base,
3435 I915_GTT_MIN_ALIGNMENT);
3436 size = round_up(plane_config->base + plane_config->size,
3437 I915_GTT_MIN_ALIGNMENT);
3441 * If the FB is too big, just don't use it since fbdev is not very
3442 * important and we should probably use that space with FBC or other
3445 if (size * 2 > i915->stolen_usable_size)
3448 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3453 * Mark it WT ahead of time to avoid changing the
3454 * cache_level during fbdev initialization. The
3455 * unbind there would get stuck waiting for rcu.
3457 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3458 I915_CACHE_WT : I915_CACHE_NONE);
3460 switch (plane_config->tiling) {
3461 case I915_TILING_NONE:
3465 obj->tiling_and_stride =
3466 plane_config->fb->base.pitches[0] |
3467 plane_config->tiling;
3470 MISSING_CASE(plane_config->tiling);
3474 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3478 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3481 if (i915_gem_object_is_tiled(obj) &&
3482 !i915_vma_is_map_and_fenceable(vma))
3488 i915_gem_object_put(obj);
3493 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3494 struct intel_initial_plane_config *plane_config)
3496 struct drm_device *dev = crtc->base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3499 struct drm_framebuffer *fb = &plane_config->fb->base;
3500 struct i915_vma *vma;
3502 switch (fb->modifier) {
3503 case DRM_FORMAT_MOD_LINEAR:
3504 case I915_FORMAT_MOD_X_TILED:
3505 case I915_FORMAT_MOD_Y_TILED:
3508 drm_dbg(&dev_priv->drm,
3509 "Unsupported modifier for initial FB: 0x%llx\n",
3514 vma = initial_plane_vma(dev_priv, plane_config);
3518 mode_cmd.pixel_format = fb->format->format;
3519 mode_cmd.width = fb->width;
3520 mode_cmd.height = fb->height;
3521 mode_cmd.pitches[0] = fb->pitches[0];
3522 mode_cmd.modifier[0] = fb->modifier;
3523 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3525 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3526 vma->obj, &mode_cmd)) {
3527 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3531 plane_config->vma = vma;
3540 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3541 struct intel_plane_state *plane_state,
3544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3546 plane_state->uapi.visible = visible;
3549 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3551 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3554 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3556 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3557 struct drm_plane *plane;
3560 * Active_planes aliases if multiple "primary" or cursor planes
3561 * have been used on the same (or wrong) pipe. plane_mask uses
3562 * unique ids, hence we can use that to reconstruct active_planes.
3564 crtc_state->active_planes = 0;
3566 drm_for_each_plane_mask(plane, &dev_priv->drm,
3567 crtc_state->uapi.plane_mask)
3568 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3571 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3572 struct intel_plane *plane)
3574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3575 struct intel_crtc_state *crtc_state =
3576 to_intel_crtc_state(crtc->base.state);
3577 struct intel_plane_state *plane_state =
3578 to_intel_plane_state(plane->base.state);
3580 drm_dbg_kms(&dev_priv->drm,
3581 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3582 plane->base.base.id, plane->base.name,
3583 crtc->base.base.id, crtc->base.name);
3585 intel_set_plane_visible(crtc_state, plane_state, false);
3586 fixup_active_planes(crtc_state);
3587 crtc_state->data_rate[plane->id] = 0;
3588 crtc_state->min_cdclk[plane->id] = 0;
3590 if (plane->id == PLANE_PRIMARY)
3591 hsw_disable_ips(crtc_state);
3594 * Vblank time updates from the shadow to live plane control register
3595 * are blocked if the memory self-refresh mode is active at that
3596 * moment. So to make sure the plane gets truly disabled, disable
3597 * first the self-refresh mode. The self-refresh enable bit in turn
3598 * will be checked/applied by the HW only at the next frame start
3599 * event which is after the vblank start event, so we need to have a
3600 * wait-for-vblank between disabling the plane and the pipe.
3602 if (HAS_GMCH(dev_priv) &&
3603 intel_set_memory_cxsr(dev_priv, false))
3604 intel_wait_for_vblank(dev_priv, crtc->pipe);
3607 * Gen2 reports pipe underruns whenever all planes are disabled.
3608 * So disable underrun reporting before all the planes get disabled.
3610 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3611 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3613 intel_disable_plane(plane, crtc_state);
3616 static struct intel_frontbuffer *
3617 to_intel_frontbuffer(struct drm_framebuffer *fb)
3619 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3623 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3624 struct intel_initial_plane_config *plane_config)
3626 struct drm_device *dev = intel_crtc->base.dev;
3627 struct drm_i915_private *dev_priv = to_i915(dev);
3629 struct drm_plane *primary = intel_crtc->base.primary;
3630 struct drm_plane_state *plane_state = primary->state;
3631 struct intel_plane *intel_plane = to_intel_plane(primary);
3632 struct intel_plane_state *intel_state =
3633 to_intel_plane_state(plane_state);
3634 struct drm_framebuffer *fb;
3635 struct i915_vma *vma;
3637 if (!plane_config->fb)
3640 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3641 fb = &plane_config->fb->base;
3642 vma = plane_config->vma;
3647 * Failed to alloc the obj, check to see if we should share
3648 * an fb with another CRTC instead
3650 for_each_crtc(dev, c) {
3651 struct intel_plane_state *state;
3653 if (c == &intel_crtc->base)
3656 if (!to_intel_crtc(c)->active)
3659 state = to_intel_plane_state(c->primary->state);
3663 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3671 * We've failed to reconstruct the BIOS FB. Current display state
3672 * indicates that the primary plane is visible, but has a NULL FB,
3673 * which will lead to problems later if we don't fix it up. The
3674 * simplest solution is to just disable the primary plane now and
3675 * pretend the BIOS never had it enabled.
3677 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3682 intel_state->hw.rotation = plane_config->rotation;
3683 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3684 intel_state->hw.rotation);
3685 intel_state->color_plane[0].stride =
3686 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3688 __i915_vma_pin(vma);
3689 intel_state->vma = i915_vma_get(vma);
3690 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3692 intel_state->flags |= PLANE_HAS_FENCE;
3694 plane_state->src_x = 0;
3695 plane_state->src_y = 0;
3696 plane_state->src_w = fb->width << 16;
3697 plane_state->src_h = fb->height << 16;
3699 plane_state->crtc_x = 0;
3700 plane_state->crtc_y = 0;
3701 plane_state->crtc_w = fb->width;
3702 plane_state->crtc_h = fb->height;
3704 intel_state->uapi.src = drm_plane_state_src(plane_state);
3705 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3707 if (plane_config->tiling)
3708 dev_priv->preserve_bios_swizzle = true;
3710 plane_state->fb = fb;
3711 drm_framebuffer_get(fb);
3713 plane_state->crtc = &intel_crtc->base;
3714 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3716 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3718 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3719 &to_intel_frontbuffer(fb)->bits);
3722 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3724 unsigned int rotation)
3726 int cpp = fb->format->cpp[color_plane];
3728 switch (fb->modifier) {
3729 case DRM_FORMAT_MOD_LINEAR:
3730 case I915_FORMAT_MOD_X_TILED:
3732 * Validated limit is 4k, but has 5k should
3733 * work apart from the following features:
3734 * - Ytile (already limited to 4k)
3735 * - FP16 (already limited to 4k)
3736 * - render compression (already limited to 4k)
3737 * - KVMR sprite and cursor (don't care)
3738 * - horizontal panning (TODO verify this)
3739 * - pipe and plane scaling (TODO verify this)
3745 case I915_FORMAT_MOD_Y_TILED_CCS:
3746 case I915_FORMAT_MOD_Yf_TILED_CCS:
3747 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3748 /* FIXME AUX plane? */
3749 case I915_FORMAT_MOD_Y_TILED:
3750 case I915_FORMAT_MOD_Yf_TILED:
3756 MISSING_CASE(fb->modifier);
3761 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3763 unsigned int rotation)
3765 int cpp = fb->format->cpp[color_plane];
3767 switch (fb->modifier) {
3768 case DRM_FORMAT_MOD_LINEAR:
3769 case I915_FORMAT_MOD_X_TILED:
3774 case I915_FORMAT_MOD_Y_TILED_CCS:
3775 case I915_FORMAT_MOD_Yf_TILED_CCS:
3776 /* FIXME AUX plane? */
3777 case I915_FORMAT_MOD_Y_TILED:
3778 case I915_FORMAT_MOD_Yf_TILED:
3784 MISSING_CASE(fb->modifier);
3789 static int icl_min_plane_width(const struct drm_framebuffer *fb)
3791 /* Wa_14011264657, Wa_14011050563: gen11+ */
3792 switch (fb->format->format) {
3795 case DRM_FORMAT_RGB565:
3797 case DRM_FORMAT_XRGB8888:
3798 case DRM_FORMAT_XBGR8888:
3799 case DRM_FORMAT_ARGB8888:
3800 case DRM_FORMAT_ABGR8888:
3801 case DRM_FORMAT_XRGB2101010:
3802 case DRM_FORMAT_XBGR2101010:
3803 case DRM_FORMAT_ARGB2101010:
3804 case DRM_FORMAT_ABGR2101010:
3805 case DRM_FORMAT_XVYU2101010:
3806 case DRM_FORMAT_Y212:
3807 case DRM_FORMAT_Y216:
3809 case DRM_FORMAT_NV12:
3811 case DRM_FORMAT_P010:
3812 case DRM_FORMAT_P012:
3813 case DRM_FORMAT_P016:
3815 case DRM_FORMAT_XRGB16161616F:
3816 case DRM_FORMAT_XBGR16161616F:
3817 case DRM_FORMAT_ARGB16161616F:
3818 case DRM_FORMAT_ABGR16161616F:
3819 case DRM_FORMAT_XVYU12_16161616:
3820 case DRM_FORMAT_XVYU16161616:
3827 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3829 unsigned int rotation)
3834 static int skl_max_plane_height(void)
3839 static int icl_max_plane_height(void)
3845 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3846 int main_x, int main_y, u32 main_offset,
3849 const struct drm_framebuffer *fb = plane_state->hw.fb;
3850 int aux_x = plane_state->color_plane[ccs_plane].x;
3851 int aux_y = plane_state->color_plane[ccs_plane].y;
3852 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3853 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3857 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3858 while (aux_offset >= main_offset && aux_y <= main_y) {
3861 if (aux_x == main_x && aux_y == main_y)
3864 if (aux_offset == 0)
3869 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3875 aux_x = x * hsub + aux_x % hsub;
3876 aux_y = y * vsub + aux_y % vsub;
3879 if (aux_x != main_x || aux_y != main_y)
3882 plane_state->color_plane[ccs_plane].offset = aux_offset;
3883 plane_state->color_plane[ccs_plane].x = aux_x;
3884 plane_state->color_plane[ccs_plane].y = aux_y;
3890 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3894 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3895 plane_state->color_plane[0].offset, 0);
3900 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3902 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3903 const struct drm_framebuffer *fb = plane_state->hw.fb;
3904 unsigned int rotation = plane_state->hw.rotation;
3905 int x = plane_state->uapi.src.x1 >> 16;
3906 int y = plane_state->uapi.src.y1 >> 16;
3907 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3908 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3909 int max_width, min_width, max_height;
3910 u32 alignment, offset;
3911 int aux_plane = intel_main_to_aux_plane(fb, 0);
3912 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3914 if (INTEL_GEN(dev_priv) >= 11) {
3915 max_width = icl_max_plane_width(fb, 0, rotation);
3916 min_width = icl_min_plane_width(fb);
3917 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
3918 max_width = glk_max_plane_width(fb, 0, rotation);
3921 max_width = skl_max_plane_width(fb, 0, rotation);
3925 if (INTEL_GEN(dev_priv) >= 11)
3926 max_height = icl_max_plane_height();
3928 max_height = skl_max_plane_height();
3930 if (w > max_width || w < min_width || h > max_height) {
3931 drm_dbg_kms(&dev_priv->drm,
3932 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3933 w, h, min_width, max_width, max_height);
3937 intel_add_fb_offsets(&x, &y, plane_state, 0);
3938 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3939 alignment = intel_surf_alignment(fb, 0);
3940 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3944 * AUX surface offset is specified as the distance from the
3945 * main surface offset, and it must be non-negative. Make
3946 * sure that is what we will get.
3948 if (aux_plane && offset > aux_offset)
3949 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3950 offset, aux_offset & ~(alignment - 1));
3953 * When using an X-tiled surface, the plane blows up
3954 * if the x offset + width exceed the stride.
3956 * TODO: linear and Y-tiled seem fine, Yf untested,
3958 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3959 int cpp = fb->format->cpp[0];
3961 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3963 drm_dbg_kms(&dev_priv->drm,
3964 "Unable to find suitable display surface offset due to X-tiling\n");
3968 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3969 offset, offset - alignment);
3974 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3975 * they match with the main surface x/y offsets.
3977 if (is_ccs_modifier(fb->modifier)) {
3978 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3979 offset, aux_plane)) {
3983 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3984 offset, offset - alignment);
3987 if (x != plane_state->color_plane[aux_plane].x ||
3988 y != plane_state->color_plane[aux_plane].y) {
3989 drm_dbg_kms(&dev_priv->drm,
3990 "Unable to find suitable display surface offset due to CCS\n");
3995 plane_state->color_plane[0].offset = offset;
3996 plane_state->color_plane[0].x = x;
3997 plane_state->color_plane[0].y = y;
4000 * Put the final coordinates back so that the src
4001 * coordinate checks will see the right values.
4003 drm_rect_translate_to(&plane_state->uapi.src,
4009 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
4011 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
4012 const struct drm_framebuffer *fb = plane_state->hw.fb;
4013 unsigned int rotation = plane_state->hw.rotation;
4015 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
4016 int max_height = 4096;
4017 int x = plane_state->uapi.src.x1 >> 17;
4018 int y = plane_state->uapi.src.y1 >> 17;
4019 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4020 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4023 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4024 offset = intel_plane_compute_aligned_offset(&x, &y,
4025 plane_state, uv_plane);
4027 /* FIXME not quite sure how/if these apply to the chroma plane */
4028 if (w > max_width || h > max_height) {
4029 drm_dbg_kms(&i915->drm,
4030 "CbCr source size %dx%d too big (limit %dx%d)\n",
4031 w, h, max_width, max_height);
4035 if (is_ccs_modifier(fb->modifier)) {
4036 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4037 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
4038 u32 alignment = intel_surf_alignment(fb, uv_plane);
4040 if (offset > aux_offset)
4041 offset = intel_plane_adjust_aligned_offset(&x, &y,
4045 aux_offset & ~(alignment - 1));
4047 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4048 offset, ccs_plane)) {
4052 offset = intel_plane_adjust_aligned_offset(&x, &y,
4055 offset, offset - alignment);
4058 if (x != plane_state->color_plane[ccs_plane].x ||
4059 y != plane_state->color_plane[ccs_plane].y) {
4060 drm_dbg_kms(&i915->drm,
4061 "Unable to find suitable display surface offset due to CCS\n");
4066 plane_state->color_plane[uv_plane].offset = offset;
4067 plane_state->color_plane[uv_plane].x = x;
4068 plane_state->color_plane[uv_plane].y = y;
4073 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4075 const struct drm_framebuffer *fb = plane_state->hw.fb;
4076 int src_x = plane_state->uapi.src.x1 >> 16;
4077 int src_y = plane_state->uapi.src.y1 >> 16;
4081 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4082 int main_hsub, main_vsub;
4086 if (!is_ccs_plane(fb, ccs_plane))
4089 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4090 ccs_to_main_plane(fb, ccs_plane));
4091 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4098 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4100 offset = intel_plane_compute_aligned_offset(&x, &y,
4104 plane_state->color_plane[ccs_plane].offset = offset;
4105 plane_state->color_plane[ccs_plane].x = (x * hsub +
4108 plane_state->color_plane[ccs_plane].y = (y * vsub +
4116 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4118 const struct drm_framebuffer *fb = plane_state->hw.fb;
4121 ret = intel_plane_compute_gtt(plane_state);
4125 if (!plane_state->uapi.visible)
4129 * Handle the AUX surface first since the main surface setup depends on
4132 if (is_ccs_modifier(fb->modifier)) {
4133 ret = skl_check_ccs_aux_surface(plane_state);
4138 if (intel_format_info_is_yuv_semiplanar(fb->format,
4140 ret = skl_check_nv12_aux_surface(plane_state);
4145 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4146 plane_state->color_plane[i].offset = 0;
4147 plane_state->color_plane[i].x = 0;
4148 plane_state->color_plane[i].y = 0;
4151 ret = skl_check_main_surface(plane_state);
4158 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4159 const struct intel_plane_state *plane_state,
4160 unsigned int *num, unsigned int *den)
4162 const struct drm_framebuffer *fb = plane_state->hw.fb;
4163 unsigned int cpp = fb->format->cpp[0];
4166 * g4x bspec says 64bpp pixel rate can't exceed 80%
4167 * of cdclk when the sprite plane is enabled on the
4168 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4169 * never allowed to exceed 80% of cdclk. Let's just go
4170 * with the ilk/snb limit always.
4181 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4182 const struct intel_plane_state *plane_state)
4184 unsigned int pixel_rate;
4185 unsigned int num, den;
4188 * Note that crtc_state->pixel_rate accounts for both
4189 * horizontal and vertical panel fitter downscaling factors.
4190 * Pre-HSW bspec tells us to only consider the horizontal
4191 * downscaling factor here. We ignore that and just consider
4192 * both for simplicity.
4194 pixel_rate = crtc_state->pixel_rate;
4196 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4198 /* two pixels per clock with double wide pipe */
4199 if (crtc_state->double_wide)
4202 return DIV_ROUND_UP(pixel_rate * num, den);
4206 i9xx_plane_max_stride(struct intel_plane *plane,
4207 u32 pixel_format, u64 modifier,
4208 unsigned int rotation)
4210 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4212 if (!HAS_GMCH(dev_priv)) {
4214 } else if (INTEL_GEN(dev_priv) >= 4) {
4215 if (modifier == I915_FORMAT_MOD_X_TILED)
4219 } else if (INTEL_GEN(dev_priv) >= 3) {
4220 if (modifier == I915_FORMAT_MOD_X_TILED)
4225 if (plane->i9xx_plane == PLANE_C)
4232 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4238 if (crtc_state->gamma_enable)
4239 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4241 if (crtc_state->csc_enable)
4242 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4244 if (INTEL_GEN(dev_priv) < 5)
4245 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4250 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4251 const struct intel_plane_state *plane_state)
4253 struct drm_i915_private *dev_priv =
4254 to_i915(plane_state->uapi.plane->dev);
4255 const struct drm_framebuffer *fb = plane_state->hw.fb;
4256 unsigned int rotation = plane_state->hw.rotation;
4259 dspcntr = DISPLAY_PLANE_ENABLE;
4261 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4262 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4263 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4265 switch (fb->format->format) {
4267 dspcntr |= DISPPLANE_8BPP;
4269 case DRM_FORMAT_XRGB1555:
4270 dspcntr |= DISPPLANE_BGRX555;
4272 case DRM_FORMAT_ARGB1555:
4273 dspcntr |= DISPPLANE_BGRA555;
4275 case DRM_FORMAT_RGB565:
4276 dspcntr |= DISPPLANE_BGRX565;
4278 case DRM_FORMAT_XRGB8888:
4279 dspcntr |= DISPPLANE_BGRX888;
4281 case DRM_FORMAT_XBGR8888:
4282 dspcntr |= DISPPLANE_RGBX888;
4284 case DRM_FORMAT_ARGB8888:
4285 dspcntr |= DISPPLANE_BGRA888;
4287 case DRM_FORMAT_ABGR8888:
4288 dspcntr |= DISPPLANE_RGBA888;
4290 case DRM_FORMAT_XRGB2101010:
4291 dspcntr |= DISPPLANE_BGRX101010;
4293 case DRM_FORMAT_XBGR2101010:
4294 dspcntr |= DISPPLANE_RGBX101010;
4296 case DRM_FORMAT_ARGB2101010:
4297 dspcntr |= DISPPLANE_BGRA101010;
4299 case DRM_FORMAT_ABGR2101010:
4300 dspcntr |= DISPPLANE_RGBA101010;
4302 case DRM_FORMAT_XBGR16161616F:
4303 dspcntr |= DISPPLANE_RGBX161616;
4306 MISSING_CASE(fb->format->format);
4310 if (INTEL_GEN(dev_priv) >= 4 &&
4311 fb->modifier == I915_FORMAT_MOD_X_TILED)
4312 dspcntr |= DISPPLANE_TILED;
4314 if (rotation & DRM_MODE_ROTATE_180)
4315 dspcntr |= DISPPLANE_ROTATE_180;
4317 if (rotation & DRM_MODE_REFLECT_X)
4318 dspcntr |= DISPPLANE_MIRROR;
4323 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4325 struct drm_i915_private *dev_priv =
4326 to_i915(plane_state->uapi.plane->dev);
4327 const struct drm_framebuffer *fb = plane_state->hw.fb;
4328 int src_x, src_y, src_w;
4332 ret = intel_plane_compute_gtt(plane_state);
4336 if (!plane_state->uapi.visible)
4339 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4340 src_x = plane_state->uapi.src.x1 >> 16;
4341 src_y = plane_state->uapi.src.y1 >> 16;
4343 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4344 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4347 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4349 if (INTEL_GEN(dev_priv) >= 4)
4350 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4356 * Put the final coordinates back so that the src
4357 * coordinate checks will see the right values.
4359 drm_rect_translate_to(&plane_state->uapi.src,
4360 src_x << 16, src_y << 16);
4362 /* HSW/BDW do this automagically in hardware */
4363 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4364 unsigned int rotation = plane_state->hw.rotation;
4365 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4366 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4368 if (rotation & DRM_MODE_ROTATE_180) {
4371 } else if (rotation & DRM_MODE_REFLECT_X) {
4376 plane_state->color_plane[0].offset = offset;
4377 plane_state->color_plane[0].x = src_x;
4378 plane_state->color_plane[0].y = src_y;
4383 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4385 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4386 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4388 if (IS_CHERRYVIEW(dev_priv))
4389 return i9xx_plane == PLANE_B;
4390 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4392 else if (IS_GEN(dev_priv, 4))
4393 return i9xx_plane == PLANE_C;
4395 return i9xx_plane == PLANE_B ||
4396 i9xx_plane == PLANE_C;
4400 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4401 struct intel_plane_state *plane_state)
4403 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4406 ret = chv_plane_check_rotation(plane_state);
4410 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4412 DRM_PLANE_HELPER_NO_SCALING,
4413 DRM_PLANE_HELPER_NO_SCALING,
4414 i9xx_plane_has_windowing(plane),
4419 ret = i9xx_check_plane_surface(plane_state);
4423 if (!plane_state->uapi.visible)
4426 ret = intel_plane_check_src_coordinates(plane_state);
4430 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4435 static void i9xx_update_plane(struct intel_plane *plane,
4436 const struct intel_crtc_state *crtc_state,
4437 const struct intel_plane_state *plane_state)
4439 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4440 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4442 int x = plane_state->color_plane[0].x;
4443 int y = plane_state->color_plane[0].y;
4444 int crtc_x = plane_state->uapi.dst.x1;
4445 int crtc_y = plane_state->uapi.dst.y1;
4446 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4447 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4448 unsigned long irqflags;
4452 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4454 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4456 if (INTEL_GEN(dev_priv) >= 4)
4457 dspaddr_offset = plane_state->color_plane[0].offset;
4459 dspaddr_offset = linear_offset;
4461 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4463 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4464 plane_state->color_plane[0].stride);
4466 if (INTEL_GEN(dev_priv) < 4) {
4468 * PLANE_A doesn't actually have a full window
4469 * generator but let's assume we still need to
4470 * program whatever is there.
4472 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4473 (crtc_y << 16) | crtc_x);
4474 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4475 ((crtc_h - 1) << 16) | (crtc_w - 1));
4476 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4477 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4478 (crtc_y << 16) | crtc_x);
4479 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4480 ((crtc_h - 1) << 16) | (crtc_w - 1));
4481 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4484 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4485 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4487 } else if (INTEL_GEN(dev_priv) >= 4) {
4488 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4490 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4495 * The control register self-arms if the plane was previously
4496 * disabled. Try to make the plane enable atomic by writing
4497 * the control register just before the surface register.
4499 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4500 if (INTEL_GEN(dev_priv) >= 4)
4501 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4502 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4504 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4505 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4507 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4510 static void i9xx_disable_plane(struct intel_plane *plane,
4511 const struct intel_crtc_state *crtc_state)
4513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4514 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4515 unsigned long irqflags;
4519 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4520 * enable on ilk+ affect the pipe bottom color as
4521 * well, so we must configure them even if the plane
4524 * On pre-g4x there is no way to gamma correct the
4525 * pipe bottom color but we'll keep on doing this
4526 * anyway so that the crtc state readout works correctly.
4528 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4530 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4532 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4533 if (INTEL_GEN(dev_priv) >= 4)
4534 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4536 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4538 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4541 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4544 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4545 enum intel_display_power_domain power_domain;
4546 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4547 intel_wakeref_t wakeref;
4552 * Not 100% correct for planes that can move between pipes,
4553 * but that's only the case for gen2-4 which don't have any
4554 * display power wells.
4556 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4557 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4561 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4563 ret = val & DISPLAY_PLANE_ENABLE;
4565 if (INTEL_GEN(dev_priv) >= 5)
4566 *pipe = plane->pipe;
4568 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4569 DISPPLANE_SEL_PIPE_SHIFT;
4571 intel_display_power_put(dev_priv, power_domain, wakeref);
4576 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4578 struct drm_device *dev = intel_crtc->base.dev;
4579 struct drm_i915_private *dev_priv = to_i915(dev);
4580 unsigned long irqflags;
4582 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4584 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4585 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4586 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4588 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4592 * This function detaches (aka. unbinds) unused scalers in hardware
4594 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4597 const struct intel_crtc_scaler_state *scaler_state =
4598 &crtc_state->scaler_state;
4601 /* loop through and disable scalers that aren't in use */
4602 for (i = 0; i < intel_crtc->num_scalers; i++) {
4603 if (!scaler_state->scalers[i].in_use)
4604 skl_detach_scaler(intel_crtc, i);
4608 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4609 int color_plane, unsigned int rotation)
4612 * The stride is either expressed as a multiple of 64 bytes chunks for
4613 * linear buffers or in number of tiles for tiled buffers.
4615 if (is_surface_linear(fb, color_plane))
4617 else if (drm_rotation_90_or_270(rotation))
4618 return intel_tile_height(fb, color_plane);
4620 return intel_tile_width_bytes(fb, color_plane);
4623 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4626 const struct drm_framebuffer *fb = plane_state->hw.fb;
4627 unsigned int rotation = plane_state->hw.rotation;
4628 u32 stride = plane_state->color_plane[color_plane].stride;
4630 if (color_plane >= fb->format->num_planes)
4633 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4636 static u32 skl_plane_ctl_format(u32 pixel_format)
4638 switch (pixel_format) {
4640 return PLANE_CTL_FORMAT_INDEXED;
4641 case DRM_FORMAT_RGB565:
4642 return PLANE_CTL_FORMAT_RGB_565;
4643 case DRM_FORMAT_XBGR8888:
4644 case DRM_FORMAT_ABGR8888:
4645 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4646 case DRM_FORMAT_XRGB8888:
4647 case DRM_FORMAT_ARGB8888:
4648 return PLANE_CTL_FORMAT_XRGB_8888;
4649 case DRM_FORMAT_XBGR2101010:
4650 case DRM_FORMAT_ABGR2101010:
4651 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4652 case DRM_FORMAT_XRGB2101010:
4653 case DRM_FORMAT_ARGB2101010:
4654 return PLANE_CTL_FORMAT_XRGB_2101010;
4655 case DRM_FORMAT_XBGR16161616F:
4656 case DRM_FORMAT_ABGR16161616F:
4657 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4658 case DRM_FORMAT_XRGB16161616F:
4659 case DRM_FORMAT_ARGB16161616F:
4660 return PLANE_CTL_FORMAT_XRGB_16161616F;
4661 case DRM_FORMAT_XYUV8888:
4662 return PLANE_CTL_FORMAT_XYUV;
4663 case DRM_FORMAT_YUYV:
4664 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4665 case DRM_FORMAT_YVYU:
4666 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4667 case DRM_FORMAT_UYVY:
4668 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4669 case DRM_FORMAT_VYUY:
4670 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4671 case DRM_FORMAT_NV12:
4672 return PLANE_CTL_FORMAT_NV12;
4673 case DRM_FORMAT_P010:
4674 return PLANE_CTL_FORMAT_P010;
4675 case DRM_FORMAT_P012:
4676 return PLANE_CTL_FORMAT_P012;
4677 case DRM_FORMAT_P016:
4678 return PLANE_CTL_FORMAT_P016;
4679 case DRM_FORMAT_Y210:
4680 return PLANE_CTL_FORMAT_Y210;
4681 case DRM_FORMAT_Y212:
4682 return PLANE_CTL_FORMAT_Y212;
4683 case DRM_FORMAT_Y216:
4684 return PLANE_CTL_FORMAT_Y216;
4685 case DRM_FORMAT_XVYU2101010:
4686 return PLANE_CTL_FORMAT_Y410;
4687 case DRM_FORMAT_XVYU12_16161616:
4688 return PLANE_CTL_FORMAT_Y412;
4689 case DRM_FORMAT_XVYU16161616:
4690 return PLANE_CTL_FORMAT_Y416;
4692 MISSING_CASE(pixel_format);
4698 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4700 if (!plane_state->hw.fb->format->has_alpha)
4701 return PLANE_CTL_ALPHA_DISABLE;
4703 switch (plane_state->hw.pixel_blend_mode) {
4704 case DRM_MODE_BLEND_PIXEL_NONE:
4705 return PLANE_CTL_ALPHA_DISABLE;
4706 case DRM_MODE_BLEND_PREMULTI:
4707 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4708 case DRM_MODE_BLEND_COVERAGE:
4709 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4711 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4712 return PLANE_CTL_ALPHA_DISABLE;
4716 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4718 if (!plane_state->hw.fb->format->has_alpha)
4719 return PLANE_COLOR_ALPHA_DISABLE;
4721 switch (plane_state->hw.pixel_blend_mode) {
4722 case DRM_MODE_BLEND_PIXEL_NONE:
4723 return PLANE_COLOR_ALPHA_DISABLE;
4724 case DRM_MODE_BLEND_PREMULTI:
4725 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4726 case DRM_MODE_BLEND_COVERAGE:
4727 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4729 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4730 return PLANE_COLOR_ALPHA_DISABLE;
4734 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4736 switch (fb_modifier) {
4737 case DRM_FORMAT_MOD_LINEAR:
4739 case I915_FORMAT_MOD_X_TILED:
4740 return PLANE_CTL_TILED_X;
4741 case I915_FORMAT_MOD_Y_TILED:
4742 return PLANE_CTL_TILED_Y;
4743 case I915_FORMAT_MOD_Y_TILED_CCS:
4744 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4745 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4746 return PLANE_CTL_TILED_Y |
4747 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4748 PLANE_CTL_CLEAR_COLOR_DISABLE;
4749 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4750 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4751 case I915_FORMAT_MOD_Yf_TILED:
4752 return PLANE_CTL_TILED_YF;
4753 case I915_FORMAT_MOD_Yf_TILED_CCS:
4754 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4756 MISSING_CASE(fb_modifier);
4762 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4765 case DRM_MODE_ROTATE_0:
4768 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4769 * while i915 HW rotation is clockwise, thats why this swapping.
4771 case DRM_MODE_ROTATE_90:
4772 return PLANE_CTL_ROTATE_270;
4773 case DRM_MODE_ROTATE_180:
4774 return PLANE_CTL_ROTATE_180;
4775 case DRM_MODE_ROTATE_270:
4776 return PLANE_CTL_ROTATE_90;
4778 MISSING_CASE(rotate);
4784 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4789 case DRM_MODE_REFLECT_X:
4790 return PLANE_CTL_FLIP_HORIZONTAL;
4791 case DRM_MODE_REFLECT_Y:
4793 MISSING_CASE(reflect);
4799 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4801 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4804 if (crtc_state->uapi.async_flip)
4805 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
4807 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4810 if (crtc_state->gamma_enable)
4811 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4813 if (crtc_state->csc_enable)
4814 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4819 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4820 const struct intel_plane_state *plane_state)
4822 struct drm_i915_private *dev_priv =
4823 to_i915(plane_state->uapi.plane->dev);
4824 const struct drm_framebuffer *fb = plane_state->hw.fb;
4825 unsigned int rotation = plane_state->hw.rotation;
4826 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4829 plane_ctl = PLANE_CTL_ENABLE;
4831 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4832 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4833 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4835 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4836 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4838 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4839 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4842 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4843 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4844 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4846 if (INTEL_GEN(dev_priv) >= 10)
4847 plane_ctl |= cnl_plane_ctl_flip(rotation &
4848 DRM_MODE_REFLECT_MASK);
4850 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4851 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4852 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4853 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4858 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4860 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4861 u32 plane_color_ctl = 0;
4863 if (INTEL_GEN(dev_priv) >= 11)
4864 return plane_color_ctl;
4866 if (crtc_state->gamma_enable)
4867 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4869 if (crtc_state->csc_enable)
4870 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4872 return plane_color_ctl;
4875 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4876 const struct intel_plane_state *plane_state)
4878 struct drm_i915_private *dev_priv =
4879 to_i915(plane_state->uapi.plane->dev);
4880 const struct drm_framebuffer *fb = plane_state->hw.fb;
4881 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4882 u32 plane_color_ctl = 0;
4884 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4885 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4887 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4888 switch (plane_state->hw.color_encoding) {
4889 case DRM_COLOR_YCBCR_BT709:
4890 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4892 case DRM_COLOR_YCBCR_BT2020:
4894 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4898 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4900 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4901 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4902 } else if (fb->format->is_yuv) {
4903 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4906 return plane_color_ctl;
4910 __intel_display_resume(struct drm_device *dev,
4911 struct drm_atomic_state *state,
4912 struct drm_modeset_acquire_ctx *ctx)
4914 struct drm_crtc_state *crtc_state;
4915 struct drm_crtc *crtc;
4918 intel_modeset_setup_hw_state(dev, ctx);
4919 intel_vga_redisable(to_i915(dev));
4925 * We've duplicated the state, pointers to the old state are invalid.
4927 * Don't attempt to use the old state until we commit the duplicated state.
4929 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4931 * Force recalculation even if we restore
4932 * current state. With fast modeset this may not result
4933 * in a modeset when the state is compatible.
4935 crtc_state->mode_changed = true;
4938 /* ignore any reset values/BIOS leftovers in the WM registers */
4939 if (!HAS_GMCH(to_i915(dev)))
4940 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4942 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4944 drm_WARN_ON(dev, ret == -EDEADLK);
4948 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4950 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4951 intel_has_gpu_reset(&dev_priv->gt));
4954 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4956 struct drm_device *dev = &dev_priv->drm;
4957 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4958 struct drm_atomic_state *state;
4961 /* reset doesn't touch the display */
4962 if (!dev_priv->params.force_reset_modeset_test &&
4963 !gpu_reset_clobbers_display(dev_priv))
4966 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4967 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4968 smp_mb__after_atomic();
4969 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4971 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4972 drm_dbg_kms(&dev_priv->drm,
4973 "Modeset potentially stuck, unbreaking through wedging\n");
4974 intel_gt_set_wedged(&dev_priv->gt);
4978 * Need mode_config.mutex so that we don't
4979 * trample ongoing ->detect() and whatnot.
4981 mutex_lock(&dev->mode_config.mutex);
4982 drm_modeset_acquire_init(ctx, 0);
4984 ret = drm_modeset_lock_all_ctx(dev, ctx);
4985 if (ret != -EDEADLK)
4988 drm_modeset_backoff(ctx);
4991 * Disabling the crtcs gracefully seems nicer. Also the
4992 * g33 docs say we should at least disable all the planes.
4994 state = drm_atomic_helper_duplicate_state(dev, ctx);
4995 if (IS_ERR(state)) {
4996 ret = PTR_ERR(state);
4997 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
5002 ret = drm_atomic_helper_disable_all(dev, ctx);
5004 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
5006 drm_atomic_state_put(state);
5010 dev_priv->modeset_restore_state = state;
5011 state->acquire_ctx = ctx;
5014 void intel_finish_reset(struct drm_i915_private *dev_priv)
5016 struct drm_device *dev = &dev_priv->drm;
5017 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
5018 struct drm_atomic_state *state;
5021 /* reset doesn't touch the display */
5022 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
5025 state = fetch_and_zero(&dev_priv->modeset_restore_state);
5029 /* reset doesn't touch the display */
5030 if (!gpu_reset_clobbers_display(dev_priv)) {
5031 /* for testing only restore the display */
5032 ret = __intel_display_resume(dev, state, ctx);
5034 drm_err(&dev_priv->drm,
5035 "Restoring old state failed with %i\n", ret);
5038 * The display has been reset as well,
5039 * so need a full re-initialization.
5041 intel_pps_unlock_regs_wa(dev_priv);
5042 intel_modeset_init_hw(dev_priv);
5043 intel_init_clock_gating(dev_priv);
5045 spin_lock_irq(&dev_priv->irq_lock);
5046 if (dev_priv->display.hpd_irq_setup)
5047 dev_priv->display.hpd_irq_setup(dev_priv);
5048 spin_unlock_irq(&dev_priv->irq_lock);
5050 ret = __intel_display_resume(dev, state, ctx);
5052 drm_err(&dev_priv->drm,
5053 "Restoring old state failed with %i\n", ret);
5055 intel_hpd_init(dev_priv);
5058 drm_atomic_state_put(state);
5060 drm_modeset_drop_locks(ctx);
5061 drm_modeset_acquire_fini(ctx);
5062 mutex_unlock(&dev->mode_config.mutex);
5064 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
5067 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5069 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5070 enum pipe pipe = crtc->pipe;
5073 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
5076 * Display WA #1153: icl
5077 * enable hardware to bypass the alpha math
5078 * and rounding for per-pixel values 00 and 0xff
5080 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
5082 * Display WA # 1605353570: icl
5083 * Set the pixel rounding bit to 1 for allowing
5084 * passthrough of Frame buffer pixels unmodified
5087 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
5088 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
5091 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5093 struct drm_device *dev = crtc->base.dev;
5094 struct drm_i915_private *dev_priv = to_i915(dev);
5095 enum pipe pipe = crtc->pipe;
5099 /* enable normal train */
5100 reg = FDI_TX_CTL(pipe);
5101 temp = intel_de_read(dev_priv, reg);
5102 if (IS_IVYBRIDGE(dev_priv)) {
5103 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5104 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5106 temp &= ~FDI_LINK_TRAIN_NONE;
5107 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5109 intel_de_write(dev_priv, reg, temp);
5111 reg = FDI_RX_CTL(pipe);
5112 temp = intel_de_read(dev_priv, reg);
5113 if (HAS_PCH_CPT(dev_priv)) {
5114 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5115 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5117 temp &= ~FDI_LINK_TRAIN_NONE;
5118 temp |= FDI_LINK_TRAIN_NONE;
5120 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5122 /* wait one idle pattern time */
5123 intel_de_posting_read(dev_priv, reg);
5126 /* IVB wants error correction enabled */
5127 if (IS_IVYBRIDGE(dev_priv))
5128 intel_de_write(dev_priv, reg,
5129 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5132 /* The FDI link training functions for ILK/Ibexpeak. */
5133 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5134 const struct intel_crtc_state *crtc_state)
5136 struct drm_device *dev = crtc->base.dev;
5137 struct drm_i915_private *dev_priv = to_i915(dev);
5138 enum pipe pipe = crtc->pipe;
5142 /* FDI needs bits from pipe first */
5143 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5145 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5147 reg = FDI_RX_IMR(pipe);
5148 temp = intel_de_read(dev_priv, reg);
5149 temp &= ~FDI_RX_SYMBOL_LOCK;
5150 temp &= ~FDI_RX_BIT_LOCK;
5151 intel_de_write(dev_priv, reg, temp);
5152 intel_de_read(dev_priv, reg);
5155 /* enable CPU FDI TX and PCH FDI RX */
5156 reg = FDI_TX_CTL(pipe);
5157 temp = intel_de_read(dev_priv, reg);
5158 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5159 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5160 temp &= ~FDI_LINK_TRAIN_NONE;
5161 temp |= FDI_LINK_TRAIN_PATTERN_1;
5162 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5164 reg = FDI_RX_CTL(pipe);
5165 temp = intel_de_read(dev_priv, reg);
5166 temp &= ~FDI_LINK_TRAIN_NONE;
5167 temp |= FDI_LINK_TRAIN_PATTERN_1;
5168 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5170 intel_de_posting_read(dev_priv, reg);
5173 /* Ironlake workaround, enable clock pointer after FDI enable*/
5174 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5175 FDI_RX_PHASE_SYNC_POINTER_OVR);
5176 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5177 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5179 reg = FDI_RX_IIR(pipe);
5180 for (tries = 0; tries < 5; tries++) {
5181 temp = intel_de_read(dev_priv, reg);
5182 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5184 if ((temp & FDI_RX_BIT_LOCK)) {
5185 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5186 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5191 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5194 reg = FDI_TX_CTL(pipe);
5195 temp = intel_de_read(dev_priv, reg);
5196 temp &= ~FDI_LINK_TRAIN_NONE;
5197 temp |= FDI_LINK_TRAIN_PATTERN_2;
5198 intel_de_write(dev_priv, reg, temp);
5200 reg = FDI_RX_CTL(pipe);
5201 temp = intel_de_read(dev_priv, reg);
5202 temp &= ~FDI_LINK_TRAIN_NONE;
5203 temp |= FDI_LINK_TRAIN_PATTERN_2;
5204 intel_de_write(dev_priv, reg, temp);
5206 intel_de_posting_read(dev_priv, reg);
5209 reg = FDI_RX_IIR(pipe);
5210 for (tries = 0; tries < 5; tries++) {
5211 temp = intel_de_read(dev_priv, reg);
5212 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5214 if (temp & FDI_RX_SYMBOL_LOCK) {
5215 intel_de_write(dev_priv, reg,
5216 temp | FDI_RX_SYMBOL_LOCK);
5217 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5222 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5224 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5228 static const int snb_b_fdi_train_param[] = {
5229 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5230 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5231 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5232 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5235 /* The FDI link training functions for SNB/Cougarpoint. */
5236 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5237 const struct intel_crtc_state *crtc_state)
5239 struct drm_device *dev = crtc->base.dev;
5240 struct drm_i915_private *dev_priv = to_i915(dev);
5241 enum pipe pipe = crtc->pipe;
5245 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5247 reg = FDI_RX_IMR(pipe);
5248 temp = intel_de_read(dev_priv, reg);
5249 temp &= ~FDI_RX_SYMBOL_LOCK;
5250 temp &= ~FDI_RX_BIT_LOCK;
5251 intel_de_write(dev_priv, reg, temp);
5253 intel_de_posting_read(dev_priv, reg);
5256 /* enable CPU FDI TX and PCH FDI RX */
5257 reg = FDI_TX_CTL(pipe);
5258 temp = intel_de_read(dev_priv, reg);
5259 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5260 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5261 temp &= ~FDI_LINK_TRAIN_NONE;
5262 temp |= FDI_LINK_TRAIN_PATTERN_1;
5263 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5265 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5266 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5268 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5269 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5271 reg = FDI_RX_CTL(pipe);
5272 temp = intel_de_read(dev_priv, reg);
5273 if (HAS_PCH_CPT(dev_priv)) {
5274 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5275 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5277 temp &= ~FDI_LINK_TRAIN_NONE;
5278 temp |= FDI_LINK_TRAIN_PATTERN_1;
5280 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5282 intel_de_posting_read(dev_priv, reg);
5285 for (i = 0; i < 4; i++) {
5286 reg = FDI_TX_CTL(pipe);
5287 temp = intel_de_read(dev_priv, reg);
5288 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5289 temp |= snb_b_fdi_train_param[i];
5290 intel_de_write(dev_priv, reg, temp);
5292 intel_de_posting_read(dev_priv, reg);
5295 for (retry = 0; retry < 5; retry++) {
5296 reg = FDI_RX_IIR(pipe);
5297 temp = intel_de_read(dev_priv, reg);
5298 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5299 if (temp & FDI_RX_BIT_LOCK) {
5300 intel_de_write(dev_priv, reg,
5301 temp | FDI_RX_BIT_LOCK);
5302 drm_dbg_kms(&dev_priv->drm,
5303 "FDI train 1 done.\n");
5312 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5315 reg = FDI_TX_CTL(pipe);
5316 temp = intel_de_read(dev_priv, reg);
5317 temp &= ~FDI_LINK_TRAIN_NONE;
5318 temp |= FDI_LINK_TRAIN_PATTERN_2;
5319 if (IS_GEN(dev_priv, 6)) {
5320 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5322 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5324 intel_de_write(dev_priv, reg, temp);
5326 reg = FDI_RX_CTL(pipe);
5327 temp = intel_de_read(dev_priv, reg);
5328 if (HAS_PCH_CPT(dev_priv)) {
5329 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5330 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5332 temp &= ~FDI_LINK_TRAIN_NONE;
5333 temp |= FDI_LINK_TRAIN_PATTERN_2;
5335 intel_de_write(dev_priv, reg, temp);
5337 intel_de_posting_read(dev_priv, reg);
5340 for (i = 0; i < 4; i++) {
5341 reg = FDI_TX_CTL(pipe);
5342 temp = intel_de_read(dev_priv, reg);
5343 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5344 temp |= snb_b_fdi_train_param[i];
5345 intel_de_write(dev_priv, reg, temp);
5347 intel_de_posting_read(dev_priv, reg);
5350 for (retry = 0; retry < 5; retry++) {
5351 reg = FDI_RX_IIR(pipe);
5352 temp = intel_de_read(dev_priv, reg);
5353 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5354 if (temp & FDI_RX_SYMBOL_LOCK) {
5355 intel_de_write(dev_priv, reg,
5356 temp | FDI_RX_SYMBOL_LOCK);
5357 drm_dbg_kms(&dev_priv->drm,
5358 "FDI train 2 done.\n");
5367 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5369 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5372 /* Manual link training for Ivy Bridge A0 parts */
5373 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5374 const struct intel_crtc_state *crtc_state)
5376 struct drm_device *dev = crtc->base.dev;
5377 struct drm_i915_private *dev_priv = to_i915(dev);
5378 enum pipe pipe = crtc->pipe;
5382 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5384 reg = FDI_RX_IMR(pipe);
5385 temp = intel_de_read(dev_priv, reg);
5386 temp &= ~FDI_RX_SYMBOL_LOCK;
5387 temp &= ~FDI_RX_BIT_LOCK;
5388 intel_de_write(dev_priv, reg, temp);
5390 intel_de_posting_read(dev_priv, reg);
5393 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5394 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5396 /* Try each vswing and preemphasis setting twice before moving on */
5397 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5398 /* disable first in case we need to retry */
5399 reg = FDI_TX_CTL(pipe);
5400 temp = intel_de_read(dev_priv, reg);
5401 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5402 temp &= ~FDI_TX_ENABLE;
5403 intel_de_write(dev_priv, reg, temp);
5405 reg = FDI_RX_CTL(pipe);
5406 temp = intel_de_read(dev_priv, reg);
5407 temp &= ~FDI_LINK_TRAIN_AUTO;
5408 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5409 temp &= ~FDI_RX_ENABLE;
5410 intel_de_write(dev_priv, reg, temp);
5412 /* enable CPU FDI TX and PCH FDI RX */
5413 reg = FDI_TX_CTL(pipe);
5414 temp = intel_de_read(dev_priv, reg);
5415 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5416 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5417 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5418 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5419 temp |= snb_b_fdi_train_param[j/2];
5420 temp |= FDI_COMPOSITE_SYNC;
5421 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5423 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5424 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5426 reg = FDI_RX_CTL(pipe);
5427 temp = intel_de_read(dev_priv, reg);
5428 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5429 temp |= FDI_COMPOSITE_SYNC;
5430 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5432 intel_de_posting_read(dev_priv, reg);
5433 udelay(1); /* should be 0.5us */
5435 for (i = 0; i < 4; i++) {
5436 reg = FDI_RX_IIR(pipe);
5437 temp = intel_de_read(dev_priv, reg);
5438 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5440 if (temp & FDI_RX_BIT_LOCK ||
5441 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5442 intel_de_write(dev_priv, reg,
5443 temp | FDI_RX_BIT_LOCK);
5444 drm_dbg_kms(&dev_priv->drm,
5445 "FDI train 1 done, level %i.\n",
5449 udelay(1); /* should be 0.5us */
5452 drm_dbg_kms(&dev_priv->drm,
5453 "FDI train 1 fail on vswing %d\n", j / 2);
5458 reg = FDI_TX_CTL(pipe);
5459 temp = intel_de_read(dev_priv, reg);
5460 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5461 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5462 intel_de_write(dev_priv, reg, temp);
5464 reg = FDI_RX_CTL(pipe);
5465 temp = intel_de_read(dev_priv, reg);
5466 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5467 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5468 intel_de_write(dev_priv, reg, temp);
5470 intel_de_posting_read(dev_priv, reg);
5471 udelay(2); /* should be 1.5us */
5473 for (i = 0; i < 4; i++) {
5474 reg = FDI_RX_IIR(pipe);
5475 temp = intel_de_read(dev_priv, reg);
5476 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5478 if (temp & FDI_RX_SYMBOL_LOCK ||
5479 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5480 intel_de_write(dev_priv, reg,
5481 temp | FDI_RX_SYMBOL_LOCK);
5482 drm_dbg_kms(&dev_priv->drm,
5483 "FDI train 2 done, level %i.\n",
5487 udelay(2); /* should be 1.5us */
5490 drm_dbg_kms(&dev_priv->drm,
5491 "FDI train 2 fail on vswing %d\n", j / 2);
5495 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5498 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5501 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5502 enum pipe pipe = intel_crtc->pipe;
5506 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5507 reg = FDI_RX_CTL(pipe);
5508 temp = intel_de_read(dev_priv, reg);
5509 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5510 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5511 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5512 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5514 intel_de_posting_read(dev_priv, reg);
5517 /* Switch from Rawclk to PCDclk */
5518 temp = intel_de_read(dev_priv, reg);
5519 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5521 intel_de_posting_read(dev_priv, reg);
5524 /* Enable CPU FDI TX PLL, always on for Ironlake */
5525 reg = FDI_TX_CTL(pipe);
5526 temp = intel_de_read(dev_priv, reg);
5527 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5528 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5530 intel_de_posting_read(dev_priv, reg);
5535 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5537 struct drm_device *dev = intel_crtc->base.dev;
5538 struct drm_i915_private *dev_priv = to_i915(dev);
5539 enum pipe pipe = intel_crtc->pipe;
5543 /* Switch from PCDclk to Rawclk */
5544 reg = FDI_RX_CTL(pipe);
5545 temp = intel_de_read(dev_priv, reg);
5546 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5548 /* Disable CPU FDI TX PLL */
5549 reg = FDI_TX_CTL(pipe);
5550 temp = intel_de_read(dev_priv, reg);
5551 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5553 intel_de_posting_read(dev_priv, reg);
5556 reg = FDI_RX_CTL(pipe);
5557 temp = intel_de_read(dev_priv, reg);
5558 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5560 /* Wait for the clocks to turn off. */
5561 intel_de_posting_read(dev_priv, reg);
5565 static void ilk_fdi_disable(struct intel_crtc *crtc)
5567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5568 enum pipe pipe = crtc->pipe;
5572 /* disable CPU FDI tx and PCH FDI rx */
5573 reg = FDI_TX_CTL(pipe);
5574 temp = intel_de_read(dev_priv, reg);
5575 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5576 intel_de_posting_read(dev_priv, reg);
5578 reg = FDI_RX_CTL(pipe);
5579 temp = intel_de_read(dev_priv, reg);
5580 temp &= ~(0x7 << 16);
5581 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5582 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5584 intel_de_posting_read(dev_priv, reg);
5587 /* Ironlake workaround, disable clock pointer after downing FDI */
5588 if (HAS_PCH_IBX(dev_priv))
5589 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5590 FDI_RX_PHASE_SYNC_POINTER_OVR);
5592 /* still set train pattern 1 */
5593 reg = FDI_TX_CTL(pipe);
5594 temp = intel_de_read(dev_priv, reg);
5595 temp &= ~FDI_LINK_TRAIN_NONE;
5596 temp |= FDI_LINK_TRAIN_PATTERN_1;
5597 intel_de_write(dev_priv, reg, temp);
5599 reg = FDI_RX_CTL(pipe);
5600 temp = intel_de_read(dev_priv, reg);
5601 if (HAS_PCH_CPT(dev_priv)) {
5602 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5603 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5605 temp &= ~FDI_LINK_TRAIN_NONE;
5606 temp |= FDI_LINK_TRAIN_PATTERN_1;
5608 /* BPC in FDI rx is consistent with that in PIPECONF */
5609 temp &= ~(0x07 << 16);
5610 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5611 intel_de_write(dev_priv, reg, temp);
5613 intel_de_posting_read(dev_priv, reg);
5617 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5619 struct drm_crtc *crtc;
5622 drm_for_each_crtc(crtc, &dev_priv->drm) {
5623 struct drm_crtc_commit *commit;
5624 spin_lock(&crtc->commit_lock);
5625 commit = list_first_entry_or_null(&crtc->commit_list,
5626 struct drm_crtc_commit, commit_entry);
5627 cleanup_done = commit ?
5628 try_wait_for_completion(&commit->cleanup_done) : true;
5629 spin_unlock(&crtc->commit_lock);
5634 drm_crtc_wait_one_vblank(crtc);
5642 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5646 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5648 mutex_lock(&dev_priv->sb_lock);
5650 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5651 temp |= SBI_SSCCTL_DISABLE;
5652 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5654 mutex_unlock(&dev_priv->sb_lock);
5657 /* Program iCLKIP clock to the desired frequency */
5658 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5660 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5661 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5662 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5663 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5666 lpt_disable_iclkip(dev_priv);
5668 /* The iCLK virtual clock root frequency is in MHz,
5669 * but the adjusted_mode->crtc_clock in in KHz. To get the
5670 * divisors, it is necessary to divide one by another, so we
5671 * convert the virtual clock precision to KHz here for higher
5674 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5675 u32 iclk_virtual_root_freq = 172800 * 1000;
5676 u32 iclk_pi_range = 64;
5677 u32 desired_divisor;
5679 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5681 divsel = (desired_divisor / iclk_pi_range) - 2;
5682 phaseinc = desired_divisor % iclk_pi_range;
5685 * Near 20MHz is a corner case which is
5686 * out of range for the 7-bit divisor
5692 /* This should not happen with any sane values */
5693 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5694 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5695 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5696 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5698 drm_dbg_kms(&dev_priv->drm,
5699 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5700 clock, auxdiv, divsel, phasedir, phaseinc);
5702 mutex_lock(&dev_priv->sb_lock);
5704 /* Program SSCDIVINTPHASE6 */
5705 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5706 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5707 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5708 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5709 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5710 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5711 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5712 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5714 /* Program SSCAUXDIV */
5715 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5716 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5717 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5718 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5720 /* Enable modulator and associated divider */
5721 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5722 temp &= ~SBI_SSCCTL_DISABLE;
5723 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5725 mutex_unlock(&dev_priv->sb_lock);
5727 /* Wait for initialization time */
5730 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5733 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5735 u32 divsel, phaseinc, auxdiv;
5736 u32 iclk_virtual_root_freq = 172800 * 1000;
5737 u32 iclk_pi_range = 64;
5738 u32 desired_divisor;
5741 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5744 mutex_lock(&dev_priv->sb_lock);
5746 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5747 if (temp & SBI_SSCCTL_DISABLE) {
5748 mutex_unlock(&dev_priv->sb_lock);
5752 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5753 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5754 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5755 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5756 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5758 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5759 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5760 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5762 mutex_unlock(&dev_priv->sb_lock);
5764 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5766 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5767 desired_divisor << auxdiv);
5770 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5771 enum pipe pch_transcoder)
5773 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5774 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5775 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5777 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5778 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5779 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5780 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5781 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5782 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5784 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5785 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5786 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5787 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5788 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5789 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5790 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5791 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5794 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5798 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5799 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5802 drm_WARN_ON(&dev_priv->drm,
5803 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5805 drm_WARN_ON(&dev_priv->drm,
5806 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5809 temp &= ~FDI_BC_BIFURCATION_SELECT;
5811 temp |= FDI_BC_BIFURCATION_SELECT;
5813 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5814 enable ? "en" : "dis");
5815 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5816 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5819 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5821 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5824 switch (crtc->pipe) {
5828 if (crtc_state->fdi_lanes > 2)
5829 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5831 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5835 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5844 * Finds the encoder associated with the given CRTC. This can only be
5845 * used when we know that the CRTC isn't feeding multiple encoders!
5847 static struct intel_encoder *
5848 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5849 const struct intel_crtc_state *crtc_state)
5851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5852 const struct drm_connector_state *connector_state;
5853 const struct drm_connector *connector;
5854 struct intel_encoder *encoder = NULL;
5855 int num_encoders = 0;
5858 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5859 if (connector_state->crtc != &crtc->base)
5862 encoder = to_intel_encoder(connector_state->best_encoder);
5866 drm_WARN(encoder->base.dev, num_encoders != 1,
5867 "%d encoders for pipe %c\n",
5868 num_encoders, pipe_name(crtc->pipe));
5874 * Enable PCH resources required for PCH ports:
5876 * - FDI training & RX/TX
5877 * - update transcoder timings
5878 * - DP transcoding bits
5881 static void ilk_pch_enable(const struct intel_atomic_state *state,
5882 const struct intel_crtc_state *crtc_state)
5884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5885 struct drm_device *dev = crtc->base.dev;
5886 struct drm_i915_private *dev_priv = to_i915(dev);
5887 enum pipe pipe = crtc->pipe;
5890 assert_pch_transcoder_disabled(dev_priv, pipe);
5892 if (IS_IVYBRIDGE(dev_priv))
5893 ivb_update_fdi_bc_bifurcation(crtc_state);
5895 /* Write the TU size bits before fdi link training, so that error
5896 * detection works. */
5897 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5898 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5900 /* For PCH output, training FDI link */
5901 dev_priv->display.fdi_link_train(crtc, crtc_state);
5903 /* We need to program the right clock selection before writing the pixel
5904 * mutliplier into the DPLL. */
5905 if (HAS_PCH_CPT(dev_priv)) {
5908 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5909 temp |= TRANS_DPLL_ENABLE(pipe);
5910 sel = TRANS_DPLLB_SEL(pipe);
5911 if (crtc_state->shared_dpll ==
5912 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5916 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5919 /* XXX: pch pll's can be enabled any time before we enable the PCH
5920 * transcoder, and we actually should do this to not upset any PCH
5921 * transcoder that already use the clock when we share it.
5923 * Note that enable_shared_dpll tries to do the right thing, but
5924 * get_shared_dpll unconditionally resets the pll - we need that to have
5925 * the right LVDS enable sequence. */
5926 intel_enable_shared_dpll(crtc_state);
5928 /* set transcoder timing, panel must allow it */
5929 assert_panel_unlocked(dev_priv, pipe);
5930 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5932 intel_fdi_normal_train(crtc);
5934 /* For PCH DP, enable TRANS_DP_CTL */
5935 if (HAS_PCH_CPT(dev_priv) &&
5936 intel_crtc_has_dp_encoder(crtc_state)) {
5937 const struct drm_display_mode *adjusted_mode =
5938 &crtc_state->hw.adjusted_mode;
5939 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5940 i915_reg_t reg = TRANS_DP_CTL(pipe);
5943 temp = intel_de_read(dev_priv, reg);
5944 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5945 TRANS_DP_SYNC_MASK |
5947 temp |= TRANS_DP_OUTPUT_ENABLE;
5948 temp |= bpc << 9; /* same format but at 11:9 */
5950 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5951 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5952 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5953 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5955 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5956 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5957 temp |= TRANS_DP_PORT_SEL(port);
5959 intel_de_write(dev_priv, reg, temp);
5962 ilk_enable_pch_transcoder(crtc_state);
5965 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5967 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5968 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5969 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5971 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5973 lpt_program_iclkip(crtc_state);
5975 /* Set transcoder timing. */
5976 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5978 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5981 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5984 i915_reg_t dslreg = PIPEDSL(pipe);
5987 temp = intel_de_read(dev_priv, dslreg);
5989 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5990 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5991 drm_err(&dev_priv->drm,
5992 "mode set failed: pipe %c stuck\n",
5998 * The hardware phase 0.0 refers to the center of the pixel.
5999 * We want to start from the top/left edge which is phase
6000 * -0.5. That matches how the hardware calculates the scaling
6001 * factors (from top-left of the first pixel to bottom-right
6002 * of the last pixel, as opposed to the pixel centers).
6004 * For 4:2:0 subsampled chroma planes we obviously have to
6005 * adjust that so that the chroma sample position lands in
6008 * Note that for packed YCbCr 4:2:2 formats there is no way to
6009 * control chroma siting. The hardware simply replicates the
6010 * chroma samples for both of the luma samples, and thus we don't
6011 * actually get the expected MPEG2 chroma siting convention :(
6012 * The same behaviour is observed on pre-SKL platforms as well.
6014 * Theory behind the formula (note that we ignore sub-pixel
6015 * source coordinates):
6016 * s = source sample position
6017 * d = destination sample position
6022 * | | 1.5 (initial phase)
6030 * | -0.375 (initial phase)
6037 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
6039 int phase = -0x8000;
6043 phase += (sub - 1) * 0x8000 / sub;
6045 phase += scale / (2 * sub);
6048 * Hardware initial phase limited to [-0.5:1.5].
6049 * Since the max hardware scale factor is 3.0, we
6050 * should never actually excdeed 1.0 here.
6052 WARN_ON(phase < -0x8000 || phase > 0x18000);
6055 phase = 0x10000 + phase;
6057 trip = PS_PHASE_TRIP;
6059 return ((phase >> 2) & PS_PHASE_MASK) | trip;
6062 #define SKL_MIN_SRC_W 8
6063 #define SKL_MAX_SRC_W 4096
6064 #define SKL_MIN_SRC_H 8
6065 #define SKL_MAX_SRC_H 4096
6066 #define SKL_MIN_DST_W 8
6067 #define SKL_MAX_DST_W 4096
6068 #define SKL_MIN_DST_H 8
6069 #define SKL_MAX_DST_H 4096
6070 #define ICL_MAX_SRC_W 5120
6071 #define ICL_MAX_SRC_H 4096
6072 #define ICL_MAX_DST_W 5120
6073 #define ICL_MAX_DST_H 4096
6074 #define SKL_MIN_YUV_420_SRC_W 16
6075 #define SKL_MIN_YUV_420_SRC_H 16
6078 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6079 unsigned int scaler_user, int *scaler_id,
6080 int src_w, int src_h, int dst_w, int dst_h,
6081 const struct drm_format_info *format,
6082 u64 modifier, bool need_scaler)
6084 struct intel_crtc_scaler_state *scaler_state =
6085 &crtc_state->scaler_state;
6086 struct intel_crtc *intel_crtc =
6087 to_intel_crtc(crtc_state->uapi.crtc);
6088 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6089 const struct drm_display_mode *adjusted_mode =
6090 &crtc_state->hw.adjusted_mode;
6093 * Src coordinates are already rotated by 270 degrees for
6094 * the 90/270 degree plane rotation cases (to match the
6095 * GTT mapping), hence no need to account for rotation here.
6097 if (src_w != dst_w || src_h != dst_h)
6101 * Scaling/fitting not supported in IF-ID mode in GEN9+
6102 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6103 * Once NV12 is enabled, handle it here while allocating scaler
6106 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6107 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6108 drm_dbg_kms(&dev_priv->drm,
6109 "Pipe/Plane scaling not supported with IF-ID mode\n");
6114 * if plane is being disabled or scaler is no more required or force detach
6115 * - free scaler binded to this plane/crtc
6116 * - in order to do this, update crtc->scaler_usage
6118 * Here scaler state in crtc_state is set free so that
6119 * scaler can be assigned to other user. Actual register
6120 * update to free the scaler is done in plane/panel-fit programming.
6121 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6123 if (force_detach || !need_scaler) {
6124 if (*scaler_id >= 0) {
6125 scaler_state->scaler_users &= ~(1 << scaler_user);
6126 scaler_state->scalers[*scaler_id].in_use = 0;
6128 drm_dbg_kms(&dev_priv->drm,
6129 "scaler_user index %u.%u: "
6130 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6131 intel_crtc->pipe, scaler_user, *scaler_id,
6132 scaler_state->scaler_users);
6138 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6139 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6140 drm_dbg_kms(&dev_priv->drm,
6141 "Planar YUV: src dimensions not met\n");
6146 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6147 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6148 (INTEL_GEN(dev_priv) >= 11 &&
6149 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6150 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6151 (INTEL_GEN(dev_priv) < 11 &&
6152 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6153 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6154 drm_dbg_kms(&dev_priv->drm,
6155 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6156 "size is out of scaler range\n",
6157 intel_crtc->pipe, scaler_user, src_w, src_h,
6162 /* mark this plane as a scaler user in crtc_state */
6163 scaler_state->scaler_users |= (1 << scaler_user);
6164 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6165 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6166 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6167 scaler_state->scaler_users);
6172 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6174 const struct drm_display_mode *adjusted_mode =
6175 &crtc_state->hw.adjusted_mode;
6178 if (crtc_state->pch_pfit.enabled) {
6179 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6180 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6182 width = adjusted_mode->crtc_hdisplay;
6183 height = adjusted_mode->crtc_vdisplay;
6186 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6188 &crtc_state->scaler_state.scaler_id,
6189 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6190 width, height, NULL, 0,
6191 crtc_state->pch_pfit.enabled);
6195 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6196 * @crtc_state: crtc's scaler state
6197 * @plane_state: atomic plane state to update
6200 * 0 - scaler_usage updated successfully
6201 * error - requested scaling cannot be supported or other error condition
6203 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6204 struct intel_plane_state *plane_state)
6206 struct intel_plane *intel_plane =
6207 to_intel_plane(plane_state->uapi.plane);
6208 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6209 struct drm_framebuffer *fb = plane_state->hw.fb;
6211 bool force_detach = !fb || !plane_state->uapi.visible;
6212 bool need_scaler = false;
6214 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6215 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6216 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6219 ret = skl_update_scaler(crtc_state, force_detach,
6220 drm_plane_index(&intel_plane->base),
6221 &plane_state->scaler_id,
6222 drm_rect_width(&plane_state->uapi.src) >> 16,
6223 drm_rect_height(&plane_state->uapi.src) >> 16,
6224 drm_rect_width(&plane_state->uapi.dst),
6225 drm_rect_height(&plane_state->uapi.dst),
6226 fb ? fb->format : NULL,
6227 fb ? fb->modifier : 0,
6230 if (ret || plane_state->scaler_id < 0)
6233 /* check colorkey */
6234 if (plane_state->ckey.flags) {
6235 drm_dbg_kms(&dev_priv->drm,
6236 "[PLANE:%d:%s] scaling with color key not allowed",
6237 intel_plane->base.base.id,
6238 intel_plane->base.name);
6242 /* Check src format */
6243 switch (fb->format->format) {
6244 case DRM_FORMAT_RGB565:
6245 case DRM_FORMAT_XBGR8888:
6246 case DRM_FORMAT_XRGB8888:
6247 case DRM_FORMAT_ABGR8888:
6248 case DRM_FORMAT_ARGB8888:
6249 case DRM_FORMAT_XRGB2101010:
6250 case DRM_FORMAT_XBGR2101010:
6251 case DRM_FORMAT_ARGB2101010:
6252 case DRM_FORMAT_ABGR2101010:
6253 case DRM_FORMAT_YUYV:
6254 case DRM_FORMAT_YVYU:
6255 case DRM_FORMAT_UYVY:
6256 case DRM_FORMAT_VYUY:
6257 case DRM_FORMAT_NV12:
6258 case DRM_FORMAT_XYUV8888:
6259 case DRM_FORMAT_P010:
6260 case DRM_FORMAT_P012:
6261 case DRM_FORMAT_P016:
6262 case DRM_FORMAT_Y210:
6263 case DRM_FORMAT_Y212:
6264 case DRM_FORMAT_Y216:
6265 case DRM_FORMAT_XVYU2101010:
6266 case DRM_FORMAT_XVYU12_16161616:
6267 case DRM_FORMAT_XVYU16161616:
6269 case DRM_FORMAT_XBGR16161616F:
6270 case DRM_FORMAT_ABGR16161616F:
6271 case DRM_FORMAT_XRGB16161616F:
6272 case DRM_FORMAT_ARGB16161616F:
6273 if (INTEL_GEN(dev_priv) >= 11)
6277 drm_dbg_kms(&dev_priv->drm,
6278 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6279 intel_plane->base.base.id, intel_plane->base.name,
6280 fb->base.id, fb->format->format);
6287 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6289 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6292 for (i = 0; i < crtc->num_scalers; i++)
6293 skl_detach_scaler(crtc, i);
6296 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6300 const struct intel_crtc_scaler_state *scaler_state =
6301 &crtc_state->scaler_state;
6302 struct drm_rect src = {
6303 .x2 = crtc_state->pipe_src_w << 16,
6304 .y2 = crtc_state->pipe_src_h << 16,
6306 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6307 u16 uv_rgb_hphase, uv_rgb_vphase;
6308 enum pipe pipe = crtc->pipe;
6309 int width = drm_rect_width(dst);
6310 int height = drm_rect_height(dst);
6314 unsigned long irqflags;
6317 if (!crtc_state->pch_pfit.enabled)
6320 if (drm_WARN_ON(&dev_priv->drm,
6321 crtc_state->scaler_state.scaler_id < 0))
6324 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6325 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6327 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6328 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6330 id = scaler_state->scaler_id;
6332 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6334 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6335 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6336 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6337 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6338 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6339 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6340 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6342 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6343 width << 16 | height);
6345 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6348 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6351 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6352 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6353 enum pipe pipe = crtc->pipe;
6354 int width = drm_rect_width(dst);
6355 int height = drm_rect_height(dst);
6359 if (!crtc_state->pch_pfit.enabled)
6362 /* Force use of hard-coded filter coefficients
6363 * as some pre-programmed values are broken,
6366 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6367 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6368 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6370 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6372 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6373 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6376 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6378 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6379 struct drm_device *dev = crtc->base.dev;
6380 struct drm_i915_private *dev_priv = to_i915(dev);
6382 if (!crtc_state->ips_enabled)
6386 * We can only enable IPS after we enable a plane and wait for a vblank
6387 * This function is called from post_plane_update, which is run after
6390 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6392 if (IS_BROADWELL(dev_priv)) {
6393 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6394 IPS_ENABLE | IPS_PCODE_CONTROL));
6395 /* Quoting Art Runyan: "its not safe to expect any particular
6396 * value in IPS_CTL bit 31 after enabling IPS through the
6397 * mailbox." Moreover, the mailbox may return a bogus state,
6398 * so we need to just enable it and continue on.
6401 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6402 /* The bit only becomes 1 in the next vblank, so this wait here
6403 * is essentially intel_wait_for_vblank. If we don't have this
6404 * and don't wait for vblanks until the end of crtc_enable, then
6405 * the HW state readout code will complain that the expected
6406 * IPS_CTL value is not the one we read. */
6407 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6408 drm_err(&dev_priv->drm,
6409 "Timed out waiting for IPS enable\n");
6413 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6415 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6416 struct drm_device *dev = crtc->base.dev;
6417 struct drm_i915_private *dev_priv = to_i915(dev);
6419 if (!crtc_state->ips_enabled)
6422 if (IS_BROADWELL(dev_priv)) {
6424 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6426 * Wait for PCODE to finish disabling IPS. The BSpec specified
6427 * 42ms timeout value leads to occasional timeouts so use 100ms
6430 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6431 drm_err(&dev_priv->drm,
6432 "Timed out waiting for IPS disable\n");
6434 intel_de_write(dev_priv, IPS_CTL, 0);
6435 intel_de_posting_read(dev_priv, IPS_CTL);
6438 /* We need to wait for a vblank before we can disable the plane. */
6439 intel_wait_for_vblank(dev_priv, crtc->pipe);
6442 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6444 if (intel_crtc->overlay)
6445 (void) intel_overlay_switch_off(intel_crtc->overlay);
6447 /* Let userspace switch the overlay on again. In most cases userspace
6448 * has to recompute where to put it anyway.
6452 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6453 const struct intel_crtc_state *new_crtc_state)
6455 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6458 if (!old_crtc_state->ips_enabled)
6461 if (needs_modeset(new_crtc_state))
6465 * Workaround : Do not read or write the pipe palette/gamma data while
6466 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6468 * Disable IPS before we program the LUT.
6470 if (IS_HASWELL(dev_priv) &&
6471 (new_crtc_state->uapi.color_mgmt_changed ||
6472 new_crtc_state->update_pipe) &&
6473 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6476 return !new_crtc_state->ips_enabled;
6479 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6480 const struct intel_crtc_state *new_crtc_state)
6482 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6485 if (!new_crtc_state->ips_enabled)
6488 if (needs_modeset(new_crtc_state))
6492 * Workaround : Do not read or write the pipe palette/gamma data while
6493 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6495 * Re-enable IPS after the LUT has been programmed.
6497 if (IS_HASWELL(dev_priv) &&
6498 (new_crtc_state->uapi.color_mgmt_changed ||
6499 new_crtc_state->update_pipe) &&
6500 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6504 * We can't read out IPS on broadwell, assume the worst and
6505 * forcibly enable IPS on the first fastset.
6507 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6510 return !old_crtc_state->ips_enabled;
6513 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6515 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6517 if (!crtc_state->nv12_planes)
6520 /* WA Display #0827: Gen9:all */
6521 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6527 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6529 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6531 /* Wa_2006604312:icl,ehl */
6532 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6538 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6539 const struct intel_crtc_state *new_crtc_state)
6541 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6542 new_crtc_state->active_planes;
6545 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6546 const struct intel_crtc_state *new_crtc_state)
6548 return old_crtc_state->active_planes &&
6549 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6552 static void intel_post_plane_update(struct intel_atomic_state *state,
6553 struct intel_crtc *crtc)
6555 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6556 const struct intel_crtc_state *old_crtc_state =
6557 intel_atomic_get_old_crtc_state(state, crtc);
6558 const struct intel_crtc_state *new_crtc_state =
6559 intel_atomic_get_new_crtc_state(state, crtc);
6560 enum pipe pipe = crtc->pipe;
6562 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6564 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6565 intel_update_watermarks(crtc);
6567 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6568 hsw_enable_ips(new_crtc_state);
6570 intel_fbc_post_update(state, crtc);
6572 if (needs_nv12_wa(old_crtc_state) &&
6573 !needs_nv12_wa(new_crtc_state))
6574 skl_wa_827(dev_priv, pipe, false);
6576 if (needs_scalerclk_wa(old_crtc_state) &&
6577 !needs_scalerclk_wa(new_crtc_state))
6578 icl_wa_scalerclkgating(dev_priv, pipe, false);
6581 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
6582 struct intel_crtc *crtc,
6583 const struct intel_crtc_state *new_crtc_state)
6585 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6586 struct intel_plane *plane;
6587 struct intel_plane_state *new_plane_state;
6590 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
6591 u32 update_mask = new_crtc_state->update_planes;
6592 u32 plane_ctl, surf_addr;
6593 enum plane_id plane_id;
6594 unsigned long irqflags;
6597 if (crtc->pipe != plane->pipe ||
6598 !(update_mask & BIT(plane->id)))
6601 plane_id = plane->id;
6604 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6605 plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
6606 surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
6608 plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
6610 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
6611 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
6612 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6615 intel_wait_for_vblank(dev_priv, crtc->pipe);
6618 static void intel_pre_plane_update(struct intel_atomic_state *state,
6619 struct intel_crtc *crtc)
6621 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6622 const struct intel_crtc_state *old_crtc_state =
6623 intel_atomic_get_old_crtc_state(state, crtc);
6624 const struct intel_crtc_state *new_crtc_state =
6625 intel_atomic_get_new_crtc_state(state, crtc);
6626 enum pipe pipe = crtc->pipe;
6628 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6629 hsw_disable_ips(old_crtc_state);
6631 if (intel_fbc_pre_update(state, crtc))
6632 intel_wait_for_vblank(dev_priv, pipe);
6634 /* Display WA 827 */
6635 if (!needs_nv12_wa(old_crtc_state) &&
6636 needs_nv12_wa(new_crtc_state))
6637 skl_wa_827(dev_priv, pipe, true);
6639 /* Wa_2006604312:icl,ehl */
6640 if (!needs_scalerclk_wa(old_crtc_state) &&
6641 needs_scalerclk_wa(new_crtc_state))
6642 icl_wa_scalerclkgating(dev_priv, pipe, true);
6645 * Vblank time updates from the shadow to live plane control register
6646 * are blocked if the memory self-refresh mode is active at that
6647 * moment. So to make sure the plane gets truly disabled, disable
6648 * first the self-refresh mode. The self-refresh enable bit in turn
6649 * will be checked/applied by the HW only at the next frame start
6650 * event which is after the vblank start event, so we need to have a
6651 * wait-for-vblank between disabling the plane and the pipe.
6653 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6654 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6655 intel_wait_for_vblank(dev_priv, pipe);
6658 * IVB workaround: must disable low power watermarks for at least
6659 * one frame before enabling scaling. LP watermarks can be re-enabled
6660 * when scaling is disabled.
6662 * WaCxSRDisabledForSpriteScaling:ivb
6664 if (old_crtc_state->hw.active &&
6665 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6666 intel_wait_for_vblank(dev_priv, pipe);
6669 * If we're doing a modeset we don't need to do any
6670 * pre-vblank watermark programming here.
6672 if (!needs_modeset(new_crtc_state)) {
6674 * For platforms that support atomic watermarks, program the
6675 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6676 * will be the intermediate values that are safe for both pre- and
6677 * post- vblank; when vblank happens, the 'active' values will be set
6678 * to the final 'target' values and we'll do this again to get the
6679 * optimal watermarks. For gen9+ platforms, the values we program here
6680 * will be the final target values which will get automatically latched
6681 * at vblank time; no further programming will be necessary.
6683 * If a platform hasn't been transitioned to atomic watermarks yet,
6684 * we'll continue to update watermarks the old way, if flags tell
6687 if (dev_priv->display.initial_watermarks)
6688 dev_priv->display.initial_watermarks(state, crtc);
6689 else if (new_crtc_state->update_wm_pre)
6690 intel_update_watermarks(crtc);
6694 * Gen2 reports pipe underruns whenever all planes are disabled.
6695 * So disable underrun reporting before all the planes get disabled.
6697 * We do this after .initial_watermarks() so that we have a
6698 * chance of catching underruns with the intermediate watermarks
6699 * vs. the old plane configuration.
6701 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6702 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6705 * WA for platforms where async address update enable bit
6706 * is double buffered and only latched at start of vblank.
6708 if (old_crtc_state->uapi.async_flip &&
6709 !new_crtc_state->uapi.async_flip &&
6710 IS_GEN_RANGE(dev_priv, 9, 10))
6711 skl_disable_async_flip_wa(state, crtc, new_crtc_state);
6714 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6715 struct intel_crtc *crtc)
6717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6718 const struct intel_crtc_state *new_crtc_state =
6719 intel_atomic_get_new_crtc_state(state, crtc);
6720 unsigned int update_mask = new_crtc_state->update_planes;
6721 const struct intel_plane_state *old_plane_state;
6722 struct intel_plane *plane;
6723 unsigned fb_bits = 0;
6726 intel_crtc_dpms_overlay_disable(crtc);
6728 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6729 if (crtc->pipe != plane->pipe ||
6730 !(update_mask & BIT(plane->id)))
6733 intel_disable_plane(plane, new_crtc_state);
6735 if (old_plane_state->uapi.visible)
6736 fb_bits |= plane->frontbuffer_bit;
6739 intel_frontbuffer_flip(dev_priv, fb_bits);
6743 * intel_connector_primary_encoder - get the primary encoder for a connector
6744 * @connector: connector for which to return the encoder
6746 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6747 * all connectors to their encoder, except for DP-MST connectors which have
6748 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6749 * pointed to by as many DP-MST connectors as there are pipes.
6751 static struct intel_encoder *
6752 intel_connector_primary_encoder(struct intel_connector *connector)
6754 struct intel_encoder *encoder;
6756 if (connector->mst_port)
6757 return &dp_to_dig_port(connector->mst_port)->base;
6759 encoder = intel_attached_encoder(connector);
6760 drm_WARN_ON(connector->base.dev, !encoder);
6765 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6767 struct drm_connector_state *new_conn_state;
6768 struct drm_connector *connector;
6771 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6773 struct intel_connector *intel_connector;
6774 struct intel_encoder *encoder;
6775 struct intel_crtc *crtc;
6777 if (!intel_connector_needs_modeset(state, connector))
6780 intel_connector = to_intel_connector(connector);
6781 encoder = intel_connector_primary_encoder(intel_connector);
6782 if (!encoder->update_prepare)
6785 crtc = new_conn_state->crtc ?
6786 to_intel_crtc(new_conn_state->crtc) : NULL;
6787 encoder->update_prepare(state, encoder, crtc);
6791 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6793 struct drm_connector_state *new_conn_state;
6794 struct drm_connector *connector;
6797 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6799 struct intel_connector *intel_connector;
6800 struct intel_encoder *encoder;
6801 struct intel_crtc *crtc;
6803 if (!intel_connector_needs_modeset(state, connector))
6806 intel_connector = to_intel_connector(connector);
6807 encoder = intel_connector_primary_encoder(intel_connector);
6808 if (!encoder->update_complete)
6811 crtc = new_conn_state->crtc ?
6812 to_intel_crtc(new_conn_state->crtc) : NULL;
6813 encoder->update_complete(state, encoder, crtc);
6817 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6818 struct intel_crtc *crtc)
6820 const struct intel_crtc_state *crtc_state =
6821 intel_atomic_get_new_crtc_state(state, crtc);
6822 const struct drm_connector_state *conn_state;
6823 struct drm_connector *conn;
6826 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6827 struct intel_encoder *encoder =
6828 to_intel_encoder(conn_state->best_encoder);
6830 if (conn_state->crtc != &crtc->base)
6833 if (encoder->pre_pll_enable)
6834 encoder->pre_pll_enable(state, encoder,
6835 crtc_state, conn_state);
6839 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6840 struct intel_crtc *crtc)
6842 const struct intel_crtc_state *crtc_state =
6843 intel_atomic_get_new_crtc_state(state, crtc);
6844 const struct drm_connector_state *conn_state;
6845 struct drm_connector *conn;
6848 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6849 struct intel_encoder *encoder =
6850 to_intel_encoder(conn_state->best_encoder);
6852 if (conn_state->crtc != &crtc->base)
6855 if (encoder->pre_enable)
6856 encoder->pre_enable(state, encoder,
6857 crtc_state, conn_state);
6861 static void intel_encoders_enable(struct intel_atomic_state *state,
6862 struct intel_crtc *crtc)
6864 const struct intel_crtc_state *crtc_state =
6865 intel_atomic_get_new_crtc_state(state, crtc);
6866 const struct drm_connector_state *conn_state;
6867 struct drm_connector *conn;
6870 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6871 struct intel_encoder *encoder =
6872 to_intel_encoder(conn_state->best_encoder);
6874 if (conn_state->crtc != &crtc->base)
6877 if (encoder->enable)
6878 encoder->enable(state, encoder,
6879 crtc_state, conn_state);
6880 intel_opregion_notify_encoder(encoder, true);
6884 static void intel_encoders_disable(struct intel_atomic_state *state,
6885 struct intel_crtc *crtc)
6887 const struct intel_crtc_state *old_crtc_state =
6888 intel_atomic_get_old_crtc_state(state, crtc);
6889 const struct drm_connector_state *old_conn_state;
6890 struct drm_connector *conn;
6893 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6894 struct intel_encoder *encoder =
6895 to_intel_encoder(old_conn_state->best_encoder);
6897 if (old_conn_state->crtc != &crtc->base)
6900 intel_opregion_notify_encoder(encoder, false);
6901 if (encoder->disable)
6902 encoder->disable(state, encoder,
6903 old_crtc_state, old_conn_state);
6907 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6908 struct intel_crtc *crtc)
6910 const struct intel_crtc_state *old_crtc_state =
6911 intel_atomic_get_old_crtc_state(state, crtc);
6912 const struct drm_connector_state *old_conn_state;
6913 struct drm_connector *conn;
6916 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6917 struct intel_encoder *encoder =
6918 to_intel_encoder(old_conn_state->best_encoder);
6920 if (old_conn_state->crtc != &crtc->base)
6923 if (encoder->post_disable)
6924 encoder->post_disable(state, encoder,
6925 old_crtc_state, old_conn_state);
6929 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6930 struct intel_crtc *crtc)
6932 const struct intel_crtc_state *old_crtc_state =
6933 intel_atomic_get_old_crtc_state(state, crtc);
6934 const struct drm_connector_state *old_conn_state;
6935 struct drm_connector *conn;
6938 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6939 struct intel_encoder *encoder =
6940 to_intel_encoder(old_conn_state->best_encoder);
6942 if (old_conn_state->crtc != &crtc->base)
6945 if (encoder->post_pll_disable)
6946 encoder->post_pll_disable(state, encoder,
6947 old_crtc_state, old_conn_state);
6951 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6952 struct intel_crtc *crtc)
6954 const struct intel_crtc_state *crtc_state =
6955 intel_atomic_get_new_crtc_state(state, crtc);
6956 const struct drm_connector_state *conn_state;
6957 struct drm_connector *conn;
6960 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6961 struct intel_encoder *encoder =
6962 to_intel_encoder(conn_state->best_encoder);
6964 if (conn_state->crtc != &crtc->base)
6967 if (encoder->update_pipe)
6968 encoder->update_pipe(state, encoder,
6969 crtc_state, conn_state);
6973 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6976 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6978 plane->disable_plane(plane, crtc_state);
6981 static void ilk_crtc_enable(struct intel_atomic_state *state,
6982 struct intel_crtc *crtc)
6984 const struct intel_crtc_state *new_crtc_state =
6985 intel_atomic_get_new_crtc_state(state, crtc);
6986 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6987 enum pipe pipe = crtc->pipe;
6989 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6993 * Sometimes spurious CPU pipe underruns happen during FDI
6994 * training, at least with VGA+HDMI cloning. Suppress them.
6996 * On ILK we get an occasional spurious CPU pipe underruns
6997 * between eDP port A enable and vdd enable. Also PCH port
6998 * enable seems to result in the occasional CPU pipe underrun.
7000 * Spurious PCH underruns also occur during PCH enabling.
7002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7003 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7005 if (new_crtc_state->has_pch_encoder)
7006 intel_prepare_shared_dpll(new_crtc_state);
7008 if (intel_crtc_has_dp_encoder(new_crtc_state))
7009 intel_dp_set_m_n(new_crtc_state, M1_N1);
7011 intel_set_pipe_timings(new_crtc_state);
7012 intel_set_pipe_src_size(new_crtc_state);
7014 if (new_crtc_state->has_pch_encoder)
7015 intel_cpu_transcoder_set_m_n(new_crtc_state,
7016 &new_crtc_state->fdi_m_n, NULL);
7018 ilk_set_pipeconf(new_crtc_state);
7020 crtc->active = true;
7022 intel_encoders_pre_enable(state, crtc);
7024 if (new_crtc_state->has_pch_encoder) {
7025 /* Note: FDI PLL enabling _must_ be done before we enable the
7026 * cpu pipes, hence this is separate from all the other fdi/pch
7028 ilk_fdi_pll_enable(new_crtc_state);
7030 assert_fdi_tx_disabled(dev_priv, pipe);
7031 assert_fdi_rx_disabled(dev_priv, pipe);
7034 ilk_pfit_enable(new_crtc_state);
7037 * On ILK+ LUT must be loaded before the pipe is running but with
7040 intel_color_load_luts(new_crtc_state);
7041 intel_color_commit(new_crtc_state);
7042 /* update DSPCNTR to configure gamma for pipe bottom color */
7043 intel_disable_primary_plane(new_crtc_state);
7045 if (dev_priv->display.initial_watermarks)
7046 dev_priv->display.initial_watermarks(state, crtc);
7047 intel_enable_pipe(new_crtc_state);
7049 if (new_crtc_state->has_pch_encoder)
7050 ilk_pch_enable(state, new_crtc_state);
7052 intel_crtc_vblank_on(new_crtc_state);
7054 intel_encoders_enable(state, crtc);
7056 if (HAS_PCH_CPT(dev_priv))
7057 cpt_verify_modeset(dev_priv, pipe);
7060 * Must wait for vblank to avoid spurious PCH FIFO underruns.
7061 * And a second vblank wait is needed at least on ILK with
7062 * some interlaced HDMI modes. Let's do the double wait always
7063 * in case there are more corner cases we don't know about.
7065 if (new_crtc_state->has_pch_encoder) {
7066 intel_wait_for_vblank(dev_priv, pipe);
7067 intel_wait_for_vblank(dev_priv, pipe);
7069 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7070 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7073 /* IPS only exists on ULT machines and is tied to pipe A. */
7074 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7076 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7079 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7080 enum pipe pipe, bool apply)
7082 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7083 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7090 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7093 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7096 enum pipe pipe = crtc->pipe;
7099 val = MBUS_DBOX_A_CREDIT(2);
7101 if (INTEL_GEN(dev_priv) >= 12) {
7102 val |= MBUS_DBOX_BW_CREDIT(2);
7103 val |= MBUS_DBOX_B_CREDIT(12);
7105 val |= MBUS_DBOX_BW_CREDIT(1);
7106 val |= MBUS_DBOX_B_CREDIT(8);
7109 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7112 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7115 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7117 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7118 HSW_LINETIME(crtc_state->linetime) |
7119 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7122 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7126 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7129 val = intel_de_read(dev_priv, reg);
7130 val &= ~HSW_FRAME_START_DELAY_MASK;
7131 val |= HSW_FRAME_START_DELAY(0);
7132 intel_de_write(dev_priv, reg, val);
7135 static void hsw_crtc_enable(struct intel_atomic_state *state,
7136 struct intel_crtc *crtc)
7138 const struct intel_crtc_state *new_crtc_state =
7139 intel_atomic_get_new_crtc_state(state, crtc);
7140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7141 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7142 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7143 bool psl_clkgate_wa;
7145 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7148 intel_encoders_pre_pll_enable(state, crtc);
7150 if (new_crtc_state->shared_dpll)
7151 intel_enable_shared_dpll(new_crtc_state);
7153 intel_encoders_pre_enable(state, crtc);
7155 if (!transcoder_is_dsi(cpu_transcoder))
7156 intel_set_pipe_timings(new_crtc_state);
7158 intel_set_pipe_src_size(new_crtc_state);
7160 if (cpu_transcoder != TRANSCODER_EDP &&
7161 !transcoder_is_dsi(cpu_transcoder))
7162 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7163 new_crtc_state->pixel_multiplier - 1);
7165 if (new_crtc_state->has_pch_encoder)
7166 intel_cpu_transcoder_set_m_n(new_crtc_state,
7167 &new_crtc_state->fdi_m_n, NULL);
7169 if (!transcoder_is_dsi(cpu_transcoder)) {
7170 hsw_set_frame_start_delay(new_crtc_state);
7171 hsw_set_pipeconf(new_crtc_state);
7174 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7175 bdw_set_pipemisc(new_crtc_state);
7177 crtc->active = true;
7179 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7180 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7181 new_crtc_state->pch_pfit.enabled;
7183 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7185 if (INTEL_GEN(dev_priv) >= 9)
7186 skl_pfit_enable(new_crtc_state);
7188 ilk_pfit_enable(new_crtc_state);
7191 * On ILK+ LUT must be loaded before the pipe is running but with
7194 intel_color_load_luts(new_crtc_state);
7195 intel_color_commit(new_crtc_state);
7196 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7197 if (INTEL_GEN(dev_priv) < 9)
7198 intel_disable_primary_plane(new_crtc_state);
7200 hsw_set_linetime_wm(new_crtc_state);
7202 if (INTEL_GEN(dev_priv) >= 11)
7203 icl_set_pipe_chicken(crtc);
7205 if (dev_priv->display.initial_watermarks)
7206 dev_priv->display.initial_watermarks(state, crtc);
7208 if (INTEL_GEN(dev_priv) >= 11)
7209 icl_pipe_mbus_enable(crtc);
7211 intel_encoders_enable(state, crtc);
7213 if (psl_clkgate_wa) {
7214 intel_wait_for_vblank(dev_priv, pipe);
7215 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7218 /* If we change the relative order between pipe/planes enabling, we need
7219 * to change the workaround. */
7220 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7221 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7222 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7223 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7227 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7229 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7230 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7231 enum pipe pipe = crtc->pipe;
7233 /* To avoid upsetting the power well on haswell only disable the pfit if
7234 * it's in use. The hw state code will make sure we get this right. */
7235 if (!old_crtc_state->pch_pfit.enabled)
7238 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7239 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7240 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7243 static void ilk_crtc_disable(struct intel_atomic_state *state,
7244 struct intel_crtc *crtc)
7246 const struct intel_crtc_state *old_crtc_state =
7247 intel_atomic_get_old_crtc_state(state, crtc);
7248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7249 enum pipe pipe = crtc->pipe;
7252 * Sometimes spurious CPU pipe underruns happen when the
7253 * pipe is already disabled, but FDI RX/TX is still enabled.
7254 * Happens at least with VGA+HDMI cloning. Suppress them.
7256 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7257 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7259 intel_encoders_disable(state, crtc);
7261 intel_crtc_vblank_off(old_crtc_state);
7263 intel_disable_pipe(old_crtc_state);
7265 ilk_pfit_disable(old_crtc_state);
7267 if (old_crtc_state->has_pch_encoder)
7268 ilk_fdi_disable(crtc);
7270 intel_encoders_post_disable(state, crtc);
7272 if (old_crtc_state->has_pch_encoder) {
7273 ilk_disable_pch_transcoder(dev_priv, pipe);
7275 if (HAS_PCH_CPT(dev_priv)) {
7279 /* disable TRANS_DP_CTL */
7280 reg = TRANS_DP_CTL(pipe);
7281 temp = intel_de_read(dev_priv, reg);
7282 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7283 TRANS_DP_PORT_SEL_MASK);
7284 temp |= TRANS_DP_PORT_SEL_NONE;
7285 intel_de_write(dev_priv, reg, temp);
7287 /* disable DPLL_SEL */
7288 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7289 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7290 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7293 ilk_fdi_pll_disable(crtc);
7296 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7297 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7300 static void hsw_crtc_disable(struct intel_atomic_state *state,
7301 struct intel_crtc *crtc)
7304 * FIXME collapse everything to one hook.
7305 * Need care with mst->ddi interactions.
7307 intel_encoders_disable(state, crtc);
7308 intel_encoders_post_disable(state, crtc);
7311 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7316 if (!crtc_state->gmch_pfit.control)
7320 * The panel fitter should only be adjusted whilst the pipe is disabled,
7321 * according to register description and PRM.
7323 drm_WARN_ON(&dev_priv->drm,
7324 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7325 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7327 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7328 crtc_state->gmch_pfit.pgm_ratios);
7329 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7331 /* Border color in case we don't scale up to the full screen. Black by
7332 * default, change to something else for debugging. */
7333 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7336 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7338 if (phy == PHY_NONE)
7340 else if (IS_ROCKETLAKE(dev_priv))
7341 return phy <= PHY_D;
7342 else if (IS_JSL_EHL(dev_priv))
7343 return phy <= PHY_C;
7344 else if (INTEL_GEN(dev_priv) >= 11)
7345 return phy <= PHY_B;
7350 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7352 if (IS_ROCKETLAKE(dev_priv))
7354 else if (INTEL_GEN(dev_priv) >= 12)
7355 return phy >= PHY_D && phy <= PHY_I;
7356 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
7357 return phy >= PHY_C && phy <= PHY_F;
7362 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7364 if (IS_ROCKETLAKE(i915) && port >= PORT_D)
7365 return (enum phy)port - 1;
7366 else if (IS_JSL_EHL(i915) && port == PORT_D)
7369 return (enum phy)port;
7372 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7374 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7375 return PORT_TC_NONE;
7377 if (INTEL_GEN(dev_priv) >= 12)
7378 return port - PORT_D;
7380 return port - PORT_C;
7383 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7387 return POWER_DOMAIN_PORT_DDI_A_LANES;
7389 return POWER_DOMAIN_PORT_DDI_B_LANES;
7391 return POWER_DOMAIN_PORT_DDI_C_LANES;
7393 return POWER_DOMAIN_PORT_DDI_D_LANES;
7395 return POWER_DOMAIN_PORT_DDI_E_LANES;
7397 return POWER_DOMAIN_PORT_DDI_F_LANES;
7399 return POWER_DOMAIN_PORT_DDI_G_LANES;
7401 return POWER_DOMAIN_PORT_DDI_H_LANES;
7403 return POWER_DOMAIN_PORT_DDI_I_LANES;
7406 return POWER_DOMAIN_PORT_OTHER;
7410 enum intel_display_power_domain
7411 intel_aux_power_domain(struct intel_digital_port *dig_port)
7413 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7414 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7416 if (intel_phy_is_tc(dev_priv, phy) &&
7417 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7418 switch (dig_port->aux_ch) {
7420 return POWER_DOMAIN_AUX_C_TBT;
7422 return POWER_DOMAIN_AUX_D_TBT;
7424 return POWER_DOMAIN_AUX_E_TBT;
7426 return POWER_DOMAIN_AUX_F_TBT;
7428 return POWER_DOMAIN_AUX_G_TBT;
7430 return POWER_DOMAIN_AUX_H_TBT;
7432 return POWER_DOMAIN_AUX_I_TBT;
7434 MISSING_CASE(dig_port->aux_ch);
7435 return POWER_DOMAIN_AUX_C_TBT;
7439 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7443 * Converts aux_ch to power_domain without caring about TBT ports for that use
7444 * intel_aux_power_domain()
7446 enum intel_display_power_domain
7447 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7451 return POWER_DOMAIN_AUX_A;
7453 return POWER_DOMAIN_AUX_B;
7455 return POWER_DOMAIN_AUX_C;
7457 return POWER_DOMAIN_AUX_D;
7459 return POWER_DOMAIN_AUX_E;
7461 return POWER_DOMAIN_AUX_F;
7463 return POWER_DOMAIN_AUX_G;
7465 return POWER_DOMAIN_AUX_H;
7467 return POWER_DOMAIN_AUX_I;
7469 MISSING_CASE(aux_ch);
7470 return POWER_DOMAIN_AUX_A;
7474 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7476 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7478 struct drm_encoder *encoder;
7479 enum pipe pipe = crtc->pipe;
7481 enum transcoder transcoder = crtc_state->cpu_transcoder;
7483 if (!crtc_state->hw.active)
7486 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7487 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7488 if (crtc_state->pch_pfit.enabled ||
7489 crtc_state->pch_pfit.force_thru)
7490 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7492 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7493 crtc_state->uapi.encoder_mask) {
7494 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7496 mask |= BIT_ULL(intel_encoder->power_domain);
7499 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7500 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7502 if (crtc_state->shared_dpll)
7503 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7509 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7511 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7512 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7513 enum intel_display_power_domain domain;
7514 u64 domains, new_domains, old_domains;
7516 old_domains = crtc->enabled_power_domains;
7517 crtc->enabled_power_domains = new_domains =
7518 get_crtc_power_domains(crtc_state);
7520 domains = new_domains & ~old_domains;
7522 for_each_power_domain(domain, domains)
7523 intel_display_power_get(dev_priv, domain);
7525 return old_domains & ~new_domains;
7528 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7531 enum intel_display_power_domain domain;
7533 for_each_power_domain(domain, domains)
7534 intel_display_power_put_unchecked(dev_priv, domain);
7537 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7538 struct intel_crtc *crtc)
7540 const struct intel_crtc_state *new_crtc_state =
7541 intel_atomic_get_new_crtc_state(state, crtc);
7542 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7543 enum pipe pipe = crtc->pipe;
7545 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7548 if (intel_crtc_has_dp_encoder(new_crtc_state))
7549 intel_dp_set_m_n(new_crtc_state, M1_N1);
7551 intel_set_pipe_timings(new_crtc_state);
7552 intel_set_pipe_src_size(new_crtc_state);
7554 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7555 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7556 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7559 i9xx_set_pipeconf(new_crtc_state);
7561 crtc->active = true;
7563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7565 intel_encoders_pre_pll_enable(state, crtc);
7567 if (IS_CHERRYVIEW(dev_priv)) {
7568 chv_prepare_pll(crtc, new_crtc_state);
7569 chv_enable_pll(crtc, new_crtc_state);
7571 vlv_prepare_pll(crtc, new_crtc_state);
7572 vlv_enable_pll(crtc, new_crtc_state);
7575 intel_encoders_pre_enable(state, crtc);
7577 i9xx_pfit_enable(new_crtc_state);
7579 intel_color_load_luts(new_crtc_state);
7580 intel_color_commit(new_crtc_state);
7581 /* update DSPCNTR to configure gamma for pipe bottom color */
7582 intel_disable_primary_plane(new_crtc_state);
7584 dev_priv->display.initial_watermarks(state, crtc);
7585 intel_enable_pipe(new_crtc_state);
7587 intel_crtc_vblank_on(new_crtc_state);
7589 intel_encoders_enable(state, crtc);
7592 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7594 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7597 intel_de_write(dev_priv, FP0(crtc->pipe),
7598 crtc_state->dpll_hw_state.fp0);
7599 intel_de_write(dev_priv, FP1(crtc->pipe),
7600 crtc_state->dpll_hw_state.fp1);
7603 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7604 struct intel_crtc *crtc)
7606 const struct intel_crtc_state *new_crtc_state =
7607 intel_atomic_get_new_crtc_state(state, crtc);
7608 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7609 enum pipe pipe = crtc->pipe;
7611 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7614 i9xx_set_pll_dividers(new_crtc_state);
7616 if (intel_crtc_has_dp_encoder(new_crtc_state))
7617 intel_dp_set_m_n(new_crtc_state, M1_N1);
7619 intel_set_pipe_timings(new_crtc_state);
7620 intel_set_pipe_src_size(new_crtc_state);
7622 i9xx_set_pipeconf(new_crtc_state);
7624 crtc->active = true;
7626 if (!IS_GEN(dev_priv, 2))
7627 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7629 intel_encoders_pre_enable(state, crtc);
7631 i9xx_enable_pll(crtc, new_crtc_state);
7633 i9xx_pfit_enable(new_crtc_state);
7635 intel_color_load_luts(new_crtc_state);
7636 intel_color_commit(new_crtc_state);
7637 /* update DSPCNTR to configure gamma for pipe bottom color */
7638 intel_disable_primary_plane(new_crtc_state);
7640 if (dev_priv->display.initial_watermarks)
7641 dev_priv->display.initial_watermarks(state, crtc);
7643 intel_update_watermarks(crtc);
7644 intel_enable_pipe(new_crtc_state);
7646 intel_crtc_vblank_on(new_crtc_state);
7648 intel_encoders_enable(state, crtc);
7650 /* prevents spurious underruns */
7651 if (IS_GEN(dev_priv, 2))
7652 intel_wait_for_vblank(dev_priv, pipe);
7655 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7657 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7658 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7660 if (!old_crtc_state->gmch_pfit.control)
7663 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7665 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7666 intel_de_read(dev_priv, PFIT_CONTROL));
7667 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7670 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7671 struct intel_crtc *crtc)
7673 struct intel_crtc_state *old_crtc_state =
7674 intel_atomic_get_old_crtc_state(state, crtc);
7675 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7676 enum pipe pipe = crtc->pipe;
7679 * On gen2 planes are double buffered but the pipe isn't, so we must
7680 * wait for planes to fully turn off before disabling the pipe.
7682 if (IS_GEN(dev_priv, 2))
7683 intel_wait_for_vblank(dev_priv, pipe);
7685 intel_encoders_disable(state, crtc);
7687 intel_crtc_vblank_off(old_crtc_state);
7689 intel_disable_pipe(old_crtc_state);
7691 i9xx_pfit_disable(old_crtc_state);
7693 intel_encoders_post_disable(state, crtc);
7695 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7696 if (IS_CHERRYVIEW(dev_priv))
7697 chv_disable_pll(dev_priv, pipe);
7698 else if (IS_VALLEYVIEW(dev_priv))
7699 vlv_disable_pll(dev_priv, pipe);
7701 i9xx_disable_pll(old_crtc_state);
7704 intel_encoders_post_pll_disable(state, crtc);
7706 if (!IS_GEN(dev_priv, 2))
7707 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7709 if (!dev_priv->display.initial_watermarks)
7710 intel_update_watermarks(crtc);
7712 /* clock the pipe down to 640x480@60 to potentially save power */
7713 if (IS_I830(dev_priv))
7714 i830_enable_pipe(dev_priv, pipe);
7717 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7718 struct drm_modeset_acquire_ctx *ctx)
7720 struct intel_encoder *encoder;
7721 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7722 struct intel_bw_state *bw_state =
7723 to_intel_bw_state(dev_priv->bw_obj.state);
7724 struct intel_cdclk_state *cdclk_state =
7725 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7726 struct intel_dbuf_state *dbuf_state =
7727 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7728 struct intel_crtc_state *crtc_state =
7729 to_intel_crtc_state(crtc->base.state);
7730 enum intel_display_power_domain domain;
7731 struct intel_plane *plane;
7732 struct drm_atomic_state *state;
7733 struct intel_crtc_state *temp_crtc_state;
7734 enum pipe pipe = crtc->pipe;
7738 if (!crtc_state->hw.active)
7741 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7742 const struct intel_plane_state *plane_state =
7743 to_intel_plane_state(plane->base.state);
7745 if (plane_state->uapi.visible)
7746 intel_plane_disable_noatomic(crtc, plane);
7749 state = drm_atomic_state_alloc(&dev_priv->drm);
7751 drm_dbg_kms(&dev_priv->drm,
7752 "failed to disable [CRTC:%d:%s], out of memory",
7753 crtc->base.base.id, crtc->base.name);
7757 state->acquire_ctx = ctx;
7759 /* Everything's already locked, -EDEADLK can't happen. */
7760 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7761 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7763 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7765 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7767 drm_atomic_state_put(state);
7769 drm_dbg_kms(&dev_priv->drm,
7770 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7771 crtc->base.base.id, crtc->base.name);
7773 crtc->active = false;
7774 crtc->base.enabled = false;
7776 drm_WARN_ON(&dev_priv->drm,
7777 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7778 crtc_state->uapi.active = false;
7779 crtc_state->uapi.connector_mask = 0;
7780 crtc_state->uapi.encoder_mask = 0;
7781 intel_crtc_free_hw_state(crtc_state);
7782 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7784 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7785 encoder->base.crtc = NULL;
7787 intel_fbc_disable(crtc);
7788 intel_update_watermarks(crtc);
7789 intel_disable_shared_dpll(crtc_state);
7791 domains = crtc->enabled_power_domains;
7792 for_each_power_domain(domain, domains)
7793 intel_display_power_put_unchecked(dev_priv, domain);
7794 crtc->enabled_power_domains = 0;
7796 dev_priv->active_pipes &= ~BIT(pipe);
7797 cdclk_state->min_cdclk[pipe] = 0;
7798 cdclk_state->min_voltage_level[pipe] = 0;
7799 cdclk_state->active_pipes &= ~BIT(pipe);
7801 dbuf_state->active_pipes &= ~BIT(pipe);
7803 bw_state->data_rate[pipe] = 0;
7804 bw_state->num_active_planes[pipe] = 0;
7808 * turn all crtc's off, but do not adjust state
7809 * This has to be paired with a call to intel_modeset_setup_hw_state.
7811 int intel_display_suspend(struct drm_device *dev)
7813 struct drm_i915_private *dev_priv = to_i915(dev);
7814 struct drm_atomic_state *state;
7817 state = drm_atomic_helper_suspend(dev);
7818 ret = PTR_ERR_OR_ZERO(state);
7820 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7823 dev_priv->modeset_restore_state = state;
7827 void intel_encoder_destroy(struct drm_encoder *encoder)
7829 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7831 drm_encoder_cleanup(encoder);
7832 kfree(intel_encoder);
7835 /* Cross check the actual hw state with our own modeset state tracking (and it's
7836 * internal consistency). */
7837 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7838 struct drm_connector_state *conn_state)
7840 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7841 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7843 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7844 connector->base.base.id, connector->base.name);
7846 if (connector->get_hw_state(connector)) {
7847 struct intel_encoder *encoder = intel_attached_encoder(connector);
7849 I915_STATE_WARN(!crtc_state,
7850 "connector enabled without attached crtc\n");
7855 I915_STATE_WARN(!crtc_state->hw.active,
7856 "connector is active, but attached crtc isn't\n");
7858 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7861 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7862 "atomic encoder doesn't match attached encoder\n");
7864 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7865 "attached encoder crtc differs from connector crtc\n");
7867 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7868 "attached crtc is active, but connector isn't\n");
7869 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7870 "best encoder set without crtc!\n");
7874 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7876 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7877 return crtc_state->fdi_lanes;
7882 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7883 struct intel_crtc_state *pipe_config)
7885 struct drm_i915_private *dev_priv = to_i915(dev);
7886 struct drm_atomic_state *state = pipe_config->uapi.state;
7887 struct intel_crtc *other_crtc;
7888 struct intel_crtc_state *other_crtc_state;
7890 drm_dbg_kms(&dev_priv->drm,
7891 "checking fdi config on pipe %c, lanes %i\n",
7892 pipe_name(pipe), pipe_config->fdi_lanes);
7893 if (pipe_config->fdi_lanes > 4) {
7894 drm_dbg_kms(&dev_priv->drm,
7895 "invalid fdi lane config on pipe %c: %i lanes\n",
7896 pipe_name(pipe), pipe_config->fdi_lanes);
7900 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7901 if (pipe_config->fdi_lanes > 2) {
7902 drm_dbg_kms(&dev_priv->drm,
7903 "only 2 lanes on haswell, required: %i lanes\n",
7904 pipe_config->fdi_lanes);
7911 if (INTEL_NUM_PIPES(dev_priv) == 2)
7914 /* Ivybridge 3 pipe is really complicated */
7919 if (pipe_config->fdi_lanes <= 2)
7922 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7924 intel_atomic_get_crtc_state(state, other_crtc);
7925 if (IS_ERR(other_crtc_state))
7926 return PTR_ERR(other_crtc_state);
7928 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7929 drm_dbg_kms(&dev_priv->drm,
7930 "invalid shared fdi lane config on pipe %c: %i lanes\n",
7931 pipe_name(pipe), pipe_config->fdi_lanes);
7936 if (pipe_config->fdi_lanes > 2) {
7937 drm_dbg_kms(&dev_priv->drm,
7938 "only 2 lanes on pipe %c: required %i lanes\n",
7939 pipe_name(pipe), pipe_config->fdi_lanes);
7943 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7945 intel_atomic_get_crtc_state(state, other_crtc);
7946 if (IS_ERR(other_crtc_state))
7947 return PTR_ERR(other_crtc_state);
7949 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7950 drm_dbg_kms(&dev_priv->drm,
7951 "fdi link B uses too many lanes to enable link C\n");
7961 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7962 struct intel_crtc_state *pipe_config)
7964 struct drm_device *dev = intel_crtc->base.dev;
7965 struct drm_i915_private *i915 = to_i915(dev);
7966 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7967 int lane, link_bw, fdi_dotclock, ret;
7968 bool needs_recompute = false;
7971 /* FDI is a binary signal running at ~2.7GHz, encoding
7972 * each output octet as 10 bits. The actual frequency
7973 * is stored as a divider into a 100MHz clock, and the
7974 * mode pixel clock is stored in units of 1KHz.
7975 * Hence the bw of each lane in terms of the mode signal
7978 link_bw = intel_fdi_link_freq(i915, pipe_config);
7980 fdi_dotclock = adjusted_mode->crtc_clock;
7982 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7983 pipe_config->pipe_bpp);
7985 pipe_config->fdi_lanes = lane;
7987 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7988 link_bw, &pipe_config->fdi_m_n, false, false);
7990 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7991 if (ret == -EDEADLK)
7994 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7995 pipe_config->pipe_bpp -= 2*3;
7996 drm_dbg_kms(&i915->drm,
7997 "fdi link bw constraint, reducing pipe bpp to %i\n",
7998 pipe_config->pipe_bpp);
7999 needs_recompute = true;
8000 pipe_config->bw_constrained = true;
8005 if (needs_recompute)
8011 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
8013 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8016 /* IPS only exists on ULT machines and is tied to pipe A. */
8017 if (!hsw_crtc_supports_ips(crtc))
8020 if (!dev_priv->params.enable_ips)
8023 if (crtc_state->pipe_bpp > 24)
8027 * We compare against max which means we must take
8028 * the increased cdclk requirement into account when
8029 * calculating the new cdclk.
8031 * Should measure whether using a lower cdclk w/o IPS
8033 if (IS_BROADWELL(dev_priv) &&
8034 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
8040 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
8042 struct drm_i915_private *dev_priv =
8043 to_i915(crtc_state->uapi.crtc->dev);
8044 struct intel_atomic_state *state =
8045 to_intel_atomic_state(crtc_state->uapi.state);
8047 crtc_state->ips_enabled = false;
8049 if (!hsw_crtc_state_ips_capable(crtc_state))
8053 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
8054 * enabled and disabled dynamically based on package C states,
8055 * user space can't make reliable use of the CRCs, so let's just
8056 * completely disable it.
8058 if (crtc_state->crc_enabled)
8061 /* IPS should be fine as long as at least one plane is enabled. */
8062 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8065 if (IS_BROADWELL(dev_priv)) {
8066 const struct intel_cdclk_state *cdclk_state;
8068 cdclk_state = intel_atomic_get_cdclk_state(state);
8069 if (IS_ERR(cdclk_state))
8070 return PTR_ERR(cdclk_state);
8072 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8073 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8077 crtc_state->ips_enabled = true;
8082 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8084 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8086 /* GDG double wide on either pipe, otherwise pipe A only */
8087 return INTEL_GEN(dev_priv) < 4 &&
8088 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8091 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8093 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8094 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8097 * We only use IF-ID interlacing. If we ever use
8098 * PF-ID we'll need to adjust the pixel_rate here.
8101 if (!crtc_state->pch_pfit.enabled)
8104 pipe_w = crtc_state->pipe_src_w;
8105 pipe_h = crtc_state->pipe_src_h;
8107 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8108 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8110 if (pipe_w < pfit_w)
8112 if (pipe_h < pfit_h)
8115 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8116 !pfit_w || !pfit_h))
8119 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8123 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8125 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8127 if (HAS_GMCH(dev_priv))
8128 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8129 crtc_state->pixel_rate =
8130 crtc_state->hw.adjusted_mode.crtc_clock;
8132 crtc_state->pixel_rate =
8133 ilk_pipe_pixel_rate(crtc_state);
8136 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8137 struct intel_crtc_state *pipe_config)
8139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8140 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8141 int clock_limit = dev_priv->max_dotclk_freq;
8143 if (INTEL_GEN(dev_priv) < 4) {
8144 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8147 * Enable double wide mode when the dot clock
8148 * is > 90% of the (display) core speed.
8150 if (intel_crtc_supports_double_wide(crtc) &&
8151 adjusted_mode->crtc_clock > clock_limit) {
8152 clock_limit = dev_priv->max_dotclk_freq;
8153 pipe_config->double_wide = true;
8157 if (adjusted_mode->crtc_clock > clock_limit) {
8158 drm_dbg_kms(&dev_priv->drm,
8159 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8160 adjusted_mode->crtc_clock, clock_limit,
8161 yesno(pipe_config->double_wide));
8165 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8166 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8167 pipe_config->hw.ctm) {
8169 * There is only one pipe CSC unit per pipe, and we need that
8170 * for output conversion from RGB->YCBCR. So if CTM is already
8171 * applied we can't support YCBCR420 output.
8173 drm_dbg_kms(&dev_priv->drm,
8174 "YCBCR420 and CTM together are not possible\n");
8179 * Pipe horizontal size must be even in:
8181 * - LVDS dual channel mode
8182 * - Double wide pipe
8184 if (pipe_config->pipe_src_w & 1) {
8185 if (pipe_config->double_wide) {
8186 drm_dbg_kms(&dev_priv->drm,
8187 "Odd pipe source width not supported with double wide pipe\n");
8191 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8192 intel_is_dual_link_lvds(dev_priv)) {
8193 drm_dbg_kms(&dev_priv->drm,
8194 "Odd pipe source width not supported with dual link LVDS\n");
8199 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8200 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8202 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8203 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8206 intel_crtc_compute_pixel_rate(pipe_config);
8208 if (pipe_config->has_pch_encoder)
8209 return ilk_fdi_compute_config(crtc, pipe_config);
8215 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8217 while (*num > DATA_LINK_M_N_MASK ||
8218 *den > DATA_LINK_M_N_MASK) {
8224 static void compute_m_n(unsigned int m, unsigned int n,
8225 u32 *ret_m, u32 *ret_n,
8229 * Several DP dongles in particular seem to be fussy about
8230 * too large link M/N values. Give N value as 0x8000 that
8231 * should be acceptable by specific devices. 0x8000 is the
8232 * specified fixed N value for asynchronous clock mode,
8233 * which the devices expect also in synchronous clock mode.
8238 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8240 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8241 intel_reduce_m_n_ratio(ret_m, ret_n);
8245 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8246 int pixel_clock, int link_clock,
8247 struct intel_link_m_n *m_n,
8248 bool constant_n, bool fec_enable)
8250 u32 data_clock = bits_per_pixel * pixel_clock;
8253 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8256 compute_m_n(data_clock,
8257 link_clock * nlanes * 8,
8258 &m_n->gmch_m, &m_n->gmch_n,
8261 compute_m_n(pixel_clock, link_clock,
8262 &m_n->link_m, &m_n->link_n,
8266 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8269 * There may be no VBT; and if the BIOS enabled SSC we can
8270 * just keep using it to avoid unnecessary flicker. Whereas if the
8271 * BIOS isn't using it, don't assume it will work even if the VBT
8272 * indicates as much.
8274 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8275 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8279 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8280 drm_dbg_kms(&dev_priv->drm,
8281 "SSC %s by BIOS, overriding VBT which says %s\n",
8282 enableddisabled(bios_lvds_use_ssc),
8283 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8284 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8289 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8291 if (dev_priv->params.panel_use_ssc >= 0)
8292 return dev_priv->params.panel_use_ssc != 0;
8293 return dev_priv->vbt.lvds_use_ssc
8294 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8297 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8299 return (1 << dpll->n) << 16 | dpll->m2;
8302 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8304 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8307 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8308 struct intel_crtc_state *crtc_state,
8309 struct dpll *reduced_clock)
8311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8314 if (IS_PINEVIEW(dev_priv)) {
8315 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8317 fp2 = pnv_dpll_compute_fp(reduced_clock);
8319 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8321 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8324 crtc_state->dpll_hw_state.fp0 = fp;
8326 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8328 crtc_state->dpll_hw_state.fp1 = fp2;
8330 crtc_state->dpll_hw_state.fp1 = fp;
8334 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8340 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8341 * and set it to a reasonable value instead.
8343 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8344 reg_val &= 0xffffff00;
8345 reg_val |= 0x00000030;
8346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8348 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8349 reg_val &= 0x00ffffff;
8350 reg_val |= 0x8c000000;
8351 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8354 reg_val &= 0xffffff00;
8355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8357 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8358 reg_val &= 0x00ffffff;
8359 reg_val |= 0xb0000000;
8360 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8363 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8364 const struct intel_link_m_n *m_n)
8366 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8367 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8368 enum pipe pipe = crtc->pipe;
8370 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8371 TU_SIZE(m_n->tu) | m_n->gmch_m);
8372 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8373 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8374 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8377 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8378 enum transcoder transcoder)
8380 if (IS_HASWELL(dev_priv))
8381 return transcoder == TRANSCODER_EDP;
8384 * Strictly speaking some registers are available before
8385 * gen7, but we only support DRRS on gen7+
8387 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8390 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8391 const struct intel_link_m_n *m_n,
8392 const struct intel_link_m_n *m2_n2)
8394 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8396 enum pipe pipe = crtc->pipe;
8397 enum transcoder transcoder = crtc_state->cpu_transcoder;
8399 if (INTEL_GEN(dev_priv) >= 5) {
8400 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8401 TU_SIZE(m_n->tu) | m_n->gmch_m);
8402 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8404 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8406 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8409 * M2_N2 registers are set only if DRRS is supported
8410 * (to make sure the registers are not unnecessarily accessed).
8412 if (m2_n2 && crtc_state->has_drrs &&
8413 transcoder_has_m2_n2(dev_priv, transcoder)) {
8414 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8415 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8416 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8418 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8420 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8424 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8425 TU_SIZE(m_n->tu) | m_n->gmch_m);
8426 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8427 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8428 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8432 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8434 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8435 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8438 dp_m_n = &crtc_state->dp_m_n;
8439 dp_m2_n2 = &crtc_state->dp_m2_n2;
8440 } else if (m_n == M2_N2) {
8443 * M2_N2 registers are not supported. Hence m2_n2 divider value
8444 * needs to be programmed into M1_N1.
8446 dp_m_n = &crtc_state->dp_m2_n2;
8448 drm_err(&i915->drm, "Unsupported divider value\n");
8452 if (crtc_state->has_pch_encoder)
8453 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8455 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8458 static void vlv_compute_dpll(struct intel_crtc *crtc,
8459 struct intel_crtc_state *pipe_config)
8461 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8462 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8463 if (crtc->pipe != PIPE_A)
8464 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8466 /* DPLL not used with DSI, but still need the rest set up */
8467 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8468 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8469 DPLL_EXT_BUFFER_ENABLE_VLV;
8471 pipe_config->dpll_hw_state.dpll_md =
8472 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8475 static void chv_compute_dpll(struct intel_crtc *crtc,
8476 struct intel_crtc_state *pipe_config)
8478 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8479 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8480 if (crtc->pipe != PIPE_A)
8481 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8483 /* DPLL not used with DSI, but still need the rest set up */
8484 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8485 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8487 pipe_config->dpll_hw_state.dpll_md =
8488 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8491 static void vlv_prepare_pll(struct intel_crtc *crtc,
8492 const struct intel_crtc_state *pipe_config)
8494 struct drm_device *dev = crtc->base.dev;
8495 struct drm_i915_private *dev_priv = to_i915(dev);
8496 enum pipe pipe = crtc->pipe;
8498 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8499 u32 coreclk, reg_val;
8502 intel_de_write(dev_priv, DPLL(pipe),
8503 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8505 /* No need to actually set up the DPLL with DSI */
8506 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8509 vlv_dpio_get(dev_priv);
8511 bestn = pipe_config->dpll.n;
8512 bestm1 = pipe_config->dpll.m1;
8513 bestm2 = pipe_config->dpll.m2;
8514 bestp1 = pipe_config->dpll.p1;
8515 bestp2 = pipe_config->dpll.p2;
8517 /* See eDP HDMI DPIO driver vbios notes doc */
8519 /* PLL B needs special handling */
8521 vlv_pllb_recal_opamp(dev_priv, pipe);
8523 /* Set up Tx target for periodic Rcomp update */
8524 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8526 /* Disable target IRef on PLL */
8527 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8528 reg_val &= 0x00ffffff;
8529 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8531 /* Disable fast lock */
8532 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8534 /* Set idtafcrecal before PLL is enabled */
8535 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8536 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8537 mdiv |= ((bestn << DPIO_N_SHIFT));
8538 mdiv |= (1 << DPIO_K_SHIFT);
8541 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8542 * but we don't support that).
8543 * Note: don't use the DAC post divider as it seems unstable.
8545 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8546 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8548 mdiv |= DPIO_ENABLE_CALIBRATION;
8549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8551 /* Set HBR and RBR LPF coefficients */
8552 if (pipe_config->port_clock == 162000 ||
8553 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8554 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8555 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8561 if (intel_crtc_has_dp_encoder(pipe_config)) {
8562 /* Use SSC source */
8564 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8567 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8569 } else { /* HDMI or VGA */
8570 /* Use bend source */
8572 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8579 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8580 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8581 if (intel_crtc_has_dp_encoder(pipe_config))
8582 coreclk |= 0x01000000;
8583 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8587 vlv_dpio_put(dev_priv);
8590 static void chv_prepare_pll(struct intel_crtc *crtc,
8591 const struct intel_crtc_state *pipe_config)
8593 struct drm_device *dev = crtc->base.dev;
8594 struct drm_i915_private *dev_priv = to_i915(dev);
8595 enum pipe pipe = crtc->pipe;
8596 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8597 u32 loopfilter, tribuf_calcntr;
8598 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8602 /* Enable Refclk and SSC */
8603 intel_de_write(dev_priv, DPLL(pipe),
8604 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8606 /* No need to actually set up the DPLL with DSI */
8607 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8610 bestn = pipe_config->dpll.n;
8611 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8612 bestm1 = pipe_config->dpll.m1;
8613 bestm2 = pipe_config->dpll.m2 >> 22;
8614 bestp1 = pipe_config->dpll.p1;
8615 bestp2 = pipe_config->dpll.p2;
8616 vco = pipe_config->dpll.vco;
8620 vlv_dpio_get(dev_priv);
8622 /* p1 and p2 divider */
8623 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8624 5 << DPIO_CHV_S1_DIV_SHIFT |
8625 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8626 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8627 1 << DPIO_CHV_K_DIV_SHIFT);
8629 /* Feedback post-divider - m2 */
8630 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8632 /* Feedback refclk divider - n and m1 */
8633 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8634 DPIO_CHV_M1_DIV_BY_2 |
8635 1 << DPIO_CHV_N_DIV_SHIFT);
8637 /* M2 fraction division */
8638 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8640 /* M2 fraction division enable */
8641 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8642 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8643 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8645 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8646 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8648 /* Program digital lock detect threshold */
8649 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8650 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8651 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8652 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8654 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8655 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8658 if (vco == 5400000) {
8659 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8660 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8661 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8662 tribuf_calcntr = 0x9;
8663 } else if (vco <= 6200000) {
8664 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8665 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8666 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8667 tribuf_calcntr = 0x9;
8668 } else if (vco <= 6480000) {
8669 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8670 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8671 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8672 tribuf_calcntr = 0x8;
8674 /* Not supported. Apply the same limits as in the max case */
8675 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8676 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8677 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8680 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8682 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8683 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8684 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8685 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8688 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8689 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8692 vlv_dpio_put(dev_priv);
8696 * vlv_force_pll_on - forcibly enable just the PLL
8697 * @dev_priv: i915 private structure
8698 * @pipe: pipe PLL to enable
8699 * @dpll: PLL configuration
8701 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8702 * in cases where we need the PLL enabled even when @pipe is not going to
8705 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8706 const struct dpll *dpll)
8708 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8709 struct intel_crtc_state *pipe_config;
8711 pipe_config = intel_crtc_state_alloc(crtc);
8715 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8716 pipe_config->pixel_multiplier = 1;
8717 pipe_config->dpll = *dpll;
8719 if (IS_CHERRYVIEW(dev_priv)) {
8720 chv_compute_dpll(crtc, pipe_config);
8721 chv_prepare_pll(crtc, pipe_config);
8722 chv_enable_pll(crtc, pipe_config);
8724 vlv_compute_dpll(crtc, pipe_config);
8725 vlv_prepare_pll(crtc, pipe_config);
8726 vlv_enable_pll(crtc, pipe_config);
8735 * vlv_force_pll_off - forcibly disable just the PLL
8736 * @dev_priv: i915 private structure
8737 * @pipe: pipe PLL to disable
8739 * Disable the PLL for @pipe. To be used in cases where we need
8740 * the PLL enabled even when @pipe is not going to be enabled.
8742 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8744 if (IS_CHERRYVIEW(dev_priv))
8745 chv_disable_pll(dev_priv, pipe);
8747 vlv_disable_pll(dev_priv, pipe);
8750 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8751 struct intel_crtc_state *crtc_state,
8752 struct dpll *reduced_clock)
8754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8756 struct dpll *clock = &crtc_state->dpll;
8758 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8760 dpll = DPLL_VGA_MODE_DIS;
8762 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8763 dpll |= DPLLB_MODE_LVDS;
8765 dpll |= DPLLB_MODE_DAC_SERIAL;
8767 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8768 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8769 dpll |= (crtc_state->pixel_multiplier - 1)
8770 << SDVO_MULTIPLIER_SHIFT_HIRES;
8773 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8774 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8775 dpll |= DPLL_SDVO_HIGH_SPEED;
8777 if (intel_crtc_has_dp_encoder(crtc_state))
8778 dpll |= DPLL_SDVO_HIGH_SPEED;
8780 /* compute bitmask from p1 value */
8781 if (IS_PINEVIEW(dev_priv))
8782 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8784 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8785 if (IS_G4X(dev_priv) && reduced_clock)
8786 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8788 switch (clock->p2) {
8790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8802 if (INTEL_GEN(dev_priv) >= 4)
8803 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8805 if (crtc_state->sdvo_tv_clock)
8806 dpll |= PLL_REF_INPUT_TVCLKINBC;
8807 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8808 intel_panel_use_ssc(dev_priv))
8809 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8811 dpll |= PLL_REF_INPUT_DREFCLK;
8813 dpll |= DPLL_VCO_ENABLE;
8814 crtc_state->dpll_hw_state.dpll = dpll;
8816 if (INTEL_GEN(dev_priv) >= 4) {
8817 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8818 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8819 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8823 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8824 struct intel_crtc_state *crtc_state,
8825 struct dpll *reduced_clock)
8827 struct drm_device *dev = crtc->base.dev;
8828 struct drm_i915_private *dev_priv = to_i915(dev);
8830 struct dpll *clock = &crtc_state->dpll;
8832 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8834 dpll = DPLL_VGA_MODE_DIS;
8836 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8837 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8840 dpll |= PLL_P1_DIVIDE_BY_TWO;
8842 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8844 dpll |= PLL_P2_DIVIDE_BY_4;
8849 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8850 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8851 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8852 * Enable) must be set to “1” in both the DPLL A Control Register
8853 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8855 * For simplicity We simply keep both bits always enabled in
8856 * both DPLLS. The spec says we should disable the DVO 2X clock
8857 * when not needed, but this seems to work fine in practice.
8859 if (IS_I830(dev_priv) ||
8860 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8861 dpll |= DPLL_DVO_2X_MODE;
8863 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8864 intel_panel_use_ssc(dev_priv))
8865 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8867 dpll |= PLL_REF_INPUT_DREFCLK;
8869 dpll |= DPLL_VCO_ENABLE;
8870 crtc_state->dpll_hw_state.dpll = dpll;
8873 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8877 enum pipe pipe = crtc->pipe;
8878 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8879 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8880 u32 crtc_vtotal, crtc_vblank_end;
8883 /* We need to be careful not to changed the adjusted mode, for otherwise
8884 * the hw state checker will get angry at the mismatch. */
8885 crtc_vtotal = adjusted_mode->crtc_vtotal;
8886 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8888 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8889 /* the chip adds 2 halflines automatically */
8891 crtc_vblank_end -= 1;
8893 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8894 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8896 vsyncshift = adjusted_mode->crtc_hsync_start -
8897 adjusted_mode->crtc_htotal / 2;
8899 vsyncshift += adjusted_mode->crtc_htotal;
8902 if (INTEL_GEN(dev_priv) > 3)
8903 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8906 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8907 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8908 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8909 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8910 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8911 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8913 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8914 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8915 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8916 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8917 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8918 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8920 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8921 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8922 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8924 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8925 (pipe == PIPE_B || pipe == PIPE_C))
8926 intel_de_write(dev_priv, VTOTAL(pipe),
8927 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8931 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8933 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8934 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8935 enum pipe pipe = crtc->pipe;
8937 /* pipesrc controls the size that is scaled from, which should
8938 * always be the user's requested size.
8940 intel_de_write(dev_priv, PIPESRC(pipe),
8941 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8944 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8946 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8947 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8949 if (IS_GEN(dev_priv, 2))
8952 if (INTEL_GEN(dev_priv) >= 9 ||
8953 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8954 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8956 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8959 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8960 struct intel_crtc_state *pipe_config)
8962 struct drm_device *dev = crtc->base.dev;
8963 struct drm_i915_private *dev_priv = to_i915(dev);
8964 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8967 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8968 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8969 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8971 if (!transcoder_is_dsi(cpu_transcoder)) {
8972 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8973 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8975 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8976 ((tmp >> 16) & 0xffff) + 1;
8978 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8979 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8980 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8982 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8983 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8984 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8986 if (!transcoder_is_dsi(cpu_transcoder)) {
8987 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8988 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8990 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8991 ((tmp >> 16) & 0xffff) + 1;
8993 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8994 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8995 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8997 if (intel_pipe_is_interlaced(pipe_config)) {
8998 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8999 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
9000 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
9004 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
9005 struct intel_crtc_state *pipe_config)
9007 struct drm_device *dev = crtc->base.dev;
9008 struct drm_i915_private *dev_priv = to_i915(dev);
9011 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
9012 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
9013 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
9015 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
9016 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
9019 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
9020 struct intel_crtc_state *pipe_config)
9022 mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
9023 mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
9024 mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
9025 mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
9027 mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
9028 mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
9029 mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
9030 mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
9032 mode->flags = pipe_config->hw.adjusted_mode.flags;
9033 mode->type = DRM_MODE_TYPE_DRIVER;
9035 mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
9037 drm_mode_set_name(mode);
9040 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
9042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9048 /* we keep both pipes enabled on 830 */
9049 if (IS_I830(dev_priv))
9050 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
9052 if (crtc_state->double_wide)
9053 pipeconf |= PIPECONF_DOUBLE_WIDE;
9055 /* only g4x and later have fancy bpc/dither controls */
9056 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9057 IS_CHERRYVIEW(dev_priv)) {
9058 /* Bspec claims that we can't use dithering for 30bpp pipes. */
9059 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
9060 pipeconf |= PIPECONF_DITHER_EN |
9061 PIPECONF_DITHER_TYPE_SP;
9063 switch (crtc_state->pipe_bpp) {
9065 pipeconf |= PIPECONF_6BPC;
9068 pipeconf |= PIPECONF_8BPC;
9071 pipeconf |= PIPECONF_10BPC;
9074 /* Case prevented by intel_choose_pipe_bpp_dither. */
9079 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9080 if (INTEL_GEN(dev_priv) < 4 ||
9081 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9082 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9084 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9086 pipeconf |= PIPECONF_PROGRESSIVE;
9089 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9090 crtc_state->limited_color_range)
9091 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9093 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9095 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9097 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9098 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9101 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9102 struct intel_crtc_state *crtc_state)
9104 struct drm_device *dev = crtc->base.dev;
9105 struct drm_i915_private *dev_priv = to_i915(dev);
9106 const struct intel_limit *limit;
9109 memset(&crtc_state->dpll_hw_state, 0,
9110 sizeof(crtc_state->dpll_hw_state));
9112 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9113 if (intel_panel_use_ssc(dev_priv)) {
9114 refclk = dev_priv->vbt.lvds_ssc_freq;
9115 drm_dbg_kms(&dev_priv->drm,
9116 "using SSC reference clock of %d kHz\n",
9120 limit = &intel_limits_i8xx_lvds;
9121 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9122 limit = &intel_limits_i8xx_dvo;
9124 limit = &intel_limits_i8xx_dac;
9127 if (!crtc_state->clock_set &&
9128 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9129 refclk, NULL, &crtc_state->dpll)) {
9130 drm_err(&dev_priv->drm,
9131 "Couldn't find PLL settings for mode!\n");
9135 i8xx_compute_dpll(crtc, crtc_state, NULL);
9140 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9141 struct intel_crtc_state *crtc_state)
9143 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9144 const struct intel_limit *limit;
9147 memset(&crtc_state->dpll_hw_state, 0,
9148 sizeof(crtc_state->dpll_hw_state));
9150 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9151 if (intel_panel_use_ssc(dev_priv)) {
9152 refclk = dev_priv->vbt.lvds_ssc_freq;
9153 drm_dbg_kms(&dev_priv->drm,
9154 "using SSC reference clock of %d kHz\n",
9158 if (intel_is_dual_link_lvds(dev_priv))
9159 limit = &intel_limits_g4x_dual_channel_lvds;
9161 limit = &intel_limits_g4x_single_channel_lvds;
9162 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9163 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9164 limit = &intel_limits_g4x_hdmi;
9165 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9166 limit = &intel_limits_g4x_sdvo;
9168 /* The option is for other outputs */
9169 limit = &intel_limits_i9xx_sdvo;
9172 if (!crtc_state->clock_set &&
9173 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9174 refclk, NULL, &crtc_state->dpll)) {
9175 drm_err(&dev_priv->drm,
9176 "Couldn't find PLL settings for mode!\n");
9180 i9xx_compute_dpll(crtc, crtc_state, NULL);
9185 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9186 struct intel_crtc_state *crtc_state)
9188 struct drm_device *dev = crtc->base.dev;
9189 struct drm_i915_private *dev_priv = to_i915(dev);
9190 const struct intel_limit *limit;
9193 memset(&crtc_state->dpll_hw_state, 0,
9194 sizeof(crtc_state->dpll_hw_state));
9196 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9197 if (intel_panel_use_ssc(dev_priv)) {
9198 refclk = dev_priv->vbt.lvds_ssc_freq;
9199 drm_dbg_kms(&dev_priv->drm,
9200 "using SSC reference clock of %d kHz\n",
9204 limit = &pnv_limits_lvds;
9206 limit = &pnv_limits_sdvo;
9209 if (!crtc_state->clock_set &&
9210 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9211 refclk, NULL, &crtc_state->dpll)) {
9212 drm_err(&dev_priv->drm,
9213 "Couldn't find PLL settings for mode!\n");
9217 i9xx_compute_dpll(crtc, crtc_state, NULL);
9222 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9223 struct intel_crtc_state *crtc_state)
9225 struct drm_device *dev = crtc->base.dev;
9226 struct drm_i915_private *dev_priv = to_i915(dev);
9227 const struct intel_limit *limit;
9230 memset(&crtc_state->dpll_hw_state, 0,
9231 sizeof(crtc_state->dpll_hw_state));
9233 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9234 if (intel_panel_use_ssc(dev_priv)) {
9235 refclk = dev_priv->vbt.lvds_ssc_freq;
9236 drm_dbg_kms(&dev_priv->drm,
9237 "using SSC reference clock of %d kHz\n",
9241 limit = &intel_limits_i9xx_lvds;
9243 limit = &intel_limits_i9xx_sdvo;
9246 if (!crtc_state->clock_set &&
9247 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9248 refclk, NULL, &crtc_state->dpll)) {
9249 drm_err(&dev_priv->drm,
9250 "Couldn't find PLL settings for mode!\n");
9254 i9xx_compute_dpll(crtc, crtc_state, NULL);
9259 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9260 struct intel_crtc_state *crtc_state)
9262 int refclk = 100000;
9263 const struct intel_limit *limit = &intel_limits_chv;
9264 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9266 memset(&crtc_state->dpll_hw_state, 0,
9267 sizeof(crtc_state->dpll_hw_state));
9269 if (!crtc_state->clock_set &&
9270 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9271 refclk, NULL, &crtc_state->dpll)) {
9272 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9276 chv_compute_dpll(crtc, crtc_state);
9281 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9282 struct intel_crtc_state *crtc_state)
9284 int refclk = 100000;
9285 const struct intel_limit *limit = &intel_limits_vlv;
9286 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9288 memset(&crtc_state->dpll_hw_state, 0,
9289 sizeof(crtc_state->dpll_hw_state));
9291 if (!crtc_state->clock_set &&
9292 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9293 refclk, NULL, &crtc_state->dpll)) {
9294 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9298 vlv_compute_dpll(crtc, crtc_state);
9303 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9305 if (IS_I830(dev_priv))
9308 return INTEL_GEN(dev_priv) >= 4 ||
9309 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9312 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9314 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9318 if (!i9xx_has_pfit(dev_priv))
9321 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9322 if (!(tmp & PFIT_ENABLE))
9325 /* Check whether the pfit is attached to our pipe. */
9326 if (INTEL_GEN(dev_priv) < 4) {
9327 if (crtc->pipe != PIPE_B)
9330 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9334 crtc_state->gmch_pfit.control = tmp;
9335 crtc_state->gmch_pfit.pgm_ratios =
9336 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9339 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9340 struct intel_crtc_state *pipe_config)
9342 struct drm_device *dev = crtc->base.dev;
9343 struct drm_i915_private *dev_priv = to_i915(dev);
9344 enum pipe pipe = crtc->pipe;
9347 int refclk = 100000;
9349 /* In case of DSI, DPLL will not be used */
9350 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9353 vlv_dpio_get(dev_priv);
9354 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9355 vlv_dpio_put(dev_priv);
9357 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9358 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9359 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9360 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9361 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9363 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9367 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9368 struct intel_initial_plane_config *plane_config)
9370 struct drm_device *dev = crtc->base.dev;
9371 struct drm_i915_private *dev_priv = to_i915(dev);
9372 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9373 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9375 u32 val, base, offset;
9376 int fourcc, pixel_format;
9377 unsigned int aligned_height;
9378 struct drm_framebuffer *fb;
9379 struct intel_framebuffer *intel_fb;
9381 if (!plane->get_hw_state(plane, &pipe))
9384 drm_WARN_ON(dev, pipe != crtc->pipe);
9386 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9388 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9392 fb = &intel_fb->base;
9396 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9398 if (INTEL_GEN(dev_priv) >= 4) {
9399 if (val & DISPPLANE_TILED) {
9400 plane_config->tiling = I915_TILING_X;
9401 fb->modifier = I915_FORMAT_MOD_X_TILED;
9404 if (val & DISPPLANE_ROTATE_180)
9405 plane_config->rotation = DRM_MODE_ROTATE_180;
9408 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9409 val & DISPPLANE_MIRROR)
9410 plane_config->rotation |= DRM_MODE_REFLECT_X;
9412 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9413 fourcc = i9xx_format_to_fourcc(pixel_format);
9414 fb->format = drm_format_info(fourcc);
9416 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9417 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9418 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9419 } else if (INTEL_GEN(dev_priv) >= 4) {
9420 if (plane_config->tiling)
9421 offset = intel_de_read(dev_priv,
9422 DSPTILEOFF(i9xx_plane));
9424 offset = intel_de_read(dev_priv,
9425 DSPLINOFF(i9xx_plane));
9426 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9428 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9430 plane_config->base = base;
9432 val = intel_de_read(dev_priv, PIPESRC(pipe));
9433 fb->width = ((val >> 16) & 0xfff) + 1;
9434 fb->height = ((val >> 0) & 0xfff) + 1;
9436 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9437 fb->pitches[0] = val & 0xffffffc0;
9439 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9441 plane_config->size = fb->pitches[0] * aligned_height;
9443 drm_dbg_kms(&dev_priv->drm,
9444 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9445 crtc->base.name, plane->base.name, fb->width, fb->height,
9446 fb->format->cpp[0] * 8, base, fb->pitches[0],
9447 plane_config->size);
9449 plane_config->fb = intel_fb;
9452 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9453 struct intel_crtc_state *pipe_config)
9455 struct drm_device *dev = crtc->base.dev;
9456 struct drm_i915_private *dev_priv = to_i915(dev);
9457 enum pipe pipe = crtc->pipe;
9458 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9460 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9461 int refclk = 100000;
9463 /* In case of DSI, DPLL will not be used */
9464 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9467 vlv_dpio_get(dev_priv);
9468 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9469 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9470 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9471 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9472 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9473 vlv_dpio_put(dev_priv);
9475 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9476 clock.m2 = (pll_dw0 & 0xff) << 22;
9477 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9478 clock.m2 |= pll_dw2 & 0x3fffff;
9479 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9480 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9481 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9483 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9486 static enum intel_output_format
9487 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9492 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9494 if (tmp & PIPEMISC_YUV420_ENABLE) {
9495 /* We support 4:2:0 in full blend mode only */
9496 drm_WARN_ON(&dev_priv->drm,
9497 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9499 return INTEL_OUTPUT_FORMAT_YCBCR420;
9500 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9501 return INTEL_OUTPUT_FORMAT_YCBCR444;
9503 return INTEL_OUTPUT_FORMAT_RGB;
9507 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9509 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9510 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9511 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9512 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9515 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9517 if (tmp & DISPPLANE_GAMMA_ENABLE)
9518 crtc_state->gamma_enable = true;
9520 if (!HAS_GMCH(dev_priv) &&
9521 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9522 crtc_state->csc_enable = true;
9525 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9526 struct intel_crtc_state *pipe_config)
9528 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9529 enum intel_display_power_domain power_domain;
9530 intel_wakeref_t wakeref;
9534 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9535 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9539 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9540 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9541 pipe_config->shared_dpll = NULL;
9545 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9546 if (!(tmp & PIPECONF_ENABLE))
9549 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9550 IS_CHERRYVIEW(dev_priv)) {
9551 switch (tmp & PIPECONF_BPC_MASK) {
9553 pipe_config->pipe_bpp = 18;
9556 pipe_config->pipe_bpp = 24;
9558 case PIPECONF_10BPC:
9559 pipe_config->pipe_bpp = 30;
9566 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9567 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9568 pipe_config->limited_color_range = true;
9570 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9571 PIPECONF_GAMMA_MODE_SHIFT;
9573 if (IS_CHERRYVIEW(dev_priv))
9574 pipe_config->cgm_mode = intel_de_read(dev_priv,
9575 CGM_PIPE_MODE(crtc->pipe));
9577 i9xx_get_pipe_color_config(pipe_config);
9578 intel_color_get_config(pipe_config);
9580 if (INTEL_GEN(dev_priv) < 4)
9581 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9583 intel_get_pipe_timings(crtc, pipe_config);
9584 intel_get_pipe_src_size(crtc, pipe_config);
9586 i9xx_get_pfit_config(pipe_config);
9588 if (INTEL_GEN(dev_priv) >= 4) {
9589 /* No way to read it out on pipes B and C */
9590 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9591 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9593 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9594 pipe_config->pixel_multiplier =
9595 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9596 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9597 pipe_config->dpll_hw_state.dpll_md = tmp;
9598 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9599 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9600 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9601 pipe_config->pixel_multiplier =
9602 ((tmp & SDVO_MULTIPLIER_MASK)
9603 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9605 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9606 * port and will be fixed up in the encoder->get_config
9608 pipe_config->pixel_multiplier = 1;
9610 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9612 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9613 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9615 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9618 /* Mask out read-only status bits. */
9619 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9620 DPLL_PORTC_READY_MASK |
9621 DPLL_PORTB_READY_MASK);
9624 if (IS_CHERRYVIEW(dev_priv))
9625 chv_crtc_clock_get(crtc, pipe_config);
9626 else if (IS_VALLEYVIEW(dev_priv))
9627 vlv_crtc_clock_get(crtc, pipe_config);
9629 i9xx_crtc_clock_get(crtc, pipe_config);
9632 * Normally the dotclock is filled in by the encoder .get_config()
9633 * but in case the pipe is enabled w/o any ports we need a sane
9636 pipe_config->hw.adjusted_mode.crtc_clock =
9637 pipe_config->port_clock / pipe_config->pixel_multiplier;
9642 intel_display_power_put(dev_priv, power_domain, wakeref);
9647 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9649 struct intel_encoder *encoder;
9652 bool has_lvds = false;
9653 bool has_cpu_edp = false;
9654 bool has_panel = false;
9655 bool has_ck505 = false;
9656 bool can_ssc = false;
9657 bool using_ssc_source = false;
9659 /* We need to take the global config into account */
9660 for_each_intel_encoder(&dev_priv->drm, encoder) {
9661 switch (encoder->type) {
9662 case INTEL_OUTPUT_LVDS:
9666 case INTEL_OUTPUT_EDP:
9668 if (encoder->port == PORT_A)
9676 if (HAS_PCH_IBX(dev_priv)) {
9677 has_ck505 = dev_priv->vbt.display_clock_mode;
9678 can_ssc = has_ck505;
9684 /* Check if any DPLLs are using the SSC source */
9685 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9686 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9688 if (!(temp & DPLL_VCO_ENABLE))
9691 if ((temp & PLL_REF_INPUT_MASK) ==
9692 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9693 using_ssc_source = true;
9698 drm_dbg_kms(&dev_priv->drm,
9699 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9700 has_panel, has_lvds, has_ck505, using_ssc_source);
9702 /* Ironlake: try to setup display ref clock before DPLL
9703 * enabling. This is only under driver's control after
9704 * PCH B stepping, previous chipset stepping should be
9705 * ignoring this setting.
9707 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9709 /* As we must carefully and slowly disable/enable each source in turn,
9710 * compute the final state we want first and check if we need to
9711 * make any changes at all.
9714 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9716 final |= DREF_NONSPREAD_CK505_ENABLE;
9718 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9720 final &= ~DREF_SSC_SOURCE_MASK;
9721 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9722 final &= ~DREF_SSC1_ENABLE;
9725 final |= DREF_SSC_SOURCE_ENABLE;
9727 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9728 final |= DREF_SSC1_ENABLE;
9731 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9732 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9734 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9736 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9737 } else if (using_ssc_source) {
9738 final |= DREF_SSC_SOURCE_ENABLE;
9739 final |= DREF_SSC1_ENABLE;
9745 /* Always enable nonspread source */
9746 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9749 val |= DREF_NONSPREAD_CK505_ENABLE;
9751 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9754 val &= ~DREF_SSC_SOURCE_MASK;
9755 val |= DREF_SSC_SOURCE_ENABLE;
9757 /* SSC must be turned on before enabling the CPU output */
9758 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9759 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9760 val |= DREF_SSC1_ENABLE;
9762 val &= ~DREF_SSC1_ENABLE;
9764 /* Get SSC going before enabling the outputs */
9765 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9766 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9769 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9771 /* Enable CPU source on CPU attached eDP */
9773 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9774 drm_dbg_kms(&dev_priv->drm,
9775 "Using SSC on eDP\n");
9776 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9778 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9780 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9782 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9783 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9786 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9788 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9790 /* Turn off CPU output */
9791 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9793 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9794 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9797 if (!using_ssc_source) {
9798 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9800 /* Turn off the SSC source */
9801 val &= ~DREF_SSC_SOURCE_MASK;
9802 val |= DREF_SSC_SOURCE_DISABLE;
9805 val &= ~DREF_SSC1_ENABLE;
9807 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9808 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9813 BUG_ON(val != final);
9816 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9820 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9821 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9822 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9824 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9825 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9826 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9828 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9829 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9830 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9832 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9833 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9834 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9837 /* WaMPhyProgramming:hsw */
9838 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9842 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9843 tmp &= ~(0xFF << 24);
9844 tmp |= (0x12 << 24);
9845 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9847 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9849 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9851 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9853 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9855 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9856 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9857 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9859 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9860 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9861 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9863 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9866 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9868 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9871 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9873 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9876 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9878 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9881 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9883 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9884 tmp &= ~(0xFF << 16);
9885 tmp |= (0x1C << 16);
9886 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9888 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9889 tmp &= ~(0xFF << 16);
9890 tmp |= (0x1C << 16);
9891 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9893 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9895 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9897 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9899 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9901 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9902 tmp &= ~(0xF << 28);
9904 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9906 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9907 tmp &= ~(0xF << 28);
9909 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9912 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9913 * Programming" based on the parameters passed:
9914 * - Sequence to enable CLKOUT_DP
9915 * - Sequence to enable CLKOUT_DP without spread
9916 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9918 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9919 bool with_spread, bool with_fdi)
9923 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9924 "FDI requires downspread\n"))
9926 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9927 with_fdi, "LP PCH doesn't have FDI\n"))
9930 mutex_lock(&dev_priv->sb_lock);
9932 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9933 tmp &= ~SBI_SSCCTL_DISABLE;
9934 tmp |= SBI_SSCCTL_PATHALT;
9935 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9940 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9941 tmp &= ~SBI_SSCCTL_PATHALT;
9942 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9945 lpt_reset_fdi_mphy(dev_priv);
9946 lpt_program_fdi_mphy(dev_priv);
9950 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9951 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9952 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9953 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9955 mutex_unlock(&dev_priv->sb_lock);
9958 /* Sequence to disable CLKOUT_DP */
9959 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9963 mutex_lock(&dev_priv->sb_lock);
9965 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9966 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9967 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9968 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9970 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9971 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9972 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9973 tmp |= SBI_SSCCTL_PATHALT;
9974 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9977 tmp |= SBI_SSCCTL_DISABLE;
9978 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9981 mutex_unlock(&dev_priv->sb_lock);
9984 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9986 static const u16 sscdivintphase[] = {
9987 [BEND_IDX( 50)] = 0x3B23,
9988 [BEND_IDX( 45)] = 0x3B23,
9989 [BEND_IDX( 40)] = 0x3C23,
9990 [BEND_IDX( 35)] = 0x3C23,
9991 [BEND_IDX( 30)] = 0x3D23,
9992 [BEND_IDX( 25)] = 0x3D23,
9993 [BEND_IDX( 20)] = 0x3E23,
9994 [BEND_IDX( 15)] = 0x3E23,
9995 [BEND_IDX( 10)] = 0x3F23,
9996 [BEND_IDX( 5)] = 0x3F23,
9997 [BEND_IDX( 0)] = 0x0025,
9998 [BEND_IDX( -5)] = 0x0025,
9999 [BEND_IDX(-10)] = 0x0125,
10000 [BEND_IDX(-15)] = 0x0125,
10001 [BEND_IDX(-20)] = 0x0225,
10002 [BEND_IDX(-25)] = 0x0225,
10003 [BEND_IDX(-30)] = 0x0325,
10004 [BEND_IDX(-35)] = 0x0325,
10005 [BEND_IDX(-40)] = 0x0425,
10006 [BEND_IDX(-45)] = 0x0425,
10007 [BEND_IDX(-50)] = 0x0525,
10012 * steps -50 to 50 inclusive, in steps of 5
10013 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
10014 * change in clock period = -(steps / 10) * 5.787 ps
10016 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
10019 int idx = BEND_IDX(steps);
10021 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
10024 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
10027 mutex_lock(&dev_priv->sb_lock);
10029 if (steps % 10 != 0)
10033 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
10035 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
10037 tmp |= sscdivintphase[idx];
10038 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
10040 mutex_unlock(&dev_priv->sb_lock);
10045 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
10047 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10048 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
10050 if ((ctl & SPLL_PLL_ENABLE) == 0)
10053 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
10054 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10057 if (IS_BROADWELL(dev_priv) &&
10058 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10064 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10065 enum intel_dpll_id id)
10067 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10068 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10070 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10073 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10076 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10077 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10078 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10084 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10086 struct intel_encoder *encoder;
10087 bool has_fdi = false;
10089 for_each_intel_encoder(&dev_priv->drm, encoder) {
10090 switch (encoder->type) {
10091 case INTEL_OUTPUT_ANALOG:
10100 * The BIOS may have decided to use the PCH SSC
10101 * reference so we must not disable it until the
10102 * relevant PLLs have stopped relying on it. We'll
10103 * just leave the PCH SSC reference enabled in case
10104 * any active PLL is using it. It will get disabled
10105 * after runtime suspend if we don't have FDI.
10107 * TODO: Move the whole reference clock handling
10108 * to the modeset sequence proper so that we can
10109 * actually enable/disable/reconfigure these things
10110 * safely. To do that we need to introduce a real
10111 * clock hierarchy. That would also allow us to do
10112 * clock bending finally.
10114 dev_priv->pch_ssc_use = 0;
10116 if (spll_uses_pch_ssc(dev_priv)) {
10117 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10118 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10121 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10122 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10123 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10126 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10127 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10128 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10131 if (dev_priv->pch_ssc_use)
10135 lpt_bend_clkout_dp(dev_priv, 0);
10136 lpt_enable_clkout_dp(dev_priv, true, true);
10138 lpt_disable_clkout_dp(dev_priv);
10143 * Initialize reference clocks when the driver loads
10145 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10147 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10148 ilk_init_pch_refclk(dev_priv);
10149 else if (HAS_PCH_LPT(dev_priv))
10150 lpt_init_pch_refclk(dev_priv);
10153 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10156 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10157 enum pipe pipe = crtc->pipe;
10162 switch (crtc_state->pipe_bpp) {
10164 val |= PIPECONF_6BPC;
10167 val |= PIPECONF_8BPC;
10170 val |= PIPECONF_10BPC;
10173 val |= PIPECONF_12BPC;
10176 /* Case prevented by intel_choose_pipe_bpp_dither. */
10180 if (crtc_state->dither)
10181 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10183 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10184 val |= PIPECONF_INTERLACED_ILK;
10186 val |= PIPECONF_PROGRESSIVE;
10189 * This would end up with an odd purple hue over
10190 * the entire display. Make sure we don't do it.
10192 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10193 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10195 if (crtc_state->limited_color_range &&
10196 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10197 val |= PIPECONF_COLOR_RANGE_SELECT;
10199 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10200 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10202 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10204 val |= PIPECONF_FRAME_START_DELAY(0);
10206 intel_de_write(dev_priv, PIPECONF(pipe), val);
10207 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10210 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10212 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10214 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10217 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10218 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10220 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10221 val |= PIPECONF_INTERLACED_ILK;
10223 val |= PIPECONF_PROGRESSIVE;
10225 if (IS_HASWELL(dev_priv) &&
10226 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10227 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10229 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10230 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10233 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10235 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10236 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10239 switch (crtc_state->pipe_bpp) {
10241 val |= PIPEMISC_DITHER_6_BPC;
10244 val |= PIPEMISC_DITHER_8_BPC;
10247 val |= PIPEMISC_DITHER_10_BPC;
10250 val |= PIPEMISC_DITHER_12_BPC;
10253 MISSING_CASE(crtc_state->pipe_bpp);
10257 if (crtc_state->dither)
10258 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10260 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10261 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10262 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10264 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10265 val |= PIPEMISC_YUV420_ENABLE |
10266 PIPEMISC_YUV420_MODE_FULL_BLEND;
10268 if (INTEL_GEN(dev_priv) >= 11 &&
10269 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10270 BIT(PLANE_CURSOR))) == 0)
10271 val |= PIPEMISC_HDR_MODE_PRECISION;
10273 if (INTEL_GEN(dev_priv) >= 12)
10274 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10276 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10279 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10284 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10286 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10287 case PIPEMISC_DITHER_6_BPC:
10289 case PIPEMISC_DITHER_8_BPC:
10291 case PIPEMISC_DITHER_10_BPC:
10293 case PIPEMISC_DITHER_12_BPC:
10301 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10304 * Account for spread spectrum to avoid
10305 * oversubscribing the link. Max center spread
10306 * is 2.5%; use 5% for safety's sake.
10308 u32 bps = target_clock * bpp * 21 / 20;
10309 return DIV_ROUND_UP(bps, link_bw * 8);
10312 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10314 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10317 static void ilk_compute_dpll(struct intel_crtc *crtc,
10318 struct intel_crtc_state *crtc_state,
10319 struct dpll *reduced_clock)
10321 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10325 /* Enable autotuning of the PLL clock (if permissible) */
10327 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10328 if ((intel_panel_use_ssc(dev_priv) &&
10329 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10330 (HAS_PCH_IBX(dev_priv) &&
10331 intel_is_dual_link_lvds(dev_priv)))
10333 } else if (crtc_state->sdvo_tv_clock) {
10337 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10339 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10342 if (reduced_clock) {
10343 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10345 if (reduced_clock->m < factor * reduced_clock->n)
10353 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10354 dpll |= DPLLB_MODE_LVDS;
10356 dpll |= DPLLB_MODE_DAC_SERIAL;
10358 dpll |= (crtc_state->pixel_multiplier - 1)
10359 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10361 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10362 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10363 dpll |= DPLL_SDVO_HIGH_SPEED;
10365 if (intel_crtc_has_dp_encoder(crtc_state))
10366 dpll |= DPLL_SDVO_HIGH_SPEED;
10369 * The high speed IO clock is only really required for
10370 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10371 * possible to share the DPLL between CRT and HDMI. Enabling
10372 * the clock needlessly does no real harm, except use up a
10373 * bit of power potentially.
10375 * We'll limit this to IVB with 3 pipes, since it has only two
10376 * DPLLs and so DPLL sharing is the only way to get three pipes
10377 * driving PCH ports at the same time. On SNB we could do this,
10378 * and potentially avoid enabling the second DPLL, but it's not
10379 * clear if it''s a win or loss power wise. No point in doing
10380 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10382 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10383 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10384 dpll |= DPLL_SDVO_HIGH_SPEED;
10386 /* compute bitmask from p1 value */
10387 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10389 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10391 switch (crtc_state->dpll.p2) {
10393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10399 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10402 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10406 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10407 intel_panel_use_ssc(dev_priv))
10408 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10410 dpll |= PLL_REF_INPUT_DREFCLK;
10412 dpll |= DPLL_VCO_ENABLE;
10414 crtc_state->dpll_hw_state.dpll = dpll;
10415 crtc_state->dpll_hw_state.fp0 = fp;
10416 crtc_state->dpll_hw_state.fp1 = fp2;
10419 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10420 struct intel_crtc_state *crtc_state)
10422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10423 struct intel_atomic_state *state =
10424 to_intel_atomic_state(crtc_state->uapi.state);
10425 const struct intel_limit *limit;
10426 int refclk = 120000;
10428 memset(&crtc_state->dpll_hw_state, 0,
10429 sizeof(crtc_state->dpll_hw_state));
10431 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10432 if (!crtc_state->has_pch_encoder)
10435 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10436 if (intel_panel_use_ssc(dev_priv)) {
10437 drm_dbg_kms(&dev_priv->drm,
10438 "using SSC reference clock of %d kHz\n",
10439 dev_priv->vbt.lvds_ssc_freq);
10440 refclk = dev_priv->vbt.lvds_ssc_freq;
10443 if (intel_is_dual_link_lvds(dev_priv)) {
10444 if (refclk == 100000)
10445 limit = &ilk_limits_dual_lvds_100m;
10447 limit = &ilk_limits_dual_lvds;
10449 if (refclk == 100000)
10450 limit = &ilk_limits_single_lvds_100m;
10452 limit = &ilk_limits_single_lvds;
10455 limit = &ilk_limits_dac;
10458 if (!crtc_state->clock_set &&
10459 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10460 refclk, NULL, &crtc_state->dpll)) {
10461 drm_err(&dev_priv->drm,
10462 "Couldn't find PLL settings for mode!\n");
10466 ilk_compute_dpll(crtc, crtc_state, NULL);
10468 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10469 drm_dbg_kms(&dev_priv->drm,
10470 "failed to find PLL for pipe %c\n",
10471 pipe_name(crtc->pipe));
10478 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10479 struct intel_link_m_n *m_n)
10481 struct drm_device *dev = crtc->base.dev;
10482 struct drm_i915_private *dev_priv = to_i915(dev);
10483 enum pipe pipe = crtc->pipe;
10485 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10486 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10487 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10489 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10490 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10491 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10494 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10495 enum transcoder transcoder,
10496 struct intel_link_m_n *m_n,
10497 struct intel_link_m_n *m2_n2)
10499 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10500 enum pipe pipe = crtc->pipe;
10502 if (INTEL_GEN(dev_priv) >= 5) {
10503 m_n->link_m = intel_de_read(dev_priv,
10504 PIPE_LINK_M1(transcoder));
10505 m_n->link_n = intel_de_read(dev_priv,
10506 PIPE_LINK_N1(transcoder));
10507 m_n->gmch_m = intel_de_read(dev_priv,
10508 PIPE_DATA_M1(transcoder))
10510 m_n->gmch_n = intel_de_read(dev_priv,
10511 PIPE_DATA_N1(transcoder));
10512 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10513 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10515 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10516 m2_n2->link_m = intel_de_read(dev_priv,
10517 PIPE_LINK_M2(transcoder));
10518 m2_n2->link_n = intel_de_read(dev_priv,
10519 PIPE_LINK_N2(transcoder));
10520 m2_n2->gmch_m = intel_de_read(dev_priv,
10521 PIPE_DATA_M2(transcoder))
10523 m2_n2->gmch_n = intel_de_read(dev_priv,
10524 PIPE_DATA_N2(transcoder));
10525 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10526 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10529 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10530 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10531 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10533 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10534 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10535 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10539 void intel_dp_get_m_n(struct intel_crtc *crtc,
10540 struct intel_crtc_state *pipe_config)
10542 if (pipe_config->has_pch_encoder)
10543 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10545 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10546 &pipe_config->dp_m_n,
10547 &pipe_config->dp_m2_n2);
10550 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10551 struct intel_crtc_state *pipe_config)
10553 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10554 &pipe_config->fdi_m_n, NULL);
10557 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10560 drm_rect_init(&crtc_state->pch_pfit.dst,
10561 pos >> 16, pos & 0xffff,
10562 size >> 16, size & 0xffff);
10565 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10567 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10569 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10573 /* find scaler attached to this pipe */
10574 for (i = 0; i < crtc->num_scalers; i++) {
10575 u32 ctl, pos, size;
10577 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10578 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10582 crtc_state->pch_pfit.enabled = true;
10584 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10585 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10587 ilk_get_pfit_pos_size(crtc_state, pos, size);
10589 scaler_state->scalers[i].in_use = true;
10593 scaler_state->scaler_id = id;
10595 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10597 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10601 skl_get_initial_plane_config(struct intel_crtc *crtc,
10602 struct intel_initial_plane_config *plane_config)
10604 struct drm_device *dev = crtc->base.dev;
10605 struct drm_i915_private *dev_priv = to_i915(dev);
10606 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10607 enum plane_id plane_id = plane->id;
10609 u32 val, base, offset, stride_mult, tiling, alpha;
10610 int fourcc, pixel_format;
10611 unsigned int aligned_height;
10612 struct drm_framebuffer *fb;
10613 struct intel_framebuffer *intel_fb;
10615 if (!plane->get_hw_state(plane, &pipe))
10618 drm_WARN_ON(dev, pipe != crtc->pipe);
10620 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10622 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10626 fb = &intel_fb->base;
10630 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10632 if (INTEL_GEN(dev_priv) >= 11)
10633 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10635 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10637 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10638 alpha = intel_de_read(dev_priv,
10639 PLANE_COLOR_CTL(pipe, plane_id));
10640 alpha &= PLANE_COLOR_ALPHA_MASK;
10642 alpha = val & PLANE_CTL_ALPHA_MASK;
10645 fourcc = skl_format_to_fourcc(pixel_format,
10646 val & PLANE_CTL_ORDER_RGBX, alpha);
10647 fb->format = drm_format_info(fourcc);
10649 tiling = val & PLANE_CTL_TILED_MASK;
10651 case PLANE_CTL_TILED_LINEAR:
10652 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10654 case PLANE_CTL_TILED_X:
10655 plane_config->tiling = I915_TILING_X;
10656 fb->modifier = I915_FORMAT_MOD_X_TILED;
10658 case PLANE_CTL_TILED_Y:
10659 plane_config->tiling = I915_TILING_Y;
10660 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10661 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10662 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10663 I915_FORMAT_MOD_Y_TILED_CCS;
10664 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10665 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10667 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10669 case PLANE_CTL_TILED_YF:
10670 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10671 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10673 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10676 MISSING_CASE(tiling);
10681 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10682 * while i915 HW rotation is clockwise, thats why this swapping.
10684 switch (val & PLANE_CTL_ROTATE_MASK) {
10685 case PLANE_CTL_ROTATE_0:
10686 plane_config->rotation = DRM_MODE_ROTATE_0;
10688 case PLANE_CTL_ROTATE_90:
10689 plane_config->rotation = DRM_MODE_ROTATE_270;
10691 case PLANE_CTL_ROTATE_180:
10692 plane_config->rotation = DRM_MODE_ROTATE_180;
10694 case PLANE_CTL_ROTATE_270:
10695 plane_config->rotation = DRM_MODE_ROTATE_90;
10699 if (INTEL_GEN(dev_priv) >= 10 &&
10700 val & PLANE_CTL_FLIP_HORIZONTAL)
10701 plane_config->rotation |= DRM_MODE_REFLECT_X;
10703 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10704 plane_config->base = base;
10706 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10708 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10709 fb->height = ((val >> 16) & 0xffff) + 1;
10710 fb->width = ((val >> 0) & 0xffff) + 1;
10712 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10713 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10714 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10716 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10718 plane_config->size = fb->pitches[0] * aligned_height;
10720 drm_dbg_kms(&dev_priv->drm,
10721 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10722 crtc->base.name, plane->base.name, fb->width, fb->height,
10723 fb->format->cpp[0] * 8, base, fb->pitches[0],
10724 plane_config->size);
10726 plane_config->fb = intel_fb;
10733 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10736 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10737 u32 ctl, pos, size;
10739 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10740 if ((ctl & PF_ENABLE) == 0)
10743 crtc_state->pch_pfit.enabled = true;
10745 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10746 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10748 ilk_get_pfit_pos_size(crtc_state, pos, size);
10751 * We currently do not free assignements of panel fitters on
10752 * ivb/hsw (since we don't use the higher upscaling modes which
10753 * differentiates them) so just WARN about this case for now.
10755 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10756 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10759 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10760 struct intel_crtc_state *pipe_config)
10762 struct drm_device *dev = crtc->base.dev;
10763 struct drm_i915_private *dev_priv = to_i915(dev);
10764 enum intel_display_power_domain power_domain;
10765 intel_wakeref_t wakeref;
10769 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10770 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10774 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10775 pipe_config->shared_dpll = NULL;
10778 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10779 if (!(tmp & PIPECONF_ENABLE))
10782 switch (tmp & PIPECONF_BPC_MASK) {
10783 case PIPECONF_6BPC:
10784 pipe_config->pipe_bpp = 18;
10786 case PIPECONF_8BPC:
10787 pipe_config->pipe_bpp = 24;
10789 case PIPECONF_10BPC:
10790 pipe_config->pipe_bpp = 30;
10792 case PIPECONF_12BPC:
10793 pipe_config->pipe_bpp = 36;
10799 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10800 pipe_config->limited_color_range = true;
10802 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10803 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10804 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10805 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10808 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10812 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10813 PIPECONF_GAMMA_MODE_SHIFT;
10815 pipe_config->csc_mode = intel_de_read(dev_priv,
10816 PIPE_CSC_MODE(crtc->pipe));
10818 i9xx_get_pipe_color_config(pipe_config);
10819 intel_color_get_config(pipe_config);
10821 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10822 struct intel_shared_dpll *pll;
10823 enum intel_dpll_id pll_id;
10825 pipe_config->has_pch_encoder = true;
10827 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10828 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10829 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10831 ilk_get_fdi_m_n_config(crtc, pipe_config);
10833 if (HAS_PCH_IBX(dev_priv)) {
10835 * The pipe->pch transcoder and pch transcoder->pll
10836 * mapping is fixed.
10838 pll_id = (enum intel_dpll_id) crtc->pipe;
10840 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10841 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10842 pll_id = DPLL_ID_PCH_PLL_B;
10844 pll_id= DPLL_ID_PCH_PLL_A;
10847 pipe_config->shared_dpll =
10848 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10849 pll = pipe_config->shared_dpll;
10851 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10852 &pipe_config->dpll_hw_state));
10854 tmp = pipe_config->dpll_hw_state.dpll;
10855 pipe_config->pixel_multiplier =
10856 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10857 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10859 ilk_pch_clock_get(crtc, pipe_config);
10861 pipe_config->pixel_multiplier = 1;
10864 intel_get_pipe_timings(crtc, pipe_config);
10865 intel_get_pipe_src_size(crtc, pipe_config);
10867 ilk_get_pfit_config(pipe_config);
10872 intel_display_power_put(dev_priv, power_domain, wakeref);
10877 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10878 struct intel_crtc_state *crtc_state)
10880 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10881 struct intel_atomic_state *state =
10882 to_intel_atomic_state(crtc_state->uapi.state);
10884 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10885 INTEL_GEN(dev_priv) >= 11) {
10886 struct intel_encoder *encoder =
10887 intel_get_crtc_new_encoder(state, crtc_state);
10889 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10890 drm_dbg_kms(&dev_priv->drm,
10891 "failed to find PLL for pipe %c\n",
10892 pipe_name(crtc->pipe));
10900 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10901 struct intel_crtc_state *pipe_config)
10903 enum intel_dpll_id id;
10906 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10907 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10909 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10912 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10915 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10916 struct intel_crtc_state *pipe_config)
10918 enum phy phy = intel_port_to_phy(dev_priv, port);
10919 enum icl_port_dpll_id port_dpll_id;
10920 enum intel_dpll_id id;
10923 if (intel_phy_is_combo(dev_priv, phy)) {
10926 if (IS_ROCKETLAKE(dev_priv)) {
10927 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10928 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10930 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10931 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10934 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10935 id = temp >> shift;
10936 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10937 } else if (intel_phy_is_tc(dev_priv, phy)) {
10938 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10940 if (clk_sel == DDI_CLK_SEL_MG) {
10941 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10943 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10945 drm_WARN_ON(&dev_priv->drm,
10946 clk_sel < DDI_CLK_SEL_TBT_162);
10947 id = DPLL_ID_ICL_TBTPLL;
10948 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10951 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10955 pipe_config->icl_port_dplls[port_dpll_id].pll =
10956 intel_get_shared_dpll_by_id(dev_priv, id);
10958 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10961 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10963 struct intel_crtc_state *pipe_config)
10965 enum intel_dpll_id id;
10969 id = DPLL_ID_SKL_DPLL0;
10972 id = DPLL_ID_SKL_DPLL1;
10975 id = DPLL_ID_SKL_DPLL2;
10978 drm_err(&dev_priv->drm, "Incorrect port type\n");
10982 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10985 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10986 struct intel_crtc_state *pipe_config)
10988 enum intel_dpll_id id;
10991 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10992 id = temp >> (port * 3 + 1);
10994 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10997 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11000 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11001 struct intel_crtc_state *pipe_config)
11003 enum intel_dpll_id id;
11004 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
11006 switch (ddi_pll_sel) {
11007 case PORT_CLK_SEL_WRPLL1:
11008 id = DPLL_ID_WRPLL1;
11010 case PORT_CLK_SEL_WRPLL2:
11011 id = DPLL_ID_WRPLL2;
11013 case PORT_CLK_SEL_SPLL:
11016 case PORT_CLK_SEL_LCPLL_810:
11017 id = DPLL_ID_LCPLL_810;
11019 case PORT_CLK_SEL_LCPLL_1350:
11020 id = DPLL_ID_LCPLL_1350;
11022 case PORT_CLK_SEL_LCPLL_2700:
11023 id = DPLL_ID_LCPLL_2700;
11026 MISSING_CASE(ddi_pll_sel);
11028 case PORT_CLK_SEL_NONE:
11032 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11035 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
11036 struct intel_crtc_state *pipe_config,
11037 u64 *power_domain_mask,
11038 intel_wakeref_t *wakerefs)
11040 struct drm_device *dev = crtc->base.dev;
11041 struct drm_i915_private *dev_priv = to_i915(dev);
11042 enum intel_display_power_domain power_domain;
11043 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
11044 unsigned long enabled_panel_transcoders = 0;
11045 enum transcoder panel_transcoder;
11046 intel_wakeref_t wf;
11049 if (INTEL_GEN(dev_priv) >= 11)
11050 panel_transcoder_mask |=
11051 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
11054 * The pipe->transcoder mapping is fixed with the exception of the eDP
11055 * and DSI transcoders handled below.
11057 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11060 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11061 * consistency and less surprising code; it's in always on power).
11063 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11064 panel_transcoder_mask) {
11065 bool force_thru = false;
11066 enum pipe trans_pipe;
11068 tmp = intel_de_read(dev_priv,
11069 TRANS_DDI_FUNC_CTL(panel_transcoder));
11070 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11074 * Log all enabled ones, only use the first one.
11076 * FIXME: This won't work for two separate DSI displays.
11078 enabled_panel_transcoders |= BIT(panel_transcoder);
11079 if (enabled_panel_transcoders != BIT(panel_transcoder))
11082 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11085 "unknown pipe linked to transcoder %s\n",
11086 transcoder_name(panel_transcoder));
11088 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11091 case TRANS_DDI_EDP_INPUT_A_ON:
11092 trans_pipe = PIPE_A;
11094 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11095 trans_pipe = PIPE_B;
11097 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11098 trans_pipe = PIPE_C;
11100 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11101 trans_pipe = PIPE_D;
11105 if (trans_pipe == crtc->pipe) {
11106 pipe_config->cpu_transcoder = panel_transcoder;
11107 pipe_config->pch_pfit.force_thru = force_thru;
11112 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11114 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11115 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11117 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11118 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11120 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11124 wakerefs[power_domain] = wf;
11125 *power_domain_mask |= BIT_ULL(power_domain);
11127 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11129 return tmp & PIPECONF_ENABLE;
11132 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11133 struct intel_crtc_state *pipe_config,
11134 u64 *power_domain_mask,
11135 intel_wakeref_t *wakerefs)
11137 struct drm_device *dev = crtc->base.dev;
11138 struct drm_i915_private *dev_priv = to_i915(dev);
11139 enum intel_display_power_domain power_domain;
11140 enum transcoder cpu_transcoder;
11141 intel_wakeref_t wf;
11145 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11146 if (port == PORT_A)
11147 cpu_transcoder = TRANSCODER_DSI_A;
11149 cpu_transcoder = TRANSCODER_DSI_C;
11151 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11152 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11154 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11158 wakerefs[power_domain] = wf;
11159 *power_domain_mask |= BIT_ULL(power_domain);
11162 * The PLL needs to be enabled with a valid divider
11163 * configuration, otherwise accessing DSI registers will hang
11164 * the machine. See BSpec North Display Engine
11165 * registers/MIPI[BXT]. We can break out here early, since we
11166 * need the same DSI PLL to be enabled for both DSI ports.
11168 if (!bxt_dsi_pll_is_enabled(dev_priv))
11171 /* XXX: this works for video mode only */
11172 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11173 if (!(tmp & DPI_ENABLE))
11176 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11177 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11180 pipe_config->cpu_transcoder = cpu_transcoder;
11184 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11187 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11188 struct intel_crtc_state *pipe_config)
11190 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11191 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11192 struct intel_shared_dpll *pll;
11196 if (transcoder_is_dsi(cpu_transcoder)) {
11197 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11200 tmp = intel_de_read(dev_priv,
11201 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11202 if (INTEL_GEN(dev_priv) >= 12)
11203 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11205 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11208 if (INTEL_GEN(dev_priv) >= 11)
11209 icl_get_ddi_pll(dev_priv, port, pipe_config);
11210 else if (IS_CANNONLAKE(dev_priv))
11211 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11212 else if (IS_GEN9_BC(dev_priv))
11213 skl_get_ddi_pll(dev_priv, port, pipe_config);
11214 else if (IS_GEN9_LP(dev_priv))
11215 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11217 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11219 pll = pipe_config->shared_dpll;
11221 drm_WARN_ON(&dev_priv->drm,
11222 !pll->info->funcs->get_hw_state(dev_priv, pll,
11223 &pipe_config->dpll_hw_state));
11227 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11228 * DDI E. So just check whether this pipe is wired to DDI E and whether
11229 * the PCH transcoder is on.
11231 if (INTEL_GEN(dev_priv) < 9 &&
11232 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11233 pipe_config->has_pch_encoder = true;
11235 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11236 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11237 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11239 ilk_get_fdi_m_n_config(crtc, pipe_config);
11243 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11244 struct intel_crtc_state *pipe_config)
11246 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11247 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11248 enum intel_display_power_domain power_domain;
11249 u64 power_domain_mask;
11253 pipe_config->master_transcoder = INVALID_TRANSCODER;
11255 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11256 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11260 wakerefs[power_domain] = wf;
11261 power_domain_mask = BIT_ULL(power_domain);
11263 pipe_config->shared_dpll = NULL;
11265 active = hsw_get_transcoder_state(crtc, pipe_config,
11266 &power_domain_mask, wakerefs);
11268 if (IS_GEN9_LP(dev_priv) &&
11269 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11270 &power_domain_mask, wakerefs)) {
11271 drm_WARN_ON(&dev_priv->drm, active);
11278 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11279 INTEL_GEN(dev_priv) >= 11) {
11280 hsw_get_ddi_port_state(crtc, pipe_config);
11281 intel_get_pipe_timings(crtc, pipe_config);
11284 intel_get_pipe_src_size(crtc, pipe_config);
11286 if (IS_HASWELL(dev_priv)) {
11287 u32 tmp = intel_de_read(dev_priv,
11288 PIPECONF(pipe_config->cpu_transcoder));
11290 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11291 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11293 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11295 pipe_config->output_format =
11296 bdw_get_pipemisc_output_format(crtc);
11299 * Currently there is no interface defined to
11300 * check user preference between RGB/YCBCR444
11301 * or YCBCR420. So the only possible case for
11302 * YCBCR444 usage is driving YCBCR420 output
11303 * with LSPCON, when pipe is configured for
11304 * YCBCR444 output and LSPCON takes care of
11307 pipe_config->lspcon_downsampling =
11308 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11311 pipe_config->gamma_mode = intel_de_read(dev_priv,
11312 GAMMA_MODE(crtc->pipe));
11314 pipe_config->csc_mode = intel_de_read(dev_priv,
11315 PIPE_CSC_MODE(crtc->pipe));
11317 if (INTEL_GEN(dev_priv) >= 9) {
11318 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11320 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11321 pipe_config->gamma_enable = true;
11323 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11324 pipe_config->csc_enable = true;
11326 i9xx_get_pipe_color_config(pipe_config);
11329 intel_color_get_config(pipe_config);
11331 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11332 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11333 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11334 pipe_config->ips_linetime =
11335 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11337 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11338 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11340 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11342 wakerefs[power_domain] = wf;
11343 power_domain_mask |= BIT_ULL(power_domain);
11345 if (INTEL_GEN(dev_priv) >= 9)
11346 skl_get_pfit_config(pipe_config);
11348 ilk_get_pfit_config(pipe_config);
11351 if (hsw_crtc_supports_ips(crtc)) {
11352 if (IS_HASWELL(dev_priv))
11353 pipe_config->ips_enabled = intel_de_read(dev_priv,
11354 IPS_CTL) & IPS_ENABLE;
11357 * We cannot readout IPS state on broadwell, set to
11358 * true so we can set it to a defined state on first
11361 pipe_config->ips_enabled = true;
11365 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11366 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11367 pipe_config->pixel_multiplier =
11368 intel_de_read(dev_priv,
11369 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11371 pipe_config->pixel_multiplier = 1;
11375 for_each_power_domain(power_domain, power_domain_mask)
11376 intel_display_power_put(dev_priv,
11377 power_domain, wakerefs[power_domain]);
11382 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11384 struct drm_i915_private *dev_priv =
11385 to_i915(plane_state->uapi.plane->dev);
11386 const struct drm_framebuffer *fb = plane_state->hw.fb;
11387 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11390 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11391 base = sg_dma_address(obj->mm.pages->sgl);
11393 base = intel_plane_ggtt_offset(plane_state);
11395 return base + plane_state->color_plane[0].offset;
11398 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11400 int x = plane_state->uapi.dst.x1;
11401 int y = plane_state->uapi.dst.y1;
11405 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11408 pos |= x << CURSOR_X_SHIFT;
11411 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11414 pos |= y << CURSOR_Y_SHIFT;
11419 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11421 const struct drm_mode_config *config =
11422 &plane_state->uapi.plane->dev->mode_config;
11423 int width = drm_rect_width(&plane_state->uapi.dst);
11424 int height = drm_rect_height(&plane_state->uapi.dst);
11426 return width > 0 && width <= config->cursor_width &&
11427 height > 0 && height <= config->cursor_height;
11430 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11432 struct drm_i915_private *dev_priv =
11433 to_i915(plane_state->uapi.plane->dev);
11434 unsigned int rotation = plane_state->hw.rotation;
11439 ret = intel_plane_compute_gtt(plane_state);
11443 if (!plane_state->uapi.visible)
11446 src_x = plane_state->uapi.src.x1 >> 16;
11447 src_y = plane_state->uapi.src.y1 >> 16;
11449 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11450 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11453 if (src_x != 0 || src_y != 0) {
11454 drm_dbg_kms(&dev_priv->drm,
11455 "Arbitrary cursor panning not supported\n");
11460 * Put the final coordinates back so that the src
11461 * coordinate checks will see the right values.
11463 drm_rect_translate_to(&plane_state->uapi.src,
11464 src_x << 16, src_y << 16);
11466 /* ILK+ do this automagically in hardware */
11467 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11468 const struct drm_framebuffer *fb = plane_state->hw.fb;
11469 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11470 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11472 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11475 plane_state->color_plane[0].offset = offset;
11476 plane_state->color_plane[0].x = src_x;
11477 plane_state->color_plane[0].y = src_y;
11482 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11483 struct intel_plane_state *plane_state)
11485 const struct drm_framebuffer *fb = plane_state->hw.fb;
11486 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11489 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11490 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11494 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11496 DRM_PLANE_HELPER_NO_SCALING,
11497 DRM_PLANE_HELPER_NO_SCALING,
11502 /* Use the unclipped src/dst rectangles, which we program to hw */
11503 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11504 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11506 ret = intel_cursor_check_surface(plane_state);
11510 if (!plane_state->uapi.visible)
11513 ret = intel_plane_check_src_coordinates(plane_state);
11520 static unsigned int
11521 i845_cursor_max_stride(struct intel_plane *plane,
11522 u32 pixel_format, u64 modifier,
11523 unsigned int rotation)
11528 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11532 if (crtc_state->gamma_enable)
11533 cntl |= CURSOR_GAMMA_ENABLE;
11538 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11539 const struct intel_plane_state *plane_state)
11541 return CURSOR_ENABLE |
11542 CURSOR_FORMAT_ARGB |
11543 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11546 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11548 int width = drm_rect_width(&plane_state->uapi.dst);
11551 * 845g/865g are only limited by the width of their cursors,
11552 * the height is arbitrary up to the precision of the register.
11554 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11557 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11558 struct intel_plane_state *plane_state)
11560 const struct drm_framebuffer *fb = plane_state->hw.fb;
11561 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11564 ret = intel_check_cursor(crtc_state, plane_state);
11568 /* if we want to turn off the cursor ignore width and height */
11572 /* Check for which cursor types we support */
11573 if (!i845_cursor_size_ok(plane_state)) {
11574 drm_dbg_kms(&i915->drm,
11575 "Cursor dimension %dx%d not supported\n",
11576 drm_rect_width(&plane_state->uapi.dst),
11577 drm_rect_height(&plane_state->uapi.dst));
11581 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11582 plane_state->color_plane[0].stride != fb->pitches[0]);
11584 switch (fb->pitches[0]) {
11591 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11596 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11601 static void i845_update_cursor(struct intel_plane *plane,
11602 const struct intel_crtc_state *crtc_state,
11603 const struct intel_plane_state *plane_state)
11605 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11606 u32 cntl = 0, base = 0, pos = 0, size = 0;
11607 unsigned long irqflags;
11609 if (plane_state && plane_state->uapi.visible) {
11610 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11611 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11613 cntl = plane_state->ctl |
11614 i845_cursor_ctl_crtc(crtc_state);
11616 size = (height << 12) | width;
11618 base = intel_cursor_base(plane_state);
11619 pos = intel_cursor_position(plane_state);
11622 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11624 /* On these chipsets we can only modify the base/size/stride
11625 * whilst the cursor is disabled.
11627 if (plane->cursor.base != base ||
11628 plane->cursor.size != size ||
11629 plane->cursor.cntl != cntl) {
11630 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11631 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11632 intel_de_write_fw(dev_priv, CURSIZE, size);
11633 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11634 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11636 plane->cursor.base = base;
11637 plane->cursor.size = size;
11638 plane->cursor.cntl = cntl;
11640 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11643 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11646 static void i845_disable_cursor(struct intel_plane *plane,
11647 const struct intel_crtc_state *crtc_state)
11649 i845_update_cursor(plane, crtc_state, NULL);
11652 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11655 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11656 enum intel_display_power_domain power_domain;
11657 intel_wakeref_t wakeref;
11660 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11661 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11665 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11669 intel_display_power_put(dev_priv, power_domain, wakeref);
11674 static unsigned int
11675 i9xx_cursor_max_stride(struct intel_plane *plane,
11676 u32 pixel_format, u64 modifier,
11677 unsigned int rotation)
11679 return plane->base.dev->mode_config.cursor_width * 4;
11682 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11688 if (INTEL_GEN(dev_priv) >= 11)
11691 if (crtc_state->gamma_enable)
11692 cntl = MCURSOR_GAMMA_ENABLE;
11694 if (crtc_state->csc_enable)
11695 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11697 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11698 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11703 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11704 const struct intel_plane_state *plane_state)
11706 struct drm_i915_private *dev_priv =
11707 to_i915(plane_state->uapi.plane->dev);
11710 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11711 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11713 switch (drm_rect_width(&plane_state->uapi.dst)) {
11715 cntl |= MCURSOR_MODE_64_ARGB_AX;
11718 cntl |= MCURSOR_MODE_128_ARGB_AX;
11721 cntl |= MCURSOR_MODE_256_ARGB_AX;
11724 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11728 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11729 cntl |= MCURSOR_ROTATE_180;
11734 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11736 struct drm_i915_private *dev_priv =
11737 to_i915(plane_state->uapi.plane->dev);
11738 int width = drm_rect_width(&plane_state->uapi.dst);
11739 int height = drm_rect_height(&plane_state->uapi.dst);
11741 if (!intel_cursor_size_ok(plane_state))
11744 /* Cursor width is limited to a few power-of-two sizes */
11755 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11756 * height from 8 lines up to the cursor width, when the
11757 * cursor is not rotated. Everything else requires square
11760 if (HAS_CUR_FBC(dev_priv) &&
11761 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11762 if (height < 8 || height > width)
11765 if (height != width)
11772 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11773 struct intel_plane_state *plane_state)
11775 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11776 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11777 const struct drm_framebuffer *fb = plane_state->hw.fb;
11778 enum pipe pipe = plane->pipe;
11781 ret = intel_check_cursor(crtc_state, plane_state);
11785 /* if we want to turn off the cursor ignore width and height */
11789 /* Check for which cursor types we support */
11790 if (!i9xx_cursor_size_ok(plane_state)) {
11791 drm_dbg(&dev_priv->drm,
11792 "Cursor dimension %dx%d not supported\n",
11793 drm_rect_width(&plane_state->uapi.dst),
11794 drm_rect_height(&plane_state->uapi.dst));
11798 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11799 plane_state->color_plane[0].stride != fb->pitches[0]);
11801 if (fb->pitches[0] !=
11802 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11803 drm_dbg_kms(&dev_priv->drm,
11804 "Invalid cursor stride (%u) (cursor width %d)\n",
11806 drm_rect_width(&plane_state->uapi.dst));
11811 * There's something wrong with the cursor on CHV pipe C.
11812 * If it straddles the left edge of the screen then
11813 * moving it away from the edge or disabling it often
11814 * results in a pipe underrun, and often that can lead to
11815 * dead pipe (constant underrun reported, and it scans
11816 * out just a solid color). To recover from that, the
11817 * display power well must be turned off and on again.
11818 * Refuse the put the cursor into that compromised position.
11820 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11821 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11822 drm_dbg_kms(&dev_priv->drm,
11823 "CHV cursor C not allowed to straddle the left screen edge\n");
11827 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11832 static void i9xx_update_cursor(struct intel_plane *plane,
11833 const struct intel_crtc_state *crtc_state,
11834 const struct intel_plane_state *plane_state)
11836 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11837 enum pipe pipe = plane->pipe;
11838 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11839 unsigned long irqflags;
11841 if (plane_state && plane_state->uapi.visible) {
11842 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11843 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11845 cntl = plane_state->ctl |
11846 i9xx_cursor_ctl_crtc(crtc_state);
11848 if (width != height)
11849 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11851 base = intel_cursor_base(plane_state);
11852 pos = intel_cursor_position(plane_state);
11855 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11858 * On some platforms writing CURCNTR first will also
11859 * cause CURPOS to be armed by the CURBASE write.
11860 * Without the CURCNTR write the CURPOS write would
11861 * arm itself. Thus we always update CURCNTR before
11864 * On other platforms CURPOS always requires the
11865 * CURBASE write to arm the update. Additonally
11866 * a write to any of the cursor register will cancel
11867 * an already armed cursor update. Thus leaving out
11868 * the CURBASE write after CURPOS could lead to a
11869 * cursor that doesn't appear to move, or even change
11870 * shape. Thus we always write CURBASE.
11872 * The other registers are armed by by the CURBASE write
11873 * except when the plane is getting enabled at which time
11874 * the CURCNTR write arms the update.
11877 if (INTEL_GEN(dev_priv) >= 9)
11878 skl_write_cursor_wm(plane, crtc_state);
11880 if (!needs_modeset(crtc_state))
11881 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
11883 if (plane->cursor.base != base ||
11884 plane->cursor.size != fbc_ctl ||
11885 plane->cursor.cntl != cntl) {
11886 if (HAS_CUR_FBC(dev_priv))
11887 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11889 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11890 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11891 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11893 plane->cursor.base = base;
11894 plane->cursor.size = fbc_ctl;
11895 plane->cursor.cntl = cntl;
11897 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11898 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11901 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11904 static void i9xx_disable_cursor(struct intel_plane *plane,
11905 const struct intel_crtc_state *crtc_state)
11907 i9xx_update_cursor(plane, crtc_state, NULL);
11910 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11913 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11914 enum intel_display_power_domain power_domain;
11915 intel_wakeref_t wakeref;
11920 * Not 100% correct for planes that can move between pipes,
11921 * but that's only the case for gen2-3 which don't have any
11922 * display power wells.
11924 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11925 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11929 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11931 ret = val & MCURSOR_MODE;
11933 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11934 *pipe = plane->pipe;
11936 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11937 MCURSOR_PIPE_SELECT_SHIFT;
11939 intel_display_power_put(dev_priv, power_domain, wakeref);
11944 /* VESA 640x480x72Hz mode to set on the pipe */
11945 static const struct drm_display_mode load_detect_mode = {
11946 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11947 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11950 struct drm_framebuffer *
11951 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11952 struct drm_mode_fb_cmd2 *mode_cmd)
11954 struct intel_framebuffer *intel_fb;
11957 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11959 return ERR_PTR(-ENOMEM);
11961 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11965 return &intel_fb->base;
11969 return ERR_PTR(ret);
11972 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11973 struct drm_crtc *crtc)
11975 struct drm_plane *plane;
11976 struct drm_plane_state *plane_state;
11979 ret = drm_atomic_add_affected_planes(state, crtc);
11983 for_each_new_plane_in_state(state, plane, plane_state, i) {
11984 if (plane_state->crtc != crtc)
11987 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11991 drm_atomic_set_fb_for_plane(plane_state, NULL);
11997 int intel_get_load_detect_pipe(struct drm_connector *connector,
11998 struct intel_load_detect_pipe *old,
11999 struct drm_modeset_acquire_ctx *ctx)
12001 struct intel_crtc *intel_crtc;
12002 struct intel_encoder *intel_encoder =
12003 intel_attached_encoder(to_intel_connector(connector));
12004 struct drm_crtc *possible_crtc;
12005 struct drm_encoder *encoder = &intel_encoder->base;
12006 struct drm_crtc *crtc = NULL;
12007 struct drm_device *dev = encoder->dev;
12008 struct drm_i915_private *dev_priv = to_i915(dev);
12009 struct drm_mode_config *config = &dev->mode_config;
12010 struct drm_atomic_state *state = NULL, *restore_state = NULL;
12011 struct drm_connector_state *connector_state;
12012 struct intel_crtc_state *crtc_state;
12015 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12016 connector->base.id, connector->name,
12017 encoder->base.id, encoder->name);
12019 old->restore_state = NULL;
12021 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
12024 * Algorithm gets a little messy:
12026 * - if the connector already has an assigned crtc, use it (but make
12027 * sure it's on first)
12029 * - try to find the first unused crtc that can drive this connector,
12030 * and use that if we find one
12033 /* See if we already have a CRTC for this connector */
12034 if (connector->state->crtc) {
12035 crtc = connector->state->crtc;
12037 ret = drm_modeset_lock(&crtc->mutex, ctx);
12041 /* Make sure the crtc and connector are running */
12045 /* Find an unused one (if possible) */
12046 for_each_crtc(dev, possible_crtc) {
12048 if (!(encoder->possible_crtcs & (1 << i)))
12051 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
12055 if (possible_crtc->state->enable) {
12056 drm_modeset_unlock(&possible_crtc->mutex);
12060 crtc = possible_crtc;
12065 * If we didn't find an unused CRTC, don't use any.
12068 drm_dbg_kms(&dev_priv->drm,
12069 "no pipe available for load-detect\n");
12075 intel_crtc = to_intel_crtc(crtc);
12077 state = drm_atomic_state_alloc(dev);
12078 restore_state = drm_atomic_state_alloc(dev);
12079 if (!state || !restore_state) {
12084 state->acquire_ctx = ctx;
12085 restore_state->acquire_ctx = ctx;
12087 connector_state = drm_atomic_get_connector_state(state, connector);
12088 if (IS_ERR(connector_state)) {
12089 ret = PTR_ERR(connector_state);
12093 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12097 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12098 if (IS_ERR(crtc_state)) {
12099 ret = PTR_ERR(crtc_state);
12103 crtc_state->uapi.active = true;
12105 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12106 &load_detect_mode);
12110 ret = intel_modeset_disable_planes(state, crtc);
12114 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12116 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12118 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12120 drm_dbg_kms(&dev_priv->drm,
12121 "Failed to create a copy of old state to restore: %i\n",
12126 ret = drm_atomic_commit(state);
12128 drm_dbg_kms(&dev_priv->drm,
12129 "failed to set mode on load-detect pipe\n");
12133 old->restore_state = restore_state;
12134 drm_atomic_state_put(state);
12136 /* let the connector get through one full cycle before testing */
12137 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12142 drm_atomic_state_put(state);
12145 if (restore_state) {
12146 drm_atomic_state_put(restore_state);
12147 restore_state = NULL;
12150 if (ret == -EDEADLK)
12156 void intel_release_load_detect_pipe(struct drm_connector *connector,
12157 struct intel_load_detect_pipe *old,
12158 struct drm_modeset_acquire_ctx *ctx)
12160 struct intel_encoder *intel_encoder =
12161 intel_attached_encoder(to_intel_connector(connector));
12162 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12163 struct drm_encoder *encoder = &intel_encoder->base;
12164 struct drm_atomic_state *state = old->restore_state;
12167 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12168 connector->base.id, connector->name,
12169 encoder->base.id, encoder->name);
12174 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12176 drm_dbg_kms(&i915->drm,
12177 "Couldn't release load detect pipe: %i\n", ret);
12178 drm_atomic_state_put(state);
12181 static int i9xx_pll_refclk(struct drm_device *dev,
12182 const struct intel_crtc_state *pipe_config)
12184 struct drm_i915_private *dev_priv = to_i915(dev);
12185 u32 dpll = pipe_config->dpll_hw_state.dpll;
12187 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12188 return dev_priv->vbt.lvds_ssc_freq;
12189 else if (HAS_PCH_SPLIT(dev_priv))
12191 else if (!IS_GEN(dev_priv, 2))
12197 /* Returns the clock of the currently programmed mode of the given pipe. */
12198 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12199 struct intel_crtc_state *pipe_config)
12201 struct drm_device *dev = crtc->base.dev;
12202 struct drm_i915_private *dev_priv = to_i915(dev);
12203 enum pipe pipe = crtc->pipe;
12204 u32 dpll = pipe_config->dpll_hw_state.dpll;
12208 int refclk = i9xx_pll_refclk(dev, pipe_config);
12210 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12211 fp = pipe_config->dpll_hw_state.fp0;
12213 fp = pipe_config->dpll_hw_state.fp1;
12215 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12216 if (IS_PINEVIEW(dev_priv)) {
12217 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12218 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12220 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12221 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12224 if (!IS_GEN(dev_priv, 2)) {
12225 if (IS_PINEVIEW(dev_priv))
12226 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12227 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12229 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12230 DPLL_FPA01_P1_POST_DIV_SHIFT);
12232 switch (dpll & DPLL_MODE_MASK) {
12233 case DPLLB_MODE_DAC_SERIAL:
12234 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12237 case DPLLB_MODE_LVDS:
12238 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12242 drm_dbg_kms(&dev_priv->drm,
12243 "Unknown DPLL mode %08x in programmed "
12244 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12248 if (IS_PINEVIEW(dev_priv))
12249 port_clock = pnv_calc_dpll_params(refclk, &clock);
12251 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12253 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12255 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12258 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12259 DPLL_FPA01_P1_POST_DIV_SHIFT);
12261 if (lvds & LVDS_CLKB_POWER_UP)
12266 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12269 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12270 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12272 if (dpll & PLL_P2_DIVIDE_BY_4)
12278 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12282 * This value includes pixel_multiplier. We will use
12283 * port_clock to compute adjusted_mode.crtc_clock in the
12284 * encoder's get_config() function.
12286 pipe_config->port_clock = port_clock;
12289 int intel_dotclock_calculate(int link_freq,
12290 const struct intel_link_m_n *m_n)
12293 * The calculation for the data clock is:
12294 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12295 * But we want to avoid losing precison if possible, so:
12296 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12298 * and the link clock is simpler:
12299 * link_clock = (m * link_clock) / n
12305 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12308 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12309 struct intel_crtc_state *pipe_config)
12311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12313 /* read out port_clock from the DPLL */
12314 i9xx_crtc_clock_get(crtc, pipe_config);
12317 * In case there is an active pipe without active ports,
12318 * we may need some idea for the dotclock anyway.
12319 * Calculate one based on the FDI configuration.
12321 pipe_config->hw.adjusted_mode.crtc_clock =
12322 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12323 &pipe_config->fdi_m_n);
12326 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12327 struct intel_crtc *crtc)
12329 memset(crtc_state, 0, sizeof(*crtc_state));
12331 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12333 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12334 crtc_state->master_transcoder = INVALID_TRANSCODER;
12335 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12336 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12337 crtc_state->scaler_state.scaler_id = -1;
12338 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12341 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12343 struct intel_crtc_state *crtc_state;
12345 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12348 intel_crtc_state_reset(crtc_state, crtc);
12353 /* Returns the currently programmed mode of the given encoder. */
12354 struct drm_display_mode *
12355 intel_encoder_current_mode(struct intel_encoder *encoder)
12357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12358 struct intel_crtc_state *crtc_state;
12359 struct drm_display_mode *mode;
12360 struct intel_crtc *crtc;
12363 if (!encoder->get_hw_state(encoder, &pipe))
12366 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12368 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12372 crtc_state = intel_crtc_state_alloc(crtc);
12378 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12384 encoder->get_config(encoder, crtc_state);
12386 intel_mode_from_pipe_config(mode, crtc_state);
12393 static void intel_crtc_destroy(struct drm_crtc *crtc)
12395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12397 drm_crtc_cleanup(crtc);
12402 * intel_wm_need_update - Check whether watermarks need updating
12403 * @cur: current plane state
12404 * @new: new plane state
12406 * Check current plane state versus the new one to determine whether
12407 * watermarks need to be recalculated.
12409 * Returns true or false.
12411 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12412 struct intel_plane_state *new)
12414 /* Update watermarks on tiling or size changes. */
12415 if (new->uapi.visible != cur->uapi.visible)
12418 if (!cur->hw.fb || !new->hw.fb)
12421 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12422 cur->hw.rotation != new->hw.rotation ||
12423 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12424 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12425 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12426 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12432 static bool needs_scaling(const struct intel_plane_state *state)
12434 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12435 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12436 int dst_w = drm_rect_width(&state->uapi.dst);
12437 int dst_h = drm_rect_height(&state->uapi.dst);
12439 return (src_w != dst_w || src_h != dst_h);
12442 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12443 struct intel_crtc_state *crtc_state,
12444 const struct intel_plane_state *old_plane_state,
12445 struct intel_plane_state *plane_state)
12447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12448 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12450 bool mode_changed = needs_modeset(crtc_state);
12451 bool was_crtc_enabled = old_crtc_state->hw.active;
12452 bool is_crtc_enabled = crtc_state->hw.active;
12453 bool turn_off, turn_on, visible, was_visible;
12456 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12457 ret = skl_update_scaler_plane(crtc_state, plane_state);
12462 was_visible = old_plane_state->uapi.visible;
12463 visible = plane_state->uapi.visible;
12465 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12466 was_visible = false;
12469 * Visibility is calculated as if the crtc was on, but
12470 * after scaler setup everything depends on it being off
12471 * when the crtc isn't active.
12473 * FIXME this is wrong for watermarks. Watermarks should also
12474 * be computed as if the pipe would be active. Perhaps move
12475 * per-plane wm computation to the .check_plane() hook, and
12476 * only combine the results from all planes in the current place?
12478 if (!is_crtc_enabled) {
12479 intel_plane_set_invisible(crtc_state, plane_state);
12483 if (!was_visible && !visible)
12486 turn_off = was_visible && (!visible || mode_changed);
12487 turn_on = visible && (!was_visible || mode_changed);
12489 drm_dbg_atomic(&dev_priv->drm,
12490 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12491 crtc->base.base.id, crtc->base.name,
12492 plane->base.base.id, plane->base.name,
12493 was_visible, visible,
12494 turn_off, turn_on, mode_changed);
12497 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12498 crtc_state->update_wm_pre = true;
12500 /* must disable cxsr around plane enable/disable */
12501 if (plane->id != PLANE_CURSOR)
12502 crtc_state->disable_cxsr = true;
12503 } else if (turn_off) {
12504 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12505 crtc_state->update_wm_post = true;
12507 /* must disable cxsr around plane enable/disable */
12508 if (plane->id != PLANE_CURSOR)
12509 crtc_state->disable_cxsr = true;
12510 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12511 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12512 /* FIXME bollocks */
12513 crtc_state->update_wm_pre = true;
12514 crtc_state->update_wm_post = true;
12518 if (visible || was_visible)
12519 crtc_state->fb_bits |= plane->frontbuffer_bit;
12522 * ILK/SNB DVSACNTR/Sprite Enable
12523 * IVB SPR_CTL/Sprite Enable
12524 * "When in Self Refresh Big FIFO mode, a write to enable the
12525 * plane will be internally buffered and delayed while Big FIFO
12526 * mode is exiting."
12528 * Which means that enabling the sprite can take an extra frame
12529 * when we start in big FIFO mode (LP1+). Thus we need to drop
12530 * down to LP0 and wait for vblank in order to make sure the
12531 * sprite gets enabled on the next vblank after the register write.
12532 * Doing otherwise would risk enabling the sprite one frame after
12533 * we've already signalled flip completion. We can resume LP1+
12534 * once the sprite has been enabled.
12537 * WaCxSRDisabledForSpriteScaling:ivb
12538 * IVB SPR_SCALE/Scaling Enable
12539 * "Low Power watermarks must be disabled for at least one
12540 * frame before enabling sprite scaling, and kept disabled
12541 * until sprite scaling is disabled."
12543 * ILK/SNB DVSASCALE/Scaling Enable
12544 * "When in Self Refresh Big FIFO mode, scaling enable will be
12545 * masked off while Big FIFO mode is exiting."
12547 * Despite the w/a only being listed for IVB we assume that
12548 * the ILK/SNB note has similar ramifications, hence we apply
12549 * the w/a on all three platforms.
12551 * With experimental results seems this is needed also for primary
12552 * plane, not only sprite plane.
12554 if (plane->id != PLANE_CURSOR &&
12555 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12556 IS_IVYBRIDGE(dev_priv)) &&
12557 (turn_on || (!needs_scaling(old_plane_state) &&
12558 needs_scaling(plane_state))))
12559 crtc_state->disable_lp_wm = true;
12564 static bool encoders_cloneable(const struct intel_encoder *a,
12565 const struct intel_encoder *b)
12567 /* masks could be asymmetric, so check both ways */
12568 return a == b || (a->cloneable & (1 << b->type) &&
12569 b->cloneable & (1 << a->type));
12572 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12573 struct intel_crtc *crtc,
12574 struct intel_encoder *encoder)
12576 struct intel_encoder *source_encoder;
12577 struct drm_connector *connector;
12578 struct drm_connector_state *connector_state;
12581 for_each_new_connector_in_state(state, connector, connector_state, i) {
12582 if (connector_state->crtc != &crtc->base)
12586 to_intel_encoder(connector_state->best_encoder);
12587 if (!encoders_cloneable(encoder, source_encoder))
12594 static int icl_add_linked_planes(struct intel_atomic_state *state)
12596 struct intel_plane *plane, *linked;
12597 struct intel_plane_state *plane_state, *linked_plane_state;
12600 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12601 linked = plane_state->planar_linked_plane;
12606 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12607 if (IS_ERR(linked_plane_state))
12608 return PTR_ERR(linked_plane_state);
12610 drm_WARN_ON(state->base.dev,
12611 linked_plane_state->planar_linked_plane != plane);
12612 drm_WARN_ON(state->base.dev,
12613 linked_plane_state->planar_slave == plane_state->planar_slave);
12619 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12621 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12622 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12623 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12624 struct intel_plane *plane, *linked;
12625 struct intel_plane_state *plane_state;
12628 if (INTEL_GEN(dev_priv) < 11)
12632 * Destroy all old plane links and make the slave plane invisible
12633 * in the crtc_state->active_planes mask.
12635 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12636 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12639 plane_state->planar_linked_plane = NULL;
12640 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12641 crtc_state->active_planes &= ~BIT(plane->id);
12642 crtc_state->update_planes |= BIT(plane->id);
12645 plane_state->planar_slave = false;
12648 if (!crtc_state->nv12_planes)
12651 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12652 struct intel_plane_state *linked_state = NULL;
12654 if (plane->pipe != crtc->pipe ||
12655 !(crtc_state->nv12_planes & BIT(plane->id)))
12658 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12659 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12662 if (crtc_state->active_planes & BIT(linked->id))
12665 linked_state = intel_atomic_get_plane_state(state, linked);
12666 if (IS_ERR(linked_state))
12667 return PTR_ERR(linked_state);
12672 if (!linked_state) {
12673 drm_dbg_kms(&dev_priv->drm,
12674 "Need %d free Y planes for planar YUV\n",
12675 hweight8(crtc_state->nv12_planes));
12680 plane_state->planar_linked_plane = linked;
12682 linked_state->planar_slave = true;
12683 linked_state->planar_linked_plane = plane;
12684 crtc_state->active_planes |= BIT(linked->id);
12685 crtc_state->update_planes |= BIT(linked->id);
12686 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12687 linked->base.name, plane->base.name);
12689 /* Copy parameters to slave plane */
12690 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12691 linked_state->color_ctl = plane_state->color_ctl;
12692 linked_state->view = plane_state->view;
12693 memcpy(linked_state->color_plane, plane_state->color_plane,
12694 sizeof(linked_state->color_plane));
12696 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12697 linked_state->uapi.src = plane_state->uapi.src;
12698 linked_state->uapi.dst = plane_state->uapi.dst;
12700 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12701 if (linked->id == PLANE_SPRITE5)
12702 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12703 else if (linked->id == PLANE_SPRITE4)
12704 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12705 else if (linked->id == PLANE_SPRITE3)
12706 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12707 else if (linked->id == PLANE_SPRITE2)
12708 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12710 MISSING_CASE(linked->id);
12717 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12719 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12720 struct intel_atomic_state *state =
12721 to_intel_atomic_state(new_crtc_state->uapi.state);
12722 const struct intel_crtc_state *old_crtc_state =
12723 intel_atomic_get_old_crtc_state(state, crtc);
12725 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12728 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12730 const struct drm_display_mode *adjusted_mode =
12731 &crtc_state->hw.adjusted_mode;
12734 if (!crtc_state->hw.enable)
12737 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12738 adjusted_mode->crtc_clock);
12740 return min(linetime_wm, 0x1ff);
12743 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12744 const struct intel_cdclk_state *cdclk_state)
12746 const struct drm_display_mode *adjusted_mode =
12747 &crtc_state->hw.adjusted_mode;
12750 if (!crtc_state->hw.enable)
12753 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12754 cdclk_state->logical.cdclk);
12756 return min(linetime_wm, 0x1ff);
12759 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12763 const struct drm_display_mode *adjusted_mode =
12764 &crtc_state->hw.adjusted_mode;
12767 if (!crtc_state->hw.enable)
12770 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12771 crtc_state->pixel_rate);
12773 /* Display WA #1135: BXT:ALL GLK:ALL */
12774 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12777 return min(linetime_wm, 0x1ff);
12780 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12781 struct intel_crtc *crtc)
12783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12784 struct intel_crtc_state *crtc_state =
12785 intel_atomic_get_new_crtc_state(state, crtc);
12786 const struct intel_cdclk_state *cdclk_state;
12788 if (INTEL_GEN(dev_priv) >= 9)
12789 crtc_state->linetime = skl_linetime_wm(crtc_state);
12791 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12793 if (!hsw_crtc_supports_ips(crtc))
12796 cdclk_state = intel_atomic_get_cdclk_state(state);
12797 if (IS_ERR(cdclk_state))
12798 return PTR_ERR(cdclk_state);
12800 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12806 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12807 struct intel_crtc *crtc)
12809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12810 struct intel_crtc_state *crtc_state =
12811 intel_atomic_get_new_crtc_state(state, crtc);
12812 bool mode_changed = needs_modeset(crtc_state);
12815 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12816 mode_changed && !crtc_state->hw.active)
12817 crtc_state->update_wm_post = true;
12819 if (mode_changed && crtc_state->hw.enable &&
12820 dev_priv->display.crtc_compute_clock &&
12821 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12822 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12828 * May need to update pipe gamma enable bits
12829 * when C8 planes are getting enabled/disabled.
12831 if (c8_planes_changed(crtc_state))
12832 crtc_state->uapi.color_mgmt_changed = true;
12834 if (mode_changed || crtc_state->update_pipe ||
12835 crtc_state->uapi.color_mgmt_changed) {
12836 ret = intel_color_check(crtc_state);
12841 if (dev_priv->display.compute_pipe_wm) {
12842 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12844 drm_dbg_kms(&dev_priv->drm,
12845 "Target pipe watermarks are invalid\n");
12850 if (dev_priv->display.compute_intermediate_wm) {
12851 if (drm_WARN_ON(&dev_priv->drm,
12852 !dev_priv->display.compute_pipe_wm))
12856 * Calculate 'intermediate' watermarks that satisfy both the
12857 * old state and the new state. We can program these
12860 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12862 drm_dbg_kms(&dev_priv->drm,
12863 "No valid intermediate pipe watermarks are possible\n");
12868 if (INTEL_GEN(dev_priv) >= 9) {
12869 if (mode_changed || crtc_state->update_pipe) {
12870 ret = skl_update_scaler_crtc(crtc_state);
12875 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12880 if (HAS_IPS(dev_priv)) {
12881 ret = hsw_compute_ips_config(crtc_state);
12886 if (INTEL_GEN(dev_priv) >= 9 ||
12887 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12888 ret = hsw_compute_linetime_wm(state, crtc);
12894 if (!mode_changed) {
12895 ret = intel_psr2_sel_fetch_update(state, crtc);
12903 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12905 struct intel_connector *connector;
12906 struct drm_connector_list_iter conn_iter;
12908 drm_connector_list_iter_begin(dev, &conn_iter);
12909 for_each_intel_connector_iter(connector, &conn_iter) {
12910 if (connector->base.state->crtc)
12911 drm_connector_put(&connector->base);
12913 if (connector->base.encoder) {
12914 connector->base.state->best_encoder =
12915 connector->base.encoder;
12916 connector->base.state->crtc =
12917 connector->base.encoder->crtc;
12919 drm_connector_get(&connector->base);
12921 connector->base.state->best_encoder = NULL;
12922 connector->base.state->crtc = NULL;
12925 drm_connector_list_iter_end(&conn_iter);
12929 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12930 struct intel_crtc_state *pipe_config)
12932 struct drm_connector *connector = conn_state->connector;
12933 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12934 const struct drm_display_info *info = &connector->display_info;
12937 switch (conn_state->max_bpc) {
12954 if (bpp < pipe_config->pipe_bpp) {
12955 drm_dbg_kms(&i915->drm,
12956 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12957 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12958 connector->base.id, connector->name,
12959 bpp, 3 * info->bpc,
12960 3 * conn_state->max_requested_bpc,
12961 pipe_config->pipe_bpp);
12963 pipe_config->pipe_bpp = bpp;
12970 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12971 struct intel_crtc_state *pipe_config)
12973 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12974 struct drm_atomic_state *state = pipe_config->uapi.state;
12975 struct drm_connector *connector;
12976 struct drm_connector_state *connector_state;
12979 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12980 IS_CHERRYVIEW(dev_priv)))
12982 else if (INTEL_GEN(dev_priv) >= 5)
12987 pipe_config->pipe_bpp = bpp;
12989 /* Clamp display bpp to connector max bpp */
12990 for_each_new_connector_in_state(state, connector, connector_state, i) {
12993 if (connector_state->crtc != &crtc->base)
12996 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
13004 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
13005 const struct drm_display_mode *mode)
13007 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
13008 "type: 0x%x flags: 0x%x\n",
13010 mode->crtc_hdisplay, mode->crtc_hsync_start,
13011 mode->crtc_hsync_end, mode->crtc_htotal,
13012 mode->crtc_vdisplay, mode->crtc_vsync_start,
13013 mode->crtc_vsync_end, mode->crtc_vtotal,
13014 mode->type, mode->flags);
13018 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
13019 const char *id, unsigned int lane_count,
13020 const struct intel_link_m_n *m_n)
13022 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13024 drm_dbg_kms(&i915->drm,
13025 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
13027 m_n->gmch_m, m_n->gmch_n,
13028 m_n->link_m, m_n->link_n, m_n->tu);
13032 intel_dump_infoframe(struct drm_i915_private *dev_priv,
13033 const union hdmi_infoframe *frame)
13035 if (!drm_debug_enabled(DRM_UT_KMS))
13038 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
13042 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
13043 const struct drm_dp_vsc_sdp *vsc)
13045 if (!drm_debug_enabled(DRM_UT_KMS))
13048 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
13051 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
13053 static const char * const output_type_str[] = {
13054 OUTPUT_TYPE(UNUSED),
13055 OUTPUT_TYPE(ANALOG),
13059 OUTPUT_TYPE(TVOUT),
13065 OUTPUT_TYPE(DP_MST),
13070 static void snprintf_output_types(char *buf, size_t len,
13071 unsigned int output_types)
13078 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13081 if ((output_types & BIT(i)) == 0)
13084 r = snprintf(str, len, "%s%s",
13085 str != buf ? "," : "", output_type_str[i]);
13091 output_types &= ~BIT(i);
13094 WARN_ON_ONCE(output_types != 0);
13097 static const char * const output_format_str[] = {
13098 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13099 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13100 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13101 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13104 static const char *output_formats(enum intel_output_format format)
13106 if (format >= ARRAY_SIZE(output_format_str))
13107 format = INTEL_OUTPUT_FORMAT_INVALID;
13108 return output_format_str[format];
13111 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13113 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13114 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13115 const struct drm_framebuffer *fb = plane_state->hw.fb;
13116 struct drm_format_name_buf format_name;
13119 drm_dbg_kms(&i915->drm,
13120 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13121 plane->base.base.id, plane->base.name,
13122 yesno(plane_state->uapi.visible));
13126 drm_dbg_kms(&i915->drm,
13127 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13128 plane->base.base.id, plane->base.name,
13129 fb->base.id, fb->width, fb->height,
13130 drm_get_format_name(fb->format->format, &format_name),
13131 yesno(plane_state->uapi.visible));
13132 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13133 plane_state->hw.rotation, plane_state->scaler_id);
13134 if (plane_state->uapi.visible)
13135 drm_dbg_kms(&i915->drm,
13136 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13137 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13138 DRM_RECT_ARG(&plane_state->uapi.dst));
13141 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13142 struct intel_atomic_state *state,
13143 const char *context)
13145 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13146 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13147 const struct intel_plane_state *plane_state;
13148 struct intel_plane *plane;
13152 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13153 crtc->base.base.id, crtc->base.name,
13154 yesno(pipe_config->hw.enable), context);
13156 if (!pipe_config->hw.enable)
13159 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13160 drm_dbg_kms(&dev_priv->drm,
13161 "active: %s, output_types: %s (0x%x), output format: %s\n",
13162 yesno(pipe_config->hw.active),
13163 buf, pipe_config->output_types,
13164 output_formats(pipe_config->output_format));
13166 drm_dbg_kms(&dev_priv->drm,
13167 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13168 transcoder_name(pipe_config->cpu_transcoder),
13169 pipe_config->pipe_bpp, pipe_config->dither);
13171 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13172 transcoder_name(pipe_config->mst_master_transcoder));
13174 drm_dbg_kms(&dev_priv->drm,
13175 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13176 transcoder_name(pipe_config->master_transcoder),
13177 pipe_config->sync_mode_slaves_mask);
13179 if (pipe_config->has_pch_encoder)
13180 intel_dump_m_n_config(pipe_config, "fdi",
13181 pipe_config->fdi_lanes,
13182 &pipe_config->fdi_m_n);
13184 if (intel_crtc_has_dp_encoder(pipe_config)) {
13185 intel_dump_m_n_config(pipe_config, "dp m_n",
13186 pipe_config->lane_count, &pipe_config->dp_m_n);
13187 if (pipe_config->has_drrs)
13188 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13189 pipe_config->lane_count,
13190 &pipe_config->dp_m2_n2);
13193 drm_dbg_kms(&dev_priv->drm,
13194 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13195 pipe_config->has_audio, pipe_config->has_infoframe,
13196 pipe_config->infoframes.enable);
13198 if (pipe_config->infoframes.enable &
13199 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13200 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13201 pipe_config->infoframes.gcp);
13202 if (pipe_config->infoframes.enable &
13203 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13204 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13205 if (pipe_config->infoframes.enable &
13206 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13207 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13208 if (pipe_config->infoframes.enable &
13209 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13210 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13211 if (pipe_config->infoframes.enable &
13212 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13213 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13214 if (pipe_config->infoframes.enable &
13215 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13216 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13217 if (pipe_config->infoframes.enable &
13218 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13219 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13221 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13222 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13223 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13224 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13225 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13226 drm_dbg_kms(&dev_priv->drm,
13227 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13228 pipe_config->port_clock,
13229 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13230 pipe_config->pixel_rate);
13232 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13233 pipe_config->linetime, pipe_config->ips_linetime);
13235 if (INTEL_GEN(dev_priv) >= 9)
13236 drm_dbg_kms(&dev_priv->drm,
13237 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13239 pipe_config->scaler_state.scaler_users,
13240 pipe_config->scaler_state.scaler_id);
13242 if (HAS_GMCH(dev_priv))
13243 drm_dbg_kms(&dev_priv->drm,
13244 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13245 pipe_config->gmch_pfit.control,
13246 pipe_config->gmch_pfit.pgm_ratios,
13247 pipe_config->gmch_pfit.lvds_border_bits);
13249 drm_dbg_kms(&dev_priv->drm,
13250 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13251 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13252 enableddisabled(pipe_config->pch_pfit.enabled),
13253 yesno(pipe_config->pch_pfit.force_thru));
13255 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13256 pipe_config->ips_enabled, pipe_config->double_wide);
13258 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13260 if (IS_CHERRYVIEW(dev_priv))
13261 drm_dbg_kms(&dev_priv->drm,
13262 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13263 pipe_config->cgm_mode, pipe_config->gamma_mode,
13264 pipe_config->gamma_enable, pipe_config->csc_enable);
13266 drm_dbg_kms(&dev_priv->drm,
13267 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13268 pipe_config->csc_mode, pipe_config->gamma_mode,
13269 pipe_config->gamma_enable, pipe_config->csc_enable);
13271 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
13272 pipe_config->hw.degamma_lut ?
13273 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
13274 pipe_config->hw.gamma_lut ?
13275 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
13281 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13282 if (plane->pipe == crtc->pipe)
13283 intel_dump_plane_state(plane_state);
13287 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13289 struct drm_device *dev = state->base.dev;
13290 struct drm_connector *connector;
13291 struct drm_connector_list_iter conn_iter;
13292 unsigned int used_ports = 0;
13293 unsigned int used_mst_ports = 0;
13297 * We're going to peek into connector->state,
13298 * hence connection_mutex must be held.
13300 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13303 * Walk the connector list instead of the encoder
13304 * list to detect the problem on ddi platforms
13305 * where there's just one encoder per digital port.
13307 drm_connector_list_iter_begin(dev, &conn_iter);
13308 drm_for_each_connector_iter(connector, &conn_iter) {
13309 struct drm_connector_state *connector_state;
13310 struct intel_encoder *encoder;
13313 drm_atomic_get_new_connector_state(&state->base,
13315 if (!connector_state)
13316 connector_state = connector->state;
13318 if (!connector_state->best_encoder)
13321 encoder = to_intel_encoder(connector_state->best_encoder);
13323 drm_WARN_ON(dev, !connector_state->crtc);
13325 switch (encoder->type) {
13326 case INTEL_OUTPUT_DDI:
13327 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13330 case INTEL_OUTPUT_DP:
13331 case INTEL_OUTPUT_HDMI:
13332 case INTEL_OUTPUT_EDP:
13333 /* the same port mustn't appear more than once */
13334 if (used_ports & BIT(encoder->port))
13337 used_ports |= BIT(encoder->port);
13339 case INTEL_OUTPUT_DP_MST:
13341 1 << encoder->port;
13347 drm_connector_list_iter_end(&conn_iter);
13349 /* can't mix MST and SST/HDMI on the same port */
13350 if (used_ports & used_mst_ports)
13357 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13359 intel_crtc_copy_color_blobs(crtc_state);
13363 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13365 crtc_state->hw.enable = crtc_state->uapi.enable;
13366 crtc_state->hw.active = crtc_state->uapi.active;
13367 crtc_state->hw.mode = crtc_state->uapi.mode;
13368 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13369 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13372 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13374 crtc_state->uapi.enable = crtc_state->hw.enable;
13375 crtc_state->uapi.active = crtc_state->hw.active;
13376 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13377 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13379 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13381 /* copy color blobs to uapi */
13382 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13383 crtc_state->hw.degamma_lut);
13384 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13385 crtc_state->hw.gamma_lut);
13386 drm_property_replace_blob(&crtc_state->uapi.ctm,
13387 crtc_state->hw.ctm);
13391 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13395 struct intel_crtc_state *saved_state;
13397 saved_state = intel_crtc_state_alloc(crtc);
13401 /* free the old crtc_state->hw members */
13402 intel_crtc_free_hw_state(crtc_state);
13404 /* FIXME: before the switch to atomic started, a new pipe_config was
13405 * kzalloc'd. Code that depends on any field being zero should be
13406 * fixed, so that the crtc_state can be safely duplicated. For now,
13407 * only fields that are know to not cause problems are preserved. */
13409 saved_state->uapi = crtc_state->uapi;
13410 saved_state->scaler_state = crtc_state->scaler_state;
13411 saved_state->shared_dpll = crtc_state->shared_dpll;
13412 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13413 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13414 sizeof(saved_state->icl_port_dplls));
13415 saved_state->crc_enabled = crtc_state->crc_enabled;
13416 if (IS_G4X(dev_priv) ||
13417 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13418 saved_state->wm = crtc_state->wm;
13420 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13421 kfree(saved_state);
13423 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13429 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13431 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13432 struct drm_atomic_state *state = pipe_config->uapi.state;
13433 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13434 struct drm_connector *connector;
13435 struct drm_connector_state *connector_state;
13436 int base_bpp, ret, i;
13439 pipe_config->cpu_transcoder =
13440 (enum transcoder) to_intel_crtc(crtc)->pipe;
13443 * Sanitize sync polarity flags based on requested ones. If neither
13444 * positive or negative polarity is requested, treat this as meaning
13445 * negative polarity.
13447 if (!(pipe_config->hw.adjusted_mode.flags &
13448 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13449 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13451 if (!(pipe_config->hw.adjusted_mode.flags &
13452 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13453 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13455 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13460 base_bpp = pipe_config->pipe_bpp;
13463 * Determine the real pipe dimensions. Note that stereo modes can
13464 * increase the actual pipe size due to the frame doubling and
13465 * insertion of additional space for blanks between the frame. This
13466 * is stored in the crtc timings. We use the requested mode to do this
13467 * computation to clearly distinguish it from the adjusted mode, which
13468 * can be changed by the connectors in the below retry loop.
13470 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13471 &pipe_config->pipe_src_w,
13472 &pipe_config->pipe_src_h);
13474 for_each_new_connector_in_state(state, connector, connector_state, i) {
13475 struct intel_encoder *encoder =
13476 to_intel_encoder(connector_state->best_encoder);
13478 if (connector_state->crtc != crtc)
13481 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13482 drm_dbg_kms(&i915->drm,
13483 "rejecting invalid cloning configuration\n");
13488 * Determine output_types before calling the .compute_config()
13489 * hooks so that the hooks can use this information safely.
13491 if (encoder->compute_output_type)
13492 pipe_config->output_types |=
13493 BIT(encoder->compute_output_type(encoder, pipe_config,
13496 pipe_config->output_types |= BIT(encoder->type);
13500 /* Ensure the port clock defaults are reset when retrying. */
13501 pipe_config->port_clock = 0;
13502 pipe_config->pixel_multiplier = 1;
13504 /* Fill in default crtc timings, allow encoders to overwrite them. */
13505 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13506 CRTC_STEREO_DOUBLE);
13508 /* Pass our mode to the connectors and the CRTC to give them a chance to
13509 * adjust it according to limitations or connector properties, and also
13510 * a chance to reject the mode entirely.
13512 for_each_new_connector_in_state(state, connector, connector_state, i) {
13513 struct intel_encoder *encoder =
13514 to_intel_encoder(connector_state->best_encoder);
13516 if (connector_state->crtc != crtc)
13519 ret = encoder->compute_config(encoder, pipe_config,
13522 if (ret != -EDEADLK)
13523 drm_dbg_kms(&i915->drm,
13524 "Encoder config failure: %d\n",
13530 /* Set default port clock if not overwritten by the encoder. Needs to be
13531 * done afterwards in case the encoder adjusts the mode. */
13532 if (!pipe_config->port_clock)
13533 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13534 * pipe_config->pixel_multiplier;
13536 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13537 if (ret == -EDEADLK)
13540 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13544 if (ret == RETRY) {
13545 if (drm_WARN(&i915->drm, !retry,
13546 "loop in pipe configuration computation\n"))
13549 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13551 goto encoder_retry;
13554 /* Dithering seems to not pass-through bits correctly when it should, so
13555 * only enable it on 6bpc panels and when its not a compliance
13556 * test requesting 6bpc video pattern.
13558 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13559 !pipe_config->dither_force_disable;
13560 drm_dbg_kms(&i915->drm,
13561 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13562 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13565 * Make drm_calc_timestamping_constants in
13566 * drm_atomic_helper_update_legacy_modeset_state() happy
13568 pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13574 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13576 struct intel_atomic_state *state =
13577 to_intel_atomic_state(crtc_state->uapi.state);
13578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13579 struct drm_connector_state *conn_state;
13580 struct drm_connector *connector;
13583 for_each_new_connector_in_state(&state->base, connector,
13585 struct intel_encoder *encoder =
13586 to_intel_encoder(conn_state->best_encoder);
13589 if (conn_state->crtc != &crtc->base ||
13590 !encoder->compute_config_late)
13593 ret = encoder->compute_config_late(encoder, crtc_state,
13602 bool intel_fuzzy_clock_check(int clock1, int clock2)
13606 if (clock1 == clock2)
13609 if (!clock1 || !clock2)
13612 diff = abs(clock1 - clock2);
13614 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13621 intel_compare_m_n(unsigned int m, unsigned int n,
13622 unsigned int m2, unsigned int n2,
13625 if (m == m2 && n == n2)
13628 if (exact || !m || !n || !m2 || !n2)
13631 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13638 } else if (n < n2) {
13648 return intel_fuzzy_clock_check(m, m2);
13652 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13653 const struct intel_link_m_n *m2_n2,
13656 return m_n->tu == m2_n2->tu &&
13657 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13658 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13659 intel_compare_m_n(m_n->link_m, m_n->link_n,
13660 m2_n2->link_m, m2_n2->link_n, exact);
13664 intel_compare_infoframe(const union hdmi_infoframe *a,
13665 const union hdmi_infoframe *b)
13667 return memcmp(a, b, sizeof(*a)) == 0;
13671 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13672 const struct drm_dp_vsc_sdp *b)
13674 return memcmp(a, b, sizeof(*a)) == 0;
13678 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13679 bool fastset, const char *name,
13680 const union hdmi_infoframe *a,
13681 const union hdmi_infoframe *b)
13684 if (!drm_debug_enabled(DRM_UT_KMS))
13687 drm_dbg_kms(&dev_priv->drm,
13688 "fastset mismatch in %s infoframe\n", name);
13689 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13690 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13691 drm_dbg_kms(&dev_priv->drm, "found:\n");
13692 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13694 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13695 drm_err(&dev_priv->drm, "expected:\n");
13696 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13697 drm_err(&dev_priv->drm, "found:\n");
13698 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13703 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13704 bool fastset, const char *name,
13705 const struct drm_dp_vsc_sdp *a,
13706 const struct drm_dp_vsc_sdp *b)
13709 if (!drm_debug_enabled(DRM_UT_KMS))
13712 drm_dbg_kms(&dev_priv->drm,
13713 "fastset mismatch in %s dp sdp\n", name);
13714 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13715 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13716 drm_dbg_kms(&dev_priv->drm, "found:\n");
13717 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13719 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13720 drm_err(&dev_priv->drm, "expected:\n");
13721 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13722 drm_err(&dev_priv->drm, "found:\n");
13723 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13727 static void __printf(4, 5)
13728 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13729 const char *name, const char *format, ...)
13731 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13732 struct va_format vaf;
13735 va_start(args, format);
13740 drm_dbg_kms(&i915->drm,
13741 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13742 crtc->base.base.id, crtc->base.name, name, &vaf);
13744 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13745 crtc->base.base.id, crtc->base.name, name, &vaf);
13750 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13752 if (dev_priv->params.fastboot != -1)
13753 return dev_priv->params.fastboot;
13755 /* Enable fastboot by default on Skylake and newer */
13756 if (INTEL_GEN(dev_priv) >= 9)
13759 /* Enable fastboot by default on VLV and CHV */
13760 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13763 /* Disabled by default on all others */
13768 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13769 const struct intel_crtc_state *pipe_config,
13772 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13773 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13776 bool fixup_inherited = fastset &&
13777 current_config->inherited && !pipe_config->inherited;
13779 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13780 drm_dbg_kms(&dev_priv->drm,
13781 "initial modeset and fastboot not set\n");
13785 #define PIPE_CONF_CHECK_X(name) do { \
13786 if (current_config->name != pipe_config->name) { \
13787 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13788 "(expected 0x%08x, found 0x%08x)", \
13789 current_config->name, \
13790 pipe_config->name); \
13795 #define PIPE_CONF_CHECK_I(name) do { \
13796 if (current_config->name != pipe_config->name) { \
13797 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13798 "(expected %i, found %i)", \
13799 current_config->name, \
13800 pipe_config->name); \
13805 #define PIPE_CONF_CHECK_BOOL(name) do { \
13806 if (current_config->name != pipe_config->name) { \
13807 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13808 "(expected %s, found %s)", \
13809 yesno(current_config->name), \
13810 yesno(pipe_config->name)); \
13816 * Checks state where we only read out the enabling, but not the entire
13817 * state itself (like full infoframes or ELD for audio). These states
13818 * require a full modeset on bootup to fix up.
13820 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13821 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13822 PIPE_CONF_CHECK_BOOL(name); \
13824 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13825 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13826 yesno(current_config->name), \
13827 yesno(pipe_config->name)); \
13832 #define PIPE_CONF_CHECK_P(name) do { \
13833 if (current_config->name != pipe_config->name) { \
13834 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13835 "(expected %p, found %p)", \
13836 current_config->name, \
13837 pipe_config->name); \
13842 #define PIPE_CONF_CHECK_M_N(name) do { \
13843 if (!intel_compare_link_m_n(¤t_config->name, \
13844 &pipe_config->name,\
13846 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13847 "(expected tu %i gmch %i/%i link %i/%i, " \
13848 "found tu %i, gmch %i/%i link %i/%i)", \
13849 current_config->name.tu, \
13850 current_config->name.gmch_m, \
13851 current_config->name.gmch_n, \
13852 current_config->name.link_m, \
13853 current_config->name.link_n, \
13854 pipe_config->name.tu, \
13855 pipe_config->name.gmch_m, \
13856 pipe_config->name.gmch_n, \
13857 pipe_config->name.link_m, \
13858 pipe_config->name.link_n); \
13863 /* This is required for BDW+ where there is only one set of registers for
13864 * switching between high and low RR.
13865 * This macro can be used whenever a comparison has to be made between one
13866 * hw state and multiple sw state variables.
13868 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13869 if (!intel_compare_link_m_n(¤t_config->name, \
13870 &pipe_config->name, !fastset) && \
13871 !intel_compare_link_m_n(¤t_config->alt_name, \
13872 &pipe_config->name, !fastset)) { \
13873 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13874 "(expected tu %i gmch %i/%i link %i/%i, " \
13875 "or tu %i gmch %i/%i link %i/%i, " \
13876 "found tu %i, gmch %i/%i link %i/%i)", \
13877 current_config->name.tu, \
13878 current_config->name.gmch_m, \
13879 current_config->name.gmch_n, \
13880 current_config->name.link_m, \
13881 current_config->name.link_n, \
13882 current_config->alt_name.tu, \
13883 current_config->alt_name.gmch_m, \
13884 current_config->alt_name.gmch_n, \
13885 current_config->alt_name.link_m, \
13886 current_config->alt_name.link_n, \
13887 pipe_config->name.tu, \
13888 pipe_config->name.gmch_m, \
13889 pipe_config->name.gmch_n, \
13890 pipe_config->name.link_m, \
13891 pipe_config->name.link_n); \
13896 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13897 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13898 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13899 "(%x) (expected %i, found %i)", \
13901 current_config->name & (mask), \
13902 pipe_config->name & (mask)); \
13907 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13908 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13909 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13910 "(expected %i, found %i)", \
13911 current_config->name, \
13912 pipe_config->name); \
13917 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13918 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
13919 &pipe_config->infoframes.name)) { \
13920 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13921 ¤t_config->infoframes.name, \
13922 &pipe_config->infoframes.name); \
13927 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13928 if (!current_config->has_psr && !pipe_config->has_psr && \
13929 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
13930 &pipe_config->infoframes.name)) { \
13931 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13932 ¤t_config->infoframes.name, \
13933 &pipe_config->infoframes.name); \
13938 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13939 if (current_config->name1 != pipe_config->name1) { \
13940 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13941 "(expected %i, found %i, won't compare lut values)", \
13942 current_config->name1, \
13943 pipe_config->name1); \
13946 if (!intel_color_lut_equal(current_config->name2, \
13947 pipe_config->name2, pipe_config->name1, \
13948 bit_precision)) { \
13949 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13950 "hw_state doesn't match sw_state"); \
13956 #define PIPE_CONF_QUIRK(quirk) \
13957 ((current_config->quirks | pipe_config->quirks) & (quirk))
13959 PIPE_CONF_CHECK_I(cpu_transcoder);
13961 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13962 PIPE_CONF_CHECK_I(fdi_lanes);
13963 PIPE_CONF_CHECK_M_N(fdi_m_n);
13965 PIPE_CONF_CHECK_I(lane_count);
13966 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13968 if (INTEL_GEN(dev_priv) < 8) {
13969 PIPE_CONF_CHECK_M_N(dp_m_n);
13971 if (current_config->has_drrs)
13972 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13974 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13976 PIPE_CONF_CHECK_X(output_types);
13978 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13979 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13980 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13981 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13982 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13983 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13985 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13986 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13987 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13988 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13989 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13990 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13992 PIPE_CONF_CHECK_I(pixel_multiplier);
13993 PIPE_CONF_CHECK_I(output_format);
13994 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13995 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13996 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13997 PIPE_CONF_CHECK_BOOL(limited_color_range);
13999 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
14000 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
14001 PIPE_CONF_CHECK_BOOL(has_infoframe);
14002 PIPE_CONF_CHECK_BOOL(fec_enable);
14004 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
14006 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14007 DRM_MODE_FLAG_INTERLACE);
14009 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
14010 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14011 DRM_MODE_FLAG_PHSYNC);
14012 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14013 DRM_MODE_FLAG_NHSYNC);
14014 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14015 DRM_MODE_FLAG_PVSYNC);
14016 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14017 DRM_MODE_FLAG_NVSYNC);
14020 PIPE_CONF_CHECK_X(gmch_pfit.control);
14021 /* pfit ratios are autocomputed by the hw on gen4+ */
14022 if (INTEL_GEN(dev_priv) < 4)
14023 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
14024 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
14027 * Changing the EDP transcoder input mux
14028 * (A_ONOFF vs. A_ON) requires a full modeset.
14030 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
14033 PIPE_CONF_CHECK_I(pipe_src_w);
14034 PIPE_CONF_CHECK_I(pipe_src_h);
14036 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
14037 if (current_config->pch_pfit.enabled) {
14038 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
14039 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
14040 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
14041 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
14044 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
14045 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
14047 PIPE_CONF_CHECK_X(gamma_mode);
14048 if (IS_CHERRYVIEW(dev_priv))
14049 PIPE_CONF_CHECK_X(cgm_mode);
14051 PIPE_CONF_CHECK_X(csc_mode);
14052 PIPE_CONF_CHECK_BOOL(gamma_enable);
14053 PIPE_CONF_CHECK_BOOL(csc_enable);
14055 PIPE_CONF_CHECK_I(linetime);
14056 PIPE_CONF_CHECK_I(ips_linetime);
14058 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
14060 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
14063 PIPE_CONF_CHECK_BOOL(double_wide);
14065 PIPE_CONF_CHECK_P(shared_dpll);
14066 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
14067 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
14068 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
14069 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
14070 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
14071 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
14072 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
14073 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
14074 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
14075 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
14076 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
14077 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14078 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14079 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14080 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14081 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14082 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14083 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14084 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14085 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14086 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14087 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14088 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14089 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14090 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14091 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14092 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14093 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14094 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14095 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14096 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14098 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14099 PIPE_CONF_CHECK_X(dsi_pll.div);
14101 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14102 PIPE_CONF_CHECK_I(pipe_bpp);
14104 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14105 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14107 PIPE_CONF_CHECK_I(min_voltage_level);
14109 PIPE_CONF_CHECK_X(infoframes.enable);
14110 PIPE_CONF_CHECK_X(infoframes.gcp);
14111 PIPE_CONF_CHECK_INFOFRAME(avi);
14112 PIPE_CONF_CHECK_INFOFRAME(spd);
14113 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14114 PIPE_CONF_CHECK_INFOFRAME(drm);
14115 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14117 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14118 PIPE_CONF_CHECK_I(master_transcoder);
14120 PIPE_CONF_CHECK_I(dsc.compression_enable);
14121 PIPE_CONF_CHECK_I(dsc.dsc_split);
14122 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14124 PIPE_CONF_CHECK_I(mst_master_transcoder);
14126 #undef PIPE_CONF_CHECK_X
14127 #undef PIPE_CONF_CHECK_I
14128 #undef PIPE_CONF_CHECK_BOOL
14129 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14130 #undef PIPE_CONF_CHECK_P
14131 #undef PIPE_CONF_CHECK_FLAGS
14132 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14133 #undef PIPE_CONF_CHECK_COLOR_LUT
14134 #undef PIPE_CONF_QUIRK
14139 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14140 const struct intel_crtc_state *pipe_config)
14142 if (pipe_config->has_pch_encoder) {
14143 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14144 &pipe_config->fdi_m_n);
14145 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14148 * FDI already provided one idea for the dotclock.
14149 * Yell if the encoder disagrees.
14151 drm_WARN(&dev_priv->drm,
14152 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14153 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14154 fdi_dotclock, dotclock);
14158 static void verify_wm_state(struct intel_crtc *crtc,
14159 struct intel_crtc_state *new_crtc_state)
14161 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14162 struct skl_hw_state {
14163 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14164 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14165 struct skl_pipe_wm wm;
14167 struct skl_pipe_wm *sw_wm;
14168 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14169 u8 hw_enabled_slices;
14170 const enum pipe pipe = crtc->pipe;
14171 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14173 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14176 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14180 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14181 sw_wm = &new_crtc_state->wm.skl.optimal;
14183 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14185 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14187 if (INTEL_GEN(dev_priv) >= 11 &&
14188 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14189 drm_err(&dev_priv->drm,
14190 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14191 dev_priv->dbuf.enabled_slices,
14192 hw_enabled_slices);
14195 for_each_universal_plane(dev_priv, pipe, plane) {
14196 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14198 hw_plane_wm = &hw->wm.planes[plane];
14199 sw_plane_wm = &sw_wm->planes[plane];
14202 for (level = 0; level <= max_level; level++) {
14203 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14204 &sw_plane_wm->wm[level]) ||
14205 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14206 &sw_plane_wm->sagv_wm0)))
14209 drm_err(&dev_priv->drm,
14210 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14211 pipe_name(pipe), plane + 1, level,
14212 sw_plane_wm->wm[level].plane_en,
14213 sw_plane_wm->wm[level].plane_res_b,
14214 sw_plane_wm->wm[level].plane_res_l,
14215 hw_plane_wm->wm[level].plane_en,
14216 hw_plane_wm->wm[level].plane_res_b,
14217 hw_plane_wm->wm[level].plane_res_l);
14220 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14221 &sw_plane_wm->trans_wm)) {
14222 drm_err(&dev_priv->drm,
14223 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14224 pipe_name(pipe), plane + 1,
14225 sw_plane_wm->trans_wm.plane_en,
14226 sw_plane_wm->trans_wm.plane_res_b,
14227 sw_plane_wm->trans_wm.plane_res_l,
14228 hw_plane_wm->trans_wm.plane_en,
14229 hw_plane_wm->trans_wm.plane_res_b,
14230 hw_plane_wm->trans_wm.plane_res_l);
14234 hw_ddb_entry = &hw->ddb_y[plane];
14235 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14237 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14238 drm_err(&dev_priv->drm,
14239 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14240 pipe_name(pipe), plane + 1,
14241 sw_ddb_entry->start, sw_ddb_entry->end,
14242 hw_ddb_entry->start, hw_ddb_entry->end);
14248 * If the cursor plane isn't active, we may not have updated it's ddb
14249 * allocation. In that case since the ddb allocation will be updated
14250 * once the plane becomes visible, we can skip this check
14253 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14255 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14256 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14259 for (level = 0; level <= max_level; level++) {
14260 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14261 &sw_plane_wm->wm[level]) ||
14262 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14263 &sw_plane_wm->sagv_wm0)))
14266 drm_err(&dev_priv->drm,
14267 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14268 pipe_name(pipe), level,
14269 sw_plane_wm->wm[level].plane_en,
14270 sw_plane_wm->wm[level].plane_res_b,
14271 sw_plane_wm->wm[level].plane_res_l,
14272 hw_plane_wm->wm[level].plane_en,
14273 hw_plane_wm->wm[level].plane_res_b,
14274 hw_plane_wm->wm[level].plane_res_l);
14277 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14278 &sw_plane_wm->trans_wm)) {
14279 drm_err(&dev_priv->drm,
14280 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14282 sw_plane_wm->trans_wm.plane_en,
14283 sw_plane_wm->trans_wm.plane_res_b,
14284 sw_plane_wm->trans_wm.plane_res_l,
14285 hw_plane_wm->trans_wm.plane_en,
14286 hw_plane_wm->trans_wm.plane_res_b,
14287 hw_plane_wm->trans_wm.plane_res_l);
14291 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14292 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14294 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14295 drm_err(&dev_priv->drm,
14296 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14298 sw_ddb_entry->start, sw_ddb_entry->end,
14299 hw_ddb_entry->start, hw_ddb_entry->end);
14307 verify_connector_state(struct intel_atomic_state *state,
14308 struct intel_crtc *crtc)
14310 struct drm_connector *connector;
14311 struct drm_connector_state *new_conn_state;
14314 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14315 struct drm_encoder *encoder = connector->encoder;
14316 struct intel_crtc_state *crtc_state = NULL;
14318 if (new_conn_state->crtc != &crtc->base)
14322 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14324 intel_connector_verify_state(crtc_state, new_conn_state);
14326 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14327 "connector's atomic encoder doesn't match legacy encoder\n");
14332 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14334 struct intel_encoder *encoder;
14335 struct drm_connector *connector;
14336 struct drm_connector_state *old_conn_state, *new_conn_state;
14339 for_each_intel_encoder(&dev_priv->drm, encoder) {
14340 bool enabled = false, found = false;
14343 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14344 encoder->base.base.id,
14345 encoder->base.name);
14347 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14348 new_conn_state, i) {
14349 if (old_conn_state->best_encoder == &encoder->base)
14352 if (new_conn_state->best_encoder != &encoder->base)
14354 found = enabled = true;
14356 I915_STATE_WARN(new_conn_state->crtc !=
14357 encoder->base.crtc,
14358 "connector's crtc doesn't match encoder crtc\n");
14364 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14365 "encoder's enabled state mismatch "
14366 "(expected %i, found %i)\n",
14367 !!encoder->base.crtc, enabled);
14369 if (!encoder->base.crtc) {
14372 active = encoder->get_hw_state(encoder, &pipe);
14373 I915_STATE_WARN(active,
14374 "encoder detached but still enabled on pipe %c.\n",
14381 verify_crtc_state(struct intel_crtc *crtc,
14382 struct intel_crtc_state *old_crtc_state,
14383 struct intel_crtc_state *new_crtc_state)
14385 struct drm_device *dev = crtc->base.dev;
14386 struct drm_i915_private *dev_priv = to_i915(dev);
14387 struct intel_encoder *encoder;
14388 struct intel_crtc_state *pipe_config = old_crtc_state;
14389 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14391 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14392 intel_crtc_free_hw_state(old_crtc_state);
14393 intel_crtc_state_reset(old_crtc_state, crtc);
14394 old_crtc_state->uapi.state = state;
14396 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14399 pipe_config->hw.enable = new_crtc_state->hw.enable;
14401 pipe_config->hw.active =
14402 dev_priv->display.get_pipe_config(crtc, pipe_config);
14404 /* we keep both pipes enabled on 830 */
14405 if (IS_I830(dev_priv) && pipe_config->hw.active)
14406 pipe_config->hw.active = new_crtc_state->hw.active;
14408 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14409 "crtc active state doesn't match with hw state "
14410 "(expected %i, found %i)\n",
14411 new_crtc_state->hw.active, pipe_config->hw.active);
14413 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14414 "transitional active state does not match atomic hw state "
14415 "(expected %i, found %i)\n",
14416 new_crtc_state->hw.active, crtc->active);
14418 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14422 active = encoder->get_hw_state(encoder, &pipe);
14423 I915_STATE_WARN(active != new_crtc_state->hw.active,
14424 "[ENCODER:%i] active %i with crtc active %i\n",
14425 encoder->base.base.id, active,
14426 new_crtc_state->hw.active);
14428 I915_STATE_WARN(active && crtc->pipe != pipe,
14429 "Encoder connected to wrong pipe %c\n",
14433 encoder->get_config(encoder, pipe_config);
14436 intel_crtc_compute_pixel_rate(pipe_config);
14438 if (!new_crtc_state->hw.active)
14441 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14443 if (!intel_pipe_config_compare(new_crtc_state,
14444 pipe_config, false)) {
14445 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14446 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14447 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14452 intel_verify_planes(struct intel_atomic_state *state)
14454 struct intel_plane *plane;
14455 const struct intel_plane_state *plane_state;
14458 for_each_new_intel_plane_in_state(state, plane,
14460 assert_plane(plane, plane_state->planar_slave ||
14461 plane_state->uapi.visible);
14465 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14466 struct intel_shared_dpll *pll,
14467 struct intel_crtc *crtc,
14468 struct intel_crtc_state *new_crtc_state)
14470 struct intel_dpll_hw_state dpll_hw_state;
14471 unsigned int crtc_mask;
14474 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14476 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14478 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14480 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14481 I915_STATE_WARN(!pll->on && pll->active_mask,
14482 "pll in active use but not on in sw tracking\n");
14483 I915_STATE_WARN(pll->on && !pll->active_mask,
14484 "pll is on but not used by any active crtc\n");
14485 I915_STATE_WARN(pll->on != active,
14486 "pll on state mismatch (expected %i, found %i)\n",
14491 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14492 "more active pll users than references: %x vs %x\n",
14493 pll->active_mask, pll->state.crtc_mask);
14498 crtc_mask = drm_crtc_mask(&crtc->base);
14500 if (new_crtc_state->hw.active)
14501 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14502 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14503 pipe_name(crtc->pipe), pll->active_mask);
14505 I915_STATE_WARN(pll->active_mask & crtc_mask,
14506 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14507 pipe_name(crtc->pipe), pll->active_mask);
14509 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14510 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14511 crtc_mask, pll->state.crtc_mask);
14513 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14515 sizeof(dpll_hw_state)),
14516 "pll hw state mismatch\n");
14520 verify_shared_dpll_state(struct intel_crtc *crtc,
14521 struct intel_crtc_state *old_crtc_state,
14522 struct intel_crtc_state *new_crtc_state)
14524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14526 if (new_crtc_state->shared_dpll)
14527 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14529 if (old_crtc_state->shared_dpll &&
14530 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14531 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14532 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14534 I915_STATE_WARN(pll->active_mask & crtc_mask,
14535 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14536 pipe_name(crtc->pipe));
14537 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14538 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14539 pipe_name(crtc->pipe));
14544 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14545 struct intel_atomic_state *state,
14546 struct intel_crtc_state *old_crtc_state,
14547 struct intel_crtc_state *new_crtc_state)
14549 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14552 verify_wm_state(crtc, new_crtc_state);
14553 verify_connector_state(state, crtc);
14554 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14555 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14559 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14563 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14564 verify_single_dpll_state(dev_priv,
14565 &dev_priv->dpll.shared_dplls[i],
14570 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14571 struct intel_atomic_state *state)
14573 verify_encoder_state(dev_priv, state);
14574 verify_connector_state(state, NULL);
14575 verify_disabled_dpll_state(dev_priv);
14579 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14581 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14583 const struct drm_display_mode *adjusted_mode =
14584 &crtc_state->hw.adjusted_mode;
14586 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14588 crtc->mode_flags = crtc_state->mode_flags;
14591 * The scanline counter increments at the leading edge of hsync.
14593 * On most platforms it starts counting from vtotal-1 on the
14594 * first active line. That means the scanline counter value is
14595 * always one less than what we would expect. Ie. just after
14596 * start of vblank, which also occurs at start of hsync (on the
14597 * last active line), the scanline counter will read vblank_start-1.
14599 * On gen2 the scanline counter starts counting from 1 instead
14600 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14601 * to keep the value positive), instead of adding one.
14603 * On HSW+ the behaviour of the scanline counter depends on the output
14604 * type. For DP ports it behaves like most other platforms, but on HDMI
14605 * there's an extra 1 line difference. So we need to add two instead of
14606 * one to the value.
14608 * On VLV/CHV DSI the scanline counter would appear to increment
14609 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14610 * that means we can't tell whether we're in vblank or not while
14611 * we're on that particular line. We must still set scanline_offset
14612 * to 1 so that the vblank timestamps come out correct when we query
14613 * the scanline counter from within the vblank interrupt handler.
14614 * However if queried just before the start of vblank we'll get an
14615 * answer that's slightly in the future.
14617 if (IS_GEN(dev_priv, 2)) {
14620 vtotal = adjusted_mode->crtc_vtotal;
14621 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14624 crtc->scanline_offset = vtotal - 1;
14625 } else if (HAS_DDI(dev_priv) &&
14626 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14627 crtc->scanline_offset = 2;
14629 crtc->scanline_offset = 1;
14633 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14635 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14636 struct intel_crtc_state *new_crtc_state;
14637 struct intel_crtc *crtc;
14640 if (!dev_priv->display.crtc_compute_clock)
14643 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14644 if (!needs_modeset(new_crtc_state))
14647 intel_release_shared_dplls(state, crtc);
14652 * This implements the workaround described in the "notes" section of the mode
14653 * set sequence documentation. When going from no pipes or single pipe to
14654 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14655 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14657 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14659 struct intel_crtc_state *crtc_state;
14660 struct intel_crtc *crtc;
14661 struct intel_crtc_state *first_crtc_state = NULL;
14662 struct intel_crtc_state *other_crtc_state = NULL;
14663 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14666 /* look at all crtc's that are going to be enabled in during modeset */
14667 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14668 if (!crtc_state->hw.active ||
14669 !needs_modeset(crtc_state))
14672 if (first_crtc_state) {
14673 other_crtc_state = crtc_state;
14676 first_crtc_state = crtc_state;
14677 first_pipe = crtc->pipe;
14681 /* No workaround needed? */
14682 if (!first_crtc_state)
14685 /* w/a possibly needed, check how many crtc's are already enabled. */
14686 for_each_intel_crtc(state->base.dev, crtc) {
14687 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14688 if (IS_ERR(crtc_state))
14689 return PTR_ERR(crtc_state);
14691 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14693 if (!crtc_state->hw.active ||
14694 needs_modeset(crtc_state))
14697 /* 2 or more enabled crtcs means no need for w/a */
14698 if (enabled_pipe != INVALID_PIPE)
14701 enabled_pipe = crtc->pipe;
14704 if (enabled_pipe != INVALID_PIPE)
14705 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14706 else if (other_crtc_state)
14707 other_crtc_state->hsw_workaround_pipe = first_pipe;
14712 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14715 const struct intel_crtc_state *crtc_state;
14716 struct intel_crtc *crtc;
14719 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14720 if (crtc_state->hw.active)
14721 active_pipes |= BIT(crtc->pipe);
14723 active_pipes &= ~BIT(crtc->pipe);
14726 return active_pipes;
14729 static int intel_modeset_checks(struct intel_atomic_state *state)
14731 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14733 state->modeset = true;
14735 if (IS_HASWELL(dev_priv))
14736 return hsw_mode_set_planes_workaround(state);
14742 * Handle calculation of various watermark data at the end of the atomic check
14743 * phase. The code here should be run after the per-crtc and per-plane 'check'
14744 * handlers to ensure that all derived state has been updated.
14746 static int calc_watermark_data(struct intel_atomic_state *state)
14748 struct drm_device *dev = state->base.dev;
14749 struct drm_i915_private *dev_priv = to_i915(dev);
14751 /* Is there platform-specific watermark information to calculate? */
14752 if (dev_priv->display.compute_global_watermarks)
14753 return dev_priv->display.compute_global_watermarks(state);
14758 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14759 struct intel_crtc_state *new_crtc_state)
14761 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14764 new_crtc_state->uapi.mode_changed = false;
14765 new_crtc_state->update_pipe = true;
14768 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14769 struct intel_crtc_state *new_crtc_state)
14772 * If we're not doing the full modeset we want to
14773 * keep the current M/N values as they may be
14774 * sufficiently different to the computed values
14775 * to cause problems.
14777 * FIXME: should really copy more fuzzy state here
14779 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14780 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14781 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14782 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14785 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14786 struct intel_crtc *crtc,
14789 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14790 struct intel_plane *plane;
14792 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14793 struct intel_plane_state *plane_state;
14795 if ((plane_ids_mask & BIT(plane->id)) == 0)
14798 plane_state = intel_atomic_get_plane_state(state, plane);
14799 if (IS_ERR(plane_state))
14800 return PTR_ERR(plane_state);
14806 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14808 /* See {hsw,vlv,ivb}_plane_ratio() */
14809 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14810 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14811 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14814 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14816 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14817 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14818 struct intel_plane_state *plane_state;
14819 struct intel_plane *plane;
14820 struct intel_crtc *crtc;
14823 ret = icl_add_linked_planes(state);
14827 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14828 ret = intel_plane_atomic_check(state, plane);
14830 drm_dbg_atomic(&dev_priv->drm,
14831 "[PLANE:%d:%s] atomic driver check failed\n",
14832 plane->base.base.id, plane->base.name);
14837 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14838 new_crtc_state, i) {
14839 u8 old_active_planes, new_active_planes;
14841 ret = icl_check_nv12_planes(new_crtc_state);
14846 * On some platforms the number of active planes affects
14847 * the planes' minimum cdclk calculation. Add such planes
14848 * to the state before we compute the minimum cdclk.
14850 if (!active_planes_affects_min_cdclk(dev_priv))
14853 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14854 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14857 * Not only the number of planes, but if the plane configuration had
14858 * changed might already mean we need to recompute min CDCLK,
14859 * because different planes might consume different amount of Dbuf bandwidth
14860 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14862 if (old_active_planes == new_active_planes)
14865 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14873 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14874 bool *need_cdclk_calc)
14876 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14877 const struct intel_cdclk_state *old_cdclk_state;
14878 const struct intel_cdclk_state *new_cdclk_state;
14879 struct intel_plane_state *plane_state;
14880 struct intel_bw_state *new_bw_state;
14881 struct intel_plane *plane;
14887 * active_planes bitmask has been updated, and potentially
14888 * affected planes are part of the state. We can now
14889 * compute the minimum cdclk for each plane.
14891 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14892 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14897 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14898 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14900 if (new_cdclk_state &&
14901 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14902 *need_cdclk_calc = true;
14904 ret = dev_priv->display.bw_calc_min_cdclk(state);
14908 new_bw_state = intel_atomic_get_new_bw_state(state);
14910 if (!new_cdclk_state || !new_bw_state)
14913 for_each_pipe(dev_priv, pipe) {
14914 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14917 * Currently do this change only if we need to increase
14919 if (new_bw_state->min_cdclk > min_cdclk)
14920 *need_cdclk_calc = true;
14926 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14928 struct intel_crtc_state *crtc_state;
14929 struct intel_crtc *crtc;
14932 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14933 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14936 ret = intel_crtc_atomic_check(state, crtc);
14938 drm_dbg_atomic(&i915->drm,
14939 "[CRTC:%d:%s] atomic driver check failed\n",
14940 crtc->base.base.id, crtc->base.name);
14948 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14951 const struct intel_crtc_state *new_crtc_state;
14952 struct intel_crtc *crtc;
14955 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14956 if (new_crtc_state->hw.enable &&
14957 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14958 needs_modeset(new_crtc_state))
14966 * DOC: asynchronous flip implementation
14968 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
14969 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
14970 * Correspondingly, support is currently added for primary plane only.
14972 * Async flip can only change the plane surface address, so anything else
14973 * changing is rejected from the intel_atomic_check_async() function.
14974 * Once this check is cleared, flip done interrupt is enabled using
14975 * the skl_enable_flip_done() function.
14977 * As soon as the surface address register is written, flip done interrupt is
14978 * generated and the requested events are sent to the usersapce in the interrupt
14979 * handler itself. The timestamp and sequence sent during the flip done event
14980 * correspond to the last vblank and have no relation to the actual time when
14981 * the flip done event was sent.
14983 static int intel_atomic_check_async(struct intel_atomic_state *state)
14985 struct drm_i915_private *i915 = to_i915(state->base.dev);
14986 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14987 const struct intel_plane_state *new_plane_state, *old_plane_state;
14988 struct intel_crtc *crtc;
14989 struct intel_plane *plane;
14992 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14993 new_crtc_state, i) {
14994 if (needs_modeset(new_crtc_state)) {
14995 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
14999 if (!new_crtc_state->hw.active) {
15000 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
15003 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
15004 drm_dbg_kms(&i915->drm,
15005 "Active planes cannot be changed during async flip\n");
15010 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15011 new_plane_state, i) {
15013 * TODO: Async flip is only supported through the page flip IOCTL
15014 * as of now. So support currently added for primary plane only.
15015 * Support for other planes on platforms on which supports
15016 * this(vlv/chv and icl+) should be added when async flip is
15017 * enabled in the atomic IOCTL path.
15019 if (plane->id != PLANE_PRIMARY)
15023 * FIXME: This check is kept generic for all platforms.
15024 * Need to verify this for all gen9 and gen10 platforms to enable
15025 * this selectively if required.
15027 switch (new_plane_state->hw.fb->modifier) {
15028 case I915_FORMAT_MOD_X_TILED:
15029 case I915_FORMAT_MOD_Y_TILED:
15030 case I915_FORMAT_MOD_Yf_TILED:
15033 drm_dbg_kms(&i915->drm,
15034 "Linear memory/CCS does not support async flips\n");
15038 if (old_plane_state->color_plane[0].stride !=
15039 new_plane_state->color_plane[0].stride) {
15040 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
15044 if (old_plane_state->hw.fb->modifier !=
15045 new_plane_state->hw.fb->modifier) {
15046 drm_dbg_kms(&i915->drm,
15047 "Framebuffer modifiers cannot be changed in async flip\n");
15051 if (old_plane_state->hw.fb->format !=
15052 new_plane_state->hw.fb->format) {
15053 drm_dbg_kms(&i915->drm,
15054 "Framebuffer format cannot be changed in async flip\n");
15058 if (old_plane_state->hw.rotation !=
15059 new_plane_state->hw.rotation) {
15060 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
15064 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
15065 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
15066 drm_dbg_kms(&i915->drm,
15067 "Plane size/co-ordinates cannot be changed in async flip\n");
15071 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
15072 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
15076 if (old_plane_state->hw.pixel_blend_mode !=
15077 new_plane_state->hw.pixel_blend_mode) {
15078 drm_dbg_kms(&i915->drm,
15079 "Pixel blend mode cannot be changed in async flip\n");
15083 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
15084 drm_dbg_kms(&i915->drm,
15085 "Color encoding cannot be changed in async flip\n");
15089 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
15090 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
15099 * intel_atomic_check - validate state object
15101 * @_state: state to validate
15103 static int intel_atomic_check(struct drm_device *dev,
15104 struct drm_atomic_state *_state)
15106 struct drm_i915_private *dev_priv = to_i915(dev);
15107 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15108 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15109 struct intel_crtc *crtc;
15111 bool any_ms = false;
15113 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15114 new_crtc_state, i) {
15115 if (new_crtc_state->inherited != old_crtc_state->inherited)
15116 new_crtc_state->uapi.mode_changed = true;
15119 ret = drm_atomic_helper_check_modeset(dev, &state->base);
15123 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15124 new_crtc_state, i) {
15125 if (!needs_modeset(new_crtc_state)) {
15127 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
15132 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
15136 if (!new_crtc_state->hw.enable)
15139 ret = intel_modeset_pipe_config(new_crtc_state);
15144 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15145 new_crtc_state, i) {
15146 if (!needs_modeset(new_crtc_state))
15149 ret = intel_modeset_pipe_config_late(new_crtc_state);
15153 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
15157 * Check if fastset is allowed by external dependencies like other
15158 * pipes and transcoders.
15160 * Right now it only forces a fullmodeset when the MST master
15161 * transcoder did not changed but the pipe of the master transcoder
15162 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
15163 * in case of port synced crtcs, if one of the synced crtcs
15164 * needs a full modeset, all other synced crtcs should be
15165 * forced a full modeset.
15167 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15168 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
15171 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
15172 enum transcoder master = new_crtc_state->mst_master_transcoder;
15174 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
15175 new_crtc_state->uapi.mode_changed = true;
15176 new_crtc_state->update_pipe = false;
15180 if (is_trans_port_sync_mode(new_crtc_state)) {
15181 u8 trans = new_crtc_state->sync_mode_slaves_mask;
15183 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
15184 trans |= BIT(new_crtc_state->master_transcoder);
15186 if (intel_cpu_transcoders_need_modeset(state, trans)) {
15187 new_crtc_state->uapi.mode_changed = true;
15188 new_crtc_state->update_pipe = false;
15193 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15194 new_crtc_state, i) {
15195 if (needs_modeset(new_crtc_state)) {
15200 if (!new_crtc_state->update_pipe)
15203 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
15206 if (any_ms && !check_digital_port_conflicts(state)) {
15207 drm_dbg_kms(&dev_priv->drm,
15208 "rejecting conflicting digital port configuration\n");
15213 ret = drm_dp_mst_atomic_check(&state->base);
15217 ret = intel_atomic_check_planes(state);
15222 * distrust_bios_wm will force a full dbuf recomputation
15223 * but the hardware state will only get updated accordingly
15224 * if state->modeset==true. Hence distrust_bios_wm==true &&
15225 * state->modeset==false is an invalid combination which
15226 * would cause the hardware and software dbuf state to get
15227 * out of sync. We must prevent that.
15229 * FIXME clean up this mess and introduce better
15230 * state tracking for dbuf.
15232 if (dev_priv->wm.distrust_bios_wm)
15235 intel_fbc_choose_crtc(dev_priv, state);
15236 ret = calc_watermark_data(state);
15240 ret = intel_bw_atomic_check(state);
15244 ret = intel_atomic_check_cdclk(state, &any_ms);
15249 ret = intel_modeset_checks(state);
15253 ret = intel_modeset_calc_cdclk(state);
15257 intel_modeset_clear_plls(state);
15260 ret = intel_atomic_check_crtcs(state);
15264 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15265 new_crtc_state, i) {
15266 if (new_crtc_state->uapi.async_flip) {
15267 ret = intel_atomic_check_async(state);
15272 if (!needs_modeset(new_crtc_state) &&
15273 !new_crtc_state->update_pipe)
15276 intel_dump_pipe_config(new_crtc_state, state,
15277 needs_modeset(new_crtc_state) ?
15278 "[modeset]" : "[fastset]");
15284 if (ret == -EDEADLK)
15288 * FIXME would probably be nice to know which crtc specifically
15289 * caused the failure, in cases where we can pinpoint it.
15291 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15293 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15298 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15300 struct intel_crtc_state *crtc_state;
15301 struct intel_crtc *crtc;
15304 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15308 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15309 bool mode_changed = needs_modeset(crtc_state);
15311 if (mode_changed || crtc_state->update_pipe ||
15312 crtc_state->uapi.color_mgmt_changed) {
15313 intel_dsb_prepare(crtc_state);
15320 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15322 struct drm_device *dev = crtc->base.dev;
15323 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15325 if (!vblank->max_vblank_count)
15326 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15328 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15331 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15332 struct intel_crtc_state *crtc_state)
15334 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15336 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15337 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15339 if (crtc_state->has_pch_encoder) {
15340 enum pipe pch_transcoder =
15341 intel_crtc_pch_transcoder(crtc);
15343 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15347 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15348 const struct intel_crtc_state *new_crtc_state)
15350 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15351 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15354 * Update pipe size and adjust fitter if needed: the reason for this is
15355 * that in compute_mode_changes we check the native mode (not the pfit
15356 * mode) to see if we can flip rather than do a full mode set. In the
15357 * fastboot case, we'll flip, but if we don't update the pipesrc and
15358 * pfit state, we'll end up with a big fb scanned out into the wrong
15361 intel_set_pipe_src_size(new_crtc_state);
15363 /* on skylake this is done by detaching scalers */
15364 if (INTEL_GEN(dev_priv) >= 9) {
15365 skl_detach_scalers(new_crtc_state);
15367 if (new_crtc_state->pch_pfit.enabled)
15368 skl_pfit_enable(new_crtc_state);
15369 } else if (HAS_PCH_SPLIT(dev_priv)) {
15370 if (new_crtc_state->pch_pfit.enabled)
15371 ilk_pfit_enable(new_crtc_state);
15372 else if (old_crtc_state->pch_pfit.enabled)
15373 ilk_pfit_disable(old_crtc_state);
15377 * The register is supposedly single buffered so perhaps
15378 * not 100% correct to do this here. But SKL+ calculate
15379 * this based on the adjust pixel rate so pfit changes do
15380 * affect it and so it must be updated for fastsets.
15381 * HSW/BDW only really need this here for fastboot, after
15382 * that the value should not change without a full modeset.
15384 if (INTEL_GEN(dev_priv) >= 9 ||
15385 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15386 hsw_set_linetime_wm(new_crtc_state);
15388 if (INTEL_GEN(dev_priv) >= 11)
15389 icl_set_pipe_chicken(crtc);
15392 static void commit_pipe_config(struct intel_atomic_state *state,
15393 struct intel_crtc *crtc)
15395 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15396 const struct intel_crtc_state *old_crtc_state =
15397 intel_atomic_get_old_crtc_state(state, crtc);
15398 const struct intel_crtc_state *new_crtc_state =
15399 intel_atomic_get_new_crtc_state(state, crtc);
15400 bool modeset = needs_modeset(new_crtc_state);
15403 * During modesets pipe configuration was programmed as the
15404 * CRTC was enabled.
15407 if (new_crtc_state->uapi.color_mgmt_changed ||
15408 new_crtc_state->update_pipe)
15409 intel_color_commit(new_crtc_state);
15411 if (INTEL_GEN(dev_priv) >= 9)
15412 skl_detach_scalers(new_crtc_state);
15414 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15415 bdw_set_pipemisc(new_crtc_state);
15417 if (new_crtc_state->update_pipe)
15418 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15420 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15423 if (dev_priv->display.atomic_update_watermarks)
15424 dev_priv->display.atomic_update_watermarks(state, crtc);
15427 static void intel_enable_crtc(struct intel_atomic_state *state,
15428 struct intel_crtc *crtc)
15430 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15431 const struct intel_crtc_state *new_crtc_state =
15432 intel_atomic_get_new_crtc_state(state, crtc);
15434 if (!needs_modeset(new_crtc_state))
15437 intel_crtc_update_active_timings(new_crtc_state);
15439 dev_priv->display.crtc_enable(state, crtc);
15441 /* vblanks work again, re-enable pipe CRC. */
15442 intel_crtc_enable_pipe_crc(crtc);
15445 static void intel_update_crtc(struct intel_atomic_state *state,
15446 struct intel_crtc *crtc)
15448 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15449 const struct intel_crtc_state *old_crtc_state =
15450 intel_atomic_get_old_crtc_state(state, crtc);
15451 struct intel_crtc_state *new_crtc_state =
15452 intel_atomic_get_new_crtc_state(state, crtc);
15453 bool modeset = needs_modeset(new_crtc_state);
15456 if (new_crtc_state->preload_luts &&
15457 (new_crtc_state->uapi.color_mgmt_changed ||
15458 new_crtc_state->update_pipe))
15459 intel_color_load_luts(new_crtc_state);
15461 intel_pre_plane_update(state, crtc);
15463 if (new_crtc_state->update_pipe)
15464 intel_encoders_update_pipe(state, crtc);
15467 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15468 intel_fbc_disable(crtc);
15470 intel_fbc_enable(state, crtc);
15472 /* Perform vblank evasion around commit operation */
15473 intel_pipe_update_start(new_crtc_state);
15475 commit_pipe_config(state, crtc);
15477 if (INTEL_GEN(dev_priv) >= 9)
15478 skl_update_planes_on_crtc(state, crtc);
15480 i9xx_update_planes_on_crtc(state, crtc);
15482 intel_pipe_update_end(new_crtc_state);
15485 * We usually enable FIFO underrun interrupts as part of the
15486 * CRTC enable sequence during modesets. But when we inherit a
15487 * valid pipe configuration from the BIOS we need to take care
15488 * of enabling them on the CRTC's first fastset.
15490 if (new_crtc_state->update_pipe && !modeset &&
15491 old_crtc_state->inherited)
15492 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15496 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15497 struct intel_crtc_state *old_crtc_state,
15498 struct intel_crtc_state *new_crtc_state,
15499 struct intel_crtc *crtc)
15501 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15503 intel_crtc_disable_planes(state, crtc);
15506 * We need to disable pipe CRC before disabling the pipe,
15507 * or we race against vblank off.
15509 intel_crtc_disable_pipe_crc(crtc);
15511 dev_priv->display.crtc_disable(state, crtc);
15512 crtc->active = false;
15513 intel_fbc_disable(crtc);
15514 intel_disable_shared_dpll(old_crtc_state);
15516 /* FIXME unify this for all platforms */
15517 if (!new_crtc_state->hw.active &&
15518 !HAS_GMCH(dev_priv) &&
15519 dev_priv->display.initial_watermarks)
15520 dev_priv->display.initial_watermarks(state, crtc);
15523 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15525 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15526 struct intel_crtc *crtc;
15530 /* Only disable port sync and MST slaves */
15531 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15532 new_crtc_state, i) {
15533 if (!needs_modeset(new_crtc_state))
15536 if (!old_crtc_state->hw.active)
15539 /* In case of Transcoder port Sync master slave CRTCs can be
15540 * assigned in any order and we need to make sure that
15541 * slave CRTCs are disabled first and then master CRTC since
15542 * Slave vblanks are masked till Master Vblanks.
15544 if (!is_trans_port_sync_slave(old_crtc_state) &&
15545 !intel_dp_mst_is_slave_trans(old_crtc_state))
15548 intel_pre_plane_update(state, crtc);
15549 intel_old_crtc_state_disables(state, old_crtc_state,
15550 new_crtc_state, crtc);
15551 handled |= BIT(crtc->pipe);
15554 /* Disable everything else left on */
15555 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15556 new_crtc_state, i) {
15557 if (!needs_modeset(new_crtc_state) ||
15558 (handled & BIT(crtc->pipe)))
15561 intel_pre_plane_update(state, crtc);
15562 if (old_crtc_state->hw.active)
15563 intel_old_crtc_state_disables(state, old_crtc_state,
15564 new_crtc_state, crtc);
15568 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15570 struct intel_crtc_state *new_crtc_state;
15571 struct intel_crtc *crtc;
15574 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15575 if (!new_crtc_state->hw.active)
15578 intel_enable_crtc(state, crtc);
15579 intel_update_crtc(state, crtc);
15583 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15585 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15586 struct intel_crtc *crtc;
15587 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15588 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15589 u8 update_pipes = 0, modeset_pipes = 0;
15592 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15593 enum pipe pipe = crtc->pipe;
15595 if (!new_crtc_state->hw.active)
15598 /* ignore allocations for crtc's that have been turned off. */
15599 if (!needs_modeset(new_crtc_state)) {
15600 entries[pipe] = old_crtc_state->wm.skl.ddb;
15601 update_pipes |= BIT(pipe);
15603 modeset_pipes |= BIT(pipe);
15608 * Whenever the number of active pipes changes, we need to make sure we
15609 * update the pipes in the right order so that their ddb allocations
15610 * never overlap with each other between CRTC updates. Otherwise we'll
15611 * cause pipe underruns and other bad stuff.
15613 * So first lets enable all pipes that do not need a fullmodeset as
15614 * those don't have any external dependency.
15616 while (update_pipes) {
15617 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15618 new_crtc_state, i) {
15619 enum pipe pipe = crtc->pipe;
15621 if ((update_pipes & BIT(pipe)) == 0)
15624 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15625 entries, I915_MAX_PIPES, pipe))
15628 entries[pipe] = new_crtc_state->wm.skl.ddb;
15629 update_pipes &= ~BIT(pipe);
15631 intel_update_crtc(state, crtc);
15634 * If this is an already active pipe, it's DDB changed,
15635 * and this isn't the last pipe that needs updating
15636 * then we need to wait for a vblank to pass for the
15637 * new ddb allocation to take effect.
15639 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15640 &old_crtc_state->wm.skl.ddb) &&
15641 (update_pipes | modeset_pipes))
15642 intel_wait_for_vblank(dev_priv, pipe);
15646 update_pipes = modeset_pipes;
15649 * Enable all pipes that needs a modeset and do not depends on other
15652 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15653 enum pipe pipe = crtc->pipe;
15655 if ((modeset_pipes & BIT(pipe)) == 0)
15658 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15659 is_trans_port_sync_master(new_crtc_state))
15662 modeset_pipes &= ~BIT(pipe);
15664 intel_enable_crtc(state, crtc);
15668 * Then we enable all remaining pipes that depend on other
15669 * pipes: MST slaves and port sync masters.
15671 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15672 enum pipe pipe = crtc->pipe;
15674 if ((modeset_pipes & BIT(pipe)) == 0)
15677 modeset_pipes &= ~BIT(pipe);
15679 intel_enable_crtc(state, crtc);
15683 * Finally we do the plane updates/etc. for all pipes that got enabled.
15685 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15686 enum pipe pipe = crtc->pipe;
15688 if ((update_pipes & BIT(pipe)) == 0)
15691 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15692 entries, I915_MAX_PIPES, pipe));
15694 entries[pipe] = new_crtc_state->wm.skl.ddb;
15695 update_pipes &= ~BIT(pipe);
15697 intel_update_crtc(state, crtc);
15700 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15701 drm_WARN_ON(&dev_priv->drm, update_pipes);
15704 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15706 struct intel_atomic_state *state, *next;
15707 struct llist_node *freed;
15709 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15710 llist_for_each_entry_safe(state, next, freed, freed)
15711 drm_atomic_state_put(&state->base);
15714 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15716 struct drm_i915_private *dev_priv =
15717 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15719 intel_atomic_helper_free_state(dev_priv);
15722 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15724 struct wait_queue_entry wait_fence, wait_reset;
15725 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15727 init_wait_entry(&wait_fence, 0);
15728 init_wait_entry(&wait_reset, 0);
15730 prepare_to_wait(&intel_state->commit_ready.wait,
15731 &wait_fence, TASK_UNINTERRUPTIBLE);
15732 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15733 I915_RESET_MODESET),
15734 &wait_reset, TASK_UNINTERRUPTIBLE);
15737 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15738 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15743 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15744 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15745 I915_RESET_MODESET),
15749 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15751 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15752 struct intel_crtc *crtc;
15755 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15757 intel_dsb_cleanup(old_crtc_state);
15760 static void intel_atomic_cleanup_work(struct work_struct *work)
15762 struct intel_atomic_state *state =
15763 container_of(work, struct intel_atomic_state, base.commit_work);
15764 struct drm_i915_private *i915 = to_i915(state->base.dev);
15766 intel_cleanup_dsbs(state);
15767 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15768 drm_atomic_helper_commit_cleanup_done(&state->base);
15769 drm_atomic_state_put(&state->base);
15771 intel_atomic_helper_free_state(i915);
15774 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15776 struct drm_device *dev = state->base.dev;
15777 struct drm_i915_private *dev_priv = to_i915(dev);
15778 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15779 struct intel_crtc *crtc;
15780 u64 put_domains[I915_MAX_PIPES] = {};
15781 intel_wakeref_t wakeref = 0;
15784 intel_atomic_commit_fence_wait(state);
15786 drm_atomic_helper_wait_for_dependencies(&state->base);
15788 if (state->modeset)
15789 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15791 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15792 new_crtc_state, i) {
15793 if (needs_modeset(new_crtc_state) ||
15794 new_crtc_state->update_pipe) {
15796 put_domains[crtc->pipe] =
15797 modeset_get_crtc_power_domains(new_crtc_state);
15801 intel_commit_modeset_disables(state);
15803 /* FIXME: Eventually get rid of our crtc->config pointer */
15804 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15805 crtc->config = new_crtc_state;
15807 if (state->modeset) {
15808 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15810 intel_set_cdclk_pre_plane_update(state);
15812 intel_modeset_verify_disabled(dev_priv, state);
15815 intel_sagv_pre_plane_update(state);
15817 /* Complete the events for pipes that have now been disabled */
15818 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15819 bool modeset = needs_modeset(new_crtc_state);
15821 /* Complete events for now disable pipes here. */
15822 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15823 spin_lock_irq(&dev->event_lock);
15824 drm_crtc_send_vblank_event(&crtc->base,
15825 new_crtc_state->uapi.event);
15826 spin_unlock_irq(&dev->event_lock);
15828 new_crtc_state->uapi.event = NULL;
15832 if (state->modeset)
15833 intel_encoders_update_prepare(state);
15835 intel_dbuf_pre_plane_update(state);
15837 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15838 if (new_crtc_state->uapi.async_flip)
15839 skl_enable_flip_done(crtc);
15842 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15843 dev_priv->display.commit_modeset_enables(state);
15845 if (state->modeset) {
15846 intel_encoders_update_complete(state);
15848 intel_set_cdclk_post_plane_update(state);
15851 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15852 * already, but still need the state for the delayed optimization. To
15854 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15855 * - schedule that vblank worker _before_ calling hw_done
15856 * - at the start of commit_tail, cancel it _synchrously
15857 * - switch over to the vblank wait helper in the core after that since
15858 * we don't need out special handling any more.
15860 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15862 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15863 if (new_crtc_state->uapi.async_flip)
15864 skl_disable_flip_done(crtc);
15866 if (new_crtc_state->hw.active &&
15867 !needs_modeset(new_crtc_state) &&
15868 !new_crtc_state->preload_luts &&
15869 (new_crtc_state->uapi.color_mgmt_changed ||
15870 new_crtc_state->update_pipe))
15871 intel_color_load_luts(new_crtc_state);
15875 * Now that the vblank has passed, we can go ahead and program the
15876 * optimal watermarks on platforms that need two-step watermark
15879 * TODO: Move this (and other cleanup) to an async worker eventually.
15881 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15882 new_crtc_state, i) {
15884 * Gen2 reports pipe underruns whenever all planes are disabled.
15885 * So re-enable underrun reporting after some planes get enabled.
15887 * We do this before .optimize_watermarks() so that we have a
15888 * chance of catching underruns with the intermediate watermarks
15889 * vs. the new plane configuration.
15891 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15892 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15894 if (dev_priv->display.optimize_watermarks)
15895 dev_priv->display.optimize_watermarks(state, crtc);
15898 intel_dbuf_post_plane_update(state);
15900 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15901 intel_post_plane_update(state, crtc);
15903 if (put_domains[i])
15904 modeset_put_power_domains(dev_priv, put_domains[i]);
15906 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15909 * DSB cleanup is done in cleanup_work aligning with framebuffer
15910 * cleanup. So copy and reset the dsb structure to sync with
15911 * commit_done and later do dsb cleanup in cleanup_work.
15913 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15916 /* Underruns don't always raise interrupts, so check manually */
15917 intel_check_cpu_fifo_underruns(dev_priv);
15918 intel_check_pch_fifo_underruns(dev_priv);
15920 if (state->modeset)
15921 intel_verify_planes(state);
15923 intel_sagv_post_plane_update(state);
15925 drm_atomic_helper_commit_hw_done(&state->base);
15927 if (state->modeset) {
15928 /* As one of the primary mmio accessors, KMS has a high
15929 * likelihood of triggering bugs in unclaimed access. After we
15930 * finish modesetting, see if an error has been flagged, and if
15931 * so enable debugging for the next modeset - and hope we catch
15934 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15935 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15937 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15940 * Defer the cleanup of the old state to a separate worker to not
15941 * impede the current task (userspace for blocking modesets) that
15942 * are executed inline. For out-of-line asynchronous modesets/flips,
15943 * deferring to a new worker seems overkill, but we would place a
15944 * schedule point (cond_resched()) here anyway to keep latencies
15947 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15948 queue_work(system_highpri_wq, &state->base.commit_work);
15951 static void intel_atomic_commit_work(struct work_struct *work)
15953 struct intel_atomic_state *state =
15954 container_of(work, struct intel_atomic_state, base.commit_work);
15956 intel_atomic_commit_tail(state);
15959 static int __i915_sw_fence_call
15960 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15961 enum i915_sw_fence_notify notify)
15963 struct intel_atomic_state *state =
15964 container_of(fence, struct intel_atomic_state, commit_ready);
15967 case FENCE_COMPLETE:
15968 /* we do blocking waits in the worker, nothing to do here */
15972 struct intel_atomic_helper *helper =
15973 &to_i915(state->base.dev)->atomic_helper;
15975 if (llist_add(&state->freed, &helper->free_list))
15976 schedule_work(&helper->free_work);
15981 return NOTIFY_DONE;
15984 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15986 struct intel_plane_state *old_plane_state, *new_plane_state;
15987 struct intel_plane *plane;
15990 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15991 new_plane_state, i)
15992 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15993 to_intel_frontbuffer(new_plane_state->hw.fb),
15994 plane->frontbuffer_bit);
15997 static int intel_atomic_commit(struct drm_device *dev,
15998 struct drm_atomic_state *_state,
16001 struct intel_atomic_state *state = to_intel_atomic_state(_state);
16002 struct drm_i915_private *dev_priv = to_i915(dev);
16005 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
16007 drm_atomic_state_get(&state->base);
16008 i915_sw_fence_init(&state->commit_ready,
16009 intel_atomic_commit_ready);
16012 * The intel_legacy_cursor_update() fast path takes care
16013 * of avoiding the vblank waits for simple cursor
16014 * movement and flips. For cursor on/off and size changes,
16015 * we want to perform the vblank waits so that watermark
16016 * updates happen during the correct frames. Gen9+ have
16017 * double buffered watermarks and so shouldn't need this.
16019 * Unset state->legacy_cursor_update before the call to
16020 * drm_atomic_helper_setup_commit() because otherwise
16021 * drm_atomic_helper_wait_for_flip_done() is a noop and
16022 * we get FIFO underruns because we didn't wait
16025 * FIXME doing watermarks and fb cleanup from a vblank worker
16026 * (assuming we had any) would solve these problems.
16028 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
16029 struct intel_crtc_state *new_crtc_state;
16030 struct intel_crtc *crtc;
16033 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16034 if (new_crtc_state->wm.need_postvbl_update ||
16035 new_crtc_state->update_wm_post)
16036 state->base.legacy_cursor_update = false;
16039 ret = intel_atomic_prepare_commit(state);
16041 drm_dbg_atomic(&dev_priv->drm,
16042 "Preparing state failed with %i\n", ret);
16043 i915_sw_fence_commit(&state->commit_ready);
16044 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16048 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
16050 ret = drm_atomic_helper_swap_state(&state->base, true);
16052 intel_atomic_swap_global_state(state);
16055 struct intel_crtc_state *new_crtc_state;
16056 struct intel_crtc *crtc;
16059 i915_sw_fence_commit(&state->commit_ready);
16061 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16062 intel_dsb_cleanup(new_crtc_state);
16064 drm_atomic_helper_cleanup_planes(dev, &state->base);
16065 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16068 dev_priv->wm.distrust_bios_wm = false;
16069 intel_shared_dpll_swap_state(state);
16070 intel_atomic_track_fbs(state);
16072 drm_atomic_state_get(&state->base);
16073 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
16075 i915_sw_fence_commit(&state->commit_ready);
16076 if (nonblock && state->modeset) {
16077 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
16078 } else if (nonblock) {
16079 queue_work(dev_priv->flip_wq, &state->base.commit_work);
16081 if (state->modeset)
16082 flush_workqueue(dev_priv->modeset_wq);
16083 intel_atomic_commit_tail(state);
16089 struct wait_rps_boost {
16090 struct wait_queue_entry wait;
16092 struct drm_crtc *crtc;
16093 struct i915_request *request;
16096 static int do_rps_boost(struct wait_queue_entry *_wait,
16097 unsigned mode, int sync, void *key)
16099 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
16100 struct i915_request *rq = wait->request;
16103 * If we missed the vblank, but the request is already running it
16104 * is reasonable to assume that it will complete before the next
16105 * vblank without our intervention, so leave RPS alone.
16107 if (!i915_request_started(rq))
16108 intel_rps_boost(rq);
16109 i915_request_put(rq);
16111 drm_crtc_vblank_put(wait->crtc);
16113 list_del(&wait->wait.entry);
16118 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
16119 struct dma_fence *fence)
16121 struct wait_rps_boost *wait;
16123 if (!dma_fence_is_i915(fence))
16126 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
16129 if (drm_crtc_vblank_get(crtc))
16132 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
16134 drm_crtc_vblank_put(crtc);
16138 wait->request = to_request(dma_fence_get(fence));
16141 wait->wait.func = do_rps_boost;
16142 wait->wait.flags = 0;
16144 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
16147 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
16149 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
16150 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16151 struct drm_framebuffer *fb = plane_state->hw.fb;
16152 struct i915_vma *vma;
16154 if (plane->id == PLANE_CURSOR &&
16155 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
16156 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16157 const int align = intel_cursor_alignment(dev_priv);
16160 err = i915_gem_object_attach_phys(obj, align);
16165 vma = intel_pin_and_fence_fb_obj(fb,
16166 &plane_state->view,
16167 intel_plane_uses_fence(plane_state),
16168 &plane_state->flags);
16170 return PTR_ERR(vma);
16172 plane_state->vma = vma;
16177 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
16179 struct i915_vma *vma;
16181 vma = fetch_and_zero(&old_plane_state->vma);
16183 intel_unpin_fb_vma(vma, old_plane_state->flags);
16186 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
16188 struct i915_sched_attr attr = {
16189 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
16192 i915_gem_object_wait_priority(obj, 0, &attr);
16196 * intel_prepare_plane_fb - Prepare fb for usage on plane
16197 * @_plane: drm plane to prepare for
16198 * @_new_plane_state: the plane state being prepared
16200 * Prepares a framebuffer for usage on a display plane. Generally this
16201 * involves pinning the underlying object and updating the frontbuffer tracking
16202 * bits. Some older platforms need special physical address handling for
16205 * Returns 0 on success, negative error code on failure.
16208 intel_prepare_plane_fb(struct drm_plane *_plane,
16209 struct drm_plane_state *_new_plane_state)
16211 struct intel_plane *plane = to_intel_plane(_plane);
16212 struct intel_plane_state *new_plane_state =
16213 to_intel_plane_state(_new_plane_state);
16214 struct intel_atomic_state *state =
16215 to_intel_atomic_state(new_plane_state->uapi.state);
16216 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16217 const struct intel_plane_state *old_plane_state =
16218 intel_atomic_get_old_plane_state(state, plane);
16219 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
16220 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
16224 const struct intel_crtc_state *crtc_state =
16225 intel_atomic_get_new_crtc_state(state,
16226 to_intel_crtc(old_plane_state->hw.crtc));
16228 /* Big Hammer, we also need to ensure that any pending
16229 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16230 * current scanout is retired before unpinning the old
16231 * framebuffer. Note that we rely on userspace rendering
16232 * into the buffer attached to the pipe they are waiting
16233 * on. If not, userspace generates a GPU hang with IPEHR
16234 * point to the MI_WAIT_FOR_EVENT.
16236 * This should only fail upon a hung GPU, in which case we
16237 * can safely continue.
16239 if (needs_modeset(crtc_state)) {
16240 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16241 old_obj->base.resv, NULL,
16249 if (new_plane_state->uapi.fence) { /* explicit fencing */
16250 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16251 new_plane_state->uapi.fence,
16252 i915_fence_timeout(dev_priv),
16261 ret = i915_gem_object_pin_pages(obj);
16265 ret = intel_plane_pin_fb(new_plane_state);
16267 i915_gem_object_unpin_pages(obj);
16271 fb_obj_bump_render_priority(obj);
16272 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16274 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16275 struct dma_fence *fence;
16277 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16278 obj->base.resv, NULL,
16280 i915_fence_timeout(dev_priv),
16285 fence = dma_resv_get_excl_rcu(obj->base.resv);
16287 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16289 dma_fence_put(fence);
16292 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16293 new_plane_state->uapi.fence);
16297 * We declare pageflips to be interactive and so merit a small bias
16298 * towards upclocking to deliver the frame on time. By only changing
16299 * the RPS thresholds to sample more regularly and aim for higher
16300 * clocks we can hopefully deliver low power workloads (like kodi)
16301 * that are not quite steady state without resorting to forcing
16302 * maximum clocks following a vblank miss (see do_rps_boost()).
16304 if (!state->rps_interactive) {
16305 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16306 state->rps_interactive = true;
16312 intel_plane_unpin_fb(new_plane_state);
16318 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16319 * @plane: drm plane to clean up for
16320 * @_old_plane_state: the state from the previous modeset
16322 * Cleans up a framebuffer that has just been removed from a plane.
16325 intel_cleanup_plane_fb(struct drm_plane *plane,
16326 struct drm_plane_state *_old_plane_state)
16328 struct intel_plane_state *old_plane_state =
16329 to_intel_plane_state(_old_plane_state);
16330 struct intel_atomic_state *state =
16331 to_intel_atomic_state(old_plane_state->uapi.state);
16332 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16333 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16338 if (state->rps_interactive) {
16339 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16340 state->rps_interactive = false;
16343 /* Should only be called after a successful intel_prepare_plane_fb()! */
16344 intel_plane_unpin_fb(old_plane_state);
16348 * intel_plane_destroy - destroy a plane
16349 * @plane: plane to destroy
16351 * Common destruction function for all types of planes (primary, cursor,
16354 void intel_plane_destroy(struct drm_plane *plane)
16356 drm_plane_cleanup(plane);
16357 kfree(to_intel_plane(plane));
16360 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16361 u32 format, u64 modifier)
16363 switch (modifier) {
16364 case DRM_FORMAT_MOD_LINEAR:
16365 case I915_FORMAT_MOD_X_TILED:
16372 case DRM_FORMAT_C8:
16373 case DRM_FORMAT_RGB565:
16374 case DRM_FORMAT_XRGB1555:
16375 case DRM_FORMAT_XRGB8888:
16376 return modifier == DRM_FORMAT_MOD_LINEAR ||
16377 modifier == I915_FORMAT_MOD_X_TILED;
16383 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16384 u32 format, u64 modifier)
16386 switch (modifier) {
16387 case DRM_FORMAT_MOD_LINEAR:
16388 case I915_FORMAT_MOD_X_TILED:
16395 case DRM_FORMAT_C8:
16396 case DRM_FORMAT_RGB565:
16397 case DRM_FORMAT_XRGB8888:
16398 case DRM_FORMAT_XBGR8888:
16399 case DRM_FORMAT_ARGB8888:
16400 case DRM_FORMAT_ABGR8888:
16401 case DRM_FORMAT_XRGB2101010:
16402 case DRM_FORMAT_XBGR2101010:
16403 case DRM_FORMAT_ARGB2101010:
16404 case DRM_FORMAT_ABGR2101010:
16405 case DRM_FORMAT_XBGR16161616F:
16406 return modifier == DRM_FORMAT_MOD_LINEAR ||
16407 modifier == I915_FORMAT_MOD_X_TILED;
16413 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16414 u32 format, u64 modifier)
16416 return modifier == DRM_FORMAT_MOD_LINEAR &&
16417 format == DRM_FORMAT_ARGB8888;
16420 static const struct drm_plane_funcs i965_plane_funcs = {
16421 .update_plane = drm_atomic_helper_update_plane,
16422 .disable_plane = drm_atomic_helper_disable_plane,
16423 .destroy = intel_plane_destroy,
16424 .atomic_duplicate_state = intel_plane_duplicate_state,
16425 .atomic_destroy_state = intel_plane_destroy_state,
16426 .format_mod_supported = i965_plane_format_mod_supported,
16429 static const struct drm_plane_funcs i8xx_plane_funcs = {
16430 .update_plane = drm_atomic_helper_update_plane,
16431 .disable_plane = drm_atomic_helper_disable_plane,
16432 .destroy = intel_plane_destroy,
16433 .atomic_duplicate_state = intel_plane_duplicate_state,
16434 .atomic_destroy_state = intel_plane_destroy_state,
16435 .format_mod_supported = i8xx_plane_format_mod_supported,
16439 intel_legacy_cursor_update(struct drm_plane *_plane,
16440 struct drm_crtc *_crtc,
16441 struct drm_framebuffer *fb,
16442 int crtc_x, int crtc_y,
16443 unsigned int crtc_w, unsigned int crtc_h,
16444 u32 src_x, u32 src_y,
16445 u32 src_w, u32 src_h,
16446 struct drm_modeset_acquire_ctx *ctx)
16448 struct intel_plane *plane = to_intel_plane(_plane);
16449 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16450 struct intel_plane_state *old_plane_state =
16451 to_intel_plane_state(plane->base.state);
16452 struct intel_plane_state *new_plane_state;
16453 struct intel_crtc_state *crtc_state =
16454 to_intel_crtc_state(crtc->base.state);
16455 struct intel_crtc_state *new_crtc_state;
16459 * When crtc is inactive or there is a modeset pending,
16460 * wait for it to complete in the slowpath
16462 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16463 crtc_state->update_pipe)
16467 * Don't do an async update if there is an outstanding commit modifying
16468 * the plane. This prevents our async update's changes from getting
16469 * overridden by a previous synchronous update's state.
16471 if (old_plane_state->uapi.commit &&
16472 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16476 * If any parameters change that may affect watermarks,
16477 * take the slowpath. Only changing fb or position should be
16480 if (old_plane_state->uapi.crtc != &crtc->base ||
16481 old_plane_state->uapi.src_w != src_w ||
16482 old_plane_state->uapi.src_h != src_h ||
16483 old_plane_state->uapi.crtc_w != crtc_w ||
16484 old_plane_state->uapi.crtc_h != crtc_h ||
16485 !old_plane_state->uapi.fb != !fb)
16488 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16489 if (!new_plane_state)
16492 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16493 if (!new_crtc_state) {
16498 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16500 new_plane_state->uapi.src_x = src_x;
16501 new_plane_state->uapi.src_y = src_y;
16502 new_plane_state->uapi.src_w = src_w;
16503 new_plane_state->uapi.src_h = src_h;
16504 new_plane_state->uapi.crtc_x = crtc_x;
16505 new_plane_state->uapi.crtc_y = crtc_y;
16506 new_plane_state->uapi.crtc_w = crtc_w;
16507 new_plane_state->uapi.crtc_h = crtc_h;
16509 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16511 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16512 old_plane_state, new_plane_state);
16516 ret = intel_plane_pin_fb(new_plane_state);
16520 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16522 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16523 to_intel_frontbuffer(new_plane_state->hw.fb),
16524 plane->frontbuffer_bit);
16526 /* Swap plane state */
16527 plane->base.state = &new_plane_state->uapi;
16530 * We cannot swap crtc_state as it may be in use by an atomic commit or
16531 * page flip that's running simultaneously. If we swap crtc_state and
16532 * destroy the old state, we will cause a use-after-free there.
16534 * Only update active_planes, which is needed for our internal
16535 * bookkeeping. Either value will do the right thing when updating
16536 * planes atomically. If the cursor was part of the atomic update then
16537 * we would have taken the slowpath.
16539 crtc_state->active_planes = new_crtc_state->active_planes;
16541 if (new_plane_state->uapi.visible)
16542 intel_update_plane(plane, crtc_state, new_plane_state);
16544 intel_disable_plane(plane, crtc_state);
16546 intel_plane_unpin_fb(old_plane_state);
16549 if (new_crtc_state)
16550 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16552 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16554 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16558 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16559 crtc_x, crtc_y, crtc_w, crtc_h,
16560 src_x, src_y, src_w, src_h, ctx);
16563 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16564 .update_plane = intel_legacy_cursor_update,
16565 .disable_plane = drm_atomic_helper_disable_plane,
16566 .destroy = intel_plane_destroy,
16567 .atomic_duplicate_state = intel_plane_duplicate_state,
16568 .atomic_destroy_state = intel_plane_destroy_state,
16569 .format_mod_supported = intel_cursor_format_mod_supported,
16572 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16573 enum i9xx_plane_id i9xx_plane)
16575 if (!HAS_FBC(dev_priv))
16578 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16579 return i9xx_plane == PLANE_A; /* tied to pipe A */
16580 else if (IS_IVYBRIDGE(dev_priv))
16581 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16582 i9xx_plane == PLANE_C;
16583 else if (INTEL_GEN(dev_priv) >= 4)
16584 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16586 return i9xx_plane == PLANE_A;
16589 static struct intel_plane *
16590 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16592 struct intel_plane *plane;
16593 const struct drm_plane_funcs *plane_funcs;
16594 unsigned int supported_rotations;
16595 const u32 *formats;
16599 if (INTEL_GEN(dev_priv) >= 9)
16600 return skl_universal_plane_create(dev_priv, pipe,
16603 plane = intel_plane_alloc();
16607 plane->pipe = pipe;
16609 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16610 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16612 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16613 INTEL_NUM_PIPES(dev_priv) == 2)
16614 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16616 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16617 plane->id = PLANE_PRIMARY;
16618 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16620 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16621 if (plane->has_fbc) {
16622 struct intel_fbc *fbc = &dev_priv->fbc;
16624 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16627 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16628 formats = vlv_primary_formats;
16629 num_formats = ARRAY_SIZE(vlv_primary_formats);
16630 } else if (INTEL_GEN(dev_priv) >= 4) {
16632 * WaFP16GammaEnabling:ivb
16633 * "Workaround : When using the 64-bit format, the plane
16634 * output on each color channel has one quarter amplitude.
16635 * It can be brought up to full amplitude by using pipe
16636 * gamma correction or pipe color space conversion to
16637 * multiply the plane output by four."
16639 * There is no dedicated plane gamma for the primary plane,
16640 * and using the pipe gamma/csc could conflict with other
16641 * planes, so we choose not to expose fp16 on IVB primary
16642 * planes. HSW primary planes no longer have this problem.
16644 if (IS_IVYBRIDGE(dev_priv)) {
16645 formats = ivb_primary_formats;
16646 num_formats = ARRAY_SIZE(ivb_primary_formats);
16648 formats = i965_primary_formats;
16649 num_formats = ARRAY_SIZE(i965_primary_formats);
16652 formats = i8xx_primary_formats;
16653 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16656 if (INTEL_GEN(dev_priv) >= 4)
16657 plane_funcs = &i965_plane_funcs;
16659 plane_funcs = &i8xx_plane_funcs;
16661 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16662 plane->min_cdclk = vlv_plane_min_cdclk;
16663 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16664 plane->min_cdclk = hsw_plane_min_cdclk;
16665 else if (IS_IVYBRIDGE(dev_priv))
16666 plane->min_cdclk = ivb_plane_min_cdclk;
16668 plane->min_cdclk = i9xx_plane_min_cdclk;
16670 plane->max_stride = i9xx_plane_max_stride;
16671 plane->update_plane = i9xx_update_plane;
16672 plane->disable_plane = i9xx_disable_plane;
16673 plane->get_hw_state = i9xx_plane_get_hw_state;
16674 plane->check_plane = i9xx_plane_check;
16676 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16677 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16679 formats, num_formats,
16680 i9xx_format_modifiers,
16681 DRM_PLANE_TYPE_PRIMARY,
16682 "primary %c", pipe_name(pipe));
16684 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16686 formats, num_formats,
16687 i9xx_format_modifiers,
16688 DRM_PLANE_TYPE_PRIMARY,
16690 plane_name(plane->i9xx_plane));
16694 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16695 supported_rotations =
16696 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16697 DRM_MODE_REFLECT_X;
16698 } else if (INTEL_GEN(dev_priv) >= 4) {
16699 supported_rotations =
16700 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16702 supported_rotations = DRM_MODE_ROTATE_0;
16705 if (INTEL_GEN(dev_priv) >= 4)
16706 drm_plane_create_rotation_property(&plane->base,
16708 supported_rotations);
16711 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16713 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16718 intel_plane_free(plane);
16720 return ERR_PTR(ret);
16723 static struct intel_plane *
16724 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16727 struct intel_plane *cursor;
16730 cursor = intel_plane_alloc();
16731 if (IS_ERR(cursor))
16734 cursor->pipe = pipe;
16735 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16736 cursor->id = PLANE_CURSOR;
16737 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16739 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16740 cursor->max_stride = i845_cursor_max_stride;
16741 cursor->update_plane = i845_update_cursor;
16742 cursor->disable_plane = i845_disable_cursor;
16743 cursor->get_hw_state = i845_cursor_get_hw_state;
16744 cursor->check_plane = i845_check_cursor;
16746 cursor->max_stride = i9xx_cursor_max_stride;
16747 cursor->update_plane = i9xx_update_cursor;
16748 cursor->disable_plane = i9xx_disable_cursor;
16749 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16750 cursor->check_plane = i9xx_check_cursor;
16753 cursor->cursor.base = ~0;
16754 cursor->cursor.cntl = ~0;
16756 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16757 cursor->cursor.size = ~0;
16759 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16760 0, &intel_cursor_plane_funcs,
16761 intel_cursor_formats,
16762 ARRAY_SIZE(intel_cursor_formats),
16763 cursor_format_modifiers,
16764 DRM_PLANE_TYPE_CURSOR,
16765 "cursor %c", pipe_name(pipe));
16769 if (INTEL_GEN(dev_priv) >= 4)
16770 drm_plane_create_rotation_property(&cursor->base,
16772 DRM_MODE_ROTATE_0 |
16773 DRM_MODE_ROTATE_180);
16775 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16776 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16778 if (INTEL_GEN(dev_priv) >= 12)
16779 drm_plane_enable_fb_damage_clips(&cursor->base);
16781 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16786 intel_plane_free(cursor);
16788 return ERR_PTR(ret);
16791 #define INTEL_CRTC_FUNCS \
16792 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16793 .set_config = drm_atomic_helper_set_config, \
16794 .destroy = intel_crtc_destroy, \
16795 .page_flip = drm_atomic_helper_page_flip, \
16796 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16797 .atomic_destroy_state = intel_crtc_destroy_state, \
16798 .set_crc_source = intel_crtc_set_crc_source, \
16799 .verify_crc_source = intel_crtc_verify_crc_source, \
16800 .get_crc_sources = intel_crtc_get_crc_sources
16802 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16805 .get_vblank_counter = g4x_get_vblank_counter,
16806 .enable_vblank = bdw_enable_vblank,
16807 .disable_vblank = bdw_disable_vblank,
16808 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16811 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16814 .get_vblank_counter = g4x_get_vblank_counter,
16815 .enable_vblank = ilk_enable_vblank,
16816 .disable_vblank = ilk_disable_vblank,
16817 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16820 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16823 .get_vblank_counter = g4x_get_vblank_counter,
16824 .enable_vblank = i965_enable_vblank,
16825 .disable_vblank = i965_disable_vblank,
16826 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16829 static const struct drm_crtc_funcs i965_crtc_funcs = {
16832 .get_vblank_counter = i915_get_vblank_counter,
16833 .enable_vblank = i965_enable_vblank,
16834 .disable_vblank = i965_disable_vblank,
16835 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16838 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16841 .get_vblank_counter = i915_get_vblank_counter,
16842 .enable_vblank = i915gm_enable_vblank,
16843 .disable_vblank = i915gm_disable_vblank,
16844 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16847 static const struct drm_crtc_funcs i915_crtc_funcs = {
16850 .get_vblank_counter = i915_get_vblank_counter,
16851 .enable_vblank = i8xx_enable_vblank,
16852 .disable_vblank = i8xx_disable_vblank,
16853 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16856 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16859 /* no hw vblank counter */
16860 .enable_vblank = i8xx_enable_vblank,
16861 .disable_vblank = i8xx_disable_vblank,
16862 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16865 static struct intel_crtc *intel_crtc_alloc(void)
16867 struct intel_crtc_state *crtc_state;
16868 struct intel_crtc *crtc;
16870 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16872 return ERR_PTR(-ENOMEM);
16874 crtc_state = intel_crtc_state_alloc(crtc);
16877 return ERR_PTR(-ENOMEM);
16880 crtc->base.state = &crtc_state->uapi;
16881 crtc->config = crtc_state;
16886 static void intel_crtc_free(struct intel_crtc *crtc)
16888 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16892 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16894 struct intel_plane *plane;
16896 for_each_intel_plane(&dev_priv->drm, plane) {
16897 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16900 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16904 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16906 struct intel_plane *primary, *cursor;
16907 const struct drm_crtc_funcs *funcs;
16908 struct intel_crtc *crtc;
16911 crtc = intel_crtc_alloc();
16913 return PTR_ERR(crtc);
16916 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16918 primary = intel_primary_plane_create(dev_priv, pipe);
16919 if (IS_ERR(primary)) {
16920 ret = PTR_ERR(primary);
16923 crtc->plane_ids_mask |= BIT(primary->id);
16925 for_each_sprite(dev_priv, pipe, sprite) {
16926 struct intel_plane *plane;
16928 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16929 if (IS_ERR(plane)) {
16930 ret = PTR_ERR(plane);
16933 crtc->plane_ids_mask |= BIT(plane->id);
16936 cursor = intel_cursor_plane_create(dev_priv, pipe);
16937 if (IS_ERR(cursor)) {
16938 ret = PTR_ERR(cursor);
16941 crtc->plane_ids_mask |= BIT(cursor->id);
16943 if (HAS_GMCH(dev_priv)) {
16944 if (IS_CHERRYVIEW(dev_priv) ||
16945 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16946 funcs = &g4x_crtc_funcs;
16947 else if (IS_GEN(dev_priv, 4))
16948 funcs = &i965_crtc_funcs;
16949 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16950 funcs = &i915gm_crtc_funcs;
16951 else if (IS_GEN(dev_priv, 3))
16952 funcs = &i915_crtc_funcs;
16954 funcs = &i8xx_crtc_funcs;
16956 if (INTEL_GEN(dev_priv) >= 8)
16957 funcs = &bdw_crtc_funcs;
16959 funcs = &ilk_crtc_funcs;
16962 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16963 &primary->base, &cursor->base,
16964 funcs, "pipe %c", pipe_name(pipe));
16968 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16969 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16970 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16972 if (INTEL_GEN(dev_priv) < 9) {
16973 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16975 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16976 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16977 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16980 intel_color_init(crtc);
16982 intel_crtc_crc_init(crtc);
16984 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16989 intel_crtc_free(crtc);
16994 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16995 struct drm_file *file)
16997 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16998 struct drm_crtc *drmmode_crtc;
16999 struct intel_crtc *crtc;
17001 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
17005 crtc = to_intel_crtc(drmmode_crtc);
17006 pipe_from_crtc_id->pipe = crtc->pipe;
17011 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
17013 struct drm_device *dev = encoder->base.dev;
17014 struct intel_encoder *source_encoder;
17015 u32 possible_clones = 0;
17017 for_each_intel_encoder(dev, source_encoder) {
17018 if (encoders_cloneable(encoder, source_encoder))
17019 possible_clones |= drm_encoder_mask(&source_encoder->base);
17022 return possible_clones;
17025 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
17027 struct drm_device *dev = encoder->base.dev;
17028 struct intel_crtc *crtc;
17029 u32 possible_crtcs = 0;
17031 for_each_intel_crtc(dev, crtc) {
17032 if (encoder->pipe_mask & BIT(crtc->pipe))
17033 possible_crtcs |= drm_crtc_mask(&crtc->base);
17036 return possible_crtcs;
17039 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
17041 if (!IS_MOBILE(dev_priv))
17044 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
17047 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
17053 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
17055 if (INTEL_GEN(dev_priv) >= 9)
17058 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
17061 if (HAS_PCH_LPT_H(dev_priv) &&
17062 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
17065 /* DDI E can't be used if DDI A requires 4 lanes */
17066 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
17069 if (!dev_priv->vbt.int_crt_support)
17075 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
17080 if (HAS_DDI(dev_priv))
17083 * This w/a is needed at least on CPT/PPT, but to be sure apply it
17084 * everywhere where registers can be write protected.
17086 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17091 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
17092 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
17094 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
17095 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
17099 static void intel_pps_init(struct drm_i915_private *dev_priv)
17101 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
17102 dev_priv->pps_mmio_base = PCH_PPS_BASE;
17103 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17104 dev_priv->pps_mmio_base = VLV_PPS_BASE;
17106 dev_priv->pps_mmio_base = PPS_BASE;
17108 intel_pps_unlock_regs_wa(dev_priv);
17111 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
17113 struct intel_encoder *encoder;
17114 bool dpd_is_edp = false;
17116 intel_pps_init(dev_priv);
17118 if (!HAS_DISPLAY(dev_priv))
17121 if (IS_ROCKETLAKE(dev_priv)) {
17122 intel_ddi_init(dev_priv, PORT_A);
17123 intel_ddi_init(dev_priv, PORT_B);
17124 intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
17125 intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
17126 } else if (INTEL_GEN(dev_priv) >= 12) {
17127 intel_ddi_init(dev_priv, PORT_A);
17128 intel_ddi_init(dev_priv, PORT_B);
17129 intel_ddi_init(dev_priv, PORT_D);
17130 intel_ddi_init(dev_priv, PORT_E);
17131 intel_ddi_init(dev_priv, PORT_F);
17132 intel_ddi_init(dev_priv, PORT_G);
17133 intel_ddi_init(dev_priv, PORT_H);
17134 intel_ddi_init(dev_priv, PORT_I);
17135 icl_dsi_init(dev_priv);
17136 } else if (IS_JSL_EHL(dev_priv)) {
17137 intel_ddi_init(dev_priv, PORT_A);
17138 intel_ddi_init(dev_priv, PORT_B);
17139 intel_ddi_init(dev_priv, PORT_C);
17140 intel_ddi_init(dev_priv, PORT_D);
17141 icl_dsi_init(dev_priv);
17142 } else if (IS_GEN(dev_priv, 11)) {
17143 intel_ddi_init(dev_priv, PORT_A);
17144 intel_ddi_init(dev_priv, PORT_B);
17145 intel_ddi_init(dev_priv, PORT_C);
17146 intel_ddi_init(dev_priv, PORT_D);
17147 intel_ddi_init(dev_priv, PORT_E);
17149 * On some ICL SKUs port F is not present. No strap bits for
17150 * this, so rely on VBT.
17151 * Work around broken VBTs on SKUs known to have no port F.
17153 if (IS_ICL_WITH_PORT_F(dev_priv) &&
17154 intel_bios_is_port_present(dev_priv, PORT_F))
17155 intel_ddi_init(dev_priv, PORT_F);
17157 icl_dsi_init(dev_priv);
17158 } else if (IS_GEN9_LP(dev_priv)) {
17160 * FIXME: Broxton doesn't support port detection via the
17161 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
17162 * detect the ports.
17164 intel_ddi_init(dev_priv, PORT_A);
17165 intel_ddi_init(dev_priv, PORT_B);
17166 intel_ddi_init(dev_priv, PORT_C);
17168 vlv_dsi_init(dev_priv);
17169 } else if (HAS_DDI(dev_priv)) {
17172 if (intel_ddi_crt_present(dev_priv))
17173 intel_crt_init(dev_priv);
17176 * Haswell uses DDI functions to detect digital outputs.
17177 * On SKL pre-D0 the strap isn't connected, so we assume
17180 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
17181 /* WaIgnoreDDIAStrap: skl */
17182 if (found || IS_GEN9_BC(dev_priv))
17183 intel_ddi_init(dev_priv, PORT_A);
17185 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
17187 found = intel_de_read(dev_priv, SFUSE_STRAP);
17189 if (found & SFUSE_STRAP_DDIB_DETECTED)
17190 intel_ddi_init(dev_priv, PORT_B);
17191 if (found & SFUSE_STRAP_DDIC_DETECTED)
17192 intel_ddi_init(dev_priv, PORT_C);
17193 if (found & SFUSE_STRAP_DDID_DETECTED)
17194 intel_ddi_init(dev_priv, PORT_D);
17195 if (found & SFUSE_STRAP_DDIF_DETECTED)
17196 intel_ddi_init(dev_priv, PORT_F);
17198 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
17200 if (IS_GEN9_BC(dev_priv) &&
17201 intel_bios_is_port_present(dev_priv, PORT_E))
17202 intel_ddi_init(dev_priv, PORT_E);
17204 } else if (HAS_PCH_SPLIT(dev_priv)) {
17208 * intel_edp_init_connector() depends on this completing first,
17209 * to prevent the registration of both eDP and LVDS and the
17210 * incorrect sharing of the PPS.
17212 intel_lvds_init(dev_priv);
17213 intel_crt_init(dev_priv);
17215 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
17217 if (ilk_has_edp_a(dev_priv))
17218 intel_dp_init(dev_priv, DP_A, PORT_A);
17220 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
17221 /* PCH SDVOB multiplex with HDMIB */
17222 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
17224 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
17225 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
17226 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17229 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17230 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17232 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17233 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17235 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17236 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17238 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17239 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17240 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17241 bool has_edp, has_port;
17243 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17244 intel_crt_init(dev_priv);
17247 * The DP_DETECTED bit is the latched state of the DDC
17248 * SDA pin at boot. However since eDP doesn't require DDC
17249 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17250 * eDP ports may have been muxed to an alternate function.
17251 * Thus we can't rely on the DP_DETECTED bit alone to detect
17252 * eDP ports. Consult the VBT as well as DP_DETECTED to
17253 * detect eDP ports.
17255 * Sadly the straps seem to be missing sometimes even for HDMI
17256 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17257 * and VBT for the presence of the port. Additionally we can't
17258 * trust the port type the VBT declares as we've seen at least
17259 * HDMI ports that the VBT claim are DP or eDP.
17261 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17262 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17263 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17264 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17265 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17266 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17268 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17269 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17270 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17271 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17272 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17273 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17275 if (IS_CHERRYVIEW(dev_priv)) {
17277 * eDP not supported on port D,
17278 * so no need to worry about it
17280 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17281 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17282 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17283 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17284 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17287 vlv_dsi_init(dev_priv);
17288 } else if (IS_PINEVIEW(dev_priv)) {
17289 intel_lvds_init(dev_priv);
17290 intel_crt_init(dev_priv);
17291 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17292 bool found = false;
17294 if (IS_MOBILE(dev_priv))
17295 intel_lvds_init(dev_priv);
17297 intel_crt_init(dev_priv);
17299 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17300 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17301 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17302 if (!found && IS_G4X(dev_priv)) {
17303 drm_dbg_kms(&dev_priv->drm,
17304 "probing HDMI on SDVOB\n");
17305 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17308 if (!found && IS_G4X(dev_priv))
17309 intel_dp_init(dev_priv, DP_B, PORT_B);
17312 /* Before G4X SDVOC doesn't have its own detect register */
17314 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17315 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17316 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17319 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17321 if (IS_G4X(dev_priv)) {
17322 drm_dbg_kms(&dev_priv->drm,
17323 "probing HDMI on SDVOC\n");
17324 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17326 if (IS_G4X(dev_priv))
17327 intel_dp_init(dev_priv, DP_C, PORT_C);
17330 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17331 intel_dp_init(dev_priv, DP_D, PORT_D);
17333 if (SUPPORTS_TV(dev_priv))
17334 intel_tv_init(dev_priv);
17335 } else if (IS_GEN(dev_priv, 2)) {
17336 if (IS_I85X(dev_priv))
17337 intel_lvds_init(dev_priv);
17339 intel_crt_init(dev_priv);
17340 intel_dvo_init(dev_priv);
17343 intel_psr_init(dev_priv);
17345 for_each_intel_encoder(&dev_priv->drm, encoder) {
17346 encoder->base.possible_crtcs =
17347 intel_encoder_possible_crtcs(encoder);
17348 encoder->base.possible_clones =
17349 intel_encoder_possible_clones(encoder);
17352 intel_init_pch_refclk(dev_priv);
17354 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17357 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17359 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17361 drm_framebuffer_cleanup(fb);
17362 intel_frontbuffer_put(intel_fb->frontbuffer);
17367 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17368 struct drm_file *file,
17369 unsigned int *handle)
17371 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17372 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17374 if (obj->userptr.mm) {
17375 drm_dbg(&i915->drm,
17376 "attempting to use a userptr for a framebuffer, denied\n");
17380 return drm_gem_handle_create(file, &obj->base, handle);
17383 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17384 struct drm_file *file,
17385 unsigned flags, unsigned color,
17386 struct drm_clip_rect *clips,
17387 unsigned num_clips)
17389 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17391 i915_gem_object_flush_if_display(obj);
17392 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17397 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17398 .destroy = intel_user_framebuffer_destroy,
17399 .create_handle = intel_user_framebuffer_create_handle,
17400 .dirty = intel_user_framebuffer_dirty,
17403 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17404 struct drm_i915_gem_object *obj,
17405 struct drm_mode_fb_cmd2 *mode_cmd)
17407 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17408 struct drm_framebuffer *fb = &intel_fb->base;
17410 unsigned int tiling, stride;
17414 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17415 if (!intel_fb->frontbuffer)
17418 i915_gem_object_lock(obj, NULL);
17419 tiling = i915_gem_object_get_tiling(obj);
17420 stride = i915_gem_object_get_stride(obj);
17421 i915_gem_object_unlock(obj);
17423 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17425 * If there's a fence, enforce that
17426 * the fb modifier and tiling mode match.
17428 if (tiling != I915_TILING_NONE &&
17429 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17430 drm_dbg_kms(&dev_priv->drm,
17431 "tiling_mode doesn't match fb modifier\n");
17435 if (tiling == I915_TILING_X) {
17436 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17437 } else if (tiling == I915_TILING_Y) {
17438 drm_dbg_kms(&dev_priv->drm,
17439 "No Y tiling for legacy addfb\n");
17444 if (!drm_any_plane_has_format(&dev_priv->drm,
17445 mode_cmd->pixel_format,
17446 mode_cmd->modifier[0])) {
17447 struct drm_format_name_buf format_name;
17449 drm_dbg_kms(&dev_priv->drm,
17450 "unsupported pixel format %s / modifier 0x%llx\n",
17451 drm_get_format_name(mode_cmd->pixel_format,
17453 mode_cmd->modifier[0]);
17458 * gen2/3 display engine uses the fence if present,
17459 * so the tiling mode must match the fb modifier exactly.
17461 if (INTEL_GEN(dev_priv) < 4 &&
17462 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17463 drm_dbg_kms(&dev_priv->drm,
17464 "tiling_mode must match fb modifier exactly on gen2/3\n");
17468 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17469 mode_cmd->modifier[0]);
17470 if (mode_cmd->pitches[0] > max_stride) {
17471 drm_dbg_kms(&dev_priv->drm,
17472 "%s pitch (%u) must be at most %d\n",
17473 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17474 "tiled" : "linear",
17475 mode_cmd->pitches[0], max_stride);
17480 * If there's a fence, enforce that
17481 * the fb pitch and fence stride match.
17483 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17484 drm_dbg_kms(&dev_priv->drm,
17485 "pitch (%d) must match tiling stride (%d)\n",
17486 mode_cmd->pitches[0], stride);
17490 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17491 if (mode_cmd->offsets[0] != 0) {
17492 drm_dbg_kms(&dev_priv->drm,
17493 "plane 0 offset (0x%08x) must be 0\n",
17494 mode_cmd->offsets[0]);
17498 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17500 for (i = 0; i < fb->format->num_planes; i++) {
17501 u32 stride_alignment;
17503 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17504 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17509 stride_alignment = intel_fb_stride_alignment(fb, i);
17510 if (fb->pitches[i] & (stride_alignment - 1)) {
17511 drm_dbg_kms(&dev_priv->drm,
17512 "plane %d pitch (%d) must be at least %u byte aligned\n",
17513 i, fb->pitches[i], stride_alignment);
17517 if (is_gen12_ccs_plane(fb, i)) {
17518 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17520 if (fb->pitches[i] != ccs_aux_stride) {
17521 drm_dbg_kms(&dev_priv->drm,
17522 "ccs aux plane %d pitch (%d) must be %d\n",
17524 fb->pitches[i], ccs_aux_stride);
17529 fb->obj[i] = &obj->base;
17532 ret = intel_fill_fb_info(dev_priv, fb);
17536 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17538 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17545 intel_frontbuffer_put(intel_fb->frontbuffer);
17549 static struct drm_framebuffer *
17550 intel_user_framebuffer_create(struct drm_device *dev,
17551 struct drm_file *filp,
17552 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17554 struct drm_framebuffer *fb;
17555 struct drm_i915_gem_object *obj;
17556 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17558 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17560 return ERR_PTR(-ENOENT);
17562 fb = intel_framebuffer_create(obj, &mode_cmd);
17563 i915_gem_object_put(obj);
17568 static enum drm_mode_status
17569 intel_mode_valid(struct drm_device *dev,
17570 const struct drm_display_mode *mode)
17572 struct drm_i915_private *dev_priv = to_i915(dev);
17573 int hdisplay_max, htotal_max;
17574 int vdisplay_max, vtotal_max;
17577 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17578 * of DBLSCAN modes to the output's mode list when they detect
17579 * the scaling mode property on the connector. And they don't
17580 * ask the kernel to validate those modes in any way until
17581 * modeset time at which point the client gets a protocol error.
17582 * So in order to not upset those clients we silently ignore the
17583 * DBLSCAN flag on such connectors. For other connectors we will
17584 * reject modes with the DBLSCAN flag in encoder->compute_config().
17585 * And we always reject DBLSCAN modes in connector->mode_valid()
17586 * as we never want such modes on the connector's mode list.
17589 if (mode->vscan > 1)
17590 return MODE_NO_VSCAN;
17592 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17593 return MODE_H_ILLEGAL;
17595 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17596 DRM_MODE_FLAG_NCSYNC |
17597 DRM_MODE_FLAG_PCSYNC))
17600 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17601 DRM_MODE_FLAG_PIXMUX |
17602 DRM_MODE_FLAG_CLKDIV2))
17605 /* Transcoder timing limits */
17606 if (INTEL_GEN(dev_priv) >= 11) {
17607 hdisplay_max = 16384;
17608 vdisplay_max = 8192;
17609 htotal_max = 16384;
17611 } else if (INTEL_GEN(dev_priv) >= 9 ||
17612 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17613 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17614 vdisplay_max = 4096;
17617 } else if (INTEL_GEN(dev_priv) >= 3) {
17618 hdisplay_max = 4096;
17619 vdisplay_max = 4096;
17623 hdisplay_max = 2048;
17624 vdisplay_max = 2048;
17629 if (mode->hdisplay > hdisplay_max ||
17630 mode->hsync_start > htotal_max ||
17631 mode->hsync_end > htotal_max ||
17632 mode->htotal > htotal_max)
17633 return MODE_H_ILLEGAL;
17635 if (mode->vdisplay > vdisplay_max ||
17636 mode->vsync_start > vtotal_max ||
17637 mode->vsync_end > vtotal_max ||
17638 mode->vtotal > vtotal_max)
17639 return MODE_V_ILLEGAL;
17641 if (INTEL_GEN(dev_priv) >= 5) {
17642 if (mode->hdisplay < 64 ||
17643 mode->htotal - mode->hdisplay < 32)
17644 return MODE_H_ILLEGAL;
17646 if (mode->vtotal - mode->vdisplay < 5)
17647 return MODE_V_ILLEGAL;
17649 if (mode->htotal - mode->hdisplay < 32)
17650 return MODE_H_ILLEGAL;
17652 if (mode->vtotal - mode->vdisplay < 3)
17653 return MODE_V_ILLEGAL;
17659 enum drm_mode_status
17660 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17661 const struct drm_display_mode *mode)
17663 int plane_width_max, plane_height_max;
17666 * intel_mode_valid() should be
17667 * sufficient on older platforms.
17669 if (INTEL_GEN(dev_priv) < 9)
17673 * Most people will probably want a fullscreen
17674 * plane so let's not advertize modes that are
17675 * too big for that.
17677 if (INTEL_GEN(dev_priv) >= 11) {
17678 plane_width_max = 5120;
17679 plane_height_max = 4320;
17681 plane_width_max = 5120;
17682 plane_height_max = 4096;
17685 if (mode->hdisplay > plane_width_max)
17686 return MODE_H_ILLEGAL;
17688 if (mode->vdisplay > plane_height_max)
17689 return MODE_V_ILLEGAL;
17694 static const struct drm_mode_config_funcs intel_mode_funcs = {
17695 .fb_create = intel_user_framebuffer_create,
17696 .get_format_info = intel_get_format_info,
17697 .output_poll_changed = intel_fbdev_output_poll_changed,
17698 .mode_valid = intel_mode_valid,
17699 .atomic_check = intel_atomic_check,
17700 .atomic_commit = intel_atomic_commit,
17701 .atomic_state_alloc = intel_atomic_state_alloc,
17702 .atomic_state_clear = intel_atomic_state_clear,
17703 .atomic_state_free = intel_atomic_state_free,
17707 * intel_init_display_hooks - initialize the display modesetting hooks
17708 * @dev_priv: device private
17710 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17712 intel_init_cdclk_hooks(dev_priv);
17714 if (INTEL_GEN(dev_priv) >= 9) {
17715 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17716 dev_priv->display.get_initial_plane_config =
17717 skl_get_initial_plane_config;
17718 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17719 dev_priv->display.crtc_enable = hsw_crtc_enable;
17720 dev_priv->display.crtc_disable = hsw_crtc_disable;
17721 } else if (HAS_DDI(dev_priv)) {
17722 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17723 dev_priv->display.get_initial_plane_config =
17724 i9xx_get_initial_plane_config;
17725 dev_priv->display.crtc_compute_clock =
17726 hsw_crtc_compute_clock;
17727 dev_priv->display.crtc_enable = hsw_crtc_enable;
17728 dev_priv->display.crtc_disable = hsw_crtc_disable;
17729 } else if (HAS_PCH_SPLIT(dev_priv)) {
17730 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17731 dev_priv->display.get_initial_plane_config =
17732 i9xx_get_initial_plane_config;
17733 dev_priv->display.crtc_compute_clock =
17734 ilk_crtc_compute_clock;
17735 dev_priv->display.crtc_enable = ilk_crtc_enable;
17736 dev_priv->display.crtc_disable = ilk_crtc_disable;
17737 } else if (IS_CHERRYVIEW(dev_priv)) {
17738 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17739 dev_priv->display.get_initial_plane_config =
17740 i9xx_get_initial_plane_config;
17741 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17742 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17743 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17744 } else if (IS_VALLEYVIEW(dev_priv)) {
17745 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17746 dev_priv->display.get_initial_plane_config =
17747 i9xx_get_initial_plane_config;
17748 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17749 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17750 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17751 } else if (IS_G4X(dev_priv)) {
17752 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17753 dev_priv->display.get_initial_plane_config =
17754 i9xx_get_initial_plane_config;
17755 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17756 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17757 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17758 } else if (IS_PINEVIEW(dev_priv)) {
17759 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17760 dev_priv->display.get_initial_plane_config =
17761 i9xx_get_initial_plane_config;
17762 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17763 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17764 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17765 } else if (!IS_GEN(dev_priv, 2)) {
17766 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17767 dev_priv->display.get_initial_plane_config =
17768 i9xx_get_initial_plane_config;
17769 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17770 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17771 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17773 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17774 dev_priv->display.get_initial_plane_config =
17775 i9xx_get_initial_plane_config;
17776 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17777 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17778 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17781 if (IS_GEN(dev_priv, 5)) {
17782 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17783 } else if (IS_GEN(dev_priv, 6)) {
17784 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17785 } else if (IS_IVYBRIDGE(dev_priv)) {
17786 /* FIXME: detect B0+ stepping and use auto training */
17787 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17790 if (INTEL_GEN(dev_priv) >= 9)
17791 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17793 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17797 void intel_modeset_init_hw(struct drm_i915_private *i915)
17799 struct intel_cdclk_state *cdclk_state =
17800 to_intel_cdclk_state(i915->cdclk.obj.state);
17801 struct intel_dbuf_state *dbuf_state =
17802 to_intel_dbuf_state(i915->dbuf.obj.state);
17804 intel_update_cdclk(i915);
17805 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17806 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17808 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17811 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17813 struct drm_plane *plane;
17814 struct intel_crtc *crtc;
17816 for_each_intel_crtc(state->dev, crtc) {
17817 struct intel_crtc_state *crtc_state;
17819 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17820 if (IS_ERR(crtc_state))
17821 return PTR_ERR(crtc_state);
17823 if (crtc_state->hw.active) {
17825 * Preserve the inherited flag to avoid
17826 * taking the full modeset path.
17828 crtc_state->inherited = true;
17832 drm_for_each_plane(plane, state->dev) {
17833 struct drm_plane_state *plane_state;
17835 plane_state = drm_atomic_get_plane_state(state, plane);
17836 if (IS_ERR(plane_state))
17837 return PTR_ERR(plane_state);
17844 * Calculate what we think the watermarks should be for the state we've read
17845 * out of the hardware and then immediately program those watermarks so that
17846 * we ensure the hardware settings match our internal state.
17848 * We can calculate what we think WM's should be by creating a duplicate of the
17849 * current state (which was constructed during hardware readout) and running it
17850 * through the atomic check code to calculate new watermark values in the
17853 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17855 struct drm_atomic_state *state;
17856 struct intel_atomic_state *intel_state;
17857 struct intel_crtc *crtc;
17858 struct intel_crtc_state *crtc_state;
17859 struct drm_modeset_acquire_ctx ctx;
17863 /* Only supported on platforms that use atomic watermark design */
17864 if (!dev_priv->display.optimize_watermarks)
17867 state = drm_atomic_state_alloc(&dev_priv->drm);
17868 if (drm_WARN_ON(&dev_priv->drm, !state))
17871 intel_state = to_intel_atomic_state(state);
17873 drm_modeset_acquire_init(&ctx, 0);
17876 state->acquire_ctx = &ctx;
17879 * Hardware readout is the only time we don't want to calculate
17880 * intermediate watermarks (since we don't trust the current
17883 if (!HAS_GMCH(dev_priv))
17884 intel_state->skip_intermediate_wm = true;
17886 ret = sanitize_watermarks_add_affected(state);
17890 ret = intel_atomic_check(&dev_priv->drm, state);
17894 /* Write calculated watermark values back */
17895 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17896 crtc_state->wm.need_postvbl_update = true;
17897 dev_priv->display.optimize_watermarks(intel_state, crtc);
17899 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17903 if (ret == -EDEADLK) {
17904 drm_atomic_state_clear(state);
17905 drm_modeset_backoff(&ctx);
17910 * If we fail here, it means that the hardware appears to be
17911 * programmed in a way that shouldn't be possible, given our
17912 * understanding of watermark requirements. This might mean a
17913 * mistake in the hardware readout code or a mistake in the
17914 * watermark calculations for a given platform. Raise a WARN
17915 * so that this is noticeable.
17917 * If this actually happens, we'll have to just leave the
17918 * BIOS-programmed watermarks untouched and hope for the best.
17920 drm_WARN(&dev_priv->drm, ret,
17921 "Could not determine valid watermarks for inherited state\n");
17923 drm_atomic_state_put(state);
17925 drm_modeset_drop_locks(&ctx);
17926 drm_modeset_acquire_fini(&ctx);
17929 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17931 if (IS_GEN(dev_priv, 5)) {
17933 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17935 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17936 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17937 dev_priv->fdi_pll_freq = 270000;
17942 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17945 static int intel_initial_commit(struct drm_device *dev)
17947 struct drm_atomic_state *state = NULL;
17948 struct drm_modeset_acquire_ctx ctx;
17949 struct intel_crtc *crtc;
17952 state = drm_atomic_state_alloc(dev);
17956 drm_modeset_acquire_init(&ctx, 0);
17959 state->acquire_ctx = &ctx;
17961 for_each_intel_crtc(dev, crtc) {
17962 struct intel_crtc_state *crtc_state =
17963 intel_atomic_get_crtc_state(state, crtc);
17965 if (IS_ERR(crtc_state)) {
17966 ret = PTR_ERR(crtc_state);
17970 if (crtc_state->hw.active) {
17971 struct intel_encoder *encoder;
17974 * We've not yet detected sink capabilities
17975 * (audio,infoframes,etc.) and thus we don't want to
17976 * force a full state recomputation yet. We want that to
17977 * happen only for the first real commit from userspace.
17978 * So preserve the inherited flag for the time being.
17980 crtc_state->inherited = true;
17982 ret = drm_atomic_add_affected_planes(state, &crtc->base);
17987 * FIXME hack to force a LUT update to avoid the
17988 * plane update forcing the pipe gamma on without
17989 * having a proper LUT loaded. Remove once we
17990 * have readout for pipe gamma enable.
17992 crtc_state->uapi.color_mgmt_changed = true;
17994 for_each_intel_encoder_mask(dev, encoder,
17995 crtc_state->uapi.encoder_mask) {
17996 if (encoder->initial_fastset_check &&
17997 !encoder->initial_fastset_check(encoder, crtc_state)) {
17998 ret = drm_atomic_add_affected_connectors(state,
18007 ret = drm_atomic_commit(state);
18010 if (ret == -EDEADLK) {
18011 drm_atomic_state_clear(state);
18012 drm_modeset_backoff(&ctx);
18016 drm_atomic_state_put(state);
18018 drm_modeset_drop_locks(&ctx);
18019 drm_modeset_acquire_fini(&ctx);
18024 static void intel_mode_config_init(struct drm_i915_private *i915)
18026 struct drm_mode_config *mode_config = &i915->drm.mode_config;
18028 drm_mode_config_init(&i915->drm);
18029 INIT_LIST_HEAD(&i915->global_obj_list);
18031 mode_config->min_width = 0;
18032 mode_config->min_height = 0;
18034 mode_config->preferred_depth = 24;
18035 mode_config->prefer_shadow = 1;
18037 mode_config->allow_fb_modifiers = true;
18039 mode_config->funcs = &intel_mode_funcs;
18041 if (INTEL_GEN(i915) >= 9)
18042 mode_config->async_page_flip = true;
18045 * Maximum framebuffer dimensions, chosen to match
18046 * the maximum render engine surface size on gen4+.
18048 if (INTEL_GEN(i915) >= 7) {
18049 mode_config->max_width = 16384;
18050 mode_config->max_height = 16384;
18051 } else if (INTEL_GEN(i915) >= 4) {
18052 mode_config->max_width = 8192;
18053 mode_config->max_height = 8192;
18054 } else if (IS_GEN(i915, 3)) {
18055 mode_config->max_width = 4096;
18056 mode_config->max_height = 4096;
18058 mode_config->max_width = 2048;
18059 mode_config->max_height = 2048;
18062 if (IS_I845G(i915) || IS_I865G(i915)) {
18063 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
18064 mode_config->cursor_height = 1023;
18065 } else if (IS_I830(i915) || IS_I85X(i915) ||
18066 IS_I915G(i915) || IS_I915GM(i915)) {
18067 mode_config->cursor_width = 64;
18068 mode_config->cursor_height = 64;
18070 mode_config->cursor_width = 256;
18071 mode_config->cursor_height = 256;
18075 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
18077 intel_atomic_global_obj_cleanup(i915);
18078 drm_mode_config_cleanup(&i915->drm);
18081 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
18083 if (plane_config->fb) {
18084 struct drm_framebuffer *fb = &plane_config->fb->base;
18086 /* We may only have the stub and not a full framebuffer */
18087 if (drm_framebuffer_read_refcount(fb))
18088 drm_framebuffer_put(fb);
18093 if (plane_config->vma)
18094 i915_vma_put(plane_config->vma);
18097 /* part #1: call before irq install */
18098 int intel_modeset_init_noirq(struct drm_i915_private *i915)
18102 if (i915_inject_probe_failure(i915))
18105 if (HAS_DISPLAY(i915)) {
18106 ret = drm_vblank_init(&i915->drm,
18107 INTEL_NUM_PIPES(i915));
18112 intel_bios_init(i915);
18114 ret = intel_vga_register(i915);
18118 /* FIXME: completely on the wrong abstraction layer */
18119 intel_power_domains_init_hw(i915, false);
18121 intel_csr_ucode_init(i915);
18123 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
18124 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
18125 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
18127 intel_mode_config_init(i915);
18129 ret = intel_cdclk_init(i915);
18131 goto cleanup_vga_client_pw_domain_csr;
18133 ret = intel_dbuf_init(i915);
18135 goto cleanup_vga_client_pw_domain_csr;
18137 ret = intel_bw_init(i915);
18139 goto cleanup_vga_client_pw_domain_csr;
18141 init_llist_head(&i915->atomic_helper.free_list);
18142 INIT_WORK(&i915->atomic_helper.free_work,
18143 intel_atomic_helper_free_state_worker);
18145 intel_init_quirks(i915);
18147 intel_fbc_init(i915);
18151 cleanup_vga_client_pw_domain_csr:
18152 intel_csr_ucode_fini(i915);
18153 intel_power_domains_driver_remove(i915);
18154 intel_vga_unregister(i915);
18156 intel_bios_driver_remove(i915);
18161 /* part #2: call after irq install, but before gem init */
18162 int intel_modeset_init_nogem(struct drm_i915_private *i915)
18164 struct drm_device *dev = &i915->drm;
18166 struct intel_crtc *crtc;
18169 intel_init_pm(i915);
18171 intel_panel_sanitize_ssc(i915);
18173 intel_gmbus_setup(i915);
18175 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
18176 INTEL_NUM_PIPES(i915),
18177 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
18179 if (HAS_DISPLAY(i915)) {
18180 for_each_pipe(i915, pipe) {
18181 ret = intel_crtc_init(i915, pipe);
18183 intel_mode_config_cleanup(i915);
18189 intel_plane_possible_crtcs_init(i915);
18190 intel_shared_dpll_init(dev);
18191 intel_update_fdi_pll_freq(i915);
18193 intel_update_czclk(i915);
18194 intel_modeset_init_hw(i915);
18196 intel_hdcp_component_init(i915);
18198 if (i915->max_cdclk_freq == 0)
18199 intel_update_max_cdclk(i915);
18202 * If the platform has HTI, we need to find out whether it has reserved
18203 * any display resources before we create our display outputs.
18205 if (INTEL_INFO(i915)->display.has_hti)
18206 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
18208 /* Just disable it once at startup */
18209 intel_vga_disable(i915);
18210 intel_setup_outputs(i915);
18212 drm_modeset_lock_all(dev);
18213 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
18214 drm_modeset_unlock_all(dev);
18216 for_each_intel_crtc(dev, crtc) {
18217 struct intel_initial_plane_config plane_config = {};
18223 * Note that reserving the BIOS fb up front prevents us
18224 * from stuffing other stolen allocations like the ring
18225 * on top. This prevents some ugliness at boot time, and
18226 * can even allow for smooth boot transitions if the BIOS
18227 * fb is large enough for the active pipe configuration.
18229 i915->display.get_initial_plane_config(crtc, &plane_config);
18232 * If the fb is shared between multiple heads, we'll
18233 * just get the first one.
18235 intel_find_initial_plane_obj(crtc, &plane_config);
18237 plane_config_fini(&plane_config);
18241 * Make sure hardware watermarks really match the state we read out.
18242 * Note that we need to do this after reconstructing the BIOS fb's
18243 * since the watermark calculation done here will use pstate->fb.
18245 if (!HAS_GMCH(i915))
18246 sanitize_watermarks(i915);
18249 * Force all active planes to recompute their states. So that on
18250 * mode_setcrtc after probe, all the intel_plane_state variables
18251 * are already calculated and there is no assert_plane warnings
18254 ret = intel_initial_commit(dev);
18256 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18261 /* part #3: call after gem init */
18262 int intel_modeset_init(struct drm_i915_private *i915)
18266 intel_overlay_setup(i915);
18268 if (!HAS_DISPLAY(i915))
18271 ret = intel_fbdev_init(&i915->drm);
18275 /* Only enable hotplug handling once the fbdev is fully set up. */
18276 intel_hpd_init(i915);
18278 intel_init_ipc(i915);
18280 intel_psr_set_force_mode_changed(i915->psr.dp);
18285 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18287 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18288 /* 640x480@60Hz, ~25175 kHz */
18289 struct dpll clock = {
18299 drm_WARN_ON(&dev_priv->drm,
18300 i9xx_calc_dpll_params(48000, &clock) != 25154);
18302 drm_dbg_kms(&dev_priv->drm,
18303 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18304 pipe_name(pipe), clock.vco, clock.dot);
18306 fp = i9xx_dpll_compute_fp(&clock);
18307 dpll = DPLL_DVO_2X_MODE |
18308 DPLL_VGA_MODE_DIS |
18309 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18310 PLL_P2_DIVIDE_BY_4 |
18311 PLL_REF_INPUT_DREFCLK |
18314 intel_de_write(dev_priv, FP0(pipe), fp);
18315 intel_de_write(dev_priv, FP1(pipe), fp);
18317 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18318 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18319 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18320 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18321 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18322 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18323 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18326 * Apparently we need to have VGA mode enabled prior to changing
18327 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18328 * dividers, even though the register value does change.
18330 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18331 intel_de_write(dev_priv, DPLL(pipe), dpll);
18333 /* Wait for the clocks to stabilize. */
18334 intel_de_posting_read(dev_priv, DPLL(pipe));
18337 /* The pixel multiplier can only be updated once the
18338 * DPLL is enabled and the clocks are stable.
18340 * So write it again.
18342 intel_de_write(dev_priv, DPLL(pipe), dpll);
18344 /* We do this three times for luck */
18345 for (i = 0; i < 3 ; i++) {
18346 intel_de_write(dev_priv, DPLL(pipe), dpll);
18347 intel_de_posting_read(dev_priv, DPLL(pipe));
18348 udelay(150); /* wait for warmup */
18351 intel_de_write(dev_priv, PIPECONF(pipe),
18352 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18353 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18355 intel_wait_for_pipe_scanline_moving(crtc);
18358 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18360 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18362 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18365 drm_WARN_ON(&dev_priv->drm,
18366 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18367 DISPLAY_PLANE_ENABLE);
18368 drm_WARN_ON(&dev_priv->drm,
18369 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18370 DISPLAY_PLANE_ENABLE);
18371 drm_WARN_ON(&dev_priv->drm,
18372 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18373 DISPLAY_PLANE_ENABLE);
18374 drm_WARN_ON(&dev_priv->drm,
18375 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18376 drm_WARN_ON(&dev_priv->drm,
18377 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18379 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18380 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18382 intel_wait_for_pipe_scanline_stopped(crtc);
18384 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18385 intel_de_posting_read(dev_priv, DPLL(pipe));
18389 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18391 struct intel_crtc *crtc;
18393 if (INTEL_GEN(dev_priv) >= 4)
18396 for_each_intel_crtc(&dev_priv->drm, crtc) {
18397 struct intel_plane *plane =
18398 to_intel_plane(crtc->base.primary);
18399 struct intel_crtc *plane_crtc;
18402 if (!plane->get_hw_state(plane, &pipe))
18405 if (pipe == crtc->pipe)
18408 drm_dbg_kms(&dev_priv->drm,
18409 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18410 plane->base.base.id, plane->base.name);
18412 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18413 intel_plane_disable_noatomic(plane_crtc, plane);
18417 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18419 struct drm_device *dev = crtc->base.dev;
18420 struct intel_encoder *encoder;
18422 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18428 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18430 struct drm_device *dev = encoder->base.dev;
18431 struct intel_connector *connector;
18433 for_each_connector_on_encoder(dev, &encoder->base, connector)
18439 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18440 enum pipe pch_transcoder)
18442 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18443 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18446 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18448 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18450 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18452 if (INTEL_GEN(dev_priv) >= 9 ||
18453 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18454 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18457 if (transcoder_is_dsi(cpu_transcoder))
18460 val = intel_de_read(dev_priv, reg);
18461 val &= ~HSW_FRAME_START_DELAY_MASK;
18462 val |= HSW_FRAME_START_DELAY(0);
18463 intel_de_write(dev_priv, reg, val);
18465 i915_reg_t reg = PIPECONF(cpu_transcoder);
18468 val = intel_de_read(dev_priv, reg);
18469 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18470 val |= PIPECONF_FRAME_START_DELAY(0);
18471 intel_de_write(dev_priv, reg, val);
18474 if (!crtc_state->has_pch_encoder)
18477 if (HAS_PCH_IBX(dev_priv)) {
18478 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18481 val = intel_de_read(dev_priv, reg);
18482 val &= ~TRANS_FRAME_START_DELAY_MASK;
18483 val |= TRANS_FRAME_START_DELAY(0);
18484 intel_de_write(dev_priv, reg, val);
18486 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18487 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18490 val = intel_de_read(dev_priv, reg);
18491 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18492 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18493 intel_de_write(dev_priv, reg, val);
18497 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18498 struct drm_modeset_acquire_ctx *ctx)
18500 struct drm_device *dev = crtc->base.dev;
18501 struct drm_i915_private *dev_priv = to_i915(dev);
18502 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18504 if (crtc_state->hw.active) {
18505 struct intel_plane *plane;
18507 /* Clear any frame start delays used for debugging left by the BIOS */
18508 intel_sanitize_frame_start_delay(crtc_state);
18510 /* Disable everything but the primary plane */
18511 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18512 const struct intel_plane_state *plane_state =
18513 to_intel_plane_state(plane->base.state);
18515 if (plane_state->uapi.visible &&
18516 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18517 intel_plane_disable_noatomic(crtc, plane);
18521 * Disable any background color set by the BIOS, but enable the
18522 * gamma and CSC to match how we program our planes.
18524 if (INTEL_GEN(dev_priv) >= 9)
18525 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18526 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18529 /* Adjust the state of the output pipe according to whether we
18530 * have active connectors/encoders. */
18531 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18532 intel_crtc_disable_noatomic(crtc, ctx);
18534 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18536 * We start out with underrun reporting disabled to avoid races.
18537 * For correct bookkeeping mark this on active crtcs.
18539 * Also on gmch platforms we dont have any hardware bits to
18540 * disable the underrun reporting. Which means we need to start
18541 * out with underrun reporting disabled also on inactive pipes,
18542 * since otherwise we'll complain about the garbage we read when
18543 * e.g. coming up after runtime pm.
18545 * No protection against concurrent access is required - at
18546 * worst a fifo underrun happens which also sets this to false.
18548 crtc->cpu_fifo_underrun_disabled = true;
18550 * We track the PCH trancoder underrun reporting state
18551 * within the crtc. With crtc for pipe A housing the underrun
18552 * reporting state for PCH transcoder A, crtc for pipe B housing
18553 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18554 * and marking underrun reporting as disabled for the non-existing
18555 * PCH transcoders B and C would prevent enabling the south
18556 * error interrupt (see cpt_can_enable_serr_int()).
18558 if (has_pch_trancoder(dev_priv, crtc->pipe))
18559 crtc->pch_fifo_underrun_disabled = true;
18563 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18565 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18568 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18569 * the hardware when a high res displays plugged in. DPLL P
18570 * divider is zero, and the pipe timings are bonkers. We'll
18571 * try to disable everything in that case.
18573 * FIXME would be nice to be able to sanitize this state
18574 * without several WARNs, but for now let's take the easy
18577 return IS_GEN(dev_priv, 6) &&
18578 crtc_state->hw.active &&
18579 crtc_state->shared_dpll &&
18580 crtc_state->port_clock == 0;
18583 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18585 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18586 struct intel_connector *connector;
18587 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18588 struct intel_crtc_state *crtc_state = crtc ?
18589 to_intel_crtc_state(crtc->base.state) : NULL;
18591 /* We need to check both for a crtc link (meaning that the
18592 * encoder is active and trying to read from a pipe) and the
18593 * pipe itself being active. */
18594 bool has_active_crtc = crtc_state &&
18595 crtc_state->hw.active;
18597 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18598 drm_dbg_kms(&dev_priv->drm,
18599 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18600 pipe_name(crtc->pipe));
18601 has_active_crtc = false;
18604 connector = intel_encoder_find_connector(encoder);
18605 if (connector && !has_active_crtc) {
18606 drm_dbg_kms(&dev_priv->drm,
18607 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18608 encoder->base.base.id,
18609 encoder->base.name);
18611 /* Connector is active, but has no active pipe. This is
18612 * fallout from our resume register restoring. Disable
18613 * the encoder manually again. */
18615 struct drm_encoder *best_encoder;
18617 drm_dbg_kms(&dev_priv->drm,
18618 "[ENCODER:%d:%s] manually disabled\n",
18619 encoder->base.base.id,
18620 encoder->base.name);
18622 /* avoid oopsing in case the hooks consult best_encoder */
18623 best_encoder = connector->base.state->best_encoder;
18624 connector->base.state->best_encoder = &encoder->base;
18626 /* FIXME NULL atomic state passed! */
18627 if (encoder->disable)
18628 encoder->disable(NULL, encoder, crtc_state,
18629 connector->base.state);
18630 if (encoder->post_disable)
18631 encoder->post_disable(NULL, encoder, crtc_state,
18632 connector->base.state);
18634 connector->base.state->best_encoder = best_encoder;
18636 encoder->base.crtc = NULL;
18638 /* Inconsistent output/port/pipe state happens presumably due to
18639 * a bug in one of the get_hw_state functions. Or someplace else
18640 * in our code, like the register restore mess on resume. Clamp
18641 * things to off as a safer default. */
18643 connector->base.dpms = DRM_MODE_DPMS_OFF;
18644 connector->base.encoder = NULL;
18647 /* notify opregion of the sanitized encoder state */
18648 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18650 if (INTEL_GEN(dev_priv) >= 11)
18651 icl_sanitize_encoder_pll_mapping(encoder);
18654 /* FIXME read out full plane state for all planes */
18655 static void readout_plane_state(struct drm_i915_private *dev_priv)
18657 struct intel_plane *plane;
18658 struct intel_crtc *crtc;
18660 for_each_intel_plane(&dev_priv->drm, plane) {
18661 struct intel_plane_state *plane_state =
18662 to_intel_plane_state(plane->base.state);
18663 struct intel_crtc_state *crtc_state;
18664 enum pipe pipe = PIPE_A;
18667 visible = plane->get_hw_state(plane, &pipe);
18669 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18670 crtc_state = to_intel_crtc_state(crtc->base.state);
18672 intel_set_plane_visible(crtc_state, plane_state, visible);
18674 drm_dbg_kms(&dev_priv->drm,
18675 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18676 plane->base.base.id, plane->base.name,
18677 enableddisabled(visible), pipe_name(pipe));
18680 for_each_intel_crtc(&dev_priv->drm, crtc) {
18681 struct intel_crtc_state *crtc_state =
18682 to_intel_crtc_state(crtc->base.state);
18684 fixup_active_planes(crtc_state);
18688 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18690 struct drm_i915_private *dev_priv = to_i915(dev);
18691 struct intel_cdclk_state *cdclk_state =
18692 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18693 struct intel_dbuf_state *dbuf_state =
18694 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18696 struct intel_crtc *crtc;
18697 struct intel_encoder *encoder;
18698 struct intel_connector *connector;
18699 struct drm_connector_list_iter conn_iter;
18700 u8 active_pipes = 0;
18702 for_each_intel_crtc(dev, crtc) {
18703 struct intel_crtc_state *crtc_state =
18704 to_intel_crtc_state(crtc->base.state);
18706 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18707 intel_crtc_free_hw_state(crtc_state);
18708 intel_crtc_state_reset(crtc_state, crtc);
18710 crtc_state->hw.active = crtc_state->hw.enable =
18711 dev_priv->display.get_pipe_config(crtc, crtc_state);
18713 crtc->base.enabled = crtc_state->hw.enable;
18714 crtc->active = crtc_state->hw.active;
18716 if (crtc_state->hw.active)
18717 active_pipes |= BIT(crtc->pipe);
18719 drm_dbg_kms(&dev_priv->drm,
18720 "[CRTC:%d:%s] hw state readout: %s\n",
18721 crtc->base.base.id, crtc->base.name,
18722 enableddisabled(crtc_state->hw.active));
18725 dev_priv->active_pipes = cdclk_state->active_pipes =
18726 dbuf_state->active_pipes = active_pipes;
18728 readout_plane_state(dev_priv);
18730 intel_dpll_readout_hw_state(dev_priv);
18732 for_each_intel_encoder(dev, encoder) {
18735 if (encoder->get_hw_state(encoder, &pipe)) {
18736 struct intel_crtc_state *crtc_state;
18738 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18739 crtc_state = to_intel_crtc_state(crtc->base.state);
18741 encoder->base.crtc = &crtc->base;
18742 encoder->get_config(encoder, crtc_state);
18743 if (encoder->sync_state)
18744 encoder->sync_state(encoder, crtc_state);
18746 encoder->base.crtc = NULL;
18749 drm_dbg_kms(&dev_priv->drm,
18750 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18751 encoder->base.base.id, encoder->base.name,
18752 enableddisabled(encoder->base.crtc),
18756 drm_connector_list_iter_begin(dev, &conn_iter);
18757 for_each_intel_connector_iter(connector, &conn_iter) {
18758 if (connector->get_hw_state(connector)) {
18759 struct intel_crtc_state *crtc_state;
18760 struct intel_crtc *crtc;
18762 connector->base.dpms = DRM_MODE_DPMS_ON;
18764 encoder = intel_attached_encoder(connector);
18765 connector->base.encoder = &encoder->base;
18767 crtc = to_intel_crtc(encoder->base.crtc);
18768 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18770 if (crtc_state && crtc_state->hw.active) {
18772 * This has to be done during hardware readout
18773 * because anything calling .crtc_disable may
18774 * rely on the connector_mask being accurate.
18776 crtc_state->uapi.connector_mask |=
18777 drm_connector_mask(&connector->base);
18778 crtc_state->uapi.encoder_mask |=
18779 drm_encoder_mask(&encoder->base);
18782 connector->base.dpms = DRM_MODE_DPMS_OFF;
18783 connector->base.encoder = NULL;
18785 drm_dbg_kms(&dev_priv->drm,
18786 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18787 connector->base.base.id, connector->base.name,
18788 enableddisabled(connector->base.encoder));
18790 drm_connector_list_iter_end(&conn_iter);
18792 for_each_intel_crtc(dev, crtc) {
18793 struct intel_bw_state *bw_state =
18794 to_intel_bw_state(dev_priv->bw_obj.state);
18795 struct intel_crtc_state *crtc_state =
18796 to_intel_crtc_state(crtc->base.state);
18797 struct intel_plane *plane;
18800 if (crtc_state->hw.active) {
18801 struct drm_display_mode *mode = &crtc_state->hw.mode;
18803 intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18806 *mode = crtc_state->hw.adjusted_mode;
18807 mode->hdisplay = crtc_state->pipe_src_w;
18808 mode->vdisplay = crtc_state->pipe_src_h;
18811 * The initial mode needs to be set in order to keep
18812 * the atomic core happy. It wants a valid mode if the
18813 * crtc's enabled, so we do the above call.
18815 * But we don't set all the derived state fully, hence
18816 * set a flag to indicate that a full recalculation is
18817 * needed on the next commit.
18819 crtc_state->inherited = true;
18821 intel_crtc_compute_pixel_rate(crtc_state);
18823 intel_crtc_update_active_timings(crtc_state);
18825 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18828 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18829 const struct intel_plane_state *plane_state =
18830 to_intel_plane_state(plane->base.state);
18833 * FIXME don't have the fb yet, so can't
18834 * use intel_plane_data_rate() :(
18836 if (plane_state->uapi.visible)
18837 crtc_state->data_rate[plane->id] =
18838 4 * crtc_state->pixel_rate;
18840 * FIXME don't have the fb yet, so can't
18841 * use plane->min_cdclk() :(
18843 if (plane_state->uapi.visible && plane->min_cdclk) {
18844 if (crtc_state->double_wide ||
18845 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18846 crtc_state->min_cdclk[plane->id] =
18847 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18849 crtc_state->min_cdclk[plane->id] =
18850 crtc_state->pixel_rate;
18852 drm_dbg_kms(&dev_priv->drm,
18853 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18854 plane->base.base.id, plane->base.name,
18855 crtc_state->min_cdclk[plane->id]);
18858 if (crtc_state->hw.active) {
18859 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18860 if (drm_WARN_ON(dev, min_cdclk < 0))
18864 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18865 cdclk_state->min_voltage_level[crtc->pipe] =
18866 crtc_state->min_voltage_level;
18868 intel_bw_crtc_update(bw_state, crtc_state);
18870 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18875 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18877 struct intel_encoder *encoder;
18879 for_each_intel_encoder(&dev_priv->drm, encoder) {
18880 struct intel_crtc_state *crtc_state;
18882 if (!encoder->get_power_domains)
18886 * MST-primary and inactive encoders don't have a crtc state
18887 * and neither of these require any power domain references.
18889 if (!encoder->base.crtc)
18892 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18893 encoder->get_power_domains(encoder, crtc_state);
18897 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18900 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18901 * Also known as Wa_14010480278.
18903 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18904 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18905 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18907 if (IS_HASWELL(dev_priv)) {
18909 * WaRsPkgCStateDisplayPMReq:hsw
18910 * System hang if this isn't done before disabling all planes!
18912 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18913 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18916 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
18917 /* Display WA #1142:kbl,cfl,cml */
18918 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
18919 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
18920 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
18921 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
18922 KBL_ARB_FILL_SPARE_14);
18926 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18927 enum port port, i915_reg_t hdmi_reg)
18929 u32 val = intel_de_read(dev_priv, hdmi_reg);
18931 if (val & SDVO_ENABLE ||
18932 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18935 drm_dbg_kms(&dev_priv->drm,
18936 "Sanitizing transcoder select for HDMI %c\n",
18939 val &= ~SDVO_PIPE_SEL_MASK;
18940 val |= SDVO_PIPE_SEL(PIPE_A);
18942 intel_de_write(dev_priv, hdmi_reg, val);
18945 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18946 enum port port, i915_reg_t dp_reg)
18948 u32 val = intel_de_read(dev_priv, dp_reg);
18950 if (val & DP_PORT_EN ||
18951 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18954 drm_dbg_kms(&dev_priv->drm,
18955 "Sanitizing transcoder select for DP %c\n",
18958 val &= ~DP_PIPE_SEL_MASK;
18959 val |= DP_PIPE_SEL(PIPE_A);
18961 intel_de_write(dev_priv, dp_reg, val);
18964 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18967 * The BIOS may select transcoder B on some of the PCH
18968 * ports even it doesn't enable the port. This would trip
18969 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18970 * Sanitize the transcoder select bits to prevent that. We
18971 * assume that the BIOS never actually enabled the port,
18972 * because if it did we'd actually have to toggle the port
18973 * on and back off to make the transcoder A select stick
18974 * (see. intel_dp_link_down(), intel_disable_hdmi(),
18975 * intel_disable_sdvo()).
18977 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18978 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18979 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18981 /* PCH SDVOB multiplex with HDMIB */
18982 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18983 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18984 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18987 /* Scan out the current hw modeset state,
18988 * and sanitizes it to the current state
18991 intel_modeset_setup_hw_state(struct drm_device *dev,
18992 struct drm_modeset_acquire_ctx *ctx)
18994 struct drm_i915_private *dev_priv = to_i915(dev);
18995 struct intel_encoder *encoder;
18996 struct intel_crtc *crtc;
18997 intel_wakeref_t wakeref;
18999 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
19001 intel_early_display_was(dev_priv);
19002 intel_modeset_readout_hw_state(dev);
19004 /* HW state is read out, now we need to sanitize this mess. */
19006 /* Sanitize the TypeC port mode upfront, encoders depend on this */
19007 for_each_intel_encoder(dev, encoder) {
19008 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
19010 /* We need to sanitize only the MST primary port. */
19011 if (encoder->type != INTEL_OUTPUT_DP_MST &&
19012 intel_phy_is_tc(dev_priv, phy))
19013 intel_tc_port_sanitize(enc_to_dig_port(encoder));
19016 get_encoder_power_domains(dev_priv);
19018 if (HAS_PCH_IBX(dev_priv))
19019 ibx_sanitize_pch_ports(dev_priv);
19022 * intel_sanitize_plane_mapping() may need to do vblank
19023 * waits, so we need vblank interrupts restored beforehand.
19025 for_each_intel_crtc(&dev_priv->drm, crtc) {
19026 struct intel_crtc_state *crtc_state =
19027 to_intel_crtc_state(crtc->base.state);
19029 drm_crtc_vblank_reset(&crtc->base);
19031 if (crtc_state->hw.active)
19032 intel_crtc_vblank_on(crtc_state);
19035 intel_sanitize_plane_mapping(dev_priv);
19037 for_each_intel_encoder(dev, encoder)
19038 intel_sanitize_encoder(encoder);
19040 for_each_intel_crtc(&dev_priv->drm, crtc) {
19041 struct intel_crtc_state *crtc_state =
19042 to_intel_crtc_state(crtc->base.state);
19044 intel_sanitize_crtc(crtc, ctx);
19045 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
19048 intel_modeset_update_connector_atomic_state(dev);
19050 intel_dpll_sanitize_state(dev_priv);
19052 if (IS_G4X(dev_priv)) {
19053 g4x_wm_get_hw_state(dev_priv);
19054 g4x_wm_sanitize(dev_priv);
19055 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
19056 vlv_wm_get_hw_state(dev_priv);
19057 vlv_wm_sanitize(dev_priv);
19058 } else if (INTEL_GEN(dev_priv) >= 9) {
19059 skl_wm_get_hw_state(dev_priv);
19060 } else if (HAS_PCH_SPLIT(dev_priv)) {
19061 ilk_wm_get_hw_state(dev_priv);
19064 for_each_intel_crtc(dev, crtc) {
19065 struct intel_crtc_state *crtc_state =
19066 to_intel_crtc_state(crtc->base.state);
19069 put_domains = modeset_get_crtc_power_domains(crtc_state);
19070 if (drm_WARN_ON(dev, put_domains))
19071 modeset_put_power_domains(dev_priv, put_domains);
19074 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
19077 void intel_display_resume(struct drm_device *dev)
19079 struct drm_i915_private *dev_priv = to_i915(dev);
19080 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
19081 struct drm_modeset_acquire_ctx ctx;
19084 dev_priv->modeset_restore_state = NULL;
19086 state->acquire_ctx = &ctx;
19088 drm_modeset_acquire_init(&ctx, 0);
19091 ret = drm_modeset_lock_all_ctx(dev, &ctx);
19092 if (ret != -EDEADLK)
19095 drm_modeset_backoff(&ctx);
19099 ret = __intel_display_resume(dev, state, &ctx);
19101 intel_enable_ipc(dev_priv);
19102 drm_modeset_drop_locks(&ctx);
19103 drm_modeset_acquire_fini(&ctx);
19106 drm_err(&dev_priv->drm,
19107 "Restoring old state failed with %i\n", ret);
19109 drm_atomic_state_put(state);
19112 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
19114 struct intel_connector *connector;
19115 struct drm_connector_list_iter conn_iter;
19117 /* Kill all the work that may have been queued by hpd. */
19118 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
19119 for_each_intel_connector_iter(connector, &conn_iter) {
19120 if (connector->modeset_retry_work.func)
19121 cancel_work_sync(&connector->modeset_retry_work);
19122 if (connector->hdcp.shim) {
19123 cancel_delayed_work_sync(&connector->hdcp.check_work);
19124 cancel_work_sync(&connector->hdcp.prop_work);
19127 drm_connector_list_iter_end(&conn_iter);
19130 /* part #1: call before irq uninstall */
19131 void intel_modeset_driver_remove(struct drm_i915_private *i915)
19133 flush_workqueue(i915->flip_wq);
19134 flush_workqueue(i915->modeset_wq);
19136 flush_work(&i915->atomic_helper.free_work);
19137 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
19140 /* part #2: call after irq uninstall */
19141 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
19144 * Due to the hpd irq storm handling the hotplug work can re-arm the
19145 * poll handlers. Hence disable polling after hpd handling is shut down.
19147 intel_hpd_poll_fini(i915);
19150 * MST topology needs to be suspended so we don't have any calls to
19151 * fbdev after it's finalized. MST will be destroyed later as part of
19152 * drm_mode_config_cleanup()
19154 intel_dp_mst_suspend(i915);
19156 /* poll work can call into fbdev, hence clean that up afterwards */
19157 intel_fbdev_fini(i915);
19159 intel_unregister_dsm_handler();
19161 intel_fbc_global_disable(i915);
19163 /* flush any delayed tasks or pending work */
19164 flush_scheduled_work();
19166 intel_hdcp_component_fini(i915);
19168 intel_mode_config_cleanup(i915);
19170 intel_overlay_cleanup(i915);
19172 intel_gmbus_teardown(i915);
19174 destroy_workqueue(i915->flip_wq);
19175 destroy_workqueue(i915->modeset_wq);
19177 intel_fbc_cleanup_cfb(i915);
19180 /* part #3: call after gem init */
19181 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
19183 intel_csr_ucode_fini(i915);
19185 intel_power_domains_driver_remove(i915);
19187 intel_vga_unregister(i915);
19189 intel_bios_driver_remove(i915);
19192 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
19194 struct intel_display_error_state {
19196 u32 power_well_driver;
19198 struct intel_cursor_error_state {
19203 } cursor[I915_MAX_PIPES];
19205 struct intel_pipe_error_state {
19206 bool power_domain_on;
19209 } pipe[I915_MAX_PIPES];
19211 struct intel_plane_error_state {
19219 } plane[I915_MAX_PIPES];
19221 struct intel_transcoder_error_state {
19223 bool power_domain_on;
19224 enum transcoder cpu_transcoder;
19237 struct intel_display_error_state *
19238 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19240 struct intel_display_error_state *error;
19241 int transcoders[] = {
19250 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19252 if (!HAS_DISPLAY(dev_priv))
19255 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19259 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19260 error->power_well_driver = intel_de_read(dev_priv,
19261 HSW_PWR_WELL_CTL2);
19263 for_each_pipe(dev_priv, i) {
19264 error->pipe[i].power_domain_on =
19265 __intel_display_power_is_enabled(dev_priv,
19266 POWER_DOMAIN_PIPE(i));
19267 if (!error->pipe[i].power_domain_on)
19270 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19271 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19272 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19274 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19275 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19276 if (INTEL_GEN(dev_priv) <= 3) {
19277 error->plane[i].size = intel_de_read(dev_priv,
19279 error->plane[i].pos = intel_de_read(dev_priv,
19282 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19283 error->plane[i].addr = intel_de_read(dev_priv,
19285 if (INTEL_GEN(dev_priv) >= 4) {
19286 error->plane[i].surface = intel_de_read(dev_priv,
19288 error->plane[i].tile_offset = intel_de_read(dev_priv,
19292 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19294 if (HAS_GMCH(dev_priv))
19295 error->pipe[i].stat = intel_de_read(dev_priv,
19299 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19300 enum transcoder cpu_transcoder = transcoders[i];
19302 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19305 error->transcoder[i].available = true;
19306 error->transcoder[i].power_domain_on =
19307 __intel_display_power_is_enabled(dev_priv,
19308 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19309 if (!error->transcoder[i].power_domain_on)
19312 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19314 error->transcoder[i].conf = intel_de_read(dev_priv,
19315 PIPECONF(cpu_transcoder));
19316 error->transcoder[i].htotal = intel_de_read(dev_priv,
19317 HTOTAL(cpu_transcoder));
19318 error->transcoder[i].hblank = intel_de_read(dev_priv,
19319 HBLANK(cpu_transcoder));
19320 error->transcoder[i].hsync = intel_de_read(dev_priv,
19321 HSYNC(cpu_transcoder));
19322 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19323 VTOTAL(cpu_transcoder));
19324 error->transcoder[i].vblank = intel_de_read(dev_priv,
19325 VBLANK(cpu_transcoder));
19326 error->transcoder[i].vsync = intel_de_read(dev_priv,
19327 VSYNC(cpu_transcoder));
19333 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19336 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19337 struct intel_display_error_state *error)
19339 struct drm_i915_private *dev_priv = m->i915;
19345 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19346 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19347 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19348 error->power_well_driver);
19349 for_each_pipe(dev_priv, i) {
19350 err_printf(m, "Pipe [%d]:\n", i);
19351 err_printf(m, " Power: %s\n",
19352 onoff(error->pipe[i].power_domain_on));
19353 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19354 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19356 err_printf(m, "Plane [%d]:\n", i);
19357 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19358 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19359 if (INTEL_GEN(dev_priv) <= 3) {
19360 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19361 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19363 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19364 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19365 if (INTEL_GEN(dev_priv) >= 4) {
19366 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19367 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19370 err_printf(m, "Cursor [%d]:\n", i);
19371 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19372 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19373 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19376 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19377 if (!error->transcoder[i].available)
19380 err_printf(m, "CPU transcoder: %s\n",
19381 transcoder_name(error->transcoder[i].cpu_transcoder));
19382 err_printf(m, " Power: %s\n",
19383 onoff(error->transcoder[i].power_domain_on));
19384 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19385 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19386 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19387 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19388 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19389 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19390 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);