drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_damage_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "gem/i915_gem_lmem.h"
  46 #include "gem/i915_gem_object.h"
  47
  48 #include "g4x_dp.h"
  49 #include "g4x_hdmi.h"
  50 #include "hsw_ips.h"
  51 #include "i915_drv.h"
  52 #include "i915_reg.h"
  53 #include "i915_utils.h"
  54 #include "i9xx_plane.h"
  55 #include "i9xx_wm.h"
  56 #include "intel_atomic.h"
  57 #include "intel_atomic_plane.h"
  58 #include "intel_audio.h"
  59 #include "intel_bw.h"
  60 #include "intel_cdclk.h"
  61 #include "intel_clock_gating.h"
  62 #include "intel_color.h"
  63 #include "intel_crt.h"
  64 #include "intel_crtc.h"
  65 #include "intel_crtc_state_dump.h"
  66 #include "intel_ddi.h"
  67 #include "intel_de.h"
  68 #include "intel_display_driver.h"
  69 #include "intel_display_power.h"
  70 #include "intel_display_types.h"
  71 #include "intel_dmc.h"
  72 #include "intel_dp.h"
  73 #include "intel_dp_link_training.h"
  74 #include "intel_dp_mst.h"
  75 #include "intel_dpio_phy.h"
  76 #include "intel_dpll.h"
  77 #include "intel_dpll_mgr.h"
  78 #include "intel_dpt.h"
  79 #include "intel_drrs.h"
  80 #include "intel_dsb.h"
  81 #include "intel_dsi.h"
  82 #include "intel_dvo.h"
  83 #include "intel_fb.h"
  84 #include "intel_fbc.h"
  85 #include "intel_fbdev.h"
  86 #include "intel_fdi.h"
  87 #include "intel_fifo_underrun.h"
  88 #include "intel_frontbuffer.h"
  89 #include "intel_hdmi.h"
  90 #include "intel_hotplug.h"
  91 #include "intel_link_bw.h"
  92 #include "intel_lvds.h"
  93 #include "intel_lvds_regs.h"
  94 #include "intel_modeset_setup.h"
  95 #include "intel_modeset_verify.h"
  96 #include "intel_overlay.h"
  97 #include "intel_panel.h"
  98 #include "intel_pch_display.h"
  99 #include "intel_pch_refclk.h"
 100 #include "intel_pcode.h"
 101 #include "intel_pipe_crc.h"
 102 #include "intel_plane_initial.h"
 103 #include "intel_pmdemand.h"
 104 #include "intel_pps.h"
 105 #include "intel_psr.h"
 106 #include "intel_sdvo.h"
 107 #include "intel_snps_phy.h"
 108 #include "intel_tc.h"
 109 #include "intel_tv.h"
 110 #include "intel_vblank.h"
 111 #include "intel_vdsc.h"
 112 #include "intel_vdsc_regs.h"
 113 #include "intel_vga.h"
 114 #include "intel_vrr.h"
 115 #include "intel_wm.h"
 116 #include "skl_scaler.h"
 117 #include "skl_universal_plane.h"
 118 #include "skl_watermark.h"
 119 #include "vlv_dsi.h"
 120 #include "vlv_dsi_pll.h"
 121 #include "vlv_dsi_regs.h"
 122 #include "vlv_sideband.h"
 123
 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 127 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 128
 129 /* returns HPLL frequency in kHz */
 130 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 131 {
 132         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 133
 134         /* Obtain SKU information */
 135         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 136                 CCK_FUSE_HPLL_FREQ_MASK;
 137
 138         return vco_freq[hpll_freq] * 1000;
 139 }
 140
 141 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 142                       const char *name, u32 reg, int ref_freq)
 143 {
 144         u32 val;
 145         int divider;
 146
 147         val = vlv_cck_read(dev_priv, reg);
 148         divider = val & CCK_FREQUENCY_VALUES;
 149
 150         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 151                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 152                  "%s change in progress\n", name);
 153
 154         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 155 }
 156
 157 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 158                            const char *name, u32 reg)
 159 {
 160         int hpll;
 161
 162         vlv_cck_get(dev_priv);
 163
 164         if (dev_priv->hpll_freq == 0)
 165                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 166
 167         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 168
 169         vlv_cck_put(dev_priv);
 170
 171         return hpll;
 172 }
 173
 174 void intel_update_czclk(struct drm_i915_private *dev_priv)
 175 {
 176         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 177                 return;
 178
 179         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 180                                                       CCK_CZ_CLOCK_CONTROL);
 181
 182         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 183                 dev_priv->czclk_freq);
 184 }
 185
 186 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 187 {
 188         return (crtc_state->active_planes &
 189                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 190 }
 191
 192 /* WA Display #0827: Gen9:all */
 193 static void
 194 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 195 {
 196         if (enable)
 197                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 198                              0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 199         else
 200                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 201                              DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
 202 }
 203
 204 /* Wa_2006604312:icl,ehl */
 205 static void
 206 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 207                        bool enable)
 208 {
 209         if (enable)
 210                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
 211         else
 212                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
 213 }
 214
 215 /* Wa_1604331009:icl,jsl,ehl */
 216 static void
 217 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 218                        bool enable)
 219 {
 220         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 221                      enable ? CURSOR_GATING_DIS : 0);
 222 }
 223
 224 static bool
 225 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 226 {
 227         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 228 }
 229
 230 bool
 231 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 232 {
 233         return crtc_state->sync_mode_slaves_mask != 0;
 234 }
 235
 236 bool
 237 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 238 {
 239         return is_trans_port_sync_master(crtc_state) ||
 240                 is_trans_port_sync_slave(crtc_state);
 241 }
 242
 243 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 244 {
 245         return ffs(crtc_state->bigjoiner_pipes) - 1;
 246 }
 247
 248 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 249 {
 250         if (crtc_state->bigjoiner_pipes)
 251                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 252         else
 253                 return 0;
 254 }
 255
 256 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 257 {
 258         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 259
 260         return crtc_state->bigjoiner_pipes &&
 261                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 262 }
 263
 264 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 265 {
 266         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 267
 268         return crtc_state->bigjoiner_pipes &&
 269                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 270 }
 271
 272 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 273 {
 274         return hweight8(crtc_state->bigjoiner_pipes);
 275 }
 276
 277 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 278 {
 279         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 280
 281         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 282                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 283         else
 284                 return to_intel_crtc(crtc_state->uapi.crtc);
 285 }
 286
 287 static void
 288 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 289 {
 290         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 291         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 292
 293         if (DISPLAY_VER(dev_priv) >= 4) {
 294                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 295
 296                 /* Wait for the Pipe State to go off */
 297                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 298                                             TRANSCONF_STATE_ENABLE, 100))
 299                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 300         } else {
 301                 intel_wait_for_pipe_scanline_stopped(crtc);
 302         }
 303 }
 304
 305 void assert_transcoder(struct drm_i915_private *dev_priv,
 306                        enum transcoder cpu_transcoder, bool state)
 307 {
 308         bool cur_state;
 309         enum intel_display_power_domain power_domain;
 310         intel_wakeref_t wakeref;
 311
 312         /* we keep both pipes enabled on 830 */
 313         if (IS_I830(dev_priv))
 314                 state = true;
 315
 316         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 317         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 318         if (wakeref) {
 319                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 320                 cur_state = !!(val & TRANSCONF_ENABLE);
 321
 322                 intel_display_power_put(dev_priv, power_domain, wakeref);
 323         } else {
 324                 cur_state = false;
 325         }
 326
 327         I915_STATE_WARN(dev_priv, cur_state != state,
 328                         "transcoder %s assertion failure (expected %s, current %s)\n",
 329                         transcoder_name(cpu_transcoder), str_on_off(state),
 330                         str_on_off(cur_state));
 331 }
 332
 333 static void assert_plane(struct intel_plane *plane, bool state)
 334 {
 335         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 336         enum pipe pipe;
 337         bool cur_state;
 338
 339         cur_state = plane->get_hw_state(plane, &pipe);
 340
 341         I915_STATE_WARN(i915, cur_state != state,
 342                         "%s assertion failure (expected %s, current %s)\n",
 343                         plane->base.name, str_on_off(state),
 344                         str_on_off(cur_state));
 345 }
 346
 347 #define assert_plane_enabled(p) assert_plane(p, true)
 348 #define assert_plane_disabled(p) assert_plane(p, false)
 349
 350 static void assert_planes_disabled(struct intel_crtc *crtc)
 351 {
 352         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 353         struct intel_plane *plane;
 354
 355         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 356                 assert_plane_disabled(plane);
 357 }
 358
 359 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 360                          struct intel_digital_port *dig_port,
 361                          unsigned int expected_mask)
 362 {
 363         u32 port_mask;
 364         i915_reg_t dpll_reg;
 365
 366         switch (dig_port->base.port) {
 367         default:
 368                 MISSING_CASE(dig_port->base.port);
 369                 fallthrough;
 370         case PORT_B:
 371                 port_mask = DPLL_PORTB_READY_MASK;
 372                 dpll_reg = DPLL(0);
 373                 break;
 374         case PORT_C:
 375                 port_mask = DPLL_PORTC_READY_MASK;
 376                 dpll_reg = DPLL(0);
 377                 expected_mask <<= 4;
 378                 break;
 379         case PORT_D:
 380                 port_mask = DPLL_PORTD_READY_MASK;
 381                 dpll_reg = DPIO_PHY_STATUS;
 382                 break;
 383         }
 384
 385         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 386                                        port_mask, expected_mask, 1000))
 387                 drm_WARN(&dev_priv->drm, 1,
 388                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 389                          dig_port->base.base.base.id, dig_port->base.base.name,
 390                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 391                          expected_mask);
 392 }
 393
 394 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 395 {
 396         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 397         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 398         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 399         enum pipe pipe = crtc->pipe;
 400         i915_reg_t reg;
 401         u32 val;
 402
 403         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 404
 405         assert_planes_disabled(crtc);
 406
 407         /*
 408          * A pipe without a PLL won't actually be able to drive bits from
 409          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 410          * need the check.
 411          */
 412         if (HAS_GMCH(dev_priv)) {
 413                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 414                         assert_dsi_pll_enabled(dev_priv);
 415                 else
 416                         assert_pll_enabled(dev_priv, pipe);
 417         } else {
 418                 if (new_crtc_state->has_pch_encoder) {
 419                         /* if driving the PCH, we need FDI enabled */
 420                         assert_fdi_rx_pll_enabled(dev_priv,
 421                                                   intel_crtc_pch_transcoder(crtc));
 422                         assert_fdi_tx_pll_enabled(dev_priv,
 423                                                   (enum pipe) cpu_transcoder);
 424                 }
 425                 /* FIXME: assert CPU port conditions for SNB+ */
 426         }
 427
 428         /* Wa_22012358565:adl-p */
 429         if (DISPLAY_VER(dev_priv) == 13)
 430                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 431                              0, PIPE_ARB_USE_PROG_SLOTS);
 432
 433         reg = TRANSCONF(cpu_transcoder);
 434         val = intel_de_read(dev_priv, reg);
 435         if (val & TRANSCONF_ENABLE) {
 436                 /* we keep both pipes enabled on 830 */
 437                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 438                 return;
 439         }
 440
 441         intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
 442         intel_de_posting_read(dev_priv, reg);
 443
 444         /*
 445          * Until the pipe starts PIPEDSL reads will return a stale value,
 446          * which causes an apparent vblank timestamp jump when PIPEDSL
 447          * resets to its proper value. That also messes up the frame count
 448          * when it's derived from the timestamps. So let's wait for the
 449          * pipe to start properly before we call drm_crtc_vblank_on()
 450          */
 451         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 452                 intel_wait_for_pipe_scanline_moving(crtc);
 453 }
 454
 455 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 456 {
 457         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 458         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 459         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 460         enum pipe pipe = crtc->pipe;
 461         i915_reg_t reg;
 462         u32 val;
 463
 464         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 465
 466         /*
 467          * Make sure planes won't keep trying to pump pixels to us,
 468          * or we might hang the display.
 469          */
 470         assert_planes_disabled(crtc);
 471
 472         reg = TRANSCONF(cpu_transcoder);
 473         val = intel_de_read(dev_priv, reg);
 474         if ((val & TRANSCONF_ENABLE) == 0)
 475                 return;
 476
 477         /*
 478          * Double wide has implications for planes
 479          * so best keep it disabled when not needed.
 480          */
 481         if (old_crtc_state->double_wide)
 482                 val &= ~TRANSCONF_DOUBLE_WIDE;
 483
 484         /* Don't disable pipe or pipe PLLs if needed */
 485         if (!IS_I830(dev_priv))
 486                 val &= ~TRANSCONF_ENABLE;
 487
 488         if (DISPLAY_VER(dev_priv) >= 14)
 489                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 490                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 491         else if (DISPLAY_VER(dev_priv) >= 12)
 492                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 493                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 494
 495         intel_de_write(dev_priv, reg, val);
 496         if ((val & TRANSCONF_ENABLE) == 0)
 497                 intel_wait_for_pipe_off(old_crtc_state);
 498 }
 499
 500 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 501 {
 502         unsigned int size = 0;
 503         int i;
 504
 505         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 506                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 507
 508         return size;
 509 }
 510
 511 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 512 {
 513         unsigned int size = 0;
 514         int i;
 515
 516         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 517                 unsigned int plane_size;
 518
 519                 if (rem_info->plane[i].linear)
 520                         plane_size = rem_info->plane[i].size;
 521                 else
 522                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 523
 524                 if (plane_size == 0)
 525                         continue;
 526
 527                 if (rem_info->plane_alignment)
 528                         size = ALIGN(size, rem_info->plane_alignment);
 529
 530                 size += plane_size;
 531         }
 532
 533         return size;
 534 }
 535
 536 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 537 {
 538         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 539         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 540
 541         return DISPLAY_VER(dev_priv) < 4 ||
 542                 (plane->fbc &&
 543                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 544 }
 545
 546 /*
 547  * Convert the x/y offsets into a linear offset.
 548  * Only valid with 0/180 degree rotation, which is fine since linear
 549  * offset is only used with linear buffers on pre-hsw and tiled buffers
 550  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 551  */
 552 u32 intel_fb_xy_to_linear(int x, int y,
 553                           const struct intel_plane_state *state,
 554                           int color_plane)
 555 {
 556         const struct drm_framebuffer *fb = state->hw.fb;
 557         unsigned int cpp = fb->format->cpp[color_plane];
 558         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 559
 560         return y * pitch + x * cpp;
 561 }
 562
 563 /*
 564  * Add the x/y offsets derived from fb->offsets[] to the user
 565  * specified plane src x/y offsets. The resulting x/y offsets
 566  * specify the start of scanout from the beginning of the gtt mapping.
 567  */
 568 void intel_add_fb_offsets(int *x, int *y,
 569                           const struct intel_plane_state *state,
 570                           int color_plane)
 571
 572 {
 573         *x += state->view.color_plane[color_plane].x;
 574         *y += state->view.color_plane[color_plane].y;
 575 }
 576
 577 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 578                               u32 pixel_format, u64 modifier)
 579 {
 580         struct intel_crtc *crtc;
 581         struct intel_plane *plane;
 582
 583         if (!HAS_DISPLAY(dev_priv))
 584                 return 0;
 585
 586         /*
 587          * We assume the primary plane for pipe A has
 588          * the highest stride limits of them all,
 589          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 590          */
 591         crtc = intel_first_crtc(dev_priv);
 592         if (!crtc)
 593                 return 0;
 594
 595         plane = to_intel_plane(crtc->base.primary);
 596
 597         return plane->max_stride(plane, pixel_format, modifier,
 598                                  DRM_MODE_ROTATE_0);
 599 }
 600
 601 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 602                              struct intel_plane_state *plane_state,
 603                              bool visible)
 604 {
 605         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 606
 607         plane_state->uapi.visible = visible;
 608
 609         if (visible)
 610                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 611         else
 612                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 613 }
 614
 615 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 616 {
 617         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 618         struct drm_plane *plane;
 619
 620         /*
 621          * Active_planes aliases if multiple "primary" or cursor planes
 622          * have been used on the same (or wrong) pipe. plane_mask uses
 623          * unique ids, hence we can use that to reconstruct active_planes.
 624          */
 625         crtc_state->enabled_planes = 0;
 626         crtc_state->active_planes = 0;
 627
 628         drm_for_each_plane_mask(plane, &dev_priv->drm,
 629                                 crtc_state->uapi.plane_mask) {
 630                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 631                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 632         }
 633 }
 634
 635 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 636                                   struct intel_plane *plane)
 637 {
 638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 639         struct intel_crtc_state *crtc_state =
 640                 to_intel_crtc_state(crtc->base.state);
 641         struct intel_plane_state *plane_state =
 642                 to_intel_plane_state(plane->base.state);
 643
 644         drm_dbg_kms(&dev_priv->drm,
 645                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 646                     plane->base.base.id, plane->base.name,
 647                     crtc->base.base.id, crtc->base.name);
 648
 649         intel_set_plane_visible(crtc_state, plane_state, false);
 650         intel_plane_fixup_bitmasks(crtc_state);
 651         crtc_state->data_rate[plane->id] = 0;
 652         crtc_state->data_rate_y[plane->id] = 0;
 653         crtc_state->rel_data_rate[plane->id] = 0;
 654         crtc_state->rel_data_rate_y[plane->id] = 0;
 655         crtc_state->min_cdclk[plane->id] = 0;
 656
 657         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 658             hsw_ips_disable(crtc_state)) {
 659                 crtc_state->ips_enabled = false;
 660                 intel_crtc_wait_for_next_vblank(crtc);
 661         }
 662
 663         /*
 664          * Vblank time updates from the shadow to live plane control register
 665          * are blocked if the memory self-refresh mode is active at that
 666          * moment. So to make sure the plane gets truly disabled, disable
 667          * first the self-refresh mode. The self-refresh enable bit in turn
 668          * will be checked/applied by the HW only at the next frame start
 669          * event which is after the vblank start event, so we need to have a
 670          * wait-for-vblank between disabling the plane and the pipe.
 671          */
 672         if (HAS_GMCH(dev_priv) &&
 673             intel_set_memory_cxsr(dev_priv, false))
 674                 intel_crtc_wait_for_next_vblank(crtc);
 675
 676         /*
 677          * Gen2 reports pipe underruns whenever all planes are disabled.
 678          * So disable underrun reporting before all the planes get disabled.
 679          */
 680         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 681                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 682
 683         intel_plane_disable_arm(plane, crtc_state);
 684         intel_crtc_wait_for_next_vblank(crtc);
 685 }
 686
 687 unsigned int
 688 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 689 {
 690         int x = 0, y = 0;
 691
 692         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 693                                           plane_state->view.color_plane[0].offset, 0);
 694
 695         return y;
 696 }
 697
 698 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 699 {
 700         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 701         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 702         enum pipe pipe = crtc->pipe;
 703         u32 tmp;
 704
 705         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 706
 707         /*
 708          * Display WA #1153: icl
 709          * enable hardware to bypass the alpha math
 710          * and rounding for per-pixel values 00 and 0xff
 711          */
 712         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 713         /*
 714          * Display WA # 1605353570: icl
 715          * Set the pixel rounding bit to 1 for allowing
 716          * passthrough of Frame buffer pixels unmodified
 717          * across pipe
 718          */
 719         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 720
 721         /*
 722          * Underrun recovery must always be disabled on display 13+.
 723          * DG2 chicken bit meaning is inverted compared to other platforms.
 724          */
 725         if (IS_DG2(dev_priv))
 726                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 727         else if (DISPLAY_VER(dev_priv) >= 13)
 728                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 729
 730         /* Wa_14010547955:dg2 */
 731         if (IS_DG2(dev_priv))
 732                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 733
 734         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 735 }
 736
 737 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 738 {
 739         struct drm_crtc *crtc;
 740         bool cleanup_done;
 741
 742         drm_for_each_crtc(crtc, &dev_priv->drm) {
 743                 struct drm_crtc_commit *commit;
 744                 spin_lock(&crtc->commit_lock);
 745                 commit = list_first_entry_or_null(&crtc->commit_list,
 746                                                   struct drm_crtc_commit, commit_entry);
 747                 cleanup_done = commit ?
 748                         try_wait_for_completion(&commit->cleanup_done) : true;
 749                 spin_unlock(&crtc->commit_lock);
 750
 751                 if (cleanup_done)
 752                         continue;
 753
 754                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 755
 756                 return true;
 757         }
 758
 759         return false;
 760 }
 761
 762 /*
 763  * Finds the encoder associated with the given CRTC. This can only be
 764  * used when we know that the CRTC isn't feeding multiple encoders!
 765  */
 766 struct intel_encoder *
 767 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 768                            const struct intel_crtc_state *crtc_state)
 769 {
 770         const struct drm_connector_state *connector_state;
 771         const struct drm_connector *connector;
 772         struct intel_encoder *encoder = NULL;
 773         struct intel_crtc *master_crtc;
 774         int num_encoders = 0;
 775         int i;
 776
 777         master_crtc = intel_master_crtc(crtc_state);
 778
 779         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 780                 if (connector_state->crtc != &master_crtc->base)
 781                         continue;
 782
 783                 encoder = to_intel_encoder(connector_state->best_encoder);
 784                 num_encoders++;
 785         }
 786
 787         drm_WARN(state->base.dev, num_encoders != 1,
 788                  "%d encoders for pipe %c\n",
 789                  num_encoders, pipe_name(master_crtc->pipe));
 790
 791         return encoder;
 792 }
 793
 794 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 795 {
 796         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 797         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 798         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 799         enum pipe pipe = crtc->pipe;
 800         int width = drm_rect_width(dst);
 801         int height = drm_rect_height(dst);
 802         int x = dst->x1;
 803         int y = dst->y1;
 804
 805         if (!crtc_state->pch_pfit.enabled)
 806                 return;
 807
 808         /* Force use of hard-coded filter coefficients
 809          * as some pre-programmed values are broken,
 810          * e.g. x201.
 811          */
 812         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 813                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 814                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 815         else
 816                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 817                                   PF_FILTER_MED_3x3);
 818         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 819                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 820         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 821                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 822 }
 823
 824 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 825 {
 826         if (crtc->overlay)
 827                 (void) intel_overlay_switch_off(crtc->overlay);
 828
 829         /* Let userspace switch the overlay on again. In most cases userspace
 830          * has to recompute where to put it anyway.
 831          */
 832 }
 833
 834 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 835 {
 836         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 837
 838         if (!crtc_state->nv12_planes)
 839                 return false;
 840
 841         /* WA Display #0827: Gen9:all */
 842         if (DISPLAY_VER(dev_priv) == 9)
 843                 return true;
 844
 845         return false;
 846 }
 847
 848 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 849 {
 850         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 851
 852         /* Wa_2006604312:icl,ehl */
 853         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 854                 return true;
 855
 856         return false;
 857 }
 858
 859 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 860 {
 861         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 862
 863         /* Wa_1604331009:icl,jsl,ehl */
 864         if (is_hdr_mode(crtc_state) &&
 865             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 866             DISPLAY_VER(dev_priv) == 11)
 867                 return true;
 868
 869         return false;
 870 }
 871
 872 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 873                                     enum pipe pipe, bool enable)
 874 {
 875         if (DISPLAY_VER(i915) == 9) {
 876                 /*
 877                  * "Plane N strech max must be programmed to 11b (x1)
 878                  *  when Async flips are enabled on that plane."
 879                  */
 880                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 881                              SKL_PLANE1_STRETCH_MAX_MASK,
 882                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 883         } else {
 884                 /* Also needed on HSW/BDW albeit undocumented */
 885                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 886                              HSW_PRI_STRETCH_MAX_MASK,
 887                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 888         }
 889 }
 890
 891 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 892 {
 893         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 894
 895         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 896                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 897 }
 898
 899 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 900         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 901          (new_crtc_state)->feature)
 902 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 903         ((old_crtc_state)->feature && \
 904          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 905
 906 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 907                             const struct intel_crtc_state *new_crtc_state)
 908 {
 909         if (!new_crtc_state->hw.active)
 910                 return false;
 911
 912         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 913 }
 914
 915 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 916                              const struct intel_crtc_state *new_crtc_state)
 917 {
 918         if (!old_crtc_state->hw.active)
 919                 return false;
 920
 921         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 922 }
 923
 924 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 925                                const struct intel_crtc_state *new_crtc_state)
 926 {
 927         return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
 928                 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
 929                 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
 930                 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
 931                 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 932 }
 933
 934 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 935                          const struct intel_crtc_state *new_crtc_state)
 936 {
 937         if (!new_crtc_state->hw.active)
 938                 return false;
 939
 940         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 941                 (new_crtc_state->vrr.enable &&
 942                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 943                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 944 }
 945
 946 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 947                           const struct intel_crtc_state *new_crtc_state)
 948 {
 949         if (!old_crtc_state->hw.active)
 950                 return false;
 951
 952         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 953                 (old_crtc_state->vrr.enable &&
 954                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 955                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 956 }
 957
 958 #undef is_disabling
 959 #undef is_enabling
 960
 961 static void intel_post_plane_update(struct intel_atomic_state *state,
 962                                     struct intel_crtc *crtc)
 963 {
 964         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 965         const struct intel_crtc_state *old_crtc_state =
 966                 intel_atomic_get_old_crtc_state(state, crtc);
 967         const struct intel_crtc_state *new_crtc_state =
 968                 intel_atomic_get_new_crtc_state(state, crtc);
 969         enum pipe pipe = crtc->pipe;
 970
 971         intel_psr_post_plane_update(state, crtc);
 972
 973         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 974
 975         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 976                 intel_update_watermarks(dev_priv);
 977
 978         intel_fbc_post_update(state, crtc);
 979
 980         if (needs_async_flip_vtd_wa(old_crtc_state) &&
 981             !needs_async_flip_vtd_wa(new_crtc_state))
 982                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
 983
 984         if (needs_nv12_wa(old_crtc_state) &&
 985             !needs_nv12_wa(new_crtc_state))
 986                 skl_wa_827(dev_priv, pipe, false);
 987
 988         if (needs_scalerclk_wa(old_crtc_state) &&
 989             !needs_scalerclk_wa(new_crtc_state))
 990                 icl_wa_scalerclkgating(dev_priv, pipe, false);
 991
 992         if (needs_cursorclk_wa(old_crtc_state) &&
 993             !needs_cursorclk_wa(new_crtc_state))
 994                 icl_wa_cursorclkgating(dev_priv, pipe, false);
 995
 996         if (intel_crtc_needs_color_update(new_crtc_state))
 997                 intel_color_post_update(new_crtc_state);
 998 }
 999
1000 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1001                                         struct intel_crtc *crtc)
1002 {
1003         const struct intel_crtc_state *crtc_state =
1004                 intel_atomic_get_new_crtc_state(state, crtc);
1005         u8 update_planes = crtc_state->update_planes;
1006         const struct intel_plane_state __maybe_unused *plane_state;
1007         struct intel_plane *plane;
1008         int i;
1009
1010         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1011                 if (plane->pipe == crtc->pipe &&
1012                     update_planes & BIT(plane->id))
1013                         plane->enable_flip_done(plane);
1014         }
1015 }
1016
1017 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1018                                          struct intel_crtc *crtc)
1019 {
1020         const struct intel_crtc_state *crtc_state =
1021                 intel_atomic_get_new_crtc_state(state, crtc);
1022         u8 update_planes = crtc_state->update_planes;
1023         const struct intel_plane_state __maybe_unused *plane_state;
1024         struct intel_plane *plane;
1025         int i;
1026
1027         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1028                 if (plane->pipe == crtc->pipe &&
1029                     update_planes & BIT(plane->id))
1030                         plane->disable_flip_done(plane);
1031         }
1032 }
1033
1034 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1035                                              struct intel_crtc *crtc)
1036 {
1037         const struct intel_crtc_state *old_crtc_state =
1038                 intel_atomic_get_old_crtc_state(state, crtc);
1039         const struct intel_crtc_state *new_crtc_state =
1040                 intel_atomic_get_new_crtc_state(state, crtc);
1041         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1042                                        ~new_crtc_state->async_flip_planes;
1043         const struct intel_plane_state *old_plane_state;
1044         struct intel_plane *plane;
1045         bool need_vbl_wait = false;
1046         int i;
1047
1048         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1049                 if (plane->need_async_flip_disable_wa &&
1050                     plane->pipe == crtc->pipe &&
1051                     disable_async_flip_planes & BIT(plane->id)) {
1052                         /*
1053                          * Apart from the async flip bit we want to
1054                          * preserve the old state for the plane.
1055                          */
1056                         plane->async_flip(plane, old_crtc_state,
1057                                           old_plane_state, false);
1058                         need_vbl_wait = true;
1059                 }
1060         }
1061
1062         if (need_vbl_wait)
1063                 intel_crtc_wait_for_next_vblank(crtc);
1064 }
1065
1066 static void intel_pre_plane_update(struct intel_atomic_state *state,
1067                                    struct intel_crtc *crtc)
1068 {
1069         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1070         const struct intel_crtc_state *old_crtc_state =
1071                 intel_atomic_get_old_crtc_state(state, crtc);
1072         const struct intel_crtc_state *new_crtc_state =
1073                 intel_atomic_get_new_crtc_state(state, crtc);
1074         enum pipe pipe = crtc->pipe;
1075
1076         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1077                 intel_vrr_disable(old_crtc_state);
1078                 intel_crtc_update_active_timings(old_crtc_state, false);
1079         }
1080
1081         intel_drrs_deactivate(old_crtc_state);
1082
1083         intel_psr_pre_plane_update(state, crtc);
1084
1085         if (hsw_ips_pre_update(state, crtc))
1086                 intel_crtc_wait_for_next_vblank(crtc);
1087
1088         if (intel_fbc_pre_update(state, crtc))
1089                 intel_crtc_wait_for_next_vblank(crtc);
1090
1091         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1092             needs_async_flip_vtd_wa(new_crtc_state))
1093                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1094
1095         /* Display WA 827 */
1096         if (!needs_nv12_wa(old_crtc_state) &&
1097             needs_nv12_wa(new_crtc_state))
1098                 skl_wa_827(dev_priv, pipe, true);
1099
1100         /* Wa_2006604312:icl,ehl */
1101         if (!needs_scalerclk_wa(old_crtc_state) &&
1102             needs_scalerclk_wa(new_crtc_state))
1103                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1104
1105         /* Wa_1604331009:icl,jsl,ehl */
1106         if (!needs_cursorclk_wa(old_crtc_state) &&
1107             needs_cursorclk_wa(new_crtc_state))
1108                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1109
1110         /*
1111          * Vblank time updates from the shadow to live plane control register
1112          * are blocked if the memory self-refresh mode is active at that
1113          * moment. So to make sure the plane gets truly disabled, disable
1114          * first the self-refresh mode. The self-refresh enable bit in turn
1115          * will be checked/applied by the HW only at the next frame start
1116          * event which is after the vblank start event, so we need to have a
1117          * wait-for-vblank between disabling the plane and the pipe.
1118          */
1119         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1120             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1121                 intel_crtc_wait_for_next_vblank(crtc);
1122
1123         /*
1124          * IVB workaround: must disable low power watermarks for at least
1125          * one frame before enabling scaling.  LP watermarks can be re-enabled
1126          * when scaling is disabled.
1127          *
1128          * WaCxSRDisabledForSpriteScaling:ivb
1129          */
1130         if (old_crtc_state->hw.active &&
1131             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1132                 intel_crtc_wait_for_next_vblank(crtc);
1133
1134         /*
1135          * If we're doing a modeset we don't need to do any
1136          * pre-vblank watermark programming here.
1137          */
1138         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1139                 /*
1140                  * For platforms that support atomic watermarks, program the
1141                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1142                  * will be the intermediate values that are safe for both pre- and
1143                  * post- vblank; when vblank happens, the 'active' values will be set
1144                  * to the final 'target' values and we'll do this again to get the
1145                  * optimal watermarks.  For gen9+ platforms, the values we program here
1146                  * will be the final target values which will get automatically latched
1147                  * at vblank time; no further programming will be necessary.
1148                  *
1149                  * If a platform hasn't been transitioned to atomic watermarks yet,
1150                  * we'll continue to update watermarks the old way, if flags tell
1151                  * us to.
1152                  */
1153                 if (!intel_initial_watermarks(state, crtc))
1154                         if (new_crtc_state->update_wm_pre)
1155                                 intel_update_watermarks(dev_priv);
1156         }
1157
1158         /*
1159          * Gen2 reports pipe underruns whenever all planes are disabled.
1160          * So disable underrun reporting before all the planes get disabled.
1161          *
1162          * We do this after .initial_watermarks() so that we have a
1163          * chance of catching underruns with the intermediate watermarks
1164          * vs. the old plane configuration.
1165          */
1166         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1167                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1168
1169         /*
1170          * WA for platforms where async address update enable bit
1171          * is double buffered and only latched at start of vblank.
1172          */
1173         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1174                 intel_crtc_async_flip_disable_wa(state, crtc);
1175 }
1176
1177 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1178                                       struct intel_crtc *crtc)
1179 {
1180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1181         const struct intel_crtc_state *new_crtc_state =
1182                 intel_atomic_get_new_crtc_state(state, crtc);
1183         unsigned int update_mask = new_crtc_state->update_planes;
1184         const struct intel_plane_state *old_plane_state;
1185         struct intel_plane *plane;
1186         unsigned fb_bits = 0;
1187         int i;
1188
1189         intel_crtc_dpms_overlay_disable(crtc);
1190
1191         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1192                 if (crtc->pipe != plane->pipe ||
1193                     !(update_mask & BIT(plane->id)))
1194                         continue;
1195
1196                 intel_plane_disable_arm(plane, new_crtc_state);
1197
1198                 if (old_plane_state->uapi.visible)
1199                         fb_bits |= plane->frontbuffer_bit;
1200         }
1201
1202         intel_frontbuffer_flip(dev_priv, fb_bits);
1203 }
1204
1205 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1206 {
1207         struct drm_i915_private *i915 = to_i915(state->base.dev);
1208         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1209         struct intel_crtc *crtc;
1210         int i;
1211
1212         /*
1213          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1214          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1215          */
1216         if (i915->display.dpll.mgr) {
1217                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1218                         if (intel_crtc_needs_modeset(new_crtc_state))
1219                                 continue;
1220
1221                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1222                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1223                 }
1224         }
1225 }
1226
1227 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1228                                           struct intel_crtc *crtc)
1229 {
1230         const struct intel_crtc_state *crtc_state =
1231                 intel_atomic_get_new_crtc_state(state, crtc);
1232         const struct drm_connector_state *conn_state;
1233         struct drm_connector *conn;
1234         int i;
1235
1236         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1237                 struct intel_encoder *encoder =
1238                         to_intel_encoder(conn_state->best_encoder);
1239
1240                 if (conn_state->crtc != &crtc->base)
1241                         continue;
1242
1243                 if (encoder->pre_pll_enable)
1244                         encoder->pre_pll_enable(state, encoder,
1245                                                 crtc_state, conn_state);
1246         }
1247 }
1248
1249 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1250                                       struct intel_crtc *crtc)
1251 {
1252         const struct intel_crtc_state *crtc_state =
1253                 intel_atomic_get_new_crtc_state(state, crtc);
1254         const struct drm_connector_state *conn_state;
1255         struct drm_connector *conn;
1256         int i;
1257
1258         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1259                 struct intel_encoder *encoder =
1260                         to_intel_encoder(conn_state->best_encoder);
1261
1262                 if (conn_state->crtc != &crtc->base)
1263                         continue;
1264
1265                 if (encoder->pre_enable)
1266                         encoder->pre_enable(state, encoder,
1267                                             crtc_state, conn_state);
1268         }
1269 }
1270
1271 static void intel_encoders_enable(struct intel_atomic_state *state,
1272                                   struct intel_crtc *crtc)
1273 {
1274         const struct intel_crtc_state *crtc_state =
1275                 intel_atomic_get_new_crtc_state(state, crtc);
1276         const struct drm_connector_state *conn_state;
1277         struct drm_connector *conn;
1278         int i;
1279
1280         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1281                 struct intel_encoder *encoder =
1282                         to_intel_encoder(conn_state->best_encoder);
1283
1284                 if (conn_state->crtc != &crtc->base)
1285                         continue;
1286
1287                 if (encoder->enable)
1288                         encoder->enable(state, encoder,
1289                                         crtc_state, conn_state);
1290                 intel_opregion_notify_encoder(encoder, true);
1291         }
1292 }
1293
1294 static void intel_encoders_disable(struct intel_atomic_state *state,
1295                                    struct intel_crtc *crtc)
1296 {
1297         const struct intel_crtc_state *old_crtc_state =
1298                 intel_atomic_get_old_crtc_state(state, crtc);
1299         const struct drm_connector_state *old_conn_state;
1300         struct drm_connector *conn;
1301         int i;
1302
1303         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1304                 struct intel_encoder *encoder =
1305                         to_intel_encoder(old_conn_state->best_encoder);
1306
1307                 if (old_conn_state->crtc != &crtc->base)
1308                         continue;
1309
1310                 intel_opregion_notify_encoder(encoder, false);
1311                 if (encoder->disable)
1312                         encoder->disable(state, encoder,
1313                                          old_crtc_state, old_conn_state);
1314         }
1315 }
1316
1317 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1318                                         struct intel_crtc *crtc)
1319 {
1320         const struct intel_crtc_state *old_crtc_state =
1321                 intel_atomic_get_old_crtc_state(state, crtc);
1322         const struct drm_connector_state *old_conn_state;
1323         struct drm_connector *conn;
1324         int i;
1325
1326         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1327                 struct intel_encoder *encoder =
1328                         to_intel_encoder(old_conn_state->best_encoder);
1329
1330                 if (old_conn_state->crtc != &crtc->base)
1331                         continue;
1332
1333                 if (encoder->post_disable)
1334                         encoder->post_disable(state, encoder,
1335                                               old_crtc_state, old_conn_state);
1336         }
1337 }
1338
1339 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1340                                             struct intel_crtc *crtc)
1341 {
1342         const struct intel_crtc_state *old_crtc_state =
1343                 intel_atomic_get_old_crtc_state(state, crtc);
1344         const struct drm_connector_state *old_conn_state;
1345         struct drm_connector *conn;
1346         int i;
1347
1348         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1349                 struct intel_encoder *encoder =
1350                         to_intel_encoder(old_conn_state->best_encoder);
1351
1352                 if (old_conn_state->crtc != &crtc->base)
1353                         continue;
1354
1355                 if (encoder->post_pll_disable)
1356                         encoder->post_pll_disable(state, encoder,
1357                                                   old_crtc_state, old_conn_state);
1358         }
1359 }
1360
1361 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1362                                        struct intel_crtc *crtc)
1363 {
1364         const struct intel_crtc_state *crtc_state =
1365                 intel_atomic_get_new_crtc_state(state, crtc);
1366         const struct drm_connector_state *conn_state;
1367         struct drm_connector *conn;
1368         int i;
1369
1370         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1371                 struct intel_encoder *encoder =
1372                         to_intel_encoder(conn_state->best_encoder);
1373
1374                 if (conn_state->crtc != &crtc->base)
1375                         continue;
1376
1377                 if (encoder->update_pipe)
1378                         encoder->update_pipe(state, encoder,
1379                                              crtc_state, conn_state);
1380         }
1381 }
1382
1383 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1384 {
1385         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1386         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1387
1388         plane->disable_arm(plane, crtc_state);
1389 }
1390
1391 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1392 {
1393         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1394         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1395
1396         if (crtc_state->has_pch_encoder) {
1397                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1398                                                &crtc_state->fdi_m_n);
1399         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1400                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1401                                                &crtc_state->dp_m_n);
1402                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1403                                                &crtc_state->dp_m2_n2);
1404         }
1405
1406         intel_set_transcoder_timings(crtc_state);
1407
1408         ilk_set_pipeconf(crtc_state);
1409 }
1410
1411 static void ilk_crtc_enable(struct intel_atomic_state *state,
1412                             struct intel_crtc *crtc)
1413 {
1414         const struct intel_crtc_state *new_crtc_state =
1415                 intel_atomic_get_new_crtc_state(state, crtc);
1416         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1417         enum pipe pipe = crtc->pipe;
1418
1419         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1420                 return;
1421
1422         /*
1423          * Sometimes spurious CPU pipe underruns happen during FDI
1424          * training, at least with VGA+HDMI cloning. Suppress them.
1425          *
1426          * On ILK we get an occasional spurious CPU pipe underruns
1427          * between eDP port A enable and vdd enable. Also PCH port
1428          * enable seems to result in the occasional CPU pipe underrun.
1429          *
1430          * Spurious PCH underruns also occur during PCH enabling.
1431          */
1432         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1433         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1434
1435         ilk_configure_cpu_transcoder(new_crtc_state);
1436
1437         intel_set_pipe_src_size(new_crtc_state);
1438
1439         crtc->active = true;
1440
1441         intel_encoders_pre_enable(state, crtc);
1442
1443         if (new_crtc_state->has_pch_encoder) {
1444                 ilk_pch_pre_enable(state, crtc);
1445         } else {
1446                 assert_fdi_tx_disabled(dev_priv, pipe);
1447                 assert_fdi_rx_disabled(dev_priv, pipe);
1448         }
1449
1450         ilk_pfit_enable(new_crtc_state);
1451
1452         /*
1453          * On ILK+ LUT must be loaded before the pipe is running but with
1454          * clocks enabled
1455          */
1456         intel_color_load_luts(new_crtc_state);
1457         intel_color_commit_noarm(new_crtc_state);
1458         intel_color_commit_arm(new_crtc_state);
1459         /* update DSPCNTR to configure gamma for pipe bottom color */
1460         intel_disable_primary_plane(new_crtc_state);
1461
1462         intel_initial_watermarks(state, crtc);
1463         intel_enable_transcoder(new_crtc_state);
1464
1465         if (new_crtc_state->has_pch_encoder)
1466                 ilk_pch_enable(state, crtc);
1467
1468         intel_crtc_vblank_on(new_crtc_state);
1469
1470         intel_encoders_enable(state, crtc);
1471
1472         if (HAS_PCH_CPT(dev_priv))
1473                 intel_wait_for_pipe_scanline_moving(crtc);
1474
1475         /*
1476          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1477          * And a second vblank wait is needed at least on ILK with
1478          * some interlaced HDMI modes. Let's do the double wait always
1479          * in case there are more corner cases we don't know about.
1480          */
1481         if (new_crtc_state->has_pch_encoder) {
1482                 intel_crtc_wait_for_next_vblank(crtc);
1483                 intel_crtc_wait_for_next_vblank(crtc);
1484         }
1485         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1486         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1487 }
1488
1489 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1490                                             enum pipe pipe, bool apply)
1491 {
1492         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1493         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1494
1495         if (apply)
1496                 val |= mask;
1497         else
1498                 val &= ~mask;
1499
1500         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1501 }
1502
1503 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1504 {
1505         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1506         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1507
1508         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1509                        HSW_LINETIME(crtc_state->linetime) |
1510                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1511 }
1512
1513 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1514 {
1515         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1517         enum transcoder transcoder = crtc_state->cpu_transcoder;
1518         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1519                          CHICKEN_TRANS(transcoder);
1520
1521         intel_de_rmw(dev_priv, reg,
1522                      HSW_FRAME_START_DELAY_MASK,
1523                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1524 }
1525
1526 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1527                                          const struct intel_crtc_state *crtc_state)
1528 {
1529         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1530
1531         /*
1532          * Enable sequence steps 1-7 on bigjoiner master
1533          */
1534         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1535                 intel_encoders_pre_pll_enable(state, master_crtc);
1536
1537         if (crtc_state->shared_dpll)
1538                 intel_enable_shared_dpll(crtc_state);
1539
1540         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1541                 intel_encoders_pre_enable(state, master_crtc);
1542 }
1543
1544 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1545 {
1546         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1547         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1548         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1549
1550         if (crtc_state->has_pch_encoder) {
1551                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1552                                                &crtc_state->fdi_m_n);
1553         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1554                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1555                                                &crtc_state->dp_m_n);
1556                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1557                                                &crtc_state->dp_m2_n2);
1558         }
1559
1560         intel_set_transcoder_timings(crtc_state);
1561         if (HAS_VRR(dev_priv))
1562                 intel_vrr_set_transcoder_timings(crtc_state);
1563
1564         if (cpu_transcoder != TRANSCODER_EDP)
1565                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1566                                crtc_state->pixel_multiplier - 1);
1567
1568         hsw_set_frame_start_delay(crtc_state);
1569
1570         hsw_set_transconf(crtc_state);
1571 }
1572
1573 static void hsw_crtc_enable(struct intel_atomic_state *state,
1574                             struct intel_crtc *crtc)
1575 {
1576         const struct intel_crtc_state *new_crtc_state =
1577                 intel_atomic_get_new_crtc_state(state, crtc);
1578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1580         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1581         bool psl_clkgate_wa;
1582
1583         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1584                 return;
1585
1586         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1587
1588         if (!new_crtc_state->bigjoiner_pipes) {
1589                 intel_encoders_pre_pll_enable(state, crtc);
1590
1591                 if (new_crtc_state->shared_dpll)
1592                         intel_enable_shared_dpll(new_crtc_state);
1593
1594                 intel_encoders_pre_enable(state, crtc);
1595         } else {
1596                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1597         }
1598
1599         intel_dsc_enable(new_crtc_state);
1600
1601         if (DISPLAY_VER(dev_priv) >= 13)
1602                 intel_uncompressed_joiner_enable(new_crtc_state);
1603
1604         intel_set_pipe_src_size(new_crtc_state);
1605         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1606                 bdw_set_pipe_misc(new_crtc_state);
1607
1608         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1609             !transcoder_is_dsi(cpu_transcoder))
1610                 hsw_configure_cpu_transcoder(new_crtc_state);
1611
1612         crtc->active = true;
1613
1614         /* Display WA #1180: WaDisableScalarClockGating: glk */
1615         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1616                 new_crtc_state->pch_pfit.enabled;
1617         if (psl_clkgate_wa)
1618                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1619
1620         if (DISPLAY_VER(dev_priv) >= 9)
1621                 skl_pfit_enable(new_crtc_state);
1622         else
1623                 ilk_pfit_enable(new_crtc_state);
1624
1625         /*
1626          * On ILK+ LUT must be loaded before the pipe is running but with
1627          * clocks enabled
1628          */
1629         intel_color_load_luts(new_crtc_state);
1630         intel_color_commit_noarm(new_crtc_state);
1631         intel_color_commit_arm(new_crtc_state);
1632         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1633         if (DISPLAY_VER(dev_priv) < 9)
1634                 intel_disable_primary_plane(new_crtc_state);
1635
1636         hsw_set_linetime_wm(new_crtc_state);
1637
1638         if (DISPLAY_VER(dev_priv) >= 11)
1639                 icl_set_pipe_chicken(new_crtc_state);
1640
1641         intel_initial_watermarks(state, crtc);
1642
1643         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1644                 intel_crtc_vblank_on(new_crtc_state);
1645
1646         intel_encoders_enable(state, crtc);
1647
1648         if (psl_clkgate_wa) {
1649                 intel_crtc_wait_for_next_vblank(crtc);
1650                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1651         }
1652
1653         /* If we change the relative order between pipe/planes enabling, we need
1654          * to change the workaround. */
1655         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1656         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1657                 struct intel_crtc *wa_crtc;
1658
1659                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1660
1661                 intel_crtc_wait_for_next_vblank(wa_crtc);
1662                 intel_crtc_wait_for_next_vblank(wa_crtc);
1663         }
1664 }
1665
1666 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1667 {
1668         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1669         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* To avoid upsetting the power well on haswell only disable the pfit if
1673          * it's in use. The hw state code will make sure we get this right. */
1674         if (!old_crtc_state->pch_pfit.enabled)
1675                 return;
1676
1677         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1678         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1679         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1680 }
1681
1682 static void ilk_crtc_disable(struct intel_atomic_state *state,
1683                              struct intel_crtc *crtc)
1684 {
1685         const struct intel_crtc_state *old_crtc_state =
1686                 intel_atomic_get_old_crtc_state(state, crtc);
1687         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /*
1691          * Sometimes spurious CPU pipe underruns happen when the
1692          * pipe is already disabled, but FDI RX/TX is still enabled.
1693          * Happens at least with VGA+HDMI cloning. Suppress them.
1694          */
1695         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1696         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1697
1698         intel_encoders_disable(state, crtc);
1699
1700         intel_crtc_vblank_off(old_crtc_state);
1701
1702         intel_disable_transcoder(old_crtc_state);
1703
1704         ilk_pfit_disable(old_crtc_state);
1705
1706         if (old_crtc_state->has_pch_encoder)
1707                 ilk_pch_disable(state, crtc);
1708
1709         intel_encoders_post_disable(state, crtc);
1710
1711         if (old_crtc_state->has_pch_encoder)
1712                 ilk_pch_post_disable(state, crtc);
1713
1714         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1715         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1716
1717         intel_disable_shared_dpll(old_crtc_state);
1718 }
1719
1720 static void hsw_crtc_disable(struct intel_atomic_state *state,
1721                              struct intel_crtc *crtc)
1722 {
1723         const struct intel_crtc_state *old_crtc_state =
1724                 intel_atomic_get_old_crtc_state(state, crtc);
1725         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1726
1727         /*
1728          * FIXME collapse everything to one hook.
1729          * Need care with mst->ddi interactions.
1730          */
1731         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1732                 intel_encoders_disable(state, crtc);
1733                 intel_encoders_post_disable(state, crtc);
1734         }
1735
1736         intel_disable_shared_dpll(old_crtc_state);
1737
1738         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1739                 struct intel_crtc *slave_crtc;
1740
1741                 intel_encoders_post_pll_disable(state, crtc);
1742
1743                 intel_dmc_disable_pipe(i915, crtc->pipe);
1744
1745                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1746                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1747                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1748         }
1749 }
1750
1751 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1752 {
1753         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1754         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1755
1756         if (!crtc_state->gmch_pfit.control)
1757                 return;
1758
1759         /*
1760          * The panel fitter should only be adjusted whilst the pipe is disabled,
1761          * according to register description and PRM.
1762          */
1763         drm_WARN_ON(&dev_priv->drm,
1764                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1765         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1766
1767         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1768                        crtc_state->gmch_pfit.pgm_ratios);
1769         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1770
1771         /* Border color in case we don't scale up to the full screen. Black by
1772          * default, change to something else for debugging. */
1773         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1774 }
1775
1776 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1777 {
1778         if (phy == PHY_NONE)
1779                 return false;
1780         else if (IS_ALDERLAKE_S(dev_priv))
1781                 return phy <= PHY_E;
1782         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1783                 return phy <= PHY_D;
1784         else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1785                 return phy <= PHY_C;
1786         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1787                 return phy <= PHY_B;
1788         else
1789                 /*
1790                  * DG2 outputs labelled as "combo PHY" in the bspec use
1791                  * SNPS PHYs with completely different programming,
1792                  * hence we always return false here.
1793                  */
1794                 return false;
1795 }
1796
1797 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1798 {
1799         if (IS_DG2(dev_priv))
1800                 /* DG2's "TC1" output uses a SNPS PHY */
1801                 return false;
1802         else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
1803                 return phy >= PHY_F && phy <= PHY_I;
1804         else if (IS_TIGERLAKE(dev_priv))
1805                 return phy >= PHY_D && phy <= PHY_I;
1806         else if (IS_ICELAKE(dev_priv))
1807                 return phy >= PHY_C && phy <= PHY_F;
1808         else
1809                 return false;
1810 }
1811
1812 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1813 {
1814         if (phy == PHY_NONE)
1815                 return false;
1816         else if (IS_DG2(dev_priv))
1817                 /*
1818                  * All four "combo" ports and the TC1 port (PHY E) use
1819                  * Synopsis PHYs.
1820                  */
1821                 return phy <= PHY_E;
1822
1823         return false;
1824 }
1825
1826 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1827 {
1828         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1829                 return PHY_D + port - PORT_D_XELPD;
1830         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1831                 return PHY_F + port - PORT_TC1;
1832         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1833                 return PHY_B + port - PORT_TC1;
1834         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1835                 return PHY_C + port - PORT_TC1;
1836         else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1837                  port == PORT_D)
1838                 return PHY_A;
1839
1840         return PHY_A + port - PORT_A;
1841 }
1842
1843 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1844 {
1845         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1846                 return TC_PORT_NONE;
1847
1848         if (DISPLAY_VER(dev_priv) >= 12)
1849                 return TC_PORT_1 + port - PORT_TC1;
1850         else
1851                 return TC_PORT_1 + port - PORT_C;
1852 }
1853
1854 enum intel_display_power_domain
1855 intel_aux_power_domain(struct intel_digital_port *dig_port)
1856 {
1857         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1858
1859         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1860                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1861
1862         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1863 }
1864
1865 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1866                                    struct intel_power_domain_mask *mask)
1867 {
1868         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1869         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1870         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1871         struct drm_encoder *encoder;
1872         enum pipe pipe = crtc->pipe;
1873
1874         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1875
1876         if (!crtc_state->hw.active)
1877                 return;
1878
1879         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1880         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1881         if (crtc_state->pch_pfit.enabled ||
1882             crtc_state->pch_pfit.force_thru)
1883                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1884
1885         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1886                                   crtc_state->uapi.encoder_mask) {
1887                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1888
1889                 set_bit(intel_encoder->power_domain, mask->bits);
1890         }
1891
1892         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
1893                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1894
1895         if (crtc_state->shared_dpll)
1896                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1897
1898         if (crtc_state->dsc.compression_enable)
1899                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1900 }
1901
1902 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1903                                           struct intel_power_domain_mask *old_domains)
1904 {
1905         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1906         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1907         enum intel_display_power_domain domain;
1908         struct intel_power_domain_mask domains, new_domains;
1909
1910         get_crtc_power_domains(crtc_state, &domains);
1911
1912         bitmap_andnot(new_domains.bits,
1913                       domains.bits,
1914                       crtc->enabled_power_domains.mask.bits,
1915                       POWER_DOMAIN_NUM);
1916         bitmap_andnot(old_domains->bits,
1917                       crtc->enabled_power_domains.mask.bits,
1918                       domains.bits,
1919                       POWER_DOMAIN_NUM);
1920
1921         for_each_power_domain(domain, &new_domains)
1922                 intel_display_power_get_in_set(dev_priv,
1923                                                &crtc->enabled_power_domains,
1924                                                domain);
1925 }
1926
1927 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1928                                           struct intel_power_domain_mask *domains)
1929 {
1930         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
1931                                             &crtc->enabled_power_domains,
1932                                             domains);
1933 }
1934
1935 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1936 {
1937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1938         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1939
1940         if (intel_crtc_has_dp_encoder(crtc_state)) {
1941                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1942                                                &crtc_state->dp_m_n);
1943                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1944                                                &crtc_state->dp_m2_n2);
1945         }
1946
1947         intel_set_transcoder_timings(crtc_state);
1948
1949         i9xx_set_pipeconf(crtc_state);
1950 }
1951
1952 static void valleyview_crtc_enable(struct intel_atomic_state *state,
1953                                    struct intel_crtc *crtc)
1954 {
1955         const struct intel_crtc_state *new_crtc_state =
1956                 intel_atomic_get_new_crtc_state(state, crtc);
1957         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1958         enum pipe pipe = crtc->pipe;
1959
1960         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1961                 return;
1962
1963         i9xx_configure_cpu_transcoder(new_crtc_state);
1964
1965         intel_set_pipe_src_size(new_crtc_state);
1966
1967         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
1968
1969         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1970                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
1971                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
1972         }
1973
1974         crtc->active = true;
1975
1976         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1977
1978         intel_encoders_pre_pll_enable(state, crtc);
1979
1980         if (IS_CHERRYVIEW(dev_priv))
1981                 chv_enable_pll(new_crtc_state);
1982         else
1983                 vlv_enable_pll(new_crtc_state);
1984
1985         intel_encoders_pre_enable(state, crtc);
1986
1987         i9xx_pfit_enable(new_crtc_state);
1988
1989         intel_color_load_luts(new_crtc_state);
1990         intel_color_commit_noarm(new_crtc_state);
1991         intel_color_commit_arm(new_crtc_state);
1992         /* update DSPCNTR to configure gamma for pipe bottom color */
1993         intel_disable_primary_plane(new_crtc_state);
1994
1995         intel_initial_watermarks(state, crtc);
1996         intel_enable_transcoder(new_crtc_state);
1997
1998         intel_crtc_vblank_on(new_crtc_state);
1999
2000         intel_encoders_enable(state, crtc);
2001 }
2002
2003 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2004                              struct intel_crtc *crtc)
2005 {
2006         const struct intel_crtc_state *new_crtc_state =
2007                 intel_atomic_get_new_crtc_state(state, crtc);
2008         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2009         enum pipe pipe = crtc->pipe;
2010
2011         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2012                 return;
2013
2014         i9xx_configure_cpu_transcoder(new_crtc_state);
2015
2016         intel_set_pipe_src_size(new_crtc_state);
2017
2018         crtc->active = true;
2019
2020         if (DISPLAY_VER(dev_priv) != 2)
2021                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2022
2023         intel_encoders_pre_enable(state, crtc);
2024
2025         i9xx_enable_pll(new_crtc_state);
2026
2027         i9xx_pfit_enable(new_crtc_state);
2028
2029         intel_color_load_luts(new_crtc_state);
2030         intel_color_commit_noarm(new_crtc_state);
2031         intel_color_commit_arm(new_crtc_state);
2032         /* update DSPCNTR to configure gamma for pipe bottom color */
2033         intel_disable_primary_plane(new_crtc_state);
2034
2035         if (!intel_initial_watermarks(state, crtc))
2036                 intel_update_watermarks(dev_priv);
2037         intel_enable_transcoder(new_crtc_state);
2038
2039         intel_crtc_vblank_on(new_crtc_state);
2040
2041         intel_encoders_enable(state, crtc);
2042
2043         /* prevents spurious underruns */
2044         if (DISPLAY_VER(dev_priv) == 2)
2045                 intel_crtc_wait_for_next_vblank(crtc);
2046 }
2047
2048 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2049 {
2050         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2051         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2052
2053         if (!old_crtc_state->gmch_pfit.control)
2054                 return;
2055
2056         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2057
2058         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2059                     intel_de_read(dev_priv, PFIT_CONTROL));
2060         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2061 }
2062
2063 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2064                               struct intel_crtc *crtc)
2065 {
2066         struct intel_crtc_state *old_crtc_state =
2067                 intel_atomic_get_old_crtc_state(state, crtc);
2068         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2069         enum pipe pipe = crtc->pipe;
2070
2071         /*
2072          * On gen2 planes are double buffered but the pipe isn't, so we must
2073          * wait for planes to fully turn off before disabling the pipe.
2074          */
2075         if (DISPLAY_VER(dev_priv) == 2)
2076                 intel_crtc_wait_for_next_vblank(crtc);
2077
2078         intel_encoders_disable(state, crtc);
2079
2080         intel_crtc_vblank_off(old_crtc_state);
2081
2082         intel_disable_transcoder(old_crtc_state);
2083
2084         i9xx_pfit_disable(old_crtc_state);
2085
2086         intel_encoders_post_disable(state, crtc);
2087
2088         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2089                 if (IS_CHERRYVIEW(dev_priv))
2090                         chv_disable_pll(dev_priv, pipe);
2091                 else if (IS_VALLEYVIEW(dev_priv))
2092                         vlv_disable_pll(dev_priv, pipe);
2093                 else
2094                         i9xx_disable_pll(old_crtc_state);
2095         }
2096
2097         intel_encoders_post_pll_disable(state, crtc);
2098
2099         if (DISPLAY_VER(dev_priv) != 2)
2100                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2101
2102         if (!dev_priv->display.funcs.wm->initial_watermarks)
2103                 intel_update_watermarks(dev_priv);
2104
2105         /* clock the pipe down to 640x480@60 to potentially save power */
2106         if (IS_I830(dev_priv))
2107                 i830_enable_pipe(dev_priv, pipe);
2108 }
2109
2110 void intel_encoder_destroy(struct drm_encoder *encoder)
2111 {
2112         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2113
2114         drm_encoder_cleanup(encoder);
2115         kfree(intel_encoder);
2116 }
2117
2118 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2119 {
2120         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2121
2122         /* GDG double wide on either pipe, otherwise pipe A only */
2123         return DISPLAY_VER(dev_priv) < 4 &&
2124                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2125 }
2126
2127 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2128 {
2129         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2130         struct drm_rect src;
2131
2132         /*
2133          * We only use IF-ID interlacing. If we ever use
2134          * PF-ID we'll need to adjust the pixel_rate here.
2135          */
2136
2137         if (!crtc_state->pch_pfit.enabled)
2138                 return pixel_rate;
2139
2140         drm_rect_init(&src, 0, 0,
2141                       drm_rect_width(&crtc_state->pipe_src) << 16,
2142                       drm_rect_height(&crtc_state->pipe_src) << 16);
2143
2144         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2145                                    pixel_rate);
2146 }
2147
2148 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2149                                          const struct drm_display_mode *timings)
2150 {
2151         mode->hdisplay = timings->crtc_hdisplay;
2152         mode->htotal = timings->crtc_htotal;
2153         mode->hsync_start = timings->crtc_hsync_start;
2154         mode->hsync_end = timings->crtc_hsync_end;
2155
2156         mode->vdisplay = timings->crtc_vdisplay;
2157         mode->vtotal = timings->crtc_vtotal;
2158         mode->vsync_start = timings->crtc_vsync_start;
2159         mode->vsync_end = timings->crtc_vsync_end;
2160
2161         mode->flags = timings->flags;
2162         mode->type = DRM_MODE_TYPE_DRIVER;
2163
2164         mode->clock = timings->crtc_clock;
2165
2166         drm_mode_set_name(mode);
2167 }
2168
2169 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2170 {
2171         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2172
2173         if (HAS_GMCH(dev_priv))
2174                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2175                 crtc_state->pixel_rate =
2176                         crtc_state->hw.pipe_mode.crtc_clock;
2177         else
2178                 crtc_state->pixel_rate =
2179                         ilk_pipe_pixel_rate(crtc_state);
2180 }
2181
2182 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2183                                            struct drm_display_mode *mode)
2184 {
2185         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2186
2187         if (num_pipes < 2)
2188                 return;
2189
2190         mode->crtc_clock /= num_pipes;
2191         mode->crtc_hdisplay /= num_pipes;
2192         mode->crtc_hblank_start /= num_pipes;
2193         mode->crtc_hblank_end /= num_pipes;
2194         mode->crtc_hsync_start /= num_pipes;
2195         mode->crtc_hsync_end /= num_pipes;
2196         mode->crtc_htotal /= num_pipes;
2197 }
2198
2199 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2200                                           struct drm_display_mode *mode)
2201 {
2202         int overlap = crtc_state->splitter.pixel_overlap;
2203         int n = crtc_state->splitter.link_count;
2204
2205         if (!crtc_state->splitter.enable)
2206                 return;
2207
2208         /*
2209          * eDP MSO uses segment timings from EDID for transcoder
2210          * timings, but full mode for everything else.
2211          *
2212          * h_full = (h_segment - pixel_overlap) * link_count
2213          */
2214         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2215         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2216         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2217         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2218         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2219         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2220         mode->crtc_clock *= n;
2221 }
2222
2223 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2224 {
2225         struct drm_display_mode *mode = &crtc_state->hw.mode;
2226         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2227         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2228
2229         /*
2230          * Start with the adjusted_mode crtc timings, which
2231          * have been filled with the transcoder timings.
2232          */
2233         drm_mode_copy(pipe_mode, adjusted_mode);
2234
2235         /* Expand MSO per-segment transcoder timings to full */
2236         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2237
2238         /*
2239          * We want the full numbers in adjusted_mode normal timings,
2240          * adjusted_mode crtc timings are left with the raw transcoder
2241          * timings.
2242          */
2243         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2244
2245         /* Populate the "user" mode with full numbers */
2246         drm_mode_copy(mode, pipe_mode);
2247         intel_mode_from_crtc_timings(mode, mode);
2248         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2249                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2250         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2251
2252         /* Derive per-pipe timings in case bigjoiner is used */
2253         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2254         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2255
2256         intel_crtc_compute_pixel_rate(crtc_state);
2257 }
2258
2259 void intel_encoder_get_config(struct intel_encoder *encoder,
2260                               struct intel_crtc_state *crtc_state)
2261 {
2262         encoder->get_config(encoder, crtc_state);
2263
2264         intel_crtc_readout_derived_state(crtc_state);
2265 }
2266
2267 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2268 {
2269         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2270         int width, height;
2271
2272         if (num_pipes < 2)
2273                 return;
2274
2275         width = drm_rect_width(&crtc_state->pipe_src);
2276         height = drm_rect_height(&crtc_state->pipe_src);
2277
2278         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2279                       width / num_pipes, height);
2280 }
2281
2282 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2283 {
2284         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2285         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2286
2287         intel_bigjoiner_compute_pipe_src(crtc_state);
2288
2289         /*
2290          * Pipe horizontal size must be even in:
2291          * - DVO ganged mode
2292          * - LVDS dual channel mode
2293          * - Double wide pipe
2294          */
2295         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2296                 if (crtc_state->double_wide) {
2297                         drm_dbg_kms(&i915->drm,
2298                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2299                                     crtc->base.base.id, crtc->base.name);
2300                         return -EINVAL;
2301                 }
2302
2303                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2304                     intel_is_dual_link_lvds(i915)) {
2305                         drm_dbg_kms(&i915->drm,
2306                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2307                                     crtc->base.base.id, crtc->base.name);
2308                         return -EINVAL;
2309                 }
2310         }
2311
2312         return 0;
2313 }
2314
2315 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2316 {
2317         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2318         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2319         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2320         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2321         int clock_limit = i915->max_dotclk_freq;
2322
2323         /*
2324          * Start with the adjusted_mode crtc timings, which
2325          * have been filled with the transcoder timings.
2326          */
2327         drm_mode_copy(pipe_mode, adjusted_mode);
2328
2329         /* Expand MSO per-segment transcoder timings to full */
2330         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2331
2332         /* Derive per-pipe timings in case bigjoiner is used */
2333         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2334         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2335
2336         if (DISPLAY_VER(i915) < 4) {
2337                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2338
2339                 /*
2340                  * Enable double wide mode when the dot clock
2341                  * is > 90% of the (display) core speed.
2342                  */
2343                 if (intel_crtc_supports_double_wide(crtc) &&
2344                     pipe_mode->crtc_clock > clock_limit) {
2345                         clock_limit = i915->max_dotclk_freq;
2346                         crtc_state->double_wide = true;
2347                 }
2348         }
2349
2350         if (pipe_mode->crtc_clock > clock_limit) {
2351                 drm_dbg_kms(&i915->drm,
2352                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2353                             crtc->base.base.id, crtc->base.name,
2354                             pipe_mode->crtc_clock, clock_limit,
2355                             str_yes_no(crtc_state->double_wide));
2356                 return -EINVAL;
2357         }
2358
2359         return 0;
2360 }
2361
2362 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2363                                      struct intel_crtc *crtc)
2364 {
2365         struct intel_crtc_state *crtc_state =
2366                 intel_atomic_get_new_crtc_state(state, crtc);
2367         int ret;
2368
2369         ret = intel_dpll_crtc_compute_clock(state, crtc);
2370         if (ret)
2371                 return ret;
2372
2373         ret = intel_crtc_compute_pipe_src(crtc_state);
2374         if (ret)
2375                 return ret;
2376
2377         ret = intel_crtc_compute_pipe_mode(crtc_state);
2378         if (ret)
2379                 return ret;
2380
2381         intel_crtc_compute_pixel_rate(crtc_state);
2382
2383         if (crtc_state->has_pch_encoder)
2384                 return ilk_fdi_compute_config(crtc, crtc_state);
2385
2386         return 0;
2387 }
2388
2389 static void
2390 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2391 {
2392         while (*num > DATA_LINK_M_N_MASK ||
2393                *den > DATA_LINK_M_N_MASK) {
2394                 *num >>= 1;
2395                 *den >>= 1;
2396         }
2397 }
2398
2399 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2400                         u32 m, u32 n, u32 constant_n)
2401 {
2402         if (constant_n)
2403                 *ret_n = constant_n;
2404         else
2405                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2406
2407         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2408         intel_reduce_m_n_ratio(ret_m, ret_n);
2409 }
2410
2411 void
2412 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2413                        int pixel_clock, int link_clock,
2414                        struct intel_link_m_n *m_n,
2415                        bool fec_enable)
2416 {
2417         u32 data_clock = bits_per_pixel * pixel_clock;
2418
2419         if (fec_enable)
2420                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2421
2422         /*
2423          * Windows/BIOS uses fixed M/N values always. Follow suit.
2424          *
2425          * Also several DP dongles in particular seem to be fussy
2426          * about too large link M/N values. Presumably the 20bit
2427          * value used by Windows/BIOS is acceptable to everyone.
2428          */
2429         m_n->tu = 64;
2430         compute_m_n(&m_n->data_m, &m_n->data_n,
2431                     data_clock, link_clock * nlanes * 8,
2432                     0x8000000);
2433
2434         compute_m_n(&m_n->link_m, &m_n->link_n,
2435                     pixel_clock, link_clock,
2436                     0x80000);
2437 }
2438
2439 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2440 {
2441         /*
2442          * There may be no VBT; and if the BIOS enabled SSC we can
2443          * just keep using it to avoid unnecessary flicker.  Whereas if the
2444          * BIOS isn't using it, don't assume it will work even if the VBT
2445          * indicates as much.
2446          */
2447         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2448                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2449                                                        PCH_DREF_CONTROL) &
2450                         DREF_SSC1_ENABLE;
2451
2452                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2453                         drm_dbg_kms(&dev_priv->drm,
2454                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2455                                     str_enabled_disabled(bios_lvds_use_ssc),
2456                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2457                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2458                 }
2459         }
2460 }
2461
2462 void intel_zero_m_n(struct intel_link_m_n *m_n)
2463 {
2464         /* corresponds to 0 register value */
2465         memset(m_n, 0, sizeof(*m_n));
2466         m_n->tu = 1;
2467 }
2468
2469 void intel_set_m_n(struct drm_i915_private *i915,
2470                    const struct intel_link_m_n *m_n,
2471                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2472                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2473 {
2474         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2475         intel_de_write(i915, data_n_reg, m_n->data_n);
2476         intel_de_write(i915, link_m_reg, m_n->link_m);
2477         /*
2478          * On BDW+ writing LINK_N arms the double buffered update
2479          * of all the M/N registers, so it must be written last.
2480          */
2481         intel_de_write(i915, link_n_reg, m_n->link_n);
2482 }
2483
2484 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2485                                     enum transcoder transcoder)
2486 {
2487         if (IS_HASWELL(dev_priv))
2488                 return transcoder == TRANSCODER_EDP;
2489
2490         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2491 }
2492
2493 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2494                                     enum transcoder transcoder,
2495                                     const struct intel_link_m_n *m_n)
2496 {
2497         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2498         enum pipe pipe = crtc->pipe;
2499
2500         if (DISPLAY_VER(dev_priv) >= 5)
2501                 intel_set_m_n(dev_priv, m_n,
2502                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2503                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2504         else
2505                 intel_set_m_n(dev_priv, m_n,
2506                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2507                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2508 }
2509
2510 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2511                                     enum transcoder transcoder,
2512                                     const struct intel_link_m_n *m_n)
2513 {
2514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2515
2516         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2517                 return;
2518
2519         intel_set_m_n(dev_priv, m_n,
2520                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2521                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2522 }
2523
2524 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2525 {
2526         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2527         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2528         enum pipe pipe = crtc->pipe;
2529         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2530         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2531         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2532         int vsyncshift = 0;
2533
2534         /* We need to be careful not to changed the adjusted mode, for otherwise
2535          * the hw state checker will get angry at the mismatch. */
2536         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2537         crtc_vtotal = adjusted_mode->crtc_vtotal;
2538         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2539         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2540
2541         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2542                 /* the chip adds 2 halflines automatically */
2543                 crtc_vtotal -= 1;
2544                 crtc_vblank_end -= 1;
2545
2546                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2547                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2548                 else
2549                         vsyncshift = adjusted_mode->crtc_hsync_start -
2550                                 adjusted_mode->crtc_htotal / 2;
2551                 if (vsyncshift < 0)
2552                         vsyncshift += adjusted_mode->crtc_htotal;
2553         }
2554
2555         /*
2556          * VBLANK_START no longer works on ADL+, instead we must use
2557          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2558          */
2559         if (DISPLAY_VER(dev_priv) >= 13) {
2560                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2561                                crtc_vblank_start - crtc_vdisplay);
2562
2563                 /*
2564                  * VBLANK_START not used by hw, just clear it
2565                  * to make it stand out in register dumps.
2566                  */
2567                 crtc_vblank_start = 1;
2568         }
2569
2570         if (DISPLAY_VER(dev_priv) > 3)
2571                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2572                                vsyncshift);
2573
2574         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2575                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2576                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2577         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2578                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2579                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2580         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2581                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2582                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2583
2584         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2585                        VACTIVE(crtc_vdisplay - 1) |
2586                        VTOTAL(crtc_vtotal - 1));
2587         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2588                        VBLANK_START(crtc_vblank_start - 1) |
2589                        VBLANK_END(crtc_vblank_end - 1));
2590         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2591                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2592                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2593
2594         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2595          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2596          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2597          * bits. */
2598         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2599             (pipe == PIPE_B || pipe == PIPE_C))
2600                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2601                                VACTIVE(crtc_vdisplay - 1) |
2602                                VTOTAL(crtc_vtotal - 1));
2603 }
2604
2605 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2606 {
2607         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2608         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2609         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2610         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2611         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2612
2613         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2614         crtc_vtotal = adjusted_mode->crtc_vtotal;
2615         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2616         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2617
2618         drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2619
2620         /*
2621          * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2622          * But let's write it anyway to keep the state checker happy.
2623          */
2624         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2625                        VBLANK_START(crtc_vblank_start - 1) |
2626                        VBLANK_END(crtc_vblank_end - 1));
2627         /*
2628          * The double buffer latch point for TRANS_VTOTAL
2629          * is the transcoder's undelayed vblank.
2630          */
2631         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2632                        VACTIVE(crtc_vdisplay - 1) |
2633                        VTOTAL(crtc_vtotal - 1));
2634 }
2635
2636 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2637 {
2638         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2639         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2640         int width = drm_rect_width(&crtc_state->pipe_src);
2641         int height = drm_rect_height(&crtc_state->pipe_src);
2642         enum pipe pipe = crtc->pipe;
2643
2644         /* pipesrc controls the size that is scaled from, which should
2645          * always be the user's requested size.
2646          */
2647         intel_de_write(dev_priv, PIPESRC(pipe),
2648                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2649 }
2650
2651 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2652 {
2653         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2654         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2655
2656         if (DISPLAY_VER(dev_priv) == 2)
2657                 return false;
2658
2659         if (DISPLAY_VER(dev_priv) >= 9 ||
2660             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2661                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2662         else
2663                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2664 }
2665
2666 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2667                                          struct intel_crtc_state *pipe_config)
2668 {
2669         struct drm_device *dev = crtc->base.dev;
2670         struct drm_i915_private *dev_priv = to_i915(dev);
2671         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2672         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2673         u32 tmp;
2674
2675         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2676         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2677         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2678
2679         if (!transcoder_is_dsi(cpu_transcoder)) {
2680                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2681                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2682                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2683         }
2684
2685         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2686         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2687         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2688
2689         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2690         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2691         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2692
2693         /* FIXME TGL+ DSI transcoders have this! */
2694         if (!transcoder_is_dsi(cpu_transcoder)) {
2695                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2696                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2697                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2698         }
2699         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2700         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2701         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2702
2703         if (intel_pipe_is_interlaced(pipe_config)) {
2704                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2705                 adjusted_mode->crtc_vtotal += 1;
2706                 adjusted_mode->crtc_vblank_end += 1;
2707         }
2708
2709         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2710                 adjusted_mode->crtc_vblank_start =
2711                         adjusted_mode->crtc_vdisplay +
2712                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2713 }
2714
2715 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2716 {
2717         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2718         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2719         enum pipe master_pipe, pipe = crtc->pipe;
2720         int width;
2721
2722         if (num_pipes < 2)
2723                 return;
2724
2725         master_pipe = bigjoiner_master_pipe(crtc_state);
2726         width = drm_rect_width(&crtc_state->pipe_src);
2727
2728         drm_rect_translate_to(&crtc_state->pipe_src,
2729                               (pipe - master_pipe) * width, 0);
2730 }
2731
2732 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2733                                     struct intel_crtc_state *pipe_config)
2734 {
2735         struct drm_device *dev = crtc->base.dev;
2736         struct drm_i915_private *dev_priv = to_i915(dev);
2737         u32 tmp;
2738
2739         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2740
2741         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2742                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2743                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2744
2745         intel_bigjoiner_adjust_pipe_src(pipe_config);
2746 }
2747
2748 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2749 {
2750         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2751         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2752         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2753         u32 val = 0;
2754
2755         /*
2756          * - We keep both pipes enabled on 830
2757          * - During modeset the pipe is still disabled and must remain so
2758          * - During fastset the pipe is already enabled and must remain so
2759          */
2760         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2761                 val |= TRANSCONF_ENABLE;
2762
2763         if (crtc_state->double_wide)
2764                 val |= TRANSCONF_DOUBLE_WIDE;
2765
2766         /* only g4x and later have fancy bpc/dither controls */
2767         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2768             IS_CHERRYVIEW(dev_priv)) {
2769                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2770                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2771                         val |= TRANSCONF_DITHER_EN |
2772                                 TRANSCONF_DITHER_TYPE_SP;
2773
2774                 switch (crtc_state->pipe_bpp) {
2775                 default:
2776                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2777                         MISSING_CASE(crtc_state->pipe_bpp);
2778                         fallthrough;
2779                 case 18:
2780                         val |= TRANSCONF_BPC_6;
2781                         break;
2782                 case 24:
2783                         val |= TRANSCONF_BPC_8;
2784                         break;
2785                 case 30:
2786                         val |= TRANSCONF_BPC_10;
2787                         break;
2788                 }
2789         }
2790
2791         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2792                 if (DISPLAY_VER(dev_priv) < 4 ||
2793                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2794                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2795                 else
2796                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2797         } else {
2798                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2799         }
2800
2801         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2802              crtc_state->limited_color_range)
2803                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2804
2805         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2806
2807         if (crtc_state->wgc_enable)
2808                 val |= TRANSCONF_WGC_ENABLE;
2809
2810         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2811
2812         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2813         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2814 }
2815
2816 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2817 {
2818         if (IS_I830(dev_priv))
2819                 return false;
2820
2821         return DISPLAY_VER(dev_priv) >= 4 ||
2822                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2823 }
2824
2825 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2826 {
2827         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2829         enum pipe pipe;
2830         u32 tmp;
2831
2832         if (!i9xx_has_pfit(dev_priv))
2833                 return;
2834
2835         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2836         if (!(tmp & PFIT_ENABLE))
2837                 return;
2838
2839         /* Check whether the pfit is attached to our pipe. */
2840         if (DISPLAY_VER(dev_priv) >= 4)
2841                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2842         else
2843                 pipe = PIPE_B;
2844
2845         if (pipe != crtc->pipe)
2846                 return;
2847
2848         crtc_state->gmch_pfit.control = tmp;
2849         crtc_state->gmch_pfit.pgm_ratios =
2850                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2851 }
2852
2853 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2854                                struct intel_crtc_state *pipe_config)
2855 {
2856         struct drm_device *dev = crtc->base.dev;
2857         struct drm_i915_private *dev_priv = to_i915(dev);
2858         enum pipe pipe = crtc->pipe;
2859         struct dpll clock;
2860         u32 mdiv;
2861         int refclk = 100000;
2862
2863         /* In case of DSI, DPLL will not be used */
2864         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2865                 return;
2866
2867         vlv_dpio_get(dev_priv);
2868         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2869         vlv_dpio_put(dev_priv);
2870
2871         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2872         clock.m2 = mdiv & DPIO_M2DIV_MASK;
2873         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2874         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2875         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2876
2877         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2878 }
2879
2880 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2881                                struct intel_crtc_state *pipe_config)
2882 {
2883         struct drm_device *dev = crtc->base.dev;
2884         struct drm_i915_private *dev_priv = to_i915(dev);
2885         enum pipe pipe = crtc->pipe;
2886         enum dpio_channel port = vlv_pipe_to_channel(pipe);
2887         struct dpll clock;
2888         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2889         int refclk = 100000;
2890
2891         /* In case of DSI, DPLL will not be used */
2892         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2893                 return;
2894
2895         vlv_dpio_get(dev_priv);
2896         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
2897         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
2898         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
2899         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
2900         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
2901         vlv_dpio_put(dev_priv);
2902
2903         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
2904         clock.m2 = (pll_dw0 & 0xff) << 22;
2905         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
2906                 clock.m2 |= pll_dw2 & 0x3fffff;
2907         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
2908         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
2909         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
2910
2911         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
2912 }
2913
2914 static enum intel_output_format
2915 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2916 {
2917         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2918         u32 tmp;
2919
2920         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2921
2922         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2923                 /* We support 4:2:0 in full blend mode only */
2924                 drm_WARN_ON(&dev_priv->drm,
2925                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2926
2927                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2928         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2929                 return INTEL_OUTPUT_FORMAT_YCBCR444;
2930         } else {
2931                 return INTEL_OUTPUT_FORMAT_RGB;
2932         }
2933 }
2934
2935 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2936                                  struct intel_crtc_state *pipe_config)
2937 {
2938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2939         enum intel_display_power_domain power_domain;
2940         intel_wakeref_t wakeref;
2941         u32 tmp;
2942         bool ret;
2943
2944         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2945         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
2946         if (!wakeref)
2947                 return false;
2948
2949         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2950         pipe_config->sink_format = pipe_config->output_format;
2951         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
2952         pipe_config->shared_dpll = NULL;
2953
2954         ret = false;
2955
2956         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
2957         if (!(tmp & TRANSCONF_ENABLE))
2958                 goto out;
2959
2960         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2961             IS_CHERRYVIEW(dev_priv)) {
2962                 switch (tmp & TRANSCONF_BPC_MASK) {
2963                 case TRANSCONF_BPC_6:
2964                         pipe_config->pipe_bpp = 18;
2965                         break;
2966                 case TRANSCONF_BPC_8:
2967                         pipe_config->pipe_bpp = 24;
2968                         break;
2969                 case TRANSCONF_BPC_10:
2970                         pipe_config->pipe_bpp = 30;
2971                         break;
2972                 default:
2973                         MISSING_CASE(tmp);
2974                         break;
2975                 }
2976         }
2977
2978         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2979             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
2980                 pipe_config->limited_color_range = true;
2981
2982         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
2983
2984         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
2985
2986         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2987             (tmp & TRANSCONF_WGC_ENABLE))
2988                 pipe_config->wgc_enable = true;
2989
2990         intel_color_get_config(pipe_config);
2991
2992         if (DISPLAY_VER(dev_priv) < 4)
2993                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
2994
2995         intel_get_transcoder_timings(crtc, pipe_config);
2996         intel_get_pipe_src_size(crtc, pipe_config);
2997
2998         i9xx_get_pfit_config(pipe_config);
2999
3000         if (DISPLAY_VER(dev_priv) >= 4) {
3001                 /* No way to read it out on pipes B and C */
3002                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3003                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
3004                 else
3005                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3006                 pipe_config->pixel_multiplier =
3007                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3008                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3009                 pipe_config->dpll_hw_state.dpll_md = tmp;
3010         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3011                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3012                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3013                 pipe_config->pixel_multiplier =
3014                         ((tmp & SDVO_MULTIPLIER_MASK)
3015                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3016         } else {
3017                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3018                  * port and will be fixed up in the encoder->get_config
3019                  * function. */
3020                 pipe_config->pixel_multiplier = 1;
3021         }
3022         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3023                                                         DPLL(crtc->pipe));
3024         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3025                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3026                                                                FP0(crtc->pipe));
3027                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3028                                                                FP1(crtc->pipe));
3029         } else {
3030                 /* Mask out read-only status bits. */
3031                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3032                                                      DPLL_PORTC_READY_MASK |
3033                                                      DPLL_PORTB_READY_MASK);
3034         }
3035
3036         if (IS_CHERRYVIEW(dev_priv))
3037                 chv_crtc_clock_get(crtc, pipe_config);
3038         else if (IS_VALLEYVIEW(dev_priv))
3039                 vlv_crtc_clock_get(crtc, pipe_config);
3040         else
3041                 i9xx_crtc_clock_get(crtc, pipe_config);
3042
3043         /*
3044          * Normally the dotclock is filled in by the encoder .get_config()
3045          * but in case the pipe is enabled w/o any ports we need a sane
3046          * default.
3047          */
3048         pipe_config->hw.adjusted_mode.crtc_clock =
3049                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3050
3051         ret = true;
3052
3053 out:
3054         intel_display_power_put(dev_priv, power_domain, wakeref);
3055
3056         return ret;
3057 }
3058
3059 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3060 {
3061         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3062         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3063         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3064         u32 val = 0;
3065
3066         /*
3067          * - During modeset the pipe is still disabled and must remain so
3068          * - During fastset the pipe is already enabled and must remain so
3069          */
3070         if (!intel_crtc_needs_modeset(crtc_state))
3071                 val |= TRANSCONF_ENABLE;
3072
3073         switch (crtc_state->pipe_bpp) {
3074         default:
3075                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3076                 MISSING_CASE(crtc_state->pipe_bpp);
3077                 fallthrough;
3078         case 18:
3079                 val |= TRANSCONF_BPC_6;
3080                 break;
3081         case 24:
3082                 val |= TRANSCONF_BPC_8;
3083                 break;
3084         case 30:
3085                 val |= TRANSCONF_BPC_10;
3086                 break;
3087         case 36:
3088                 val |= TRANSCONF_BPC_12;
3089                 break;
3090         }
3091
3092         if (crtc_state->dither)
3093                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3094
3095         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3096                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3097         else
3098                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3099
3100         /*
3101          * This would end up with an odd purple hue over
3102          * the entire display. Make sure we don't do it.
3103          */
3104         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3105                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3106
3107         if (crtc_state->limited_color_range &&
3108             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3109                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3110
3111         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3112                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3113
3114         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3115
3116         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3117         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3118
3119         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3120         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3121 }
3122
3123 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3124 {
3125         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3127         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3128         u32 val = 0;
3129
3130         /*
3131          * - During modeset the pipe is still disabled and must remain so
3132          * - During fastset the pipe is already enabled and must remain so
3133          */
3134         if (!intel_crtc_needs_modeset(crtc_state))
3135                 val |= TRANSCONF_ENABLE;
3136
3137         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3138                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3139
3140         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3141                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3142         else
3143                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3144
3145         if (IS_HASWELL(dev_priv) &&
3146             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3147                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3148
3149         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3150         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3151 }
3152
3153 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3154 {
3155         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3156         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3157         u32 val = 0;
3158
3159         switch (crtc_state->pipe_bpp) {
3160         case 18:
3161                 val |= PIPE_MISC_BPC_6;
3162                 break;
3163         case 24:
3164                 val |= PIPE_MISC_BPC_8;
3165                 break;
3166         case 30:
3167                 val |= PIPE_MISC_BPC_10;
3168                 break;
3169         case 36:
3170                 /* Port output 12BPC defined for ADLP+ */
3171                 if (DISPLAY_VER(dev_priv) > 12)
3172                         val |= PIPE_MISC_BPC_12_ADLP;
3173                 break;
3174         default:
3175                 MISSING_CASE(crtc_state->pipe_bpp);
3176                 break;
3177         }
3178
3179         if (crtc_state->dither)
3180                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3181
3182         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3183             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3184                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3185
3186         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3187                 val |= PIPE_MISC_YUV420_ENABLE |
3188                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3189
3190         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3191                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3192
3193         if (DISPLAY_VER(dev_priv) >= 12)
3194                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3195
3196         /* allow PSR with sprite enabled */
3197         if (IS_BROADWELL(dev_priv))
3198                 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3199
3200         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3201 }
3202
3203 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3204 {
3205         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3206         u32 tmp;
3207
3208         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3209
3210         switch (tmp & PIPE_MISC_BPC_MASK) {
3211         case PIPE_MISC_BPC_6:
3212                 return 18;
3213         case PIPE_MISC_BPC_8:
3214                 return 24;
3215         case PIPE_MISC_BPC_10:
3216                 return 30;
3217         /*
3218          * PORT OUTPUT 12 BPC defined for ADLP+.
3219          *
3220          * TODO:
3221          * For previous platforms with DSI interface, bits 5:7
3222          * are used for storing pipe_bpp irrespective of dithering.
3223          * Since the value of 12 BPC is not defined for these bits
3224          * on older platforms, need to find a workaround for 12 BPC
3225          * MIPI DSI HW readout.
3226          */
3227         case PIPE_MISC_BPC_12_ADLP:
3228                 if (DISPLAY_VER(dev_priv) > 12)
3229                         return 36;
3230                 fallthrough;
3231         default:
3232                 MISSING_CASE(tmp);
3233                 return 0;
3234         }
3235 }
3236
3237 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3238 {
3239         /*
3240          * Account for spread spectrum to avoid
3241          * oversubscribing the link. Max center spread
3242          * is 2.5%; use 5% for safety's sake.
3243          */
3244         u32 bps = target_clock * bpp * 21 / 20;
3245         return DIV_ROUND_UP(bps, link_bw * 8);
3246 }
3247
3248 void intel_get_m_n(struct drm_i915_private *i915,
3249                    struct intel_link_m_n *m_n,
3250                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3251                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3252 {
3253         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3254         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3255         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3256         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3257         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3258 }
3259
3260 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3261                                     enum transcoder transcoder,
3262                                     struct intel_link_m_n *m_n)
3263 {
3264         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3265         enum pipe pipe = crtc->pipe;
3266
3267         if (DISPLAY_VER(dev_priv) >= 5)
3268                 intel_get_m_n(dev_priv, m_n,
3269                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3270                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3271         else
3272                 intel_get_m_n(dev_priv, m_n,
3273                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3274                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3275 }
3276
3277 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3278                                     enum transcoder transcoder,
3279                                     struct intel_link_m_n *m_n)
3280 {
3281         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3282
3283         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3284                 return;
3285
3286         intel_get_m_n(dev_priv, m_n,
3287                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3288                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3289 }
3290
3291 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3292 {
3293         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3294         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3295         u32 ctl, pos, size;
3296         enum pipe pipe;
3297
3298         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3299         if ((ctl & PF_ENABLE) == 0)
3300                 return;
3301
3302         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3303                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3304         else
3305                 pipe = crtc->pipe;
3306
3307         crtc_state->pch_pfit.enabled = true;
3308
3309         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3310         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3311
3312         drm_rect_init(&crtc_state->pch_pfit.dst,
3313                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3314                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3315                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3316                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3317
3318         /*
3319          * We currently do not free assignements of panel fitters on
3320          * ivb/hsw (since we don't use the higher upscaling modes which
3321          * differentiates them) so just WARN about this case for now.
3322          */
3323         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3324 }
3325
3326 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3327                                 struct intel_crtc_state *pipe_config)
3328 {
3329         struct drm_device *dev = crtc->base.dev;
3330         struct drm_i915_private *dev_priv = to_i915(dev);
3331         enum intel_display_power_domain power_domain;
3332         intel_wakeref_t wakeref;
3333         u32 tmp;
3334         bool ret;
3335
3336         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3337         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3338         if (!wakeref)
3339                 return false;
3340
3341         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3342         pipe_config->shared_dpll = NULL;
3343
3344         ret = false;
3345         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3346         if (!(tmp & TRANSCONF_ENABLE))
3347                 goto out;
3348
3349         switch (tmp & TRANSCONF_BPC_MASK) {
3350         case TRANSCONF_BPC_6:
3351                 pipe_config->pipe_bpp = 18;
3352                 break;
3353         case TRANSCONF_BPC_8:
3354                 pipe_config->pipe_bpp = 24;
3355                 break;
3356         case TRANSCONF_BPC_10:
3357                 pipe_config->pipe_bpp = 30;
3358                 break;
3359         case TRANSCONF_BPC_12:
3360                 pipe_config->pipe_bpp = 36;
3361                 break;
3362         default:
3363                 break;
3364         }
3365
3366         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3367                 pipe_config->limited_color_range = true;
3368
3369         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3370         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3371         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3372                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3373                 break;
3374         default:
3375                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3376                 break;
3377         }
3378
3379         pipe_config->sink_format = pipe_config->output_format;
3380
3381         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3382
3383         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3384
3385         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3386
3387         intel_color_get_config(pipe_config);
3388
3389         pipe_config->pixel_multiplier = 1;
3390
3391         ilk_pch_get_config(pipe_config);
3392
3393         intel_get_transcoder_timings(crtc, pipe_config);
3394         intel_get_pipe_src_size(crtc, pipe_config);
3395
3396         ilk_get_pfit_config(pipe_config);
3397
3398         ret = true;
3399
3400 out:
3401         intel_display_power_put(dev_priv, power_domain, wakeref);
3402
3403         return ret;
3404 }
3405
3406 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3407 {
3408         u8 pipes;
3409
3410         if (DISPLAY_VER(i915) >= 12)
3411                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3412         else if (DISPLAY_VER(i915) >= 11)
3413                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3414         else
3415                 pipes = 0;
3416
3417         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3418 }
3419
3420 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3421                                            enum transcoder cpu_transcoder)
3422 {
3423         enum intel_display_power_domain power_domain;
3424         intel_wakeref_t wakeref;
3425         u32 tmp = 0;
3426
3427         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3428
3429         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3430                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3431
3432         return tmp & TRANS_DDI_FUNC_ENABLE;
3433 }
3434
3435 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3436                                     u8 *master_pipes, u8 *slave_pipes)
3437 {
3438         struct intel_crtc *crtc;
3439
3440         *master_pipes = 0;
3441         *slave_pipes = 0;
3442
3443         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3444                                          bigjoiner_pipes(dev_priv)) {
3445                 enum intel_display_power_domain power_domain;
3446                 enum pipe pipe = crtc->pipe;
3447                 intel_wakeref_t wakeref;
3448
3449                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3450                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3451                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3452
3453                         if (!(tmp & BIG_JOINER_ENABLE))
3454                                 continue;
3455
3456                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3457                                 *master_pipes |= BIT(pipe);
3458                         else
3459                                 *slave_pipes |= BIT(pipe);
3460                 }
3461
3462                 if (DISPLAY_VER(dev_priv) < 13)
3463                         continue;
3464
3465                 power_domain = POWER_DOMAIN_PIPE(pipe);
3466                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3467                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3468
3469                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3470                                 *master_pipes |= BIT(pipe);
3471                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3472                                 *slave_pipes |= BIT(pipe);
3473                 }
3474         }
3475
3476         /* Bigjoiner pipes should always be consecutive master and slave */
3477         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3478                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3479                  *master_pipes, *slave_pipes);
3480 }
3481
3482 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3483 {
3484         if ((slave_pipes & BIT(pipe)) == 0)
3485                 return pipe;
3486
3487         /* ignore everything above our pipe */
3488         master_pipes &= ~GENMASK(7, pipe);
3489
3490         /* highest remaining bit should be our master pipe */
3491         return fls(master_pipes) - 1;
3492 }
3493
3494 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3495 {
3496         enum pipe master_pipe, next_master_pipe;
3497
3498         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3499
3500         if ((master_pipes & BIT(master_pipe)) == 0)
3501                 return 0;
3502
3503         /* ignore our master pipe and everything below it */
3504         master_pipes &= ~GENMASK(master_pipe, 0);
3505         /* make sure a high bit is set for the ffs() */
3506         master_pipes |= BIT(7);
3507         /* lowest remaining bit should be the next master pipe */
3508         next_master_pipe = ffs(master_pipes) - 1;
3509
3510         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3511 }
3512
3513 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3514 {
3515         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3516
3517         if (DISPLAY_VER(i915) >= 11)
3518                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3519
3520         return panel_transcoder_mask;
3521 }
3522
3523 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3524 {
3525         struct drm_device *dev = crtc->base.dev;
3526         struct drm_i915_private *dev_priv = to_i915(dev);
3527         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3528         enum transcoder cpu_transcoder;
3529         u8 master_pipes, slave_pipes;
3530         u8 enabled_transcoders = 0;
3531
3532         /*
3533          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3534          * consistency and less surprising code; it's in always on power).
3535          */
3536         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3537                                        panel_transcoder_mask) {
3538                 enum intel_display_power_domain power_domain;
3539                 intel_wakeref_t wakeref;
3540                 enum pipe trans_pipe;
3541                 u32 tmp = 0;
3542
3543                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3544                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3545                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3546
3547                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3548                         continue;
3549
3550                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3551                 default:
3552                         drm_WARN(dev, 1,
3553                                  "unknown pipe linked to transcoder %s\n",
3554                                  transcoder_name(cpu_transcoder));
3555                         fallthrough;
3556                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3557                 case TRANS_DDI_EDP_INPUT_A_ON:
3558                         trans_pipe = PIPE_A;
3559                         break;
3560                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3561                         trans_pipe = PIPE_B;
3562                         break;
3563                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3564                         trans_pipe = PIPE_C;
3565                         break;
3566                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3567                         trans_pipe = PIPE_D;
3568                         break;
3569                 }
3570
3571                 if (trans_pipe == crtc->pipe)
3572                         enabled_transcoders |= BIT(cpu_transcoder);
3573         }
3574
3575         /* single pipe or bigjoiner master */
3576         cpu_transcoder = (enum transcoder) crtc->pipe;
3577         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3578                 enabled_transcoders |= BIT(cpu_transcoder);
3579
3580         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3581         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3582         if (slave_pipes & BIT(crtc->pipe)) {
3583                 cpu_transcoder = (enum transcoder)
3584                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3585                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3586                         enabled_transcoders |= BIT(cpu_transcoder);
3587         }
3588
3589         return enabled_transcoders;
3590 }
3591
3592 static bool has_edp_transcoders(u8 enabled_transcoders)
3593 {
3594         return enabled_transcoders & BIT(TRANSCODER_EDP);
3595 }
3596
3597 static bool has_dsi_transcoders(u8 enabled_transcoders)
3598 {
3599         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3600                                       BIT(TRANSCODER_DSI_1));
3601 }
3602
3603 static bool has_pipe_transcoders(u8 enabled_transcoders)
3604 {
3605         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3606                                        BIT(TRANSCODER_DSI_0) |
3607                                        BIT(TRANSCODER_DSI_1));
3608 }
3609
3610 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3611                                        u8 enabled_transcoders)
3612 {
3613         /* Only one type of transcoder please */
3614         drm_WARN_ON(&i915->drm,
3615                     has_edp_transcoders(enabled_transcoders) +
3616                     has_dsi_transcoders(enabled_transcoders) +
3617                     has_pipe_transcoders(enabled_transcoders) > 1);
3618
3619         /* Only DSI transcoders can be ganged */
3620         drm_WARN_ON(&i915->drm,
3621                     !has_dsi_transcoders(enabled_transcoders) &&
3622                     !is_power_of_2(enabled_transcoders));
3623 }
3624
3625 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3626                                      struct intel_crtc_state *pipe_config,
3627                                      struct intel_display_power_domain_set *power_domain_set)
3628 {
3629         struct drm_device *dev = crtc->base.dev;
3630         struct drm_i915_private *dev_priv = to_i915(dev);
3631         unsigned long enabled_transcoders;
3632         u32 tmp;
3633
3634         enabled_transcoders = hsw_enabled_transcoders(crtc);
3635         if (!enabled_transcoders)
3636                 return false;
3637
3638         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3639
3640         /*
3641          * With the exception of DSI we should only ever have
3642          * a single enabled transcoder. With DSI let's just
3643          * pick the first one.
3644          */
3645         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3646
3647         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3648                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3649                 return false;
3650
3651         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3652                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3653
3654                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3655                         pipe_config->pch_pfit.force_thru = true;
3656         }
3657
3658         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3659
3660         return tmp & TRANSCONF_ENABLE;
3661 }
3662
3663 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3664                                          struct intel_crtc_state *pipe_config,
3665                                          struct intel_display_power_domain_set *power_domain_set)
3666 {
3667         struct drm_device *dev = crtc->base.dev;
3668         struct drm_i915_private *dev_priv = to_i915(dev);
3669         enum transcoder cpu_transcoder;
3670         enum port port;
3671         u32 tmp;
3672
3673         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3674                 if (port == PORT_A)
3675                         cpu_transcoder = TRANSCODER_DSI_A;
3676                 else
3677                         cpu_transcoder = TRANSCODER_DSI_C;
3678
3679                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3680                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3681                         continue;
3682
3683                 /*
3684                  * The PLL needs to be enabled with a valid divider
3685                  * configuration, otherwise accessing DSI registers will hang
3686                  * the machine. See BSpec North Display Engine
3687                  * registers/MIPI[BXT]. We can break out here early, since we
3688                  * need the same DSI PLL to be enabled for both DSI ports.
3689                  */
3690                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3691                         break;
3692
3693                 /* XXX: this works for video mode only */
3694                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3695                 if (!(tmp & DPI_ENABLE))
3696                         continue;
3697
3698                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3699                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3700                         continue;
3701
3702                 pipe_config->cpu_transcoder = cpu_transcoder;
3703                 break;
3704         }
3705
3706         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3707 }
3708
3709 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3710 {
3711         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3712         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3713         u8 master_pipes, slave_pipes;
3714         enum pipe pipe = crtc->pipe;
3715
3716         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3717
3718         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3719                 return;
3720
3721         crtc_state->bigjoiner_pipes =
3722                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3723                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3724 }
3725
3726 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3727                                 struct intel_crtc_state *pipe_config)
3728 {
3729         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3730         bool active;
3731         u32 tmp;
3732
3733         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3734                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3735                 return false;
3736
3737         pipe_config->shared_dpll = NULL;
3738
3739         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3740
3741         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3742             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3743                 drm_WARN_ON(&dev_priv->drm, active);
3744                 active = true;
3745         }
3746
3747         if (!active)
3748                 goto out;
3749
3750         intel_dsc_get_config(pipe_config);
3751         intel_bigjoiner_get_config(pipe_config);
3752
3753         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3754             DISPLAY_VER(dev_priv) >= 11)
3755                 intel_get_transcoder_timings(crtc, pipe_config);
3756
3757         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3758                 intel_vrr_get_config(pipe_config);
3759
3760         intel_get_pipe_src_size(crtc, pipe_config);
3761
3762         if (IS_HASWELL(dev_priv)) {
3763                 u32 tmp = intel_de_read(dev_priv,
3764                                         TRANSCONF(pipe_config->cpu_transcoder));
3765
3766                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3767                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3768                 else
3769                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3770         } else {
3771                 pipe_config->output_format =
3772                         bdw_get_pipe_misc_output_format(crtc);
3773         }
3774
3775         pipe_config->sink_format = pipe_config->output_format;
3776
3777         intel_color_get_config(pipe_config);
3778
3779         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3780         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3781         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3782                 pipe_config->ips_linetime =
3783                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3784
3785         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3786                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3787                 if (DISPLAY_VER(dev_priv) >= 9)
3788                         skl_scaler_get_config(pipe_config);
3789                 else
3790                         ilk_get_pfit_config(pipe_config);
3791         }
3792
3793         hsw_ips_get_config(pipe_config);
3794
3795         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3796             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3797                 pipe_config->pixel_multiplier =
3798                         intel_de_read(dev_priv,
3799                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3800         } else {
3801                 pipe_config->pixel_multiplier = 1;
3802         }
3803
3804         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3805                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3806                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3807                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
3808
3809                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3810         } else {
3811                 /* no idea if this is correct */
3812                 pipe_config->framestart_delay = 1;
3813         }
3814
3815 out:
3816         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3817
3818         return active;
3819 }
3820
3821 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3822 {
3823         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3824         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3825
3826         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3827                 return false;
3828
3829         crtc_state->hw.active = true;
3830
3831         intel_crtc_readout_derived_state(crtc_state);
3832
3833         return true;
3834 }
3835
3836 static int i9xx_pll_refclk(struct drm_device *dev,
3837                            const struct intel_crtc_state *pipe_config)
3838 {
3839         struct drm_i915_private *dev_priv = to_i915(dev);
3840         u32 dpll = pipe_config->dpll_hw_state.dpll;
3841
3842         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
3843                 return dev_priv->display.vbt.lvds_ssc_freq;
3844         else if (HAS_PCH_SPLIT(dev_priv))
3845                 return 120000;
3846         else if (DISPLAY_VER(dev_priv) != 2)
3847                 return 96000;
3848         else
3849                 return 48000;
3850 }
3851
3852 /* Returns the clock of the currently programmed mode of the given pipe. */
3853 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
3854                          struct intel_crtc_state *pipe_config)
3855 {
3856         struct drm_device *dev = crtc->base.dev;
3857         struct drm_i915_private *dev_priv = to_i915(dev);
3858         u32 dpll = pipe_config->dpll_hw_state.dpll;
3859         u32 fp;
3860         struct dpll clock;
3861         int port_clock;
3862         int refclk = i9xx_pll_refclk(dev, pipe_config);
3863
3864         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3865                 fp = pipe_config->dpll_hw_state.fp0;
3866         else
3867                 fp = pipe_config->dpll_hw_state.fp1;
3868
3869         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3870         if (IS_PINEVIEW(dev_priv)) {
3871                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3872                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3873         } else {
3874                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3875                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3876         }
3877
3878         if (DISPLAY_VER(dev_priv) != 2) {
3879                 if (IS_PINEVIEW(dev_priv))
3880                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3881                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3882                 else
3883                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3884                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3885
3886                 switch (dpll & DPLL_MODE_MASK) {
3887                 case DPLLB_MODE_DAC_SERIAL:
3888                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3889                                 5 : 10;
3890                         break;
3891                 case DPLLB_MODE_LVDS:
3892                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3893                                 7 : 14;
3894                         break;
3895                 default:
3896                         drm_dbg_kms(&dev_priv->drm,
3897                                     "Unknown DPLL mode %08x in programmed "
3898                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
3899                         return;
3900                 }
3901
3902                 if (IS_PINEVIEW(dev_priv))
3903                         port_clock = pnv_calc_dpll_params(refclk, &clock);
3904                 else
3905                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
3906         } else {
3907                 enum pipe lvds_pipe;
3908
3909                 if (IS_I85X(dev_priv) &&
3910                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
3911                     lvds_pipe == crtc->pipe) {
3912                         u32 lvds = intel_de_read(dev_priv, LVDS);
3913
3914                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3915                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3916
3917                         if (lvds & LVDS_CLKB_POWER_UP)
3918                                 clock.p2 = 7;
3919                         else
3920                                 clock.p2 = 14;
3921                 } else {
3922                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3923                                 clock.p1 = 2;
3924                         else {
3925                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3926                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3927                         }
3928                         if (dpll & PLL_P2_DIVIDE_BY_4)
3929                                 clock.p2 = 4;
3930                         else
3931                                 clock.p2 = 2;
3932                 }
3933
3934                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
3935         }
3936
3937         /*
3938          * This value includes pixel_multiplier. We will use
3939          * port_clock to compute adjusted_mode.crtc_clock in the
3940          * encoder's get_config() function.
3941          */
3942         pipe_config->port_clock = port_clock;
3943 }
3944
3945 int intel_dotclock_calculate(int link_freq,
3946                              const struct intel_link_m_n *m_n)
3947 {
3948         /*
3949          * The calculation for the data clock is:
3950          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3951          * But we want to avoid losing precison if possible, so:
3952          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3953          *
3954          * and the link clock is simpler:
3955          * link_clock = (m * link_clock) / n
3956          */
3957
3958         if (!m_n->link_n)
3959                 return 0;
3960
3961         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
3962                                 m_n->link_n);
3963 }
3964
3965 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3966 {
3967         int dotclock;
3968
3969         if (intel_crtc_has_dp_encoder(pipe_config))
3970                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3971                                                     &pipe_config->dp_m_n);
3972         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3973                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3974                                              pipe_config->pipe_bpp);
3975         else
3976                 dotclock = pipe_config->port_clock;
3977
3978         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3979             !intel_crtc_has_dp_encoder(pipe_config))
3980                 dotclock *= 2;
3981
3982         if (pipe_config->pixel_multiplier)
3983                 dotclock /= pipe_config->pixel_multiplier;
3984
3985         return dotclock;
3986 }
3987
3988 /* Returns the currently programmed mode of the given encoder. */
3989 struct drm_display_mode *
3990 intel_encoder_current_mode(struct intel_encoder *encoder)
3991 {
3992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3993         struct intel_crtc_state *crtc_state;
3994         struct drm_display_mode *mode;
3995         struct intel_crtc *crtc;
3996         enum pipe pipe;
3997
3998         if (!encoder->get_hw_state(encoder, &pipe))
3999                 return NULL;
4000
4001         crtc = intel_crtc_for_pipe(dev_priv, pipe);
4002
4003         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4004         if (!mode)
4005                 return NULL;
4006
4007         crtc_state = intel_crtc_state_alloc(crtc);
4008         if (!crtc_state) {
4009                 kfree(mode);
4010                 return NULL;
4011         }
4012
4013         if (!intel_crtc_get_pipe_config(crtc_state)) {
4014                 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4015                 kfree(mode);
4016                 return NULL;
4017         }
4018
4019         intel_encoder_get_config(encoder, crtc_state);
4020
4021         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4022
4023         intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4024
4025         return mode;
4026 }
4027
4028 static bool encoders_cloneable(const struct intel_encoder *a,
4029                                const struct intel_encoder *b)
4030 {
4031         /* masks could be asymmetric, so check both ways */
4032         return a == b || (a->cloneable & BIT(b->type) &&
4033                           b->cloneable & BIT(a->type));
4034 }
4035
4036 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4037                                          struct intel_crtc *crtc,
4038                                          struct intel_encoder *encoder)
4039 {
4040         struct intel_encoder *source_encoder;
4041         struct drm_connector *connector;
4042         struct drm_connector_state *connector_state;
4043         int i;
4044
4045         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4046                 if (connector_state->crtc != &crtc->base)
4047                         continue;
4048
4049                 source_encoder =
4050                         to_intel_encoder(connector_state->best_encoder);
4051                 if (!encoders_cloneable(encoder, source_encoder))
4052                         return false;
4053         }
4054
4055         return true;
4056 }
4057
4058 static int icl_add_linked_planes(struct intel_atomic_state *state)
4059 {
4060         struct intel_plane *plane, *linked;
4061         struct intel_plane_state *plane_state, *linked_plane_state;
4062         int i;
4063
4064         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4065                 linked = plane_state->planar_linked_plane;
4066
4067                 if (!linked)
4068                         continue;
4069
4070                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4071                 if (IS_ERR(linked_plane_state))
4072                         return PTR_ERR(linked_plane_state);
4073
4074                 drm_WARN_ON(state->base.dev,
4075                             linked_plane_state->planar_linked_plane != plane);
4076                 drm_WARN_ON(state->base.dev,
4077                             linked_plane_state->planar_slave == plane_state->planar_slave);
4078         }
4079
4080         return 0;
4081 }
4082
4083 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4084 {
4085         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4086         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4087         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4088         struct intel_plane *plane, *linked;
4089         struct intel_plane_state *plane_state;
4090         int i;
4091
4092         if (DISPLAY_VER(dev_priv) < 11)
4093                 return 0;
4094
4095         /*
4096          * Destroy all old plane links and make the slave plane invisible
4097          * in the crtc_state->active_planes mask.
4098          */
4099         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4100                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4101                         continue;
4102
4103                 plane_state->planar_linked_plane = NULL;
4104                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4105                         crtc_state->enabled_planes &= ~BIT(plane->id);
4106                         crtc_state->active_planes &= ~BIT(plane->id);
4107                         crtc_state->update_planes |= BIT(plane->id);
4108                         crtc_state->data_rate[plane->id] = 0;
4109                         crtc_state->rel_data_rate[plane->id] = 0;
4110                 }
4111
4112                 plane_state->planar_slave = false;
4113         }
4114
4115         if (!crtc_state->nv12_planes)
4116                 return 0;
4117
4118         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4119                 struct intel_plane_state *linked_state = NULL;
4120
4121                 if (plane->pipe != crtc->pipe ||
4122                     !(crtc_state->nv12_planes & BIT(plane->id)))
4123                         continue;
4124
4125                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4126                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4127                                 continue;
4128
4129                         if (crtc_state->active_planes & BIT(linked->id))
4130                                 continue;
4131
4132                         linked_state = intel_atomic_get_plane_state(state, linked);
4133                         if (IS_ERR(linked_state))
4134                                 return PTR_ERR(linked_state);
4135
4136                         break;
4137                 }
4138
4139                 if (!linked_state) {
4140                         drm_dbg_kms(&dev_priv->drm,
4141                                     "Need %d free Y planes for planar YUV\n",
4142                                     hweight8(crtc_state->nv12_planes));
4143
4144                         return -EINVAL;
4145                 }
4146
4147                 plane_state->planar_linked_plane = linked;
4148
4149                 linked_state->planar_slave = true;
4150                 linked_state->planar_linked_plane = plane;
4151                 crtc_state->enabled_planes |= BIT(linked->id);
4152                 crtc_state->active_planes |= BIT(linked->id);
4153                 crtc_state->update_planes |= BIT(linked->id);
4154                 crtc_state->data_rate[linked->id] =
4155                         crtc_state->data_rate_y[plane->id];
4156                 crtc_state->rel_data_rate[linked->id] =
4157                         crtc_state->rel_data_rate_y[plane->id];
4158                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4159                             linked->base.name, plane->base.name);
4160
4161                 /* Copy parameters to slave plane */
4162                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4163                 linked_state->color_ctl = plane_state->color_ctl;
4164                 linked_state->view = plane_state->view;
4165                 linked_state->decrypt = plane_state->decrypt;
4166
4167                 intel_plane_copy_hw_state(linked_state, plane_state);
4168                 linked_state->uapi.src = plane_state->uapi.src;
4169                 linked_state->uapi.dst = plane_state->uapi.dst;
4170
4171                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4172                         if (linked->id == PLANE_SPRITE5)
4173                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4174                         else if (linked->id == PLANE_SPRITE4)
4175                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4176                         else if (linked->id == PLANE_SPRITE3)
4177                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4178                         else if (linked->id == PLANE_SPRITE2)
4179                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4180                         else
4181                                 MISSING_CASE(linked->id);
4182                 }
4183         }
4184
4185         return 0;
4186 }
4187
4188 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4189 {
4190         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4191         struct intel_atomic_state *state =
4192                 to_intel_atomic_state(new_crtc_state->uapi.state);
4193         const struct intel_crtc_state *old_crtc_state =
4194                 intel_atomic_get_old_crtc_state(state, crtc);
4195
4196         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4197 }
4198
4199 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4200 {
4201         const struct drm_display_mode *pipe_mode =
4202                 &crtc_state->hw.pipe_mode;
4203         int linetime_wm;
4204
4205         if (!crtc_state->hw.enable)
4206                 return 0;
4207
4208         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4209                                         pipe_mode->crtc_clock);
4210
4211         return min(linetime_wm, 0x1ff);
4212 }
4213
4214 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4215                                const struct intel_cdclk_state *cdclk_state)
4216 {
4217         const struct drm_display_mode *pipe_mode =
4218                 &crtc_state->hw.pipe_mode;
4219         int linetime_wm;
4220
4221         if (!crtc_state->hw.enable)
4222                 return 0;
4223
4224         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4225                                         cdclk_state->logical.cdclk);
4226
4227         return min(linetime_wm, 0x1ff);
4228 }
4229
4230 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4231 {
4232         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4234         const struct drm_display_mode *pipe_mode =
4235                 &crtc_state->hw.pipe_mode;
4236         int linetime_wm;
4237
4238         if (!crtc_state->hw.enable)
4239                 return 0;
4240
4241         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4242                                    crtc_state->pixel_rate);
4243
4244         /* Display WA #1135: BXT:ALL GLK:ALL */
4245         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4246             skl_watermark_ipc_enabled(dev_priv))
4247                 linetime_wm /= 2;
4248
4249         return min(linetime_wm, 0x1ff);
4250 }
4251
4252 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4253                                    struct intel_crtc *crtc)
4254 {
4255         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4256         struct intel_crtc_state *crtc_state =
4257                 intel_atomic_get_new_crtc_state(state, crtc);
4258         const struct intel_cdclk_state *cdclk_state;
4259
4260         if (DISPLAY_VER(dev_priv) >= 9)
4261                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4262         else
4263                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4264
4265         if (!hsw_crtc_supports_ips(crtc))
4266                 return 0;
4267
4268         cdclk_state = intel_atomic_get_cdclk_state(state);
4269         if (IS_ERR(cdclk_state))
4270                 return PTR_ERR(cdclk_state);
4271
4272         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4273                                                        cdclk_state);
4274
4275         return 0;
4276 }
4277
4278 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4279                                    struct intel_crtc *crtc)
4280 {
4281         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4282         struct intel_crtc_state *crtc_state =
4283                 intel_atomic_get_new_crtc_state(state, crtc);
4284         int ret;
4285
4286         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4287             intel_crtc_needs_modeset(crtc_state) &&
4288             !crtc_state->hw.active)
4289                 crtc_state->update_wm_post = true;
4290
4291         if (intel_crtc_needs_modeset(crtc_state)) {
4292                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4293                 if (ret)
4294                         return ret;
4295         }
4296
4297         /*
4298          * May need to update pipe gamma enable bits
4299          * when C8 planes are getting enabled/disabled.
4300          */
4301         if (c8_planes_changed(crtc_state))
4302                 crtc_state->uapi.color_mgmt_changed = true;
4303
4304         if (intel_crtc_needs_color_update(crtc_state)) {
4305                 ret = intel_color_check(crtc_state);
4306                 if (ret)
4307                         return ret;
4308         }
4309
4310         ret = intel_compute_pipe_wm(state, crtc);
4311         if (ret) {
4312                 drm_dbg_kms(&dev_priv->drm,
4313                             "Target pipe watermarks are invalid\n");
4314                 return ret;
4315         }
4316
4317         /*
4318          * Calculate 'intermediate' watermarks that satisfy both the
4319          * old state and the new state.  We can program these
4320          * immediately.
4321          */
4322         ret = intel_compute_intermediate_wm(state, crtc);
4323         if (ret) {
4324                 drm_dbg_kms(&dev_priv->drm,
4325                             "No valid intermediate pipe watermarks are possible\n");
4326                 return ret;
4327         }
4328
4329         if (DISPLAY_VER(dev_priv) >= 9) {
4330                 if (intel_crtc_needs_modeset(crtc_state) ||
4331                     intel_crtc_needs_fastset(crtc_state)) {
4332                         ret = skl_update_scaler_crtc(crtc_state);
4333                         if (ret)
4334                                 return ret;
4335                 }
4336
4337                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4338                 if (ret)
4339                         return ret;
4340         }
4341
4342         if (HAS_IPS(dev_priv)) {
4343                 ret = hsw_ips_compute_config(state, crtc);
4344                 if (ret)
4345                         return ret;
4346         }
4347
4348         if (DISPLAY_VER(dev_priv) >= 9 ||
4349             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4350                 ret = hsw_compute_linetime_wm(state, crtc);
4351                 if (ret)
4352                         return ret;
4353
4354         }
4355
4356         ret = intel_psr2_sel_fetch_update(state, crtc);
4357         if (ret)
4358                 return ret;
4359
4360         return 0;
4361 }
4362
4363 static int
4364 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4365                       struct intel_crtc_state *crtc_state)
4366 {
4367         struct drm_connector *connector = conn_state->connector;
4368         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4369         const struct drm_display_info *info = &connector->display_info;
4370         int bpp;
4371
4372         switch (conn_state->max_bpc) {
4373         case 6 ... 7:
4374                 bpp = 6 * 3;
4375                 break;
4376         case 8 ... 9:
4377                 bpp = 8 * 3;
4378                 break;
4379         case 10 ... 11:
4380                 bpp = 10 * 3;
4381                 break;
4382         case 12 ... 16:
4383                 bpp = 12 * 3;
4384                 break;
4385         default:
4386                 MISSING_CASE(conn_state->max_bpc);
4387                 return -EINVAL;
4388         }
4389
4390         if (bpp < crtc_state->pipe_bpp) {
4391                 drm_dbg_kms(&i915->drm,
4392                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4393                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4394                             connector->base.id, connector->name,
4395                             bpp, 3 * info->bpc,
4396                             3 * conn_state->max_requested_bpc,
4397                             crtc_state->pipe_bpp);
4398
4399                 crtc_state->pipe_bpp = bpp;
4400         }
4401
4402         return 0;
4403 }
4404
4405 static int
4406 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4407                           struct intel_crtc *crtc)
4408 {
4409         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4410         struct intel_crtc_state *crtc_state =
4411                 intel_atomic_get_new_crtc_state(state, crtc);
4412         struct drm_connector *connector;
4413         struct drm_connector_state *connector_state;
4414         int bpp, i;
4415
4416         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4417             IS_CHERRYVIEW(dev_priv)))
4418                 bpp = 10*3;
4419         else if (DISPLAY_VER(dev_priv) >= 5)
4420                 bpp = 12*3;
4421         else
4422                 bpp = 8*3;
4423
4424         crtc_state->pipe_bpp = bpp;
4425
4426         /* Clamp display bpp to connector max bpp */
4427         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4428                 int ret;
4429
4430                 if (connector_state->crtc != &crtc->base)
4431                         continue;
4432
4433                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4434                 if (ret)
4435                         return ret;
4436         }
4437
4438         return 0;
4439 }
4440
4441 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4442 {
4443         struct drm_device *dev = state->base.dev;
4444         struct drm_connector *connector;
4445         struct drm_connector_list_iter conn_iter;
4446         unsigned int used_ports = 0;
4447         unsigned int used_mst_ports = 0;
4448         bool ret = true;
4449
4450         /*
4451          * We're going to peek into connector->state,
4452          * hence connection_mutex must be held.
4453          */
4454         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4455
4456         /*
4457          * Walk the connector list instead of the encoder
4458          * list to detect the problem on ddi platforms
4459          * where there's just one encoder per digital port.
4460          */
4461         drm_connector_list_iter_begin(dev, &conn_iter);
4462         drm_for_each_connector_iter(connector, &conn_iter) {
4463                 struct drm_connector_state *connector_state;
4464                 struct intel_encoder *encoder;
4465
4466                 connector_state =
4467                         drm_atomic_get_new_connector_state(&state->base,
4468                                                            connector);
4469                 if (!connector_state)
4470                         connector_state = connector->state;
4471
4472                 if (!connector_state->best_encoder)
4473                         continue;
4474
4475                 encoder = to_intel_encoder(connector_state->best_encoder);
4476
4477                 drm_WARN_ON(dev, !connector_state->crtc);
4478
4479                 switch (encoder->type) {
4480                 case INTEL_OUTPUT_DDI:
4481                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4482                                 break;
4483                         fallthrough;
4484                 case INTEL_OUTPUT_DP:
4485                 case INTEL_OUTPUT_HDMI:
4486                 case INTEL_OUTPUT_EDP:
4487                         /* the same port mustn't appear more than once */
4488                         if (used_ports & BIT(encoder->port))
4489                                 ret = false;
4490
4491                         used_ports |= BIT(encoder->port);
4492                         break;
4493                 case INTEL_OUTPUT_DP_MST:
4494                         used_mst_ports |=
4495                                 1 << encoder->port;
4496                         break;
4497                 default:
4498                         break;
4499                 }
4500         }
4501         drm_connector_list_iter_end(&conn_iter);
4502
4503         /* can't mix MST and SST/HDMI on the same port */
4504         if (used_ports & used_mst_ports)
4505                 return false;
4506
4507         return ret;
4508 }
4509
4510 static void
4511 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4512                                            struct intel_crtc *crtc)
4513 {
4514         struct intel_crtc_state *crtc_state =
4515                 intel_atomic_get_new_crtc_state(state, crtc);
4516
4517         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4518
4519         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4520                                   crtc_state->uapi.degamma_lut);
4521         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4522                                   crtc_state->uapi.gamma_lut);
4523         drm_property_replace_blob(&crtc_state->hw.ctm,
4524                                   crtc_state->uapi.ctm);
4525 }
4526
4527 static void
4528 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4529                                          struct intel_crtc *crtc)
4530 {
4531         struct intel_crtc_state *crtc_state =
4532                 intel_atomic_get_new_crtc_state(state, crtc);
4533
4534         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4535
4536         crtc_state->hw.enable = crtc_state->uapi.enable;
4537         crtc_state->hw.active = crtc_state->uapi.active;
4538         drm_mode_copy(&crtc_state->hw.mode,
4539                       &crtc_state->uapi.mode);
4540         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4541                       &crtc_state->uapi.adjusted_mode);
4542         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4543
4544         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4545 }
4546
4547 static void
4548 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4549                                     struct intel_crtc *slave_crtc)
4550 {
4551         struct intel_crtc_state *slave_crtc_state =
4552                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4553         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4554         const struct intel_crtc_state *master_crtc_state =
4555                 intel_atomic_get_new_crtc_state(state, master_crtc);
4556
4557         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4558                                   master_crtc_state->hw.degamma_lut);
4559         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4560                                   master_crtc_state->hw.gamma_lut);
4561         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4562                                   master_crtc_state->hw.ctm);
4563
4564         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4565 }
4566
4567 static int
4568 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4569                                   struct intel_crtc *slave_crtc)
4570 {
4571         struct intel_crtc_state *slave_crtc_state =
4572                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4573         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4574         const struct intel_crtc_state *master_crtc_state =
4575                 intel_atomic_get_new_crtc_state(state, master_crtc);
4576         struct intel_crtc_state *saved_state;
4577
4578         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4579                 slave_crtc_state->bigjoiner_pipes);
4580
4581         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4582         if (!saved_state)
4583                 return -ENOMEM;
4584
4585         /* preserve some things from the slave's original crtc state */
4586         saved_state->uapi = slave_crtc_state->uapi;
4587         saved_state->scaler_state = slave_crtc_state->scaler_state;
4588         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4589         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4590
4591         intel_crtc_free_hw_state(slave_crtc_state);
4592         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4593         kfree(saved_state);
4594
4595         /* Re-init hw state */
4596         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4597         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4598         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4599         drm_mode_copy(&slave_crtc_state->hw.mode,
4600                       &master_crtc_state->hw.mode);
4601         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4602                       &master_crtc_state->hw.pipe_mode);
4603         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4604                       &master_crtc_state->hw.adjusted_mode);
4605         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4606
4607         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4608
4609         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4610         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4611         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4612
4613         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4614                 slave_crtc_state->bigjoiner_pipes);
4615
4616         return 0;
4617 }
4618
4619 static int
4620 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4621                                  struct intel_crtc *crtc)
4622 {
4623         struct intel_crtc_state *crtc_state =
4624                 intel_atomic_get_new_crtc_state(state, crtc);
4625         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4626         struct intel_crtc_state *saved_state;
4627
4628         saved_state = intel_crtc_state_alloc(crtc);
4629         if (!saved_state)
4630                 return -ENOMEM;
4631
4632         /* free the old crtc_state->hw members */
4633         intel_crtc_free_hw_state(crtc_state);
4634
4635         /* FIXME: before the switch to atomic started, a new pipe_config was
4636          * kzalloc'd. Code that depends on any field being zero should be
4637          * fixed, so that the crtc_state can be safely duplicated. For now,
4638          * only fields that are know to not cause problems are preserved. */
4639
4640         saved_state->uapi = crtc_state->uapi;
4641         saved_state->inherited = crtc_state->inherited;
4642         saved_state->scaler_state = crtc_state->scaler_state;
4643         saved_state->shared_dpll = crtc_state->shared_dpll;
4644         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4645         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4646                sizeof(saved_state->icl_port_dplls));
4647         saved_state->crc_enabled = crtc_state->crc_enabled;
4648         if (IS_G4X(dev_priv) ||
4649             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4650                 saved_state->wm = crtc_state->wm;
4651
4652         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4653         kfree(saved_state);
4654
4655         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4656
4657         return 0;
4658 }
4659
4660 static int
4661 intel_modeset_pipe_config(struct intel_atomic_state *state,
4662                           struct intel_crtc *crtc,
4663                           const struct intel_link_bw_limits *limits)
4664 {
4665         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4666         struct intel_crtc_state *crtc_state =
4667                 intel_atomic_get_new_crtc_state(state, crtc);
4668         struct drm_connector *connector;
4669         struct drm_connector_state *connector_state;
4670         int pipe_src_w, pipe_src_h;
4671         int base_bpp, ret, i;
4672
4673         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4674
4675         crtc_state->framestart_delay = 1;
4676
4677         /*
4678          * Sanitize sync polarity flags based on requested ones. If neither
4679          * positive or negative polarity is requested, treat this as meaning
4680          * negative polarity.
4681          */
4682         if (!(crtc_state->hw.adjusted_mode.flags &
4683               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4684                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4685
4686         if (!(crtc_state->hw.adjusted_mode.flags &
4687               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4688                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4689
4690         ret = compute_baseline_pipe_bpp(state, crtc);
4691         if (ret)
4692                 return ret;
4693
4694         crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4695
4696         if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
4697                 drm_dbg_kms(&i915->drm,
4698                             "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
4699                             crtc->base.base.id, crtc->base.name,
4700                             BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
4701                 crtc_state->bw_constrained = true;
4702         }
4703
4704         base_bpp = crtc_state->pipe_bpp;
4705
4706         /*
4707          * Determine the real pipe dimensions. Note that stereo modes can
4708          * increase the actual pipe size due to the frame doubling and
4709          * insertion of additional space for blanks between the frame. This
4710          * is stored in the crtc timings. We use the requested mode to do this
4711          * computation to clearly distinguish it from the adjusted mode, which
4712          * can be changed by the connectors in the below retry loop.
4713          */
4714         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4715                                &pipe_src_w, &pipe_src_h);
4716         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4717                       pipe_src_w, pipe_src_h);
4718
4719         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4720                 struct intel_encoder *encoder =
4721                         to_intel_encoder(connector_state->best_encoder);
4722
4723                 if (connector_state->crtc != &crtc->base)
4724                         continue;
4725
4726                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4727                         drm_dbg_kms(&i915->drm,
4728                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4729                                     encoder->base.base.id, encoder->base.name);
4730                         return -EINVAL;
4731                 }
4732
4733                 /*
4734                  * Determine output_types before calling the .compute_config()
4735                  * hooks so that the hooks can use this information safely.
4736                  */
4737                 if (encoder->compute_output_type)
4738                         crtc_state->output_types |=
4739                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4740                                                                  connector_state));
4741                 else
4742                         crtc_state->output_types |= BIT(encoder->type);
4743         }
4744
4745         /* Ensure the port clock defaults are reset when retrying. */
4746         crtc_state->port_clock = 0;
4747         crtc_state->pixel_multiplier = 1;
4748
4749         /* Fill in default crtc timings, allow encoders to overwrite them. */
4750         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4751                               CRTC_STEREO_DOUBLE);
4752
4753         /* Pass our mode to the connectors and the CRTC to give them a chance to
4754          * adjust it according to limitations or connector properties, and also
4755          * a chance to reject the mode entirely.
4756          */
4757         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4758                 struct intel_encoder *encoder =
4759                         to_intel_encoder(connector_state->best_encoder);
4760
4761                 if (connector_state->crtc != &crtc->base)
4762                         continue;
4763
4764                 ret = encoder->compute_config(encoder, crtc_state,
4765                                               connector_state);
4766                 if (ret == -EDEADLK)
4767                         return ret;
4768                 if (ret < 0) {
4769                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4770                                     encoder->base.base.id, encoder->base.name, ret);
4771                         return ret;
4772                 }
4773         }
4774
4775         /* Set default port clock if not overwritten by the encoder. Needs to be
4776          * done afterwards in case the encoder adjusts the mode. */
4777         if (!crtc_state->port_clock)
4778                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4779                         * crtc_state->pixel_multiplier;
4780
4781         ret = intel_crtc_compute_config(state, crtc);
4782         if (ret == -EDEADLK)
4783                 return ret;
4784         if (ret < 0) {
4785                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4786                             crtc->base.base.id, crtc->base.name, ret);
4787                 return ret;
4788         }
4789
4790         /* Dithering seems to not pass-through bits correctly when it should, so
4791          * only enable it on 6bpc panels and when its not a compliance
4792          * test requesting 6bpc video pattern.
4793          */
4794         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4795                 !crtc_state->dither_force_disable;
4796         drm_dbg_kms(&i915->drm,
4797                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4798                     crtc->base.base.id, crtc->base.name,
4799                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4800
4801         return 0;
4802 }
4803
4804 static int
4805 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4806                                struct intel_crtc *crtc)
4807 {
4808         struct intel_crtc_state *crtc_state =
4809                 intel_atomic_get_new_crtc_state(state, crtc);
4810         struct drm_connector_state *conn_state;
4811         struct drm_connector *connector;
4812         int i;
4813
4814         intel_bigjoiner_adjust_pipe_src(crtc_state);
4815
4816         for_each_new_connector_in_state(&state->base, connector,
4817                                         conn_state, i) {
4818                 struct intel_encoder *encoder =
4819                         to_intel_encoder(conn_state->best_encoder);
4820                 int ret;
4821
4822                 if (conn_state->crtc != &crtc->base ||
4823                     !encoder->compute_config_late)
4824                         continue;
4825
4826                 ret = encoder->compute_config_late(encoder, crtc_state,
4827                                                    conn_state);
4828                 if (ret)
4829                         return ret;
4830         }
4831
4832         return 0;
4833 }
4834
4835 bool intel_fuzzy_clock_check(int clock1, int clock2)
4836 {
4837         int diff;
4838
4839         if (clock1 == clock2)
4840                 return true;
4841
4842         if (!clock1 || !clock2)
4843                 return false;
4844
4845         diff = abs(clock1 - clock2);
4846
4847         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4848                 return true;
4849
4850         return false;
4851 }
4852
4853 static bool
4854 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4855                        const struct intel_link_m_n *m2_n2)
4856 {
4857         return m_n->tu == m2_n2->tu &&
4858                 m_n->data_m == m2_n2->data_m &&
4859                 m_n->data_n == m2_n2->data_n &&
4860                 m_n->link_m == m2_n2->link_m &&
4861                 m_n->link_n == m2_n2->link_n;
4862 }
4863
4864 static bool
4865 intel_compare_infoframe(const union hdmi_infoframe *a,
4866                         const union hdmi_infoframe *b)
4867 {
4868         return memcmp(a, b, sizeof(*a)) == 0;
4869 }
4870
4871 static bool
4872 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4873                          const struct drm_dp_vsc_sdp *b)
4874 {
4875         return memcmp(a, b, sizeof(*a)) == 0;
4876 }
4877
4878 static bool
4879 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4880 {
4881         return memcmp(a, b, len) == 0;
4882 }
4883
4884 static void
4885 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
4886                                bool fastset, const char *name,
4887                                const union hdmi_infoframe *a,
4888                                const union hdmi_infoframe *b)
4889 {
4890         if (fastset) {
4891                 if (!drm_debug_enabled(DRM_UT_KMS))
4892                         return;
4893
4894                 drm_dbg_kms(&dev_priv->drm,
4895                             "fastset requirement not met in %s infoframe\n", name);
4896                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4897                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
4898                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4899                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
4900         } else {
4901                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
4902                 drm_err(&dev_priv->drm, "expected:\n");
4903                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
4904                 drm_err(&dev_priv->drm, "found:\n");
4905                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
4906         }
4907 }
4908
4909 static void
4910 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
4911                                 bool fastset, const char *name,
4912                                 const struct drm_dp_vsc_sdp *a,
4913                                 const struct drm_dp_vsc_sdp *b)
4914 {
4915         if (fastset) {
4916                 if (!drm_debug_enabled(DRM_UT_KMS))
4917                         return;
4918
4919                 drm_dbg_kms(&dev_priv->drm,
4920                             "fastset requirement not met in %s dp sdp\n", name);
4921                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4922                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
4923                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4924                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
4925         } else {
4926                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
4927                 drm_err(&dev_priv->drm, "expected:\n");
4928                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
4929                 drm_err(&dev_priv->drm, "found:\n");
4930                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
4931         }
4932 }
4933
4934 /* Returns the length up to and including the last differing byte */
4935 static size_t
4936 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4937 {
4938         int i;
4939
4940         for (i = len - 1; i >= 0; i--) {
4941                 if (a[i] != b[i])
4942                         return i + 1;
4943         }
4944
4945         return 0;
4946 }
4947
4948 static void
4949 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
4950                             bool fastset, const char *name,
4951                             const u8 *a, const u8 *b, size_t len)
4952 {
4953         if (fastset) {
4954                 if (!drm_debug_enabled(DRM_UT_KMS))
4955                         return;
4956
4957                 /* only dump up to the last difference */
4958                 len = memcmp_diff_len(a, b, len);
4959
4960                 drm_dbg_kms(&dev_priv->drm,
4961                             "fastset requirement not met in %s buffer\n", name);
4962                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
4963                                16, 0, a, len, false);
4964                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
4965                                16, 0, b, len, false);
4966         } else {
4967                 /* only dump up to the last difference */
4968                 len = memcmp_diff_len(a, b, len);
4969
4970                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
4971                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
4972                                16, 0, a, len, false);
4973                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
4974                                16, 0, b, len, false);
4975         }
4976 }
4977
4978 static void __printf(4, 5)
4979 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
4980                      const char *name, const char *format, ...)
4981 {
4982         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4983         struct va_format vaf;
4984         va_list args;
4985
4986         va_start(args, format);
4987         vaf.fmt = format;
4988         vaf.va = &args;
4989
4990         if (fastset)
4991                 drm_dbg_kms(&i915->drm,
4992                             "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4993                             crtc->base.base.id, crtc->base.name, name, &vaf);
4994         else
4995                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
4996                         crtc->base.base.id, crtc->base.name, name, &vaf);
4997
4998         va_end(args);
4999 }
5000
5001 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5002 {
5003         /* Enable fastboot by default on Skylake and newer */
5004         if (DISPLAY_VER(dev_priv) >= 9)
5005                 return true;
5006
5007         /* Enable fastboot by default on VLV and CHV */
5008         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5009                 return true;
5010
5011         /* Disabled by default on all others */
5012         return false;
5013 }
5014
5015 bool
5016 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5017                           const struct intel_crtc_state *pipe_config,
5018                           bool fastset)
5019 {
5020         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5021         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5022         bool ret = true;
5023         bool fixup_inherited = fastset &&
5024                 current_config->inherited && !pipe_config->inherited;
5025
5026         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5027                 drm_dbg_kms(&dev_priv->drm,
5028                             "initial modeset and fastboot not set\n");
5029                 ret = false;
5030         }
5031
5032 #define PIPE_CONF_CHECK_X(name) do { \
5033         if (current_config->name != pipe_config->name) { \
5034                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5035                                      "(expected 0x%08x, found 0x%08x)", \
5036                                      current_config->name, \
5037                                      pipe_config->name); \
5038                 ret = false; \
5039         } \
5040 } while (0)
5041
5042 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5043         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5044                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5045                                      "(expected 0x%08x, found 0x%08x)", \
5046                                      current_config->name & (mask), \
5047                                      pipe_config->name & (mask)); \
5048                 ret = false; \
5049         } \
5050 } while (0)
5051
5052 #define PIPE_CONF_CHECK_I(name) do { \
5053         if (current_config->name != pipe_config->name) { \
5054                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5055                                      "(expected %i, found %i)", \
5056                                      current_config->name, \
5057                                      pipe_config->name); \
5058                 ret = false; \
5059         } \
5060 } while (0)
5061
5062 #define PIPE_CONF_CHECK_BOOL(name) do { \
5063         if (current_config->name != pipe_config->name) { \
5064                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5065                                      "(expected %s, found %s)", \
5066                                      str_yes_no(current_config->name), \
5067                                      str_yes_no(pipe_config->name)); \
5068                 ret = false; \
5069         } \
5070 } while (0)
5071
5072 /*
5073  * Checks state where we only read out the enabling, but not the entire
5074  * state itself (like full infoframes or ELD for audio). These states
5075  * require a full modeset on bootup to fix up.
5076  */
5077 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5078         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5079                 PIPE_CONF_CHECK_BOOL(name); \
5080         } else { \
5081                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5082                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5083                                      str_yes_no(current_config->name), \
5084                                      str_yes_no(pipe_config->name)); \
5085                 ret = false; \
5086         } \
5087 } while (0)
5088
5089 #define PIPE_CONF_CHECK_P(name) do { \
5090         if (current_config->name != pipe_config->name) { \
5091                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5092                                      "(expected %p, found %p)", \
5093                                      current_config->name, \
5094                                      pipe_config->name); \
5095                 ret = false; \
5096         } \
5097 } while (0)
5098
5099 #define PIPE_CONF_CHECK_M_N(name) do { \
5100         if (!intel_compare_link_m_n(&current_config->name, \
5101                                     &pipe_config->name)) { \
5102                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5103                                      "(expected tu %i data %i/%i link %i/%i, " \
5104                                      "found tu %i, data %i/%i link %i/%i)", \
5105                                      current_config->name.tu, \
5106                                      current_config->name.data_m, \
5107                                      current_config->name.data_n, \
5108                                      current_config->name.link_m, \
5109                                      current_config->name.link_n, \
5110                                      pipe_config->name.tu, \
5111                                      pipe_config->name.data_m, \
5112                                      pipe_config->name.data_n, \
5113                                      pipe_config->name.link_m, \
5114                                      pipe_config->name.link_n); \
5115                 ret = false; \
5116         } \
5117 } while (0)
5118
5119 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5120         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5121         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5122         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5123         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5124         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5125         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5126         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5127         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5128         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5129         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5130         if (!fastset || !pipe_config->update_lrr) { \
5131                 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5132                 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5133         } \
5134 } while (0)
5135
5136 #define PIPE_CONF_CHECK_RECT(name) do { \
5137         PIPE_CONF_CHECK_I(name.x1); \
5138         PIPE_CONF_CHECK_I(name.x2); \
5139         PIPE_CONF_CHECK_I(name.y1); \
5140         PIPE_CONF_CHECK_I(name.y2); \
5141 } while (0)
5142
5143 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5144         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5145                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5146                                      "(%x) (expected %i, found %i)", \
5147                                      (mask), \
5148                                      current_config->name & (mask), \
5149                                      pipe_config->name & (mask)); \
5150                 ret = false; \
5151         } \
5152 } while (0)
5153
5154 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5155         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5156                                      &pipe_config->infoframes.name)) { \
5157                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5158                                                &current_config->infoframes.name, \
5159                                                &pipe_config->infoframes.name); \
5160                 ret = false; \
5161         } \
5162 } while (0)
5163
5164 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5165         if (!current_config->has_psr && !pipe_config->has_psr && \
5166             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5167                                       &pipe_config->infoframes.name)) { \
5168                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5169                                                 &current_config->infoframes.name, \
5170                                                 &pipe_config->infoframes.name); \
5171                 ret = false; \
5172         } \
5173 } while (0)
5174
5175 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5176         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5177         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5178         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5179                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5180                                             current_config->name, \
5181                                             pipe_config->name, \
5182                                             (len)); \
5183                 ret = false; \
5184         } \
5185 } while (0)
5186
5187 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5188         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5189             !intel_color_lut_equal(current_config, \
5190                                    current_config->lut, pipe_config->lut, \
5191                                    is_pre_csc_lut)) {   \
5192                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5193                                      "hw_state doesn't match sw_state"); \
5194                 ret = false; \
5195         } \
5196 } while (0)
5197
5198 #define PIPE_CONF_CHECK_CSC(name) do { \
5199         PIPE_CONF_CHECK_X(name.preoff[0]); \
5200         PIPE_CONF_CHECK_X(name.preoff[1]); \
5201         PIPE_CONF_CHECK_X(name.preoff[2]); \
5202         PIPE_CONF_CHECK_X(name.coeff[0]); \
5203         PIPE_CONF_CHECK_X(name.coeff[1]); \
5204         PIPE_CONF_CHECK_X(name.coeff[2]); \
5205         PIPE_CONF_CHECK_X(name.coeff[3]); \
5206         PIPE_CONF_CHECK_X(name.coeff[4]); \
5207         PIPE_CONF_CHECK_X(name.coeff[5]); \
5208         PIPE_CONF_CHECK_X(name.coeff[6]); \
5209         PIPE_CONF_CHECK_X(name.coeff[7]); \
5210         PIPE_CONF_CHECK_X(name.coeff[8]); \
5211         PIPE_CONF_CHECK_X(name.postoff[0]); \
5212         PIPE_CONF_CHECK_X(name.postoff[1]); \
5213         PIPE_CONF_CHECK_X(name.postoff[2]); \
5214 } while (0)
5215
5216 #define PIPE_CONF_QUIRK(quirk) \
5217         ((current_config->quirks | pipe_config->quirks) & (quirk))
5218
5219         PIPE_CONF_CHECK_I(hw.enable);
5220         PIPE_CONF_CHECK_I(hw.active);
5221
5222         PIPE_CONF_CHECK_I(cpu_transcoder);
5223         PIPE_CONF_CHECK_I(mst_master_transcoder);
5224
5225         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5226         PIPE_CONF_CHECK_I(fdi_lanes);
5227         PIPE_CONF_CHECK_M_N(fdi_m_n);
5228
5229         PIPE_CONF_CHECK_I(lane_count);
5230         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5231
5232         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5233                 if (!fastset || !pipe_config->update_m_n)
5234                         PIPE_CONF_CHECK_M_N(dp_m_n);
5235         } else {
5236                 PIPE_CONF_CHECK_M_N(dp_m_n);
5237                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5238         }
5239
5240         PIPE_CONF_CHECK_X(output_types);
5241
5242         PIPE_CONF_CHECK_I(framestart_delay);
5243         PIPE_CONF_CHECK_I(msa_timing_delay);
5244
5245         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5246         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5247
5248         PIPE_CONF_CHECK_I(pixel_multiplier);
5249
5250         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5251                               DRM_MODE_FLAG_INTERLACE);
5252
5253         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5254                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5255                                       DRM_MODE_FLAG_PHSYNC);
5256                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5257                                       DRM_MODE_FLAG_NHSYNC);
5258                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5259                                       DRM_MODE_FLAG_PVSYNC);
5260                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5261                                       DRM_MODE_FLAG_NVSYNC);
5262         }
5263
5264         PIPE_CONF_CHECK_I(output_format);
5265         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5266         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5267             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5268                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5269
5270         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5271         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5272         PIPE_CONF_CHECK_BOOL(has_infoframe);
5273         PIPE_CONF_CHECK_BOOL(enhanced_framing);
5274         PIPE_CONF_CHECK_BOOL(fec_enable);
5275
5276         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5277         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5278
5279         PIPE_CONF_CHECK_X(gmch_pfit.control);
5280         /* pfit ratios are autocomputed by the hw on gen4+ */
5281         if (DISPLAY_VER(dev_priv) < 4)
5282                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5283         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5284
5285         /*
5286          * Changing the EDP transcoder input mux
5287          * (A_ONOFF vs. A_ON) requires a full modeset.
5288          */
5289         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5290
5291         if (!fastset) {
5292                 PIPE_CONF_CHECK_RECT(pipe_src);
5293
5294                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5295                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5296
5297                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5298                 PIPE_CONF_CHECK_I(pixel_rate);
5299
5300                 PIPE_CONF_CHECK_X(gamma_mode);
5301                 if (IS_CHERRYVIEW(dev_priv))
5302                         PIPE_CONF_CHECK_X(cgm_mode);
5303                 else
5304                         PIPE_CONF_CHECK_X(csc_mode);
5305                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5306                 PIPE_CONF_CHECK_BOOL(csc_enable);
5307                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5308
5309                 PIPE_CONF_CHECK_I(linetime);
5310                 PIPE_CONF_CHECK_I(ips_linetime);
5311
5312                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5313                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5314
5315                 PIPE_CONF_CHECK_CSC(csc);
5316                 PIPE_CONF_CHECK_CSC(output_csc);
5317
5318                 if (current_config->active_planes) {
5319                         PIPE_CONF_CHECK_BOOL(has_psr);
5320                         PIPE_CONF_CHECK_BOOL(has_psr2);
5321                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5322                         PIPE_CONF_CHECK_I(dc3co_exitline);
5323                 }
5324         }
5325
5326         PIPE_CONF_CHECK_BOOL(double_wide);
5327
5328         if (dev_priv->display.dpll.mgr) {
5329                 PIPE_CONF_CHECK_P(shared_dpll);
5330
5331                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5332                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5333                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5334                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5335                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5336                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5337                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5338                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5339                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5340                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5341                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5342                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5343                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5344                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5345                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5346                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5347                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5348                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5349                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5350                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5351                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5352                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5353                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5354                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5355                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5356                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5357                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5358                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5359                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5360                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5361                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5362                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5363         }
5364
5365         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5366         PIPE_CONF_CHECK_X(dsi_pll.div);
5367
5368         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5369                 PIPE_CONF_CHECK_I(pipe_bpp);
5370
5371         if (!fastset || !pipe_config->update_m_n) {
5372                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5373                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5374         }
5375         PIPE_CONF_CHECK_I(port_clock);
5376
5377         PIPE_CONF_CHECK_I(min_voltage_level);
5378
5379         if (current_config->has_psr || pipe_config->has_psr)
5380                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5381                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5382         else
5383                 PIPE_CONF_CHECK_X(infoframes.enable);
5384
5385         PIPE_CONF_CHECK_X(infoframes.gcp);
5386         PIPE_CONF_CHECK_INFOFRAME(avi);
5387         PIPE_CONF_CHECK_INFOFRAME(spd);
5388         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5389         PIPE_CONF_CHECK_INFOFRAME(drm);
5390         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5391
5392         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5393         PIPE_CONF_CHECK_I(master_transcoder);
5394         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5395
5396         PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5397         PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5398         PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5399         PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5400         PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5401         PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5402         PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5403         PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5404         PIPE_CONF_CHECK_I(dsc.config.pic_width);
5405         PIPE_CONF_CHECK_I(dsc.config.pic_height);
5406         PIPE_CONF_CHECK_I(dsc.config.slice_width);
5407         PIPE_CONF_CHECK_I(dsc.config.slice_height);
5408         PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5409         PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5410         PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5411         PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5412         PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5413         PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5414         PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5415         PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5416         PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5417         PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5418         PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5419         PIPE_CONF_CHECK_I(dsc.config.final_offset);
5420         PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5421         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5422         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5423         PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5424         PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5425         PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5426
5427         PIPE_CONF_CHECK_I(dsc.compression_enable);
5428         PIPE_CONF_CHECK_I(dsc.dsc_split);
5429         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5430
5431         PIPE_CONF_CHECK_BOOL(splitter.enable);
5432         PIPE_CONF_CHECK_I(splitter.link_count);
5433         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5434
5435         if (!fastset) {
5436                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5437                 PIPE_CONF_CHECK_I(vrr.vmin);
5438                 PIPE_CONF_CHECK_I(vrr.vmax);
5439                 PIPE_CONF_CHECK_I(vrr.flipline);
5440                 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5441                 PIPE_CONF_CHECK_I(vrr.guardband);
5442         }
5443
5444 #undef PIPE_CONF_CHECK_X
5445 #undef PIPE_CONF_CHECK_I
5446 #undef PIPE_CONF_CHECK_BOOL
5447 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5448 #undef PIPE_CONF_CHECK_P
5449 #undef PIPE_CONF_CHECK_FLAGS
5450 #undef PIPE_CONF_CHECK_COLOR_LUT
5451 #undef PIPE_CONF_CHECK_TIMINGS
5452 #undef PIPE_CONF_CHECK_RECT
5453 #undef PIPE_CONF_QUIRK
5454
5455         return ret;
5456 }
5457
5458 static void
5459 intel_verify_planes(struct intel_atomic_state *state)
5460 {
5461         struct intel_plane *plane;
5462         const struct intel_plane_state *plane_state;
5463         int i;
5464
5465         for_each_new_intel_plane_in_state(state, plane,
5466                                           plane_state, i)
5467                 assert_plane(plane, plane_state->planar_slave ||
5468                              plane_state->uapi.visible);
5469 }
5470
5471 static int intel_modeset_pipe(struct intel_atomic_state *state,
5472                               struct intel_crtc_state *crtc_state,
5473                               const char *reason)
5474 {
5475         struct drm_i915_private *i915 = to_i915(state->base.dev);
5476         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5477         int ret;
5478
5479         drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5480                     crtc->base.base.id, crtc->base.name, reason);
5481
5482         ret = drm_atomic_add_affected_connectors(&state->base,
5483                                                  &crtc->base);
5484         if (ret)
5485                 return ret;
5486
5487         ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5488         if (ret)
5489                 return ret;
5490
5491         ret = intel_atomic_add_affected_planes(state, crtc);
5492         if (ret)
5493                 return ret;
5494
5495         crtc_state->uapi.mode_changed = true;
5496
5497         return 0;
5498 }
5499
5500 /**
5501  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5502  * @state: intel atomic state
5503  * @reason: the reason for the full modeset
5504  * @mask: mask of pipes to modeset
5505  *
5506  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5507  * due to the description in @reason.
5508  * This function can be called only before new plane states are computed.
5509  *
5510  * Returns 0 in case of success, negative error code otherwise.
5511  */
5512 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5513                                       const char *reason, u8 mask)
5514 {
5515         struct drm_i915_private *i915 = to_i915(state->base.dev);
5516         struct intel_crtc *crtc;
5517
5518         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
5519                 struct intel_crtc_state *crtc_state;
5520                 int ret;
5521
5522                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5523                 if (IS_ERR(crtc_state))
5524                         return PTR_ERR(crtc_state);
5525
5526                 if (!crtc_state->hw.enable ||
5527                     intel_crtc_needs_modeset(crtc_state))
5528                         continue;
5529
5530                 ret = intel_modeset_pipe(state, crtc_state, reason);
5531                 if (ret)
5532                         return ret;
5533         }
5534
5535         return 0;
5536 }
5537
5538 /**
5539  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5540  * @state: intel atomic state
5541  * @reason: the reason for the full modeset
5542  *
5543  * Add all pipes to @state and force a full modeset on the active ones due to
5544  * the description in @reason.
5545  * This function can be called only after new plane states are computed already.
5546  *
5547  * Returns 0 in case of success, negative error code otherwise.
5548  */
5549 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5550                                  const char *reason)
5551 {
5552         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5553         struct intel_crtc *crtc;
5554
5555         for_each_intel_crtc(&dev_priv->drm, crtc) {
5556                 struct intel_crtc_state *crtc_state;
5557                 int ret;
5558
5559                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5560                 if (IS_ERR(crtc_state))
5561                         return PTR_ERR(crtc_state);
5562
5563                 if (!crtc_state->hw.active ||
5564                     intel_crtc_needs_modeset(crtc_state))
5565                         continue;
5566
5567                 ret = intel_modeset_pipe(state, crtc_state, reason);
5568                 if (ret)
5569                         return ret;
5570
5571                 crtc_state->update_pipe = false;
5572                 crtc_state->update_m_n = false;
5573                 crtc_state->update_lrr = false;
5574                 crtc_state->update_planes |= crtc_state->active_planes;
5575                 crtc_state->async_flip_planes = 0;
5576                 crtc_state->do_async_flip = false;
5577         }
5578
5579         return 0;
5580 }
5581
5582 /*
5583  * This implements the workaround described in the "notes" section of the mode
5584  * set sequence documentation. When going from no pipes or single pipe to
5585  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5586  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5587  */
5588 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5589 {
5590         struct intel_crtc_state *crtc_state;
5591         struct intel_crtc *crtc;
5592         struct intel_crtc_state *first_crtc_state = NULL;
5593         struct intel_crtc_state *other_crtc_state = NULL;
5594         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5595         int i;
5596
5597         /* look at all crtc's that are going to be enabled in during modeset */
5598         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5599                 if (!crtc_state->hw.active ||
5600                     !intel_crtc_needs_modeset(crtc_state))
5601                         continue;
5602
5603                 if (first_crtc_state) {
5604                         other_crtc_state = crtc_state;
5605                         break;
5606                 } else {
5607                         first_crtc_state = crtc_state;
5608                         first_pipe = crtc->pipe;
5609                 }
5610         }
5611
5612         /* No workaround needed? */
5613         if (!first_crtc_state)
5614                 return 0;
5615
5616         /* w/a possibly needed, check how many crtc's are already enabled. */
5617         for_each_intel_crtc(state->base.dev, crtc) {
5618                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5619                 if (IS_ERR(crtc_state))
5620                         return PTR_ERR(crtc_state);
5621
5622                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5623
5624                 if (!crtc_state->hw.active ||
5625                     intel_crtc_needs_modeset(crtc_state))
5626                         continue;
5627
5628                 /* 2 or more enabled crtcs means no need for w/a */
5629                 if (enabled_pipe != INVALID_PIPE)
5630                         return 0;
5631
5632                 enabled_pipe = crtc->pipe;
5633         }
5634
5635         if (enabled_pipe != INVALID_PIPE)
5636                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5637         else if (other_crtc_state)
5638                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5639
5640         return 0;
5641 }
5642
5643 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5644                            u8 active_pipes)
5645 {
5646         const struct intel_crtc_state *crtc_state;
5647         struct intel_crtc *crtc;
5648         int i;
5649
5650         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5651                 if (crtc_state->hw.active)
5652                         active_pipes |= BIT(crtc->pipe);
5653                 else
5654                         active_pipes &= ~BIT(crtc->pipe);
5655         }
5656
5657         return active_pipes;
5658 }
5659
5660 static int intel_modeset_checks(struct intel_atomic_state *state)
5661 {
5662         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5663
5664         state->modeset = true;
5665
5666         if (IS_HASWELL(dev_priv))
5667                 return hsw_mode_set_planes_workaround(state);
5668
5669         return 0;
5670 }
5671
5672 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5673                                      struct intel_crtc_state *new_crtc_state)
5674 {
5675         struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
5676
5677         /* only allow LRR when the timings stay within the VRR range */
5678         if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5679                 new_crtc_state->update_lrr = false;
5680
5681         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5682                 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5683         else
5684                 new_crtc_state->uapi.mode_changed = false;
5685
5686         if (intel_crtc_needs_modeset(new_crtc_state) ||
5687             intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5688                                    &new_crtc_state->dp_m_n))
5689                 new_crtc_state->update_m_n = false;
5690
5691         if (intel_crtc_needs_modeset(new_crtc_state) ||
5692             (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5693              old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
5694                 new_crtc_state->update_lrr = false;
5695
5696         if (!intel_crtc_needs_modeset(new_crtc_state))
5697                 new_crtc_state->update_pipe = true;
5698 }
5699
5700 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5701                                           struct intel_crtc *crtc,
5702                                           u8 plane_ids_mask)
5703 {
5704         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5705         struct intel_plane *plane;
5706
5707         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5708                 struct intel_plane_state *plane_state;
5709
5710                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5711                         continue;
5712
5713                 plane_state = intel_atomic_get_plane_state(state, plane);
5714                 if (IS_ERR(plane_state))
5715                         return PTR_ERR(plane_state);
5716         }
5717
5718         return 0;
5719 }
5720
5721 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5722                                      struct intel_crtc *crtc)
5723 {
5724         const struct intel_crtc_state *old_crtc_state =
5725                 intel_atomic_get_old_crtc_state(state, crtc);
5726         const struct intel_crtc_state *new_crtc_state =
5727                 intel_atomic_get_new_crtc_state(state, crtc);
5728
5729         return intel_crtc_add_planes_to_state(state, crtc,
5730                                               old_crtc_state->enabled_planes |
5731                                               new_crtc_state->enabled_planes);
5732 }
5733
5734 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5735 {
5736         /* See {hsw,vlv,ivb}_plane_ratio() */
5737         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5738                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5739                 IS_IVYBRIDGE(dev_priv);
5740 }
5741
5742 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5743                                            struct intel_crtc *crtc,
5744                                            struct intel_crtc *other)
5745 {
5746         const struct intel_plane_state __maybe_unused *plane_state;
5747         struct intel_plane *plane;
5748         u8 plane_ids = 0;
5749         int i;
5750
5751         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5752                 if (plane->pipe == crtc->pipe)
5753                         plane_ids |= BIT(plane->id);
5754         }
5755
5756         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5757 }
5758
5759 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5760 {
5761         struct drm_i915_private *i915 = to_i915(state->base.dev);
5762         const struct intel_crtc_state *crtc_state;
5763         struct intel_crtc *crtc;
5764         int i;
5765
5766         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5767                 struct intel_crtc *other;
5768
5769                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5770                                                  crtc_state->bigjoiner_pipes) {
5771                         int ret;
5772
5773                         if (crtc == other)
5774                                 continue;
5775
5776                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5777                         if (ret)
5778                                 return ret;
5779                 }
5780         }
5781
5782         return 0;
5783 }
5784
5785 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5786 {
5787         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5788         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5789         struct intel_plane_state __maybe_unused *plane_state;
5790         struct intel_plane *plane;
5791         struct intel_crtc *crtc;
5792         int i, ret;
5793
5794         ret = icl_add_linked_planes(state);
5795         if (ret)
5796                 return ret;
5797
5798         ret = intel_bigjoiner_add_affected_planes(state);
5799         if (ret)
5800                 return ret;
5801
5802         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5803                 ret = intel_plane_atomic_check(state, plane);
5804                 if (ret) {
5805                         drm_dbg_atomic(&dev_priv->drm,
5806                                        "[PLANE:%d:%s] atomic driver check failed\n",
5807                                        plane->base.base.id, plane->base.name);
5808                         return ret;
5809                 }
5810         }
5811
5812         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5813                                             new_crtc_state, i) {
5814                 u8 old_active_planes, new_active_planes;
5815
5816                 ret = icl_check_nv12_planes(new_crtc_state);
5817                 if (ret)
5818                         return ret;
5819
5820                 /*
5821                  * On some platforms the number of active planes affects
5822                  * the planes' minimum cdclk calculation. Add such planes
5823                  * to the state before we compute the minimum cdclk.
5824                  */
5825                 if (!active_planes_affects_min_cdclk(dev_priv))
5826                         continue;
5827
5828                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5829                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5830
5831                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5832                         continue;
5833
5834                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5835                 if (ret)
5836                         return ret;
5837         }
5838
5839         return 0;
5840 }
5841
5842 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5843 {
5844         struct intel_crtc_state __maybe_unused *crtc_state;
5845         struct intel_crtc *crtc;
5846         int i;
5847
5848         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5849                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5850                 int ret;
5851
5852                 ret = intel_crtc_atomic_check(state, crtc);
5853                 if (ret) {
5854                         drm_dbg_atomic(&i915->drm,
5855                                        "[CRTC:%d:%s] atomic driver check failed\n",
5856                                        crtc->base.base.id, crtc->base.name);
5857                         return ret;
5858                 }
5859         }
5860
5861         return 0;
5862 }
5863
5864 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5865                                                u8 transcoders)
5866 {
5867         const struct intel_crtc_state *new_crtc_state;
5868         struct intel_crtc *crtc;
5869         int i;
5870
5871         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5872                 if (new_crtc_state->hw.enable &&
5873                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5874                     intel_crtc_needs_modeset(new_crtc_state))
5875                         return true;
5876         }
5877
5878         return false;
5879 }
5880
5881 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5882                                      u8 pipes)
5883 {
5884         const struct intel_crtc_state *new_crtc_state;
5885         struct intel_crtc *crtc;
5886         int i;
5887
5888         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5889                 if (new_crtc_state->hw.enable &&
5890                     pipes & BIT(crtc->pipe) &&
5891                     intel_crtc_needs_modeset(new_crtc_state))
5892                         return true;
5893         }
5894
5895         return false;
5896 }
5897
5898 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5899                                         struct intel_crtc *master_crtc)
5900 {
5901         struct drm_i915_private *i915 = to_i915(state->base.dev);
5902         struct intel_crtc_state *master_crtc_state =
5903                 intel_atomic_get_new_crtc_state(state, master_crtc);
5904         struct intel_crtc *slave_crtc;
5905
5906         if (!master_crtc_state->bigjoiner_pipes)
5907                 return 0;
5908
5909         /* sanity check */
5910         if (drm_WARN_ON(&i915->drm,
5911                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5912                 return -EINVAL;
5913
5914         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5915                 drm_dbg_kms(&i915->drm,
5916                             "[CRTC:%d:%s] Cannot act as big joiner master "
5917                             "(need 0x%x as pipes, only 0x%x possible)\n",
5918                             master_crtc->base.base.id, master_crtc->base.name,
5919                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5920                 return -EINVAL;
5921         }
5922
5923         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5924                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5925                 struct intel_crtc_state *slave_crtc_state;
5926                 int ret;
5927
5928                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5929                 if (IS_ERR(slave_crtc_state))
5930                         return PTR_ERR(slave_crtc_state);
5931
5932                 /* master being enabled, slave was already configured? */
5933                 if (slave_crtc_state->uapi.enable) {
5934                         drm_dbg_kms(&i915->drm,
5935                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5936                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5937                                     slave_crtc->base.base.id, slave_crtc->base.name,
5938                                     master_crtc->base.base.id, master_crtc->base.name);
5939                         return -EINVAL;
5940                 }
5941
5942                 /*
5943                  * The state copy logic assumes the master crtc gets processed
5944                  * before the slave crtc during the main compute_config loop.
5945                  * This works because the crtcs are created in pipe order,
5946                  * and the hardware requires master pipe < slave pipe as well.
5947                  * Should that change we need to rethink the logic.
5948                  */
5949                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5950                             drm_crtc_index(&slave_crtc->base)))
5951                         return -EINVAL;
5952
5953                 drm_dbg_kms(&i915->drm,
5954                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5955                             slave_crtc->base.base.id, slave_crtc->base.name,
5956                             master_crtc->base.base.id, master_crtc->base.name);
5957
5958                 slave_crtc_state->bigjoiner_pipes =
5959                         master_crtc_state->bigjoiner_pipes;
5960
5961                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5962                 if (ret)
5963                         return ret;
5964         }
5965
5966         return 0;
5967 }
5968
5969 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5970                                  struct intel_crtc *master_crtc)
5971 {
5972         struct drm_i915_private *i915 = to_i915(state->base.dev);
5973         struct intel_crtc_state *master_crtc_state =
5974                 intel_atomic_get_new_crtc_state(state, master_crtc);
5975         struct intel_crtc *slave_crtc;
5976
5977         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5978                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5979                 struct intel_crtc_state *slave_crtc_state =
5980                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5981
5982                 slave_crtc_state->bigjoiner_pipes = 0;
5983
5984                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5985         }
5986
5987         master_crtc_state->bigjoiner_pipes = 0;
5988 }
5989
5990 /**
5991  * DOC: asynchronous flip implementation
5992  *
5993  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5994  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5995  * Correspondingly, support is currently added for primary plane only.
5996  *
5997  * Async flip can only change the plane surface address, so anything else
5998  * changing is rejected from the intel_async_flip_check_hw() function.
5999  * Once this check is cleared, flip done interrupt is enabled using
6000  * the intel_crtc_enable_flip_done() function.
6001  *
6002  * As soon as the surface address register is written, flip done interrupt is
6003  * generated and the requested events are sent to the usersapce in the interrupt
6004  * handler itself. The timestamp and sequence sent during the flip done event
6005  * correspond to the last vblank and have no relation to the actual time when
6006  * the flip done event was sent.
6007  */
6008 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6009                                        struct intel_crtc *crtc)
6010 {
6011         struct drm_i915_private *i915 = to_i915(state->base.dev);
6012         const struct intel_crtc_state *new_crtc_state =
6013                 intel_atomic_get_new_crtc_state(state, crtc);
6014         const struct intel_plane_state *old_plane_state;
6015         struct intel_plane_state *new_plane_state;
6016         struct intel_plane *plane;
6017         int i;
6018
6019         if (!new_crtc_state->uapi.async_flip)
6020                 return 0;
6021
6022         if (!new_crtc_state->uapi.active) {
6023                 drm_dbg_kms(&i915->drm,
6024                             "[CRTC:%d:%s] not active\n",
6025                             crtc->base.base.id, crtc->base.name);
6026                 return -EINVAL;
6027         }
6028
6029         if (intel_crtc_needs_modeset(new_crtc_state)) {
6030                 drm_dbg_kms(&i915->drm,
6031                             "[CRTC:%d:%s] modeset required\n",
6032                             crtc->base.base.id, crtc->base.name);
6033                 return -EINVAL;
6034         }
6035
6036         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6037                                              new_plane_state, i) {
6038                 if (plane->pipe != crtc->pipe)
6039                         continue;
6040
6041                 /*
6042                  * TODO: Async flip is only supported through the page flip IOCTL
6043                  * as of now. So support currently added for primary plane only.
6044                  * Support for other planes on platforms on which supports
6045                  * this(vlv/chv and icl+) should be added when async flip is
6046                  * enabled in the atomic IOCTL path.
6047                  */
6048                 if (!plane->async_flip) {
6049                         drm_dbg_kms(&i915->drm,
6050                                     "[PLANE:%d:%s] async flip not supported\n",
6051                                     plane->base.base.id, plane->base.name);
6052                         return -EINVAL;
6053                 }
6054
6055                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6056                         drm_dbg_kms(&i915->drm,
6057                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6058                                     plane->base.base.id, plane->base.name);
6059                         return -EINVAL;
6060                 }
6061         }
6062
6063         return 0;
6064 }
6065
6066 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6067 {
6068         struct drm_i915_private *i915 = to_i915(state->base.dev);
6069         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6070         const struct intel_plane_state *new_plane_state, *old_plane_state;
6071         struct intel_plane *plane;
6072         int i;
6073
6074         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6075         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6076
6077         if (!new_crtc_state->uapi.async_flip)
6078                 return 0;
6079
6080         if (!new_crtc_state->hw.active) {
6081                 drm_dbg_kms(&i915->drm,
6082                             "[CRTC:%d:%s] not active\n",
6083                             crtc->base.base.id, crtc->base.name);
6084                 return -EINVAL;
6085         }
6086
6087         if (intel_crtc_needs_modeset(new_crtc_state)) {
6088                 drm_dbg_kms(&i915->drm,
6089                             "[CRTC:%d:%s] modeset required\n",
6090                             crtc->base.base.id, crtc->base.name);
6091                 return -EINVAL;
6092         }
6093
6094         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6095                 drm_dbg_kms(&i915->drm,
6096                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6097                             crtc->base.base.id, crtc->base.name);
6098                 return -EINVAL;
6099         }
6100
6101         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6102                                              new_plane_state, i) {
6103                 if (plane->pipe != crtc->pipe)
6104                         continue;
6105
6106                 /*
6107                  * Only async flip capable planes should be in the state
6108                  * if we're really about to ask the hardware to perform
6109                  * an async flip. We should never get this far otherwise.
6110                  */
6111                 if (drm_WARN_ON(&i915->drm,
6112                                 new_crtc_state->do_async_flip && !plane->async_flip))
6113                         return -EINVAL;
6114
6115                 /*
6116                  * Only check async flip capable planes other planes
6117                  * may be involved in the initial commit due to
6118                  * the wm0/ddb optimization.
6119                  *
6120                  * TODO maybe should track which planes actually
6121                  * were requested to do the async flip...
6122                  */
6123                 if (!plane->async_flip)
6124                         continue;
6125
6126                 /*
6127                  * FIXME: This check is kept generic for all platforms.
6128                  * Need to verify this for all gen9 platforms to enable
6129                  * this selectively if required.
6130                  */
6131                 switch (new_plane_state->hw.fb->modifier) {
6132                 case DRM_FORMAT_MOD_LINEAR:
6133                         /*
6134                          * FIXME: Async on Linear buffer is supported on ICL as
6135                          * but with additional alignment and fbc restrictions
6136                          * need to be taken care of. These aren't applicable for
6137                          * gen12+.
6138                          */
6139                         if (DISPLAY_VER(i915) < 12) {
6140                                 drm_dbg_kms(&i915->drm,
6141                                             "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6142                                             plane->base.base.id, plane->base.name,
6143                                             new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6144                                 return -EINVAL;
6145                         }
6146                         break;
6147
6148                 case I915_FORMAT_MOD_X_TILED:
6149                 case I915_FORMAT_MOD_Y_TILED:
6150                 case I915_FORMAT_MOD_Yf_TILED:
6151                 case I915_FORMAT_MOD_4_TILED:
6152                         break;
6153                 default:
6154                         drm_dbg_kms(&i915->drm,
6155                                     "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6156                                     plane->base.base.id, plane->base.name,
6157                                     new_plane_state->hw.fb->modifier);
6158                         return -EINVAL;
6159                 }
6160
6161                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6162                         drm_dbg_kms(&i915->drm,
6163                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6164                                     plane->base.base.id, plane->base.name);
6165                         return -EINVAL;
6166                 }
6167
6168                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6169                     new_plane_state->view.color_plane[0].mapping_stride) {
6170                         drm_dbg_kms(&i915->drm,
6171                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6172                                     plane->base.base.id, plane->base.name);
6173                         return -EINVAL;
6174                 }
6175
6176                 if (old_plane_state->hw.fb->modifier !=
6177                     new_plane_state->hw.fb->modifier) {
6178                         drm_dbg_kms(&i915->drm,
6179                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6180                                     plane->base.base.id, plane->base.name);
6181                         return -EINVAL;
6182                 }
6183
6184                 if (old_plane_state->hw.fb->format !=
6185                     new_plane_state->hw.fb->format) {
6186                         drm_dbg_kms(&i915->drm,
6187                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6188                                     plane->base.base.id, plane->base.name);
6189                         return -EINVAL;
6190                 }
6191
6192                 if (old_plane_state->hw.rotation !=
6193                     new_plane_state->hw.rotation) {
6194                         drm_dbg_kms(&i915->drm,
6195                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6196                                     plane->base.base.id, plane->base.name);
6197                         return -EINVAL;
6198                 }
6199
6200                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6201                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6202                         drm_dbg_kms(&i915->drm,
6203                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6204                                     plane->base.base.id, plane->base.name);
6205                         return -EINVAL;
6206                 }
6207
6208                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6209                         drm_dbg_kms(&i915->drm,
6210                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6211                                     plane->base.base.id, plane->base.name);
6212                         return -EINVAL;
6213                 }
6214
6215                 if (old_plane_state->hw.pixel_blend_mode !=
6216                     new_plane_state->hw.pixel_blend_mode) {
6217                         drm_dbg_kms(&i915->drm,
6218                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6219                                     plane->base.base.id, plane->base.name);
6220                         return -EINVAL;
6221                 }
6222
6223                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6224                         drm_dbg_kms(&i915->drm,
6225                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6226                                     plane->base.base.id, plane->base.name);
6227                         return -EINVAL;
6228                 }
6229
6230                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6231                         drm_dbg_kms(&i915->drm,
6232                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6233                                     plane->base.base.id, plane->base.name);
6234                         return -EINVAL;
6235                 }
6236
6237                 /* plane decryption is allow to change only in synchronous flips */
6238                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6239                         drm_dbg_kms(&i915->drm,
6240                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6241                                     plane->base.base.id, plane->base.name);
6242                         return -EINVAL;
6243                 }
6244         }
6245
6246         return 0;
6247 }
6248
6249 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6250 {
6251         struct drm_i915_private *i915 = to_i915(state->base.dev);
6252         struct intel_crtc_state *crtc_state;
6253         struct intel_crtc *crtc;
6254         u8 affected_pipes = 0;
6255         u8 modeset_pipes = 0;
6256         int i;
6257
6258         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6259                 affected_pipes |= crtc_state->bigjoiner_pipes;
6260                 if (intel_crtc_needs_modeset(crtc_state))
6261                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6262         }
6263
6264         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6265                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6266                 if (IS_ERR(crtc_state))
6267                         return PTR_ERR(crtc_state);
6268         }
6269
6270         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6271                 int ret;
6272
6273                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6274
6275                 crtc_state->uapi.mode_changed = true;
6276
6277                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6278                 if (ret)
6279                         return ret;
6280
6281                 ret = intel_atomic_add_affected_planes(state, crtc);
6282                 if (ret)
6283                         return ret;
6284         }
6285
6286         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6287                 /* Kill old bigjoiner link, we may re-establish afterwards */
6288                 if (intel_crtc_needs_modeset(crtc_state) &&
6289                     intel_crtc_is_bigjoiner_master(crtc_state))
6290                         kill_bigjoiner_slave(state, crtc);
6291         }
6292
6293         return 0;
6294 }
6295
6296 static int intel_atomic_check_config(struct intel_atomic_state *state,
6297                                      struct intel_link_bw_limits *limits,
6298                                      enum pipe *failed_pipe)
6299 {
6300         struct drm_i915_private *i915 = to_i915(state->base.dev);
6301         struct intel_crtc_state *new_crtc_state;
6302         struct intel_crtc *crtc;
6303         int ret;
6304         int i;
6305
6306         *failed_pipe = INVALID_PIPE;
6307
6308         ret = intel_bigjoiner_add_affected_crtcs(state);
6309         if (ret)
6310                 return ret;
6311
6312         ret = intel_fdi_add_affected_crtcs(state);
6313         if (ret)
6314                 return ret;
6315
6316         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6317                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6318                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6319                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6320                         else
6321                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6322                         continue;
6323                 }
6324
6325                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6326                         drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
6327                         continue;
6328                 }
6329
6330                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6331                 if (ret)
6332                         break;
6333
6334                 if (!new_crtc_state->hw.enable)
6335                         continue;
6336
6337                 ret = intel_modeset_pipe_config(state, crtc, limits);
6338                 if (ret)
6339                         break;
6340
6341                 ret = intel_atomic_check_bigjoiner(state, crtc);
6342                 if (ret)
6343                         break;
6344         }
6345
6346         if (ret)
6347                 *failed_pipe = crtc->pipe;
6348
6349         return ret;
6350 }
6351
6352 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6353 {
6354         struct drm_i915_private *i915 = to_i915(state->base.dev);
6355         struct intel_link_bw_limits new_limits;
6356         struct intel_link_bw_limits old_limits;
6357         int ret;
6358
6359         intel_link_bw_init_limits(i915, &new_limits);
6360         old_limits = new_limits;
6361
6362         while (true) {
6363                 enum pipe failed_pipe;
6364
6365                 ret = intel_atomic_check_config(state, &new_limits,
6366                                                 &failed_pipe);
6367                 if (ret) {
6368                         /*
6369                          * The bpp limit for a pipe is below the minimum it supports, set the
6370                          * limit to the minimum and recalculate the config.
6371                          */
6372                         if (ret == -EINVAL &&
6373                             intel_link_bw_set_bpp_limit_for_pipe(state,
6374                                                                  &old_limits,
6375                                                                  &new_limits,
6376                                                                  failed_pipe))
6377                                 continue;
6378
6379                         break;
6380                 }
6381
6382                 old_limits = new_limits;
6383
6384                 ret = intel_link_bw_atomic_check(state, &new_limits);
6385                 if (ret != -EAGAIN)
6386                         break;
6387         }
6388
6389         return ret;
6390 }
6391 /**
6392  * intel_atomic_check - validate state object
6393  * @dev: drm device
6394  * @_state: state to validate
6395  */
6396 int intel_atomic_check(struct drm_device *dev,
6397                        struct drm_atomic_state *_state)
6398 {
6399         struct drm_i915_private *dev_priv = to_i915(dev);
6400         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6401         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6402         struct intel_crtc *crtc;
6403         int ret, i;
6404         bool any_ms = false;
6405
6406         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6407                                             new_crtc_state, i) {
6408                 /*
6409                  * crtc's state no longer considered to be inherited
6410                  * after the first userspace/client initiated commit.
6411                  */
6412                 if (!state->internal)
6413                         new_crtc_state->inherited = false;
6414
6415                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6416                         new_crtc_state->uapi.mode_changed = true;
6417
6418                 if (new_crtc_state->uapi.scaling_filter !=
6419                     old_crtc_state->uapi.scaling_filter)
6420                         new_crtc_state->uapi.mode_changed = true;
6421         }
6422
6423         intel_vrr_check_modeset(state);
6424
6425         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6426         if (ret)
6427                 goto fail;
6428
6429         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6430                 ret = intel_async_flip_check_uapi(state, crtc);
6431                 if (ret)
6432                         return ret;
6433         }
6434
6435         ret = intel_atomic_check_config_and_link(state);
6436         if (ret)
6437                 goto fail;
6438
6439         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6440                                             new_crtc_state, i) {
6441                 if (!intel_crtc_needs_modeset(new_crtc_state))
6442                         continue;
6443
6444                 if (new_crtc_state->hw.enable) {
6445                         ret = intel_modeset_pipe_config_late(state, crtc);
6446                         if (ret)
6447                                 goto fail;
6448                 }
6449
6450                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6451         }
6452
6453         /**
6454          * Check if fastset is allowed by external dependencies like other
6455          * pipes and transcoders.
6456          *
6457          * Right now it only forces a fullmodeset when the MST master
6458          * transcoder did not changed but the pipe of the master transcoder
6459          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6460          * in case of port synced crtcs, if one of the synced crtcs
6461          * needs a full modeset, all other synced crtcs should be
6462          * forced a full modeset.
6463          */
6464         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6465                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6466                         continue;
6467
6468                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6469                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6470
6471                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6472                                 new_crtc_state->uapi.mode_changed = true;
6473                                 new_crtc_state->update_pipe = false;
6474                                 new_crtc_state->update_m_n = false;
6475                                 new_crtc_state->update_lrr = false;
6476                         }
6477                 }
6478
6479                 if (is_trans_port_sync_mode(new_crtc_state)) {
6480                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6481
6482                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6483                                 trans |= BIT(new_crtc_state->master_transcoder);
6484
6485                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6486                                 new_crtc_state->uapi.mode_changed = true;
6487                                 new_crtc_state->update_pipe = false;
6488                                 new_crtc_state->update_m_n = false;
6489                                 new_crtc_state->update_lrr = false;
6490                         }
6491                 }
6492
6493                 if (new_crtc_state->bigjoiner_pipes) {
6494                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6495                                 new_crtc_state->uapi.mode_changed = true;
6496                                 new_crtc_state->update_pipe = false;
6497                                 new_crtc_state->update_m_n = false;
6498                                 new_crtc_state->update_lrr = false;
6499                         }
6500                 }
6501         }
6502
6503         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6504                                             new_crtc_state, i) {
6505                 if (!intel_crtc_needs_modeset(new_crtc_state))
6506                         continue;
6507
6508                 any_ms = true;
6509
6510                 intel_release_shared_dplls(state, crtc);
6511         }
6512
6513         if (any_ms && !check_digital_port_conflicts(state)) {
6514                 drm_dbg_kms(&dev_priv->drm,
6515                             "rejecting conflicting digital port configuration\n");
6516                 ret = -EINVAL;
6517                 goto fail;
6518         }
6519
6520         ret = drm_dp_mst_atomic_check(&state->base);
6521         if (ret)
6522                 goto fail;
6523
6524         ret = intel_atomic_check_planes(state);
6525         if (ret)
6526                 goto fail;
6527
6528         ret = intel_compute_global_watermarks(state);
6529         if (ret)
6530                 goto fail;
6531
6532         ret = intel_bw_atomic_check(state);
6533         if (ret)
6534                 goto fail;
6535
6536         ret = intel_cdclk_atomic_check(state, &any_ms);
6537         if (ret)
6538                 goto fail;
6539
6540         if (intel_any_crtc_needs_modeset(state))
6541                 any_ms = true;
6542
6543         if (any_ms) {
6544                 ret = intel_modeset_checks(state);
6545                 if (ret)
6546                         goto fail;
6547
6548                 ret = intel_modeset_calc_cdclk(state);
6549                 if (ret)
6550                         return ret;
6551         }
6552
6553         ret = intel_pmdemand_atomic_check(state);
6554         if (ret)
6555                 goto fail;
6556
6557         ret = intel_atomic_check_crtcs(state);
6558         if (ret)
6559                 goto fail;
6560
6561         ret = intel_fbc_atomic_check(state);
6562         if (ret)
6563                 goto fail;
6564
6565         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6566                                             new_crtc_state, i) {
6567                 intel_color_assert_luts(new_crtc_state);
6568
6569                 ret = intel_async_flip_check_hw(state, crtc);
6570                 if (ret)
6571                         goto fail;
6572
6573                 /* Either full modeset or fastset (or neither), never both */
6574                 drm_WARN_ON(&dev_priv->drm,
6575                             intel_crtc_needs_modeset(new_crtc_state) &&
6576                             intel_crtc_needs_fastset(new_crtc_state));
6577
6578                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6579                     !intel_crtc_needs_fastset(new_crtc_state))
6580                         continue;
6581
6582                 intel_crtc_state_dump(new_crtc_state, state,
6583                                       intel_crtc_needs_modeset(new_crtc_state) ?
6584                                       "modeset" : "fastset");
6585         }
6586
6587         return 0;
6588
6589  fail:
6590         if (ret == -EDEADLK)
6591                 return ret;
6592
6593         /*
6594          * FIXME would probably be nice to know which crtc specifically
6595          * caused the failure, in cases where we can pinpoint it.
6596          */
6597         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6598                                             new_crtc_state, i)
6599                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6600
6601         return ret;
6602 }
6603
6604 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6605 {
6606         struct intel_crtc_state *crtc_state;
6607         struct intel_crtc *crtc;
6608         int i, ret;
6609
6610         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6611         if (ret < 0)
6612                 return ret;
6613
6614         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6615                 if (intel_crtc_needs_color_update(crtc_state))
6616                         intel_color_prepare_commit(crtc_state);
6617         }
6618
6619         return 0;
6620 }
6621
6622 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6623                                   struct intel_crtc_state *crtc_state)
6624 {
6625         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6626
6627         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6628                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6629
6630         if (crtc_state->has_pch_encoder) {
6631                 enum pipe pch_transcoder =
6632                         intel_crtc_pch_transcoder(crtc);
6633
6634                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6635         }
6636 }
6637
6638 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6639                                const struct intel_crtc_state *new_crtc_state)
6640 {
6641         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6642         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6643
6644         /*
6645          * Update pipe size and adjust fitter if needed: the reason for this is
6646          * that in compute_mode_changes we check the native mode (not the pfit
6647          * mode) to see if we can flip rather than do a full mode set. In the
6648          * fastboot case, we'll flip, but if we don't update the pipesrc and
6649          * pfit state, we'll end up with a big fb scanned out into the wrong
6650          * sized surface.
6651          */
6652         intel_set_pipe_src_size(new_crtc_state);
6653
6654         /* on skylake this is done by detaching scalers */
6655         if (DISPLAY_VER(dev_priv) >= 9) {
6656                 if (new_crtc_state->pch_pfit.enabled)
6657                         skl_pfit_enable(new_crtc_state);
6658         } else if (HAS_PCH_SPLIT(dev_priv)) {
6659                 if (new_crtc_state->pch_pfit.enabled)
6660                         ilk_pfit_enable(new_crtc_state);
6661                 else if (old_crtc_state->pch_pfit.enabled)
6662                         ilk_pfit_disable(old_crtc_state);
6663         }
6664
6665         /*
6666          * The register is supposedly single buffered so perhaps
6667          * not 100% correct to do this here. But SKL+ calculate
6668          * this based on the adjust pixel rate so pfit changes do
6669          * affect it and so it must be updated for fastsets.
6670          * HSW/BDW only really need this here for fastboot, after
6671          * that the value should not change without a full modeset.
6672          */
6673         if (DISPLAY_VER(dev_priv) >= 9 ||
6674             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6675                 hsw_set_linetime_wm(new_crtc_state);
6676
6677         if (new_crtc_state->update_m_n)
6678                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6679                                                &new_crtc_state->dp_m_n);
6680
6681         if (new_crtc_state->update_lrr)
6682                 intel_set_transcoder_timings_lrr(new_crtc_state);
6683 }
6684
6685 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6686                                    struct intel_crtc *crtc)
6687 {
6688         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6689         const struct intel_crtc_state *old_crtc_state =
6690                 intel_atomic_get_old_crtc_state(state, crtc);
6691         const struct intel_crtc_state *new_crtc_state =
6692                 intel_atomic_get_new_crtc_state(state, crtc);
6693         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6694
6695         /*
6696          * During modesets pipe configuration was programmed as the
6697          * CRTC was enabled.
6698          */
6699         if (!modeset) {
6700                 if (intel_crtc_needs_color_update(new_crtc_state))
6701                         intel_color_commit_arm(new_crtc_state);
6702
6703                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6704                         bdw_set_pipe_misc(new_crtc_state);
6705
6706                 if (intel_crtc_needs_fastset(new_crtc_state))
6707                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6708         }
6709
6710         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6711
6712         intel_atomic_update_watermarks(state, crtc);
6713 }
6714
6715 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6716                                     struct intel_crtc *crtc)
6717 {
6718         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6719         const struct intel_crtc_state *old_crtc_state =
6720                 intel_atomic_get_old_crtc_state(state, crtc);
6721         const struct intel_crtc_state *new_crtc_state =
6722                 intel_atomic_get_new_crtc_state(state, crtc);
6723
6724         /*
6725          * Disable the scaler(s) after the plane(s) so that we don't
6726          * get a catastrophic underrun even if the two operations
6727          * end up happening in two different frames.
6728          */
6729         if (DISPLAY_VER(dev_priv) >= 9 &&
6730             !intel_crtc_needs_modeset(new_crtc_state))
6731                 skl_detach_scalers(new_crtc_state);
6732
6733         if (vrr_enabling(old_crtc_state, new_crtc_state))
6734                 intel_vrr_enable(new_crtc_state);
6735 }
6736
6737 static void intel_enable_crtc(struct intel_atomic_state *state,
6738                               struct intel_crtc *crtc)
6739 {
6740         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6741         const struct intel_crtc_state *new_crtc_state =
6742                 intel_atomic_get_new_crtc_state(state, crtc);
6743
6744         if (!intel_crtc_needs_modeset(new_crtc_state))
6745                 return;
6746
6747         /* VRR will be enable later, if required */
6748         intel_crtc_update_active_timings(new_crtc_state, false);
6749
6750         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6751
6752         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6753                 return;
6754
6755         /* vblanks work again, re-enable pipe CRC. */
6756         intel_crtc_enable_pipe_crc(crtc);
6757 }
6758
6759 static void intel_update_crtc(struct intel_atomic_state *state,
6760                               struct intel_crtc *crtc)
6761 {
6762         struct drm_i915_private *i915 = to_i915(state->base.dev);
6763         const struct intel_crtc_state *old_crtc_state =
6764                 intel_atomic_get_old_crtc_state(state, crtc);
6765         struct intel_crtc_state *new_crtc_state =
6766                 intel_atomic_get_new_crtc_state(state, crtc);
6767         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6768
6769         if (old_crtc_state->inherited ||
6770             intel_crtc_needs_modeset(new_crtc_state)) {
6771                 if (HAS_DPT(i915))
6772                         intel_dpt_configure(crtc);
6773         }
6774
6775         if (!modeset) {
6776                 if (new_crtc_state->preload_luts &&
6777                     intel_crtc_needs_color_update(new_crtc_state))
6778                         intel_color_load_luts(new_crtc_state);
6779
6780                 intel_pre_plane_update(state, crtc);
6781
6782                 if (intel_crtc_needs_fastset(new_crtc_state))
6783                         intel_encoders_update_pipe(state, crtc);
6784
6785                 if (DISPLAY_VER(i915) >= 11 &&
6786                     intel_crtc_needs_fastset(new_crtc_state))
6787                         icl_set_pipe_chicken(new_crtc_state);
6788
6789                 if (vrr_params_changed(old_crtc_state, new_crtc_state))
6790                         intel_vrr_set_transcoder_timings(new_crtc_state);
6791         }
6792
6793         intel_fbc_update(state, crtc);
6794
6795         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6796
6797         if (!modeset &&
6798             intel_crtc_needs_color_update(new_crtc_state))
6799                 intel_color_commit_noarm(new_crtc_state);
6800
6801         intel_crtc_planes_update_noarm(state, crtc);
6802
6803         /* Perform vblank evasion around commit operation */
6804         intel_pipe_update_start(state, crtc);
6805
6806         commit_pipe_pre_planes(state, crtc);
6807
6808         intel_crtc_planes_update_arm(state, crtc);
6809
6810         commit_pipe_post_planes(state, crtc);
6811
6812         intel_pipe_update_end(state, crtc);
6813
6814         /*
6815          * VRR/Seamless M/N update may need to update frame timings.
6816          *
6817          * FIXME Should be synchronized with the start of vblank somehow...
6818          */
6819         if (vrr_enabling(old_crtc_state, new_crtc_state) ||
6820             new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6821                 intel_crtc_update_active_timings(new_crtc_state,
6822                                                  new_crtc_state->vrr.enable);
6823
6824         /*
6825          * We usually enable FIFO underrun interrupts as part of the
6826          * CRTC enable sequence during modesets.  But when we inherit a
6827          * valid pipe configuration from the BIOS we need to take care
6828          * of enabling them on the CRTC's first fastset.
6829          */
6830         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6831             old_crtc_state->inherited)
6832                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6833 }
6834
6835 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6836                                           struct intel_crtc_state *old_crtc_state,
6837                                           struct intel_crtc_state *new_crtc_state,
6838                                           struct intel_crtc *crtc)
6839 {
6840         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6841
6842         /*
6843          * We need to disable pipe CRC before disabling the pipe,
6844          * or we race against vblank off.
6845          */
6846         intel_crtc_disable_pipe_crc(crtc);
6847
6848         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6849         crtc->active = false;
6850         intel_fbc_disable(crtc);
6851
6852         if (!new_crtc_state->hw.active)
6853                 intel_initial_watermarks(state, crtc);
6854 }
6855
6856 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6857 {
6858         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6859         struct intel_crtc *crtc;
6860         u32 handled = 0;
6861         int i;
6862
6863         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6864                                             new_crtc_state, i) {
6865                 if (!intel_crtc_needs_modeset(new_crtc_state))
6866                         continue;
6867
6868                 intel_pre_plane_update(state, crtc);
6869
6870                 if (!old_crtc_state->hw.active)
6871                         continue;
6872
6873                 intel_crtc_disable_planes(state, crtc);
6874         }
6875
6876         /* Only disable port sync and MST slaves */
6877         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6878                                             new_crtc_state, i) {
6879                 if (!intel_crtc_needs_modeset(new_crtc_state))
6880                         continue;
6881
6882                 if (!old_crtc_state->hw.active)
6883                         continue;
6884
6885                 /* In case of Transcoder port Sync master slave CRTCs can be
6886                  * assigned in any order and we need to make sure that
6887                  * slave CRTCs are disabled first and then master CRTC since
6888                  * Slave vblanks are masked till Master Vblanks.
6889                  */
6890                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6891                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
6892                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
6893                         continue;
6894
6895                 intel_old_crtc_state_disables(state, old_crtc_state,
6896                                               new_crtc_state, crtc);
6897                 handled |= BIT(crtc->pipe);
6898         }
6899
6900         /* Disable everything else left on */
6901         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6902                                             new_crtc_state, i) {
6903                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
6904                     (handled & BIT(crtc->pipe)))
6905                         continue;
6906
6907                 if (!old_crtc_state->hw.active)
6908                         continue;
6909
6910                 intel_old_crtc_state_disables(state, old_crtc_state,
6911                                               new_crtc_state, crtc);
6912         }
6913 }
6914
6915 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6916 {
6917         struct intel_crtc_state *new_crtc_state;
6918         struct intel_crtc *crtc;
6919         int i;
6920
6921         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6922                 if (!new_crtc_state->hw.active)
6923                         continue;
6924
6925                 intel_enable_crtc(state, crtc);
6926                 intel_update_crtc(state, crtc);
6927         }
6928 }
6929
6930 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6931 {
6932         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6933         struct intel_crtc *crtc;
6934         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6935         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6936         u8 update_pipes = 0, modeset_pipes = 0;
6937         int i;
6938
6939         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6940                 enum pipe pipe = crtc->pipe;
6941
6942                 if (!new_crtc_state->hw.active)
6943                         continue;
6944
6945                 /* ignore allocations for crtc's that have been turned off. */
6946                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6947                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6948                         update_pipes |= BIT(pipe);
6949                 } else {
6950                         modeset_pipes |= BIT(pipe);
6951                 }
6952         }
6953
6954         /*
6955          * Whenever the number of active pipes changes, we need to make sure we
6956          * update the pipes in the right order so that their ddb allocations
6957          * never overlap with each other between CRTC updates. Otherwise we'll
6958          * cause pipe underruns and other bad stuff.
6959          *
6960          * So first lets enable all pipes that do not need a fullmodeset as
6961          * those don't have any external dependency.
6962          */
6963         while (update_pipes) {
6964                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6965                                                     new_crtc_state, i) {
6966                         enum pipe pipe = crtc->pipe;
6967
6968                         if ((update_pipes & BIT(pipe)) == 0)
6969                                 continue;
6970
6971                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6972                                                         entries, I915_MAX_PIPES, pipe))
6973                                 continue;
6974
6975                         entries[pipe] = new_crtc_state->wm.skl.ddb;
6976                         update_pipes &= ~BIT(pipe);
6977
6978                         intel_update_crtc(state, crtc);
6979
6980                         /*
6981                          * If this is an already active pipe, it's DDB changed,
6982                          * and this isn't the last pipe that needs updating
6983                          * then we need to wait for a vblank to pass for the
6984                          * new ddb allocation to take effect.
6985                          */
6986                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6987                                                  &old_crtc_state->wm.skl.ddb) &&
6988                             (update_pipes | modeset_pipes))
6989                                 intel_crtc_wait_for_next_vblank(crtc);
6990                 }
6991         }
6992
6993         update_pipes = modeset_pipes;
6994
6995         /*
6996          * Enable all pipes that needs a modeset and do not depends on other
6997          * pipes
6998          */
6999         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7000                 enum pipe pipe = crtc->pipe;
7001
7002                 if ((modeset_pipes & BIT(pipe)) == 0)
7003                         continue;
7004
7005                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7006                     is_trans_port_sync_master(new_crtc_state) ||
7007                     intel_crtc_is_bigjoiner_master(new_crtc_state))
7008                         continue;
7009
7010                 modeset_pipes &= ~BIT(pipe);
7011
7012                 intel_enable_crtc(state, crtc);
7013         }
7014
7015         /*
7016          * Then we enable all remaining pipes that depend on other
7017          * pipes: MST slaves and port sync masters, big joiner master
7018          */
7019         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7020                 enum pipe pipe = crtc->pipe;
7021
7022                 if ((modeset_pipes & BIT(pipe)) == 0)
7023                         continue;
7024
7025                 modeset_pipes &= ~BIT(pipe);
7026
7027                 intel_enable_crtc(state, crtc);
7028         }
7029
7030         /*
7031          * Finally we do the plane updates/etc. for all pipes that got enabled.
7032          */
7033         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7034                 enum pipe pipe = crtc->pipe;
7035
7036                 if ((update_pipes & BIT(pipe)) == 0)
7037                         continue;
7038
7039                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7040                                                                         entries, I915_MAX_PIPES, pipe));
7041
7042                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7043                 update_pipes &= ~BIT(pipe);
7044
7045                 intel_update_crtc(state, crtc);
7046         }
7047
7048         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7049         drm_WARN_ON(&dev_priv->drm, update_pipes);
7050 }
7051
7052 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7053 {
7054         struct intel_atomic_state *state, *next;
7055         struct llist_node *freed;
7056
7057         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
7058         llist_for_each_entry_safe(state, next, freed, freed)
7059                 drm_atomic_state_put(&state->base);
7060 }
7061
7062 void intel_atomic_helper_free_state_worker(struct work_struct *work)
7063 {
7064         struct drm_i915_private *dev_priv =
7065                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
7066
7067         intel_atomic_helper_free_state(dev_priv);
7068 }
7069
7070 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7071 {
7072         struct wait_queue_entry wait_fence, wait_reset;
7073         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7074
7075         init_wait_entry(&wait_fence, 0);
7076         init_wait_entry(&wait_reset, 0);
7077         for (;;) {
7078                 prepare_to_wait(&intel_state->commit_ready.wait,
7079                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7080                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7081                                               I915_RESET_MODESET),
7082                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7083
7084
7085                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7086                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7087                         break;
7088
7089                 schedule();
7090         }
7091         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7092         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7093                                   I915_RESET_MODESET),
7094                     &wait_reset);
7095 }
7096
7097 static void intel_atomic_cleanup_work(struct work_struct *work)
7098 {
7099         struct intel_atomic_state *state =
7100                 container_of(work, struct intel_atomic_state, base.commit_work);
7101         struct drm_i915_private *i915 = to_i915(state->base.dev);
7102         struct intel_crtc_state *old_crtc_state;
7103         struct intel_crtc *crtc;
7104         int i;
7105
7106         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7107                 intel_color_cleanup_commit(old_crtc_state);
7108
7109         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7110         drm_atomic_helper_commit_cleanup_done(&state->base);
7111         drm_atomic_state_put(&state->base);
7112
7113         intel_atomic_helper_free_state(i915);
7114 }
7115
7116 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7117 {
7118         struct drm_i915_private *i915 = to_i915(state->base.dev);
7119         struct intel_plane *plane;
7120         struct intel_plane_state *plane_state;
7121         int i;
7122
7123         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7124                 struct drm_framebuffer *fb = plane_state->hw.fb;
7125                 int cc_plane;
7126                 int ret;
7127
7128                 if (!fb)
7129                         continue;
7130
7131                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7132                 if (cc_plane < 0)
7133                         continue;
7134
7135                 /*
7136                  * The layout of the fast clear color value expected by HW
7137                  * (the DRM ABI requiring this value to be located in fb at
7138                  * offset 0 of cc plane, plane #2 previous generations or
7139                  * plane #1 for flat ccs):
7140                  * - 4 x 4 bytes per-channel value
7141                  *   (in surface type specific float/int format provided by the fb user)
7142                  * - 8 bytes native color value used by the display
7143                  *   (converted/written by GPU during a fast clear operation using the
7144                  *    above per-channel values)
7145                  *
7146                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7147                  * caller made sure that the object is synced wrt. the related color clear value
7148                  * GPU write on it.
7149                  */
7150                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7151                                                      fb->offsets[cc_plane] + 16,
7152                                                      &plane_state->ccval,
7153                                                      sizeof(plane_state->ccval));
7154                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7155                 drm_WARN_ON(&i915->drm, ret);
7156         }
7157 }
7158
7159 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7160 {
7161         struct drm_device *dev = state->base.dev;
7162         struct drm_i915_private *dev_priv = to_i915(dev);
7163         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7164         struct intel_crtc *crtc;
7165         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7166         intel_wakeref_t wakeref = 0;
7167         int i;
7168
7169         intel_atomic_commit_fence_wait(state);
7170
7171         drm_atomic_helper_wait_for_dependencies(&state->base);
7172         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7173
7174         /*
7175          * During full modesets we write a lot of registers, wait
7176          * for PLLs, etc. Doing that while DC states are enabled
7177          * is not a good idea.
7178          *
7179          * During fastsets and other updates we also need to
7180          * disable DC states due to the following scenario:
7181          * 1. DC5 exit and PSR exit happen
7182          * 2. Some or all _noarm() registers are written
7183          * 3. Due to some long delay PSR is re-entered
7184          * 4. DC5 entry -> DMC saves the already written new
7185          *    _noarm() registers and the old not yet written
7186          *    _arm() registers
7187          * 5. DC5 exit -> DMC restores a mixture of old and
7188          *    new register values and arms the update
7189          * 6. PSR exit -> hardware latches a mixture of old and
7190          *    new register values -> corrupted frame, or worse
7191          * 7. New _arm() registers are finally written
7192          * 8. Hardware finally latches a complete set of new
7193          *    register values, and subsequent frames will be OK again
7194          *
7195          * Also note that due to the pipe CSC hardware issues on
7196          * SKL/GLK DC states must remain off until the pipe CSC
7197          * state readout has happened. Otherwise we risk corrupting
7198          * the CSC latched register values with the readout (see
7199          * skl_read_csc() and skl_color_commit_noarm()).
7200          */
7201         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7202
7203         intel_atomic_prepare_plane_clear_colors(state);
7204
7205         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7206                                             new_crtc_state, i) {
7207                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7208                     intel_crtc_needs_fastset(new_crtc_state))
7209                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7210         }
7211
7212         intel_commit_modeset_disables(state);
7213
7214         /* FIXME: Eventually get rid of our crtc->config pointer */
7215         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7216                 crtc->config = new_crtc_state;
7217
7218         /*
7219          * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7220          * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7221          * index, cdclk/ddiclk frequencies are supposed to be configured before
7222          * the cdclk config is set.
7223          */
7224         intel_pmdemand_pre_plane_update(state);
7225
7226         if (state->modeset) {
7227                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7228
7229                 intel_set_cdclk_pre_plane_update(state);
7230
7231                 intel_modeset_verify_disabled(state);
7232         }
7233
7234         intel_sagv_pre_plane_update(state);
7235
7236         /* Complete the events for pipes that have now been disabled */
7237         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7238                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7239
7240                 /* Complete events for now disable pipes here. */
7241                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7242                         spin_lock_irq(&dev->event_lock);
7243                         drm_crtc_send_vblank_event(&crtc->base,
7244                                                    new_crtc_state->uapi.event);
7245                         spin_unlock_irq(&dev->event_lock);
7246
7247                         new_crtc_state->uapi.event = NULL;
7248                 }
7249         }
7250
7251         intel_encoders_update_prepare(state);
7252
7253         intel_dbuf_pre_plane_update(state);
7254         intel_mbus_dbox_update(state);
7255
7256         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7257                 if (new_crtc_state->do_async_flip)
7258                         intel_crtc_enable_flip_done(state, crtc);
7259         }
7260
7261         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7262         dev_priv->display.funcs.display->commit_modeset_enables(state);
7263
7264         if (state->modeset)
7265                 intel_set_cdclk_post_plane_update(state);
7266
7267         intel_wait_for_vblank_workers(state);
7268
7269         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7270          * already, but still need the state for the delayed optimization. To
7271          * fix this:
7272          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7273          * - schedule that vblank worker _before_ calling hw_done
7274          * - at the start of commit_tail, cancel it _synchrously
7275          * - switch over to the vblank wait helper in the core after that since
7276          *   we don't need out special handling any more.
7277          */
7278         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7279
7280         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7281                 if (new_crtc_state->do_async_flip)
7282                         intel_crtc_disable_flip_done(state, crtc);
7283
7284                 intel_color_wait_commit(new_crtc_state);
7285         }
7286
7287         /*
7288          * Now that the vblank has passed, we can go ahead and program the
7289          * optimal watermarks on platforms that need two-step watermark
7290          * programming.
7291          *
7292          * TODO: Move this (and other cleanup) to an async worker eventually.
7293          */
7294         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7295                                             new_crtc_state, i) {
7296                 /*
7297                  * Gen2 reports pipe underruns whenever all planes are disabled.
7298                  * So re-enable underrun reporting after some planes get enabled.
7299                  *
7300                  * We do this before .optimize_watermarks() so that we have a
7301                  * chance of catching underruns with the intermediate watermarks
7302                  * vs. the new plane configuration.
7303                  */
7304                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7305                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7306
7307                 intel_optimize_watermarks(state, crtc);
7308         }
7309
7310         intel_dbuf_post_plane_update(state);
7311
7312         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7313                 intel_post_plane_update(state, crtc);
7314
7315                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7316
7317                 intel_modeset_verify_crtc(state, crtc);
7318
7319                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7320                 hsw_ips_post_update(state, crtc);
7321
7322                 /*
7323                  * Activate DRRS after state readout to avoid
7324                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7325                  */
7326                 intel_drrs_activate(new_crtc_state);
7327
7328                 /*
7329                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7330                  * cleanup. So copy and reset the dsb structure to sync with
7331                  * commit_done and later do dsb cleanup in cleanup_work.
7332                  *
7333                  * FIXME get rid of this funny new->old swapping
7334                  */
7335                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7336         }
7337
7338         /* Underruns don't always raise interrupts, so check manually */
7339         intel_check_cpu_fifo_underruns(dev_priv);
7340         intel_check_pch_fifo_underruns(dev_priv);
7341
7342         if (state->modeset)
7343                 intel_verify_planes(state);
7344
7345         intel_sagv_post_plane_update(state);
7346         intel_pmdemand_post_plane_update(state);
7347
7348         drm_atomic_helper_commit_hw_done(&state->base);
7349
7350         if (state->modeset) {
7351                 /* As one of the primary mmio accessors, KMS has a high
7352                  * likelihood of triggering bugs in unclaimed access. After we
7353                  * finish modesetting, see if an error has been flagged, and if
7354                  * so enable debugging for the next modeset - and hope we catch
7355                  * the culprit.
7356                  */
7357                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7358         }
7359         /*
7360          * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7361          * toggling overhead at and above 60 FPS.
7362          */
7363         intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7364         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7365
7366         /*
7367          * Defer the cleanup of the old state to a separate worker to not
7368          * impede the current task (userspace for blocking modesets) that
7369          * are executed inline. For out-of-line asynchronous modesets/flips,
7370          * deferring to a new worker seems overkill, but we would place a
7371          * schedule point (cond_resched()) here anyway to keep latencies
7372          * down.
7373          */
7374         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7375         queue_work(system_highpri_wq, &state->base.commit_work);
7376 }
7377
7378 static void intel_atomic_commit_work(struct work_struct *work)
7379 {
7380         struct intel_atomic_state *state =
7381                 container_of(work, struct intel_atomic_state, base.commit_work);
7382
7383         intel_atomic_commit_tail(state);
7384 }
7385
7386 static int
7387 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7388                           enum i915_sw_fence_notify notify)
7389 {
7390         struct intel_atomic_state *state =
7391                 container_of(fence, struct intel_atomic_state, commit_ready);
7392
7393         switch (notify) {
7394         case FENCE_COMPLETE:
7395                 /* we do blocking waits in the worker, nothing to do here */
7396                 break;
7397         case FENCE_FREE:
7398                 {
7399                         struct drm_i915_private *i915 = to_i915(state->base.dev);
7400                         struct intel_atomic_helper *helper =
7401                                 &i915->display.atomic_helper;
7402
7403                         if (llist_add(&state->freed, &helper->free_list))
7404                                 queue_work(i915->unordered_wq, &helper->free_work);
7405                         break;
7406                 }
7407         }
7408
7409         return NOTIFY_DONE;
7410 }
7411
7412 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7413 {
7414         struct intel_plane_state *old_plane_state, *new_plane_state;
7415         struct intel_plane *plane;
7416         int i;
7417
7418         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7419                                              new_plane_state, i)
7420                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7421                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7422                                         plane->frontbuffer_bit);
7423 }
7424
7425 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7426                         bool nonblock)
7427 {
7428         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7429         struct drm_i915_private *dev_priv = to_i915(dev);
7430         int ret = 0;
7431
7432         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7433
7434         drm_atomic_state_get(&state->base);
7435         i915_sw_fence_init(&state->commit_ready,
7436                            intel_atomic_commit_ready);
7437
7438         /*
7439          * The intel_legacy_cursor_update() fast path takes care
7440          * of avoiding the vblank waits for simple cursor
7441          * movement and flips. For cursor on/off and size changes,
7442          * we want to perform the vblank waits so that watermark
7443          * updates happen during the correct frames. Gen9+ have
7444          * double buffered watermarks and so shouldn't need this.
7445          *
7446          * Unset state->legacy_cursor_update before the call to
7447          * drm_atomic_helper_setup_commit() because otherwise
7448          * drm_atomic_helper_wait_for_flip_done() is a noop and
7449          * we get FIFO underruns because we didn't wait
7450          * for vblank.
7451          *
7452          * FIXME doing watermarks and fb cleanup from a vblank worker
7453          * (assuming we had any) would solve these problems.
7454          */
7455         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7456                 struct intel_crtc_state *new_crtc_state;
7457                 struct intel_crtc *crtc;
7458                 int i;
7459
7460                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7461                         if (new_crtc_state->wm.need_postvbl_update ||
7462                             new_crtc_state->update_wm_post)
7463                                 state->base.legacy_cursor_update = false;
7464         }
7465
7466         ret = intel_atomic_prepare_commit(state);
7467         if (ret) {
7468                 drm_dbg_atomic(&dev_priv->drm,
7469                                "Preparing state failed with %i\n", ret);
7470                 i915_sw_fence_commit(&state->commit_ready);
7471                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7472                 return ret;
7473         }
7474
7475         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7476         if (!ret)
7477                 ret = drm_atomic_helper_swap_state(&state->base, true);
7478         if (!ret)
7479                 intel_atomic_swap_global_state(state);
7480
7481         if (ret) {
7482                 struct intel_crtc_state *new_crtc_state;
7483                 struct intel_crtc *crtc;
7484                 int i;
7485
7486                 i915_sw_fence_commit(&state->commit_ready);
7487
7488                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7489                         intel_color_cleanup_commit(new_crtc_state);
7490
7491                 drm_atomic_helper_unprepare_planes(dev, &state->base);
7492                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7493                 return ret;
7494         }
7495         intel_shared_dpll_swap_state(state);
7496         intel_atomic_track_fbs(state);
7497
7498         drm_atomic_state_get(&state->base);
7499         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7500
7501         i915_sw_fence_commit(&state->commit_ready);
7502         if (nonblock && state->modeset) {
7503                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7504         } else if (nonblock) {
7505                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7506         } else {
7507                 if (state->modeset)
7508                         flush_workqueue(dev_priv->display.wq.modeset);
7509                 intel_atomic_commit_tail(state);
7510         }
7511
7512         return 0;
7513 }
7514
7515 /**
7516  * intel_plane_destroy - destroy a plane
7517  * @plane: plane to destroy
7518  *
7519  * Common destruction function for all types of planes (primary, cursor,
7520  * sprite).
7521  */
7522 void intel_plane_destroy(struct drm_plane *plane)
7523 {
7524         drm_plane_cleanup(plane);
7525         kfree(to_intel_plane(plane));
7526 }
7527
7528 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7529                                       struct drm_file *file)
7530 {
7531         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7532         struct drm_crtc *drmmode_crtc;
7533         struct intel_crtc *crtc;
7534
7535         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7536         if (!drmmode_crtc)
7537                 return -ENOENT;
7538
7539         crtc = to_intel_crtc(drmmode_crtc);
7540         pipe_from_crtc_id->pipe = crtc->pipe;
7541
7542         return 0;
7543 }
7544
7545 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7546 {
7547         struct drm_device *dev = encoder->base.dev;
7548         struct intel_encoder *source_encoder;
7549         u32 possible_clones = 0;
7550
7551         for_each_intel_encoder(dev, source_encoder) {
7552                 if (encoders_cloneable(encoder, source_encoder))
7553                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7554         }
7555
7556         return possible_clones;
7557 }
7558
7559 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7560 {
7561         struct drm_device *dev = encoder->base.dev;
7562         struct intel_crtc *crtc;
7563         u32 possible_crtcs = 0;
7564
7565         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7566                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7567
7568         return possible_crtcs;
7569 }
7570
7571 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7572 {
7573         if (!IS_MOBILE(dev_priv))
7574                 return false;
7575
7576         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7577                 return false;
7578
7579         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7580                 return false;
7581
7582         return true;
7583 }
7584
7585 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7586 {
7587         if (DISPLAY_VER(dev_priv) >= 9)
7588                 return false;
7589
7590         if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7591                 return false;
7592
7593         if (HAS_PCH_LPT_H(dev_priv) &&
7594             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7595                 return false;
7596
7597         /* DDI E can't be used if DDI A requires 4 lanes */
7598         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7599                 return false;
7600
7601         if (!dev_priv->display.vbt.int_crt_support)
7602                 return false;
7603
7604         return true;
7605 }
7606
7607 bool assert_port_valid(struct drm_i915_private *i915, enum port port)
7608 {
7609         return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
7610                          "Platform does not support port %c\n", port_name(port));
7611 }
7612
7613 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7614 {
7615         struct intel_encoder *encoder;
7616         bool dpd_is_edp = false;
7617
7618         intel_pps_unlock_regs_wa(dev_priv);
7619
7620         if (!HAS_DISPLAY(dev_priv))
7621                 return;
7622
7623         if (HAS_DDI(dev_priv)) {
7624                 if (intel_ddi_crt_present(dev_priv))
7625                         intel_crt_init(dev_priv);
7626
7627                 intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
7628
7629                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
7630                         vlv_dsi_init(dev_priv);
7631         } else if (HAS_PCH_SPLIT(dev_priv)) {
7632                 int found;
7633
7634                 /*
7635                  * intel_edp_init_connector() depends on this completing first,
7636                  * to prevent the registration of both eDP and LVDS and the
7637                  * incorrect sharing of the PPS.
7638                  */
7639                 intel_lvds_init(dev_priv);
7640                 intel_crt_init(dev_priv);
7641
7642                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7643
7644                 if (ilk_has_edp_a(dev_priv))
7645                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7646
7647                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7648                         /* PCH SDVOB multiplex with HDMIB */
7649                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7650                         if (!found)
7651                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7652                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7653                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7654                 }
7655
7656                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7657                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7658
7659                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7660                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7661
7662                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7663                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7664
7665                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7666                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7667         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7668                 bool has_edp, has_port;
7669
7670                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7671                         intel_crt_init(dev_priv);
7672
7673                 /*
7674                  * The DP_DETECTED bit is the latched state of the DDC
7675                  * SDA pin at boot. However since eDP doesn't require DDC
7676                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7677                  * eDP ports may have been muxed to an alternate function.
7678                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7679                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7680                  * detect eDP ports.
7681                  *
7682                  * Sadly the straps seem to be missing sometimes even for HDMI
7683                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7684                  * and VBT for the presence of the port. Additionally we can't
7685                  * trust the port type the VBT declares as we've seen at least
7686                  * HDMI ports that the VBT claim are DP or eDP.
7687                  */
7688                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7689                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7690                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7691                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7692                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7693                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7694
7695                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7696                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7697                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7698                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7699                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7700                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7701
7702                 if (IS_CHERRYVIEW(dev_priv)) {
7703                         /*
7704                          * eDP not supported on port D,
7705                          * so no need to worry about it
7706                          */
7707                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7708                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7709                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7710                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7711                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7712                 }
7713
7714                 vlv_dsi_init(dev_priv);
7715         } else if (IS_PINEVIEW(dev_priv)) {
7716                 intel_lvds_init(dev_priv);
7717                 intel_crt_init(dev_priv);
7718         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7719                 bool found = false;
7720
7721                 if (IS_MOBILE(dev_priv))
7722                         intel_lvds_init(dev_priv);
7723
7724                 intel_crt_init(dev_priv);
7725
7726                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7727                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7728                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7729                         if (!found && IS_G4X(dev_priv)) {
7730                                 drm_dbg_kms(&dev_priv->drm,
7731                                             "probing HDMI on SDVOB\n");
7732                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7733                         }
7734
7735                         if (!found && IS_G4X(dev_priv))
7736                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7737                 }
7738
7739                 /* Before G4X SDVOC doesn't have its own detect register */
7740
7741                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7742                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7743                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7744                 }
7745
7746                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7747
7748                         if (IS_G4X(dev_priv)) {
7749                                 drm_dbg_kms(&dev_priv->drm,
7750                                             "probing HDMI on SDVOC\n");
7751                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7752                         }
7753                         if (IS_G4X(dev_priv))
7754                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7755                 }
7756
7757                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7758                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7759
7760                 if (SUPPORTS_TV(dev_priv))
7761                         intel_tv_init(dev_priv);
7762         } else if (DISPLAY_VER(dev_priv) == 2) {
7763                 if (IS_I85X(dev_priv))
7764                         intel_lvds_init(dev_priv);
7765
7766                 intel_crt_init(dev_priv);
7767                 intel_dvo_init(dev_priv);
7768         }
7769
7770         for_each_intel_encoder(&dev_priv->drm, encoder) {
7771                 encoder->base.possible_crtcs =
7772                         intel_encoder_possible_crtcs(encoder);
7773                 encoder->base.possible_clones =
7774                         intel_encoder_possible_clones(encoder);
7775         }
7776
7777         intel_init_pch_refclk(dev_priv);
7778
7779         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7780 }
7781
7782 static int max_dotclock(struct drm_i915_private *i915)
7783 {
7784         int max_dotclock = i915->max_dotclk_freq;
7785
7786         /* icl+ might use bigjoiner */
7787         if (DISPLAY_VER(i915) >= 11)
7788                 max_dotclock *= 2;
7789
7790         return max_dotclock;
7791 }
7792
7793 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7794                                       const struct drm_display_mode *mode)
7795 {
7796         struct drm_i915_private *dev_priv = to_i915(dev);
7797         int hdisplay_max, htotal_max;
7798         int vdisplay_max, vtotal_max;
7799
7800         /*
7801          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7802          * of DBLSCAN modes to the output's mode list when they detect
7803          * the scaling mode property on the connector. And they don't
7804          * ask the kernel to validate those modes in any way until
7805          * modeset time at which point the client gets a protocol error.
7806          * So in order to not upset those clients we silently ignore the
7807          * DBLSCAN flag on such connectors. For other connectors we will
7808          * reject modes with the DBLSCAN flag in encoder->compute_config().
7809          * And we always reject DBLSCAN modes in connector->mode_valid()
7810          * as we never want such modes on the connector's mode list.
7811          */
7812
7813         if (mode->vscan > 1)
7814                 return MODE_NO_VSCAN;
7815
7816         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7817                 return MODE_H_ILLEGAL;
7818
7819         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7820                            DRM_MODE_FLAG_NCSYNC |
7821                            DRM_MODE_FLAG_PCSYNC))
7822                 return MODE_HSYNC;
7823
7824         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7825                            DRM_MODE_FLAG_PIXMUX |
7826                            DRM_MODE_FLAG_CLKDIV2))
7827                 return MODE_BAD;
7828
7829         /*
7830          * Reject clearly excessive dotclocks early to
7831          * avoid having to worry about huge integers later.
7832          */
7833         if (mode->clock > max_dotclock(dev_priv))
7834                 return MODE_CLOCK_HIGH;
7835
7836         /* Transcoder timing limits */
7837         if (DISPLAY_VER(dev_priv) >= 11) {
7838                 hdisplay_max = 16384;
7839                 vdisplay_max = 8192;
7840                 htotal_max = 16384;
7841                 vtotal_max = 8192;
7842         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7843                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7844                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7845                 vdisplay_max = 4096;
7846                 htotal_max = 8192;
7847                 vtotal_max = 8192;
7848         } else if (DISPLAY_VER(dev_priv) >= 3) {
7849                 hdisplay_max = 4096;
7850                 vdisplay_max = 4096;
7851                 htotal_max = 8192;
7852                 vtotal_max = 8192;
7853         } else {
7854                 hdisplay_max = 2048;
7855                 vdisplay_max = 2048;
7856                 htotal_max = 4096;
7857                 vtotal_max = 4096;
7858         }
7859
7860         if (mode->hdisplay > hdisplay_max ||
7861             mode->hsync_start > htotal_max ||
7862             mode->hsync_end > htotal_max ||
7863             mode->htotal > htotal_max)
7864                 return MODE_H_ILLEGAL;
7865
7866         if (mode->vdisplay > vdisplay_max ||
7867             mode->vsync_start > vtotal_max ||
7868             mode->vsync_end > vtotal_max ||
7869             mode->vtotal > vtotal_max)
7870                 return MODE_V_ILLEGAL;
7871
7872         return MODE_OK;
7873 }
7874
7875 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
7876                                                      const struct drm_display_mode *mode)
7877 {
7878         /*
7879          * Additional transcoder timing limits,
7880          * excluding BXT/GLK DSI transcoders.
7881          */
7882         if (DISPLAY_VER(dev_priv) >= 5) {
7883                 if (mode->hdisplay < 64 ||
7884                     mode->htotal - mode->hdisplay < 32)
7885                         return MODE_H_ILLEGAL;
7886
7887                 if (mode->vtotal - mode->vdisplay < 5)
7888                         return MODE_V_ILLEGAL;
7889         } else {
7890                 if (mode->htotal - mode->hdisplay < 32)
7891                         return MODE_H_ILLEGAL;
7892
7893                 if (mode->vtotal - mode->vdisplay < 3)
7894                         return MODE_V_ILLEGAL;
7895         }
7896
7897         /*
7898          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7899          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7900          */
7901         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7902             mode->hsync_start == mode->hdisplay)
7903                 return MODE_H_ILLEGAL;
7904
7905         return MODE_OK;
7906 }
7907
7908 enum drm_mode_status
7909 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7910                                 const struct drm_display_mode *mode,
7911                                 bool bigjoiner)
7912 {
7913         int plane_width_max, plane_height_max;
7914
7915         /*
7916          * intel_mode_valid() should be
7917          * sufficient on older platforms.
7918          */
7919         if (DISPLAY_VER(dev_priv) < 9)
7920                 return MODE_OK;
7921
7922         /*
7923          * Most people will probably want a fullscreen
7924          * plane so let's not advertize modes that are
7925          * too big for that.
7926          */
7927         if (DISPLAY_VER(dev_priv) >= 11) {
7928                 plane_width_max = 5120 << bigjoiner;
7929                 plane_height_max = 4320;
7930         } else {
7931                 plane_width_max = 5120;
7932                 plane_height_max = 4096;
7933         }
7934
7935         if (mode->hdisplay > plane_width_max)
7936                 return MODE_H_ILLEGAL;
7937
7938         if (mode->vdisplay > plane_height_max)
7939                 return MODE_V_ILLEGAL;
7940
7941         return MODE_OK;
7942 }
7943
7944 static const struct intel_display_funcs skl_display_funcs = {
7945         .get_pipe_config = hsw_get_pipe_config,
7946         .crtc_enable = hsw_crtc_enable,
7947         .crtc_disable = hsw_crtc_disable,
7948         .commit_modeset_enables = skl_commit_modeset_enables,
7949         .get_initial_plane_config = skl_get_initial_plane_config,
7950 };
7951
7952 static const struct intel_display_funcs ddi_display_funcs = {
7953         .get_pipe_config = hsw_get_pipe_config,
7954         .crtc_enable = hsw_crtc_enable,
7955         .crtc_disable = hsw_crtc_disable,
7956         .commit_modeset_enables = intel_commit_modeset_enables,
7957         .get_initial_plane_config = i9xx_get_initial_plane_config,
7958 };
7959
7960 static const struct intel_display_funcs pch_split_display_funcs = {
7961         .get_pipe_config = ilk_get_pipe_config,
7962         .crtc_enable = ilk_crtc_enable,
7963         .crtc_disable = ilk_crtc_disable,
7964         .commit_modeset_enables = intel_commit_modeset_enables,
7965         .get_initial_plane_config = i9xx_get_initial_plane_config,
7966 };
7967
7968 static const struct intel_display_funcs vlv_display_funcs = {
7969         .get_pipe_config = i9xx_get_pipe_config,
7970         .crtc_enable = valleyview_crtc_enable,
7971         .crtc_disable = i9xx_crtc_disable,
7972         .commit_modeset_enables = intel_commit_modeset_enables,
7973         .get_initial_plane_config = i9xx_get_initial_plane_config,
7974 };
7975
7976 static const struct intel_display_funcs i9xx_display_funcs = {
7977         .get_pipe_config = i9xx_get_pipe_config,
7978         .crtc_enable = i9xx_crtc_enable,
7979         .crtc_disable = i9xx_crtc_disable,
7980         .commit_modeset_enables = intel_commit_modeset_enables,
7981         .get_initial_plane_config = i9xx_get_initial_plane_config,
7982 };
7983
7984 /**
7985  * intel_init_display_hooks - initialize the display modesetting hooks
7986  * @dev_priv: device private
7987  */
7988 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
7989 {
7990         if (DISPLAY_VER(dev_priv) >= 9) {
7991                 dev_priv->display.funcs.display = &skl_display_funcs;
7992         } else if (HAS_DDI(dev_priv)) {
7993                 dev_priv->display.funcs.display = &ddi_display_funcs;
7994         } else if (HAS_PCH_SPLIT(dev_priv)) {
7995                 dev_priv->display.funcs.display = &pch_split_display_funcs;
7996         } else if (IS_CHERRYVIEW(dev_priv) ||
7997                    IS_VALLEYVIEW(dev_priv)) {
7998                 dev_priv->display.funcs.display = &vlv_display_funcs;
7999         } else {
8000                 dev_priv->display.funcs.display = &i9xx_display_funcs;
8001         }
8002 }
8003
8004 int intel_initial_commit(struct drm_device *dev)
8005 {
8006         struct drm_atomic_state *state = NULL;
8007         struct drm_modeset_acquire_ctx ctx;
8008         struct intel_crtc *crtc;
8009         int ret = 0;
8010
8011         state = drm_atomic_state_alloc(dev);
8012         if (!state)
8013                 return -ENOMEM;
8014
8015         drm_modeset_acquire_init(&ctx, 0);
8016
8017         state->acquire_ctx = &ctx;
8018         to_intel_atomic_state(state)->internal = true;
8019
8020 retry:
8021         for_each_intel_crtc(dev, crtc) {
8022                 struct intel_crtc_state *crtc_state =
8023                         intel_atomic_get_crtc_state(state, crtc);
8024
8025                 if (IS_ERR(crtc_state)) {
8026                         ret = PTR_ERR(crtc_state);
8027                         goto out;
8028                 }
8029
8030                 if (crtc_state->hw.active) {
8031                         struct intel_encoder *encoder;
8032
8033                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8034                         if (ret)
8035                                 goto out;
8036
8037                         /*
8038                          * FIXME hack to force a LUT update to avoid the
8039                          * plane update forcing the pipe gamma on without
8040                          * having a proper LUT loaded. Remove once we
8041                          * have readout for pipe gamma enable.
8042                          */
8043                         crtc_state->uapi.color_mgmt_changed = true;
8044
8045                         for_each_intel_encoder_mask(dev, encoder,
8046                                                     crtc_state->uapi.encoder_mask) {
8047                                 if (encoder->initial_fastset_check &&
8048                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8049                                         ret = drm_atomic_add_affected_connectors(state,
8050                                                                                  &crtc->base);
8051                                         if (ret)
8052                                                 goto out;
8053                                 }
8054                         }
8055                 }
8056         }
8057
8058         ret = drm_atomic_commit(state);
8059
8060 out:
8061         if (ret == -EDEADLK) {
8062                 drm_atomic_state_clear(state);
8063                 drm_modeset_backoff(&ctx);
8064                 goto retry;
8065         }
8066
8067         drm_atomic_state_put(state);
8068
8069         drm_modeset_drop_locks(&ctx);
8070         drm_modeset_acquire_fini(&ctx);
8071
8072         return ret;
8073 }
8074
8075 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8076 {
8077         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8078         enum transcoder cpu_transcoder = (enum transcoder)pipe;
8079         /* 640x480@60Hz, ~25175 kHz */
8080         struct dpll clock = {
8081                 .m1 = 18,
8082                 .m2 = 7,
8083                 .p1 = 13,
8084                 .p2 = 4,
8085                 .n = 2,
8086         };
8087         u32 dpll, fp;
8088         int i;
8089
8090         drm_WARN_ON(&dev_priv->drm,
8091                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8092
8093         drm_dbg_kms(&dev_priv->drm,
8094                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8095                     pipe_name(pipe), clock.vco, clock.dot);
8096
8097         fp = i9xx_dpll_compute_fp(&clock);
8098         dpll = DPLL_DVO_2X_MODE |
8099                 DPLL_VGA_MODE_DIS |
8100                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8101                 PLL_P2_DIVIDE_BY_4 |
8102                 PLL_REF_INPUT_DREFCLK |
8103                 DPLL_VCO_ENABLE;
8104
8105         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8106                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
8107         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8108                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8109         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8110                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8111         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8112                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
8113         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8114                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8115         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8116                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8117         intel_de_write(dev_priv, PIPESRC(pipe),
8118                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8119
8120         intel_de_write(dev_priv, FP0(pipe), fp);
8121         intel_de_write(dev_priv, FP1(pipe), fp);
8122
8123         /*
8124          * Apparently we need to have VGA mode enabled prior to changing
8125          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8126          * dividers, even though the register value does change.
8127          */
8128         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8129         intel_de_write(dev_priv, DPLL(pipe), dpll);
8130
8131         /* Wait for the clocks to stabilize. */
8132         intel_de_posting_read(dev_priv, DPLL(pipe));
8133         udelay(150);
8134
8135         /* The pixel multiplier can only be updated once the
8136          * DPLL is enabled and the clocks are stable.
8137          *
8138          * So write it again.
8139          */
8140         intel_de_write(dev_priv, DPLL(pipe), dpll);
8141
8142         /* We do this three times for luck */
8143         for (i = 0; i < 3 ; i++) {
8144                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8145                 intel_de_posting_read(dev_priv, DPLL(pipe));
8146                 udelay(150); /* wait for warmup */
8147         }
8148
8149         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8150         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8151
8152         intel_wait_for_pipe_scanline_moving(crtc);
8153 }
8154
8155 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8156 {
8157         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8158
8159         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8160                     pipe_name(pipe));
8161
8162         drm_WARN_ON(&dev_priv->drm,
8163                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8164         drm_WARN_ON(&dev_priv->drm,
8165                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8166         drm_WARN_ON(&dev_priv->drm,
8167                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8168         drm_WARN_ON(&dev_priv->drm,
8169                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8170         drm_WARN_ON(&dev_priv->drm,
8171                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8172
8173         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8174         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8175
8176         intel_wait_for_pipe_scanline_stopped(crtc);
8177
8178         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8179         intel_de_posting_read(dev_priv, DPLL(pipe));
8180 }
8181
8182 void intel_hpd_poll_fini(struct drm_i915_private *i915)
8183 {
8184         struct intel_connector *connector;
8185         struct drm_connector_list_iter conn_iter;
8186
8187         /* Kill all the work that may have been queued by hpd. */
8188         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8189         for_each_intel_connector_iter(connector, &conn_iter) {
8190                 if (connector->modeset_retry_work.func)
8191                         cancel_work_sync(&connector->modeset_retry_work);
8192                 if (connector->hdcp.shim) {
8193                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8194                         cancel_work_sync(&connector->hdcp.prop_work);
8195                 }
8196         }
8197         drm_connector_list_iter_end(&conn_iter);
8198 }
8199
8200 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8201 {
8202         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8203 }